From 2717781048834a6b0b5a0c408e693cf2f960c56d Mon Sep 17 00:00:00 2001 From: Fujr Date: Sun, 26 Feb 2023 09:29:50 +0800 Subject: [PATCH 01/18] add 360t7 support --- .../0005-add_360t7-support.patch | 8335 +++++++++++++++++ 1 file changed, 8335 insertions(+) create mode 100644 patches-mt798x-7.6.6.1/0005-add_360t7-support.patch diff --git a/patches-mt798x-7.6.6.1/0005-add_360t7-support.patch b/patches-mt798x-7.6.6.1/0005-add_360t7-support.patch new file mode 100644 index 0000000..993a673 --- /dev/null +++ b/patches-mt798x-7.6.6.1/0005-add_360t7-support.patch @@ -0,0 +1,8335 @@ +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts 2023-02-26 09:01:19.877971900 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,591 +0,0 @@ +-/* +- * Copyright (c) 2018 MediaTek Inc. +- * Author: Ryder Lee +- * +- * SPDX-License-Identifier: (GPL-2.0-only OR MIT) +- */ +- +-/dts-v1/; +-#include +-#include +- +-#include "mt7622.dtsi" +-#include "mt6380.dtsi" +- +-/ { +- model = "Bananapi BPI-R64"; +- compatible = "bananapi,bpi-r64-rootdisk", "mediatek,mt7622"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=/dev/mmcblk0p7 rootfstype=squashfs,f2fs"; +- }; +- +- cpus { +- cpu@0 { +- proc-supply = <&mt6380_vcpu_reg>; +- sram-supply = <&mt6380_vm_reg>; +- }; +- +- cpu@1 { +- proc-supply = <&mt6380_vcpu_reg>; +- sram-supply = <&mt6380_vm_reg>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- factory { +- label = "factory"; +- linux,code = ; +- gpios = <&pio 0 GPIO_ACTIVE_HIGH>; +- }; +- +- wps { +- label = "wps"; +- linux,code = ; +- gpios = <&pio 102 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- green { +- label = "bpi-r64:pio:green"; +- gpios = <&pio 89 GPIO_ACTIVE_HIGH>; +- }; +- +- red { +- label = "bpi-r64:pio:red"; +- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&bch { +- status = "disabled"; +-}; +- +-&btif { +- status = "okay"; +-}; +- +-&cir { +- pinctrl-names = "default"; +- pinctrl-0 = <&irrx_pins>; +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "2500base-x"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "rgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch@1f { +- compatible = "mediatek,mt7531"; +- reg = <0x1f>; +- reset-gpios = <&pio 54 0>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- wan: port@0 { +- reg = <0>; +- label = "wan"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan0"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan1"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan2"; +- }; +- +- port@4 { +- reg = <4>; +- label = "lan3"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "2500base-x"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&emmc_pins_default>; +- pinctrl-1 = <&emmc_pins_uhs>; +- status = "okay"; +- bus-width = <8>; +- max-frequency = <50000000>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; +- non-removable; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&sd0_pins_default>; +- pinctrl-1 = <&sd0_pins_uhs>; +- status = "okay"; +- bus-width = <4>; +- max-frequency = <50000000>; +- cap-sd-highspeed; +- r_smpl = <1>; +- cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +- assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; +-}; +- +-&nandc { +- pinctrl-names = "default"; +- pinctrl-0 = <¶llel_nand_pins>; +- status = "disabled"; +-}; +- +-&nor_flash { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_nor_pins>; +- status = "disabled"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- }; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_pins>; +- status = "okay"; +-}; +- +-&pio { +- /* Attention: GPIO 90 is used to switch between PCIe@1,0 and +- * SATA functions. i.e. output-high: PCIe, output-low: SATA +- */ +- asm_sel { +- gpio-hog; +- gpios = <90 GPIO_ACTIVE_HIGH>; +- output-high; +- }; +- +- /* eMMC is shared pin with parallel NAND */ +- emmc_pins_default: emmc-pins-default { +- mux { +- function = "emmc", "emmc_rst"; +- groups = "emmc"; +- }; +- +- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", +- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, +- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively +- */ +- conf-cmd-dat { +- pins = "NDL0", "NDL1", "NDL2", +- "NDL3", "NDL4", "NDL5", +- "NDL6", "NDL7", "NRB"; +- input-enable; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "NCLE"; +- bias-pull-down; +- }; +- }; +- +- emmc_pins_uhs: emmc-pins-uhs { +- mux { +- function = "emmc"; +- groups = "emmc"; +- }; +- +- conf-cmd-dat { +- pins = "NDL0", "NDL1", "NDL2", +- "NDL3", "NDL4", "NDL5", +- "NDL6", "NDL7", "NRB"; +- input-enable; +- drive-strength = <4>; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "NCLE"; +- drive-strength = <4>; +- bias-pull-down; +- }; +- }; +- +- eth_pins: eth-pins { +- mux { +- function = "eth"; +- groups = "mdc_mdio", "rgmii_via_gmac2"; +- }; +- }; +- +- i2c1_pins: i2c1-pins { +- mux { +- function = "i2c"; +- groups = "i2c1_0"; +- }; +- }; +- +- i2c2_pins: i2c2-pins { +- mux { +- function = "i2c"; +- groups = "i2c2_0"; +- }; +- }; +- +- i2s1_pins: i2s1-pins { +- mux { +- function = "i2s"; +- groups = "i2s_out_mclk_bclk_ws", +- "i2s1_in_data", +- "i2s1_out_data"; +- }; +- +- conf { +- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", +- "I2S_WS", "I2S_MCLK"; +- drive-strength = <12>; +- bias-pull-down; +- }; +- }; +- +- irrx_pins: irrx-pins { +- mux { +- function = "ir"; +- groups = "ir_1_rx"; +- }; +- }; +- +- irtx_pins: irtx-pins { +- mux { +- function = "ir"; +- groups = "ir_1_tx"; +- }; +- }; +- +- /* Parallel nand is shared pin with eMMC */ +- parallel_nand_pins: parallel-nand-pins { +- mux { +- function = "flash"; +- groups = "par_nand"; +- }; +- }; +- +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie0_pad_perst", +- "pcie0_1_waken", +- "pcie0_1_clkreq"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie1_pad_perst", +- "pcie1_0_waken", +- "pcie1_0_clkreq"; +- }; +- }; +- +- pmic_bus_pins: pmic-bus-pins { +- mux { +- function = "pmic"; +- groups = "pmic_bus"; +- }; +- }; +- +- pwm7_pins: pwm1-2-pins { +- mux { +- function = "pwm"; +- groups = "pwm_ch7_2"; +- }; +- }; +- +- wled_pins: wled-pins { +- mux { +- function = "led"; +- groups = "wled"; +- }; +- }; +- +- sd0_pins_default: sd0-pins-default { +- mux { +- function = "sd"; +- groups = "sd_0"; +- }; +- +- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", +- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, +- * DAT2, DAT3, CMD, CLK for SD respectively. +- */ +- conf-cmd-data { +- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", +- "I2S2_IN","I2S4_OUT"; +- input-enable; +- drive-strength = <8>; +- bias-pull-up; +- }; +- conf-clk { +- pins = "I2S3_OUT"; +- drive-strength = <12>; +- bias-pull-down; +- }; +- conf-cd { +- pins = "TXD3"; +- bias-pull-up; +- }; +- }; +- +- sd0_pins_uhs: sd0-pins-uhs { +- mux { +- function = "sd"; +- groups = "sd_0"; +- }; +- +- conf-cmd-data { +- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", +- "I2S2_IN","I2S4_OUT"; +- input-enable; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "I2S3_OUT"; +- bias-pull-down; +- }; +- }; +- +- /* Serial NAND is shared pin with SPI-NOR */ +- serial_nand_pins: serial-nand-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- spic0_pins: spic0-pins { +- mux { +- function = "spi"; +- groups = "spic0_0"; +- }; +- }; +- +- spic1_pins: spic1-pins { +- mux { +- function = "spi"; +- groups = "spic1_0"; +- }; +- }; +- +- /* SPI-NOR is shared pin with serial NAND */ +- spi_nor_pins: spi-nor-pins { +- mux { +- function = "flash"; +- groups = "spi_nor"; +- }; +- }; +- +- /* serial NAND is shared pin with SPI-NOR */ +- serial_nand_pins: serial-nand-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- uart0_pins: uart0-pins { +- mux { +- function = "uart"; +- groups = "uart0_0_tx_rx" ; +- }; +- }; +- +- uart2_pins: uart2-pins { +- mux { +- function = "uart"; +- groups = "uart2_1_tx_rx" ; +- }; +- }; +- +- watchdog_pins: watchdog-pins { +- mux { +- function = "watchdog"; +- groups = "watchdog"; +- }; +- }; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm7_pins>; +- status = "okay"; +-}; +- +-&pwrap { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_bus_pins>; +- +- status = "okay"; +-}; +- +-&sata { +- status = "disable"; +-}; +- +-&sata_phy { +- status = "disable"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spic0_pins>; +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spic1_pins>; +- status = "okay"; +-}; +- +-&ssusb { +- vusb33-supply = <®_3p3v>; +- vbus-supply = <®_5v>; +- status = "okay"; +-}; +- +-&u3phy { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-&watchdog { +- pinctrl-names = "default"; +- pinctrl-0 = <&watchdog_pins>; +- status = "okay"; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts 2023-02-26 09:01:19.878971500 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,608 +0,0 @@ +-/* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Ming Huang +- * Sean Wang +- * +- * SPDX-License-Identifier: (GPL-2.0-only OR MIT) +- */ +- +-/dts-v1/; +-#include +-#include +- +-#include "mt7622.dtsi" +-#include "mt6380.dtsi" +- +-/ { +- model = "Elecom WRC-2533"; +- compatible = "elecom,wrc-2533gent", "mediatek,mt7622"; +- +- aliases { +- led-boot = &led_power; +- led-failsafe = &led_power; +- led-running = &led_power; +- led-upgrade = &led_power; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8"; +- }; +- +- cpus { +- cpu@0 { +- proc-supply = <&mt6380_vcpu_reg>; +- sram-supply = <&mt6380_vm_reg>; +- }; +- +- cpu@1 { +- proc-supply = <&mt6380_vcpu_reg>; +- sram-supply = <&mt6380_vm_reg>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- poll-interval = <100>; +- +- wps { +- label = "wps"; +- linux,code = ; +- gpios = <&pio 0 GPIO_ACTIVE_HIGH>; +- }; +- +- factory { +- label = "factory"; +- linux,code = ; +- gpios = <&pio 102 GPIO_ACTIVE_LOW>; +- }; +- +- switch0 { +- label = "switch0"; +- gpios = <&pio 1 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- }; +- +- switch1 { +- label = "switch1"; +- gpios = <&pio 16 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- }; +- +- switch2 { +- label = "switch2"; +- gpios = <&pio 17 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- }; +- +- switch3 { +- label = "switch3"; +- gpios = <&pio 18 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led_power: power_g { +- label = "wrc-2533:green:power"; +- gpios = <&pio 2 GPIO_ACTIVE_HIGH>; +- }; +- +- power_b { +- label = "wrc-2533:blue:power"; +- gpios = <&pio 19 GPIO_ACTIVE_HIGH>; +- }; +- +- power_r { +- label = "wrc-2533:red:power"; +- gpios = <&pio 73 GPIO_ACTIVE_HIGH>; +- }; +- +- usb { +- label = "wrc-2533:blue:usb"; +- gpios = <&pio 74 GPIO_ACTIVE_HIGH>; +- }; +- +- wps { +- label = "wrc-2533:red:wps"; +- gpios = <&pio 76 GPIO_ACTIVE_LOW>; +- }; +- +- wifi2 { +- label = "wrc-2533:blue:wifi2g"; +- gpios = <&pio 85 GPIO_ACTIVE_LOW>; +- }; +- +- wifi5 { +- label = "wrc-2533:blue:wifi5g"; +- gpios = <&pio 91 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- reg_usb_vbus: regulator { +- compatible = "regulator-fixed"; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&pio 22 GPIO_ACTIVE_LOW>; +- enable-active-high; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x3F000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- rtkgsw: rtkgsw@0 { +- compatible = "mediatek,rtk-gsw"; +- mediatek,ethsys = <ðsys>; +- mediatek,mdio = <&mdio>; +- mediatek,reset-pin = <&pio 54 0>; +- status = "okay"; +- }; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&slot0 { +- mt7615@0,0 { +- reg = <0x0000 0 0 0 0>; +- mediatek,mtd-eeprom = <&factory 0x05000>; +- }; +-}; +- +-&pio { +- /* eMMC is shared pin with parallel NAND */ +- emmc_pins_default: emmc-pins-default { +- mux { +- function = "emmc", "emmc_rst"; +- groups = "emmc"; +- }; +- +- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", +- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, +- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively +- */ +- conf-cmd-dat { +- pins = "NDL0", "NDL1", "NDL2", +- "NDL3", "NDL4", "NDL5", +- "NDL6", "NDL7", "NRB"; +- input-enable; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "NCLE"; +- bias-pull-down; +- }; +- }; +- +- emmc_pins_uhs: emmc-pins-uhs { +- mux { +- function = "emmc"; +- groups = "emmc"; +- }; +- +- conf-cmd-dat { +- pins = "NDL0", "NDL1", "NDL2", +- "NDL3", "NDL4", "NDL5", +- "NDL6", "NDL7", "NRB"; +- input-enable; +- drive-strength = <4>; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "NCLE"; +- drive-strength = <4>; +- bias-pull-down; +- }; +- }; +- +- eth_pins: eth-pins { +- mux { +- function = "eth"; +- groups = "mdc_mdio", "rgmii_via_gmac2"; +- }; +- }; +- +- i2c1_pins: i2c1-pins { +- mux { +- function = "i2c"; +- groups = "i2c1_0"; +- }; +- }; +- +- i2c2_pins: i2c2-pins { +- mux { +- function = "i2c"; +- groups = "i2c2_0"; +- }; +- }; +- +- i2s1_pins: i2s1-pins { +- mux { +- function = "i2s"; +- groups = "i2s_out_mclk_bclk_ws", +- "i2s1_in_data", +- "i2s1_out_data"; +- }; +- +- conf { +- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", +- "I2S_WS", "I2S_MCLK"; +- drive-strength = <12>; +- bias-pull-down; +- }; +- }; +- +- irrx_pins: irrx-pins { +- mux { +- function = "ir"; +- groups = "ir_1_rx"; +- }; +- }; +- +- irtx_pins: irtx-pins { +- mux { +- function = "ir"; +- groups = "ir_1_tx"; +- }; +- }; +- +- /* Parallel nand is shared pin with eMMC */ +- parallel_nand_pins: parallel-nand-pins { +- mux { +- function = "flash"; +- groups = "par_nand"; +- }; +- }; +- +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie0_pad_perst", +- "pcie0_1_waken", +- "pcie0_1_clkreq"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie1_pad_perst", +- "pcie1_0_waken", +- "pcie1_0_clkreq"; +- }; +- }; +- +- pmic_bus_pins: pmic-bus-pins { +- mux { +- function = "pmic"; +- groups = "pmic_bus"; +- }; +- }; +- +- pwm7_pins: pwm1-2-pins { +- mux { +- function = "pwm"; +- groups = "pwm_ch7_2"; +- }; +- }; +- +- wled_pins: wled-pins { +- mux { +- function = "led"; +- groups = "wled"; +- }; +- }; +- +- sd0_pins_default: sd0-pins-default { +- mux { +- function = "sd"; +- groups = "sd_0"; +- }; +- +- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", +- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, +- * DAT2, DAT3, CMD, CLK for SD respectively. +- */ +- conf-cmd-data { +- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", +- "I2S2_IN","I2S4_OUT"; +- input-enable; +- drive-strength = <8>; +- bias-pull-up; +- }; +- conf-clk { +- pins = "I2S3_OUT"; +- drive-strength = <12>; +- bias-pull-down; +- }; +- conf-cd { +- pins = "TXD3"; +- bias-pull-up; +- }; +- }; +- +- sd0_pins_uhs: sd0-pins-uhs { +- mux { +- function = "sd"; +- groups = "sd_0"; +- }; +- +- conf-cmd-data { +- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", +- "I2S2_IN","I2S4_OUT"; +- input-enable; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "I2S3_OUT"; +- bias-pull-down; +- }; +- }; +- +- /* Serial NAND is shared pin with SPI-NOR */ +- serial_nand_pins: serial-nand-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- spic0_pins: spic0-pins { +- mux { +- function = "spi"; +- groups = "spic0_0"; +- }; +- }; +- +- spic1_pins: spic1-pins { +- mux { +- function = "spi"; +- groups = "spic1_0"; +- }; +- }; +- +- /* SPI-NOR is shared pin with serial NAND */ +- spi_nor_pins: spi-nor-pins { +- mux { +- function = "flash"; +- groups = "spi_nor"; +- }; +- }; +- +- /* serial NAND is shared pin with SPI-NOR */ +- serial_nand_pins: serial-nand-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- uart0_pins: uart0-pins { +- mux { +- function = "uart"; +- groups = "uart0_0_tx_rx" ; +- }; +- }; +- +- uart2_pins: uart2-pins { +- mux { +- function = "uart"; +- groups = "uart2_1_tx_rx" ; +- }; +- }; +- +- watchdog_pins: watchdog-pins { +- mux { +- function = "watchdog"; +- groups = "watchdog"; +- }; +- }; +-}; +- +-&bch { +- status = "okay"; +-}; +- +-&btif { +- status = "disabled"; +-}; +- +-&cir { +- pinctrl-names = "default"; +- pinctrl-0 = <&irrx_pins>; +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <ð_pins>; +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "sgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "rgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm7_pins>; +- status = "okay"; +-}; +- +-&pwrap { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_bus_pins>; +- +- status = "okay"; +-}; +- +-&snfi { +- pinctrl-names = "default"; +- pinctrl-0 = <&serial_nand_pins>; +- status = "okay"; +- +- spi_nand@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- spi-max-frequency = <104000000>; +- reg = <0>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "Preloader"; +- reg = <0x00000 0x0080000>; +- read-only; +- }; +- +- partition@80000 { +- label = "ATF"; +- reg = <0x80000 0x0040000>; +- read-only; +- }; +- +- partition@c0000 { +- label = "uboot"; +- reg = <0xc0000 0x0080000>; +- read-only; +- }; +- +- partition@140000 { +- label = "uboot-env"; +- reg = <0x140000 0x0080000>; +- read-only; +- }; +- +- factory: partition@1c0000 { +- label = "factory"; +- reg = <0x1c0000 0x0040000>; +- read-only; +- }; +- +- partition@200000 { +- label = "firmware"; +- reg = <0x200000 0x2000000>; +- }; +- +- partition@2200000 { +- label = "reserved"; +- reg = <0x2200000 0x4000000>; +- }; +- }; +- }; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spic0_pins>; +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spic1_pins>; +- status = "okay"; +-}; +- +-&ssusb { +- vusb33-supply = <®_3p3v>; +- vbus-supply = <®_usb_vbus>; +- status = "okay"; +-}; +- +-&u3phy { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-&watchdog { +- pinctrl-names = "default"; +- pinctrl-0 = <&watchdog_pins>; +- status = "okay"; +-}; +- +-&wmac { +- mediatek,mtd-eeprom = <&factory 0x0000>; +- status = "okay"; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts 2023-02-26 09:01:19.879971900 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,644 +0,0 @@ +-/* +- * Copyright (c) 2018 MediaTek Inc. +- * Author: Ryder Lee +- * +- * SPDX-License-Identifier: (GPL-2.0-only OR MIT) +- */ +- +-/dts-v1/; +-#include +-#include +- +-#include "mt7622.dtsi" +-#include "mt6380.dtsi" +- +-/ { +- model = "MT7622_MT7531 RFB"; +- compatible = "mediatek,mt7622,ubi"; +- +- aliases { +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; +- }; +- +- cpus { +- cpu@0 { +- proc-supply = <&mt6380_vcpu_reg>; +- sram-supply = <&mt6380_vm_reg>; +- }; +- +- cpu@1 { +- proc-supply = <&mt6380_vcpu_reg>; +- sram-supply = <&mt6380_vm_reg>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- factory { +- label = "factory"; +- linux,code = ; +- gpios = <&pio 0 GPIO_ACTIVE_HIGH>; +- }; +- +- wps { +- label = "wps"; +- linux,code = ; +- gpios = <&pio 102 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- gsw: gsw@0 { +- compatible = "mediatek,mt753x"; +- mediatek,ethsys = <ðsys>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- green { +- label = "bpi-r64:pio:green"; +- gpios = <&pio 89 GPIO_ACTIVE_HIGH>; +- }; +- +- red { +- label = "bpi-r64:pio:red"; +- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; +- }; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x40000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_5v: regulator-5v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&bch { +- status = "okay"; +-}; +- +-&btif { +- status = "okay"; +-}; +- +-&cir { +- pinctrl-names = "default"; +- pinctrl-0 = <&irrx_pins>; +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "2500base-x"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "rgmii"; +- +- fixed-link { +- speed = <1000>; +- full-duplex; +- pause; +- }; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&gsw { +- mediatek,mdio = <&mdio>; +- mediatek,portmap = "llllw"; +- mediatek,mdio_master_pinmux = <0>; +- reset-gpios = <&pio 54 0>; +- interrupt-parent = <&pio>; +- interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; +- status = "okay"; +- +- port5: port@5 { +- compatible = "mediatek,mt753x-port"; +- reg = <5>; +- phy-mode = "rgmii"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- +- port6: port@6 { +- compatible = "mediatek,mt753x-port"; +- reg = <6>; +- phy-mode = "sgmii"; +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&emmc_pins_default>; +- pinctrl-1 = <&emmc_pins_uhs>; +- status = "okay"; +- bus-width = <8>; +- max-frequency = <50000000>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_1p8v>; +- assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; +- non-removable; +-}; +- +-&mmc1 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&sd0_pins_default>; +- pinctrl-1 = <&sd0_pins_uhs>; +- status = "okay"; +- bus-width = <4>; +- max-frequency = <50000000>; +- cap-sd-highspeed; +- r_smpl = <1>; +- cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +- assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; +-}; +- +-&nandc { +- pinctrl-names = "default"; +- pinctrl-0 = <¶llel_nand_pins>; +- status = "disabled"; +-}; +- +-&nor_flash { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_nor_pins>; +- status = "disabled"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- }; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_pins>; +- status = "okay"; +-}; +- +-&pio { +- /* Attention: GPIO 90 is used to switch between PCIe@1,0 and +- * SATA functions. i.e. output-high: PCIe, output-low: SATA +- */ +- asm_sel { +- gpio-hog; +- gpios = <90 GPIO_ACTIVE_HIGH>; +- output-high; +- }; +- +- /* eMMC is shared pin with parallel NAND */ +- emmc_pins_default: emmc-pins-default { +- mux { +- function = "emmc", "emmc_rst"; +- groups = "emmc"; +- }; +- +- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", +- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, +- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively +- */ +- conf-cmd-dat { +- pins = "NDL0", "NDL1", "NDL2", +- "NDL3", "NDL4", "NDL5", +- "NDL6", "NDL7", "NRB"; +- input-enable; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "NCLE"; +- bias-pull-down; +- }; +- }; +- +- emmc_pins_uhs: emmc-pins-uhs { +- mux { +- function = "emmc"; +- groups = "emmc"; +- }; +- +- conf-cmd-dat { +- pins = "NDL0", "NDL1", "NDL2", +- "NDL3", "NDL4", "NDL5", +- "NDL6", "NDL7", "NRB"; +- input-enable; +- drive-strength = <4>; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "NCLE"; +- drive-strength = <4>; +- bias-pull-down; +- }; +- }; +- +- eth_pins: eth-pins { +- mux { +- function = "eth"; +- groups = "mdc_mdio", "rgmii_via_gmac2"; +- }; +- }; +- +- i2c1_pins: i2c1-pins { +- mux { +- function = "i2c"; +- groups = "i2c1_0"; +- }; +- }; +- +- i2c2_pins: i2c2-pins { +- mux { +- function = "i2c"; +- groups = "i2c2_0"; +- }; +- }; +- +- i2s1_pins: i2s1-pins { +- mux { +- function = "i2s"; +- groups = "i2s_out_mclk_bclk_ws", +- "i2s1_in_data", +- "i2s1_out_data"; +- }; +- +- conf { +- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", +- "I2S_WS", "I2S_MCLK"; +- drive-strength = <12>; +- bias-pull-down; +- }; +- }; +- +- irrx_pins: irrx-pins { +- mux { +- function = "ir"; +- groups = "ir_1_rx"; +- }; +- }; +- +- irtx_pins: irtx-pins { +- mux { +- function = "ir"; +- groups = "ir_1_tx"; +- }; +- }; +- +- /* Parallel nand is shared pin with eMMC */ +- parallel_nand_pins: parallel-nand-pins { +- mux { +- function = "flash"; +- groups = "par_nand"; +- }; +- }; +- +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie0_pad_perst", +- "pcie0_1_waken", +- "pcie0_1_clkreq"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie1_pad_perst", +- "pcie1_0_waken", +- "pcie1_0_clkreq"; +- }; +- }; +- +- pmic_bus_pins: pmic-bus-pins { +- mux { +- function = "pmic"; +- groups = "pmic_bus"; +- }; +- }; +- +- pwm7_pins: pwm1-2-pins { +- mux { +- function = "pwm"; +- groups = "pwm_ch7_2"; +- }; +- }; +- +- wled_pins: wled-pins { +- mux { +- function = "led"; +- groups = "wled"; +- }; +- }; +- +- sd0_pins_default: sd0-pins-default { +- mux { +- function = "sd"; +- groups = "sd_0"; +- }; +- +- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", +- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, +- * DAT2, DAT3, CMD, CLK for SD respectively. +- */ +- conf-cmd-data { +- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", +- "I2S2_IN","I2S4_OUT"; +- input-enable; +- drive-strength = <8>; +- bias-pull-up; +- }; +- conf-clk { +- pins = "I2S3_OUT"; +- drive-strength = <12>; +- bias-pull-down; +- }; +- conf-cd { +- pins = "TXD3"; +- bias-pull-up; +- }; +- }; +- +- sd0_pins_uhs: sd0-pins-uhs { +- mux { +- function = "sd"; +- groups = "sd_0"; +- }; +- +- conf-cmd-data { +- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", +- "I2S2_IN","I2S4_OUT"; +- input-enable; +- bias-pull-up; +- }; +- +- conf-clk { +- pins = "I2S3_OUT"; +- bias-pull-down; +- }; +- }; +- +- /* Serial NAND is shared pin with SPI-NOR */ +- serial_nand_pins: serial-nand-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- spic0_pins: spic0-pins { +- mux { +- function = "spi"; +- groups = "spic0_0"; +- }; +- }; +- +- spic1_pins: spic1-pins { +- mux { +- function = "spi"; +- groups = "spic1_0"; +- }; +- }; +- +- /* SPI-NOR is shared pin with serial NAND */ +- spi_nor_pins: spi-nor-pins { +- mux { +- function = "flash"; +- groups = "spi_nor"; +- }; +- }; +- +- /* serial NAND is shared pin with SPI-NOR */ +- serial_nand_pins: serial-nand-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- uart0_pins: uart0-pins { +- mux { +- function = "uart"; +- groups = "uart0_0_tx_rx" ; +- }; +- }; +- +- uart2_pins: uart2-pins { +- mux { +- function = "uart"; +- groups = "uart2_1_tx_rx" ; +- }; +- }; +- +- watchdog_pins: watchdog-pins { +- mux { +- function = "watchdog"; +- groups = "watchdog"; +- }; +- }; +-}; +- +-&pwm { +- pinctrl-names = "default"; +- pinctrl-0 = <&pwm7_pins>; +- status = "okay"; +-}; +- +-&pwrap { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_bus_pins>; +- +- status = "okay"; +-}; +- +-&sata { +- status = "disable"; +-}; +- +-&sata_phy { +- status = "disable"; +-}; +- +-&snfi { +- pinctrl-names = "default"; +- pinctrl-0 = <&serial_nand_pins>; +- status = "okay"; +- +- spi_nand@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- spi-max-frequency = <104000000>; +- reg = <0>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "Preloader"; +- reg = <0x00000 0x0080000>; +- read-only; +- }; +- +- partition@80000 { +- label = "ATF"; +- reg = <0x80000 0x0040000>; +- }; +- +- partition@c0000 { +- label = "Bootloader"; +- reg = <0xc0000 0x0080000>; +- }; +- +- partition@140000 { +- label = "Config"; +- reg = <0x140000 0x0080000>; +- }; +- +- factory: partition@1c0000 { +- label = "Factory"; +- reg = <0x1c0000 0x0040000>; +- }; +- +- partition@200000 { +- label = "kernel"; +- reg = <0x200000 0x400000>; +- }; +- +- partition@600000 { +- label = "ubi"; +- reg = <0x600000 0x1C00000>; +- }; +- +- partition@2200000 { +- label = "User_data"; +- reg = <0x2200000 0x4000000>; +- }; +- }; +- }; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spic0_pins>; +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spic1_pins>; +- status = "okay"; +-}; +- +-&ssusb { +- vusb33-supply = <®_3p3v>; +- vbus-supply = <®_5v>; +- status = "okay"; +-}; +- +-&u3phy { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-&watchdog { +- pinctrl-names = "default"; +- pinctrl-0 = <&watchdog_pins>; +- status = "okay"; +-}; +- +-&wmac { +- mediatek,mtd-eeprom = <&factory 0x0000>; +- status = "okay"; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-ubnt-unifi-6-lr.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-ubnt-unifi-6-lr.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-ubnt-unifi-6-lr.dts 2023-02-26 09:01:19.879971900 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-ubnt-unifi-6-lr.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,327 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +- +-/dts-v1/; +-#include +-#include +-#include +- +-#include "mt7622.dtsi" +-#include "mt6380.dtsi" +- +-/ { +- model = "Ubiquiti UniFi 6 LR"; +- compatible = "ubnt,unifi-6-lr", "mediatek,mt7622"; +- +- aliases { +- led-boot = &led_blue; +- led-failsafe = &led_blue; +- led-running = &led_blue; +- led-upgrade = &led_blue; +- label-mac-device = &gmac0; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8"; +- }; +- +- cpus { +- cpu@0 { +- proc-supply = <&mt6380_vcpu_reg>; +- sram-supply = <&mt6380_vm_reg>; +- }; +- +- cpu@1 { +- proc-supply = <&mt6380_vcpu_reg>; +- sram-supply = <&mt6380_vm_reg>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- reset { +- label = "reset"; +- linux,code = ; +- gpios = <&pio 62 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x3f000000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&slot0 { +- wifi@0,0 { +- reg = <0x0 0 0 0 0>; +- mediatek,mtd-eeprom = <&factory 0x20000>; +- mtd-mac-address = <&eeprom 0x6>; +- ieee80211-freq-limit = <5000000 6000000>; +- }; +-}; +- +-&pio { +- eth_pins: eth-pins { +- mux { +- function = "eth"; +- groups = "mdc_mdio", "rgmii_via_gmac2"; +- }; +- }; +- +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie0_pad_perst", +- "pcie0_1_waken", +- "pcie0_1_clkreq"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie1_pad_perst", +- "pcie1_0_waken", +- "pcie1_0_clkreq"; +- }; +- }; +- +- pmic_bus_pins: pmic-bus-pins { +- mux { +- function = "pmic"; +- groups = "pmic_bus"; +- }; +- }; +- +- spi_nor_pins: spi-nor-pins { +- mux { +- function = "flash"; +- groups = "spi_nor"; +- }; +- }; +- +- uart0_pins: uart0-pins { +- mux { +- function = "uart"; +- groups = "uart0_0_tx_rx" ; +- }; +- }; +- +- uart3_pins: uart3-pins { +- mux { +- function = "uart"; +- groups = "uart3_1_tx_rx" ; +- }; +- }; +- +- i2c0_pins: i2c0-pins { +- mux { +- function = "i2c"; +- groups = "i2c0"; +- }; +- }; +- +- watchdog_pins: watchdog-pins { +- mux { +- function = "watchdog"; +- groups = "watchdog"; +- }; +- }; +-}; +- +-&bch { +- status = "okay"; +-}; +- +-&btif { +- status = "disabled"; +-}; +- +-ð { +- status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <ð_pins>; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- +- phy-mode = "2500base-x"; +- mtd-mac-address = <&eeprom 0x0>; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethernet-phy@8 { +- /* Marvell AQRate AQR112W - no driver */ +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <0x8>; +- }; +- }; +-}; +- +-&pwrap { +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_bus_pins>; +- +- status = "okay"; +-}; +- +-&nor_flash { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_nor_pins>; +- +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "preloader"; +- reg = <0x0 0x40000>; +- read-only; +- }; +- +- partition@40000 { +- label = "atf"; +- reg = <0x40000 0x20000>; +- read-only; +- }; +- +- partition@60000 { +- label = "u-boot"; +- reg = <0x60000 0x60000>; +- read-only; +- }; +- +- partition@c0000 { +- label = "u-boot-env"; +- reg = <0xc0000 0x10000>; +- }; +- +- factory: partition@d0000 { +- label = "factory"; +- reg = <0xd0000 0x40000>; +- read-only; +- }; +- +- eeprom: partition@110000 { +- label = "eeprom"; +- reg = <0x110000 0x10000>; +- read-only; +- }; +- +- partition@120000 { +- label = "bs"; +- reg = <0x120000 0x10000>; +- }; +- +- partition@130000 { +- label = "cfg"; +- reg = <0x130000 0x100000>; +- read-only; +- }; +- +- partition@230000 { +- compatible = "denx,fit"; +- label = "firmware"; +- reg = <0x230000 0x1ee0000>; +- }; +- +- partition@2110000 { +- label = "kernel1"; +- reg = <0x2110000 0x1ee0000>; +- }; +- }; +- }; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins>; +- status = "okay"; +- +- /* MT7915 Bluetooth */ +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- led-controller@30 { +- compatible = "ubnt,ledbar"; +- reg = <0x30>; +- +- enable-gpio = <&pio 59 0>; +- +- red { +- label = "red"; +- }; +- +- green { +- label = "green"; +- }; +- +- led_blue: blue { +- label = "blue"; +- }; +- }; +-}; +- +-&watchdog { +- pinctrl-names = "default"; +- pinctrl-0 = <&watchdog_pins>; +- status = "okay"; +-}; +- +-&wmac { +- mediatek,mtd-eeprom = <&factory 0x0>; +- mtd-mac-address = <&eeprom 0x0>; +- status = "okay"; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi 2023-02-26 09:01:19.889971600 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi 2023-02-26 09:22:13.529444900 +0800 +@@ -140,12 +140,6 @@ + #size-cells = <2>; + ranges; + +- ramoops@42ff0000 { +- compatible = "ramoops"; +- reg = <0 0x42ff0000 0 0x10000>; +- record-size = <0x1000>; +- }; +- + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts 2023-02-26 09:01:19.881972500 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,70 +0,0 @@ +-/dts-v1/; +-#include "mt7981-360-t7-base.dtsi" +- +-/ { +- nmbm_spim_nand { +- compatible = "generic,nmbm"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- lower-mtd-device = <&spi_nand>; +- forced-create; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "BL2"; +- reg = <0x00 0x100000>; +- }; +- +- partition@100000 { +- label = "u-boot-env"; +- reg = <0x100000 0x80000>; +- }; +- +- partition@180000 { +- label = "Factory"; +- reg = <0x180000 0x200000>; +- }; +- +- partition@380000 { +- label = "FIP"; +- reg = <0x380000 0x200000>; +- }; +- +- partition@580000 { +- label = "ubi"; +- reg = <0x580000 0x2400000>; +- }; +- +- partition@2980000 { +- label = "firmware-1"; +- reg = <0x2980000 0x2400000>; +- }; +- +- partition@4D80000 { +- label = "plugin"; +- reg = <0x4d80000 0x2400000>; +- }; +- +- partition@7180000 { +- label = "stock-config"; +- reg = <0x7180000 0x100000>; +- }; +- +- partition@7280000 { +- label = "stock-factory"; +- reg = <0x7280000 0x80000>; +- }; +- +- partition@7300000 { +- label = "stock-log"; +- reg = <0x7300000 0x400000>; +- }; +- }; +- }; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts 2023-02-26 09:01:19.881069000 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,60 +0,0 @@ +-/dts-v1/; +-#include "mt7981-360-t7-base.dtsi" +- +-/ { +- nmbm_spim_nand { +- compatible = "generic,nmbm"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- lower-mtd-device = <&spi_nand>; +- forced-create; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "BL2"; +- reg = <0x00 0x100000>; +- }; +- +- partition@100000 { +- label = "u-boot-env"; +- reg = <0x100000 0x80000>; +- }; +- +- partition@180000 { +- label = "Factory"; +- reg = <0x180000 0x200000>; +- }; +- +- partition@380000 { +- label = "FIP"; +- reg = <0x380000 0x200000>; +- }; +- +- partition@580000 { +- label = "ubi"; +- reg = <0x580000 0x6c00000>; +- }; +- +- partition@7180000 { +- label = "stock-config"; +- reg = <0x7180000 0x100000>; +- }; +- +- partition@7280000 { +- label = "stock-factory"; +- reg = <0x7280000 0x80000>; +- }; +- +- partition@7300000 { +- label = "stock-log"; +- reg = <0x7300000 0x400000>; +- }; +- }; +- }; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi 2023-02-26 09:01:19.881069000 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi 1970-01-01 08:00:00.000000000 +0800 +@@ -1,217 +0,0 @@ +-/dts-v1/; +-#include "mt7981.dtsi" +- +-/ { +- model = "360 T7"; +- compatible = "360,t7", "mediatek,mt7981"; +- +- aliases { +- led-boot = &red_led; +- led-failsafe = &red_led; +- led-running = &green_led; +- led-upgrade = &green_led; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n1 loglevel=8 \ +- earlycon=uart8250,mmio32,0x11002000"; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x10000000>; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- green_led: green { +- label = "360t7:green"; +- gpios = <&pio 7 GPIO_ACTIVE_LOW>; +- }; +- +- red_led: red { +- label = "360t7:red"; +- gpios = <&pio 3 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- reset { +- label = "reset"; +- linux,code = ; +- gpios = <&pio 1 GPIO_ACTIVE_LOW>; +- }; +- +- wps { +- label = "wps"; +- linux,code = ; +- gpios = <&pio 0 GPIO_ACTIVE_LOW>; +- }; +- }; +- +- gsw: gsw@0 { +- compatible = "mediatek,mt753x"; +- mediatek,ethsys = <ðsys>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "2500base-x"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "2500base-x"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&gsw { +- mediatek,mdio = <&mdio>; +- mediatek,mdio_master_pinmux = <0>; +- reset-gpios = <&pio 39 0>; +- interrupt-parent = <&pio>; +- interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; +- status = "okay"; +- +- port5: port@5 { +- compatible = "mediatek,mt753x-port"; +- reg = <5>; +- phy-mode = "sgmii"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +- +- port6: port@6 { +- compatible = "mediatek,mt753x-port"; +- mediatek,ssc-on; +- reg = <6>; +- phy-mode = "sgmii"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +-}; +- +-&hnat { +- mtketh-wan = "eth1"; +- mtketh-lan = "eth0"; +- mtketh-max-gmac = <2>; +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_flash_pins>; +- status = "okay"; +- +- spi_nand: spi_nand@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- reg = <0>; +- spi-max-frequency = <52000000>; +- spi-tx-buswidth = <4>; +- spi-rx-buswidth = <4>; +- spi-cal-enable; +- spi-cal-mode = "read-data"; +- spi-cal-datalen = <7>; +- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; /* 'SPINAND' */ +- spi-cal-addrlen = <5>; +- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; +- }; +-}; +- +-&pio { +- pwm0_pin: pwm0-pin-g0 { +- mux { +- function = "pwm"; +- groups = "pwm0_0"; +- }; +- }; +- +- pwm1_pin: pwm1-pin-g0 { +- mux { +- function = "pwm"; +- groups = "pwm1_0"; +- }; +- }; +- +- pwm2_pin: pwm2-pin { +- mux { +- function = "pwm"; +- groups = "pwm2"; +- }; +- }; +- +- spi0_flash_pins: spi0-pins { +- mux { +- function = "spi"; +- groups = "spi0", "spi0_wp_hold"; +- }; +- +- conf-pu { +- pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; +- drive-strength = ; +- bias-pull-up = ; +- }; +- +- conf-pd { +- pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; +- drive-strength = ; +- bias-pull-down = ; +- }; +- }; +- +- uart1_pins: uart1-pins-g1 { +- mux { +- function = "uart"; +- groups = "uart1_1"; +- }; +- }; +- +- uart2_pins: uart2-pins-g1 { +- mux { +- function = "uart"; +- groups = "uart2_1"; +- }; +- }; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi 2023-02-26 09:01:19.900973100 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi 2023-02-26 09:22:13.650749300 +0800 +@@ -124,12 +124,6 @@ + #size-cells = <2>; + ranges; + +- ramoops@42ff0000 { +- compatible = "ramoops"; +- reg = <0 0x42ff0000 0 0x10000>; +- record-size = <0x1000>; +- }; +- + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-emmc-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-emmc-rfb.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-emmc-rfb.dts 2023-02-26 09:01:19.893973500 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-emmc-rfb.dts 2023-02-26 09:22:13.585278500 +0800 +@@ -68,7 +68,7 @@ + &uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +- status = "okay"; ++ status = "disabled"; + }; + + &i2c0 { +@@ -102,6 +102,9 @@ + speed = <2500>; + full-duplex; + pause; ++ link-gpio = <&pio 47 0>; ++ phy-handle = <&phy5>; ++ label = "lan5"; + }; + }; + +@@ -109,7 +112,14 @@ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; +- phy-handle = <&phy6>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ link-gpio = <&pio 46 0>; ++ phy-handle = <&phy6>; ++ }; + }; + + mdio: mdio-bus { +@@ -120,12 +130,12 @@ + reset-delay-us = <600>; + + phy5: phy@5 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + }; + + phy6: phy@6 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + +@@ -167,7 +177,12 @@ + reg = <5>; + label = "lan5"; + phy-mode = "2500base-x"; +- phy-handle = <&phy5>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; + }; + + port@6 { +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-gsw-spim-nand-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-gsw-spim-nand-rfb.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-gsw-spim-nand-rfb.dts 2023-02-26 09:01:19.893973500 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-gsw-spim-nand-rfb.dts 2023-02-26 09:22:13.590311200 +0800 +@@ -101,7 +101,14 @@ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; +- phy-handle = <&phy6>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ link-gpio = <&pio 46 0>; ++ phy-handle = <&phy6>; ++ }; + }; + + mdio: mdio-bus { +@@ -117,7 +124,7 @@ + }; + + phy6: phy@6 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + }; +@@ -141,6 +148,7 @@ + speed = <2500>; + full-duplex; + }; ++ + }; + + port6: port@6 { +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-sd-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-sd-rfb.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-sd-rfb.dts 2023-02-26 09:01:19.894972800 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-sd-rfb.dts 2023-02-26 09:22:13.595335800 +0800 +@@ -59,7 +59,7 @@ + &uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +- status = "okay"; ++ status = "disabled"; + }; + + &i2c0 { +@@ -93,6 +93,9 @@ + speed = <2500>; + full-duplex; + pause; ++ link-gpio = <&pio 47 0>; ++ phy-handle = <&phy5>; ++ label = "lan5"; + }; + }; + +@@ -100,7 +103,14 @@ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; +- phy-handle = <&phy6>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ link-gpio = <&pio 46 0>; ++ phy-handle = <&phy6>; ++ }; + }; + + mdio: mdio-bus { +@@ -111,12 +121,12 @@ + reset-delay-us = <600>; + + phy5: phy@5 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + }; + + phy6: phy@6 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + +@@ -158,7 +168,12 @@ + reg = <5>; + label = "lan5"; + phy-mode = "2500base-x"; +- phy-handle = <&phy5>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; + }; + + port@6 { +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nand-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nand-rfb.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nand-rfb.dts 2023-02-26 09:01:19.894972800 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nand-rfb.dts 2023-02-26 09:22:13.604310900 +0800 +@@ -50,7 +50,7 @@ + &uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +- status = "okay"; ++ status = "disabled"; + }; + + &i2c0 { +@@ -84,6 +84,9 @@ + speed = <2500>; + full-duplex; + pause; ++ link-gpio = <&pio 47 0>; ++ phy-handle = <&phy5>; ++ label = "lan5"; + }; + }; + +@@ -91,7 +94,14 @@ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; +- phy-handle = <&phy6>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ link-gpio = <&pio 46 0>; ++ phy-handle = <&phy6>; ++ }; + }; + + mdio: mdio-bus { +@@ -102,12 +112,12 @@ + reset-delay-us = <600>; + + phy5: phy@5 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + }; + + phy6: phy@6 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + +@@ -149,7 +159,12 @@ + reg = <5>; + label = "lan5"; + phy-mode = "2500base-x"; +- phy-handle = <&phy5>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; + }; + + port@6 { +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nor-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nor-rfb.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nor-rfb.dts 2023-02-26 09:01:19.895973300 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nor-rfb.dts 2023-02-26 09:22:13.609018800 +0800 +@@ -84,6 +84,9 @@ + speed = <2500>; + full-duplex; + pause; ++ link-gpio = <&pio 47 0>; ++ phy-handle = <&phy5>; ++ label = "lan5"; + }; + }; + +@@ -91,7 +94,14 @@ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; +- phy-handle = <&phy6>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ link-gpio = <&pio 46 0>; ++ phy-handle = <&phy6>; ++ }; + }; + + mdio: mdio-bus { +@@ -102,12 +112,12 @@ + reset-delay-us = <600>; + + phy5: phy@5 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + }; + + phy6: phy@6 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + +@@ -149,7 +159,12 @@ + reg = <5>; + label = "lan5"; + phy-mode = "2500base-x"; +- phy-handle = <&phy5>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; + }; + + port@6 { +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dts 2023-02-26 09:01:19.899973100 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,61 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +- +-/dts-v1/; +-#include "mt7986a-xiaomi-redmi-router-ax6000.dtsi" +- +-/ { +- nmbm_spim_nand { +- compatible = "generic,nmbm"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- lower-mtd-device = <&spi_nand>; +- forced-create; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <0x01>; +- #size-cells = <0x01>; +- +- partition@0 { +- label = "BL2"; +- reg = <0x00 0x100000>; +- }; +- +- partition@100000 { +- label = "Nvram"; +- reg = <0x100000 0x40000>; +- }; +- +- partition@140000 { +- label = "Bdata"; +- reg = <0x140000 0x40000>; +- }; +- +- partition@180000 { +- label = "Factory"; +- reg = <0x180000 0x200000>; +- }; +- +- partition@380000 { +- label = "FIP"; +- reg = <0x380000 0x200000>; +- }; +- +- partition@580000 { +- label = "crash"; +- reg = <0x580000 0x40000>; +- }; +- +- partition@5c0000 { +- label = "crash_log"; +- reg = <0x5c0000 0x40000>; +- }; +- +- partition@600000 { +- label = "ubi"; +- reg = <0x600000 0x6e00000>; +- }; +- }; +- }; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dtsi openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dtsi +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dtsi 2023-02-26 09:01:19.899973100 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dtsi 1970-01-01 08:00:00.000000000 +0800 +@@ -1,244 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +- +-/dts-v1/; +-#include +-#include +-#include +- +-#include "mt7986a.dtsi" +-#include "mt7986a-pinctrl.dtsi" +- +-/ { +- model = "Xiaomi Redmi Router AX6000"; +- compatible = "xiaomi,redmi-router-ax6000", "mediatek,mt7986a"; +- +- aliases { +- led-boot = &led_status_rgb; +- led-failsafe = &led_status_rgb; +- led-running = &led_status_rgb; +- led-upgrade = &led_status_rgb; +- }; +- +- chosen { +- bootargs = "console=ttyS0,115200n1 loglevel=8 earlycon=uart8250,mmio32,0x11002000"; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x10000000>; +- }; +- +- gsw: gsw@0 { +- compatible = "mediatek,mt753x"; +- mediatek,ethsys = <ðsys>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- keys { +- compatible = "gpio-keys"; +- +- reset { +- label = "reset"; +- gpios = <&pio 9 GPIO_ACTIVE_LOW>; +- linux,code = ; +- }; +- +- mesh { +- label = "mesh"; +- gpios = <&pio 10 GPIO_ACTIVE_LOW>; +- linux,code = ; +- linux,input-type = ; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "2500base-x"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "2500base-x"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&gsw { +- mediatek,mdio = <&mdio>; +- mediatek,mdio_master_pinmux = <0>; +- reset-gpios = <&pio 5 0>; +- interrupt-parent = <&pio>; +- interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; +- status = "okay"; +- +- port5: port@5 { +- compatible = "mediatek,mt753x-port"; +- reg = <5>; +- phy-mode = "sgmii"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +- +- port6: port@6 { +- compatible = "mediatek,mt753x-port"; +- mediatek,ssc-on; +- reg = <6>; +- phy-mode = "sgmii"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +-}; +- +-&hnat { +- mtketh-wan = "eth1"; +- mtketh-lan = "eth0"; +- mtketh-max-gmac = <2>; +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_flash_pins>; +- cs-gpios = <0>, <0>; +- status = "okay"; +- +- spi_nand: spi_nand@1 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- reg = <1>; +- spi-max-frequency = <52000000>; +- spi-tx-buswidth = <4>; +- spi-rx-buswidth = <4>; +- spi-cal-enable; +- spi-cal-mode = "read-data"; +- spi-cal-datalen = <7>; +- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; /* 'SPINAND' */ +- spi-cal-addrlen = <5>; +- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; +- }; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spic_pins_g2>; +- status = "okay"; +- +- ws2812b@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "worldsemi,ws2812b"; +- reg = <0>; +- spi-max-frequency = <3000000>; +- +- led_status_rgb: led@0 { +- reg = <0>; +- label = "rgb:status"; +- color-index = ; +- color-intensity = <0 255 0>; /* GREEN */ +- }; +- +- led_network_rgb: led@1 { +- reg = <1>; +- label = "rgb:network"; +- color-index = ; +- color-intensity = <0 0 255>; /* BLUE */ +- }; +- }; +-}; +- +-&wbsys { +- status = "okay"; +- pinctrl-names = "default", "dbdc"; +- pinctrl-0 = <&wf_2g_5g_pins>; +- pinctrl-1 = <&wf_dbdc_pins>; +-}; +- +-&pio { +- spi_flash_pins: spi-flash-pins-33-to-38 { +- mux { +- function = "flash"; +- groups = "spi0", "spi0_wp_hold"; +- }; +- conf-pu { +- pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; +- drive-strength = <8>; +- mediatek,pull-up-adv = <0>; +- }; +- conf-pd { +- pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; +- drive-strength = <8>; +- mediatek,pull-down-adv = <0>; +- }; +- }; +- +- wf_2g_5g_pins: wf_2g_5g-pins { +- mux { +- function = "wifi"; +- groups = "wf_2g", "wf_5g"; +- }; +- conf { +- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", +- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", +- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", +- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", +- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", +- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", +- "WF1_TOP_CLK", "WF1_TOP_DATA"; +- drive-strength = ; +- }; +- }; +- +- wf_dbdc_pins: wf_dbdc-pins { +- mux { +- function = "wifi"; +- groups = "wf_dbdc"; +- }; +- conf { +- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", +- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", +- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", +- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", +- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", +- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", +- "WF1_TOP_CLK", "WF1_TOP_DATA"; +- drive-strength = ; +- }; +- }; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000-stock.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000-stock.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000-stock.dts 2023-02-26 09:01:19.898973300 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000-stock.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,69 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +- +-/dts-v1/; +-#include "mt7986a-xiaomi-redmi-router-ax6000.dtsi" +- +-/ { +- model = "Xiaomi Redmi Router AX6000 (stock layout)"; +- compatible = "xiaomi,redmi-router-ax6000-stock", "mediatek,mt7986a"; +- +- nmbm_spim_nand { +- compatible = "generic,nmbm"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- lower-mtd-device = <&spi_nand>; +- forced-create; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <0x01>; +- #size-cells = <0x01>; +- +- partition@0 { +- label = "BL2"; +- reg = <0x00 0x100000>; +- }; +- +- partition@100000 { +- label = "Nvram"; +- reg = <0x100000 0x40000>; +- }; +- +- partition@140000 { +- label = "Bdata"; +- reg = <0x140000 0x40000>; +- }; +- +- partition@180000 { +- label = "Factory"; +- reg = <0x180000 0x200000>; +- }; +- +- partition@380000 { +- label = "FIP"; +- reg = <0x380000 0x200000>; +- }; +- +- partition@580000 { +- label = "crash"; +- reg = <0x580000 0x40000>; +- }; +- +- partition@5c0000 { +- label = "crash_log"; +- reg = <0x5c0000 0x40000>; +- }; +- +- partition@600000 { +- label = "ubi_kernel"; +- reg = <0x600000 0x1e00000>; +- }; +- +- partition@2400000 { +- label = "ubi"; +- reg = <0x2400000 0x5000000>; +- }; +- }; +- }; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-emmc-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-emmc-rfb.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-emmc-rfb.dts 2023-02-26 09:01:19.900973100 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-emmc-rfb.dts 2023-02-26 09:22:13.661752900 +0800 +@@ -64,6 +64,9 @@ + speed = <2500>; + full-duplex; + pause; ++ link-gpio = <&pio 47 0>; ++ phy-handle = <&phy5>; ++ label = "lan5"; + }; + }; + +@@ -71,7 +74,14 @@ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; +- phy-handle = <&phy6>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ link-gpio = <&pio 46 0>; ++ phy-handle = <&phy6>; ++ }; + }; + + mdio: mdio-bus { +@@ -82,12 +92,12 @@ + reset-delay-us = <600>; + + phy5: phy@5 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + }; + + phy6: phy@6 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + +@@ -129,7 +139,12 @@ + reg = <5>; + label = "lan5"; + phy-mode = "2500base-x"; +- phy-handle = <&phy5>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; + }; + + port@6 { +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-gsw-spim-nand-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-gsw-spim-nand-rfb.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-gsw-spim-nand-rfb.dts 2023-02-26 09:01:19.901972100 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-gsw-spim-nand-rfb.dts 2023-02-26 09:22:13.670785000 +0800 +@@ -72,7 +72,14 @@ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; +- phy-handle = <&phy6>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ link-gpio = <&pio 46 0>; ++ phy-handle = <&phy6>; ++ }; + }; + + mdio: mdio-bus { +@@ -88,7 +95,7 @@ + }; + + phy6: phy@6 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + }; +@@ -112,6 +119,7 @@ + speed = <2500>; + full-duplex; + }; ++ + }; + + port6: port@6 { +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-sd-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-sd-rfb.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-sd-rfb.dts 2023-02-26 09:01:19.901972100 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-sd-rfb.dts 2023-02-26 09:22:13.676750700 +0800 +@@ -64,6 +64,9 @@ + speed = <2500>; + full-duplex; + pause; ++ link-gpio = <&pio 47 0>; ++ phy-handle = <&phy5>; ++ label = "lan5"; + }; + }; + +@@ -71,7 +74,14 @@ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; +- phy-handle = <&phy6>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ link-gpio = <&pio 46 0>; ++ phy-handle = <&phy6>; ++ }; + }; + + mdio: mdio-bus { +@@ -82,12 +92,12 @@ + reset-delay-us = <600>; + + phy5: phy@5 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + }; + + phy6: phy@6 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + +@@ -129,7 +139,12 @@ + reg = <5>; + label = "lan5"; + phy-mode = "2500base-x"; +- phy-handle = <&phy5>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; + }; + + port@6 { +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-snfi-nand-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-snfi-nand-rfb.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-snfi-nand-rfb.dts 2023-02-26 09:01:19.902972900 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-snfi-nand-rfb.dts 2023-02-26 09:22:13.681750700 +0800 +@@ -55,6 +55,9 @@ + speed = <2500>; + full-duplex; + pause; ++ link-gpio = <&pio 47 0>; ++ phy-handle = <&phy5>; ++ label = "lan5"; + }; + }; + +@@ -62,7 +65,14 @@ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; +- phy-handle = <&phy6>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ link-gpio = <&pio 46 0>; ++ phy-handle = <&phy6>; ++ }; + }; + + mdio: mdio-bus { +@@ -73,12 +83,12 @@ + reset-delay-us = <600>; + + phy5: phy@5 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + }; + + phy6: phy@6 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + +@@ -120,7 +130,12 @@ + reg = <5>; + label = "lan5"; + phy-mode = "2500base-x"; +- phy-handle = <&phy5>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; + }; + + port@6 { +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nand-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nand-rfb.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nand-rfb.dts 2023-02-26 09:01:19.903971500 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nand-rfb.dts 2023-02-26 09:22:13.689750600 +0800 +@@ -55,6 +55,9 @@ + speed = <2500>; + full-duplex; + pause; ++ link-gpio = <&pio 47 0>; ++ phy-handle = <&phy5>; ++ label = "lan5"; + }; + }; + +@@ -62,7 +65,14 @@ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; +- phy-handle = <&phy6>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ link-gpio = <&pio 46 0>; ++ phy-handle = <&phy6>; ++ }; + }; + + mdio: mdio-bus { +@@ -73,12 +83,12 @@ + reset-delay-us = <600>; + + phy5: phy@5 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + }; + + phy6: phy@6 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + +@@ -120,7 +130,12 @@ + reg = <5>; + label = "lan5"; + phy-mode = "2500base-x"; +- phy-handle = <&phy5>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; + }; + + port@6 { +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nor-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nor-rfb.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nor-rfb.dts 2023-02-26 09:01:19.903971500 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nor-rfb.dts 2023-02-26 09:22:13.694751600 +0800 +@@ -55,6 +55,9 @@ + speed = <2500>; + full-duplex; + pause; ++ link-gpio = <&pio 47 0>; ++ phy-handle = <&phy5>; ++ label = "lan5"; + }; + }; + +@@ -62,7 +65,14 @@ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; +- phy-handle = <&phy6>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ link-gpio = <&pio 46 0>; ++ phy-handle = <&phy6>; ++ }; + }; + + mdio: mdio-bus { +@@ -73,12 +83,12 @@ + reset-delay-us = <600>; + + phy5: phy@5 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + }; + + phy6: phy@6 { +- compatible = "ethernet-phy-ieee802.3-c45"; ++ compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + +@@ -120,7 +130,12 @@ + reg = <5>; + label = "lan5"; + phy-mode = "2500base-x"; +- phy-handle = <&phy5>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; + }; + + port@6 { +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi 2023-02-26 09:01:19.907972100 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi 1970-01-01 08:00:00.000000000 +0800 +@@ -1,1096 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2021 MediaTek Inc. +- * Author: Sam.Shih +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/ { +- compatible = "mediatek,mt7988-rfb"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a73"; +- enable-method = "psci"; +- reg = <0x0>; +- clocks = <&mcusys CK_MCU_ARM_DIV_SEL>, +- <&topckgen CK_TOP_CB_NET1_D4>, +- <&apmixedsys CK_APMIXED_ARM_B>, +- <&mcusys CK_MCU_BUS_DIV_SEL>, +- <&apmixedsys CK_APMIXED_CCIPLL2_B>; +- clock-names = "cpu", "intermediate", "armpll", "cci", +- "ccipll"; +- operating-points-v2 = <&cluster0_opp>; +- nvmem-cells = <&cpufreq_calibration>; +- nvmem-cell-names = "calibration-data"; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a73"; +- enable-method = "psci"; +- reg = <0x1>; +- clocks = <&mcusys CK_MCU_ARM_DIV_SEL>, +- <&topckgen CK_TOP_CB_NET1_D4>, +- <&apmixedsys CK_APMIXED_ARM_B>, +- <&mcusys CK_MCU_BUS_DIV_SEL>, +- <&apmixedsys CK_APMIXED_CCIPLL2_B>; +- clock-names = "cpu", "intermediate", "armpll", "cci", +- "ccipll"; +- operating-points-v2 = <&cluster0_opp>; +- nvmem-cells = <&cpufreq_calibration>; +- nvmem-cell-names = "calibration-data"; +- }; +- +- cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a73"; +- enable-method = "psci"; +- reg = <0x2>; +- clocks = <&mcusys CK_MCU_ARM_DIV_SEL>, +- <&topckgen CK_TOP_CB_NET1_D4>, +- <&apmixedsys CK_APMIXED_ARM_B>, +- <&mcusys CK_MCU_BUS_DIV_SEL>, +- <&apmixedsys CK_APMIXED_CCIPLL2_B>; +- clock-names = "cpu", "intermediate", "armpll", "cci", +- "ccipll"; +- operating-points-v2 = <&cluster0_opp>; +- nvmem-cells = <&cpufreq_calibration>; +- nvmem-cell-names = "calibration-data"; +- }; +- +- cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a73"; +- enable-method = "psci"; +- reg = <0x3>; +- clocks = <&mcusys CK_MCU_ARM_DIV_SEL>, +- <&topckgen CK_TOP_CB_NET1_D4>, +- <&apmixedsys CK_APMIXED_ARM_B>, +- <&mcusys CK_MCU_BUS_DIV_SEL>, +- <&apmixedsys CK_APMIXED_CCIPLL2_B>; +- clock-names = "cpu", "intermediate", "armpll", "cci", +- "ccipll"; +- operating-points-v2 = <&cluster0_opp>; +- nvmem-cells = <&cpufreq_calibration>; +- nvmem-cell-names = "calibration-data"; +- }; +- +- cluster0_opp: opp_table0 { +- compatible = "operating-points-v2"; +- opp-shared; +- opp00 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <850000>; +- }; +- opp01 { +- opp-hz = /bits/ 64 <1100000000>; +- opp-microvolt = <850000>; +- }; +- opp02 { +- opp-hz = /bits/ 64 <1500000000>; +- opp-microvolt = <850000>; +- }; +- opp03 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <900000>; +- }; +- }; +- }; +- +- thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <1000>; +- polling-delay = <1000>; +- thermal-sensors = <&lvts 0>; +- trips { +- cpu_trip_crit: crit { +- temperature = <125000>; +- hysteresis = <2000>; +- type = "critical"; +- }; +- +- cpu_trip_hot: hot { +- temperature = <120000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- cpu_trip_active_high: active-high { +- temperature = <115000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_trip_active_low: active-low { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_trip_passive: passive { +- temperature = <40000>; +- hysteresis = <2000>; +- type = "passive"; +- }; +- }; +- +- cooling-maps { +- cpu-active-high { +- /* active: set fan to cooling level 2 */ +- cooling-device = <&fan 2 2>; +- trip = <&cpu_trip_active_high>; +- }; +- +- cpu-active-low { +- /* active: set fan to cooling level 1 */ +- cooling-device = <&fan 1 1>; +- trip = <&cpu_trip_active_low>; +- }; +- +- cpu-passive { +- /* passive: set fan to cooling level 0 */ +- cooling-device = <&fan 0 0>; +- trip = <&cpu_trip_passive>; +- }; +- }; +- +- }; +- }; +- +- mmc0: mmc@11230000 { +- compatible = "mediatek,mt7986-mmc"; +- reg = <0 0x11230000 0 0x1000>, +- <0 0x11D60000 0 0x1000>; +- interrupts = ; +- clocks = <&infracfg_ao CK_INFRA_MSDC400>, +- <&infracfg_ao CK_INFRA_MSDC2_HCK>, +- <&infracfg_ao CK_INFRA_133M_MSDC_0_HCK>, +- <&infracfg_ao CK_INFRA_66M_MSDC_0_HCK>; +- clock-names = "source", "hclk", "ahb_cg", "axi_cg"; +- status = "disabled"; +- }; +- +- wed: wed@15010000 { +- compatible = "mediatek,wed"; +- wed_num = <3>; +- /* add this property for wed get the pci slot number. */ +- pci_slot_map = <0>, <1>, <2>; +- reg = <0 0x15010000 0 0x2000>, +- <0 0x15012000 0 0x2000>, +- <0 0x15014000 0 0x2000>; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- ; +- }; +- +- wed2: wed2@15012000 { +- compatible = "mediatek,wed2"; +- wed_num = <3>; +- /* add this property for wed get the pci slot number. */ +- reg = <0 0x15010000 0 0x2000>, +- <0 0x15012000 0 0x2000>, +- <0 0x15014000 0 0x2000>; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- ; +- }; +- +- wed3: wed3@15014000 { +- compatible = "mediatek,wed3"; +- wed_num = <3>; +- /* add this property for wed get the pci slot number. */ +- reg = <0 0x15010000 0 0x2000>, +- <0 0x15012000 0 0x2000>, +- <0 0x15014000 0 0x2000>; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- ; +- }; +- +- wdma: wdma@15104800 { +- compatible = "mediatek,wed-wdma"; +- reg = <0 0x15104800 0 0x400>, +- <0 0x15104c00 0 0x400>, +- <0 0x15105000 0 0x400>; +- }; +- +- ap2woccif: ap2woccif@151A5000 { +- compatible = "mediatek,ap2woccif"; +- reg = <0 0x151A5000 0 0x1000>, +- <0 0x152A5000 0 0x1000>, +- <0 0x153A5000 0 0x1000>; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- ; +- }; +- +- wocpu0_ilm: wocpu0_ilm@151E0000 { +- compatible = "mediatek,wocpu0_ilm"; +- reg = <0 0x151E0000 0 0x8000>; +- }; +- +- wocpu1_ilm: wocpu1_ilm@152E0000 { +- compatible = "mediatek,wocpu1_ilm"; +- reg = <0 0x152E0000 0 0x8000>; +- }; +- +- wocpu2_ilm: wocpu2_ilm@153E0000 { +- compatible = "mediatek,wocpu2_ilm"; +- reg = <0 0x153E0000 0 0x8000>; +- }; +- +- wocpu_dlm: wocpu_dlm@151E8000 { +- compatible = "mediatek,wocpu_dlm"; +- reg = <0 0x151E8000 0 0x2000>, +- <0 0x152E8000 0 0x2000>, +- <0 0x153E8000 0 0x2000>; +- +- resets = <ðsysrst 0>; +- reset-names = "wocpu_rst"; +- }; +- +- cpu_boot: wocpu_boot@15194000 { +- compatible = "mediatek,wocpu_boot"; +- reg = <0 0x15194000 0 0x1000>, +- <0 0x15294000 0 0x1000>, +- <0 0x15394000 0 0x1000>; +- }; +- +- reserved-memory { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ +- secmon_reserved: secmon@43000000 { +- reg = <0 0x43000000 0 0x30000>; +- no-map; +- }; +- +- wmcpu_emi: wmcpu-reserved@47CC0000 { +- compatible = "mediatek,wmcpu-reserved"; +- no-map; +- reg = <0 0x47CC0000 0 0x00100000>; +- }; +- +- wocpu0_emi: wocpu0_emi@4F600000 { +- compatible = "mediatek,wocpu0_emi"; +- no-map; +- reg = <0 0x4F600000 0 0x40000>; +- shared = <0>; +- }; +- +- wocpu1_emi: wocpu1_emi@4F640000 { +- compatible = "mediatek,wocpu1_emi"; +- no-map; +- reg = <0 0x4F640000 0 0x40000>; +- shared = <0>; +- }; +- +- wocpu2_emi: wocpu2_emi@4F680000 { +- compatible = "mediatek,wocpu2_emi"; +- no-map; +- reg = <0 0x4F680000 0 0x40000>; +- shared = <0>; +- }; +- +- wocpu_data: wocpu_data@4F700000 { +- compatible = "mediatek,wocpu_data"; +- no-map; +- reg = <0 0x4F700000 0 0x800000>; +- shared = <1>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- system_clk: dummy_system_clk { +- compatible = "fixed-clock"; +- clock-frequency = <40000000>; +- #clock-cells = <0>; +- }; +- +- uart_clk: dummy_uart_clk { +- compatible = "fixed-clock"; +- clock-frequency = <40000000>; +- #clock-cells = <0>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupt-parent = <&gic>; +- interrupts = , +- , +- , +- ; +- +- }; +- +- tops: tops@09100000 { +- compatible = "mediatek,tops"; +- reg = <0 0x09100000 0 0x01000000>; +- reg-names = "tops-base"; +- clocks = <&topckgen CK_TOP_BUS_TOPS_SEL>, +- <&topckgen CK_TOP_TOPS_P2_26M_SEL>, +- <&topckgen CK_TOP_NETSYS_TOPS_400M_SEL>, +- <&topckgen CK_TOP_NPU_TOPS_SEL>, +- <&topckgen CK_TOP_CK_NPU_SEL_CM_TOPS_SEL>; +- clock-names = "bus", "sram", "xdma", "offload", "mgmt"; +- interrupt-parent = <&gic>; +- interrupts = , +- ; +- interrupt-names = "tdma-tx-pause", "mbox"; +- topmisc = <&topmisc>; +- fe_mem = <ð>; +- topckgen = <&topckgen>; +- }; +- hpdma1: hpdma@09106000 { +- compatible = "mediatek,hpdma-top"; +- reg = <0 0x09106000 0 0x1000>; +- reg-names = "base"; +- }; +- hpdma2: hpdma@09606000 { +- compatible = "mediatek,hpdma-sub"; +- reg = <0 0x09606000 0 0x1000>; +- reg-names = "base"; +- }; +- +- watchdog: watchdog@1001c000 { +- compatible = "mediatek,mt7622-wdt", +- "mediatek,mt6589-wdt", +- "syscon"; +- reg = <0 0x1001c000 0 0x1000>; +- interrupts = ; +- #reset-cells = <1>; +- }; +- +- phyfw: phy-firmware@f000000 { +- compatible = "mediatek,2p5gphy-fw"; +- reg = <0 0x0f000000 0 0x8000>, +- <0 0x0f100000 0 0x20000>, +- <0 0x0f0f0000 0 0x200>; +- }; +- +- gic: interrupt-controller@c000000 { +- compatible = "arm,gic-v3"; +- #interrupt-cells = <3>; +- interrupt-parent = <&gic>; +- interrupt-controller; +- reg = <0 0x0c000000 0 0x40000>, /* GICD */ +- <0 0x0c080000 0 0x200000>; /* GICR */ +- +- interrupts = ; +- }; +- +- trng: trng@1020f000 { +- compatible = "mediatek,mt7988-rng"; +- }; +- +- uart0: serial@11000000 { +- compatible = "mediatek,mt7986-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11000000 0 0x100>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart1: serial@11000100 { +- compatible = "mediatek,mt7986-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11000100 0 0x100>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- uart2: serial@11000200 { +- compatible = "mediatek,mt7986-uart", +- "mediatek,mt6577-uart"; +- reg = <0 0x11000200 0 0x100>; +- interrupts = ; +- clocks = <&uart_clk>; +- status = "disabled"; +- }; +- +- i2c0: i2c@11003000 { +- compatible = "mediatek,mt7988-i2c", +- "mediatek,mt7981-i2c"; +- reg = <0 0x11003000 0 0x1000>, +- <0 0x10217080 0 0x80>; +- interrupts = ; +- clock-div = <1>; +- clocks = <&system_clk>, +- <&system_clk>; +- clock-names = "main", "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@11004000 { +- compatible = "mediatek,mt7988-i2c", +- "mediatek,mt7981-i2c"; +- reg = <0 0x11004000 0 0x1000>, +- <0 0x10217100 0 0x80>; +- interrupts = ; +- clock-div = <1>; +- clocks = <&system_clk>, +- <&system_clk>; +- clock-names = "main", "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@11005000 { +- compatible = "mediatek,mt7988-i2c", +- "mediatek,mt7981-i2c"; +- reg = <0 0x11005000 0 0x1000>, +- <0 0x10217180 0 0x80>; +- interrupts = ; +- clock-div = <1>; +- clocks = <&system_clk>, +- <&system_clk>; +- clock-names = "main", "dma"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- pwm: pwm@10048000 { +- compatible = "mediatek,mt7988-pwm"; +- reg = <0 0x10048000 0 0x1000>; +- #pwm-cells = <2>; +- clocks = <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>; +- clock-names = "top", "main", "pwm1", "pwm2", "pwm3", +- "pwm4","pwm5","pwm6","pwm7","pwm8"; +- status = "disabled"; +- }; +- +- fan: pwm-fan { +- compatible = "pwm-fan"; +- /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ +- cooling-levels = <0 128 255>; +- #cooling-cells = <2>; +- #thermal-sensor-cells = <1>; +- status = "disabled"; +- }; +- +- lvts: lvts@1100a000 { +- compatible = "mediatek,mt7988-lvts"; +- #thermal-sensor-cells = <1>; +- reg = <0 0x1100a000 0 0x1000>; +- clocks = <&system_clk>; +- clock-names = "lvts_clk"; +- nvmem-cells = <&lvts_calibration>; +- nvmem-cell-names = "e_data1"; +- }; +- +- crypto: crypto@15600000 { +- compatible = "inside-secure,safexcel-eip197b"; +- reg = <0 0x15600000 0 0x180000>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "ring0", "ring1", "ring2", "ring3"; +- status = "okay"; +- }; +- +- pcie0: pcie@11300000 { +- compatible = "mediatek,mt7988-pcie", +- "mediatek,mt7986-pcie"; +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- reg = <0 0x11300000 0 0x2000>; +- reg-names = "pcie-mac"; +- linux,pci-domain = <0>; +- interrupts = ; +- bus-range = <0x00 0xff>; +- ranges = <0x81000000 0x00 0x30000000 0x00 +- 0x30000000 0x00 0x00200000>, +- <0x82000000 0x00 0x30200000 0x00 +- 0x30200000 0x00 0x07e00000>; +- status = "disabled"; +- +- clocks = <&topckgen CK_TOP_PEXTP_P0_SEL>, +- <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P0>, +- <&infracfg_ao CK_INFRA_PCIE_PIPE_P0>, +- <&infracfg_ao CK_INFRA_133M_PCIE_CK_P0>, +- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P0>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &pcie_intc0 0>, +- <0 0 0 2 &pcie_intc0 1>, +- <0 0 0 3 &pcie_intc0 2>, +- <0 0 0 4 &pcie_intc0 3>; +- pcie_intc0: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- }; +- }; +- +- pcie1: pcie@11310000 { +- compatible = "mediatek,mt7988-pcie", +- "mediatek,mt7986-pcie"; +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- reg = <0 0x11310000 0 0x2000>; +- reg-names = "pcie-mac"; +- linux,pci-domain = <1>; +- interrupts = ; +- bus-range = <0x00 0xff>; +- ranges = <0x81000000 0x00 0x38000000 0x00 +- 0x38000000 0x00 0x00200000>, +- <0x82000000 0x00 0x38200000 0x00 +- 0x38200000 0x00 0x07e00000>; +- status = "disabled"; +- +- clocks = <&topckgen CK_TOP_PEXTP_P1_SEL>, +- <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P1>, +- <&infracfg_ao CK_INFRA_PCIE_PIPE_P1>, +- <&infracfg_ao CK_INFRA_133M_PCIE_CK_P1>, +- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P1>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &pcie_intc1 0>, +- <0 0 0 2 &pcie_intc1 1>, +- <0 0 0 3 &pcie_intc1 2>, +- <0 0 0 4 &pcie_intc1 3>; +- pcie_intc1: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- }; +- }; +- +- pcie2: pcie@11280000 { +- compatible = "mediatek,mt7988-pcie", +- "mediatek,mt7986-pcie"; +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- reg = <0 0x11280000 0 0x2000>; +- reg-names = "pcie-mac"; +- linux,pci-domain = <3>; +- interrupts = ; +- bus-range = <0x00 0xff>; +- ranges = <0x81000000 0x00 0x20000000 0x00 +- 0x20000000 0x00 0x00200000>, +- <0x82000000 0x00 0x20200000 0x00 +- 0x20200000 0x00 0x07e00000>; +- status = "disabled"; +- +- clocks = <&topckgen CK_TOP_PEXTP_P2_SEL>, +- <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P2>, +- <&infracfg_ao CK_INFRA_PCIE_PIPE_P2>, +- <&infracfg_ao CK_INFRA_133M_PCIE_CK_P2>, +- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P2>, +- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P3>; +- +- phys = <&xphyu3port0 PHY_TYPE_PCIE>; +- phy-names = "pcie-phy"; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &pcie_intc2 0>, +- <0 0 0 2 &pcie_intc2 1>, +- <0 0 0 3 &pcie_intc2 2>, +- <0 0 0 4 &pcie_intc2 3>; +- pcie_intc2: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- }; +- }; +- +- pcie3: pcie@11290000 { +- compatible = "mediatek,mt7988-pcie", +- "mediatek,mt7986-pcie"; +- device_type = "pci"; +- #address-cells = <3>; +- #size-cells = <2>; +- reg = <0 0x11290000 0 0x2000>; +- reg-names = "pcie-mac"; +- linux,pci-domain = <2>; +- interrupts = ; +- bus-range = <0x00 0xff>; +- ranges = <0x81000000 0x00 0x28000000 0x00 +- 0x28000000 0x00 0x00200000>, +- <0x82000000 0x00 0x28200000 0x00 +- 0x28200000 0x00 0x07e00000>; +- status = "disabled"; +- +- clocks = <&topckgen CK_TOP_PEXTP_P3_SEL>, +- <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P3>, +- <&infracfg_ao CK_INFRA_PCIE_PIPE_P3>, +- <&infracfg_ao CK_INFRA_133M_PCIE_CK_P3>, +- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P3>; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &pcie_intc3 0>, +- <0 0 0 2 &pcie_intc3 1>, +- <0 0 0 3 &pcie_intc3 2>, +- <0 0 0 4 &pcie_intc3 3>; +- pcie_intc3: interrupt-controller { +- #address-cells = <0>; +- #interrupt-cells = <1>; +- interrupt-controller; +- }; +- }; +- +- pio: pinctrl@1001f000 { +- compatible = "mediatek,mt7988-pinctrl"; +- reg = <0 0x1001f000 0 0x1000>, +- <0 0x11c10000 0 0x1000>, +- <0 0x11d00000 0 0x1000>, +- <0 0x11d20000 0 0x1000>, +- <0 0x11e00000 0 0x1000>, +- <0 0x11f00000 0 0x1000>, +- <0 0x1000b000 0 0x1000>; +- reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base", +- "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", +- "eint"; +- gpio-controller; +- #gpio-cells = <2>; +- gpio-ranges = <&pio 0 0 83>; +- interrupt-controller; +- interrupts = ; +- interrupt-parent = <&gic>; +- #interrupt-cells = <2>; +- }; +- +- ethsys: syscon@15000000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mediatek,mt7988-ethsys", +- "syscon"; +- reg = <0 0x15000000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- +- ethsysrst: reset-controller { +- compatible = "ti,syscon-reset"; +- #reset-cells = <1>; +- ti,reset-bits = +- <0x34 4 0x34 4 0x34 4 +- (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; +- }; +- }; +- +- ethwarp: syscon@15031000 { +- compatible = "mediatek,mt7988-ethwarp", "syscon"; +- reg = <0 0x15031000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- switch0: switch0@15020000 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "mediatek,mt7988-switch", "syscon"; +- reg = <0 0x15020000 0 0x8000>; +- }; +- +- eth: ethernet@15100000 { +- compatible = "mediatek,mt7988-eth"; +- reg = <0 0x15100000 0 0x80000>, +- <0 0x15400000 0 0x380000>; +- interrupts = , +- , +- , +- ; +- clocks = <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>; +- clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", +- "sgmii_tx250m", "sgmii_rx250m", +- "sgmii_cdr_ref", "sgmii_cdr_fb", +- "sgmii2_tx250m", "sgmii2_rx250m", +- "sgmii2_cdr_ref", "sgmii2_cdr_fb"; +- mediatek,ethsys = <ðsys>; +- mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; +- mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>; +- mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>; +- mediatek,xfi_pll = <&xfi_pll>; +- mediatek,infracfg = <&topmisc>; +- mediatek,toprgu = <&watchdog>; +- #reset-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hnat: hnat@15000000 { +- compatible = "mediatek,mtk-hnat_v5"; +- reg = <0 0x15100000 0 0x80000>; +- resets = <ðsys 0>; +- reset-names = "mtketh"; +- status = "disabled"; +- }; +- +- sgmiisys0: syscon@10060000 { +- compatible = "mediatek,mt7988-sgmiisys", +- "mediatek,mt7988-sgmiisys_0", +- "syscon"; +- reg = <0 0x10060000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- sgmiisys1: syscon@10070000 { +- compatible = "mediatek,mt7988-sgmiisys", +- "mediatek,mt7988-sgmiisys_1", +- "syscon"; +- reg = <0 0x10070000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- usxgmiisys0: usxgmiisys@10080000 { +- compatible = "mediatek,mt7988-usxgmiisys", +- "mediatek,mt7988-usxgmiisys_0", +- "syscon"; +- reg = <0 0x10080000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- usxgmiisys1: usxgmiisys@10081000 { +- compatible = "mediatek,mt7988-usxgmiisys", +- "mediatek,mt7988-usxgmiisys_1", +- "syscon"; +- reg = <0 0x10081000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- xfi_pextp0: xfi_pextp@11f20000 { +- compatible = "mediatek,mt7988-xfi_pextp", +- "mediatek,mt7988-xfi_pextp_0", +- "syscon"; +- reg = <0 0x11f20000 0 0x10000>; +- #clock-cells = <1>; +- }; +- +- xfi_pextp1: xfi_pextp@11f30000 { +- compatible = "mediatek,mt7988-xfi_pextp", +- "mediatek,mt7988-xfi_pextp_1", +- "syscon"; +- reg = <0 0x11f30000 0 0x10000>; +- #clock-cells = <1>; +- }; +- +- xfi_pll: xfi_pll@11f40000 { +- compatible = "mediatek,mt7988-xfi_pll", "syscon"; +- reg = <0 0x11f40000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- topmisc: topmisc@11d10000 { +- compatible = "mediatek,mt7988-topmisc", "syscon", +- "mediatek,mt7988-power-controller"; +- reg = <0 0x11d10000 0 0x10000>; +- #clock-cells = <1>; +- #power-domain-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- /* power domain of the SoC */ +- tops0@MT7988_POWER_DOMAIN_TOPS0 { +- reg = ; +- #power-domain-cells = <0>; +- }; +- tops1@MT7988_POWER_DOMAIN_TOPS1 { +- reg = ; +- #power-domain-cells = <0>; +- }; +- eth2p5@MT7988_POWER_DOMAIN_ETH2P5 { +- reg = ; +- #power-domain-cells = <0>; +- }; +- }; +- +- snand: snfi@11001000 { +- compatible = "mediatek,mt7986-snand"; +- reg = <0 0x11001000 0 0x1000>, <0 0x11002000 0 0x1000>; +- reg-names = "nfi", "ecc"; +- interrupts = ; +- clocks = <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>; +- clock-names = "nfi_clk", "pad_clk", "ecc_clk", "nfi_hclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- wbsys: wbsys@18000000 { +- compatible = "mediatek,wbsys"; +- reg = <0 0x18000000 0 0x1000000>; +- linux,pci-domain = <4>; +- interrupts = , +- , +- , +- ; +- chip_id = <0x7981>; +- }; +- +- wed_pcie: wed_pcie@10003000 { +- compatible = "mediatek,wed_pcie"; +- reg = <0 0x10003000 0 0x10>; +- }; +- +- spi0: spi@11007000 { +- compatible = "mediatek,ipm-spi-quad"; +- reg = <0 0x11007000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CK_TOP_CB_M_D2>, +- <&topckgen CK_TOP_SPI_SEL>, +- <&infracfg_ao CK_INFRA_104M_SPI0>, +- <&infracfg_ao CK_INFRA_66M_SPI0_HCK>; +- clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; +- status = "disabled"; +- }; +- +- spi1: spi@11008000 { +- compatible = "mediatek,ipm-spi-single"; +- reg = <0 0x11008000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CK_TOP_CB_M_D2>, +- <&topckgen CK_TOP_SPI_SEL>, +- <&infracfg_ao CK_INFRA_104M_SPI1>, +- <&infracfg_ao CK_INFRA_66M_SPI1_HCK>; +- clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; +- status = "disabled"; +- }; +- +- spi2: spi@11009000 { +- compatible = "mediatek,ipm-spi-quad"; +- reg = <0 0x11009000 0 0x100>; +- interrupts = ; +- clocks = <&topckgen CK_TOP_CB_M_D2>, +- <&topckgen CK_TOP_SPI_SEL>, +- <&infracfg_ao CK_INFRA_104M_SPI2_BCK>, +- <&infracfg_ao CK_INFRA_66M_SPI2_HCK>; +- clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; +- status = "disabled"; +- }; +- +- consys: consys@10000000 { +- compatible = "mediatek,mt7981-consys"; +- reg = <0 0x10000000 0 0x8600000>; +- memory-region = <&wmcpu_emi>; +- }; +- +- xhci0: xhci@11190000 { +- compatible = "mediatek,mt7988-xhci", +- "mediatek,mtk-xhci"; +- reg = <0 0x11190000 0 0x2e00>, +- <0 0x11193e00 0 0x0100>; +- reg-names = "mac", "ippc"; +- interrupts = ; +- phys = <&xphyu2port0 PHY_TYPE_USB2>, +- <&xphyu3port0 PHY_TYPE_USB3>; +- clocks = <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>; +- clock-names = "sys_ck", +- "xhci_ck", +- "ref_ck", +- "mcu_ck", +- "dma_ck"; +- #address-cells = <2>; +- #size-cells = <2>; +- status = "okay"; +- }; +- +- usbxphy: usb-phy@11e10000 { +- compatible = "mediatek,mt7988", +- "mediatek,xsphy"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "okay"; +- +- xphyu2port0: usb-phy@11e10000 { +- reg = <0 0x11e10000 0 0x400>; +- clocks = <&system_clk>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- xphyu3port0: usb-phy@11e13000 { +- reg = <0 0x11e13400 0 0x500>; +- clocks = <&system_clk>; +- clock-names = "ref"; +- #phy-cells = <1>; +- mediatek,syscon-type = <&topmisc 0x218 0>; +- status = "okay"; +- }; +- }; +- +- xhci1: xhci@11200000 { +- compatible = "mediatek,mt7988-xhci", +- "mediatek,mtk-xhci"; +- reg = <0 0x11200000 0 0x2e00>, +- <0 0x11203e00 0 0x0100>; +- reg-names = "mac", "ippc"; +- interrupts = ; +- phys = <&tphyu2port0 PHY_TYPE_USB2>, +- <&tphyu3port0 PHY_TYPE_USB3>; +- clocks = <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>; +- clock-names = "sys_ck", +- "xhci_ck", +- "ref_ck", +- "mcu_ck", +- "dma_ck"; +- #address-cells = <2>; +- #size-cells = <2>; +- status = "okay"; +- }; +- +- usbtphy: usb-phy@11c50000 { +- compatible = "mediatek,mt7988", +- "mediatek,generic-tphy-v2"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- status = "okay"; +- +- tphyu2port0: usb-phy@11c50000 { +- reg = <0 0x11c50000 0 0x700>; +- clocks = <&system_clk>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- +- tphyu3port0: usb-phy@11c50700 { +- reg = <0 0x11c50700 0 0x900>; +- clocks = <&system_clk>; +- clock-names = "ref"; +- #phy-cells = <1>; +- status = "okay"; +- }; +- }; +- +- clk40m: oscillator@0 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <40000000>; +- clock-output-names = "clkxtal"; +- }; +- +- infracfg_ao: infracfg_ao@10001000 { +- compatible = "mediatek,mt7988-infracfg_ao", "syscon"; +- reg = <0 0x10001000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- infracfg: infracfg@10209000 { +- compatible = "mediatek,mt7988-infracfg", "syscon"; +- reg = <0 0x10209000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- topckgen: topckgen@1001B000 { +- compatible = "mediatek,mt7988-topckgen", "syscon"; +- reg = <0 0x1001B000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- apmixedsys: apmixedsys@1001E000 { +- compatible = "mediatek,mt7988-apmixedsys", "syscon"; +- reg = <0 0x1001E000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- mcusys: mcusys@100E0000 { +- compatible = "mediatek,mt7988-mcusys", "syscon"; +- reg = <0 0x100E0000 0 0x1000>; +- #clock-cells = <1>; +- }; +- +- clkitg: clkitg { +- compatible = "simple-bus"; +- }; +- +- efuse: efuse@11f50000 { +- compatible = "mediatek,efuse"; +- reg = <0 0x11f50000 0 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- lvts_calibration: calib@918 { +- reg = <0x918 0x28>; +- }; +- phy_calibration_p0: calib@940 { +- reg = <0x940 0x10>; +- }; +- phy_calibration_p1: calib@954 { +- reg = <0x954 0x10>; +- }; +- phy_calibration_p2: calib@968 { +- reg = <0x968 0x10>; +- }; +- phy_calibration_p3: calib@97c { +- reg = <0x97c 0x10>; +- }; +- cpufreq_calibration: calib@278 { +- reg = <0x278 0x1>; +- }; +- }; +-}; +- +-#include "mt7988-clkitg.dtsi" +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-emmc.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-emmc.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-emmc.dts 2023-02-26 09:01:19.908972500 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-emmc.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,271 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2021 MediaTek Inc. +- * Author: Sam.Shih +- */ +- +-/dts-v1/; +-#include "mt7988.dtsi" +- +-/ { +- model = "MediaTek MT7988A DSA 10G eMMC RFB"; +- compatible = "mediatek,mt7988a-dsa-10g-emmc", +- /* Reserve this for DVFS if creating new dts */ +- "mediatek,mt7988"; +- chosen { +- bootargs = "console=ttyS0,115200n1 loglevel=8 \ +- earlycon=uart8250,mmio32,0x11000000 \ +- root=PARTLABEL=rootfs rootwait \ +- rootfstype=squashfs,f2fs pci=pcie_bus_perf"; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x10000000>; +- }; +- +- wsys_adie: wsys_adie@0 { +- // fpga cases need to manual change adie_id / sku_type for dvt only +- compatible = "mediatek,rebb-mt7988-adie"; +- adie_id = <7976>; +- sku_type = <3000>; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&fan { +- pwms = <&pwm 0 50000 0>; +- status = "okay"; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- /* pin shared with snfi */ +- pinctrl-0 = <&spic_pins>; +- status = "disabled"; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_pins>; +- status = "okay"; +-}; +- +-&pcie2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_pins>; +- status = "disabled"; +-}; +- +-&pcie3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_pins>; +- status = "okay"; +-}; +- +-&pio { +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", +- "pcie_wake_n0_0"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", +- "pcie_wake_n1_0"; +- }; +- }; +- +- pcie2_pins: pcie2-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", +- "pcie_wake_n2_0"; +- }; +- }; +- +- pcie3_pins: pcie3-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", +- "pcie_wake_n3_0"; +- }; +- }; +- +- spic_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1_1"; +- }; +- }; +- +- mmc0_pins_default: mmc0-pins-default { +- mux { +- function = "flash"; +- groups = "emmc_51"; +- }; +- }; +- +- mmc0_pins_uhs: mmc0-pins-uhs { +- mux { +- function = "flash"; +- groups = "emmc_51"; +- }; +- }; +-}; +- +-&watchdog { +- status = "disabled"; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy0>; +- }; +- +- gmac2: mac@2 { +- compatible = "mediatek,eth-mac"; +- reg = <2>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy1>; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@0 { +- reg = <0>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 71 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- +- phy1: ethernet-phy@8 { +- reg = <8>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 72 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- +- switch@0 { +- compatible = "mediatek,mt7988"; +- reg = <31>; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <10000>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&hnat { +- mtketh-wan = "eth1"; +- mtketh-lan = "lan"; +- mtketh-lan2 = "eth2"; +- mtketh-max-gmac = <3>; +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc0_pins_default>; +- pinctrl-1 = <&mmc0_pins_uhs>; +- bus-width = <8>; +- max-frequency = <200000000>; +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- hs400-ds-delay = <0x12814>; +- vqmmc-supply = <®_1p8v>; +- vmmc-supply = <®_3p3v>; +- non-removable; +- no-sd; +- no-sdio; +- status = "okay"; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-sd.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-sd.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-sd.dts 2023-02-26 09:01:19.908972500 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-sd.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,258 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2021 MediaTek Inc. +- * Author: Sam.Shih +- */ +- +-/dts-v1/; +-#include "mt7988.dtsi" +- +-/ { +- model = "MediaTek MT7988A DSA 10G SD RFB"; +- compatible = "mediatek,mt7988a-dsa-10g-sd", +- /* Reserve this for DVFS if creating new dts */ +- "mediatek,mt7988"; +- chosen { +- bootargs = "console=ttyS0,115200n1 loglevel=8 \ +- earlycon=uart8250,mmio32,0x11000000 \ +- root=PARTLABEL=rootfs rootwait \ +- rootfstype=squashfs,f2fs pci=pcie_bus_perf"; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x10000000>; +- }; +- +- wsys_adie: wsys_adie@0 { +- // fpga cases need to manual change adie_id / sku_type for dvt only +- compatible = "mediatek,rebb-mt7988-adie"; +- adie_id = <7976>; +- sku_type = <3000>; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; +-}; +- +-&fan { +- pwms = <&pwm 0 50000 0>; +- status = "okay"; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- /* pin shared with snfi */ +- pinctrl-0 = <&spic_pins>; +- status = "disabled"; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_pins>; +- status = "okay"; +-}; +- +-&pcie2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_pins>; +- status = "disabled"; +-}; +- +-&pcie3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_pins>; +- status = "okay"; +-}; +- +-&pio { +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", +- "pcie_wake_n0_0"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", +- "pcie_wake_n1_0"; +- }; +- }; +- +- pcie2_pins: pcie2-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", +- "pcie_wake_n2_0"; +- }; +- }; +- +- pcie3_pins: pcie3-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", +- "pcie_wake_n3_0"; +- }; +- }; +- +- spic_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1_1"; +- }; +- }; +- +- mmc0_pins_default: mmc0-pins-default { +- mux { +- function = "flash"; +- groups = "emmc_45"; +- }; +- }; +- +- mmc0_pins_uhs: mmc0-pins-uhs { +- mux { +- function = "flash"; +- groups = "emmc_45"; +- }; +- }; +-}; +- +-&watchdog { +- status = "disabled"; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy0>; +- }; +- +- gmac2: mac@2 { +- compatible = "mediatek,eth-mac"; +- reg = <2>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy1>; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@0 { +- reg = <0>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 71 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- +- phy1: ethernet-phy@8 { +- reg = <8>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 72 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- +- switch@0 { +- compatible = "mediatek,mt7988"; +- reg = <31>; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <10000>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&hnat { +- mtketh-wan = "eth1"; +- mtketh-lan = "lan"; +- mtketh-lan2 = "eth2"; +- mtketh-max-gmac = <3>; +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default", "state_uhs"; +- pinctrl-0 = <&mmc0_pins_default>; +- pinctrl-1 = <&mmc0_pins_uhs>; +- bus-width = <4>; +- max-frequency = <52000000>; +- cap-sd-highspeed; +- vmmc-supply = <®_3p3v>; +- vqmmc-supply = <®_3p3v>; +- no-mmc; +- no-sdio; +- status = "okay"; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-snfi-nand.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-snfi-nand.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-snfi-nand.dts 2023-02-26 09:01:19.909973900 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-snfi-nand.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,279 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2021 MediaTek Inc. +- * Author: Sam.Shih +- */ +- +-/dts-v1/; +-#include "mt7988.dtsi" +- +-/ { +- model = "MediaTek MT7988A DSA 10G SNFI-NAND RFB"; +- compatible = "mediatek,mt7988a-dsa-10g-snfi-snand", +- /* Reserve this for DVFS if creating new dts */ +- "mediatek,mt7988"; +- +- chosen { +- bootargs = "console=ttyS0,115200n1 loglevel=8 \ +- earlycon=uart8250,mmio32,0x11000000 \ +- pci=pcie_bus_perf"; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x10000000>; +- }; +- +- nmbm_snfi { +- compatible = "generic,nmbm"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- lower-mtd-device = <&snand>; +- forced-create; +- empty-page-ecc-protected; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "BL2"; +- reg = <0x00000 0x0100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot-env"; +- reg = <0x0100000 0x0080000>; +- }; +- +- factory: partition@180000 { +- label = "Factory"; +- reg = <0x180000 0x0400000>; +- }; +- +- partition@580000 { +- label = "FIP"; +- reg = <0x580000 0x0200000>; +- }; +- +- partition@780000 { +- label = "ubi"; +- reg = <0x780000 0x4000000>; +- }; +- }; +- }; +- +- wsys_adie: wsys_adie@0 { +- // fpga cases need to manual change adie_id / sku_type for dvt only +- compatible = "mediatek,rebb-mt7988-adie"; +- adie_id = <7976>; +- sku_type = <3000>; +- }; +-}; +- +-&fan { +- pwms = <&pwm 0 50000 0>; +- status = "okay"; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- /* pin shared with snfi */ +- pinctrl-0 = <&spic_pins>; +- status = "disabled"; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_pins>; +- status = "okay"; +-}; +- +-&pcie2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_pins>; +- status = "disabled"; +-}; +- +-&pcie3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_pins>; +- status = "okay"; +-}; +- +-&pio { +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", +- "pcie_wake_n0_0"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", +- "pcie_wake_n1_0"; +- }; +- }; +- +- pcie2_pins: pcie2-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", +- "pcie_wake_n2_0"; +- }; +- }; +- +- pcie3_pins: pcie3-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", +- "pcie_wake_n3_0"; +- }; +- }; +- +- snfi_pins: snfi-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- spic_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1_1"; +- }; +- }; +-}; +- +-&watchdog { +- status = "disabled"; +-}; +- +-&snand { +- pinctrl-names = "default"; +- /* pin shared with spic */ +- pinctrl-0 = <&snfi_pins>; +- status = "okay"; +- mediatek,quad-spi; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy0>; +- }; +- +- gmac2: mac@2 { +- compatible = "mediatek,eth-mac"; +- reg = <2>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy1>; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@0 { +- reg = <0>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 71 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- +- phy1: ethernet-phy@8 { +- reg = <8>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 72 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- +- switch@0 { +- compatible = "mediatek,mt7988"; +- reg = <31>; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <10000>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&hnat { +- mtketh-wan = "eth1"; +- mtketh-lan = "lan"; +- mtketh-lan2 = "eth2"; +- mtketh-max-gmac = <3>; +- status = "okay"; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts 2023-02-26 09:01:19.910973200 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,292 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2021 MediaTek Inc. +- * Author: Sam.Shih +- */ +- +-/dts-v1/; +-#include "mt7988.dtsi" +- +-/ { +- model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; +- compatible = "mediatek,mt7988a-dsa-10g-spim-snand", +- /* Reserve this for DVFS if creating new dts */ +- "mediatek,mt7988"; +- +- chosen { +- bootargs = "console=ttyS0,115200n1 loglevel=8 \ +- earlycon=uart8250,mmio32,0x11000000 \ +- pci=pcie_bus_perf"; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x10000000>; +- }; +- +- nmbm_spim_nand { +- compatible = "generic,nmbm"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- lower-mtd-device = <&spi_nand>; +- forced-create; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "BL2"; +- reg = <0x00000 0x0100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot-env"; +- reg = <0x0100000 0x0080000>; +- }; +- +- factory: partition@180000 { +- label = "Factory"; +- reg = <0x180000 0x0400000>; +- }; +- +- partition@580000 { +- label = "FIP"; +- reg = <0x580000 0x0200000>; +- }; +- +- partition@780000 { +- label = "ubi"; +- reg = <0x780000 0x4000000>; +- }; +- }; +- }; +- +- wsys_adie: wsys_adie@0 { +- // fpga cases need to manual change adie_id / sku_type for dvt only +- compatible = "mediatek,rebb-mt7988-adie"; +- adie_id = <7976>; +- sku_type = <3000>; +- }; +-}; +- +-&fan { +- pwms = <&pwm 0 50000 0>; +- status = "okay"; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_flash_pins>; +- status = "okay"; +- +- spi_nand: spi_nand@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- spi-cal-enable; +- spi-cal-mode = "read-data"; +- spi-cal-datalen = <7>; +- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; +- spi-cal-addrlen = <5>; +- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; +- reg = <0>; +- spi-max-frequency = <52000000>; +- spi-tx-buswidth = <4>; +- spi-rx-buswidth = <4>; +- }; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- /* pin shared with snfi */ +- pinctrl-0 = <&spic_pins>; +- status = "disabled"; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_pins>; +- status = "okay"; +-}; +- +-&pcie2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_pins>; +- status = "disabled"; +-}; +- +-&pcie3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_pins>; +- status = "okay"; +-}; +- +-&pio { +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", +- "pcie_wake_n0_0"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", +- "pcie_wake_n1_0"; +- }; +- }; +- +- pcie2_pins: pcie2-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", +- "pcie_wake_n2_0"; +- }; +- }; +- +- pcie3_pins: pcie3-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", +- "pcie_wake_n3_0"; +- }; +- }; +- +- spi0_flash_pins: spi0-pins { +- mux { +- function = "spi"; +- groups = "spi0", "spi0_wp_hold"; +- }; +- }; +- +- spic_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1_1"; +- }; +- }; +-}; +- +-&watchdog { +- status = "disabled"; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy0>; +- }; +- +- gmac2: mac@2 { +- compatible = "mediatek,eth-mac"; +- reg = <2>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy1>; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@0 { +- reg = <0>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 71 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- +- phy1: ethernet-phy@8 { +- reg = <8>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 72 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- +- switch@0 { +- compatible = "mediatek,mt7988"; +- reg = <31>; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <10000>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&hnat { +- mtketh-wan = "eth1"; +- mtketh-lan = "lan"; +- mtketh-lan2 = "eth2"; +- mtketh-max-gmac = <3>; +- status = "okay"; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts 2023-02-26 09:01:19.910973200 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,276 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2021 MediaTek Inc. +- * Author: Sam.Shih +- */ +- +-/dts-v1/; +-#include "mt7988.dtsi" +- +-/ { +- model = "MediaTek MT7988A DSA 10G SPIM-NOR RFB"; +- compatible = "mediatek,mt7988a-dsa-10g-spim-nor", +- /* Reserve this for DVFS if creating new dts */ +- "mediatek,mt7988"; +- +- chosen { +- bootargs = "console=ttyS0,115200n1 loglevel=8 \ +- earlycon=uart8250,mmio32,0x11000000 \ +- pci=pcie_bus_perf"; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x10000000>; +- }; +- +- wsys_adie: wsys_adie@0 { +- // fpga cases need to manual change adie_id / sku_type for dvt only +- compatible = "mediatek,rebb-mt7988-adie"; +- adie_id = <7976>; +- sku_type = <3000>; +- }; +-}; +- +-&fan { +- pwms = <&pwm 0 50000 0>; +- status = "okay"; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- /* pin shared with snfi */ +- pinctrl-0 = <&spic_pins>; +- status = "disabled"; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_flash_pins>; +- status = "okay"; +- spi_nor@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- spi-cal-enable; +- spi-cal-mode = "read-data"; +- spi-cal-datalen = <7>; +- spi-cal-data = /bits/ 8 < +- 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ +- spi-cal-addrlen = <1>; +- spi-cal-addr = /bits/ 32 <0x0>; +- reg = <0>; +- spi-max-frequency = <52000000>; +- +- partition@00000 { +- label = "BL2"; +- reg = <0x00000 0x0040000>; +- }; +- partition@40000 { +- label = "u-boot-env"; +- reg = <0x40000 0x0010000>; +- }; +- factory: partition@50000 { +- label = "Factory"; +- reg = <0x50000 0x00B0000>; +- }; +- partition@100000 { +- label = "FIP"; +- reg = <0x100000 0x0080000>; +- }; +- partition@180000 { +- label = "firmware"; +- reg = <0x180000 0xE00000>; +- }; +- }; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_pins>; +- status = "okay"; +-}; +- +-&pcie2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_pins>; +- status = "disabled"; +-}; +- +-&pcie3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_pins>; +- status = "okay"; +-}; +- +-&pio { +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", +- "pcie_wake_n0_0"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", +- "pcie_wake_n1_0"; +- }; +- }; +- +- pcie2_pins: pcie2-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", +- "pcie_wake_n2_0"; +- }; +- }; +- +- pcie3_pins: pcie3-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", +- "pcie_wake_n3_0"; +- }; +- }; +- +- spic_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1_1"; +- }; +- }; +- +- spi2_flash_pins: spi2-pins { +- mux { +- function = "spi"; +- groups = "spi2", "spi2_wp_hold"; +- }; +- }; +-}; +- +-&watchdog { +- status = "disabled"; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy0>; +- }; +- +- gmac2: mac@2 { +- compatible = "mediatek,eth-mac"; +- reg = <2>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy1>; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@0 { +- reg = <0>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 71 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- +- phy1: ethernet-phy@8 { +- reg = <8>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 72 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- +- switch@0 { +- compatible = "mediatek,mt7988"; +- reg = <31>; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <10000>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&hnat { +- mtketh-wan = "eth1"; +- mtketh-lan = "lan"; +- mtketh-lan2 = "eth2"; +- mtketh-max-gmac = <3>; +- status = "okay"; +-}; +- +-&wed { +- dy_txbm_enable = "true"; +- dy_txbm_budge = <8>; +- txbm_init_sz = <10>; +- status = "okay"; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-e2p5g-spim-nand.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-e2p5g-spim-nand.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-e2p5g-spim-nand.dts 2023-02-26 09:01:19.910973200 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-e2p5g-spim-nand.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,365 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2021 MediaTek Inc. +- * Author: Sam.Shih +- */ +- +-/dts-v1/; +-#include "mt7988.dtsi" +- +-/ { +- model = "MediaTek MT7988 DSA external-2.5G SPIM-NAND RFB"; +- compatible = "mediatek,mt7988a-dsa-e2p5g-spim-snand", +- /* Reserve this for DVFS if creating new dts */ +- "mediatek,mt7988"; +- +- chosen { +- bootargs = "console=ttyS0,115200n1 loglevel=8 \ +- earlycon=uart8250,mmio32,0x11000000 \ +- pci=pcie_bus_perf"; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x10000000>; +- }; +- +- nmbm_spim_nand { +- compatible = "generic,nmbm"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- lower-mtd-device = <&spi_nand>; +- forced-create; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "BL2"; +- reg = <0x00000 0x0100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot-env"; +- reg = <0x0100000 0x0080000>; +- }; +- +- factory: partition@180000 { +- label = "Factory"; +- reg = <0x180000 0x0400000>; +- }; +- +- partition@580000 { +- label = "FIP"; +- reg = <0x580000 0x0200000>; +- }; +- +- partition@780000 { +- label = "ubi"; +- reg = <0x780000 0x4000000>; +- }; +- }; +- }; +- +- wsys_adie: wsys_adie@0 { +- // fpga cases need to manual change adie_id / sku_type for dvt only +- compatible = "mediatek,rebb-mt7988-adie"; +- adie_id = <7976>; +- sku_type = <3000>; +- }; +-}; +- +-&fan { +- pwms = <&pwm 0 50000 0>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- rt5190a_64: rt5190a@64 { +- compatible = "richtek,rt5190a"; +- reg = <0x64>; +- /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ +- vin2-supply = <&rt5190_buck1>; +- vin3-supply = <&rt5190_buck1>; +- vin4-supply = <&rt5190_buck1>; +- +- regulators { +- rt5190_buck1: buck1 { +- regulator-name = "rt5190a-buck1"; +- regulator-min-microvolt = <5090000>; +- regulator-max-microvolt = <5090000>; +- regulator-allowed-modes = +- ; +- regulator-boot-on; +- }; +- buck2 { +- regulator-name = "vcore"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- }; +- buck3 { +- regulator-name = "proc"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- }; +- buck4 { +- regulator-name = "rt5190a-buck4"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-allowed-modes = +- ; +- regulator-boot-on; +- }; +- ldo { +- regulator-name = "rt5190a-ldo"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_flash_pins>; +- status = "okay"; +- +- spi_nand: spi_nand@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- spi-cal-enable; +- spi-cal-mode = "read-data"; +- spi-cal-datalen = <7>; +- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; +- spi-cal-addrlen = <5>; +- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; +- reg = <0>; +- spi-max-frequency = <52000000>; +- spi-tx-buswidth = <4>; +- spi-rx-buswidth = <4>; +- }; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- /* pin shared with snfi */ +- pinctrl-0 = <&spic_pins>; +- status = "disabled"; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_pins>; +- status = "okay"; +-}; +- +-&pcie2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_pins>; +- status = "disabled"; +-}; +- +-&pcie3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_pins>; +- status = "okay"; +-}; +- +-&pio { +- i2c0_pins: i2c0-pins-g0 { +- mux { +- function = "i2c"; +- groups = "i2c0_1"; +- }; +- }; +- +- i2c1_pins: i2c1-pins-g0 { +- mux { +- function = "i2c"; +- groups = "i2c1_0"; +- }; +- }; +- +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", +- "pcie_wake_n0_0"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", +- "pcie_wake_n1_0"; +- }; +- }; +- +- pcie2_pins: pcie2-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", +- "pcie_wake_n2_0"; +- }; +- }; +- +- pcie3_pins: pcie3-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", +- "pcie_wake_n3_0"; +- }; +- }; +- +- spi0_flash_pins: spi0-pins { +- mux { +- function = "spi"; +- groups = "spi0", "spi0_wp_hold"; +- }; +- }; +- +- spic_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1_1"; +- }; +- }; +-}; +- +-&watchdog { +- status = "disabled"; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "2500base-x"; +- phy-handle = <&phy13>; +- }; +- +- gmac2: mac@2 { +- compatible = "mediatek,eth-mac"; +- reg = <2>; +- phy-mode = "2500base-x"; +- phy-handle = <&phy5>; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- phy5: phy@5 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <5>; +- reset-gpios = <&pio 0 1>; +- reset-assert-us = <600>; +- reset-deassert-us = <20000>; +- }; +- +- phy13: phy@13 { +- compatible = "ethernet-phy-ieee802.3-c45"; +- reg = <13>; +- reset-gpios = <&pio 1 1>; +- reset-assert-us = <600>; +- reset-deassert-us = <20000>; +- }; +- +- switch@0 { +- compatible = "mediatek,mt7988"; +- reg = <31>; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <10000>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&hnat { +- mtketh-wan = "eth1"; +- mtketh-lan = "lan"; +- mtketh-lan2 = "eth2"; +- mtketh-max-gmac = <3>; +- status = "okay"; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts 2023-02-26 09:01:19.911972900 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,282 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2021 MediaTek Inc. +- * Author: Sam.Shih +- */ +- +-/dts-v1/; +-#include "mt7988.dtsi" +- +-/ { +- model = "MediaTek MT7988 DSA internal-2.5G SPIM-NAND RFB"; +- compatible = "mediatek,mt7988a-dsa-i2p5g-spim-snand", +- /* Reserve this for DVFS if creating new dts */ +- "mediatek,mt7988"; +- +- chosen { +- bootargs = "console=ttyS0,115200n1 loglevel=8 \ +- earlycon=uart8250,mmio32,0x11000000 \ +- pci=pcie_bus_perf"; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x10000000>; +- }; +- +- nmbm_spim_nand { +- compatible = "generic,nmbm"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- lower-mtd-device = <&spi_nand>; +- forced-create; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "BL2"; +- reg = <0x00000 0x0100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot-env"; +- reg = <0x0100000 0x0080000>; +- }; +- +- factory: partition@180000 { +- label = "Factory"; +- reg = <0x180000 0x0400000>; +- }; +- +- partition@580000 { +- label = "FIP"; +- reg = <0x580000 0x0200000>; +- }; +- +- partition@780000 { +- label = "ubi"; +- reg = <0x780000 0x4000000>; +- }; +- }; +- }; +- +- wsys_adie: wsys_adie@0 { +- // fpga cases need to manual change adie_id / sku_type for dvt only +- compatible = "mediatek,rebb-mt7988-adie"; +- adie_id = <7976>; +- sku_type = <3000>; +- }; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_flash_pins>; +- status = "okay"; +- +- spi_nand: spi_nand@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- spi-cal-enable; +- spi-cal-mode = "read-data"; +- spi-cal-datalen = <7>; +- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; +- spi-cal-addrlen = <5>; +- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; +- reg = <0>; +- spi-max-frequency = <52000000>; +- spi-tx-buswidth = <4>; +- spi-rx-buswidth = <4>; +- }; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- /* pin shared with snfi */ +- pinctrl-0 = <&spic_pins>; +- status = "disabled"; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_pins>; +- status = "okay"; +-}; +- +-&pcie2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_pins>; +- status = "disabled"; +-}; +- +-&pcie3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_pins>; +- status = "okay"; +-}; +- +-&pio { +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", +- "pcie_wake_n0_0"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", +- "pcie_wake_n1_0"; +- }; +- }; +- +- pcie2_pins: pcie2-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", +- "pcie_wake_n2_0"; +- }; +- }; +- +- pcie3_pins: pcie3-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", +- "pcie_wake_n3_0"; +- }; +- }; +- +- spi0_flash_pins: spi0-pins { +- mux { +- function = "spi"; +- groups = "spi0", "spi0_wp_hold"; +- }; +- }; +- +- spic_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1_1"; +- }; +- }; +-}; +- +-&watchdog { +- status = "disabled"; +-}; +- +-&usxgmiisys1 { +- internal_2500; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy0>; +- }; +- +- gmac2: mac@2 { +- compatible = "mediatek,eth-mac"; +- reg = <2>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy1>; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@0 { +- reg = <15>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- phy-mode = "10gbase-kr"; +- }; +- +- phy1: ethernet-phy@8 { +- reg = <8>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- }; +- +- switch@0 { +- compatible = "mediatek,mt7988"; +- reg = <31>; +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- label = "lan0"; +- }; +- +- port@1 { +- reg = <1>; +- label = "lan1"; +- }; +- +- port@2 { +- reg = <2>; +- label = "lan2"; +- }; +- +- port@3 { +- reg = <3>; +- label = "lan3"; +- }; +- +- port@6 { +- reg = <6>; +- label = "cpu"; +- ethernet = <&gmac0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <10000>; +- full-duplex; +- pause; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&hnat { +- mtketh-wan = "eth1"; +- mtketh-lan = "lan"; +- mtketh-lan2 = "eth2"; +- mtketh-max-gmac = <3>; +- status = "okay"; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-sfp-spim-nand.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-sfp-spim-nand.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-sfp-spim-nand.dts 2023-02-26 09:01:19.911972900 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-sfp-spim-nand.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,405 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2021 MediaTek Inc. +- * Author: Sam.Shih +- */ +- +-/dts-v1/; +-#include "mt7988.dtsi" +- +-/ { +- model = "MediaTek MT7988 GSW 10G SFP SPIM-NAND RFB"; +- compatible = "mediatek,mt7988a-gsw-10g-sfp-spim-snand", +- /* Reserve this for DVFS if creating new dts */ +- "mediatek,mt7988"; +- +- chosen { +- bootargs = "console=ttyS0,115200n1 loglevel=8 \ +- earlycon=uart8250,mmio32,0x11000000"; +- }; +- +- gsw: gsw@0 { +- compatible = "mediatek,mt753x"; +- mediatek,sysctrl = <ðwarp>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x10000000>; +- }; +- +- nmbm_spim_nand { +- compatible = "generic,nmbm"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- lower-mtd-device = <&spi_nand>; +- forced-create; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "BL2"; +- reg = <0x00000 0x0100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot-env"; +- reg = <0x0100000 0x0080000>; +- }; +- +- factory: partition@180000 { +- label = "Factory"; +- reg = <0x180000 0x0400000>; +- }; +- +- partition@580000 { +- label = "FIP"; +- reg = <0x580000 0x0200000>; +- }; +- +- partition@780000 { +- label = "ubi"; +- reg = <0x780000 0x4000000>; +- }; +- }; +- }; +- +- wsys_adie: wsys_adie@0 { +- // fpga cases need to manual change adie_id / sku_type for dvt only +- compatible = "mediatek,rebb-mt7988-adie"; +- adie_id = <7976>; +- sku_type = <3000>; +- }; +- +- sfp_esp0: sfp@0 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c2>; +- tx-disable-gpios = <&pio 29 0>; +- }; +- +- sfp_esp1: sfp@1 { +- compatible = "sff,sfp"; +- i2c-bus = <&i2c1>; +- tx-disable-gpios = <&pio 36 0>; +- }; +-}; +- +-&fan { +- pwms = <&pwm 0 50000 0>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- rt5190a_64: rt5190a@64 { +- compatible = "richtek,rt5190a"; +- reg = <0x64>; +- /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ +- vin2-supply = <&rt5190_buck1>; +- vin3-supply = <&rt5190_buck1>; +- vin4-supply = <&rt5190_buck1>; +- +- regulators { +- rt5190_buck1: buck1 { +- regulator-name = "rt5190a-buck1"; +- regulator-min-microvolt = <5090000>; +- regulator-max-microvolt = <5090000>; +- regulator-allowed-modes = +- ; +- regulator-boot-on; +- }; +- buck2 { +- regulator-name = "vcore"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- }; +- buck3 { +- regulator-name = "proc"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- }; +- buck4 { +- regulator-name = "rt5190a-buck4"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-allowed-modes = +- ; +- regulator-boot-on; +- }; +- ldo { +- regulator-name = "rt5190a-ldo"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_flash_pins>; +- status = "okay"; +- +- spi_nand: spi_nand@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- spi-cal-enable; +- spi-cal-mode = "read-data"; +- spi-cal-datalen = <7>; +- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; +- spi-cal-addrlen = <5>; +- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; +- reg = <0>; +- spi-max-frequency = <52000000>; +- spi-tx-buswidth = <4>; +- spi-rx-buswidth = <4>; +- }; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- /* pin shared with snfi */ +- pinctrl-0 = <&spic_pins>; +- status = "disabled"; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_pins>; +- status = "okay"; +-}; +- +-&pcie2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_pins>; +- status = "disabled"; +-}; +- +-&pcie3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_pins>; +- status = "okay"; +-}; +- +-&pio { +- i2c0_pins: i2c0-pins-g0 { +- mux { +- function = "i2c"; +- groups = "i2c0_1"; +- }; +- }; +- +- i2c1_pins: i2c1-pins-g0 { +- mux { +- function = "i2c"; +- groups = "i2c1_sfp"; +- }; +- }; +- +- i2c2_pins: i2c2-pins-g0 { +- mux { +- function = "i2c"; +- groups = "i2c2_0"; +- }; +- }; +- +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", +- "pcie_wake_n0_0"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", +- "pcie_wake_n1_0"; +- }; +- }; +- +- pcie2_pins: pcie2-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", +- "pcie_wake_n2_0"; +- }; +- }; +- +- pcie3_pins: pcie3-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", +- "pcie_wake_n3_0"; +- }; +- }; +- +- spi0_flash_pins: spi0-pins { +- mux { +- function = "spi"; +- groups = "spi0", "spi0_wp_hold"; +- }; +- }; +- +- spic_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1_1"; +- }; +- }; +-}; +- +-&watchdog { +- status = "disabled"; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "10gbase-kr"; +- managed = "in-band-status"; +- sfp = <&sfp_esp1>; +- }; +- +- gmac2: mac@2 { +- compatible = "mediatek,eth-mac"; +- reg = <2>; +- phy-mode = "10gbase-kr"; +- managed = "in-band-status"; +- sfp = <&sfp_esp0>; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- }; +-}; +- +-&hnat { +- mtketh-wan = "eth1"; +- mtketh-lan = "eth0"; +- mtketh-lan2 = "eth2"; +- mtketh-max-gmac = <3>; +- status = "okay"; +-}; +- +-&gsw { +- mediatek,mdio = <&mdio>; +- mediatek,portmap = "llllw"; +- mediatek,mdio_master_pinmux = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- status = "okay"; +- +- port6: port@6 { +- compatible = "mediatek,mt753x-port"; +- mediatek,ssc-on; +- phy-mode = "10gbase-kr"; +- reg = <6>; +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +- +- mdio1: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- gsw_phy0: ethernet-phy@0 { +- compatible = "ethernet-phy-id03a2.9481"; +- reg = <0>; +- phy-mode = "gmii"; +- rext = "efuse"; +- tx_r50 = "efuse"; +- nvmem-cells = <&phy_calibration_p0>; +- nvmem-cell-names = "phy-cal-data"; +- }; +- +- gsw_phy1: ethernet-phy@1 { +- compatible = "ethernet-phy-id03a2.9481"; +- reg = <1>; +- phy-mode = "gmii"; +- rext = "efuse"; +- tx_r50 = "efuse"; +- nvmem-cells = <&phy_calibration_p1>; +- nvmem-cell-names = "phy-cal-data"; +- }; +- +- gsw_phy2: ethernet-phy@2 { +- compatible = "ethernet-phy-id03a2.9481"; +- reg = <2>; +- phy-mode = "gmii"; +- rext = "efuse"; +- tx_r50 = "efuse"; +- nvmem-cells = <&phy_calibration_p2>; +- nvmem-cell-names = "phy-cal-data"; +- }; +- +- gsw_phy3: ethernet-phy@3 { +- compatible = "ethernet-phy-id03a2.9481"; +- reg = <3>; +- phy-mode = "gmii"; +- rext = "efuse"; +- tx_r50 = "efuse"; +- nvmem-cells = <&phy_calibration_p3>; +- nvmem-cell-names = "phy-cal-data"; +- }; +- }; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand.dts 2023-02-26 09:01:19.913974400 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,395 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2021 MediaTek Inc. +- * Author: Sam.Shih +- */ +- +-/dts-v1/; +- +-#include "mt7988.dtsi" +- +-/ { +- model = "MediaTek MT7988 GSW 10G SPIM-NAND RFB"; +- compatible = "mediatek,mt7988a-gsw-10g-spim-snand", +- /* Reserve this for DVFS if creating new dts */ +- "mediatek,mt7988"; +- +- chosen { +- bootargs = "console=ttyS0,115200n1 loglevel=8 \ +- earlycon=uart8250,mmio32,0x11000000 \ +- pci=pcie_bus_perf"; +- }; +- +- gsw: gsw@0 { +- compatible = "mediatek,mt753x"; +- mediatek,sysctrl = <ðwarp>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x10000000>; +- }; +- +- nmbm_spim_nand { +- compatible = "generic,nmbm"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- lower-mtd-device = <&spi_nand>; +- forced-create; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "BL2"; +- reg = <0x00000 0x0100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot-env"; +- reg = <0x0100000 0x0080000>; +- }; +- +- factory: partition@180000 { +- label = "Factory"; +- reg = <0x180000 0x0400000>; +- }; +- +- partition@580000 { +- label = "FIP"; +- reg = <0x580000 0x0200000>; +- }; +- +- partition@780000 { +- label = "ubi"; +- reg = <0x780000 0x4000000>; +- }; +- }; +- }; +- +- wsys_adie: wsys_adie@0 { +- // fpga cases need to manual change adie_id / sku_type for dvt only +- compatible = "mediatek,rebb-mt7988-adie"; +- adie_id = <7976>; +- sku_type = <3000>; +- }; +-}; +- +-&fan { +- pwms = <&pwm 0 50000 0>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- rt5190a_64: rt5190a@64 { +- compatible = "richtek,rt5190a"; +- reg = <0x64>; +- /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ +- vin2-supply = <&rt5190_buck1>; +- vin3-supply = <&rt5190_buck1>; +- vin4-supply = <&rt5190_buck1>; +- +- regulators { +- rt5190_buck1: buck1 { +- regulator-name = "rt5190a-buck1"; +- regulator-min-microvolt = <5090000>; +- regulator-max-microvolt = <5090000>; +- regulator-allowed-modes = +- ; +- regulator-boot-on; +- }; +- buck2 { +- regulator-name = "vcore"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- }; +- buck3 { +- regulator-name = "proc"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- }; +- buck4 { +- regulator-name = "rt5190a-buck4"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-allowed-modes = +- ; +- regulator-boot-on; +- }; +- ldo { +- regulator-name = "rt5190a-ldo"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_flash_pins>; +- status = "okay"; +- +- spi_nand: spi_nand@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- spi-cal-enable; +- spi-cal-mode = "read-data"; +- spi-cal-datalen = <7>; +- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; +- spi-cal-addrlen = <5>; +- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; +- reg = <0>; +- spi-max-frequency = <52000000>; +- spi-tx-buswidth = <4>; +- spi-rx-buswidth = <4>; +- }; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- /* pin shared with snfi */ +- pinctrl-0 = <&spic_pins>; +- status = "disabled"; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_pins>; +- status = "okay"; +-}; +- +-&pcie2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_pins>; +- status = "disabled"; +-}; +- +-&pcie3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_pins>; +- status = "okay"; +-}; +- +-&pio { +- i2c0_pins: i2c0-pins-g0 { +- mux { +- function = "i2c"; +- groups = "i2c0_1"; +- }; +- }; +- +- i2c1_pins: i2c1-pins-g0 { +- mux { +- function = "i2c"; +- groups = "i2c1_0"; +- }; +- }; +- +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", +- "pcie_wake_n0_0"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", +- "pcie_wake_n1_0"; +- }; +- }; +- +- pcie2_pins: pcie2-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", +- "pcie_wake_n2_0"; +- }; +- }; +- +- pcie3_pins: pcie3-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", +- "pcie_wake_n3_0"; +- }; +- }; +- +- spi0_flash_pins: spi0-pins { +- mux { +- function = "spi"; +- groups = "spi0", "spi0_wp_hold"; +- }; +- }; +- +- spic_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1_1"; +- }; +- }; +-}; +- +-&watchdog { +- status = "disabled"; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy0>; +- }; +- +- gmac2: mac@2 { +- compatible = "mediatek,eth-mac"; +- reg = <2>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy1>; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@0 { +- reg = <0>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 71 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- +- phy1: ethernet-phy@8 { +- reg = <8>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 72 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- }; +-}; +- +-&hnat { +- mtketh-wan = "eth1"; +- mtketh-lan = "eth0"; +- mtketh-lan2 = "eth2"; +- mtketh-max-gmac = <3>; +- status = "okay"; +-}; +- +-&gsw { +- mediatek,mdio = <&mdio>; +- mediatek,portmap = "llllw"; +- mediatek,mdio_master_pinmux = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- status = "okay"; +- +- port6: port@6 { +- compatible = "mediatek,mt753x-port"; +- mediatek,ssc-on; +- phy-mode = "10gbase-kr"; +- reg = <6>; +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +- +- mdio1: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- gsw_phy0: ethernet-phy@0 { +- compatible = "ethernet-phy-id03a2.9481"; +- reg = <0>; +- phy-mode = "gmii"; +- rext = "efuse"; +- tx_r50 = "efuse"; +- nvmem-cells = <&phy_calibration_p0>; +- nvmem-cell-names = "phy-cal-data"; +- }; +- +- gsw_phy1: ethernet-phy@1 { +- compatible = "ethernet-phy-id03a2.9481"; +- reg = <1>; +- phy-mode = "gmii"; +- rext = "efuse"; +- tx_r50 = "efuse"; +- nvmem-cells = <&phy_calibration_p1>; +- nvmem-cell-names = "phy-cal-data"; +- }; +- +- gsw_phy2: ethernet-phy@2 { +- compatible = "ethernet-phy-id03a2.9481"; +- reg = <2>; +- phy-mode = "gmii"; +- rext = "efuse"; +- tx_r50 = "efuse"; +- nvmem-cells = <&phy_calibration_p2>; +- nvmem-cell-names = "phy-cal-data"; +- }; +- +- gsw_phy3: ethernet-phy@3 { +- compatible = "ethernet-phy-id03a2.9481"; +- reg = <3>; +- phy-mode = "gmii"; +- rext = "efuse"; +- tx_r50 = "efuse"; +- nvmem-cells = <&phy_calibration_p3>; +- nvmem-cell-names = "phy-cal-data"; +- }; +- }; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand-4pcie.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand-4pcie.dts +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand-4pcie.dts 2023-02-26 09:01:19.912971600 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand-4pcie.dts 1970-01-01 08:00:00.000000000 +0800 +@@ -1,398 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* +- * Copyright (C) 2021 MediaTek Inc. +- * Author: Sam.Shih +- */ +- +-/dts-v1/; +-#include "mt7988.dtsi" +- +-/ { +- model = "MediaTek MT7988 GSW 10G SPIM-NAND 4PCIe RFB"; +- compatible = "mediatek,mt7988a-gsw-10g-spim-snand-4pcie", +- /* Reserve this for DVFS if creating new dts */ +- "mediatek,mt7988"; +- +- chosen { +- bootargs = "console=ttyS0,115200n1 loglevel=8 \ +- earlycon=uart8250,mmio32,0x11000000 \ +- pci=pcie_bus_perf"; +- }; +- +- gsw: gsw@0 { +- compatible = "mediatek,mt753x"; +- mediatek,sysctrl = <ðwarp>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- memory { +- reg = <0 0x40000000 0 0x10000000>; +- }; +- +- nmbm_spim_nand { +- compatible = "generic,nmbm"; +- +- #address-cells = <1>; +- #size-cells = <1>; +- +- lower-mtd-device = <&spi_nand>; +- forced-create; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "BL2"; +- reg = <0x00000 0x0100000>; +- read-only; +- }; +- +- partition@100000 { +- label = "u-boot-env"; +- reg = <0x0100000 0x0080000>; +- }; +- +- factory: partition@180000 { +- label = "Factory"; +- reg = <0x180000 0x0400000>; +- }; +- +- partition@580000 { +- label = "FIP"; +- reg = <0x580000 0x0200000>; +- }; +- +- partition@780000 { +- label = "ubi"; +- reg = <0x780000 0x4000000>; +- }; +- }; +- }; +- +- wsys_adie: wsys_adie@0 { +- // fpga cases need to manual change adie_id / sku_type for dvt only +- compatible = "mediatek,rebb-mt7988-adie"; +- adie_id = <7976>; +- sku_type = <3000>; +- }; +-}; +- +-&fan { +- pwms = <&pwm 0 50000 0>; +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- rt5190a_64: rt5190a@64 { +- compatible = "richtek,rt5190a"; +- reg = <0x64>; +- /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ +- vin2-supply = <&rt5190_buck1>; +- vin3-supply = <&rt5190_buck1>; +- vin4-supply = <&rt5190_buck1>; +- +- regulators { +- rt5190_buck1: buck1 { +- regulator-name = "rt5190a-buck1"; +- regulator-min-microvolt = <5090000>; +- regulator-max-microvolt = <5090000>; +- regulator-allowed-modes = +- ; +- regulator-boot-on; +- }; +- buck2 { +- regulator-name = "vcore"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- }; +- buck3 { +- regulator-name = "proc"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- }; +- buck4 { +- regulator-name = "rt5190a-buck4"; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-allowed-modes = +- ; +- regulator-boot-on; +- }; +- ldo { +- regulator-name = "rt5190a-ldo"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-boot-on; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&spi0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi0_flash_pins>; +- status = "okay"; +- +- spi_nand: spi_nand@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "spi-nand"; +- spi-cal-enable; +- spi-cal-mode = "read-data"; +- spi-cal-datalen = <7>; +- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; +- spi-cal-addrlen = <5>; +- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; +- reg = <0>; +- spi-max-frequency = <52000000>; +- spi-tx-buswidth = <4>; +- spi-rx-buswidth = <4>; +- }; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- /* pin shared with snfi */ +- pinctrl-0 = <&spic_pins>; +- status = "disabled"; +-}; +- +-&pcie0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; +- status = "okay"; +-}; +- +-&pcie1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie1_pins>; +- status = "okay"; +-}; +- +-&pcie2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_pins>; +- status = "okay"; +-}; +- +-&pcie3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_pins>; +- status = "okay"; +-}; +- +-&pio { +- i2c0_pins: i2c0-pins-g0 { +- mux { +- function = "i2c"; +- groups = "i2c0_1"; +- }; +- }; +- +- i2c1_pins: i2c1-pins-g0 { +- mux { +- function = "i2c"; +- groups = "i2c1_0"; +- }; +- }; +- +- pcie0_pins: pcie0-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", +- "pcie_wake_n0_0"; +- }; +- }; +- +- pcie1_pins: pcie1-pins { +- mux { +- function = "pcie"; +- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", +- "pcie_wake_n1_0"; +- }; +- }; +- +- pcie2_pins: pcie2-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", +- "pcie_wake_n2_0"; +- }; +- }; +- +- pcie3_pins: pcie3-pins { +- mux { +- function = "pcie"; +- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", +- "pcie_wake_n3_0"; +- }; +- }; +- +- spi0_flash_pins: spi0-pins { +- mux { +- function = "spi"; +- groups = "spi0", "spi0_wp_hold"; +- }; +- }; +- +- spic_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1_1"; +- }; +- }; +-}; +- +-&watchdog { +- status = "disabled"; +-}; +- +-&xhci0 { +- status = "disabled"; +-}; +- +-ð { +- status = "okay"; +- +- gmac0: mac@0 { +- compatible = "mediatek,eth-mac"; +- reg = <0>; +- phy-mode = "10gbase-kr"; +- +- fixed-link { +- speed = <2500>; +- full-duplex; +- pause; +- }; +- }; +- +- gmac1: mac@1 { +- compatible = "mediatek,eth-mac"; +- reg = <1>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy0>; +- }; +- +- gmac2: mac@2 { +- compatible = "mediatek,eth-mac"; +- reg = <2>; +- phy-mode = "10gbase-kr"; +- phy-handle = <&phy1>; +- }; +- +- mdio: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- phy0: ethernet-phy@0 { +- reg = <0>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 71 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- +- phy1: ethernet-phy@8 { +- reg = <8>; +- compatible = "ethernet-phy-ieee802.3-c45"; +- reset-gpios = <&pio 72 1>; +- reset-assert-us = <1000000>; +- reset-deassert-us = <1000000>; +- }; +- }; +-}; +- +-&hnat { +- mtketh-wan = "eth1"; +- mtketh-lan = "eth0"; +- mtketh-lan2 = "eth2"; +- mtketh-max-gmac = <3>; +- status = "okay"; +-}; +- +-&gsw { +- mediatek,mdio = <&mdio>; +- mediatek,portmap = "llllw"; +- mediatek,mdio_master_pinmux = <1>; +- interrupt-parent = <&gic>; +- interrupts = ; +- status = "okay"; +- +- port6: port@6 { +- compatible = "mediatek,mt753x-port"; +- mediatek,ssc-on; +- phy-mode = "10gbase-kr"; +- reg = <6>; +- fixed-link { +- speed = <2500>; +- full-duplex; +- }; +- }; +- +- mdio1: mdio-bus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- gsw_phy0: ethernet-phy@0 { +- compatible = "ethernet-phy-id03a2.9481"; +- reg = <0>; +- phy-mode = "gmii"; +- rext = "efuse"; +- tx_r50 = "efuse"; +- nvmem-cells = <&phy_calibration_p0>; +- nvmem-cell-names = "phy-cal-data"; +- }; +- +- gsw_phy1: ethernet-phy@1 { +- compatible = "ethernet-phy-id03a2.9481"; +- reg = <1>; +- phy-mode = "gmii"; +- rext = "efuse"; +- tx_r50 = "efuse"; +- nvmem-cells = <&phy_calibration_p1>; +- nvmem-cell-names = "phy-cal-data"; +- }; +- +- gsw_phy2: ethernet-phy@2 { +- compatible = "ethernet-phy-id03a2.9481"; +- reg = <2>; +- phy-mode = "gmii"; +- rext = "efuse"; +- tx_r50 = "efuse"; +- nvmem-cells = <&phy_calibration_p2>; +- nvmem-cell-names = "phy-cal-data"; +- }; +- +- gsw_phy3: ethernet-phy@3 { +- compatible = "ethernet-phy-id03a2.9481"; +- reg = <3>; +- phy-mode = "gmii"; +- rext = "efuse"; +- tx_r50 = "efuse"; +- nvmem-cells = <&phy_calibration_p3>; +- nvmem-cell-names = "phy-cal-data"; +- }; +- }; +-}; +diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi +--- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi 2023-02-26 09:01:19.906972700 +0800 ++++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi 1970-01-01 08:00:00.000000000 +0800 +@@ -1,386 +0,0 @@ +-/* +- * Copyright (c) 2022 MediaTek Inc. +- * Author: Author: Xiufeng Li +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-&clkitg { +- bring-up { +- compatible = "mediatek,clk-bring-up"; +- clocks = +- <&apmixedsys CK_APMIXED_NETSYSPLL>, +- <&apmixedsys CK_APMIXED_MPLL>, +- <&apmixedsys CK_APMIXED_MMPLL>, +- <&apmixedsys CK_APMIXED_APLL2>, +- <&apmixedsys CK_APMIXED_NET1PLL>, +- <&apmixedsys CK_APMIXED_NET2PLL>, +- <&apmixedsys CK_APMIXED_WEDMCUPLL>, +- <&apmixedsys CK_APMIXED_SGMPLL>, +- <&apmixedsys CK_APMIXED_ARM_B>, +- <&apmixedsys CK_APMIXED_CCIPLL2_B>, +- <&apmixedsys CK_APMIXED_USXGMIIPLL>, +- <&apmixedsys CK_APMIXED_MSDCPLL>, +- <&topckgen CK_TOP_CB_CKSQ_40M>, +- <&topckgen CK_TOP_CB_M_416M>, +- <&topckgen CK_TOP_CB_M_D2>, +- <&topckgen CK_TOP_M_D3_D2>, +- <&topckgen CK_TOP_CB_M_D4>, +- <&topckgen CK_TOP_CB_M_D8>, +- <&topckgen CK_TOP_M_D8_D2>, +- <&topckgen CK_TOP_CB_MM_720M>, +- <&topckgen CK_TOP_CB_MM_D2>, +- <&topckgen CK_TOP_CB_MM_D3_D5>, +- <&topckgen CK_TOP_CB_MM_D4>, +- <&topckgen CK_TOP_MM_D6_D2>, +- <&topckgen CK_TOP_CB_MM_D8>, +- <&topckgen CK_TOP_CB_APLL2_196M>, +- <&topckgen CK_TOP_CB_APLL2_D4>, +- <&topckgen CK_TOP_CB_NET1_D4>, +- <&topckgen CK_TOP_CB_NET1_D5>, +- <&topckgen CK_TOP_NET1_D5_D2>, +- <&topckgen CK_TOP_NET1_D5_D4>, +- <&topckgen CK_TOP_CB_NET1_D8>, +- <&topckgen CK_TOP_NET1_D8_D2>, +- <&topckgen CK_TOP_NET1_D8_D4>, +- <&topckgen CK_TOP_NET1_D8_D8>, +- <&topckgen CK_TOP_NET1_D8_D16>, +- <&topckgen CK_TOP_CB_NET2_800M>, +- <&topckgen CK_TOP_CB_NET2_D2>, +- <&topckgen CK_TOP_CB_NET2_D4>, +- <&topckgen CK_TOP_NET2_D4_D4>, +- <&topckgen CK_TOP_NET2_D4_D8>, +- <&topckgen CK_TOP_CB_NET2_D6>, +- <&topckgen CK_TOP_CB_NET2_D8>, +- <&topckgen CK_TOP_CB_WEDMCU_208M>, +- <&topckgen CK_TOP_CB_SGM_325M>, +- <&topckgen CK_TOP_CB_NETSYS_850M>, +- <&topckgen CK_TOP_CB_MSDC_400M>, +- <&topckgen CK_TOP_CKSQ_40M_D2>, +- <&topckgen CK_TOP_CB_RTC_32K>, +- <&topckgen CK_TOP_CB_RTC_32P7K>, +- <&topckgen CK_TOP_INFRA_F32K>, +- <&topckgen CK_TOP_CKSQ_SRC>, +- <&topckgen CK_TOP_NETSYS_2X>, +- <&topckgen CK_TOP_NETSYS_GSW>, +- <&topckgen CK_TOP_NETSYS_WED_MCU>, +- <&topckgen CK_TOP_EIP197>, +- <&topckgen CK_TOP_EMMC_250M>, +- <&topckgen CK_TOP_EMMC_400M>, +- <&topckgen CK_TOP_SPI>, +- <&topckgen CK_TOP_SPIM_MST>, +- <&topckgen CK_TOP_NFI1X>, +- <&topckgen CK_TOP_SPINFI_BCK>, +- <&topckgen CK_TOP_I2C_BCK>, +- <&topckgen CK_TOP_USB_SYS>, +- <&topckgen CK_TOP_USB_SYS_P1>, +- <&topckgen CK_TOP_USB_XHCI>, +- <&topckgen CK_TOP_USB_XHCI_P1>, +- <&topckgen CK_TOP_USB_FRMCNT>, +- <&topckgen CK_TOP_USB_FRMCNT_P1>, +- <&topckgen CK_TOP_AUD>, +- <&topckgen CK_TOP_A1SYS>, +- <&topckgen CK_TOP_AUD_L>, +- <&topckgen CK_TOP_A_TUNER>, +- <&topckgen CK_TOP_SYSAXI>, +- <&topckgen CK_TOP_INFRA_F26M>, +- <&topckgen CK_TOP_USB_REF>, +- <&topckgen CK_TOP_USB_CK_P1>, +- <&topckgen CK_TOP_AUD_I2S_M>, +- <&topckgen CK_TOP_NETSYS_SEL>, +- <&topckgen CK_TOP_NETSYS_500M_SEL>, +- <&topckgen CK_TOP_NETSYS_2X_SEL>, +- <&topckgen CK_TOP_NETSYS_GSW_SEL>, +- <&topckgen CK_TOP_ETH_GMII_SEL>, +- <&topckgen CK_TOP_NETSYS_MCU_SEL>, +- <&topckgen CK_TOP_NETSYS_PAO_2X_SEL>, +- <&topckgen CK_TOP_EIP197_SEL>, +- <&topckgen CK_TOP_AXI_INFRA_SEL>, +- <&topckgen CK_TOP_UART_SEL>, +- <&topckgen CK_TOP_EMMC_250M_SEL>, +- <&topckgen CK_TOP_EMMC_400M_SEL>, +- <&topckgen CK_TOP_SPI_SEL>, +- <&topckgen CK_TOP_SPIM_MST_SEL>, +- <&topckgen CK_TOP_NFI1X_SEL>, +- <&topckgen CK_TOP_SPINFI_SEL>, +- <&topckgen CK_TOP_PWM_SEL>, +- <&topckgen CK_TOP_I2C_SEL>, +- <&topckgen CK_TOP_PCIE_MBIST_250M_SEL>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&topckgen CK_TOP_USB_SYS_SEL>, +- <&topckgen CK_TOP_USB_SYS_P1_SEL>, +- <&topckgen CK_TOP_USB_XHCI_SEL>, +- <&topckgen CK_TOP_USB_XHCI_P1_SEL>, +- <&topckgen CK_TOP_USB_FRMCNT_SEL>, +- <&topckgen CK_TOP_USB_FRMCNT_P1_SEL>, +- <&topckgen CK_TOP_AUD_SEL>, +- <&topckgen CK_TOP_A1SYS_SEL>, +- <&topckgen CK_TOP_AUD_L_SEL>, +- <&topckgen CK_TOP_A_TUNER_SEL>, +- <&topckgen CK_TOP_SSPXTP_SEL>, +- <&topckgen CK_TOP_USB_PHY_SEL>, +- <&topckgen CK_TOP_USXGMII_SBUS_0_SEL>, +- <&topckgen CK_TOP_USXGMII_SBUS_1_SEL>, +- <&topckgen CK_TOP_SGM_0_SEL>, +- <&topckgen CK_TOP_SGM_SBUS_0_SEL>, +- <&topckgen CK_TOP_SGM_1_SEL>, +- <&topckgen CK_TOP_SGM_SBUS_1_SEL>, +- <&topckgen CK_TOP_XFI_PHY_0_XTAL_SEL>, +- <&topckgen CK_TOP_XFI_PHY_1_XTAL_SEL>, +- <&topckgen CK_TOP_SYSAXI_SEL>, +- <&topckgen CK_TOP_SYSAPB_SEL>, +- <&topckgen CK_TOP_ETH_REFCK_50M_SEL>, +- <&topckgen CK_TOP_ETH_SYS_200M_SEL>, +- <&topckgen CK_TOP_ETH_SYS_SEL>, +- <&topckgen CK_TOP_ETH_XGMII_SEL>, +- <&topckgen CK_TOP_BUS_TOPS_SEL>, +- <&topckgen CK_TOP_NPU_TOPS_SEL>, +- <&topckgen CK_TOP_DRAMC_SEL>, +- <&topckgen CK_TOP_DRAMC_MD32_SEL>, +- <&topckgen CK_TOP_INFRA_F26M_SEL>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&topckgen CK_TOP_DA_XTP_GLB_P0_SEL>, +- <&topckgen CK_TOP_DA_XTP_GLB_P1_SEL>, +- <&topckgen CK_TOP_DA_XTP_GLB_P2_SEL>, +- <&topckgen CK_TOP_DA_XTP_GLB_P3_SEL>, +- <&topckgen CK_TOP_CKM_SEL>, +- <&topckgen CK_TOP_DA_SELM_XTAL_SEL>, +- <&topckgen CK_TOP_PEXTP_SEL>, +- <&topckgen CK_TOP_TOPS_P2_26M_SEL>, +- <&topckgen CK_TOP_MCUSYS_BACKUP_625M_SEL>, +- <&topckgen CK_TOP_NETSYS_SYNC_250M_SEL>, +- <&topckgen CK_TOP_MACSEC_SEL>, +- <&topckgen CK_TOP_NETSYS_TOPS_400M_SEL>, +- <&topckgen CK_TOP_NETSYS_PPEFB_250M_SEL>, +- <&topckgen CK_TOP_NETSYS_WARP_SEL>, +- <&topckgen CK_TOP_ETH_MII_SEL>, +- <&topckgen CK_TOP_CK_NPU_SEL_CM_TOPS_SEL>, +- <&infracfg CK_INFRA_CK_F26M>, +- <&infracfg CK_INFRA_PWM_O>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&infracfg CK_INFRA_133M_HCK>, +- <&infracfg CK_INFRA_133M_PHCK>, +- <&infracfg CK_INFRA_66M_PHCK>, +- <&infracfg CK_INFRA_FAUD_L_O>, +- <&infracfg CK_INFRA_FAUD_AUD_O>, +- <&infracfg CK_INFRA_FAUD_EG2_O>, +- <&infracfg CK_INFRA_I2C_O>, +- <&infracfg CK_INFRA_UART_O0>, +- <&infracfg CK_INFRA_UART_O1>, +- <&infracfg CK_INFRA_UART_O2>, +- <&infracfg CK_INFRA_NFI_O>, +- <&infracfg CK_INFRA_SPINFI_O>, +- <&infracfg CK_INFRA_SPI0_O>, +- <&infracfg CK_INFRA_SPI1_O>, +- <&infracfg CK_INFRA_LB_MUX_FRTC>, +- <&infracfg CK_INFRA_FRTC>, +- <&infracfg CK_INFRA_FMSDC400_O>, +- <&infracfg CK_INFRA_FMSDC2_HCK_OCC>, +- <&infracfg CK_INFRA_PERI_133M>, +- <&infracfg CK_INFRA_USB_O>, +- <&infracfg CK_INFRA_USB_O_P1>, +- <&infracfg CK_INFRA_USB_FRMCNT_O>, +- <&infracfg CK_INFRA_USB_FRMCNT_O_P1>, +- <&infracfg CK_INFRA_USB_XHCI_O>, +- <&infracfg CK_INFRA_USB_XHCI_O_P1>, +- <&infracfg CK_INFRA_USB_PIPE_O>, +- <&infracfg CK_INFRA_USB_PIPE_O_P1>, +- <&infracfg CK_INFRA_USB_UTMI_O>, +- <&infracfg CK_INFRA_USB_UTMI_O_P1>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&infracfg CK_INFRA_F26M_O0>, +- <&infracfg CK_INFRA_F26M_O1>, +- <&infracfg CK_INFRA_133M_MCK>, +- <&infracfg CK_INFRA_66M_MCK>, +- <&infracfg CK_INFRA_PERI_66M_O>, +- <&infracfg CK_INFRA_USB_SYS_O>, +- <&infracfg CK_INFRA_USB_SYS_O_P1>, +- <&infracfg_ao CK_INFRA_66M_GPT_BCK>, +- <&infracfg_ao CK_INFRA_66M_PWM_HCK>, +- <&infracfg_ao CK_INFRA_66M_PWM_BCK>, +- <&infracfg_ao CK_INFRA_66M_PWM_CK1>, +- <&infracfg_ao CK_INFRA_66M_PWM_CK2>, +- <&infracfg_ao CK_INFRA_66M_PWM_CK3>, +- <&infracfg_ao CK_INFRA_66M_PWM_CK4>, +- <&infracfg_ao CK_INFRA_66M_PWM_CK5>, +- <&infracfg_ao CK_INFRA_66M_PWM_CK6>, +- <&infracfg_ao CK_INFRA_66M_PWM_CK7>, +- <&infracfg_ao CK_INFRA_66M_PWM_CK8>, +- <&infracfg_ao CK_INFRA_133M_CQDMA_BCK>, +- <&infracfg_ao CK_INFRA_66M_AUD_SLV_BCK>, +- <&infracfg_ao CK_INFRA_AUD_26M>, +- <&infracfg_ao CK_INFRA_AUD_L>, +- <&infracfg_ao CK_INFRA_AUD_AUD>, +- <&infracfg_ao CK_INFRA_AUD_EG2>, +- <&infracfg_ao CK_INFRA_DRAMC_F26M>, +- <&infracfg_ao CK_INFRA_133M_DBG_ACKM>, +- <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>, +- <&infracfg_ao CK_INFRA_66M_SEJ_BCK>, +- <&infracfg_ao CK_INFRA_PRE_CK_SEJ_F13M>, +- <&infracfg_ao CK_INFRA_66M_TRNG>, +- <&infracfg_ao CK_INFRA_26M_THERM_SYSTEM>, +- <&infracfg_ao CK_INFRA_I2C_BCK>, +- <&infracfg_ao CK_INFRA_66M_UART0_PCK>, +- <&infracfg_ao CK_INFRA_66M_UART1_PCK>, +- <&infracfg_ao CK_INFRA_66M_UART2_PCK>, +- <&infracfg_ao CK_INFRA_52M_UART0_CK>, +- <&infracfg_ao CK_INFRA_52M_UART1_CK>, +- <&infracfg_ao CK_INFRA_52M_UART2_CK>, +- <&infracfg_ao CK_INFRA_NFI>, +- <&infracfg_ao CK_INFRA_SPINFI>, +- <&infracfg_ao CK_INFRA_66M_NFI_HCK>, +- <&infracfg_ao CK_INFRA_104M_SPI0>, +- <&infracfg_ao CK_INFRA_104M_SPI1>, +- <&infracfg_ao CK_INFRA_104M_SPI2_BCK>, +- <&infracfg_ao CK_INFRA_66M_SPI0_HCK>, +- <&infracfg_ao CK_INFRA_66M_SPI1_HCK>, +- <&infracfg_ao CK_INFRA_66M_SPI2_HCK>, +- <&infracfg_ao CK_INFRA_66M_FLASHIF_AXI>, +- <&infracfg_ao CK_INFRA_RTC>, +- <&infracfg_ao CK_INFRA_26M_ADC_BCK>, +- <&infracfg_ao CK_INFRA_RC_ADC>, +- <&infracfg_ao CK_INFRA_MSDC400>, +- <&infracfg_ao CK_INFRA_MSDC2_HCK>, +- <&infracfg_ao CK_INFRA_133M_MSDC_0_HCK>, +- <&infracfg_ao CK_INFRA_66M_MSDC_0_HCK>, +- <&infracfg_ao CK_INFRA_133M_CPUM_BCK>, +- <&infracfg_ao CK_INFRA_BIST2FPC>, +- <&infracfg_ao CK_INFRA_I2C_X16W_MCK_CK_P1>, +- <&infracfg_ao CK_INFRA_I2C_X16W_PCK_CK_P1>, +- <&infracfg_ao CK_INFRA_133M_USB_HCK>, +- <&infracfg_ao CK_INFRA_133M_USB_HCK_CK_P1>, +- <&infracfg_ao CK_INFRA_66M_USB_HCK>, +- <&infracfg_ao CK_INFRA_66M_USB_HCK_CK_P1>, +- <&infracfg_ao CK_INFRA_USB_SYS>, +- <&infracfg_ao CK_INFRA_USB_SYS_CK_P1>, +- <&infracfg_ao CK_INFRA_USB_REF>, +- <&infracfg_ao CK_INFRA_USB_CK_P1>, +- <&infracfg_ao CK_INFRA_USB_FRMCNT>, +- <&infracfg_ao CK_INFRA_USB_FRMCNT_CK_P1>, +- <&infracfg_ao CK_INFRA_USB_PIPE>, +- <&infracfg_ao CK_INFRA_USB_PIPE_CK_P1>, +- <&infracfg_ao CK_INFRA_USB_UTMI>, +- <&infracfg_ao CK_INFRA_USB_UTMI_CK_P1>, +- <&infracfg_ao CK_INFRA_USB_XHCI>, +- <&infracfg_ao CK_INFRA_USB_XHCI_CK_P1>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&infracfg_ao CK_INFRA_MUX_UART0_SEL>, +- <&infracfg_ao CK_INFRA_MUX_UART1_SEL>, +- <&infracfg_ao CK_INFRA_MUX_UART2_SEL>, +- <&infracfg_ao CK_INFRA_MUX_SPI0_SEL>, +- <&infracfg_ao CK_INFRA_MUX_SPI1_SEL>, +- <&infracfg_ao CK_INFRA_MUX_SPI2_SEL>, +- <&infracfg_ao CK_INFRA_PWM_SEL>, +- <&infracfg_ao CK_INFRA_PWM_CK1_SEL>, +- <&infracfg_ao CK_INFRA_PWM_CK2_SEL>, +- <&infracfg_ao CK_INFRA_PWM_CK3_SEL>, +- <&infracfg_ao CK_INFRA_PWM_CK4_SEL>, +- <&infracfg_ao CK_INFRA_PWM_CK5_SEL>, +- <&infracfg_ao CK_INFRA_PWM_CK6_SEL>, +- <&infracfg_ao CK_INFRA_PWM_CK7_SEL>, +- <&infracfg_ao CK_INFRA_PWM_CK8_SEL>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <&system_clk>, +- <ðsys CK_ETHDMA_XGP1_EN>, +- <ðsys CK_ETHDMA_XGP2_EN>, +- <ðsys CK_ETHDMA_XGP3_EN>, +- <ðsys CK_ETHDMA_FE_EN>, +- <ðsys CK_ETHDMA_GP2_EN>, +- <ðsys CK_ETHDMA_GP1_EN>, +- <ðsys CK_ETHDMA_GP3_EN>, +- <ðsys CK_ETHDMA_ESW_EN>, +- <ðsys CK_ETHDMA_CRYPT0_EN>, +- <ðwarp CK_ETHWARP_WOCPU2_EN>, +- <ðwarp CK_ETHWARP_WOCPU1_EN>, +- <ðwarp CK_ETHWARP_WOCPU0_EN>, +- <&sgmiisys0 CK_SGM0_TX_EN>, +- <&sgmiisys0 CK_SGM0_RX_EN>, +- <&sgmiisys1 CK_SGM1_TX_EN>, +- <&sgmiisys1 CK_SGM1_RX_EN>, +- <&mcusys CK_MCU_BUS_DIV_SEL>, +- <&mcusys CK_MCU_ARM_DIV_SEL>; +- +- clock-names = "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", +- "10", "11", "12", "13", "14", "15", "16", "17", +- "18", "19", "20", "21", "22", "23", "24", "25", +- "26", "27", "28", "29", "30", "31", "32", "33", +- "34", "35", "36", "37", "38", "39", "40", "41", +- "42", "43", "44", "45", "46", "47", "48", "49", +- "50", "51", "52", "53", "54", "55", "56", "57", +- "58", "59", "60", "61", "62", "63", "64", "65", +- "66", "67", "68", "69", "70", "71", "72", "73", +- "74", "75", "76", "77", "78", "79", "80", "81", +- "82", "83", "84", "85", "86", "87", "88", "89", +- "90", "91", "92", "93", "94", "95", "96", "97", +- "98", "99", "100", "101", "102", "103", "104", +- "105", "106", "107", "108", "109", "110", "111", +- "112", "113", "114", "115", "116", "117", "118", +- "119", "120", "121", "122", "123", "124", "125", +- "126", "127", "128", "129", "130", "131", "132", +- "133", "134", "135", "136", "137", "138", "139", +- "140", "141", "142", "143", "144", "145", "146", +- "147", "148", "149", "150", "151", "152", "153", +- "154", "155", "156", "157", "158", "159", "160", +- "161", "162", "163", "164", "165", "166", "167", +- "168", "169", "170", "171", "172", "173", "174", +- "175", "176", "177", "178", "179", "180", "181", +- "182", "183", "184", "185", "186", "187", "188", +- "189", "190", "191", "192", "193", "194", "195", +- "196", "197", "198", "199", "200", "201", "202", +- "203", "204", "205", "206", "207", "208", "209", +- "210", "211", "212", "213", "214", "215", "216", +- "217", "218", "219", "220", "221", "222", "223", +- "224", "225", "226", "227", "228", "229", "230", +- "231", "232", "233", "234", "235", "236", "237", +- "238", "239", "240", "241", "242", "243", "244", +- "245", "246", "247", "248", "249", "250", "251", +- "252", "253", "254", "255", "256", "257", "258", +- "259", "260", "261", "262", "263", "264", "265", +- "266", "267", "268", "269", "270", "271", "272", +- "273", "274", "275", "276", "277", "278", "279", +- "280", "281", "282", "283", "284", "285", "286", +- "287", "288", "289", "290", "291", "292", "293", +- "294", "295", "296", "297", "298", "299", "300", +- "301", "302", "303", "304", "305", "306", "307", +- "308", "309", "310", "311", "312", "313", "314", +- "315", "316", "317", "318", "319", "320", "321", +- "322", "323"; +- }; +-}; +- From 2cd2e61bee26e891097151ae66e9e18d6a1e84a4 Mon Sep 17 00:00:00 2001 From: Fujr Date: Sun, 26 Feb 2023 09:34:33 +0800 Subject: [PATCH 02/18] suport 360 t7 --- .../0005-add_360t7-support.patch => 4010-support-360-t7.patch | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename patches-mt798x-7.6.6.1/0005-add_360t7-support.patch => 4010-support-360-t7.patch (100%) diff --git a/patches-mt798x-7.6.6.1/0005-add_360t7-support.patch b/4010-support-360-t7.patch similarity index 100% rename from patches-mt798x-7.6.6.1/0005-add_360t7-support.patch rename to 4010-support-360-t7.patch From 146f7129a9f3ee57ed700e2c93cfd5567f44b82b Mon Sep 17 00:00:00 2001 From: Fujr Date: Sun, 26 Feb 2023 09:39:10 +0800 Subject: [PATCH 03/18] renamed: 4010-support-360-t7.patch -> patches-mt798x-7.6.6.1/4010-support-360-t7.patch --- .../4010-support-360-t7.patch | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename 4010-support-360-t7.patch => patches-mt798x-7.6.6.1/4010-support-360-t7.patch (100%) diff --git a/4010-support-360-t7.patch b/patches-mt798x-7.6.6.1/4010-support-360-t7.patch similarity index 100% rename from 4010-support-360-t7.patch rename to patches-mt798x-7.6.6.1/4010-support-360-t7.patch From a3dcbab2d77007080be87d6ed94e31e1628365ca Mon Sep 17 00:00:00 2001 From: Fujr Date: Sun, 26 Feb 2023 10:00:29 +0800 Subject: [PATCH 04/18] ed: patches-mt798x-7.6.6.1/4010-support-360-t7.patch --- .../4010-support-360-t7.patch | 8618 +---------------- 1 file changed, 324 insertions(+), 8294 deletions(-) diff --git a/patches-mt798x-7.6.6.1/4010-support-360-t7.patch b/patches-mt798x-7.6.6.1/4010-support-360-t7.patch index 993a673..115eb7a 100644 --- a/patches-mt798x-7.6.6.1/4010-support-360-t7.patch +++ b/patches-mt798x-7.6.6.1/4010-support-360-t7.patch @@ -1,8335 +1,365 @@ -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts 2023-02-26 09:01:19.877971900 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,591 +0,0 @@ --/* -- * Copyright (c) 2018 MediaTek Inc. -- * Author: Ryder Lee -- * -- * SPDX-License-Identifier: (GPL-2.0-only OR MIT) -- */ -- --/dts-v1/; --#include --#include -- --#include "mt7622.dtsi" --#include "mt6380.dtsi" -- --/ { -- model = "Bananapi BPI-R64"; -- compatible = "bananapi,bpi-r64-rootdisk", "mediatek,mt7622"; -- -- aliases { -- serial0 = &uart0; -- }; -- -- chosen { -- stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=/dev/mmcblk0p7 rootfstype=squashfs,f2fs"; -- }; -- -- cpus { -- cpu@0 { -- proc-supply = <&mt6380_vcpu_reg>; -- sram-supply = <&mt6380_vm_reg>; -- }; -- -- cpu@1 { -- proc-supply = <&mt6380_vcpu_reg>; -- sram-supply = <&mt6380_vm_reg>; -- }; -- }; -- -- gpio-keys { -- compatible = "gpio-keys"; -- -- factory { -- label = "factory"; -- linux,code = ; -- gpios = <&pio 0 GPIO_ACTIVE_HIGH>; -- }; -- -- wps { -- label = "wps"; -- linux,code = ; -- gpios = <&pio 102 GPIO_ACTIVE_HIGH>; -- }; -- }; -- -- leds { -- compatible = "gpio-leds"; -- -- green { -- label = "bpi-r64:pio:green"; -- gpios = <&pio 89 GPIO_ACTIVE_HIGH>; -- }; -- -- red { -- label = "bpi-r64:pio:red"; -- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -- }; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x40000000>; -- }; -- -- reg_1p8v: regulator-1p8v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-1.8V"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-always-on; -- }; -- -- reg_3p3v: regulator-3p3v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-3.3V"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-boot-on; -- regulator-always-on; -- }; -- -- reg_5v: regulator-5v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-5V"; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- regulator-boot-on; -- regulator-always-on; -- }; --}; -- --&bch { -- status = "disabled"; --}; -- --&btif { -- status = "okay"; --}; -- --&cir { -- pinctrl-names = "default"; -- pinctrl-0 = <&irrx_pins>; -- status = "okay"; --}; -- --ð { -- status = "okay"; -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "2500base-x"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "rgmii"; -- -- fixed-link { -- speed = <1000>; -- full-duplex; -- pause; -- }; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- -- switch@1f { -- compatible = "mediatek,mt7531"; -- reg = <0x1f>; -- reset-gpios = <&pio 54 0>; -- -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- wan: port@0 { -- reg = <0>; -- label = "wan"; -- }; -- -- port@1 { -- reg = <1>; -- label = "lan0"; -- }; -- -- port@2 { -- reg = <2>; -- label = "lan1"; -- }; -- -- port@3 { -- reg = <3>; -- label = "lan2"; -- }; -- -- port@4 { -- reg = <4>; -- label = "lan3"; -- }; -- -- port@6 { -- reg = <6>; -- label = "cpu"; -- ethernet = <&gmac0>; -- phy-mode = "2500base-x"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- }; -- }; -- -- }; --}; -- --&i2c1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c1_pins>; -- status = "okay"; --}; -- --&i2c2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c2_pins>; -- status = "okay"; --}; -- --&mmc0 { -- pinctrl-names = "default", "state_uhs"; -- pinctrl-0 = <&emmc_pins_default>; -- pinctrl-1 = <&emmc_pins_uhs>; -- status = "okay"; -- bus-width = <8>; -- max-frequency = <50000000>; -- cap-mmc-highspeed; -- mmc-hs200-1_8v; -- vmmc-supply = <®_3p3v>; -- vqmmc-supply = <®_1p8v>; -- assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; -- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; -- non-removable; --}; -- --&mmc1 { -- pinctrl-names = "default", "state_uhs"; -- pinctrl-0 = <&sd0_pins_default>; -- pinctrl-1 = <&sd0_pins_uhs>; -- status = "okay"; -- bus-width = <4>; -- max-frequency = <50000000>; -- cap-sd-highspeed; -- r_smpl = <1>; -- cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; -- vmmc-supply = <®_3p3v>; -- vqmmc-supply = <®_3p3v>; -- assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; -- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; --}; -- --&nandc { -- pinctrl-names = "default"; -- pinctrl-0 = <¶llel_nand_pins>; -- status = "disabled"; --}; -- --&nor_flash { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi_nor_pins>; -- status = "disabled"; -- -- flash@0 { -- compatible = "jedec,spi-nor"; -- reg = <0>; -- }; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&pcie1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie1_pins>; -- status = "okay"; --}; -- --&pio { -- /* Attention: GPIO 90 is used to switch between PCIe@1,0 and -- * SATA functions. i.e. output-high: PCIe, output-low: SATA -- */ -- asm_sel { -- gpio-hog; -- gpios = <90 GPIO_ACTIVE_HIGH>; -- output-high; -- }; -- -- /* eMMC is shared pin with parallel NAND */ -- emmc_pins_default: emmc-pins-default { -- mux { -- function = "emmc", "emmc_rst"; -- groups = "emmc"; -- }; -- -- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", -- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, -- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively -- */ -- conf-cmd-dat { -- pins = "NDL0", "NDL1", "NDL2", -- "NDL3", "NDL4", "NDL5", -- "NDL6", "NDL7", "NRB"; -- input-enable; -- bias-pull-up; -- }; -- -- conf-clk { -- pins = "NCLE"; -- bias-pull-down; -- }; -- }; -- -- emmc_pins_uhs: emmc-pins-uhs { -- mux { -- function = "emmc"; -- groups = "emmc"; -- }; -- -- conf-cmd-dat { -- pins = "NDL0", "NDL1", "NDL2", -- "NDL3", "NDL4", "NDL5", -- "NDL6", "NDL7", "NRB"; -- input-enable; -- drive-strength = <4>; -- bias-pull-up; -- }; -- -- conf-clk { -- pins = "NCLE"; -- drive-strength = <4>; -- bias-pull-down; -- }; -- }; -- -- eth_pins: eth-pins { -- mux { -- function = "eth"; -- groups = "mdc_mdio", "rgmii_via_gmac2"; -- }; -- }; -- -- i2c1_pins: i2c1-pins { -- mux { -- function = "i2c"; -- groups = "i2c1_0"; -- }; -- }; -- -- i2c2_pins: i2c2-pins { -- mux { -- function = "i2c"; -- groups = "i2c2_0"; -- }; -- }; -- -- i2s1_pins: i2s1-pins { -- mux { -- function = "i2s"; -- groups = "i2s_out_mclk_bclk_ws", -- "i2s1_in_data", -- "i2s1_out_data"; -- }; -- -- conf { -- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", -- "I2S_WS", "I2S_MCLK"; -- drive-strength = <12>; -- bias-pull-down; -- }; -- }; -- -- irrx_pins: irrx-pins { -- mux { -- function = "ir"; -- groups = "ir_1_rx"; -- }; -- }; -- -- irtx_pins: irtx-pins { -- mux { -- function = "ir"; -- groups = "ir_1_tx"; -- }; -- }; -- -- /* Parallel nand is shared pin with eMMC */ -- parallel_nand_pins: parallel-nand-pins { -- mux { -- function = "flash"; -- groups = "par_nand"; -- }; -- }; -- -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie0_pad_perst", -- "pcie0_1_waken", -- "pcie0_1_clkreq"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie1_pad_perst", -- "pcie1_0_waken", -- "pcie1_0_clkreq"; -- }; -- }; -- -- pmic_bus_pins: pmic-bus-pins { -- mux { -- function = "pmic"; -- groups = "pmic_bus"; -- }; -- }; -- -- pwm7_pins: pwm1-2-pins { -- mux { -- function = "pwm"; -- groups = "pwm_ch7_2"; -- }; -- }; -- -- wled_pins: wled-pins { -- mux { -- function = "led"; -- groups = "wled"; -- }; -- }; -- -- sd0_pins_default: sd0-pins-default { -- mux { -- function = "sd"; -- groups = "sd_0"; -- }; -- -- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", -- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, -- * DAT2, DAT3, CMD, CLK for SD respectively. -- */ -- conf-cmd-data { -- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", -- "I2S2_IN","I2S4_OUT"; -- input-enable; -- drive-strength = <8>; -- bias-pull-up; -- }; -- conf-clk { -- pins = "I2S3_OUT"; -- drive-strength = <12>; -- bias-pull-down; -- }; -- conf-cd { -- pins = "TXD3"; -- bias-pull-up; -- }; -- }; -- -- sd0_pins_uhs: sd0-pins-uhs { -- mux { -- function = "sd"; -- groups = "sd_0"; -- }; -- -- conf-cmd-data { -- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", -- "I2S2_IN","I2S4_OUT"; -- input-enable; -- bias-pull-up; -- }; -- -- conf-clk { -- pins = "I2S3_OUT"; -- bias-pull-down; -- }; -- }; -- -- /* Serial NAND is shared pin with SPI-NOR */ -- serial_nand_pins: serial-nand-pins { -- mux { -- function = "flash"; -- groups = "snfi"; -- }; -- }; -- -- spic0_pins: spic0-pins { -- mux { -- function = "spi"; -- groups = "spic0_0"; -- }; -- }; -- -- spic1_pins: spic1-pins { -- mux { -- function = "spi"; -- groups = "spic1_0"; -- }; -- }; -- -- /* SPI-NOR is shared pin with serial NAND */ -- spi_nor_pins: spi-nor-pins { -- mux { -- function = "flash"; -- groups = "spi_nor"; -- }; -- }; -- -- /* serial NAND is shared pin with SPI-NOR */ -- serial_nand_pins: serial-nand-pins { -- mux { -- function = "flash"; -- groups = "snfi"; -- }; -- }; -- -- uart0_pins: uart0-pins { -- mux { -- function = "uart"; -- groups = "uart0_0_tx_rx" ; -- }; -- }; -- -- uart2_pins: uart2-pins { -- mux { -- function = "uart"; -- groups = "uart2_1_tx_rx" ; -- }; -- }; -- -- watchdog_pins: watchdog-pins { -- mux { -- function = "watchdog"; -- groups = "watchdog"; -- }; -- }; --}; -- --&pwm { -- pinctrl-names = "default"; -- pinctrl-0 = <&pwm7_pins>; -- status = "okay"; --}; -- --&pwrap { -- pinctrl-names = "default"; -- pinctrl-0 = <&pmic_bus_pins>; -- -- status = "okay"; --}; -- --&sata { -- status = "disable"; --}; -- --&sata_phy { -- status = "disable"; --}; -- --&spi0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spic0_pins>; -- status = "okay"; --}; -- --&spi1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spic1_pins>; -- status = "okay"; --}; -- --&ssusb { -- vusb33-supply = <®_3p3v>; -- vbus-supply = <®_5v>; -- status = "okay"; --}; -- --&u3phy { -- status = "okay"; --}; -- --&uart0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart0_pins>; -- status = "okay"; --}; -- --&uart2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart2_pins>; -- status = "okay"; --}; -- --&watchdog { -- pinctrl-names = "default"; -- pinctrl-0 = <&watchdog_pins>; -- status = "okay"; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts 2023-02-26 09:01:19.878971500 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,608 +0,0 @@ --/* -- * Copyright (c) 2017 MediaTek Inc. -- * Author: Ming Huang -- * Sean Wang -- * -- * SPDX-License-Identifier: (GPL-2.0-only OR MIT) -- */ -- --/dts-v1/; --#include --#include -- --#include "mt7622.dtsi" --#include "mt6380.dtsi" -- --/ { -- model = "Elecom WRC-2533"; -- compatible = "elecom,wrc-2533gent", "mediatek,mt7622"; -- -- aliases { -- led-boot = &led_power; -- led-failsafe = &led_power; -- led-running = &led_power; -- led-upgrade = &led_power; -- serial0 = &uart0; -- }; -- -- chosen { -- stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8"; -- }; -- -- cpus { -- cpu@0 { -- proc-supply = <&mt6380_vcpu_reg>; -- sram-supply = <&mt6380_vm_reg>; -- }; -- -- cpu@1 { -- proc-supply = <&mt6380_vcpu_reg>; -- sram-supply = <&mt6380_vm_reg>; -- }; -- }; -- -- gpio-keys { -- compatible = "gpio-keys"; -- poll-interval = <100>; -- -- wps { -- label = "wps"; -- linux,code = ; -- gpios = <&pio 0 GPIO_ACTIVE_HIGH>; -- }; -- -- factory { -- label = "factory"; -- linux,code = ; -- gpios = <&pio 102 GPIO_ACTIVE_LOW>; -- }; -- -- switch0 { -- label = "switch0"; -- gpios = <&pio 1 GPIO_ACTIVE_LOW>; -- linux,code = ; -- linux,input-type = ; -- }; -- -- switch1 { -- label = "switch1"; -- gpios = <&pio 16 GPIO_ACTIVE_LOW>; -- linux,code = ; -- linux,input-type = ; -- }; -- -- switch2 { -- label = "switch2"; -- gpios = <&pio 17 GPIO_ACTIVE_LOW>; -- linux,code = ; -- linux,input-type = ; -- }; -- -- switch3 { -- label = "switch3"; -- gpios = <&pio 18 GPIO_ACTIVE_LOW>; -- linux,code = ; -- linux,input-type = ; -- }; -- }; -- -- leds { -- compatible = "gpio-leds"; -- -- led_power: power_g { -- label = "wrc-2533:green:power"; -- gpios = <&pio 2 GPIO_ACTIVE_HIGH>; -- }; -- -- power_b { -- label = "wrc-2533:blue:power"; -- gpios = <&pio 19 GPIO_ACTIVE_HIGH>; -- }; -- -- power_r { -- label = "wrc-2533:red:power"; -- gpios = <&pio 73 GPIO_ACTIVE_HIGH>; -- }; -- -- usb { -- label = "wrc-2533:blue:usb"; -- gpios = <&pio 74 GPIO_ACTIVE_HIGH>; -- }; -- -- wps { -- label = "wrc-2533:red:wps"; -- gpios = <&pio 76 GPIO_ACTIVE_LOW>; -- }; -- -- wifi2 { -- label = "wrc-2533:blue:wifi2g"; -- gpios = <&pio 85 GPIO_ACTIVE_LOW>; -- }; -- -- wifi5 { -- label = "wrc-2533:blue:wifi5g"; -- gpios = <&pio 91 GPIO_ACTIVE_LOW>; -- }; -- }; -- -- reg_usb_vbus: regulator { -- compatible = "regulator-fixed"; -- regulator-name = "usb_vbus"; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- gpio = <&pio 22 GPIO_ACTIVE_LOW>; -- enable-active-high; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x3F000000>; -- }; -- -- reg_1p8v: regulator-1p8v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-1.8V"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-always-on; -- }; -- -- reg_3p3v: regulator-3p3v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-3.3V"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-boot-on; -- regulator-always-on; -- }; -- -- rtkgsw: rtkgsw@0 { -- compatible = "mediatek,rtk-gsw"; -- mediatek,ethsys = <ðsys>; -- mediatek,mdio = <&mdio>; -- mediatek,reset-pin = <&pio 54 0>; -- status = "okay"; -- }; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&slot0 { -- mt7615@0,0 { -- reg = <0x0000 0 0 0 0>; -- mediatek,mtd-eeprom = <&factory 0x05000>; -- }; --}; -- --&pio { -- /* eMMC is shared pin with parallel NAND */ -- emmc_pins_default: emmc-pins-default { -- mux { -- function = "emmc", "emmc_rst"; -- groups = "emmc"; -- }; -- -- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", -- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, -- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively -- */ -- conf-cmd-dat { -- pins = "NDL0", "NDL1", "NDL2", -- "NDL3", "NDL4", "NDL5", -- "NDL6", "NDL7", "NRB"; -- input-enable; -- bias-pull-up; -- }; -- -- conf-clk { -- pins = "NCLE"; -- bias-pull-down; -- }; -- }; -- -- emmc_pins_uhs: emmc-pins-uhs { -- mux { -- function = "emmc"; -- groups = "emmc"; -- }; -- -- conf-cmd-dat { -- pins = "NDL0", "NDL1", "NDL2", -- "NDL3", "NDL4", "NDL5", -- "NDL6", "NDL7", "NRB"; -- input-enable; -- drive-strength = <4>; -- bias-pull-up; -- }; -- -- conf-clk { -- pins = "NCLE"; -- drive-strength = <4>; -- bias-pull-down; -- }; -- }; -- -- eth_pins: eth-pins { -- mux { -- function = "eth"; -- groups = "mdc_mdio", "rgmii_via_gmac2"; -- }; -- }; -- -- i2c1_pins: i2c1-pins { -- mux { -- function = "i2c"; -- groups = "i2c1_0"; -- }; -- }; -- -- i2c2_pins: i2c2-pins { -- mux { -- function = "i2c"; -- groups = "i2c2_0"; -- }; -- }; -- -- i2s1_pins: i2s1-pins { -- mux { -- function = "i2s"; -- groups = "i2s_out_mclk_bclk_ws", -- "i2s1_in_data", -- "i2s1_out_data"; -- }; -- -- conf { -- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", -- "I2S_WS", "I2S_MCLK"; -- drive-strength = <12>; -- bias-pull-down; -- }; -- }; -- -- irrx_pins: irrx-pins { -- mux { -- function = "ir"; -- groups = "ir_1_rx"; -- }; -- }; -- -- irtx_pins: irtx-pins { -- mux { -- function = "ir"; -- groups = "ir_1_tx"; -- }; -- }; -- -- /* Parallel nand is shared pin with eMMC */ -- parallel_nand_pins: parallel-nand-pins { -- mux { -- function = "flash"; -- groups = "par_nand"; -- }; -- }; -- -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie0_pad_perst", -- "pcie0_1_waken", -- "pcie0_1_clkreq"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie1_pad_perst", -- "pcie1_0_waken", -- "pcie1_0_clkreq"; -- }; -- }; -- -- pmic_bus_pins: pmic-bus-pins { -- mux { -- function = "pmic"; -- groups = "pmic_bus"; -- }; -- }; -- -- pwm7_pins: pwm1-2-pins { -- mux { -- function = "pwm"; -- groups = "pwm_ch7_2"; -- }; -- }; -- -- wled_pins: wled-pins { -- mux { -- function = "led"; -- groups = "wled"; -- }; -- }; -- -- sd0_pins_default: sd0-pins-default { -- mux { -- function = "sd"; -- groups = "sd_0"; -- }; -- -- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", -- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, -- * DAT2, DAT3, CMD, CLK for SD respectively. -- */ -- conf-cmd-data { -- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", -- "I2S2_IN","I2S4_OUT"; -- input-enable; -- drive-strength = <8>; -- bias-pull-up; -- }; -- conf-clk { -- pins = "I2S3_OUT"; -- drive-strength = <12>; -- bias-pull-down; -- }; -- conf-cd { -- pins = "TXD3"; -- bias-pull-up; -- }; -- }; -- -- sd0_pins_uhs: sd0-pins-uhs { -- mux { -- function = "sd"; -- groups = "sd_0"; -- }; -- -- conf-cmd-data { -- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", -- "I2S2_IN","I2S4_OUT"; -- input-enable; -- bias-pull-up; -- }; -- -- conf-clk { -- pins = "I2S3_OUT"; -- bias-pull-down; -- }; -- }; -- -- /* Serial NAND is shared pin with SPI-NOR */ -- serial_nand_pins: serial-nand-pins { -- mux { -- function = "flash"; -- groups = "snfi"; -- }; -- }; -- -- spic0_pins: spic0-pins { -- mux { -- function = "spi"; -- groups = "spic0_0"; -- }; -- }; -- -- spic1_pins: spic1-pins { -- mux { -- function = "spi"; -- groups = "spic1_0"; -- }; -- }; -- -- /* SPI-NOR is shared pin with serial NAND */ -- spi_nor_pins: spi-nor-pins { -- mux { -- function = "flash"; -- groups = "spi_nor"; -- }; -- }; -- -- /* serial NAND is shared pin with SPI-NOR */ -- serial_nand_pins: serial-nand-pins { -- mux { -- function = "flash"; -- groups = "snfi"; -- }; -- }; -- -- uart0_pins: uart0-pins { -- mux { -- function = "uart"; -- groups = "uart0_0_tx_rx" ; -- }; -- }; -- -- uart2_pins: uart2-pins { -- mux { -- function = "uart"; -- groups = "uart2_1_tx_rx" ; -- }; -- }; -- -- watchdog_pins: watchdog-pins { -- mux { -- function = "watchdog"; -- groups = "watchdog"; -- }; -- }; --}; -- --&bch { -- status = "okay"; --}; -- --&btif { -- status = "disabled"; --}; -- --&cir { -- pinctrl-names = "default"; -- pinctrl-0 = <&irrx_pins>; -- status = "okay"; --}; -- --ð { -- status = "okay"; -- pinctrl-names = "default"; -- pinctrl-0 = <ð_pins>; -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "sgmii"; -- fixed-link { -- speed = <1000>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "rgmii"; -- fixed-link { -- speed = <1000>; -- full-duplex; -- pause; -- }; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- }; --}; -- --&i2c1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c1_pins>; -- status = "okay"; --}; -- --&i2c2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c2_pins>; -- status = "okay"; --}; -- --&pwm { -- pinctrl-names = "default"; -- pinctrl-0 = <&pwm7_pins>; -- status = "okay"; --}; -- --&pwrap { -- pinctrl-names = "default"; -- pinctrl-0 = <&pmic_bus_pins>; -- -- status = "okay"; --}; -- --&snfi { -- pinctrl-names = "default"; -- pinctrl-0 = <&serial_nand_pins>; -- status = "okay"; -- -- spi_nand@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "spi-nand"; -- spi-max-frequency = <104000000>; -- reg = <0>; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "Preloader"; -- reg = <0x00000 0x0080000>; -- read-only; -- }; -- -- partition@80000 { -- label = "ATF"; -- reg = <0x80000 0x0040000>; -- read-only; -- }; -- -- partition@c0000 { -- label = "uboot"; -- reg = <0xc0000 0x0080000>; -- read-only; -- }; -- -- partition@140000 { -- label = "uboot-env"; -- reg = <0x140000 0x0080000>; -- read-only; -- }; -- -- factory: partition@1c0000 { -- label = "factory"; -- reg = <0x1c0000 0x0040000>; -- read-only; -- }; -- -- partition@200000 { -- label = "firmware"; -- reg = <0x200000 0x2000000>; -- }; -- -- partition@2200000 { -- label = "reserved"; -- reg = <0x2200000 0x4000000>; -- }; -- }; -- }; --}; -- --&spi0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spic0_pins>; -- status = "okay"; --}; -- --&spi1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spic1_pins>; -- status = "okay"; --}; -- --&ssusb { -- vusb33-supply = <®_3p3v>; -- vbus-supply = <®_usb_vbus>; -- status = "okay"; --}; -- --&u3phy { -- status = "okay"; --}; -- --&uart0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart0_pins>; -- status = "okay"; --}; -- --&uart2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart2_pins>; -- status = "okay"; --}; -- --&watchdog { -- pinctrl-names = "default"; -- pinctrl-0 = <&watchdog_pins>; -- status = "okay"; --}; -- --&wmac { -- mediatek,mtd-eeprom = <&factory 0x0000>; -- status = "okay"; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts 2023-02-26 09:01:19.879971900 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,644 +0,0 @@ --/* -- * Copyright (c) 2018 MediaTek Inc. -- * Author: Ryder Lee -- * -- * SPDX-License-Identifier: (GPL-2.0-only OR MIT) -- */ -- --/dts-v1/; --#include --#include -- --#include "mt7622.dtsi" --#include "mt6380.dtsi" -- --/ { -- model = "MT7622_MT7531 RFB"; -- compatible = "mediatek,mt7622,ubi"; -- -- aliases { -- serial0 = &uart0; -- }; -- -- chosen { -- stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; -- }; -- -- cpus { -- cpu@0 { -- proc-supply = <&mt6380_vcpu_reg>; -- sram-supply = <&mt6380_vm_reg>; -- }; -- -- cpu@1 { -- proc-supply = <&mt6380_vcpu_reg>; -- sram-supply = <&mt6380_vm_reg>; -- }; -- }; -- -- gpio-keys { -- compatible = "gpio-keys"; -- -- factory { -- label = "factory"; -- linux,code = ; -- gpios = <&pio 0 GPIO_ACTIVE_HIGH>; -- }; -- -- wps { -- label = "wps"; -- linux,code = ; -- gpios = <&pio 102 GPIO_ACTIVE_HIGH>; -- }; -- }; -- -- gsw: gsw@0 { -- compatible = "mediatek,mt753x"; -- mediatek,ethsys = <ðsys>; -- #address-cells = <1>; -- #size-cells = <0>; -- }; -- -- leds { -- compatible = "gpio-leds"; -- -- green { -- label = "bpi-r64:pio:green"; -- gpios = <&pio 89 GPIO_ACTIVE_HIGH>; -- }; -- -- red { -- label = "bpi-r64:pio:red"; -- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -- }; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x40000000>; -- }; -- -- reg_1p8v: regulator-1p8v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-1.8V"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-always-on; -- }; -- -- reg_3p3v: regulator-3p3v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-3.3V"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-boot-on; -- regulator-always-on; -- }; -- -- reg_5v: regulator-5v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-5V"; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- regulator-boot-on; -- regulator-always-on; -- }; --}; -- --&bch { -- status = "okay"; --}; -- --&btif { -- status = "okay"; --}; -- --&cir { -- pinctrl-names = "default"; -- pinctrl-0 = <&irrx_pins>; -- status = "okay"; --}; -- --ð { -- status = "okay"; -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "2500base-x"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "rgmii"; -- -- fixed-link { -- speed = <1000>; -- full-duplex; -- pause; -- }; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- }; --}; -- --&gsw { -- mediatek,mdio = <&mdio>; -- mediatek,portmap = "llllw"; -- mediatek,mdio_master_pinmux = <0>; -- reset-gpios = <&pio 54 0>; -- interrupt-parent = <&pio>; -- interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; -- status = "okay"; -- -- port5: port@5 { -- compatible = "mediatek,mt753x-port"; -- reg = <5>; -- phy-mode = "rgmii"; -- fixed-link { -- speed = <1000>; -- full-duplex; -- }; -- }; -- -- port6: port@6 { -- compatible = "mediatek,mt753x-port"; -- reg = <6>; -- phy-mode = "sgmii"; -- fixed-link { -- speed = <2500>; -- full-duplex; -- }; -- }; --}; -- --&i2c1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c1_pins>; -- status = "okay"; --}; -- --&i2c2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c2_pins>; -- status = "okay"; --}; -- --&mmc0 { -- pinctrl-names = "default", "state_uhs"; -- pinctrl-0 = <&emmc_pins_default>; -- pinctrl-1 = <&emmc_pins_uhs>; -- status = "okay"; -- bus-width = <8>; -- max-frequency = <50000000>; -- cap-mmc-highspeed; -- mmc-hs200-1_8v; -- vmmc-supply = <®_3p3v>; -- vqmmc-supply = <®_1p8v>; -- assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; -- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; -- non-removable; --}; -- --&mmc1 { -- pinctrl-names = "default", "state_uhs"; -- pinctrl-0 = <&sd0_pins_default>; -- pinctrl-1 = <&sd0_pins_uhs>; -- status = "okay"; -- bus-width = <4>; -- max-frequency = <50000000>; -- cap-sd-highspeed; -- r_smpl = <1>; -- cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; -- vmmc-supply = <®_3p3v>; -- vqmmc-supply = <®_3p3v>; -- assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; -- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; --}; -- --&nandc { -- pinctrl-names = "default"; -- pinctrl-0 = <¶llel_nand_pins>; -- status = "disabled"; --}; -- --&nor_flash { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi_nor_pins>; -- status = "disabled"; -- -- flash@0 { -- compatible = "jedec,spi-nor"; -- reg = <0>; -- }; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&pcie1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie1_pins>; -- status = "okay"; --}; -- --&pio { -- /* Attention: GPIO 90 is used to switch between PCIe@1,0 and -- * SATA functions. i.e. output-high: PCIe, output-low: SATA -- */ -- asm_sel { -- gpio-hog; -- gpios = <90 GPIO_ACTIVE_HIGH>; -- output-high; -- }; -- -- /* eMMC is shared pin with parallel NAND */ -- emmc_pins_default: emmc-pins-default { -- mux { -- function = "emmc", "emmc_rst"; -- groups = "emmc"; -- }; -- -- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", -- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, -- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively -- */ -- conf-cmd-dat { -- pins = "NDL0", "NDL1", "NDL2", -- "NDL3", "NDL4", "NDL5", -- "NDL6", "NDL7", "NRB"; -- input-enable; -- bias-pull-up; -- }; -- -- conf-clk { -- pins = "NCLE"; -- bias-pull-down; -- }; -- }; -- -- emmc_pins_uhs: emmc-pins-uhs { -- mux { -- function = "emmc"; -- groups = "emmc"; -- }; -- -- conf-cmd-dat { -- pins = "NDL0", "NDL1", "NDL2", -- "NDL3", "NDL4", "NDL5", -- "NDL6", "NDL7", "NRB"; -- input-enable; -- drive-strength = <4>; -- bias-pull-up; -- }; -- -- conf-clk { -- pins = "NCLE"; -- drive-strength = <4>; -- bias-pull-down; -- }; -- }; -- -- eth_pins: eth-pins { -- mux { -- function = "eth"; -- groups = "mdc_mdio", "rgmii_via_gmac2"; -- }; -- }; -- -- i2c1_pins: i2c1-pins { -- mux { -- function = "i2c"; -- groups = "i2c1_0"; -- }; -- }; -- -- i2c2_pins: i2c2-pins { -- mux { -- function = "i2c"; -- groups = "i2c2_0"; -- }; -- }; -- -- i2s1_pins: i2s1-pins { -- mux { -- function = "i2s"; -- groups = "i2s_out_mclk_bclk_ws", -- "i2s1_in_data", -- "i2s1_out_data"; -- }; -- -- conf { -- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", -- "I2S_WS", "I2S_MCLK"; -- drive-strength = <12>; -- bias-pull-down; -- }; -- }; -- -- irrx_pins: irrx-pins { -- mux { -- function = "ir"; -- groups = "ir_1_rx"; -- }; -- }; -- -- irtx_pins: irtx-pins { -- mux { -- function = "ir"; -- groups = "ir_1_tx"; -- }; -- }; -- -- /* Parallel nand is shared pin with eMMC */ -- parallel_nand_pins: parallel-nand-pins { -- mux { -- function = "flash"; -- groups = "par_nand"; -- }; -- }; -- -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie0_pad_perst", -- "pcie0_1_waken", -- "pcie0_1_clkreq"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie1_pad_perst", -- "pcie1_0_waken", -- "pcie1_0_clkreq"; -- }; -- }; -- -- pmic_bus_pins: pmic-bus-pins { -- mux { -- function = "pmic"; -- groups = "pmic_bus"; -- }; -- }; -- -- pwm7_pins: pwm1-2-pins { -- mux { -- function = "pwm"; -- groups = "pwm_ch7_2"; -- }; -- }; -- -- wled_pins: wled-pins { -- mux { -- function = "led"; -- groups = "wled"; -- }; -- }; -- -- sd0_pins_default: sd0-pins-default { -- mux { -- function = "sd"; -- groups = "sd_0"; -- }; -- -- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", -- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, -- * DAT2, DAT3, CMD, CLK for SD respectively. -- */ -- conf-cmd-data { -- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", -- "I2S2_IN","I2S4_OUT"; -- input-enable; -- drive-strength = <8>; -- bias-pull-up; -- }; -- conf-clk { -- pins = "I2S3_OUT"; -- drive-strength = <12>; -- bias-pull-down; -- }; -- conf-cd { -- pins = "TXD3"; -- bias-pull-up; -- }; -- }; -- -- sd0_pins_uhs: sd0-pins-uhs { -- mux { -- function = "sd"; -- groups = "sd_0"; -- }; -- -- conf-cmd-data { -- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", -- "I2S2_IN","I2S4_OUT"; -- input-enable; -- bias-pull-up; -- }; -- -- conf-clk { -- pins = "I2S3_OUT"; -- bias-pull-down; -- }; -- }; -- -- /* Serial NAND is shared pin with SPI-NOR */ -- serial_nand_pins: serial-nand-pins { -- mux { -- function = "flash"; -- groups = "snfi"; -- }; -- }; -- -- spic0_pins: spic0-pins { -- mux { -- function = "spi"; -- groups = "spic0_0"; -- }; -- }; -- -- spic1_pins: spic1-pins { -- mux { -- function = "spi"; -- groups = "spic1_0"; -- }; -- }; -- -- /* SPI-NOR is shared pin with serial NAND */ -- spi_nor_pins: spi-nor-pins { -- mux { -- function = "flash"; -- groups = "spi_nor"; -- }; -- }; -- -- /* serial NAND is shared pin with SPI-NOR */ -- serial_nand_pins: serial-nand-pins { -- mux { -- function = "flash"; -- groups = "snfi"; -- }; -- }; -- -- uart0_pins: uart0-pins { -- mux { -- function = "uart"; -- groups = "uart0_0_tx_rx" ; -- }; -- }; -- -- uart2_pins: uart2-pins { -- mux { -- function = "uart"; -- groups = "uart2_1_tx_rx" ; -- }; -- }; -- -- watchdog_pins: watchdog-pins { -- mux { -- function = "watchdog"; -- groups = "watchdog"; -- }; -- }; --}; -- --&pwm { -- pinctrl-names = "default"; -- pinctrl-0 = <&pwm7_pins>; -- status = "okay"; --}; -- --&pwrap { -- pinctrl-names = "default"; -- pinctrl-0 = <&pmic_bus_pins>; -- -- status = "okay"; --}; -- --&sata { -- status = "disable"; --}; -- --&sata_phy { -- status = "disable"; --}; -- --&snfi { -- pinctrl-names = "default"; -- pinctrl-0 = <&serial_nand_pins>; -- status = "okay"; -- -- spi_nand@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "spi-nand"; -- spi-max-frequency = <104000000>; -- reg = <0>; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "Preloader"; -- reg = <0x00000 0x0080000>; -- read-only; -- }; -- -- partition@80000 { -- label = "ATF"; -- reg = <0x80000 0x0040000>; -- }; -- -- partition@c0000 { -- label = "Bootloader"; -- reg = <0xc0000 0x0080000>; -- }; -- -- partition@140000 { -- label = "Config"; -- reg = <0x140000 0x0080000>; -- }; -- -- factory: partition@1c0000 { -- label = "Factory"; -- reg = <0x1c0000 0x0040000>; -- }; -- -- partition@200000 { -- label = "kernel"; -- reg = <0x200000 0x400000>; -- }; -- -- partition@600000 { -- label = "ubi"; -- reg = <0x600000 0x1C00000>; -- }; -- -- partition@2200000 { -- label = "User_data"; -- reg = <0x2200000 0x4000000>; -- }; -- }; -- }; --}; -- --&spi0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spic0_pins>; -- status = "okay"; --}; -- --&spi1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spic1_pins>; -- status = "okay"; --}; -- --&ssusb { -- vusb33-supply = <®_3p3v>; -- vbus-supply = <®_5v>; -- status = "okay"; --}; -- --&u3phy { -- status = "okay"; --}; -- --&uart0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart0_pins>; -- status = "okay"; --}; -- --&uart2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart2_pins>; -- status = "okay"; --}; -- --&watchdog { -- pinctrl-names = "default"; -- pinctrl-0 = <&watchdog_pins>; -- status = "okay"; --}; -- --&wmac { -- mediatek,mtd-eeprom = <&factory 0x0000>; -- status = "okay"; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-ubnt-unifi-6-lr.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-ubnt-unifi-6-lr.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-ubnt-unifi-6-lr.dts 2023-02-26 09:01:19.879971900 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-ubnt-unifi-6-lr.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,327 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -- --/dts-v1/; --#include --#include --#include -- --#include "mt7622.dtsi" --#include "mt6380.dtsi" -- --/ { -- model = "Ubiquiti UniFi 6 LR"; -- compatible = "ubnt,unifi-6-lr", "mediatek,mt7622"; -- -- aliases { -- led-boot = &led_blue; -- led-failsafe = &led_blue; -- led-running = &led_blue; -- led-upgrade = &led_blue; -- label-mac-device = &gmac0; -- serial0 = &uart0; -- }; -- -- chosen { -- stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8"; -- }; -- -- cpus { -- cpu@0 { -- proc-supply = <&mt6380_vcpu_reg>; -- sram-supply = <&mt6380_vm_reg>; -- }; -- -- cpu@1 { -- proc-supply = <&mt6380_vcpu_reg>; -- sram-supply = <&mt6380_vm_reg>; -- }; -- }; -- -- gpio-keys { -- compatible = "gpio-keys"; -- -- reset { -- label = "reset"; -- linux,code = ; -- gpios = <&pio 62 GPIO_ACTIVE_LOW>; -- }; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x3f000000>; -- }; -- -- reg_1p8v: regulator-1p8v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-1.8V"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-always-on; -- }; -- -- reg_3p3v: regulator-3p3v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-3.3V"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-boot-on; -- regulator-always-on; -- }; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&slot0 { -- wifi@0,0 { -- reg = <0x0 0 0 0 0>; -- mediatek,mtd-eeprom = <&factory 0x20000>; -- mtd-mac-address = <&eeprom 0x6>; -- ieee80211-freq-limit = <5000000 6000000>; -- }; --}; -- --&pio { -- eth_pins: eth-pins { -- mux { -- function = "eth"; -- groups = "mdc_mdio", "rgmii_via_gmac2"; -- }; -- }; -- -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie0_pad_perst", -- "pcie0_1_waken", -- "pcie0_1_clkreq"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie1_pad_perst", -- "pcie1_0_waken", -- "pcie1_0_clkreq"; -- }; -- }; -- -- pmic_bus_pins: pmic-bus-pins { -- mux { -- function = "pmic"; -- groups = "pmic_bus"; -- }; -- }; -- -- spi_nor_pins: spi-nor-pins { -- mux { -- function = "flash"; -- groups = "spi_nor"; -- }; -- }; -- -- uart0_pins: uart0-pins { -- mux { -- function = "uart"; -- groups = "uart0_0_tx_rx" ; -- }; -- }; -- -- uart3_pins: uart3-pins { -- mux { -- function = "uart"; -- groups = "uart3_1_tx_rx" ; -- }; -- }; -- -- i2c0_pins: i2c0-pins { -- mux { -- function = "i2c"; -- groups = "i2c0"; -- }; -- }; -- -- watchdog_pins: watchdog-pins { -- mux { -- function = "watchdog"; -- groups = "watchdog"; -- }; -- }; --}; -- --&bch { -- status = "okay"; --}; -- --&btif { -- status = "disabled"; --}; -- --ð { -- status = "okay"; -- pinctrl-names = "default"; -- pinctrl-0 = <ð_pins>; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- -- phy-mode = "2500base-x"; -- mtd-mac-address = <&eeprom 0x0>; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- }; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- -- ethernet-phy@8 { -- /* Marvell AQRate AQR112W - no driver */ -- compatible = "ethernet-phy-ieee802.3-c45"; -- reg = <0x8>; -- }; -- }; --}; -- --&pwrap { -- pinctrl-names = "default"; -- pinctrl-0 = <&pmic_bus_pins>; -- -- status = "okay"; --}; -- --&nor_flash { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi_nor_pins>; -- -- status = "okay"; -- -- flash@0 { -- compatible = "jedec,spi-nor"; -- reg = <0>; -- spi-max-frequency = <50000000>; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "preloader"; -- reg = <0x0 0x40000>; -- read-only; -- }; -- -- partition@40000 { -- label = "atf"; -- reg = <0x40000 0x20000>; -- read-only; -- }; -- -- partition@60000 { -- label = "u-boot"; -- reg = <0x60000 0x60000>; -- read-only; -- }; -- -- partition@c0000 { -- label = "u-boot-env"; -- reg = <0xc0000 0x10000>; -- }; -- -- factory: partition@d0000 { -- label = "factory"; -- reg = <0xd0000 0x40000>; -- read-only; -- }; -- -- eeprom: partition@110000 { -- label = "eeprom"; -- reg = <0x110000 0x10000>; -- read-only; -- }; -- -- partition@120000 { -- label = "bs"; -- reg = <0x120000 0x10000>; -- }; -- -- partition@130000 { -- label = "cfg"; -- reg = <0x130000 0x100000>; -- read-only; -- }; -- -- partition@230000 { -- compatible = "denx,fit"; -- label = "firmware"; -- reg = <0x230000 0x1ee0000>; -- }; -- -- partition@2110000 { -- label = "kernel1"; -- reg = <0x2110000 0x1ee0000>; -- }; -- }; -- }; --}; -- --&uart0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart0_pins>; -- status = "okay"; --}; -- --&uart3 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart3_pins>; -- status = "okay"; -- -- /* MT7915 Bluetooth */ --}; -- --&i2c0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c0_pins>; -- status = "okay"; -- -- led-controller@30 { -- compatible = "ubnt,ledbar"; -- reg = <0x30>; -- -- enable-gpio = <&pio 59 0>; -- -- red { -- label = "red"; -- }; -- -- green { -- label = "green"; -- }; -- -- led_blue: blue { -- label = "blue"; -- }; -- }; --}; -- --&watchdog { -- pinctrl-names = "default"; -- pinctrl-0 = <&watchdog_pins>; -- status = "okay"; --}; -- --&wmac { -- mediatek,mtd-eeprom = <&factory 0x0>; -- mtd-mac-address = <&eeprom 0x0>; -- status = "okay"; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi 2023-02-26 09:01:19.889971600 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi 2023-02-26 09:22:13.529444900 +0800 -@@ -140,12 +140,6 @@ - #size-cells = <2>; - ranges; - -- ramoops@42ff0000 { -- compatible = "ramoops"; -- reg = <0 0x42ff0000 0 0x10000>; -- record-size = <0x1000>; -- }; -- - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts 2023-02-26 09:01:19.881972500 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,70 +0,0 @@ --/dts-v1/; --#include "mt7981-360-t7-base.dtsi" -- --/ { -- nmbm_spim_nand { -- compatible = "generic,nmbm"; -- -- #address-cells = <1>; -- #size-cells = <1>; -- -- lower-mtd-device = <&spi_nand>; -- forced-create; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "BL2"; -- reg = <0x00 0x100000>; -- }; -- -- partition@100000 { -- label = "u-boot-env"; -- reg = <0x100000 0x80000>; -- }; -- -- partition@180000 { -- label = "Factory"; -- reg = <0x180000 0x200000>; -- }; -- -- partition@380000 { -- label = "FIP"; -- reg = <0x380000 0x200000>; -- }; -- -- partition@580000 { -- label = "ubi"; -- reg = <0x580000 0x2400000>; -- }; -- -- partition@2980000 { -- label = "firmware-1"; -- reg = <0x2980000 0x2400000>; -- }; -- -- partition@4D80000 { -- label = "plugin"; -- reg = <0x4d80000 0x2400000>; -- }; -- -- partition@7180000 { -- label = "stock-config"; -- reg = <0x7180000 0x100000>; -- }; -- -- partition@7280000 { -- label = "stock-factory"; -- reg = <0x7280000 0x80000>; -- }; -- -- partition@7300000 { -- label = "stock-log"; -- reg = <0x7300000 0x400000>; -- }; -- }; -- }; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts 2023-02-26 09:01:19.881069000 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,60 +0,0 @@ --/dts-v1/; --#include "mt7981-360-t7-base.dtsi" -- --/ { -- nmbm_spim_nand { -- compatible = "generic,nmbm"; -- -- #address-cells = <1>; -- #size-cells = <1>; -- -- lower-mtd-device = <&spi_nand>; -- forced-create; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "BL2"; -- reg = <0x00 0x100000>; -- }; -- -- partition@100000 { -- label = "u-boot-env"; -- reg = <0x100000 0x80000>; -- }; -- -- partition@180000 { -- label = "Factory"; -- reg = <0x180000 0x200000>; -- }; -- -- partition@380000 { -- label = "FIP"; -- reg = <0x380000 0x200000>; -- }; -- -- partition@580000 { -- label = "ubi"; -- reg = <0x580000 0x6c00000>; -- }; -- -- partition@7180000 { -- label = "stock-config"; -- reg = <0x7180000 0x100000>; -- }; -- -- partition@7280000 { -- label = "stock-factory"; -- reg = <0x7280000 0x80000>; -- }; -- -- partition@7300000 { -- label = "stock-log"; -- reg = <0x7300000 0x400000>; -- }; -- }; -- }; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi 2023-02-26 09:01:19.881069000 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi 1970-01-01 08:00:00.000000000 +0800 -@@ -1,217 +0,0 @@ --/dts-v1/; --#include "mt7981.dtsi" -- --/ { -- model = "360 T7"; -- compatible = "360,t7", "mediatek,mt7981"; -- -- aliases { -- led-boot = &red_led; -- led-failsafe = &red_led; -- led-running = &green_led; -- led-upgrade = &green_led; -- }; -- -- chosen { -- bootargs = "console=ttyS0,115200n1 loglevel=8 \ -- earlycon=uart8250,mmio32,0x11002000"; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x10000000>; -- }; -- -- leds { -- compatible = "gpio-leds"; -- -- green_led: green { -- label = "360t7:green"; -- gpios = <&pio 7 GPIO_ACTIVE_LOW>; -- }; -- -- red_led: red { -- label = "360t7:red"; -- gpios = <&pio 3 GPIO_ACTIVE_LOW>; -- }; -- }; -- -- gpio-keys { -- compatible = "gpio-keys"; -- reset { -- label = "reset"; -- linux,code = ; -- gpios = <&pio 1 GPIO_ACTIVE_LOW>; -- }; -- -- wps { -- label = "wps"; -- linux,code = ; -- gpios = <&pio 0 GPIO_ACTIVE_LOW>; -- }; -- }; -- -- gsw: gsw@0 { -- compatible = "mediatek,mt753x"; -- mediatek,ethsys = <ðsys>; -- #address-cells = <1>; -- #size-cells = <0>; -- }; --}; -- --&uart0 { -- status = "okay"; --}; -- --&watchdog { -- status = "okay"; --}; -- --ð { -- status = "okay"; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "2500base-x"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "2500base-x"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- }; --}; -- --&gsw { -- mediatek,mdio = <&mdio>; -- mediatek,mdio_master_pinmux = <0>; -- reset-gpios = <&pio 39 0>; -- interrupt-parent = <&pio>; -- interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; -- status = "okay"; -- -- port5: port@5 { -- compatible = "mediatek,mt753x-port"; -- reg = <5>; -- phy-mode = "sgmii"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- }; -- }; -- -- port6: port@6 { -- compatible = "mediatek,mt753x-port"; -- mediatek,ssc-on; -- reg = <6>; -- phy-mode = "sgmii"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- }; -- }; --}; -- --&hnat { -- mtketh-wan = "eth1"; -- mtketh-lan = "eth0"; -- mtketh-max-gmac = <2>; -- status = "okay"; --}; -- --&spi0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi0_flash_pins>; -- status = "okay"; -- -- spi_nand: spi_nand@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "spi-nand"; -- reg = <0>; -- spi-max-frequency = <52000000>; -- spi-tx-buswidth = <4>; -- spi-rx-buswidth = <4>; -- spi-cal-enable; -- spi-cal-mode = "read-data"; -- spi-cal-datalen = <7>; -- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; /* 'SPINAND' */ -- spi-cal-addrlen = <5>; -- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; -- }; --}; -- --&pio { -- pwm0_pin: pwm0-pin-g0 { -- mux { -- function = "pwm"; -- groups = "pwm0_0"; -- }; -- }; -- -- pwm1_pin: pwm1-pin-g0 { -- mux { -- function = "pwm"; -- groups = "pwm1_0"; -- }; -- }; -- -- pwm2_pin: pwm2-pin { -- mux { -- function = "pwm"; -- groups = "pwm2"; -- }; -- }; -- -- spi0_flash_pins: spi0-pins { -- mux { -- function = "spi"; -- groups = "spi0", "spi0_wp_hold"; -- }; -- -- conf-pu { -- pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; -- drive-strength = ; -- bias-pull-up = ; -- }; -- -- conf-pd { -- pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; -- drive-strength = ; -- bias-pull-down = ; -- }; -- }; -- -- uart1_pins: uart1-pins-g1 { -- mux { -- function = "uart"; -- groups = "uart1_1"; -- }; -- }; -- -- uart2_pins: uart2-pins-g1 { -- mux { -- function = "uart"; -- groups = "uart2_1"; -- }; -- }; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi 2023-02-26 09:01:19.900973100 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi 2023-02-26 09:22:13.650749300 +0800 -@@ -124,12 +124,6 @@ - #size-cells = <2>; - ranges; - -- ramoops@42ff0000 { -- compatible = "ramoops"; -- reg = <0 0x42ff0000 0 0x10000>; -- record-size = <0x1000>; -- }; -- - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-emmc-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-emmc-rfb.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-emmc-rfb.dts 2023-02-26 09:01:19.893973500 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-emmc-rfb.dts 2023-02-26 09:22:13.585278500 +0800 -@@ -68,7 +68,7 @@ - &uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -- status = "okay"; -+ status = "disabled"; - }; - - &i2c0 { -@@ -102,6 +102,9 @@ - speed = <2500>; - full-duplex; - pause; -+ link-gpio = <&pio 47 0>; -+ phy-handle = <&phy5>; -+ label = "lan5"; - }; - }; - -@@ -109,7 +112,14 @@ - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; -- phy-handle = <&phy6>; +diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts +new file mode 100644 +index 0000000000..3be72d2960 +--- /dev/null ++++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts +@@ -0,0 +1,60 @@ ++/dts-v1/; ++#include "mt7981-360-t7-base.dtsi" ++ ++/ { ++ nmbm_spim_nand { ++ compatible = "generic,nmbm"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ lower-mtd-device = <&spi_nand>; ++ forced-create; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x00 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "FIP"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x6c00000>; ++ }; ++ ++ partition@7180000 { ++ label = "stock-config"; ++ reg = <0x7180000 0x100000>; ++ }; ++ ++ partition@7280000 { ++ label = "stock-factory"; ++ reg = <0x7280000 0x80000>; ++ }; ++ ++ partition@7300000 { ++ label = "stock-log"; ++ reg = <0x7300000 0x400000>; ++ }; ++ }; ++ }; ++}; +diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi +new file mode 100644 +index 0000000000..54be7d2ad4 +--- /dev/null ++++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi +@@ -0,0 +1,217 @@ ++/dts-v1/; ++#include "mt7981.dtsi" ++ ++/ { ++ model = "360 T7"; ++ compatible = "360,t7", "mediatek,mt7981"; ++ ++ aliases { ++ led-boot = &red_led; ++ led-failsafe = &red_led; ++ led-running = &green_led; ++ led-upgrade = &green_led; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n1 loglevel=8 \ ++ earlycon=uart8250,mmio32,0x11002000"; ++ }; ++ ++ memory { ++ reg = <0 0x40000000 0 0x10000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ green_led: green { ++ label = "360t7:green"; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ red_led: red { ++ label = "360t7:red"; ++ gpios = <&pio 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ reset { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "wps"; ++ linux,code = ; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gsw: gsw@0 { ++ compatible = "mediatek,mt753x"; ++ mediatek,ethsys = <ðsys>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ ++ gmac0: mac@0 { ++ compatible = "mediatek,eth-mac"; ++ reg = <0>; ++ phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; -+ link-gpio = <&pio 46 0>; -+ phy-handle = <&phy6>; + }; - }; - - mdio: mdio-bus { -@@ -120,12 +130,12 @@ - reset-delay-us = <600>; - - phy5: phy@5 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - }; - - phy6: phy@6 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - -@@ -167,7 +177,12 @@ - reg = <5>; - label = "lan5"; - phy-mode = "2500base-x"; -- phy-handle = <&phy5>; ++ }; + -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; - }; - - port@6 { -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-gsw-spim-nand-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-gsw-spim-nand-rfb.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-gsw-spim-nand-rfb.dts 2023-02-26 09:01:19.893973500 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-gsw-spim-nand-rfb.dts 2023-02-26 09:22:13.590311200 +0800 -@@ -101,7 +101,14 @@ - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; -- phy-handle = <&phy6>; ++ gmac1: mac@1 { ++ compatible = "mediatek,eth-mac"; ++ reg = <1>; ++ phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; -+ link-gpio = <&pio 46 0>; -+ phy-handle = <&phy6>; + }; - }; - - mdio: mdio-bus { -@@ -117,7 +124,7 @@ - }; - - phy6: phy@6 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - }; -@@ -141,6 +148,7 @@ - speed = <2500>; - full-duplex; - }; ++ }; + - }; - - port6: port@6 { -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-sd-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-sd-rfb.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-sd-rfb.dts 2023-02-26 09:01:19.894972800 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-sd-rfb.dts 2023-02-26 09:22:13.595335800 +0800 -@@ -59,7 +59,7 @@ - &uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -- status = "okay"; -+ status = "disabled"; - }; - - &i2c0 { -@@ -93,6 +93,9 @@ - speed = <2500>; - full-duplex; - pause; -+ link-gpio = <&pio 47 0>; -+ phy-handle = <&phy5>; -+ label = "lan5"; - }; - }; - -@@ -100,7 +103,14 @@ - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; -- phy-handle = <&phy6>; ++ mdio: mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++}; ++ ++&gsw { ++ mediatek,mdio = <&mdio>; ++ mediatek,mdio_master_pinmux = <0>; ++ reset-gpios = <&pio 39 0>; ++ interrupt-parent = <&pio>; ++ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; ++ status = "okay"; ++ ++ port5: port@5 { ++ compatible = "mediatek,mt753x-port"; ++ reg = <5>; ++ phy-mode = "sgmii"; + + fixed-link { + speed = <2500>; + full-duplex; -+ pause; -+ link-gpio = <&pio 46 0>; -+ phy-handle = <&phy6>; + }; - }; - - mdio: mdio-bus { -@@ -111,12 +121,12 @@ - reset-delay-us = <600>; - - phy5: phy@5 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - }; - - phy6: phy@6 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - -@@ -158,7 +168,12 @@ - reg = <5>; - label = "lan5"; - phy-mode = "2500base-x"; -- phy-handle = <&phy5>; ++ }; + -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; - }; - - port@6 { -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nand-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nand-rfb.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nand-rfb.dts 2023-02-26 09:01:19.894972800 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nand-rfb.dts 2023-02-26 09:22:13.604310900 +0800 -@@ -50,7 +50,7 @@ - &uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -- status = "okay"; -+ status = "disabled"; - }; - - &i2c0 { -@@ -84,6 +84,9 @@ - speed = <2500>; - full-duplex; - pause; -+ link-gpio = <&pio 47 0>; -+ phy-handle = <&phy5>; -+ label = "lan5"; - }; - }; - -@@ -91,7 +94,14 @@ - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; -- phy-handle = <&phy6>; ++ port6: port@6 { ++ compatible = "mediatek,mt753x-port"; ++ mediatek,ssc-on; ++ reg = <6>; ++ phy-mode = "sgmii"; + + fixed-link { + speed = <2500>; + full-duplex; -+ pause; -+ link-gpio = <&pio 46 0>; -+ phy-handle = <&phy6>; + }; - }; - - mdio: mdio-bus { -@@ -102,12 +112,12 @@ - reset-delay-us = <600>; - - phy5: phy@5 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - }; - - phy6: phy@6 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - -@@ -149,7 +159,12 @@ - reg = <5>; - label = "lan5"; - phy-mode = "2500base-x"; -- phy-handle = <&phy5>; ++ }; ++}; + -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; - }; - - port@6 { -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nor-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nor-rfb.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nor-rfb.dts 2023-02-26 09:01:19.895973300 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-spim-nor-rfb.dts 2023-02-26 09:22:13.609018800 +0800 -@@ -84,6 +84,9 @@ - speed = <2500>; - full-duplex; - pause; -+ link-gpio = <&pio 47 0>; -+ phy-handle = <&phy5>; -+ label = "lan5"; - }; - }; - -@@ -91,7 +94,14 @@ - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; -- phy-handle = <&phy6>; ++&hnat { ++ mtketh-wan = "eth1"; ++ mtketh-lan = "eth0"; ++ mtketh-max-gmac = <2>; ++ status = "okay"; ++}; + -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ link-gpio = <&pio 46 0>; -+ phy-handle = <&phy6>; ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_flash_pins>; ++ status = "okay"; ++ ++ spi_nand: spi_nand@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ spi-tx-buswidth = <4>; ++ spi-rx-buswidth = <4>; ++ spi-cal-enable; ++ spi-cal-mode = "read-data"; ++ spi-cal-datalen = <7>; ++ spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; /* 'SPINAND' */ ++ spi-cal-addrlen = <5>; ++ spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; ++ }; ++}; ++ ++&pio { ++ pwm0_pin: pwm0-pin-g0 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_0"; + }; - }; - - mdio: mdio-bus { -@@ -102,12 +112,12 @@ - reset-delay-us = <600>; - - phy5: phy@5 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - }; - - phy6: phy@6 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - -@@ -149,7 +159,12 @@ - reg = <5>; - label = "lan5"; - phy-mode = "2500base-x"; -- phy-handle = <&phy5>; ++ }; + -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; - }; - - port@6 { -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dts 2023-02-26 09:01:19.899973100 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,61 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) -- --/dts-v1/; --#include "mt7986a-xiaomi-redmi-router-ax6000.dtsi" -- --/ { -- nmbm_spim_nand { -- compatible = "generic,nmbm"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- lower-mtd-device = <&spi_nand>; -- forced-create; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <0x01>; -- #size-cells = <0x01>; -- -- partition@0 { -- label = "BL2"; -- reg = <0x00 0x100000>; -- }; -- -- partition@100000 { -- label = "Nvram"; -- reg = <0x100000 0x40000>; -- }; -- -- partition@140000 { -- label = "Bdata"; -- reg = <0x140000 0x40000>; -- }; -- -- partition@180000 { -- label = "Factory"; -- reg = <0x180000 0x200000>; -- }; -- -- partition@380000 { -- label = "FIP"; -- reg = <0x380000 0x200000>; -- }; -- -- partition@580000 { -- label = "crash"; -- reg = <0x580000 0x40000>; -- }; -- -- partition@5c0000 { -- label = "crash_log"; -- reg = <0x5c0000 0x40000>; -- }; -- -- partition@600000 { -- label = "ubi"; -- reg = <0x600000 0x6e00000>; -- }; -- }; -- }; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dtsi openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dtsi ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dtsi 2023-02-26 09:01:19.899973100 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000.dtsi 1970-01-01 08:00:00.000000000 +0800 -@@ -1,244 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) -- --/dts-v1/; --#include --#include --#include -- --#include "mt7986a.dtsi" --#include "mt7986a-pinctrl.dtsi" -- --/ { -- model = "Xiaomi Redmi Router AX6000"; -- compatible = "xiaomi,redmi-router-ax6000", "mediatek,mt7986a"; -- -- aliases { -- led-boot = &led_status_rgb; -- led-failsafe = &led_status_rgb; -- led-running = &led_status_rgb; -- led-upgrade = &led_status_rgb; -- }; -- -- chosen { -- bootargs = "console=ttyS0,115200n1 loglevel=8 earlycon=uart8250,mmio32,0x11002000"; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x10000000>; -- }; -- -- gsw: gsw@0 { -- compatible = "mediatek,mt753x"; -- mediatek,ethsys = <ðsys>; -- #address-cells = <1>; -- #size-cells = <0>; -- }; -- -- keys { -- compatible = "gpio-keys"; -- -- reset { -- label = "reset"; -- gpios = <&pio 9 GPIO_ACTIVE_LOW>; -- linux,code = ; -- }; -- -- mesh { -- label = "mesh"; -- gpios = <&pio 10 GPIO_ACTIVE_LOW>; -- linux,code = ; -- linux,input-type = ; -- }; -- }; --}; -- --&uart0 { -- status = "okay"; --}; -- --&watchdog { -- status = "okay"; --}; -- --ð { -- status = "okay"; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "2500base-x"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "2500base-x"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- }; --}; -- --&gsw { -- mediatek,mdio = <&mdio>; -- mediatek,mdio_master_pinmux = <0>; -- reset-gpios = <&pio 5 0>; -- interrupt-parent = <&pio>; -- interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; -- status = "okay"; -- -- port5: port@5 { -- compatible = "mediatek,mt753x-port"; -- reg = <5>; -- phy-mode = "sgmii"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- }; -- }; -- -- port6: port@6 { -- compatible = "mediatek,mt753x-port"; -- mediatek,ssc-on; -- reg = <6>; -- phy-mode = "sgmii"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- }; -- }; --}; -- --&hnat { -- mtketh-wan = "eth1"; -- mtketh-lan = "eth0"; -- mtketh-max-gmac = <2>; -- status = "okay"; --}; -- --&spi0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi_flash_pins>; -- cs-gpios = <0>, <0>; -- status = "okay"; -- -- spi_nand: spi_nand@1 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "spi-nand"; -- reg = <1>; -- spi-max-frequency = <52000000>; -- spi-tx-buswidth = <4>; -- spi-rx-buswidth = <4>; -- spi-cal-enable; -- spi-cal-mode = "read-data"; -- spi-cal-datalen = <7>; -- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; /* 'SPINAND' */ -- spi-cal-addrlen = <5>; -- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; -- }; --}; -- --&spi1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spic_pins_g2>; -- status = "okay"; -- -- ws2812b@0 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "worldsemi,ws2812b"; -- reg = <0>; -- spi-max-frequency = <3000000>; -- -- led_status_rgb: led@0 { -- reg = <0>; -- label = "rgb:status"; -- color-index = ; -- color-intensity = <0 255 0>; /* GREEN */ -- }; -- -- led_network_rgb: led@1 { -- reg = <1>; -- label = "rgb:network"; -- color-index = ; -- color-intensity = <0 0 255>; /* BLUE */ -- }; -- }; --}; -- --&wbsys { -- status = "okay"; -- pinctrl-names = "default", "dbdc"; -- pinctrl-0 = <&wf_2g_5g_pins>; -- pinctrl-1 = <&wf_dbdc_pins>; --}; -- --&pio { -- spi_flash_pins: spi-flash-pins-33-to-38 { -- mux { -- function = "flash"; -- groups = "spi0", "spi0_wp_hold"; -- }; -- conf-pu { -- pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; -- drive-strength = <8>; -- mediatek,pull-up-adv = <0>; -- }; -- conf-pd { -- pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; -- drive-strength = <8>; -- mediatek,pull-down-adv = <0>; -- }; -- }; -- -- wf_2g_5g_pins: wf_2g_5g-pins { -- mux { -- function = "wifi"; -- groups = "wf_2g", "wf_5g"; -- }; -- conf { -- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -- "WF1_TOP_CLK", "WF1_TOP_DATA"; -- drive-strength = ; -- }; -- }; -- -- wf_dbdc_pins: wf_dbdc-pins { -- mux { -- function = "wifi"; -- groups = "wf_dbdc"; -- }; -- conf { -- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -- "WF1_TOP_CLK", "WF1_TOP_DATA"; -- drive-strength = ; -- }; -- }; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000-stock.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000-stock.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000-stock.dts 2023-02-26 09:01:19.898973300 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-xiaomi-redmi-router-ax6000-stock.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,69 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) -- --/dts-v1/; --#include "mt7986a-xiaomi-redmi-router-ax6000.dtsi" -- --/ { -- model = "Xiaomi Redmi Router AX6000 (stock layout)"; -- compatible = "xiaomi,redmi-router-ax6000-stock", "mediatek,mt7986a"; -- -- nmbm_spim_nand { -- compatible = "generic,nmbm"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- lower-mtd-device = <&spi_nand>; -- forced-create; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <0x01>; -- #size-cells = <0x01>; -- -- partition@0 { -- label = "BL2"; -- reg = <0x00 0x100000>; -- }; -- -- partition@100000 { -- label = "Nvram"; -- reg = <0x100000 0x40000>; -- }; -- -- partition@140000 { -- label = "Bdata"; -- reg = <0x140000 0x40000>; -- }; -- -- partition@180000 { -- label = "Factory"; -- reg = <0x180000 0x200000>; -- }; -- -- partition@380000 { -- label = "FIP"; -- reg = <0x380000 0x200000>; -- }; -- -- partition@580000 { -- label = "crash"; -- reg = <0x580000 0x40000>; -- }; -- -- partition@5c0000 { -- label = "crash_log"; -- reg = <0x5c0000 0x40000>; -- }; -- -- partition@600000 { -- label = "ubi_kernel"; -- reg = <0x600000 0x1e00000>; -- }; -- -- partition@2400000 { -- label = "ubi"; -- reg = <0x2400000 0x5000000>; -- }; -- }; -- }; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-emmc-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-emmc-rfb.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-emmc-rfb.dts 2023-02-26 09:01:19.900973100 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-emmc-rfb.dts 2023-02-26 09:22:13.661752900 +0800 -@@ -64,6 +64,9 @@ - speed = <2500>; - full-duplex; - pause; -+ link-gpio = <&pio 47 0>; -+ phy-handle = <&phy5>; -+ label = "lan5"; - }; - }; - -@@ -71,7 +74,14 @@ - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; -- phy-handle = <&phy6>; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ link-gpio = <&pio 46 0>; -+ phy-handle = <&phy6>; ++ pwm1_pin: pwm1-pin-g0 { ++ mux { ++ function = "pwm"; ++ groups = "pwm1_0"; + }; - }; - - mdio: mdio-bus { -@@ -82,12 +92,12 @@ - reset-delay-us = <600>; - - phy5: phy@5 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - }; - - phy6: phy@6 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - -@@ -129,7 +139,12 @@ - reg = <5>; - label = "lan5"; - phy-mode = "2500base-x"; -- phy-handle = <&phy5>; ++ }; + -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; - }; - - port@6 { -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-gsw-spim-nand-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-gsw-spim-nand-rfb.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-gsw-spim-nand-rfb.dts 2023-02-26 09:01:19.901972100 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-gsw-spim-nand-rfb.dts 2023-02-26 09:22:13.670785000 +0800 -@@ -72,7 +72,14 @@ - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; -- phy-handle = <&phy6>; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ link-gpio = <&pio 46 0>; -+ phy-handle = <&phy6>; ++ pwm2_pin: pwm2-pin { ++ mux { ++ function = "pwm"; ++ groups = "pwm2"; + }; - }; - - mdio: mdio-bus { -@@ -88,7 +95,7 @@ - }; - - phy6: phy@6 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - }; -@@ -112,6 +119,7 @@ - speed = <2500>; - full-duplex; - }; ++ }; + - }; - - port6: port@6 { -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-sd-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-sd-rfb.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-sd-rfb.dts 2023-02-26 09:01:19.901972100 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-sd-rfb.dts 2023-02-26 09:22:13.676750700 +0800 -@@ -64,6 +64,9 @@ - speed = <2500>; - full-duplex; - pause; -+ link-gpio = <&pio 47 0>; -+ phy-handle = <&phy5>; -+ label = "lan5"; - }; - }; - -@@ -71,7 +74,14 @@ - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; -- phy-handle = <&phy6>; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ link-gpio = <&pio 46 0>; -+ phy-handle = <&phy6>; ++ spi0_flash_pins: spi0-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; + }; - }; - - mdio: mdio-bus { -@@ -82,12 +92,12 @@ - reset-delay-us = <600>; - - phy5: phy@5 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - }; - - phy6: phy@6 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - -@@ -129,7 +139,12 @@ - reg = <5>; - label = "lan5"; - phy-mode = "2500base-x"; -- phy-handle = <&phy5>; + -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; - }; - - port@6 { -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-snfi-nand-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-snfi-nand-rfb.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-snfi-nand-rfb.dts 2023-02-26 09:01:19.902972900 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-snfi-nand-rfb.dts 2023-02-26 09:22:13.681750700 +0800 -@@ -55,6 +55,9 @@ - speed = <2500>; - full-duplex; - pause; -+ link-gpio = <&pio 47 0>; -+ phy-handle = <&phy5>; -+ label = "lan5"; - }; - }; - -@@ -62,7 +65,14 @@ - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; -- phy-handle = <&phy6>; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ link-gpio = <&pio 46 0>; -+ phy-handle = <&phy6>; ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = ; ++ bias-pull-up = ; + }; - }; - - mdio: mdio-bus { -@@ -73,12 +83,12 @@ - reset-delay-us = <600>; - - phy5: phy@5 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - }; - - phy6: phy@6 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - -@@ -120,7 +130,12 @@ - reg = <5>; - label = "lan5"; - phy-mode = "2500base-x"; -- phy-handle = <&phy5>; + -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; - }; - - port@6 { -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nand-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nand-rfb.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nand-rfb.dts 2023-02-26 09:01:19.903971500 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nand-rfb.dts 2023-02-26 09:22:13.689750600 +0800 -@@ -55,6 +55,9 @@ - speed = <2500>; - full-duplex; - pause; -+ link-gpio = <&pio 47 0>; -+ phy-handle = <&phy5>; -+ label = "lan5"; - }; - }; - -@@ -62,7 +65,14 @@ - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; -- phy-handle = <&phy6>; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ link-gpio = <&pio 46 0>; -+ phy-handle = <&phy6>; ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = ; ++ bias-pull-down = ; + }; - }; - - mdio: mdio-bus { -@@ -73,12 +83,12 @@ - reset-delay-us = <600>; - - phy5: phy@5 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - }; - - phy6: phy@6 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - -@@ -120,7 +130,12 @@ - reg = <5>; - label = "lan5"; - phy-mode = "2500base-x"; -- phy-handle = <&phy5>; ++ }; + -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; - }; - - port@6 { -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nor-rfb.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nor-rfb.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nor-rfb.dts 2023-02-26 09:01:19.903971500 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-spim-nor-rfb.dts 2023-02-26 09:22:13.694751600 +0800 -@@ -55,6 +55,9 @@ - speed = <2500>; - full-duplex; - pause; -+ link-gpio = <&pio 47 0>; -+ phy-handle = <&phy5>; -+ label = "lan5"; - }; - }; - -@@ -62,7 +65,14 @@ - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; -- phy-handle = <&phy6>; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ link-gpio = <&pio 46 0>; -+ phy-handle = <&phy6>; ++ uart1_pins: uart1-pins-g1 { ++ mux { ++ function = "uart"; ++ groups = "uart1_1"; + }; - }; - - mdio: mdio-bus { -@@ -73,12 +83,12 @@ - reset-delay-us = <600>; - - phy5: phy@5 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - }; - - phy6: phy@6 { -- compatible = "ethernet-phy-ieee802.3-c45"; -+ compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - -@@ -120,7 +130,12 @@ - reg = <5>; - label = "lan5"; - phy-mode = "2500base-x"; -- phy-handle = <&phy5>; ++ }; + -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; - }; - - port@6 { -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi 2023-02-26 09:01:19.907972100 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi 1970-01-01 08:00:00.000000000 +0800 -@@ -1,1096 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) --/* -- * Copyright (C) 2021 MediaTek Inc. -- * Author: Sam.Shih -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include --#include -- --/ { -- compatible = "mediatek,mt7988-rfb"; -- interrupt-parent = <&gic>; -- #address-cells = <2>; -- #size-cells = <2>; -- cpus { -- #address-cells = <1>; -- #size-cells = <0>; -- cpu@0 { -- device_type = "cpu"; -- compatible = "arm,cortex-a73"; -- enable-method = "psci"; -- reg = <0x0>; -- clocks = <&mcusys CK_MCU_ARM_DIV_SEL>, -- <&topckgen CK_TOP_CB_NET1_D4>, -- <&apmixedsys CK_APMIXED_ARM_B>, -- <&mcusys CK_MCU_BUS_DIV_SEL>, -- <&apmixedsys CK_APMIXED_CCIPLL2_B>; -- clock-names = "cpu", "intermediate", "armpll", "cci", -- "ccipll"; -- operating-points-v2 = <&cluster0_opp>; -- nvmem-cells = <&cpufreq_calibration>; -- nvmem-cell-names = "calibration-data"; -- }; -- -- cpu@1 { -- device_type = "cpu"; -- compatible = "arm,cortex-a73"; -- enable-method = "psci"; -- reg = <0x1>; -- clocks = <&mcusys CK_MCU_ARM_DIV_SEL>, -- <&topckgen CK_TOP_CB_NET1_D4>, -- <&apmixedsys CK_APMIXED_ARM_B>, -- <&mcusys CK_MCU_BUS_DIV_SEL>, -- <&apmixedsys CK_APMIXED_CCIPLL2_B>; -- clock-names = "cpu", "intermediate", "armpll", "cci", -- "ccipll"; -- operating-points-v2 = <&cluster0_opp>; -- nvmem-cells = <&cpufreq_calibration>; -- nvmem-cell-names = "calibration-data"; -- }; -- -- cpu@2 { -- device_type = "cpu"; -- compatible = "arm,cortex-a73"; -- enable-method = "psci"; -- reg = <0x2>; -- clocks = <&mcusys CK_MCU_ARM_DIV_SEL>, -- <&topckgen CK_TOP_CB_NET1_D4>, -- <&apmixedsys CK_APMIXED_ARM_B>, -- <&mcusys CK_MCU_BUS_DIV_SEL>, -- <&apmixedsys CK_APMIXED_CCIPLL2_B>; -- clock-names = "cpu", "intermediate", "armpll", "cci", -- "ccipll"; -- operating-points-v2 = <&cluster0_opp>; -- nvmem-cells = <&cpufreq_calibration>; -- nvmem-cell-names = "calibration-data"; -- }; -- -- cpu@3 { -- device_type = "cpu"; -- compatible = "arm,cortex-a73"; -- enable-method = "psci"; -- reg = <0x3>; -- clocks = <&mcusys CK_MCU_ARM_DIV_SEL>, -- <&topckgen CK_TOP_CB_NET1_D4>, -- <&apmixedsys CK_APMIXED_ARM_B>, -- <&mcusys CK_MCU_BUS_DIV_SEL>, -- <&apmixedsys CK_APMIXED_CCIPLL2_B>; -- clock-names = "cpu", "intermediate", "armpll", "cci", -- "ccipll"; -- operating-points-v2 = <&cluster0_opp>; -- nvmem-cells = <&cpufreq_calibration>; -- nvmem-cell-names = "calibration-data"; -- }; -- -- cluster0_opp: opp_table0 { -- compatible = "operating-points-v2"; -- opp-shared; -- opp00 { -- opp-hz = /bits/ 64 <800000000>; -- opp-microvolt = <850000>; -- }; -- opp01 { -- opp-hz = /bits/ 64 <1100000000>; -- opp-microvolt = <850000>; -- }; -- opp02 { -- opp-hz = /bits/ 64 <1500000000>; -- opp-microvolt = <850000>; -- }; -- opp03 { -- opp-hz = /bits/ 64 <1800000000>; -- opp-microvolt = <900000>; -- }; -- }; -- }; -- -- thermal-zones { -- cpu_thermal: cpu-thermal { -- polling-delay-passive = <1000>; -- polling-delay = <1000>; -- thermal-sensors = <&lvts 0>; -- trips { -- cpu_trip_crit: crit { -- temperature = <125000>; -- hysteresis = <2000>; -- type = "critical"; -- }; -- -- cpu_trip_hot: hot { -- temperature = <120000>; -- hysteresis = <2000>; -- type = "hot"; -- }; -- -- cpu_trip_active_high: active-high { -- temperature = <115000>; -- hysteresis = <2000>; -- type = "active"; -- }; -- -- cpu_trip_active_low: active-low { -- temperature = <85000>; -- hysteresis = <2000>; -- type = "active"; -- }; -- -- cpu_trip_passive: passive { -- temperature = <40000>; -- hysteresis = <2000>; -- type = "passive"; -- }; -- }; -- -- cooling-maps { -- cpu-active-high { -- /* active: set fan to cooling level 2 */ -- cooling-device = <&fan 2 2>; -- trip = <&cpu_trip_active_high>; -- }; -- -- cpu-active-low { -- /* active: set fan to cooling level 1 */ -- cooling-device = <&fan 1 1>; -- trip = <&cpu_trip_active_low>; -- }; -- -- cpu-passive { -- /* passive: set fan to cooling level 0 */ -- cooling-device = <&fan 0 0>; -- trip = <&cpu_trip_passive>; -- }; -- }; -- -- }; -- }; -- -- mmc0: mmc@11230000 { -- compatible = "mediatek,mt7986-mmc"; -- reg = <0 0x11230000 0 0x1000>, -- <0 0x11D60000 0 0x1000>; -- interrupts = ; -- clocks = <&infracfg_ao CK_INFRA_MSDC400>, -- <&infracfg_ao CK_INFRA_MSDC2_HCK>, -- <&infracfg_ao CK_INFRA_133M_MSDC_0_HCK>, -- <&infracfg_ao CK_INFRA_66M_MSDC_0_HCK>; -- clock-names = "source", "hclk", "ahb_cg", "axi_cg"; -- status = "disabled"; -- }; -- -- wed: wed@15010000 { -- compatible = "mediatek,wed"; -- wed_num = <3>; -- /* add this property for wed get the pci slot number. */ -- pci_slot_map = <0>, <1>, <2>; -- reg = <0 0x15010000 0 0x2000>, -- <0 0x15012000 0 0x2000>, -- <0 0x15014000 0 0x2000>; -- interrupt-parent = <&gic>; -- interrupts = , -- , -- ; -- }; -- -- wed2: wed2@15012000 { -- compatible = "mediatek,wed2"; -- wed_num = <3>; -- /* add this property for wed get the pci slot number. */ -- reg = <0 0x15010000 0 0x2000>, -- <0 0x15012000 0 0x2000>, -- <0 0x15014000 0 0x2000>; -- interrupt-parent = <&gic>; -- interrupts = , -- , -- ; -- }; -- -- wed3: wed3@15014000 { -- compatible = "mediatek,wed3"; -- wed_num = <3>; -- /* add this property for wed get the pci slot number. */ -- reg = <0 0x15010000 0 0x2000>, -- <0 0x15012000 0 0x2000>, -- <0 0x15014000 0 0x2000>; -- interrupt-parent = <&gic>; -- interrupts = , -- , -- ; -- }; -- -- wdma: wdma@15104800 { -- compatible = "mediatek,wed-wdma"; -- reg = <0 0x15104800 0 0x400>, -- <0 0x15104c00 0 0x400>, -- <0 0x15105000 0 0x400>; -- }; -- -- ap2woccif: ap2woccif@151A5000 { -- compatible = "mediatek,ap2woccif"; -- reg = <0 0x151A5000 0 0x1000>, -- <0 0x152A5000 0 0x1000>, -- <0 0x153A5000 0 0x1000>; -- interrupt-parent = <&gic>; -- interrupts = , -- , -- ; -- }; -- -- wocpu0_ilm: wocpu0_ilm@151E0000 { -- compatible = "mediatek,wocpu0_ilm"; -- reg = <0 0x151E0000 0 0x8000>; -- }; -- -- wocpu1_ilm: wocpu1_ilm@152E0000 { -- compatible = "mediatek,wocpu1_ilm"; -- reg = <0 0x152E0000 0 0x8000>; -- }; -- -- wocpu2_ilm: wocpu2_ilm@153E0000 { -- compatible = "mediatek,wocpu2_ilm"; -- reg = <0 0x153E0000 0 0x8000>; -- }; -- -- wocpu_dlm: wocpu_dlm@151E8000 { -- compatible = "mediatek,wocpu_dlm"; -- reg = <0 0x151E8000 0 0x2000>, -- <0 0x152E8000 0 0x2000>, -- <0 0x153E8000 0 0x2000>; -- -- resets = <ðsysrst 0>; -- reset-names = "wocpu_rst"; -- }; -- -- cpu_boot: wocpu_boot@15194000 { -- compatible = "mediatek,wocpu_boot"; -- reg = <0 0x15194000 0 0x1000>, -- <0 0x15294000 0 0x1000>, -- <0 0x15394000 0 0x1000>; -- }; -- -- reserved-memory { -- #address-cells = <2>; -- #size-cells = <2>; -- ranges; -- -- /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ -- secmon_reserved: secmon@43000000 { -- reg = <0 0x43000000 0 0x30000>; -- no-map; -- }; -- -- wmcpu_emi: wmcpu-reserved@47CC0000 { -- compatible = "mediatek,wmcpu-reserved"; -- no-map; -- reg = <0 0x47CC0000 0 0x00100000>; -- }; -- -- wocpu0_emi: wocpu0_emi@4F600000 { -- compatible = "mediatek,wocpu0_emi"; -- no-map; -- reg = <0 0x4F600000 0 0x40000>; -- shared = <0>; -- }; -- -- wocpu1_emi: wocpu1_emi@4F640000 { -- compatible = "mediatek,wocpu1_emi"; -- no-map; -- reg = <0 0x4F640000 0 0x40000>; -- shared = <0>; -- }; -- -- wocpu2_emi: wocpu2_emi@4F680000 { -- compatible = "mediatek,wocpu2_emi"; -- no-map; -- reg = <0 0x4F680000 0 0x40000>; -- shared = <0>; -- }; -- -- wocpu_data: wocpu_data@4F700000 { -- compatible = "mediatek,wocpu_data"; -- no-map; -- reg = <0 0x4F700000 0 0x800000>; -- shared = <1>; -- }; -- }; -- -- psci { -- compatible = "arm,psci-0.2"; -- method = "smc"; -- }; -- -- system_clk: dummy_system_clk { -- compatible = "fixed-clock"; -- clock-frequency = <40000000>; -- #clock-cells = <0>; -- }; -- -- uart_clk: dummy_uart_clk { -- compatible = "fixed-clock"; -- clock-frequency = <40000000>; -- #clock-cells = <0>; -- }; -- -- timer { -- compatible = "arm,armv8-timer"; -- interrupt-parent = <&gic>; -- interrupts = , -- , -- , -- ; -- -- }; -- -- tops: tops@09100000 { -- compatible = "mediatek,tops"; -- reg = <0 0x09100000 0 0x01000000>; -- reg-names = "tops-base"; -- clocks = <&topckgen CK_TOP_BUS_TOPS_SEL>, -- <&topckgen CK_TOP_TOPS_P2_26M_SEL>, -- <&topckgen CK_TOP_NETSYS_TOPS_400M_SEL>, -- <&topckgen CK_TOP_NPU_TOPS_SEL>, -- <&topckgen CK_TOP_CK_NPU_SEL_CM_TOPS_SEL>; -- clock-names = "bus", "sram", "xdma", "offload", "mgmt"; -- interrupt-parent = <&gic>; -- interrupts = , -- ; -- interrupt-names = "tdma-tx-pause", "mbox"; -- topmisc = <&topmisc>; -- fe_mem = <ð>; -- topckgen = <&topckgen>; -- }; -- hpdma1: hpdma@09106000 { -- compatible = "mediatek,hpdma-top"; -- reg = <0 0x09106000 0 0x1000>; -- reg-names = "base"; -- }; -- hpdma2: hpdma@09606000 { -- compatible = "mediatek,hpdma-sub"; -- reg = <0 0x09606000 0 0x1000>; -- reg-names = "base"; -- }; -- -- watchdog: watchdog@1001c000 { -- compatible = "mediatek,mt7622-wdt", -- "mediatek,mt6589-wdt", -- "syscon"; -- reg = <0 0x1001c000 0 0x1000>; -- interrupts = ; -- #reset-cells = <1>; -- }; -- -- phyfw: phy-firmware@f000000 { -- compatible = "mediatek,2p5gphy-fw"; -- reg = <0 0x0f000000 0 0x8000>, -- <0 0x0f100000 0 0x20000>, -- <0 0x0f0f0000 0 0x200>; -- }; -- -- gic: interrupt-controller@c000000 { -- compatible = "arm,gic-v3"; -- #interrupt-cells = <3>; -- interrupt-parent = <&gic>; -- interrupt-controller; -- reg = <0 0x0c000000 0 0x40000>, /* GICD */ -- <0 0x0c080000 0 0x200000>; /* GICR */ -- -- interrupts = ; -- }; -- -- trng: trng@1020f000 { -- compatible = "mediatek,mt7988-rng"; -- }; -- -- uart0: serial@11000000 { -- compatible = "mediatek,mt7986-uart", -- "mediatek,mt6577-uart"; -- reg = <0 0x11000000 0 0x100>; -- interrupts = ; -- clocks = <&uart_clk>; -- status = "disabled"; -- }; -- -- uart1: serial@11000100 { -- compatible = "mediatek,mt7986-uart", -- "mediatek,mt6577-uart"; -- reg = <0 0x11000100 0 0x100>; -- interrupts = ; -- clocks = <&uart_clk>; -- status = "disabled"; -- }; -- -- uart2: serial@11000200 { -- compatible = "mediatek,mt7986-uart", -- "mediatek,mt6577-uart"; -- reg = <0 0x11000200 0 0x100>; -- interrupts = ; -- clocks = <&uart_clk>; -- status = "disabled"; -- }; -- -- i2c0: i2c@11003000 { -- compatible = "mediatek,mt7988-i2c", -- "mediatek,mt7981-i2c"; -- reg = <0 0x11003000 0 0x1000>, -- <0 0x10217080 0 0x80>; -- interrupts = ; -- clock-div = <1>; -- clocks = <&system_clk>, -- <&system_clk>; -- clock-names = "main", "dma"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c1: i2c@11004000 { -- compatible = "mediatek,mt7988-i2c", -- "mediatek,mt7981-i2c"; -- reg = <0 0x11004000 0 0x1000>, -- <0 0x10217100 0 0x80>; -- interrupts = ; -- clock-div = <1>; -- clocks = <&system_clk>, -- <&system_clk>; -- clock-names = "main", "dma"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c2: i2c@11005000 { -- compatible = "mediatek,mt7988-i2c", -- "mediatek,mt7981-i2c"; -- reg = <0 0x11005000 0 0x1000>, -- <0 0x10217180 0 0x80>; -- interrupts = ; -- clock-div = <1>; -- clocks = <&system_clk>, -- <&system_clk>; -- clock-names = "main", "dma"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- pwm: pwm@10048000 { -- compatible = "mediatek,mt7988-pwm"; -- reg = <0 0x10048000 0 0x1000>; -- #pwm-cells = <2>; -- clocks = <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>; -- clock-names = "top", "main", "pwm1", "pwm2", "pwm3", -- "pwm4","pwm5","pwm6","pwm7","pwm8"; -- status = "disabled"; -- }; -- -- fan: pwm-fan { -- compatible = "pwm-fan"; -- /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ -- cooling-levels = <0 128 255>; -- #cooling-cells = <2>; -- #thermal-sensor-cells = <1>; -- status = "disabled"; -- }; -- -- lvts: lvts@1100a000 { -- compatible = "mediatek,mt7988-lvts"; -- #thermal-sensor-cells = <1>; -- reg = <0 0x1100a000 0 0x1000>; -- clocks = <&system_clk>; -- clock-names = "lvts_clk"; -- nvmem-cells = <&lvts_calibration>; -- nvmem-cell-names = "e_data1"; -- }; -- -- crypto: crypto@15600000 { -- compatible = "inside-secure,safexcel-eip197b"; -- reg = <0 0x15600000 0 0x180000>; -- interrupts = , -- , -- , -- ; -- interrupt-names = "ring0", "ring1", "ring2", "ring3"; -- status = "okay"; -- }; -- -- pcie0: pcie@11300000 { -- compatible = "mediatek,mt7988-pcie", -- "mediatek,mt7986-pcie"; -- device_type = "pci"; -- #address-cells = <3>; -- #size-cells = <2>; -- reg = <0 0x11300000 0 0x2000>; -- reg-names = "pcie-mac"; -- linux,pci-domain = <0>; -- interrupts = ; -- bus-range = <0x00 0xff>; -- ranges = <0x81000000 0x00 0x30000000 0x00 -- 0x30000000 0x00 0x00200000>, -- <0x82000000 0x00 0x30200000 0x00 -- 0x30200000 0x00 0x07e00000>; -- status = "disabled"; -- -- clocks = <&topckgen CK_TOP_PEXTP_P0_SEL>, -- <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P0>, -- <&infracfg_ao CK_INFRA_PCIE_PIPE_P0>, -- <&infracfg_ao CK_INFRA_133M_PCIE_CK_P0>, -- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P0>; -- -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 0x7>; -- interrupt-map = <0 0 0 1 &pcie_intc0 0>, -- <0 0 0 2 &pcie_intc0 1>, -- <0 0 0 3 &pcie_intc0 2>, -- <0 0 0 4 &pcie_intc0 3>; -- pcie_intc0: interrupt-controller { -- #address-cells = <0>; -- #interrupt-cells = <1>; -- interrupt-controller; -- }; -- }; -- -- pcie1: pcie@11310000 { -- compatible = "mediatek,mt7988-pcie", -- "mediatek,mt7986-pcie"; -- device_type = "pci"; -- #address-cells = <3>; -- #size-cells = <2>; -- reg = <0 0x11310000 0 0x2000>; -- reg-names = "pcie-mac"; -- linux,pci-domain = <1>; -- interrupts = ; -- bus-range = <0x00 0xff>; -- ranges = <0x81000000 0x00 0x38000000 0x00 -- 0x38000000 0x00 0x00200000>, -- <0x82000000 0x00 0x38200000 0x00 -- 0x38200000 0x00 0x07e00000>; -- status = "disabled"; -- -- clocks = <&topckgen CK_TOP_PEXTP_P1_SEL>, -- <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P1>, -- <&infracfg_ao CK_INFRA_PCIE_PIPE_P1>, -- <&infracfg_ao CK_INFRA_133M_PCIE_CK_P1>, -- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P1>; -- -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 0x7>; -- interrupt-map = <0 0 0 1 &pcie_intc1 0>, -- <0 0 0 2 &pcie_intc1 1>, -- <0 0 0 3 &pcie_intc1 2>, -- <0 0 0 4 &pcie_intc1 3>; -- pcie_intc1: interrupt-controller { -- #address-cells = <0>; -- #interrupt-cells = <1>; -- interrupt-controller; -- }; -- }; -- -- pcie2: pcie@11280000 { -- compatible = "mediatek,mt7988-pcie", -- "mediatek,mt7986-pcie"; -- device_type = "pci"; -- #address-cells = <3>; -- #size-cells = <2>; -- reg = <0 0x11280000 0 0x2000>; -- reg-names = "pcie-mac"; -- linux,pci-domain = <3>; -- interrupts = ; -- bus-range = <0x00 0xff>; -- ranges = <0x81000000 0x00 0x20000000 0x00 -- 0x20000000 0x00 0x00200000>, -- <0x82000000 0x00 0x20200000 0x00 -- 0x20200000 0x00 0x07e00000>; -- status = "disabled"; -- -- clocks = <&topckgen CK_TOP_PEXTP_P2_SEL>, -- <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P2>, -- <&infracfg_ao CK_INFRA_PCIE_PIPE_P2>, -- <&infracfg_ao CK_INFRA_133M_PCIE_CK_P2>, -- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P2>, -- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P3>; -- -- phys = <&xphyu3port0 PHY_TYPE_PCIE>; -- phy-names = "pcie-phy"; -- -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 0x7>; -- interrupt-map = <0 0 0 1 &pcie_intc2 0>, -- <0 0 0 2 &pcie_intc2 1>, -- <0 0 0 3 &pcie_intc2 2>, -- <0 0 0 4 &pcie_intc2 3>; -- pcie_intc2: interrupt-controller { -- #address-cells = <0>; -- #interrupt-cells = <1>; -- interrupt-controller; -- }; -- }; -- -- pcie3: pcie@11290000 { -- compatible = "mediatek,mt7988-pcie", -- "mediatek,mt7986-pcie"; -- device_type = "pci"; -- #address-cells = <3>; -- #size-cells = <2>; -- reg = <0 0x11290000 0 0x2000>; -- reg-names = "pcie-mac"; -- linux,pci-domain = <2>; -- interrupts = ; -- bus-range = <0x00 0xff>; -- ranges = <0x81000000 0x00 0x28000000 0x00 -- 0x28000000 0x00 0x00200000>, -- <0x82000000 0x00 0x28200000 0x00 -- 0x28200000 0x00 0x07e00000>; -- status = "disabled"; -- -- clocks = <&topckgen CK_TOP_PEXTP_P3_SEL>, -- <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P3>, -- <&infracfg_ao CK_INFRA_PCIE_PIPE_P3>, -- <&infracfg_ao CK_INFRA_133M_PCIE_CK_P3>, -- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P3>; -- -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 0x7>; -- interrupt-map = <0 0 0 1 &pcie_intc3 0>, -- <0 0 0 2 &pcie_intc3 1>, -- <0 0 0 3 &pcie_intc3 2>, -- <0 0 0 4 &pcie_intc3 3>; -- pcie_intc3: interrupt-controller { -- #address-cells = <0>; -- #interrupt-cells = <1>; -- interrupt-controller; -- }; -- }; -- -- pio: pinctrl@1001f000 { -- compatible = "mediatek,mt7988-pinctrl"; -- reg = <0 0x1001f000 0 0x1000>, -- <0 0x11c10000 0 0x1000>, -- <0 0x11d00000 0 0x1000>, -- <0 0x11d20000 0 0x1000>, -- <0 0x11e00000 0 0x1000>, -- <0 0x11f00000 0 0x1000>, -- <0 0x1000b000 0 0x1000>; -- reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base", -- "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", -- "eint"; -- gpio-controller; -- #gpio-cells = <2>; -- gpio-ranges = <&pio 0 0 83>; -- interrupt-controller; -- interrupts = ; -- interrupt-parent = <&gic>; -- #interrupt-cells = <2>; -- }; -- -- ethsys: syscon@15000000 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "mediatek,mt7988-ethsys", -- "syscon"; -- reg = <0 0x15000000 0 0x1000>; -- #clock-cells = <1>; -- #reset-cells = <1>; -- -- ethsysrst: reset-controller { -- compatible = "ti,syscon-reset"; -- #reset-cells = <1>; -- ti,reset-bits = -- <0x34 4 0x34 4 0x34 4 -- (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; -- }; -- }; -- -- ethwarp: syscon@15031000 { -- compatible = "mediatek,mt7988-ethwarp", "syscon"; -- reg = <0 0x15031000 0 0x1000>; -- #clock-cells = <1>; -- }; -- -- switch0: switch0@15020000 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "mediatek,mt7988-switch", "syscon"; -- reg = <0 0x15020000 0 0x8000>; -- }; -- -- eth: ethernet@15100000 { -- compatible = "mediatek,mt7988-eth"; -- reg = <0 0x15100000 0 0x80000>, -- <0 0x15400000 0 0x380000>; -- interrupts = , -- , -- , -- ; -- clocks = <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>; -- clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", -- "sgmii_tx250m", "sgmii_rx250m", -- "sgmii_cdr_ref", "sgmii_cdr_fb", -- "sgmii2_tx250m", "sgmii2_rx250m", -- "sgmii2_cdr_ref", "sgmii2_cdr_fb"; -- mediatek,ethsys = <ðsys>; -- mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; -- mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>; -- mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>; -- mediatek,xfi_pll = <&xfi_pll>; -- mediatek,infracfg = <&topmisc>; -- mediatek,toprgu = <&watchdog>; -- #reset-cells = <1>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- hnat: hnat@15000000 { -- compatible = "mediatek,mtk-hnat_v5"; -- reg = <0 0x15100000 0 0x80000>; -- resets = <ðsys 0>; -- reset-names = "mtketh"; -- status = "disabled"; -- }; -- -- sgmiisys0: syscon@10060000 { -- compatible = "mediatek,mt7988-sgmiisys", -- "mediatek,mt7988-sgmiisys_0", -- "syscon"; -- reg = <0 0x10060000 0 0x1000>; -- #clock-cells = <1>; -- }; -- -- sgmiisys1: syscon@10070000 { -- compatible = "mediatek,mt7988-sgmiisys", -- "mediatek,mt7988-sgmiisys_1", -- "syscon"; -- reg = <0 0x10070000 0 0x1000>; -- #clock-cells = <1>; -- }; -- -- usxgmiisys0: usxgmiisys@10080000 { -- compatible = "mediatek,mt7988-usxgmiisys", -- "mediatek,mt7988-usxgmiisys_0", -- "syscon"; -- reg = <0 0x10080000 0 0x1000>; -- #clock-cells = <1>; -- }; -- -- usxgmiisys1: usxgmiisys@10081000 { -- compatible = "mediatek,mt7988-usxgmiisys", -- "mediatek,mt7988-usxgmiisys_1", -- "syscon"; -- reg = <0 0x10081000 0 0x1000>; -- #clock-cells = <1>; -- }; -- -- xfi_pextp0: xfi_pextp@11f20000 { -- compatible = "mediatek,mt7988-xfi_pextp", -- "mediatek,mt7988-xfi_pextp_0", -- "syscon"; -- reg = <0 0x11f20000 0 0x10000>; -- #clock-cells = <1>; -- }; -- -- xfi_pextp1: xfi_pextp@11f30000 { -- compatible = "mediatek,mt7988-xfi_pextp", -- "mediatek,mt7988-xfi_pextp_1", -- "syscon"; -- reg = <0 0x11f30000 0 0x10000>; -- #clock-cells = <1>; -- }; -- -- xfi_pll: xfi_pll@11f40000 { -- compatible = "mediatek,mt7988-xfi_pll", "syscon"; -- reg = <0 0x11f40000 0 0x1000>; -- #clock-cells = <1>; -- }; -- -- topmisc: topmisc@11d10000 { -- compatible = "mediatek,mt7988-topmisc", "syscon", -- "mediatek,mt7988-power-controller"; -- reg = <0 0x11d10000 0 0x10000>; -- #clock-cells = <1>; -- #power-domain-cells = <1>; -- #address-cells = <1>; -- #size-cells = <0>; -- /* power domain of the SoC */ -- tops0@MT7988_POWER_DOMAIN_TOPS0 { -- reg = ; -- #power-domain-cells = <0>; -- }; -- tops1@MT7988_POWER_DOMAIN_TOPS1 { -- reg = ; -- #power-domain-cells = <0>; -- }; -- eth2p5@MT7988_POWER_DOMAIN_ETH2P5 { -- reg = ; -- #power-domain-cells = <0>; -- }; -- }; -- -- snand: snfi@11001000 { -- compatible = "mediatek,mt7986-snand"; -- reg = <0 0x11001000 0 0x1000>, <0 0x11002000 0 0x1000>; -- reg-names = "nfi", "ecc"; -- interrupts = ; -- clocks = <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>; -- clock-names = "nfi_clk", "pad_clk", "ecc_clk", "nfi_hclk"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- wbsys: wbsys@18000000 { -- compatible = "mediatek,wbsys"; -- reg = <0 0x18000000 0 0x1000000>; -- linux,pci-domain = <4>; -- interrupts = , -- , -- , -- ; -- chip_id = <0x7981>; -- }; -- -- wed_pcie: wed_pcie@10003000 { -- compatible = "mediatek,wed_pcie"; -- reg = <0 0x10003000 0 0x10>; -- }; -- -- spi0: spi@11007000 { -- compatible = "mediatek,ipm-spi-quad"; -- reg = <0 0x11007000 0 0x100>; -- interrupts = ; -- clocks = <&topckgen CK_TOP_CB_M_D2>, -- <&topckgen CK_TOP_SPI_SEL>, -- <&infracfg_ao CK_INFRA_104M_SPI0>, -- <&infracfg_ao CK_INFRA_66M_SPI0_HCK>; -- clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; -- status = "disabled"; -- }; -- -- spi1: spi@11008000 { -- compatible = "mediatek,ipm-spi-single"; -- reg = <0 0x11008000 0 0x100>; -- interrupts = ; -- clocks = <&topckgen CK_TOP_CB_M_D2>, -- <&topckgen CK_TOP_SPI_SEL>, -- <&infracfg_ao CK_INFRA_104M_SPI1>, -- <&infracfg_ao CK_INFRA_66M_SPI1_HCK>; -- clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; -- status = "disabled"; -- }; -- -- spi2: spi@11009000 { -- compatible = "mediatek,ipm-spi-quad"; -- reg = <0 0x11009000 0 0x100>; -- interrupts = ; -- clocks = <&topckgen CK_TOP_CB_M_D2>, -- <&topckgen CK_TOP_SPI_SEL>, -- <&infracfg_ao CK_INFRA_104M_SPI2_BCK>, -- <&infracfg_ao CK_INFRA_66M_SPI2_HCK>; -- clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; -- status = "disabled"; -- }; -- -- consys: consys@10000000 { -- compatible = "mediatek,mt7981-consys"; -- reg = <0 0x10000000 0 0x8600000>; -- memory-region = <&wmcpu_emi>; -- }; -- -- xhci0: xhci@11190000 { -- compatible = "mediatek,mt7988-xhci", -- "mediatek,mtk-xhci"; -- reg = <0 0x11190000 0 0x2e00>, -- <0 0x11193e00 0 0x0100>; -- reg-names = "mac", "ippc"; -- interrupts = ; -- phys = <&xphyu2port0 PHY_TYPE_USB2>, -- <&xphyu3port0 PHY_TYPE_USB3>; -- clocks = <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>; -- clock-names = "sys_ck", -- "xhci_ck", -- "ref_ck", -- "mcu_ck", -- "dma_ck"; -- #address-cells = <2>; -- #size-cells = <2>; -- status = "okay"; -- }; -- -- usbxphy: usb-phy@11e10000 { -- compatible = "mediatek,mt7988", -- "mediatek,xsphy"; -- #address-cells = <2>; -- #size-cells = <2>; -- ranges; -- status = "okay"; -- -- xphyu2port0: usb-phy@11e10000 { -- reg = <0 0x11e10000 0 0x400>; -- clocks = <&system_clk>; -- clock-names = "ref"; -- #phy-cells = <1>; -- status = "okay"; -- }; -- -- xphyu3port0: usb-phy@11e13000 { -- reg = <0 0x11e13400 0 0x500>; -- clocks = <&system_clk>; -- clock-names = "ref"; -- #phy-cells = <1>; -- mediatek,syscon-type = <&topmisc 0x218 0>; -- status = "okay"; -- }; -- }; -- -- xhci1: xhci@11200000 { -- compatible = "mediatek,mt7988-xhci", -- "mediatek,mtk-xhci"; -- reg = <0 0x11200000 0 0x2e00>, -- <0 0x11203e00 0 0x0100>; -- reg-names = "mac", "ippc"; -- interrupts = ; -- phys = <&tphyu2port0 PHY_TYPE_USB2>, -- <&tphyu3port0 PHY_TYPE_USB3>; -- clocks = <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>; -- clock-names = "sys_ck", -- "xhci_ck", -- "ref_ck", -- "mcu_ck", -- "dma_ck"; -- #address-cells = <2>; -- #size-cells = <2>; -- status = "okay"; -- }; -- -- usbtphy: usb-phy@11c50000 { -- compatible = "mediatek,mt7988", -- "mediatek,generic-tphy-v2"; -- #address-cells = <2>; -- #size-cells = <2>; -- ranges; -- status = "okay"; -- -- tphyu2port0: usb-phy@11c50000 { -- reg = <0 0x11c50000 0 0x700>; -- clocks = <&system_clk>; -- clock-names = "ref"; -- #phy-cells = <1>; -- status = "okay"; -- }; -- -- tphyu3port0: usb-phy@11c50700 { -- reg = <0 0x11c50700 0 0x900>; -- clocks = <&system_clk>; -- clock-names = "ref"; -- #phy-cells = <1>; -- status = "okay"; -- }; -- }; -- -- clk40m: oscillator@0 { -- compatible = "fixed-clock"; -- #clock-cells = <0>; -- clock-frequency = <40000000>; -- clock-output-names = "clkxtal"; -- }; -- -- infracfg_ao: infracfg_ao@10001000 { -- compatible = "mediatek,mt7988-infracfg_ao", "syscon"; -- reg = <0 0x10001000 0 0x1000>; -- #clock-cells = <1>; -- }; -- -- infracfg: infracfg@10209000 { -- compatible = "mediatek,mt7988-infracfg", "syscon"; -- reg = <0 0x10209000 0 0x1000>; -- #clock-cells = <1>; -- }; -- -- topckgen: topckgen@1001B000 { -- compatible = "mediatek,mt7988-topckgen", "syscon"; -- reg = <0 0x1001B000 0 0x1000>; -- #clock-cells = <1>; -- }; -- -- apmixedsys: apmixedsys@1001E000 { -- compatible = "mediatek,mt7988-apmixedsys", "syscon"; -- reg = <0 0x1001E000 0 0x1000>; -- #clock-cells = <1>; -- }; -- -- mcusys: mcusys@100E0000 { -- compatible = "mediatek,mt7988-mcusys", "syscon"; -- reg = <0 0x100E0000 0 0x1000>; -- #clock-cells = <1>; -- }; -- -- clkitg: clkitg { -- compatible = "simple-bus"; -- }; -- -- efuse: efuse@11f50000 { -- compatible = "mediatek,efuse"; -- reg = <0 0x11f50000 0 0x1000>; -- #address-cells = <1>; -- #size-cells = <1>; -- -- lvts_calibration: calib@918 { -- reg = <0x918 0x28>; -- }; -- phy_calibration_p0: calib@940 { -- reg = <0x940 0x10>; -- }; -- phy_calibration_p1: calib@954 { -- reg = <0x954 0x10>; -- }; -- phy_calibration_p2: calib@968 { -- reg = <0x968 0x10>; -- }; -- phy_calibration_p3: calib@97c { -- reg = <0x97c 0x10>; -- }; -- cpufreq_calibration: calib@278 { -- reg = <0x278 0x1>; -- }; -- }; --}; -- --#include "mt7988-clkitg.dtsi" -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-emmc.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-emmc.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-emmc.dts 2023-02-26 09:01:19.908972500 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-emmc.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,271 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) --/* -- * Copyright (C) 2021 MediaTek Inc. -- * Author: Sam.Shih -- */ -- --/dts-v1/; --#include "mt7988.dtsi" -- --/ { -- model = "MediaTek MT7988A DSA 10G eMMC RFB"; -- compatible = "mediatek,mt7988a-dsa-10g-emmc", -- /* Reserve this for DVFS if creating new dts */ -- "mediatek,mt7988"; -- chosen { -- bootargs = "console=ttyS0,115200n1 loglevel=8 \ -- earlycon=uart8250,mmio32,0x11000000 \ -- root=PARTLABEL=rootfs rootwait \ -- rootfstype=squashfs,f2fs pci=pcie_bus_perf"; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x10000000>; -- }; -- -- wsys_adie: wsys_adie@0 { -- // fpga cases need to manual change adie_id / sku_type for dvt only -- compatible = "mediatek,rebb-mt7988-adie"; -- adie_id = <7976>; -- sku_type = <3000>; -- }; -- -- reg_1p8v: regulator-1p8v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-1.8V"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-boot-on; -- regulator-always-on; -- }; -- -- reg_3p3v: regulator-3p3v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-3.3V"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-boot-on; -- regulator-always-on; -- }; --}; -- --&fan { -- pwms = <&pwm 0 50000 0>; -- status = "okay"; --}; -- --&pwm { -- status = "okay"; --}; -- --&uart0 { -- status = "okay"; --}; -- --&spi1 { -- pinctrl-names = "default"; -- /* pin shared with snfi */ -- pinctrl-0 = <&spic_pins>; -- status = "disabled"; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&pcie1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie1_pins>; -- status = "okay"; --}; -- --&pcie2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_pins>; -- status = "disabled"; --}; -- --&pcie3 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_pins>; -- status = "okay"; --}; -- --&pio { -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", -- "pcie_wake_n0_0"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", -- "pcie_wake_n1_0"; -- }; -- }; -- -- pcie2_pins: pcie2-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", -- "pcie_wake_n2_0"; -- }; -- }; -- -- pcie3_pins: pcie3-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", -- "pcie_wake_n3_0"; -- }; -- }; -- -- spic_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1_1"; -- }; -- }; -- -- mmc0_pins_default: mmc0-pins-default { -- mux { -- function = "flash"; -- groups = "emmc_51"; -- }; -- }; -- -- mmc0_pins_uhs: mmc0-pins-uhs { -- mux { -- function = "flash"; -- groups = "emmc_51"; -- }; -- }; --}; -- --&watchdog { -- status = "disabled"; --}; -- --ð { -- status = "okay"; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy0>; -- }; -- -- gmac2: mac@2 { -- compatible = "mediatek,eth-mac"; -- reg = <2>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy1>; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- phy0: ethernet-phy@0 { -- reg = <0>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 71 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- -- phy1: ethernet-phy@8 { -- reg = <8>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 72 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- -- switch@0 { -- compatible = "mediatek,mt7988"; -- reg = <31>; -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@0 { -- reg = <0>; -- label = "lan0"; -- }; -- -- port@1 { -- reg = <1>; -- label = "lan1"; -- }; -- -- port@2 { -- reg = <2>; -- label = "lan2"; -- }; -- -- port@3 { -- reg = <3>; -- label = "lan3"; -- }; -- -- port@6 { -- reg = <6>; -- label = "cpu"; -- ethernet = <&gmac0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <10000>; -- full-duplex; -- pause; -- }; -- }; -- }; -- }; -- }; --}; -- --&hnat { -- mtketh-wan = "eth1"; -- mtketh-lan = "lan"; -- mtketh-lan2 = "eth2"; -- mtketh-max-gmac = <3>; -- status = "okay"; --}; -- --&mmc0 { -- pinctrl-names = "default", "state_uhs"; -- pinctrl-0 = <&mmc0_pins_default>; -- pinctrl-1 = <&mmc0_pins_uhs>; -- bus-width = <8>; -- max-frequency = <200000000>; -- cap-mmc-highspeed; -- mmc-hs200-1_8v; -- mmc-hs400-1_8v; -- hs400-ds-delay = <0x12814>; -- vqmmc-supply = <®_1p8v>; -- vmmc-supply = <®_3p3v>; -- non-removable; -- no-sd; -- no-sdio; -- status = "okay"; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-sd.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-sd.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-sd.dts 2023-02-26 09:01:19.908972500 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-sd.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,258 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) --/* -- * Copyright (C) 2021 MediaTek Inc. -- * Author: Sam.Shih -- */ -- --/dts-v1/; --#include "mt7988.dtsi" -- --/ { -- model = "MediaTek MT7988A DSA 10G SD RFB"; -- compatible = "mediatek,mt7988a-dsa-10g-sd", -- /* Reserve this for DVFS if creating new dts */ -- "mediatek,mt7988"; -- chosen { -- bootargs = "console=ttyS0,115200n1 loglevel=8 \ -- earlycon=uart8250,mmio32,0x11000000 \ -- root=PARTLABEL=rootfs rootwait \ -- rootfstype=squashfs,f2fs pci=pcie_bus_perf"; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x10000000>; -- }; -- -- wsys_adie: wsys_adie@0 { -- // fpga cases need to manual change adie_id / sku_type for dvt only -- compatible = "mediatek,rebb-mt7988-adie"; -- adie_id = <7976>; -- sku_type = <3000>; -- }; -- -- reg_3p3v: regulator-3p3v { -- compatible = "regulator-fixed"; -- regulator-name = "fixed-3.3V"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-boot-on; -- regulator-always-on; -- }; --}; -- --&fan { -- pwms = <&pwm 0 50000 0>; -- status = "okay"; --}; -- --&pwm { -- status = "okay"; --}; -- --&uart0 { -- status = "okay"; --}; -- --&spi1 { -- pinctrl-names = "default"; -- /* pin shared with snfi */ -- pinctrl-0 = <&spic_pins>; -- status = "disabled"; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&pcie1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie1_pins>; -- status = "okay"; --}; -- --&pcie2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_pins>; -- status = "disabled"; --}; -- --&pcie3 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_pins>; -- status = "okay"; --}; -- --&pio { -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", -- "pcie_wake_n0_0"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", -- "pcie_wake_n1_0"; -- }; -- }; -- -- pcie2_pins: pcie2-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", -- "pcie_wake_n2_0"; -- }; -- }; -- -- pcie3_pins: pcie3-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", -- "pcie_wake_n3_0"; -- }; -- }; -- -- spic_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1_1"; -- }; -- }; -- -- mmc0_pins_default: mmc0-pins-default { -- mux { -- function = "flash"; -- groups = "emmc_45"; -- }; -- }; -- -- mmc0_pins_uhs: mmc0-pins-uhs { -- mux { -- function = "flash"; -- groups = "emmc_45"; -- }; -- }; --}; -- --&watchdog { -- status = "disabled"; --}; -- --ð { -- status = "okay"; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy0>; -- }; -- -- gmac2: mac@2 { -- compatible = "mediatek,eth-mac"; -- reg = <2>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy1>; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- phy0: ethernet-phy@0 { -- reg = <0>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 71 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- -- phy1: ethernet-phy@8 { -- reg = <8>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 72 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- -- switch@0 { -- compatible = "mediatek,mt7988"; -- reg = <31>; -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@0 { -- reg = <0>; -- label = "lan0"; -- }; -- -- port@1 { -- reg = <1>; -- label = "lan1"; -- }; -- -- port@2 { -- reg = <2>; -- label = "lan2"; -- }; -- -- port@3 { -- reg = <3>; -- label = "lan3"; -- }; -- -- port@6 { -- reg = <6>; -- label = "cpu"; -- ethernet = <&gmac0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <10000>; -- full-duplex; -- pause; -- }; -- }; -- }; -- }; -- }; --}; -- --&hnat { -- mtketh-wan = "eth1"; -- mtketh-lan = "lan"; -- mtketh-lan2 = "eth2"; -- mtketh-max-gmac = <3>; -- status = "okay"; --}; -- --&mmc0 { -- pinctrl-names = "default", "state_uhs"; -- pinctrl-0 = <&mmc0_pins_default>; -- pinctrl-1 = <&mmc0_pins_uhs>; -- bus-width = <4>; -- max-frequency = <52000000>; -- cap-sd-highspeed; -- vmmc-supply = <®_3p3v>; -- vqmmc-supply = <®_3p3v>; -- no-mmc; -- no-sdio; -- status = "okay"; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-snfi-nand.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-snfi-nand.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-snfi-nand.dts 2023-02-26 09:01:19.909973900 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-snfi-nand.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,279 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) --/* -- * Copyright (C) 2021 MediaTek Inc. -- * Author: Sam.Shih -- */ -- --/dts-v1/; --#include "mt7988.dtsi" -- --/ { -- model = "MediaTek MT7988A DSA 10G SNFI-NAND RFB"; -- compatible = "mediatek,mt7988a-dsa-10g-snfi-snand", -- /* Reserve this for DVFS if creating new dts */ -- "mediatek,mt7988"; -- -- chosen { -- bootargs = "console=ttyS0,115200n1 loglevel=8 \ -- earlycon=uart8250,mmio32,0x11000000 \ -- pci=pcie_bus_perf"; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x10000000>; -- }; -- -- nmbm_snfi { -- compatible = "generic,nmbm"; -- -- #address-cells = <1>; -- #size-cells = <1>; -- -- lower-mtd-device = <&snand>; -- forced-create; -- empty-page-ecc-protected; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "BL2"; -- reg = <0x00000 0x0100000>; -- read-only; -- }; -- -- partition@100000 { -- label = "u-boot-env"; -- reg = <0x0100000 0x0080000>; -- }; -- -- factory: partition@180000 { -- label = "Factory"; -- reg = <0x180000 0x0400000>; -- }; -- -- partition@580000 { -- label = "FIP"; -- reg = <0x580000 0x0200000>; -- }; -- -- partition@780000 { -- label = "ubi"; -- reg = <0x780000 0x4000000>; -- }; -- }; -- }; -- -- wsys_adie: wsys_adie@0 { -- // fpga cases need to manual change adie_id / sku_type for dvt only -- compatible = "mediatek,rebb-mt7988-adie"; -- adie_id = <7976>; -- sku_type = <3000>; -- }; --}; -- --&fan { -- pwms = <&pwm 0 50000 0>; -- status = "okay"; --}; -- --&pwm { -- status = "okay"; --}; -- --&uart0 { -- status = "okay"; --}; -- --&spi1 { -- pinctrl-names = "default"; -- /* pin shared with snfi */ -- pinctrl-0 = <&spic_pins>; -- status = "disabled"; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&pcie1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie1_pins>; -- status = "okay"; --}; -- --&pcie2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_pins>; -- status = "disabled"; --}; -- --&pcie3 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_pins>; -- status = "okay"; --}; -- --&pio { -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", -- "pcie_wake_n0_0"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", -- "pcie_wake_n1_0"; -- }; -- }; -- -- pcie2_pins: pcie2-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", -- "pcie_wake_n2_0"; -- }; -- }; -- -- pcie3_pins: pcie3-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", -- "pcie_wake_n3_0"; -- }; -- }; -- -- snfi_pins: snfi-pins { -- mux { -- function = "flash"; -- groups = "snfi"; -- }; -- }; -- -- spic_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1_1"; -- }; -- }; --}; -- --&watchdog { -- status = "disabled"; --}; -- --&snand { -- pinctrl-names = "default"; -- /* pin shared with spic */ -- pinctrl-0 = <&snfi_pins>; -- status = "okay"; -- mediatek,quad-spi; --}; -- --ð { -- status = "okay"; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy0>; -- }; -- -- gmac2: mac@2 { -- compatible = "mediatek,eth-mac"; -- reg = <2>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy1>; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- phy0: ethernet-phy@0 { -- reg = <0>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 71 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- -- phy1: ethernet-phy@8 { -- reg = <8>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 72 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- -- switch@0 { -- compatible = "mediatek,mt7988"; -- reg = <31>; -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@0 { -- reg = <0>; -- label = "lan0"; -- }; -- -- port@1 { -- reg = <1>; -- label = "lan1"; -- }; -- -- port@2 { -- reg = <2>; -- label = "lan2"; -- }; -- -- port@3 { -- reg = <3>; -- label = "lan3"; -- }; -- -- port@6 { -- reg = <6>; -- label = "cpu"; -- ethernet = <&gmac0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <10000>; -- full-duplex; -- pause; -- }; -- }; -- }; -- }; -- }; --}; -- --&hnat { -- mtketh-wan = "eth1"; -- mtketh-lan = "lan"; -- mtketh-lan2 = "eth2"; -- mtketh-max-gmac = <3>; -- status = "okay"; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts 2023-02-26 09:01:19.910973200 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,292 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) --/* -- * Copyright (C) 2021 MediaTek Inc. -- * Author: Sam.Shih -- */ -- --/dts-v1/; --#include "mt7988.dtsi" -- --/ { -- model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; -- compatible = "mediatek,mt7988a-dsa-10g-spim-snand", -- /* Reserve this for DVFS if creating new dts */ -- "mediatek,mt7988"; -- -- chosen { -- bootargs = "console=ttyS0,115200n1 loglevel=8 \ -- earlycon=uart8250,mmio32,0x11000000 \ -- pci=pcie_bus_perf"; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x10000000>; -- }; -- -- nmbm_spim_nand { -- compatible = "generic,nmbm"; -- -- #address-cells = <1>; -- #size-cells = <1>; -- -- lower-mtd-device = <&spi_nand>; -- forced-create; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "BL2"; -- reg = <0x00000 0x0100000>; -- read-only; -- }; -- -- partition@100000 { -- label = "u-boot-env"; -- reg = <0x0100000 0x0080000>; -- }; -- -- factory: partition@180000 { -- label = "Factory"; -- reg = <0x180000 0x0400000>; -- }; -- -- partition@580000 { -- label = "FIP"; -- reg = <0x580000 0x0200000>; -- }; -- -- partition@780000 { -- label = "ubi"; -- reg = <0x780000 0x4000000>; -- }; -- }; -- }; -- -- wsys_adie: wsys_adie@0 { -- // fpga cases need to manual change adie_id / sku_type for dvt only -- compatible = "mediatek,rebb-mt7988-adie"; -- adie_id = <7976>; -- sku_type = <3000>; -- }; --}; -- --&fan { -- pwms = <&pwm 0 50000 0>; -- status = "okay"; --}; -- --&pwm { -- status = "okay"; --}; -- --&uart0 { -- status = "okay"; --}; -- --&spi0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi0_flash_pins>; -- status = "okay"; -- -- spi_nand: spi_nand@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "spi-nand"; -- spi-cal-enable; -- spi-cal-mode = "read-data"; -- spi-cal-datalen = <7>; -- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; -- spi-cal-addrlen = <5>; -- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; -- reg = <0>; -- spi-max-frequency = <52000000>; -- spi-tx-buswidth = <4>; -- spi-rx-buswidth = <4>; -- }; --}; -- --&spi1 { -- pinctrl-names = "default"; -- /* pin shared with snfi */ -- pinctrl-0 = <&spic_pins>; -- status = "disabled"; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&pcie1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie1_pins>; -- status = "okay"; --}; -- --&pcie2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_pins>; -- status = "disabled"; --}; -- --&pcie3 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_pins>; -- status = "okay"; --}; -- --&pio { -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", -- "pcie_wake_n0_0"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", -- "pcie_wake_n1_0"; -- }; -- }; -- -- pcie2_pins: pcie2-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", -- "pcie_wake_n2_0"; -- }; -- }; -- -- pcie3_pins: pcie3-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", -- "pcie_wake_n3_0"; -- }; -- }; -- -- spi0_flash_pins: spi0-pins { -- mux { -- function = "spi"; -- groups = "spi0", "spi0_wp_hold"; -- }; -- }; -- -- spic_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1_1"; -- }; -- }; --}; -- --&watchdog { -- status = "disabled"; --}; -- --ð { -- status = "okay"; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy0>; -- }; -- -- gmac2: mac@2 { -- compatible = "mediatek,eth-mac"; -- reg = <2>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy1>; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- phy0: ethernet-phy@0 { -- reg = <0>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 71 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- -- phy1: ethernet-phy@8 { -- reg = <8>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 72 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- -- switch@0 { -- compatible = "mediatek,mt7988"; -- reg = <31>; -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@0 { -- reg = <0>; -- label = "lan0"; -- }; -- -- port@1 { -- reg = <1>; -- label = "lan1"; -- }; -- -- port@2 { -- reg = <2>; -- label = "lan2"; -- }; -- -- port@3 { -- reg = <3>; -- label = "lan3"; -- }; -- -- port@6 { -- reg = <6>; -- label = "cpu"; -- ethernet = <&gmac0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <10000>; -- full-duplex; -- pause; -- }; -- }; -- }; -- }; -- }; --}; -- --&hnat { -- mtketh-wan = "eth1"; -- mtketh-lan = "lan"; -- mtketh-lan2 = "eth2"; -- mtketh-max-gmac = <3>; -- status = "okay"; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts 2023-02-26 09:01:19.910973200 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,276 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) --/* -- * Copyright (C) 2021 MediaTek Inc. -- * Author: Sam.Shih -- */ -- --/dts-v1/; --#include "mt7988.dtsi" -- --/ { -- model = "MediaTek MT7988A DSA 10G SPIM-NOR RFB"; -- compatible = "mediatek,mt7988a-dsa-10g-spim-nor", -- /* Reserve this for DVFS if creating new dts */ -- "mediatek,mt7988"; -- -- chosen { -- bootargs = "console=ttyS0,115200n1 loglevel=8 \ -- earlycon=uart8250,mmio32,0x11000000 \ -- pci=pcie_bus_perf"; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x10000000>; -- }; -- -- wsys_adie: wsys_adie@0 { -- // fpga cases need to manual change adie_id / sku_type for dvt only -- compatible = "mediatek,rebb-mt7988-adie"; -- adie_id = <7976>; -- sku_type = <3000>; -- }; --}; -- --&fan { -- pwms = <&pwm 0 50000 0>; -- status = "okay"; --}; -- --&pwm { -- status = "okay"; --}; -- --&uart0 { -- status = "okay"; --}; -- --&spi1 { -- pinctrl-names = "default"; -- /* pin shared with snfi */ -- pinctrl-0 = <&spic_pins>; -- status = "disabled"; --}; -- --&spi2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi2_flash_pins>; -- status = "okay"; -- spi_nor@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "jedec,spi-nor"; -- spi-cal-enable; -- spi-cal-mode = "read-data"; -- spi-cal-datalen = <7>; -- spi-cal-data = /bits/ 8 < -- 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ -- spi-cal-addrlen = <1>; -- spi-cal-addr = /bits/ 32 <0x0>; -- reg = <0>; -- spi-max-frequency = <52000000>; -- -- partition@00000 { -- label = "BL2"; -- reg = <0x00000 0x0040000>; -- }; -- partition@40000 { -- label = "u-boot-env"; -- reg = <0x40000 0x0010000>; -- }; -- factory: partition@50000 { -- label = "Factory"; -- reg = <0x50000 0x00B0000>; -- }; -- partition@100000 { -- label = "FIP"; -- reg = <0x100000 0x0080000>; -- }; -- partition@180000 { -- label = "firmware"; -- reg = <0x180000 0xE00000>; -- }; -- }; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&pcie1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie1_pins>; -- status = "okay"; --}; -- --&pcie2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_pins>; -- status = "disabled"; --}; -- --&pcie3 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_pins>; -- status = "okay"; --}; -- --&pio { -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", -- "pcie_wake_n0_0"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", -- "pcie_wake_n1_0"; -- }; -- }; -- -- pcie2_pins: pcie2-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", -- "pcie_wake_n2_0"; -- }; -- }; -- -- pcie3_pins: pcie3-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", -- "pcie_wake_n3_0"; -- }; -- }; -- -- spic_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1_1"; -- }; -- }; -- -- spi2_flash_pins: spi2-pins { -- mux { -- function = "spi"; -- groups = "spi2", "spi2_wp_hold"; -- }; -- }; --}; -- --&watchdog { -- status = "disabled"; --}; -- --ð { -- status = "okay"; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy0>; -- }; -- -- gmac2: mac@2 { -- compatible = "mediatek,eth-mac"; -- reg = <2>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy1>; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- phy0: ethernet-phy@0 { -- reg = <0>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 71 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- -- phy1: ethernet-phy@8 { -- reg = <8>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 72 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- -- switch@0 { -- compatible = "mediatek,mt7988"; -- reg = <31>; -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@0 { -- reg = <0>; -- label = "lan0"; -- }; -- -- port@1 { -- reg = <1>; -- label = "lan1"; -- }; -- -- port@2 { -- reg = <2>; -- label = "lan2"; -- }; -- -- port@3 { -- reg = <3>; -- label = "lan3"; -- }; -- -- port@6 { -- reg = <6>; -- label = "cpu"; -- ethernet = <&gmac0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <10000>; -- full-duplex; -- pause; -- }; -- }; -- }; -- }; -- }; --}; -- --&hnat { -- mtketh-wan = "eth1"; -- mtketh-lan = "lan"; -- mtketh-lan2 = "eth2"; -- mtketh-max-gmac = <3>; -- status = "okay"; --}; -- --&wed { -- dy_txbm_enable = "true"; -- dy_txbm_budge = <8>; -- txbm_init_sz = <10>; -- status = "okay"; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-e2p5g-spim-nand.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-e2p5g-spim-nand.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-e2p5g-spim-nand.dts 2023-02-26 09:01:19.910973200 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-e2p5g-spim-nand.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,365 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) --/* -- * Copyright (C) 2021 MediaTek Inc. -- * Author: Sam.Shih -- */ -- --/dts-v1/; --#include "mt7988.dtsi" -- --/ { -- model = "MediaTek MT7988 DSA external-2.5G SPIM-NAND RFB"; -- compatible = "mediatek,mt7988a-dsa-e2p5g-spim-snand", -- /* Reserve this for DVFS if creating new dts */ -- "mediatek,mt7988"; -- -- chosen { -- bootargs = "console=ttyS0,115200n1 loglevel=8 \ -- earlycon=uart8250,mmio32,0x11000000 \ -- pci=pcie_bus_perf"; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x10000000>; -- }; -- -- nmbm_spim_nand { -- compatible = "generic,nmbm"; -- -- #address-cells = <1>; -- #size-cells = <1>; -- -- lower-mtd-device = <&spi_nand>; -- forced-create; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "BL2"; -- reg = <0x00000 0x0100000>; -- read-only; -- }; -- -- partition@100000 { -- label = "u-boot-env"; -- reg = <0x0100000 0x0080000>; -- }; -- -- factory: partition@180000 { -- label = "Factory"; -- reg = <0x180000 0x0400000>; -- }; -- -- partition@580000 { -- label = "FIP"; -- reg = <0x580000 0x0200000>; -- }; -- -- partition@780000 { -- label = "ubi"; -- reg = <0x780000 0x4000000>; -- }; -- }; -- }; -- -- wsys_adie: wsys_adie@0 { -- // fpga cases need to manual change adie_id / sku_type for dvt only -- compatible = "mediatek,rebb-mt7988-adie"; -- adie_id = <7976>; -- sku_type = <3000>; -- }; --}; -- --&fan { -- pwms = <&pwm 0 50000 0>; -- status = "okay"; --}; -- --&i2c0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c0_pins>; -- status = "okay"; -- -- rt5190a_64: rt5190a@64 { -- compatible = "richtek,rt5190a"; -- reg = <0x64>; -- /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ -- vin2-supply = <&rt5190_buck1>; -- vin3-supply = <&rt5190_buck1>; -- vin4-supply = <&rt5190_buck1>; -- -- regulators { -- rt5190_buck1: buck1 { -- regulator-name = "rt5190a-buck1"; -- regulator-min-microvolt = <5090000>; -- regulator-max-microvolt = <5090000>; -- regulator-allowed-modes = -- ; -- regulator-boot-on; -- }; -- buck2 { -- regulator-name = "vcore"; -- regulator-min-microvolt = <600000>; -- regulator-max-microvolt = <1400000>; -- regulator-boot-on; -- }; -- buck3 { -- regulator-name = "proc"; -- regulator-min-microvolt = <600000>; -- regulator-max-microvolt = <1400000>; -- regulator-boot-on; -- }; -- buck4 { -- regulator-name = "rt5190a-buck4"; -- regulator-min-microvolt = <850000>; -- regulator-max-microvolt = <850000>; -- regulator-allowed-modes = -- ; -- regulator-boot-on; -- }; -- ldo { -- regulator-name = "rt5190a-ldo"; -- regulator-min-microvolt = <1200000>; -- regulator-max-microvolt = <1200000>; -- regulator-boot-on; -- }; -- }; -- }; --}; -- --&i2c1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c1_pins>; -- status = "okay"; --}; -- --&pwm { -- status = "okay"; --}; -- --&uart0 { -- status = "okay"; --}; -- --&spi0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi0_flash_pins>; -- status = "okay"; -- -- spi_nand: spi_nand@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "spi-nand"; -- spi-cal-enable; -- spi-cal-mode = "read-data"; -- spi-cal-datalen = <7>; -- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; -- spi-cal-addrlen = <5>; -- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; -- reg = <0>; -- spi-max-frequency = <52000000>; -- spi-tx-buswidth = <4>; -- spi-rx-buswidth = <4>; -- }; --}; -- --&spi1 { -- pinctrl-names = "default"; -- /* pin shared with snfi */ -- pinctrl-0 = <&spic_pins>; -- status = "disabled"; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&pcie1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie1_pins>; -- status = "okay"; --}; -- --&pcie2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_pins>; -- status = "disabled"; --}; -- --&pcie3 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_pins>; -- status = "okay"; --}; -- --&pio { -- i2c0_pins: i2c0-pins-g0 { -- mux { -- function = "i2c"; -- groups = "i2c0_1"; -- }; -- }; -- -- i2c1_pins: i2c1-pins-g0 { -- mux { -- function = "i2c"; -- groups = "i2c1_0"; -- }; -- }; -- -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", -- "pcie_wake_n0_0"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", -- "pcie_wake_n1_0"; -- }; -- }; -- -- pcie2_pins: pcie2-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", -- "pcie_wake_n2_0"; -- }; -- }; -- -- pcie3_pins: pcie3-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", -- "pcie_wake_n3_0"; -- }; -- }; -- -- spi0_flash_pins: spi0-pins { -- mux { -- function = "spi"; -- groups = "spi0", "spi0_wp_hold"; -- }; -- }; -- -- spic_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1_1"; -- }; -- }; --}; -- --&watchdog { -- status = "disabled"; --}; -- --ð { -- status = "okay"; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "2500base-x"; -- phy-handle = <&phy13>; -- }; -- -- gmac2: mac@2 { -- compatible = "mediatek,eth-mac"; -- reg = <2>; -- phy-mode = "2500base-x"; -- phy-handle = <&phy5>; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- -- phy5: phy@5 { -- compatible = "ethernet-phy-ieee802.3-c45"; -- reg = <5>; -- reset-gpios = <&pio 0 1>; -- reset-assert-us = <600>; -- reset-deassert-us = <20000>; -- }; -- -- phy13: phy@13 { -- compatible = "ethernet-phy-ieee802.3-c45"; -- reg = <13>; -- reset-gpios = <&pio 1 1>; -- reset-assert-us = <600>; -- reset-deassert-us = <20000>; -- }; -- -- switch@0 { -- compatible = "mediatek,mt7988"; -- reg = <31>; -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@0 { -- reg = <0>; -- label = "lan0"; -- }; -- -- port@1 { -- reg = <1>; -- label = "lan1"; -- }; -- -- port@2 { -- reg = <2>; -- label = "lan2"; -- }; -- -- port@3 { -- reg = <3>; -- label = "lan3"; -- }; -- -- port@6 { -- reg = <6>; -- label = "cpu"; -- ethernet = <&gmac0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <10000>; -- full-duplex; -- pause; -- }; -- }; -- }; -- }; -- }; --}; -- --&hnat { -- mtketh-wan = "eth1"; -- mtketh-lan = "lan"; -- mtketh-lan2 = "eth2"; -- mtketh-max-gmac = <3>; -- status = "okay"; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts 2023-02-26 09:01:19.911972900 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,282 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) --/* -- * Copyright (C) 2021 MediaTek Inc. -- * Author: Sam.Shih -- */ -- --/dts-v1/; --#include "mt7988.dtsi" -- --/ { -- model = "MediaTek MT7988 DSA internal-2.5G SPIM-NAND RFB"; -- compatible = "mediatek,mt7988a-dsa-i2p5g-spim-snand", -- /* Reserve this for DVFS if creating new dts */ -- "mediatek,mt7988"; -- -- chosen { -- bootargs = "console=ttyS0,115200n1 loglevel=8 \ -- earlycon=uart8250,mmio32,0x11000000 \ -- pci=pcie_bus_perf"; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x10000000>; -- }; -- -- nmbm_spim_nand { -- compatible = "generic,nmbm"; -- -- #address-cells = <1>; -- #size-cells = <1>; -- -- lower-mtd-device = <&spi_nand>; -- forced-create; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "BL2"; -- reg = <0x00000 0x0100000>; -- read-only; -- }; -- -- partition@100000 { -- label = "u-boot-env"; -- reg = <0x0100000 0x0080000>; -- }; -- -- factory: partition@180000 { -- label = "Factory"; -- reg = <0x180000 0x0400000>; -- }; -- -- partition@580000 { -- label = "FIP"; -- reg = <0x580000 0x0200000>; -- }; -- -- partition@780000 { -- label = "ubi"; -- reg = <0x780000 0x4000000>; -- }; -- }; -- }; -- -- wsys_adie: wsys_adie@0 { -- // fpga cases need to manual change adie_id / sku_type for dvt only -- compatible = "mediatek,rebb-mt7988-adie"; -- adie_id = <7976>; -- sku_type = <3000>; -- }; --}; -- --&uart0 { -- status = "okay"; --}; -- --&spi0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi0_flash_pins>; -- status = "okay"; -- -- spi_nand: spi_nand@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "spi-nand"; -- spi-cal-enable; -- spi-cal-mode = "read-data"; -- spi-cal-datalen = <7>; -- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; -- spi-cal-addrlen = <5>; -- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; -- reg = <0>; -- spi-max-frequency = <52000000>; -- spi-tx-buswidth = <4>; -- spi-rx-buswidth = <4>; -- }; --}; -- --&spi1 { -- pinctrl-names = "default"; -- /* pin shared with snfi */ -- pinctrl-0 = <&spic_pins>; -- status = "disabled"; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&pcie1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie1_pins>; -- status = "okay"; --}; -- --&pcie2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_pins>; -- status = "disabled"; --}; -- --&pcie3 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_pins>; -- status = "okay"; --}; -- --&pio { -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", -- "pcie_wake_n0_0"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", -- "pcie_wake_n1_0"; -- }; -- }; -- -- pcie2_pins: pcie2-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", -- "pcie_wake_n2_0"; -- }; -- }; -- -- pcie3_pins: pcie3-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", -- "pcie_wake_n3_0"; -- }; -- }; -- -- spi0_flash_pins: spi0-pins { -- mux { -- function = "spi"; -- groups = "spi0", "spi0_wp_hold"; -- }; -- }; -- -- spic_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1_1"; -- }; -- }; --}; -- --&watchdog { -- status = "disabled"; --}; -- --&usxgmiisys1 { -- internal_2500; --}; -- --ð { -- status = "okay"; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy0>; -- }; -- -- gmac2: mac@2 { -- compatible = "mediatek,eth-mac"; -- reg = <2>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy1>; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- phy0: ethernet-phy@0 { -- reg = <15>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- phy-mode = "10gbase-kr"; -- }; -- -- phy1: ethernet-phy@8 { -- reg = <8>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- }; -- -- switch@0 { -- compatible = "mediatek,mt7988"; -- reg = <31>; -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@0 { -- reg = <0>; -- label = "lan0"; -- }; -- -- port@1 { -- reg = <1>; -- label = "lan1"; -- }; -- -- port@2 { -- reg = <2>; -- label = "lan2"; -- }; -- -- port@3 { -- reg = <3>; -- label = "lan3"; -- }; -- -- port@6 { -- reg = <6>; -- label = "cpu"; -- ethernet = <&gmac0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <10000>; -- full-duplex; -- pause; -- }; -- }; -- }; -- }; -- }; --}; -- --&hnat { -- mtketh-wan = "eth1"; -- mtketh-lan = "lan"; -- mtketh-lan2 = "eth2"; -- mtketh-max-gmac = <3>; -- status = "okay"; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-sfp-spim-nand.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-sfp-spim-nand.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-sfp-spim-nand.dts 2023-02-26 09:01:19.911972900 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-sfp-spim-nand.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,405 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) --/* -- * Copyright (C) 2021 MediaTek Inc. -- * Author: Sam.Shih -- */ -- --/dts-v1/; --#include "mt7988.dtsi" -- --/ { -- model = "MediaTek MT7988 GSW 10G SFP SPIM-NAND RFB"; -- compatible = "mediatek,mt7988a-gsw-10g-sfp-spim-snand", -- /* Reserve this for DVFS if creating new dts */ -- "mediatek,mt7988"; -- -- chosen { -- bootargs = "console=ttyS0,115200n1 loglevel=8 \ -- earlycon=uart8250,mmio32,0x11000000"; -- }; -- -- gsw: gsw@0 { -- compatible = "mediatek,mt753x"; -- mediatek,sysctrl = <ðwarp>; -- #address-cells = <1>; -- #size-cells = <0>; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x10000000>; -- }; -- -- nmbm_spim_nand { -- compatible = "generic,nmbm"; -- -- #address-cells = <1>; -- #size-cells = <1>; -- -- lower-mtd-device = <&spi_nand>; -- forced-create; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "BL2"; -- reg = <0x00000 0x0100000>; -- read-only; -- }; -- -- partition@100000 { -- label = "u-boot-env"; -- reg = <0x0100000 0x0080000>; -- }; -- -- factory: partition@180000 { -- label = "Factory"; -- reg = <0x180000 0x0400000>; -- }; -- -- partition@580000 { -- label = "FIP"; -- reg = <0x580000 0x0200000>; -- }; -- -- partition@780000 { -- label = "ubi"; -- reg = <0x780000 0x4000000>; -- }; -- }; -- }; -- -- wsys_adie: wsys_adie@0 { -- // fpga cases need to manual change adie_id / sku_type for dvt only -- compatible = "mediatek,rebb-mt7988-adie"; -- adie_id = <7976>; -- sku_type = <3000>; -- }; -- -- sfp_esp0: sfp@0 { -- compatible = "sff,sfp"; -- i2c-bus = <&i2c2>; -- tx-disable-gpios = <&pio 29 0>; -- }; -- -- sfp_esp1: sfp@1 { -- compatible = "sff,sfp"; -- i2c-bus = <&i2c1>; -- tx-disable-gpios = <&pio 36 0>; -- }; --}; -- --&fan { -- pwms = <&pwm 0 50000 0>; -- status = "okay"; --}; -- --&i2c0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c0_pins>; -- status = "okay"; -- -- rt5190a_64: rt5190a@64 { -- compatible = "richtek,rt5190a"; -- reg = <0x64>; -- /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ -- vin2-supply = <&rt5190_buck1>; -- vin3-supply = <&rt5190_buck1>; -- vin4-supply = <&rt5190_buck1>; -- -- regulators { -- rt5190_buck1: buck1 { -- regulator-name = "rt5190a-buck1"; -- regulator-min-microvolt = <5090000>; -- regulator-max-microvolt = <5090000>; -- regulator-allowed-modes = -- ; -- regulator-boot-on; -- }; -- buck2 { -- regulator-name = "vcore"; -- regulator-min-microvolt = <600000>; -- regulator-max-microvolt = <1400000>; -- regulator-boot-on; -- }; -- buck3 { -- regulator-name = "proc"; -- regulator-min-microvolt = <600000>; -- regulator-max-microvolt = <1400000>; -- regulator-boot-on; -- }; -- buck4 { -- regulator-name = "rt5190a-buck4"; -- regulator-min-microvolt = <850000>; -- regulator-max-microvolt = <850000>; -- regulator-allowed-modes = -- ; -- regulator-boot-on; -- }; -- ldo { -- regulator-name = "rt5190a-ldo"; -- regulator-min-microvolt = <1200000>; -- regulator-max-microvolt = <1200000>; -- regulator-boot-on; -- }; -- }; -- }; --}; -- --&i2c1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c1_pins>; -- status = "okay"; --}; -- --&i2c2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c2_pins>; -- status = "okay"; --}; -- --&pwm { -- status = "okay"; --}; -- --&uart0 { -- status = "okay"; --}; -- --&spi0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi0_flash_pins>; -- status = "okay"; -- -- spi_nand: spi_nand@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "spi-nand"; -- spi-cal-enable; -- spi-cal-mode = "read-data"; -- spi-cal-datalen = <7>; -- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; -- spi-cal-addrlen = <5>; -- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; -- reg = <0>; -- spi-max-frequency = <52000000>; -- spi-tx-buswidth = <4>; -- spi-rx-buswidth = <4>; -- }; --}; -- --&spi1 { -- pinctrl-names = "default"; -- /* pin shared with snfi */ -- pinctrl-0 = <&spic_pins>; -- status = "disabled"; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&pcie1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie1_pins>; -- status = "okay"; --}; -- --&pcie2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_pins>; -- status = "disabled"; --}; -- --&pcie3 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_pins>; -- status = "okay"; --}; -- --&pio { -- i2c0_pins: i2c0-pins-g0 { -- mux { -- function = "i2c"; -- groups = "i2c0_1"; -- }; -- }; -- -- i2c1_pins: i2c1-pins-g0 { -- mux { -- function = "i2c"; -- groups = "i2c1_sfp"; -- }; -- }; -- -- i2c2_pins: i2c2-pins-g0 { -- mux { -- function = "i2c"; -- groups = "i2c2_0"; -- }; -- }; -- -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", -- "pcie_wake_n0_0"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", -- "pcie_wake_n1_0"; -- }; -- }; -- -- pcie2_pins: pcie2-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", -- "pcie_wake_n2_0"; -- }; -- }; -- -- pcie3_pins: pcie3-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", -- "pcie_wake_n3_0"; -- }; -- }; -- -- spi0_flash_pins: spi0-pins { -- mux { -- function = "spi"; -- groups = "spi0", "spi0_wp_hold"; -- }; -- }; -- -- spic_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1_1"; -- }; -- }; --}; -- --&watchdog { -- status = "disabled"; --}; -- --ð { -- status = "okay"; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "10gbase-kr"; -- managed = "in-band-status"; -- sfp = <&sfp_esp1>; -- }; -- -- gmac2: mac@2 { -- compatible = "mediatek,eth-mac"; -- reg = <2>; -- phy-mode = "10gbase-kr"; -- managed = "in-band-status"; -- sfp = <&sfp_esp0>; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- }; --}; -- --&hnat { -- mtketh-wan = "eth1"; -- mtketh-lan = "eth0"; -- mtketh-lan2 = "eth2"; -- mtketh-max-gmac = <3>; -- status = "okay"; --}; -- --&gsw { -- mediatek,mdio = <&mdio>; -- mediatek,portmap = "llllw"; -- mediatek,mdio_master_pinmux = <1>; -- interrupt-parent = <&gic>; -- interrupts = ; -- status = "okay"; -- -- port6: port@6 { -- compatible = "mediatek,mt753x-port"; -- mediatek,ssc-on; -- phy-mode = "10gbase-kr"; -- reg = <6>; -- fixed-link { -- speed = <2500>; -- full-duplex; -- }; -- }; -- -- mdio1: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- -- gsw_phy0: ethernet-phy@0 { -- compatible = "ethernet-phy-id03a2.9481"; -- reg = <0>; -- phy-mode = "gmii"; -- rext = "efuse"; -- tx_r50 = "efuse"; -- nvmem-cells = <&phy_calibration_p0>; -- nvmem-cell-names = "phy-cal-data"; -- }; -- -- gsw_phy1: ethernet-phy@1 { -- compatible = "ethernet-phy-id03a2.9481"; -- reg = <1>; -- phy-mode = "gmii"; -- rext = "efuse"; -- tx_r50 = "efuse"; -- nvmem-cells = <&phy_calibration_p1>; -- nvmem-cell-names = "phy-cal-data"; -- }; -- -- gsw_phy2: ethernet-phy@2 { -- compatible = "ethernet-phy-id03a2.9481"; -- reg = <2>; -- phy-mode = "gmii"; -- rext = "efuse"; -- tx_r50 = "efuse"; -- nvmem-cells = <&phy_calibration_p2>; -- nvmem-cell-names = "phy-cal-data"; -- }; -- -- gsw_phy3: ethernet-phy@3 { -- compatible = "ethernet-phy-id03a2.9481"; -- reg = <3>; -- phy-mode = "gmii"; -- rext = "efuse"; -- tx_r50 = "efuse"; -- nvmem-cells = <&phy_calibration_p3>; -- nvmem-cell-names = "phy-cal-data"; -- }; -- }; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand.dts 2023-02-26 09:01:19.913974400 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,395 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) --/* -- * Copyright (C) 2021 MediaTek Inc. -- * Author: Sam.Shih -- */ -- --/dts-v1/; -- --#include "mt7988.dtsi" -- --/ { -- model = "MediaTek MT7988 GSW 10G SPIM-NAND RFB"; -- compatible = "mediatek,mt7988a-gsw-10g-spim-snand", -- /* Reserve this for DVFS if creating new dts */ -- "mediatek,mt7988"; -- -- chosen { -- bootargs = "console=ttyS0,115200n1 loglevel=8 \ -- earlycon=uart8250,mmio32,0x11000000 \ -- pci=pcie_bus_perf"; -- }; -- -- gsw: gsw@0 { -- compatible = "mediatek,mt753x"; -- mediatek,sysctrl = <ðwarp>; -- #address-cells = <1>; -- #size-cells = <0>; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x10000000>; -- }; -- -- nmbm_spim_nand { -- compatible = "generic,nmbm"; -- -- #address-cells = <1>; -- #size-cells = <1>; -- -- lower-mtd-device = <&spi_nand>; -- forced-create; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "BL2"; -- reg = <0x00000 0x0100000>; -- read-only; -- }; -- -- partition@100000 { -- label = "u-boot-env"; -- reg = <0x0100000 0x0080000>; -- }; -- -- factory: partition@180000 { -- label = "Factory"; -- reg = <0x180000 0x0400000>; -- }; -- -- partition@580000 { -- label = "FIP"; -- reg = <0x580000 0x0200000>; -- }; -- -- partition@780000 { -- label = "ubi"; -- reg = <0x780000 0x4000000>; -- }; -- }; -- }; -- -- wsys_adie: wsys_adie@0 { -- // fpga cases need to manual change adie_id / sku_type for dvt only -- compatible = "mediatek,rebb-mt7988-adie"; -- adie_id = <7976>; -- sku_type = <3000>; -- }; --}; -- --&fan { -- pwms = <&pwm 0 50000 0>; -- status = "okay"; --}; -- --&i2c0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c0_pins>; -- status = "okay"; -- -- rt5190a_64: rt5190a@64 { -- compatible = "richtek,rt5190a"; -- reg = <0x64>; -- /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ -- vin2-supply = <&rt5190_buck1>; -- vin3-supply = <&rt5190_buck1>; -- vin4-supply = <&rt5190_buck1>; -- -- regulators { -- rt5190_buck1: buck1 { -- regulator-name = "rt5190a-buck1"; -- regulator-min-microvolt = <5090000>; -- regulator-max-microvolt = <5090000>; -- regulator-allowed-modes = -- ; -- regulator-boot-on; -- }; -- buck2 { -- regulator-name = "vcore"; -- regulator-min-microvolt = <600000>; -- regulator-max-microvolt = <1400000>; -- regulator-boot-on; -- }; -- buck3 { -- regulator-name = "proc"; -- regulator-min-microvolt = <600000>; -- regulator-max-microvolt = <1400000>; -- regulator-boot-on; -- }; -- buck4 { -- regulator-name = "rt5190a-buck4"; -- regulator-min-microvolt = <850000>; -- regulator-max-microvolt = <850000>; -- regulator-allowed-modes = -- ; -- regulator-boot-on; -- }; -- ldo { -- regulator-name = "rt5190a-ldo"; -- regulator-min-microvolt = <1200000>; -- regulator-max-microvolt = <1200000>; -- regulator-boot-on; -- }; -- }; -- }; --}; -- --&i2c1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c1_pins>; -- status = "okay"; --}; -- --&pwm { -- status = "okay"; --}; -- --&uart0 { -- status = "okay"; --}; -- --&spi0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi0_flash_pins>; -- status = "okay"; -- -- spi_nand: spi_nand@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "spi-nand"; -- spi-cal-enable; -- spi-cal-mode = "read-data"; -- spi-cal-datalen = <7>; -- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; -- spi-cal-addrlen = <5>; -- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; -- reg = <0>; -- spi-max-frequency = <52000000>; -- spi-tx-buswidth = <4>; -- spi-rx-buswidth = <4>; -- }; --}; -- --&spi1 { -- pinctrl-names = "default"; -- /* pin shared with snfi */ -- pinctrl-0 = <&spic_pins>; -- status = "disabled"; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&pcie1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie1_pins>; -- status = "okay"; --}; -- --&pcie2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_pins>; -- status = "disabled"; --}; -- --&pcie3 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_pins>; -- status = "okay"; --}; -- --&pio { -- i2c0_pins: i2c0-pins-g0 { -- mux { -- function = "i2c"; -- groups = "i2c0_1"; -- }; -- }; -- -- i2c1_pins: i2c1-pins-g0 { -- mux { -- function = "i2c"; -- groups = "i2c1_0"; -- }; -- }; -- -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", -- "pcie_wake_n0_0"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", -- "pcie_wake_n1_0"; -- }; -- }; -- -- pcie2_pins: pcie2-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", -- "pcie_wake_n2_0"; -- }; -- }; -- -- pcie3_pins: pcie3-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", -- "pcie_wake_n3_0"; -- }; -- }; -- -- spi0_flash_pins: spi0-pins { -- mux { -- function = "spi"; -- groups = "spi0", "spi0_wp_hold"; -- }; -- }; -- -- spic_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1_1"; -- }; -- }; --}; -- --&watchdog { -- status = "disabled"; --}; -- --ð { -- status = "okay"; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy0>; -- }; -- -- gmac2: mac@2 { -- compatible = "mediatek,eth-mac"; -- reg = <2>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy1>; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- phy0: ethernet-phy@0 { -- reg = <0>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 71 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- -- phy1: ethernet-phy@8 { -- reg = <8>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 72 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- }; --}; -- --&hnat { -- mtketh-wan = "eth1"; -- mtketh-lan = "eth0"; -- mtketh-lan2 = "eth2"; -- mtketh-max-gmac = <3>; -- status = "okay"; --}; -- --&gsw { -- mediatek,mdio = <&mdio>; -- mediatek,portmap = "llllw"; -- mediatek,mdio_master_pinmux = <1>; -- interrupt-parent = <&gic>; -- interrupts = ; -- status = "okay"; -- -- port6: port@6 { -- compatible = "mediatek,mt753x-port"; -- mediatek,ssc-on; -- phy-mode = "10gbase-kr"; -- reg = <6>; -- fixed-link { -- speed = <2500>; -- full-duplex; -- }; -- }; -- -- mdio1: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- -- gsw_phy0: ethernet-phy@0 { -- compatible = "ethernet-phy-id03a2.9481"; -- reg = <0>; -- phy-mode = "gmii"; -- rext = "efuse"; -- tx_r50 = "efuse"; -- nvmem-cells = <&phy_calibration_p0>; -- nvmem-cell-names = "phy-cal-data"; -- }; -- -- gsw_phy1: ethernet-phy@1 { -- compatible = "ethernet-phy-id03a2.9481"; -- reg = <1>; -- phy-mode = "gmii"; -- rext = "efuse"; -- tx_r50 = "efuse"; -- nvmem-cells = <&phy_calibration_p1>; -- nvmem-cell-names = "phy-cal-data"; -- }; -- -- gsw_phy2: ethernet-phy@2 { -- compatible = "ethernet-phy-id03a2.9481"; -- reg = <2>; -- phy-mode = "gmii"; -- rext = "efuse"; -- tx_r50 = "efuse"; -- nvmem-cells = <&phy_calibration_p2>; -- nvmem-cell-names = "phy-cal-data"; -- }; -- -- gsw_phy3: ethernet-phy@3 { -- compatible = "ethernet-phy-id03a2.9481"; -- reg = <3>; -- phy-mode = "gmii"; -- rext = "efuse"; -- tx_r50 = "efuse"; -- nvmem-cells = <&phy_calibration_p3>; -- nvmem-cell-names = "phy-cal-data"; -- }; -- }; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand-4pcie.dts openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand-4pcie.dts ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand-4pcie.dts 2023-02-26 09:01:19.912971600 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand-4pcie.dts 1970-01-01 08:00:00.000000000 +0800 -@@ -1,398 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0 OR MIT) --/* -- * Copyright (C) 2021 MediaTek Inc. -- * Author: Sam.Shih -- */ -- --/dts-v1/; --#include "mt7988.dtsi" -- --/ { -- model = "MediaTek MT7988 GSW 10G SPIM-NAND 4PCIe RFB"; -- compatible = "mediatek,mt7988a-gsw-10g-spim-snand-4pcie", -- /* Reserve this for DVFS if creating new dts */ -- "mediatek,mt7988"; -- -- chosen { -- bootargs = "console=ttyS0,115200n1 loglevel=8 \ -- earlycon=uart8250,mmio32,0x11000000 \ -- pci=pcie_bus_perf"; -- }; -- -- gsw: gsw@0 { -- compatible = "mediatek,mt753x"; -- mediatek,sysctrl = <ðwarp>; -- #address-cells = <1>; -- #size-cells = <0>; -- }; -- -- memory { -- reg = <0 0x40000000 0 0x10000000>; -- }; -- -- nmbm_spim_nand { -- compatible = "generic,nmbm"; -- -- #address-cells = <1>; -- #size-cells = <1>; -- -- lower-mtd-device = <&spi_nand>; -- forced-create; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "BL2"; -- reg = <0x00000 0x0100000>; -- read-only; -- }; -- -- partition@100000 { -- label = "u-boot-env"; -- reg = <0x0100000 0x0080000>; -- }; -- -- factory: partition@180000 { -- label = "Factory"; -- reg = <0x180000 0x0400000>; -- }; -- -- partition@580000 { -- label = "FIP"; -- reg = <0x580000 0x0200000>; -- }; -- -- partition@780000 { -- label = "ubi"; -- reg = <0x780000 0x4000000>; -- }; -- }; -- }; -- -- wsys_adie: wsys_adie@0 { -- // fpga cases need to manual change adie_id / sku_type for dvt only -- compatible = "mediatek,rebb-mt7988-adie"; -- adie_id = <7976>; -- sku_type = <3000>; -- }; --}; -- --&fan { -- pwms = <&pwm 0 50000 0>; -- status = "okay"; --}; -- --&i2c0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c0_pins>; -- status = "okay"; -- -- rt5190a_64: rt5190a@64 { -- compatible = "richtek,rt5190a"; -- reg = <0x64>; -- /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ -- vin2-supply = <&rt5190_buck1>; -- vin3-supply = <&rt5190_buck1>; -- vin4-supply = <&rt5190_buck1>; -- -- regulators { -- rt5190_buck1: buck1 { -- regulator-name = "rt5190a-buck1"; -- regulator-min-microvolt = <5090000>; -- regulator-max-microvolt = <5090000>; -- regulator-allowed-modes = -- ; -- regulator-boot-on; -- }; -- buck2 { -- regulator-name = "vcore"; -- regulator-min-microvolt = <600000>; -- regulator-max-microvolt = <1400000>; -- regulator-boot-on; -- }; -- buck3 { -- regulator-name = "proc"; -- regulator-min-microvolt = <600000>; -- regulator-max-microvolt = <1400000>; -- regulator-boot-on; -- }; -- buck4 { -- regulator-name = "rt5190a-buck4"; -- regulator-min-microvolt = <850000>; -- regulator-max-microvolt = <850000>; -- regulator-allowed-modes = -- ; -- regulator-boot-on; -- }; -- ldo { -- regulator-name = "rt5190a-ldo"; -- regulator-min-microvolt = <1200000>; -- regulator-max-microvolt = <1200000>; -- regulator-boot-on; -- }; -- }; -- }; --}; -- --&i2c1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c1_pins>; -- status = "okay"; --}; -- --&pwm { -- status = "okay"; --}; -- --&uart0 { -- status = "okay"; --}; -- --&spi0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi0_flash_pins>; -- status = "okay"; -- -- spi_nand: spi_nand@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "spi-nand"; -- spi-cal-enable; -- spi-cal-mode = "read-data"; -- spi-cal-datalen = <7>; -- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; -- spi-cal-addrlen = <5>; -- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; -- reg = <0>; -- spi-max-frequency = <52000000>; -- spi-tx-buswidth = <4>; -- spi-rx-buswidth = <4>; -- }; --}; -- --&spi1 { -- pinctrl-names = "default"; -- /* pin shared with snfi */ -- pinctrl-0 = <&spic_pins>; -- status = "disabled"; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -- status = "okay"; --}; -- --&pcie1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie1_pins>; -- status = "okay"; --}; -- --&pcie2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_pins>; -- status = "okay"; --}; -- --&pcie3 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_pins>; -- status = "okay"; --}; -- --&pio { -- i2c0_pins: i2c0-pins-g0 { -- mux { -- function = "i2c"; -- groups = "i2c0_1"; -- }; -- }; -- -- i2c1_pins: i2c1-pins-g0 { -- mux { -- function = "i2c"; -- groups = "i2c1_0"; -- }; -- }; -- -- pcie0_pins: pcie0-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", -- "pcie_wake_n0_0"; -- }; -- }; -- -- pcie1_pins: pcie1-pins { -- mux { -- function = "pcie"; -- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", -- "pcie_wake_n1_0"; -- }; -- }; -- -- pcie2_pins: pcie2-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", -- "pcie_wake_n2_0"; -- }; -- }; -- -- pcie3_pins: pcie3-pins { -- mux { -- function = "pcie"; -- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", -- "pcie_wake_n3_0"; -- }; -- }; -- -- spi0_flash_pins: spi0-pins { -- mux { -- function = "spi"; -- groups = "spi0", "spi0_wp_hold"; -- }; -- }; -- -- spic_pins: spi1-pins { -- mux { -- function = "spi"; -- groups = "spi1_1"; -- }; -- }; --}; -- --&watchdog { -- status = "disabled"; --}; -- --&xhci0 { -- status = "disabled"; --}; -- --ð { -- status = "okay"; -- -- gmac0: mac@0 { -- compatible = "mediatek,eth-mac"; -- reg = <0>; -- phy-mode = "10gbase-kr"; -- -- fixed-link { -- speed = <2500>; -- full-duplex; -- pause; -- }; -- }; -- -- gmac1: mac@1 { -- compatible = "mediatek,eth-mac"; -- reg = <1>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy0>; -- }; -- -- gmac2: mac@2 { -- compatible = "mediatek,eth-mac"; -- reg = <2>; -- phy-mode = "10gbase-kr"; -- phy-handle = <&phy1>; -- }; -- -- mdio: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- phy0: ethernet-phy@0 { -- reg = <0>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 71 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- -- phy1: ethernet-phy@8 { -- reg = <8>; -- compatible = "ethernet-phy-ieee802.3-c45"; -- reset-gpios = <&pio 72 1>; -- reset-assert-us = <1000000>; -- reset-deassert-us = <1000000>; -- }; -- }; --}; -- --&hnat { -- mtketh-wan = "eth1"; -- mtketh-lan = "eth0"; -- mtketh-lan2 = "eth2"; -- mtketh-max-gmac = <3>; -- status = "okay"; --}; -- --&gsw { -- mediatek,mdio = <&mdio>; -- mediatek,portmap = "llllw"; -- mediatek,mdio_master_pinmux = <1>; -- interrupt-parent = <&gic>; -- interrupts = ; -- status = "okay"; -- -- port6: port@6 { -- compatible = "mediatek,mt753x-port"; -- mediatek,ssc-on; -- phy-mode = "10gbase-kr"; -- reg = <6>; -- fixed-link { -- speed = <2500>; -- full-duplex; -- }; -- }; -- -- mdio1: mdio-bus { -- #address-cells = <1>; -- #size-cells = <0>; -- -- gsw_phy0: ethernet-phy@0 { -- compatible = "ethernet-phy-id03a2.9481"; -- reg = <0>; -- phy-mode = "gmii"; -- rext = "efuse"; -- tx_r50 = "efuse"; -- nvmem-cells = <&phy_calibration_p0>; -- nvmem-cell-names = "phy-cal-data"; -- }; -- -- gsw_phy1: ethernet-phy@1 { -- compatible = "ethernet-phy-id03a2.9481"; -- reg = <1>; -- phy-mode = "gmii"; -- rext = "efuse"; -- tx_r50 = "efuse"; -- nvmem-cells = <&phy_calibration_p1>; -- nvmem-cell-names = "phy-cal-data"; -- }; -- -- gsw_phy2: ethernet-phy@2 { -- compatible = "ethernet-phy-id03a2.9481"; -- reg = <2>; -- phy-mode = "gmii"; -- rext = "efuse"; -- tx_r50 = "efuse"; -- nvmem-cells = <&phy_calibration_p2>; -- nvmem-cell-names = "phy-cal-data"; -- }; -- -- gsw_phy3: ethernet-phy@3 { -- compatible = "ethernet-phy-id03a2.9481"; -- reg = <3>; -- phy-mode = "gmii"; -- rext = "efuse"; -- tx_r50 = "efuse"; -- nvmem-cells = <&phy_calibration_p3>; -- nvmem-cell-names = "phy-cal-data"; -- }; -- }; --}; -diff -uNpar immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi ---- immortalwrt-mt798x/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi 2023-02-26 09:01:19.906972700 +0800 -+++ openwrt/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi 1970-01-01 08:00:00.000000000 +0800 -@@ -1,386 +0,0 @@ --/* -- * Copyright (c) 2022 MediaTek Inc. -- * Author: Author: Xiufeng Li -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License version 2 as -- * published by the Free Software Foundation. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- */ -- --&clkitg { -- bring-up { -- compatible = "mediatek,clk-bring-up"; -- clocks = -- <&apmixedsys CK_APMIXED_NETSYSPLL>, -- <&apmixedsys CK_APMIXED_MPLL>, -- <&apmixedsys CK_APMIXED_MMPLL>, -- <&apmixedsys CK_APMIXED_APLL2>, -- <&apmixedsys CK_APMIXED_NET1PLL>, -- <&apmixedsys CK_APMIXED_NET2PLL>, -- <&apmixedsys CK_APMIXED_WEDMCUPLL>, -- <&apmixedsys CK_APMIXED_SGMPLL>, -- <&apmixedsys CK_APMIXED_ARM_B>, -- <&apmixedsys CK_APMIXED_CCIPLL2_B>, -- <&apmixedsys CK_APMIXED_USXGMIIPLL>, -- <&apmixedsys CK_APMIXED_MSDCPLL>, -- <&topckgen CK_TOP_CB_CKSQ_40M>, -- <&topckgen CK_TOP_CB_M_416M>, -- <&topckgen CK_TOP_CB_M_D2>, -- <&topckgen CK_TOP_M_D3_D2>, -- <&topckgen CK_TOP_CB_M_D4>, -- <&topckgen CK_TOP_CB_M_D8>, -- <&topckgen CK_TOP_M_D8_D2>, -- <&topckgen CK_TOP_CB_MM_720M>, -- <&topckgen CK_TOP_CB_MM_D2>, -- <&topckgen CK_TOP_CB_MM_D3_D5>, -- <&topckgen CK_TOP_CB_MM_D4>, -- <&topckgen CK_TOP_MM_D6_D2>, -- <&topckgen CK_TOP_CB_MM_D8>, -- <&topckgen CK_TOP_CB_APLL2_196M>, -- <&topckgen CK_TOP_CB_APLL2_D4>, -- <&topckgen CK_TOP_CB_NET1_D4>, -- <&topckgen CK_TOP_CB_NET1_D5>, -- <&topckgen CK_TOP_NET1_D5_D2>, -- <&topckgen CK_TOP_NET1_D5_D4>, -- <&topckgen CK_TOP_CB_NET1_D8>, -- <&topckgen CK_TOP_NET1_D8_D2>, -- <&topckgen CK_TOP_NET1_D8_D4>, -- <&topckgen CK_TOP_NET1_D8_D8>, -- <&topckgen CK_TOP_NET1_D8_D16>, -- <&topckgen CK_TOP_CB_NET2_800M>, -- <&topckgen CK_TOP_CB_NET2_D2>, -- <&topckgen CK_TOP_CB_NET2_D4>, -- <&topckgen CK_TOP_NET2_D4_D4>, -- <&topckgen CK_TOP_NET2_D4_D8>, -- <&topckgen CK_TOP_CB_NET2_D6>, -- <&topckgen CK_TOP_CB_NET2_D8>, -- <&topckgen CK_TOP_CB_WEDMCU_208M>, -- <&topckgen CK_TOP_CB_SGM_325M>, -- <&topckgen CK_TOP_CB_NETSYS_850M>, -- <&topckgen CK_TOP_CB_MSDC_400M>, -- <&topckgen CK_TOP_CKSQ_40M_D2>, -- <&topckgen CK_TOP_CB_RTC_32K>, -- <&topckgen CK_TOP_CB_RTC_32P7K>, -- <&topckgen CK_TOP_INFRA_F32K>, -- <&topckgen CK_TOP_CKSQ_SRC>, -- <&topckgen CK_TOP_NETSYS_2X>, -- <&topckgen CK_TOP_NETSYS_GSW>, -- <&topckgen CK_TOP_NETSYS_WED_MCU>, -- <&topckgen CK_TOP_EIP197>, -- <&topckgen CK_TOP_EMMC_250M>, -- <&topckgen CK_TOP_EMMC_400M>, -- <&topckgen CK_TOP_SPI>, -- <&topckgen CK_TOP_SPIM_MST>, -- <&topckgen CK_TOP_NFI1X>, -- <&topckgen CK_TOP_SPINFI_BCK>, -- <&topckgen CK_TOP_I2C_BCK>, -- <&topckgen CK_TOP_USB_SYS>, -- <&topckgen CK_TOP_USB_SYS_P1>, -- <&topckgen CK_TOP_USB_XHCI>, -- <&topckgen CK_TOP_USB_XHCI_P1>, -- <&topckgen CK_TOP_USB_FRMCNT>, -- <&topckgen CK_TOP_USB_FRMCNT_P1>, -- <&topckgen CK_TOP_AUD>, -- <&topckgen CK_TOP_A1SYS>, -- <&topckgen CK_TOP_AUD_L>, -- <&topckgen CK_TOP_A_TUNER>, -- <&topckgen CK_TOP_SYSAXI>, -- <&topckgen CK_TOP_INFRA_F26M>, -- <&topckgen CK_TOP_USB_REF>, -- <&topckgen CK_TOP_USB_CK_P1>, -- <&topckgen CK_TOP_AUD_I2S_M>, -- <&topckgen CK_TOP_NETSYS_SEL>, -- <&topckgen CK_TOP_NETSYS_500M_SEL>, -- <&topckgen CK_TOP_NETSYS_2X_SEL>, -- <&topckgen CK_TOP_NETSYS_GSW_SEL>, -- <&topckgen CK_TOP_ETH_GMII_SEL>, -- <&topckgen CK_TOP_NETSYS_MCU_SEL>, -- <&topckgen CK_TOP_NETSYS_PAO_2X_SEL>, -- <&topckgen CK_TOP_EIP197_SEL>, -- <&topckgen CK_TOP_AXI_INFRA_SEL>, -- <&topckgen CK_TOP_UART_SEL>, -- <&topckgen CK_TOP_EMMC_250M_SEL>, -- <&topckgen CK_TOP_EMMC_400M_SEL>, -- <&topckgen CK_TOP_SPI_SEL>, -- <&topckgen CK_TOP_SPIM_MST_SEL>, -- <&topckgen CK_TOP_NFI1X_SEL>, -- <&topckgen CK_TOP_SPINFI_SEL>, -- <&topckgen CK_TOP_PWM_SEL>, -- <&topckgen CK_TOP_I2C_SEL>, -- <&topckgen CK_TOP_PCIE_MBIST_250M_SEL>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&topckgen CK_TOP_USB_SYS_SEL>, -- <&topckgen CK_TOP_USB_SYS_P1_SEL>, -- <&topckgen CK_TOP_USB_XHCI_SEL>, -- <&topckgen CK_TOP_USB_XHCI_P1_SEL>, -- <&topckgen CK_TOP_USB_FRMCNT_SEL>, -- <&topckgen CK_TOP_USB_FRMCNT_P1_SEL>, -- <&topckgen CK_TOP_AUD_SEL>, -- <&topckgen CK_TOP_A1SYS_SEL>, -- <&topckgen CK_TOP_AUD_L_SEL>, -- <&topckgen CK_TOP_A_TUNER_SEL>, -- <&topckgen CK_TOP_SSPXTP_SEL>, -- <&topckgen CK_TOP_USB_PHY_SEL>, -- <&topckgen CK_TOP_USXGMII_SBUS_0_SEL>, -- <&topckgen CK_TOP_USXGMII_SBUS_1_SEL>, -- <&topckgen CK_TOP_SGM_0_SEL>, -- <&topckgen CK_TOP_SGM_SBUS_0_SEL>, -- <&topckgen CK_TOP_SGM_1_SEL>, -- <&topckgen CK_TOP_SGM_SBUS_1_SEL>, -- <&topckgen CK_TOP_XFI_PHY_0_XTAL_SEL>, -- <&topckgen CK_TOP_XFI_PHY_1_XTAL_SEL>, -- <&topckgen CK_TOP_SYSAXI_SEL>, -- <&topckgen CK_TOP_SYSAPB_SEL>, -- <&topckgen CK_TOP_ETH_REFCK_50M_SEL>, -- <&topckgen CK_TOP_ETH_SYS_200M_SEL>, -- <&topckgen CK_TOP_ETH_SYS_SEL>, -- <&topckgen CK_TOP_ETH_XGMII_SEL>, -- <&topckgen CK_TOP_BUS_TOPS_SEL>, -- <&topckgen CK_TOP_NPU_TOPS_SEL>, -- <&topckgen CK_TOP_DRAMC_SEL>, -- <&topckgen CK_TOP_DRAMC_MD32_SEL>, -- <&topckgen CK_TOP_INFRA_F26M_SEL>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&topckgen CK_TOP_DA_XTP_GLB_P0_SEL>, -- <&topckgen CK_TOP_DA_XTP_GLB_P1_SEL>, -- <&topckgen CK_TOP_DA_XTP_GLB_P2_SEL>, -- <&topckgen CK_TOP_DA_XTP_GLB_P3_SEL>, -- <&topckgen CK_TOP_CKM_SEL>, -- <&topckgen CK_TOP_DA_SELM_XTAL_SEL>, -- <&topckgen CK_TOP_PEXTP_SEL>, -- <&topckgen CK_TOP_TOPS_P2_26M_SEL>, -- <&topckgen CK_TOP_MCUSYS_BACKUP_625M_SEL>, -- <&topckgen CK_TOP_NETSYS_SYNC_250M_SEL>, -- <&topckgen CK_TOP_MACSEC_SEL>, -- <&topckgen CK_TOP_NETSYS_TOPS_400M_SEL>, -- <&topckgen CK_TOP_NETSYS_PPEFB_250M_SEL>, -- <&topckgen CK_TOP_NETSYS_WARP_SEL>, -- <&topckgen CK_TOP_ETH_MII_SEL>, -- <&topckgen CK_TOP_CK_NPU_SEL_CM_TOPS_SEL>, -- <&infracfg CK_INFRA_CK_F26M>, -- <&infracfg CK_INFRA_PWM_O>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&infracfg CK_INFRA_133M_HCK>, -- <&infracfg CK_INFRA_133M_PHCK>, -- <&infracfg CK_INFRA_66M_PHCK>, -- <&infracfg CK_INFRA_FAUD_L_O>, -- <&infracfg CK_INFRA_FAUD_AUD_O>, -- <&infracfg CK_INFRA_FAUD_EG2_O>, -- <&infracfg CK_INFRA_I2C_O>, -- <&infracfg CK_INFRA_UART_O0>, -- <&infracfg CK_INFRA_UART_O1>, -- <&infracfg CK_INFRA_UART_O2>, -- <&infracfg CK_INFRA_NFI_O>, -- <&infracfg CK_INFRA_SPINFI_O>, -- <&infracfg CK_INFRA_SPI0_O>, -- <&infracfg CK_INFRA_SPI1_O>, -- <&infracfg CK_INFRA_LB_MUX_FRTC>, -- <&infracfg CK_INFRA_FRTC>, -- <&infracfg CK_INFRA_FMSDC400_O>, -- <&infracfg CK_INFRA_FMSDC2_HCK_OCC>, -- <&infracfg CK_INFRA_PERI_133M>, -- <&infracfg CK_INFRA_USB_O>, -- <&infracfg CK_INFRA_USB_O_P1>, -- <&infracfg CK_INFRA_USB_FRMCNT_O>, -- <&infracfg CK_INFRA_USB_FRMCNT_O_P1>, -- <&infracfg CK_INFRA_USB_XHCI_O>, -- <&infracfg CK_INFRA_USB_XHCI_O_P1>, -- <&infracfg CK_INFRA_USB_PIPE_O>, -- <&infracfg CK_INFRA_USB_PIPE_O_P1>, -- <&infracfg CK_INFRA_USB_UTMI_O>, -- <&infracfg CK_INFRA_USB_UTMI_O_P1>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&infracfg CK_INFRA_F26M_O0>, -- <&infracfg CK_INFRA_F26M_O1>, -- <&infracfg CK_INFRA_133M_MCK>, -- <&infracfg CK_INFRA_66M_MCK>, -- <&infracfg CK_INFRA_PERI_66M_O>, -- <&infracfg CK_INFRA_USB_SYS_O>, -- <&infracfg CK_INFRA_USB_SYS_O_P1>, -- <&infracfg_ao CK_INFRA_66M_GPT_BCK>, -- <&infracfg_ao CK_INFRA_66M_PWM_HCK>, -- <&infracfg_ao CK_INFRA_66M_PWM_BCK>, -- <&infracfg_ao CK_INFRA_66M_PWM_CK1>, -- <&infracfg_ao CK_INFRA_66M_PWM_CK2>, -- <&infracfg_ao CK_INFRA_66M_PWM_CK3>, -- <&infracfg_ao CK_INFRA_66M_PWM_CK4>, -- <&infracfg_ao CK_INFRA_66M_PWM_CK5>, -- <&infracfg_ao CK_INFRA_66M_PWM_CK6>, -- <&infracfg_ao CK_INFRA_66M_PWM_CK7>, -- <&infracfg_ao CK_INFRA_66M_PWM_CK8>, -- <&infracfg_ao CK_INFRA_133M_CQDMA_BCK>, -- <&infracfg_ao CK_INFRA_66M_AUD_SLV_BCK>, -- <&infracfg_ao CK_INFRA_AUD_26M>, -- <&infracfg_ao CK_INFRA_AUD_L>, -- <&infracfg_ao CK_INFRA_AUD_AUD>, -- <&infracfg_ao CK_INFRA_AUD_EG2>, -- <&infracfg_ao CK_INFRA_DRAMC_F26M>, -- <&infracfg_ao CK_INFRA_133M_DBG_ACKM>, -- <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>, -- <&infracfg_ao CK_INFRA_66M_SEJ_BCK>, -- <&infracfg_ao CK_INFRA_PRE_CK_SEJ_F13M>, -- <&infracfg_ao CK_INFRA_66M_TRNG>, -- <&infracfg_ao CK_INFRA_26M_THERM_SYSTEM>, -- <&infracfg_ao CK_INFRA_I2C_BCK>, -- <&infracfg_ao CK_INFRA_66M_UART0_PCK>, -- <&infracfg_ao CK_INFRA_66M_UART1_PCK>, -- <&infracfg_ao CK_INFRA_66M_UART2_PCK>, -- <&infracfg_ao CK_INFRA_52M_UART0_CK>, -- <&infracfg_ao CK_INFRA_52M_UART1_CK>, -- <&infracfg_ao CK_INFRA_52M_UART2_CK>, -- <&infracfg_ao CK_INFRA_NFI>, -- <&infracfg_ao CK_INFRA_SPINFI>, -- <&infracfg_ao CK_INFRA_66M_NFI_HCK>, -- <&infracfg_ao CK_INFRA_104M_SPI0>, -- <&infracfg_ao CK_INFRA_104M_SPI1>, -- <&infracfg_ao CK_INFRA_104M_SPI2_BCK>, -- <&infracfg_ao CK_INFRA_66M_SPI0_HCK>, -- <&infracfg_ao CK_INFRA_66M_SPI1_HCK>, -- <&infracfg_ao CK_INFRA_66M_SPI2_HCK>, -- <&infracfg_ao CK_INFRA_66M_FLASHIF_AXI>, -- <&infracfg_ao CK_INFRA_RTC>, -- <&infracfg_ao CK_INFRA_26M_ADC_BCK>, -- <&infracfg_ao CK_INFRA_RC_ADC>, -- <&infracfg_ao CK_INFRA_MSDC400>, -- <&infracfg_ao CK_INFRA_MSDC2_HCK>, -- <&infracfg_ao CK_INFRA_133M_MSDC_0_HCK>, -- <&infracfg_ao CK_INFRA_66M_MSDC_0_HCK>, -- <&infracfg_ao CK_INFRA_133M_CPUM_BCK>, -- <&infracfg_ao CK_INFRA_BIST2FPC>, -- <&infracfg_ao CK_INFRA_I2C_X16W_MCK_CK_P1>, -- <&infracfg_ao CK_INFRA_I2C_X16W_PCK_CK_P1>, -- <&infracfg_ao CK_INFRA_133M_USB_HCK>, -- <&infracfg_ao CK_INFRA_133M_USB_HCK_CK_P1>, -- <&infracfg_ao CK_INFRA_66M_USB_HCK>, -- <&infracfg_ao CK_INFRA_66M_USB_HCK_CK_P1>, -- <&infracfg_ao CK_INFRA_USB_SYS>, -- <&infracfg_ao CK_INFRA_USB_SYS_CK_P1>, -- <&infracfg_ao CK_INFRA_USB_REF>, -- <&infracfg_ao CK_INFRA_USB_CK_P1>, -- <&infracfg_ao CK_INFRA_USB_FRMCNT>, -- <&infracfg_ao CK_INFRA_USB_FRMCNT_CK_P1>, -- <&infracfg_ao CK_INFRA_USB_PIPE>, -- <&infracfg_ao CK_INFRA_USB_PIPE_CK_P1>, -- <&infracfg_ao CK_INFRA_USB_UTMI>, -- <&infracfg_ao CK_INFRA_USB_UTMI_CK_P1>, -- <&infracfg_ao CK_INFRA_USB_XHCI>, -- <&infracfg_ao CK_INFRA_USB_XHCI_CK_P1>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&infracfg_ao CK_INFRA_MUX_UART0_SEL>, -- <&infracfg_ao CK_INFRA_MUX_UART1_SEL>, -- <&infracfg_ao CK_INFRA_MUX_UART2_SEL>, -- <&infracfg_ao CK_INFRA_MUX_SPI0_SEL>, -- <&infracfg_ao CK_INFRA_MUX_SPI1_SEL>, -- <&infracfg_ao CK_INFRA_MUX_SPI2_SEL>, -- <&infracfg_ao CK_INFRA_PWM_SEL>, -- <&infracfg_ao CK_INFRA_PWM_CK1_SEL>, -- <&infracfg_ao CK_INFRA_PWM_CK2_SEL>, -- <&infracfg_ao CK_INFRA_PWM_CK3_SEL>, -- <&infracfg_ao CK_INFRA_PWM_CK4_SEL>, -- <&infracfg_ao CK_INFRA_PWM_CK5_SEL>, -- <&infracfg_ao CK_INFRA_PWM_CK6_SEL>, -- <&infracfg_ao CK_INFRA_PWM_CK7_SEL>, -- <&infracfg_ao CK_INFRA_PWM_CK8_SEL>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <&system_clk>, -- <ðsys CK_ETHDMA_XGP1_EN>, -- <ðsys CK_ETHDMA_XGP2_EN>, -- <ðsys CK_ETHDMA_XGP3_EN>, -- <ðsys CK_ETHDMA_FE_EN>, -- <ðsys CK_ETHDMA_GP2_EN>, -- <ðsys CK_ETHDMA_GP1_EN>, -- <ðsys CK_ETHDMA_GP3_EN>, -- <ðsys CK_ETHDMA_ESW_EN>, -- <ðsys CK_ETHDMA_CRYPT0_EN>, -- <ðwarp CK_ETHWARP_WOCPU2_EN>, -- <ðwarp CK_ETHWARP_WOCPU1_EN>, -- <ðwarp CK_ETHWARP_WOCPU0_EN>, -- <&sgmiisys0 CK_SGM0_TX_EN>, -- <&sgmiisys0 CK_SGM0_RX_EN>, -- <&sgmiisys1 CK_SGM1_TX_EN>, -- <&sgmiisys1 CK_SGM1_RX_EN>, -- <&mcusys CK_MCU_BUS_DIV_SEL>, -- <&mcusys CK_MCU_ARM_DIV_SEL>; -- -- clock-names = "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", -- "10", "11", "12", "13", "14", "15", "16", "17", -- "18", "19", "20", "21", "22", "23", "24", "25", -- "26", "27", "28", "29", "30", "31", "32", "33", -- "34", "35", "36", "37", "38", "39", "40", "41", -- "42", "43", "44", "45", "46", "47", "48", "49", -- "50", "51", "52", "53", "54", "55", "56", "57", -- "58", "59", "60", "61", "62", "63", "64", "65", -- "66", "67", "68", "69", "70", "71", "72", "73", -- "74", "75", "76", "77", "78", "79", "80", "81", -- "82", "83", "84", "85", "86", "87", "88", "89", -- "90", "91", "92", "93", "94", "95", "96", "97", -- "98", "99", "100", "101", "102", "103", "104", -- "105", "106", "107", "108", "109", "110", "111", -- "112", "113", "114", "115", "116", "117", "118", -- "119", "120", "121", "122", "123", "124", "125", -- "126", "127", "128", "129", "130", "131", "132", -- "133", "134", "135", "136", "137", "138", "139", -- "140", "141", "142", "143", "144", "145", "146", -- "147", "148", "149", "150", "151", "152", "153", -- "154", "155", "156", "157", "158", "159", "160", -- "161", "162", "163", "164", "165", "166", "167", -- "168", "169", "170", "171", "172", "173", "174", -- "175", "176", "177", "178", "179", "180", "181", -- "182", "183", "184", "185", "186", "187", "188", -- "189", "190", "191", "192", "193", "194", "195", -- "196", "197", "198", "199", "200", "201", "202", -- "203", "204", "205", "206", "207", "208", "209", -- "210", "211", "212", "213", "214", "215", "216", -- "217", "218", "219", "220", "221", "222", "223", -- "224", "225", "226", "227", "228", "229", "230", -- "231", "232", "233", "234", "235", "236", "237", -- "238", "239", "240", "241", "242", "243", "244", -- "245", "246", "247", "248", "249", "250", "251", -- "252", "253", "254", "255", "256", "257", "258", -- "259", "260", "261", "262", "263", "264", "265", -- "266", "267", "268", "269", "270", "271", "272", -- "273", "274", "275", "276", "277", "278", "279", -- "280", "281", "282", "283", "284", "285", "286", -- "287", "288", "289", "290", "291", "292", "293", -- "294", "295", "296", "297", "298", "299", "300", -- "301", "302", "303", "304", "305", "306", "307", -- "308", "309", "310", "311", "312", "313", "314", -- "315", "316", "317", "318", "319", "320", "321", -- "322", "323"; -- }; --}; -- ++ uart2_pins: uart2-pins-g1 { ++ mux { ++ function = "uart"; ++ groups = "uart2_1"; ++ }; ++ }; ++}; +diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts +new file mode 100644 +index 0000000000..0fcb42ee28 +--- /dev/null ++++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts +@@ -0,0 +1,70 @@ ++/dts-v1/; ++#include "mt7981-360-t7-base.dtsi" ++ ++/ { ++ nmbm_spim_nand { ++ compatible = "generic,nmbm"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ lower-mtd-device = <&spi_nand>; ++ forced-create; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x00 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "FIP"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x2400000>; ++ }; ++ ++ partition@2980000 { ++ label = "firmware-1"; ++ reg = <0x2980000 0x2400000>; ++ }; ++ ++ partition@4D80000 { ++ label = "plugin"; ++ reg = <0x4d80000 0x2400000>; ++ }; ++ ++ partition@7180000 { ++ label = "stock-config"; ++ reg = <0x7180000 0x100000>; ++ }; ++ ++ partition@7280000 { ++ label = "stock-factory"; ++ reg = <0x7280000 0x80000>; ++ }; ++ ++ partition@7300000 { ++ label = "stock-log"; ++ reg = <0x7300000 0x400000>; ++ }; ++ }; ++ }; ++}; From ac862d1317f362b1fbad941a905d7214bc2c8f06 Mon Sep 17 00:00:00 2001 From: Fujr Date: Mon, 27 Feb 2023 19:49:38 +0800 Subject: [PATCH 05/18] add 360-t7 profile --- profiles/mt7981-360-t7-108M.yml | 18 ++++++++++++++ profiles/mt7981-360-t7.yml | 18 ++++++++++++++ profiles/target_mt7981_360t7-108M.yml | 35 +++++++++++++++++++++++++++ profiles/target_mt7981_360t7.yml | 35 +++++++++++++++++++++++++++ 4 files changed, 106 insertions(+) create mode 100644 profiles/mt7981-360-t7-108M.yml create mode 100644 profiles/mt7981-360-t7.yml create mode 100644 profiles/target_mt7981_360t7-108M.yml create mode 100644 profiles/target_mt7981_360t7.yml diff --git a/profiles/mt7981-360-t7-108M.yml b/profiles/mt7981-360-t7-108M.yml new file mode 100644 index 0000000..48b6c5f --- /dev/null +++ b/profiles/mt7981-360-t7-108M.yml @@ -0,0 +1,18 @@ +--- +description: Add the glinet dependencies for the GL.iNET MT3000 + +feeds: + - name: mt7981_private + uri: https://gitlab.com/gl.sdk4.0/gl.router/mt7981-feeds.git + revision: c4306a00ef9b5067e83e30378ddd6b5fdaf0ce84 + - name: glinet + uri: https://gitlab.com/gl.sdk4.0/gl.router/gl-sdk4-collect.git + revision: 9f4a704d13a5e6d18f8f7daccdc26997688b023f + +packages: + - gl-sdk4-led + - gl-sdk4-adguardhome + - gl-sdk4-timer + - gl-sdk4-igmp + - gl-sdk4-mwan3 + - gl-sdk4-ui-hwnat diff --git a/profiles/mt7981-360-t7.yml b/profiles/mt7981-360-t7.yml new file mode 100644 index 0000000..48b6c5f --- /dev/null +++ b/profiles/mt7981-360-t7.yml @@ -0,0 +1,18 @@ +--- +description: Add the glinet dependencies for the GL.iNET MT3000 + +feeds: + - name: mt7981_private + uri: https://gitlab.com/gl.sdk4.0/gl.router/mt7981-feeds.git + revision: c4306a00ef9b5067e83e30378ddd6b5fdaf0ce84 + - name: glinet + uri: https://gitlab.com/gl.sdk4.0/gl.router/gl-sdk4-collect.git + revision: 9f4a704d13a5e6d18f8f7daccdc26997688b023f + +packages: + - gl-sdk4-led + - gl-sdk4-adguardhome + - gl-sdk4-timer + - gl-sdk4-igmp + - gl-sdk4-mwan3 + - gl-sdk4-ui-hwnat diff --git a/profiles/target_mt7981_360t7-108M.yml b/profiles/target_mt7981_360t7-108M.yml new file mode 100644 index 0000000..3fc72dd --- /dev/null +++ b/profiles/target_mt7981_360t7-108M.yml @@ -0,0 +1,35 @@ +--- +profile: mt7981-360-t7-108M +target: mediatek +subtarget: mt7981 +description: Build image for the GL.iNET 360T7 108M + +feeds: + - name: gl_feed_common + uri: https://github.com/gl-inet/gl-feeds.git + revision: ac1ff5fb455c6d304aa435abb1c3eccf4878e28b + - name: gl_feed_21_02 + uri: https://github.com/gl-inet/gl-feeds.git + revision: 581563a214d313c367d7ffe5a1e9038fc18292ed + - name: gl_feed_mtk + uri: https://github.com/gl-inet/gl-feeds.git + revision: 5e48f72b4020fca612bedc480231c9081a00efa4 + +packages: + - ethtool + - iwinfo + - wireless-tools + - gl-sdk4-mtk-wifi-v2 + - kmod-conninfra-mt7981-ko + - kmod-mt-wifi-mt7981-ko + - kmod-warp-mt7981-ko + - kmod-mediatek_hnat + - kmod-gl-sdk4-fan + - mii_mgr + - mtkhnat_util + - regs + - luci + - 8021xd + - fwdd + - kmod-mtfwd + - kmod-mtqos diff --git a/profiles/target_mt7981_360t7.yml b/profiles/target_mt7981_360t7.yml new file mode 100644 index 0000000..85650da --- /dev/null +++ b/profiles/target_mt7981_360t7.yml @@ -0,0 +1,35 @@ +--- +profile: mt7981-360-t7 +target: mediatek +subtarget: mt7981 +description: Build image for the GL.iNET 360T7 + +feeds: + - name: gl_feed_common + uri: https://github.com/gl-inet/gl-feeds.git + revision: ac1ff5fb455c6d304aa435abb1c3eccf4878e28b + - name: gl_feed_21_02 + uri: https://github.com/gl-inet/gl-feeds.git + revision: 581563a214d313c367d7ffe5a1e9038fc18292ed + - name: gl_feed_mtk + uri: https://github.com/gl-inet/gl-feeds.git + revision: 5e48f72b4020fca612bedc480231c9081a00efa4 + +packages: + - ethtool + - iwinfo + - wireless-tools + - gl-sdk4-mtk-wifi-v2 + - kmod-conninfra-mt7981-ko + - kmod-mt-wifi-mt7981-ko + - kmod-warp-mt7981-ko + - kmod-mediatek_hnat + - kmod-gl-sdk4-fan + - mii_mgr + - mtkhnat_util + - regs + - luci + - 8021xd + - fwdd + - kmod-mtfwd + - kmod-mtqos From 973a8f08ed442c64cdec5d73b8024ef3a86ae98a Mon Sep 17 00:00:00 2001 From: Fujr Date: Mon, 27 Feb 2023 19:57:48 +0800 Subject: [PATCH 06/18] add support for 360t7 --- .../4010-support-360-t7.patch | 415 +++--------------- 1 file changed, 55 insertions(+), 360 deletions(-) diff --git a/patches-mt798x-7.6.6.1/4010-support-360-t7.patch b/patches-mt798x-7.6.6.1/4010-support-360-t7.patch index 115eb7a..3b6e751 100644 --- a/patches-mt798x-7.6.6.1/4010-support-360-t7.patch +++ b/patches-mt798x-7.6.6.1/4010-support-360-t7.patch @@ -1,365 +1,60 @@ -diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts -new file mode 100644 -index 0000000000..3be72d2960 ---- /dev/null -+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts -@@ -0,0 +1,60 @@ -+/dts-v1/; -+#include "mt7981-360-t7-base.dtsi" -+ -+/ { -+ nmbm_spim_nand { -+ compatible = "generic,nmbm"; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ lower-mtd-device = <&spi_nand>; -+ forced-create; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "BL2"; -+ reg = <0x00 0x100000>; -+ }; -+ -+ partition@100000 { -+ label = "u-boot-env"; -+ reg = <0x100000 0x80000>; -+ }; -+ -+ partition@180000 { -+ label = "Factory"; -+ reg = <0x180000 0x200000>; -+ }; -+ -+ partition@380000 { -+ label = "FIP"; -+ reg = <0x380000 0x200000>; -+ }; -+ -+ partition@580000 { -+ label = "ubi"; -+ reg = <0x580000 0x6c00000>; -+ }; -+ -+ partition@7180000 { -+ label = "stock-config"; -+ reg = <0x7180000 0x100000>; -+ }; -+ -+ partition@7280000 { -+ label = "stock-factory"; -+ reg = <0x7280000 0x80000>; -+ }; -+ -+ partition@7300000 { -+ label = "stock-log"; -+ reg = <0x7300000 0x400000>; -+ }; -+ }; -+ }; -+}; +From d5cd3a824cd58b2b9eec31a0407c23fa39540386 Mon Sep 17 00:00:00 2001 +From: fujr +Date: Mon, 27 Feb 2023 19:52:22 +0800 +Subject: [PATCH] add gl config + +--- + .../boot/dts/mediatek/mt7981-360-t7-base.dtsi | 30 +++++++++++++++++++ + 1 file changed, 30 insertions(+) + diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi -new file mode 100644 -index 0000000000..54be7d2ad4 ---- /dev/null +index 92a704e5e2..1f3ce6da9e 100644 +--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi +++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi -@@ -0,0 +1,217 @@ -+/dts-v1/; -+#include "mt7981.dtsi" +@@ -12,6 +12,29 @@ + led-upgrade = &green_led; + }; + + -+/ { -+ model = "360 T7"; -+ compatible = "360,t7", "mediatek,mt7981"; ++ gl-hw { ++ compatible = "gl-hw-info"; ++ model = "mt3000"; ++ wan = "eth0"; ++ lan = "eth1"; ++ temperature = "/sys/devices/virtual/thermal/thermal_zone0/temp"; ++ switch-button = "gpio-455"; ++ reset-button = "gpio-456"; ++ radio = "mt798111 mt798112"; ++ cfg-partition = "/dev/mtd7"; ++ flash_size = <128>; ++ dfs; ++ factory_data { ++ device_mac = "stock-factory", "0xb0"; ++ device_ddns = "stock-factory", "0xc0"; ++ device_sn_bak = "stock-factory", "0xd0"; ++ device_sn = "stock-factory", "0xe0"; ++ country_code = "stock-factory", "0x7a"; ++ }; ++ }; + -+ aliases { -+ led-boot = &red_led; -+ led-failsafe = &red_led; -+ led-running = &green_led; -+ led-upgrade = &green_led; -+ }; + -+ chosen { -+ bootargs = "console=ttyS0,115200n1 loglevel=8 \ -+ earlycon=uart8250,mmio32,0x11002000"; -+ }; -+ -+ memory { -+ reg = <0 0x40000000 0 0x10000000>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ green_led: green { -+ label = "360t7:green"; -+ gpios = <&pio 7 GPIO_ACTIVE_LOW>; -+ }; -+ -+ red_led: red { -+ label = "360t7:red"; -+ gpios = <&pio 3 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ reset { -+ label = "reset"; -+ linux,code = ; -+ gpios = <&pio 1 GPIO_ACTIVE_LOW>; -+ }; -+ -+ wps { -+ label = "wps"; -+ linux,code = ; -+ gpios = <&pio 0 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gsw: gsw@0 { -+ compatible = "mediatek,mt753x"; -+ mediatek,ethsys = <ðsys>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "okay"; -+}; -+ -+ð { -+ status = "okay"; -+ -+ gmac0: mac@0 { -+ compatible = "mediatek,eth-mac"; -+ reg = <0>; -+ phy-mode = "2500base-x"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ -+ gmac1: mac@1 { -+ compatible = "mediatek,eth-mac"; -+ reg = <1>; -+ phy-mode = "2500base-x"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ -+ mdio: mdio-bus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+}; -+ -+&gsw { -+ mediatek,mdio = <&mdio>; -+ mediatek,mdio_master_pinmux = <0>; -+ reset-gpios = <&pio 39 0>; -+ interrupt-parent = <&pio>; -+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; -+ status = "okay"; -+ -+ port5: port@5 { -+ compatible = "mediatek,mt753x-port"; -+ reg = <5>; -+ phy-mode = "sgmii"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ }; -+ }; -+ -+ port6: port@6 { -+ compatible = "mediatek,mt753x-port"; -+ mediatek,ssc-on; -+ reg = <6>; -+ phy-mode = "sgmii"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ }; -+ }; -+}; -+ -+&hnat { -+ mtketh-wan = "eth1"; -+ mtketh-lan = "eth0"; -+ mtketh-max-gmac = <2>; -+ status = "okay"; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_flash_pins>; -+ status = "okay"; -+ -+ spi_nand: spi_nand@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ spi-tx-buswidth = <4>; -+ spi-rx-buswidth = <4>; -+ spi-cal-enable; -+ spi-cal-mode = "read-data"; -+ spi-cal-datalen = <7>; -+ spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; /* 'SPINAND' */ -+ spi-cal-addrlen = <5>; -+ spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; -+ }; -+}; -+ -+&pio { -+ pwm0_pin: pwm0-pin-g0 { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_0"; -+ }; -+ }; -+ -+ pwm1_pin: pwm1-pin-g0 { -+ mux { -+ function = "pwm"; -+ groups = "pwm1_0"; -+ }; -+ }; -+ -+ pwm2_pin: pwm2-pin { -+ mux { -+ function = "pwm"; -+ groups = "pwm2"; -+ }; -+ }; -+ -+ spi0_flash_pins: spi0-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ -+ conf-pu { -+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ }; -+ -+ uart1_pins: uart1-pins-g1 { -+ mux { -+ function = "uart"; -+ groups = "uart1_1"; -+ }; -+ }; -+ -+ uart2_pins: uart2-pins-g1 { -+ mux { -+ function = "uart"; -+ groups = "uart2_1"; -+ }; -+ }; -+}; -diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts -new file mode 100644 -index 0000000000..0fcb42ee28 ---- /dev/null -+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts -@@ -0,0 +1,70 @@ -+/dts-v1/; -+#include "mt7981-360-t7-base.dtsi" -+ -+/ { -+ nmbm_spim_nand { -+ compatible = "generic,nmbm"; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ lower-mtd-device = <&spi_nand>; -+ forced-create; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "BL2"; -+ reg = <0x00 0x100000>; -+ }; -+ -+ partition@100000 { -+ label = "u-boot-env"; -+ reg = <0x100000 0x80000>; -+ }; -+ -+ partition@180000 { -+ label = "Factory"; -+ reg = <0x180000 0x200000>; -+ }; -+ -+ partition@380000 { -+ label = "FIP"; -+ reg = <0x380000 0x200000>; -+ }; -+ -+ partition@580000 { -+ label = "ubi"; -+ reg = <0x580000 0x2400000>; -+ }; -+ -+ partition@2980000 { -+ label = "firmware-1"; -+ reg = <0x2980000 0x2400000>; -+ }; -+ -+ partition@4D80000 { -+ label = "plugin"; -+ reg = <0x4d80000 0x2400000>; -+ }; -+ -+ partition@7180000 { -+ label = "stock-config"; -+ reg = <0x7180000 0x100000>; -+ }; -+ -+ partition@7280000 { -+ label = "stock-factory"; -+ reg = <0x7280000 0x80000>; -+ }; -+ -+ partition@7300000 { -+ label = "stock-log"; -+ reg = <0x7300000 0x400000>; -+ }; -+ }; -+ }; -+}; + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11002000"; +@@ -96,6 +119,13 @@ + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; ++ ethernet-phy@0 { ++ compatible = "ethernet-phy-id03a2.9461"; ++ reg = <0x00>; ++ phy-mode = "gmii"; ++ nvmem-cells = <0x12>; ++ nvmem-cell-names = "phy-cal-data"; ++ }; + }; + }; + +-- +2.25.1 + From 2928d632f355cb76b5ce288d5f6388d5f3669e0b Mon Sep 17 00:00:00 2001 From: Fujr Date: Mon, 27 Feb 2023 20:11:37 +0800 Subject: [PATCH 07/18] upport-360-t7 --- .../4010-support-360-t7.patch | 547 +++++++++++++++++- 1 file changed, 527 insertions(+), 20 deletions(-) diff --git a/patches-mt798x-7.6.6.1/4010-support-360-t7.patch b/patches-mt798x-7.6.6.1/4010-support-360-t7.patch index 3b6e751..17d9d1c 100644 --- a/patches-mt798x-7.6.6.1/4010-support-360-t7.patch +++ b/patches-mt798x-7.6.6.1/4010-support-360-t7.patch @@ -1,20 +1,107 @@ -From d5cd3a824cd58b2b9eec31a0407c23fa39540386 Mon Sep 17 00:00:00 2001 +From 88dde81e304c3bd316d96b306892f8578f47737e Mon Sep 17 00:00:00 2001 From: fujr -Date: Mon, 27 Feb 2023 19:52:22 +0800 -Subject: [PATCH] add gl config +Date: Mon, 27 Feb 2023 20:08:06 +0800 +Subject: [PATCH] add support for 360t7 --- - .../boot/dts/mediatek/mt7981-360-t7-base.dtsi | 30 +++++++++++++++++++ - 1 file changed, 30 insertions(+) + .../boot/dts/mediatek/mt7981-360-t7-108M.dts | 61 +++++ + .../boot/dts/mediatek/mt7981-360-t7-base.dtsi | 248 ++++++++++++++++++ + .../arm64/boot/dts/mediatek/mt7981-360-t7.dts | 71 +++++ + target/linux/mediatek/image/mt7981.mk | 35 +++ + .../mt7981/base-files/etc/board.d/01_leds | 6 + + .../mt7981/base-files/etc/board.d/02_network | 59 +++++ + 6 files changed, 480 insertions(+) + create mode 100644 target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts + create mode 100644 target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi + create mode 100644 target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts +diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts +new file mode 100644 +index 0000000000..c1749442e3 +--- /dev/null ++++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts +@@ -0,0 +1,61 @@ ++/dts-v1/; ++#include "mt7981-360-t7-base.dtsi" ++ ++/ { ++ nmbm_spim_nand { ++ compatible = "generic,nmbm"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ lower-mtd-device = <&spi_nand>; ++ forced-create; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x00 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "FIP"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x6c00000>; ++ }; ++ ++ partition@7180000 { ++ label = "stock-config"; ++ reg = <0x7180000 0x100000>; ++ }; ++ ++ partition@7280000 { ++ label = "stock-factory"; ++ reg = <0x7280000 0x80000>; ++ }; ++ ++ partition@7300000 { ++ label = "stock-log"; ++ reg = <0x7300000 0x400000>; ++ }; ++ }; ++ }; ++}; ++ diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi -index 92a704e5e2..1f3ce6da9e 100644 ---- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi +new file mode 100644 +index 0000000000..1f3ce6da9e +--- /dev/null +++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi -@@ -12,6 +12,29 @@ - led-upgrade = &green_led; - }; - +@@ -0,0 +1,248 @@ ++/dts-v1/; ++#include "mt7981.dtsi" ++ ++/ { ++ model = "360 T7"; ++ compatible = "360,t7", "mediatek,mt7981"; ++ ++ aliases { ++ led-boot = &red_led; ++ led-failsafe = &red_led; ++ led-running = &green_led; ++ led-upgrade = &green_led; ++ }; ++ + + gl-hw { + compatible = "gl-hw-info"; @@ -38,13 +125,90 @@ index 92a704e5e2..1f3ce6da9e 100644 + }; + + - chosen { - bootargs = "console=ttyS0,115200n1 loglevel=8 \ - earlycon=uart8250,mmio32,0x11002000"; -@@ -96,6 +119,13 @@ - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; ++ chosen { ++ bootargs = "console=ttyS0,115200n1 loglevel=8 \ ++ earlycon=uart8250,mmio32,0x11002000"; ++ }; ++ ++ memory { ++ reg = <0 0x40000000 0 0x10000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ green_led: green { ++ label = "360t7:green"; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ red_led: red { ++ label = "360t7:red"; ++ gpios = <&pio 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ reset { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "wps"; ++ linux,code = ; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gsw: gsw@0 { ++ compatible = "mediatek,mt753x"; ++ mediatek,ethsys = <ðsys>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ ++ gmac0: mac@0 { ++ compatible = "mediatek,eth-mac"; ++ reg = <0>; ++ phy-mode = "2500base-x"; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ ++ gmac1: mac@1 { ++ compatible = "mediatek,eth-mac"; ++ reg = <1>; ++ phy-mode = "2500base-x"; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ ++ mdio: mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; + ethernet-phy@0 { + compatible = "ethernet-phy-id03a2.9461"; + reg = <0x00>; @@ -52,9 +216,352 @@ index 92a704e5e2..1f3ce6da9e 100644 + nvmem-cells = <0x12>; + nvmem-cell-names = "phy-cal-data"; + }; - }; - }; ++ }; ++}; ++ ++&gsw { ++ mediatek,mdio = <&mdio>; ++ mediatek,mdio_master_pinmux = <0>; ++ reset-gpios = <&pio 39 0>; ++ interrupt-parent = <&pio>; ++ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; ++ status = "okay"; ++ ++ port5: port@5 { ++ compatible = "mediatek,mt753x-port"; ++ reg = <5>; ++ phy-mode = "sgmii"; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++ }; ++ ++ port6: port@6 { ++ compatible = "mediatek,mt753x-port"; ++ mediatek,ssc-on; ++ reg = <6>; ++ phy-mode = "sgmii"; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++ }; ++}; ++ ++&hnat { ++ mtketh-wan = "eth1"; ++ mtketh-lan = "eth0"; ++ mtketh-max-gmac = <2>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_flash_pins>; ++ status = "okay"; ++ ++ spi_nand: spi_nand@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ spi-tx-buswidth = <4>; ++ spi-rx-buswidth = <4>; ++ spi-cal-enable; ++ spi-cal-mode = "read-data"; ++ spi-cal-datalen = <7>; ++ spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; /* 'SPINAND' */ ++ spi-cal-addrlen = <5>; ++ spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; ++ }; ++}; ++ ++&pio { ++ pwm0_pin: pwm0-pin-g0 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_0"; ++ }; ++ }; ++ ++ pwm1_pin: pwm1-pin-g0 { ++ mux { ++ function = "pwm"; ++ groups = "pwm1_0"; ++ }; ++ }; ++ ++ pwm2_pin: pwm2-pin { ++ mux { ++ function = "pwm"; ++ groups = "pwm2"; ++ }; ++ }; ++ ++ spi0_flash_pins: spi0-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ }; ++ ++ uart1_pins: uart1-pins-g1 { ++ mux { ++ function = "uart"; ++ groups = "uart1_1"; ++ }; ++ }; ++ ++ uart2_pins: uart2-pins-g1 { ++ mux { ++ function = "uart"; ++ groups = "uart2_1"; ++ }; ++ }; ++}; ++ +diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts +new file mode 100644 +index 0000000000..8b1de92dfa +--- /dev/null ++++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts +@@ -0,0 +1,71 @@ ++/dts-v1/; ++#include "mt7981-360-t7-base.dtsi" ++ ++/ { ++ nmbm_spim_nand { ++ compatible = "generic,nmbm"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ lower-mtd-device = <&spi_nand>; ++ forced-create; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x00 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "FIP"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x2400000>; ++ }; ++ ++ partition@2980000 { ++ label = "firmware-1"; ++ reg = <0x2980000 0x2400000>; ++ }; ++ ++ partition@4D80000 { ++ label = "plugin"; ++ reg = <0x4d80000 0x2400000>; ++ }; ++ ++ partition@7180000 { ++ label = "stock-config"; ++ reg = <0x7180000 0x100000>; ++ }; ++ ++ partition@7280000 { ++ label = "stock-factory"; ++ reg = <0x7280000 0x80000>; ++ }; ++ ++ partition@7300000 { ++ label = "stock-log"; ++ reg = <0x7300000 0x400000>; ++ }; ++ }; ++ }; ++}; ++ +diff --git a/target/linux/mediatek/image/mt7981.mk b/target/linux/mediatek/image/mt7981.mk +index b7f1f6d437..7a436bb61d 100755 +--- a/target/linux/mediatek/image/mt7981.mk ++++ b/target/linux/mediatek/image/mt7981.mk +@@ -222,3 +222,38 @@ define Device/glinet_gl-mt2500 + IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata + endef + TARGET_DEVICES += glinet_gl-mt2500 ++ ++define Device/mt7981-360-t7 ++ DEVICE_VENDOR := GL.iNet ++ DEVICE_MODEL := 360 T7 ++ DEVICE_DTS := mt7981-360-t7 ++ DEVICE_DTS_DIR := $(DTS_DIR)/mediatek ++ SUPPORTED_DEVICES := 360,t7 ++ UBINIZE_OPTS := -E 5 ++ BLOCKSIZE := 128k ++ PAGESIZE := 2048 ++ IMAGE_SIZE := 36864k ++ KERNEL_IN_UBI := 1 ++ IMAGES += factory.bin ++ IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) ++ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata ++endef ++TARGET_DEVICES += mt7981-360-t7 ++ ++define Device/mt7981-360-t7-108M ++ DEVICE_VENDOR := GL.iNet ++ DEVICE_MODEL := 360 T7 (with 108M ubi) ++ DEVICE_DTS := mt7981-360-t7-108M ++ DEVICE_DTS_DIR := $(DTS_DIR)/mediatek ++ SUPPORTED_DEVICES := 360,t7 ++ UBINIZE_OPTS := -E 5 ++ BLOCKSIZE := 128k ++ PAGESIZE := 2048 ++ IMAGE_SIZE := 110592k ++ KERNEL_IN_UBI := 1 ++ IMAGES += factory.bin ++ IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) ++ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata ++endef ++TARGET_DEVICES += mt7981-360-t7-108M ++ +diff --git a/target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds b/target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds +index 43905e604d..779ac123b1 100755 +--- a/target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds ++++ b/target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds +@@ -13,6 +13,12 @@ glinet,x3000-emmc) + ucidef_set_led_default "power" "POWER" "power" "1" + ;; + esac ++case "$(board_name)" in ++*360,t7*) ++ ucidef_set_led_default "green" "GREEN" "360t7:green" "1" ++ ucidef_set_led_default "red" "RED" "360t7:red" "0" ++ ;; ++esac + board_config_flush + +diff --git a/target/linux/mediatek/mt7981/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7981/base-files/etc/board.d/02_network +index c2a22e425b..936ea35aea 100755 +--- a/target/linux/mediatek/mt7981/base-files/etc/board.d/02_network ++++ b/target/linux/mediatek/mt7981/base-files/etc/board.d/02_network +@@ -28,18 +28,63 @@ mediatek_setup_interfaces() + *mt2500*) + ucidef_set_interfaces_lan_wan eth1 eth0 + ;; ++ *360,t7*) ++ ucidef_set_interfaces_lan_wan "eth0" "eth1" ++ ucidef_add_switch "switch0" \ ++ "0:lan" "1:lan" "2:lan" "3:wan" "6u@eth0" "5u@eth1" ++ ;; + *) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1 + ;; + esac + } + ++mtk_facrory_write_mac() ++{ ++ local part_name=$1 ++ local offset=$2 ++ local macaddr=$3 #aa:bb:cc:dd:ee:ff ++ local data="" ++ ++ part=$(find_mtd_part $part_name) ++ if [ -n "$part" ] && [ -n "$macaddr" ]; then ++ local i=1 ++ for x in ${macaddr//:/ }; do ++ [ $i -gt 6 ] && break ++ data=${data}"\x${x}" ++ i=$((i+1)) ++ done ++ dd if=$part of=/tmp/Factory.backup ++ printf "${data}" | dd conv=notrunc of=/tmp/Factory.backup bs=1 seek=$((${offset})) ++ mtd write /tmp/Factory.backup $part_name ++ rm -rf /tmp/Factory.backup ++ fi ++} ++ ++mtk_factory_get_byte() ++{ ++ local part_name=$1 ++ local offset=$2 ++ local len=$3 ++ ++ part=$(find_mtd_part $part_name) ++ if [ -n "$part" ]; then ++ hexdump -n $len -s $offset -e ''`expr ${len} - 1`'/1 "%02x-" "%02x"' $part ++ fi ++} ++ ++ + mediatek_setup_macs() + { + local board="$1" + local part_name="Factory" + local lan_mac="" + local wan_mac="" ++ local lan_mac_offset="0x2A" ++ local wan_mac_offset="0x24" ++ ++ lan_mac=$(mtd_get_mac_binary $part_name $lan_mac_offset) ++ wan_mac=$(mtd_get_mac_binary $part_name $wan_mac_offset) + + case $board in + *mt3000*) +@@ -55,6 +100,20 @@ mediatek_setup_macs() + wan_mac=$(get_mac_binary /dev/mmcblk0p3 0x0a) + lan_mac=$(macaddr_add "$wan_mac" 1) + ;; ++ *360,t7*) ++ local part=$(find_mtd_part "stock-factory") ++ if [ -n "$part" ]; then ++ local factoryMac="$(dd if=$part bs=1 count=200 2>/dev/null |grep "^lanMac=")" ++ if [ -n "$factoryMac" ]; then ++ lan_mac="${factoryMac#lanMac=}" ++ wan_mac="$(macaddr_add $lan_mac 0x1)" ++ if [ "$(mtk_factory_get_byte "Factory" 4 2)" = "00-0c" ]; then ++ local wifi_mac="$(macaddr_add $lan_mac 0x2)" ++ mtk_facrory_write_mac "Factory" 4 $wifi_mac ++ fi ++ fi ++ fi ++ ;; + esac + + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" "$wan_mac" -- 2.25.1 From 68443512e79918c260c65e0811e5fa5d5f560701 Mon Sep 17 00:00:00 2001 From: Fujr Date: Mon, 27 Feb 2023 23:38:25 +0800 Subject: [PATCH 08/18] remove gpy211 support,now only support 360t7 --- ...iatek-mtk-eth-poll-gpy211-link-state.patch | 144 ------------------ 1 file changed, 144 deletions(-) delete mode 100644 patches-mt798x-7.6.6.1/3003-target-mediatek-mtk-eth-poll-gpy211-link-state.patch diff --git a/patches-mt798x-7.6.6.1/3003-target-mediatek-mtk-eth-poll-gpy211-link-state.patch b/patches-mt798x-7.6.6.1/3003-target-mediatek-mtk-eth-poll-gpy211-link-state.patch deleted file mode 100644 index 4b514c7..0000000 --- a/patches-mt798x-7.6.6.1/3003-target-mediatek-mtk-eth-poll-gpy211-link-state.patch +++ /dev/null @@ -1,144 +0,0 @@ -From 140ddd19397760be888eb3aa0a977182a30e9f9e Mon Sep 17 00:00:00 2001 -From: Jianhui Zhao -Date: Mon, 19 Sep 2022 14:11:34 +0800 -Subject: [PATCH] target/mediatek: mtk-eth poll gpy211 link state - -Signed-off-by: Jianhui Zhao ---- - .../net/ethernet/mediatek/mtk_eth_dbg.c | 8 ++-- - .../net/ethernet/mediatek/mtk_eth_soc.c | 44 +++++++++++++++++-- - .../drivers/net/ethernet/mediatek/mtk_sgmii.c | 5 ++- - 3 files changed, 48 insertions(+), 9 deletions(-) - -diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c -index 0d5ca16e4f..8977afb21c 100755 ---- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c -+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c -@@ -417,7 +417,7 @@ void mii_mgr_read_combine(struct mtk_eth *eth, u32 phy_addr, u32 phy_register, - *read_data = mt7530_mdio_r32(eth, phy_register); - - else -- *read_data = _mtk_mdio_read(eth, phy_addr, phy_register); -+ *read_data = mdiobus_read(eth->mii_bus, phy_addr, phy_register); - } - - void mii_mgr_write_combine(struct mtk_eth *eth, u16 phy_addr, u16 phy_register, -@@ -427,17 +427,17 @@ void mii_mgr_write_combine(struct mtk_eth *eth, u16 phy_addr, u16 phy_register, - mt7530_mdio_w32(eth, phy_register, write_data); - - else -- _mtk_mdio_write(eth, phy_addr, phy_register, write_data); -+ mdiobus_write(eth->mii_bus, phy_addr, phy_register, write_data); - } - - static void mii_mgr_read_cl45(struct mtk_eth *eth, u16 port, u16 devad, u16 reg, u16 *data) - { -- *data = _mtk_mdio_read(eth, port, mdiobus_c45_addr(devad, reg)); -+ *data = mdiobus_read(eth->mii_bus, port, mdiobus_c45_addr(devad, reg)); - } - - static void mii_mgr_write_cl45(struct mtk_eth *eth, u16 port, u16 devad, u16 reg, u16 data) - { -- _mtk_mdio_write(eth, port, mdiobus_c45_addr(devad, reg), data); -+ mdiobus_write(eth->mii_bus, port, mdiobus_c45_addr(devad, reg), data); - } - - int mtk_do_priv_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c -index a05cd19df6..d97776ba00 100755 ---- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2765,10 +2765,10 @@ static int mtk_open(struct net_device *dev) - */ - - // clear interrupt source for gpy211 -- _mtk_mdio_read(eth, phylink_priv->phyaddr, 0x1A); -+ mdiobus_read(eth->mii_bus, phylink_priv->phyaddr, 0x1A); - - // enable link status change interrupt for gpy211 -- _mtk_mdio_write(eth, phylink_priv->phyaddr, 0x19, 0x0001); -+ mdiobus_write(eth->mii_bus, phylink_priv->phyaddr, 0x19, 0x0001); - - phylink_priv->dev = dev; - -@@ -2828,9 +2828,9 @@ static int mtk_stop(struct net_device *dev) - - phy_node = of_parse_phandle(mac->of_node, "phy-handle", 0); - if (phy_node) { -- val = _mtk_mdio_read(eth, 0, 0); -+ val = mdiobus_read(eth->mii_bus, 0, 0); - val |= BMCR_PDOWN; -- _mtk_mdio_write(eth, 0, 0, val); -+ mdiobus_write(eth->mii_bus, 0, 0, val); - } else if (eth->sgmii->regmap[mac->id]) { - regmap_read(eth->sgmii->regmap[mac->id], SGMSYS_QPHY_PWR_STATE_CTRL, &val); - val |= SGMII_PHYA_PWD; -@@ -3509,6 +3509,40 @@ static const struct net_device_ops mtk_netdev_ops = { - #endif - }; - -+static void phylink_fixed_state(struct net_device *dev, -+ struct phylink_link_state *state) -+{ -+#define PHY_MIISTAT 0x18 /* MII state */ -+#define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) -+#define PHY_MIISTAT_DPX BIT(3) -+#define PHY_MIISTAT_LS BIT(10) -+#define PHY_MIISTAT_SPD_10 0 -+#define PHY_MIISTAT_SPD_100 1 -+#define PHY_MIISTAT_SPD_1000 2 -+#define PHY_MIISTAT_SPD_2500 4 -+ -+ struct mtk_mac *mac = netdev_priv(dev); -+ u32 val = mdiobus_read(mac->hw->mii_bus, 0x05, PHY_MIISTAT); -+ -+ state->link = (val & PHY_MIISTAT_LS) ? 1 : 0; -+ state->duplex = (val & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF; -+ -+ switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, val)) { -+ case PHY_MIISTAT_SPD_10: -+ state->speed = SPEED_10; -+ break; -+ case PHY_MIISTAT_SPD_100: -+ state->speed = SPEED_100; -+ break; -+ case PHY_MIISTAT_SPD_1000: -+ state->speed = SPEED_1000; -+ break; -+ case PHY_MIISTAT_SPD_2500: -+ state->speed = SPEED_2500; -+ break; -+ } -+} -+ - static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) - { - const __be32 *_id = of_get_property(np, "reg", NULL); -@@ -3590,6 +3624,8 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) - fixed_node = fwnode_get_named_child_node(of_fwnode_handle(mac->of_node), - "fixed-link"); - if (fixed_node) { -+ phylink_fixed_state_cb(phylink, phylink_fixed_state); -+ - desc = fwnode_get_named_gpiod(fixed_node, "link-gpio", - 0, GPIOD_IN, "?"); - if (!IS_ERR(desc)) { -diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c -index 8198c7cb59..e0406e2b86 100755 ---- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c -+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c -@@ -111,7 +111,10 @@ int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, unsigned int id, - val |= SGMII_SPEED_10; - break; - case SPEED_100: -- val |= SGMII_SPEED_100; -+ if (state->interface == PHY_INTERFACE_MODE_2500BASEX) -+ val |= SGMII_SPEED_1000; -+ else -+ val |= SGMII_SPEED_100; - break; - case SPEED_2500: - case SPEED_1000: --- -2.25.1 - From 699d943821fbf39c8f044cbdc9622609852377ab Mon Sep 17 00:00:00 2001 From: Fujr Date: Mon, 27 Feb 2023 23:50:03 +0800 Subject: [PATCH 09/18] add 360t7-108M --- README.md | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/README.md b/README.md index c9379ac..1bc2fcf 100644 --- a/README.md +++ b/README.md @@ -57,6 +57,50 @@ $ ls -l /usr/bin/python3* # Example compile firmware +## 0.Compile 360T7（2023.2.27） + +0.0 + +with gl-inet package installed,original partition is not big enough,you should flash the bl blow. + +https://github.com/FUjr/gl-infra-builder + +1.1 Compile 360t7-108M OpenWrt firmware(No GL.iNet packages) + +``` + git clone https://github.com/gl-inet/gl-infra-builder.git && cd gl-infra-builder +``` + +``` + python3 setup.py -c configs/config-mt798x-7.6.6.1.yml && cd mt7981 +``` + +``` + ./scripts/gen_config.py target_mt7981_360t7-108M luci +``` + +1.2 Compile 360t7-108M GL.iNet standard firmware + +``` + git clone https://github.com/gl-inet/glinet4.x.git +``` + +``` + cp ./glinet4.x/pkg_config/gl_pkg_config_mt7981_mt2500.mk ./glinet4.x/mt7981/gl_pkg_config.mk +``` + +``` + ./scripts/gen_config.py target_mt7981_360t7-108M glinet_depends +``` + +``` + make V=s -j5 GL_PKGDIR=`pwd`/glinet4.x/mt7981/ +``` + +## + + + ## 1. Compile MT2500(2023.02.22) 1.1 Compile MT2500 OpenWrt firmware(No GL.iNet packages) @@ -74,6 +118,7 @@ $ ls -l /usr/bin/python3* ``` 1.2 Compile MT2500 GL.iNet standard firmware + ``` git clone https://github.com/gl-inet/glinet4.x.git ``` From ae8ac2d70a35d394dcfd01354322055b89d83059 Mon Sep 17 00:00:00 2001 From: Fujr Date: Mon, 27 Feb 2023 23:51:22 +0800 Subject: [PATCH 10/18] fix error link --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 1bc2fcf..a3e04a4 100644 --- a/README.md +++ b/README.md @@ -63,7 +63,7 @@ $ ls -l /usr/bin/python3* with gl-inet package installed,original partition is not big enough,you should flash the bl blow. -https://github.com/FUjr/gl-infra-builder +https://github.com/hanwckf/bl-mt798x 1.1 Compile 360t7-108M OpenWrt firmware(No GL.iNet packages) From 9b947332b89ae87cab2bb6b1180076c3b973d99d Mon Sep 17 00:00:00 2001 From: fujr Date: Tue, 28 Feb 2023 05:10:53 +0800 Subject: [PATCH 11/18] rm remove conflect patch --- ...iatek-mtk-eth-poll-gpy211-link-state.patch | 144 ------------------ 1 file changed, 144 deletions(-) delete mode 100644 patches-mt798x-7.6.6.1/3003-target-mediatek-mtk-eth-poll-gpy211-link-state.patch diff --git a/patches-mt798x-7.6.6.1/3003-target-mediatek-mtk-eth-poll-gpy211-link-state.patch b/patches-mt798x-7.6.6.1/3003-target-mediatek-mtk-eth-poll-gpy211-link-state.patch deleted file mode 100644 index 4b514c7..0000000 --- a/patches-mt798x-7.6.6.1/3003-target-mediatek-mtk-eth-poll-gpy211-link-state.patch +++ /dev/null @@ -1,144 +0,0 @@ -From 140ddd19397760be888eb3aa0a977182a30e9f9e Mon Sep 17 00:00:00 2001 -From: Jianhui Zhao -Date: Mon, 19 Sep 2022 14:11:34 +0800 -Subject: [PATCH] target/mediatek: mtk-eth poll gpy211 link state - -Signed-off-by: Jianhui Zhao ---- - .../net/ethernet/mediatek/mtk_eth_dbg.c | 8 ++-- - .../net/ethernet/mediatek/mtk_eth_soc.c | 44 +++++++++++++++++-- - .../drivers/net/ethernet/mediatek/mtk_sgmii.c | 5 ++- - 3 files changed, 48 insertions(+), 9 deletions(-) - -diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c -index 0d5ca16e4f..8977afb21c 100755 ---- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c -+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c -@@ -417,7 +417,7 @@ void mii_mgr_read_combine(struct mtk_eth *eth, u32 phy_addr, u32 phy_register, - *read_data = mt7530_mdio_r32(eth, phy_register); - - else -- *read_data = _mtk_mdio_read(eth, phy_addr, phy_register); -+ *read_data = mdiobus_read(eth->mii_bus, phy_addr, phy_register); - } - - void mii_mgr_write_combine(struct mtk_eth *eth, u16 phy_addr, u16 phy_register, -@@ -427,17 +427,17 @@ void mii_mgr_write_combine(struct mtk_eth *eth, u16 phy_addr, u16 phy_register, - mt7530_mdio_w32(eth, phy_register, write_data); - - else -- _mtk_mdio_write(eth, phy_addr, phy_register, write_data); -+ mdiobus_write(eth->mii_bus, phy_addr, phy_register, write_data); - } - - static void mii_mgr_read_cl45(struct mtk_eth *eth, u16 port, u16 devad, u16 reg, u16 *data) - { -- *data = _mtk_mdio_read(eth, port, mdiobus_c45_addr(devad, reg)); -+ *data = mdiobus_read(eth->mii_bus, port, mdiobus_c45_addr(devad, reg)); - } - - static void mii_mgr_write_cl45(struct mtk_eth *eth, u16 port, u16 devad, u16 reg, u16 data) - { -- _mtk_mdio_write(eth, port, mdiobus_c45_addr(devad, reg), data); -+ mdiobus_write(eth->mii_bus, port, mdiobus_c45_addr(devad, reg), data); - } - - int mtk_do_priv_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c -index a05cd19df6..d97776ba00 100755 ---- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2765,10 +2765,10 @@ static int mtk_open(struct net_device *dev) - */ - - // clear interrupt source for gpy211 -- _mtk_mdio_read(eth, phylink_priv->phyaddr, 0x1A); -+ mdiobus_read(eth->mii_bus, phylink_priv->phyaddr, 0x1A); - - // enable link status change interrupt for gpy211 -- _mtk_mdio_write(eth, phylink_priv->phyaddr, 0x19, 0x0001); -+ mdiobus_write(eth->mii_bus, phylink_priv->phyaddr, 0x19, 0x0001); - - phylink_priv->dev = dev; - -@@ -2828,9 +2828,9 @@ static int mtk_stop(struct net_device *dev) - - phy_node = of_parse_phandle(mac->of_node, "phy-handle", 0); - if (phy_node) { -- val = _mtk_mdio_read(eth, 0, 0); -+ val = mdiobus_read(eth->mii_bus, 0, 0); - val |= BMCR_PDOWN; -- _mtk_mdio_write(eth, 0, 0, val); -+ mdiobus_write(eth->mii_bus, 0, 0, val); - } else if (eth->sgmii->regmap[mac->id]) { - regmap_read(eth->sgmii->regmap[mac->id], SGMSYS_QPHY_PWR_STATE_CTRL, &val); - val |= SGMII_PHYA_PWD; -@@ -3509,6 +3509,40 @@ static const struct net_device_ops mtk_netdev_ops = { - #endif - }; - -+static void phylink_fixed_state(struct net_device *dev, -+ struct phylink_link_state *state) -+{ -+#define PHY_MIISTAT 0x18 /* MII state */ -+#define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) -+#define PHY_MIISTAT_DPX BIT(3) -+#define PHY_MIISTAT_LS BIT(10) -+#define PHY_MIISTAT_SPD_10 0 -+#define PHY_MIISTAT_SPD_100 1 -+#define PHY_MIISTAT_SPD_1000 2 -+#define PHY_MIISTAT_SPD_2500 4 -+ -+ struct mtk_mac *mac = netdev_priv(dev); -+ u32 val = mdiobus_read(mac->hw->mii_bus, 0x05, PHY_MIISTAT); -+ -+ state->link = (val & PHY_MIISTAT_LS) ? 1 : 0; -+ state->duplex = (val & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF; -+ -+ switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, val)) { -+ case PHY_MIISTAT_SPD_10: -+ state->speed = SPEED_10; -+ break; -+ case PHY_MIISTAT_SPD_100: -+ state->speed = SPEED_100; -+ break; -+ case PHY_MIISTAT_SPD_1000: -+ state->speed = SPEED_1000; -+ break; -+ case PHY_MIISTAT_SPD_2500: -+ state->speed = SPEED_2500; -+ break; -+ } -+} -+ - static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) - { - const __be32 *_id = of_get_property(np, "reg", NULL); -@@ -3590,6 +3624,8 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) - fixed_node = fwnode_get_named_child_node(of_fwnode_handle(mac->of_node), - "fixed-link"); - if (fixed_node) { -+ phylink_fixed_state_cb(phylink, phylink_fixed_state); -+ - desc = fwnode_get_named_gpiod(fixed_node, "link-gpio", - 0, GPIOD_IN, "?"); - if (!IS_ERR(desc)) { -diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c -index 8198c7cb59..e0406e2b86 100755 ---- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c -+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c -@@ -111,7 +111,10 @@ int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, unsigned int id, - val |= SGMII_SPEED_10; - break; - case SPEED_100: -- val |= SGMII_SPEED_100; -+ if (state->interface == PHY_INTERFACE_MODE_2500BASEX) -+ val |= SGMII_SPEED_1000; -+ else -+ val |= SGMII_SPEED_100; - break; - case SPEED_2500: - case SPEED_1000: --- -2.25.1 - From 7a94327ffc3e95352a1c744cadd4209bfa9ec2a9 Mon Sep 17 00:00:00 2001 From: fujr Date: Tue, 28 Feb 2023 05:35:40 +0800 Subject: [PATCH 12/18] add profile for 360T7 --- profiles/mt7981-360-t7-108M.yml | 18 ++++++++++++++ profiles/target_mt7981_360t7-108M.yml | 35 +++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 profiles/mt7981-360-t7-108M.yml create mode 100644 profiles/target_mt7981_360t7-108M.yml diff --git a/profiles/mt7981-360-t7-108M.yml b/profiles/mt7981-360-t7-108M.yml new file mode 100644 index 0000000..48b6c5f --- /dev/null +++ b/profiles/mt7981-360-t7-108M.yml @@ -0,0 +1,18 @@ +--- +description: Add the glinet dependencies for the GL.iNET MT3000 + +feeds: + - name: mt7981_private + uri: https://gitlab.com/gl.sdk4.0/gl.router/mt7981-feeds.git + revision: c4306a00ef9b5067e83e30378ddd6b5fdaf0ce84 + - name: glinet + uri: https://gitlab.com/gl.sdk4.0/gl.router/gl-sdk4-collect.git + revision: 9f4a704d13a5e6d18f8f7daccdc26997688b023f + +packages: + - gl-sdk4-led + - gl-sdk4-adguardhome + - gl-sdk4-timer + - gl-sdk4-igmp + - gl-sdk4-mwan3 + - gl-sdk4-ui-hwnat diff --git a/profiles/target_mt7981_360t7-108M.yml b/profiles/target_mt7981_360t7-108M.yml new file mode 100644 index 0000000..3fc72dd --- /dev/null +++ b/profiles/target_mt7981_360t7-108M.yml @@ -0,0 +1,35 @@ +--- +profile: mt7981-360-t7-108M +target: mediatek +subtarget: mt7981 +description: Build image for the GL.iNET 360T7 108M + +feeds: + - name: gl_feed_common + uri: https://github.com/gl-inet/gl-feeds.git + revision: ac1ff5fb455c6d304aa435abb1c3eccf4878e28b + - name: gl_feed_21_02 + uri: https://github.com/gl-inet/gl-feeds.git + revision: 581563a214d313c367d7ffe5a1e9038fc18292ed + - name: gl_feed_mtk + uri: https://github.com/gl-inet/gl-feeds.git + revision: 5e48f72b4020fca612bedc480231c9081a00efa4 + +packages: + - ethtool + - iwinfo + - wireless-tools + - gl-sdk4-mtk-wifi-v2 + - kmod-conninfra-mt7981-ko + - kmod-mt-wifi-mt7981-ko + - kmod-warp-mt7981-ko + - kmod-mediatek_hnat + - kmod-gl-sdk4-fan + - mii_mgr + - mtkhnat_util + - regs + - luci + - 8021xd + - fwdd + - kmod-mtfwd + - kmod-mtqos From 1de46cd5095af4b87fe603524778898c3f8f732c Mon Sep 17 00:00:00 2001 From: fujr Date: Tue, 28 Feb 2023 05:38:21 +0800 Subject: [PATCH 13/18] add patch for qihoo 360T7 --- .../4010-support-Qihoo-360T7.patch | 482 ++++++++++++++++++ 1 file changed, 482 insertions(+) create mode 100644 patches-mt798x-7.6.6.1/4010-support-Qihoo-360T7.patch diff --git a/patches-mt798x-7.6.6.1/4010-support-Qihoo-360T7.patch b/patches-mt798x-7.6.6.1/4010-support-Qihoo-360T7.patch new file mode 100644 index 0000000..2a2894c --- /dev/null +++ b/patches-mt798x-7.6.6.1/4010-support-Qihoo-360T7.patch @@ -0,0 +1,482 @@ +From c96d75cce852adf3106112c33b920ed8e52baa35 Mon Sep 17 00:00:00 2001 +From: fujr +Date: Tue, 28 Feb 2023 05:22:15 +0800 +Subject: [PATCH 2/2] Add support for qihoo 360T7 + +--- + .../boot/dts/mediatek/mt7981-360-t7-108M.dts | 61 +++++ + .../boot/dts/mediatek/mt7981-360-t7-base.dtsi | 242 ++++++++++++++++++ + target/linux/mediatek/image/mt7981.mk | 35 +++ + .../mt7981/base-files/etc/board.d/01_leds | 6 + + .../mt7981/base-files/etc/board.d/02_network | 59 +++++ + 5 files changed, 403 insertions(+) + create mode 100644 target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts + create mode 100644 target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi + +diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts +new file mode 100644 +index 0000000000..c1749442e3 +--- /dev/null ++++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts +@@ -0,0 +1,61 @@ ++/dts-v1/; ++#include "mt7981-360-t7-base.dtsi" ++ ++/ { ++ nmbm_spim_nand { ++ compatible = "generic,nmbm"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ lower-mtd-device = <&spi_nand>; ++ forced-create; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x00 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "FIP"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x6c00000>; ++ }; ++ ++ partition@7180000 { ++ label = "stock-config"; ++ reg = <0x7180000 0x100000>; ++ }; ++ ++ partition@7280000 { ++ label = "stock-factory"; ++ reg = <0x7280000 0x80000>; ++ }; ++ ++ partition@7300000 { ++ label = "stock-log"; ++ reg = <0x7300000 0x400000>; ++ }; ++ }; ++ }; ++}; ++ +diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi +new file mode 100644 +index 0000000000..271dc68f57 +--- /dev/null ++++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi +@@ -0,0 +1,242 @@ ++/dts-v1/; ++#include "mt7981.dtsi" ++ ++/ { ++ model = "360 T7"; ++ compatible = "360,t7", "mediatek,mt7981"; ++ ++ aliases { ++ led-boot = &red_led; ++ led-failsafe = &red_led; ++ led-running = &green_led; ++ led-upgrade = &green_led; ++ }; ++ ++ ++ gl-hw { ++ compatible = "gl-hw-info"; ++ model = "mt3000"; ++ wan = "eth1"; ++ lan = "eth0"; ++ temperature = "/sys/devices/virtual/thermal/thermal_zone0/temp"; ++ switch-button = "gpio-455"; ++ reset-button = "gpio-456"; ++ radio = "mt798111 mt798112"; ++ cfg-partition = "/dev/mtd7"; ++ flash_size = <128>; ++ dfs; ++ factory_data { ++ device_mac = "stock-factory", "0xb0"; ++ device_ddns = "stock-factory", "0xc0"; ++ device_sn_bak = "stock-factory", "0xd0"; ++ device_sn = "stock-factory", "0xe0"; ++ country_code = "stock-factory", "0x7a"; ++ }; ++ }; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n1 loglevel=8 \ ++ earlycon=uart8250,mmio32,0x11002000"; ++ }; ++ ++ memory { ++ reg = <0 0x40000000 0 0x10000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ green_led: green { ++ label = "360t7:green"; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ red_led: red { ++ label = "360t7:red"; ++ gpios = <&pio 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ reset { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "wps"; ++ linux,code = ; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gsw: gsw@0 { ++ compatible = "mediatek,mt753x"; ++ mediatek,ethsys = <ðsys>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ ++ gmac0: mac@0 { ++ compatible = "mediatek,eth-mac"; ++ reg = <0>; ++ phy-mode = "2500base-x"; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ ++ gmac1: mac@1 { ++ compatible = "mediatek,eth-mac"; ++ reg = <1>; ++ phy-mode = "2500base-x"; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ mdio: mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++}; ++ ++&gsw { ++ mediatek,mdio = <&mdio>; ++ mediatek,mdio_master_pinmux = <0>; ++ reset-gpios = <&pio 39 0>; ++ interrupt-parent = <&pio>; ++ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; ++ status = "okay"; ++ ++ port5: port@5 { ++ compatible = "mediatek,mt753x-port"; ++ reg = <5>; ++ phy-mode = "sgmii"; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++ }; ++ ++ port6: port@6 { ++ compatible = "mediatek,mt753x-port"; ++ mediatek,ssc-on; ++ reg = <6>; ++ phy-mode = "sgmii"; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++ }; ++}; ++ ++&hnat { ++ mtketh-wan = "eth0"; ++ mtketh-lan = "eth1"; ++ mtketh-ppd = "eth1"; ++ mtketh-max-gmac = <2>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_flash_pins>; ++ status = "okay"; ++ ++ spi_nand: spi_nand@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ spi-tx-buswidth = <4>; ++ spi-rx-buswidth = <4>; ++ spi-cal-enable; ++ spi-cal-mode = "read-data"; ++ spi-cal-datalen = <7>; ++ spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; /* 'SPINAND' */ ++ spi-cal-addrlen = <5>; ++ spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; ++ }; ++}; ++ ++&pio { ++ pwm0_pin: pwm0-pin-g0 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_0"; ++ }; ++ }; ++ ++ pwm1_pin: pwm1-pin-g0 { ++ mux { ++ function = "pwm"; ++ groups = "pwm1_0"; ++ }; ++ }; ++ ++ pwm2_pin: pwm2-pin { ++ mux { ++ function = "pwm"; ++ groups = "pwm2"; ++ }; ++ }; ++ ++ spi0_flash_pins: spi0-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ }; ++ ++ uart1_pins: uart1-pins-g1 { ++ mux { ++ function = "uart"; ++ groups = "uart1_1"; ++ }; ++ }; ++ ++ uart2_pins: uart2-pins-g1 { ++ mux { ++ function = "uart"; ++ groups = "uart2_1"; ++ }; ++ }; ++}; ++ +diff --git a/target/linux/mediatek/image/mt7981.mk b/target/linux/mediatek/image/mt7981.mk +index b7f1f6d437..7a436bb61d 100755 +--- a/target/linux/mediatek/image/mt7981.mk ++++ b/target/linux/mediatek/image/mt7981.mk +@@ -222,3 +222,38 @@ define Device/glinet_gl-mt2500 + IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata + endef + TARGET_DEVICES += glinet_gl-mt2500 ++ ++define Device/mt7981-360-t7 ++ DEVICE_VENDOR := GL.iNet ++ DEVICE_MODEL := 360 T7 ++ DEVICE_DTS := mt7981-360-t7 ++ DEVICE_DTS_DIR := $(DTS_DIR)/mediatek ++ SUPPORTED_DEVICES := 360,t7 ++ UBINIZE_OPTS := -E 5 ++ BLOCKSIZE := 128k ++ PAGESIZE := 2048 ++ IMAGE_SIZE := 36864k ++ KERNEL_IN_UBI := 1 ++ IMAGES += factory.bin ++ IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) ++ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata ++endef ++TARGET_DEVICES += mt7981-360-t7 ++ ++define Device/mt7981-360-t7-108M ++ DEVICE_VENDOR := GL.iNet ++ DEVICE_MODEL := 360 T7 (with 108M ubi) ++ DEVICE_DTS := mt7981-360-t7-108M ++ DEVICE_DTS_DIR := $(DTS_DIR)/mediatek ++ SUPPORTED_DEVICES := 360,t7 ++ UBINIZE_OPTS := -E 5 ++ BLOCKSIZE := 128k ++ PAGESIZE := 2048 ++ IMAGE_SIZE := 110592k ++ KERNEL_IN_UBI := 1 ++ IMAGES += factory.bin ++ IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) ++ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata ++endef ++TARGET_DEVICES += mt7981-360-t7-108M ++ +diff --git a/target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds b/target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds +index 43905e604d..779ac123b1 100755 +--- a/target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds ++++ b/target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds +@@ -13,6 +13,12 @@ glinet,x3000-emmc) + ucidef_set_led_default "power" "POWER" "power" "1" + ;; + esac ++case "$(board_name)" in ++*360,t7*) ++ ucidef_set_led_default "green" "GREEN" "360t7:green" "1" ++ ucidef_set_led_default "red" "RED" "360t7:red" "0" ++ ;; ++esac + + board_config_flush + +diff --git a/target/linux/mediatek/mt7981/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7981/base-files/etc/board.d/02_network +index c2a22e425b..936ea35aea 100755 +--- a/target/linux/mediatek/mt7981/base-files/etc/board.d/02_network ++++ b/target/linux/mediatek/mt7981/base-files/etc/board.d/02_network +@@ -28,18 +28,63 @@ mediatek_setup_interfaces() + *mt2500*) + ucidef_set_interfaces_lan_wan eth1 eth0 + ;; ++ *360,t7*) ++ ucidef_set_interfaces_lan_wan "eth0" "eth1" ++ ucidef_add_switch "switch0" \ ++ "0:lan" "1:lan" "2:lan" "3:wan" "6u@eth0" "5u@eth1" ++ ;; + *) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1 + ;; + esac + } + ++mtk_facrory_write_mac() ++{ ++ local part_name=$1 ++ local offset=$2 ++ local macaddr=$3 #aa:bb:cc:dd:ee:ff ++ local data="" ++ ++ part=$(find_mtd_part $part_name) ++ if [ -n "$part" ] && [ -n "$macaddr" ]; then ++ local i=1 ++ for x in ${macaddr//:/ }; do ++ [ $i -gt 6 ] && break ++ data=${data}"\x${x}" ++ i=$((i+1)) ++ done ++ dd if=$part of=/tmp/Factory.backup ++ printf "${data}" | dd conv=notrunc of=/tmp/Factory.backup bs=1 seek=$((${offset})) ++ mtd write /tmp/Factory.backup $part_name ++ rm -rf /tmp/Factory.backup ++ fi ++} ++ ++mtk_factory_get_byte() ++{ ++ local part_name=$1 ++ local offset=$2 ++ local len=$3 ++ ++ part=$(find_mtd_part $part_name) ++ if [ -n "$part" ]; then ++ hexdump -n $len -s $offset -e ''`expr ${len} - 1`'/1 "%02x-" "%02x"' $part ++ fi ++} ++ ++ + mediatek_setup_macs() + { + local board="$1" + local part_name="Factory" + local lan_mac="" + local wan_mac="" ++ local lan_mac_offset="0x2A" ++ local wan_mac_offset="0x24" ++ ++ lan_mac=$(mtd_get_mac_binary $part_name $lan_mac_offset) ++ wan_mac=$(mtd_get_mac_binary $part_name $wan_mac_offset) + + case $board in + *mt3000*) +@@ -55,6 +100,20 @@ mediatek_setup_macs() + wan_mac=$(get_mac_binary /dev/mmcblk0p3 0x0a) + lan_mac=$(macaddr_add "$wan_mac" 1) + ;; ++ *360,t7*) ++ local part=$(find_mtd_part "stock-factory") ++ if [ -n "$part" ]; then ++ local factoryMac="$(dd if=$part bs=1 count=200 2>/dev/null |grep "^lanMac=")" ++ if [ -n "$factoryMac" ]; then ++ lan_mac="${factoryMac#lanMac=}" ++ wan_mac="$(macaddr_add $lan_mac 0x1)" ++ if [ "$(mtk_factory_get_byte "Factory" 4 2)" = "00-0c" ]; then ++ local wifi_mac="$(macaddr_add $lan_mac 0x2)" ++ mtk_facrory_write_mac "Factory" 4 $wifi_mac ++ fi ++ fi ++ fi ++ ;; + esac + + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" "$wan_mac" +-- +2.25.1 + From 53c4ab9cfa816da7db9fdd816d143fa35f2334a7 Mon Sep 17 00:00:00 2001 From: FUjr <53910283+FUjr@users.noreply.github.com> Date: Wed, 1 Mar 2023 13:06:56 +0000 Subject: [PATCH 14/18] fix :rm wrong 360t7 patch --- .../4010-support-360-t7.patch | 567 ------------------ 1 file changed, 567 deletions(-) delete mode 100644 patches-mt798x-7.6.6.1/4010-support-360-t7.patch diff --git a/patches-mt798x-7.6.6.1/4010-support-360-t7.patch b/patches-mt798x-7.6.6.1/4010-support-360-t7.patch deleted file mode 100644 index 17d9d1c..0000000 --- a/patches-mt798x-7.6.6.1/4010-support-360-t7.patch +++ /dev/null @@ -1,567 +0,0 @@ -From 88dde81e304c3bd316d96b306892f8578f47737e Mon Sep 17 00:00:00 2001 -From: fujr -Date: Mon, 27 Feb 2023 20:08:06 +0800 -Subject: [PATCH] add support for 360t7 - ---- - .../boot/dts/mediatek/mt7981-360-t7-108M.dts | 61 +++++ - .../boot/dts/mediatek/mt7981-360-t7-base.dtsi | 248 ++++++++++++++++++ - .../arm64/boot/dts/mediatek/mt7981-360-t7.dts | 71 +++++ - target/linux/mediatek/image/mt7981.mk | 35 +++ - .../mt7981/base-files/etc/board.d/01_leds | 6 + - .../mt7981/base-files/etc/board.d/02_network | 59 +++++ - 6 files changed, 480 insertions(+) - create mode 100644 target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts - create mode 100644 target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi - create mode 100644 target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts - -diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts -new file mode 100644 -index 0000000000..c1749442e3 ---- /dev/null -+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-108M.dts -@@ -0,0 +1,61 @@ -+/dts-v1/; -+#include "mt7981-360-t7-base.dtsi" -+ -+/ { -+ nmbm_spim_nand { -+ compatible = "generic,nmbm"; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ lower-mtd-device = <&spi_nand>; -+ forced-create; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "BL2"; -+ reg = <0x00 0x100000>; -+ }; -+ -+ partition@100000 { -+ label = "u-boot-env"; -+ reg = <0x100000 0x80000>; -+ }; -+ -+ partition@180000 { -+ label = "Factory"; -+ reg = <0x180000 0x200000>; -+ }; -+ -+ partition@380000 { -+ label = "FIP"; -+ reg = <0x380000 0x200000>; -+ }; -+ -+ partition@580000 { -+ label = "ubi"; -+ reg = <0x580000 0x6c00000>; -+ }; -+ -+ partition@7180000 { -+ label = "stock-config"; -+ reg = <0x7180000 0x100000>; -+ }; -+ -+ partition@7280000 { -+ label = "stock-factory"; -+ reg = <0x7280000 0x80000>; -+ }; -+ -+ partition@7300000 { -+ label = "stock-log"; -+ reg = <0x7300000 0x400000>; -+ }; -+ }; -+ }; -+}; -+ -diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi -new file mode 100644 -index 0000000000..1f3ce6da9e ---- /dev/null -+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7-base.dtsi -@@ -0,0 +1,248 @@ -+/dts-v1/; -+#include "mt7981.dtsi" -+ -+/ { -+ model = "360 T7"; -+ compatible = "360,t7", "mediatek,mt7981"; -+ -+ aliases { -+ led-boot = &red_led; -+ led-failsafe = &red_led; -+ led-running = &green_led; -+ led-upgrade = &green_led; -+ }; -+ -+ -+ gl-hw { -+ compatible = "gl-hw-info"; -+ model = "mt3000"; -+ wan = "eth0"; -+ lan = "eth1"; -+ temperature = "/sys/devices/virtual/thermal/thermal_zone0/temp"; -+ switch-button = "gpio-455"; -+ reset-button = "gpio-456"; -+ radio = "mt798111 mt798112"; -+ cfg-partition = "/dev/mtd7"; -+ flash_size = <128>; -+ dfs; -+ factory_data { -+ device_mac = "stock-factory", "0xb0"; -+ device_ddns = "stock-factory", "0xc0"; -+ device_sn_bak = "stock-factory", "0xd0"; -+ device_sn = "stock-factory", "0xe0"; -+ country_code = "stock-factory", "0x7a"; -+ }; -+ }; -+ -+ -+ chosen { -+ bootargs = "console=ttyS0,115200n1 loglevel=8 \ -+ earlycon=uart8250,mmio32,0x11002000"; -+ }; -+ -+ memory { -+ reg = <0 0x40000000 0 0x10000000>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ green_led: green { -+ label = "360t7:green"; -+ gpios = <&pio 7 GPIO_ACTIVE_LOW>; -+ }; -+ -+ red_led: red { -+ label = "360t7:red"; -+ gpios = <&pio 3 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ reset { -+ label = "reset"; -+ linux,code = ; -+ gpios = <&pio 1 GPIO_ACTIVE_LOW>; -+ }; -+ -+ wps { -+ label = "wps"; -+ linux,code = ; -+ gpios = <&pio 0 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gsw: gsw@0 { -+ compatible = "mediatek,mt753x"; -+ mediatek,ethsys = <ðsys>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "okay"; -+}; -+ -+ð { -+ status = "okay"; -+ -+ gmac0: mac@0 { -+ compatible = "mediatek,eth-mac"; -+ reg = <0>; -+ phy-mode = "2500base-x"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ -+ gmac1: mac@1 { -+ compatible = "mediatek,eth-mac"; -+ reg = <1>; -+ phy-mode = "2500base-x"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ -+ mdio: mdio-bus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ethernet-phy@0 { -+ compatible = "ethernet-phy-id03a2.9461"; -+ reg = <0x00>; -+ phy-mode = "gmii"; -+ nvmem-cells = <0x12>; -+ nvmem-cell-names = "phy-cal-data"; -+ }; -+ }; -+}; -+ -+&gsw { -+ mediatek,mdio = <&mdio>; -+ mediatek,mdio_master_pinmux = <0>; -+ reset-gpios = <&pio 39 0>; -+ interrupt-parent = <&pio>; -+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; -+ status = "okay"; -+ -+ port5: port@5 { -+ compatible = "mediatek,mt753x-port"; -+ reg = <5>; -+ phy-mode = "sgmii"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ }; -+ }; -+ -+ port6: port@6 { -+ compatible = "mediatek,mt753x-port"; -+ mediatek,ssc-on; -+ reg = <6>; -+ phy-mode = "sgmii"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ }; -+ }; -+}; -+ -+&hnat { -+ mtketh-wan = "eth1"; -+ mtketh-lan = "eth0"; -+ mtketh-max-gmac = <2>; -+ status = "okay"; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_flash_pins>; -+ status = "okay"; -+ -+ spi_nand: spi_nand@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ spi-tx-buswidth = <4>; -+ spi-rx-buswidth = <4>; -+ spi-cal-enable; -+ spi-cal-mode = "read-data"; -+ spi-cal-datalen = <7>; -+ spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; /* 'SPINAND' */ -+ spi-cal-addrlen = <5>; -+ spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; -+ }; -+}; -+ -+&pio { -+ pwm0_pin: pwm0-pin-g0 { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_0"; -+ }; -+ }; -+ -+ pwm1_pin: pwm1-pin-g0 { -+ mux { -+ function = "pwm"; -+ groups = "pwm1_0"; -+ }; -+ }; -+ -+ pwm2_pin: pwm2-pin { -+ mux { -+ function = "pwm"; -+ groups = "pwm2"; -+ }; -+ }; -+ -+ spi0_flash_pins: spi0-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ -+ conf-pu { -+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ }; -+ -+ uart1_pins: uart1-pins-g1 { -+ mux { -+ function = "uart"; -+ groups = "uart1_1"; -+ }; -+ }; -+ -+ uart2_pins: uart2-pins-g1 { -+ mux { -+ function = "uart"; -+ groups = "uart2_1"; -+ }; -+ }; -+}; -+ -diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts -new file mode 100644 -index 0000000000..8b1de92dfa ---- /dev/null -+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts -@@ -0,0 +1,71 @@ -+/dts-v1/; -+#include "mt7981-360-t7-base.dtsi" -+ -+/ { -+ nmbm_spim_nand { -+ compatible = "generic,nmbm"; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ lower-mtd-device = <&spi_nand>; -+ forced-create; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "BL2"; -+ reg = <0x00 0x100000>; -+ }; -+ -+ partition@100000 { -+ label = "u-boot-env"; -+ reg = <0x100000 0x80000>; -+ }; -+ -+ partition@180000 { -+ label = "Factory"; -+ reg = <0x180000 0x200000>; -+ }; -+ -+ partition@380000 { -+ label = "FIP"; -+ reg = <0x380000 0x200000>; -+ }; -+ -+ partition@580000 { -+ label = "ubi"; -+ reg = <0x580000 0x2400000>; -+ }; -+ -+ partition@2980000 { -+ label = "firmware-1"; -+ reg = <0x2980000 0x2400000>; -+ }; -+ -+ partition@4D80000 { -+ label = "plugin"; -+ reg = <0x4d80000 0x2400000>; -+ }; -+ -+ partition@7180000 { -+ label = "stock-config"; -+ reg = <0x7180000 0x100000>; -+ }; -+ -+ partition@7280000 { -+ label = "stock-factory"; -+ reg = <0x7280000 0x80000>; -+ }; -+ -+ partition@7300000 { -+ label = "stock-log"; -+ reg = <0x7300000 0x400000>; -+ }; -+ }; -+ }; -+}; -+ -diff --git a/target/linux/mediatek/image/mt7981.mk b/target/linux/mediatek/image/mt7981.mk -index b7f1f6d437..7a436bb61d 100755 ---- a/target/linux/mediatek/image/mt7981.mk -+++ b/target/linux/mediatek/image/mt7981.mk -@@ -222,3 +222,38 @@ define Device/glinet_gl-mt2500 - IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata - endef - TARGET_DEVICES += glinet_gl-mt2500 -+ -+define Device/mt7981-360-t7 -+ DEVICE_VENDOR := GL.iNet -+ DEVICE_MODEL := 360 T7 -+ DEVICE_DTS := mt7981-360-t7 -+ DEVICE_DTS_DIR := $(DTS_DIR)/mediatek -+ SUPPORTED_DEVICES := 360,t7 -+ UBINIZE_OPTS := -E 5 -+ BLOCKSIZE := 128k -+ PAGESIZE := 2048 -+ IMAGE_SIZE := 36864k -+ KERNEL_IN_UBI := 1 -+ IMAGES += factory.bin -+ IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) -+ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -+endef -+TARGET_DEVICES += mt7981-360-t7 -+ -+define Device/mt7981-360-t7-108M -+ DEVICE_VENDOR := GL.iNet -+ DEVICE_MODEL := 360 T7 (with 108M ubi) -+ DEVICE_DTS := mt7981-360-t7-108M -+ DEVICE_DTS_DIR := $(DTS_DIR)/mediatek -+ SUPPORTED_DEVICES := 360,t7 -+ UBINIZE_OPTS := -E 5 -+ BLOCKSIZE := 128k -+ PAGESIZE := 2048 -+ IMAGE_SIZE := 110592k -+ KERNEL_IN_UBI := 1 -+ IMAGES += factory.bin -+ IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) -+ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -+endef -+TARGET_DEVICES += mt7981-360-t7-108M -+ -diff --git a/target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds b/target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds -index 43905e604d..779ac123b1 100755 ---- a/target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds -+++ b/target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds -@@ -13,6 +13,12 @@ glinet,x3000-emmc) - ucidef_set_led_default "power" "POWER" "power" "1" - ;; - esac -+case "$(board_name)" in -+*360,t7*) -+ ucidef_set_led_default "green" "GREEN" "360t7:green" "1" -+ ucidef_set_led_default "red" "RED" "360t7:red" "0" -+ ;; -+esac - - board_config_flush - -diff --git a/target/linux/mediatek/mt7981/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7981/base-files/etc/board.d/02_network -index c2a22e425b..936ea35aea 100755 ---- a/target/linux/mediatek/mt7981/base-files/etc/board.d/02_network -+++ b/target/linux/mediatek/mt7981/base-files/etc/board.d/02_network -@@ -28,18 +28,63 @@ mediatek_setup_interfaces() - *mt2500*) - ucidef_set_interfaces_lan_wan eth1 eth0 - ;; -+ *360,t7*) -+ ucidef_set_interfaces_lan_wan "eth0" "eth1" -+ ucidef_add_switch "switch0" \ -+ "0:lan" "1:lan" "2:lan" "3:wan" "6u@eth0" "5u@eth1" -+ ;; - *) - ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1 - ;; - esac - } - -+mtk_facrory_write_mac() -+{ -+ local part_name=$1 -+ local offset=$2 -+ local macaddr=$3 #aa:bb:cc:dd:ee:ff -+ local data="" -+ -+ part=$(find_mtd_part $part_name) -+ if [ -n "$part" ] && [ -n "$macaddr" ]; then -+ local i=1 -+ for x in ${macaddr//:/ }; do -+ [ $i -gt 6 ] && break -+ data=${data}"\x${x}" -+ i=$((i+1)) -+ done -+ dd if=$part of=/tmp/Factory.backup -+ printf "${data}" | dd conv=notrunc of=/tmp/Factory.backup bs=1 seek=$((${offset})) -+ mtd write /tmp/Factory.backup $part_name -+ rm -rf /tmp/Factory.backup -+ fi -+} -+ -+mtk_factory_get_byte() -+{ -+ local part_name=$1 -+ local offset=$2 -+ local len=$3 -+ -+ part=$(find_mtd_part $part_name) -+ if [ -n "$part" ]; then -+ hexdump -n $len -s $offset -e ''`expr ${len} - 1`'/1 "%02x-" "%02x"' $part -+ fi -+} -+ -+ - mediatek_setup_macs() - { - local board="$1" - local part_name="Factory" - local lan_mac="" - local wan_mac="" -+ local lan_mac_offset="0x2A" -+ local wan_mac_offset="0x24" -+ -+ lan_mac=$(mtd_get_mac_binary $part_name $lan_mac_offset) -+ wan_mac=$(mtd_get_mac_binary $part_name $wan_mac_offset) - - case $board in - *mt3000*) -@@ -55,6 +100,20 @@ mediatek_setup_macs() - wan_mac=$(get_mac_binary /dev/mmcblk0p3 0x0a) - lan_mac=$(macaddr_add "$wan_mac" 1) - ;; -+ *360,t7*) -+ local part=$(find_mtd_part "stock-factory") -+ if [ -n "$part" ]; then -+ local factoryMac="$(dd if=$part bs=1 count=200 2>/dev/null |grep "^lanMac=")" -+ if [ -n "$factoryMac" ]; then -+ lan_mac="${factoryMac#lanMac=}" -+ wan_mac="$(macaddr_add $lan_mac 0x1)" -+ if [ "$(mtk_factory_get_byte "Factory" 4 2)" = "00-0c" ]; then -+ local wifi_mac="$(macaddr_add $lan_mac 0x2)" -+ mtk_facrory_write_mac "Factory" 4 $wifi_mac -+ fi -+ fi -+ fi -+ ;; - esac - - [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" "$wan_mac" --- -2.25.1 - From bc6a6aa9714bce4bb27a0987baf066a7c2752a16 Mon Sep 17 00:00:00 2001 From: FUjr <53910283+FUjr@users.noreply.github.com> Date: Wed, 1 Mar 2023 13:09:35 +0000 Subject: [PATCH 15/18] fix: fix wrong 360t7 guide --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index a3e04a4..df24ca9 100644 --- a/README.md +++ b/README.md @@ -86,7 +86,7 @@ https://github.com/hanwckf/bl-mt798x ``` ``` - cp ./glinet4.x/pkg_config/gl_pkg_config_mt7981_mt2500.mk ./glinet4.x/mt7981/gl_pkg_config.mk + cp ./glinet4.x/pkg_config/gl_pkg_config_mt7981_mt3000.mk ./glinet4.x/mt7981/gl_pkg_config.mk ``` ``` From 1b56bc60b4517f454cfe7a22110ebca285715c3d Mon Sep 17 00:00:00 2001 From: fujr Date: Thu, 2 Mar 2023 06:34:34 +0800 Subject: [PATCH 16/18] fix: miss depends --- profiles/target_mt7981_360t7-108M.yml | 13 ++++++++++++- profiles/target_mt7981_360t7.yml | 17 ++++++++++++++--- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/profiles/target_mt7981_360t7-108M.yml b/profiles/target_mt7981_360t7-108M.yml index 3fc72dd..56ace08 100644 --- a/profiles/target_mt7981_360t7-108M.yml +++ b/profiles/target_mt7981_360t7-108M.yml @@ -14,7 +14,7 @@ feeds: - name: gl_feed_mtk uri: https://github.com/gl-inet/gl-feeds.git revision: 5e48f72b4020fca612bedc480231c9081a00efa4 - + packages: - ethtool - iwinfo @@ -33,3 +33,14 @@ packages: - fwdd - kmod-mtfwd - kmod-mtqos + - kmod-zram + - tailscale + - tailscaled + - dhcpdiscover + - zram-swap + - zerotier + - kmod-fs-nfs-v4 + - kmod-fs-nfsd + - nfs-kernel-server + - nfs-utils-libs + - vsftpd-tls diff --git a/profiles/target_mt7981_360t7.yml b/profiles/target_mt7981_360t7.yml index 85650da..56ace08 100644 --- a/profiles/target_mt7981_360t7.yml +++ b/profiles/target_mt7981_360t7.yml @@ -1,8 +1,8 @@ --- -profile: mt7981-360-t7 +profile: mt7981-360-t7-108M target: mediatek subtarget: mt7981 -description: Build image for the GL.iNET 360T7 +description: Build image for the GL.iNET 360T7 108M feeds: - name: gl_feed_common @@ -14,7 +14,7 @@ feeds: - name: gl_feed_mtk uri: https://github.com/gl-inet/gl-feeds.git revision: 5e48f72b4020fca612bedc480231c9081a00efa4 - + packages: - ethtool - iwinfo @@ -33,3 +33,14 @@ packages: - fwdd - kmod-mtfwd - kmod-mtqos + - kmod-zram + - tailscale + - tailscaled + - dhcpdiscover + - zram-swap + - zerotier + - kmod-fs-nfs-v4 + - kmod-fs-nfsd + - nfs-kernel-server + - nfs-utils-libs + - vsftpd-tls From 3baa4a3ba156aed95feed1b79f6c9f42ead68da2 Mon Sep 17 00:00:00 2001 From: fujr Date: Thu, 2 Mar 2023 06:41:54 +0800 Subject: [PATCH 17/18] add support for original uboot of 360t7 --- .../4011-support-original-360t7-uboot.patch | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 patches-mt798x-7.6.6.1/4011-support-original-360t7-uboot.patch diff --git a/patches-mt798x-7.6.6.1/4011-support-original-360t7-uboot.patch b/patches-mt798x-7.6.6.1/4011-support-original-360t7-uboot.patch new file mode 100644 index 0000000..9c5edf7 --- /dev/null +++ b/patches-mt798x-7.6.6.1/4011-support-original-360t7-uboot.patch @@ -0,0 +1,90 @@ +From 12c791651c6ff7117e9ef7b2751e96a04e579458 Mon Sep 17 00:00:00 2001 +From: fujr +Date: Thu, 2 Mar 2023 06:38:10 +0800 +Subject: [PATCH] add support for origin uboot of 360t7(not recommmand) + +--- + .../arm64/boot/dts/mediatek/mt7981-360-t7.dts | 71 +++++++++++++++++++ + 1 file changed, 71 insertions(+) + create mode 100644 target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts + +diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts +new file mode 100644 +index 0000000000..8b1de92dfa +--- /dev/null ++++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-360-t7.dts +@@ -0,0 +1,71 @@ ++/dts-v1/; ++#include "mt7981-360-t7-base.dtsi" ++ ++/ { ++ nmbm_spim_nand { ++ compatible = "generic,nmbm"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ lower-mtd-device = <&spi_nand>; ++ forced-create; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x00 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "FIP"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x2400000>; ++ }; ++ ++ partition@2980000 { ++ label = "firmware-1"; ++ reg = <0x2980000 0x2400000>; ++ }; ++ ++ partition@4D80000 { ++ label = "plugin"; ++ reg = <0x4d80000 0x2400000>; ++ }; ++ ++ partition@7180000 { ++ label = "stock-config"; ++ reg = <0x7180000 0x100000>; ++ }; ++ ++ partition@7280000 { ++ label = "stock-factory"; ++ reg = <0x7280000 0x80000>; ++ }; ++ ++ partition@7300000 { ++ label = "stock-log"; ++ reg = <0x7300000 0x400000>; ++ }; ++ }; ++ }; ++}; ++ +-- +2.25.1 + From 44beab2bdc99712e172939380a30c478c6bfb6ac Mon Sep 17 00:00:00 2001 From: FUjr <53910283+FUjr@users.noreply.github.com> Date: Fri, 3 Mar 2023 17:03:49 +0800 Subject: [PATCH 18/18] move gl depends to proper config file --- profiles/glinet_depends.yml | 12 ++++++++++++ profiles/target_mt7981_360t7-108M.yml | 11 ----------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/profiles/glinet_depends.yml b/profiles/glinet_depends.yml index ef84380..de2b77a 100644 --- a/profiles/glinet_depends.yml +++ b/profiles/glinet_depends.yml @@ -99,6 +99,18 @@ packages: - tor - tor-geoip - swconfig + - kmod-zram + - tailscale + - tailscaled + - dhcpdiscover + - zram-swap + - zerotier + - kmod-fs-nfs-v4 + - kmod-fs-nfsd + - nfs-kernel-server + - nfs-utils-libs + - vsftpd-tls + diff --git a/profiles/target_mt7981_360t7-108M.yml b/profiles/target_mt7981_360t7-108M.yml index 56ace08..e285a9f 100644 --- a/profiles/target_mt7981_360t7-108M.yml +++ b/profiles/target_mt7981_360t7-108M.yml @@ -33,14 +33,3 @@ packages: - fwdd - kmod-mtfwd - kmod-mtqos - - kmod-zram - - tailscale - - tailscaled - - dhcpdiscover - - zram-swap - - zerotier - - kmod-fs-nfs-v4 - - kmod-fs-nfsd - - nfs-kernel-server - - nfs-utils-libs - - vsftpd-tls