diff --git a/configs/config-21.02.2.yml b/configs/config-21.02.2.yml new file mode 100644 index 0000000..1805a3a --- /dev/null +++ b/configs/config-21.02.2.yml @@ -0,0 +1,8 @@ +repo: https://github.com/openwrt/openwrt.git +branch: v21.02.2 +git_clone_dir: openwrt-21.02/openwrt-21.02.2 +openwrt_root_dir: openwrt-21.02/openwrt-21.02.2 +revision: 30e2782e0647a837044ada77ce86b29c5af8a9f2 + +patch_folders: + - patches-21.02.2/ diff --git a/patches-21.02.2/0001-ath79-add-support-for-gl-xe300.patch b/patches-21.02.2/0001-ath79-add-support-for-gl-xe300.patch new file mode 100644 index 0000000..5f4e00f --- /dev/null +++ b/patches-21.02.2/0001-ath79-add-support-for-gl-xe300.patch @@ -0,0 +1,602 @@ +From 426542a5861386b9f85ca636d7eecd7374c7b82b Mon Sep 17 00:00:00 2001 +From: "GL.iNet-Hongjian.Zhang" +Date: Fri, 17 Sep 2021 11:45:31 +0800 +Subject: [PATCH 1/8] ath79: add support for gl xe300 + +--- + include/image-commands.mk | 33 +++ + scripts/sysupgrade-tar-compat-1806.sh | 79 +++++++ + .../ath79/dts/qca9531_glinet_gl-xe300-iot.dts | 29 +++ + .../dts/qca9531_glinet_gl-xe300-nor-nand.dts | 25 +++ + .../ath79/dts/qca9531_glinet_gl-xe300-nor.dts | 18 ++ + .../ath79/dts/qca9531_glinet_gl-xe300.dtsi | 199 ++++++++++++++++++ + target/linux/ath79/dts/qca953x.dtsi | 2 +- + target/linux/ath79/image/Makefile | 2 +- + target/linux/ath79/image/nand.mk | 41 ++++ + .../ath79/nand/base-files/etc/board.d/01_leds | 7 + + .../nand/base-files/etc/board.d/02_network | 5 + + .../etc/uci-defaults/04_led_migration | 4 +- + .../nand/base-files/lib/upgrade/platform.sh | 4 + + 13 files changed, 444 insertions(+), 4 deletions(-) + create mode 100755 scripts/sysupgrade-tar-compat-1806.sh + create mode 100644 target/linux/ath79/dts/qca9531_glinet_gl-xe300-iot.dts + create mode 100644 target/linux/ath79/dts/qca9531_glinet_gl-xe300-nor-nand.dts + create mode 100644 target/linux/ath79/dts/qca9531_glinet_gl-xe300-nor.dts + create mode 100755 target/linux/ath79/dts/qca9531_glinet_gl-xe300.dtsi + +diff --git a/include/image-commands.mk b/include/image-commands.mk +index 4d54a14ba4..6908f5b5c1 100644 +--- a/include/image-commands.mk ++++ b/include/image-commands.mk +@@ -64,6 +64,31 @@ define Build/append-metadata + } + endef + ++metadata_gl_json = \ ++ '{ $(if $(IMAGE_METADATA),$(IMAGE_METADATA)$(comma)) \ ++ "metadata_version": "1.0", \ ++ "supported_devices":[$(call metadata_devices,$(1))], \ ++ "version": { \ ++ "release": "$(shell cat $(TOPDIR)/release)", \ ++ "date": "$(shell TZ='Asia/Chongqing' date '+%Y%m%d%H%M%S')", \ ++ "dist": "$(call json_quote,$(VERSION_DIST))", \ ++ "version": "$(call json_quote,$(VERSION_NUMBER))", \ ++ "revision": "$(call json_quote,$(REVISION))", \ ++ "target": "$(call json_quote,$(TARGETID))", \ ++ "board": "$(call json_quote,$(if $(BOARD_NAME),$(BOARD_NAME),$(DEVICE_NAME)))" \ ++ }, \ ++ }' ++ ++define Build/append-gl-metadata ++ $(if $(SUPPORTED_DEVICES),-echo $(call metadata_gl_json,$(SUPPORTED_DEVICES)) | fwtool -I - $@) ++ [ ! -s "$(BUILD_KEY)" -o ! -s "$(BUILD_KEY).ucert" -o ! -s "$@" ] || { \ ++ cp "$(BUILD_KEY).ucert" "$@.ucert" ;\ ++ usign -S -m "$@" -s "$(BUILD_KEY)" -x "$@.sig" ;\ ++ ucert -A -c "$@.ucert" -x "$@.sig" ;\ ++ fwtool -S "$@.ucert" "$@" ;\ ++ } ++endef ++ + define Build/append-rootfs + dd if=$(IMAGE_ROOTFS) >> $@ + endef +@@ -377,6 +402,14 @@ define Build/sysupgrade-tar + $@ + endef + ++define Build/sysupgrade-tar-compat-1806 ++ sh $(TOPDIR)/scripts/sysupgrade-tar-compat-1806.sh \ ++ --board $(if $(BOARD_NAME),$(BOARD_NAME),$(DEVICE_NAME)) \ ++ --kernel $(call param_get_default,kernel,$(1),$(IMAGE_KERNEL)) \ ++ --rootfs $(call param_get_default,rootfs,$(1),$(IMAGE_ROOTFS)) \ ++ $@ ++endef ++ + define Build/tplink-safeloader + -$(STAGING_DIR_HOST)/bin/tplink-safeloader \ + -B $(TPLINK_BOARD_ID) \ +diff --git a/scripts/sysupgrade-tar-compat-1806.sh b/scripts/sysupgrade-tar-compat-1806.sh +new file mode 100755 +index 0000000000..c479688e55 +--- /dev/null ++++ b/scripts/sysupgrade-tar-compat-1806.sh +@@ -0,0 +1,79 @@ ++#!/bin/sh ++ ++board="" ++board1806="" ++kernel="" ++rootfs="" ++outfile="" ++err="" ++ ++while [ "$1" ]; do ++ case "$1" in ++ "--board") ++ board="$2" ++ shift ++ shift ++ continue ++ ;; ++ "--kernel") ++ kernel="$2" ++ shift ++ shift ++ continue ++ ;; ++ "--rootfs") ++ rootfs="$2" ++ shift ++ shift ++ continue ++ ;; ++ *) ++ if [ ! "$outfile" ]; then ++ outfile=$1 ++ shift ++ continue ++ fi ++ ;; ++ esac ++done ++ ++if [ ! -n "$board" -o ! -r "$kernel" -a ! -r "$rootfs" -o ! "$outfile" ]; then ++ echo "syntax: $0 [--board boardname] [--kernel kernelimage] [--rootfs rootfs] out" ++ exit 1 ++fi ++ ++tmpdir="$( mktemp -d 2> /dev/null )" ++if [ -z "$tmpdir" ]; then ++ # try OSX signature ++ tmpdir="$( mktemp -t 'ubitmp' -d )" ++fi ++ ++if [ -z "$tmpdir" ]; then ++ exit 1 ++fi ++ ++echo "$tmpdir ########################################################" ++ ++board1806="$(echo "$board"|cut -d '_' -f 2|awk -F '-' '{print $1 "-" $2}')" ++mkdir -p "${tmpdir}/sysupgrade-${board}" ++echo "BOARD=${board}" > "${tmpdir}/sysupgrade-${board}/CONTROL" ++mkdir -p "${tmpdir}/sysupgrade-${board1806}" ++echo "BOARD=${board1806}" > "${tmpdir}/sysupgrade-${board1806}/CONTROL" ++[ -z "${rootfs}" ] || cp "${rootfs}" "${tmpdir}/sysupgrade-${board}/root" ++[ -z "${kernel}" ] || cp "${kernel}" "${tmpdir}/sysupgrade-${board}/kernel" ++ ++mtime="" ++if [ -n "$SOURCE_DATE_EPOCH" ]; then ++ mtime="--mtime=@${SOURCE_DATE_EPOCH}" ++fi ++ ++(cd "$tmpdir"; tar --sort=name --owner=0 --group=0 --numeric-owner -cvf sysupgrade.tar sysupgrade-${board} sysupgrade-${board1806} ${mtime}) ++err="$?" ++if [ -e "$tmpdir/sysupgrade.tar" ]; then ++ cp "$tmpdir/sysupgrade.tar" "$outfile" ++else ++ err=2 ++fi ++rm -rf "$tmpdir" ++ ++exit $err +diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-xe300-iot.dts b/target/linux/ath79/dts/qca9531_glinet_gl-xe300-iot.dts +new file mode 100644 +index 0000000000..461ec1720a +--- /dev/null ++++ b/target/linux/ath79/dts/qca9531_glinet_gl-xe300-iot.dts +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++/dts-v1/; ++ ++#include "qca9531_glinet_gl-xe300.dtsi" ++ ++/ { ++ compatible = "glinet,gl-xe300-iot", "qca,qca9531"; ++ model = "GL.iNet GL-XE300 (NOR/NAND IOT)"; ++}; ++ ++&nor_partitions { ++ partition@60000 { ++ label = "kernel"; ++ reg = <0x060000 0x400000>; ++ }; ++ parition@460000 { ++ label = "nor_reserved"; ++ reg = <0x460000 0xba0000>; ++ }; ++}; ++ ++&nand_ubi { ++ label = "ubi"; ++}; ++ ++&bootargs { ++ bootargs=""; ++}; +diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-xe300-nor-nand.dts b/target/linux/ath79/dts/qca9531_glinet_gl-xe300-nor-nand.dts +new file mode 100644 +index 0000000000..35117ad875 +--- /dev/null ++++ b/target/linux/ath79/dts/qca9531_glinet_gl-xe300-nor-nand.dts +@@ -0,0 +1,25 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++/dts-v1/; ++ ++#include "qca9531_glinet_gl-xe300.dtsi" ++ ++/ { ++ compatible = "glinet,gl-xe300-nor-nand", "qca,qca9531"; ++ model = "GL.iNet GL-XE300 (NOR/NAND)"; ++}; ++ ++&nor_partitions { ++ partition@60000 { ++ label = "kernel"; ++ reg = <0x060000 0x400000>; ++ }; ++ parition@460000 { ++ label = "nor_reserved"; ++ reg = <0x460000 0xba0000>; ++ }; ++}; ++ ++&nand_ubi { ++ label = "ubi"; ++}; +diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-xe300-nor.dts b/target/linux/ath79/dts/qca9531_glinet_gl-xe300-nor.dts +new file mode 100644 +index 0000000000..9b67f49368 +--- /dev/null ++++ b/target/linux/ath79/dts/qca9531_glinet_gl-xe300-nor.dts +@@ -0,0 +1,18 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++/dts-v1/; ++ ++#include "qca9531_glinet_gl-xe300.dtsi" ++ ++/ { ++ compatible = "glinet,gl-xe300-nor", "qca,qca9531"; ++ model = "GL.iNet GL-XE300 (NOR)"; ++}; ++ ++&nor_partitions { ++ partition@60000 { ++ compatible = "denx,uimage"; ++ label = "firmware"; ++ reg = <0x060000 0xfa0000>; ++ }; ++}; +diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dtsi b/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dtsi +new file mode 100755 +index 0000000000..07e4f9cd44 +--- /dev/null ++++ b/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dtsi +@@ -0,0 +1,199 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/dts-v1/; ++ ++#include ++#include ++ ++#include "qca953x.dtsi" ++ ++/ { ++ compatible = "glinet,gl-xe300", "qca,qca9531"; ++ model = "GL.iNet GL-XE300"; ++ ++ gl_hw { ++ compatible = "gl-hw-info"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "xe300"; ++ wan = "eth1"; ++ lan = "eth0"; ++ build-in-modem = "1-1.2"; ++ reset-button = "gpio-3"; ++ usb-port = "1-1.3"; ++ nand; ++ factory_data { ++ device_mac = "art"; ++ device_ddns = "art", "0x10"; ++ device_sn_bak = "art", "0x20"; ++ device_sn = "art", "0x30"; ++ country_code = "art", "0x88"; ++ }; ++ }; ++ ++ keys { ++ compatible = "gpio-keys-polled"; ++ ++ poll-interval = <20>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&jtag_disable_pins>; ++ ++ button0 { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&gpio 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ wan { ++ label = "gl-xe300:green:wan"; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ lan { ++ label = "gl-xe300:green:lan"; ++ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wlan { ++ label = "gl-xe300:green:wlan"; ++ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "phy0tpt"; ++ }; ++ ++ lte { ++ label = "gl-xe300:green:lte"; ++ gpios = <&gpio 13 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-export { ++ compatible = "gpio-export"; ++ ++ gpio_lte_power { ++ gpio-export,name = "lte_power"; ++ gpio-export,output = <1>; ++ gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ gpio_sd_detect { ++ gpio-export,name = "sd_detect"; ++ gpio-export,output = <0>; ++ gpios = <&gpio 17 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ i2c: i2c { ++ compatible = "i2c-gpio"; ++ ++ sda-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; ++ scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rtc@32 { ++ compatible = "rtc-sd2068"; ++ reg = <0x32>; ++ }; ++ ++ }; ++}; ++ ++&pcie0 { ++ status = "okay"; ++}; ++ ++&uart { ++ status = "okay"; ++}; ++ ++&usb0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub_port: port@1 { ++ reg = <1>; ++ #trigger-source-cells = <0>; ++ }; ++}; ++ ++&usb_phy { ++ status = "okay"; ++}; ++ ++&spi { ++ status = "okay"; ++ num-cs = <2>; ++ cs-gpios = <0>, <0>; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <25000000>; ++ ++ nor_partitions: partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x000000 0x040000>; ++ read-only; ++ }; ++ ++ partition@40000 { ++ label = "u-boot-env"; ++ reg = <0x040000 0x010000>; ++ }; ++ ++ art: partition@50000 { ++ label = "art"; ++ reg = <0x050000 0x010000>; ++ read-only; ++ }; ++ }; ++ }; ++ ++ flash_nand: flash@1 { ++ compatible = "spi-nand"; ++ reg = <1>; ++ spi-max-frequency = <25000000>; ++ ++ nand_partitions: partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ nand_ubi: partition@0 { ++ label = "nand_ubi"; ++ reg = <0x000000 0x8000000>; ++ }; ++ }; ++ }; ++ ++}; ++ ++ð0 { ++ status = "okay"; ++ mtd-mac-address = <&art 0x0>; ++ phy-handle = <&swphy4>; ++ ifname = "eth1"; ++}; ++ ++ð1 { ++ mtd-mac-address = <&art 0x0>; ++ mtd-mac-address-increment = <1>; ++ ifname = "eth0"; ++}; ++ ++&wmac { ++ status = "okay"; ++ mtd-cal-data = <&art 0x1000>; ++ mtd-mac-address = <&art 0x1002>; ++}; +diff --git a/target/linux/ath79/dts/qca953x.dtsi b/target/linux/ath79/dts/qca953x.dtsi +index 801438be29..943e42437a 100644 +--- a/target/linux/ath79/dts/qca953x.dtsi ++++ b/target/linux/ath79/dts/qca953x.dtsi +@@ -8,7 +8,7 @@ + #address-cells = <1>; + #size-cells = <1>; + +- chosen { ++ bootargs: chosen { + bootargs = "console=ttyS0,115200n8"; + }; + +diff --git a/target/linux/ath79/image/Makefile b/target/linux/ath79/image/Makefile +index 3c126f479e..439d1710e5 100644 +--- a/target/linux/ath79/image/Makefile ++++ b/target/linux/ath79/image/Makefile +@@ -77,7 +77,7 @@ define Device/Default + COMPILE := + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin = append-kernel | pad-to $$$$(BLOCKSIZE) | \ +- append-rootfs | pad-rootfs | append-metadata | check-size ++ append-rootfs | pad-rootfs | append-gl-metadata | check-size + endef + + include $(SUBTARGET).mk +diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk +index abf269a8ce..cfc07f14a3 100644 +--- a/target/linux/ath79/image/nand.mk ++++ b/target/linux/ath79/image/nand.mk +@@ -107,6 +107,47 @@ define Device/glinet_gl-ar300m-nor + endef + TARGET_DEVICES += glinet_gl-ar300m-nor + ++define Device/glinet_gl-xe300-common ++ SOC := qca9531 ++ DEVICE_VENDOR := GL.iNet ++ DEVICE_MODEL := GL-XE300 ++ DEVICE_PACKAGES := kmod-usb2 block-mount kmod-usb-serial-ch341 ++ SUPPORTED_DEVICES += gl-xe300 glinet,gl-xe300 ++endef ++ ++define Device/glinet_gl-xe300-nor ++ $(Device/glinet_gl-xe300-common) ++ DEVICE_VARIANT := NOR ++ IMAGE_SIZE := 16000k ++endef ++TARGET_DEVICES += glinet_gl-xe300-nor ++ ++define Device/glinet_gl-xe300-nor-nand ++ $(Device/glinet_gl-xe300-common) ++ DEVICE_VARIANT := NOR/NAND ++ KERNEL_SIZE := 4096k ++ BLOCKSIZE := 128k ++ PAGESIZE := 2048 ++ VID_HDR_OFFSET := 2048 ++ IMAGES := factory.img sysupgrade.tar ++ IMAGE/sysupgrade.tar := sysupgrade-tar-compat-1806 | append-gl-metadata ++ IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | append-gl-metadata ++endef ++TARGET_DEVICES += glinet_gl-xe300-nor-nand ++ ++define Device/glinet_gl-xe300-iot ++ $(Device/glinet_gl-xe300-common) ++ DEVICE_VARIANT := NOR/NAND IOT ++ KERNEL_SIZE := 4096k ++ BLOCKSIZE := 128k ++ PAGESIZE := 2048 ++ VID_HDR_OFFSET := 2048 ++ IMAGES := factory.img sysupgrade.tar ++ IMAGE/sysupgrade.tar := sysupgrade-tar-compat-1806 | append-gl-metadata ++ IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | append-gl-metadata ++endef ++TARGET_DEVICES += glinet_gl-xe300-iot ++ + define Device/glinet_gl-ar750s-common + SOC := qca9563 + DEVICE_VENDOR := GL.iNet +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/01_leds b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +index 8eda666a81..4a90c4673f 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/01_leds ++++ b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +@@ -11,6 +11,13 @@ glinet,gl-ar300m-nand|\ + glinet,gl-ar300m-nor) + ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" + ;; ++glinet,gl-xe300-iot|\ ++glinet,gl-xe300-nor|\ ++glinet,gl-xe300-nor-nand) ++ ucidef_set_led_switch "lan" "LAN" "gl-xe300:green:lan" "switch0" "0x10" ++ ucidef_set_led_netdev "wan" "WAN" "gl-xe300:green:wan" "eth1" ++ ucidef_set_led_netdev "3gnet" "LTE" "gl-xe300:green:lte" "wwan0" ++ ;; + netgear,wndr3700-v4|\ + netgear,wndr4300|\ + netgear,wndr4300sw|\ +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/02_network b/target/linux/ath79/nand/base-files/etc/board.d/02_network +index 910df517aa..17348e001b 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/02_network ++++ b/target/linux/ath79/nand/base-files/etc/board.d/02_network +@@ -21,6 +21,11 @@ ath79_setup_interfaces() + ucidef_add_switch "switch0" \ + "0@eth0" "2:lan:2" "3:lan:1" "1:wan" + ;; ++ glinet,gl-xe300-iot|\ ++ glinet,gl-xe300-nor|\ ++ glinet,gl-xe300-nor-nand) ++ ucidef_set_interfaces_lan_wan "eth0" "eth1" ++ ;; + netgear,wndr3700-v4|\ + netgear,wndr4300|\ + netgear,wndr4300sw|\ +diff --git a/target/linux/ath79/nand/base-files/etc/uci-defaults/04_led_migration b/target/linux/ath79/nand/base-files/etc/uci-defaults/04_led_migration +index 281d6ac0bc..3175ca9cb4 100644 +--- a/target/linux/ath79/nand/base-files/etc/uci-defaults/04_led_migration ++++ b/target/linux/ath79/nand/base-files/etc/uci-defaults/04_led_migration +@@ -6,8 +6,8 @@ board=$(board_name) + case "$board" in + esac + +-remove_devicename_leds ++#remove_devicename_leds + +-migrations_apply system ++#migrations_apply system + + exit 0 +diff --git a/target/linux/ath79/nand/base-files/lib/upgrade/platform.sh b/target/linux/ath79/nand/base-files/lib/upgrade/platform.sh +index ea77345b06..c9b336898e 100644 +--- a/target/linux/ath79/nand/base-files/lib/upgrade/platform.sh ++++ b/target/linux/ath79/nand/base-files/lib/upgrade/platform.sh +@@ -22,6 +22,10 @@ platform_do_upgrade() { + glinet,gl-ar750s-nor-nand) + nand_nor_do_upgrade "$1" + ;; ++ glinet,gl-xe300-iot|\ ++ glinet,gl-xe300-nor-nand) ++ nand_nor_do_upgrade "$1" ++ ;; + *) + nand_do_upgrade "$1" + ;; +-- +2.17.1 + diff --git a/patches-21.02.2/0002-ath79-add-support-for-gl-mifi.patch b/patches-21.02.2/0002-ath79-add-support-for-gl-mifi.patch new file mode 100644 index 0000000..44ce5a9 --- /dev/null +++ b/patches-21.02.2/0002-ath79-add-support-for-gl-mifi.patch @@ -0,0 +1,1887 @@ +From 120ee81bb20b8aa01998916c87f763bdcc9e327f Mon Sep 17 00:00:00 2001 +From: "GL.iNet-Hongjian.Zhang" +Date: Sat, 18 Sep 2021 10:39:16 +0800 +Subject: [PATCH 2/8] ath79: add support for gl mifi + +--- + target/linux/ath79/dts/ar9330_glinet.dtsi | 218 +++ + .../linux/ath79/dts/ar9331_glinet_gl-mifi.dts | 83 +- + .../net/ethernet/atheros/ag71xx/Makefile | 1 + + .../ethernet/atheros/ag71xx/ag71xx_ar7240.c | 1349 +++++++++++++++++ + .../net/ethernet/atheros/ag71xx/ag71xx_main.c | 4 + + .../generic/base-files/etc/board.d/01_leds | 1 - + .../etc/uci-defaults/04_led_migration | 3 - + target/linux/ath79/image/generic.mk | 10 - + target/linux/ath79/image/nand.mk | 10 + + .../ath79/nand/base-files/etc/board.d/01_leds | 6 + + .../nand/base-files/etc/board.d/02_network | 3 + + 11 files changed, 1647 insertions(+), 41 deletions(-) + create mode 100644 target/linux/ath79/dts/ar9330_glinet.dtsi + create mode 100755 target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c + +diff --git a/target/linux/ath79/dts/ar9330_glinet.dtsi b/target/linux/ath79/dts/ar9330_glinet.dtsi +new file mode 100644 +index 0000000000..77387bf37c +--- /dev/null ++++ b/target/linux/ath79/dts/ar9330_glinet.dtsi +@@ -0,0 +1,218 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++#include ++#include "ath79.dtsi" ++ ++/ { ++ compatible = "qca,ar9330"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "mips,mips24Kc"; ++ clocks = <&pll ATH79_CLK_CPU>; ++ reg = <0>; ++ }; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyATH0,115200"; ++ }; ++ ++ ahb { ++ apb { ++ ddr_ctrl: memory-controller@18000000 { ++ compatible = "qca,ar7240-ddr-controller"; ++ reg = <0x18000000 0x100>; ++ ++ #qca,ddr-wb-channel-cells = <1>; ++ }; ++ ++ uart: uart@18020000 { ++ compatible = "qca,ar9330-uart"; ++ reg = <0x18020000 0x14>; ++ ++ interrupts = <3>; ++ ++ clocks = <&pll ATH79_CLK_REF>; ++ clock-names = "uart"; ++ ++ status = "disabled"; ++ }; ++ ++ gpio: gpio@18040000 { ++ compatible = "qca,ar7100-gpio"; ++ reg = <0x18040000 0x34>; ++ interrupts = <2>; ++ ++ ngpios = <30>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ pinmux: pinmux@18040028 { ++ compatible = "pinctrl-single"; ++ reg = <0x18040028 0x8>; ++ ++ pinctrl-single,bit-per-mux; ++ pinctrl-single,register-width = <32>; ++ pinctrl-single,function-mask = <0x1>; ++ #pinctrl-cells = <2>; ++ ++ jtag_disable_pins: pinmux_jtag_disable_pins { ++ pinctrl-single,bits = <0x0 0x1 0x1>; ++ }; ++ ++ switch_led_disable_pins: pinmux_switch_led_disable_pins { ++ pinctrl-single,bits = <0x0 0x0 0xf8>; ++ }; ++ }; ++ ++ pll: pll-controller@18050000 { ++ compatible = "qca,ar9330-pll"; ++ reg = <0x18050000 0x100>; ++ ++ #clock-cells = <1>; ++ }; ++ ++ wdt: wdt@18060008 { ++ compatible = "qca,ar7130-wdt"; ++ reg = <0x18060008 0x8>; ++ ++ interrupts = <4>; ++ ++ clocks = <&pll ATH79_CLK_AHB>; ++ clock-names = "wdt"; ++ }; ++ ++ rst: reset-controller@1806001c { ++ compatible = "qca,ar7100-reset"; ++ reg = <0x1806001c 0x4>; ++ ++ #reset-cells = <1>; ++ }; ++ }; ++ ++ usb: usb@1b000000 { ++ compatible = "generic-ehci"; ++ reg = <0x1b000000 0x200>; ++ ++ interrupts = <3>; ++ resets = <&rst 5>; ++ reset-names = "usb-host"; ++ dr_mode = "host"; ++ ++ has-transaction-translator; ++ caps-offset = <0x100>; ++ ++ phy-names = "usb-phy"; ++ phys = <&usb_phy>; ++ ++ status = "disabled"; ++ }; ++ ++ spi: spi@1f000000 { ++ compatible = "qca,ar7100-spi"; ++ reg = <0x1f000000 0x10>; ++ ++ clocks = <&pll ATH79_CLK_AHB>; ++ clock-names = "ahb"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ ++ gmac: gmac@18070000 { ++ compatible = "qca,ar9330-gmac"; ++ reg = <0x18070000 0x4>; ++ }; ++ ++ wmac: wmac@18100000 { ++ compatible = "qca,ar9330-wmac"; ++ reg = <0x18100000 0x20000>; ++ ++ interrupts = <2>; ++ ++ status = "disabled"; ++ }; ++ }; ++ ++ usb_phy: usb-phy { ++ compatible = "qca,ar7200-usb-phy"; ++ ++ reset-names = "usb-phy", "usb-suspend-override"; ++ resets = <&rst 4>, <&rst 3>; ++ ++ #phy-cells = <0>; ++ ++ status = "disabled"; ++ }; ++}; ++ ++&cpuintc { ++ qca,ddr-wb-channel-interrupts = <2>, <3>; ++ qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>; ++}; ++ ++ð0 { ++ compatible = "qca,ar9330-eth", "syscon"; ++ ++ pll-data = <0x00110000 0x00001099 0x00991099>; ++ ++ resets = <&rst 9>; ++ reset-names = "mac"; ++ phy-mode = "mii"; ++ phy-handle = <&swphy4>; ++}; ++ ++&mdio1 { ++ status = "okay"; ++ compatible = "qca,ar9330-mdio"; ++ ++ resets = <&rst 23>; ++ reset-names = "mdio"; ++ builtin-switch; ++ ++ builtin_switch: switch0@1f { ++ compatible = "qca,ar8216-builtin"; ++ reg = <0x1f>; ++ resets = <&rst 8>; ++ reset-names = "switch"; ++ ++ mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ swphy4: ethernet-phy@4 { ++ reg = <4>; ++ phy-mode = "mii"; ++ }; ++ }; ++ }; ++}; ++ ++ð1 { ++ compatible = "qca,ar9330-eth", "syscon"; ++ ++ pll-data = <0x00110000 0x00001099 0x00991099>; ++ phy-mode = "gmii"; ++ ++ resets = <&rst 13>; ++ reset-names = "mac"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++}; +diff --git a/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts b/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts +index 7d6e7bd4af..863275b712 100644 +--- a/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts ++++ b/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts +@@ -1,39 +1,59 @@ + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +-#include "ar9331.dtsi" ++#include "ar9330_glinet.dtsi" + + #include + #include + + / { +- compatible = "glinet,gl-mifi", "qca,ar9331"; ++ compatible = "glinet,gl-mifi", "qca,ar9330"; + model = "GL.iNet GL-MiFi"; + +- aliases { +- label-mac-device = ð0; +- }; +- +- leds { ++ aliases { ++ serial0 = &uart; ++ }; ++ ++ gl_hw { ++ compatible = "gl-hw-info"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "mifi"; ++ wan = "eth0"; ++ lan = "eth1"; ++ build-in-modem = "1-1.2"; ++ reset-button = "gpio-11"; ++ usb-port = "1-1.3"; ++ factory_data { ++ device_mac = "art"; ++ device_ddns = "art", "0x10"; ++ device_sn_bak = "art", "0x20"; ++ device_sn = "art", "0x30"; ++ country_code = "art", "0x88"; ++ }; ++ }; ++ ++ leds { + compatible = "gpio-leds"; + + wlan { +- label = "green:wlan"; ++ label = "gl-mifi:green:wlan"; + gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; + }; + + lan { +- label = "green:lan"; ++ label = "gl-mifi:green:lan"; + gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + }; + + wan { +- label = "green:wan"; ++ label = "gl-mifi:green:wan"; + gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; + }; + +- 3g4g { +- label = "green:3g4g"; ++ net { ++ label = "gl-mifi:green:net"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + }; + }; +@@ -49,14 +69,6 @@ + }; + }; + +- reg_usb_vbus: reg_usb_vbus { +- compatible = "regulator-fixed"; +- regulator-name = "usb_vbus"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- gpio = <&gpio 6 GPIO_ACTIVE_LOW>; +- }; +- + gpio-export { + compatible = "gpio-export"; + +@@ -65,14 +77,27 @@ + gpio-export,output = <0>; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + }; ++ gpio_usb_power { ++ gpio-export,name = "usb_power"; ++ gpio-export,output = <0>; ++ gpios = <&gpio 6 GPIO_ACTIVE_LOW>; ++ }; + }; + }; + ++&uart { ++ status = "okay"; ++}; ++ + &usb { + status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; + +- dr_mode = "host"; +- vbus-supply = <®_usb_vbus>; ++ hub_port: port@1 { ++ reg = <1>; ++ #trigger-source-cells = <0>; ++ }; + }; + + &usb_phy { +@@ -122,6 +147,14 @@ + status = "okay"; + + mtd-mac-address = <&art 0x0>; ++ ifname = "eth0"; ++}; ++ ++ð1 { ++ status = "okay"; ++ ++ mtd-mac-address = <&art 0x0>; ++ ifname = "eth1"; + + gmac-config { + device = <&gmac>; +@@ -131,14 +164,10 @@ + }; + }; + +-ð1 { +- status = "okay"; +- +- mtd-mac-address = <&art 0x0>; +-}; + + &wmac { + status = "okay"; + + mtd-cal-data = <&art 0x1000>; ++ mtd-mac-address = <&art 0x0>; + }; +diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/Makefile b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/Makefile +index 87add0d208..480dbb62c0 100644 +--- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/Makefile ++++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/Makefile +@@ -9,5 +9,6 @@ ag71xx-y += ag71xx_phy.o + + ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o + ++obj-$(CONFIG_AG71XX) += ag71xx_ar7240.o + obj-$(CONFIG_AG71XX) += ag71xx_mdio.o + obj-$(CONFIG_AG71XX) += ag71xx.o +diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c +new file mode 100755 +index 0000000000..600e0d49d2 +--- /dev/null ++++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c +@@ -0,0 +1,1349 @@ ++/* ++ * Driver for the built-in ethernet switch of the Atheros AR7240 SoC ++ * Copyright (c) 2010 Gabor Juhos ++ * Copyright (c) 2010 Felix Fietkau ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ag71xx.h" ++ ++#define BITM(_count) (BIT(_count) - 1) ++#define BITS(_shift, _count) (BITM(_count) << _shift) ++ ++#define AR7240_REG_MASK_CTRL 0x00 ++#define AR7240_MASK_CTRL_REVISION_M BITM(8) ++#define AR7240_MASK_CTRL_VERSION_M BITM(8) ++#define AR7240_MASK_CTRL_VERSION_S 8 ++#define AR7240_MASK_CTRL_VERSION_AR7240 0x01 ++#define AR7240_MASK_CTRL_VERSION_AR934X 0x02 ++#define AR7240_MASK_CTRL_SOFT_RESET BIT(31) ++ ++#define AR7240_REG_MAC_ADDR0 0x20 ++#define AR7240_REG_MAC_ADDR1 0x24 ++ ++#define AR7240_REG_FLOOD_MASK 0x2c ++#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26) ++ ++#define AR7240_REG_GLOBAL_CTRL 0x30 ++#define AR7240_GLOBAL_CTRL_MTU_M BITM(11) ++#define AR9340_GLOBAL_CTRL_MTU_M BITM(14) ++ ++#define AR7240_REG_VTU 0x0040 ++#define AR7240_VTU_OP BITM(3) ++#define AR7240_VTU_OP_NOOP 0x0 ++#define AR7240_VTU_OP_FLUSH 0x1 ++#define AR7240_VTU_OP_LOAD 0x2 ++#define AR7240_VTU_OP_PURGE 0x3 ++#define AR7240_VTU_OP_REMOVE_PORT 0x4 ++#define AR7240_VTU_ACTIVE BIT(3) ++#define AR7240_VTU_FULL BIT(4) ++#define AR7240_VTU_PORT BITS(8, 4) ++#define AR7240_VTU_PORT_S 8 ++#define AR7240_VTU_VID BITS(16, 12) ++#define AR7240_VTU_VID_S 16 ++#define AR7240_VTU_PRIO BITS(28, 3) ++#define AR7240_VTU_PRIO_S 28 ++#define AR7240_VTU_PRIO_EN BIT(31) ++ ++#define AR7240_REG_VTU_DATA 0x0044 ++#define AR7240_VTUDATA_MEMBER BITS(0, 10) ++#define AR7240_VTUDATA_VALID BIT(11) ++ ++#define AR7240_REG_ATU 0x50 ++#define AR7240_ATU_FLUSH_ALL 0x1 ++ ++#define AR7240_REG_AT_CTRL 0x5c ++#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15) ++#define AR7240_AT_CTRL_AGE_EN BIT(17) ++#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18) ++#define AR7240_AT_CTRL_RESERVED BIT(19) ++#define AR7240_AT_CTRL_ARP_EN BIT(20) ++ ++#define AR7240_REG_TAG_PRIORITY 0x70 ++ ++#define AR7240_REG_SERVICE_TAG 0x74 ++#define AR7240_SERVICE_TAG_M BITM(16) ++ ++#define AR7240_REG_CPU_PORT 0x78 ++#define AR7240_MIRROR_PORT_S 4 ++#define AR7240_MIRROR_PORT_M BITM(4) ++#define AR7240_CPU_PORT_EN BIT(8) ++ ++#define AR7240_REG_MIB_FUNCTION0 0x80 ++#define AR7240_MIB_TIMER_M BITM(16) ++#define AR7240_MIB_AT_HALF_EN BIT(16) ++#define AR7240_MIB_BUSY BIT(17) ++#define AR7240_MIB_FUNC_S 24 ++#define AR7240_MIB_FUNC_M BITM(3) ++#define AR7240_MIB_FUNC_NO_OP 0x0 ++#define AR7240_MIB_FUNC_FLUSH 0x1 ++#define AR7240_MIB_FUNC_CAPTURE 0x3 ++ ++#define AR7240_REG_MDIO_CTRL 0x98 ++#define AR7240_MDIO_CTRL_DATA_M BITM(16) ++#define AR7240_MDIO_CTRL_REG_ADDR_S 16 ++#define AR7240_MDIO_CTRL_PHY_ADDR_S 21 ++#define AR7240_MDIO_CTRL_CMD_WRITE 0 ++#define AR7240_MDIO_CTRL_CMD_READ BIT(27) ++#define AR7240_MDIO_CTRL_MASTER_EN BIT(30) ++#define AR7240_MDIO_CTRL_BUSY BIT(31) ++ ++#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) ++ ++#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00) ++#define AR7240_PORT_STATUS_SPEED_S 0 ++#define AR7240_PORT_STATUS_SPEED_M BITM(2) ++#define AR7240_PORT_STATUS_SPEED_10 0 ++#define AR7240_PORT_STATUS_SPEED_100 1 ++#define AR7240_PORT_STATUS_SPEED_1000 2 ++#define AR7240_PORT_STATUS_TXMAC BIT(2) ++#define AR7240_PORT_STATUS_RXMAC BIT(3) ++#define AR7240_PORT_STATUS_TXFLOW BIT(4) ++#define AR7240_PORT_STATUS_RXFLOW BIT(5) ++#define AR7240_PORT_STATUS_DUPLEX BIT(6) ++#define AR7240_PORT_STATUS_LINK_UP BIT(8) ++#define AR7240_PORT_STATUS_LINK_AUTO BIT(9) ++#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10) ++ ++#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04) ++#define AR7240_PORT_CTRL_STATE_M BITM(3) ++#define AR7240_PORT_CTRL_STATE_DISABLED 0 ++#define AR7240_PORT_CTRL_STATE_BLOCK 1 ++#define AR7240_PORT_CTRL_STATE_LISTEN 2 ++#define AR7240_PORT_CTRL_STATE_LEARN 3 ++#define AR7240_PORT_CTRL_STATE_FORWARD 4 ++#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7) ++#define AR7240_PORT_CTRL_VLAN_MODE_S 8 ++#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0 ++#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1 ++#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2 ++#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3 ++#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10) ++#define AR7240_PORT_CTRL_HEADER BIT(11) ++#define AR7240_PORT_CTRL_MAC_LOOP BIT(12) ++#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13) ++#define AR7240_PORT_CTRL_LEARN BIT(14) ++#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15) ++#define AR7240_PORT_CTRL_MIRROR_TX BIT(16) ++#define AR7240_PORT_CTRL_MIRROR_RX BIT(17) ++ ++#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08) ++ ++#define AR7240_PORT_VLAN_DEFAULT_ID_S 0 ++#define AR7240_PORT_VLAN_DEST_PORTS_S 16 ++#define AR7240_PORT_VLAN_MODE_S 30 ++#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0 ++#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1 ++#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2 ++#define AR7240_PORT_VLAN_MODE_SECURE 3 ++ ++ ++#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100) ++ ++#define AR7240_STATS_RXBROAD 0x00 ++#define AR7240_STATS_RXPAUSE 0x04 ++#define AR7240_STATS_RXMULTI 0x08 ++#define AR7240_STATS_RXFCSERR 0x0c ++#define AR7240_STATS_RXALIGNERR 0x10 ++#define AR7240_STATS_RXRUNT 0x14 ++#define AR7240_STATS_RXFRAGMENT 0x18 ++#define AR7240_STATS_RX64BYTE 0x1c ++#define AR7240_STATS_RX128BYTE 0x20 ++#define AR7240_STATS_RX256BYTE 0x24 ++#define AR7240_STATS_RX512BYTE 0x28 ++#define AR7240_STATS_RX1024BYTE 0x2c ++#define AR7240_STATS_RX1518BYTE 0x30 ++#define AR7240_STATS_RXMAXBYTE 0x34 ++#define AR7240_STATS_RXTOOLONG 0x38 ++#define AR7240_STATS_RXGOODBYTE 0x3c ++#define AR7240_STATS_RXBADBYTE 0x44 ++#define AR7240_STATS_RXOVERFLOW 0x4c ++#define AR7240_STATS_FILTERED 0x50 ++#define AR7240_STATS_TXBROAD 0x54 ++#define AR7240_STATS_TXPAUSE 0x58 ++#define AR7240_STATS_TXMULTI 0x5c ++#define AR7240_STATS_TXUNDERRUN 0x60 ++#define AR7240_STATS_TX64BYTE 0x64 ++#define AR7240_STATS_TX128BYTE 0x68 ++#define AR7240_STATS_TX256BYTE 0x6c ++#define AR7240_STATS_TX512BYTE 0x70 ++#define AR7240_STATS_TX1024BYTE 0x74 ++#define AR7240_STATS_TX1518BYTE 0x78 ++#define AR7240_STATS_TXMAXBYTE 0x7c ++#define AR7240_STATS_TXOVERSIZE 0x80 ++#define AR7240_STATS_TXBYTE 0x84 ++#define AR7240_STATS_TXCOLLISION 0x8c ++#define AR7240_STATS_TXABORTCOL 0x90 ++#define AR7240_STATS_TXMULTICOL 0x94 ++#define AR7240_STATS_TXSINGLECOL 0x98 ++#define AR7240_STATS_TXEXCDEFER 0x9c ++#define AR7240_STATS_TXDEFER 0xa0 ++#define AR7240_STATS_TXLATECOL 0xa4 ++ ++#define AR7240_PORT_CPU 0 ++#define AR7240_NUM_PORTS 6 ++#define AR7240_NUM_PHYS 5 ++ ++#define AR7240_PHY_ID1 0x004d ++#define AR7240_PHY_ID2 0xd041 ++ ++#define AR934X_PHY_ID1 0x004d ++#define AR934X_PHY_ID2 0xd042 ++ ++#define AR7240_MAX_VLANS 16 ++ ++#define AR934X_REG_OPER_MODE0 0x04 ++#define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6) ++#define AR934X_OPER_MODE0_PHY_MII_EN BIT(10) ++ ++#define AR934X_REG_OPER_MODE1 0x08 ++#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28) ++ ++#define AR934X_REG_FLOOD_MASK 0x2c ++#define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p)) ++#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p)) ++ ++#define AR934X_REG_QM_CTRL 0x3c ++#define AR934X_QM_CTRL_ARP_EN BIT(15) ++ ++#define AR934X_REG_AT_CTRL 0x5c ++#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15) ++#define AR934X_AT_CTRL_AGE_EN BIT(17) ++#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18) ++ ++#define AR934X_MIB_ENABLE BIT(30) ++ ++#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) ++ ++#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08) ++#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0 ++#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12) ++#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13) ++#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14) ++#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15) ++#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16 ++#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28) ++#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29 ++ ++#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c) ++#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16 ++#define AR934X_PORT_VLAN2_8021Q_MODE_S 30 ++#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0 ++#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1 ++#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2 ++#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3 ++ ++#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev) ++ ++struct ar7240sw_port_stat { ++ unsigned long rx_broadcast; ++ unsigned long rx_pause; ++ unsigned long rx_multicast; ++ unsigned long rx_fcs_error; ++ unsigned long rx_align_error; ++ unsigned long rx_runt; ++ unsigned long rx_fragments; ++ unsigned long rx_64byte; ++ unsigned long rx_128byte; ++ unsigned long rx_256byte; ++ unsigned long rx_512byte; ++ unsigned long rx_1024byte; ++ unsigned long rx_1518byte; ++ unsigned long rx_maxbyte; ++ unsigned long rx_toolong; ++ unsigned long rx_good_byte; ++ unsigned long rx_bad_byte; ++ unsigned long rx_overflow; ++ unsigned long filtered; ++ ++ unsigned long tx_broadcast; ++ unsigned long tx_pause; ++ unsigned long tx_multicast; ++ unsigned long tx_underrun; ++ unsigned long tx_64byte; ++ unsigned long tx_128byte; ++ unsigned long tx_256byte; ++ unsigned long tx_512byte; ++ unsigned long tx_1024byte; ++ unsigned long tx_1518byte; ++ unsigned long tx_maxbyte; ++ unsigned long tx_oversize; ++ unsigned long tx_byte; ++ unsigned long tx_collision; ++ unsigned long tx_abortcol; ++ unsigned long tx_multicol; ++ unsigned long tx_singlecol; ++ unsigned long tx_excdefer; ++ unsigned long tx_defer; ++ unsigned long tx_xlatecol; ++}; ++ ++struct ar7240sw { ++ struct mii_bus *mii_bus; ++ struct mii_bus *switch_mii_bus; ++ struct device_node *of_node; ++ struct device_node *mdio_node; ++ struct switch_dev swdev; ++ int num_ports; ++ u8 ver; ++ bool vlan; ++ u16 vlan_id[AR7240_MAX_VLANS]; ++ u8 vlan_table[AR7240_MAX_VLANS]; ++ u8 vlan_tagged; ++ u16 pvid[AR7240_NUM_PORTS]; ++ char buf[80]; ++ ++ rwlock_t stats_lock; ++ struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS]; ++}; ++ ++struct ar7240sw_hw_stat { ++ char string[ETH_GSTRING_LEN]; ++ int sizeof_stat; ++ int reg; ++}; ++ ++static DEFINE_MUTEX(reg_mutex); ++ ++static inline int sw_is_ar7240(struct ar7240sw *as) ++{ ++ return as->ver == AR7240_MASK_CTRL_VERSION_AR7240; ++} ++ ++static inline int sw_is_ar934x(struct ar7240sw *as) ++{ ++ return as->ver == AR7240_MASK_CTRL_VERSION_AR934X; ++} ++ ++static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port) ++{ ++ return BIT(port); ++} ++ ++static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as) ++{ ++ return BIT(as->swdev.ports) - 1; ++} ++ ++static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port) ++{ ++ return ar7240sw_port_mask_all(as) & ~BIT(port); ++} ++ ++static inline u16 mk_phy_addr(u32 reg) ++{ ++ return 0x17 & ((reg >> 4) | 0x10); ++} ++ ++static inline u16 mk_phy_reg(u32 reg) ++{ ++ return (reg << 1) & 0x1e; ++} ++ ++static inline u16 mk_high_addr(u32 reg) ++{ ++ return (reg >> 7) & 0x1ff; ++} ++ ++static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg) ++{ ++ unsigned long flags; ++ u16 phy_addr; ++ u16 phy_reg; ++ u32 hi, lo; ++ ++ reg = (reg & 0xfffffffc) >> 2; ++ phy_addr = mk_phy_addr(reg); ++ phy_reg = mk_phy_reg(reg); ++ ++ local_irq_save(flags); ++ mutex_lock(&mii->mdio_lock); ++ mii->write(mii, 0x1f, 0x10, mk_high_addr(reg)); ++ lo = (u32) mii->read(mii, phy_addr, phy_reg); ++ hi = (u32) mii->read(mii, phy_addr, phy_reg + 1); ++ mutex_unlock(&mii->mdio_lock); ++ local_irq_restore(flags); ++ ++ return (hi << 16) | lo; ++} ++ ++static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val) ++{ ++ unsigned long flags; ++ u16 phy_addr; ++ u16 phy_reg; ++ ++ reg = (reg & 0xfffffffc) >> 2; ++ phy_addr = mk_phy_addr(reg); ++ phy_reg = mk_phy_reg(reg); ++ ++ local_irq_save(flags); ++ mutex_lock(&mii->mdio_lock); ++ mii->write(mii, 0x1f, 0x10, mk_high_addr(reg)); ++ mii->write(mii, phy_addr, phy_reg + 1, (val >> 16)); ++ mii->write(mii, phy_addr, phy_reg, (val & 0xffff)); ++ mutex_unlock(&mii->mdio_lock); ++ local_irq_restore(flags); ++} ++ ++static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr) ++{ ++ u32 ret; ++ ++ mutex_lock(®_mutex); ++ ret = __ar7240sw_reg_read(mii, reg_addr); ++ mutex_unlock(®_mutex); ++ ++ return ret; ++} ++ ++static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val) ++{ ++ mutex_lock(®_mutex); ++ __ar7240sw_reg_write(mii, reg_addr, reg_val); ++ mutex_unlock(®_mutex); ++} ++ ++static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val) ++{ ++ u32 t; ++ ++ mutex_lock(®_mutex); ++ t = __ar7240sw_reg_read(mii, reg); ++ t &= ~mask; ++ t |= val; ++ __ar7240sw_reg_write(mii, reg, t); ++ mutex_unlock(®_mutex); ++ ++ return t; ++} ++ ++static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val) ++{ ++ u32 t; ++ ++ mutex_lock(®_mutex); ++ t = __ar7240sw_reg_read(mii, reg); ++ t |= val; ++ __ar7240sw_reg_write(mii, reg, t); ++ mutex_unlock(®_mutex); ++} ++ ++static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val, ++ unsigned timeout) ++{ ++ int i; ++ ++ for (i = 0; i < timeout; i++) { ++ u32 t; ++ ++ t = __ar7240sw_reg_read(mii, reg); ++ if ((t & mask) == val) ++ return 0; ++ ++ usleep_range(1000, 2000); ++ } ++ ++ return -ETIMEDOUT; ++} ++ ++static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val, ++ unsigned timeout) ++{ ++ int ret; ++ ++ mutex_lock(®_mutex); ++ ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout); ++ mutex_unlock(®_mutex); ++ return ret; ++} ++ ++int ar7240sw_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr) ++{ ++ u32 t, val = 0xffff; ++ int err; ++ struct ar7240sw *as = bus->priv; ++ struct mii_bus *mii = as->mii_bus; ++ ++ if (phy_addr >= AR7240_NUM_PHYS) ++ return 0xffff; ++ ++ mutex_lock(®_mutex); ++ t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | ++ (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | ++ AR7240_MDIO_CTRL_MASTER_EN | ++ AR7240_MDIO_CTRL_BUSY | ++ AR7240_MDIO_CTRL_CMD_READ; ++ ++ __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t); ++ err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL, ++ AR7240_MDIO_CTRL_BUSY, 0, 5); ++ if (!err) ++ val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL); ++ mutex_unlock(®_mutex); ++ ++ return val & AR7240_MDIO_CTRL_DATA_M; ++} ++ ++int ar7240sw_phy_write(struct mii_bus *bus, int phy_addr, int reg_addr, ++ u16 reg_val) ++{ ++ u32 t; ++ int ret; ++ struct ar7240sw *as = bus->priv; ++ struct mii_bus *mii = as->mii_bus; ++ ++ if (phy_addr >= AR7240_NUM_PHYS) ++ return -EINVAL; ++ ++ mutex_lock(®_mutex); ++ t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | ++ (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | ++ AR7240_MDIO_CTRL_MASTER_EN | ++ AR7240_MDIO_CTRL_BUSY | ++ AR7240_MDIO_CTRL_CMD_WRITE | ++ reg_val; ++ ++ __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t); ++ ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL, ++ AR7240_MDIO_CTRL_BUSY, 0, 5); ++ mutex_unlock(®_mutex); ++ ++ return ret; ++} ++ ++static int ar7240sw_capture_stats(struct ar7240sw *as) ++{ ++ struct mii_bus *mii = as->mii_bus; ++ int port; ++ int ret; ++ ++ write_lock(&as->stats_lock); ++ ++ /* Capture the hardware statistics for all ports */ ++ ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0, ++ (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S), ++ (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S)); ++ ++ /* Wait for the capturing to complete. */ ++ ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0, ++ AR7240_MIB_BUSY, 0, 10); ++ ++ if (ret) ++ goto unlock; ++ ++ for (port = 0; port < AR7240_NUM_PORTS; port++) { ++ unsigned int base; ++ struct ar7240sw_port_stat *stats; ++ ++ base = AR7240_REG_STATS_BASE(port); ++ stats = &as->port_stats[port]; ++ ++#define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r) ++ ++ stats->rx_good_byte += READ_STAT(RXGOODBYTE); ++ stats->tx_byte += READ_STAT(TXBYTE); ++ ++#undef READ_STAT ++ } ++ ++ ret = 0; ++ ++unlock: ++ write_unlock(&as->stats_lock); ++ return ret; ++} ++ ++static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port) ++{ ++ ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port), ++ AR7240_PORT_CTRL_STATE_DISABLED); ++} ++ ++static void ar7240sw_setup(struct ar7240sw *as) ++{ ++ struct mii_bus *mii = as->mii_bus; ++ ++ /* Enable CPU port, and disable mirror port */ ++ ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT, ++ AR7240_CPU_PORT_EN | ++ (15 << AR7240_MIRROR_PORT_S)); ++ ++ /* Setup TAG priority mapping */ ++ ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50); ++ ++ if (sw_is_ar934x(as)) { ++ /* Enable aging, MAC replacing */ ++ ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL, ++ 0x2b /* 5 min age time */ | ++ AR934X_AT_CTRL_AGE_EN | ++ AR934X_AT_CTRL_LEARN_CHANGE); ++ /* Enable ARP frame acknowledge */ ++ ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL, ++ AR934X_QM_CTRL_ARP_EN); ++ /* Enable Broadcast/Multicast frames transmitted to the CPU */ ++ ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK, ++ AR934X_FLOOD_MASK_BC_DP(0) | ++ AR934X_FLOOD_MASK_MC_DP(0)); ++ ++ /* setup MTU */ ++ ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, ++ AR9340_GLOBAL_CTRL_MTU_M, ++ AR9340_GLOBAL_CTRL_MTU_M); ++ ++ /* Enable MIB counters */ ++ ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0, ++ AR934X_MIB_ENABLE); ++ ++ } else { ++ /* Enable ARP frame acknowledge, aging, MAC replacing */ ++ ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL, ++ AR7240_AT_CTRL_RESERVED | ++ 0x2b /* 5 min age time */ | ++ AR7240_AT_CTRL_AGE_EN | ++ AR7240_AT_CTRL_ARP_EN | ++ AR7240_AT_CTRL_LEARN_CHANGE); ++ /* Enable Broadcast frames transmitted to the CPU */ ++ ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK, ++ AR7240_FLOOD_MASK_BROAD_TO_CPU); ++ ++ /* setup MTU */ ++ ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, ++ AR7240_GLOBAL_CTRL_MTU_M, ++ AR7240_GLOBAL_CTRL_MTU_M); ++ } ++ ++ /* setup Service TAG */ ++ ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0); ++} ++ ++/* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */ ++static int ++ar7240sw_phy_poll_reset(struct mii_bus *bus) ++{ ++ const unsigned int sleep_msecs = 20; ++ int ret, elapsed, i; ++ ++ for (elapsed = sleep_msecs; elapsed <= 600; ++ elapsed += sleep_msecs) { ++ msleep(sleep_msecs); ++ for (i = 0; i < AR7240_NUM_PHYS; i++) { ++ ret = ar7240sw_phy_read(bus, i, MII_BMCR); ++ if (ret < 0) ++ return ret; ++ if (ret & BMCR_RESET) ++ break; ++ if (i == AR7240_NUM_PHYS - 1) { ++ usleep_range(1000, 2000); ++ return 0; ++ } ++ } ++ } ++ return -ETIMEDOUT; ++} ++ ++static int ar7240sw_reset(struct ar7240sw *as) ++{ ++ struct mii_bus *mii = as->mii_bus; ++ struct mii_bus *swmii = as->switch_mii_bus; ++ int ret; ++ int i; ++ ++ /* Set all ports to disabled state. */ ++ for (i = 0; i < AR7240_NUM_PORTS; i++) ++ ar7240sw_disable_port(as, i); ++ ++ /* Wait for transmit queues to drain. */ ++ usleep_range(2000, 3000); ++ ++ /* Reset the switch. */ ++ ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL, ++ AR7240_MASK_CTRL_SOFT_RESET); ++ ++ ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL, ++ AR7240_MASK_CTRL_SOFT_RESET, 0, 1000); ++ ++ /* setup PHYs */ ++ for (i = 0; i < AR7240_NUM_PHYS; i++) { ++ ar7240sw_phy_write(swmii, i, MII_ADVERTISE, ++ ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ++ ADVERTISE_PAUSE_ASYM); ++ ar7240sw_phy_write(swmii, i, MII_BMCR, ++ BMCR_RESET | BMCR_ANENABLE); ++ } ++ ret = ar7240sw_phy_poll_reset(swmii); ++ if (ret) ++ return ret; ++ ++ ar7240sw_setup(as); ++ return ret; ++} ++ ++static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask) ++{ ++ struct mii_bus *mii = as->mii_bus; ++ u32 ctrl; ++ u32 vid, mode; ++ ++ ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN | ++ AR7240_PORT_CTRL_SINGLE_VLAN; ++ ++ if (port == AR7240_PORT_CPU) { ++ ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port), ++ AR7240_PORT_STATUS_SPEED_1000 | ++ AR7240_PORT_STATUS_TXFLOW | ++ AR7240_PORT_STATUS_RXFLOW | ++ AR7240_PORT_STATUS_TXMAC | ++ AR7240_PORT_STATUS_RXMAC | ++ AR7240_PORT_STATUS_DUPLEX); ++ } else { ++ ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port), ++ AR7240_PORT_STATUS_LINK_AUTO); ++ } ++ ++ /* Set the default VID for this port */ ++ if (as->vlan) { ++ vid = as->vlan_id[as->pvid[port]]; ++ mode = AR7240_PORT_VLAN_MODE_SECURE; ++ } else { ++ vid = port; ++ mode = AR7240_PORT_VLAN_MODE_PORT_ONLY; ++ } ++ ++ if (as->vlan) { ++ if (as->vlan_tagged & BIT(port)) ++ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD << ++ AR7240_PORT_CTRL_VLAN_MODE_S; ++ else ++ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP << ++ AR7240_PORT_CTRL_VLAN_MODE_S; ++ } else { ++ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP << ++ AR7240_PORT_CTRL_VLAN_MODE_S; ++ } ++ ++ if (!portmask) { ++ if (port == AR7240_PORT_CPU) ++ portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU); ++ else ++ portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU); ++ } ++ ++ /* preserve mirror rx&tx flags */ ++ ctrl |= ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port)) & ++ (AR7240_PORT_CTRL_MIRROR_RX | AR7240_PORT_CTRL_MIRROR_TX); ++ ++ /* allow the port to talk to all other ports, but exclude its ++ * own ID to prevent frames from being reflected back to the ++ * port that they came from */ ++ portmask &= ar7240sw_port_mask_but(as, port); ++ ++ ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl); ++ if (sw_is_ar934x(as)) { ++ u32 vlan1, vlan2; ++ ++ vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S); ++ vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) | ++ (mode << AR934X_PORT_VLAN2_8021Q_MODE_S); ++ ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1); ++ ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2); ++ } else { ++ u32 vlan; ++ ++ vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) | ++ (portmask << AR7240_PORT_VLAN_DEST_PORTS_S); ++ ++ ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan); ++ } ++} ++ ++static int ++ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ as->vlan_id[val->port_vlan] = val->value.i; ++ return 0; ++} ++ ++static int ++ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ val->value.i = as->vlan_id[val->port_vlan]; ++ return 0; ++} ++ ++static int ++ar7240_set_pvid(struct switch_dev *dev, int port, int vlan) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ ++ /* make sure no invalid PVIDs get set */ ++ ++ if (vlan >= dev->vlans) ++ return -EINVAL; ++ ++ as->pvid[port] = vlan; ++ return 0; ++} ++ ++static int ++ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ *vlan = as->pvid[port]; ++ return 0; ++} ++ ++static int ++ar7240_get_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ u8 ports = as->vlan_table[val->port_vlan]; ++ int i; ++ ++ val->len = 0; ++ for (i = 0; i < as->swdev.ports; i++) { ++ struct switch_port *p; ++ ++ if (!(ports & (1 << i))) ++ continue; ++ ++ p = &val->value.ports[val->len++]; ++ p->id = i; ++ if (as->vlan_tagged & (1 << i)) ++ p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); ++ else ++ p->flags = 0; ++ } ++ return 0; ++} ++ ++static int ++ar7240_set_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ u8 *vt = &as->vlan_table[val->port_vlan]; ++ int i, j; ++ ++ *vt = 0; ++ for (i = 0; i < val->len; i++) { ++ struct switch_port *p = &val->value.ports[i]; ++ ++ if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) ++ as->vlan_tagged |= (1 << p->id); ++ else { ++ as->vlan_tagged &= ~(1 << p->id); ++ as->pvid[p->id] = val->port_vlan; ++ ++ /* make sure that an untagged port does not ++ * appear in other vlans */ ++ for (j = 0; j < AR7240_MAX_VLANS; j++) { ++ if (j == val->port_vlan) ++ continue; ++ as->vlan_table[j] &= ~(1 << p->id); ++ } ++ } ++ ++ *vt |= 1 << p->id; ++ } ++ return 0; ++} ++ ++static int ++ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ as->vlan = !!val->value.i; ++ return 0; ++} ++ ++static int ++ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ val->value.i = as->vlan; ++ return 0; ++} ++ ++static void ++ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val) ++{ ++ struct mii_bus *mii = as->mii_bus; ++ ++ if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5)) ++ return; ++ ++ if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) { ++ val &= AR7240_VTUDATA_MEMBER; ++ val |= AR7240_VTUDATA_VALID; ++ ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val); ++ } ++ op |= AR7240_VTU_ACTIVE; ++ ar7240sw_reg_write(mii, AR7240_REG_VTU, op); ++} ++ ++static int ++ar7240_hw_apply(struct switch_dev *dev) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ u8 portmask[AR7240_NUM_PORTS]; ++ int i, j; ++ ++ /* flush all vlan translation unit entries */ ++ ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0); ++ ++ memset(portmask, 0, sizeof(portmask)); ++ if (as->vlan) { ++ /* calculate the port destination masks and load vlans ++ * into the vlan translation unit */ ++ for (j = 0; j < AR7240_MAX_VLANS; j++) { ++ u8 vp = as->vlan_table[j]; ++ ++ if (!vp) ++ continue; ++ ++ for (i = 0; i < as->swdev.ports; i++) { ++ u8 mask = (1 << i); ++ if (vp & mask) ++ portmask[i] |= vp & ~mask; ++ } ++ ++ ar7240_vtu_op(as, ++ AR7240_VTU_OP_LOAD | ++ (as->vlan_id[j] << AR7240_VTU_VID_S), ++ as->vlan_table[j]); ++ } ++ } else { ++ /* vlan disabled: ++ * isolate all ports, but connect them to the cpu port */ ++ for (i = 0; i < as->swdev.ports; i++) { ++ if (i == AR7240_PORT_CPU) ++ continue; ++ ++ portmask[i] = 1 << AR7240_PORT_CPU; ++ portmask[AR7240_PORT_CPU] |= (1 << i); ++ } ++ } ++ ++ /* update the port destination mask registers and tag settings */ ++ for (i = 0; i < as->swdev.ports; i++) ++ ar7240sw_setup_port(as, i, portmask[i]); ++ ++ return 0; ++} ++ ++static int ++ar7240_reset_switch(struct switch_dev *dev) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ ar7240sw_reset(as); ++ ++ /* ar7240 reapply hardware settings*/ ++ if (sw_is_ar7240(as)) ++ ar7240_hw_apply(dev); ++ ++ return 0; ++} ++ ++static int ++ar7240_get_port_link(struct switch_dev *dev, int port, ++ struct switch_port_link *link) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ struct mii_bus *mii = as->mii_bus; ++ u32 status; ++ ++ if (port >= AR7240_NUM_PORTS) ++ return -EINVAL; ++ ++ status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port)); ++ link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO); ++ if (link->aneg) { ++ link->link = !!(status & AR7240_PORT_STATUS_LINK_UP); ++ if (!link->link) ++ return 0; ++ } else { ++ link->link = true; ++ } ++ ++ link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX); ++ link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW); ++ link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW); ++ switch (status & AR7240_PORT_STATUS_SPEED_M) { ++ case AR7240_PORT_STATUS_SPEED_10: ++ link->speed = SWITCH_PORT_SPEED_10; ++ break; ++ case AR7240_PORT_STATUS_SPEED_100: ++ link->speed = SWITCH_PORT_SPEED_100; ++ break; ++ case AR7240_PORT_STATUS_SPEED_1000: ++ link->speed = SWITCH_PORT_SPEED_1000; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int ++ar7240_get_port_stats(struct switch_dev *dev, int port, ++ struct switch_port_stats *stats) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ ++ if (port >= AR7240_NUM_PORTS) ++ return -EINVAL; ++ ++ ar7240sw_capture_stats(as); ++ ++ read_lock(&as->stats_lock); ++ stats->rx_bytes = as->port_stats[port].rx_good_byte; ++ stats->tx_bytes = as->port_stats[port].tx_byte; ++ read_unlock(&as->stats_lock); ++ ++ return 0; ++} ++ ++static int ++ar7240_set_mirror_monitor_port(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ struct mii_bus *mii = as->mii_bus; ++ ++ int port = val->value.i; ++ ++ if (port > 15) ++ return -EINVAL; ++ ++ ar7240sw_reg_rmw(mii, AR7240_REG_CPU_PORT, ++ AR7240_MIRROR_PORT_M << AR7240_MIRROR_PORT_S, ++ port << AR7240_MIRROR_PORT_S); ++ ++ return 0; ++} ++ ++static int ++ar7240_get_mirror_monitor_port(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ struct mii_bus *mii = as->mii_bus; ++ ++ u32 ret; ++ ++ ret = ar7240sw_reg_read(mii, AR7240_REG_CPU_PORT); ++ val->value.i = (ret >> AR7240_MIRROR_PORT_S) & AR7240_MIRROR_PORT_M; ++ ++ return 0; ++} ++ ++static int ++ar7240_set_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ struct mii_bus *mii = as->mii_bus; ++ ++ int port = val->port_vlan; ++ ++ if (port >= dev->ports) ++ return -EINVAL; ++ ++ if (val && val->value.i == 1) ++ ar7240sw_reg_set(mii, AR7240_REG_PORT_CTRL(port), ++ AR7240_PORT_CTRL_MIRROR_RX); ++ else ++ ar7240sw_reg_rmw(mii, AR7240_REG_PORT_CTRL(port), ++ AR7240_PORT_CTRL_MIRROR_RX, 0); ++ ++ return 0; ++} ++ ++static int ++ar7240_get_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ struct mii_bus *mii = as->mii_bus; ++ ++ u32 ctrl; ++ ++ int port = val->port_vlan; ++ ++ if (port >= dev->ports) ++ return -EINVAL; ++ ++ ctrl = ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port)); ++ ++ if ((ctrl & AR7240_PORT_CTRL_MIRROR_RX) == AR7240_PORT_CTRL_MIRROR_RX) ++ val->value.i = 1; ++ else ++ val->value.i = 0; ++ ++ return 0; ++} ++ ++static int ++ar7240_set_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ struct mii_bus *mii = as->mii_bus; ++ ++ int port = val->port_vlan; ++ ++ if (port >= dev->ports) ++ return -EINVAL; ++ ++ if (val && val->value.i == 1) ++ ar7240sw_reg_set(mii, AR7240_REG_PORT_CTRL(port), ++ AR7240_PORT_CTRL_MIRROR_TX); ++ else ++ ar7240sw_reg_rmw(mii, AR7240_REG_PORT_CTRL(port), ++ AR7240_PORT_CTRL_MIRROR_TX, 0); ++ ++ return 0; ++} ++ ++static int ++ar7240_get_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ struct mii_bus *mii = as->mii_bus; ++ ++ u32 ctrl; ++ ++ int port = val->port_vlan; ++ ++ if (port >= dev->ports) ++ return -EINVAL; ++ ++ ctrl = ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port)); ++ ++ if ((ctrl & AR7240_PORT_CTRL_MIRROR_TX) == AR7240_PORT_CTRL_MIRROR_TX) ++ val->value.i = 1; ++ else ++ val->value.i = 0; ++ ++ return 0; ++} ++ ++static struct switch_attr ar7240_globals[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "enable_vlan", ++ .description = "Enable VLAN mode", ++ .set = ar7240_set_vlan, ++ .get = ar7240_get_vlan, ++ .max = 1 ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "mirror_monitor_port", ++ .description = "Mirror monitor port", ++ .set = ar7240_set_mirror_monitor_port, ++ .get = ar7240_get_mirror_monitor_port, ++ .max = 15 ++ }, ++}; ++ ++static struct switch_attr ar7240_port[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "enable_mirror_rx", ++ .description = "Enable mirroring of RX packets", ++ .set = ar7240_set_mirror_rx, ++ .get = ar7240_get_mirror_rx, ++ .max = 1 ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "enable_mirror_tx", ++ .description = "Enable mirroring of TX packets", ++ .set = ar7240_set_mirror_tx, ++ .get = ar7240_get_mirror_tx, ++ .max = 1 ++ }, ++}; ++ ++static struct switch_attr ar7240_vlan[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "vid", ++ .description = "VLAN ID", ++ .set = ar7240_set_vid, ++ .get = ar7240_get_vid, ++ .max = 4094, ++ }, ++}; ++ ++static const struct switch_dev_ops ar7240_ops = { ++ .attr_global = { ++ .attr = ar7240_globals, ++ .n_attr = ARRAY_SIZE(ar7240_globals), ++ }, ++ .attr_port = { ++ .attr = ar7240_port, ++ .n_attr = ARRAY_SIZE(ar7240_port), ++ }, ++ .attr_vlan = { ++ .attr = ar7240_vlan, ++ .n_attr = ARRAY_SIZE(ar7240_vlan), ++ }, ++ .get_port_pvid = ar7240_get_pvid, ++ .set_port_pvid = ar7240_set_pvid, ++ .get_vlan_ports = ar7240_get_ports, ++ .set_vlan_ports = ar7240_set_ports, ++ .apply_config = ar7240_hw_apply, ++ .reset_switch = ar7240_reset_switch, ++ .get_port_link = ar7240_get_port_link, ++ .get_port_stats = ar7240_get_port_stats, ++}; ++ ++static int ++ag71xx_ar7240_probe(struct mdio_device *mdiodev) ++{ ++ struct mii_bus *mii = mdiodev->bus; ++ struct ar7240sw *as; ++ struct switch_dev *swdev; ++ struct reset_control *switch_reset; ++ u32 ctrl; ++ int phy_if_mode, err, i; ++ ++ as = devm_kzalloc(&mdiodev->dev, sizeof(*as), GFP_KERNEL); ++ if (!as) ++ return -ENOMEM; ++ ++ as->mii_bus = mii; ++ as->of_node = mdiodev->dev.of_node; ++ as->mdio_node = of_get_child_by_name(as->of_node, "mdio-bus"); ++ ++ swdev = &as->swdev; ++ ++ switch_reset = devm_reset_control_get_optional(&mdiodev->dev, "switch"); ++ if (switch_reset) { ++ reset_control_assert(switch_reset); ++ msleep(50); ++ reset_control_deassert(switch_reset); ++ msleep(200); ++ } ++ ++ ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL); ++ as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & ++ AR7240_MASK_CTRL_VERSION_M; ++ ++ if (sw_is_ar7240(as)) { ++ swdev->name = "AR7240/AR9330 built-in switch"; ++ swdev->ports = AR7240_NUM_PORTS - 1; ++ } else if (sw_is_ar934x(as)) { ++ swdev->name = "AR934X built-in switch"; ++ phy_if_mode = of_get_phy_mode(as->of_node); ++ ++ if (phy_if_mode == PHY_INTERFACE_MODE_GMII) { ++ ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0, ++ AR934X_OPER_MODE0_MAC_GMII_EN); ++ } else if (phy_if_mode == PHY_INTERFACE_MODE_MII) { ++ ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0, ++ AR934X_OPER_MODE0_PHY_MII_EN); ++ } else { ++ pr_err("%s: invalid PHY interface mode\n", ++ dev_name(&mdiodev->dev)); ++ return -EINVAL; ++ } ++ ++ if (of_property_read_bool(as->of_node, "phy4-mii-enable")) { ++ ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1, ++ AR934X_REG_OPER_MODE1_PHY4_MII_EN); ++ swdev->ports = AR7240_NUM_PORTS - 1; ++ } else { ++ swdev->ports = AR7240_NUM_PORTS; ++ } ++ } else { ++ pr_err("%s: unsupported chip, ctrl=%08x\n", ++ dev_name(&mdiodev->dev), ctrl); ++ return -EINVAL; ++ } ++ ++ swdev->cpu_port = AR7240_PORT_CPU; ++ swdev->vlans = AR7240_MAX_VLANS; ++ swdev->ops = &ar7240_ops; ++ swdev->alias = dev_name(&mdiodev->dev); ++ ++ if ((err = register_switch(&as->swdev, NULL)) < 0) ++ return err; ++ ++ pr_info("%s: Found an %s\n", dev_name(&mdiodev->dev), swdev->name); ++ ++ as->switch_mii_bus = devm_mdiobus_alloc(&mdiodev->dev); ++ as->switch_mii_bus->name = "ar7240sw_mdio"; ++ as->switch_mii_bus->read = ar7240sw_phy_read; ++ as->switch_mii_bus->write = ar7240sw_phy_write; ++ as->switch_mii_bus->priv = as; ++ as->switch_mii_bus->parent = &mdiodev->dev; ++ snprintf(as->switch_mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&mdiodev->dev)); ++ ++ if(as->mdio_node) { ++ err = of_mdiobus_register(as->switch_mii_bus, as->mdio_node); ++ if (err) ++ return err; ++ } ++ ++ /* initialize defaults */ ++ for (i = 0; i < AR7240_MAX_VLANS; i++) ++ as->vlan_id[i] = i; ++ ++ as->vlan_table[0] = ar7240sw_port_mask_all(as); ++ ar7240sw_reset(as); ++ ar7240_hw_apply(&as->swdev); ++ rwlock_init(&as->stats_lock); ++ dev_set_drvdata(&mdiodev->dev, as); ++ return 0; ++} ++ ++static void ++ag71xx_ar7240_remove(struct mdio_device *mdiodev) ++{ ++ struct ar7240sw *as = dev_get_drvdata(&mdiodev->dev); ++ if(as->mdio_node) ++ mdiobus_unregister(as->switch_mii_bus); ++ unregister_switch(&as->swdev); ++} ++ ++static const struct of_device_id ag71xx_sw_of_match[] = { ++ { .compatible = "qca,ar8216-builtin" }, ++ { .compatible = "qca,ar8229-builtin" }, ++ { /* sentinel */ }, ++}; ++ ++static struct mdio_driver ag71xx_sw_driver = { ++ .probe = ag71xx_ar7240_probe, ++ .remove = ag71xx_ar7240_remove, ++ .mdiodrv.driver = { ++ .name = "ag71xx-switch", ++ .of_match_table = ag71xx_sw_of_match, ++ }, ++}; ++ ++mdio_module_driver(ag71xx_sw_driver); ++MODULE_LICENSE("GPL"); +diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c +index 84b0f9e4ac..79b3e64b16 100644 +--- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c ++++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c +@@ -1516,6 +1516,7 @@ static int ag71xx_probe(struct platform_device *pdev) + struct resource *res; + struct ag71xx *ag; + const void *mac_addr; ++ const char *ifname = NULL; + u32 max_frame_len; + int tx_size, err; + +@@ -1730,6 +1731,9 @@ static int ag71xx_probe(struct platform_device *pdev) + + platform_set_drvdata(pdev, dev); + ++ if(!of_property_read_string(np, "ifname",&ifname)) ++ memcpy(dev->name,ifname,strlen(ifname)+1); ++ + err = register_netdev(dev); + if (err) { + dev_err(&pdev->dev, "unable to register net device\n"); +diff --git a/target/linux/ath79/generic/base-files/etc/board.d/01_leds b/target/linux/ath79/generic/base-files/etc/board.d/01_leds +index 7c5eeb1112..985adfc6a7 100755 +--- a/target/linux/ath79/generic/base-files/etc/board.d/01_leds ++++ b/target/linux/ath79/generic/base-files/etc/board.d/01_leds +@@ -204,7 +204,6 @@ etactica,eg200) + ucidef_set_led_netdev "lan" "LAN" "red:eth0" "eth0" + ucidef_set_led_oneshot "modbus" "Modbus" "red:modbus" "100" "33" + ;; +-glinet,gl-mifi|\ + qxwlan,e600g-v2-8m|\ + qxwlan,e600g-v2-16m|\ + qxwlan,e600gac-v2-8m|\ +diff --git a/target/linux/ath79/generic/base-files/etc/uci-defaults/04_led_migration b/target/linux/ath79/generic/base-files/etc/uci-defaults/04_led_migration +index e9b0fade38..fba1fdcd59 100644 +--- a/target/linux/ath79/generic/base-files/etc/uci-defaults/04_led_migration ++++ b/target/linux/ath79/generic/base-files/etc/uci-defaults/04_led_migration +@@ -14,9 +14,6 @@ dlink,dap-1330-a1) + engenius,epg5000) + migrate_leds ":wlan-2g=:wlan2g" ":wlan-5g=:wlan5g" + ;; +-glinet,gl-mifi) +- migrate_leds ":net=:3g4g" +- ;; + meraki,mr12) + migrate_leds ":wifi=:link" ":wan=:lan" + ;; +diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk +index 5ba64b9803..05ed698401 100644 +--- a/target/linux/ath79/image/generic.mk ++++ b/target/linux/ath79/image/generic.mk +@@ -1198,16 +1198,6 @@ define Device/glinet_gl-ar750 + endef + TARGET_DEVICES += glinet_gl-ar750 + +-define Device/glinet_gl-mifi +- SOC := ar9331 +- DEVICE_VENDOR := GL.iNET +- DEVICE_MODEL := GL-MiFi +- DEVICE_PACKAGES := kmod-usb-chipidea2 +- IMAGE_SIZE := 16000k +- SUPPORTED_DEVICES += gl-mifi +-endef +-TARGET_DEVICES += glinet_gl-mifi +- + define Device/glinet_gl-usb150 + SOC := ar9331 + DEVICE_VENDOR := GL.iNET +diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk +index cfc07f14a3..0c6dd699f5 100644 +--- a/target/linux/ath79/image/nand.mk ++++ b/target/linux/ath79/image/nand.mk +@@ -107,6 +107,16 @@ define Device/glinet_gl-ar300m-nor + endef + TARGET_DEVICES += glinet_gl-ar300m-nor + ++define Device/glinet_gl-mifi ++ SOC := ar9331 ++ DEVICE_VENDOR := GL.iNET ++ DEVICE_MODEL := GL-MiFi ++ DEVICE_PACKAGES := kmod-usb-chipidea2 ++ IMAGE_SIZE := 16000k ++ SUPPORTED_DEVICES += gl-mifi glinet,gl-mifi ++endef ++TARGET_DEVICES += glinet_gl-mifi ++ + define Device/glinet_gl-xe300-common + SOC := qca9531 + DEVICE_VENDOR := GL.iNet +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/01_leds b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +index 4a90c4673f..16545083fb 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/01_leds ++++ b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +@@ -11,6 +11,12 @@ glinet,gl-ar300m-nand|\ + glinet,gl-ar300m-nor) + ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" + ;; ++glinet,gl-mifi) ++ ucidef_set_led_wlan "wlan" "WLAN" "gl-mifi:green:wlan" "phy0tpt" ++ ucidef_set_led_netdev "wan" "WAN" "gl-mifi:green:wan" "eth0" ++ ucidef_set_led_switch "lan" "LAN" "gl-mifi:green:lan" "switch0" "0x2" ++ ucidef_set_led_netdev "3gnet" "3GNET" "gl-mifi:green:net" "3g-wan" ++ ;; + glinet,gl-xe300-iot|\ + glinet,gl-xe300-nor|\ + glinet,gl-xe300-nor-nand) +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/02_network b/target/linux/ath79/nand/base-files/etc/board.d/02_network +index 17348e001b..73e23e5eb9 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/02_network ++++ b/target/linux/ath79/nand/base-files/etc/board.d/02_network +@@ -21,6 +21,9 @@ ath79_setup_interfaces() + ucidef_add_switch "switch0" \ + "0@eth0" "2:lan:2" "3:lan:1" "1:wan" + ;; ++ glinet,gl-mifi) ++ ucidef_set_interfaces_lan_wan "eth1" "eth0" ++ ;; + glinet,gl-xe300-iot|\ + glinet,gl-xe300-nor|\ + glinet,gl-xe300-nor-nand) +-- +2.17.1 + diff --git a/patches-21.02.2/0003-add-modem-support.patch b/patches-21.02.2/0003-add-modem-support.patch new file mode 100644 index 0000000..b956d4a --- /dev/null +++ b/patches-21.02.2/0003-add-modem-support.patch @@ -0,0 +1,322 @@ +From 180dac974bb796e5e9a5b5350baa7404ff5e235d Mon Sep 17 00:00:00 2001 +From: "GL.iNet-Hongjian.Zhang" +Date: Sat, 18 Sep 2021 14:19:35 +0800 +Subject: [PATCH 3/8] add modem support + +--- + .../patches-5.4/701-add-modem-support.patch | 303 ++++++++++++++++++ + 1 file changed, 303 insertions(+) + create mode 100644 target/linux/ath79/patches-5.4/701-add-modem-support.patch + +diff --git a/target/linux/ath79/patches-5.4/701-add-modem-support.patch b/target/linux/ath79/patches-5.4/701-add-modem-support.patch +new file mode 100644 +index 0000000000..4c83520426 +--- /dev/null ++++ b/target/linux/ath79/patches-5.4/701-add-modem-support.patch +@@ -0,0 +1,303 @@ ++Index: b/drivers/net/usb/qmi_wwan.c ++=================================================================== ++--- a/drivers/net/usb/qmi_wwan.c 2021-09-18 12:18:32.582950993 +0800 +++++ b/drivers/net/usb/qmi_wwan.c 2021-09-18 12:18:32.578950684 +0800 ++@@ -507,6 +507,24 @@ static const u8 default_modem_addr[ETH_A ++ ++ static const u8 buggy_fw_addr[ETH_ALEN] = {0x00, 0xa0, 0xc6, 0x00, 0x00, 0x00}; ++ +++#if 1 //Added by Quectel +++#include +++struct sk_buff *qmi_wwan_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags) +++{ +++ if (dev->udev->descriptor.idVendor != cpu_to_le16(0x2C7C)) +++ return skb; +++ // Skip Ethernet header from message +++ if (skb_pull(skb, ETH_HLEN)) { +++ return skb; +++ } else { +++ dev_err(&dev->intf->dev, "Packet Dropped "); +++ } +++ // Filter the packet out, release it +++ dev_kfree_skb_any(skb); +++ return NULL; +++} +++#endif +++ ++ /* Make up an ethernet header if the packet doesn't have one. ++ * ++ * A firmware bug common among several devices cause them to send raw ++@@ -801,6 +819,20 @@ static int qmi_wwan_bind(struct usbnet * ++ } ++ dev->net->netdev_ops = &qmi_wwan_netdev_ops; ++ dev->net->sysfs_groups[0] = &qmi_wwan_sysfs_attr_group; +++#if 1 //Added by Quectel +++ if (dev->udev->descriptor.idVendor == cpu_to_le16(0x2C7C)) { +++ dev_info(&intf->dev, "QuectelEC25&EC21&EG91&EG95&EG06&EP06&EM06&BG96&AG35 work on RawIP mode\n"); +++ dev->net->flags |= IFF_NOARP; +++ usb_control_msg( +++ interface_to_usbdev(intf), +++ usb_sndctrlpipe(interface_to_usbdev(intf), 0), +++ 0x22, //USB_CDC_REQ_SET_CONTROL_LINE_STATE +++ 0x21, //USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE +++ 1, //active CDC DTR +++ intf->cur_altsetting->desc.bInterfaceNumber, +++ NULL, 0, 100); +++ } +++#endif ++ err: ++ return status; ++ } ++@@ -891,7 +923,10 @@ static const struct driver_info qmi_wwan ++ .bind = qmi_wwan_bind, ++ .unbind = qmi_wwan_unbind, ++ .manage_power = qmi_wwan_manage_power, ++- .rx_fixup = qmi_wwan_rx_fixup, +++ #if 1 //Added by Quectel +++ .tx_fixup = qmi_wwan_tx_fixup, +++ .rx_fixup = qmi_wwan_rx_fixup, +++ #endif ++ }; ++ ++ static const struct driver_info qmi_wwan_info_quirk_dtr = { ++@@ -938,6 +973,17 @@ static const struct driver_info qmi_wwan ++ .driver_info = (unsigned long)&qmi_wwan_info_quirk_dtr ++ ++ static const struct usb_device_id products[] = { +++#if 1 //Added by Quectel +++ { QMI_FIXED_INTF(0x05C6, 0x9003, 4) }, /* Quectel UC20 */ +++ { QMI_FIXED_INTF(0x2C7C, 0x0125, 4) }, /* Quectel EC25 */ +++ { QMI_FIXED_INTF(0x2C7C, 0x0121, 4) }, /* Quectel EC21 */ +++ { QMI_FIXED_INTF(0x05C6, 0x9215, 4) }, /* Quectel EC20 */ +++ { QMI_FIXED_INTF(0x2C7C, 0x0191, 4) }, /* Quectel EG91 */ +++ { QMI_FIXED_INTF(0x2C7C, 0x0195, 4) }, /* Quectel EG95 */ +++ { QMI_FIXED_INTF(0x2C7C, 0x0306, 4) }, /* Quectel EG06/EP06/EM06 */ +++ { QMI_FIXED_INTF(0x2C7C, 0x0296, 4) }, /* Quectel BG96 */ +++ { QMI_FIXED_INTF(0x2C7C, 0x0435, 4) }, /* Quectel AG35 */ +++#endif ++ /* 1. CDC ECM like devices match on the control interface */ ++ { /* Huawei E392, E398 and possibly others sharing both device id and more... */ ++ USB_VENDOR_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, USB_CLASS_VENDOR_SPEC, 1, 9), ++@@ -1396,7 +1442,6 @@ static const struct usb_device_id produc ++ {QMI_GOBI_DEVICE(0x05c6, 0x9225)}, /* Sony Gobi 2000 Modem device (N0279, VU730) */ ++ {QMI_GOBI_DEVICE(0x05c6, 0x9245)}, /* Samsung Gobi 2000 Modem device (VL176) */ ++ {QMI_GOBI_DEVICE(0x03f0, 0x251d)}, /* HP Gobi 2000 Modem device (VP412) */ ++- {QMI_GOBI_DEVICE(0x05c6, 0x9215)}, /* Acer Gobi 2000 Modem device (VP413) */ ++ {QMI_FIXED_INTF(0x05c6, 0x9215, 4)}, /* Quectel EC20 Mini PCIe */ ++ {QMI_GOBI_DEVICE(0x05c6, 0x9265)}, /* Asus Gobi 2000 Modem device (VR305) */ ++ {QMI_GOBI_DEVICE(0x05c6, 0x9235)}, /* Top Global Gobi 2000 Modem device (VR306) */ ++Index: b/drivers/usb/serial/option.c ++=================================================================== ++--- a/drivers/usb/serial/option.c 2021-09-18 12:18:32.582950993 +0800 +++++ b/drivers/usb/serial/option.c 2021-09-18 12:20:11.062584026 +0800 ++@@ -564,6 +564,23 @@ static void option_instat_callback(struc ++ #define WETELECOM_PRODUCT_WMD300 0x6803 ++ ++ +++#define LONGSUNG_PRODUCT_U9300C 0x9b3c +++ +++/* FORGE PRODUCT */ +++#define FORGE_VENDOR_ID 0x05c6 +++ +++#define FORGE_PRODUCT_SLM750 0xf601 +++ +++/* NODECOM PRODUCT */ +++#define NODECOM_VENDOR_ID 0x1508 +++ +++#define NODECOM_PRODUCT_NL660 0x1001 +++ +++/* NEOWAY PRODUCT */ +++#define NEOWAY_VENDOR_ID 0x2949 +++ +++#define NEOWAY_PRODUCT_N720 0x8243 +++ ++ /* Device flags */ ++ ++ /* Highest interface number which can be used with NCTRL() and RSVD() */ ++@@ -583,6 +600,29 @@ static void option_instat_callback(struc ++ ++ ++ static const struct usb_device_id option_ids[] = { +++#if 1 //Added by Quectel +++ { USB_DEVICE(0x05C6, 0x9090) }, /* Quectel UC15 */ +++ { USB_DEVICE(0x05C6, 0x9003) }, /* Quectel UC20 */ +++ { USB_DEVICE(0x2C7C, 0x0125) }, /* Quectel EC25 */ +++ { USB_DEVICE(0x2C7C, 0x0121) }, /* Quectel EC21 */ +++ { USB_DEVICE(0x05C6, 0x9215) }, /* Quectel EC20 */ +++ { USB_DEVICE(0x2C7C, 0x0191) }, /* Quectel EG91 */ +++ { USB_DEVICE(0x2C7C, 0x0195) }, /* Quectel EG95 */ +++ { USB_DEVICE(0x2C7C, 0x0306) }, /* Quectel EG06/EP06/EM06 */ +++ { USB_DEVICE(0x2C7C, 0x0700) }, /* Quectel BG95 */ +++ { USB_DEVICE(0x2C7C, 0x0296) }, /* Quectel BG96 */ +++ { USB_DEVICE(0x2C7C, 0x0435) }, /* Quectel AG35 */ +++ { USB_DEVICE(0x2C7C, 0x6026) }, /* Quectel EC200t */ +++#endif +++ { USB_DEVICE(0x19d2, 0x0536) },/* MZ386 */ +++ { USB_DEVICE(0x19d2, 0x0117) }, +++ { USB_DEVICE(0x19d2, 0x0199) }, +++ { USB_DEVICE(0x19d2, 0x1476) }, +++ { USB_DEVICE(LONGCHEER_VENDOR_ID, LONGSUNG_PRODUCT_U9300C) }, +++ { USB_DEVICE(FORGE_VENDOR_ID, FORGE_PRODUCT_SLM750) }, +++ { USB_DEVICE(NODECOM_VENDOR_ID, NODECOM_PRODUCT_NL660) }, +++ { USB_DEVICE(NEOWAY_VENDOR_ID, NEOWAY_PRODUCT_N720) }, +++ ++ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_COLT) }, ++ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_RICOLA) }, ++ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_RICOLA_LIGHT) }, ++@@ -2114,6 +2154,9 @@ static struct usb_serial_driver option_1 ++ #ifdef CONFIG_PM ++ .suspend = usb_wwan_suspend, ++ .resume = usb_wwan_resume, +++#if 1 //Added by Quectel +++ .reset_resume = usb_wwan_resume, +++#endif ++ #endif ++ }; ++ ++@@ -2136,6 +2179,7 @@ static int option_probe(struct usb_seria ++ { ++ struct usb_interface_descriptor *iface_desc = ++ &serial->interface->cur_altsetting->desc; +++ struct usb_device_descriptor *dev_desc = &serial->dev->descriptor; ++ unsigned long device_flags = id->driver_info; ++ ++ /* Never bind to the CD-Rom emulation interface */ ++@@ -2151,15 +2195,99 @@ static int option_probe(struct usb_seria ++ return -ENODEV; ++ ++ /* +++ * Don't bind network interface on Samsung GT-B3730, it is handled by +++ * a separate module. +++ */ +++ if (dev_desc->idVendor == cpu_to_le16(SAMSUNG_VENDOR_ID) && +++ dev_desc->idProduct == cpu_to_le16(SAMSUNG_PRODUCT_GT_B3730) && +++ iface_desc->bInterfaceClass != USB_CLASS_CDC_DATA) +++ return -ENODEV; +++ +++ /* ++ * Allow matching on bNumEndpoints for devices whose interface numbers ++ * can change (e.g. Quectel EP06). ++ */ ++ if (device_flags & NUMEP2 && iface_desc->bNumEndpoints != 2) ++ return -ENODEV; ++ ++- /* Store the device flags so we can use them during attach. */ ++- usb_set_serial_data(serial, (void *)device_flags); ++- +++#if 1 //Added by Quectel +++ //Quectel UC20's interface 4 can be used as USB network device +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x05C6) && \ +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x9003) \ +++ && serial->interface->cur_altsetting->desc.bInterfaceNumber >= 4) +++ return -ENODEV; +++ //Quectel EC20's interface 4 can be used as USB network device +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x05C6) && \ +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x9215) \ +++ && serial->interface->cur_altsetting->desc.bInterfaceNumber >= 4) +++ return -ENODEV; +++ //Quectel EC25&EC21&EG91&EG95&EG06&EP06&EM06&BG96/AG35's interface 4 can be used as USB network device +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x2C7C) && \ +++ serial->dev->descriptor.idProduct != cpu_to_le16(0x6026) \ +++ && serial->interface->cur_altsetting->desc.bInterfaceNumber >= 4) +++ return -ENODEV; +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x2C7C) && \ +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x6026) \ +++ && serial->interface->cur_altsetting->desc.bInterfaceNumber<= 1) +++ return -ENODEV; +++#endif +++#if 1 //Added by Quectel +++ //For USB Auto Suspend +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x05C6) && +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x9090)) { +++ pm_runtime_set_autosuspend_delay(&serial->dev->dev, 3000); +++ usb_enable_autosuspend(serial->dev); +++ } +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x05C6) && +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x9003)) { +++ pm_runtime_set_autosuspend_delay(&serial->dev->dev, 3000); +++ usb_enable_autosuspend(serial->dev); +++ } +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x05C6) && +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x9215)) { +++ pm_runtime_set_autosuspend_delay(&serial->dev->dev, 3000); +++ usb_set_serial_data(serial, (void *)device_flags); +++ usb_enable_autosuspend(serial->dev); +++ } +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x2C7C)) { +++ pm_runtime_set_autosuspend_delay(&serial->dev->dev, 3000); +++ usb_enable_autosuspend(serial->dev); +++ } +++#endif +++#if 1 //Added by Quectel +++ //For USB Remote Wakeup +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x05C6) && +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x9090)) { +++ device_init_wakeup(&serial->dev->dev, 1); //usb remote wakeup +++ } +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x05C6) && +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x9003)) { +++ device_init_wakeup(&serial->dev->dev, 1); //usb remote wakeup +++ } +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x05C6) && +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x9215)) { +++ device_init_wakeup(&serial->dev->dev, 1); //usb remote wakeup +++ } +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x2C7C)) { +++ device_init_wakeup(&serial->dev->dev, 1); //usb remote wakeup +++ } +++#endif +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x19d2) && +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x1476) && +++ serial->interface->cur_altsetting->desc. bInterfaceNumber == 3) +++ return -ENODEV; +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x19d2) && +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x1476) && +++ serial->interface->cur_altsetting->desc. bInterfaceNumber == 4) +++ return -ENODEV; +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x19d2) && +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x1509) && +++ serial->interface->cur_altsetting->desc. bInterfaceNumber == 4) +++ return -ENODEV; +++ if (serial->dev->descriptor.idVendor == cpu_to_le16(0x19d2) && +++ serial->dev->descriptor.idProduct == cpu_to_le16(0x1509) && +++ serial->interface->cur_altsetting->desc. bInterfaceNumber == 5) +++ return -ENODEV; ++ return 0; ++ } ++ ++Index: b/drivers/usb/serial/qcserial.c ++=================================================================== ++--- a/drivers/usb/serial/qcserial.c 2021-09-18 12:18:32.582950993 +0800 +++++ b/drivers/usb/serial/qcserial.c 2021-09-18 12:18:32.582950993 +0800 ++@@ -88,7 +88,6 @@ static const struct usb_device_id id_tab ++ {USB_DEVICE(0x03f0, 0x241d)}, /* HP Gobi 2000 QDL device (VP412) */ ++ {USB_DEVICE(0x03f0, 0x251d)}, /* HP Gobi 2000 Modem device (VP412) */ ++ {USB_DEVICE(0x05c6, 0x9214)}, /* Acer Gobi 2000 QDL device (VP413) */ ++- {USB_DEVICE(0x05c6, 0x9215)}, /* Acer Gobi 2000 Modem device (VP413) */ ++ {USB_DEVICE(0x05c6, 0x9264)}, /* Asus Gobi 2000 QDL device (VR305) */ ++ {USB_DEVICE(0x05c6, 0x9265)}, /* Asus Gobi 2000 Modem device (VR305) */ ++ {USB_DEVICE(0x05c6, 0x9234)}, /* Top Global Gobi 2000 QDL device (VR306) */ ++Index: b/drivers/usb/serial/usb_wwan.c ++=================================================================== ++--- a/drivers/usb/serial/usb_wwan.c 2021-09-18 12:18:32.582950993 +0800 +++++ b/drivers/usb/serial/usb_wwan.c 2021-09-18 12:18:32.582950993 +0800 ++@@ -476,6 +476,19 @@ static struct urb *usb_wwan_setup_urb(st ++ usb_fill_bulk_urb(urb, serial->dev, ++ usb_sndbulkpipe(serial->dev, endpoint) | dir, ++ buf, len, callback, ctx); +++#if 1 //Added by Quectel for zero packet +++ if (dir == USB_DIR_OUT) { +++ struct usb_device_descriptor *desc = &serial->dev->descriptor; +++ if (desc->idVendor == cpu_to_le16(0x05C6) && desc->idProduct == cpu_to_le16(0x9090)) +++ urb->transfer_flags |= URB_ZERO_PACKET; +++ if (desc->idVendor == cpu_to_le16(0x05C6) && desc->idProduct == cpu_to_le16(0x9003)) +++ urb->transfer_flags |= URB_ZERO_PACKET; +++ if (desc->idVendor == cpu_to_le16(0x05C6) && desc->idProduct == cpu_to_le16(0x9215)) +++ urb->transfer_flags |= URB_ZERO_PACKET; +++ if (desc->idVendor == cpu_to_le16(0x2C7C)) +++ urb->transfer_flags |= URB_ZERO_PACKET; +++ } +++#endif ++ ++ if (intfdata->use_zlp && dir == USB_DIR_OUT) ++ urb->transfer_flags |= URB_ZERO_PACKET; +-- +2.17.1 + diff --git a/patches-21.02.2/0004-add-RS485-support.patch b/patches-21.02.2/0004-add-RS485-support.patch new file mode 100644 index 0000000..4393e24 --- /dev/null +++ b/patches-21.02.2/0004-add-RS485-support.patch @@ -0,0 +1,102 @@ +From d5bdb37fd02b420cc6a682bf9e51e7e50658c85b Mon Sep 17 00:00:00 2001 +From: "GL.iNet-Hongjian.Zhang" +Date: Sat, 18 Sep 2021 14:44:13 +0800 +Subject: [PATCH 4/8] add RS485 support + +--- + .../821-fix-glinet-rs485-auto-txrx.patch | 83 +++++++++++++++++++ + 1 file changed, 83 insertions(+) + create mode 100644 target/linux/ath79/patches-5.4/821-fix-glinet-rs485-auto-txrx.patch + +diff --git a/target/linux/ath79/patches-5.4/821-fix-glinet-rs485-auto-txrx.patch b/target/linux/ath79/patches-5.4/821-fix-glinet-rs485-auto-txrx.patch +new file mode 100644 +index 0000000000..2030cad53d +--- /dev/null ++++ b/target/linux/ath79/patches-5.4/821-fix-glinet-rs485-auto-txrx.patch +@@ -0,0 +1,83 @@ ++Index: b/drivers/tty/serial/8250/8250.h ++=================================================================== ++--- a/drivers/tty/serial/8250/8250.h 2021-08-26 20:55:22.000000000 +0800 +++++ b/drivers/tty/serial/8250/8250.h 2021-09-18 14:30:46.200708724 +0800 ++@@ -13,6 +13,8 @@ ++ ++ #include "../serial_mctrl_gpio.h" ++ +++extern unsigned int rs485txen_gpio; +++ ++ struct uart_8250_dma { ++ int (*tx_dma)(struct uart_8250_port *p); ++ int (*rx_dma)(struct uart_8250_port *p); ++Index: b/drivers/tty/serial/8250/8250_of.c ++=================================================================== ++--- a/drivers/tty/serial/8250/8250_of.c 2021-08-26 20:55:22.000000000 +0800 +++++ b/drivers/tty/serial/8250/8250_of.c 2021-09-18 14:41:02.964067786 +0800 ++@@ -205,6 +205,7 @@ err_pmruntime: ++ /* ++ * Try to register a serial port ++ */ +++unsigned int rs485txen_gpio = 0xff; ++ static int of_platform_serial_probe(struct platform_device *ofdev) ++ { ++ struct of_serial_info *info; ++@@ -246,6 +247,10 @@ static int of_platform_serial_probe(stru ++ &port8250.overrun_backoff_time_ms) != 0) ++ port8250.overrun_backoff_time_ms = 0; ++ +++ if(!of_property_read_u32(ofdev->dev.of_node,"rs485_pin",&rs485txen_gpio)){ +++ pr_info("Serial port to 485 enable,rs485txen_gpio = gpio%d \n",rs485txen_gpio); +++ } +++ ++ ret = serial8250_register_8250_port(&port8250); ++ if (ret < 0) ++ goto err_dispose; ++Index: b/drivers/tty/serial/8250/8250_port.c ++=================================================================== ++--- a/drivers/tty/serial/8250/8250_port.c 2021-08-26 20:55:22.000000000 +0800 +++++ b/drivers/tty/serial/8250/8250_port.c 2021-09-18 14:36:49.548608917 +0800 ++@@ -34,6 +34,7 @@ ++ #include ++ #include ++ #include +++#include ++ ++ #include ++ #include ++@@ -1463,10 +1464,22 @@ static void __stop_tx_rs485(struct uart_ ++ } ++ } ++ +++static unsigned int serial8250_tx_empty(struct uart_port *port); ++ static inline void __do_stop_tx(struct uart_8250_port *p) ++ { ++- if (serial8250_clear_THRI(p)) +++ if (serial8250_clear_THRI(p)){ +++ ++ serial8250_rpm_put_tx(p); +++ +++ if(0xff != rs485txen_gpio){ +++ +++ while(!serial8250_tx_empty(&(p->port))){ +++ +++ ; +++ } +++ gpiod_set_value(gpio_to_desc(rs485txen_gpio),0); +++ } +++ } ++ } ++ ++ static inline void __stop_tx(struct uart_8250_port *p) ++@@ -1510,6 +1523,10 @@ static void serial8250_stop_tx(struct ua ++ ++ static inline void __start_tx(struct uart_port *port) ++ { +++ if(0xff != rs485txen_gpio){ +++ gpiod_set_value(gpio_to_desc(rs485txen_gpio),1); +++ } +++ ++ struct uart_8250_port *up = up_to_u8250p(port); ++ ++ if (up->dma && !up->dma->tx_dma(up)) +-- +2.17.1 + diff --git a/patches-21.02.2/0005-add-spinand-support.patch b/patches-21.02.2/0005-add-spinand-support.patch new file mode 100644 index 0000000..3b1f5fc --- /dev/null +++ b/patches-21.02.2/0005-add-spinand-support.patch @@ -0,0 +1,79 @@ +From 21020c2da30239e998d69c95c53bfbbc428f76a2 Mon Sep 17 00:00:00 2001 +From: "GL.iNet-Hongjian.Zhang" +Date: Sat, 18 Sep 2021 15:52:56 +0800 +Subject: [PATCH 5/8] add spinand support + +--- + .../499-mtd-spinand-add-support.patch | 60 +++++++++++++++++++ + 1 file changed, 60 insertions(+) + create mode 100644 target/linux/ath79/patches-5.4/499-mtd-spinand-add-support.patch + +diff --git a/target/linux/ath79/patches-5.4/499-mtd-spinand-add-support.patch b/target/linux/ath79/patches-5.4/499-mtd-spinand-add-support.patch +new file mode 100644 +index 0000000000..4a4b6e9bf0 +--- /dev/null ++++ b/target/linux/ath79/patches-5.4/499-mtd-spinand-add-support.patch +@@ -0,0 +1,60 @@ ++Index: b/drivers/mtd/nand/spi/gigadevice.c ++=================================================================== ++--- a/drivers/mtd/nand/spi/gigadevice.c 2021-09-18 14:49:34.250500716 +0800 +++++ b/drivers/mtd/nand/spi/gigadevice.c 2021-09-18 14:55:06.091509000 +0800 ++@@ -278,6 +278,15 @@ static const struct spinand_info gigadev ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, ++ gd5fxgq4uexxg_ecc_get_status)), +++ SPINAND_INFO("GD5F1GQ5UExxG", 0x51, +++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), +++ NAND_ECCREQ(8, 512), +++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +++ &write_cache_variants, +++ &update_cache_variants), +++ SPINAND_HAS_QE_BIT, +++ SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, +++ gd5fxgq4uexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148, ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++Index: b/drivers/mtd/nand/spi/macronix.c ++=================================================================== ++--- a/drivers/mtd/nand/spi/macronix.c 2021-08-26 20:55:22.000000000 +0800 +++++ b/drivers/mtd/nand/spi/macronix.c 2021-09-18 15:06:07.031203336 +0800 ++@@ -108,6 +108,15 @@ static const struct spinand_info macroni ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, ++ mx35lf1ge4ab_ecc_get_status)), +++ SPINAND_INFO("MX35LF1G24AD", 0x14, +++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), +++ NAND_ECCREQ(4, 512), +++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +++ &write_cache_variants, +++ &update_cache_variants), +++ SPINAND_HAS_QE_BIT, +++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, +++ mx35lf1ge4ab_ecc_get_status)), ++ SPINAND_INFO("MX35LF2GE4AB", 0x22, ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), ++ NAND_ECCREQ(4, 512), ++Index: b/drivers/mtd/nand/spi/paragon.c ++=================================================================== ++--- a/drivers/mtd/nand/spi/paragon.c 2021-08-26 20:55:22.000000000 +0800 +++++ b/drivers/mtd/nand/spi/paragon.c 2021-09-18 15:01:02.476309144 +0800 ++@@ -115,6 +115,15 @@ static const struct spinand_info paragon ++ 0, ++ SPINAND_ECCINFO(&pn26g0xa_ooblayout, ++ pn26g0xa_ecc_get_status)), +++ SPINAND_INFO("XT26G01xxxx", 0xf1, +++ NAND_MEMORG(1, 2048, 128, 64, 1024, 21, 1, 1, 1), +++ NAND_ECCREQ(8, 512), +++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +++ &write_cache_variants, +++ &update_cache_variants), +++ 0, +++ SPINAND_ECCINFO(&pn26g0xa_ooblayout, +++ pn26g0xa_ecc_get_status)), ++ }; ++ ++ static int paragon_spinand_detect(struct spinand_device *spinand) +-- +2.17.1 + diff --git a/patches-21.02.2/0006-led-netdev-trigger-by-wwanx.patch b/patches-21.02.2/0006-led-netdev-trigger-by-wwanx.patch new file mode 100644 index 0000000..94974de --- /dev/null +++ b/patches-21.02.2/0006-led-netdev-trigger-by-wwanx.patch @@ -0,0 +1,59 @@ +From aa487fa14318de14da3281023b8f45e7b6e7b0ff Mon Sep 17 00:00:00 2001 +From: "GL.iNet-Hongjian.Zhang" +Date: Sat, 18 Sep 2021 16:40:41 +0800 +Subject: [PATCH 6/8] led netdev trigger by wwanx + +--- + target/linux/ath79/dts/qca953x.dtsi | 2 +- + .../931-fix-led-netdev-trigger-by-wwanx.patch | 26 +++++++++++++++++++ + 2 files changed, 27 insertions(+), 1 deletion(-) + create mode 100644 target/linux/ath79/patches-5.4/931-fix-led-netdev-trigger-by-wwanx.patch + +diff --git a/target/linux/ath79/dts/qca953x.dtsi b/target/linux/ath79/dts/qca953x.dtsi +index 943e42437a..7774d073e7 100644 +--- a/target/linux/ath79/dts/qca953x.dtsi ++++ b/target/linux/ath79/dts/qca953x.dtsi +@@ -240,7 +240,7 @@ + builtin-switch; + + builtin_switch: switch0@1f { +- compatible = "qca,ar8229"; ++ compatible = "qca,ar8229-builtin"; + + reg = <0x1f>; + resets = <&rst 8>; +diff --git a/target/linux/ath79/patches-5.4/931-fix-led-netdev-trigger-by-wwanx.patch b/target/linux/ath79/patches-5.4/931-fix-led-netdev-trigger-by-wwanx.patch +new file mode 100644 +index 0000000000..e4b5950faf +--- /dev/null ++++ b/target/linux/ath79/patches-5.4/931-fix-led-netdev-trigger-by-wwanx.patch +@@ -0,0 +1,26 @@ ++Index: b/drivers/leds/trigger/ledtrig-netdev.c ++=================================================================== ++--- a/drivers/leds/trigger/ledtrig-netdev.c 2021-08-26 20:55:22.000000000 +0800 +++++ b/drivers/leds/trigger/ledtrig-netdev.c 2021-09-18 16:00:16.427666394 +0800 ++@@ -109,6 +109,7 @@ static ssize_t device_name_store(struct ++ size_t size) ++ { ++ struct led_netdev_data *trigger_data = led_trigger_get_drvdata(dev); +++ unsigned int flags; ++ ++ if (size >= IFNAMSIZ) ++ return -EINVAL; ++@@ -132,9 +133,11 @@ static ssize_t device_name_store(struct ++ dev_get_by_name(&init_net, trigger_data->device_name); ++ ++ clear_bit(NETDEV_LED_MODE_LINKUP, &trigger_data->mode); ++- if (trigger_data->net_dev != NULL) ++- if (netif_carrier_ok(trigger_data->net_dev)) +++ if (trigger_data->net_dev != NULL){ +++ flags = dev_get_flags(trigger_data->net_dev); +++ if (flags & IFF_LOWER_UP) ++ set_bit(NETDEV_LED_MODE_LINKUP, &trigger_data->mode); +++ } ++ ++ trigger_data->last_activity = 0; ++ +-- +2.17.1 + diff --git a/patches-21.02.2/0007-ath79-add-support-for-gl-ar300m.patch b/patches-21.02.2/0007-ath79-add-support-for-gl-ar300m.patch new file mode 100644 index 0000000..c8ff92f --- /dev/null +++ b/patches-21.02.2/0007-ath79-add-support-for-gl-ar300m.patch @@ -0,0 +1,240 @@ +From 35dfe90cd27e4070eb0dba1ee1d33618e2e8f4cb Mon Sep 17 00:00:00 2001 +From: "GL.iNet-Hongjian.Zhang" +Date: Sat, 18 Sep 2021 18:14:38 +0800 +Subject: [PATCH 7/8] ath79: add support for gl ar300m + +--- + .../ath79/dts/qca9531_glinet_gl-ar300m.dtsi | 42 +++++++++++++++---- + .../generic/base-files/etc/board.d/01_leds | 2 - + .../generic/base-files/etc/board.d/02_network | 1 - + target/linux/ath79/image/generic.mk | 21 ---------- + target/linux/ath79/image/nand.mk | 26 ++++++------ + .../ath79/nand/base-files/etc/board.d/01_leds | 2 +- + .../nand/base-files/etc/board.d/02_network | 2 + + 7 files changed, 49 insertions(+), 47 deletions(-) + +diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi +index d0b0d88c48..2f747e5a30 100644 +--- a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi ++++ b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi +@@ -12,6 +12,26 @@ + label-mac-device = ð0; + }; + ++ gl_hw { ++ compatible = "gl-hw-info"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "ar300m"; ++ wan = "eth0"; ++ lan = "eth1"; ++ switch-button = "gpio-0"; ++ reset-button = "gpio-3"; ++ usb-port = "1-1"; ++ factory_data { ++ device_mac = "art"; ++ device_ddns = "art", "0x10"; ++ device_sn_bak = "art", "0x20"; ++ device_sn = "art", "0x30"; ++ country_code = "art", "0x88"; ++ }; ++ }; ++ + keys { + compatible = "gpio-keys"; + +@@ -43,28 +63,31 @@ + // Colors for non-Lite versions + + led_status: status { +- label = "green:status"; ++ label = "gl-ar300m:green:status"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + + lan { +- label = "green:lan"; ++ label = "gl-ar300m:green:lan"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + }; + + led_wlan: wlan { +- label = "red:wlan"; ++ label = "gl-ar300m:green:wlan"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + }; ++ gpio-export { ++ compatible = "gpio-export"; + +- i2c: i2c { +- compatible = "i2c-gpio"; +- +- sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; +- scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; ++ gpio_usb_power { ++ gpio-export,name = "usb_power"; ++ gpio-export,output = <1>; ++ gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; ++ }; + }; ++ + }; + + &pcie0 { +@@ -147,14 +170,17 @@ + phy-handle = <&swphy4>; + + mtd-mac-address = <&art 0x0>; ++ ifname = "eth0"; + }; + + ð1 { + mtd-mac-address = <&art 0x0>; + mtd-mac-address-increment = <1>; ++ ifname = "eth1"; + }; + + &wmac { + status = "okay"; + mtd-cal-data = <&art 0x1000>; ++ mtd-mac-address = <&art 0x1002>; + }; +diff --git a/target/linux/ath79/generic/base-files/etc/board.d/01_leds b/target/linux/ath79/generic/base-files/etc/board.d/01_leds +index 985adfc6a7..f3690897ee 100755 +--- a/target/linux/ath79/generic/base-files/etc/board.d/01_leds ++++ b/target/linux/ath79/generic/base-files/etc/board.d/01_leds +@@ -16,8 +16,6 @@ alfa-network,ap121fe|\ + avm,fritz450e|\ + glinet,6408|\ + glinet,6416|\ +-glinet,gl-ar300m-lite|\ +-glinet,gl-ar300m16|\ + pcs,cap324|\ + tplink,cpe610-v1|\ + tplink,cpe610-v2) +diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network +index c4d9d76941..f446ba28c2 100755 +--- a/target/linux/ath79/generic/base-files/etc/board.d/02_network ++++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network +@@ -38,7 +38,6 @@ ath79_setup_interfaces() + engenius,ecb1750|\ + engenius,ecb600|\ + enterasys,ws-ap3705i|\ +- glinet,gl-ar300m-lite|\ + glinet,gl-usb150|\ + hak5,wifi-pineapple-nano|\ + meraki,mr16|\ +diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk +index 05ed698401..9fba9155df 100644 +--- a/target/linux/ath79/image/generic.mk ++++ b/target/linux/ath79/image/generic.mk +@@ -1167,27 +1167,6 @@ define Device/glinet_gl-ar150 + endef + TARGET_DEVICES += glinet_gl-ar150 + +-define Device/glinet_gl-ar300m-common-nor +- SOC := qca9531 +- DEVICE_VENDOR := GL.iNet +- DEVICE_PACKAGES := kmod-usb2 +- IMAGE_SIZE := 16000k +- SUPPORTED_DEVICES += gl-ar300m +-endef +- +-define Device/glinet_gl-ar300m-lite +- $(Device/glinet_gl-ar300m-common-nor) +- DEVICE_MODEL := GL-AR300M +- DEVICE_VARIANT := Lite +-endef +-TARGET_DEVICES += glinet_gl-ar300m-lite +- +-define Device/glinet_gl-ar300m16 +- $(Device/glinet_gl-ar300m-common-nor) +- DEVICE_MODEL := GL-AR300M16 +-endef +-TARGET_DEVICES += glinet_gl-ar300m16 +- + define Device/glinet_gl-ar750 + SOC := qca9531 + DEVICE_VENDOR := GL.iNet +diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk +index 0c6dd699f5..8f5c27d0fd 100644 +--- a/target/linux/ath79/image/nand.mk ++++ b/target/linux/ath79/image/nand.mk +@@ -77,33 +77,31 @@ define Device/domywifi_dw33d + endef + TARGET_DEVICES += domywifi_dw33d + +-define Device/glinet_gl-ar300m-common-nand ++define Device/glinet_gl-ar300m-common + SOC := qca9531 + DEVICE_VENDOR := GL.iNet + DEVICE_MODEL := GL-AR300M +- DEVICE_PACKAGES := kmod-usb2 +- KERNEL_SIZE := 4096k +- IMAGE_SIZE := 16000k +- PAGESIZE := 2048 +- VID_HDR_OFFSET := 2048 ++ DEVICE_PACKAGES := kmod-usb-core kmod-usb2 block-mount kmod-usb-storage kmod-usb-ledtrig-usbport ++ SUPPORTED_DEVICES += gl-ar300m glinet,gl-ar300m + endef + + define Device/glinet_gl-ar300m-nand +- $(Device/glinet_gl-ar300m-common-nand) ++ $(Device/glinet_gl-ar300m-common) + DEVICE_VARIANT := NAND ++ KERNEL_SIZE := 4096k + BLOCKSIZE := 128k +- IMAGES += factory.img +- IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi +- IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +- SUPPORTED_DEVICES += glinet,gl-ar300m-nor ++ PAGESIZE := 2048 ++ VID_HDR_OFFSET := 2048 ++ IMAGES := factory.img sysupgrade.tar ++ IMAGE/sysupgrade.tar := sysupgrade-tar-compat-1806 | append-gl-metadata ++ IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | append-gl-metadata + endef + TARGET_DEVICES += glinet_gl-ar300m-nand + + define Device/glinet_gl-ar300m-nor +- $(Device/glinet_gl-ar300m-common-nand) ++ $(Device/glinet_gl-ar300m-common) + DEVICE_VARIANT := NOR +- BLOCKSIZE := 64k +- SUPPORTED_DEVICES += glinet,gl-ar300m-nand gl-ar300m ++ IMAGE_SIZE := 16000k + endef + TARGET_DEVICES += glinet_gl-ar300m-nor + +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/01_leds b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +index 16545083fb..eb9e5817e6 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/01_leds ++++ b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +@@ -9,7 +9,7 @@ board=$(board_name) + case "$board" in + glinet,gl-ar300m-nand|\ + glinet,gl-ar300m-nor) +- ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" ++ ucidef_set_led_netdev "lan" "LAN" "gl-ar300m:green:lan" "eth1" + ;; + glinet,gl-mifi) + ucidef_set_led_wlan "wlan" "WLAN" "gl-mifi:green:wlan" "phy0tpt" +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/02_network b/target/linux/ath79/nand/base-files/etc/board.d/02_network +index 73e23e5eb9..bee36cac1b 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/02_network ++++ b/target/linux/ath79/nand/base-files/etc/board.d/02_network +@@ -21,6 +21,8 @@ ath79_setup_interfaces() + ucidef_add_switch "switch0" \ + "0@eth0" "2:lan:2" "3:lan:1" "1:wan" + ;; ++ glinet,gl-ar300m-nor|\ ++ glinet,gl-ar300m-nand|\ + glinet,gl-mifi) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; +-- +2.17.1 + diff --git a/patches-21.02.2/0008-ath79-add-support-for-gl-x300b.patch b/patches-21.02.2/0008-ath79-add-support-for-gl-x300b.patch new file mode 100644 index 0000000..8c1628b --- /dev/null +++ b/patches-21.02.2/0008-ath79-add-support-for-gl-x300b.patch @@ -0,0 +1,341 @@ +From f13cf41ee822127c8a42eb05a896f38724e0844f Mon Sep 17 00:00:00 2001 +From: "GL.iNet-Hongjian.Zhang" +Date: Wed, 22 Sep 2021 11:53:08 +0800 +Subject: [PATCH 8/8] ath79: add support for gl x300b + +--- + .../dts/qca9531_glinet_gl-x300b-nor-nand.dts | 25 +++ + .../ath79/dts/qca9531_glinet_gl-x300b-nor.dts | 18 ++ + .../ath79/dts/qca9531_glinet_gl-x300b.dtsi | 191 ++++++++++++++++++ + target/linux/ath79/image/nand.mk | 28 +++ + .../ath79/nand/base-files/etc/board.d/01_leds | 6 + + .../nand/base-files/etc/board.d/02_network | 2 + + 6 files changed, 270 insertions(+) + create mode 100644 target/linux/ath79/dts/qca9531_glinet_gl-x300b-nor-nand.dts + create mode 100644 target/linux/ath79/dts/qca9531_glinet_gl-x300b-nor.dts + create mode 100755 target/linux/ath79/dts/qca9531_glinet_gl-x300b.dtsi + +diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-x300b-nor-nand.dts b/target/linux/ath79/dts/qca9531_glinet_gl-x300b-nor-nand.dts +new file mode 100644 +index 0000000000..b50ed14f26 +--- /dev/null ++++ b/target/linux/ath79/dts/qca9531_glinet_gl-x300b-nor-nand.dts +@@ -0,0 +1,25 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++/dts-v1/; ++ ++#include "qca9531_glinet_gl-x300b.dtsi" ++ ++/ { ++ compatible = "glinet,gl-x300b-nor-nand", "qca,qca9531"; ++ model = "GL.iNet GL-X300B (NOR/NAND)"; ++}; ++ ++&nor_partitions { ++ partition@60000 { ++ label = "kernel"; ++ reg = <0x060000 0x200000>; ++ }; ++ parition@260000 { ++ label = "nor_reserved"; ++ reg = <0x260000 0xbc0000>; ++ }; ++}; ++ ++&nand_ubi { ++ label = "ubi"; ++}; +diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-x300b-nor.dts b/target/linux/ath79/dts/qca9531_glinet_gl-x300b-nor.dts +new file mode 100644 +index 0000000000..566df3c238 +--- /dev/null ++++ b/target/linux/ath79/dts/qca9531_glinet_gl-x300b-nor.dts +@@ -0,0 +1,18 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++/dts-v1/; ++ ++#include "qca9531_glinet_gl-x300b.dtsi" ++ ++/ { ++ compatible = "glinet,gl-x300b-nor", "qca,qca9531"; ++ model = "GL.iNet GL-X300B (NOR)"; ++}; ++ ++&nor_partitions { ++ partition@60000 { ++ compatible = "denx,uimage"; ++ label = "firmware"; ++ reg = <0x060000 0xfa0000>; ++ }; ++}; +diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-x300b.dtsi b/target/linux/ath79/dts/qca9531_glinet_gl-x300b.dtsi +new file mode 100755 +index 0000000000..728b40dceb +--- /dev/null ++++ b/target/linux/ath79/dts/qca9531_glinet_gl-x300b.dtsi +@@ -0,0 +1,191 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/dts-v1/; ++ ++#include ++#include ++ ++#include "qca953x.dtsi" ++ ++/ { ++ compatible = "glinet,gl-x300b", "qca,qca9531"; ++ model = "GL.iNet GL-X300B"; ++ ++ gl_hw { ++ compatible = "gl-hw-info"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "x300b"; ++ wan = "eth0"; ++ lan = "eth1"; ++ build-in-modem = "1-1"; ++ reset-button = "gpio-3"; ++ factory_data { ++ device_mac = "art"; ++ device_ddns = "art", "0x10"; ++ device_sn_bak = "art", "0x20"; ++ device_sn = "art", "0x30"; ++ country_code = "art", "0x88"; ++ }; ++ }; ++ ++ keys { ++ compatible = "gpio-keys-polled"; ++ ++ poll-interval = <20>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&jtag_disable_pins>; ++ ++ button0 { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&gpio 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ wlan2g { ++ label = "gl-x300b:green:wlan2g"; ++ gpios = <&gpio 4 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "phy0tpt"; ++ }; ++ ++ wan { ++ label = "gl-x300b:green:wan"; ++ gpios = <&gpio 13 GPIO_ACTIVE_LOW>; ++ }; ++ ++ lte { ++ label = "gl-x300b:green:lte"; ++ gpios = <&gpio 15 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ gpio-export { ++ compatible = "gpio-export"; ++ ++ gpio_lte_power { ++ gpio-export,name = "gpio0"; ++ gpio-export,output = <0>; ++ gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ gpio_rs485tx_en { ++ gpio-export,name = "gpio1"; ++ gpio-export,output = <0>; ++ gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ gpio_ble_rst { ++ gpio-export,name = "gpio16"; ++ gpio-export,output = <0>; ++ gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ }; ++ watchdog { ++ compatible = "hw_wdt"; ++ dog_en_gpio= <12>; ++ feed_dog_gpio=<2>; ++ feed_dog_interval=<100000000>; ++ }; ++ ++}; ++ ++ ++&uart { ++ status = "okay"; ++ rs485_pin=<1>; ++}; ++ ++&usb0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub_port: port@1 { ++ reg = <1>; ++ #trigger-source-cells = <0>; ++ }; ++}; ++ ++&usb_phy { ++ status = "okay"; ++}; ++ ++&spi { ++ status = "okay"; ++ num-cs = <2>; ++ cs-gpios = <0>, <0>; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <25000000>; ++ ++ nor_partitions: partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x000000 0x040000>; ++ read-only; ++ }; ++ ++ partition@40000 { ++ label = "u-boot-env"; ++ reg = <0x040000 0x010000>; ++ }; ++ ++ art: partition@50000 { ++ label = "art"; ++ reg = <0x050000 0x010000>; ++ read-only; ++ }; ++ }; ++ }; ++ ++ flash_nand: flash@1 { ++ compatible = "spi-nand"; ++ reg = <1>; ++ spi-max-frequency = <25000000>; ++ ++ nand_partitions: partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ nand_ubi: partition@0 { ++ label = "nand_ubi"; ++ reg = <0x000000 0x8000000>; ++ }; ++ }; ++ }; ++ ++}; ++/* ++&bootargs { ++ bootargs=""; ++};*/ ++ ++ð0 { ++ status = "okay"; ++ mtd-mac-address = <&art 0x0>; ++ phy-handle = <&swphy4>; ++ ifname = "eth0"; ++}; ++ ++ð1 { ++ mtd-mac-address = <&art 0x0>; ++ mtd-mac-address-increment = <1>; ++ ifname = "eth1"; ++}; ++ ++&wmac { ++ status = "okay"; ++ mtd-cal-data = <&art 0x1000>; ++ mtd-mac-address = <&art 0x1002>; ++}; +diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk +index 8f5c27d0fd..32d8fb612f 100644 +--- a/target/linux/ath79/image/nand.mk ++++ b/target/linux/ath79/image/nand.mk +@@ -77,6 +77,34 @@ define Device/domywifi_dw33d + endef + TARGET_DEVICES += domywifi_dw33d + ++define Device/glinet_gl-x300b-common ++ SOC := qca9531 ++ DEVICE_VENDOR := GL.iNet ++ DEVICE_MODEL := GL-X300B ++ DEVICE_PACKAGES := kmod-usb2 block-mount ++ SUPPORTED_DEVICES += gl-x300b glinet,gl-x300b ++endef ++ ++define Device/glinet_gl-x300b-nor ++ $(Device/glinet_gl-x300b-common) ++ DEVICE_VARIANT := NOR ++ IMAGE_SIZE := 16000k ++endef ++TARGET_DEVICES += glinet_gl-x300b-nor ++ ++define Device/glinet_gl-x300b-nor-nand ++ $(Device/glinet_gl-x300b-common) ++ DEVICE_VARIANT := NOR/NAND ++ KERNEL_SIZE := 4096k ++ BLOCKSIZE := 128k ++ PAGESIZE := 2048 ++ VID_HDR_OFFSET := 2048 ++ IMAGES := factory.img sysupgrade.tar ++ IMAGE/sysupgrade.tar := sysupgrade-tar-compat-1806 | append-gl-metadata ++ IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | append-gl-metadata ++endef ++TARGET_DEVICES += glinet_gl-x300b-nor-nand ++ + define Device/glinet_gl-ar300m-common + SOC := qca9531 + DEVICE_VENDOR := GL.iNet +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/01_leds b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +index eb9e5817e6..51cfe6562f 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/01_leds ++++ b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +@@ -17,6 +17,12 @@ glinet,gl-mifi) + ucidef_set_led_switch "lan" "LAN" "gl-mifi:green:lan" "switch0" "0x2" + ucidef_set_led_netdev "3gnet" "3GNET" "gl-mifi:green:net" "3g-wan" + ;; ++glinet,gl-x300b-nor|\ ++glinet,gl-x300b-nor-nand) ++ ucidef_set_led_netdev "wlan2g" "WLAN2G" "gl-x300b:green:wlan2g" "wlan0" ++ ucidef_set_led_netdev "wan" "WAN" "gl-x300b:green:wan" "eth0" ++ ucidef_set_led_netdev "3gnet" "3GNET" "gl-x300b:green:lte" "3g-wan" ++ ;; + glinet,gl-xe300-iot|\ + glinet,gl-xe300-nor|\ + glinet,gl-xe300-nor-nand) +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/02_network b/target/linux/ath79/nand/base-files/etc/board.d/02_network +index bee36cac1b..37fafafb0d 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/02_network ++++ b/target/linux/ath79/nand/base-files/etc/board.d/02_network +@@ -23,6 +23,8 @@ ath79_setup_interfaces() + ;; + glinet,gl-ar300m-nor|\ + glinet,gl-ar300m-nand|\ ++ glinet,gl-x300b-nor|\ ++ glinet,gl-x300b-nor-nand|\ + glinet,gl-mifi) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; +-- +2.17.1 + diff --git a/patches-21.02.2/0009-ath79-add-support-for-gl-ar150.patch b/patches-21.02.2/0009-ath79-add-support-for-gl-ar150.patch new file mode 100644 index 0000000..5369f76 --- /dev/null +++ b/patches-21.02.2/0009-ath79-add-support-for-gl-ar150.patch @@ -0,0 +1,255 @@ +From 9d8aee76faf6c15a9259d57e99b76aa052187035 Mon Sep 17 00:00:00 2001 +From: "GL.iNet-Hongjian.Zhang" +Date: Thu, 23 Sep 2021 11:48:04 +0800 +Subject: [PATCH 1/2] ath79: add support for gl ar150 + +--- + target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts | 74 +++++++++++++++++----- + target/linux/ath79/image/generic.mk | 10 --- + target/linux/ath79/image/nand.mk | 11 +++- + .../ath79/nand/base-files/etc/board.d/01_leds | 3 + + .../ath79/nand/base-files/etc/board.d/02_network | 1 + + 5 files changed, 72 insertions(+), 27 deletions(-) + +diff --git a/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts b/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts +index 6a13c1b..42edf5a 100644 +--- a/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts ++++ b/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts +@@ -1,45 +1,63 @@ + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT +- +-#include "ar9330.dtsi" ++/dts-v1/; + + #include + #include + ++#include "ar9330_glinet.dtsi" ++ + / { + model = "GL.iNet GL-AR150"; + compatible = "glinet,gl-ar150", "qca,ar9330"; + + aliases { +- led-boot = &led_power; +- led-failsafe = &led_power; +- led-running = &led_power; +- led-upgrade = &led_power; +- label-mac-device = ð0; ++ serial0 = &uart; ++ }; ++ ++ gl_hw { ++ compatible = "gl-hw-info"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "ar150"; ++ wan = "eth0"; ++ lan = "eth1"; ++ switch-button = "gpio-8"; ++ reset-button = "gpio-11"; ++ usb-port = "1-1"; ++ factory_data { ++ device_mac = "art"; ++ device_ddns = "art", "0x10"; ++ device_sn_bak = "art", "0x20"; ++ device_sn = "art", "0x30"; ++ country_code = "art", "0x88"; ++ }; + }; + + leds { + compatible = "gpio-leds"; + + wlan { +- label = "orange:wlan"; ++ label = "gl-ar150:red:wlan"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; + }; + + configurable { +- label = "green:configurable"; ++ label = "gl-ar150:green:configurable"; + gpios = <&gpio 13 GPIO_ACTIVE_HIGH>; + }; + + led_power: power { +- label = "green:power"; ++ label = "gl-ar150:green:power"; + gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + keys { +- compatible = "gpio-keys"; ++ compatible = "gpio-keys-polled"; ++ poll-interval = <100>; + + manual { + label = "manual"; +@@ -48,7 +66,7 @@ + }; + + auto { +- label = "auto"; ++ label = "BTN_8"; + linux,code = ; + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; + }; +@@ -59,6 +77,19 @@ + gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; + }; + }; ++ gpio-export { ++ compatible = "gpio-export"; ++ gpio_usb_power { ++ gpio-export,name = "usb_power"; ++ gpio-export,output = <1>; ++ gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ }; ++}; ++ ++&uart { ++ status = "okay"; + }; + + &usb { +@@ -66,17 +97,27 @@ + status = "okay"; + }; + ++&usb { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub_port: port@1 { ++ reg = <1>; ++ #trigger-source-cells = <0>; ++ }; ++}; + &usb_phy { + status = "okay"; +- gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; + }; + + &spi { ++ num-chipselects = <1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; +- spi-max-frequency = <50000000>; ++ spi-max-frequency = <104000000>; + reg = <0>; + + partitions { +@@ -114,13 +155,15 @@ + status = "okay"; + + mtd-mac-address = <&art 0x0>; ++ ++ ifname = "eth0"; + }; + + ð1 { + status = "okay"; + + mtd-mac-address = <&art 0x0>; +- ++ ifname = "eth1"; + gmac-config { + device = <&gmac>; + +@@ -131,7 +174,6 @@ + + &wmac { + status = "okay"; +- + mtd-cal-data = <&art 0x1000>; + mtd-mac-address = <&art 0x0>; + }; +diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk +index 9fba915..0799ae7 100644 +--- a/target/linux/ath79/image/generic.mk ++++ b/target/linux/ath79/image/generic.mk +@@ -1157,16 +1157,6 @@ define Device/glinet_6416 + endef + TARGET_DEVICES += glinet_6416 + +-define Device/glinet_gl-ar150 +- SOC := ar9330 +- DEVICE_VENDOR := GL.iNet +- DEVICE_MODEL := GL-AR150 +- DEVICE_PACKAGES := kmod-usb-chipidea2 +- IMAGE_SIZE := 16000k +- SUPPORTED_DEVICES += gl-ar150 +-endef +-TARGET_DEVICES += glinet_gl-ar150 +- + define Device/glinet_gl-ar750 + SOC := qca9531 + DEVICE_VENDOR := GL.iNet +diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk +index 32d8fb6..f45877e 100644 +--- a/target/linux/ath79/image/nand.mk ++++ b/target/linux/ath79/image/nand.mk +@@ -77,6 +77,15 @@ define Device/domywifi_dw33d + endef + TARGET_DEVICES += domywifi_dw33d + ++define Device/glinet_gl-ar150 ++ SOC := ar9330 ++ DEVICE_TITLE := GL.iNet GL-AR150 ++ DEVICE_PACKAGES := kmod-usb2 block-mount ++ IMAGE_SIZE := 16000k ++ SUPPORTED_DEVICES += gl-ar150 glinet,gl-ar150 ++endef ++TARGET_DEVICES += glinet_gl-ar150 ++ + define Device/glinet_gl-x300b-common + SOC := qca9531 + DEVICE_VENDOR := GL.iNet +@@ -136,7 +145,7 @@ TARGET_DEVICES += glinet_gl-ar300m-nor + define Device/glinet_gl-mifi + SOC := ar9331 + DEVICE_VENDOR := GL.iNET +- DEVICE_MODEL := GL-MiFi ++ DEVICE_MODEL := GL-MIFI + DEVICE_PACKAGES := kmod-usb-chipidea2 + IMAGE_SIZE := 16000k + SUPPORTED_DEVICES += gl-mifi glinet,gl-mifi +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/01_leds b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +index 51cfe65..27f8ee2 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/01_leds ++++ b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +@@ -7,6 +7,9 @@ board_config_update + board=$(board_name) + + case "$board" in ++glinet,gl-ar150) ++ ucidef_set_led_wlan "wlan" "WLAN" "gl-ar150:orange:wlan" "phy0tpt" ++ ;; + glinet,gl-ar300m-nand|\ + glinet,gl-ar300m-nor) + ucidef_set_led_netdev "lan" "LAN" "gl-ar300m:green:lan" "eth1" +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/02_network b/target/linux/ath79/nand/base-files/etc/board.d/02_network +index 37fafaf..9be5bef 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/02_network ++++ b/target/linux/ath79/nand/base-files/etc/board.d/02_network +@@ -25,6 +25,7 @@ ath79_setup_interfaces() + glinet,gl-ar300m-nand|\ + glinet,gl-x300b-nor|\ + glinet,gl-x300b-nor-nand|\ ++ glinet,gl-ar150|\ + glinet,gl-mifi) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; +-- +2.7.4 + diff --git a/patches-21.02.2/0010-ath79-add-support-for-gl-usb150.patch b/patches-21.02.2/0010-ath79-add-support-for-gl-usb150.patch new file mode 100644 index 0000000..0db5565 --- /dev/null +++ b/patches-21.02.2/0010-ath79-add-support-for-gl-usb150.patch @@ -0,0 +1,366 @@ +From 21ee3befaa14358ee3587eb459c150c04f56cd78 Mon Sep 17 00:00:00 2001 +From: "GL.iNet-Hongjian.Zhang" +Date: Thu, 23 Sep 2021 18:22:18 +0800 +Subject: [PATCH 2/2] ath79: add support for gl usb150 + +--- + target/linux/ath79/dts/ar9330_glinet_gl-usb150.dts | 136 +++++++++++++++++++++ + target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts | 119 ------------------ + .../generic/base-files/etc/board.d/02_network | 1 - + target/linux/ath79/image/generic.mk | 9 -- + target/linux/ath79/image/nand.mk | 9 ++ + .../ath79/nand/base-files/etc/board.d/01_leds | 4 + + .../ath79/nand/base-files/etc/board.d/02_network | 1 + + 7 files changed, 150 insertions(+), 129 deletions(-) + create mode 100755 target/linux/ath79/dts/ar9330_glinet_gl-usb150.dts + delete mode 100644 target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts + +diff --git a/target/linux/ath79/dts/ar9330_glinet_gl-usb150.dts b/target/linux/ath79/dts/ar9330_glinet_gl-usb150.dts +new file mode 100755 +index 0000000..72848a5 +--- /dev/null ++++ b/target/linux/ath79/dts/ar9330_glinet_gl-usb150.dts +@@ -0,0 +1,136 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/dts-v1/; ++ ++#include ++#include ++ ++#include "ar9330_glinet.dtsi" ++ ++/ { ++ model = "GL.iNet GL-USB150"; ++ compatible = "glinet,gl-usb150", "qca,ar9330"; ++ ++ aliases { ++ serial0 = &uart; ++ }; ++ ++ gl_hw { ++ compatible = "gl-hw-info"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "usb150"; ++ lan = "eth0"; ++ reset-button = "gpio-11"; ++ factory_data { ++ device_mac = "art"; ++ device_ddns = "art", "0x10"; ++ device_sn_bak = "art", "0x20"; ++ device_sn = "art", "0x30"; ++ country_code = "art", "0x88"; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ wlan { ++ label = "gl-usb150:orange:wlan"; ++ gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "phy0tpt"; ++ }; ++ ++ led_power: power { ++ label = "gl-usb150:green:power"; ++ gpios = <&gpio 13 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ }; ++ ++ keys { ++ compatible = "gpio-keys-polled"; ++ poll-interval = <100>; ++ ++ reset { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ gpio-export { ++ compatible = "gpio-export"; ++ gpio_usb_power { ++ gpio-export,name = "gpio7"; ++ gpio-export,output = <0>; ++ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart { ++ status = "okay"; ++}; ++ ++&spi { ++ num-chipselects = <1>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ spi-max-frequency = <104000000>; ++ reg = <0>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x000000 0x040000>; ++ read-only; ++ }; ++ ++ partition@1 { ++ label = "u-boot-env"; ++ reg = <0x040000 0x010000>; ++ }; ++ ++ partition@2 { ++ compatible = "denx,uimage"; ++ label = "firmware"; ++ reg = <0x050000 0xfa0000>; ++ }; ++ ++ art: partition@3 { ++ label = "art"; ++ reg = <0xff0000 0x010000>; ++ read-only; ++ }; ++ }; ++ }; ++}; ++ ++ð0 { ++ status = "okay"; ++ ++ mtd-mac-address = <&art 0x0>; ++ ++ gmac-config { ++ device = <&gmac>; ++ ++ switch-phy-addr-swap = <0>; ++ switch-phy-swap = <0>; ++ }; ++}; ++ ++ð1 { ++ status = "okay"; ++ compatible = "syscon", "simple-mfd"; ++}; ++ ++&wmac { ++ status = "okay"; ++ mtd-cal-data = <&art 0x1000>; ++ mtd-mac-address = <&art 0x0>; ++}; +diff --git a/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts b/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts +deleted file mode 100644 +index d1c2654..0000000 +--- a/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts ++++ /dev/null +@@ -1,119 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +- +-#include "ar9331.dtsi" +- +-#include +-#include +- +-/ { +- compatible = "glinet,gl-usb150", "qca,ar9331"; +- model = "GL.iNet GL-USB150"; +- +- aliases { +- led-boot = &led_power; +- led-failsafe = &led_power; +- led-running = &led_power; +- led-upgrade = &led_power; +- label-mac-device = ð0; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- wlan { +- label = "green:wlan"; +- gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy0tpt"; +- }; +- +- led_power: power { +- label = "green:power"; +- gpios = <&gpio 13 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- }; +- +- keys { +- compatible = "gpio-keys"; +- +- reset { +- label = "reset"; +- linux,code = ; +- gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; +- debounce-interval = <60>; +- }; +- }; +- +- gpio-export { +- compatible = "gpio-export"; +- +- gpio_lan_reset { +- gpio-export,name = "lan:reset"; +- gpio-export,output = <0>; +- gpios = <&gpio 7 GPIO_ACTIVE_LOW>; +- }; +- }; +-}; +- +-ð0 { +- status = "okay"; +- +- mtd-mac-address = <&art 0x0>; +- +- gmac-config { +- device = <&gmac>; +- switch-phy-addr-swap = <0>; +- switch-phy-swap = <0>; +- }; +-}; +- +-ð1 { +- status = "okay"; +- +- compatible = "syscon", "simple-mfd"; +-}; +- +-&spi { +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- spi-max-frequency = <33000000>; +- reg = <0>; +- +- partitions { +- compatible = "fixed-partitions"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "u-boot"; +- reg = <0x000000 0x040000>; +- read-only; +- }; +- +- partition@40000 { +- label = "u-boot-env"; +- reg = <0x040000 0x010000>; +- }; +- +- partition@50000 { +- compatible = "denx,uimage"; +- label = "firmware"; +- reg = <0x050000 0xfa0000>; +- }; +- +- art: partition@ff0000 { +- label = "art"; +- reg = <0xff0000 0x010000>; +- read-only; +- }; +- }; +- }; +-}; +- +-&wmac { +- status = "okay"; +- +- mtd-cal-data = <&art 0x1000>; +-}; +diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network +index f446ba2..dedc9fc 100755 +--- a/target/linux/ath79/generic/base-files/etc/board.d/02_network ++++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network +@@ -38,7 +38,6 @@ ath79_setup_interfaces() + engenius,ecb1750|\ + engenius,ecb600|\ + enterasys,ws-ap3705i|\ +- glinet,gl-usb150|\ + hak5,wifi-pineapple-nano|\ + meraki,mr16|\ + netgear,ex6400|\ +diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk +index 0799ae7..cf3fce3 100644 +--- a/target/linux/ath79/image/generic.mk ++++ b/target/linux/ath79/image/generic.mk +@@ -1167,15 +1167,6 @@ define Device/glinet_gl-ar750 + endef + TARGET_DEVICES += glinet_gl-ar750 + +-define Device/glinet_gl-usb150 +- SOC := ar9331 +- DEVICE_VENDOR := GL.iNET +- DEVICE_MODEL := GL-USB150 +- IMAGE_SIZE := 16000k +- SUPPORTED_DEVICES += gl-usb150 +-endef +-TARGET_DEVICES += glinet_gl-usb150 +- + define Device/glinet_gl-x750 + SOC := qca9531 + DEVICE_VENDOR := GL.iNet +diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk +index f45877e..83ca331 100644 +--- a/target/linux/ath79/image/nand.mk ++++ b/target/linux/ath79/image/nand.mk +@@ -86,6 +86,15 @@ define Device/glinet_gl-ar150 + endef + TARGET_DEVICES += glinet_gl-ar150 + ++define Device/glinet_gl-usb150 ++ SOC := ar9330 ++ DEVICE_TITLE := GL.iNet GL-USB150 ++ DEVICE_PACKAGES := kmod-usb2 block-mount ++ IMAGE_SIZE := 16000k ++ SUPPORTED_DEVICES += gl-usb150 glinet,gl-usb150 ++endef ++TARGET_DEVICES += glinet_gl-usb150 ++ + define Device/glinet_gl-x300b-common + SOC := qca9531 + DEVICE_VENDOR := GL.iNet +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/01_leds b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +index 27f8ee2..24f03a0 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/01_leds ++++ b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +@@ -10,6 +10,10 @@ case "$board" in + glinet,gl-ar150) + ucidef_set_led_wlan "wlan" "WLAN" "gl-ar150:orange:wlan" "phy0tpt" + ;; ++glinet,gl-usb150) ++ ucidef_set_led_wlan "wlan" "WLAN" "gl-usb150:green:wlan" "phy0tpt" ++ ucidef_set_led_default "power" "POWER" "gl-usb150:green:power" "1" ++ ;; + glinet,gl-ar300m-nand|\ + glinet,gl-ar300m-nor) + ucidef_set_led_netdev "lan" "LAN" "gl-ar300m:green:lan" "eth1" +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/02_network b/target/linux/ath79/nand/base-files/etc/board.d/02_network +index 9be5bef..06b664e 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/02_network ++++ b/target/linux/ath79/nand/base-files/etc/board.d/02_network +@@ -9,6 +9,7 @@ ath79_setup_interfaces() + + case "$board" in + aerohive,hiveap-121|\ ++ glinet,gl-usb150|\ + glinet,gl-e750) + ucidef_set_interface_lan "eth0" + ;; +-- +2.7.4 + diff --git a/patches-21.02.2/0011-add-support-gl-ar750-ar750s.patch b/patches-21.02.2/0011-add-support-gl-ar750-ar750s.patch new file mode 100644 index 0000000..f5bfab5 --- /dev/null +++ b/patches-21.02.2/0011-add-support-gl-ar750-ar750s.patch @@ -0,0 +1,210 @@ +From 19b1dfb78c50442878cd1926d49b00e5ea8829b6 Mon Sep 17 00:00:00 2001 +From: Kaifeng Wei +Date: Sun, 26 Sep 2021 04:58:09 -0700 +Subject: [PATCH] add support gl ar750 ar750s + +--- + target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts | 26 ++++++++++++++++++--- + .../linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi | 27 +++++++++++++++++++--- + target/linux/ath79/image/generic.mk | 2 +- + target/linux/ath79/image/nand.mk | 7 +++++- + .../ath79/nand/base-files/etc/board.d/01_leds | 4 ++++ + .../ath79/nand/base-files/etc/board.d/02_network | 6 +++++ + .../etc/hotplug.d/firmware/11-ath10k-caldata | 2 ++ + 7 files changed, 66 insertions(+), 8 deletions(-) + +diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts b/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts +index 24dc8aa..5ab0340 100644 +--- a/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts ++++ b/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts +@@ -9,6 +9,26 @@ + compatible = "glinet,gl-ar750", "qca,qca9531"; + model = "GL.iNet GL-AR750"; + ++ gl_hw { ++ compatible = "gl-hw-info"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "ar750"; ++ wan = "eth0"; ++ lan = "eth1.1"; ++ switch-button = "gpio-0"; ++ reset-button = "gpio-3"; ++ usb-port = "1-1.2"; ++ factory_data { ++ device_mac = "art"; ++ device_ddns = "art", "0x10"; ++ device_sn_bak = "art", "0x20"; ++ device_sn = "art", "0x30"; ++ country_code = "art", "0x88"; ++ }; ++ }; ++ + aliases { + led-boot = &led_power; + led-failsafe = &led_power; +@@ -40,19 +60,19 @@ + compatible = "gpio-leds"; + + led_power: power { +- label = "white:power"; ++ label = "gl-ar750:white:power"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + wlan2g { +- label = "white:wlan2g"; ++ label = "gl-ar750:white:wlan2g"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + wlan5g { +- label = "white:wlan5g"; ++ label = "gl-ar750:white:wlan5g"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; +diff --git a/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi b/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi +index 9226d37..d46b5ba 100644 +--- a/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi ++++ b/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi +@@ -9,6 +9,27 @@ + compatible = "glinet,gl-ar750s", "qca,qca9563"; + model = "GL.iNet GL-AR750S"; + ++ gl_hw { ++ compatible = "gl-hw-info"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "ar750s"; ++ wan = "eth0.2"; ++ lan = "eth0.1"; ++ switch-button = "gpio-8"; ++ reset-button = "gpio-2"; ++ usb-port = "1-1"; ++ nand; ++ factory_data { ++ device_mac = "art"; ++ device_ddns = "art", "0x10"; ++ device_sn_bak = "art", "0x20"; ++ device_sn = "art", "0x30"; ++ country_code = "art", "0x88"; ++ }; ++ }; ++ + aliases { + led-boot = &led_power; + led-failsafe = &led_power; +@@ -41,19 +62,19 @@ + compatible = "gpio-leds"; + + led_power: power { +- label = "green:power"; ++ label = "gl-ar750s:green:power"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + led_wlan2g: wlan2g { +- label = "green:wlan2g"; ++ label = "gl-ar750s:green:wlan2g"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led_wlan5g: wlan5g { +- label = "green:wlan5g"; ++ label = "gl-ar750s:green:wlan5g"; + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; + }; +diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk +index cf3fce3..d178f43 100644 +--- a/target/linux/ath79/image/generic.mk ++++ b/target/linux/ath79/image/generic.mk +@@ -1163,7 +1163,7 @@ define Device/glinet_gl-ar750 + DEVICE_MODEL := GL-AR750 + DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca9887-ct + IMAGE_SIZE := 16000k +- SUPPORTED_DEVICES += gl-ar750 ++ SUPPORTED_DEVICES += gl-ar750 glinet,gl-ar750 + endef + TARGET_DEVICES += glinet_gl-ar750 + +diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk +index 83ca331..9dd7a5b 100644 +--- a/target/linux/ath79/image/nand.mk ++++ b/target/linux/ath79/image/nand.mk +@@ -215,7 +215,12 @@ define Device/glinet_gl-ar750s-nor-nand + $(Device/glinet_gl-ar750s-common) + DEVICE_VARIANT := NOR/NAND + KERNEL_SIZE := 4096k +- IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata ++ BLOCKSIZE := 128k ++ PAGESIZE := 2048 ++ VID_HDR_OFFSET := 2048 ++ IMAGES := factory.img sysupgrade.tar ++ IMAGE/sysupgrade.tar := sysupgrade-tar | append-gl-metadata ++ IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | append-gl-metadata + SUPPORTED_DEVICES += glinet,gl-ar750s-nor + endef + TARGET_DEVICES += glinet_gl-ar750s-nor-nand +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/01_leds b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +index 24f03a0..9369f15 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/01_leds ++++ b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +@@ -37,6 +37,10 @@ glinet,gl-xe300-nor-nand) + ucidef_set_led_netdev "wan" "WAN" "gl-xe300:green:wan" "eth1" + ucidef_set_led_netdev "3gnet" "LTE" "gl-xe300:green:lte" "wwan0" + ;; ++glinet,gl-ar750) ++ ucidef_set_led_wlan "wlan2g" "WLAN2G" "gl-ar750:white:wlan2g" "phy1tpt" ++ ucidef_set_led_wlan "wlan5g" "WLAN5G" "gl-ar750:white:wlan5g" "phy0tpt" ++ ;; + netgear,wndr3700-v4|\ + netgear,wndr4300|\ + netgear,wndr4300sw|\ +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/02_network b/target/linux/ath79/nand/base-files/etc/board.d/02_network +index 06b664e..0b5a63d 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/02_network ++++ b/target/linux/ath79/nand/base-files/etc/board.d/02_network +@@ -17,6 +17,7 @@ ath79_setup_interfaces() + ucidef_add_switch "switch0" \ + "0@eth0" "1:wan" "2:lan" "3:lan" "4:lan" "5:lan" "6@eth1" + ;; ++ glinet,gl-ar750s|\ + glinet,gl-ar750s-nor|\ + glinet,gl-ar750s-nor-nand) + ucidef_add_switch "switch0" \ +@@ -35,6 +36,11 @@ ath79_setup_interfaces() + glinet,gl-xe300-nor-nand) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ;; ++ glinet,gl-ar750) ++ ucidef_set_interfaces_lan_wan "eth1.1" "eth0" ++ ucidef_add_switch "switch0" \ ++ "0@eth1" "1:lan" "2:lan" ++ ;; + netgear,wndr3700-v4|\ + netgear,wndr4300|\ + netgear,wndr4300sw|\ +diff --git a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +index d5fd3db..3226d4f 100644 +--- a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata ++++ b/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +@@ -13,6 +13,8 @@ case "$FIRMWARE" in + caldata_extract "art" 0x5000 0x844 + ath10k_patch_mac $(mtd_get_mac_binary art 0x12) + ;; ++ glinet,gl-ar750|\ ++ glinet,gl-ar750s|\ + glinet,gl-ar750s-nor|\ + glinet,gl-ar750s-nor-nand) + caldata_extract "art" 0x5000 0x844 +-- +2.7.4 + diff --git a/patches-21.02.2/0012-ath79-add-support-for-gl-x750.patch b/patches-21.02.2/0012-ath79-add-support-for-gl-x750.patch new file mode 100644 index 0000000..c95e811 --- /dev/null +++ b/patches-21.02.2/0012-ath79-add-support-for-gl-x750.patch @@ -0,0 +1,463 @@ +From 4afa87a602f9af8be38494237c4e758009d5c142 Mon Sep 17 00:00:00 2001 +From: "GL.iNet-Hongjian.Zhang" +Date: Tue, 28 Sep 2021 14:19:45 +0800 +Subject: [PATCH] ath79: add support for gl x750 + +--- + .../dts/qca9531_glinet_gl-x750-nor-nand.dts | 25 +++++ + .../ath79/dts/qca9531_glinet_gl-x750-nor.dts | 18 +++ + ...l-x750.dts => qca9531_glinet_gl-x750.dtsi} | 105 ++++++++++++++---- + target/linux/ath79/dts/qca953x.dtsi | 3 +- + .../generic/base-files/etc/board.d/01_leds | 3 - + .../etc/hotplug.d/firmware/11-ath10k-caldata | 3 +- + target/linux/ath79/image/generic.mk | 9 -- + target/linux/ath79/image/nand.mk | 30 ++++- + .../ath79/nand/base-files/etc/board.d/01_leds | 5 + + .../nand/base-files/etc/board.d/02_network | 2 + + .../etc/hotplug.d/firmware/11-ath10k-caldata | 6 +- + .../nand/base-files/lib/upgrade/platform.sh | 6 +- + 12 files changed, 174 insertions(+), 41 deletions(-) + create mode 100644 target/linux/ath79/dts/qca9531_glinet_gl-x750-nor-nand.dts + create mode 100644 target/linux/ath79/dts/qca9531_glinet_gl-x750-nor.dts + rename target/linux/ath79/dts/{qca9531_glinet_gl-x750.dts => qca9531_glinet_gl-x750.dtsi} (51%) + mode change 100644 => 100755 + +diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-x750-nor-nand.dts b/target/linux/ath79/dts/qca9531_glinet_gl-x750-nor-nand.dts +new file mode 100644 +index 0000000000..1926ff8626 +--- /dev/null ++++ b/target/linux/ath79/dts/qca9531_glinet_gl-x750-nor-nand.dts +@@ -0,0 +1,25 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++/dts-v1/; ++ ++#include "qca9531_glinet_gl-x750.dtsi" ++ ++/ { ++ compatible = "glinet,gl-x750-nor-nand", "qca,qca9531"; ++ model = "GL.iNet GL-X750 (NOR/NAND)"; ++}; ++ ++&nor_partitions { ++ partition@60000 { ++ label = "kernel"; ++ reg = <0x060000 0x200000>; ++ }; ++ parition@260000 { ++ label = "nor_reserved"; ++ reg = <0x260000 0xbc0000>; ++ }; ++}; ++ ++&nand_ubi { ++ label = "ubi"; ++}; +diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-x750-nor.dts b/target/linux/ath79/dts/qca9531_glinet_gl-x750-nor.dts +new file mode 100644 +index 0000000000..14be3e13a5 +--- /dev/null ++++ b/target/linux/ath79/dts/qca9531_glinet_gl-x750-nor.dts +@@ -0,0 +1,18 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++/dts-v1/; ++ ++#include "qca9531_glinet_gl-x750.dtsi" ++ ++/ { ++ compatible = "glinet,gl-x750-nor", "qca,qca9531"; ++ model = "GL.iNet GL-X750 (NOR)"; ++}; ++ ++&nor_partitions { ++ partition@60000 { ++ compatible = "denx,uimage"; ++ label = "firmware"; ++ reg = <0x060000 0xfa0000>; ++ }; ++}; +diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts b/target/linux/ath79/dts/qca9531_glinet_gl-x750.dtsi +old mode 100644 +new mode 100755 +similarity index 51% +rename from target/linux/ath79/dts/qca9531_glinet_gl-x750.dts +rename to target/linux/ath79/dts/qca9531_glinet_gl-x750.dtsi +index c755e00033..89a109addc +--- a/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts ++++ b/target/linux/ath79/dts/qca9531_glinet_gl-x750.dtsi +@@ -1,21 +1,43 @@ + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT +- +-#include "qca953x.dtsi" ++/dts-v1/; + + #include + #include + ++#include "qca953x.dtsi" ++ + / { + compatible = "glinet,gl-x750", "qca,qca9531"; + model = "GL.iNet GL-X750"; + ++ gl_hw { ++ compatible = "gl-hw-info"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "x750"; ++ wan = "eth0"; ++ lan = "eth1"; ++ build-in-modem = "1-1.2"; ++ reset-button = "gpio-3"; ++ usb-port = "1-1.3"; ++ factory_data { ++ device_mac = "art"; ++ device_ddns = "art", "0x10"; ++ device_sn_bak = "art", "0x20"; ++ device_sn = "art", "0x30"; ++ country_code = "art", "0x88"; ++ }; ++ }; ++ + keys { +- compatible = "gpio-keys"; ++ compatible = "gpio-keys-polled"; + ++ poll-interval = <20>; + pinctrl-names = "default"; + pinctrl-0 = <&jtag_disable_pins>; + +- reset { ++ button0 { + label = "reset"; + linux,code = ; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; +@@ -26,39 +48,66 @@ + compatible = "gpio-leds"; + + power { +- label = "green:power"; ++ label = "gl-x750:green:power"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + wlan2g { +- label = "green:wlan2g"; ++ label = "gl-x750:green:wlan2g"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + wlan5g { +- label = "green:wlan5g"; ++ label = "gl-x750:green:wlan5g"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + wan { +- label = "green:wan"; ++ label = "gl-x750:green:wan"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + +- 4g { +- label = "green:4g"; ++ lte { ++ label = "gl-x750:green:lte"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + }; ++ ++ gpio-export { ++ compatible = "gpio-export"; ++ ++ gpio_pci_power { ++ gpio-export,name = "pci_power"; ++ gpio-export,output = <0>; ++ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ }; ++ ++ gpio_usb_power { ++ gpio-export,name = "usb_power"; ++ gpio-export,output = <0>; ++ gpios = <&gpio 2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ gpio_ble_reset { ++ //set name as gpio1 to compat 1806 gpio name ++ gpio-export,name = "gpio1"; ++ gpio-export,output = <0>; ++ gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; ++ }; ++ }; + }; + + &pcie0 { + status = "okay"; + }; + ++&uart { ++ status = "okay"; ++}; ++ + &usb0 { + #address-cells = <1>; + #size-cells = <0>; +@@ -76,13 +125,15 @@ + + &spi { + status = "okay"; ++ num-cs = <2>; ++ cs-gpios = <0>, <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + +- partitions { ++ nor_partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; +@@ -103,31 +154,47 @@ + reg = <0x050000 0x010000>; + read-only; + }; ++ }; ++ }; ++ ++ flash_nand: flash@1 { ++ compatible = "spi-nand"; ++ reg = <1>; ++ spi-max-frequency = <25000000>; ++ ++ nand_partitions: partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; + +- partition@60000 { +- compatible = "denx,uimage"; +- label = "firmware"; +- reg = <0x060000 0xfa0000>; ++ nand_ubi: partition@0 { ++ label = "nand_ubi"; ++ reg = <0x000000 0x8000000>; + }; + }; + }; ++ ++}; ++ ++&bootargs { ++ bootargs = "console=null"; + }; + + ð0 { + status = "okay"; +- +- phy-handle = <&swphy4>; +- + mtd-mac-address = <&art 0x0>; ++ phy-handle = <&swphy4>; ++ ifname = "eth0"; + }; + + ð1 { + mtd-mac-address = <&art 0x0>; + mtd-mac-address-increment = <1>; ++ ifname = "eth1"; + }; + + &wmac { + status = "okay"; +- + mtd-cal-data = <&art 0x1000>; ++ mtd-mac-address = <&art 0x1002>; + }; +diff --git a/target/linux/ath79/dts/qca953x.dtsi b/target/linux/ath79/dts/qca953x.dtsi +index 7774d073e7..3bbd7acfd8 100644 +--- a/target/linux/ath79/dts/qca953x.dtsi ++++ b/target/linux/ath79/dts/qca953x.dtsi +@@ -246,8 +246,7 @@ + resets = <&rst 8>; + reset-names = "switch"; + phy-mode = "gmii"; +- qca,phy4-mii-enable; +- qca,mib-poll-interval = <500>; ++ phy4-mii-enable; + + mdio-bus { + #address-cells = <1>; +diff --git a/target/linux/ath79/generic/base-files/etc/board.d/01_leds b/target/linux/ath79/generic/base-files/etc/board.d/01_leds +index f3690897ee..0782f9c980 100755 +--- a/target/linux/ath79/generic/base-files/etc/board.d/01_leds ++++ b/target/linux/ath79/generic/base-files/etc/board.d/01_leds +@@ -211,9 +211,6 @@ qxwlan,e750a-v4-16m) + ucidef_set_led_switch "lan" "LAN" "green:lan" "switch0" "0x02" + ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" + ;; +-glinet,gl-x750) +- ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" +- ;; + hak5,lan-turtle) + ucidef_set_led_netdev "wan" "WAN" "orange:system" "eth1" + ;; +diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +index 783895525b..cbca18fef4 100644 +--- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata ++++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +@@ -12,8 +12,7 @@ case "$FIRMWARE" in + case $board in + allnet,all-wap02860ac|\ + engenius,eap1200h|\ +- engenius,enstationac-v1|\ +- glinet,gl-x750) ++ engenius,enstationac-v1) + caldata_extract "art" 0x5000 0x844 + ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) +2) + ;; +diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk +index d178f437ca..7ea12da0b2 100644 +--- a/target/linux/ath79/image/generic.mk ++++ b/target/linux/ath79/image/generic.mk +@@ -1167,15 +1167,6 @@ define Device/glinet_gl-ar750 + endef + TARGET_DEVICES += glinet_gl-ar750 + +-define Device/glinet_gl-x750 +- SOC := qca9531 +- DEVICE_VENDOR := GL.iNet +- DEVICE_MODEL := GL-X750 +- DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca9887-ct +- IMAGE_SIZE := 16000k +-endef +-TARGET_DEVICES += glinet_gl-x750 +- + define Device/hak5_lan-turtle + $(Device/tplink-16mlzma) + SOC := ar9331 +diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk +index 9dd7a5b6ff..4831a13ab9 100644 +--- a/target/linux/ath79/image/nand.mk ++++ b/target/linux/ath79/image/nand.mk +@@ -153,7 +153,7 @@ TARGET_DEVICES += glinet_gl-ar300m-nor + + define Device/glinet_gl-mifi + SOC := ar9331 +- DEVICE_VENDOR := GL.iNET ++ DEVICE_VENDOR := GL.iNet + DEVICE_MODEL := GL-MIFI + DEVICE_PACKAGES := kmod-usb-chipidea2 + IMAGE_SIZE := 16000k +@@ -202,6 +202,34 @@ define Device/glinet_gl-xe300-iot + endef + TARGET_DEVICES += glinet_gl-xe300-iot + ++define Device/glinet_gl-x750-common ++ SOC := qca9531 ++ DEVICE_VENDOR := GL.iNet ++ DEVICE_MODEL := GL-X750 ++ DEVICE_PACKAGES := kmod-usb2 kmod-ath10k ath10k-firmware-qca9887 block-mount PCI_SUPPORT kmod-usb-storage ++ SUPPORTED_DEVICES += gl-x750 glinet,gl-x750 ++endef ++ ++define Device/glinet_gl-x750-nor ++ $(Device/glinet_gl-x750-common) ++ DEVICE_VARIANT := NOR ++ IMAGE_SIZE := 16000k ++endef ++TARGET_DEVICES += glinet_gl-x750-nor ++ ++define Device/glinet_gl-x750-nor-nand ++ $(Device/glinet_gl-x750-common) ++ DEVICE_VARIANT := NOR/NAND ++ KERNEL_SIZE := 4096k ++ BLOCKSIZE := 128k ++ PAGESIZE := 2048 ++ VID_HDR_OFFSET := 2048 ++ IMAGES := factory.img sysupgrade.tar ++ IMAGE/sysupgrade.tar := sysupgrade-tar | append-gl-metadata ++ IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | append-gl-metadata ++endef ++TARGET_DEVICES += glinet_gl-x750-nor-nand ++ + define Device/glinet_gl-ar750s-common + SOC := qca9563 + DEVICE_VENDOR := GL.iNet +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/01_leds b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +index 9369f15f89..d9917bb3d2 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/01_leds ++++ b/target/linux/ath79/nand/base-files/etc/board.d/01_leds +@@ -41,6 +41,11 @@ glinet,gl-ar750) + ucidef_set_led_wlan "wlan2g" "WLAN2G" "gl-ar750:white:wlan2g" "phy1tpt" + ucidef_set_led_wlan "wlan5g" "WLAN5G" "gl-ar750:white:wlan5g" "phy0tpt" + ;; ++glinet,gl-x750-nor|\ ++glinet,gl-x750-nor-nand) ++ ucidef_set_led_netdev "wan" "WAN" "gl-x750:green:wan" "eth0" ++ ucidef_set_led_netdev "3gnet" "LTE" "gl-x750:green:lte" "wwan0" ++ ;; + netgear,wndr3700-v4|\ + netgear,wndr4300|\ + netgear,wndr4300sw|\ +diff --git a/target/linux/ath79/nand/base-files/etc/board.d/02_network b/target/linux/ath79/nand/base-files/etc/board.d/02_network +index 0b5a63d4f5..5912a4504a 100755 +--- a/target/linux/ath79/nand/base-files/etc/board.d/02_network ++++ b/target/linux/ath79/nand/base-files/etc/board.d/02_network +@@ -27,6 +27,8 @@ ath79_setup_interfaces() + glinet,gl-ar300m-nand|\ + glinet,gl-x300b-nor|\ + glinet,gl-x300b-nor-nand|\ ++ glinet,gl-x750-nor|\ ++ glinet,gl-x750-nor-nand|\ + glinet,gl-ar150|\ + glinet,gl-mifi) + ucidef_set_interfaces_lan_wan "eth1" "eth0" +diff --git a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +index 3226d4f7b1..c1c1c18500 100644 +--- a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata ++++ b/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +@@ -14,12 +14,16 @@ case "$FIRMWARE" in + ath10k_patch_mac $(mtd_get_mac_binary art 0x12) + ;; + glinet,gl-ar750|\ +- glinet,gl-ar750s|\ + glinet,gl-ar750s-nor|\ + glinet,gl-ar750s-nor-nand) + caldata_extract "art" 0x5000 0x844 + ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) +1) + ;; ++ glinet,gl-x750-nor|\ ++ glinet,gl-x750-nor-nand) ++ caldata_extract "art" 0x5000 0x844 ++ ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) +3) ++ ;; + zyxel,nbg6716) + caldata_extract "art" 0x5000 0x844 + ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) +1) +diff --git a/target/linux/ath79/nand/base-files/lib/upgrade/platform.sh b/target/linux/ath79/nand/base-files/lib/upgrade/platform.sh +index c9b336898e..21951ceba2 100644 +--- a/target/linux/ath79/nand/base-files/lib/upgrade/platform.sh ++++ b/target/linux/ath79/nand/base-files/lib/upgrade/platform.sh +@@ -18,10 +18,8 @@ platform_do_upgrade() { + glinet,gl-ar300m-nor) + glinet_nand_nor_do_upgrade "$1" + ;; +- glinet,gl-ar750s-nor|\ +- glinet,gl-ar750s-nor-nand) +- nand_nor_do_upgrade "$1" +- ;; ++ glinet,gl-x750-nor-nand|\ ++ glinet,gl-ar750s-nor-nand|\ + glinet,gl-xe300-iot|\ + glinet,gl-xe300-nor-nand) + nand_nor_do_upgrade "$1" +-- +2.17.1 +