mirror of
https://github.com/FUjr/gl-infra-builder.git
synced 2025-12-16 17:15:08 +00:00
patches-19.x: fix i2c-mt7621 + leds-et6326
Signed-off-by: Jianhui Zhao <jianhui.zhao@gl-inet.com>
This commit is contained in:
Jianhui Zhao
parent
cc89dad35f
commit
e99086d61d
@ -1,4 +1,4 @@
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From 73671e18eda8b4ad8db0c42341c1318c18e2fee6 Mon Sep 17 00:00:00 2001
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From 06fb018c751e293a1c29a066e391c206a2224ff4 Mon Sep 17 00:00:00 2001
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From: Jianhui Zhao <jianhui.zhao@gl-inet.com>
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Date: Sun, 26 Sep 2021 14:37:26 +0800
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Subject: [PATCH] target/ramips: add et6326 led driver for GL-MT1300
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@ -7,10 +7,11 @@ Signed-off-by: Jianhui Zhao <jianhui.zhao@gl-inet.com>
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---
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package/kernel/leds-et6326/Makefile | 40 ++
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package/kernel/leds-et6326/src/Makefile | 1 +
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package/kernel/leds-et6326/src/leds-et6326.c | 501 +++++++++++++++++++
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target/linux/ramips/dts/GL-MT1300.dts | 45 +-
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package/kernel/leds-et6326/src/leds-et6326.c | 501 ++++++++++++++++++
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target/linux/ramips/dts/GL-MT1300.dts | 46 +-
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target/linux/ramips/image/mt7621.mk | 2 +-
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5 files changed, 571 insertions(+), 18 deletions(-)
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.../0045-i2c-add-mt7621-driver.patch | 464 +++++++---------
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6 files changed, 766 insertions(+), 288 deletions(-)
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create mode 100644 package/kernel/leds-et6326/Makefile
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create mode 100644 package/kernel/leds-et6326/src/Makefile
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create mode 100644 package/kernel/leds-et6326/src/leds-et6326.c
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@ -576,7 +577,7 @@ index 0000000000..1326e20994
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+MODULE_DESCRIPTION("ET6326 LED driver");
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+MODULE_LICENSE("GPL v2");
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diff --git a/target/linux/ramips/dts/GL-MT1300.dts b/target/linux/ramips/dts/GL-MT1300.dts
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index 07f9b6986e..18dbb44ace 100755
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index 07f9b6986e..491238a886 100755
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--- a/target/linux/ramips/dts/GL-MT1300.dts
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+++ b/target/linux/ramips/dts/GL-MT1300.dts
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@@ -9,6 +9,13 @@
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@ -606,20 +607,14 @@ index 07f9b6986e..18dbb44ace 100755
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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@@ -56,17 +57,27 @@
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@@ -55,20 +56,6 @@
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linux,code = <BTN_0>;
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};
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};
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-
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- leds {
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- compatible = "gpio-leds";
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+ i2c-gpio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ compatible = "i2c-gpio";
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+ gpios = <&gpio0 3 GPIO_ACTIVE_HIGH &gpio0 4 GPIO_ACTIVE_HIGH>;
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+ i2c-gpio,delay-us = <10>;
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-
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- led_run: blue {
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- label = "gl-mt1300:blue";
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- gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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@ -628,6 +623,19 @@ index 07f9b6986e..18dbb44ace 100755
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- white {
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- label = "gl-mt1300:white";
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- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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- };
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- };
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};
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&sdhci {
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@@ -151,3 +138,22 @@
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};
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};
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};
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+
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+&i2c {
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+ status = "okay";
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+
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+ leds@30 {
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+ compatible = "etek,et6326";
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+ reg = <0x30>;
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@ -641,20 +649,10 @@ index 07f9b6986e..18dbb44ace 100755
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+ channel = <1>;
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+ label = "gl-mt1300:white";
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+ };
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};
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};
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};
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@@ -146,7 +157,7 @@
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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- ralink,group = "wdt", "rgmii2", "jtag", "mdio";
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+ ralink,group = "wdt", "rgmii2", "jtag", "mdio", "i2c";
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ralink,function = "gpio";
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};
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};
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+ };
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+};
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diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk
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index 708a606b98..dfadd69f93 100644
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index 708a606b98..b9c819b17e 100644
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--- a/target/linux/ramips/image/mt7621.mk
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+++ b/target/linux/ramips/image/mt7621.mk
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@@ -210,7 +210,7 @@ define Device/gl-mt1300
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@ -662,10 +660,635 @@ index 708a606b98..dfadd69f93 100644
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DEVICE_PACKAGES := \
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kmod-ata-core kmod-ata-ahci kmod-mt76x2 kmod-mt7603 kmod-usb3 \
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- kmod-usb-ledtrig-usbport wpad-basic
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+ kmod-usb-ledtrig-usbport wpad-basic kmod-i2c-gpio kmod-leds-et6326
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+ kmod-usb-ledtrig-usbport wpad-basic kmod-leds-et6326
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IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-gl-metadata | check-size $$$$(IMAGE_SIZE)
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endef
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TARGET_DEVICES += gl-mt1300
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diff --git a/target/linux/ramips/patches-4.14/0045-i2c-add-mt7621-driver.patch b/target/linux/ramips/patches-4.14/0045-i2c-add-mt7621-driver.patch
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index a848085520..c479b61b62 100644
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--- a/target/linux/ramips/patches-4.14/0045-i2c-add-mt7621-driver.patch
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+++ b/target/linux/ramips/patches-4.14/0045-i2c-add-mt7621-driver.patch
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@@ -37,300 +37,248 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
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--- /dev/null
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+++ b/drivers/i2c/busses/i2c-mt7621.c
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-@@ -0,0 +1,433 @@
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+@@ -0,0 +1,363 @@
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++// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * drivers/i2c/busses/i2c-mt7621.c
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+ *
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+ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
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+ * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
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++ * Copyright (C) 2018 Jan Breuer <jan.breuer@jaybee.cz>
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+ *
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+ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
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+ * (C) 2014 Sittisak <sittisaks@hotmail.com>
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-+ *
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-+ * This software is licensed under the terms of the GNU General Public
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-+ * License version 2, as published by the Free Software Foundation, and
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-+ * may be copied, distributed, and modified under those terms.
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-+ *
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-+ * This program is distributed in the hope that it will be useful,
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-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-+ * GNU General Public License for more details.
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-+ *
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+ */
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+
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-+#include <linux/interrupt.h>
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-+#include <linux/kernel.h>
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-+#include <linux/module.h>
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-+#include <linux/reset.h>
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++#include <linux/clk.h>
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+#include <linux/delay.h>
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-+#include <linux/slab.h>
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-+#include <linux/init.h>
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-+#include <linux/errno.h>
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-+#include <linux/platform_device.h>
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-+#include <linux/of_platform.h>
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+#include <linux/i2c.h>
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+#include <linux/io.h>
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-+#include <linux/err.h>
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-+#include <linux/clk.h>
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++#include <linux/iopoll.h>
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++#include <linux/module.h>
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++#include <linux/of_platform.h>
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++#include <linux/reset.h>
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+
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-+#define REG_SM0CFG0 0x08
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-+#define REG_SM0DOUT 0x10
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-+#define REG_SM0DIN 0x14
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-+#define REG_SM0ST 0x18
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-+#define REG_SM0AUTO 0x1C
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-+#define REG_SM0CFG1 0x20
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-+#define REG_SM0CFG2 0x28
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-+#define REG_SM0CTL0 0x40
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-+#define REG_SM0CTL1 0x44
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-+#define REG_SM0D0 0x50
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-+#define REG_SM0D1 0x54
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-+#define REG_PINTEN 0x5C
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-+#define REG_PINTST 0x60
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-+#define REG_PINTCL 0x64
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-+
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-+/* REG_SM0CFG0 */
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-+#define I2C_DEVADDR_MASK 0x7f
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-+
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-+/* REG_SM0ST */
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-+#define I2C_DATARDY BIT(2)
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-+#define I2C_SDOEMPTY BIT(1)
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-+#define I2C_BUSY BIT(0)
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-+
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-+/* REG_SM0AUTO */
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-+#define READ_CMD BIT(0)
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-+
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-+/* REG_SM0CFG1 */
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-+#define BYTECNT_MAX 64
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-+#define SET_BYTECNT(x) (x - 1)
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-+
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-+/* REG_SM0CFG2 */
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-+#define AUTOMODE_EN BIT(0)
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-+
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-+/* REG_SM0CTL0 */
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-+#define ODRAIN_HIGH_SM0 BIT(31)
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-+#define VSYNC_SHIFT 28
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-+#define VSYNC_MASK 0x3
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-+#define VSYNC_PULSE (0x1 << VSYNC_SHIFT)
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-+#define VSYNC_RISING (0x2 << VSYNC_SHIFT)
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-+#define CLK_DIV_SHIFT 16
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-+#define CLK_DIV_MASK 0xfff
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-+#define DEG_CNT_SHIFT 8
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-+#define DEG_CNT_MASK 0xff
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-+#define WAIT_HIGH BIT(6)
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-+#define DEG_EN BIT(5)
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-+#define CS_STATUA BIT(4)
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-+#define SCL_STATUS BIT(3)
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-+#define SDA_STATUS BIT(2)
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-+#define SM0_EN BIT(1)
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-+#define SCL_STRECH BIT(0)
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-+
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-+/* REG_SM0CTL1 */
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-+#define ACK_SHIFT 16
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-+#define ACK_MASK 0xff
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-+#define PGLEN_SHIFT 8
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-+#define PGLEN_MASK 0x7
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-+#define SM0_MODE_SHIFT 4
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-+#define SM0_MODE_MASK 0x7
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-+#define SM0_MODE_START 0x1
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-+#define SM0_MODE_WRITE 0x2
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-+#define SM0_MODE_STOP 0x3
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-+#define SM0_MODE_READ_NACK 0x4
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-+#define SM0_MODE_READ_ACK 0x5
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-+#define SM0_TRI_BUSY BIT(0)
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-+
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-+/* timeout waiting for I2C devices to respond (clock streching) */
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-+#define TIMEOUT_MS 1000
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-+#define DELAY_INTERVAL_US 100
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++#define REG_SM0CFG2_REG 0x28
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++#define REG_SM0CTL0_REG 0x40
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++#define REG_SM0CTL1_REG 0x44
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++#define REG_SM0D0_REG 0x50
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++#define REG_SM0D1_REG 0x54
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++#define REG_PINTEN_REG 0x5c
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++#define REG_PINTST_REG 0x60
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++#define REG_PINTCL_REG 0x64
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++
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++/* REG_SM0CFG2_REG */
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++#define SM0CFG2_IS_AUTOMODE BIT(0)
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++
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++/* REG_SM0CTL0_REG */
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++#define SM0CTL0_ODRAIN BIT(31)
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++#define SM0CTL0_CLK_DIV_MASK (0x7ff << 16)
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++#define SM0CTL0_CLK_DIV_MAX 0x7ff
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++#define SM0CTL0_CS_STATUS BIT(4)
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++#define SM0CTL0_SCL_STATE BIT(3)
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++#define SM0CTL0_SDA_STATE BIT(2)
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++#define SM0CTL0_EN BIT(1)
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++#define SM0CTL0_SCL_STRETCH BIT(0)
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++
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++/* REG_SM0CTL1_REG */
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++#define SM0CTL1_ACK_MASK (0xff << 16)
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++#define SM0CTL1_PGLEN_MASK (0x7 << 8)
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++#define SM0CTL1_PGLEN(x) ((((x) - 1) << 8) & SM0CTL1_PGLEN_MASK)
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++#define SM0CTL1_READ (5 << 4)
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++#define SM0CTL1_READ_LAST (4 << 4)
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++#define SM0CTL1_STOP (3 << 4)
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++#define SM0CTL1_WRITE (2 << 4)
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++#define SM0CTL1_START (1 << 4)
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++#define SM0CTL1_MODE_MASK (0x7 << 4)
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++#define SM0CTL1_TRI BIT(0)
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++
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++/* timeout waiting for I2C devices to respond */
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++#define TIMEOUT_MS 1000
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+
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+struct mtk_i2c {
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+ void __iomem *base;
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-+ struct clk *clk;
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+ struct device *dev;
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+ struct i2c_adapter adap;
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-+ u32 cur_clk;
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++ u32 bus_freq;
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+ u32 clk_div;
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+ u32 flags;
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++ struct clk *clk;
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+};
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+
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-+static void mtk_i2c_w32(struct mtk_i2c *i2c, u32 val, unsigned reg)
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-+{
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-+ iowrite32(val, i2c->base + reg);
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-+}
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-+
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-+static u32 mtk_i2c_r32(struct mtk_i2c *i2c, unsigned reg)
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-+{
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-+ return ioread32(i2c->base + reg);
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-+}
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-+
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-+static int poll_down_timeout(void __iomem *addr, u32 mask)
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-+{
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-+ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
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-+
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-+ do {
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-+ if (!(readl_relaxed(addr) & mask))
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-+ return 0;
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-+
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-+ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
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-+ } while (time_before(jiffies, timeout));
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-+
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-+ return (readl_relaxed(addr) & mask) ? -EAGAIN : 0;
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-+}
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-+
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+static int mtk_i2c_wait_idle(struct mtk_i2c *i2c)
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+{
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+ int ret;
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++ u32 val;
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+
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-+ ret = poll_down_timeout(i2c->base + REG_SM0ST, I2C_BUSY);
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-+ if (ret < 0)
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++ ret = readl_relaxed_poll_timeout(i2c->base + REG_SM0CTL1_REG,
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++ val, !(val & SM0CTL1_TRI),
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++ 10, TIMEOUT_MS * 1000);
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++ if (ret)
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+ dev_dbg(i2c->dev, "idle err(%d)\n", ret);
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+
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+ return ret;
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+}
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+
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-+static int poll_up_timeout(void __iomem *addr, u32 mask)
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++static void mtk_i2c_reset(struct mtk_i2c *i2c)
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+{
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-+ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
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-+ u32 status;
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-+
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-+ do {
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-+ status = readl_relaxed(addr);
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-+ if (status & mask)
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-+ return 0;
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-+ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
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-+ } while (time_before(jiffies, timeout));
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++ int ret;
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+
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-+ return -ETIMEDOUT;
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++ ret = device_reset(i2c->adap.dev.parent);
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++ if (ret)
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++ dev_err(i2c->dev, "I2C reset failed!\n");
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++
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++ /*
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++ * Don't set SM0CTL0_ODRAIN as its bit meaning is inverted. To
|
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++ * configure open-drain mode, this bit needs to be cleared.
|
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++ */
|
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++ iowrite32(((i2c->clk_div << 16) & SM0CTL0_CLK_DIV_MASK) | SM0CTL0_EN |
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++ SM0CTL0_SCL_STRETCH, i2c->base + REG_SM0CTL0_REG);
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++ iowrite32(0, i2c->base + REG_SM0CFG2_REG);
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+}
|
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+
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-+static int mtk_i2c_wait_rx_done(struct mtk_i2c *i2c)
|
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++static void mtk_i2c_dump_reg(struct mtk_i2c *i2c)
|
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+{
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-+ int ret;
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-+
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-+ ret = poll_up_timeout(i2c->base + REG_SM0ST, I2C_DATARDY);
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-+ if (ret < 0)
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-+ dev_dbg(i2c->dev, "rx err(%d)\n", ret);
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-+
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-+ return ret;
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++ dev_dbg(i2c->dev,
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++ "SM0CFG2 %08x, SM0CTL0 %08x, SM0CTL1 %08x, SM0D0 %08x, SM0D1 %08x\n",
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++ ioread32(i2c->base + REG_SM0CFG2_REG),
|
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++ ioread32(i2c->base + REG_SM0CTL0_REG),
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++ ioread32(i2c->base + REG_SM0CTL1_REG),
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++ ioread32(i2c->base + REG_SM0D0_REG),
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++ ioread32(i2c->base + REG_SM0D1_REG));
|
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+}
|
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+
|
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-+static int mtk_i2c_wait_tx_done(struct mtk_i2c *i2c)
|
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++static int mtk_i2c_check_ack(struct mtk_i2c *i2c, u32 expected)
|
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+{
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-+ int ret;
|
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++ u32 ack = readl_relaxed(i2c->base + REG_SM0CTL1_REG);
|
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++ u32 ack_expected = (expected << 16) & SM0CTL1_ACK_MASK;
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+
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-+ ret = poll_up_timeout(i2c->base + REG_SM0ST, I2C_SDOEMPTY);
|
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-+ if (ret < 0)
|
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-+ dev_dbg(i2c->dev, "tx err(%d)\n", ret);
|
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-+
|
||||
-+ return ret;
|
||||
++ return ((ack & ack_expected) == ack_expected) ? 0 : -ENXIO;
|
||||
+}
|
||||
+
|
||||
-+static void mtk_i2c_reset(struct mtk_i2c *i2c)
|
||||
++static int mtk_i2c_master_start(struct mtk_i2c *i2c)
|
||||
+{
|
||||
-+ u32 reg;
|
||||
-+ device_reset(i2c->adap.dev.parent);
|
||||
-+ barrier();
|
||||
-+
|
||||
-+ /* ctrl0 */
|
||||
-+ reg = ODRAIN_HIGH_SM0 | VSYNC_PULSE | (i2c->clk_div << CLK_DIV_SHIFT) |
|
||||
-+ WAIT_HIGH | SM0_EN;
|
||||
-+ mtk_i2c_w32(i2c, reg, REG_SM0CTL0);
|
||||
++ iowrite32(SM0CTL1_START | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG);
|
||||
++ return mtk_i2c_wait_idle(i2c);
|
||||
++}
|
||||
+
|
||||
-+ /* auto mode */
|
||||
-+ mtk_i2c_w32(i2c, AUTOMODE_EN, REG_SM0CFG2);
|
||||
++static int mtk_i2c_master_stop(struct mtk_i2c *i2c)
|
||||
++{
|
||||
++ iowrite32(SM0CTL1_STOP | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG);
|
||||
++ return mtk_i2c_wait_idle(i2c);
|
||||
+}
|
||||
+
|
||||
-+static void mtk_i2c_dump_reg(struct mtk_i2c *i2c)
|
||||
++static int mtk_i2c_master_cmd(struct mtk_i2c *i2c, u32 cmd, int page_len)
|
||||
+{
|
||||
-+ dev_dbg(i2c->dev, "cfg0 %08x, dout %08x, din %08x, " \
|
||||
-+ "status %08x, auto %08x, cfg1 %08x, " \
|
||||
-+ "cfg2 %08x, ctl0 %08x, ctl1 %08x\n",
|
||||
-+ mtk_i2c_r32(i2c, REG_SM0CFG0),
|
||||
-+ mtk_i2c_r32(i2c, REG_SM0DOUT),
|
||||
-+ mtk_i2c_r32(i2c, REG_SM0DIN),
|
||||
-+ mtk_i2c_r32(i2c, REG_SM0ST),
|
||||
-+ mtk_i2c_r32(i2c, REG_SM0AUTO),
|
||||
-+ mtk_i2c_r32(i2c, REG_SM0CFG1),
|
||||
-+ mtk_i2c_r32(i2c, REG_SM0CFG2),
|
||||
-+ mtk_i2c_r32(i2c, REG_SM0CTL0),
|
||||
-+ mtk_i2c_r32(i2c, REG_SM0CTL1));
|
||||
++ iowrite32(cmd | SM0CTL1_TRI | SM0CTL1_PGLEN(page_len),
|
||||
++ i2c->base + REG_SM0CTL1_REG);
|
||||
++ return mtk_i2c_wait_idle(i2c);
|
||||
+}
|
||||
+
|
||||
+static int mtk_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
|
||||
-+ int num)
|
||||
++ int num)
|
||||
+{
|
||||
+ struct mtk_i2c *i2c;
|
||||
+ struct i2c_msg *pmsg;
|
||||
-+ int i, j, ret;
|
||||
++ u16 addr;
|
||||
++ int i, j, ret, len, page_len;
|
||||
+ u32 cmd;
|
||||
++ u32 data[2];
|
||||
+
|
||||
+ i2c = i2c_get_adapdata(adap);
|
||||
+
|
||||
+ for (i = 0; i < num; i++) {
|
||||
+ pmsg = &msgs[i];
|
||||
-+ cmd = 0;
|
||||
+
|
||||
-+ dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x\n",
|
||||
-+ pmsg->addr, pmsg->len, pmsg->flags);
|
||||
++ if (pmsg->flags & I2C_M_NOSTART)
|
||||
++ goto nostart;
|
||||
+
|
||||
+ /* wait hardware idle */
|
||||
-+ if ((ret = mtk_i2c_wait_idle(i2c)))
|
||||
++ ret = mtk_i2c_wait_idle(i2c);
|
||||
++ if (ret)
|
||||
++ goto err_timeout;
|
||||
++
|
||||
++ /* start sequence */
|
||||
++ ret = mtk_i2c_master_start(i2c);
|
||||
++ if (ret)
|
||||
+ goto err_timeout;
|
||||
+
|
||||
++ /* write address */
|
||||
+ if (pmsg->flags & I2C_M_TEN) {
|
||||
-+ dev_dbg(i2c->dev, "10 bits addr not supported\n");
|
||||
-+ return -EINVAL;
|
||||
++ /* 10 bits address */
|
||||
++ addr = 0xf0 | ((pmsg->addr >> 7) & 0x06);
|
||||
++ addr |= (pmsg->addr & 0xff) << 8;
|
||||
++ if (pmsg->flags & I2C_M_RD)
|
||||
++ addr |= 1;
|
||||
++ iowrite32(addr, i2c->base + REG_SM0D0_REG);
|
||||
++ ret = mtk_i2c_master_cmd(i2c, SM0CTL1_WRITE, 2);
|
||||
++ if (ret)
|
||||
++ goto err_timeout;
|
||||
+ } else {
|
||||
+ /* 7 bits address */
|
||||
-+ mtk_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,
|
||||
-+ REG_SM0CFG0);
|
||||
++ addr = i2c_8bit_addr_from_msg(pmsg);
|
||||
++ if (pmsg->flags & I2C_M_REV_DIR_ADDR)
|
||||
++ addr ^= 1;
|
||||
++ iowrite32(addr, i2c->base + REG_SM0D0_REG);
|
||||
++ ret = mtk_i2c_master_cmd(i2c, SM0CTL1_WRITE, 1);
|
||||
++ if (ret)
|
||||
++ goto err_timeout;
|
||||
+ }
|
||||
+
|
||||
-+ /* buffer length */
|
||||
-+ if (pmsg->len == 0) {
|
||||
-+ dev_dbg(i2c->dev, "length is 0\n");
|
||||
-+ return -EINVAL;
|
||||
-+ } else
|
||||
-+ mtk_i2c_w32(i2c, SET_BYTECNT(pmsg->len),
|
||||
-+ REG_SM0CFG1);
|
||||
-+
|
||||
-+ j = 0;
|
||||
-+ if (pmsg->flags & I2C_M_RD) {
|
||||
-+ cmd |= READ_CMD;
|
||||
-+ /* start transfer */
|
||||
-+ barrier();
|
||||
-+ mtk_i2c_w32(i2c, cmd, REG_SM0AUTO);
|
||||
-+ do {
|
||||
-+ /* wait */
|
||||
-+ if ((ret = mtk_i2c_wait_rx_done(i2c)))
|
||||
-+ goto err_timeout;
|
||||
-+ /* read data */
|
||||
-+ if (pmsg->len)
|
||||
-+ pmsg->buf[j] = mtk_i2c_r32(i2c,
|
||||
-+ REG_SM0DIN);
|
||||
-+ j++;
|
||||
-+ } while (j < pmsg->len);
|
||||
-+ } else {
|
||||
-+ do {
|
||||
-+ /* write data */
|
||||
-+ if (pmsg->len)
|
||||
-+ mtk_i2c_w32(i2c, pmsg->buf[j],
|
||||
-+ REG_SM0DOUT);
|
||||
-+ /* start transfer */
|
||||
-+ if (j == 0) {
|
||||
-+ barrier();
|
||||
-+ mtk_i2c_w32(i2c, cmd, REG_SM0AUTO);
|
||||
++ /* check address ACK */
|
||||
++ if (!(pmsg->flags & I2C_M_IGNORE_NAK)) {
|
||||
++ ret = mtk_i2c_check_ack(i2c, BIT(0));
|
||||
++ if (ret)
|
||||
++ goto err_ack;
|
||||
++ }
|
||||
++
|
||||
++nostart:
|
||||
++ /* transfer data */
|
||||
++ for (len = pmsg->len, j = 0; len > 0; len -= 8, j += 8) {
|
||||
++ page_len = (len >= 8) ? 8 : len;
|
||||
++
|
||||
++ if (pmsg->flags & I2C_M_RD) {
|
||||
++ cmd = (len > 8) ?
|
||||
++ SM0CTL1_READ : SM0CTL1_READ_LAST;
|
||||
++ } else {
|
||||
++ memcpy(data, &pmsg->buf[j], page_len);
|
||||
++ iowrite32(data[0], i2c->base + REG_SM0D0_REG);
|
||||
++ iowrite32(data[1], i2c->base + REG_SM0D1_REG);
|
||||
++ cmd = SM0CTL1_WRITE;
|
||||
++ }
|
||||
++
|
||||
++ ret = mtk_i2c_master_cmd(i2c, cmd, page_len);
|
||||
++ if (ret)
|
||||
++ goto err_timeout;
|
||||
++
|
||||
++ if (pmsg->flags & I2C_M_RD) {
|
||||
++ data[0] = ioread32(i2c->base + REG_SM0D0_REG);
|
||||
++ data[1] = ioread32(i2c->base + REG_SM0D1_REG);
|
||||
++ memcpy(&pmsg->buf[j], data, page_len);
|
||||
++ } else {
|
||||
++ if (!(pmsg->flags & I2C_M_IGNORE_NAK)) {
|
||||
++ ret = mtk_i2c_check_ack(i2c,
|
||||
++ (1 << page_len)
|
||||
++ - 1);
|
||||
++ if (ret)
|
||||
++ goto err_ack;
|
||||
+ }
|
||||
-+ /* wait */
|
||||
-+ if ((ret = mtk_i2c_wait_tx_done(i2c)))
|
||||
-+ goto err_timeout;
|
||||
-+ j++;
|
||||
-+ } while (j < pmsg->len);
|
||||
++ }
|
||||
+ }
|
||||
+ }
|
||||
++
|
||||
++ ret = mtk_i2c_master_stop(i2c);
|
||||
++ if (ret)
|
||||
++ goto err_timeout;
|
||||
++
|
||||
+ /* the return value is number of executed messages */
|
||||
-+ ret = i;
|
||||
++ return i;
|
||||
+
|
||||
-+ return ret;
|
||||
++err_ack:
|
||||
++ ret = mtk_i2c_master_stop(i2c);
|
||||
++ if (ret)
|
||||
++ goto err_timeout;
|
||||
++ return -ENXIO;
|
||||
+
|
||||
+err_timeout:
|
||||
+ mtk_i2c_dump_reg(i2c);
|
||||
@@ -340,7 +288,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
+
|
||||
+static u32 mtk_i2c_func(struct i2c_adapter *a)
|
||||
+{
|
||||
-+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
|
||||
++ I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING;
|
||||
+}
|
||||
+
|
||||
+static const struct i2c_algorithm mtk_i2c_algo = {
|
||||
@@ -355,16 +304,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
+
|
||||
+MODULE_DEVICE_TABLE(of, i2c_mtk_dt_ids);
|
||||
+
|
||||
-+static struct i2c_adapter_quirks mtk_i2c_quirks = {
|
||||
-+ .max_write_len = BYTECNT_MAX,
|
||||
-+ .max_read_len = BYTECNT_MAX,
|
||||
-+};
|
||||
-+
|
||||
+static void mtk_i2c_init(struct mtk_i2c *i2c)
|
||||
+{
|
||||
-+ i2c->clk_div = clk_get_rate(i2c->clk) / i2c->cur_clk;
|
||||
-+ if (i2c->clk_div > CLK_DIV_MASK)
|
||||
-+ i2c->clk_div = CLK_DIV_MASK;
|
||||
++ i2c->clk_div = clk_get_rate(i2c->clk) / i2c->bus_freq - 1;
|
||||
++ if (i2c->clk_div < 99)
|
||||
++ i2c->clk_div = 99;
|
||||
++ if (i2c->clk_div > SM0CTL0_CLK_DIV_MAX)
|
||||
++ i2c->clk_div = SM0CTL0_CLK_DIV_MAX;
|
||||
+
|
||||
+ mtk_i2c_reset(i2c);
|
||||
+}
|
||||
@@ -374,22 +320,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
+ struct resource *res;
|
||||
+ struct mtk_i2c *i2c;
|
||||
+ struct i2c_adapter *adap;
|
||||
-+ const struct of_device_id *match;
|
||||
+ int ret;
|
||||
+
|
||||
-+ match = of_match_device(i2c_mtk_dt_ids, &pdev->dev);
|
||||
-+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
-+ if (!res) {
|
||||
-+ dev_err(&pdev->dev, "no memory resource found\n");
|
||||
-+ return -ENODEV;
|
||||
-+ }
|
||||
+
|
||||
+ i2c = devm_kzalloc(&pdev->dev, sizeof(struct mtk_i2c), GFP_KERNEL);
|
||||
-+ if (!i2c) {
|
||||
-+ dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
|
||||
++ if (!i2c)
|
||||
+ return -ENOMEM;
|
||||
-+ }
|
||||
+
|
||||
+ i2c->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(i2c->base))
|
||||
@@ -398,39 +335,43 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
+ i2c->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
+ if (IS_ERR(i2c->clk)) {
|
||||
+ dev_err(&pdev->dev, "no clock defined\n");
|
||||
-+ return -ENODEV;
|
||||
++ return PTR_ERR(i2c->clk);
|
||||
++ }
|
||||
++ ret = clk_prepare_enable(i2c->clk);
|
||||
++ if (ret) {
|
||||
++ dev_err(&pdev->dev, "Unable to enable clock\n");
|
||||
++ return ret;
|
||||
+ }
|
||||
-+ clk_prepare_enable(i2c->clk);
|
||||
++
|
||||
+ i2c->dev = &pdev->dev;
|
||||
+
|
||||
-+ if (of_property_read_u32(pdev->dev.of_node,
|
||||
-+ "clock-frequency", &i2c->cur_clk))
|
||||
-+ i2c->cur_clk = 100000;
|
||||
++ if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
|
||||
++ &i2c->bus_freq))
|
||||
++ i2c->bus_freq = 100000;
|
||||
++
|
||||
++ if (i2c->bus_freq == 0) {
|
||||
++ dev_warn(i2c->dev, "clock-frequency 0 not supported\n");
|
||||
++ return -EINVAL;
|
||||
++ }
|
||||
+
|
||||
+ adap = &i2c->adap;
|
||||
+ adap->owner = THIS_MODULE;
|
||||
-+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
|
||||
+ adap->algo = &mtk_i2c_algo;
|
||||
+ adap->retries = 3;
|
||||
+ adap->dev.parent = &pdev->dev;
|
||||
+ i2c_set_adapdata(adap, i2c);
|
||||
+ adap->dev.of_node = pdev->dev.of_node;
|
||||
+ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
|
||||
-+ adap->quirks = &mtk_i2c_quirks;
|
||||
+
|
||||
+ platform_set_drvdata(pdev, i2c);
|
||||
+
|
||||
+ mtk_i2c_init(i2c);
|
||||
+
|
||||
+ ret = i2c_add_adapter(adap);
|
||||
-+ if (ret < 0) {
|
||||
-+ dev_err(&pdev->dev, "failed to add adapter\n");
|
||||
-+ clk_disable_unprepare(i2c->clk);
|
||||
++ if (ret < 0)
|
||||
+ return ret;
|
||||
-+ }
|
||||
+
|
||||
-+ dev_info(&pdev->dev, "clock %uKHz, re-start not support\n",
|
||||
-+ i2c->cur_clk/1000);
|
||||
++ dev_info(&pdev->dev, "clock %u kHz\n", i2c->bus_freq / 1000);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
@@ -439,8 +380,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
+{
|
||||
+ struct mtk_i2c *i2c = platform_get_drvdata(pdev);
|
||||
+
|
||||
-+ i2c_del_adapter(&i2c->adap);
|
||||
+ clk_disable_unprepare(i2c->clk);
|
||||
++ i2c_del_adapter(&i2c->adap);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
@@ -449,25 +390,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
+ .probe = mtk_i2c_probe,
|
||||
+ .remove = mtk_i2c_remove,
|
||||
+ .driver = {
|
||||
-+ .owner = THIS_MODULE,
|
||||
+ .name = "i2c-mt7621",
|
||||
+ .of_match_table = i2c_mtk_dt_ids,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
-+static int __init i2c_mtk_init (void)
|
||||
-+{
|
||||
-+ return platform_driver_register(&mtk_i2c_driver);
|
||||
-+}
|
||||
-+subsys_initcall(i2c_mtk_init);
|
||||
-+
|
||||
-+static void __exit i2c_mtk_exit (void)
|
||||
-+{
|
||||
-+ platform_driver_unregister(&mtk_i2c_driver);
|
||||
-+}
|
||||
-+module_exit(i2c_mtk_exit);
|
||||
++module_platform_driver(mtk_i2c_driver);
|
||||
+
|
||||
-+MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
|
||||
-+MODULE_DESCRIPTION("MT7621 I2c host driver");
|
||||
-+MODULE_LICENSE("GPL");
|
||||
++MODULE_AUTHOR("Steven Liu");
|
||||
++MODULE_DESCRIPTION("MT7621 I2C host driver");
|
||||
++MODULE_LICENSE("GPL v2");
|
||||
+MODULE_ALIAS("platform:MT7621-I2C");
|
||||
--
|
||||
2.17.1
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user