mirror of
https://github.com/FUjr/gl-infra-builder.git
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80 lines
3.4 KiB
Diff
80 lines
3.4 KiB
Diff
From 21020c2da30239e998d69c95c53bfbbc428f76a2 Mon Sep 17 00:00:00 2001
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From: "GL.iNet-Hongjian.Zhang" <hongjian.zhang@gl-inet.com>
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Date: Sat, 18 Sep 2021 15:52:56 +0800
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Subject: [PATCH 5/8] add spinand support
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---
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.../499-mtd-spinand-add-support.patch | 60 +++++++++++++++++++
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1 file changed, 60 insertions(+)
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create mode 100644 target/linux/ath79/patches-5.4/499-mtd-spinand-add-support.patch
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diff --git a/target/linux/ath79/patches-5.4/499-mtd-spinand-add-support.patch b/target/linux/ath79/patches-5.4/499-mtd-spinand-add-support.patch
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new file mode 100644
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index 0000000000..4a4b6e9bf0
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--- /dev/null
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+++ b/target/linux/ath79/patches-5.4/499-mtd-spinand-add-support.patch
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@@ -0,0 +1,60 @@
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+Index: b/drivers/mtd/nand/spi/gigadevice.c
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+===================================================================
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+--- a/drivers/mtd/nand/spi/gigadevice.c 2021-09-18 14:49:34.250500716 +0800
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++++ b/drivers/mtd/nand/spi/gigadevice.c 2021-09-18 14:55:06.091509000 +0800
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+@@ -278,6 +278,15 @@ static const struct spinand_info gigadev
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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+ gd5fxgq4uexxg_ecc_get_status)),
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++ SPINAND_INFO("GD5F1GQ5UExxG", 0x51,
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++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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++ NAND_ECCREQ(8, 512),
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++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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++ &write_cache_variants,
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++ &update_cache_variants),
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++ SPINAND_HAS_QE_BIT,
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++ SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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++ gd5fxgq4uexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148,
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+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+Index: b/drivers/mtd/nand/spi/macronix.c
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+===================================================================
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+--- a/drivers/mtd/nand/spi/macronix.c 2021-08-26 20:55:22.000000000 +0800
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++++ b/drivers/mtd/nand/spi/macronix.c 2021-09-18 15:06:07.031203336 +0800
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+@@ -108,6 +108,15 @@ static const struct spinand_info macroni
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
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+ mx35lf1ge4ab_ecc_get_status)),
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++ SPINAND_INFO("MX35LF1G24AD", 0x14,
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++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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++ NAND_ECCREQ(4, 512),
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++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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++ &write_cache_variants,
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++ &update_cache_variants),
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++ SPINAND_HAS_QE_BIT,
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++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
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++ mx35lf1ge4ab_ecc_get_status)),
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+ SPINAND_INFO("MX35LF2GE4AB", 0x22,
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+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
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+ NAND_ECCREQ(4, 512),
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+Index: b/drivers/mtd/nand/spi/paragon.c
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+===================================================================
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+--- a/drivers/mtd/nand/spi/paragon.c 2021-08-26 20:55:22.000000000 +0800
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++++ b/drivers/mtd/nand/spi/paragon.c 2021-09-18 15:01:02.476309144 +0800
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+@@ -115,6 +115,15 @@ static const struct spinand_info paragon
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+ 0,
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+ SPINAND_ECCINFO(&pn26g0xa_ooblayout,
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+ pn26g0xa_ecc_get_status)),
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++ SPINAND_INFO("XT26G01xxxx", 0xf1,
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++ NAND_MEMORG(1, 2048, 128, 64, 1024, 21, 1, 1, 1),
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++ NAND_ECCREQ(8, 512),
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++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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++ &write_cache_variants,
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++ &update_cache_variants),
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++ 0,
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++ SPINAND_ECCINFO(&pn26g0xa_ooblayout,
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++ pn26g0xa_ecc_get_status)),
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+ };
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+
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+ static int paragon_spinand_detect(struct spinand_device *spinand)
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--
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2.17.1
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