mirror of
https://github.com/FUjr/gl-infra-builder.git
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100 lines
3.1 KiB
Diff
100 lines
3.1 KiB
Diff
From 07d59ad2904e15a3af23a3fbea1c2e5c11aaccdc Mon Sep 17 00:00:00 2001
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From: Dongming Han <handongming@gl-inet.com>
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Date: Wed, 24 Aug 2022 12:22:00 +0800
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Subject: [PATCH] fix GD5F1GQ5UExxG ecc info
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---
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.../999-fix-GD5F1GQ5UExxG-ecc-info.patch | 80 +++++++++++++++++++
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1 file changed, 80 insertions(+)
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create mode 100644 target/linux/ipq40xx/patches-5.4/999-fix-GD5F1GQ5UExxG-ecc-info.patch
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diff --git a/target/linux/ipq40xx/patches-5.4/999-fix-GD5F1GQ5UExxG-ecc-info.patch b/target/linux/ipq40xx/patches-5.4/999-fix-GD5F1GQ5UExxG-ecc-info.patch
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new file mode 100644
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index 0000000000..8844b7d8e2
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--- /dev/null
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+++ b/target/linux/ipq40xx/patches-5.4/999-fix-GD5F1GQ5UExxG-ecc-info.patch
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@@ -0,0 +1,80 @@
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+From 9127ffb04ad07c66b2bfa1f6d5a54f5b35ce6ed8 Mon Sep 17 00:00:00 2001
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+From: Dongming Han <handongming@gl-inet.com>
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+Date: Wed, 24 Aug 2022 12:15:05 +0800
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+Subject: [PATCH] fix GD5F1GQ5UExxG ecc info
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+
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+---
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+ drivers/mtd/nand/spi/gigadevice.c | 45 ++++++++++++++++++++++++++++---
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+ 1 file changed, 41 insertions(+), 4 deletions(-)
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+
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+diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
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+index 9bd06c59b..e63ffc55e 100644
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+--- a/drivers/mtd/nand/spi/gigadevice.c
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++++ b/drivers/mtd/nand/spi/gigadevice.c
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+@@ -203,6 +203,43 @@ static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
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+ return -EINVAL;
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+ }
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+
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++static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand,
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++ u8 status)
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++{
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++ u8 status2;
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++ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2,
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++ &status2);
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++ int ret;
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++
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++ switch (status & STATUS_ECC_MASK) {
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++ case STATUS_ECC_NO_BITFLIPS:
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++ return 0;
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++
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++ case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
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++ /*
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++ * Read status2 register to determine a more fine grained
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++ * bit error status
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++ */
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++ ret = spi_mem_exec_op(spinand->spimem, &op);
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++ if (ret)
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++ return ret;
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++
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++ /*
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++ * 1 ... 4 bits are flipped (and corrected)
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++ */
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++ /* bits sorted this way (1...0): ECCSE1, ECCSE0 */
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++ return ((status2 & STATUS_ECC_MASK) >> 4) + 1;
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++
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++ case STATUS_ECC_UNCOR_ERROR:
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++ return -EBADMSG;
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++
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++ default:
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++ break;
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++ }
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++
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++ return -EINVAL;
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++}
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++
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+ static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
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+ u8 status)
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+ {
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+@@ -233,15 +270,15 @@ static const struct spinand_info gigadevice_spinand_table[] = {
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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+ gd5fxgq4xa_ecc_get_status)),
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+- SPINAND_INFO("GD5F1GQ5xExxG", 0x51,
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++ SPINAND_INFO("GD5F1GQ5UExxG", 0x51,
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+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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+- NAND_ECCREQ(8, 512),
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++ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+- SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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+- gd5fxgq4xa_ecc_get_status)),
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++ SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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++ gd5fxgq5xexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F2GQ4xA", 0xF2,
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+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+--
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+2.25.1
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+
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--
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2.25.1
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