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46 lines
1.4 KiB
Diff
46 lines
1.4 KiB
Diff
From d36cae648736cb36e5b8b03aa8baa1788e503f71 Mon Sep 17 00:00:00 2001
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From: gl-luochongjun <luochongjun@gl-inet.com>
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Date: Thu, 8 Dec 2022 19:14:00 +0800
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Subject: [PATCH] compat gpy211 external flash
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---
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.../mediatek/files-5.4/drivers/net/phy/gpy211.c | 12 +++++++++++-
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1 file changed, 11 insertions(+), 1 deletion(-)
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diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/gpy211.c b/target/linux/mediatek/files-5.4/drivers/net/phy/gpy211.c
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index 4ac83b34c1..3023edb5a1 100644
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--- a/target/linux/mediatek/files-5.4/drivers/net/phy/gpy211.c
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+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/gpy211.c
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@@ -2,6 +2,7 @@
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#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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+#include <linux/delay.h>
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static int gpy211_phy_config_init(struct phy_device *phydev)
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{
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@@ -10,10 +11,19 @@ static int gpy211_phy_config_init(struct phy_device *phydev)
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int gpy211_phy_probe(struct phy_device *phydev)
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{
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+ int i;
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int sgmii_reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, 8);
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+ //GPY211 with external flash requires at least 750ms to wait for mdio ready, here 1000ms
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+ for(i=0;i<1000;i++){
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+ if( sgmii_reg > 0 )
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+ break;
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+ usleep_range(1000,1001);
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+ sgmii_reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, 8);
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+ }
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+
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/* enable 2.5G SGMII rate adaption */
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- phy_write_mmd(phydev, MDIO_MMD_VEND1, 8, 0x24e2);
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 8, 0xa4fa);
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return 0;
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}
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--
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2.25.1
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