mirror of
https://github.com/FUjr/gl-infra-builder.git
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79 lines
2.7 KiB
Diff
79 lines
2.7 KiB
Diff
From 24e6e2fa3c65a7f801e0aac2cff30e2df5fef233 Mon Sep 17 00:00:00 2001
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From: developer <developer@mediatek.com>
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Date: Tue, 20 Sep 2022 15:14:43 +0800
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Subject: [PATCH] [][kernel][common][eth][Remove SGMII_FIXED_2G5 from Maxlinear
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PHY driver]
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[Description]
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Remove SGMII_FIXED_2G5 from Maxlinear PHY driver.
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We no longer need SGMII_FIXED_2G5 after applying DEL_RXFIFO_CLR patch.
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[Release-log]
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N/A
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Change-Id: I6d2aea74bcee679210867580394001221f609d21
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Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6538171
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---
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.../patches-5.4/746-mxl-gpy-phy-support.patch | 17 +++--------------
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1 file changed, 3 insertions(+), 14 deletions(-)
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diff --git a/target/linux/mediatek/patches-5.4/746-mxl-gpy-phy-support.patch b/target/linux/mediatek/patches-5.4/746-mxl-gpy-phy-support.patch
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index 6812f0c..26bef5f 100644
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--- a/target/linux/mediatek/patches-5.4/746-mxl-gpy-phy-support.patch
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+++ b/target/linux/mediatek/patches-5.4/746-mxl-gpy-phy-support.patch
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@@ -32,7 +32,7 @@ new file mode 100644
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index 0000000..7304278
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--- /dev/null
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+++ b/drivers/net/phy/mxl-gpy.c
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-@@ -0,0 +1,749 @@
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+@@ -0,0 +1,738 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/* Copyright (C) 2021 Maxlinear Corporation
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+ * Copyright (C) 2020 Intel Corporation
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@@ -98,7 +98,6 @@ index 0000000..7304278
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+#define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */
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+#define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \
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+ VSPEC1_SGMII_CTRL_ANRS)
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-+#define VSPEC1_SGMII_FIXED_2G5 BIT(5)
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+
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+/* WoL */
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+#define VPSPEC2_WOL_CTL 0x0E06
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@@ -301,23 +300,13 @@ index 0000000..7304278
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+ case SPEED_2500:
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+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
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-+ VSPEC1_SGMII_CTRL_ANEN | VSPEC1_SGMII_FIXED_2G5,
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-+ 0);
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++ VSPEC1_SGMII_CTRL_ANEN, 0);
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+ if (ret < 0)
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+ phydev_err(phydev,
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+ "Error: Disable of SGMII ANEG failed: %d\n",
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+ ret);
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+ break;
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+ case SPEED_1000:
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-+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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-+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
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-+ VSPEC1_SGMII_CTRL_ANEN | VSPEC1_SGMII_FIXED_2G5,
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-+ VSPEC1_SGMII_FIXED_2G5);
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-+ if (ret < 0)
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-+ phydev_err(phydev,
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-+ "Error: Disable of SGMII ANEG failed: %d\n",
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-+ ret);
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-+ break;
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+ case SPEED_100:
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+ case SPEED_10:
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+ phydev->interface = PHY_INTERFACE_MODE_SGMII;
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@@ -327,7 +316,7 @@ index 0000000..7304278
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+ * if ANEG is disabled (in 2500-BaseX mode).
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+ */
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+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
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-+ VSPEC1_SGMII_ANEN_ANRS | VSPEC1_SGMII_FIXED_2G5,
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++ VSPEC1_SGMII_ANEN_ANRS,
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+ VSPEC1_SGMII_ANEN_ANRS);
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+ if (ret < 0)
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+ phydev_err(phydev,
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--
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2.25.1
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