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https://github.com/FUjr/gl-infra-builder.git
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91 lines
3.5 KiB
Diff
91 lines
3.5 KiB
Diff
From 2b76a9d983820ef4cce97bdcadcfcc14c18efc7f Mon Sep 17 00:00:00 2001
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From: developer <developer@mediatek.com>
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Date: Tue, 20 Sep 2022 14:59:45 +0800
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Subject: [PATCH] [][kernel][common][eth][Fix HSGMII link down issue]
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[Description]
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Fix HSGMII link down issue.
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If without this patch, HSGMII may link down when PHY performs re-AN.
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[Release-log]
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N/A
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Change-Id: I40ad6e5d35b92e4e36689ab3db9e25b7695d2f43
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Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6538088
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---
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.../drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++++
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.../drivers/net/ethernet/mediatek/mtk_sgmii.c | 13 +++++++++++--
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2 files changed, 15 insertions(+), 2 deletions(-)
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diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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index 54674ad..edaeceb 100755
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--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -720,6 +720,10 @@
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#define SGMII_SEND_AN_ERROR_EN BIT(11)
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#define SGMII_IF_MODE_MASK GENMASK(5, 1)
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+/* Register to reset SGMII design */
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+#define SGMII_RESERVED_0 0x34
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+#define SGMII_SW_RESET BIT(0)
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+
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/* Register to set SGMII speed, ANA RG_ Control Signals III*/
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#define SGMSYS_ANA_RG_CS3 0x2028
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#define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
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diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c
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index 8198c7c..2661645 100755
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--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -47,6 +47,9 @@ int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, unsigned int id)
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/* Assert PHYA power down state */
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regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
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+ /* Reset SGMII PCS state */
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+ regmap_write(ss->regmap[id], SGMII_RESERVED_0, SGMII_SW_RESET);
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+
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regmap_read(ss->regmap[id], ss->ana_rgc3, &val);
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val &= ~RG_PHY_SPEED_3_125G;
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regmap_write(ss->regmap[id], ss->ana_rgc3, val);
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@@ -66,7 +69,6 @@ int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, unsigned int id)
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regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
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regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
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- val |= SGMII_AN_RESTART;
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val |= SGMII_AN_ENABLE;
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regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
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@@ -91,6 +93,9 @@ int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, unsigned int id,
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/* Assert PHYA power down state */
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regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
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+ /* Reset SGMII PCS state */
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+ regmap_write(ss->regmap[id], SGMII_RESERVED_0, SGMII_SW_RESET);
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+
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regmap_read(ss->regmap[id], ss->ana_rgc3, &val);
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val &= ~RG_PHY_SPEED_MASK;
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if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
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@@ -105,6 +110,7 @@ int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, unsigned int id,
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/* SGMII force mode setting */
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regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
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val &= ~SGMII_IF_MODE_MASK;
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+ val &= ~SGMII_REMOTE_FAULT_DIS;
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switch (state->speed) {
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case SPEED_10:
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@@ -119,7 +125,10 @@ int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, unsigned int id,
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break;
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};
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- if (state->duplex == DUPLEX_FULL)
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+ /* SGMII 1G and 2.5G force mode can only work in full duplex
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+ * mode, no matter SGMII_FORCE_HALF_DUPLEX is set or not.
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+ */
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+ if (state->duplex != DUPLEX_FULL)
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val |= SGMII_DUPLEX_FULL;
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regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
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--
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2.25.1
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