mirror of
https://github.com/FUjr/gl-infra-builder.git
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62 lines
1.7 KiB
Diff
62 lines
1.7 KiB
Diff
From 639c5cd8f5e55b7f8f5db1eaf3bf819799ed3d79 Mon Sep 17 00:00:00 2001
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From: Dongming Han <handongming@gl-inet.com>
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Date: Fri, 9 Sep 2022 15:05:54 +0800
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Subject: [PATCH] ax1800 dts add ble uart
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---
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.../boot/dts/qcom/qcom-ipq6018-gl-ax1800.dts | 26 +++++++++++++++++++
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1 file changed, 26 insertions(+)
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diff --git a/feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq6018-gl-ax1800.dts b/feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq6018-gl-ax1800.dts
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index 685cfc68..4d9ec935 100644
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--- a/feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq6018-gl-ax1800.dts
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+++ b/feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq6018-gl-ax1800.dts
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@@ -22,6 +22,8 @@
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compatible = "glinet,ax1800", "qcom,ipq6018-cp03", "qcom,ipq6018";
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aliases {
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+ serial0 = &blsp1_uart3; //system uart = ttyMSM0
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+ serial1 = &blsp1_uart4; //tl8251 = ttyMSM1
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ethernet3 = "/soc/dp4";
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ethernet4 = "/soc/dp5";
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};
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@@ -58,6 +60,16 @@
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};
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&soc {
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+ blsp1_uart4: serial@78b2000 {
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+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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+ reg = <0x78b2000 0x200>;
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+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+
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dp4 {
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device_type = "network";
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compatible = "qcom,nss-dp";
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@@ -91,4 +103,18 @@
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bias-pull-up;
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};
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};
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+ uart_tl8251_pins: uart_tl8251_pins {
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+ mux {
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+ pins = "gpio75", "gpio76"; // gpio 77 reset tl8251
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+ function = "blsp3_uart";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+ };
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+};
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+
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+&blsp1_uart4 {
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+ pinctrl-0 = <&uart_tl8251_pins>;
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+ pinctrl-names = "default";
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+ status = "ok";
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};
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--
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2.25.1
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