mirror of
https://github.com/FUjr/gl-infra-builder.git
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78 lines
3.7 KiB
Diff
78 lines
3.7 KiB
Diff
From a417695d1bad98240995e15f697374992719198b Mon Sep 17 00:00:00 2001
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From: "GL.iNet-Hongjian.Zhang" <hongjian.zhang@gl-inet.com>
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Date: Tue, 10 May 2022 18:52:07 +0800
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Subject: [PATCH] add spi_nor_write.patch
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---
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.../ath79/patches-5.4/320-add_spi_nor_write.patch | 13 +++++++++++++
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.../patches-5.4/499-mtd-spinand-add-support.patch | 14 +++++++-------
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2 files changed, 20 insertions(+), 7 deletions(-)
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create mode 100644 target/linux/ath79/patches-5.4/320-add_spi_nor_write.patch
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diff --git a/target/linux/ath79/patches-5.4/320-add_spi_nor_write.patch b/target/linux/ath79/patches-5.4/320-add_spi_nor_write.patch
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new file mode 100644
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index 0000000000..160d2c9d2e
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--- /dev/null
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+++ b/target/linux/ath79/patches-5.4/320-add_spi_nor_write.patch
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@@ -0,0 +1,13 @@
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+Index: b/drivers/mtd/spi-nor/spi-nor.c
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+===================================================================
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+--- a/drivers/mtd/spi-nor/spi-nor.c 2022-05-10 18:48:43.628950665 +0800
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++++ b/drivers/mtd/spi-nor/spi-nor.c 2022-05-10 18:50:19.037408439 +0800
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+@@ -5023,6 +5023,8 @@ int spi_nor_scan(struct spi_nor *nor, co
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+ else
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+ mtd->_write = spi_nor_write;
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+
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++ mtd->_panic_write = spi_nor_write;
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++
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+ if (info->flags & USE_FSR)
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+ nor->flags |= SNOR_F_USE_FSR;
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+ if (info->flags & SPI_NOR_HAS_TB)
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diff --git a/target/linux/ath79/patches-5.4/499-mtd-spinand-add-support.patch b/target/linux/ath79/patches-5.4/499-mtd-spinand-add-support.patch
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index 4a4b6e9bf0..7f8965889a 100644
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--- a/target/linux/ath79/patches-5.4/499-mtd-spinand-add-support.patch
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+++ b/target/linux/ath79/patches-5.4/499-mtd-spinand-add-support.patch
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@@ -1,14 +1,14 @@
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Index: b/drivers/mtd/nand/spi/gigadevice.c
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===================================================================
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---- a/drivers/mtd/nand/spi/gigadevice.c 2021-09-18 14:49:34.250500716 +0800
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-+++ b/drivers/mtd/nand/spi/gigadevice.c 2021-09-18 14:55:06.091509000 +0800
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+--- a/drivers/mtd/nand/spi/gigadevice.c 2022-05-10 18:30:27.215588502 +0800
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++++ b/drivers/mtd/nand/spi/gigadevice.c 2022-05-10 18:30:53.308870949 +0800
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@@ -278,6 +278,15 @@ static const struct spinand_info gigadev
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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gd5fxgq4uexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F1GQ5UExxG", 0x51,
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+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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-+ NAND_ECCREQ(8, 512),
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++ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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@@ -20,8 +20,8 @@ Index: b/drivers/mtd/nand/spi/gigadevice.c
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NAND_ECCREQ(8, 512),
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Index: b/drivers/mtd/nand/spi/macronix.c
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===================================================================
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---- a/drivers/mtd/nand/spi/macronix.c 2021-08-26 20:55:22.000000000 +0800
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-+++ b/drivers/mtd/nand/spi/macronix.c 2021-09-18 15:06:07.031203336 +0800
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+--- a/drivers/mtd/nand/spi/macronix.c 2022-05-10 18:30:27.215588502 +0800
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++++ b/drivers/mtd/nand/spi/macronix.c 2022-05-10 18:30:27.211588305 +0800
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@@ -108,6 +108,15 @@ static const struct spinand_info macroni
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
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@@ -40,8 +40,8 @@ Index: b/drivers/mtd/nand/spi/macronix.c
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NAND_ECCREQ(4, 512),
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Index: b/drivers/mtd/nand/spi/paragon.c
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===================================================================
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---- a/drivers/mtd/nand/spi/paragon.c 2021-08-26 20:55:22.000000000 +0800
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-+++ b/drivers/mtd/nand/spi/paragon.c 2021-09-18 15:01:02.476309144 +0800
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+--- a/drivers/mtd/nand/spi/paragon.c 2022-05-10 18:30:27.215588502 +0800
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++++ b/drivers/mtd/nand/spi/paragon.c 2022-05-10 18:30:27.211588305 +0800
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@@ -115,6 +115,15 @@ static const struct spinand_info paragon
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0,
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SPINAND_ECCINFO(&pn26g0xa_ooblayout,
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--
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2.17.1
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