diff --git a/include/package-pack.mk b/include/package-pack.mk index 2baceae72a..c989fdb116 100644 --- a/include/package-pack.mk +++ b/include/package-pack.mk @@ -280,7 +280,7 @@ endif ) endif - $(INSTALL_DIR) $$(PDIR_$(1))/tmp + $(INSTALL_DIR) $$(PDIR_$(1)) ifeq ($(CONFIG_USE_APK),) mkdir -p $$(IDIR_$(1))/CONTROL diff --git a/package/network/utils/bpftool/Makefile b/package/network/utils/bpftool/Makefile index b2fdfc1632..1a70e9ee98 100644 --- a/package/network/utils/bpftool/Makefile +++ b/package/network/utils/bpftool/Makefile @@ -8,11 +8,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=bpftool -PKG_VERSION:=7.5.0 +PKG_VERSION:=7.6.0 PKG_RELEASE:=1 PKG_SOURCE_URL:=https://github.com/libbpf/bpftool -PKG_MIRROR_HASH:=1da7c08959e7819772145774322ffd876f3180065be1c3759336dca98ac9f666 +PKG_MIRROR_HASH:=7406a424375642fda35cae6eccaa8e27c21e4f132123c0207a83f763ef6fe899 PKG_SOURCE_PROTO:=git PKG_SOURCE_VERSION:=v$(PKG_VERSION) diff --git a/package/network/utils/bpftool/patches/002-includes.patch b/package/network/utils/bpftool/patches/002-includes.patch index e6ec3f262b..51ade9f700 100644 --- a/package/network/utils/bpftool/patches/002-includes.patch +++ b/package/network/utils/bpftool/patches/002-includes.patch @@ -1,6 +1,6 @@ --- a/src/Makefile +++ b/src/Makefile -@@ -73,10 +73,10 @@ CFLAGS += -W -Wall -Wextra -Wno-unused-p +@@ -72,10 +72,10 @@ CFLAGS += -Wno-missing-field-initializer CFLAGS += $(filter-out -Wswitch-enum -Wnested-externs,$(EXTRA_WARNINGS)) CFLAGS += -DPACKAGE='"bpftool"' -D__EXPORTED_HEADERS__ \ -I$(or $(OUTPUT),.) \ diff --git a/package/system/apk/Makefile b/package/system/apk/Makefile index 91faa60800..c879c53bcd 100644 --- a/package/system/apk/Makefile +++ b/package/system/apk/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE:=2 PKG_SOURCE_URL=https://gitlab.alpinelinux.org/alpine/apk-tools.git PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2025-10-07 -PKG_SOURCE_VERSION:=6ffc65c63004b8d991ead4ea0f3d80e05b06b977 -PKG_MIRROR_HASH:=388e0210247a49099f49e783ff3d0753bed26bbb91acec2dd2d5722aca5daf6f +PKG_SOURCE_DATE:=2025-11-10 +PKG_SOURCE_VERSION:=2c027261492169783f6aaa2b7731a4e90dc7a5b0 +PKG_MIRROR_HASH:=177769a6b7a4b0a2117ed4326060eb08b19c1b930a8a92b7c25d2f56154f497e PKG_VERSION=3.0.0_pre$(subst -,,$(PKG_SOURCE_DATE)) diff --git a/package/system/apk/patches/0001-openwrt-move-layer-db-to-temp-folder.patch b/package/system/apk/patches/0001-openwrt-move-layer-db-to-temp-folder.patch index 62c3d56453..32aaa92fa5 100644 --- a/package/system/apk/patches/0001-openwrt-move-layer-db-to-temp-folder.patch +++ b/package/system/apk/patches/0001-openwrt-move-layer-db-to-temp-folder.patch @@ -10,7 +10,7 @@ Signed-off-by: Paul Spooren --- a/src/database.c +++ b/src/database.c -@@ -1856,7 +1856,7 @@ const char *apk_db_layer_name(int layer) +@@ -1937,7 +1937,7 @@ const char *apk_db_layer_name(int layer) { switch (layer) { case APK_DB_LAYER_ROOT: return "lib/apk/db"; diff --git a/package/system/apk/patches/010-libressl4.patch b/package/system/apk/patches/010-libressl4.patch new file mode 100644 index 0000000000..16e337e013 --- /dev/null +++ b/package/system/apk/patches/010-libressl4.patch @@ -0,0 +1,32 @@ +From aa71510f843d5cce5f75b6abfa3a70caeacbe36d Mon Sep 17 00:00:00 2001 +From: Rosen Penev +Date: Thu, 20 Nov 2025 18:26:52 -0800 +Subject: [PATCH] fix usage under LibreSSL > 3 + +crypto needs to be initialized as the context relies on it. + +Fixes crash in EVP_DigestInit_ex being called with a NULL digest. + +Signed-off-by: Rosen Penev +--- + src/apk.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/src/apk.c ++++ b/src/apk.c +@@ -571,6 +571,7 @@ int main(int argc, char **argv) + apk_argv[argc] = NULL; + apk_argv[argc+1] = NULL; + ++ apk_crypto_init(); + apk_ctx_init(&ctx); + umask(0); + setup_terminal(); +@@ -583,7 +584,6 @@ int main(int argc, char **argv) + if (applet->parse) applet->parse(applet_ctx, &ctx, APK_OPTIONS_INIT, NULL); + } + +- apk_crypto_init(); + apk_io_url_init(&ctx.out); + apk_io_url_set_timeout(60); + apk_io_url_set_redirect_callback(redirect_callback); diff --git a/package/system/apk/patches/999-small-scripts-tar.patch b/package/system/apk/patches/999-small-scripts-tar.patch index ff93e821eb..e690502ccf 100644 --- a/package/system/apk/patches/999-small-scripts-tar.patch +++ b/package/system/apk/patches/999-small-scripts-tar.patch @@ -1,8 +1,6 @@ -diff --git a/doc/apk.8.scd b/doc/apk.8.scd -index bd15fe75d7a4..cbac8c6c8b7b 100644 --- a/doc/apk.8.scd +++ b/doc/apk.8.scd -@@ -461,7 +461,8 @@ timeout 120 +@@ -462,7 +462,8 @@ timeout 120 */lib/apk/db/installed* Database of installed packages and their contents. @@ -12,11 +10,9 @@ index bd15fe75d7a4..cbac8c6c8b7b 100644 Collection of all package scripts from currently installed packages. */lib/apk/db/triggers* -diff --git a/src/apk_database.h b/src/apk_database.h -index 9f8670ac8ebb..10f1414c9e06 100644 --- a/src/apk_database.h +++ b/src/apk_database.h -@@ -202,6 +202,7 @@ struct apk_database { +@@ -210,6 +210,7 @@ struct apk_database { unsigned int compat_depversions : 1; unsigned int sorted_names : 1; unsigned int sorted_installed_packages : 1; @@ -24,11 +20,9 @@ index 9f8670ac8ebb..10f1414c9e06 100644 struct apk_dependency_array *world; struct apk_id_cache *id_cache; -diff --git a/src/database.c b/src/database.c -index cbe58ebbf885..cb1b709140af 100644 --- a/src/database.c +++ b/src/database.c -@@ -1255,8 +1255,11 @@ static int apk_db_read_layer(struct apk_database *db, unsigned layer) +@@ -1338,8 +1338,11 @@ static int apk_db_read_layer(struct apk_ } if (!(flags & APK_OPENF_NO_SCRIPTS)) { @@ -42,7 +36,7 @@ index cbe58ebbf885..cb1b709140af 100644 if (!ret && r != -ENOENT) ret = r; } -@@ -2128,8 +2131,9 @@ static int apk_db_write_layers(struct apk_database *db) +@@ -2214,8 +2217,9 @@ static int apk_db_write_layers(struct ap continue; } ld->installed = apk_ostream_to_file(ld->fd, "installed", 0644); diff --git a/package/system/rpcd/Makefile b/package/system/rpcd/Makefile index dcd9948966..22e73f21fc 100644 --- a/package/system/rpcd/Makefile +++ b/package/system/rpcd/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/rpcd.git -PKG_MIRROR_HASH:=79a5e17e29396e98c2bb2b0004d370223628ee32dc033cb073a1115c5386f5aa -PKG_SOURCE_DATE:=2025-11-07 -PKG_SOURCE_VERSION:=917000075eb48c934f0a456be3b884758c376e0b +PKG_MIRROR_HASH:=b7b813e0b76f586bfe3432ef94883bd1b079c48003666a2128fbf028109a1a65 +PKG_SOURCE_DATE:=2025-11-10 +PKG_SOURCE_VERSION:=483263c7b0cd3922b93be2cf9dad5eeccbb9fedb PKG_MAINTAINER:=Jo-Philipp Wich PKG_LICENSE:=ISC diff --git a/package/system/ubus/Makefile b/package/system/ubus/Makefile index bf930cd0d1..43eb5cd843 100644 --- a/package/system/ubus/Makefile +++ b/package/system/ubus/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/ubus.git -PKG_SOURCE_DATE:=2025-11-03 -PKG_SOURCE_VERSION:=0d4bcb56f5e1386e7dc99f1ec9f3b6c9211c8ab6 -PKG_MIRROR_HASH:=c3f8519fbe1fa3795925e327eeaf292f0325c9ebb696ff2ea73877e9d0186075 +PKG_SOURCE_DATE:=2025-11-18 +PKG_SOURCE_VERSION:=2737da3819fefafa5b63d5f82efb77ff0032a5d8 +PKG_MIRROR_HASH:=6044e9bde877ee585a69386ab377e3bc1924e15b7343db8df8234b1d76f870ec PKG_ABI_VERSION:=$(call abi_version_str,$(PKG_SOURCE_DATE)) CMAKE_INSTALL:=1 diff --git a/package/system/uci/Makefile b/package/system/uci/Makefile index f73078842a..5d4750ca5c 100644 --- a/package/system/uci/Makefile +++ b/package/system/uci/Makefile @@ -13,9 +13,9 @@ PKG_RELEASE:=1 PKG_SOURCE_URL=$(PROJECT_GIT)/project/uci.git PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2025-11-03 -PKG_SOURCE_VERSION:=c1e2eee6c5e35438daf13fa72b04778ff07a00c7 -PKG_MIRROR_HASH:=cad94326f6d0bae44ad59d6dc371c78cbb1ed5f74f85d79167cba0f1f8d01eee +PKG_SOURCE_DATE:=2025-11-18 +PKG_SOURCE_VERSION:=5bea13572325af4fb3057ff600cc7f7d5b82012b +PKG_MIRROR_HASH:=62a0f20970e7db5b0de4814168e0f9f558f16d5e8caa1203d247ae1faa1c2a18 PKG_ABI_VERSION:=20250120 PKG_LICENSE:=LGPL-2.1 diff --git a/package/utils/ucode/Makefile b/package/utils/ucode/Makefile index 45740848fb..1ca10cb88d 100644 --- a/package/utils/ucode/Makefile +++ b/package/utils/ucode/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=https://github.com/jow-/ucode.git -PKG_SOURCE_DATE:=2025-11-07 -PKG_SOURCE_VERSION:=ea579046a619e5325b994780bf2ce1ffde448794 -PKG_MIRROR_HASH:=4c152c337963eda588650f439f7633fc1ead20864d8939e45fd95563ea2b0b4f +PKG_SOURCE_DATE:=2025-11-19 +PKG_SOURCE_VERSION:=48ed18d2532e9197212c34473ab926c7b5e8ac73 +PKG_MIRROR_HASH:=34529706bcb413dffb3d73e78fe97971bd2b518c097c86470edadc1ca79a480c PKG_MAINTAINER:=Jo-Philipp Wich PKG_LICENSE:=ISC diff --git a/package/utils/ucode/patches/010-Revert-nl80211-read-all-pending-event-messages.patch b/package/utils/ucode/patches/010-Revert-nl80211-read-all-pending-event-messages.patch deleted file mode 100644 index 0af66b25ad..0000000000 --- a/package/utils/ucode/patches/010-Revert-nl80211-read-all-pending-event-messages.patch +++ /dev/null @@ -1,22 +0,0 @@ -From: Felix Fietkau -Date: Tue, 14 Oct 2025 10:59:26 +0000 -Subject: [PATCH] Revert "nl80211: read all pending event messages" - -This reverts commit 387880348c89b5be54ddf13b9543b19266dd02ae. -This commit is broken and causes infinite polling on netlink sockets. - -Signed-off-by: Felix Fietkau ---- - ---- a/lib/nl80211.c -+++ b/lib/nl80211.c -@@ -2722,8 +2722,7 @@ uc_nl_request(uc_vm_t *vm, size_t nargs) - static void - uc_nl_listener_cb(struct uloop_fd *fd, unsigned int events) - { -- while (nl_recvmsgs(nl80211_conn.evsock, nl80211_conn.evsock_cb) == 0) -- ; -+ nl_recvmsgs(nl80211_conn.evsock, nl80211_conn.evsock_cb); - } - - static uc_value_t * diff --git a/target/linux/apm821xx/Makefile b/target/linux/apm821xx/Makefile index ac28b00211..dc1997719f 100644 --- a/target/linux/apm821xx/Makefile +++ b/target/linux/apm821xx/Makefile @@ -9,8 +9,7 @@ CPU_TYPE:=464fp FEATURES:=fpu dt gpio ramdisk squashfs usb SUBTARGETS:=nand sata -KERNEL_PATCHVER:=6.6 -KERNEL_TESTING_PATCHVER:=6.12 +KERNEL_PATCHVER:=6.12 define Target/Description Build images for AppliedMicro APM821xx based boards. diff --git a/target/linux/apm821xx/config-6.6 b/target/linux/apm821xx/config-6.6 deleted file mode 100644 index a9c9a952c8..0000000000 --- a/target/linux/apm821xx/config-6.6 +++ /dev/null @@ -1,276 +0,0 @@ -# CONFIG_40x is not set -# CONFIG_440_CPU is not set -CONFIG_44x=y -CONFIG_464_CPU=y -CONFIG_4xx=y -CONFIG_4xx_SOC=y -# CONFIG_ADVANCED_OPTIONS is not set -CONFIG_APM821xx=y -# CONFIG_APOLLO3G is not set -# CONFIG_ARCHES is not set -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_MMAP_RND_BITS=11 -CONFIG_ARCH_MMAP_RND_BITS_MAX=17 -CONFIG_ARCH_MMAP_RND_BITS_MIN=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SPLIT_ARG64=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y -CONFIG_AUDIT_ARCH=y -# CONFIG_BAMBOO is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_MQ_PCI=y -CONFIG_BLUESTONE=y -CONFIG_BOOKE=y -CONFIG_BOOKE_OR_40x=y -CONFIG_BOOKE_WDT=y -# CONFIG_CANYONLANDS is not set -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs noinitrd" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_COMMON_CLK=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_MITIGATIONS=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_GF128MUL=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_MD5_PPC is not set -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -# CONFIG_CRYPTO_SHA1_PPC is not set -CONFIG_CRYPTO_SHA3=y -CONFIG_DATA_SHIFT=12 -CONFIG_DEBUG_INFO=y -CONFIG_DMADEVICES=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DTC=y -CONFIG_DW_DMAC=y -CONFIG_DW_DMAC_CORE=y -CONFIG_EARLY_PRINTK=y -# CONFIG_EBONY is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -# CONFIG_EIGER is not set -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXTRA_TARGETS="uImage" -CONFIG_FIXED_PHY=y -CONFIG_FORCE_NR_CPUS=y -CONFIG_FORCE_PCI=y -# CONFIG_FSL_LBC is not set -CONFIG_FS_IOMAP=y -CONFIG_FUNCTION_ALIGNMENT=0 -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -# CONFIG_GEN_RTC is not set -# CONFIG_GLACIER is not set -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_IBM_IIC=y -CONFIG_IBM_EMAC=y -CONFIG_IBM_EMAC_EMAC4=y -CONFIG_IBM_EMAC_POLL_WEIGHT=32 -CONFIG_IBM_EMAC_RGMII=y -CONFIG_IBM_EMAC_RXB=128 -CONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256 -CONFIG_IBM_EMAC_TAH=y -CONFIG_IBM_EMAC_TXB=128 -# CONFIG_ICON is not set -CONFIG_ILLEGAL_POINTER_VALUE=0 -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_ISA_DMA_API=y -# CONFIG_JFFS2_FS is not set -# CONFIG_KATMAI is not set -CONFIG_KERNEL_START=0xc0000000 -CONFIG_LEDS_TRIGGER_MTD=y -CONFIG_LEDS_TRIGGER_PATTERN=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MATH_EMULATION is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MIGRATION=y -CONFIG_MMU_GATHER_MERGE_VMAS=y -CONFIG_MMU_GATHER_PAGE_SIZE=y -CONFIG_MMU_LAZY_TLB_REFCOUNT=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -# CONFIG_MTD_CFI_GEOMETRY is not set -# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_EGRESS=y -CONFIG_NET_INGRESS=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_XGRESS=y -CONFIG_NOT_COHERENT_CACHE=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=1 -CONFIG_NR_IRQS=512 -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y -CONFIG_NVMEM_SYSFS=y -CONFIG_NVMEM_U_BOOT_ENV=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_GPIO_MM_GPIOCHIP=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND=y -CONFIG_PACKING=y -CONFIG_PAGE_OFFSET=0xc0000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_ARCH_FALLBACKS=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -CONFIG_PHYSICAL_START=0x00000000 -CONFIG_PHYS_64BIT=y -CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PMU_SYSFS is not set -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_PPC44x_SIMPLE=y -CONFIG_PPC4xx_GPIO=y -CONFIG_PPC4xx_PCI_EXPRESS=y -# CONFIG_PPC64 is not set -# CONFIG_PPC_47x is not set -# CONFIG_PPC_85xx is not set -# CONFIG_PPC_8xx is not set -CONFIG_PPC_ADV_DEBUG_DACS=2 -CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y -CONFIG_PPC_ADV_DEBUG_DVCS=2 -CONFIG_PPC_ADV_DEBUG_IACS=4 -CONFIG_PPC_ADV_DEBUG_REGS=y -# CONFIG_PPC_BOOK3S_32 is not set -CONFIG_PPC_DCR=y -CONFIG_PPC_DCR_NATIVE=y -# CONFIG_PPC_EARLY_DEBUG is not set -CONFIG_PPC_FPU=y -CONFIG_PPC_FPU_REGS=y -CONFIG_PPC_INDIRECT_PCI=y -CONFIG_PPC_KUAP=y -# CONFIG_PPC_KUAP_DEBUG is not set -CONFIG_PPC_KUEP=y -CONFIG_PPC_MMU_NOHASH=y -CONFIG_PPC_PAGE_SHIFT=12 -# CONFIG_PPC_PCI_BUS_NUM_DOMAIN_DEPENDENT is not set -CONFIG_PPC_UDBG_16550=y -CONFIG_PPC_WERROR=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTE_64BIT=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -# CONFIG_RAINIER is not set -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGULATOR=y -CONFIG_RSEQ=y -# CONFIG_SAM440EP is not set -# CONFIG_SCOM_DEBUGFS is not set -# CONFIG_SEQUOIA is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SMT_NUM_THREADS_DYNAMIC=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSE_IRQ=y -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y -# CONFIG_STATIC_CALL_SELFTEST is not set -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -# CONFIG_TAISHAN is not set -CONFIG_TARGET_CPU="464" -CONFIG_TARGET_CPU_BOOL=y -CONFIG_TASK_SIZE=0xc0000000 -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_THREAD_SHIFT=13 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -# CONFIG_TOOLCHAIN_DEFAULT_CPU is not set -CONFIG_USB_SUPPORT=y -CONFIG_VDSO32=y -# CONFIG_VIRTIO_MENU is not set -# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set -# CONFIG_WARP is not set -CONFIG_WATCHDOG_CORE=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_POWERPC=y -# CONFIG_YOSEMITE is not set -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/apm821xx/patches-6.6/201-add-amcc-apollo3g-support.patch b/target/linux/apm821xx/patches-6.6/201-add-amcc-apollo3g-support.patch deleted file mode 100644 index d26e74dfb7..0000000000 --- a/target/linux/apm821xx/patches-6.6/201-add-amcc-apollo3g-support.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/powerpc/platforms/44x/Kconfig -+++ b/arch/powerpc/platforms/44x/Kconfig -@@ -118,6 +118,17 @@ config CANYONLANDS - help - This option enables support for the AMCC PPC460EX evaluation board. - -+config APOLLO3G -+ bool "Apollo3G" -+ depends on 44x -+ default n -+ select PPC44x_SIMPLE -+ select APM821xx -+ select IBM_EMAC_RGMII -+ select 460EX -+ help -+ This option enables support for the AMCC Apollo 3G board. -+ - config GLACIER - bool "Glacier" - depends on 44x ---- a/arch/powerpc/platforms/44x/ppc44x_simple.c -+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c -@@ -46,6 +46,7 @@ machine_device_initcall(ppc44x_simple, p - * board.c file for it rather than adding it to this list. - */ - static char *board[] __initdata = { -+ "amcc,apollo3g", - "amcc,arches", - "amcc,bamboo", - "apm,bluestone", diff --git a/target/linux/apm821xx/patches-6.6/300-fix-atheros-nics-on-apm82181.patch b/target/linux/apm821xx/patches-6.6/300-fix-atheros-nics-on-apm82181.patch deleted file mode 100644 index 48c57acde8..0000000000 --- a/target/linux/apm821xx/patches-6.6/300-fix-atheros-nics-on-apm82181.patch +++ /dev/null @@ -1,51 +0,0 @@ ---- a/arch/powerpc/platforms/4xx/pci.c -+++ b/arch/powerpc/platforms/4xx/pci.c -@@ -1058,15 +1058,24 @@ static int __init apm821xx_pciex_init_po - u32 val; - - /* -- * Do a software reset on PCIe ports. -- * This code is to fix the issue that pci drivers doesn't re-assign -- * bus number for PCIE devices after Uboot -- * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000 -- * PT quad port, SAS LSI 1064E) -+ * Only reset the PHY when no link is currently established. -+ * This is for the Atheros PCIe board which has problems to establish -+ * the link (again) after this PHY reset. All other currently tested -+ * PCIe boards don't show this problem. - */ -- -- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); -- mdelay(10); -+ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); -+ if (!(val & 0x00001000)) { -+ /* -+ * Do a software reset on PCIe ports. -+ * This code is to fix the issue that pci drivers doesn't re-assign -+ * bus number for PCIE devices after Uboot -+ * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000 -+ * PT quad port, SAS LSI 1064E) -+ */ -+ -+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); -+ mdelay(10); -+ } - - if (port->endpoint) - val = PTYPE_LEGACY_ENDPOINT << 20; -@@ -1083,9 +1092,12 @@ static int __init apm821xx_pciex_init_po - mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); - mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); - -- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); -- mdelay(50); -- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); -+ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); -+ if (!(val & 0x00001000)) { -+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); -+ mdelay(50); -+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); -+ } - - mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, - mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | diff --git a/target/linux/apm821xx/patches-6.6/301-fix-memory-map-wndr4700.patch b/target/linux/apm821xx/patches-6.6/301-fix-memory-map-wndr4700.patch deleted file mode 100644 index bd022ca220..0000000000 --- a/target/linux/apm821xx/patches-6.6/301-fix-memory-map-wndr4700.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/arch/powerpc/platforms/4xx/pci.c -+++ b/arch/powerpc/platforms/4xx/pci.c -@@ -1900,9 +1900,9 @@ static void __init ppc4xx_configure_pcie - * if it works - */ - out_le32(mbase + PECFG_PIM0LAL, 0x00000000); -- out_le32(mbase + PECFG_PIM0LAH, 0x00000000); -+ out_le32(mbase + PECFG_PIM0LAH, 0x00000008); - out_le32(mbase + PECFG_PIM1LAL, 0x00000000); -- out_le32(mbase + PECFG_PIM1LAH, 0x00000000); -+ out_le32(mbase + PECFG_PIM1LAH, 0x0000000c); - out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); - out_le32(mbase + PECFG_PIM01SAL, 0x00000000); - diff --git a/target/linux/apm821xx/patches-6.6/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch b/target/linux/apm821xx/patches-6.6/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch deleted file mode 100644 index dcc82546a2..0000000000 --- a/target/linux/apm821xx/patches-6.6/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch +++ /dev/null @@ -1,29 +0,0 @@ -From c9395ad54e2cabb87d408becc37566f3d8248933 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sun, 1 Dec 2019 02:08:23 +0100 -Subject: [PATCH] powerpc: bootwrapper: force gzip as mkimage's compression - method - -Due to CONFIG_KERNEL_XZ symbol, the bootwrapper code tries to -instruct the mkimage to use the xz compression, which isn't -supported. This patch forces the gzip compression, which is -supported and doesn't matter because the generated uImage for -the apm821xx target gets ignored as the OpenWrt toolchain will -do separate U-Boot kernel images for each device individually. - -Signed-off-by: Christian Lamparter ---- - arch/powerpc/boot/Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/powerpc/boot/Makefile -+++ b/arch/powerpc/boot/Makefile -@@ -277,7 +277,7 @@ compressor-$(CONFIG_KERNEL_LZO) := lzo - - # args (to if_changed): 1 = (this rule), 2 = platform, 3 = dts 4=dtb 5=initrd - quiet_cmd_wrap = WRAP $@ -- cmd_wrap =$(CONFIG_SHELL) $(wrapper) -Z $(compressor-y) -c -o $@ -p $2 \ -+ cmd_wrap =$(CONFIG_SHELL) $(wrapper) -Z gzip -c -o $@ -p $2 \ - $(CROSSWRAP) $(if $3, -s $3)$(if $4, -d $4)$(if $5, -i $5) \ - vmlinux - diff --git a/target/linux/at91/Makefile b/target/linux/at91/Makefile index 752ac4c398..467ff0824a 100644 --- a/target/linux/at91/Makefile +++ b/target/linux/at91/Makefile @@ -11,6 +11,7 @@ FEATURES:=ext4 squashfs targz usbgadget ubifs SUBTARGETS:=sama7 sama5 sam9x KERNEL_PATCHVER:=6.6 +KERNEL_TESTING_PATCHVER:=6.12 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/at91/sam9x/config-6.12 b/target/linux/at91/sam9x/config-6.12 new file mode 100644 index 0000000000..0cafecf83c --- /dev/null +++ b/target/linux/at91/sam9x/config-6.12 @@ -0,0 +1,346 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_AT91=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_V4 is not set +CONFIG_ARCH_MULTI_V4T=y +CONFIG_ARCH_MULTI_V4_V5=y +CONFIG_ARCH_MULTI_V5=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_HAS_GROUP_RELOCS=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +# CONFIG_AT91RM9200_WATCHDOG is not set +CONFIG_AT91SAM9X_WATCHDOG=y +# CONFIG_AT91_ADC is not set +CONFIG_AT91_SAMA5D2_ADC=y +CONFIG_AT91_SOC_ID=y +# CONFIG_AT91_SOC_SFR is not set +CONFIG_ATMEL_AIC5_IRQ=y +CONFIG_ATMEL_AIC_IRQ=y +CONFIG_ATMEL_CLOCKSOURCE_PIT=y +CONFIG_ATMEL_CLOCKSOURCE_TCB=y +CONFIG_ATMEL_EBI=y +CONFIG_ATMEL_PIT=y +CONFIG_ATMEL_PM=y +CONFIG_ATMEL_SSC=y +CONFIG_ATMEL_ST=y +CONFIG_ATMEL_TCB_CLKSRC=y +CONFIG_AT_HDMAC=y +CONFIG_AT_XDMAC=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_PM=y +CONFIG_BUFFER_HEAD=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_AT91=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CPU_32v4T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_ARM920T=y +CONFIG_CPU_ARM926T=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_CPU_CACHE_V4WT=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_NO_EFFICIENT_FFS=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_PM=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CRC16=y +CONFIG_CRC7=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS_HELPERS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FORCE_NR_CPUS=y +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ATMEL=y +CONFIG_HZ=128 +CONFIG_HZ_FIXED=128 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_AT91=y +# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACB=y +CONFIG_MACB_USE_HWSTAMP=y +# CONFIG_MCHP_EIC is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMORY=y +CONFIG_MFD_AT91_USART=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_MFD_ATMEL_HLCDC=y +CONFIG_MFD_ATMEL_SMC=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y +CONFIG_MICROCHIP_PIT64B=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_AT91=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_OTP is not set +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_GLUEBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DEVMEM=y +CONFIG_NET_EGRESS=y +CONFIG_NET_INGRESS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +# CONFIG_NVMEM_MICROCHIP_OTPC is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +# CONFIG_PINCTRL_AT91PIO4 is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_SLEEP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_AT91_POWEROFF=y +CONFIG_POWER_RESET_AT91_RESET=y +CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_ATMEL=y +CONFIG_PWM_ATMEL_HLCDC_PWM=y +CONFIG_PWM_ATMEL_TCB=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +CONFIG_RTC_DRV_AT91SAM9=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_SAMA5D4_WATCHDOG=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SGL_ALLOC=y +CONFIG_SOC_AT91RM9200=y +CONFIG_SOC_AT91SAM9=y +CONFIG_SOC_BUS=y +CONFIG_SOC_SAM9X60=y +# CONFIG_SOC_SAM9X7 is not set +CONFIG_SOC_SAM_V4_V5=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_AT91_USART is not set +CONFIG_SPI_ATMEL=y +CONFIG_SPI_ATMEL_QUADSPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_SPIDEV=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWPHY=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_ACM=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +# CONFIG_USB_AT91 is not set +# CONFIG_USB_ATMEL_USBA is not set +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_AT91=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_GADGET=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_AT91=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +# CONFIG_VFP is not set +# CONFIG_VIDEO_MICROCHIP_CSI2DC is not set +# CONFIG_VIDEO_MICROCHIP_ISC is not set +# CONFIG_VIDEO_MICROCHIP_XISC is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_XXHASH=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/at91/sama5/config-6.12 b/target/linux/at91/sama5/config-6.12 new file mode 100644 index 0000000000..581335739e --- /dev/null +++ b/target/linux/at91/sama5/config-6.12 @@ -0,0 +1,524 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_AT91=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_AT91_CPUIDLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_HAS_GROUP_RELOCS=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_AT91SAM9X_WATCHDOG=y +CONFIG_AT91_ADC=y +CONFIG_AT91_SAMA5D2_ADC=y +CONFIG_AT91_SOC_ID=y +# CONFIG_AT91_SOC_SFR is not set +CONFIG_ATMEL_AIC5_IRQ=y +# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set +CONFIG_ATMEL_CLOCKSOURCE_TCB=y +CONFIG_ATMEL_EBI=y +CONFIG_ATMEL_PM=y +# CONFIG_ATMEL_SECURE_PM is not set +CONFIG_ATMEL_SSC=y +CONFIG_ATMEL_TCB_CLKSRC=y +CONFIG_AT_HDMAC=y +CONFIG_AT_XDMAC=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BATTERY_ACT8945A=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_PM=y +CONFIG_BUFFER_HEAD=y +CONFIG_CACHE_L2X0=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_AT91=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONTIG_ALLOC=y +CONFIG_COREDUMP=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRASH_DUMP=y +CONFIG_CRASH_RESERVE=y +CONFIG_CRC16=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_GENIV=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_USER=y +CONFIG_DMADEVICES=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS_HELPERS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DNOTIFY=y +CONFIG_DRM=y +CONFIG_DRM_ATMEL_HLCDC=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_DMA_HELPER=y +CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER is not set +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_BRIDGE=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DTC=y +CONFIG_DVB_CORE=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_ELF_CORE=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_FAT_FS=y +CONFIG_FB=y +CONFIG_FB_CORE=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_DMAMEM_HELPERS=y +CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y +CONFIG_FB_SYSMEM_FOPS=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FORCE_NR_CPUS=y +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +# CONFIG_HARDEN_BRANCH_HISTORY is not set +# CONFIG_HARDEN_BRANCH_PREDICTOR is not set +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HDMI=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ATMEL=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_AT91=y +# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +# CONFIG_JFFS2_FS is not set +CONFIG_KCMP=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_QT1070=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEGACY_DIRECT_IO=y +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACB=y +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_MCHP_EIC is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +CONFIG_MEDIA_TUNER=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_MEMORY=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MFD_ACT8945A=y +CONFIG_MFD_AT91_USART=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_MFD_ATMEL_HLCDC=y +CONFIG_MFD_ATMEL_SMC=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +# CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B is not set +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_AT91=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_NEON is not set +CONFIG_NET_DEVMEM=y +CONFIG_NET_EGRESS=y +CONFIG_NET_INGRESS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +# CONFIG_NVMEM_MICROCHIP_OTPC is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_PINCTRL_AT91PIO4=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_SLEEP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_AT91_POWEROFF=y +CONFIG_POWER_RESET_AT91_RESET=y +CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_PRINTK_TIME=y +CONFIG_PROC_VMCORE=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_ATMEL=y +CONFIG_PWM_ATMEL_HLCDC_PWM=y +CONFIG_PWM_ATMEL_TCB=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_ACT8865=y +CONFIG_REGULATOR_ACT8945A=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +# CONFIG_RTC_DRV_AT91SAM9 is not set +# CONFIG_RTC_DRV_CMOS is not set +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_SAMA5D4_WATCHDOG=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SND=y +CONFIG_SND_ARM=y +# CONFIG_SND_AT73C213 is not set +# CONFIG_SND_AT91_SOC_SAM9G20_WM8731 is not set +# CONFIG_SND_AT91_SOC_SAM9X5_WM8731 is not set +CONFIG_SND_ATMEL_SOC=y +CONFIG_SND_ATMEL_SOC_CLASSD=y +CONFIG_SND_ATMEL_SOC_DMA=y +CONFIG_SND_ATMEL_SOC_I2S=y +CONFIG_SND_ATMEL_SOC_PDC=y +# CONFIG_SND_ATMEL_SOC_PDMIC is not set +CONFIG_SND_ATMEL_SOC_SSC=y +CONFIG_SND_ATMEL_SOC_SSC_DMA=y +# CONFIG_SND_ATMEL_SOC_SSC_PDC is not set +# CONFIG_SND_ATMEL_SOC_TSE850_PCM5142 is not set +CONFIG_SND_ATMEL_SOC_WM8904=y +# CONFIG_SND_COMPRESS_OFFLOAD is not set +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_MCHP_SOC_I2S_MCC is not set +# CONFIG_SND_MCHP_SOC_PDMC is not set +# CONFIG_SND_MCHP_SOC_SPDIFRX is not set +# CONFIG_SND_MCHP_SOC_SPDIFTX is not set +CONFIG_SND_PCM=y +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_I2C_AND_SPI=y +CONFIG_SND_SOC_MIKROE_PROTO=y +CONFIG_SND_SOC_WM8731=y +CONFIG_SND_SOC_WM8904=y +CONFIG_SND_SPI=y +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_TIMER=y +CONFIG_SOC_BUS=y +# CONFIG_SOC_LAN966 is not set +CONFIG_SOC_SAMA5=y +CONFIG_SOC_SAMA5D2=y +CONFIG_SOC_SAMA5D3=y +CONFIG_SOC_SAMA5D4=y +# CONFIG_SOC_SAMA7G5 is not set +CONFIG_SOC_SAM_V7=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_AT91_USART is not set +CONFIG_SPI_ATMEL=y +CONFIG_SPI_ATMEL_QUADSPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SQUASHFS is not set +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +# CONFIG_STANDALONE is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWPHY=y +# CONFIG_SWP_EMULATE is not set +CONFIG_SYNC_FILE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_UBIFS_FS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_ACM=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +# CONFIG_USB_AT91 is not set +# CONFIG_USB_ATMEL_USBA is not set +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_AT91=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_GADGET=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_AT91=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +# CONFIG_USB_PWC is not set +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VFAT_FS=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VIDEO=y +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VIDEO_DEV=y +# CONFIG_VIDEO_MICROCHIP_CSI2DC is not set +# CONFIG_VIDEO_MICROCHIP_ISC is not set +# CONFIG_VIDEO_MICROCHIP_XISC is not set +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VMCORE_INFO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XXHASH=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/at91/sama7/config-6.12 b/target/linux/at91/sama7/config-6.12 new file mode 100644 index 0000000000..27a7f52d04 --- /dev/null +++ b/target/linux/at91/sama7/config-6.12 @@ -0,0 +1,430 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_AT91=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_GROUP_RELOCS=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_PATCH_IDIV is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +# CONFIG_AT91SAM9X_WATCHDOG is not set +# CONFIG_AT91_ADC is not set +CONFIG_AT91_SAMA5D2_ADC=y +CONFIG_AT91_SOC_ID=y +# CONFIG_AT91_SOC_SFR is not set +CONFIG_ATMEL_CLOCKSOURCE_TCB=y +# CONFIG_ATMEL_EBI is not set +CONFIG_ATMEL_TCB_CLKSRC=y +# CONFIG_AT_HDMAC is not set +CONFIG_AT_XDMAC=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_SD=y +CONFIG_BUFFER_HEAD=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CAN=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=9 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=256 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk nocache ignore_loglevel" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_AT91=y +# CONFIG_COMPACTION is not set +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTIG_ALLOC=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_AT91_SAMA7G5_FLEXCOM3=y +CONFIG_DEBUG_AT91_UART=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/at91.S" +CONFIG_DEBUG_UART_PHYS=0xe1824200 +CONFIG_DEBUG_UART_VIRT=0xe0824200 +CONFIG_DEBUG_USER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMADEVICES=y +CONFIG_DMATEST=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS_HELPERS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EARLY_PRINTK=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +# CONFIG_EFI_PARTITION is not set +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_FANOTIFY=y +CONFIG_FAT_FS=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FORCE_NR_CPUS=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GRACE_PERIOD=y +# CONFIG_HARDEN_BRANCH_HISTORY is not set +# CONFIG_HARDEN_BRANCH_PREDICTOR is not set +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_AT91=y +# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_CONFIGFS=y +# CONFIG_IIO_HRTIMER_TRIGGER is not set +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_SW_TRIGGER=y +# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_BOOTP is not set +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_LEDS_GPIO=y +CONFIG_LEGACY_DIRECT_IO=y +CONFIG_LIBFDT=y +CONFIG_LOCKD=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_LSM="N" +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACB=y +CONFIG_MACB_USE_HWSTAMP=y +# CONFIG_MCHP_EIC is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +CONFIG_MEMORY=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_MFD_AT91_USART=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y +CONFIG_MICROCHIP_PIT64B=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +# CONFIG_MMC_ATMELMCI is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_AT91=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NEON=y +CONFIG_NET_DEVMEM=y +CONFIG_NET_EGRESS=y +CONFIG_NET_HANDSHAKE=y +CONFIG_NET_INGRESS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NFS_FS=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +# CONFIG_NVMEM_MICROCHIP_OTPC is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCCARD=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_PM_OPP=y +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_AT91_POWEROFF is not set +CONFIG_POWER_RESET_AT91_RESET=y +CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y +CONFIG_PPS=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_ATMEL=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MCP16502=y +CONFIG_ROOT_NFS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +CONFIG_RTC_DRV_AT91SAM9=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_SAMA5D4_WATCHDOG=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SND=y +CONFIG_SND_ATMEL_SOC=y +# CONFIG_SND_ATMEL_SOC_CLASSD is not set +# CONFIG_SND_ATMEL_SOC_I2S is not set +# CONFIG_SND_ATMEL_SOC_PDMIC is not set +# CONFIG_SND_COMPRESS_OFFLOAD is not set +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_MCHP_SOC_I2S_MCC=y +# CONFIG_SND_MCHP_SOC_PDMC is not set +CONFIG_SND_MCHP_SOC_SPDIFRX=y +CONFIG_SND_MCHP_SOC_SPDIFTX=y +CONFIG_SND_PCM=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_SIMPLE_CARD_UTILS=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_MIKROE_PROTO is not set +CONFIG_SND_SOC_PCM5102A=y +CONFIG_SND_SOC_SPDIF=y +CONFIG_SOC_BUS=y +# CONFIG_SOC_LAN966 is not set +# CONFIG_SOC_SAMA5D2 is not set +# CONFIG_SOC_SAMA5D3 is not set +# CONFIG_SOC_SAMA5D4 is not set +CONFIG_SOC_SAMA7=y +CONFIG_SOC_SAMA7G5=y +CONFIG_SOC_SAM_V7=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_AT91_USART is not set +CONFIG_SPI_ATMEL=y +# CONFIG_SPI_ATMEL_QUADSPI is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_STACKTRACE=y +# CONFIG_STANDALONE is not set +CONFIG_SUNRPC=y +# CONFIG_SWAP is not set +CONFIG_SWPHY=y +# CONFIG_SWP_EMULATE is not set +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USE_OF=y +CONFIG_VFAT_FS=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VIDEO_DEV=y +# CONFIG_VIDEO_MICROCHIP_CSI2DC is not set +# CONFIG_VIDEO_MICROCHIP_ISC is not set +# CONFIG_VIDEO_MICROCHIP_XISC is not set +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/bmips/patches-6.12/110-net-dsa-b53-bcm531x5-fix-cpu-rgmii-mode-interpretation.patch b/target/linux/bmips/patches-6.12/110-net-dsa-b53-bcm531x5-fix-cpu-rgmii-mode-interpretation.patch index e27c4cd98f..fc2a9caadf 100644 --- a/target/linux/bmips/patches-6.12/110-net-dsa-b53-bcm531x5-fix-cpu-rgmii-mode-interpretation.patch +++ b/target/linux/bmips/patches-6.12/110-net-dsa-b53-bcm531x5-fix-cpu-rgmii-mode-interpretation.patch @@ -58,7 +58,7 @@ Signed-off-by: Jonas Gorski + the phy interface, but actually requires internal delays enabled. --- a/drivers/net/dsa/b53/b53_common.c +++ b/drivers/net/dsa/b53/b53_common.c -@@ -1435,6 +1435,16 @@ static void b53_adjust_531x5_rgmii(struc +@@ -1447,6 +1447,16 @@ static void b53_adjust_531x5_rgmii(struc else off = B53_RGMII_CTRL_P(port); @@ -75,7 +75,7 @@ Signed-off-by: Jonas Gorski /* Configure the port RGMII clock delay by DLL disabled and * tx_clk aligned timing (restoring to reset defaults) */ -@@ -1446,19 +1456,24 @@ static void b53_adjust_531x5_rgmii(struc +@@ -1458,19 +1468,24 @@ static void b53_adjust_531x5_rgmii(struc * account for this internal delay that is inserted, otherwise * the switch won't be able to receive correctly. * diff --git a/target/linux/generic/backport-6.12/610-03-v6.15-net-dsa-b53-mdio-add-support-for-BCM53101.patch b/target/linux/generic/backport-6.12/610-02-v6.15-net-dsa-b53-mdio-add-support-for-BCM53101.patch similarity index 100% rename from target/linux/generic/backport-6.12/610-03-v6.15-net-dsa-b53-mdio-add-support-for-BCM53101.patch rename to target/linux/generic/backport-6.12/610-02-v6.15-net-dsa-b53-mdio-add-support-for-BCM53101.patch diff --git a/target/linux/generic/backport-6.12/610-04-v6.16-net-dsa-b53-implement-setting-ageing-time.patch b/target/linux/generic/backport-6.12/610-03-v6.16-net-dsa-b53-implement-setting-ageing-time.patch similarity index 100% rename from target/linux/generic/backport-6.12/610-04-v6.16-net-dsa-b53-implement-setting-ageing-time.patch rename to target/linux/generic/backport-6.12/610-03-v6.16-net-dsa-b53-implement-setting-ageing-time.patch diff --git a/target/linux/generic/backport-6.12/610-07-v6.16-net-dsa-b53-do-not-configure-bcm63xx-s-IMP-port-inte.patch b/target/linux/generic/backport-6.12/610-04-v6.16-net-dsa-b53-do-not-configure-bcm63xx-s-IMP-port-inte.patch similarity index 100% rename from target/linux/generic/backport-6.12/610-07-v6.16-net-dsa-b53-do-not-configure-bcm63xx-s-IMP-port-inte.patch rename to target/linux/generic/backport-6.12/610-04-v6.16-net-dsa-b53-do-not-configure-bcm63xx-s-IMP-port-inte.patch diff --git a/target/linux/generic/backport-6.12/612-02-v6.17-net-dsa-tag_brcm-add-support-for-legacy-FCS-tags.patch b/target/linux/generic/backport-6.12/611-01-v6.17-net-dsa-tag_brcm-add-support-for-legacy-FCS-tags.patch similarity index 100% rename from target/linux/generic/backport-6.12/612-02-v6.17-net-dsa-tag_brcm-add-support-for-legacy-FCS-tags.patch rename to target/linux/generic/backport-6.12/611-01-v6.17-net-dsa-tag_brcm-add-support-for-legacy-FCS-tags.patch diff --git a/target/linux/generic/backport-6.12/612-03-v6.17-net-dsa-b53-support-legacy-FCS-tags.patch b/target/linux/generic/backport-6.12/611-02-v6.17-net-dsa-b53-support-legacy-FCS-tags.patch similarity index 100% rename from target/linux/generic/backport-6.12/612-03-v6.17-net-dsa-b53-support-legacy-FCS-tags.patch rename to target/linux/generic/backport-6.12/611-02-v6.17-net-dsa-b53-support-legacy-FCS-tags.patch diff --git a/target/linux/generic/backport-6.12/612-04-v6.17-net-dsa-b53-detect-BCM5325-variants.patch b/target/linux/generic/backport-6.12/611-03-v6.17-net-dsa-b53-detect-BCM5325-variants.patch similarity index 100% rename from target/linux/generic/backport-6.12/612-04-v6.17-net-dsa-b53-detect-BCM5325-variants.patch rename to target/linux/generic/backport-6.12/611-03-v6.17-net-dsa-b53-detect-BCM5325-variants.patch diff --git a/target/linux/generic/backport-6.12/612-05-v6.17-net-dsa-b53-add-support-for-FDB-operations-on-5325-5365.patch b/target/linux/generic/backport-6.12/611-04-v6.17-net-dsa-b53-add-support-for-FDB-operations-on-5325-5365.patch similarity index 100% rename from target/linux/generic/backport-6.12/612-05-v6.17-net-dsa-b53-add-support-for-FDB-operations-on-5325-5365.patch rename to target/linux/generic/backport-6.12/611-04-v6.17-net-dsa-b53-add-support-for-FDB-operations-on-5325-5365.patch diff --git a/target/linux/generic/backport-6.12/612-06-v6.17-net-dsa-b53-prevent-FAST_AGE-access-on-BCM5325.patch b/target/linux/generic/backport-6.12/611-05-v6.17-net-dsa-b53-prevent-FAST_AGE-access-on-BCM5325.patch similarity index 100% rename from target/linux/generic/backport-6.12/612-06-v6.17-net-dsa-b53-prevent-FAST_AGE-access-on-BCM5325.patch rename to target/linux/generic/backport-6.12/611-05-v6.17-net-dsa-b53-prevent-FAST_AGE-access-on-BCM5325.patch diff --git a/target/linux/generic/backport-6.12/612-10-v6.17-net-dsa-b53-prevent-BRCM_HDR-access-on-older-devices.patch b/target/linux/generic/backport-6.12/611-06-v6.17-net-dsa-b53-prevent-BRCM_HDR-access-on-older-devices.patch similarity index 100% rename from target/linux/generic/backport-6.12/612-10-v6.17-net-dsa-b53-prevent-BRCM_HDR-access-on-older-devices.patch rename to target/linux/generic/backport-6.12/611-06-v6.17-net-dsa-b53-prevent-BRCM_HDR-access-on-older-devices.patch diff --git a/target/linux/generic/backport-6.12/612-12-v6.17-net-dsa-b53-fix-unicast-multicast-flooding-on-BCM5325.patch b/target/linux/generic/backport-6.12/611-07-v6.17-net-dsa-b53-fix-unicast-multicast-flooding-on-BCM5325.patch similarity index 100% rename from target/linux/generic/backport-6.12/612-12-v6.17-net-dsa-b53-fix-unicast-multicast-flooding-on-BCM5325.patch rename to target/linux/generic/backport-6.12/611-07-v6.17-net-dsa-b53-fix-unicast-multicast-flooding-on-BCM5325.patch diff --git a/target/linux/generic/backport-6.12/611-08-v6.18-net-dsa-b53-Add-phy_enable-phy_disable-methods.patch b/target/linux/generic/backport-6.12/611-08-v6.18-net-dsa-b53-Add-phy_enable-phy_disable-methods.patch new file mode 100644 index 0000000000..14106e3dd2 --- /dev/null +++ b/target/linux/generic/backport-6.12/611-08-v6.18-net-dsa-b53-Add-phy_enable-phy_disable-methods.patch @@ -0,0 +1,50 @@ +From be7a79145d85af1a9d65a45560b9243b13a67782 Mon Sep 17 00:00:00 2001 +From: Kyle Hendry +Date: Wed, 23 Jul 2025 20:52:40 -0700 +Subject: [PATCH] net: dsa: b53: Add phy_enable(), phy_disable() methods + +Add phy enable/disable to b53 ops to be called when +enabling/disabling ports. + +Signed-off-by: Kyle Hendry +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250724035300.20497-2-kylehendrydev@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 6 ++++++ + drivers/net/dsa/b53/b53_priv.h | 2 ++ + 2 files changed, 8 insertions(+) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -689,6 +689,9 @@ int b53_enable_port(struct dsa_switch *d + + cpu_port = dsa_to_port(ds, port)->cpu_dp->index; + ++ if (dev->ops->phy_enable) ++ dev->ops->phy_enable(dev, port); ++ + if (dev->ops->irq_enable) + ret = dev->ops->irq_enable(dev, port); + if (ret) +@@ -727,6 +730,9 @@ void b53_disable_port(struct dsa_switch + reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; + b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); + ++ if (dev->ops->phy_disable) ++ dev->ops->phy_disable(dev, port); ++ + if (dev->ops->irq_disable) + dev->ops->irq_disable(dev, port); + } +--- a/drivers/net/dsa/b53/b53_priv.h ++++ b/drivers/net/dsa/b53/b53_priv.h +@@ -45,6 +45,8 @@ struct b53_io_ops { + int (*phy_write16)(struct b53_device *dev, int addr, int reg, u16 value); + int (*irq_enable)(struct b53_device *dev, int port); + void (*irq_disable)(struct b53_device *dev, int port); ++ void (*phy_enable)(struct b53_device *dev, int port); ++ void (*phy_disable)(struct b53_device *dev, int port); + void (*phylink_get_caps)(struct b53_device *dev, int port, + struct phylink_config *config); + struct phylink_pcs *(*phylink_mac_select_pcs)(struct b53_device *dev, diff --git a/target/linux/generic/backport-6.12/611-09-v6.18-net-dsa-b53-Define-chip-IDs-for-more-bcm63xx-SoCs.patch b/target/linux/generic/backport-6.12/611-09-v6.18-net-dsa-b53-Define-chip-IDs-for-more-bcm63xx-SoCs.patch new file mode 100644 index 0000000000..87ce5f9534 --- /dev/null +++ b/target/linux/generic/backport-6.12/611-09-v6.18-net-dsa-b53-Define-chip-IDs-for-more-bcm63xx-SoCs.patch @@ -0,0 +1,124 @@ +From fcf02a462fab52fbfcb24e617dd940745afd0dff Mon Sep 17 00:00:00 2001 +From: Kyle Hendry +Date: Wed, 23 Jul 2025 20:52:42 -0700 +Subject: [PATCH] net: dsa: b53: Define chip IDs for more bcm63xx SoCs + +Add defines for bcm6318, bcm6328, bcm6362, bcm6368 chip IDs, +update tables and switch init. + +Signed-off-by: Kyle Hendry +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250724035300.20497-4-kylehendrydev@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 21 ++++++--------------- + drivers/net/dsa/b53/b53_mmap.c | 8 ++++---- + drivers/net/dsa/b53/b53_priv.h | 13 +++++++++++-- + 3 files changed, 21 insertions(+), 21 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -1419,7 +1419,7 @@ static void b53_adjust_63xx_rgmii(struct + b53_read8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_P(port), &rgmii_ctrl); + rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); + +- if (is63268(dev)) ++ if (is6318_268(dev)) + rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE; + + rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII; +@@ -2801,19 +2801,6 @@ static const struct b53_chip_data b53_sw + .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, + }, + { +- .chip_id = BCM63268_DEVICE_ID, +- .dev_name = "BCM63268", +- .vlans = 4096, +- .enabled_ports = 0, /* pdata must provide them */ +- .arl_bins = 4, +- .arl_buckets = 1024, +- .imp_port = 8, +- .vta_regs = B53_VTA_REGS_63XX, +- .duplex_reg = B53_DUPLEX_STAT_63XX, +- .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, +- .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, +- }, +- { + .chip_id = BCM53010_DEVICE_ID, + .dev_name = "BCM53010", + .vlans = 4096, +@@ -2962,13 +2949,17 @@ static const struct b53_chip_data b53_sw + + static int b53_switch_init(struct b53_device *dev) + { ++ u32 chip_id = dev->chip_id; + unsigned int i; + int ret; + ++ if (is63xx(dev)) ++ chip_id = BCM63XX_DEVICE_ID; ++ + for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { + const struct b53_chip_data *chip = &b53_switch_chips[i]; + +- if (chip->chip_id == dev->chip_id) { ++ if (chip->chip_id == chip_id) { + if (!dev->enabled_ports) + dev->enabled_ports = chip->enabled_ports; + dev->name = chip->dev_name; +--- a/drivers/net/dsa/b53/b53_mmap.c ++++ b/drivers/net/dsa/b53/b53_mmap.c +@@ -348,16 +348,16 @@ static const struct of_device_id b53_mma + .data = (void *)BCM63XX_DEVICE_ID, + }, { + .compatible = "brcm,bcm6318-switch", +- .data = (void *)BCM63268_DEVICE_ID, ++ .data = (void *)BCM6318_DEVICE_ID, + }, { + .compatible = "brcm,bcm6328-switch", +- .data = (void *)BCM63XX_DEVICE_ID, ++ .data = (void *)BCM6328_DEVICE_ID, + }, { + .compatible = "brcm,bcm6362-switch", +- .data = (void *)BCM63XX_DEVICE_ID, ++ .data = (void *)BCM6362_DEVICE_ID, + }, { + .compatible = "brcm,bcm6368-switch", +- .data = (void *)BCM63XX_DEVICE_ID, ++ .data = (void *)BCM6368_DEVICE_ID, + }, { + .compatible = "brcm,bcm63268-switch", + .data = (void *)BCM63268_DEVICE_ID, +--- a/drivers/net/dsa/b53/b53_priv.h ++++ b/drivers/net/dsa/b53/b53_priv.h +@@ -73,6 +73,10 @@ enum { + BCM53125_DEVICE_ID = 0x53125, + BCM53128_DEVICE_ID = 0x53128, + BCM63XX_DEVICE_ID = 0x6300, ++ BCM6318_DEVICE_ID = 0x6318, ++ BCM6328_DEVICE_ID = 0x6328, ++ BCM6362_DEVICE_ID = 0x6362, ++ BCM6368_DEVICE_ID = 0x6368, + BCM63268_DEVICE_ID = 0x63268, + BCM53010_DEVICE_ID = 0x53010, + BCM53011_DEVICE_ID = 0x53011, +@@ -220,12 +224,17 @@ static inline int is531x5(struct b53_dev + static inline int is63xx(struct b53_device *dev) + { + return dev->chip_id == BCM63XX_DEVICE_ID || ++ dev->chip_id == BCM6318_DEVICE_ID || ++ dev->chip_id == BCM6328_DEVICE_ID || ++ dev->chip_id == BCM6362_DEVICE_ID || ++ dev->chip_id == BCM6368_DEVICE_ID || + dev->chip_id == BCM63268_DEVICE_ID; + } + +-static inline int is63268(struct b53_device *dev) ++static inline int is6318_268(struct b53_device *dev) + { +- return dev->chip_id == BCM63268_DEVICE_ID; ++ return dev->chip_id == BCM6318_DEVICE_ID || ++ dev->chip_id == BCM63268_DEVICE_ID; + } + + static inline int is5301x(struct b53_device *dev) diff --git a/target/linux/generic/backport-6.12/611-10-v6.18-net-dsa-b53-mmap-Add-syscon-reference-and-register-layout-for-bcm63268.patch b/target/linux/generic/backport-6.12/611-10-v6.18-net-dsa-b53-mmap-Add-syscon-reference-and-register-layout-for-bcm63268.patch new file mode 100644 index 0000000000..92e540d384 --- /dev/null +++ b/target/linux/generic/backport-6.12/611-10-v6.18-net-dsa-b53-mmap-Add-syscon-reference-and-register-layout-for-bcm63268.patch @@ -0,0 +1,69 @@ +From aed2aaa3c963f8aabbfa061a177022fee826ebfb Mon Sep 17 00:00:00 2001 +From: Kyle Hendry +Date: Wed, 23 Jul 2025 20:52:43 -0700 +Subject: [PATCH] net: dsa: b53: mmap: Add syscon reference and register layout + for bcm63268 + +On bcm63xx SoCs there are registers that control the PHYs in +the GPIO controller. Allow the b53 driver to access them +by passing in the syscon through the device tree. + +Add a structure to describe the ephy control register +and add register info for bcm63268. + +Signed-off-by: Kyle Hendry +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250724035300.20497-5-kylehendrydev@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_mmap.c | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/drivers/net/dsa/b53/b53_mmap.c ++++ b/drivers/net/dsa/b53/b53_mmap.c +@@ -21,13 +21,32 @@ + #include + #include + #include ++#include + #include + #include + + #include "b53_priv.h" + ++struct b53_phy_info { ++ u32 ephy_enable_mask; ++ u32 ephy_port_mask; ++ u32 ephy_bias_bit; ++ const u32 *ephy_offset; ++}; ++ + struct b53_mmap_priv { + void __iomem *regs; ++ struct regmap *gpio_ctrl; ++ const struct b53_phy_info *phy_info; ++}; ++ ++static const u32 bcm63268_ephy_offsets[] = {4, 9, 14}; ++ ++static const struct b53_phy_info bcm63268_ephy_info = { ++ .ephy_enable_mask = GENMASK(4, 0), ++ .ephy_port_mask = GENMASK((ARRAY_SIZE(bcm63268_ephy_offsets) - 1), 0), ++ .ephy_bias_bit = 24, ++ .ephy_offset = bcm63268_ephy_offsets, + }; + + static int b53_mmap_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) +@@ -313,6 +332,12 @@ static int b53_mmap_probe(struct platfor + + priv->regs = pdata->regs; + ++ priv->gpio_ctrl = syscon_regmap_lookup_by_phandle(np, "brcm,gpio-ctrl"); ++ if (!IS_ERR(priv->gpio_ctrl)) { ++ if (pdata->chip_id == BCM63268_DEVICE_ID) ++ priv->phy_info = &bcm63268_ephy_info; ++ } ++ + dev = b53_switch_alloc(&pdev->dev, &b53_mmap_ops, priv); + if (!dev) + return -ENOMEM; diff --git a/target/linux/generic/backport-6.12/611-11-v6.18-net-dsa-b53-mmap-Add-register-layout-for-bcm6318.patch b/target/linux/generic/backport-6.12/611-11-v6.18-net-dsa-b53-mmap-Add-register-layout-for-bcm6318.patch new file mode 100644 index 0000000000..f6c1cbaf01 --- /dev/null +++ b/target/linux/generic/backport-6.12/611-11-v6.18-net-dsa-b53-mmap-Add-register-layout-for-bcm6318.patch @@ -0,0 +1,47 @@ +From c251304ab021ff21c77e83e0babcb9eb76f8787a Mon Sep 17 00:00:00 2001 +From: Kyle Hendry +Date: Wed, 23 Jul 2025 20:52:44 -0700 +Subject: [PATCH] net: dsa: b53: mmap: Add register layout for bcm6318 + +Add ephy register info for bcm6318, which also applies to +bcm6328 and bcm6362. + +Signed-off-by: Kyle Hendry +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250724035300.20497-6-kylehendrydev@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_mmap.c | 15 ++++++++++++++- + 1 file changed, 14 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/b53/b53_mmap.c ++++ b/drivers/net/dsa/b53/b53_mmap.c +@@ -40,6 +40,15 @@ struct b53_mmap_priv { + const struct b53_phy_info *phy_info; + }; + ++static const u32 bcm6318_ephy_offsets[] = {4, 5, 6, 7}; ++ ++static const struct b53_phy_info bcm6318_ephy_info = { ++ .ephy_enable_mask = BIT(0) | BIT(4) | BIT(8) | BIT(12) | BIT(16), ++ .ephy_port_mask = GENMASK((ARRAY_SIZE(bcm6318_ephy_offsets) - 1), 0), ++ .ephy_bias_bit = 24, ++ .ephy_offset = bcm6318_ephy_offsets, ++}; ++ + static const u32 bcm63268_ephy_offsets[] = {4, 9, 14}; + + static const struct b53_phy_info bcm63268_ephy_info = { +@@ -334,7 +343,11 @@ static int b53_mmap_probe(struct platfor + + priv->gpio_ctrl = syscon_regmap_lookup_by_phandle(np, "brcm,gpio-ctrl"); + if (!IS_ERR(priv->gpio_ctrl)) { +- if (pdata->chip_id == BCM63268_DEVICE_ID) ++ if (pdata->chip_id == BCM6318_DEVICE_ID || ++ pdata->chip_id == BCM6328_DEVICE_ID || ++ pdata->chip_id == BCM6362_DEVICE_ID) ++ priv->phy_info = &bcm6318_ephy_info; ++ else if (pdata->chip_id == BCM63268_DEVICE_ID) + priv->phy_info = &bcm63268_ephy_info; + } + diff --git a/target/linux/generic/backport-6.12/611-12-v6.18-net-dsa-b53-mmap-Add-register-layout-for-bcm6368.patch b/target/linux/generic/backport-6.12/611-12-v6.18-net-dsa-b53-mmap-Add-register-layout-for-bcm6368.patch new file mode 100644 index 0000000000..f703804a40 --- /dev/null +++ b/target/linux/generic/backport-6.12/611-12-v6.18-net-dsa-b53-mmap-Add-register-layout-for-bcm6368.patch @@ -0,0 +1,42 @@ +From e8e13073dff7052b144d002bae2cfe9ddfa27e2a Mon Sep 17 00:00:00 2001 +From: Kyle Hendry +Date: Wed, 23 Jul 2025 20:52:45 -0700 +Subject: [PATCH] net: dsa: b53: mmap: Add register layout for bcm6368 + +Add ephy register info for bcm6368. + +Signed-off-by: Kyle Hendry +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250724035300.20497-7-kylehendrydev@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_mmap.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/drivers/net/dsa/b53/b53_mmap.c ++++ b/drivers/net/dsa/b53/b53_mmap.c +@@ -49,6 +49,15 @@ static const struct b53_phy_info bcm6318 + .ephy_offset = bcm6318_ephy_offsets, + }; + ++static const u32 bcm6368_ephy_offsets[] = {2, 3, 4, 5}; ++ ++static const struct b53_phy_info bcm6368_ephy_info = { ++ .ephy_enable_mask = BIT(0), ++ .ephy_port_mask = GENMASK((ARRAY_SIZE(bcm6368_ephy_offsets) - 1), 0), ++ .ephy_bias_bit = 0, ++ .ephy_offset = bcm6368_ephy_offsets, ++}; ++ + static const u32 bcm63268_ephy_offsets[] = {4, 9, 14}; + + static const struct b53_phy_info bcm63268_ephy_info = { +@@ -347,6 +356,8 @@ static int b53_mmap_probe(struct platfor + pdata->chip_id == BCM6328_DEVICE_ID || + pdata->chip_id == BCM6362_DEVICE_ID) + priv->phy_info = &bcm6318_ephy_info; ++ else if (pdata->chip_id == BCM6368_DEVICE_ID) ++ priv->phy_info = &bcm6368_ephy_info; + else if (pdata->chip_id == BCM63268_DEVICE_ID) + priv->phy_info = &bcm63268_ephy_info; + } diff --git a/target/linux/generic/backport-6.12/611-13-v6.18-net-dsa-b53-mmap-Implement-bcm63xx-ephy-power-control.patch b/target/linux/generic/backport-6.12/611-13-v6.18-net-dsa-b53-mmap-Implement-bcm63xx-ephy-power-control.patch new file mode 100644 index 0000000000..bf3aeb7047 --- /dev/null +++ b/target/linux/generic/backport-6.12/611-13-v6.18-net-dsa-b53-mmap-Implement-bcm63xx-ephy-power-control.patch @@ -0,0 +1,100 @@ +From 5ac00023852d960528a0c1d10ae6c17893fc4113 Mon Sep 17 00:00:00 2001 +From: Kyle Hendry +Date: Wed, 23 Jul 2025 20:52:46 -0700 +Subject: [PATCH] net: dsa: b53: mmap: Implement bcm63xx ephy power control + +Implement the phy enable/disable calls for b53 mmap, and +set the power down registers in the ephy control register +appropriately. + +Signed-off-by: Kyle Hendry +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250724035300.20497-8-kylehendrydev@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_mmap.c | 50 ++++++++++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +--- a/drivers/net/dsa/b53/b53_mmap.c ++++ b/drivers/net/dsa/b53/b53_mmap.c +@@ -24,9 +24,12 @@ + #include + #include + #include ++#include + + #include "b53_priv.h" + ++#define BCM63XX_EPHY_REG 0x3C ++ + struct b53_phy_info { + u32 ephy_enable_mask; + u32 ephy_port_mask; +@@ -38,6 +41,7 @@ struct b53_mmap_priv { + void __iomem *regs; + struct regmap *gpio_ctrl; + const struct b53_phy_info *phy_info; ++ u32 phys_enabled; + }; + + static const u32 bcm6318_ephy_offsets[] = {4, 5, 6, 7}; +@@ -266,6 +270,50 @@ static int b53_mmap_phy_write16(struct b + return -EIO; + } + ++static int bcm63xx_ephy_set(struct b53_device *dev, int port, bool enable) ++{ ++ struct b53_mmap_priv *priv = dev->priv; ++ const struct b53_phy_info *info = priv->phy_info; ++ struct regmap *gpio_ctrl = priv->gpio_ctrl; ++ u32 mask, val; ++ ++ if (enable) { ++ mask = (info->ephy_enable_mask << info->ephy_offset[port]) ++ | BIT(info->ephy_bias_bit); ++ val = 0; ++ } else { ++ mask = (info->ephy_enable_mask << info->ephy_offset[port]); ++ if (!((priv->phys_enabled & ~BIT(port)) & info->ephy_port_mask)) ++ mask |= BIT(info->ephy_bias_bit); ++ val = mask; ++ } ++ return regmap_update_bits(gpio_ctrl, BCM63XX_EPHY_REG, mask, val); ++} ++ ++static void b53_mmap_phy_enable(struct b53_device *dev, int port) ++{ ++ struct b53_mmap_priv *priv = dev->priv; ++ int ret = 0; ++ ++ if (priv->phy_info && (BIT(port) & priv->phy_info->ephy_port_mask)) ++ ret = bcm63xx_ephy_set(dev, port, true); ++ ++ if (!ret) ++ priv->phys_enabled |= BIT(port); ++} ++ ++static void b53_mmap_phy_disable(struct b53_device *dev, int port) ++{ ++ struct b53_mmap_priv *priv = dev->priv; ++ int ret = 0; ++ ++ if (priv->phy_info && (BIT(port) & priv->phy_info->ephy_port_mask)) ++ ret = bcm63xx_ephy_set(dev, port, false); ++ ++ if (!ret) ++ priv->phys_enabled &= ~BIT(port); ++} ++ + static const struct b53_io_ops b53_mmap_ops = { + .read8 = b53_mmap_read8, + .read16 = b53_mmap_read16, +@@ -279,6 +327,8 @@ static const struct b53_io_ops b53_mmap_ + .write64 = b53_mmap_write64, + .phy_read16 = b53_mmap_phy_read16, + .phy_write16 = b53_mmap_phy_write16, ++ .phy_enable = b53_mmap_phy_enable, ++ .phy_disable = b53_mmap_phy_disable, + }; + + static int b53_mmap_probe_of(struct platform_device *pdev, diff --git a/target/linux/generic/backport-6.12/611-14-v6.18-net-dsa-b53-mmap-Add-gphy-port-to-phy-info-for-bcm63268.patch b/target/linux/generic/backport-6.12/611-14-v6.18-net-dsa-b53-mmap-Add-gphy-port-to-phy-info-for-bcm63268.patch new file mode 100644 index 0000000000..9aa99d234e --- /dev/null +++ b/target/linux/generic/backport-6.12/611-14-v6.18-net-dsa-b53-mmap-Add-gphy-port-to-phy-info-for-bcm63268.patch @@ -0,0 +1,33 @@ +From 7f95f04fe1903a31b61085e3ab1b4730f9d72941 Mon Sep 17 00:00:00 2001 +From: Kyle Hendry +Date: Wed, 13 Aug 2025 17:25:27 -0700 +Subject: [PATCH] net: dsa: b53: mmap: Add gphy port to phy info for bcm63268 + +Add gphy mask to bcm63xx phy info struct and add data for bcm63268 + +Signed-off-by: Kyle Hendry +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250814002530.5866-2-kylehendrydev@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_mmap.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/net/dsa/b53/b53_mmap.c ++++ b/drivers/net/dsa/b53/b53_mmap.c +@@ -31,6 +31,7 @@ + #define BCM63XX_EPHY_REG 0x3C + + struct b53_phy_info { ++ u32 gphy_port_mask; + u32 ephy_enable_mask; + u32 ephy_port_mask; + u32 ephy_bias_bit; +@@ -65,6 +66,7 @@ static const struct b53_phy_info bcm6368 + static const u32 bcm63268_ephy_offsets[] = {4, 9, 14}; + + static const struct b53_phy_info bcm63268_ephy_info = { ++ .gphy_port_mask = BIT(3), + .ephy_enable_mask = GENMASK(4, 0), + .ephy_port_mask = GENMASK((ARRAY_SIZE(bcm63268_ephy_offsets) - 1), 0), + .ephy_bias_bit = 24, diff --git a/target/linux/generic/backport-6.12/611-15-v6.18-net-dsa-b53-mmap-Implement-bcm63268-gphy-power-control.patch b/target/linux/generic/backport-6.12/611-15-v6.18-net-dsa-b53-mmap-Implement-bcm63268-gphy-power-control.patch new file mode 100644 index 0000000000..8dda51e19e --- /dev/null +++ b/target/linux/generic/backport-6.12/611-15-v6.18-net-dsa-b53-mmap-Implement-bcm63268-gphy-power-control.patch @@ -0,0 +1,77 @@ +From 61730ac10ba90c52563861a0119504f6a9be9868 Mon Sep 17 00:00:00 2001 +From: Kyle Hendry +Date: Wed, 13 Aug 2025 17:25:28 -0700 +Subject: [PATCH] net: dsa: b53: mmap: Implement bcm63268 gphy power control + +Add check for gphy in enable/disable phy calls and set power bits +in gphy control register. + +Signed-off-by: Kyle Hendry +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250814002530.5866-3-kylehendrydev@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_mmap.c | 33 +++++++++++++++++++++++++++++---- + 1 file changed, 29 insertions(+), 4 deletions(-) + +--- a/drivers/net/dsa/b53/b53_mmap.c ++++ b/drivers/net/dsa/b53/b53_mmap.c +@@ -29,6 +29,10 @@ + #include "b53_priv.h" + + #define BCM63XX_EPHY_REG 0x3C ++#define BCM63268_GPHY_REG 0x54 ++ ++#define GPHY_CTRL_LOW_PWR BIT(3) ++#define GPHY_CTRL_IDDQ_BIAS BIT(0) + + struct b53_phy_info { + u32 gphy_port_mask; +@@ -292,13 +296,30 @@ static int bcm63xx_ephy_set(struct b53_d + return regmap_update_bits(gpio_ctrl, BCM63XX_EPHY_REG, mask, val); + } + ++static int bcm63268_gphy_set(struct b53_device *dev, bool enable) ++{ ++ struct b53_mmap_priv *priv = dev->priv; ++ struct regmap *gpio_ctrl = priv->gpio_ctrl; ++ u32 mask = GPHY_CTRL_IDDQ_BIAS | GPHY_CTRL_LOW_PWR; ++ u32 val = 0; ++ ++ if (!enable) ++ val = mask; ++ ++ return regmap_update_bits(gpio_ctrl, BCM63268_GPHY_REG, mask, val); ++} ++ + static void b53_mmap_phy_enable(struct b53_device *dev, int port) + { + struct b53_mmap_priv *priv = dev->priv; + int ret = 0; + +- if (priv->phy_info && (BIT(port) & priv->phy_info->ephy_port_mask)) +- ret = bcm63xx_ephy_set(dev, port, true); ++ if (priv->phy_info) { ++ if (BIT(port) & priv->phy_info->ephy_port_mask) ++ ret = bcm63xx_ephy_set(dev, port, true); ++ else if (BIT(port) & priv->phy_info->gphy_port_mask) ++ ret = bcm63268_gphy_set(dev, true); ++ } + + if (!ret) + priv->phys_enabled |= BIT(port); +@@ -309,8 +330,12 @@ static void b53_mmap_phy_disable(struct + struct b53_mmap_priv *priv = dev->priv; + int ret = 0; + +- if (priv->phy_info && (BIT(port) & priv->phy_info->ephy_port_mask)) +- ret = bcm63xx_ephy_set(dev, port, false); ++ if (priv->phy_info) { ++ if (BIT(port) & priv->phy_info->ephy_port_mask) ++ ret = bcm63xx_ephy_set(dev, port, false); ++ else if (BIT(port) & priv->phy_info->gphy_port_mask) ++ ret = bcm63268_gphy_set(dev, false); ++ } + + if (!ret) + priv->phys_enabled &= ~BIT(port); diff --git a/target/linux/generic/backport-6.12/611-16-v6.18-net-dsa-b53-fix-reserved-register-access-in-b53_fdb_dump.patch b/target/linux/generic/backport-6.12/611-16-v6.18-net-dsa-b53-fix-reserved-register-access-in-b53_fdb_dump.patch new file mode 100644 index 0000000000..7ca545840b --- /dev/null +++ b/target/linux/generic/backport-6.12/611-16-v6.18-net-dsa-b53-fix-reserved-register-access-in-b53_fdb_dump.patch @@ -0,0 +1,72 @@ +From 89eb9a62aed77b409663ba1eac152e8f758815b7 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 15 Aug 2025 22:18:09 +0200 +Subject: [PATCH] net: dsa: b53: fix reserved register access in b53_fdb_dump() + +When BCM5325 support was added in c45655386e53 ("net: dsa: b53: add +support for FDB operations on 5325/5365"), the register used for ARL access +was made conditional on the chip. + +But in b53_fdb_dump(), instead of the register argument the page +argument was replaced, causing it to write to a reserved page 0x50 on +!BCM5325*. Writing to this page seems to completely lock the switch up: + +[ 89.680000] b53-switch spi0.1 lan2: Link is Down +[ 89.680000] WARNING: CPU: 1 PID: 26 at drivers/net/phy/phy.c:1350 _phy_state_machine+0x1bc/0x454 +[ 89.720000] phy_check_link_status+0x0/0x114: returned: -5 +[ 89.730000] Modules linked in: nft_fib_inet nf_flow_table_inet nft_reject_ipv6 nft_reject_ipv4 nft_reject_inet nft_reject nft_redir nft_quota nft_numgen nft_nat nft_masq nft_log nft_limit nft_hash nft_flow_offload nft_fib_ipv6 nft_fib_ipv4 nft_fib nft_ct nft_chain_nat nf_tables nf_nat nf_flow_table nf_conntrack nfnetlink nf_reject_ipv6 nf_reject_ipv4 nf_log_syslog nf_defrag_ipv6 nf_defrag_ipv4 cls_flower sch_tbf sch_ingress sch_htb sch_hfsc em_u32 cls_u32 cls_route cls_matchall cls_fw cls_flow cls_basic act_skbedit act_mirred act_gact vrf md5 crc32c_cryptoapi +[ 89.780000] CPU: 1 UID: 0 PID: 26 Comm: kworker/u10:0 Tainted: G W 6.16.0-rc1+ #0 NONE +[ 89.780000] Tainted: [W]=WARN +[ 89.780000] Hardware name: Netgear DGND3700 v1 +[ 89.780000] Workqueue: events_power_efficient phy_state_machine +[ 89.780000] Stack : 809c762c 8006b050 00000001 820a9ce3 0000114c 000affff 805d22d0 8200ba00 +[ 89.780000] 82005000 6576656e 74735f70 6f776572 5f656666 10008b00 820a9cb8 82088700 +[ 89.780000] 00000000 00000000 809c762c 820a9a98 00000000 00000000 ffffefff 80a7a76c +[ 89.780000] 80a70000 820a9af8 80a70000 80a70000 80a70000 00000000 809c762c 820a9dd4 +[ 89.780000] 00000000 805d1494 80a029e4 80a70000 00000003 00000000 00000004 81a60004 +[ 89.780000] ... +[ 89.780000] Call Trace: +[ 89.780000] [<800228b8>] show_stack+0x38/0x118 +[ 89.780000] [<8001afc4>] dump_stack_lvl+0x6c/0xac +[ 89.780000] [<80046b90>] __warn+0x9c/0x114 +[ 89.780000] [<80046da8>] warn_slowpath_fmt+0x1a0/0x1b0 +[ 89.780000] [<805d1494>] _phy_state_machine+0x1bc/0x454 +[ 89.780000] [<805d22fc>] phy_state_machine+0x2c/0x70 +[ 89.780000] [<80066b08>] process_one_work+0x1e8/0x3e0 +[ 89.780000] [<80067a1c>] worker_thread+0x354/0x4e4 +[ 89.780000] [<800706cc>] kthread+0x130/0x274 +[ 89.780000] [<8001d808>] ret_from_kernel_thread+0x14/0x1c + +And any further accesses fail: + +[ 120.790000] b53-switch spi0.1: timeout waiting for ARL to finish: 0x81 +[ 120.800000] b53-switch spi0.1: port 2 failed to add 2c:b0:5d:27:9a:bd vid 3 to fdb: -145 +[ 121.010000] b53-switch spi0.1: timeout waiting for ARL to finish: 0xbf +[ 121.020000] b53-switch spi0.1: port 3 failed to add 2c:b0:5d:27:9a:bd vid 3 to fdb: -145 + +Restore the correct page B53_ARLIO_PAGE again, and move the offset +argument to the correct place. + +*On BCM5325, this became a write to the MIB page of Port 1. Still +a reserved offset, but likely less brokenness from that write. + +Fixes: c45655386e53 ("net: dsa: b53: add support for FDB operations on 5325/5365") +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250815201809.549195-1-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -2097,7 +2097,7 @@ int b53_fdb_dump(struct dsa_switch *ds, + + /* Start search operation */ + reg = ARL_SRCH_STDN; +- b53_write8(priv, offset, B53_ARL_SRCH_CTL, reg); ++ b53_write8(priv, B53_ARLIO_PAGE, offset, reg); + + do { + ret = b53_arl_search_wait(priv); diff --git a/target/linux/generic/backport-6.12/611-17-v6.18-net-dsa-b53-fix-ageing-time-for-BCM53101.patch b/target/linux/generic/backport-6.12/611-17-v6.18-net-dsa-b53-fix-ageing-time-for-BCM53101.patch new file mode 100644 index 0000000000..112fba7291 --- /dev/null +++ b/target/linux/generic/backport-6.12/611-17-v6.18-net-dsa-b53-fix-ageing-time-for-BCM53101.patch @@ -0,0 +1,77 @@ +From 674b34c4c770551e916ae707829c7faea4782d3a Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 5 Sep 2025 14:45:07 +0200 +Subject: [PATCH] net: dsa: b53: fix ageing time for BCM53101 + +For some reason Broadcom decided that BCM53101 uses 0.5s increments for +the ageing time register, but kept the field width the same [1]. Due to +this, the actual ageing time was always half of what was configured. + +Fix this by adapting the limits and value calculation for BCM53101. + +So far it looks like this is the only chip with the increased tick +speed: + +$ grep -l -r "Specifies the aging time in 0.5 seconds" cdk/PKG/chip | sort +cdk/PKG/chip/bcm53101/bcm53101_a0_defs.h + +$ grep -l -r "Specifies the aging time in seconds" cdk/PKG/chip | sort +cdk/PKG/chip/bcm53010/bcm53010_a0_defs.h +cdk/PKG/chip/bcm53020/bcm53020_a0_defs.h +cdk/PKG/chip/bcm53084/bcm53084_a0_defs.h +cdk/PKG/chip/bcm53115/bcm53115_a0_defs.h +cdk/PKG/chip/bcm53118/bcm53118_a0_defs.h +cdk/PKG/chip/bcm53125/bcm53125_a0_defs.h +cdk/PKG/chip/bcm53128/bcm53128_a0_defs.h +cdk/PKG/chip/bcm53134/bcm53134_a0_defs.h +cdk/PKG/chip/bcm53242/bcm53242_a0_defs.h +cdk/PKG/chip/bcm53262/bcm53262_a0_defs.h +cdk/PKG/chip/bcm53280/bcm53280_a0_defs.h +cdk/PKG/chip/bcm53280/bcm53280_b0_defs.h +cdk/PKG/chip/bcm53600/bcm53600_a0_defs.h +cdk/PKG/chip/bcm89500/bcm89500_a0_defs.h + +[1] https://github.com/Broadcom/OpenMDK/blob/a5d3fc9b12af3eeb68f2ca0ce7ec4056cd14d6c2/cdk/PKG/chip/bcm53101/bcm53101_a0_defs.h#L28966 + +Fixes: e39d14a760c0 ("net: dsa: b53: implement setting ageing time") +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250905124507.59186-1-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 17 +++++++++++++---- + 1 file changed, 13 insertions(+), 4 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -1273,9 +1273,15 @@ static int b53_setup(struct dsa_switch * + */ + ds->untag_vlan_aware_bridge_pvid = true; + +- /* Ageing time is set in seconds */ +- ds->ageing_time_min = 1 * 1000; +- ds->ageing_time_max = AGE_TIME_MAX * 1000; ++ if (dev->chip_id == BCM53101_DEVICE_ID) { ++ /* BCM53101 uses 0.5 second increments */ ++ ds->ageing_time_min = 1 * 500; ++ ds->ageing_time_max = AGE_TIME_MAX * 500; ++ } else { ++ /* Everything else uses 1 second increments */ ++ ds->ageing_time_min = 1 * 1000; ++ ds->ageing_time_max = AGE_TIME_MAX * 1000; ++ } + + ret = b53_reset_switch(dev); + if (ret) { +@@ -2584,7 +2590,10 @@ int b53_set_ageing_time(struct dsa_switc + else + reg = B53_AGING_TIME_CONTROL; + +- atc = DIV_ROUND_CLOSEST(msecs, 1000); ++ if (dev->chip_id == BCM53101_DEVICE_ID) ++ atc = DIV_ROUND_CLOSEST(msecs, 500); ++ else ++ atc = DIV_ROUND_CLOSEST(msecs, 1000); + + if (!is5325(dev) && !is5365(dev)) + atc |= AGE_CHANGE; diff --git a/target/linux/generic/backport-6.12/611-18-v6.18-net-dsa-b53-properly-bound-ARL-searches-for-4-ARL-bin-chips.patch b/target/linux/generic/backport-6.12/611-18-v6.18-net-dsa-b53-properly-bound-ARL-searches-for-4-ARL-bin-chips.patch new file mode 100644 index 0000000000..03dc36bd67 --- /dev/null +++ b/target/linux/generic/backport-6.12/611-18-v6.18-net-dsa-b53-properly-bound-ARL-searches-for-4-ARL-bin-chips.patch @@ -0,0 +1,61 @@ +From e57723fe536f040cc2635ec1545dd0a7919a321e Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 2 Nov 2025 11:07:58 +0100 +Subject: [PATCH] net: dsa: b53: properly bound ARL searches for < 4 ARL bin + chips + +When iterating over the ARL table we stop at max ARL entries / 2, but +this is only valid if the chip actually returns 2 results at once. For +chips with only one result register we will stop before reaching the end +of the table if it is more than half full. + +Fix this by only dividing the maximum results by two if we have a chip +with more than one result register (i.e. those with 4 ARL bins). + +Fixes: cd169d799bee ("net: dsa: b53: Bound check ARL searches") +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20251102100758.28352-4-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -2087,13 +2087,16 @@ static int b53_fdb_copy(int port, const + int b53_fdb_dump(struct dsa_switch *ds, int port, + dsa_fdb_dump_cb_t *cb, void *data) + { ++ unsigned int count = 0, results_per_hit = 1; + struct b53_device *priv = ds->priv; + struct b53_arl_entry results[2]; +- unsigned int count = 0; + u8 offset; + int ret; + u8 reg; + ++ if (priv->num_arl_bins > 2) ++ results_per_hit = 2; ++ + mutex_lock(&priv->arl_mutex); + + if (is5325(priv) || is5365(priv)) +@@ -2115,7 +2118,7 @@ int b53_fdb_dump(struct dsa_switch *ds, + if (ret) + break; + +- if (priv->num_arl_bins > 2) { ++ if (results_per_hit == 2) { + b53_arl_search_rd(priv, 1, &results[1]); + ret = b53_fdb_copy(port, &results[1], cb, data); + if (ret) +@@ -2125,7 +2128,7 @@ int b53_fdb_dump(struct dsa_switch *ds, + break; + } + +- } while (count++ < b53_max_arl_entries(priv) / 2); ++ } while (count++ < b53_max_arl_entries(priv) / results_per_hit); + + mutex_unlock(&priv->arl_mutex); + diff --git a/target/linux/generic/backport-6.12/611-19-v6.18-net-dsa-tag_brcm-do-not-mark-link-local-traffic-as-offloaded.patch b/target/linux/generic/backport-6.12/611-19-v6.18-net-dsa-tag_brcm-do-not-mark-link-local-traffic-as-offloaded.patch new file mode 100644 index 0000000000..7c3d06269a --- /dev/null +++ b/target/linux/generic/backport-6.12/611-19-v6.18-net-dsa-tag_brcm-do-not-mark-link-local-traffic-as-offloaded.patch @@ -0,0 +1,59 @@ +From 762e7e174da91cf4babfe77e45bc6b67334b1503 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Nov 2025 14:46:35 +0100 +Subject: [PATCH] net: dsa: tag_brcm: do not mark link local traffic as + offloaded + +Broadcom switches locally terminate link local traffic and do not +forward it, so we should not mark it as offloaded. + +In some situations we still want/need to flood this traffic, e.g. if STP +is disabled, or it is explicitly enabled via the group_fwd_mask. But if +the skb is marked as offloaded, the kernel will assume this was already +done in hardware, and the packets never reach other bridge ports. + +So ensure that link local traffic is never marked as offloaded, so that +the kernel can forward/flood these packets in software if needed. + +Since the local termination in not configurable, check the destination +MAC, and never mark packets as offloaded if it is a link local ether +address. + +While modern switches set the tag reason code to BRCM_EG_RC_PROT_TERM +for trapped link local traffic, they also set it for link local traffic +that is flooded (01:80:c2:00:00:10 to 01:80:c2:00:00:2f), so we cannot +use it and need to look at the destination address for them as well. + +Fixes: 964dbf186eaa ("net: dsa: tag_brcm: add support for legacy tags") +Fixes: 0e62f543bed0 ("net: dsa: Fix duplicate frames flooded by learning") +Signed-off-by: Jonas Gorski +Reviewed-by: Vladimir Oltean +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20251109134635.243951-1-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + net/dsa/tag_brcm.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/net/dsa/tag_brcm.c ++++ b/net/dsa/tag_brcm.c +@@ -176,7 +176,8 @@ static struct sk_buff *brcm_tag_rcv_ll(s + /* Remove Broadcom tag and update checksum */ + skb_pull_rcsum(skb, BRCM_TAG_LEN); + +- dsa_default_offload_fwd_mark(skb); ++ if (likely(!is_link_local_ether_addr(eth_hdr(skb)->h_dest))) ++ dsa_default_offload_fwd_mark(skb); + + return skb; + } +@@ -250,7 +251,8 @@ static struct sk_buff *brcm_leg_tag_rcv( + /* Remove Broadcom tag and update checksum */ + skb_pull_rcsum(skb, len); + +- dsa_default_offload_fwd_mark(skb); ++ if (likely(!is_link_local_ether_addr(eth_hdr(skb)->h_dest))) ++ dsa_default_offload_fwd_mark(skb); + + dsa_strip_etype_header(skb, len); + diff --git a/target/linux/generic/backport-6.12/612-01-v6.19-net-dsa-b53-b53_arl_read-25-use-the-entry-for-comparision.patch b/target/linux/generic/backport-6.12/612-01-v6.19-net-dsa-b53-b53_arl_read-25-use-the-entry-for-comparision.patch new file mode 100644 index 0000000000..2b6cff796f --- /dev/null +++ b/target/linux/generic/backport-6.12/612-01-v6.19-net-dsa-b53-b53_arl_read-25-use-the-entry-for-comparision.patch @@ -0,0 +1,85 @@ +From a6e4fd38bf2f2e2363b61c27f4e6c49b14e4bb07 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 7 Nov 2025 09:07:42 +0100 +Subject: [PATCH] net: dsa: b53: b53_arl_read{,25}(): use the entry for + comparision + +Align the b53_arl_read{,25}() functions by consistently using the +parsed arl entry instead of parsing the raw registers again. + +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20251107080749.26936-2-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 22 ++++++++++------------ + 1 file changed, 10 insertions(+), 12 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -1830,7 +1830,7 @@ static int b53_arl_rw_op(struct b53_devi + return b53_arl_op_wait(dev); + } + +-static int b53_arl_read(struct b53_device *dev, u64 mac, ++static int b53_arl_read(struct b53_device *dev, const u8 *mac, + u16 vid, struct b53_arl_entry *ent, u8 *idx) + { + DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); +@@ -1854,14 +1854,13 @@ static int b53_arl_read(struct b53_devic + B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); + b53_arl_to_entry(ent, mac_vid, fwd_entry); + +- if (!(fwd_entry & ARLTBL_VALID)) { ++ if (!ent->is_valid) { + set_bit(i, free_bins); + continue; + } +- if ((mac_vid & ARLTBL_MAC_MASK) != mac) ++ if (!ether_addr_equal(ent->mac, mac)) + continue; +- if (dev->vlan_enabled && +- ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) ++ if (dev->vlan_enabled && ent->vid != vid) + continue; + *idx = i; + return 0; +@@ -1871,7 +1870,7 @@ static int b53_arl_read(struct b53_devic + return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT; + } + +-static int b53_arl_read_25(struct b53_device *dev, u64 mac, ++static int b53_arl_read_25(struct b53_device *dev, const u8 *mac, + u16 vid, struct b53_arl_entry *ent, u8 *idx) + { + DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); +@@ -1893,14 +1892,13 @@ static int b53_arl_read_25(struct b53_de + + b53_arl_to_entry_25(ent, mac_vid); + +- if (!(mac_vid & ARLTBL_VALID_25)) { ++ if (!ent->is_valid) { + set_bit(i, free_bins); + continue; + } +- if ((mac_vid & ARLTBL_MAC_MASK) != mac) ++ if (!ether_addr_equal(ent->mac, mac)) + continue; +- if (dev->vlan_enabled && +- ((mac_vid >> ARLTBL_VID_S_65) & ARLTBL_VID_MASK_25) != vid) ++ if (dev->vlan_enabled && ent->vid != vid) + continue; + *idx = i; + return 0; +@@ -1933,9 +1931,9 @@ static int b53_arl_op(struct b53_device + return ret; + + if (is5325(dev) || is5365(dev)) +- ret = b53_arl_read_25(dev, mac, vid, &ent, &idx); ++ ret = b53_arl_read_25(dev, addr, vid, &ent, &idx); + else +- ret = b53_arl_read(dev, mac, vid, &ent, &idx); ++ ret = b53_arl_read(dev, addr, vid, &ent, &idx); + + /* If this is a read, just finish now */ + if (op) diff --git a/target/linux/generic/backport-6.12/612-02-v6.19-net-dsa-b53-move-reading-ARL-entries-into-their-own-function.patch b/target/linux/generic/backport-6.12/612-02-v6.19-net-dsa-b53-move-reading-ARL-entries-into-their-own-function.patch new file mode 100644 index 0000000000..8cf85ce7ad --- /dev/null +++ b/target/linux/generic/backport-6.12/612-02-v6.19-net-dsa-b53-move-reading-ARL-entries-into-their-own-function.patch @@ -0,0 +1,117 @@ +From 4a291fe7226736a465ddb3fa93c21fcef7162ec7 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 7 Nov 2025 09:07:43 +0100 +Subject: [PATCH] net: dsa: b53: move reading ARL entries into their own + function + +Instead of duplicating the whole code iterating over all bins for +BCM5325, factor out reading and parsing the entry into its own +functions, and name it the modern one after the first chip with that ARL +format, (BCM53)95. + +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20251107080749.26936-3-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 69 +++++++++++--------------------- + 1 file changed, 23 insertions(+), 46 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -1830,48 +1830,30 @@ static int b53_arl_rw_op(struct b53_devi + return b53_arl_op_wait(dev); + } + +-static int b53_arl_read(struct b53_device *dev, const u8 *mac, +- u16 vid, struct b53_arl_entry *ent, u8 *idx) ++static void b53_arl_read_entry_25(struct b53_device *dev, ++ struct b53_arl_entry *ent, u8 idx) + { +- DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); +- unsigned int i; +- int ret; +- +- ret = b53_arl_op_wait(dev); +- if (ret) +- return ret; ++ u64 mac_vid; + +- bitmap_zero(free_bins, dev->num_arl_bins); +- +- /* Read the bins */ +- for (i = 0; i < dev->num_arl_bins; i++) { +- u64 mac_vid; +- u32 fwd_entry; +- +- b53_read64(dev, B53_ARLIO_PAGE, +- B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); +- b53_read32(dev, B53_ARLIO_PAGE, +- B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); +- b53_arl_to_entry(ent, mac_vid, fwd_entry); ++ b53_read64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), ++ &mac_vid); ++ b53_arl_to_entry_25(ent, mac_vid); ++} + +- if (!ent->is_valid) { +- set_bit(i, free_bins); +- continue; +- } +- if (!ether_addr_equal(ent->mac, mac)) +- continue; +- if (dev->vlan_enabled && ent->vid != vid) +- continue; +- *idx = i; +- return 0; +- } ++static void b53_arl_read_entry_95(struct b53_device *dev, ++ struct b53_arl_entry *ent, u8 idx) ++{ ++ u32 fwd_entry; ++ u64 mac_vid; + +- *idx = find_first_bit(free_bins, dev->num_arl_bins); +- return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT; ++ b53_read64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), ++ &mac_vid); ++ b53_read32(dev, B53_ARLIO_PAGE, B53_ARLTBL_DATA_ENTRY(idx), &fwd_entry); ++ b53_arl_to_entry(ent, mac_vid, fwd_entry); + } + +-static int b53_arl_read_25(struct b53_device *dev, const u8 *mac, +- u16 vid, struct b53_arl_entry *ent, u8 *idx) ++static int b53_arl_read(struct b53_device *dev, const u8 *mac, ++ u16 vid, struct b53_arl_entry *ent, u8 *idx) + { + DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); + unsigned int i; +@@ -1885,12 +1867,10 @@ static int b53_arl_read_25(struct b53_de + + /* Read the bins */ + for (i = 0; i < dev->num_arl_bins; i++) { +- u64 mac_vid; +- +- b53_read64(dev, B53_ARLIO_PAGE, +- B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); +- +- b53_arl_to_entry_25(ent, mac_vid); ++ if (is5325(dev) || is5365(dev)) ++ b53_arl_read_entry_25(dev, ent, i); ++ else ++ b53_arl_read_entry_95(dev, ent, i); + + if (!ent->is_valid) { + set_bit(i, free_bins); +@@ -1930,10 +1910,7 @@ static int b53_arl_op(struct b53_device + if (ret) + return ret; + +- if (is5325(dev) || is5365(dev)) +- ret = b53_arl_read_25(dev, addr, vid, &ent, &idx); +- else +- ret = b53_arl_read(dev, addr, vid, &ent, &idx); ++ ret = b53_arl_read(dev, addr, vid, &ent, &idx); + + /* If this is a read, just finish now */ + if (op) diff --git a/target/linux/generic/backport-6.12/612-03-v6.19-net-dsa-b53-move-writing-ARL-entries-into-their-own-functions.patch b/target/linux/generic/backport-6.12/612-03-v6.19-net-dsa-b53-move-writing-ARL-entries-into-their-own-functions.patch new file mode 100644 index 0000000000..a171232d49 --- /dev/null +++ b/target/linux/generic/backport-6.12/612-03-v6.19-net-dsa-b53-move-writing-ARL-entries-into-their-own-functions.patch @@ -0,0 +1,93 @@ +From bf6e9d2ae1dbafee53ec4ccd126595172e1e5278 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 7 Nov 2025 09:07:44 +0100 +Subject: [PATCH] net: dsa: b53: move writing ARL entries into their own + functions + +Move writing ARL entries into individual functions for each format. + +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20251107080749.26936-4-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 38 ++++++++++++++++++++++---------- + 1 file changed, 26 insertions(+), 12 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -1840,6 +1840,16 @@ static void b53_arl_read_entry_25(struct + b53_arl_to_entry_25(ent, mac_vid); + } + ++static void b53_arl_write_entry_25(struct b53_device *dev, ++ const struct b53_arl_entry *ent, u8 idx) ++{ ++ u64 mac_vid; ++ ++ b53_arl_from_entry_25(&mac_vid, ent); ++ b53_write64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), ++ mac_vid); ++} ++ + static void b53_arl_read_entry_95(struct b53_device *dev, + struct b53_arl_entry *ent, u8 idx) + { +@@ -1852,6 +1862,19 @@ static void b53_arl_read_entry_95(struct + b53_arl_to_entry(ent, mac_vid, fwd_entry); + } + ++static void b53_arl_write_entry_95(struct b53_device *dev, ++ const struct b53_arl_entry *ent, u8 idx) ++{ ++ u32 fwd_entry; ++ u64 mac_vid; ++ ++ b53_arl_from_entry(&mac_vid, &fwd_entry, ent); ++ b53_write64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), ++ mac_vid); ++ b53_write32(dev, B53_ARLIO_PAGE, B53_ARLTBL_DATA_ENTRY(idx), ++ fwd_entry); ++} ++ + static int b53_arl_read(struct b53_device *dev, const u8 *mac, + u16 vid, struct b53_arl_entry *ent, u8 *idx) + { +@@ -1892,9 +1915,8 @@ static int b53_arl_op(struct b53_device + const unsigned char *addr, u16 vid, bool is_valid) + { + struct b53_arl_entry ent; +- u32 fwd_entry; +- u64 mac, mac_vid = 0; + u8 idx = 0; ++ u64 mac; + int ret; + + /* Convert the array into a 64-bit MAC */ +@@ -1927,7 +1949,6 @@ static int b53_arl_op(struct b53_device + /* We could not find a matching MAC, so reset to a new entry */ + dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", + addr, vid, idx); +- fwd_entry = 0; + break; + default: + dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", +@@ -1955,16 +1976,9 @@ static int b53_arl_op(struct b53_device + ent.is_age = false; + memcpy(ent.mac, addr, ETH_ALEN); + if (is5325(dev) || is5365(dev)) +- b53_arl_from_entry_25(&mac_vid, &ent); ++ b53_arl_write_entry_25(dev, &ent, idx); + else +- b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); +- +- b53_write64(dev, B53_ARLIO_PAGE, +- B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); +- +- if (!is5325(dev) && !is5365(dev)) +- b53_write32(dev, B53_ARLIO_PAGE, +- B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); ++ b53_arl_write_entry_95(dev, &ent, idx); + + return b53_arl_rw_op(dev, 0); + } diff --git a/target/linux/generic/backport-6.12/612-04-v6.19-net-dsa-b53-provide-accessors-for-accessing-ARL_SRCH_CTL.patch b/target/linux/generic/backport-6.12/612-04-v6.19-net-dsa-b53-provide-accessors-for-accessing-ARL_SRCH_CTL.patch new file mode 100644 index 0000000000..2ed88e4605 --- /dev/null +++ b/target/linux/generic/backport-6.12/612-04-v6.19-net-dsa-b53-provide-accessors-for-accessing-ARL_SRCH_CTL.patch @@ -0,0 +1,85 @@ +From 1716be6db04af53bac9b869f01156a460595cf41 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 7 Nov 2025 09:07:45 +0100 +Subject: [PATCH] net: dsa: b53: provide accessors for accessing ARL_SRCH_CTL + +In order to more easily support more formats, move accessing +ARL_SRCH_CTL into helper functions to contain the differences. + +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20251107080749.26936-5-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 37 +++++++++++++++++++++----------- + 1 file changed, 24 insertions(+), 13 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -2013,18 +2013,37 @@ int b53_fdb_del(struct dsa_switch *ds, i + } + EXPORT_SYMBOL(b53_fdb_del); + +-static int b53_arl_search_wait(struct b53_device *dev) ++static void b53_read_arl_srch_ctl(struct b53_device *dev, u8 *val) + { +- unsigned int timeout = 1000; +- u8 reg, offset; ++ u8 offset; ++ ++ if (is5325(dev) || is5365(dev)) ++ offset = B53_ARL_SRCH_CTL_25; ++ else ++ offset = B53_ARL_SRCH_CTL; ++ ++ b53_read8(dev, B53_ARLIO_PAGE, offset, val); ++} ++ ++static void b53_write_arl_srch_ctl(struct b53_device *dev, u8 val) ++{ ++ u8 offset; + + if (is5325(dev) || is5365(dev)) + offset = B53_ARL_SRCH_CTL_25; + else + offset = B53_ARL_SRCH_CTL; + ++ b53_write8(dev, B53_ARLIO_PAGE, offset, val); ++} ++ ++static int b53_arl_search_wait(struct b53_device *dev) ++{ ++ unsigned int timeout = 1000; ++ u8 reg; ++ + do { +- b53_read8(dev, B53_ARLIO_PAGE, offset, ®); ++ b53_read_arl_srch_ctl(dev, ®); + if (!(reg & ARL_SRCH_STDN)) + return -ENOENT; + +@@ -2079,23 +2098,15 @@ int b53_fdb_dump(struct dsa_switch *ds, + unsigned int count = 0, results_per_hit = 1; + struct b53_device *priv = ds->priv; + struct b53_arl_entry results[2]; +- u8 offset; + int ret; +- u8 reg; + + if (priv->num_arl_bins > 2) + results_per_hit = 2; + + mutex_lock(&priv->arl_mutex); + +- if (is5325(priv) || is5365(priv)) +- offset = B53_ARL_SRCH_CTL_25; +- else +- offset = B53_ARL_SRCH_CTL; +- + /* Start search operation */ +- reg = ARL_SRCH_STDN; +- b53_write8(priv, B53_ARLIO_PAGE, offset, reg); ++ b53_write_arl_srch_ctl(priv, ARL_SRCH_STDN); + + do { + ret = b53_arl_search_wait(priv); diff --git a/target/linux/generic/backport-6.12/612-05-v6.19-net-dsa-b53-split-reading-search-entry-into-their-own-functions.patch b/target/linux/generic/backport-6.12/612-05-v6.19-net-dsa-b53-split-reading-search-entry-into-their-own-functions.patch new file mode 100644 index 0000000000..3e263f8cfb --- /dev/null +++ b/target/linux/generic/backport-6.12/612-05-v6.19-net-dsa-b53-split-reading-search-entry-into-their-own-functions.patch @@ -0,0 +1,86 @@ +From e0c476f325a8c9b961a3d446c24d3c8ecae7d186 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 7 Nov 2025 09:07:46 +0100 +Subject: [PATCH] net: dsa: b53: split reading search entry into their own + functions + +Split reading search entries into a function for each format. + +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20251107080749.26936-6-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 56 ++++++++++++++++++++++---------- + 1 file changed, 38 insertions(+), 18 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -2056,28 +2056,48 @@ static int b53_arl_search_wait(struct b5 + return -ETIMEDOUT; + } + +-static void b53_arl_search_rd(struct b53_device *dev, u8 idx, +- struct b53_arl_entry *ent) ++static void b53_arl_search_read_25(struct b53_device *dev, u8 idx, ++ struct b53_arl_entry *ent) + { + u64 mac_vid; + +- if (is5325(dev)) { +- b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_25, +- &mac_vid); +- b53_arl_to_entry_25(ent, mac_vid); +- } else if (is5365(dev)) { +- b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_65, +- &mac_vid); +- b53_arl_to_entry_25(ent, mac_vid); +- } else { +- u32 fwd_entry; +- +- b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_MACVID(idx), +- &mac_vid); +- b53_read32(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL(idx), +- &fwd_entry); +- b53_arl_to_entry(ent, mac_vid, fwd_entry); +- } ++ b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_25, ++ &mac_vid); ++ b53_arl_to_entry_25(ent, mac_vid); ++} ++ ++static void b53_arl_search_read_65(struct b53_device *dev, u8 idx, ++ struct b53_arl_entry *ent) ++{ ++ u64 mac_vid; ++ ++ b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_65, ++ &mac_vid); ++ b53_arl_to_entry_25(ent, mac_vid); ++} ++ ++static void b53_arl_search_read_95(struct b53_device *dev, u8 idx, ++ struct b53_arl_entry *ent) ++{ ++ u32 fwd_entry; ++ u64 mac_vid; ++ ++ b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_MACVID(idx), ++ &mac_vid); ++ b53_read32(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL(idx), ++ &fwd_entry); ++ b53_arl_to_entry(ent, mac_vid, fwd_entry); ++} ++ ++static void b53_arl_search_rd(struct b53_device *dev, u8 idx, ++ struct b53_arl_entry *ent) ++{ ++ if (is5325(dev)) ++ b53_arl_search_read_25(dev, idx, ent); ++ else if (is5365(dev)) ++ b53_arl_search_read_65(dev, idx, ent); ++ else ++ b53_arl_search_read_95(dev, idx, ent); + } + + static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, diff --git a/target/linux/generic/backport-6.12/612-06-v6.19-net-dsa-b53-move-ARL-entry-functions-into-ops-struct.patch b/target/linux/generic/backport-6.12/612-06-v6.19-net-dsa-b53-move-ARL-entry-functions-into-ops-struct.patch new file mode 100644 index 0000000000..dfa902d048 --- /dev/null +++ b/target/linux/generic/backport-6.12/612-06-v6.19-net-dsa-b53-move-ARL-entry-functions-into-ops-struct.patch @@ -0,0 +1,348 @@ +From a7e73339ad46ade76d29fb6cc7d7854222608c26 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 7 Nov 2025 09:07:47 +0100 +Subject: [PATCH] net: dsa: b53: move ARL entry functions into ops struct + +Now that the differences in ARL entry formats are neatly contained into +functions per chip family, wrap them into an ops struct and add wrapper +functions to access them. + +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20251107080749.26936-7-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 67 ++++++++++++++++++++++---------- + drivers/net/dsa/b53/b53_priv.h | 30 ++++++++++++++ + 2 files changed, 76 insertions(+), 21 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -1890,10 +1890,7 @@ static int b53_arl_read(struct b53_devic + + /* Read the bins */ + for (i = 0; i < dev->num_arl_bins; i++) { +- if (is5325(dev) || is5365(dev)) +- b53_arl_read_entry_25(dev, ent, i); +- else +- b53_arl_read_entry_95(dev, ent, i); ++ b53_arl_read_entry(dev, ent, i); + + if (!ent->is_valid) { + set_bit(i, free_bins); +@@ -1975,10 +1972,7 @@ static int b53_arl_op(struct b53_device + ent.is_static = true; + ent.is_age = false; + memcpy(ent.mac, addr, ETH_ALEN); +- if (is5325(dev) || is5365(dev)) +- b53_arl_write_entry_25(dev, &ent, idx); +- else +- b53_arl_write_entry_95(dev, &ent, idx); ++ b53_arl_write_entry(dev, &ent, idx); + + return b53_arl_rw_op(dev, 0); + } +@@ -2089,17 +2083,6 @@ static void b53_arl_search_read_95(struc + b53_arl_to_entry(ent, mac_vid, fwd_entry); + } + +-static void b53_arl_search_rd(struct b53_device *dev, u8 idx, +- struct b53_arl_entry *ent) +-{ +- if (is5325(dev)) +- b53_arl_search_read_25(dev, idx, ent); +- else if (is5365(dev)) +- b53_arl_search_read_65(dev, idx, ent); +- else +- b53_arl_search_read_95(dev, idx, ent); +-} +- + static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, + dsa_fdb_dump_cb_t *cb, void *data) + { +@@ -2133,13 +2116,13 @@ int b53_fdb_dump(struct dsa_switch *ds, + if (ret) + break; + +- b53_arl_search_rd(priv, 0, &results[0]); ++ b53_arl_search_read(priv, 0, &results[0]); + ret = b53_fdb_copy(port, &results[0], cb, data); + if (ret) + break; + + if (results_per_hit == 2) { +- b53_arl_search_rd(priv, 1, &results[1]); ++ b53_arl_search_read(priv, 1, &results[1]); + ret = b53_fdb_copy(port, &results[1], cb, data); + if (ret) + break; +@@ -2672,6 +2655,24 @@ static const struct dsa_switch_ops b53_s + .port_change_mtu = b53_change_mtu, + }; + ++static const struct b53_arl_ops b53_arl_ops_25 = { ++ .arl_read_entry = b53_arl_read_entry_25, ++ .arl_write_entry = b53_arl_write_entry_25, ++ .arl_search_read = b53_arl_search_read_25, ++}; ++ ++static const struct b53_arl_ops b53_arl_ops_65 = { ++ .arl_read_entry = b53_arl_read_entry_25, ++ .arl_write_entry = b53_arl_write_entry_25, ++ .arl_search_read = b53_arl_search_read_65, ++}; ++ ++static const struct b53_arl_ops b53_arl_ops_95 = { ++ .arl_read_entry = b53_arl_read_entry_95, ++ .arl_write_entry = b53_arl_write_entry_95, ++ .arl_search_read = b53_arl_search_read_95, ++}; ++ + struct b53_chip_data { + u32 chip_id; + const char *dev_name; +@@ -2685,6 +2686,7 @@ struct b53_chip_data { + u8 duplex_reg; + u8 jumbo_pm_reg; + u8 jumbo_size_reg; ++ const struct b53_arl_ops *arl_ops; + }; + + #define B53_VTA_REGS \ +@@ -2704,6 +2706,7 @@ static const struct b53_chip_data b53_sw + .arl_buckets = 1024, + .imp_port = 5, + .duplex_reg = B53_DUPLEX_STAT_FE, ++ .arl_ops = &b53_arl_ops_25, + }, + { + .chip_id = BCM5365_DEVICE_ID, +@@ -2714,6 +2717,7 @@ static const struct b53_chip_data b53_sw + .arl_buckets = 1024, + .imp_port = 5, + .duplex_reg = B53_DUPLEX_STAT_FE, ++ .arl_ops = &b53_arl_ops_65, + }, + { + .chip_id = BCM5389_DEVICE_ID, +@@ -2727,6 +2731,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM5395_DEVICE_ID, +@@ -2740,6 +2745,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM5397_DEVICE_ID, +@@ -2753,6 +2759,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM5398_DEVICE_ID, +@@ -2766,6 +2773,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM53101_DEVICE_ID, +@@ -2779,6 +2787,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM53115_DEVICE_ID, +@@ -2792,6 +2801,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM53125_DEVICE_ID, +@@ -2805,6 +2815,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM53128_DEVICE_ID, +@@ -2818,6 +2829,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM63XX_DEVICE_ID, +@@ -2831,6 +2843,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_63XX, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM53010_DEVICE_ID, +@@ -2844,6 +2857,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM53011_DEVICE_ID, +@@ -2857,6 +2871,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM53012_DEVICE_ID, +@@ -2870,6 +2885,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM53018_DEVICE_ID, +@@ -2883,6 +2899,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM53019_DEVICE_ID, +@@ -2896,6 +2913,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM58XX_DEVICE_ID, +@@ -2909,6 +2927,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM583XX_DEVICE_ID, +@@ -2922,6 +2941,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + /* Starfighter 2 */ + { +@@ -2936,6 +2956,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM7445_DEVICE_ID, +@@ -2949,6 +2970,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM7278_DEVICE_ID, +@@ -2962,6 +2984,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + { + .chip_id = BCM53134_DEVICE_ID, +@@ -2976,6 +2999,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ .arl_ops = &b53_arl_ops_95, + }, + }; + +@@ -3004,6 +3028,7 @@ static int b53_switch_init(struct b53_de + dev->num_vlans = chip->vlans; + dev->num_arl_bins = chip->arl_bins; + dev->num_arl_buckets = chip->arl_buckets; ++ dev->arl_ops = chip->arl_ops; + break; + } + } +--- a/drivers/net/dsa/b53/b53_priv.h ++++ b/drivers/net/dsa/b53/b53_priv.h +@@ -58,6 +58,17 @@ struct b53_io_ops { + bool link_up); + }; + ++struct b53_arl_entry; ++ ++struct b53_arl_ops { ++ void (*arl_read_entry)(struct b53_device *dev, ++ struct b53_arl_entry *ent, u8 idx); ++ void (*arl_write_entry)(struct b53_device *dev, ++ const struct b53_arl_entry *ent, u8 idx); ++ void (*arl_search_read)(struct b53_device *dev, u8 idx, ++ struct b53_arl_entry *ent); ++}; ++ + #define B53_INVALID_LANE 0xff + + enum { +@@ -127,6 +138,7 @@ struct b53_device { + struct mutex stats_mutex; + struct mutex arl_mutex; + const struct b53_io_ops *ops; ++ const struct b53_arl_ops *arl_ops; + + /* chip specific data */ + u32 chip_id; +@@ -371,6 +383,24 @@ static inline void b53_arl_from_entry_25 + *mac_vid |= ARLTBL_AGE_25; + } + ++static inline void b53_arl_read_entry(struct b53_device *dev, ++ struct b53_arl_entry *ent, u8 idx) ++{ ++ dev->arl_ops->arl_read_entry(dev, ent, idx); ++} ++ ++static inline void b53_arl_write_entry(struct b53_device *dev, ++ const struct b53_arl_entry *ent, u8 idx) ++{ ++ dev->arl_ops->arl_write_entry(dev, ent, idx); ++} ++ ++static inline void b53_arl_search_read(struct b53_device *dev, u8 idx, ++ struct b53_arl_entry *ent) ++{ ++ dev->arl_ops->arl_search_read(dev, idx, ent); ++} ++ + #ifdef CONFIG_BCM47XX + + #include diff --git a/target/linux/generic/backport-6.12/612-07-v6.19-net-dsa-b53-add-support-for-5389-5397-5398-ARL-entry-format.patch b/target/linux/generic/backport-6.12/612-07-v6.19-net-dsa-b53-add-support-for-5389-5397-5398-ARL-entry-format.patch new file mode 100644 index 0000000000..f87a78355e --- /dev/null +++ b/target/linux/generic/backport-6.12/612-07-v6.19-net-dsa-b53-add-support-for-5389-5397-5398-ARL-entry-format.patch @@ -0,0 +1,221 @@ +From 300f78e8b6b7be17c2c78afeded75be68acb1aa7 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 7 Nov 2025 09:07:48 +0100 +Subject: [PATCH] net: dsa: b53: add support for 5389/5397/5398 ARL entry + format + +BCM5389, BCM5397 and BCM5398 use a different ARL entry format with just +a 16 bit fwdentry register, as well as different search control and data +offsets. + +So add appropriate ops for them and switch those chips to use them. + +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20251107080749.26936-8-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 53 ++++++++++++++++++++++++++++++-- + drivers/net/dsa/b53/b53_priv.h | 26 ++++++++++++++++ + drivers/net/dsa/b53/b53_regs.h | 13 ++++++++ + 3 files changed, 89 insertions(+), 3 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -1850,6 +1850,31 @@ static void b53_arl_write_entry_25(struc + mac_vid); + } + ++static void b53_arl_read_entry_89(struct b53_device *dev, ++ struct b53_arl_entry *ent, u8 idx) ++{ ++ u64 mac_vid; ++ u16 fwd_entry; ++ ++ b53_read64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx), ++ &mac_vid); ++ b53_read16(dev, B53_ARLIO_PAGE, B53_ARLTBL_DATA_ENTRY(idx), &fwd_entry); ++ b53_arl_to_entry_89(ent, mac_vid, fwd_entry); ++} ++ ++static void b53_arl_write_entry_89(struct b53_device *dev, ++ const struct b53_arl_entry *ent, u8 idx) ++{ ++ u32 fwd_entry; ++ u64 mac_vid; ++ ++ b53_arl_from_entry_89(&mac_vid, &fwd_entry, ent); ++ b53_write64(dev, B53_ARLIO_PAGE, ++ B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); ++ b53_write16(dev, B53_ARLIO_PAGE, ++ B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); ++} ++ + static void b53_arl_read_entry_95(struct b53_device *dev, + struct b53_arl_entry *ent, u8 idx) + { +@@ -2013,6 +2038,8 @@ static void b53_read_arl_srch_ctl(struct + + if (is5325(dev) || is5365(dev)) + offset = B53_ARL_SRCH_CTL_25; ++ else if (dev->chip_id == BCM5389_DEVICE_ID || is5397_98(dev)) ++ offset = B53_ARL_SRCH_CTL_89; + else + offset = B53_ARL_SRCH_CTL; + +@@ -2025,6 +2052,8 @@ static void b53_write_arl_srch_ctl(struc + + if (is5325(dev) || is5365(dev)) + offset = B53_ARL_SRCH_CTL_25; ++ else if (dev->chip_id == BCM5389_DEVICE_ID || is5397_98(dev)) ++ offset = B53_ARL_SRCH_CTL_89; + else + offset = B53_ARL_SRCH_CTL; + +@@ -2070,6 +2099,18 @@ static void b53_arl_search_read_65(struc + b53_arl_to_entry_25(ent, mac_vid); + } + ++static void b53_arl_search_read_89(struct b53_device *dev, u8 idx, ++ struct b53_arl_entry *ent) ++{ ++ u16 fwd_entry; ++ u64 mac_vid; ++ ++ b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_MACVID_89, ++ &mac_vid); ++ b53_read16(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_89, &fwd_entry); ++ b53_arl_to_entry_89(ent, mac_vid, fwd_entry); ++} ++ + static void b53_arl_search_read_95(struct b53_device *dev, u8 idx, + struct b53_arl_entry *ent) + { +@@ -2667,6 +2708,12 @@ static const struct b53_arl_ops b53_arl_ + .arl_search_read = b53_arl_search_read_65, + }; + ++static const struct b53_arl_ops b53_arl_ops_89 = { ++ .arl_read_entry = b53_arl_read_entry_89, ++ .arl_write_entry = b53_arl_write_entry_89, ++ .arl_search_read = b53_arl_search_read_89, ++}; ++ + static const struct b53_arl_ops b53_arl_ops_95 = { + .arl_read_entry = b53_arl_read_entry_95, + .arl_write_entry = b53_arl_write_entry_95, +@@ -2731,7 +2778,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, +- .arl_ops = &b53_arl_ops_95, ++ .arl_ops = &b53_arl_ops_89, + }, + { + .chip_id = BCM5395_DEVICE_ID, +@@ -2759,7 +2806,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, +- .arl_ops = &b53_arl_ops_95, ++ .arl_ops = &b53_arl_ops_89, + }, + { + .chip_id = BCM5398_DEVICE_ID, +@@ -2773,7 +2820,7 @@ static const struct b53_chip_data b53_sw + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, +- .arl_ops = &b53_arl_ops_95, ++ .arl_ops = &b53_arl_ops_89, + }, + { + .chip_id = BCM53101_DEVICE_ID, +--- a/drivers/net/dsa/b53/b53_priv.h ++++ b/drivers/net/dsa/b53/b53_priv.h +@@ -353,6 +353,18 @@ static inline void b53_arl_to_entry_25(s + ent->vid = mac_vid >> ARLTBL_VID_S_65; + } + ++static inline void b53_arl_to_entry_89(struct b53_arl_entry *ent, ++ u64 mac_vid, u16 fwd_entry) ++{ ++ memset(ent, 0, sizeof(*ent)); ++ ent->port = fwd_entry & ARLTBL_DATA_PORT_ID_MASK_89; ++ ent->is_valid = !!(fwd_entry & ARLTBL_VALID_89); ++ ent->is_age = !!(fwd_entry & ARLTBL_AGE_89); ++ ent->is_static = !!(fwd_entry & ARLTBL_STATIC_89); ++ u64_to_ether_addr(mac_vid, ent->mac); ++ ent->vid = mac_vid >> ARLTBL_VID_S; ++} ++ + static inline void b53_arl_from_entry(u64 *mac_vid, u32 *fwd_entry, + const struct b53_arl_entry *ent) + { +@@ -383,6 +395,20 @@ static inline void b53_arl_from_entry_25 + *mac_vid |= ARLTBL_AGE_25; + } + ++static inline void b53_arl_from_entry_89(u64 *mac_vid, u32 *fwd_entry, ++ const struct b53_arl_entry *ent) ++{ ++ *mac_vid = ether_addr_to_u64(ent->mac); ++ *mac_vid |= (u64)(ent->vid & ARLTBL_VID_MASK) << ARLTBL_VID_S; ++ *fwd_entry = ent->port & ARLTBL_DATA_PORT_ID_MASK_89; ++ if (ent->is_valid) ++ *fwd_entry |= ARLTBL_VALID_89; ++ if (ent->is_static) ++ *fwd_entry |= ARLTBL_STATIC_89; ++ if (ent->is_age) ++ *fwd_entry |= ARLTBL_AGE_89; ++} ++ + static inline void b53_arl_read_entry(struct b53_device *dev, + struct b53_arl_entry *ent, u8 idx) + { +--- a/drivers/net/dsa/b53/b53_regs.h ++++ b/drivers/net/dsa/b53/b53_regs.h +@@ -342,12 +342,20 @@ + #define ARLTBL_STATIC BIT(15) + #define ARLTBL_VALID BIT(16) + ++/* BCM5389 ARL Table Data Entry N Register format (16 bit) */ ++#define ARLTBL_DATA_PORT_ID_MASK_89 GENMASK(8, 0) ++#define ARLTBL_TC_MASK_89 GENMASK(12, 10) ++#define ARLTBL_AGE_89 BIT(13) ++#define ARLTBL_STATIC_89 BIT(14) ++#define ARLTBL_VALID_89 BIT(15) ++ + /* Maximum number of bin entries in the ARL for all switches */ + #define B53_ARLTBL_MAX_BIN_ENTRIES 4 + + /* ARL Search Control Register (8 bit) */ + #define B53_ARL_SRCH_CTL 0x50 + #define B53_ARL_SRCH_CTL_25 0x20 ++#define B53_ARL_SRCH_CTL_89 0x30 + #define ARL_SRCH_VLID BIT(0) + #define ARL_SRCH_STDN BIT(7) + +@@ -355,10 +363,12 @@ + #define B53_ARL_SRCH_ADDR 0x51 + #define B53_ARL_SRCH_ADDR_25 0x22 + #define B53_ARL_SRCH_ADDR_65 0x24 ++#define B53_ARL_SRCH_ADDR_89 0x31 + #define ARL_ADDR_MASK GENMASK(14, 0) + + /* ARL Search MAC/VID Result (64 bit) */ + #define B53_ARL_SRCH_RSTL_0_MACVID 0x60 ++#define B53_ARL_SRCH_RSLT_MACVID_89 0x33 + + /* Single register search result on 5325 */ + #define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24 +@@ -368,6 +378,9 @@ + /* ARL Search Data Result (32 bit) */ + #define B53_ARL_SRCH_RSTL_0 0x68 + ++/* BCM5389 ARL Search Data Result (16 bit) */ ++#define B53_ARL_SRCH_RSLT_89 0x3b ++ + #define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10)) + #define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10)) + diff --git a/target/linux/generic/backport-6.12/612-08-v6.19-net-dsa-b53-add-support-for-bcm63xx-ARL-entry-format.patch b/target/linux/generic/backport-6.12/612-08-v6.19-net-dsa-b53-add-support-for-bcm63xx-ARL-entry-format.patch new file mode 100644 index 0000000000..33aab1144d --- /dev/null +++ b/target/linux/generic/backport-6.12/612-08-v6.19-net-dsa-b53-add-support-for-bcm63xx-ARL-entry-format.patch @@ -0,0 +1,177 @@ +From 2b3013ac03028a2364d8779719bb6bfbc0212435 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 7 Nov 2025 09:07:49 +0100 +Subject: [PATCH] net: dsa: b53: add support for bcm63xx ARL entry format + +The ARL registers of BCM63XX embedded switches are somewhat unique. The +normal ARL table access registers have the same format as BCM5389, but +the ARL search registers differ: + +* SRCH_CTL is at the same offset of BCM5389, but 16 bits wide. It does + not have more fields, just needs to be accessed by a 16 bit read. +* SRCH_RSLT_MACVID and SRCH_RSLT are aligned to 32 bit, and have shifted + offsets. +* SRCH_RSLT has a different format than the normal ARL data entry + register. +* There is only one set of ENTRY_N registers, implying a 1 bin layout. + +So add appropriate ops for bcm63xx and let it use it. + +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20251107080749.26936-9-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 44 +++++++++++++++++++++++++++----- + drivers/net/dsa/b53/b53_priv.h | 15 +++++++++++ + drivers/net/dsa/b53/b53_regs.h | 9 +++++++ + 3 files changed, 61 insertions(+), 7 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -2038,12 +2038,20 @@ static void b53_read_arl_srch_ctl(struct + + if (is5325(dev) || is5365(dev)) + offset = B53_ARL_SRCH_CTL_25; +- else if (dev->chip_id == BCM5389_DEVICE_ID || is5397_98(dev)) ++ else if (dev->chip_id == BCM5389_DEVICE_ID || is5397_98(dev) || ++ is63xx(dev)) + offset = B53_ARL_SRCH_CTL_89; + else + offset = B53_ARL_SRCH_CTL; + +- b53_read8(dev, B53_ARLIO_PAGE, offset, val); ++ if (is63xx(dev)) { ++ u16 val16; ++ ++ b53_read16(dev, B53_ARLIO_PAGE, offset, &val16); ++ *val = val16 & 0xff; ++ } else { ++ b53_read8(dev, B53_ARLIO_PAGE, offset, val); ++ } + } + + static void b53_write_arl_srch_ctl(struct b53_device *dev, u8 val) +@@ -2052,12 +2060,16 @@ static void b53_write_arl_srch_ctl(struc + + if (is5325(dev) || is5365(dev)) + offset = B53_ARL_SRCH_CTL_25; +- else if (dev->chip_id == BCM5389_DEVICE_ID || is5397_98(dev)) ++ else if (dev->chip_id == BCM5389_DEVICE_ID || is5397_98(dev) || ++ is63xx(dev)) + offset = B53_ARL_SRCH_CTL_89; + else + offset = B53_ARL_SRCH_CTL; + +- b53_write8(dev, B53_ARLIO_PAGE, offset, val); ++ if (is63xx(dev)) ++ b53_write16(dev, B53_ARLIO_PAGE, offset, val); ++ else ++ b53_write8(dev, B53_ARLIO_PAGE, offset, val); + } + + static int b53_arl_search_wait(struct b53_device *dev) +@@ -2111,6 +2123,18 @@ static void b53_arl_search_read_89(struc + b53_arl_to_entry_89(ent, mac_vid, fwd_entry); + } + ++static void b53_arl_search_read_63xx(struct b53_device *dev, u8 idx, ++ struct b53_arl_entry *ent) ++{ ++ u16 fwd_entry; ++ u64 mac_vid; ++ ++ b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_MACVID_63XX, ++ &mac_vid); ++ b53_read16(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_63XX, &fwd_entry); ++ b53_arl_search_to_entry_63xx(ent, mac_vid, fwd_entry); ++} ++ + static void b53_arl_search_read_95(struct b53_device *dev, u8 idx, + struct b53_arl_entry *ent) + { +@@ -2714,6 +2738,12 @@ static const struct b53_arl_ops b53_arl_ + .arl_search_read = b53_arl_search_read_89, + }; + ++static const struct b53_arl_ops b53_arl_ops_63xx = { ++ .arl_read_entry = b53_arl_read_entry_89, ++ .arl_write_entry = b53_arl_write_entry_89, ++ .arl_search_read = b53_arl_search_read_63xx, ++}; ++ + static const struct b53_arl_ops b53_arl_ops_95 = { + .arl_read_entry = b53_arl_read_entry_95, + .arl_write_entry = b53_arl_write_entry_95, +@@ -2883,14 +2913,14 @@ static const struct b53_chip_data b53_sw + .dev_name = "BCM63xx", + .vlans = 4096, + .enabled_ports = 0, /* pdata must provide them */ +- .arl_bins = 4, +- .arl_buckets = 1024, ++ .arl_bins = 1, ++ .arl_buckets = 4096, + .imp_port = 8, + .vta_regs = B53_VTA_REGS_63XX, + .duplex_reg = B53_DUPLEX_STAT_63XX, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, +- .arl_ops = &b53_arl_ops_95, ++ .arl_ops = &b53_arl_ops_63xx, + }, + { + .chip_id = BCM53010_DEVICE_ID, +--- a/drivers/net/dsa/b53/b53_priv.h ++++ b/drivers/net/dsa/b53/b53_priv.h +@@ -409,6 +409,21 @@ static inline void b53_arl_from_entry_89 + *fwd_entry |= ARLTBL_AGE_89; + } + ++static inline void b53_arl_search_to_entry_63xx(struct b53_arl_entry *ent, ++ u64 mac_vid, u16 fwd_entry) ++{ ++ memset(ent, 0, sizeof(*ent)); ++ u64_to_ether_addr(mac_vid, ent->mac); ++ ent->vid = mac_vid >> ARLTBL_VID_S; ++ ++ ent->port = fwd_entry & ARL_SRST_PORT_ID_MASK_63XX; ++ ent->port >>= 1; ++ ++ ent->is_age = !!(fwd_entry & ARL_SRST_AGE_63XX); ++ ent->is_static = !!(fwd_entry & ARL_SRST_STATIC_63XX); ++ ent->is_valid = 1; ++} ++ + static inline void b53_arl_read_entry(struct b53_device *dev, + struct b53_arl_entry *ent, u8 idx) + { +--- a/drivers/net/dsa/b53/b53_regs.h ++++ b/drivers/net/dsa/b53/b53_regs.h +@@ -364,11 +364,13 @@ + #define B53_ARL_SRCH_ADDR_25 0x22 + #define B53_ARL_SRCH_ADDR_65 0x24 + #define B53_ARL_SRCH_ADDR_89 0x31 ++#define B53_ARL_SRCH_ADDR_63XX 0x32 + #define ARL_ADDR_MASK GENMASK(14, 0) + + /* ARL Search MAC/VID Result (64 bit) */ + #define B53_ARL_SRCH_RSTL_0_MACVID 0x60 + #define B53_ARL_SRCH_RSLT_MACVID_89 0x33 ++#define B53_ARL_SRCH_RSLT_MACVID_63XX 0x34 + + /* Single register search result on 5325 */ + #define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24 +@@ -384,6 +386,13 @@ + #define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10)) + #define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10)) + ++/* 63XX ARL Search Data Result (16 bit) */ ++#define B53_ARL_SRCH_RSLT_63XX 0x3c ++#define ARL_SRST_PORT_ID_MASK_63XX GENMASK(9, 1) ++#define ARL_SRST_TC_MASK_63XX GENMASK(13, 11) ++#define ARL_SRST_AGE_63XX BIT(14) ++#define ARL_SRST_STATIC_63XX BIT(15) ++ + /************************************************************************* + * IEEE 802.1X Registers + *************************************************************************/ diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_h3c_vfs.c b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_h3c_vfs.c index a766ff7c2f..a7b2b6ea7e 100644 --- a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_h3c_vfs.c +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_h3c_vfs.c @@ -98,10 +98,11 @@ static int mtdsplit_h3c_vfs_parse(struct mtd_info *mtd, if (retlen != sizeof(format_flag)) return -EIO; - if (format_flag != FORMAT_FLAG) + if (format_flag != FORMAT_FLAG) { pr_debug("mtdsplit_h3c_vfs: unexpected format flag %08x\n", format_flag); return -ENOENT; + } /* Check file entry */ err = mtd_read(mtd, FILE_ENTRY_OFFSET, sizeof(file_entry), &retlen, diff --git a/target/linux/imx/Makefile b/target/linux/imx/Makefile index bba6332eea..69a46c5403 100644 --- a/target/linux/imx/Makefile +++ b/target/linux/imx/Makefile @@ -9,8 +9,7 @@ BOARDNAME:=NXP i.MX FEATURES:=audio display fpu gpio pcie rtc usb usbgadget squashfs targz nand ubifs boot-part rootfs-part SUBTARGETS:=cortexa7 cortexa9 cortexa53 -KERNEL_PATCHVER:=6.6 -KERNEL_TESTING_PATCHVER:=6.12 +KERNEL_PATCHVER:=6.12 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/imx/config-6.6 b/target/linux/imx/config-6.6 deleted file mode 100644 index 33478f29b9..0000000000 --- a/target/linux/imx/config-6.6 +++ /dev/null @@ -1,490 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_MXC=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_ARM_ERRATA_764369=y -CONFIG_ARM_ERRATA_775420=y -CONFIG_ARM_ERRATA_814220=y -CONFIG_ARM_HAS_GROUP_RELOCS=y -CONFIG_ARM_HEAVY_MB=y -# CONFIG_ARM_IMX6Q_CPUFREQ is not set -# CONFIG_ARM_IMX_CPUFREQ_DT is not set -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASN1=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_ATA=y -CONFIG_ATAGS=y -# CONFIG_ATA_SFF is not set -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_PM=y -CONFIG_CACHE_L2X0=y -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -CONFIG_CLKSRC_IMX_GPT=y -CONFIG_CLKSRC_MMIO=y -# CONFIG_CLK_IMX8MM is not set -# CONFIG_CLK_IMX8MN is not set -# CONFIG_CLK_IMX8MP is not set -# CONFIG_CLK_IMX8MQ is not set -# CONFIG_CLK_IMX8ULP is not set -# CONFIG_CLK_IMX93 is not set -CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y -CONFIG_COMMON_CLK=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_THERMAL=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AES_ARM=y -CONFIG_CRYPTO_AES_ARM_BS=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_BLAKE2S_ARM=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CHACHA20=y -CONFIG_CRYPTO_CHACHA20_NEON=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC32_ARM_CE=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_CTS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DEV_FSL_CAAM=y -CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y -CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y -CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y -# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set -# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set -CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y -CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 -CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y -# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_ENGINE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_RSA=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA1_ARM=y -CONFIG_CRYPTO_SHA1_ARM_NEON=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SHA512_ARM=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_XTS=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CURRENT_POINTER_IN_TPIDRURO=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MISC=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set -# CONFIG_DRM_FSL_LDB is not set -# CONFIG_DRM_IMX8QM_LDB is not set -# CONFIG_DRM_IMX8QXP_LDB is not set -# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set -# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set -# CONFIG_DRM_IMX_LCDC is not set -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ENCRYPTED_KEYS=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FEC=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FSL_DPAA2_SWITCH is not set -CONFIG_FSL_GUTS=y -CONFIG_FS_ENCRYPTION=y -CONFIG_FS_ENCRYPTION_ALGS=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -# CONFIG_GIANFAR is not set -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_MXC=y -CONFIG_GPIO_VF610=y -CONFIG_GRO_CELLS=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_IMX=y -# CONFIG_I2C_IMX_LPI2C is not set -CONFIG_I2C_SLAVE=y -# CONFIG_I2C_SLAVE_TESTUNIT is not set -CONFIG_IMX2_WDT=y -# CONFIG_IMX7ULP_WDT is not set -# CONFIG_IMX8MM_THERMAL is not set -# CONFIG_IMX93_ADC is not set -CONFIG_IMX_DMA=y -# CONFIG_IMX_GPCV2_PM_DOMAINS is not set -CONFIG_IMX_INTMUX=y -CONFIG_IMX_IRQSTEER=y -CONFIG_IMX_MU_MSI=m -CONFIG_IMX_SDMA=y -CONFIG_IMX_THERMAL=y -# CONFIG_IMX_WEIM is not set -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_INPUT_BBNSM_PWRKEY is not set -CONFIG_IRQCHIP=y -CONFIG_IRQSTACKS=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -# CONFIG_JFFS2_FS is not set -CONFIG_KEYS=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -# CONFIG_MMC_MXC is not set -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ESDHC_IMX=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MPILIB=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_GPMI_NAND=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -# CONFIG_MX3_IPU is not set -CONFIG_MXC_CLK=y -CONFIG_MXS_DMA=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -# CONFIG_NET_DSA_MICROCHIP_KSZ_PTP is not set -CONFIG_NET_DSA_TAG_DSA=y -CONFIG_NET_DSA_TAG_DSA_COMMON=y -CONFIG_NET_DSA_TAG_EDSA=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -# CONFIG_NVMEM_IMX_IIM is not set -CONFIG_NVMEM_IMX_OCOTP=y -# CONFIG_NVMEM_IMX_OCOTP_ELE is not set -CONFIG_NVMEM_LAYOUTS=y -# CONFIG_NVMEM_SNVS_LPGPR is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0x80000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI_IMX6_HOST=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_IMX8ULP is not set -# CONFIG_PINCTRL_IMX93 is not set -# CONFIG_PINCTRL_IMXRT1050 is not set -# CONFIG_PINCTRL_IMXRT1170 is not set -CONFIG_PL310_ERRATA_769419=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_OPP=y -CONFIG_PPS=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -# CONFIG_PWM_IMX1 is not set -CONFIG_PWM_IMX27=y -# CONFIG_PWM_IMX_TPM is not set -CONFIG_PWM_SYSFS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RD_BZIP2=y -CONFIG_RD_GZIP=y -CONFIG_RD_LZO=y -CONFIG_RD_XZ=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_ANATOP=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_PFUZE100=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_BBNSM is not set -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_IMXDI is not set -# CONFIG_RTC_DRV_MXC is not set -# CONFIG_RTC_DRV_MXC_V2 is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_THERMAL_PRESSURE=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_IMX_EARLYCON=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BUS=y -# CONFIG_SOC_IMX50 is not set -# CONFIG_SOC_IMX51 is not set -# CONFIG_SOC_IMX53 is not set -# CONFIG_SOC_IMX6Q is not set -# CONFIG_SOC_IMX6SL is not set -# CONFIG_SOC_IMX6SLL is not set -# CONFIG_SOC_IMX6SX is not set -# CONFIG_SOC_IMX6UL is not set -# CONFIG_SOC_IMX7D is not set -# CONFIG_SOC_IMX7ULP is not set -# CONFIG_SOC_IMX8M is not set -# CONFIG_SOC_IMX9 is not set -# CONFIG_SOC_LS1021A is not set -# CONFIG_SOC_VF610 is not set -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -# CONFIG_SPI_FSL_LPSPI is not set -# CONFIG_SPI_FSL_QUADSPI is not set -CONFIG_SPI_IMX=y -CONFIG_SPI_MASTER=y -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y -CONFIG_STMP_DEVICE=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_CHIPIDEA_IMX=y -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -CONFIG_USB_GADGET=y -CONFIG_USB_MXS_PHY=y -CONFIG_USB_OTG=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ULPI_BUS=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -# CONFIG_VIDEO_DW100 is not set -# CONFIG_VIDEO_HANTRO is not set -# CONFIG_VIDEO_IMX7_CSI is not set -# CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 is not set -# CONFIG_VIDEO_IMX8_ISI is not set -# CONFIG_VIDEO_IMX_MIPI_CSIS is not set -# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set -CONFIG_VMSPLIT_2G=y -# CONFIG_VMSPLIT_3G is not set -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/imx/patches-6.6/100-bootargs.patch b/target/linux/imx/patches-6.6/100-bootargs.patch deleted file mode 100644 index 7afcebecb0..0000000000 --- a/target/linux/imx/patches-6.6/100-bootargs.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts -@@ -16,4 +16,8 @@ - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -+ -+ chosen { -+ bootargs = "console=ttymxc0,115200"; -+ }; - }; diff --git a/target/linux/imx/patches-6.6/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch b/target/linux/imx/patches-6.6/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch deleted file mode 100644 index 5a8e9550fd..0000000000 --- a/target/linux/imx/patches-6.6/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 68604e89335ccb3e893b5a05b2c0d5cd2eaaf6ec Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Petr=20=C5=A0tetiar?= -Date: Tue, 3 Mar 2020 15:14:40 +0100 -Subject: [PATCH] ARM: dts: imx6q-apalis: ixora: add status LEDs aliases -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Petr Štetiar ---- - arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts | 16 ++++++++++------ - arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts | 12 ++++++++---- - 2 files changed, 18 insertions(+), 10 deletions(-) - ---- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts -@@ -24,6 +24,10 @@ - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; -+ led-boot = &led_boot; -+ led-failsafe = &led_failsafe; -+ led-running = &led_running; -+ led-upgrade = &led_upgrade; - }; - - chosen { -@@ -35,22 +39,22 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - -- led4-green { -+ led_running: led4-green { - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - label = "LED_4_GREEN"; - }; - -- led4-red { -+ led_upgrade: led4-red { - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - label = "LED_4_RED"; - }; - -- led5-green { -+ led_boot: led5-green { - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - label = "LED_5_GREEN"; - }; - -- led5-red { -+ led_failsafe: led5-red { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - label = "LED_5_RED"; - }; ---- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts -@@ -24,6 +24,10 @@ - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; -+ led-boot = &led_boot; -+ led-failsafe = &led_failsafe; -+ led-running = &led_running; -+ led-upgrade = &led_upgrade; - }; - - chosen { -@@ -36,22 +40,22 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - -- led4-green { -- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; -+ led_running: led4-green { -+ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - label = "LED_4_GREEN"; - }; - -- led4-red { -- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; -+ led_upgrade: led4-red { -+ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - label = "LED_4_RED"; - }; - -- led5-green { -+ led_boot: led5-green { - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - label = "LED_5_GREEN"; - }; - -- led5-red { -+ led_failsafe: led5-red { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - label = "LED_5_RED"; - }; diff --git a/target/linux/imx/patches-6.6/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch b/target/linux/imx/patches-6.6/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch deleted file mode 100644 index 0a3b696128..0000000000 --- a/target/linux/imx/patches-6.6/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch +++ /dev/null @@ -1,78 +0,0 @@ -From b6764bb27c819cdcf854371db485a43d71f579f3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Petr=20=C5=A0tetiar?= -Date: Tue, 3 Mar 2020 15:15:57 +0100 -Subject: [PATCH] ARM: dts: imx6q-apalis: ixora: make switch3 reset button -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Petr Štetiar ---- - arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts | 15 ++++++++++++++- - arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts | 15 ++++++++++++++- - 2 files changed, 28 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts -@@ -59,6 +59,17 @@ - label = "LED_5_RED"; - }; - }; -+ -+ gpio-keys { -+ pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>; -+ -+ reset { -+ label = "reset"; -+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <10>; -+ }; -+ }; - }; - - &can1 { -@@ -183,4 +194,10 @@ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; -+ -+ pinctrl_switch3_ixora: switch3ixora { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 -+ >; -+ }; - }; ---- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts -@@ -61,6 +61,17 @@ - }; - }; - -+ gpio-keys { -+ pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>; -+ -+ reset { -+ label = "reset"; -+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <10>; -+ }; -+ }; -+ - reg_3v3_vmmc: regulator-3v3-vmmc { - compatible = "regulator-fixed"; - enable-active-high; -@@ -264,6 +275,12 @@ - >; - }; - -+ pinctrl_switch3_ixora: switch3ixora { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 -+ >; -+ }; -+ - pinctrl_mmc_cd_sleep: mmccdslpgrp { - fsl,pins = < - /* MMC1 CD */ diff --git a/target/linux/imx/patches-6.6/310-ARM-dts-imx7d-pico-pi-set-aliases.patch b/target/linux/imx/patches-6.6/310-ARM-dts-imx7d-pico-pi-set-aliases.patch deleted file mode 100644 index d71787b3ac..0000000000 --- a/target/linux/imx/patches-6.6/310-ARM-dts-imx7d-pico-pi-set-aliases.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts -@@ -8,12 +8,20 @@ - model = "TechNexion PICO-IMX7D Board and PI baseboard"; - compatible = "technexion,imx7d-pico-pi", "fsl,imx7d"; - -+ aliases { -+ led-boot = &led_system; -+ led-failsafe = &led_system; -+ led-running = &led_system; -+ led-upgrade = &led_system; -+ label-mac-device = &fec1; -+ }; -+ - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - -- led { -+ led_system: led { - label = "gpio-led"; - gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - }; diff --git a/target/linux/imx/patches-6.6/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch b/target/linux/imx/patches-6.6/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch deleted file mode 100644 index 244b7595ae..0000000000 --- a/target/linux/imx/patches-6.6/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 6e8e5ccfbee7a531b035ffce3f95f3901946fa9d Mon Sep 17 00:00:00 2001 -From: Robert Nelson -Date: Wed, 9 Jan 2019 14:33:24 -0600 -Subject: [PATCH] ARM: imx7d-pico-pi.dts: add default stdout-path - -Signed-off-by: Robert Nelson ---- - arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts -@@ -16,6 +16,10 @@ - label-mac-device = &fec1; - }; - -+ chosen { -+ stdout-path = "serial4:115200n8"; -+ }; -+ - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; diff --git a/target/linux/imx/patches-6.6/400-6.7-arm64-dts-imx8mp-add-imx8mp-venice-gw74xx-imx219.patch b/target/linux/imx/patches-6.6/400-6.7-arm64-dts-imx8mp-add-imx8mp-venice-gw74xx-imx219.patch deleted file mode 100644 index 36025a185c..0000000000 --- a/target/linux/imx/patches-6.6/400-6.7-arm64-dts-imx8mp-add-imx8mp-venice-gw74xx-imx219.patch +++ /dev/null @@ -1,136 +0,0 @@ -From 60fd951029603a0a6e019f16d53fb329dbd001f4 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Fri, 7 Jul 2023 16:24:19 -0700 -Subject: [PATCH 400/413] 6.7: arm64: dts: imx8mp: add - imx8mp-venice-gw74xx-imx219 overlay for rpi v2 camera - -Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module: - - https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf - - has its own on-board 24MHz osc so no clock required from baseboard - - pin 11 enables 1.8V and 2.8V LDO which is connected to - GW74xx MIPI_GPIO4 (IMX8MP GPIO1_IO4) so we use this as a gpio - -Support is added via a device-tree overlay. - -The IMX219 supports RAW8/RAW10 image formats. - -Example configuration: -media-ctl -l "'imx219 3-0010':0->'csis-32e40000.csi':0[1]" -media-ctl -v -V "'imx219 3-0010':0 [fmt:SRGGB8/640x480 field:none]" -media-ctl -v -V "'crossbar':0 [fmt:SRGGB8/640x480 field:none]" -media-ctl -v -V "'mxc_isi.0':0 [fmt:SRGGB8/640x480 field:none]" -v4l2-ctl --set-fmt-video=width=640,height=480,pixelformat=RGGB -v4l2-ctl --stream-mmap --stream-to=frame.raw --stream-count=1 -convert -size 640x480 -depth 8 gray:frame.raw frame.png -gst-launch-1.0 v4l2src ! \ - video/x-bayer,format=rggb,width=640,height=480,framerate=10/1 ! \ - bayer2rgb ! fbdevsink - -Signed-off-by: Tim Harvey ---- - arch/arm64/boot/dts/freescale/Makefile | 2 + - .../imx8mp-venice-gw74xx-imx219.dtso | 80 +++++++++++++++++++ - 2 files changed, 82 insertions(+) - create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso - ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -159,6 +159,7 @@ imx8mm-venice-gw73xx-0x-rpidsi-dtbs := i - imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo - imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo - imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo -+imx8mp-venice-gw74xx-imx219-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-imx219.dtbo - imx8mp-venice-gw74xx-rpidsi-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-rpidsi.dtbo - - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb -@@ -171,6 +172,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice- - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-imx219.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb - - dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso -@@ -0,0 +1,80 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2023 Gateworks Corporation -+ */ -+ -+#include -+ -+#include "imx8mp-pinfunc.h" -+ -+/dts-v1/; -+/plugin/; -+ -+&{/} { -+ compatible = "gw,imx8mp-gw74xx", "fsl,imx8mp"; -+ -+ reg_cam: regulator-cam { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_cam>; -+ compatible = "regulator-fixed"; -+ regulator-name = "reg_cam"; -+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ cam24m: cam24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "cam24m"; -+ }; -+}; -+ -+&i2c4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ imx219: sensor@10 { -+ compatible = "sony,imx219"; -+ reg = <0x10>; -+ clocks = <&cam24m>; -+ VDIG-supply = <®_cam>; -+ -+ port { -+ /* MIPI CSI-2 bus endpoint */ -+ imx219_to_mipi_csi2: endpoint { -+ remote-endpoint = <&mipi_csi_0_in>; -+ clock-lanes = <0>; -+ data-lanes = <1 2>; -+ link-frequencies = /bits/ 64 <456000000>; -+ }; -+ }; -+ }; -+}; -+ -+&isi_0 { -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ mipi_csi_0_in: endpoint { -+ remote-endpoint = <&imx219_to_mipi_csi2>; -+ data-lanes = <1 2>; -+ }; -+ }; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_reg_cam: regcamgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x41 -+ >; -+ }; -+}; diff --git a/target/linux/imx/patches-6.6/401-6.7-arm64-dts-imx8mm-venice-gw73xx-add-TPM-device.patch b/target/linux/imx/patches-6.6/401-6.7-arm64-dts-imx8mm-venice-gw73xx-add-TPM-device.patch deleted file mode 100644 index 782573f6d0..0000000000 --- a/target/linux/imx/patches-6.6/401-6.7-arm64-dts-imx8mm-venice-gw73xx-add-TPM-device.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 816e40232faaa4aa0364ca8da7f86eaf27b0d9ff Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Mon, 26 Jun 2023 11:51:13 -0700 -Subject: [PATCH 401/413] 6.7: arm64: dts: imx8mm-venice-gw73xx: add TPM device - -Add the TPM device found on the GW73xx revision F PCB. - -Signed-off-by: Tim Harvey ---- - .../arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi -@@ -104,8 +104,15 @@ - &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &gpio1 { -@@ -362,6 +369,7 @@ - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 -+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 - >; - }; - diff --git a/target/linux/imx/patches-6.6/402-6.7-arm64-dts-imx8mp-venice-gw73xx-add-TPM-device.patch b/target/linux/imx/patches-6.6/402-6.7-arm64-dts-imx8mp-venice-gw73xx-add-TPM-device.patch deleted file mode 100644 index a106c0bc21..0000000000 --- a/target/linux/imx/patches-6.6/402-6.7-arm64-dts-imx8mp-venice-gw73xx-add-TPM-device.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 916ffc08e8cdd3beccd78291eac9dc5592d83de1 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 24 Aug 2023 11:07:48 -0700 -Subject: [PATCH 402/413] 6.7: arm64: dts: imx8mp-venice-gw73xx: add TPM device - -Add the TPM device found on the GW73xx revision F PCB. - -Signed-off-by: Tim Harvey ---- - .../arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi -@@ -95,8 +95,15 @@ - &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &gpio4 { -@@ -327,6 +334,7 @@ - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 -+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 - >; - }; - diff --git a/target/linux/imx/patches-6.6/403-6.8-arm64-dts-imx8mm-venice-gw72xx-add-TPM-device.patch b/target/linux/imx/patches-6.6/403-6.8-arm64-dts-imx8mm-venice-gw72xx-add-TPM-device.patch deleted file mode 100644 index 01b79e26e8..0000000000 --- a/target/linux/imx/patches-6.6/403-6.8-arm64-dts-imx8mm-venice-gw72xx-add-TPM-device.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 0adf19579692623d9d9202d2868aa7cd81451148 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 28 Sep 2023 14:10:39 -0700 -Subject: [PATCH 403/413] 6.8: arm64: dts: imx8mm-venice-gw72xx: add TPM device - -Add the TPM device found on the GW72xx revision F PCB. - -Signed-off-by: Tim Harvey ---- - .../arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi -@@ -84,8 +84,15 @@ - &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &gpio1 { -@@ -313,6 +320,7 @@ - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 -+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 - >; - }; - diff --git a/target/linux/imx/patches-6.6/404-6.8-arm64-dts-imx8mp-venice-gw72xx-add-TPM-device.patch b/target/linux/imx/patches-6.6/404-6.8-arm64-dts-imx8mp-venice-gw72xx-add-TPM-device.patch deleted file mode 100644 index 1e399f72f5..0000000000 --- a/target/linux/imx/patches-6.6/404-6.8-arm64-dts-imx8mp-venice-gw72xx-add-TPM-device.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 9d3932717327f6086a9a81a41df5bf5250aee782 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 28 Sep 2023 14:11:01 -0700 -Subject: [PATCH 404/413] 6.8: arm64: dts: imx8mp-venice-gw72xx: add TPM device - -Add the TPM device found on the GW72xx revision F PCB. - -Signed-off-by: Tim Harvey ---- - .../arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi -@@ -83,8 +83,15 @@ - &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &gpio4 { -@@ -286,6 +293,7 @@ - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 -+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 - >; - }; - diff --git a/target/linux/imx/patches-6.6/405-6.9-arm64-dts-imx8mm-venice-gw71xx-add-TPM-device.patch b/target/linux/imx/patches-6.6/405-6.9-arm64-dts-imx8mm-venice-gw71xx-add-TPM-device.patch deleted file mode 100644 index 57ad826668..0000000000 --- a/target/linux/imx/patches-6.6/405-6.9-arm64-dts-imx8mm-venice-gw71xx-add-TPM-device.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 6cea7c46172eca323e9ce7e6aab8f8506eb92b4b Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Wed, 29 Nov 2023 09:53:04 -0800 -Subject: [PATCH 405/413] 6.9: arm64: dts: imx8mm-venice-gw71xx: add TPM device - -Add the TPM device found on the GW71xx revision E PCB. - -Signed-off-by: Tim Harvey ---- - .../arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi -@@ -53,8 +53,15 @@ - &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &gpio1 { -@@ -201,6 +208,7 @@ - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 -+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 - >; - }; - diff --git a/target/linux/imx/patches-6.6/406-6.9-arm64-dts-imx8mp-venice-gw71xx-add-TPM-device.patch b/target/linux/imx/patches-6.6/406-6.9-arm64-dts-imx8mp-venice-gw71xx-add-TPM-device.patch deleted file mode 100644 index b96fc907a4..0000000000 --- a/target/linux/imx/patches-6.6/406-6.9-arm64-dts-imx8mp-venice-gw71xx-add-TPM-device.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 9095a68c0b7084a7819e697ef38d0c987531c8ab Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Wed, 29 Nov 2023 17:11:51 -0800 -Subject: [PATCH 406/413] 6.9: arm64: dts: imx8mp-venice-gw71xx: add TPM device - -Add the TPM device found on the GW71xx revision E PCB. - -Signed-off-by: Tim Harvey ---- - .../arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi -@@ -48,8 +48,15 @@ - &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &gpio4 { -@@ -217,6 +224,7 @@ - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 -+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 - >; - }; - diff --git a/target/linux/imx/patches-6.6/407-6.9-arm64-dts-imx8mm-venice-gw7901-add-digital-I-O-d.patch b/target/linux/imx/patches-6.6/407-6.9-arm64-dts-imx8mm-venice-gw7901-add-digital-I-O-d.patch deleted file mode 100644 index ebee3c4be1..0000000000 --- a/target/linux/imx/patches-6.6/407-6.9-arm64-dts-imx8mm-venice-gw7901-add-digital-I-O-d.patch +++ /dev/null @@ -1,34 +0,0 @@ -From e5bc89e60590581b0d31e8c6c6361c6caf5583bb Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Tue, 21 Nov 2023 11:12:24 -0800 -Subject: [PATCH 407/413] 6.9: arm64: dts: imx8mm-venice-gw7901: add digital - I/O direction control GPIO's - -The GW7901 has GPIO's to configure the direction of its isolated -digital I/O signals. Add the GPIO pinmux and line names. - -Signed-off-by: Tim Harvey ---- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts -@@ -319,7 +319,7 @@ - - &gpio4 { - gpio-line-names = "", "", "", "", -- "", "", "uart3_rs232#", "uart3_rs422#", -+ "dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#", - "uart3_rs485#", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; -@@ -842,6 +842,8 @@ - - pinctrl_hog: hoggrp { - fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIG1_CTL */ -+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000041 /* DIG2_CTL */ - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ diff --git a/target/linux/imx/patches-6.6/408-6.9-arm64-dts-imx8mm-venice-gw7901-add-TPM-device.patch b/target/linux/imx/patches-6.6/408-6.9-arm64-dts-imx8mm-venice-gw7901-add-TPM-device.patch deleted file mode 100644 index e86c29fbb8..0000000000 --- a/target/linux/imx/patches-6.6/408-6.9-arm64-dts-imx8mm-venice-gw7901-add-TPM-device.patch +++ /dev/null @@ -1,45 +0,0 @@ -From f905e9a03cdf8edf6fa719ba89f37e6138c33834 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Tue, 21 Nov 2023 11:44:38 -0800 -Subject: [PATCH 408/413] 6.9: arm64: dts: imx8mm-venice-gw7901: add TPM device - -Add the TPM device found on the GW7901 revision D PCB. - -Signed-off-by: Tim Harvey ---- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts -@@ -285,7 +285,8 @@ - &ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; -- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, -+ <&gpio4 24 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { -@@ -294,6 +295,12 @@ - spi-max-frequency = <40000000>; - status = "okay"; - }; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &fec1 { -@@ -989,6 +996,7 @@ - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 -+ MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 - >; - }; - diff --git a/target/linux/imx/patches-6.6/409-6.9-arm64-dts-freescale-imx8mp-venice-gw72xx-2x-fix-.patch b/target/linux/imx/patches-6.6/409-6.9-arm64-dts-freescale-imx8mp-venice-gw72xx-2x-fix-.patch deleted file mode 100644 index 2c63d7c339..0000000000 --- a/target/linux/imx/patches-6.6/409-6.9-arm64-dts-freescale-imx8mp-venice-gw72xx-2x-fix-.patch +++ /dev/null @@ -1,38 +0,0 @@ -From fddb089c2ccfb8bc4bd3aba605f7eadfd9f36cfd Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Wed, 28 Feb 2024 10:22:11 -0800 -Subject: [PATCH 409/413] 6.9: arm64: dts: freescale: imx8mp-venice-gw72xx-2x: - fix USB vbus regulator - -When using usb-conn-gpio to control USB role and VBUS, the vbus-supply -property must be present in the usb-conn-gpio node. Additionally it -should not be present in the phy node as that isn't what controls vbus -and will upset the use count. - -This resolves an issue where VBUS is enabled with OTG in peripheral -mode. - -Fixes: 86c43ae03ab9 ("arm64: dts: freescale: Add imx8mp-venice-gw72xx-2x") -Signed-off-by: Tim Harvey ---- - arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi -@@ -169,7 +169,6 @@ - }; - - &usb3_phy0 { -- vbus-supply = <®_usb1_vbus>; - status = "okay"; - }; - -@@ -189,6 +188,7 @@ - pinctrl-0 = <&pinctrl_usbcon1>; - type = "micro"; - label = "otg"; -+ vbus-supply = <®_usb1_vbus>; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/target/linux/imx/patches-6.6/410-6.9-arm64-dts-freescale-imx8mp-venice-gw73xx-2x-fix-.patch b/target/linux/imx/patches-6.6/410-6.9-arm64-dts-freescale-imx8mp-venice-gw73xx-2x-fix-.patch deleted file mode 100644 index 53851b9d1b..0000000000 --- a/target/linux/imx/patches-6.6/410-6.9-arm64-dts-freescale-imx8mp-venice-gw73xx-2x-fix-.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 69e3ce6d0c2f518bf9574112f3d4cc619c38602c Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Wed, 28 Feb 2024 10:24:19 -0800 -Subject: [PATCH 410/413] 6.9: arm64: dts: freescale: imx8mp-venice-gw73xx-2x: - fix USB vbus regulator - -When using usb-conn-gpio to control USB role and VBUS, the vbus-supply -property must be present in the usb-conn-gpio node. Additionally it -should not be present in the phy node as that isn't what controls vbus -and will upset the use count. - -This resolves an issue where VBUS is enabled with OTG in peripheral -mode. - -Fixes: 716ced308234 ("arm64: dts: freescale: Add imx8mp-venice-gw73xx-2x") -Signed-off-by: Tim Harvey ---- - arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi -@@ -188,7 +188,6 @@ - }; - - &usb3_phy0 { -- vbus-supply = <®_usb1_vbus>; - status = "okay"; - }; - -@@ -208,6 +207,7 @@ - pinctrl-0 = <&pinctrl_usbcon1>; - type = "micro"; - label = "otg"; -+ vbus-supply = <®_usb1_vbus>; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/target/linux/imx/patches-6.6/411-6.10-arm64-dts-imx8mp-venice-gw74xx-add-ADC-rail-for.patch b/target/linux/imx/patches-6.6/411-6.10-arm64-dts-imx8mp-venice-gw74xx-add-ADC-rail-for.patch deleted file mode 100644 index afebad1748..0000000000 --- a/target/linux/imx/patches-6.6/411-6.10-arm64-dts-imx8mp-venice-gw74xx-add-ADC-rail-for.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 9d75bdd797d32c859d0dd9f54acc30de63831eb1 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Mon, 29 Jan 2024 15:28:39 -0800 -Subject: [PATCH 411/413] 6.10: arm64: dts: imx8mp-venice-gw74xx: add ADC rail - for VDD_1P0 - -The imx8mp-venice-gw74xx revB PCB added an ADC rail for -VDD_1P0. Add it to the GSC ADC rails. - -Fixes: 531936b218d8 ("arm64: dts: imx8mp-venice-gw74xx: update to revB PCB") -Signed-off-by: Tim Harvey ---- - arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts -@@ -391,6 +391,12 @@ - label = "vdd_dram"; - }; - -+ channel@9e { -+ gw,mode = <2>; -+ reg = <0x9e>; -+ label = "vdd_1p0"; -+ }; -+ - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; diff --git a/target/linux/imx/patches-6.6/412-6.10-arm64-dts-imx8mp-venice-gw72xx-add-mac-addr-for.patch b/target/linux/imx/patches-6.6/412-6.10-arm64-dts-imx8mp-venice-gw72xx-add-mac-addr-for.patch deleted file mode 100644 index 567571c15e..0000000000 --- a/target/linux/imx/patches-6.6/412-6.10-arm64-dts-imx8mp-venice-gw72xx-add-mac-addr-for.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 482fe0cb90d3376051304531a01edccac9ca1868 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 29 Feb 2024 10:05:26 -0800 -Subject: [PATCH 412/413] 6.10: arm64: dts: imx8mp-venice-gw72xx: add mac addr - for eth1 - -Add the PCI bus topology for eth1 so that boot firmware can set the -local-mac-address property. - -The eth1 device is behind a PCI switch: - # lspci -n - 00:00.0 0604: 16c3:abcd (rev 01) - 01:00.0 0604: 12d8:b404 (rev 01) - 02:01.0 0604: 12d8:b404 (rev 01) - 02:02.0 0604: 12d8:b404 (rev 01) - 02:03.0 0604: 12d8:b404 (rev 01) - 05:00.0 0200: 11ab:4380 - # lspci -t - -[0000:00]---00.0-[01-ff]----00.0-[02-05]--+-01.0-[03]-- - +-02.0-[04]-- - \-03.0-[05]----00.0 - -Signed-off-by: Tim Harvey ---- - .../dts/freescale/imx8mp-venice-gw72xx.dtsi | 37 +++++++++++++++++++ - 1 file changed, 37 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi -@@ -8,6 +8,10 @@ - #include - - / { -+ aliases { -+ ethernet1 = ð1; -+ }; -+ - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; -@@ -137,6 +141,39 @@ - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@3,0 { -+ reg = <0x1800 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ eth1: ethernet@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ local-mac-address = [00 00 00 00 00 00]; -+ }; -+ }; -+ }; -+ }; - }; - - /* GPS */ diff --git a/target/linux/imx/patches-6.6/413-6.10-arm64-dts-imx8mp-venice-gw73xx-add-mac-addr-for.patch b/target/linux/imx/patches-6.6/413-6.10-arm64-dts-imx8mp-venice-gw73xx-add-mac-addr-for.patch deleted file mode 100644 index faf9373ec3..0000000000 --- a/target/linux/imx/patches-6.6/413-6.10-arm64-dts-imx8mp-venice-gw73xx-add-mac-addr-for.patch +++ /dev/null @@ -1,82 +0,0 @@ -From caac9b614ee63f875b290fda429706f6ef36e2f1 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 29 Feb 2024 10:12:49 -0800 -Subject: [PATCH 413/413] 6.10: arm64: dts: imx8mp-venice-gw73xx: add mac addr - for eth1 - -Add the PCI bus topology for eth1 so that boot firmware can set the -local-mac-address property. - -The eth1 device is behind a PCI switch: - # lspci -n - 00:00.0 0604: 16c3:abcd (rev 01) - 01:00.0 0604: 12d8:2608 - 02:01.0 0604: 12d8:2608 - 02:02.0 0604: 12d8:2608 - 02:03.0 0604: 12d8:2608 - 02:04.0 0604: 12d8:2608 - c0:00.0 0200: 1055:7430 (rev 11) - # lspci -t - -[0000:00]---00.0-[01-ff]----00.0-[02-fe]--+-01.0-[03-41]-- - +-02.0-[42-80]-- - +-03.0-[81-bf]-- - \-04.0-[c0-fe]----00.0 - -Signed-off-by: Tim Harvey ---- - .../dts/freescale/imx8mp-venice-gw73xx.dtsi | 37 +++++++++++++++++++ - 1 file changed, 37 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi -@@ -8,6 +8,10 @@ - #include - - / { -+ aliases { -+ ethernet1 = ð1; -+ }; -+ - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; -@@ -149,6 +153,39 @@ - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@4,0 { -+ reg = <0x2000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ eth1: ethernet@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ local-mac-address = [00 00 00 00 00 00]; -+ }; -+ }; -+ }; -+ }; - }; - - /* GPS */ diff --git a/target/linux/imx/patches-6.6/500-6.13-arm64-dts-imx8mm-venice-add-RTC-aliases.patch b/target/linux/imx/patches-6.6/500-6.13-arm64-dts-imx8mm-venice-add-RTC-aliases.patch deleted file mode 100644 index 2d398defc4..0000000000 --- a/target/linux/imx/patches-6.6/500-6.13-arm64-dts-imx8mm-venice-add-RTC-aliases.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 82b521f4bb8cab09aa016acf2c1b55ffc736eb2e Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Mon, 9 Sep 2024 15:15:01 -0700 -Subject: [PATCH] arm64: dts: imx8mm-venice-*: add RTC aliases - -Add aliases for the RTCs on the Gateworks Venice boards and on the imx8m -SoC. This ensures that the primary RTC is always the one on-board -provided by the Gateworks System Controller (GSC) which is battery -backed as opposed to the one in the IMX8M. - -Signed-off-by: Tim Harvey -Signed-off-by: Shawn Guo ---- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi | 7 ++++++- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 4 +++- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 4 +++- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts | 4 +++- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts | 7 ++++++- - arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts | 4 +++- - arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi | 4 +++- - arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 4 +++- - 8 files changed, 30 insertions(+), 8 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi -@@ -8,6 +8,11 @@ - #include - - / { -+ aliases { -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; -+ }; -+ - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; -@@ -272,7 +277,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts -@@ -22,6 +22,8 @@ - ethernet2 = &lan2; - ethernet3 = &lan3; - ethernet4 = &lan4; -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; -@@ -495,7 +497,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts -@@ -19,6 +19,8 @@ - - aliases { - ethernet1 = ð1; -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; -@@ -562,7 +564,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts -@@ -18,6 +18,8 @@ - - aliases { - ethernet0 = &fec1; -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; - usb0 = &usbotg1; - }; - -@@ -392,7 +394,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts -@@ -16,6 +16,11 @@ - model = "Gateworks Venice GW7904 i.MX8MM board"; - compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm"; - -+ aliases { -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; -+ }; -+ - chosen { - stdout-path = &uart2; - }; -@@ -436,7 +441,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts -@@ -17,6 +17,8 @@ - compatible = "gw,imx8mn-gw7902", "fsl,imx8mn"; - - aliases { -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; - usb0 = &usbotg1; - }; - -@@ -560,7 +562,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi -@@ -10,6 +10,8 @@ - / { - aliases { - ethernet0 = &eqos; -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; - }; - - memory@40000000 { -@@ -260,7 +262,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts -@@ -24,6 +24,8 @@ - ethernet4 = &lan3; - ethernet5 = &lan4; - ethernet6 = &lan5; -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; - }; - - chosen { -@@ -444,7 +446,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; diff --git a/target/linux/imx/patches-6.6/501-6.13-arm64-dts-imx8mp-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch b/target/linux/imx/patches-6.6/501-6.13-arm64-dts-imx8mp-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch deleted file mode 100644 index 14c8f88e31..0000000000 --- a/target/linux/imx/patches-6.6/501-6.13-arm64-dts-imx8mp-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e6d8fd29bd3d796a00ff9b69f9fae011aec3cb40 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 5 Sep 2024 11:32:28 -0700 -Subject: [PATCH] arm64: dts: imx8mp-venice-gw74xx: add M2SKT_GPIO10 gpio - configuration - -The GW74xx D revision has added a M2SKT_GPIO10 GPIO which routes to the -GPIO10 pin of the M.2 socket for compatibility with certain devices. - -Add the iomux and a line name for this. - -Signed-off-by: Tim Harvey -Signed-off-by: Shawn Guo ---- - arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts -@@ -264,7 +264,7 @@ - &gpio3 { - gpio-line-names = - "", "", "", "", "", "", "m2_rst", "", -- "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "m2_gpio10", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; -@@ -786,6 +786,7 @@ - MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ - MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ - MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ -+ MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_GPIO10 */ - MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ - MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ - MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ diff --git a/target/linux/imx/patches-6.6/502-6.13-arm64-dts-freescale-rename-gw7905-to-gw75xx.patch b/target/linux/imx/patches-6.6/502-6.13-arm64-dts-freescale-rename-gw7905-to-gw75xx.patch deleted file mode 100644 index 056b85002e..0000000000 --- a/target/linux/imx/patches-6.6/502-6.13-arm64-dts-freescale-rename-gw7905-to-gw75xx.patch +++ /dev/null @@ -1,1426 +0,0 @@ -From 14c3de96e14b30b1b83016abe607034a5a7e1c6b Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Wed, 24 Jan 2024 10:16:03 -0800 -Subject: [PATCH] arm64: dts: freescale: rename gw7905 to gw75xx - -The GW7905 was renamed to GW7500 before production release. - -Signed-off-by: Tim Harvey ---- - Documentation/devicetree/bindings/arm/fsl.yaml | 4 ++-- - arch/arm64/boot/dts/freescale/Makefile | 4 ++-- - ...8mm-venice-gw7905-0x.dts => imx8mm-venice-gw75xx-0x.dts} | 6 +++--- - ...{imx8mm-venice-gw7905.dtsi => imx8mm-venice-gw75xx.dtsi} | 0 - ...8mp-venice-gw7905-2x.dts => imx8mp-venice-gw75xx-2x.dts} | 6 +++--- - ...{imx8mp-venice-gw7905.dtsi => imx8mp-venice-gw75xx.dtsi} | 0 - 6 files changed, 10 insertions(+), 10 deletions(-) - rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw7905-0x.dts => imx8mm-venice-gw75xx-0x.dts} (67%) - rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw7905.dtsi => imx8mm-venice-gw75xx.dtsi} (100%) - rename arch/arm64/boot/dts/freescale/{imx8mp-venice-gw7905-2x.dts => imx8mp-venice-gw75xx-2x.dts} (67%) - rename arch/arm64/boot/dts/freescale/{imx8mp-venice-gw7905.dtsi => imx8mp-venice-gw75xx.dtsi} (100%) - ---- a/Documentation/devicetree/bindings/arm/fsl.yaml -+++ b/Documentation/devicetree/bindings/arm/fsl.yaml -@@ -908,8 +908,8 @@ properties: - - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - - fsl,imx8mm-evk # i.MX8MM EVK Board - - fsl,imx8mm-evkb # i.MX8MM EVKB Board -+ - gateworks,imx8mm-gw75xx-0x # i.MX8MM Gateworks Board - - gateworks,imx8mm-gw7904 -- - gateworks,imx8mm-gw7905-0x # i.MX8MM Gateworks Board - - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit - - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit - - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit -@@ -1036,7 +1036,7 @@ properties: - - gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board - - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board - - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board -- - gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board -+ - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board - - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules - - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT - - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -72,11 +72,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw75xx-0x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb --dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7905-0x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb -@@ -107,7 +107,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice- - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb --dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw75xx-2x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905-0x.dts -+++ /dev/null -@@ -1,28 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR MIT) --/* -- * Copyright 2023 Gateworks Corporation -- */ -- --/dts-v1/; -- --#include "imx8mm.dtsi" --#include "imx8mm-venice-gw700x.dtsi" --#include "imx8mm-venice-gw7905.dtsi" -- --/ { -- model = "Gateworks Venice GW7905-0x i.MX8MM Development Kit"; -- compatible = "gateworks,imx8mm-gw7905-0x", "fsl,imx8mm"; -- -- chosen { -- stdout-path = &uart2; -- }; --}; -- --/* Disable SOM interfaces not used on baseboard */ --&fec1 { -- status = "disabled"; --}; -- --&usdhc1 { -- status = "disabled"; --}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx-0x.dts -@@ -0,0 +1,28 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2023 Gateworks Corporation -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm.dtsi" -+#include "imx8mm-venice-gw700x.dtsi" -+#include "imx8mm-venice-gw75xx.dtsi" -+ -+/ { -+ model = "Gateworks Venice GW75xx-0x i.MX8MM Development Kit"; -+ compatible = "gateworks,imx8mm-gw75xx-0x", "fsl,imx8mm"; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+}; -+ -+/* Disable SOM interfaces not used on baseboard */ -+&fec1 { -+ status = "disabled"; -+}; -+ -+&usdhc1 { -+ status = "disabled"; -+}; ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905-2x.dts -+++ /dev/null -@@ -1,28 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR MIT) --/* -- * Copyright 2023 Gateworks Corporation -- */ -- --/dts-v1/; -- --#include "imx8mp.dtsi" --#include "imx8mp-venice-gw702x.dtsi" --#include "imx8mp-venice-gw7905.dtsi" -- --/ { -- model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit"; -- compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp"; -- -- chosen { -- stdout-path = &uart2; -- }; --}; -- --/* Disable SOM interfaces not used on baseboard */ --&eqos { -- status = "disabled"; --}; -- --&usdhc1 { -- status = "disabled"; --}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx-2x.dts -@@ -0,0 +1,28 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2023 Gateworks Corporation -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mp.dtsi" -+#include "imx8mp-venice-gw702x.dtsi" -+#include "imx8mp-venice-gw75xx.dtsi" -+ -+/ { -+ model = "Gateworks Venice GW75xx-2x i.MX8MP Development Kit"; -+ compatible = "gateworks,imx8mp-gw75xx-2x", "fsl,imx8mp"; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+}; -+ -+/* Disable SOM interfaces not used on baseboard */ -+&eqos { -+ status = "disabled"; -+}; -+ -+&usdhc1 { -+ status = "disabled"; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi -@@ -0,0 +1,303 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2023 Gateworks Corporation -+ */ -+ -+#include -+#include -+#include -+ -+/ { -+ led-controller { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_leds>; -+ -+ led-0 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ }; -+ -+ pcie0_refclk: clock-pcie0 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pps>; -+ gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+ -+ reg_usb2_vbus: regulator-usb2-vbus { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usb2_en>; -+ regulator-name = "usb2_vbus"; -+ gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_usdhc2_vmmc: regulator-usdhc2 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; -+ regulator-name = "SD2_3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+}; -+ -+/* off-board header */ -+&ecspi2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spi2>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&gpio1 { -+ gpio-line-names = -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "gpioa", "gpiob", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = -+ "", "", "", "pci_usb_sel", -+ "", "", "", "pci_wdis#", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio5 { -+ gpio-line-names = -+ "", "", "", "", -+ "gpioc", "gpiod", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ eeprom@52 { -+ compatible = "atmel,24c32"; -+ reg = <0x52>; -+ pagesize = <32>; -+ }; -+}; -+ -+/* off-board header */ -+&i2c3 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ fsl,refclk-pad-mode = ; -+ fsl,clkreq-unsupported; -+ clocks = <&pcie0_refclk>; -+ clock-names = "ref"; -+ status = "okay"; -+}; -+ -+&pcie0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+/* GPS */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+/* USB1 - Type C front panel SINK port J14 */ -+&usbotg1 { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+/* USB2 4-port USB3.0 HUB: -+ * P1 - USBC connector (host only) -+ * P2 - USB2 test connector -+ * P3 - miniPCIe full card -+ * P4 - miniPCIe half card -+ */ -+&usbotg2 { -+ dr_mode = "host"; -+ vbus-supply = <®_usb2_vbus>; -+ status = "okay"; -+}; -+ -+/* microSD */ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */ -+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */ -+ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */ -+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */ -+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */ -+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */ -+ >; -+ }; -+ -+ pinctrl_gpio_leds: gpioledgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */ -+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */ -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 -+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 -+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 -+ >; -+ }; -+ -+ pinctrl_pcie0: pciegrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106 -+ >; -+ }; -+ -+ pinctrl_pps: ppsgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106 -+ >; -+ }; -+ -+ pinctrl_reg_usb2_en: regusb2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */ -+ >; -+ }; -+ -+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 -+ >; -+ }; -+ -+ pinctrl_spi2: spi2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140 -+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140 -+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140 -+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 -+ >; -+ }; -+}; ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905.dtsi -+++ /dev/null -@@ -1,303 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR MIT) --/* -- * Copyright 2023 Gateworks Corporation -- */ -- --#include --#include --#include -- --/ { -- led-controller { -- compatible = "gpio-leds"; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_gpio_leds>; -- -- led-0 { -- function = LED_FUNCTION_STATUS; -- color = ; -- gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; -- default-state = "on"; -- linux,default-trigger = "heartbeat"; -- }; -- -- led-1 { -- function = LED_FUNCTION_STATUS; -- color = ; -- gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; -- default-state = "off"; -- }; -- }; -- -- pcie0_refclk: clock-pcie0 { -- compatible = "fixed-clock"; -- #clock-cells = <0>; -- clock-frequency = <100000000>; -- }; -- -- pps { -- compatible = "pps-gpio"; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_pps>; -- gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; -- status = "okay"; -- }; -- -- reg_usb2_vbus: regulator-usb2-vbus { -- compatible = "regulator-fixed"; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_reg_usb2_en>; -- regulator-name = "usb2_vbus"; -- gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; -- enable-active-high; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- }; -- -- reg_usdhc2_vmmc: regulator-usdhc2 { -- compatible = "regulator-fixed"; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; -- regulator-name = "SD2_3P3V"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -- enable-active-high; -- }; --}; -- --/* off-board header */ --&ecspi2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -- status = "okay"; --}; -- --&gpio1 { -- gpio-line-names = -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "gpioa", "gpiob", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", ""; --}; -- --&gpio4 { -- gpio-line-names = -- "", "", "", "pci_usb_sel", -- "", "", "", "pci_wdis#", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", ""; --}; -- --&gpio5 { -- gpio-line-names = -- "", "", "", "", -- "gpioc", "gpiod", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", ""; --}; -- --&i2c2 { -- clock-frequency = <400000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_i2c2>; -- status = "okay"; -- -- eeprom@52 { -- compatible = "atmel,24c32"; -- reg = <0x52>; -- pagesize = <32>; -- }; --}; -- --/* off-board header */ --&i2c3 { -- clock-frequency = <400000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_i2c3>; -- status = "okay"; --}; -- --&pcie_phy { -- fsl,refclk-pad-mode = ; -- fsl,clkreq-unsupported; -- clocks = <&pcie0_refclk>; -- clock-names = "ref"; -- status = "okay"; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_pcie0>; -- reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; -- status = "okay"; --}; -- --/* GPS */ --&uart1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_uart1>; -- status = "okay"; --}; -- --/* USB1 - Type C front panel SINK port J14 */ --&usbotg1 { -- dr_mode = "peripheral"; -- status = "okay"; --}; -- --/* USB2 4-port USB3.0 HUB: -- * P1 - USBC connector (host only) -- * P2 - USB2 test connector -- * P3 - miniPCIe full card -- * P4 - miniPCIe half card -- */ --&usbotg2 { -- dr_mode = "host"; -- vbus-supply = <®_usb2_vbus>; -- status = "okay"; --}; -- --/* microSD */ --&usdhc2 { -- pinctrl-names = "default", "state_100mhz", "state_200mhz"; -- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -- vmmc-supply = <®_usdhc2_vmmc>; -- bus-width = <4>; -- status = "okay"; --}; -- --&iomuxc { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_hog>; -- -- pinctrl_hog: hoggrp { -- fsl,pins = < -- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */ -- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */ -- MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */ -- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */ -- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */ -- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */ -- >; -- }; -- -- pinctrl_gpio_leds: gpioledgrp { -- fsl,pins = < -- MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */ -- MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */ -- >; -- }; -- -- pinctrl_i2c2: i2c2grp { -- fsl,pins = < -- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 -- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 -- >; -- }; -- -- pinctrl_i2c3: i2c3grp { -- fsl,pins = < -- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 -- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 -- >; -- }; -- -- pinctrl_pcie0: pciegrp { -- fsl,pins = < -- MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106 -- >; -- }; -- -- pinctrl_pps: ppsgrp { -- fsl,pins = < -- MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106 -- >; -- }; -- -- pinctrl_reg_usb2_en: regusb2grp { -- fsl,pins = < -- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */ -- >; -- }; -- -- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { -- fsl,pins = < -- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 -- >; -- }; -- -- pinctrl_spi2: spi2grp { -- fsl,pins = < -- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140 -- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140 -- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140 -- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140 -- >; -- }; -- -- pinctrl_uart1: uart1grp { -- fsl,pins = < -- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 -- >; -- }; -- -- pinctrl_usdhc2: usdhc2grp { -- fsl,pins = < -- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 -- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 -- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 -- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 -- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 -- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 -- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 -- >; -- }; -- -- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -- fsl,pins = < -- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 -- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 -- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 -- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 -- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 -- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 -- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 -- >; -- }; -- -- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -- fsl,pins = < -- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 -- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 -- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 -- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 -- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 -- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 -- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 -- >; -- }; -- -- pinctrl_usdhc2_gpio: usdhc2gpiogrp { -- fsl,pins = < -- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 -- >; -- }; --}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi -@@ -0,0 +1,309 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2023 Gateworks Corporation -+ */ -+ -+#include -+#include -+#include -+ -+/ { -+ led-controller { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_leds>; -+ -+ led-0 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ }; -+ -+ pcie0_refclk: pcie0-refclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pps>; -+ gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+ -+ reg_usb2_vbus: regulator-usb2-vbus { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usb2_en>; -+ compatible = "regulator-fixed"; -+ regulator-name = "usb2_vbus"; -+ gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_usdhc2_vmmc: regulator-usdhc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; -+ compatible = "regulator-fixed"; -+ regulator-name = "SD2_3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+}; -+ -+/* off-board header */ -+&ecspi2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spi2>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&gpio4 { -+ gpio-line-names = -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "gpioa", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = -+ "", "gpiod", "", "", -+ "gpiob", "gpioc", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "pci_usb_sel", "", -+ "pci_wdis#", "", "", ""; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ eeprom@52 { -+ compatible = "atmel,24c32"; -+ reg = <0x52>; -+ pagesize = <32>; -+ }; -+}; -+ -+/* off-board header */ -+&i2c3 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ fsl,refclk-pad-mode = ; -+ fsl,clkreq-unsupported; -+ clocks = <&pcie0_refclk>; -+ clock-names = "ref"; -+ status = "okay"; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+/* GPS */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+/* USB1 - Type C front panel SINK port J14 */ -+&usb3_0 { -+ status = "okay"; -+}; -+ -+&usb3_phy0 { -+ status = "okay"; -+}; -+ -+&usb_dwc3_0 { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+/* USB2 4-port USB3.0 HUB: -+ * P1 - USBC connector (host only) -+ * P2 - USB2 test connector -+ * P3 - miniPCIe full card -+ * P4 - miniPCIe half card -+ */ -+&usb3_phy1 { -+ vbus-supply = <®_usb2_vbus>; -+ status = "okay"; -+}; -+ -+&usb3_1 { -+ fsl,permanently-attached; -+ fsl,disable-port-power-control; -+ status = "okay"; -+}; -+ -+&usb_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+/* microSD */ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */ -+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */ -+ MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */ -+ MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */ -+ MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */ -+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */ -+ >; -+ }; -+ -+ pinctrl_gpio_leds: gpioledgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ -+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */ -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 -+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 -+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 -+ >; -+ }; -+ -+ pinctrl_pcie0: pciegrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 -+ >; -+ }; -+ -+ pinctrl_pps: ppsgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 -+ >; -+ }; -+ -+ pinctrl_reg_usb2_en: regusb2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */ -+ >; -+ }; -+ -+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 -+ >; -+ }; -+ -+ pinctrl_spi2: spi2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 -+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 -+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 -+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 -+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 -+ >; -+ }; -+}; ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905.dtsi -+++ /dev/null -@@ -1,309 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR MIT) --/* -- * Copyright 2023 Gateworks Corporation -- */ -- --#include --#include --#include -- --/ { -- led-controller { -- compatible = "gpio-leds"; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_gpio_leds>; -- -- led-0 { -- function = LED_FUNCTION_STATUS; -- color = ; -- gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; -- default-state = "on"; -- linux,default-trigger = "heartbeat"; -- }; -- -- led-1 { -- function = LED_FUNCTION_STATUS; -- color = ; -- gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; -- default-state = "off"; -- }; -- }; -- -- pcie0_refclk: pcie0-refclk { -- compatible = "fixed-clock"; -- #clock-cells = <0>; -- clock-frequency = <100000000>; -- }; -- -- pps { -- compatible = "pps-gpio"; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_pps>; -- gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; -- status = "okay"; -- }; -- -- reg_usb2_vbus: regulator-usb2-vbus { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_reg_usb2_en>; -- compatible = "regulator-fixed"; -- regulator-name = "usb2_vbus"; -- gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; -- enable-active-high; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- }; -- -- reg_usdhc2_vmmc: regulator-usdhc2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; -- compatible = "regulator-fixed"; -- regulator-name = "SD2_3P3V"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -- enable-active-high; -- }; --}; -- --/* off-board header */ --&ecspi2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -- status = "okay"; --}; -- --&gpio4 { -- gpio-line-names = -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "gpioa", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", ""; --}; -- --&gpio4 { -- gpio-line-names = -- "", "gpiod", "", "", -- "gpiob", "gpioc", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "pci_usb_sel", "", -- "pci_wdis#", "", "", ""; --}; -- --&i2c2 { -- clock-frequency = <400000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_i2c2>; -- status = "okay"; -- -- eeprom@52 { -- compatible = "atmel,24c32"; -- reg = <0x52>; -- pagesize = <32>; -- }; --}; -- --/* off-board header */ --&i2c3 { -- clock-frequency = <400000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_i2c3>; -- status = "okay"; --}; -- --&pcie_phy { -- fsl,refclk-pad-mode = ; -- fsl,clkreq-unsupported; -- clocks = <&pcie0_refclk>; -- clock-names = "ref"; -- status = "okay"; --}; -- --&pcie { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_pcie0>; -- reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; -- status = "okay"; --}; -- --/* GPS */ --&uart1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_uart1>; -- status = "okay"; --}; -- --/* USB1 - Type C front panel SINK port J14 */ --&usb3_0 { -- status = "okay"; --}; -- --&usb3_phy0 { -- status = "okay"; --}; -- --&usb_dwc3_0 { -- dr_mode = "peripheral"; -- status = "okay"; --}; -- --/* USB2 4-port USB3.0 HUB: -- * P1 - USBC connector (host only) -- * P2 - USB2 test connector -- * P3 - miniPCIe full card -- * P4 - miniPCIe half card -- */ --&usb3_phy1 { -- vbus-supply = <®_usb2_vbus>; -- status = "okay"; --}; -- --&usb3_1 { -- fsl,permanently-attached; -- fsl,disable-port-power-control; -- status = "okay"; --}; -- --&usb_dwc3_1 { -- dr_mode = "host"; -- status = "okay"; --}; -- --/* microSD */ --&usdhc2 { -- pinctrl-names = "default", "state_100mhz", "state_200mhz"; -- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -- vmmc-supply = <®_usdhc2_vmmc>; -- bus-width = <4>; -- status = "okay"; --}; -- --&iomuxc { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_hog>; -- -- pinctrl_hog: hoggrp { -- fsl,pins = < -- MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */ -- MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */ -- MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */ -- MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */ -- MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */ -- MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */ -- >; -- }; -- -- pinctrl_gpio_leds: gpioledgrp { -- fsl,pins = < -- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ -- MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */ -- >; -- }; -- -- pinctrl_i2c2: i2c2grp { -- fsl,pins = < -- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 -- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 -- >; -- }; -- -- pinctrl_i2c3: i2c3grp { -- fsl,pins = < -- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 -- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 -- >; -- }; -- -- pinctrl_pcie0: pciegrp { -- fsl,pins = < -- MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 -- >; -- }; -- -- pinctrl_pps: ppsgrp { -- fsl,pins = < -- MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 -- >; -- }; -- -- pinctrl_reg_usb2_en: regusb2grp { -- fsl,pins = < -- MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */ -- >; -- }; -- -- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { -- fsl,pins = < -- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 -- >; -- }; -- -- pinctrl_spi2: spi2grp { -- fsl,pins = < -- MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 -- MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 -- MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 -- MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 -- >; -- }; -- -- pinctrl_uart1: uart1grp { -- fsl,pins = < -- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 -- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 -- >; -- }; -- -- pinctrl_usdhc2: usdhc2grp { -- fsl,pins = < -- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 -- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 -- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 -- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 -- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 -- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 -- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 -- >; -- }; -- -- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -- fsl,pins = < -- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 -- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 -- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 -- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 -- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 -- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 -- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 -- >; -- }; -- -- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -- fsl,pins = < -- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 -- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 -- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 -- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 -- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 -- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 -- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 -- >; -- }; -- -- pinctrl_usdhc2_gpio: usdhc2gpiogrp { -- fsl,pins = < -- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 -- >; -- }; --}; diff --git a/target/linux/imx/patches-6.6/503-6.13-arm64-dts-imx8m-venice-gw75xx-add-Accelerometer-device.patch b/target/linux/imx/patches-6.6/503-6.13-arm64-dts-imx8m-venice-gw75xx-add-Accelerometer-device.patch deleted file mode 100644 index f30b690423..0000000000 --- a/target/linux/imx/patches-6.6/503-6.13-arm64-dts-imx8m-venice-gw75xx-add-Accelerometer-device.patch +++ /dev/null @@ -1,79 +0,0 @@ -From ede044113c0418f11dbee09069ff1dd68f284dfa Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Fri, 18 Oct 2024 10:36:08 -0700 -Subject: [PATCH] arm64: dts: imx8m*-venice-gw75xx: add Accelerometer device - -The GW75xx has a LIS2DE12TR 3-axis accelerometer on the I2C bus with an -interrupt pin. Add it to the device-tree. - -Signed-off-by: Tim Harvey -Signed-off-by: Shawn Guo ---- - .../boot/dts/freescale/imx8mm-venice-gw75xx.dtsi | 16 ++++++++++++++++ - .../boot/dts/freescale/imx8mp-venice-gw75xx.dtsi | 16 ++++++++++++++++ - 2 files changed, 32 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi -@@ -116,6 +116,16 @@ - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - -+ accelerometer@19 { -+ compatible = "st,lis2de12"; -+ reg = <0x19>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_accel>; -+ interrupt-parent = <&gpio5>; -+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>; -+ st,drdy-int-pin = <1>; -+ }; -+ - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; -@@ -198,6 +208,12 @@ - >; - }; - -+ pinctrl_accel: accelgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x159 -+ >; -+ }; -+ - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */ ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi -@@ -104,6 +104,16 @@ - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - -+ accelerometer@19 { -+ compatible = "st,lis2de12"; -+ reg = <0x19>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_accel>; -+ interrupt-parent = <&gpio5>; -+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>; -+ st,drdy-int-pin = <1>; -+ }; -+ - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; -@@ -204,6 +214,12 @@ - >; - }; - -+ pinctrl_accel: accelgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x159 -+ >; -+ }; -+ - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ diff --git a/target/linux/imx/patches-6.6/504-6.13-arm64-dts-imx-Add-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch b/target/linux/imx/patches-6.6/504-6.13-arm64-dts-imx-Add-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch deleted file mode 100644 index 8765474a8a..0000000000 --- a/target/linux/imx/patches-6.6/504-6.13-arm64-dts-imx-Add-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch +++ /dev/null @@ -1,1107 +0,0 @@ -From a79d2638a7150d1605fcadebb6baa36d27cdc48e Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 30 May 2024 10:21:45 -0700 -Subject: [PATCH] arm64: dts: imx: Add i.MX8M Plus Gateworks GW82XX-2X support - -The Gateworks GW82XX-2X is an ARM based single board computer (SBC) -comprised of the i.MX8M Plus based gw702x SoM and the gw82xx -baseboard featuring: - - i.MX8M Plus SoC - - LPDDR4 DRAM - - eMMC FLASH - - Gateworks System Controller (GSC) - - microSD (1.8V/3.3V Capable) - - panel status bi-color LED - - pushbutton switch - - fan controller with tachometer - - USB Type-C connector - - PCIe switch - - 2x GbE RJ45 connectors - - multi-protocol RS232/RS485/RS422 Serial ports - - 2x Flexible Socket Adapters with SDIO/UART/USB/PCIe - (for M.2 and miniPCIe expansion) - - 2x isolated CAN - - GPS - - accelerometer - - magnetometer - - off-board connectors for: SPI, GPIO, I2C, ADC - - Wide range DC power input - - support for 802.3at PoE (via adapter) - -Signed-off-by: Tim Harvey ---- - .../devicetree/bindings/arm/fsl.yaml | 1 + - arch/arm64/boot/dts/freescale/Makefile | 1 + - .../dts/freescale/imx8mm-venice-gw82xx.dtsi | 460 +++++++++++++++ - .../boot/dts/freescale/imx8mp-venice-gw82xx-2 | 19 + - .../dts/freescale/imx8mp-venice-gw82xx-2x.dts | 19 + - .../dts/freescale/imx8mp-venice-gw82xx.dtsi | 533 ++++++++++++++++++ - 6 files changed, 1033 insertions(+) - create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw82xx.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2 - create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts - create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi - ---- a/Documentation/devicetree/bindings/arm/fsl.yaml -+++ b/Documentation/devicetree/bindings/arm/fsl.yaml -@@ -1037,6 +1037,7 @@ properties: - - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board - - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board -+ - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board - - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules - - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT - - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -108,6 +108,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice- - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw75xx-2x.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw82xx-2x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw82xx.dtsi -@@ -0,0 +1,460 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 Gateworks Corporation -+ */ -+ -+#include -+#include -+#include -+ -+/ { -+ aliases { -+ ethernet1 = ð1; -+ usb0 = &usbotg1; -+ usb1 = &usbotg2; -+ }; -+ -+ led-controller { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_leds>; -+ -+ led-0 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ }; -+ -+ pcie0_refclk: pcie0-refclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pps>; -+ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "1P8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_usb_otg1_vbus: regulator-usb-otg1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usb1_en>; -+ compatible = "regulator-fixed"; -+ regulator-name = "usb_otg1_vbus"; -+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_usb_otg2_vbus: regulator-usb-otg2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usb2_en>; -+ compatible = "regulator-fixed"; -+ regulator-name = "usb_otg2_vbus"; -+ gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_wifi_en: regulator-wifi-en { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_wl>; -+ compatible = "regulator-fixed"; -+ regulator-name = "wl"; -+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; -+ startup-delay-us = <100>; -+ enable-active-high; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+}; -+ -+/* off-board header */ -+&ecspi2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spi2>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ tpm@1 { -+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; -+}; -+ -+&gpio1 { -+ gpio-line-names = "rs485_term", "mipi_gpio4", "", "", -+ "", "", "pci_usb_sel", "dio0", -+ "", "dio1", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", -+ "mipi_gpio1", "", "", "pci_wdis#", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ accelerometer@19 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_accel>; -+ compatible = "st,lis2de12"; -+ reg = <0x19>; -+ st,drdy-int-pin = <1>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>; -+ }; -+ -+ // TODO: 0x6f PCIe switch -+}; -+ -+/* off-board header */ -+// TODO: i2c expander -+&i2c3 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ fsl,refclk-pad-mode = ; -+ fsl,clkreq-unsupported; -+ clocks = <&pcie0_refclk>; -+ clock-names = "ref"; -+ status = "okay"; -+}; -+ -+&pcie0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; -+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, -+ <&clk IMX8MM_CLK_PCIE1_AUX>; -+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, -+ <&clk IMX8MM_CLK_PCIE1_CTRL>; -+ assigned-clock-rates = <10000000>, <250000000>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, -+ <&clk IMX8MM_SYS_PLL2_250M>; -+ status = "okay"; -+ -+ // TODO: this changes - new switch -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@4,0 { -+ reg = <0x2000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ eth1: ethernet@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ local-mac-address = [00 00 00 00 00 00]; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+/* off-board header */ -+&sai3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "okay"; -+}; -+ -+/* GPS */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+/* bluetooth HCI */ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; -+ cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; -+ rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm4330-bt"; -+ shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+/* RS232 */ -+&uart4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart4>; -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ dr_mode = "otg"; -+ over-current-active-low; -+ vbus-supply = <®_usb_otg1_vbus>; -+ status = "okay"; -+}; -+ -+&usbotg2 { -+ dr_mode = "host"; -+ disable-over-current; -+ vbus-supply = <®_usb_otg2_vbus>; -+ status = "okay"; -+}; -+ -+/* SDIO WiFi */ -+&usdhc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ bus-width = <4>; -+ non-removable; -+ vmmc-supply = <®_wifi_en>; -+ status = "okay"; -+}; -+ -+/* microSD */ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ vmmc-supply = <®_3p3v>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ -+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ -+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ -+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ -+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ -+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */ -+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */ -+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */ -+ >; -+ }; -+ -+ pinctrl_accel: accelgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 -+ >; -+ }; -+ -+ pinctrl_bten: btengrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 -+ >; -+ }; -+ -+ pinctrl_gpio_leds: gpioledgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 -+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_pcie0: pcie0grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 -+ >; -+ }; -+ -+ pinctrl_pps: ppsgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 -+ >; -+ }; -+ -+ pinctrl_reg_wl: regwlgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 -+ >; -+ }; -+ -+ pinctrl_reg_usb1_en: regusb1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 -+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 -+ >; -+ }; -+ -+ pinctrl_reg_usb2_en: regusb2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 -+ >; -+ }; -+ -+ pinctrl_spi2: spi2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 -+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 -+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 -+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 -+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_uart3: uart3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 -+ MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140 -+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 -+ >; -+ }; -+ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 -+ MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2 -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2024 Gateworks Corporation -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm.dtsi" -+#include "imx8mm-venice-gw700x.dtsi" -+#include "imx8mm-venice-gw82xx.dtsi" -+ -+/ { -+ model = "Gateworks Venice GW82xx-0x i.MX8MM Development Kit"; -+ compatible = "gw,imx8mm-gw82xx-0x", "fsl,imx8mm"; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2024 Gateworks Corporation -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mp.dtsi" -+#include "imx8mp-venice-gw702x.dtsi" -+#include "imx8mp-venice-gw82xx.dtsi" -+ -+/ { -+ model = "Gateworks Venice GW82xx-2x i.MX8MP Development Kit"; -+ compatible = "gateworks,imx8mp-gw82xx-2x", "fsl,imx8mp"; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi -@@ -0,0 +1,533 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2024 Gateworks Corporation -+ */ -+ -+#include -+#include -+#include -+ -+/ { -+ aliases { -+ ethernet1 = ð1; -+ fsa1 = &fsa0; -+ fsa2 = &fsa1; -+ }; -+ -+ led-controller { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_leds>; -+ -+ led-0 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ }; -+ -+ pcie0_refclk: clock-pcie0 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pps>; -+ gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ reg_usb2_vbus: regulator-usb2 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usb2_en>; -+ regulator-name = "usb2_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc2_vmmc>; -+ regulator-name = "VDD_3V3_SD"; -+ regulator-max-microvolt = <3300000>; -+ regulator-min-microvolt = <3300000>; -+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ off-on-delay-us = <12000>; -+ startup-delay-us = <100>; -+ }; -+}; -+ -+&ecspi2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spi2>; -+ cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>, /* CS0 onboard TPM */ -+ <&gpio5 13 GPIO_ACTIVE_LOW>, /* CS1 off-board J32 SPI */ -+ <&gpio1 12 GPIO_ACTIVE_LOW>, /* CS3 off-board J52 FSA1 */ -+ <&gpio4 26 GPIO_ACTIVE_LOW>; /* CS2 off-board J51 FSA2 */ -+ status = "okay"; -+ -+ tpm@0 { -+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; -+ reg = <0x0>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_can1>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_can2>; -+ status = "okay"; -+}; -+ -+&gpio1 { -+ gpio-line-names = -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "fsa2_gpio1", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = -+ "", "", "", "", -+ "", "", "", "", -+ "dio1", "fsa1_gpio2", "", "dio0", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "rs485_en", "rs485_term", -+ "fsa2_gpio2", "fsa1_gpio1", "", "rs485_half", -+ "", "", "", ""; -+}; -+ -+&i2c2 { -+ accelerometer@19 { -+ compatible = "st,lis2de12"; -+ reg = <0x19>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_accel>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ st,drdy-int-pin = <1>; -+ }; -+ -+ magnetometer@1e { -+ compatible = "st,lis2mdl"; -+ reg = <0x1e>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mag>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <28 IRQ_TYPE_LEVEL_LOW>; -+ }; -+}; -+ -+&i2c3 { -+ i2c-mux@70 { -+ compatible = "nxp,pca9548"; -+ reg = <0x70>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* J30 */ -+ fsa1: i2c@0 { -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fsa2i2c>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gpio@20 { -+ compatible = "nxp,pca9555"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ eeprom@54 { -+ compatible = "atmel,24c02"; -+ reg = <0x54>; -+ pagesize = <16>; -+ }; -+ -+ eeprom@55 { -+ compatible = "atmel,24c02"; -+ reg = <0x55>; -+ pagesize = <16>; -+ }; -+ }; -+ -+ /* J29 */ -+ fsa0: i2c@1 { -+ reg = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fsa1i2c>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gpio@20 { -+ compatible = "nxp,pca9555"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <14 IRQ_TYPE_EDGE_FALLING>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ eeprom@54 { -+ compatible = "atmel,24c02"; -+ reg = <0x54>; -+ pagesize = <16>; -+ }; -+ -+ eeprom@55 { -+ compatible = "atmel,24c02"; -+ reg = <0x55>; -+ pagesize = <16>; -+ }; -+ }; -+ -+ /* J33 */ -+ i2c@2 { -+ reg = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+}; -+ -+&pcie_phy { -+ clocks = <&pcie0_refclk>; -+ clock-names = "ref"; -+ fsl,refclk-pad-mode = ; -+ fsl,clkreq-unsupported; -+ status = "okay"; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@7,0 { -+ reg = <0x3800 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ eth1: ethernet@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ local-mac-address = [00 00 00 00 00 00]; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+/* GPS */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+/* RS232 */ -+&uart4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart4>; -+ status = "okay"; -+}; -+ -+/* USB1 - FSA1 */ -+&usb3_0 { -+ fsl,permanently-attached; -+ fsl,disable-port-power-control; -+ status = "okay"; -+}; -+ -+&usb3_phy0 { -+ status = "okay"; -+}; -+ -+&usb_dwc3_0 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+/* USB2 - USB3.0 Hub */ -+&usb3_1 { -+ fsl,permanently-attached; -+ fsl,disable-port-power-control; -+ status = "okay"; -+}; -+ -+&usb3_phy1 { -+ vbus-supply = <®_usb2_vbus>; -+ status = "okay"; -+}; -+ -+&usb_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+/* SDIO 1.8V */ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+}; -+ -+/* microSD */ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; /* CD is active high */ -+ bus-width = <4>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ -+ MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ -+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ -+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ -+ MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ -+ >; -+ }; -+ -+ pinctrl_accel: accelgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ# */ -+ >; -+ }; -+ -+ pinctrl_can1: can1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 -+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 -+ >; -+ }; -+ -+ pinctrl_can2: can2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 -+ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 -+ >; -+ }; -+ -+ pinctrl_gpio_leds: gpioledgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ -+ MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ -+ >; -+ }; -+ -+ pinctrl_fsa1i2c: fsa1i2cgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1d0 /* FSA1_ALERT# */ -+ MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x400001d0 /* FSA1_GPIO1 */ -+ MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x400001d0 /* FSA1_GPIO2 */ -+ >; -+ }; -+ -+ pinctrl_fsa2i2c: fsa2i2cgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x1d0 /* FSA2_ALERT# */ -+ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x400001d0 /* FSA2_GPIO1 */ -+ MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x400001d0 /* FSA2_GPIO2 */ -+ >; -+ }; -+ -+ pinctrl_mag: maggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x140 /* IRQ# */ -+ >; -+ }; -+ -+ pinctrl_pcie0: pcie0grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 /* PERST# */ -+ >; -+ }; -+ -+ pinctrl_pps: ppsgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 -+ >; -+ }; -+ -+ pinctrl_reg_usb2_en: regusb2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ -+ >; -+ }; -+ -+ pinctrl_spi2: spi2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0xd0 -+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0xd0 -+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0xd0 -+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 /* J32_CS */ -+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 /* TPM_CS */ -+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 /* FSA1_CS */ -+ MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x140 /* FSA2_CS */ -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 -+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 -+ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 -+ >; -+ }; -+}; diff --git a/target/linux/imx/patches-6.6/600-PCI-imx6-Start-link-at-max-gen-first-for-IMX8MM-and-IMX8MP.patch b/target/linux/imx/patches-6.6/600-PCI-imx6-Start-link-at-max-gen-first-for-IMX8MM-and-IMX8MP.patch deleted file mode 100644 index c9878e55ad..0000000000 --- a/target/linux/imx/patches-6.6/600-PCI-imx6-Start-link-at-max-gen-first-for-IMX8MM-and-IMX8MP.patch +++ /dev/null @@ -1,121 +0,0 @@ -From cf983e4a04eecb5be93af7b53cb10805ee448998 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Mon, 21 Aug 2023 09:20:17 -0700 -Subject: [PATCH] PCI: imx6: Start link at max gen first for IMX8MM and IMX8MP - -commit fa33a6d87eac ("PCI: imx6: Start link in Gen1 before negotiating -for Gen2 mode") started link negotiation at Gen1 before attempting -faster speeds in order to work around an issue with a particular switch -on an IMX6Q SoC. - -This behavior is not the norm for PCI link negotiation and it has been -found to cause issues in other cases: -- IMX8MM with PI7C9X2G608GP switch: various endpoints (such as qca988x) - will fail to link more than 50% of the time -- IMX8MP with PI7C9X2G608GP switch: occasionally will fail to link with - switch and cause a CPU hang about 30% of the time - -Disable this behavior for IMX8MM and IMX8MP. - -Signed-off-by: Tim Harvey ---- - drivers/pci/controller/dwc/pci-imx6.c | 53 ++++++++++++++------------- - 1 file changed, 27 insertions(+), 26 deletions(-) - ---- a/drivers/pci/controller/dwc/pci-imx6.c -+++ b/drivers/pci/controller/dwc/pci-imx6.c -@@ -60,6 +60,7 @@ enum imx6_pcie_variants { - #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) - #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) - #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) -+#define IMX6_PCIE_FLAG_GEN1_LAST BIT(3) - - #define IMX6_PCIE_MAX_CLKS 6 - -@@ -836,26 +837,28 @@ static int imx6_pcie_start_link(struct d - u32 tmp; - int ret; - -- /* -- * Force Gen1 operation when starting the link. In case the link is -- * started in Gen2 mode, there is a possibility the devices on the -- * bus will not be detected at all. This happens with PCIe switches. -- */ -- dw_pcie_dbi_ro_wr_en(pci); -- tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); -- tmp &= ~PCI_EXP_LNKCAP_SLS; -- tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; -- dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); -- dw_pcie_dbi_ro_wr_dis(pci); -+ if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_GEN1_LAST)) { -+ /* -+ * Force Gen1 operation when starting the link. In case the link is -+ * started in Gen2 mode, there is a possibility the devices on the -+ * bus will not be detected at all. This happens with PCIe switches. -+ */ -+ dw_pcie_dbi_ro_wr_en(pci); -+ tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); -+ tmp &= ~PCI_EXP_LNKCAP_SLS; -+ tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; -+ dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); -+ dw_pcie_dbi_ro_wr_dis(pci); -+ } - - /* Start LTSSM. */ - imx6_pcie_ltssm_enable(dev); - -- ret = dw_pcie_wait_for_link(pci); -- if (ret) -- goto err_reset_phy; -+ if ((pci->link_gen > 1) && !(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_GEN1_LAST)) { -+ ret = dw_pcie_wait_for_link(pci); -+ if (ret) -+ goto err_reset_phy; - -- if (pci->link_gen > 1) { - /* Allow faster modes after the link is up */ - dw_pcie_dbi_ro_wr_en(pci); - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); -@@ -889,18 +892,14 @@ static int imx6_pcie_start_link(struct d - goto err_reset_phy; - } - } -- -- /* Make sure link training is finished as well! */ -- ret = dw_pcie_wait_for_link(pci); -- if (ret) -- goto err_reset_phy; -- } else { -- dev_info(dev, "Link: Only Gen1 is enabled\n"); - } - -+ ret = dw_pcie_wait_for_link(pci); -+ if (ret) -+ goto err_reset_phy; -+ - imx6_pcie->link_is_up = true; -- tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); -- dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); -+ - return 0; - - err_reset_phy: -@@ -1458,14 +1457,16 @@ static const struct imx6_pcie_drvdata dr - }, - [IMX8MM] = { - .variant = IMX8MM, -- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, -+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | -+ IMX6_PCIE_FLAG_GEN1_LAST, - .gpr = "fsl,imx8mm-iomuxc-gpr", - .clk_names = imx8mm_clks, - .clks_cnt = ARRAY_SIZE(imx8mm_clks), - }, - [IMX8MP] = { - .variant = IMX8MP, -- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, -+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | -+ IMX6_PCIE_FLAG_GEN1_LAST, - .gpr = "fsl,imx8mp-iomuxc-gpr", - .clk_names = imx8mm_clks, - .clks_cnt = ARRAY_SIZE(imx8mm_clks), diff --git a/target/linux/omap/Makefile b/target/linux/omap/Makefile index ba432ca103..a3086472cd 100644 --- a/target/linux/omap/Makefile +++ b/target/linux/omap/Makefile @@ -12,8 +12,7 @@ CPU_TYPE:=cortex-a8 CPU_SUBTYPE:=vfpv3 SUBTARGETS:=generic -KERNEL_PATCHVER:=6.6 -KERNEL_TESTING_PATCHVER:=6.12 +KERNEL_PATCHVER:=6.12 KERNELNAME:=zImage dtbs diff --git a/target/linux/omap/config-6.6 b/target/linux/omap/config-6.6 deleted file mode 100644 index 43ab179121..0000000000 --- a/target/linux/omap/config-6.6 +++ /dev/null @@ -1,720 +0,0 @@ -# CONFIG_AHCI_DM816 is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_AM335X_CONTROL_USB=y -CONFIG_AM335X_PHY_USB=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_ARCH_OMAP2PLUS_TYPICAL=y -CONFIG_ARCH_OMAP3=y -CONFIG_ARCH_OMAP4=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_ERRATA_430973=y -CONFIG_ARM_ERRATA_720789=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_ARM_ERRATA_775420=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_GROUP_RELOCS=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_OMAP2PLUS_CPUFREQ=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_TI_CPUFREQ=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_AT803X_PHY=y -CONFIG_ATA=y -CONFIG_AUDIT=y -CONFIG_AUDITSYSCALL=y -CONFIG_AUDIT_GENERIC=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_TPS65217 is not set -CONFIG_BCH=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_PM=y -CONFIG_BOUNCE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BUFFER_HEAD=y -CONFIG_CACHE_L2X0=y -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -CONFIG_CEC_CORE=y -# CONFIG_CHARGER_TPS65217 is not set -CONFIG_CLKSRC_MMIO=y -CONFIG_CLKSRC_TI_32K=y -CONFIG_CLK_TWL6040=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=16 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SYSFS is not set -CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_PALMAS is not set -# CONFIG_COMMON_CLK_TI_ADPLL is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONNECTOR=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CONTIG_ALLOC=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MITIGATIONS=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRAMFS=y -CONFIG_CRC16=y -CONFIG_CRC7=y -CONFIG_CRC_CCITT=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC_T10DIF=y -CONFIG_CRYPTO_AES_ARM=y -CONFIG_CRYPTO_AES_ARM_BS=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CHACHA20_NEON=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_OMAP=y -CONFIG_CRYPTO_DEV_OMAP_AES=y -CONFIG_CRYPTO_DEV_OMAP_DES=y -CONFIG_CRYPTO_DEV_OMAP_SHAM=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ENGINE=y -CONFIG_CRYPTO_GENIV=y -CONFIG_CRYPTO_GHASH_ARM_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 -CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 -CONFIG_CRYPTO_JITTERENTROPY_OSR=1 -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_GF128MUL=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set -# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA1_ARM=y -CONFIG_CRYPTO_SHA1_ARM_NEON=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM=y -CONFIG_CRYPTO_SHA3=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SHA512_ARM=y -CONFIG_CRYPTO_SIG2=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CURRENT_POINTER_IN_TPIDRURO=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DDR=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DMADEVICES=y -CONFIG_DMA_CMA=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OMAP=y -CONFIG_DMA_OPS=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DNS_RESOLVER=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_DISPLAY_CONNECTOR=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_OMAP=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_LG_LB035Q02=y -CONFIG_DRM_PANEL_NEC_NL8048HL11=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_PANEL_SHARP_LS037V7DW01=y -CONFIG_DRM_PANEL_SONY_ACX565AKM=y -CONFIG_DRM_PANEL_TPO_TD028TTEC1=y -CONFIG_DRM_PANEL_TPO_TD043MTEA1=y -CONFIG_DRM_SIMPLE_BRIDGE=y -CONFIG_DRM_TI_TFP410=y -CONFIG_DRM_TI_TPD12S015=y -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_93CX6=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_EXTCON_PALMAS=y -CONFIG_EXTCON_USB_GPIO=y -CONFIG_F2FS_FS=y -CONFIG_FANOTIFY=y -CONFIG_FAT_FS=y -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FUNCTION_ALIGNMENT=0 -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_OMAP=y -CONFIG_GPIO_PALMAS=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_PCF857X=y -# CONFIG_GPIO_TPS65218 is not set -CONFIG_GPIO_TPS65910=y -CONFIG_GPIO_TWL4030=y -CONFIG_GPIO_TWL6040=y -CONFIG_GRACE_PERIOD=y -CONFIG_GRO_CELLS=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HDMI=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HSI=y -CONFIG_HSI_BOARDINFO=y -# CONFIG_HSI_CHAR is not set -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_OMAP=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_RARP=y -CONFIG_IRQCHIP=y -CONFIG_IRQSTACKS=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -CONFIG_KCMP=y -CONFIG_KEYS=y -CONFIG_KMAP_LOCAL=y -CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y -CONFIG_KPROBES=y -CONFIG_KRETPROBES=y -CONFIG_KS8851=y -CONFIG_KS8851_MLL=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LEGACY_DIRECT_IO=y -CONFIG_LIBCRC32C=y -CONFIG_LIBFDT=y -CONFIG_LOCKD=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MACH_OMAP_GENERIC=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MDIO_GPIO is not set -CONFIG_MEMORY=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_CORE=y -CONFIG_MFD_PALMAS=y -CONFIG_MFD_SYSCON=y -CONFIG_MFD_TI_AM335X_TSCADC=y -CONFIG_MFD_TPS65217=y -CONFIG_MFD_TPS65218=y -CONFIG_MFD_TPS65910=y -CONFIG_MFD_TWL4030_AUDIO=y -CONFIG_MICREL_PHY=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_EXTERNAL_DMA=y -CONFIG_MMC_SDHCI_OMAP=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMU_LAZY_TLB_REFCOUNT=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MSDOS_FS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_OMAP_BCH=y -CONFIG_MTD_NAND_OMAP_BCH_BUILD=y -CONFIG_MTD_ONENAND=y -# CONFIG_MTD_ONENAND_2X_PROGRAM is not set -# CONFIG_MTD_ONENAND_GENERIC is not set -CONFIG_MTD_ONENAND_OMAP2=y -# CONFIG_MTD_ONENAND_OTP is not set -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -CONFIG_MTD_OOPS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -# CONFIG_MTD_UBI_BLOCK is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SRCU_NMI_SAFE=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_EGRESS=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_HANDSHAKE=y -CONFIG_NET_INGRESS=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_XGRESS=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_FS=y -CONFIG_NFS_USE_KERNEL_DNS=y -# CONFIG_NFS_USE_LEGACY_DNS is not set -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OID_REGISTRY=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OMAP2_DSS_DPI=y -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_HDMI_COMMON=y -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -CONFIG_OMAP2_DSS_SDI=y -CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y -CONFIG_OMAP2_DSS_VENC=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -CONFIG_OMAP3_THERMAL=y -CONFIG_OMAP4_DSS_HDMI=y -CONFIG_OMAP4_DSS_HDMI_CEC=y -CONFIG_OMAP4_THERMAL=y -CONFIG_OMAP5_DSS_HDMI=y -CONFIG_OMAP_CONTROL_PHY=y -CONFIG_OMAP_DM_SYSTIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_OMAP_GPMC=y -# CONFIG_OMAP_GPMC_DEBUG is not set -CONFIG_OMAP_HWMOD=y -CONFIG_OMAP_INTERCONNECT=y -CONFIG_OMAP_INTERCONNECT_BARRIER=y -CONFIG_OMAP_IRQCHIP=y -CONFIG_OMAP_OCP2SCP=y -# CONFIG_OMAP_SSI is not set -CONFIG_OMAP_USB2=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_OPTPROBES=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -# CONFIG_PHY_DM816X_USB is not set -CONFIG_PHY_TI_GMII_SEL=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_PALMAS is not set -CONFIG_PL310_ERRATA_588369=y -CONFIG_PL310_ERRATA_727915=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -CONFIG_POWER_AVS_OMAP=y -CONFIG_POWER_AVS_OMAP_CLASS3=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PRINTK_TIME=y -CONFIG_PROC_EVENTS=y -CONFIG_PROFILING=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -# CONFIG_PWM_OMAP_DMTIMER is not set -CONFIG_PWM_SYSFS=y -CONFIG_PWM_TIECAP=y -CONFIG_PWM_TIEHRPWM=y -# CONFIG_PWM_TWL is not set -# CONFIG_PWM_TWL_LED is not set -CONFIG_QCOM_NET_PHYLIB=y -CONFIG_QFMT_V2=y -CONFIG_QUOTA=y -CONFIG_QUOTACTL=y -CONFIG_QUOTA_TREE=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_IRQ=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_PALMAS=y -CONFIG_REGULATOR_PBIAS=y -CONFIG_REGULATOR_TI_ABB=y -CONFIG_REGULATOR_TPS62360=y -CONFIG_REGULATOR_TPS65023=y -CONFIG_REGULATOR_TPS6507X=y -CONFIG_REGULATOR_TPS65217=y -CONFIG_REGULATOR_TPS65218=y -CONFIG_REGULATOR_TPS65910=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_ROOT_NFS=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_OMAP=y -CONFIG_RTC_DRV_PALMAS=y -# CONFIG_RTC_DRV_TPS65910 is not set -CONFIG_RTC_DRV_TWL4030=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_SATA_HOST=y -CONFIG_SCHEDSTATS=y -CONFIG_SCHED_INFO=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SDIO_UART=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -CONFIG_SENSORS_GPIO_FAN=y -CONFIG_SENSORS_LM75=y -CONFIG_SENSORS_TMP102=y -CONFIG_SENSORS_TSL2550=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_NR_UARTS=32 -# CONFIG_SERIAL_8250_OMAP is not set -CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_OMAP=y -CONFIG_SERIAL_OMAP_CONSOLE=y -CONFIG_SERIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SG_SPLIT=y -CONFIG_SKB_EXTENSIONS=y -CONFIG_SMC91X=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SMSC911X=y -CONFIG_SMSC_PHY=y -CONFIG_SND=y -# CONFIG_SND_COMPRESS_OFFLOAD is not set -CONFIG_SND_DMAENGINE_PCM=y -CONFIG_SND_JACK=y -CONFIG_SND_PCM=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_SIMPLE_CARD=y -CONFIG_SND_SIMPLE_CARD_UTILS=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_DAVINCI_MCASP=y -CONFIG_SND_SOC_DMIC=y -CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_NOKIA_RX51 is not set -# CONFIG_SND_SOC_OMAP3_PANDORA is not set -CONFIG_SND_SOC_OMAP3_TWL4030=y -CONFIG_SND_SOC_OMAP_ABE_TWL6040=y -CONFIG_SND_SOC_OMAP_DMIC=y -CONFIG_SND_SOC_OMAP_HDMI=y -CONFIG_SND_SOC_OMAP_MCBSP=y -CONFIG_SND_SOC_OMAP_MCPDM=y -CONFIG_SND_SOC_TI_EDMA_PCM=y -CONFIG_SND_SOC_TI_SDMA_PCM=y -CONFIG_SND_SOC_TI_UDMA_PCM=y -CONFIG_SND_SOC_TWL4030=y -CONFIG_SND_SOC_TWL6040=y -CONFIG_SND_VERBOSE_PRINTK=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_AM33XX=y -CONFIG_SOC_AM43XX=y -CONFIG_SOC_BUS=y -CONFIG_SOC_HAS_OMAP2_SDRC=y -CONFIG_SOC_OMAP3430=y -# CONFIG_SOC_TI81XX is not set -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_OMAP24XX=y -CONFIG_SPI_TI_QSPI=y -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_STACKTRACE=y -CONFIG_SUNRPC=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TI_CPPI41=y -CONFIG_TI_CPSW=y -CONFIG_TI_CPSW_SWITCHDEV=y -CONFIG_TI_CPTS=y -CONFIG_TI_DAVINCI_EMAC=y -CONFIG_TI_DAVINCI_MDIO=y -CONFIG_TI_DMA_CROSSBAR=y -CONFIG_TI_EDMA=y -CONFIG_TI_EMIF=y -# CONFIG_TI_EMIF_SRAM is not set -CONFIG_TI_PIPE3=y -CONFIG_TI_PWMSS=y -CONFIG_TI_SOC_THERMAL=y -CONFIG_TI_SYSC=y -CONFIG_TI_THERMAL=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_TWL4030_CORE=y -CONFIG_TWL4030_POWER=y -CONFIG_TWL4030_USB=y -CONFIG_TWL4030_WATCHDOG=y -# CONFIG_TWL6030_USB is not set -CONFIG_TWL6040_CORE=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_DUAL_ROLE=y -# CONFIG_USB_DWC3_GADGET is not set -# CONFIG_USB_DWC3_HOST is not set -CONFIG_USB_DWC3_OMAP=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_OMAP=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -CONFIG_USB_GADGET=y -CONFIG_USB_INVENTRA_DMA=y -CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_MUSB_DUAL_ROLE=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OMAP2PLUS=y -CONFIG_USB_MUSB_TUSB6010=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_TI_CPPI41_DMA=y -CONFIG_USB_TUSB_OMAP_DMA=y -CONFIG_USE_OF=y -CONFIG_VFAT_FS=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_VIDEO_CMDLINE=y -CONFIG_VIDEO_NOMODESET=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XFRM_ALGO=y -CONFIG_XFRM_MIGRATE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/omap/patches-6.6/900-use-cpsw-ethernet-driver.patch b/target/linux/omap/patches-6.6/900-use-cpsw-ethernet-driver.patch deleted file mode 100644 index 31fa0028c6..0000000000 --- a/target/linux/omap/patches-6.6/900-use-cpsw-ethernet-driver.patch +++ /dev/null @@ -1,93 +0,0 @@ -From: Jan Hoffmann -Date: Sat, 27 Apr 2024 20:41:43 +0200 -Subject: ARM: dts: Use cpsw ethernet driver for some am335x devices - -The new cpsw-switch driver requires a vid for every port which is -reserved for internal usage (defaulting to 1 and 2). As a result, some -network configurations are impossible, such as a bridge with -default_pvid of 1 (even if it is not vlan aware). - -As a simple workaround, the ti,dual-emac-pvid property could be changed -to another value, but that would just shift the problem. Instead, switch -some devices back to the older cpsw ethernet driver. - -(This patch is not suitable for upstreaming, it just makes the affected -devices in OpenWrt usable again with the default network config.) - -Signed-off-by: Jan Hoffmann ---- - ---- a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi -+++ b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi -@@ -358,27 +358,24 @@ - }; - }; - --&cpsw_port1 { -+&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "mii"; -- ti,dual-emac-pvid = <1>; - }; - --&cpsw_port2 { -- status = "disabled"; --}; -- --&mac_sw { -+&mac { -+ slaves = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; - }; - --&davinci_mdio_sw { -+&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; -+ status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; ---- a/arch/arm/boot/dts/ti/omap/am335x-evm.dts -+++ b/arch/arm/boot/dts/ti/omap/am335x-evm.dts -@@ -682,31 +682,28 @@ - }; - }; - --&mac_sw { -+&mac { -+ slaves = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; - }; - --&davinci_mdio_sw { -+&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; -+ status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; - --&cpsw_port1 { -+&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; -- ti,dual-emac-pvid = <1>; --}; -- --&cpsw_port2 { -- status = "disabled"; - }; - - &tscadc { diff --git a/tools/dwarves/Makefile b/tools/dwarves/Makefile index 56259b260e..b6c08e96c9 100644 --- a/tools/dwarves/Makefile +++ b/tools/dwarves/Makefile @@ -3,12 +3,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=dwarves -PKG_VERSION:=1.29 +PKG_VERSION:=1.31 PKG_RELEASE:=1 -PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=https://fedorapeople.org/~acme/dwarves/ -PKG_HASH:=59c597d4e953c714d6f3ff36aeed2ac30cba85c1d7b94d0c87ca91d611d98a56 +PKG_HASH:=0a7f255ccacf8cc7f8cd119099eb327179b4b3c67cb015af646af6d0cb03054d PKG_MAINTAINER:=Tony Ambardar PKG_LICENSE:=GPL-2.0-only diff --git a/tools/libdeflate/Makefile b/tools/libdeflate/Makefile index ba379dfad8..c7086e615d 100644 --- a/tools/libdeflate/Makefile +++ b/tools/libdeflate/Makefile @@ -7,12 +7,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=libdeflate -PKG_VERSION:=1.24 +PKG_VERSION:=1.25 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://github.com/ebiggers/libdeflate/releases/download/v$(PKG_VERSION) -PKG_HASH:=a0dda1c4b804742066db07b9510876edd09cc0ca06cdc32c5dfe1b2016a26463 +PKG_HASH:=fed5cd22f00f30cc4c2e5329f94e2b8a901df9fa45ee255cb70e2b0b42344477 include $(INCLUDE_DIR)/host-build.mk diff --git a/tools/libressl/Makefile b/tools/libressl/Makefile index f2de5e28be..621fd7c3bd 100644 --- a/tools/libressl/Makefile +++ b/tools/libressl/Makefile @@ -8,8 +8,8 @@ include $(TOPDIR)/rules.mk PKG_NAME:=libressl -PKG_VERSION:=3.7.3 -PKG_HASH:=7948c856a90c825bd7268b6f85674a8dcd254bae42e221781b24e3f8dc335db3 +PKG_VERSION:=4.2.1 +PKG_HASH:=6d5c2f58583588ea791f4c8645004071d00dfa554a5bf788a006ca1eb5abd70b PKG_CPE_ID:=cpe:/a:openbsd:libressl diff --git a/tools/libressl/patches/010-static.patch b/tools/libressl/patches/010-static.patch new file mode 100644 index 0000000000..7cb78e1d5a --- /dev/null +++ b/tools/libressl/patches/010-static.patch @@ -0,0 +1,99 @@ +--- a/crypto/ec/ec_local.h ++++ b/crypto/ec/ec_local.h +@@ -253,9 +253,9 @@ struct ec_key_st { + int eckey_compute_pubkey(EC_KEY *eckey); + int ecdh_compute_key(unsigned char **out, size_t *out_len, + const EC_POINT *pub_key, const EC_KEY *ecdh); +-int ecdsa_verify(int type, const unsigned char *dgst, int dgst_len, ++int libressl_ecdsa_verify(int type, const unsigned char *dgst, int dgst_len, + const unsigned char *sigbuf, int sig_len, EC_KEY *eckey); +-int ecdsa_verify_sig(const unsigned char *dgst, int dgst_len, ++int libressl_ecdsa_verify_sig(const unsigned char *dgst, int dgst_len, + const ECDSA_SIG *sig, EC_KEY *eckey); + + /* +--- a/crypto/ecdsa/ecdsa.c ++++ b/crypto/ecdsa/ecdsa.c +@@ -217,7 +217,7 @@ ecdsa_prepare_digest(const unsigned char + } + + int +-ecdsa_sign(int type, const unsigned char *digest, int digest_len, ++libressl_ecdsa_sign(int type, const unsigned char *digest, int digest_len, + unsigned char *signature, unsigned int *signature_len, const BIGNUM *kinv, + const BIGNUM *r, EC_KEY *key) + { +@@ -266,7 +266,7 @@ LCRYPTO_ALIAS(ECDSA_sign); + */ + + int +-ecdsa_sign_setup(EC_KEY *key, BN_CTX *in_ctx, BIGNUM **out_kinv, BIGNUM **out_r) ++libressl_ecdsa_sign_setup(EC_KEY *key, BN_CTX *in_ctx, BIGNUM **out_kinv, BIGNUM **out_r) + { + const EC_GROUP *group; + EC_POINT *point = NULL; +@@ -517,7 +517,7 @@ ecdsa_compute_s(BIGNUM **out_s, const BI + */ + + ECDSA_SIG * +-ecdsa_sign_sig(const unsigned char *digest, int digest_len, ++libressl_ecdsa_sign_sig(const unsigned char *digest, int digest_len, + const BIGNUM *in_kinv, const BIGNUM *in_r, EC_KEY *key) + { + BN_CTX *ctx = NULL; +@@ -600,7 +600,7 @@ ECDSA_do_sign(const unsigned char *diges + LCRYPTO_ALIAS(ECDSA_do_sign); + + int +-ecdsa_verify(int type, const unsigned char *digest, int digest_len, ++libressl_ecdsa_verify(int type, const unsigned char *digest, int digest_len, + const unsigned char *sigbuf, int sig_len, EC_KEY *key) + { + ECDSA_SIG *s; +@@ -649,7 +649,7 @@ LCRYPTO_ALIAS(ECDSA_verify); + */ + + int +-ecdsa_verify_sig(const unsigned char *digest, int digest_len, ++libressl_ecdsa_verify_sig(const unsigned char *digest, int digest_len, + const ECDSA_SIG *sig, EC_KEY *key) + { + const EC_GROUP *group; +--- a/crypto/ecdsa/ecdsa_local.h ++++ b/crypto/ecdsa/ecdsa_local.h +@@ -68,12 +68,12 @@ struct ECDSA_SIG_st { + BIGNUM *s; + }; + +-int ecdsa_sign_setup(EC_KEY *eckey, BN_CTX *in_ctx, BIGNUM **out_kinv, ++int libressl_ecdsa_sign_setup(EC_KEY *eckey, BN_CTX *in_ctx, BIGNUM **out_kinv, + BIGNUM **out_r); +-int ecdsa_sign(int type, const unsigned char *digest, int digest_len, ++int libressl_ecdsa_sign(int type, const unsigned char *digest, int digest_len, + unsigned char *signature, unsigned int *signature_len, const BIGNUM *kinv, + const BIGNUM *r, EC_KEY *eckey); +-ECDSA_SIG *ecdsa_sign_sig(const unsigned char *digest, int digest_len, ++ECDSA_SIG *libressl_ecdsa_sign_sig(const unsigned char *digest, int digest_len, + const BIGNUM *in_kinv, const BIGNUM *in_r, EC_KEY *eckey); + + __END_HIDDEN_DECLS +--- a/crypto/ec/ec_key.c ++++ b/crypto/ec/ec_key.c +@@ -774,12 +774,12 @@ static const EC_KEY_METHOD openssl_ec_ke + .keygen = ec_key_gen, + .compute_key = ecdh_compute_key, + +- .sign = ecdsa_sign, +- .sign_setup = ecdsa_sign_setup, +- .sign_sig = ecdsa_sign_sig, ++ .sign = libressl_ecdsa_sign, ++ .sign_setup = libressl_ecdsa_sign_setup, ++ .sign_sig = libressl_ecdsa_sign_sig, + +- .verify = ecdsa_verify, +- .verify_sig = ecdsa_verify_sig, ++ .verify = libressl_ecdsa_verify, ++ .verify_sig = libressl_ecdsa_verify_sig, + }; + + const EC_KEY_METHOD * diff --git a/tools/libressl/patches/011-fix-linking.patch b/tools/libressl/patches/011-fix-linking.patch new file mode 100644 index 0000000000..491f0c5e99 --- /dev/null +++ b/tools/libressl/patches/011-fix-linking.patch @@ -0,0 +1,30 @@ +--- a/libcrypto.pc.in ++++ b/libcrypto.pc.in +@@ -23,6 +23,5 @@ includedir=@includedir@ + Name: LibreSSL-libcrypto + Description: LibreSSL cryptography library + Version: @VERSION@ +-Libs: -L${libdir} -lcrypto +-Libs.private: @LIBS@ @PLATFORM_LDADD@ ++Libs: -L${libdir} -lcrypto @LIBS@ @PLATFORM_LDADD@ + Cflags: -I${includedir} +--- a/libssl.pc.in ++++ b/libssl.pc.in +@@ -23,6 +23,6 @@ includedir=@includedir@ + Name: LibreSSL-libssl + Description: Secure Sockets Layer and cryptography libraries + Version: @VERSION@ +-Requires.private: libcrypto ++Requires: libcrypto + Libs: -L${libdir} -lssl + Cflags: -I${includedir} +--- a/libtls.pc.in ++++ b/libtls.pc.in +@@ -23,6 +23,5 @@ includedir=@includedir@ + Name: LibreSSL-libtls + Description: Secure communications using the TLS socket protocol. + Version: @VERSION@ +-Libs: -L${libdir} -ltls +-Libs.private: @LIBS@ @PLATFORM_LDADD@ -lssl -lcrypto ++Libs: -L${libdir} -ltls @LIBS@ @PLATFORM_LDADD@ -lssl -lcrypto + Cflags: -I${includedir} diff --git a/tools/llvm-bpf/Makefile b/tools/llvm-bpf/Makefile index a4e8b2dbaa..b7cd4944e7 100644 --- a/tools/llvm-bpf/Makefile +++ b/tools/llvm-bpf/Makefile @@ -7,11 +7,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=llvm-project -PKG_VERSION:=20.1.8 +PKG_VERSION:=21.1.6 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).src.tar.xz PKG_SOURCE_URL:=https://github.com/llvm/llvm-project/releases/download/llvmorg-$(PKG_VERSION) -PKG_HASH:=6898f963c8e938981e6c4a302e83ec5beb4630147c7311183cf61069af16333d +PKG_HASH:=ae67086eb04bed7ca11ab880349b5f1ab6f50e1b88cda376eaf8a845b935762b PKG_CPE_ID:=cpe:/a:llvm:llvm HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/$(PKG_NAME)-$(PKG_VERSION).src diff --git a/tools/squashfs4/Makefile b/tools/squashfs4/Makefile index d5612e298a..6b887353b6 100644 --- a/tools/squashfs4/Makefile +++ b/tools/squashfs4/Makefile @@ -8,14 +8,14 @@ include $(TOPDIR)/rules.mk PKG_NAME:=squashfs4 PKG_CPE_ID:=cpe:/a:phillip_lougher:squashfs -PKG_VERSION:=4.7.3 +PKG_VERSION:=4.7.4 PKG_RELEASE=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/plougher/squashfs-tools -PKG_SOURCE_DATE:=2025-11-06 -PKG_SOURCE_VERSION:=a143ab5534cc9ad4aededf1116fe37bcb1c8674d -PKG_MIRROR_HASH:=aafdeab814de1081882f858a0997d74e227081bf611fccd84e0d4990f9a51ec4 +PKG_SOURCE_DATE:=2025-11-10 +PKG_SOURCE_VERSION:=53e5a67aac42e0bc9ad4a249156d7d549ce7436c +PKG_MIRROR_HASH:=7ce390d95af4b7b4ce768cec18aeb9ac61b8ca413d0ced2c42a81446d9dd8690 HOST_BUILD_PARALLEL:=1 diff --git a/tools/squashfs4/patches/0001-mksquashfs-fix-build-for-big-endian-architectures.patch b/tools/squashfs4/patches/0001-mksquashfs-fix-build-for-big-endian-architectures.patch deleted file mode 100644 index a8efa7f3b4..0000000000 --- a/tools/squashfs4/patches/0001-mksquashfs-fix-build-for-big-endian-architectures.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 65222d06c0fa76bdbcbcb83831dd2195c19d990a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Daniel=20N=C3=A9ri?= -Date: Fri, 7 Nov 2025 11:58:37 +0100 -Subject: [PATCH 1/2] mksquashfs: fix build for big-endian architectures - ---- - squashfs-tools/mksquashfs.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/squashfs-tools/mksquashfs.c -+++ b/squashfs-tools/mksquashfs.c -@@ -7313,7 +7313,7 @@ static int sqfstar(int argc, char *argv[ - - memset(&sblk, 0, sizeof(struct squashfs_super_block)); - sblk.s_magic = SQUASHFS_MAGIC_STREAMED; -- SQUASHFS_INSWAP_SUPER_BLOCK(sblk); -+ SQUASHFS_INSWAP_SUPER_BLOCK(&sblk); - write_destination(fd, SQUASHFS_START, - sizeof(struct squashfs_super_block), &sblk); - } -@@ -8600,7 +8600,7 @@ int main(int argc, char *argv[]) - - memset(&sblk, 0, sizeof(struct squashfs_super_block)); - sblk.s_magic = SQUASHFS_MAGIC_STREAMED; -- SQUASHFS_INSWAP_SUPER_BLOCK(sblk); -+ SQUASHFS_INSWAP_SUPER_BLOCK(&sblk); - write_destination(fd, SQUASHFS_START, - sizeof(struct squashfs_super_block), &sblk); - } diff --git a/tools/squashfs4/patches/0002-gzip_wrapper-fix-byte-swapping-prototype.patch b/tools/squashfs4/patches/0002-gzip_wrapper-fix-byte-swapping-prototype.patch deleted file mode 100644 index 0651634bea..0000000000 --- a/tools/squashfs4/patches/0002-gzip_wrapper-fix-byte-swapping-prototype.patch +++ /dev/null @@ -1,20 +0,0 @@ -From bc9e11acadd441371e51696f555db031625a9065 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Daniel=20N=C3=A9ri?= -Date: Fri, 7 Nov 2025 11:58:37 +0100 -Subject: [PATCH 2/2] gzip_wrapper: fix byte swapping prototype - ---- - squashfs-tools/gzip_wrapper.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/squashfs-tools/gzip_wrapper.h -+++ b/squashfs-tools/gzip_wrapper.h -@@ -27,7 +27,7 @@ - #include "endian_compat.h" - - #if __BYTE_ORDER == __BIG_ENDIAN --extern unsigned int inswap_le16(unsigned short); -+extern unsigned short inswap_le16(unsigned short); - extern unsigned int inswap_le32(unsigned int); - - #define SQUASHFS_INSWAP_COMP_OPTS(s) { \ diff --git a/tools/squashfs4/patches/0003-mksquashfs-fix-regression-introduced-by-SEEK_DATA-op.patch b/tools/squashfs4/patches/0003-mksquashfs-fix-regression-introduced-by-SEEK_DATA-op.patch deleted file mode 100644 index 4baf0b5f50..0000000000 --- a/tools/squashfs4/patches/0003-mksquashfs-fix-regression-introduced-by-SEEK_DATA-op.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 02e51727923da21bd654ddf0ec8c006f751d86c9 Mon Sep 17 00:00:00 2001 -From: Phillip Lougher -Date: Fri, 7 Nov 2025 23:13:03 +0000 -Subject: [PATCH] mksquashfs: fix regression introduced by SEEK_DATA - optimisation - -The representation of a sparse block was changed from 0 to a negative -number. This was to optimise sparse buffer passing between threads, and -where a single buffer can now represent a multi-block sparse span. - -Unfortunately some code was not correctly updated, and this was not -picked up in testing. - -Fixes: https://github.com/plougher/squashfs-tools/issues/336 - -Signed-off-by: Phillip Lougher ---- - squashfs-tools/mksquashfs.c | 4 ++-- - squashfs-tools/process_fragments.c | 2 +- - 2 files changed, 3 insertions(+), 3 deletions(-) - ---- a/squashfs-tools/mksquashfs.c -+++ b/squashfs-tools/mksquashfs.c -@@ -2889,11 +2889,11 @@ static struct file_info *write_file_proc - sizeof(unsigned int)); - block_list[block ++] = read_buffer->c_byte; - if(!is_sparse(read_buffer)) { -- if(sparse_count(read_buffer) > 1) -- BAD_ERROR("Sparse block too large in write file process\n"); - file_bytes += read_buffer->size; - put_write_buffer_hash(read_buffer); - } else { -+ if(sparse_count(read_buffer) > 1) -+ BAD_ERROR("Sparse block too large in write file process\n"); - sparse += read_buffer->size; - gen_cache_block_put(read_buffer); - } ---- a/squashfs-tools/process_fragments.c -+++ b/squashfs-tools/process_fragments.c -@@ -285,7 +285,7 @@ void *frag_thrd(void *destination_file) - int res; - - if(sparse_files && sparse) { -- file_buffer->c_byte = 0; -+ set_sparse(file_buffer, 1); - file_buffer->fragment = FALSE; - } else - file_buffer->c_byte = file_buffer->size;