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Merge Official Source

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2023-09-20 10:41:08 +08:00
commit c7cf30e208
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GPG Key ID: 6850B6345C862176
77 changed files with 4094 additions and 55 deletions
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54
package/boot/uboot-mvebu/patches/0001-arm-mvebu-Espressobin-move-FDT-fixup-into-a-separate.patch Normal file
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@ -0,0 +1,54 @@
From 8621f6d22a9589651c6f25742294dd19a26db430 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Thu, 3 Aug 2023 13:34:13 +0200
Subject: [PATCH 1/3] arm: mvebu: Espressobin: move FDT fixup into a separate
function
Currently, Esspresobin FDT is being fixed up directly in ft_board_setup()
which makes it hard to add support for any other board to be fixed up.
So, lets just move the FDT fixup code to a separate function and call it
if compatible matches, there should be no functional change.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
board/Marvell/mvebu_armada-37xx/board.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -359,18 +359,14 @@ int last_stage_init(void)
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
+static int espressobin_fdt_setup(void *blob)
{
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
int ret;
int spi_off;
int parts_off;
int part_off;
/* Fill SPI MTD partitions for Linux kernel on Espressobin */
- if (!of_machine_is_compatible("globalscale,espressobin"))
- return 0;
-
spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
if (spi_off < 0)
return 0;
@@ -455,6 +451,14 @@ int ft_board_setup(void *blob, struct bd
return 0;
}
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+ if (of_machine_is_compatible("globalscale,espressobin"))
+ return espressobin_fdt_setup(blob);
#endif
return 0;
}

53
package/boot/uboot-mvebu/patches/0002-arm-mvebu-Espressobin-move-network-setup-into-a-sepa.patch Normal file
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@ -0,0 +1,53 @@
From 3f8c18894a50fd45b81a807f217893f289500bc6 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Thu, 3 Aug 2023 14:24:31 +0200
Subject: [PATCH 2/3] arm: mvebu: Espressobin: move network setup into a
separate function
Currently, Esspresobin switch is being setup directly in last_stage_init()
which makes it hard to add support for any other board to be setup.
So, lets just move the switch setup code to a separate function and call it
if compatible matches, there should be no functional change.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
board/Marvell/mvebu_armada-37xx/board.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -300,15 +300,11 @@ static int mii_multi_chip_mode_write(str
return 0;
}
-/* Bring-up board-specific network stuff */
-int last_stage_init(void)
+static int espressobin_last_stage_init(void)
{
struct udevice *bus;
ofnode node;
- if (!of_machine_is_compatible("globalscale,espressobin"))
- return 0;
-
node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
if (!ofnode_valid(node) ||
uclass_get_device_by_ofnode(UCLASS_MDIO, node, &bus) ||
@@ -356,6 +352,16 @@ int last_stage_init(void)
return 0;
}
+
+/* Bring-up board-specific network stuff */
+int last_stage_init(void)
+{
+
+ if (of_machine_is_compatible("globalscale,espressobin"))
+ return espressobin_last_stage_init();
+
+ return 0;
+}
#endif
#ifdef CONFIG_OF_BOARD_SETUP

297
package/boot/uboot-mvebu/patches/0003-arm-mvebu-eDPU-support-new-board-revision.patch Normal file
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@ -0,0 +1,297 @@
From 83c00ee665b8dde813458b2b07cf97ce8409248d Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Fri, 4 Aug 2023 22:39:06 +0200
Subject: [PATCH 3/3] arm: mvebu: eDPU: support new board revision
There is a new eDPU revision that uses Marvell 88E6361 switch onboard.
We can rely on detecting the switch to enable and fixup the Linux DTS
so a single DTS can be used.
There is currently no support for the 88E6361 switch and thus no working
networking in U-Boot, so we disable both ports.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
arch/arm/dts/armada-3720-eDPU-u-boot.dtsi | 13 ++-
arch/arm/dts/armada-3720-eDPU.dts | 47 ++++++++
board/Marvell/mvebu_armada-37xx/board.c | 125 ++++++++++++++++++++++
configs/eDPU_defconfig | 2 +
4 files changed, 182 insertions(+), 5 deletions(-)
--- a/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
+++ b/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
@@ -32,14 +32,17 @@
bootph-all;
};
-&eth0 {
- /* G.hn does not work without additional configuration */
- status = "disabled";
-};
-
&eth1 {
fixed-link {
speed = <1000>;
full-duplex;
};
};
+
+/*
+ * eDPU v2 has a MV88E6361 switch on the MDIO bus and U-boot is used
+ * to patch the Linux DTS if its found so enable MDIO by default.
+ */
+&mdio {
+ status = "okay";
+};
--- a/arch/arm/dts/armada-3720-eDPU.dts
+++ b/arch/arm/dts/armada-3720-eDPU.dts
@@ -12,3 +12,50 @@
&eth0 {
phy-mode = "2500base-x";
};
+
+/*
+ * External MV88E6361 switch is only available on v2 of the board.
+ * U-Boot will enable the MDIO bus and switch nodes.
+ */
+&mdio {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&smi_pins>;
+
+ /* Actual device is MV88E6361 */
+ switch: switch@0 {
+ compatible = "marvell,mv88e6190";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "cpu";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ ethernet = <&eth0>;
+ };
+
+ port@9 {
+ reg = <9>;
+ label = "downlink";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ };
+
+ port@a {
+ reg = <10>;
+ label = "uplink";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ sfp = <&sfp_eth1>;
+ };
+ };
+ };
+};
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -13,6 +13,7 @@
#include <mmc.h>
#include <miiphy.h>
#include <phy.h>
+#include <fdt_support.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
@@ -49,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Single-chip mode */
/* Switch Port Registers */
#define MVEBU_SW_LINK_CTRL_REG (1)
+#define MVEBU_SW_PORT_SWITCH_ID (3)
#define MVEBU_SW_PORT_CTRL_REG (4)
#define MVEBU_SW_PORT_BASE_VLAN (6)
@@ -56,6 +58,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define MVEBU_G2_SMI_PHY_CMD_REG (24)
#define MVEBU_G2_SMI_PHY_DATA_REG (25)
+#define SWITCH_88E6361_PRODUCT_NUMBER 0x2610
+
/*
* Memory Controller Registers
*
@@ -72,6 +76,27 @@ DECLARE_GLOBAL_DATA_PTR;
#define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
#define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
+static bool is_edpu_plus(void)
+{
+ struct udevice *bus;
+ ofnode node;
+ int val;
+
+ node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
+ if (!ofnode_valid(node) ||
+ uclass_get_device_by_ofnode(UCLASS_MDIO, node, &bus) ||
+ device_probe(bus)) {
+ printf("Cannot find MDIO bus\n");
+ return -ENODEV;
+ }
+
+ val = dm_mdio_read(bus, 0x0, MDIO_DEVAD_NONE, MVEBU_SW_PORT_SWITCH_ID);
+ if (val == SWITCH_88E6361_PRODUCT_NUMBER)
+ return true;
+ else
+ return false;
+}
+
int board_early_init_f(void)
{
return 0;
@@ -353,6 +378,41 @@ static int espressobin_last_stage_init(v
return 0;
}
+static int edpu_plus_last_stage_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (is_edpu_plus()) {
+ ret = uclass_get_device_by_name(UCLASS_ETH,
+ "ethernet@40000",
+ &dev);
+ if (!ret) {
+ device_remove(dev, DM_REMOVE_NORMAL);
+ device_unbind(dev);
+ }
+
+ /* Currently no networking support on the eDPU+ board */
+ ret = uclass_get_device_by_name(UCLASS_ETH,
+ "ethernet@30000",
+ &dev);
+ if (!ret) {
+ device_remove(dev, DM_REMOVE_NORMAL);
+ device_unbind(dev);
+ }
+ } else {
+ ret = uclass_get_device_by_name(UCLASS_ETH,
+ "ethernet@30000",
+ &dev);
+ if (!ret) {
+ device_remove(dev, DM_REMOVE_NORMAL);
+ device_unbind(dev);
+ }
+ }
+
+ return 0;
+}
+
/* Bring-up board-specific network stuff */
int last_stage_init(void)
{
@@ -360,6 +420,9 @@ int last_stage_init(void)
if (of_machine_is_compatible("globalscale,espressobin"))
return espressobin_last_stage_init();
+ if (of_machine_is_compatible("methode,edpu"))
+ return edpu_plus_last_stage_init();
+
return 0;
}
#endif
@@ -460,12 +523,74 @@ static int espressobin_fdt_setup(void *b
return 0;
}
+static int edpu_plus_fdt_setup(void *blob)
+{
+ const char *ports[] = { "downlink", "uplink" };
+ uint8_t mac[ETH_ALEN];
+ const char *path;
+ int i, ret;
+
+ if (is_edpu_plus()) {
+ ret = fdt_set_status_by_compatible(blob,
+ "marvell,orion-mdio",
+ FDT_STATUS_OKAY);
+ if (ret)
+ printf("Failed to enable MDIO!\n");
+
+ ret = fdt_set_status_by_alias(blob,
+ "ethernet1",
+ FDT_STATUS_DISABLED);
+ if (ret)
+ printf("Failed to disable ethernet1!\n");
+
+ path = fdt_get_alias(blob, "ethernet0");
+ if (path)
+ do_fixup_by_path_string(blob, path, "phy-mode", "2500base-x");
+ else
+ printf("Failed to update ethernet0 phy-mode to 2500base-x!\n");
+
+ ret = fdt_set_status_by_compatible(blob,
+ "marvell,mv88e6190",
+ FDT_STATUS_OKAY);
+ if (ret)
+ printf("Failed to enable MV88E6361!\n");
+
+ /*
+ * MAC-s for Uplink and Downlink ports are stored under
+ * non standard variable names, so lets manually fixup the
+ * switch port nodes to have the desired MAC-s.
+ */
+ for (i = 0; i < 2; i++) {
+ if (eth_env_get_enetaddr(ports[i], mac)) {
+ do_fixup_by_prop(blob,
+ "label",
+ ports[i],
+ strlen(ports[i]) + 1,
+ "mac-address",
+ mac, ARP_HLEN, 1);
+
+ do_fixup_by_prop(blob,
+ "label",
+ ports[i],
+ strlen(ports[i]) + 1,
+ "local-mac-address",
+ mac, ARP_HLEN, 1);
+ }
+ }
+ }
+
+ return 0;
+}
+
int ft_board_setup(void *blob, struct bd_info *bd)
{
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
if (of_machine_is_compatible("globalscale,espressobin"))
return espressobin_fdt_setup(blob);
#endif
+ if (of_machine_is_compatible("methode,edpu"))
+ return edpu_plus_fdt_setup(blob);
+
return 0;
}
#endif
--- a/configs/eDPU_defconfig
+++ b/configs/eDPU_defconfig
@@ -17,12 +17,14 @@ CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=1048
# CONFIG_CMD_ELF is not set

1
package/firmware/intel-microcode/Makefile
View File

@ -15,6 +15,7 @@ PKG_SOURCE:=intel-microcode_3.$(PKG_VERSION).1.tar.xz
PKG_SOURCE_URL:=@DEBIAN/pool/non-free-firmware/i/intel-microcode/
PKG_HASH:=29e77c275b3f60a691832c0844f70effbd94a4594d04af21e0c2e6e0c1ac1894
PKG_BUILD_DIR:=$(BUILD_DIR)/intel-microcode-3.$(PKG_VERSION).1
PKG_CPE_ID:=cpe:/a:intel:microcode
PKG_BUILD_DEPENDS:=iucode-tool/host

2
package/firmware/ipq-wifi/Makefile
View File

@ -44,6 +44,7 @@ ALLWIFIBOARDS:= \
yyets_le1 \
zte_mf269 \
zte_mf289f \
zte_mf287 \
zte_mf287plus \
zyxel_nbg7815
@ -135,6 +136,7 @@ $(eval $(call generate-ipq-wifi-package,xiaomi_ax9000,Xiaomi AX9000))
$(eval $(call generate-ipq-wifi-package,yyets_le1,YYeTs LE1))
$(eval $(call generate-ipq-wifi-package,zte_mf269,ZTE MF269))
$(eval $(call generate-ipq-wifi-package,zte_mf289f,ZTE MF289F))
$(eval $(call generate-ipq-wifi-package,zte_mf287,ZTE MF287))
$(eval $(call generate-ipq-wifi-package,zte_mf287plus,ZTE MF287Plus))
$(eval $(call generate-ipq-wifi-package,zyxel_nbg7815,Zyxel NBG7815))

6
package/kernel/linux/modules/hwmon.mk
View File

@ -417,9 +417,11 @@ $(eval $(call KernelPackage,hwmon-mcp3021))
define KernelPackage/hwmon-nct6775
TITLE:=NCT6106D/6775F/6776F/6779D/6791D/6792D/6793D and compatibles monitoring support
KCONFIG:=CONFIG_SENSORS_NCT6775
FILES:=$(LINUX_DIR)/drivers/hwmon/nct6775.ko
FILES:= \
$(LINUX_DIR)/drivers/hwmon/nct6775.ko \
$(LINUX_DIR)/drivers/hwmon/nct6775-core.ko@ge5.19
AUTOLOAD:=$(call AutoProbe,nct6775)
$(call AddDepends/hwmon,@PCI_SUPPORT @TARGET_x86 +kmod-hwmon-vid)
$(call AddDepends/hwmon,@PCI_SUPPORT @TARGET_x86 +kmod-hwmon-vid +LINUX_6_1:kmod-regmap-core)
endef
define KernelPackage/hwmon-nct6775/description

3
package/kernel/linux/modules/netdevices.mk
View File

@ -1383,7 +1383,8 @@ define KernelPackage/mlx5-core
CONFIG_MLX5_SW_STEERING=n \
CONFIG_MLX5_CLS_ACT=n \
CONFIG_MLX5_TC_CT=n \
CONFIG_MLX5_TLS=n
CONFIG_MLX5_TLS=n \
CONFIG_MLX5_VFIO_PCI=n
AUTOLOAD:=$(call AutoProbe,mlx5_core)
endef

34
package/kernel/linux/modules/video.mk
View File

@ -16,6 +16,24 @@ V4L2_MEM2MEM_DIR=platform
# Video Display
#
define KernelPackage/acpi-video
SUBMENU:=$(VIDEO_MENU)
TITLE:=ACPI Extensions For Display Adapters
DEPENDS:=@TARGET_x86 +kmod-backlight
HIDDEN:=1
KCONFIG:=CONFIG_ACPI_VIDEO \
CONFIG_ACPI_WMI
FILES:=$(LINUX_DIR)/drivers/acpi/video.ko \
$(LINUX_DIR)/drivers/platform/x86/wmi.ko
AUTOLOAD:=$(call AutoProbe,wmi video)
endef
define KernelPackage/acpi-video/description
Kernel support for integrated graphics devices.
endef
$(eval $(call KernelPackage,acpi-video))
define KernelPackage/backlight
SUBMENU:=$(VIDEO_MENU)
TITLE:=Backlight support
@ -264,19 +282,22 @@ $(eval $(call KernelPackage,drm))
define KernelPackage/drm-buddy
SUBMENU:=$(VIDEO_MENU)
TITLE:=A page based buddy allocator
DEPENDS:=@TARGET_x86 @DISPLAY_SUPPORT +kmod-drm @!LINUX_5_15
DEPENDS:=@DISPLAY_SUPPORT +kmod-drm @LINUX_6_1
KCONFIG:=CONFIG_DRM_BUDDY
FILES:= $(LINUX_DIR)/drivers/gpu/drm/drm_buddy.ko
AUTOLOAD:=$(call AutoProbe,drm_buddy)
endef
$(eval $(call KernelPackage,drm-buddy))
define KernelPackage/drm-buddy/description
A page based buddy allocator
endef
$(eval $(call KernelPackage,drm-buddy))
define KernelPackage/drm-display-helper
SUBMENU:=$(VIDEO_MENU)
TITLE:=DRM helpers for display adapters drivers
DEPENDS:=@DISPLAY_SUPPORT +kmod-drm +TARGET_x86:kmod-drm-buddy @!LINUX_5_15
DEPENDS:=@DISPLAY_SUPPORT +kmod-drm-kms-helper @LINUX_6_1
KCONFIG:=CONFIG_DRM_DISPLAY_HELPER
FILES:=$(LINUX_DIR)/drivers/gpu/drm/display/drm_display_helper.ko
AUTOLOAD:=$(call AutoProbe,drm_display_helper)
@ -353,7 +374,9 @@ define KernelPackage/drm-amdgpu
SUBMENU:=$(VIDEO_MENU)
TITLE:=AMDGPU DRM support
DEPENDS:=@TARGET_x86 @DISPLAY_SUPPORT +kmod-backlight +kmod-drm-ttm \
+kmod-drm-ttm-helper +kmod-drm-kms-helper +kmod-i2c-algo-bit +amdgpu-firmware
+kmod-drm-ttm-helper +kmod-drm-kms-helper +kmod-i2c-algo-bit +amdgpu-firmware \
+LINUX_6_1:kmod-drm-display-helper +LINUX_6_1:kmod-drm-buddy \
+LINUX_6_1:kmod-acpi-video
KCONFIG:=CONFIG_DRM_AMDGPU \
CONFIG_DRM_AMDGPU_SI=y \
CONFIG_DRM_AMDGPU_CIK=y \
@ -490,7 +513,8 @@ define KernelPackage/drm-radeon
SUBMENU:=$(VIDEO_MENU)
TITLE:=Radeon DRM support
DEPENDS:=@TARGET_x86 @DISPLAY_SUPPORT +kmod-backlight +kmod-drm-kms-helper \
+kmod-drm-ttm +kmod-drm-ttm-helper +kmod-i2c-algo-bit +radeon-firmware
+kmod-drm-ttm +kmod-drm-ttm-helper +kmod-i2c-algo-bit +radeon-firmware \
+LINUX_6_1:kmod-drm-display-helper +LINUX_6_1:kmod-acpi-video
KCONFIG:=CONFIG_DRM_RADEON
FILES:=$(LINUX_DIR)/drivers/gpu/drm/radeon/radeon.ko
AUTOLOAD:=$(call AutoProbe,radeon)

1
package/libs/gmp/Makefile
View File

@ -19,6 +19,7 @@ PKG_BUILD_PARALLEL:=1
PKG_INSTALL:=1
PKG_FIXUP:=autoreconf
PKG_LICENSE:=GPL-2.0-or-later
PKG_CPE_ID:=cpe:/a:gmplib:gmp
PKG_BUILD_FLAGS:=no-mips16

1
package/libs/libbpf/Makefile
View File

@ -18,6 +18,7 @@ PKG_SOURCE_VERSION:=1728e3e4bef0e138ea95ffe62163eb9a6ac6fa32
PKG_ABI_VERSION:=$(firstword $(subst .,$(space),$(PKG_VERSION)))
PKG_MAINTAINER:=Tony Ambardar <itugrok@yahoo.com>
PKG_CPE_ID:=cpe:/a:libbpf_project:libbpf
PKG_BUILD_FLAGS:=no-mips16
PKG_BUILD_PARALLEL:=1

1
package/libs/libbsd/Makefile
View File

@ -10,6 +10,7 @@ PKG_HASH:=9baa186059ebbf25c06308e9f991fda31f7183c0f24931826d83aa6abd8a0261
PKG_LICENSE:=BSD-4-Clause
PKG_LICENSE_FILES:=COPYING
PKG_CPE_ID:=cpe:/a:freedesktop:libbsd
PKG_INSTALL:=1
PKG_BUILD_PARALLEL:=1

1
package/libs/libnetfilter-conntrack/Makefile
View File

@ -18,6 +18,7 @@ PKG_HASH:=67bd9df49fe34e8b82144f6dfb93b320f384a8ea59727e92ff8d18b5f4b579a8
PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
PKG_LICENSE:=GPL-2.0-or-later
PKG_LICENSE_FILES:=COPYING
PKG_CPE_ID:=cpe:/a:netfilter:libnetfilter_conntrack
PKG_INSTALL:=1
PKG_BUILD_PARALLEL:=1

1
package/libs/libpcap/Makefile
View File

@ -18,6 +18,7 @@ PKG_HASH:=ed19a0383fad72e3ad435fd239d7cd80d64916b87269550159d20e47160ebe5f
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_LICENSE:=BSD-3-Clause
PKG_LICENSE_FILES:=LICENSE
PKG_CPE_ID:=cpe:/a:tcpdump:libpcap
PKG_ASLR_PIE_REGULAR:=1

8
package/network/config/netifd/Makefile
View File

@ -1,13 +1,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=netifd
PKG_RELEASE:=3
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/netifd.git
PKG_SOURCE_DATE:=2023-09-15.1
PKG_SOURCE_VERSION:=afcd3825dad9b6a6712fbf6ed8e4434819a34009
PKG_MIRROR_HASH:=d389db5dec7140fc12f69e8d679b9242c72d27b35c789b12adc6ebdf16913a85
PKG_SOURCE_DATE:=2023-09-19
PKG_SOURCE_VERSION:=7a58b995fdbecd9beed57e4d66d42cb3cf66aee2
PKG_MIRROR_HASH:=a460a3b912047f8802eb24bb737084a08dad65b2dd520e5f5e7459379d1fcf8c
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_LICENSE:=GPL-2.0

16
package/network/services/hostapd/files/hostapd.uc
View File

@ -26,7 +26,6 @@ function iface_remove(cfg)
if (!cfg || !cfg.bss || !cfg.bss[0] || !cfg.bss[0].ifname)
return;
hostapd.remove_iface(cfg.bss[0].ifname);
for (let bss in cfg.bss)
wdev_remove(bss.ifname);
}
@ -95,14 +94,14 @@ function iface_add(phy, config, phy_status)
let config_inline = iface_gen_config(phy, config, !!phy_status);
let bss = config.bss[0];
let ret = hostapd.add_iface(`bss_config=${bss.ifname}:${config_inline}`);
let ret = hostapd.add_iface(`bss_config=${phy}:${config_inline}`);
if (ret < 0)
return false;
if (!phy_status)
return true;
let iface = hostapd.interfaces[bss.ifname];
let iface = hostapd.interfaces[phy];
if (!iface)
return false;
@ -127,6 +126,7 @@ function iface_restart(phydev, config, old_config)
{
let phy = phydev.name;
hostapd.remove_iface(phy);
iface_remove(old_config);
iface_remove(config);
@ -267,13 +267,13 @@ function iface_reload_config(phydev, config, old_config)
if (!old_config.bss || !old_config.bss[0])
return false;
let iface_name = old_config.bss[0].ifname;
let iface = hostapd.interfaces[iface_name];
let iface = hostapd.interfaces[phy];
if (!iface) {
hostapd.printf(`Could not find previous interface ${iface_name}`);
return false;
}
let iface_name = old_config.bss[0].ifname;
let first_bss = hostapd.bss[iface_name];
if (!first_bss) {
hostapd.printf(`Could not find bss of previous interface ${iface_name}`);
@ -512,8 +512,10 @@ function iface_set_config(phy, config)
hostapd.data.config[phy] = config;
if (!config)
if (!config) {
hostapd.remove_iface(phy);
return iface_remove(old_config);
}
let phydev = phy_open(phy);
if (!phydev) {
@ -667,7 +669,7 @@ let main_obj = {
if (!config || !config.bss || !config.bss[0] || !config.bss[0].ifname)
return 0;
let iface = hostapd.interfaces[config.bss[0].ifname];
let iface = hostapd.interfaces[phy];
if (!iface)
return 0;

10
package/network/services/hostapd/patches/601-ucode_support.patch
View File

@ -142,6 +142,16 @@
{
if (!hapd)
return;
@@ -3491,7 +3495,8 @@ int hostapd_remove_iface(struct hapd_int
hapd_iface = interfaces->iface[i];
if (hapd_iface == NULL)
return -1;
- if (!os_strcmp(hapd_iface->conf->bss[0]->iface, buf)) {
+ if (!os_strcmp(hapd_iface->phy, buf) ||
+ !os_strcmp(hapd_iface->conf->bss[0]->iface, buf)) {
wpa_printf(MSG_INFO, "Remove interface '%s'", buf);
hapd_iface->driver_ap_teardown =
!!(hapd_iface->drv_flags &
--- a/wpa_supplicant/Makefile
+++ b/wpa_supplicant/Makefile
@@ -195,8 +195,20 @@ endif

4
package/network/services/hostapd/patches/991-Fix-OpenWrt-13156.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
--- a/src/ap/hostapd.c
+++ b/src/ap/hostapd.c
@@ -3563,6 +3563,8 @@ int hostapd_remove_iface(struct hapd_int
@@ -3564,6 +3564,8 @@ int hostapd_remove_iface(struct hapd_int
void hostapd_new_assoc_sta(struct hostapd_data *hapd, struct sta_info *sta,
int reassoc)
{
@ -29,7 +29,7 @@ Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
if (hapd->tkip_countermeasures) {
hostapd_drv_sta_deauth(hapd, sta->addr,
WLAN_REASON_MICHAEL_MIC_FAILURE);
@@ -3570,10 +3572,16 @@ void hostapd_new_assoc_sta(struct hostap
@@ -3571,10 +3573,16 @@ void hostapd_new_assoc_sta(struct hostap
}
#ifdef CONFIG_IEEE80211BE

1
package/network/utils/ebtables/Makefile
View File

@ -17,6 +17,7 @@ PKG_SOURCE_VERSION:=48cff25dfea5b37e16ba5dc6601e98ab140f5f99
PKG_MIRROR_HASH:=1327cdc3402e5e3056819e4e9b6f9d4a5bfd401f2c4f58447afb2c3c73fc8aac
PKG_LICENSE:=GPL-2.0
PKG_CPE_ID:=cpe:/a:netfilter:ebtables
include $(INCLUDE_DIR)/package.mk

1
package/network/utils/ipset/Makefile
View File

@ -18,6 +18,7 @@ PKG_HASH:=be49c9ff489dd6610cad6541e743c3384eac96e9f24707da7b3929d8f2ac64d8
PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
PKG_LICENSE:=GPL-2.0
PKG_CPE_ID:=cpe:/a:netfilter:ipset
PKG_FIXUP:=autoreconf
PKG_INSTALL:=1

1
package/network/utils/iw/Makefile
View File

@ -17,6 +17,7 @@ PKG_HASH:=f167bbe947dd53bb9ebc0c1dcef5db6ad73ac1d6084f2c6f9376c5c360cc4d4e
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_LICENSE:=GPL-2.0
PKG_CPE_ID:=cpe:/a:kernel:iw
PKG_BUILD_FLAGS:=gc-sections lto

1
package/utils/adb/Makefile
View File

@ -13,6 +13,7 @@ PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_SOURCE_VERSION)
PKG_SOURCE:=$(PKG_SOURCE_SUBDIR).tar.xz
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_SOURCE_SUBDIR)
PKG_MAINTAINER:=Henryk Heisig <hyniu@o2.pl>
PKG_CPE_ID:=cpe:/a:google:android_debug_bridge
include $(INCLUDE_DIR)/package.mk

1
package/utils/bsdiff/Makefile
View File

@ -18,6 +18,7 @@ PKG_MAINTAINER:=Hauke Mehrtens <hauke@hauke-m.de>
HOST_BUILD_DEPENDS:=bzip2/host
PKG_LICENSE:=BSD-2-Clause
PKG_CPE_ID:=cpe:/a:daemonology:bsdiff
include $(INCLUDE_DIR)/host-build.mk
include $(INCLUDE_DIR)/package.mk

1
package/utils/dtc/Makefile
View File

@ -15,6 +15,7 @@ PKG_SOURCE_URL:=@KERNEL/software/utils/dtc
PKG_MAINTAINER:=Yousong Zhou <yszhou4tech@gmail.com>
PKG_LICENSE:=GPL-2.0-only
PKG_LICENSE_FILES:=GPL
PKG_CPE_ID:=cpe:/a:dtc_project:dtc
PKG_INSTALL:=1

1
package/utils/lua/Makefile
View File

@ -19,6 +19,7 @@ PKG_BUILD_PARALLEL:=1
PKG_LICENSE:=MIT
PKG_LICENSE_FILES:=COPYRIGHT
PKG_CPE_ID:=cpe:/a:lua:lua
HOST_PATCH_DIR := ./patches-host

1
package/utils/lua5.3/Makefile
View File

@ -19,6 +19,7 @@ PKG_BUILD_PARALLEL:=1
PKG_LICENSE:=MIT
PKG_LICENSE_FILES:=COPYRIGHT
PKG_CPE_ID:=cpe:/a:lua:lua
HOST_PATCH_DIR := ./patches-host

46
target/linux/generic/backport-5.15/893-v6.5-01-net-dsa-mv88e6xxx-pass-directly-chip-structure-to-mv.patch Normal file
View File

@ -0,0 +1,46 @@
From 19f291d8a65cd19e7595006c7872cd95aa6f9e93 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
Date: Fri, 4 Aug 2023 19:13:10 +0200
Subject: [PATCH 893/898] net: dsa: mv88e6xxx: pass directly chip structure to
mv88e6xxx_phy_is_internal
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Since this function is a simple helper, we do not need to pass a full
dsa_switch structure, we can directly pass the mv88e6xxx_chip structure.
Doing so will allow to share this function with any other function
not manipulating dsa_switch structure but needing info about number of
internal phys
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/dsa/mv88e6xxx/chip.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -459,10 +459,8 @@ restore_link:
return err;
}
-static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
+static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
{
- struct mv88e6xxx_chip *chip = ds->priv;
-
return port < chip->info->num_internal_phys;
}
@@ -704,7 +702,7 @@ static void mv88e6xxx_mac_config(struct
mv88e6xxx_reg_lock(chip);
- if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) {
+ if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
/* In inband mode, the link may come up at any time while the
* link is not forced down. Force the link down while we
* reconfigure the interface mode.

31
target/linux/generic/backport-5.15/893-v6.5-02-net-dsa-mv88e6xxx-use-mv88e6xxx_phy_is_internal-in-m.patch Normal file
View File

@ -0,0 +1,31 @@
From 03a50b4f81d9e8bcf86165d6b2ac9376d02e5df9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
Date: Mon, 29 May 2023 10:02:42 +0200
Subject: [PATCH 894/898] net: dsa: mv88e6xxx: use mv88e6xxx_phy_is_internal in
mv88e6xxx_port_ppu_updates
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Make sure to use existing helper to get internal PHYs count instead of
redoing it manually
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/dsa/mv88e6xxx/chip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -473,7 +473,7 @@ static int mv88e6xxx_port_ppu_updates(st
* report whether the port is internal.
*/
if (chip->info->family == MV88E6XXX_FAMILY_6250)
- return port < chip->info->num_internal_phys;
+ return mv88e6xxx_phy_is_internal(chip, port);
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
if (err) {

69
target/linux/generic/backport-5.15/893-v6.5-03-net-dsa-mv88e6xxx-add-field-to-specify-internal-phys.patch Normal file
View File

@ -0,0 +1,69 @@
From 07120894b24cc3cf2318925baeaaf0893e3312e4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
Date: Mon, 29 May 2023 10:02:43 +0200
Subject: [PATCH 895/898] net: dsa: mv88e6xxx: add field to specify internal
phys layout
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
mv88e6xxx currently assumes that switch equipped with internal phys have
those phys mapped contiguously starting from port 0 (see
mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but
NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have
integrated PHYs available on ports 1 to 8
To properly support this offset, add a new field to allow specifying an
internal PHYs layout. If field is not set, default layout is assumed (start
at port 0)
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/dsa/mv88e6xxx/chip.c | 4 +++-
drivers/net/dsa/mv88e6xxx/chip.h | 5 +++++
drivers/net/dsa/mv88e6xxx/global2.c | 5 ++++-
3 files changed, 12 insertions(+), 2 deletions(-)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -461,7 +461,9 @@ restore_link:
static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
{
- return port < chip->info->num_internal_phys;
+ return port >= chip->info->internal_phys_offset &&
+ port < chip->info->num_internal_phys +
+ chip->info->internal_phys_offset;
}
static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -165,6 +165,11 @@ struct mv88e6xxx_info {
/* Supports PTP */
bool ptp_support;
+
+ /* Internal PHY start index. 0 means that internal PHYs range starts at
+ * port 0, 1 means internal PHYs range starts at port 1, etc
+ */
+ unsigned int internal_phys_offset;
};
struct mv88e6xxx_atu_entry {
--- a/drivers/net/dsa/mv88e6xxx/global2.c
+++ b/drivers/net/dsa/mv88e6xxx/global2.c
@@ -1185,8 +1185,11 @@ int mv88e6xxx_g2_irq_mdio_setup(struct m
struct mii_bus *bus)
{
int phy, irq, err, err_phy;
+ int phy_start = chip->info->internal_phys_offset;
+ int phy_end = chip->info->internal_phys_offset +
+ chip->info->num_internal_phys;
- for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
+ for (phy = phy_start; phy < phy_end; phy++) {
irq = irq_find_mapping(chip->g2_irq.domain, phy);
if (irq < 0) {
err = irq;

52
target/linux/generic/backport-5.15/893-v6.5-04-net-dsa-mv88e6xxx-fix-88E6393X-family-internal-phys-.patch Normal file
View File

@ -0,0 +1,52 @@
From 492b06747f544c19b5ffe531a24b67858764c50e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
Date: Mon, 29 May 2023 10:02:44 +0200
Subject: [PATCH 896/898] net: dsa: mv88e6xxx: fix 88E6393X family internal
phys layout
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
88E6393X/88E6193X/88E6191X switches have in fact 8 internal PHYs, but those
are not present starting at port 0: supported ports go from 1 to 8
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/dsa/mv88e6xxx/chip.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -5370,7 +5370,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6191X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
- .num_internal_phys = 9,
+ .num_internal_phys = 8,
+ .internal_phys_offset = 1,
.max_vid = 8191,
.port_base_addr = 0x0,
.phy_base_addr = 0x0,
@@ -5392,7 +5393,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6193X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
- .num_internal_phys = 9,
+ .num_internal_phys = 8,
+ .internal_phys_offset = 1,
.max_vid = 8191,
.port_base_addr = 0x0,
.phy_base_addr = 0x0,
@@ -5702,7 +5704,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6393X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
- .num_internal_phys = 9,
+ .num_internal_phys = 8,
+ .internal_phys_offset = 1,
.max_vid = 8191,
.port_base_addr = 0x0,
.phy_base_addr = 0x0,

113
target/linux/generic/backport-5.15/893-v6.5-05-net-dsa-mv88e6xxx-pass-mv88e6xxx_chip-structure-to-p.patch Normal file
View File

@ -0,0 +1,113 @@
From 68690045f8e220826517c0d6f9388ffc1faa57ea Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
Date: Mon, 29 May 2023 10:02:45 +0200
Subject: [PATCH 897/898] net: dsa: mv88e6xxx: pass mv88e6xxx_chip structure to
port_max_speed_mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Some switches families have minor differences on supported link speed for
ports. Instead of redefining a new port_max_speed_mode for each different
configuration, allow to pass mv88e6xxx_chip structure to allow
differentiating those chips by known chip id
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Update one more instance of port_max_speed_mode that 5.15 has.
[Robert Marko]
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 2 +-
drivers/net/dsa/mv88e6xxx/chip.h | 3 ++-
drivers/net/dsa/mv88e6xxx/port.c | 12 ++++++++----
drivers/net/dsa/mv88e6xxx/port.h | 12 ++++++++----
4 files changed, 19 insertions(+), 10 deletions(-)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -443,7 +443,7 @@ static int mv88e6xxx_port_setup_mac(stru
}
if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
- mode = chip->info->ops->port_max_speed_mode(port);
+ mode = chip->info->ops->port_max_speed_mode(chip, port);
if (chip->info->ops->port_set_pause) {
err = chip->info->ops->port_set_pause(chip, port, pause);
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -485,7 +485,8 @@ struct mv88e6xxx_ops {
int speed, int duplex);
/* What interface mode should be used for maximum speed? */
- phy_interface_t (*port_max_speed_mode)(int port);
+ phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip,
+ int port);
int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -357,7 +357,8 @@ int mv88e6341_port_set_speed_duplex(stru
duplex);
}
-phy_interface_t mv88e6341_port_max_speed_mode(int port)
+phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port)
{
if (port == 5)
return PHY_INTERFACE_MODE_2500BASEX;
@@ -402,7 +403,8 @@ int mv88e6390_port_set_speed_duplex(stru
duplex);
}
-phy_interface_t mv88e6390_port_max_speed_mode(int port)
+phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port)
{
if (port == 9 || port == 10)
return PHY_INTERFACE_MODE_2500BASEX;
@@ -427,7 +429,8 @@ int mv88e6390x_port_set_speed_duplex(str
duplex);
}
-phy_interface_t mv88e6390x_port_max_speed_mode(int port)
+phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port)
{
if (port == 9 || port == 10)
return PHY_INTERFACE_MODE_XAUI;
@@ -527,7 +530,8 @@ int mv88e6393x_port_set_speed_duplex(str
return 0;
}
-phy_interface_t mv88e6393x_port_max_speed_mode(int port)
+phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port)
{
if (port == 0 || port == 9 || port == 10)
return PHY_INTERFACE_MODE_10GBASER;
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -350,10 +350,14 @@ int mv88e6390x_port_set_speed_duplex(str
int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
int speed, int duplex);
-phy_interface_t mv88e6341_port_max_speed_mode(int port);
-phy_interface_t mv88e6390_port_max_speed_mode(int port);
-phy_interface_t mv88e6390x_port_max_speed_mode(int port);
-phy_interface_t mv88e6393x_port_max_speed_mode(int port);
+phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port);
+phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port);
+phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port);
+phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port);
int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);

165
target/linux/generic/backport-5.15/893-v6.5-06-net-dsa-mv88e6xxx-enable-support-for-88E6361-switch.patch Normal file
View File

@ -0,0 +1,165 @@
From f318a015330a11befd8c69336efc6284e240f535 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
Date: Mon, 29 May 2023 10:02:46 +0200
Subject: [PATCH 898/898] net: dsa: mv88e6xxx: enable support for 88E6361
switch
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Marvell 88E6361 is an 8-port switch derived from the
88E6393X/88E9193X/88E6191X switches family. It can benefit from the
existing mv88e6xxx driver by simply adding the proper switch description in
the driver. Main differences with other switches from this
family are:
- 8 ports exposed (instead of 11): ports 1, 2 and 8 not available
- No 5GBase-x nor SFI/USXGMII support
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Adapt to 5.15 since we dont have phylink_get_caps yet.
So, update the old mv88e6393x_phylink_validate instead.
Remove max_sid since 5.15 driver does not support it yet.
[Robert Marko]
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 49 +++++++++++++++++++++++++++++++-
drivers/net/dsa/mv88e6xxx/chip.h | 3 +-
drivers/net/dsa/mv88e6xxx/port.c | 14 +++++++--
drivers/net/dsa/mv88e6xxx/port.h | 1 +
4 files changed, 62 insertions(+), 5 deletions(-)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -648,6 +648,8 @@ static void mv88e6393x_phylink_validate(
{
bool is_6191x =
chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
+ bool is_6361 =
+ chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
if (((port == 0 || port == 9) && !is_6191x) || port == 10) {
phylink_set(mask, 10000baseT_Full);
@@ -662,8 +664,28 @@ static void mv88e6393x_phylink_validate(
phylink_set(mask, 2500baseT_Full);
}
+ if (port == 0 || port == 9 || port == 10) {
+ phylink_set(mask, 1000baseX_Full);
+
+ /* 6191X supports >1G modes only on port 10 */
+ if (!is_6191x || port == 10) {
+ phylink_set(mask, 2500baseX_Full);
+ phylink_set(mask, 2500baseT_Full);
+
+ if (!is_6361) {
+ phylink_set(mask, 10000baseT_Full);
+ phylink_set(mask, 10000baseKR_Full);
+ phylink_set(mask, 10000baseCR_Full);
+ phylink_set(mask, 10000baseSR_Full);
+ phylink_set(mask, 10000baseLR_Full);
+ phylink_set(mask, 10000baseLRM_Full);
+ phylink_set(mask, 10000baseER_Full);
+ phylink_set(mask, 5000baseT_Full);
+ }
+ }
+ }
+
phylink_set(mask, 1000baseT_Full);
- phylink_set(mask, 1000baseX_Full);
mv88e6065_phylink_validate(chip, port, mask, state);
}
@@ -5649,6 +5671,31 @@ static const struct mv88e6xxx_info mv88e
.ptp_support = true,
.ops = &mv88e6352_ops,
},
+ [MV88E6361] = {
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
+ .family = MV88E6XXX_FAMILY_6393,
+ .name = "Marvell 88E6361",
+ .num_databases = 4096,
+ .num_macs = 16384,
+ .num_ports = 11,
+ /* Ports 1, 2 and 8 are not routed */
+ .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
+ .num_internal_phys = 5,
+ .internal_phys_offset = 3,
+ .max_vid = 4095,
+ .port_base_addr = 0x0,
+ .phy_base_addr = 0x0,
+ .global1_addr = 0x1b,
+ .global2_addr = 0x1c,
+ .age_time_coeff = 3750,
+ .g1_irqs = 10,
+ .g2_irqs = 14,
+ .atu_move_port_mask = 0x1f,
+ .pvt = true,
+ .multi_chip = true,
+ .ptp_support = true,
+ .ops = &mv88e6393x_ops,
+ },
[MV88E6390] = {
.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
.family = MV88E6XXX_FAMILY_6390,
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -81,6 +81,7 @@ enum mv88e6xxx_model {
MV88E6350,
MV88E6351,
MV88E6352,
+ MV88E6361,
MV88E6390,
MV88E6390X,
MV88E6393X,
@@ -99,7 +100,7 @@ enum mv88e6xxx_family {
MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
- MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */
+ MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */
};
/**
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -451,6 +451,10 @@ int mv88e6393x_port_set_speed_duplex(str
if (speed == SPEED_MAX)
speed = (port > 0 && port < 9) ? 1000 : 10000;
+ if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 &&
+ speed > 2500)
+ return -EOPNOTSUPP;
+
if (speed == 200 && port != 0)
return -EOPNOTSUPP;
@@ -533,10 +537,14 @@ int mv88e6393x_port_set_speed_duplex(str
phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
int port)
{
- if (port == 0 || port == 9 || port == 10)
- return PHY_INTERFACE_MODE_10GBASER;
- return PHY_INTERFACE_MODE_NA;
+ if (port != 0 && port != 9 && port != 10)
+ return PHY_INTERFACE_MODE_NA;
+
+ if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361)
+ return PHY_INTERFACE_MODE_2500BASEX;
+
+ return PHY_INTERFACE_MODE_10GBASER;
}
static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -128,6 +128,7 @@
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6361 0x2610
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400

64
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@ -0,0 +1,64 @@
From 4f86eb098e18fd0f032877dfa1a7e8c1503ca409 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
Date: Mon, 29 May 2023 10:02:41 +0200
Subject: [PATCH 1/6] net: dsa: mv88e6xxx: pass directly chip structure to
mv88e6xxx_phy_is_internal
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Since this function is a simple helper, we do not need to pass a full
dsa_switch structure, we can directly pass the mv88e6xxx_chip structure.
Doing so will allow to share this function with any other function
not manipulating dsa_switch structure but needing info about number of
internal phys
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/dsa/mv88e6xxx/chip.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -470,10 +470,8 @@ restore_link:
return err;
}
-static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
+static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
{
- struct mv88e6xxx_chip *chip = ds->priv;
-
return port < chip->info->num_internal_phys;
}
@@ -591,7 +589,7 @@ static void mv88e6095_phylink_get_caps(s
config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
- if (mv88e6xxx_phy_is_internal(chip->ds, port)) {
+ if (mv88e6xxx_phy_is_internal(chip, port)) {
__set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
} else {
if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
@@ -839,7 +837,7 @@ static void mv88e6xxx_get_caps(struct ds
chip->info->ops->phylink_get_caps(chip, port, config);
mv88e6xxx_reg_unlock(chip);
- if (mv88e6xxx_phy_is_internal(ds, port)) {
+ if (mv88e6xxx_phy_is_internal(chip, port)) {
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
config->supported_interfaces);
/* Internal ports with no phy-mode need GMII for PHYLIB */
@@ -860,7 +858,7 @@ static void mv88e6xxx_mac_config(struct
mv88e6xxx_reg_lock(chip);
- if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) {
+ if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
/* In inband mode, the link may come up at any time while the
* link is not forced down. Force the link down while we
* reconfigure the interface mode.

31
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@ -0,0 +1,31 @@
From 73cbfad9296eed004992806e056db5b48583ca41 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
Date: Mon, 29 May 2023 10:02:42 +0200
Subject: [PATCH 2/6] net: dsa: mv88e6xxx: use mv88e6xxx_phy_is_internal in
mv88e6xxx_port_ppu_updates
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Make sure to use existing helper to get internal PHYs count instead of
redoing it manually
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/dsa/mv88e6xxx/chip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -484,7 +484,7 @@ static int mv88e6xxx_port_ppu_updates(st
* report whether the port is internal.
*/
if (chip->info->family == MV88E6XXX_FAMILY_6250)
- return port < chip->info->num_internal_phys;
+ return mv88e6xxx_phy_is_internal(chip, port);
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
if (err) {

69
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@ -0,0 +1,69 @@
From 1414d30660d201f515a9d877571ceea9ca190b6a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
Date: Mon, 29 May 2023 10:02:43 +0200
Subject: [PATCH 3/6] net: dsa: mv88e6xxx: add field to specify internal phys
layout
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
mv88e6xxx currently assumes that switch equipped with internal phys have
those phys mapped contiguously starting from port 0 (see
mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but
NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have
integrated PHYs available on ports 1 to 8
To properly support this offset, add a new field to allow specifying an
internal PHYs layout. If field is not set, default layout is assumed (start
at port 0)
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/dsa/mv88e6xxx/chip.c | 4 +++-
drivers/net/dsa/mv88e6xxx/chip.h | 5 +++++
drivers/net/dsa/mv88e6xxx/global2.c | 5 ++++-
3 files changed, 12 insertions(+), 2 deletions(-)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -472,7 +472,9 @@ restore_link:
static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
{
- return port < chip->info->num_internal_phys;
+ return port >= chip->info->internal_phys_offset &&
+ port < chip->info->num_internal_phys +
+ chip->info->internal_phys_offset;
}
static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -167,6 +167,11 @@ struct mv88e6xxx_info {
/* Supports PTP */
bool ptp_support;
+
+ /* Internal PHY start index. 0 means that internal PHYs range starts at
+ * port 0, 1 means internal PHYs range starts at port 1, etc
+ */
+ unsigned int internal_phys_offset;
};
struct mv88e6xxx_atu_entry {
--- a/drivers/net/dsa/mv88e6xxx/global2.c
+++ b/drivers/net/dsa/mv88e6xxx/global2.c
@@ -1185,8 +1185,11 @@ int mv88e6xxx_g2_irq_mdio_setup(struct m
struct mii_bus *bus)
{
int phy, irq, err, err_phy;
+ int phy_start = chip->info->internal_phys_offset;
+ int phy_end = chip->info->internal_phys_offset +
+ chip->info->num_internal_phys;
- for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
+ for (phy = phy_start; phy < phy_end; phy++) {
irq = irq_find_mapping(chip->g2_irq.domain, phy);
if (irq < 0) {
err = irq;

52
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@ -0,0 +1,52 @@
From eb8c75f82a6711387f3b9e03e28923f3e75a761b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
Date: Mon, 29 May 2023 10:02:44 +0200
Subject: [PATCH 4/6] net: dsa: mv88e6xxx: fix 88E6393X family internal phys
layout
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
88E6393X/88E6193X/88E6191X switches have in fact 8 internal PHYs, but those
are not present starting at port 0: supported ports go from 1 to 8
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/dsa/mv88e6xxx/chip.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -5942,7 +5942,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6191X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
- .num_internal_phys = 9,
+ .num_internal_phys = 8,
+ .internal_phys_offset = 1,
.max_vid = 8191,
.max_sid = 63,
.port_base_addr = 0x0,
@@ -5965,7 +5966,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6193X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
- .num_internal_phys = 9,
+ .num_internal_phys = 8,
+ .internal_phys_offset = 1,
.max_vid = 8191,
.max_sid = 63,
.port_base_addr = 0x0,
@@ -6284,7 +6286,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6393X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
- .num_internal_phys = 9,
+ .num_internal_phys = 8,
+ .internal_phys_offset = 1,
.max_vid = 8191,
.max_sid = 63,
.port_base_addr = 0x0,

110
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@ -0,0 +1,110 @@
From cef945452c8468efce75ba0dc8420510a5b84af9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
Date: Mon, 29 May 2023 10:02:45 +0200
Subject: [PATCH 5/6] net: dsa: mv88e6xxx: pass mv88e6xxx_chip structure to
port_max_speed_mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Some switches families have minor differences on supported link speed for
ports. Instead of redefining a new port_max_speed_mode for each different
configuration, allow to pass mv88e6xxx_chip structure to allow
differentiating those chips by known chip id
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/dsa/mv88e6xxx/chip.c | 2 +-
drivers/net/dsa/mv88e6xxx/chip.h | 3 ++-
drivers/net/dsa/mv88e6xxx/port.c | 12 ++++++++----
drivers/net/dsa/mv88e6xxx/port.h | 12 ++++++++----
4 files changed, 19 insertions(+), 10 deletions(-)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -3326,7 +3326,7 @@ static int mv88e6xxx_setup_port(struct m
caps = pl_config.mac_capabilities;
if (chip->info->ops->port_max_speed_mode)
- mode = chip->info->ops->port_max_speed_mode(port);
+ mode = chip->info->ops->port_max_speed_mode(chip, port);
else
mode = PHY_INTERFACE_MODE_NA;
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -508,7 +508,8 @@ struct mv88e6xxx_ops {
int speed, int duplex);
/* What interface mode should be used for maximum speed? */
- phy_interface_t (*port_max_speed_mode)(int port);
+ phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip,
+ int port);
int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -342,7 +342,8 @@ int mv88e6341_port_set_speed_duplex(stru
duplex);
}
-phy_interface_t mv88e6341_port_max_speed_mode(int port)
+phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port)
{
if (port == 5)
return PHY_INTERFACE_MODE_2500BASEX;
@@ -381,7 +382,8 @@ int mv88e6390_port_set_speed_duplex(stru
duplex);
}
-phy_interface_t mv88e6390_port_max_speed_mode(int port)
+phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port)
{
if (port == 9 || port == 10)
return PHY_INTERFACE_MODE_2500BASEX;
@@ -403,7 +405,8 @@ int mv88e6390x_port_set_speed_duplex(str
duplex);
}
-phy_interface_t mv88e6390x_port_max_speed_mode(int port)
+phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port)
{
if (port == 9 || port == 10)
return PHY_INTERFACE_MODE_XAUI;
@@ -500,7 +503,8 @@ int mv88e6393x_port_set_speed_duplex(str
return 0;
}
-phy_interface_t mv88e6393x_port_max_speed_mode(int port)
+phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port)
{
if (port == 0 || port == 9 || port == 10)
return PHY_INTERFACE_MODE_10GBASER;
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -359,10 +359,14 @@ int mv88e6390x_port_set_speed_duplex(str
int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
int speed, int duplex);
-phy_interface_t mv88e6341_port_max_speed_mode(int port);
-phy_interface_t mv88e6390_port_max_speed_mode(int port);
-phy_interface_t mv88e6390x_port_max_speed_mode(int port);
-phy_interface_t mv88e6393x_port_max_speed_mode(int port);
+phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port);
+phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port);
+phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port);
+phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port);
int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);

153
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@ -0,0 +1,153 @@
From 23680321789863bab2d60af507858ce50ff9f56a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
Date: Mon, 29 May 2023 10:02:46 +0200
Subject: [PATCH 6/6] net: dsa: mv88e6xxx: enable support for 88E6361 switch
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Marvell 88E6361 is an 8-port switch derived from the
88E6393X/88E9193X/88E6191X switches family. It can benefit from the
existing mv88e6xxx driver by simply adding the proper switch description in
the driver. Main differences with other switches from this
family are:
- 8 ports exposed (instead of 11): ports 1, 2 and 8 not available
- No 5GBase-x nor SFI/USXGMII support
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/dsa/mv88e6xxx/chip.c | 42 ++++++++++++++++++++++++++++----
drivers/net/dsa/mv88e6xxx/chip.h | 3 ++-
drivers/net/dsa/mv88e6xxx/port.c | 14 ++++++++---
drivers/net/dsa/mv88e6xxx/port.h | 1 +
4 files changed, 51 insertions(+), 9 deletions(-)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -797,6 +797,8 @@ static void mv88e6393x_phylink_get_caps(
unsigned long *supported = config->supported_interfaces;
bool is_6191x =
chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
+ bool is_6361 =
+ chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
@@ -811,13 +813,17 @@ static void mv88e6393x_phylink_get_caps(
/* 6191X supports >1G modes only on port 10 */
if (!is_6191x || port == 10) {
__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
- __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
- __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
+ config->mac_capabilities |= MAC_2500FD;
+
+ /* 6361 only supports up to 2500BaseX */
+ if (!is_6361) {
+ __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
+ config->mac_capabilities |= MAC_5000FD |
+ MAC_10000FD;
+ }
/* FIXME: USXGMII is not supported yet */
/* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */
-
- config->mac_capabilities |= MAC_2500FD | MAC_5000FD |
- MAC_10000FD;
}
}
@@ -6229,6 +6235,32 @@ static const struct mv88e6xxx_info mv88e
.ptp_support = true,
.ops = &mv88e6352_ops,
},
+ [MV88E6361] = {
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
+ .family = MV88E6XXX_FAMILY_6393,
+ .name = "Marvell 88E6361",
+ .num_databases = 4096,
+ .num_macs = 16384,
+ .num_ports = 11,
+ /* Ports 1, 2 and 8 are not routed */
+ .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
+ .num_internal_phys = 5,
+ .internal_phys_offset = 3,
+ .max_vid = 4095,
+ .max_sid = 63,
+ .port_base_addr = 0x0,
+ .phy_base_addr = 0x0,
+ .global1_addr = 0x1b,
+ .global2_addr = 0x1c,
+ .age_time_coeff = 3750,
+ .g1_irqs = 10,
+ .g2_irqs = 14,
+ .atu_move_port_mask = 0x1f,
+ .pvt = true,
+ .multi_chip = true,
+ .ptp_support = true,
+ .ops = &mv88e6393x_ops,
+ },
[MV88E6390] = {
.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
.family = MV88E6XXX_FAMILY_6390,
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -82,6 +82,7 @@ enum mv88e6xxx_model {
MV88E6350,
MV88E6351,
MV88E6352,
+ MV88E6361,
MV88E6390,
MV88E6390X,
MV88E6393X,
@@ -100,7 +101,7 @@ enum mv88e6xxx_family {
MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
- MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */
+ MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */
};
/**
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -424,6 +424,10 @@ int mv88e6393x_port_set_speed_duplex(str
u16 reg, ctrl;
int err;
+ if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 &&
+ speed > 2500)
+ return -EOPNOTSUPP;
+
if (speed == 200 && port != 0)
return -EOPNOTSUPP;
@@ -506,10 +510,14 @@ int mv88e6393x_port_set_speed_duplex(str
phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
int port)
{
- if (port == 0 || port == 9 || port == 10)
- return PHY_INTERFACE_MODE_10GBASER;
- return PHY_INTERFACE_MODE_NA;
+ if (port != 0 && port != 9 && port != 10)
+ return PHY_INTERFACE_MODE_NA;
+
+ if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361)
+ return PHY_INTERFACE_MODE_2500BASEX;
+
+ return PHY_INTERFACE_MODE_10GBASER;
}
static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -133,6 +133,7 @@
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6361 0x2610
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400

2
target/linux/generic/hack-5.15/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch
View File

@ -9,7 +9,7 @@ Subject: [PATCH] net/dsa/mv88e6xxx: disable ATU violation
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -2993,6 +2993,9 @@ static int mv88e6xxx_setup_port(struct m
@@ -3015,6 +3015,9 @@ static int mv88e6xxx_setup_port(struct m
else
reg = 1 << port;

2
target/linux/generic/hack-6.1/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch
View File

@ -9,7 +9,7 @@ Subject: [PATCH] net/dsa/mv88e6xxx: disable ATU violation
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -3480,6 +3480,9 @@ static int mv88e6xxx_setup_port(struct m
@@ -3486,6 +3486,9 @@ static int mv88e6xxx_setup_port(struct m
else
reg = 1 << port;

2
target/linux/generic/pending-5.15/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch
View File

@ -17,7 +17,7 @@ Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -6341,6 +6341,7 @@ static int mv88e6xxx_register_switch(str
@@ -6391,6 +6391,7 @@ static int mv88e6xxx_register_switch(str
ds->ops = &mv88e6xxx_switch_ops;
ds->ageing_time_min = chip->info->age_time_coeff;
ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;

2
target/linux/generic/pending-6.1/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch
View File

@ -17,7 +17,7 @@ Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -6988,6 +6988,7 @@ static int mv88e6xxx_register_switch(str
@@ -7023,6 +7023,7 @@ static int mv88e6xxx_register_switch(str
ds->ops = &mv88e6xxx_switch_ops;
ds->ageing_time_min = chip->info->age_time_coeff;
ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;

1
target/linux/ipq40xx/base-files/etc/board.d/02_network
View File

@ -114,6 +114,7 @@ ipq40xx_setup_interfaces()
zte,mf286d)
ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" "wan"
;;
zte,mf287|\
zte,mf287plus|\
zte,mf287pro)
ucidef_set_interface_lan "lan1 lan2 lan3 lan4"

1
target/linux/ipq40xx/base-files/lib/upgrade/platform.sh
View File

@ -27,6 +27,7 @@ EOF
;;
zte,mf18a |\
zte,mf286d |\
zte,mf287|\
zte,mf287plus |\
zte,mf287pro |\
zte,mf289f)

221
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-mf287.dts Normal file
View File

@ -0,0 +1,221 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
#include "qcom-ipq4018-mf287_common.dtsi"
/ {
model = "ZTE MF287";
compatible = "zte,mf287";
};
&gpio_modem_reset {
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
&key_reset {
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
};
&key_wps {
gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
};
&led_status {
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
<&tlmm 59 GPIO_ACTIVE_HIGH>,
<&tlmm 1 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0xf0000 0xc0000>;
read-only;
};
partition@1b0000 {
label = "0:reserved1";
reg = <0x1b0000 0x50000>;
read-only;
};
};
};
spi-nand@1 { /* flash@1 ? */
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "fota-flag";
reg = <0x0 0x140000>;
read-only;
};
partition@140000 {
label = "ART";
reg = <0x140000 0x140000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
partition@280000 {
label = "mac";
reg = <0x280000 0x140000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_mac_0: macaddr@0 {
reg = <0x0 0x6>;
};
};
partition@3c0000 {
label = "cfg-param";
reg = <0x3c0000 0x600000>;
read-only;
};
partition@9c0000 {
label = "oops";
reg = <0x9c0000 0x140000>;
};
partition@b00000 {
label = "web";
reg = <0xb00000 0x800000>;
};
partition@1300000 {
label = "rootfs";
reg = <0x1300000 0x2200000>;
};
partition@3500000 {
label = "data";
reg = <0x3500000 0x1900000>;
};
partition@4e00000 {
label = "fota";
reg = <0x4e00000 0x3200000>;
};
};
};
zigbee@2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "silabs,em3581";
reg = <2>;
spi-max-frequency = <12000000>;
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio54", "gpio59", "gpio1";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&wifi0 {
qcom,ath10k-calibration-variant = "zte,mf287";
};
&wifi1{
qcom,ath10k-calibration-variant = "zte,mf287";
};

12
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-mf287.dtsi → target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-mf287_common.dtsi
View File

@ -35,6 +35,16 @@
};
};
gpio_export {
compatible = "gpio-export";
#size-cells = <0>;
gpio_modem_reset: modem {
gpio-export,name = "modem-reset";
gpio-export,output = <0>;
};
};
keys {
compatible = "gpio-keys";
@ -171,7 +181,6 @@
status = "okay";
nvmem-cell-names = "pre-calibration", "mac-address";
nvmem-cells = <&precal_art_1000>, <&macaddr_mac_0>;
qcom,ath10k-calibration-variant = "zte,mf287plus";
};
&wifi1 {
@ -179,5 +188,4 @@
nvmem-cell-names = "pre-calibration", "mac-address";
nvmem-cells = <&precal_art_5000>, <&macaddr_mac_0>;
mac-address-increment = <1>;
qcom,ath10k-calibration-variant = "zte,mf287plus";
};

21
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-mf287plus.dts
View File

@ -3,20 +3,15 @@
// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
#include "qcom-ipq4018-mf287.dtsi"
#include "qcom-ipq4018-mf287_common.dtsi"
/ {
model = "ZTE MF287Plus";
compatible = "zte,mf287plus";
};
/*
* This node is used to restart modem module to avoid anomalous
* behaviours on initial communication.
*/
gpio-restart {
compatible = "gpio-restart";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
&gpio_modem_reset {
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
&key_reset {
@ -216,3 +211,11 @@
};
};
};
&wifi0 {
qcom,ath10k-calibration-variant = "zte,mf287plus";
};
&wifi1{
qcom,ath10k-calibration-variant = "zte,mf287plus";
};

27
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-mf287pro.dts
View File

@ -3,23 +3,12 @@
// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
#include "qcom-ipq4018-mf287.dtsi"
#include "qcom-ipq4018-mf287_common.dtsi"
/ {
model = "ZTE MF287Pro";
compatible = "zte,mf287pro";
gpio_export {
compatible = "gpio-export";
#size-cells = <0>;
modem {
gpio-export,name = "modem-reset";
gpio-export,output = <0>;
gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
};
};
regulator-usb-vbus {
compatible = "regulator-fixed";
regulator-name = "USB_VBUS";
@ -31,6 +20,10 @@
};
};
&gpio_modem_reset {
gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
};
&key_reset {
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
};
@ -263,3 +256,13 @@
};
};
};
/* The MF287Plus and MF287Pro share the same board data file */
&wifi0 {
qcom,ath10k-calibration-variant = "zte,mf287plus";
};
/* The MF287Plus and MF287Pro share the same board data file */
&wifi1{
qcom,ath10k-calibration-variant = "zte,mf287plus";
};

13
target/linux/ipq40xx/image/generic.mk
View File

@ -1168,7 +1168,6 @@ TARGET_DEVICES += zte_mf286d
define Device/zte_mf287_common
$(call Device/zte_mf28x_common)
DEVICE_PACKAGES += ipq-wifi-zte_mf287plus
SOC := qcom-ipq4018
# The recovery image is used to return back to stock (an initramfs-based image
# that can be flashed to the device via sysupgrade
@ -1181,15 +1180,23 @@ endef
define Device/zte_mf287plus
$(call Device/zte_mf287_common)
DEVICE_PACKAGES += ipq-wifi-zte_mf287plus
DEVICE_DTS_CONFIG := config@ap.dk01.1-c2
DEVICE_MODEL := MF287Plus
DEVICE_ALT0_VENDOR := ZTE
DEVICE_ALT0_MODEL := MF287
endef
TARGET_DEVICES += zte_mf287plus
define Device/zte_mf287
$(call Device/zte_mf287_common)
DEVICE_PACKAGES += ipq-wifi-zte_mf287
DEVICE_DTS_CONFIG := config@ap.dk01.1-c2
DEVICE_MODEL := MF287
endef
TARGET_DEVICES += zte_mf287
define Device/zte_mf287pro
$(call Device/zte_mf287_common)
DEVICE_PACKAGES += ipq-wifi-zte_mf287plus
DEVICE_DTS_CONFIG := config@ap.dk04.1-c1
DEVICE_MODEL := MF287Pro
endef

11
target/linux/mvebu/cortexa53/base-files/etc/board.d/02_network
View File

@ -21,10 +21,17 @@ globalscale,espressobin-ultra)
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "wan"
;;
marvell,armada-3720-db|\
methode,udpu|\
methode,edpu)
methode,udpu)
ucidef_set_interfaces_lan_wan "eth1" "eth0"
;;
methode,edpu)
# eDPU+ has a 88E6361 switch, so we check for it
if ip link | grep -q uplink; then
ucidef_set_interfaces_lan_wan "downlink" "uplink"
else
ucidef_set_interfaces_lan_wan "eth1" "eth0"
fi
;;
*)
ucidef_set_interface_lan "eth0"
;;

47
target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts
View File

@ -17,3 +17,50 @@
&eth0 {
phy-mode = "1000base-x";
};
/*
* External MV88E6361 switch is only available on v2 of the board.
* U-Boot will enable the MDIO bus and switch nodes.
*/
&mdio {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&smi_pins>;
/* Actual device is MV88E6361 */
switch: switch@0 {
compatible = "marvell,mv88e6190";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
phy-mode = "2500base-x";
managed = "in-band-status";
ethernet = <&eth0>;
};
port@9 {
reg = <9>;
label = "downlink";
phy-mode = "2500base-x";
managed = "in-band-status";
};
port@a {
reg = <10>;
label = "uplink";
phy-mode = "2500base-x";
managed = "in-band-status";
sfp = <&sfp_eth1>;
};
};
};
};

1
target/linux/sunxi/config-6.1
View File

@ -243,6 +243,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y

1
target/linux/sunxi/cortexa7/config-6.1
View File

@ -1,5 +1,6 @@
# CONFIG_ARM_LPAE is not set
# CONFIG_ARM_SMMU is not set
# CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set
CONFIG_B53=y
CONFIG_B53_MDIO_DRIVER=y
CONFIG_CRYPTO_BLAKE2S_ARM=y

1
target/linux/sunxi/cortexa8/config-6.1
View File

@ -1,5 +1,6 @@
# CONFIG_ARM_LPAE is not set
# CONFIG_ARM_SMMU is not set
# CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set
CONFIG_CRYPTO_BLAKE2S_ARM=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set

606
target/linux/x86/64/config-6.1 Normal file
View File

@ -0,0 +1,606 @@
CONFIG_64BIT=y
# CONFIG_ACER_WMI is not set
CONFIG_ACPI=y
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
# CONFIG_ACPI_BGRT is not set
CONFIG_ACPI_BUTTON=y
# CONFIG_ACPI_CMPC is not set
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_CPPC_LIB=y
CONFIG_ACPI_CPU_FREQ_PSS=y
# CONFIG_ACPI_DEBUG is not set
# CONFIG_ACPI_DEBUGGER is not set
# CONFIG_ACPI_DOCK is not set
# CONFIG_ACPI_DPTF is not set
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_FPDT is not set
CONFIG_ACPI_HOTPLUG_CPU=y
CONFIG_ACPI_HOTPLUG_IOAPIC=y
# CONFIG_ACPI_I2C_OPREGION is not set
CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
CONFIG_ACPI_LPIT=y
CONFIG_ACPI_PCC=y
# CONFIG_ACPI_PCI_SLOT is not set
# CONFIG_ACPI_PFRUT is not set
CONFIG_ACPI_PRMT=y
CONFIG_ACPI_PROCESSOR=y
# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
CONFIG_ACPI_PROCESSOR_CSTATE=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
# CONFIG_ACPI_SBS is not set
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
# CONFIG_ACPI_TAD is not set
CONFIG_ACPI_THERMAL=y
# CONFIG_ACPI_TOSHIBA is not set
CONFIG_ACPI_VIDEO=y
# CONFIG_ACPI_WMI is not set
# CONFIG_ACRN_GUEST is not set
# CONFIG_ADV_SWBUTTON is not set
CONFIG_AGP=y
# CONFIG_AGP_AMD64 is not set
CONFIG_AGP_INTEL=y
# CONFIG_AGP_SIS is not set
# CONFIG_AGP_VIA is not set
# CONFIG_AMD_HSMP is not set
CONFIG_AMD_IOMMU=y
CONFIG_AMD_IOMMU_V2=y
# CONFIG_AMD_PMC is not set
# CONFIG_AMD_PMF is not set
# CONFIG_AMD_PTDMA is not set
# CONFIG_AMD_SFH_HID is not set
CONFIG_ARCH_CPUIDLE_HALTPOLL=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
CONFIG_ARCH_MMAP_RND_BITS=28
CONFIG_ARCH_MMAP_RND_BITS_MAX=32
CONFIG_ARCH_MMAP_RND_BITS_MIN=28
CONFIG_ARCH_NR_GPIO=1024
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_WANTS_THP_SWAP=y
# CONFIG_ASUS_TF103C_DOCK is not set
# CONFIG_ASUS_WMI is not set
CONFIG_AUDIT_ARCH=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
CONFIG_BLK_DEV_NVME=y
CONFIG_BLK_DEV_SR=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
CONFIG_BTT=y
CONFIG_CDROM=y
CONFIG_CONNECTOR=y
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPU_IBPB_ENTRY=y
CONFIG_CPU_IBRS_ENTRY=y
# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
CONFIG_CPU_RMAP=y
CONFIG_CPU_SRSO=y
CONFIG_CPU_UNRET_ENTRY=y
CONFIG_CRC_T10DIF=y
CONFIG_CRYPTO_AES_NI_INTEL=y
# CONFIG_CRYPTO_ARIA_AESNI_AVX_X86_64 is not set
CONFIG_CRYPTO_BLAKE2S_X86=y
# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set
# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set
# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set
# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set
# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set
# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set
CONFIG_CRYPTO_CRCT10DIF=y
# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set
CONFIG_CRYPTO_CRYPTD=y
# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
CONFIG_CRYPTO_LRW=y
# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set
# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set
# CONFIG_CRYPTO_POLYVAL_CLMUL_NI is not set
# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set
# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set
# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set
# CONFIG_CRYPTO_SHA1_SSSE3 is not set
# CONFIG_CRYPTO_SHA256_SSSE3 is not set
# CONFIG_CRYPTO_SHA512_SSSE3 is not set
CONFIG_CRYPTO_SIMD=y
# CONFIG_CRYPTO_SM3_AVX_X86_64 is not set
# CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64 is not set
# CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64 is not set
# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set
# CONFIG_CRYPTO_TWOFISH_X86_64 is not set
# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set
CONFIG_CRYPTO_XTS=y
# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
CONFIG_DMA_ACPI=y
CONFIG_DMA_OPS=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DRM=y
CONFIG_DRM_BOCHS=y
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
CONFIG_DRM_GEM_SHMEM_HELPER=y
# CONFIG_DRM_HYPERV is not set
CONFIG_DRM_I915=y
CONFIG_DRM_I915_CAPTURE_ERROR=y
CONFIG_DRM_I915_COMPRESS_ERROR=y
# CONFIG_DRM_I915_DEBUG is not set
# CONFIG_DRM_I915_DEBUG_GUC is not set
# CONFIG_DRM_I915_DEBUG_MMIO is not set
# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
CONFIG_DRM_I915_FENCE_TIMEOUT=10000
CONFIG_DRM_I915_FORCE_PROBE=""
CONFIG_DRM_I915_GVT=y
CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
# CONFIG_DRM_I915_SELFTEST is not set
CONFIG_DRM_I915_STOP_TIMEOUT=100
# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
CONFIG_DRM_I915_TIMESLICE_DURATION=1
CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
CONFIG_DRM_I915_USERPTR=y
# CONFIG_DRM_I915_WERROR is not set
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_PANEL=y
CONFIG_DRM_PANEL_BRIDGE=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_TTM=y
CONFIG_DRM_TTM_HELPER=y
CONFIG_DRM_VIRTIO_GPU=y
CONFIG_DRM_VRAM_HELPER=y
CONFIG_EFI=y
CONFIG_EFIVAR_FS=m
# CONFIG_EFI_BOOTLOADER_CONTROL is not set
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_COCO_SECRET is not set
# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
# CONFIG_EFI_DISABLE_RUNTIME is not set
CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_ESRT=y
# CONFIG_EFI_FAKE_MEMMAP is not set
CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
# CONFIG_EFI_MIXED is not set
# CONFIG_EFI_PGT_DUMP is not set
# CONFIG_EFI_RCI2_TABLE is not set
CONFIG_EFI_RUNTIME_MAP=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
# CONFIG_EFI_SECRET is not set
CONFIG_EFI_STUB=y
# CONFIG_EFI_TEST is not set
# CONFIG_EFI_VARS is not set
CONFIG_FAILOVER=y
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_EFI=y
CONFIG_FB_HYPERV=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_SIMPLE=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_SYS_IMAGEBLIT=y
CONFIG_FB_TILEBLITTING=y
# CONFIG_FB_VESA is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_FONT_SUPPORT=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FREEZER=y
CONFIG_FUSION_SAS=y
CONFIG_FW_CACHE=y
CONFIG_GART_IOMMU=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CPU=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_PENDING_IRQ=y
# CONFIG_GIGABYTE_WMI is not set
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_ICH=y
CONFIG_GPIO_SCH=y
CONFIG_HALTPOLL_CPUIDLE=y
CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y
CONFIG_HDMI=y
CONFIG_HIBERNATE_CALLBACKS=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HID_GENERIC=y
CONFIG_HID_HYPERV_MOUSE=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_ACPI=y
# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_PCIE is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set
CONFIG_HOTPLUG_SMT=y
CONFIG_HPET=y
CONFIG_HPET_MMAP=y
# CONFIG_HP_ACCEL is not set
# CONFIG_HUAWEI_WMI is not set
CONFIG_HVC_DRIVER=y
CONFIG_HVC_IRQ=y
CONFIG_HVC_XEN=y
CONFIG_HVC_XEN_FRONTEND=y
CONFIG_HWMON=y
CONFIG_HWMON_VID=y
CONFIG_HW_RANDOM_AMD=y
CONFIG_HW_RANDOM_INTEL=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_HYPERV=y
CONFIG_HYPERVISOR_GUEST=y
CONFIG_HYPERV_BALLOON=y
CONFIG_HYPERV_IOMMU=y
CONFIG_HYPERV_KEYBOARD=y
CONFIG_HYPERV_NET=y
CONFIG_HYPERV_STORAGE=y
# CONFIG_HYPERV_TESTING is not set
CONFIG_HYPERV_TIMER=y
CONFIG_HYPERV_UTILS=y
# CONFIG_HYPERV_VSOCKETS is not set
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_AMD_MP2 is not set
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_HID_ACPI is not set
# CONFIG_I2C_MULTI_INSTANTIATE is not set
# CONFIG_I8K is not set
# CONFIG_IA32_EMULATION is not set
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
CONFIG_INTEL_GTT=y
CONFIG_INTEL_IDLE=y
# CONFIG_INTEL_IDXD is not set
# CONFIG_INTEL_IDXD_COMPAT is not set
CONFIG_INTEL_IOMMU=y
# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set
CONFIG_INTEL_IOMMU_FLOPPY_WA=y
# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set
# CONFIG_INTEL_IOMMU_SVM is not set
# CONFIG_INTEL_IPS is not set
# CONFIG_INTEL_MEI_HDCP is not set
# CONFIG_INTEL_MEI_PXP is not set
# CONFIG_INTEL_MENLOW is not set
CONFIG_INTEL_PCH_THERMAL=y
# CONFIG_INTEL_SAR_INT1092 is not set
# CONFIG_INTEL_SCU_PLATFORM is not set
CONFIG_INTEL_SOC_DTS_IOSF_CORE=y
CONFIG_INTEL_SOC_DTS_THERMAL=y
# CONFIG_INTEL_SPEED_SELECT_INTERFACE is not set
CONFIG_INTEL_TDX_GUEST=y
# CONFIG_INTEL_TURBO_MAX_3 is not set
# CONFIG_INTEL_TXT is not set
# CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set
# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
# CONFIG_INTEL_WMI_THUNDERBOLT is not set
CONFIG_INTERVAL_TREE=y
CONFIG_IOASID=y
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_DEBUG is not set
# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_DEFAULT_DMA_LAZY=y
# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_IOMMU_DMA=y
CONFIG_IOMMU_HELPER=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_SUPPORT=y
CONFIG_IOSF_MBI=y
# CONFIG_IOSF_MBI_DEBUG is not set
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_REMAP=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_ISO9660_FS=y
CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y
CONFIG_KCMP=y
CONFIG_KVM_GUEST=y
CONFIG_LEDS_GPIO=y
# CONFIG_LEGACY_VSYSCALL_EMULATE is not set
CONFIG_LEGACY_VSYSCALL_NONE=y
# CONFIG_LEGACY_VSYSCALL_XONLY is not set
# CONFIG_LG_LAPTOP is not set
CONFIG_LIBNVDIMM=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LPC_ICH=y
CONFIG_LPC_SCH=y
CONFIG_MAILBOX=y
# CONFIG_MAXSMP is not set
CONFIG_MEMORY_BALLOON=y
CONFIG_MEMREGION=y
# CONFIG_MERAKI_MX100 is not set
CONFIG_MFD_CORE=y
# CONFIG_MFD_INTEL_LPSS_ACPI is not set
# CONFIG_MFD_INTEL_PMC_BXT is not set
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ACPI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PCI=y
# CONFIG_MMC_SDHCI_PLTFM is not set
# CONFIG_MMC_WBSD is not set
CONFIG_MMU_NOTIFIER=y
CONFIG_MODULES_USE_ELF_RELA=y
# CONFIG_MPSC is not set
# CONFIG_MSI_WMI is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
# CONFIG_MXM_WMI is not set
CONFIG_ND_BLK=y
CONFIG_ND_BTT=y
CONFIG_ND_CLAIM=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NET_FAILOVER=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
# CONFIG_NITRO_ENCLAVES is not set
CONFIG_NR_CPUS=512
CONFIG_NR_CPUS_DEFAULT=64
CONFIG_NR_CPUS_RANGE_BEGIN=2
CONFIG_NR_CPUS_RANGE_END=512
# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
CONFIG_NVME_CORE=y
CONFIG_NVME_HWMON=y
CONFIG_NVME_MULTIPATH=y
CONFIG_OUTPUT_FORMAT="elf64-x86-64"
CONFIG_PADATA=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_REPORTING=y
CONFIG_PAGE_TABLE_ISOLATION=y
CONFIG_PARAVIRT=y
CONFIG_PARAVIRT_CLOCK=y
# CONFIG_PARAVIRT_DEBUG is not set
CONFIG_PARAVIRT_SPINLOCKS=y
CONFIG_PARAVIRT_XXL=y
CONFIG_PATA_AMD=y
CONFIG_PATA_ATIIXP=y
CONFIG_PATA_MPIIX=y
CONFIG_PATA_OLDPIIX=y
CONFIG_PATA_PLATFORM=y
CONFIG_PATA_TIMINGS=y
CONFIG_PATA_VIA=y
CONFIG_PCC=y
# CONFIG_PCENGINES_APU2 is not set
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_PME=y
CONFIG_PCI_HYPERV=y
CONFIG_PCI_HYPERV_INTERFACE=y
# CONFIG_PCI_MMCONFIG is not set
CONFIG_PCI_XEN=y
# CONFIG_PEAQ_WMI is not set
CONFIG_PGTABLE_LEVELS=4
CONFIG_PHYSICAL_ALIGN=0x1000000
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ALDERLAKE=y
CONFIG_PINCTRL_BAYTRAIL=y
CONFIG_PINCTRL_BROXTON=y
CONFIG_PINCTRL_CANNONLAKE=y
CONFIG_PINCTRL_CHERRYVIEW=y
CONFIG_PINCTRL_DENVERTON=y
CONFIG_PINCTRL_ELKHARTLAKE=y
CONFIG_PINCTRL_EMMITSBURG=y
CONFIG_PINCTRL_GEMINILAKE=y
CONFIG_PINCTRL_INTEL=y
CONFIG_PINCTRL_JASPERLAKE=y
CONFIG_PINCTRL_LAKEFIELD=y
CONFIG_PINCTRL_LEWISBURG=y
CONFIG_PINCTRL_LYNXPOINT=y
CONFIG_PINCTRL_METEORLAKE=y
CONFIG_PINCTRL_SUNRISEPOINT=y
CONFIG_PINCTRL_TIGERLAKE=y
CONFIG_PM=y
# CONFIG_PMIC_OPREGION is not set
CONFIG_PM_CLK=y
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
CONFIG_PNP=y
CONFIG_PNPACPI=y
CONFIG_PNP_DEBUG_MESSAGES=y
CONFIG_PPS=y
CONFIG_PROC_EVENTS=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_KVM=y
CONFIG_PTP_1588_CLOCK_VMW=y
CONFIG_PVH=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RAS=y
CONFIG_RELAY=y
CONFIG_RELOCATABLE=y
CONFIG_RESET_ATTACK_MITIGATION=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SAMSUNG_Q10 is not set
CONFIG_SATA_AHCI=y
# CONFIG_SCHED_CORE is not set
CONFIG_SCHED_MC=y
CONFIG_SCHED_MC_PRIO=y
CONFIG_SCHED_SMT=y
CONFIG_SCSI_SAS_ATTRS=y
CONFIG_SCSI_VIRTIO=y
# CONFIG_SENSORS_ASUS_EC is not set
# CONFIG_SENSORS_ASUS_WMI is not set
CONFIG_SENSORS_CORETEMP=y
CONFIG_SENSORS_FAM15H_POWER=y
CONFIG_SENSORS_I5500=y
CONFIG_SENSORS_K8TEMP=y
CONFIG_SENSORS_K10TEMP=y
CONFIG_SENSORS_VIA_CPUTEMP=y
CONFIG_SERIAL_8250_PNP=y
CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
CONFIG_SLS=y
CONFIG_SMP=y
# CONFIG_SND_HDA_CTL_DEV_ID is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
# CONFIG_SND_SOC_AMD_ACP6x is not set
# CONFIG_SND_SOC_AMD_ACP_COMMON is not set
# CONFIG_SND_SOC_AMD_PS is not set
# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set
# CONFIG_SND_SOC_INTEL_AVS is not set
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_MANUAL=y
# CONFIG_SPARSEMEM_VMEMMAP is not set
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_STACK_VALIDATION=y
# CONFIG_SURFACE_PLATFORMS is not set
CONFIG_SWIOTLB=y
CONFIG_SWIOTLB_XEN=y
CONFIG_SYNC_FILE=y
# CONFIG_SYSTEM76_ACPI is not set
CONFIG_SYS_HYPERVISOR=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
# CONFIG_THINKPAD_LMI is not set
# CONFIG_TOSHIBA_BT_RFKILL is not set
# CONFIG_TOSHIBA_WMI is not set
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
# CONFIG_UACCE is not set
# CONFIG_UCLAMP_TASK is not set
CONFIG_UCS2_STRING=y
# CONFIG_UNWINDER_ORC is not set
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_IPU3_CIO2 is not set
CONFIG_VIRTIO=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_BLK=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
CONFIG_VIRTIO_IOMMU=y
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_PCI_LIB=y
# CONFIG_VIRTIO_PMEM is not set
# CONFIG_VIRTIO_VSOCKETS is not set
CONFIG_VIRTIO_VSOCKETS_COMMON=y
CONFIG_VIRT_DRIVERS=y
CONFIG_VMAP_PFN=y
CONFIG_VMAP_STACK=y
# CONFIG_VMD is not set
CONFIG_VMGENID=y
CONFIG_VMWARE_BALLOON=y
CONFIG_VMWARE_PVSCSI=y
CONFIG_VMWARE_VMCI=y
CONFIG_VMWARE_VMCI_VSOCKETS=y
CONFIG_VMXNET3=y
CONFIG_VSOCKETS=y
CONFIG_VSOCKETS_LOOPBACK=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WIRELESS_HOTKEY is not set
# CONFIG_WMI_BMOF is not set
# CONFIG_X86_5LEVEL is not set
CONFIG_X86_64=y
CONFIG_X86_64_SMP=y
CONFIG_X86_ACPI_CPUFREQ=y
# CONFIG_X86_ACPI_CPUFREQ_CPB is not set
CONFIG_X86_AMD_FREQ_SENSITIVITY=y
CONFIG_X86_AMD_PLATFORM_DEVICE=y
CONFIG_X86_AMD_PSTATE=y
# CONFIG_X86_AMD_PSTATE_UT is not set
CONFIG_X86_CPUID=y
CONFIG_X86_DIRECT_GBPAGES=y
CONFIG_X86_HV_CALLBACK_VECTOR=y
CONFIG_X86_INTEL_LPSS=y
# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set
CONFIG_X86_INTEL_PSTATE=y
# CONFIG_X86_KERNEL_IBT is not set
CONFIG_X86_MINIMUM_CPU_FAMILY=64
# CONFIG_X86_PCC_CPUFREQ is not set
CONFIG_X86_PKG_TEMP_THERMAL=y
# CONFIG_X86_PMEM_LEGACY is not set
CONFIG_X86_PM_TIMER=y
# CONFIG_X86_POWERNOW_K8 is not set
# CONFIG_X86_VSYSCALL_EMULATION is not set
CONFIG_X86_X2APIC=y
# CONFIG_X86_X32 is not set
# CONFIG_X86_X32_ABI is not set
CONFIG_XEN=y
CONFIG_XENFS=y
CONFIG_XEN_512GB=y
CONFIG_XEN_ACPI=y
CONFIG_XEN_ACPI_PROCESSOR=y
CONFIG_XEN_AUTO_XLATE=y
# CONFIG_XEN_BACKEND is not set
CONFIG_XEN_BALLOON=y
CONFIG_XEN_BLKDEV_FRONTEND=y
CONFIG_XEN_COMPAT_XENFS=y
CONFIG_XEN_DEBUG_FS=y
CONFIG_XEN_DEV_EVTCHN=y
CONFIG_XEN_DOM0=y
CONFIG_XEN_EFI=y
CONFIG_XEN_FBDEV_FRONTEND=y
CONFIG_XEN_GNTDEV=y
CONFIG_XEN_GRANT_DEV_ALLOC=y
CONFIG_XEN_HAVE_PVMMU=y
CONFIG_XEN_HAVE_VPMU=y
# CONFIG_XEN_MCE_LOG is not set
CONFIG_XEN_NETDEV_FRONTEND=y
CONFIG_XEN_PCIDEV_FRONTEND=y
CONFIG_XEN_PRIVCMD=y
CONFIG_XEN_PV=y
CONFIG_XEN_PVH=y
CONFIG_XEN_PVHVM=y
CONFIG_XEN_PVHVM_GUEST=y
CONFIG_XEN_PVHVM_SMP=y
CONFIG_XEN_PV_DOM0=y
CONFIG_XEN_PV_MSR_SAFE=y
CONFIG_XEN_PV_SMP=y
CONFIG_XEN_SAVE_RESTORE=y
CONFIG_XEN_SCSI_FRONTEND=y
CONFIG_XEN_SYMS=y
CONFIG_XEN_SYS_HYPERVISOR=y
CONFIG_XEN_VIRTIO=y
# CONFIG_XEN_VIRTIO_FORCE_GRANT is not set
CONFIG_XEN_WDT=y
CONFIG_XEN_XENBUS_FRONTEND=y
# CONFIG_XIAOMI_WMI is not set
CONFIG_XPS=y
# CONFIG_YOGABOOK_WMI is not set
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZONE_DMA32=y

1
target/linux/x86/Makefile
View File

@ -11,6 +11,7 @@ FEATURES:=squashfs ext4 vdi vmdk vhdx pcmcia targz fpu boot-part rootfs-part
SUBTARGETS:=64 generic legacy geode
KERNEL_PATCHVER:=5.15
KERNEL_TESTING_PATCHVER:=6.1
KERNELNAME:=bzImage

460
target/linux/x86/config-6.1 Normal file
View File

@ -0,0 +1,460 @@
# CONFIG_60XX_WDT is not set
# CONFIG_64BIT is not set
# CONFIG_ACPI is not set
# CONFIG_ACQUIRE_WDT is not set
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ALIM1535_WDT is not set
# CONFIG_ALIX is not set
CONFIG_AMD_NB=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_CLOCKSOURCE_INIT=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_ARCH_NR_GPIO=512
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPLIT_ARG64=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USES_PG_UNCACHED=y
CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ATA=y
CONFIG_ATA_GENERIC=y
CONFIG_ATA_PIIX=y
# CONFIG_BARCO_P50_GPIO is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOUNCE=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CLKBLD_I8253=y
CONFIG_CLKEVT_I8253=y
CONFIG_CLKSRC_I8253=y
CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
CONFIG_CLOCKSOURCE_WATCHDOG=y
CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32=y
CONFIG_COMPAT_32BIT_TIME=y
# CONFIG_COMPAT_VDSO is not set
CONFIG_CONSOLE_TRANSLATIONS=y
# CONFIG_CPU5_WDT is not set
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_SUP_AMD=y
CONFIG_CPU_SUP_CENTAUR=y
CONFIG_CPU_SUP_CYRIX_32=y
CONFIG_CPU_SUP_HYGON=y
CONFIG_CPU_SUP_INTEL=y
CONFIG_CPU_SUP_TRANSMETA_32=y
CONFIG_CPU_SUP_UMC_32=y
CONFIG_CPU_SUP_VORTEX_32=y
CONFIG_CPU_SUP_ZHAOXIN=y
CONFIG_CRASH_CORE=y
CONFIG_CRC16=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRC32_PCLMUL is not set
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_RNG2=y
# CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
# CONFIG_CX_ECAT is not set
CONFIG_DCACHE_WORD_ACCESS=y
# CONFIG_DEBUG_BOOT_PARAMS is not set
# CONFIG_DEBUG_ENTRY is not set
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DEBUG_MISC=y
# CONFIG_DEBUG_NMI_SELFTEST is not set
# CONFIG_DEBUG_TLBFLUSH is not set
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DMADEVICES=y
CONFIG_DMI=y
CONFIG_DMIID=y
CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
CONFIG_DMI_SYSFS=y
CONFIG_DNOTIFY=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_DYNAMIC_SIGFRAME=y
CONFIG_EARLY_PRINTK=y
# CONFIG_EARLY_PRINTK_DBGP is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
# CONFIG_EDD is not set
# CONFIG_EISA is not set
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EXAR_WDT is not set
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXT4_FS=y
CONFIG_F2FS_FS=y
# CONFIG_F71808E_WDT is not set
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FUSION=y
# CONFIG_FUSION_CTL is not set
# CONFIG_FUSION_LOGGING is not set
CONFIG_FUSION_MAX_SGE=128
CONFIG_FUSION_SPI=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
# CONFIG_GDS_FORCE_MITIGATION is not set
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_ENTRY=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
# CONFIG_GEOS is not set
CONFIG_GLOB=y
CONFIG_GPIO_CDEV=y
# CONFIG_HANGCHECK_TIMER is not set
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HID=y
CONFIG_HIGHMEM=y
CONFIG_HIGHMEM4G=y
# CONFIG_HIGHMEM64G is not set
CONFIG_HIGHPTE=y
CONFIG_HPET_EMULATE_RTC=y
CONFIG_HPET_TIMER=y
CONFIG_HW_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_GEODE=y
CONFIG_HW_RANDOM_VIA=y
# CONFIG_HYPERVISOR_GUEST is not set
CONFIG_HZ_PERIODIC=y
CONFIG_I8253_LOCK=y
CONFIG_IA32_FEAT_CTL=y
# CONFIG_IB700_WDT is not set
# CONFIG_IBMASR is not set
# CONFIG_IBM_RTL is not set
# CONFIG_IE6XX_WDT is not set
CONFIG_ILLEGAL_POINTER_VALUE=0
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INPUT=y
CONFIG_INPUT_KEYBOARD=y
CONFIG_INPUT_VIVALDIFMAP=y
CONFIG_INSTRUCTION_DECODER=y
# CONFIG_INTEL_HFI_THERMAL is not set
# CONFIG_INTEL_LDMA is not set
# CONFIG_INTEL_PCH_THERMAL is not set
# CONFIG_INTEL_POWERCLAMP is not set
# CONFIG_INTEL_SCU_PCI is not set
# CONFIG_INTEL_TCC_COOLING is not set
# CONFIG_INTEL_VSEC is not set
# CONFIG_IOSF_MBI is not set
CONFIG_IO_DELAY_0X80=y
# CONFIG_IO_DELAY_0XED is not set
# CONFIG_IO_DELAY_NONE is not set
# CONFIG_IO_DELAY_UDELAY is not set
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_ISA is not set
CONFIG_ISA_DMA_API=y
# CONFIG_IT8712F_WDT is not set
# CONFIG_IT87_WDT is not set
# CONFIG_ITCO_WDT is not set
CONFIG_JBD2=y
CONFIG_KALLSYMS=y
CONFIG_KEXEC=y
CONFIG_KEXEC_CORE=y
CONFIG_KEYBOARD_ATKBD=y
CONFIG_KMAP_LOCAL=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_M486 is not set
# CONFIG_M486SX is not set
# CONFIG_M586 is not set
# CONFIG_M586MMX is not set
# CONFIG_M586TSC is not set
CONFIG_M686=y
# CONFIG_MACHZ_WDT is not set
# CONFIG_MATOM is not set
# CONFIG_MCORE2 is not set
# CONFIG_MCRUSOE is not set
# CONFIG_MCYRIXIII is not set
# CONFIG_MEFFICEON is not set
# CONFIG_MELAN is not set
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_INTEL_LPSS_PCI is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MICROCODE=y
CONFIG_MICROCODE_AMD=y
CONFIG_MICROCODE_INTEL=y
CONFIG_MICROCODE_LATE_LOADING=y
CONFIG_MIGRATION=y
# CONFIG_MK6 is not set
# CONFIG_MK7 is not set
# CONFIG_MK8 is not set
CONFIG_MMU_GATHER_MERGE_VMAS=y
# CONFIG_MODIFY_LDT_SYSCALL is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_MODULES_USE_ELF_REL=y
# CONFIG_MPENTIUM4 is not set
# CONFIG_MPENTIUMII is not set
# CONFIG_MPENTIUMIII is not set
# CONFIG_MPENTIUMM is not set
# CONFIG_MTD is not set
CONFIG_MTRR=y
# CONFIG_MTRR_SANITIZER is not set
# CONFIG_MVIAC3_2 is not set
# CONFIG_MVIAC7 is not set
# CONFIG_MWINCHIP3D is not set
# CONFIG_MWINCHIPC6 is not set
CONFIG_NAMESPACES=y
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
CONFIG_NEED_SG_DMA_LENGTH=y
# CONFIG_NET5501 is not set
# CONFIG_NET_NS is not set
CONFIG_NLS=y
# CONFIG_NOHIGHMEM is not set
CONFIG_NR_CPUS=1
CONFIG_NR_CPUS_DEFAULT=1
CONFIG_NR_CPUS_RANGE_BEGIN=1
CONFIG_NR_CPUS_RANGE_END=1
# CONFIG_NSC_GPIO is not set
CONFIG_NVRAM=y
# CONFIG_OF is not set
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
# CONFIG_OLPC is not set
CONFIG_OUTPUT_FORMAT="elf32-i386"
# CONFIG_P2SB is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PC104=y
# CONFIG_PC8736x_GPIO is not set
# CONFIG_PC87413_WDT is not set
# CONFIG_PCENGINES_APU2 is not set
CONFIG_PCI=y
CONFIG_PCI_ATS=y
CONFIG_PCI_BIOS=y
CONFIG_PCI_DIRECT=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_GOANY=y
# CONFIG_PCI_GOBIOS is not set
# CONFIG_PCI_GODIRECT is not set
# CONFIG_PCI_GOMMCONFIG is not set
CONFIG_PCI_IOV=y
CONFIG_PCI_LABEL=y
CONFIG_PCI_LOCKLESS_CONFIG=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCSPKR_PLATFORM=y
CONFIG_PERF_EVENTS=y
# CONFIG_PERF_EVENTS_AMD_BRS is not set
# CONFIG_PERF_EVENTS_AMD_UNCORE is not set
CONFIG_PERF_EVENTS_INTEL_CSTATE=y
CONFIG_PERF_EVENTS_INTEL_RAPL=y
CONFIG_PERF_EVENTS_INTEL_UNCORE=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYSICAL_ALIGN=0x100000
CONFIG_PHYSICAL_START=0x1000000
# CONFIG_PHY_INTEL_LGM_EMMC is not set
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POWER_SUPPLY=y
CONFIG_PREEMPT_NONE_BUILD=y
# CONFIG_PROCESSOR_SELECT is not set
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_PID_ARCH_STATUS=y
# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
# CONFIG_PUNIT_ATOM_DEBUG is not set
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
CONFIG_RD_BZIP2=y
CONFIG_RD_GZIP=y
CONFIG_RETHUNK=y
CONFIG_RETPOLINE=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_SATA_HOST=y
# CONFIG_SBC7240_WDT is not set
# CONFIG_SBC8360_WDT is not set
# CONFIG_SBC_EPX_C3_WATCHDOG is not set
# CONFIG_SC1200_WDT is not set
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
CONFIG_SCSI_SPI_ATTRS=y
CONFIG_SCx200=y
CONFIG_SCx200HR_TIMER=y
# CONFIG_SCx200_GPIO is not set
# CONFIG_SCx200_WDT is not set
CONFIG_SERIAL_8250_PCI=y
# CONFIG_SERIAL_LANTIQ is not set
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_SERPORT=y
CONFIG_SG_POOL=y
# CONFIG_SIEMENS_SIMATIC_IPC is not set
# CONFIG_SMSC37B787_WDT is not set
# CONFIG_SMSC_SCH311X_WDT is not set
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPECULATION_MITIGATIONS=y
CONFIG_SRCU=y
# CONFIG_STATIC_CALL_SELFTEST is not set
# CONFIG_STRICT_SIGALTSTACK_SIZE is not set
CONFIG_SYSCTL_EXCEPTION_TRACE=y
# CONFIG_SYSFB_SIMPLEFB is not set
# CONFIG_TELCLOCK is not set
# CONFIG_TEST_FPU is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TINY_SRCU=y
# CONFIG_TOSHIBA is not set
# CONFIG_TQMX86_WDT is not set
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_UNWINDER_FRAME_POINTER=y
# CONFIG_UNWINDER_GUESS is not set
CONFIG_UP_LATE_INIT=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_HID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=y
# CONFIG_USB_OHCI_HCD_PLATFORM is not set
CONFIG_USB_PCI=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_UHCI_HCD=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
# CONFIG_USB_XHCI_PLATFORM is not set
# CONFIG_USER_NS is not set
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_VGA_CONSOLE=y
# CONFIG_VIA_WDT is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
# CONFIG_WAFER_WDT is not set
# CONFIG_WINMATE_FM07_KEYS is not set
CONFIG_X86=y
CONFIG_X86_32=y
# CONFIG_X86_32_IRIS is not set
# CONFIG_X86_ANCIENT_MCE is not set
# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set
CONFIG_X86_CMOV=y
CONFIG_X86_CMPXCHG64=y
# CONFIG_X86_CPA_STATISTICS is not set
# CONFIG_X86_CPUFREQ_NFORCE2 is not set
# CONFIG_X86_CPUID is not set
# CONFIG_X86_CPU_RESCTRL is not set
CONFIG_X86_DEBUGCTLMSR=y
# CONFIG_X86_DEBUG_FPU is not set
# CONFIG_X86_DECODER_SELFTEST is not set
# CONFIG_X86_EXTENDED_PLATFORM is not set
CONFIG_X86_FEATURE_NAMES=y
CONFIG_X86_GENERIC=y
# CONFIG_X86_GX_SUSPMOD is not set
# CONFIG_X86_INTEL_PSTATE is not set
# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set
CONFIG_X86_INTEL_TSX_MODE_OFF=y
# CONFIG_X86_INTEL_TSX_MODE_ON is not set
CONFIG_X86_INTEL_USERCOPY=y
CONFIG_X86_INTERNODE_CACHE_SHIFT=6
CONFIG_X86_IOPL_IOPERM=y
CONFIG_X86_IO_APIC=y
CONFIG_X86_L1_CACHE_SHIFT=6
# CONFIG_X86_LEGACY_VM86 is not set
CONFIG_X86_LOCAL_APIC=y
# CONFIG_X86_LONGRUN is not set
CONFIG_X86_MCE=y
# CONFIG_X86_MCELOG_LEGACY is not set
CONFIG_X86_MCE_AMD=y
# CONFIG_X86_MCE_INJECT is not set
CONFIG_X86_MCE_INTEL=y
CONFIG_X86_MCE_THRESHOLD=y
CONFIG_X86_MINIMUM_CPU_FAMILY=6
CONFIG_X86_MPPARSE=y
CONFIG_X86_MSR=y
# CONFIG_X86_P4_CLOCKMOD is not set
CONFIG_X86_PAT=y
CONFIG_X86_PLATFORM_DEVICES=y
# CONFIG_X86_PLATFORM_DRIVERS_DELL is not set
# CONFIG_X86_PLATFORM_DRIVERS_HP is not set
# CONFIG_X86_POWERNOW_K6 is not set
# CONFIG_X86_POWERNOW_K7 is not set
# CONFIG_X86_REBOOTFIXUPS is not set
CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
# CONFIG_X86_SPEEDSTEP_ICH is not set
# CONFIG_X86_SPEEDSTEP_SMI is not set
CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
CONFIG_X86_THERMAL_VECTOR=y
CONFIG_X86_TSC=y
CONFIG_X86_UMIP=y
CONFIG_X86_UP_APIC=y
CONFIG_X86_UP_IOAPIC=y
CONFIG_X86_USE_PPRO_CHECKSUM=y
CONFIG_X86_VERBOSE_BOOTUP=y
CONFIG_X86_VMX_FEATURE_NAMES=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_XZ_DEC_X86=y
CONFIG_ZLIB_INFLATE=y

509
target/linux/x86/generic/config-6.1 Normal file
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@ -0,0 +1,509 @@
# CONFIG_3C515 is not set
# CONFIG_ACER_WMI is not set
CONFIG_ACPI=y
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
# CONFIG_ACPI_BGRT is not set
CONFIG_ACPI_BUTTON=y
# CONFIG_ACPI_CMPC is not set
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_CPU_FREQ_PSS=y
# CONFIG_ACPI_DEBUG is not set
# CONFIG_ACPI_DEBUGGER is not set
# CONFIG_ACPI_DOCK is not set
# CONFIG_ACPI_DPTF is not set
# CONFIG_ACPI_EC_DEBUGFS is not set
# CONFIG_ACPI_FAN is not set
CONFIG_ACPI_HOTPLUG_CPU=y
CONFIG_ACPI_HOTPLUG_IOAPIC=y
# CONFIG_ACPI_I2C_OPREGION is not set
CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
# CONFIG_ACPI_PCI_SLOT is not set
CONFIG_ACPI_PROCESSOR=y
# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
CONFIG_ACPI_PROCESSOR_CSTATE=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
# CONFIG_ACPI_SBS is not set
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
CONFIG_ACPI_TAD=y
CONFIG_ACPI_THERMAL=y
# CONFIG_ACPI_TOSHIBA is not set
CONFIG_ACPI_VIDEO=y
# CONFIG_ACPI_WMI is not set
# CONFIG_ADV_SWBUTTON is not set
CONFIG_AGP=y
# CONFIG_AGP_ALI is not set
# CONFIG_AGP_AMD is not set
# CONFIG_AGP_AMD64 is not set
# CONFIG_AGP_ATI is not set
# CONFIG_AGP_EFFICEON is not set
CONFIG_AGP_INTEL=y
# CONFIG_AGP_NVIDIA is not set
# CONFIG_AGP_SIS is not set
# CONFIG_AGP_SWORKS is not set
# CONFIG_AGP_VIA is not set
# CONFIG_AMD_PMC is not set
# CONFIG_AMD_PMF is not set
# CONFIG_APM is not set
CONFIG_ARCH_CPUIDLE_HALTPOLL=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
# CONFIG_ASUS_TF103C_DOCK is not set
# CONFIG_ASUS_WMI is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_BLK_DEV_SR=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
CONFIG_BTT=y
CONFIG_CDROM=y
CONFIG_CONNECTOR=y
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_RMAP=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
# CONFIG_CS89x0_ISA is not set
# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
CONFIG_DMA_ACPI=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DRM=y
CONFIG_DRM_BOCHS=y
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
CONFIG_DRM_GEM_SHMEM_HELPER=y
# CONFIG_DRM_HYPERV is not set
CONFIG_DRM_I915=y
CONFIG_DRM_I915_CAPTURE_ERROR=y
CONFIG_DRM_I915_COMPRESS_ERROR=y
# CONFIG_DRM_I915_DEBUG is not set
# CONFIG_DRM_I915_DEBUG_GUC is not set
# CONFIG_DRM_I915_DEBUG_MMIO is not set
# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
CONFIG_DRM_I915_FENCE_TIMEOUT=10000
CONFIG_DRM_I915_FORCE_PROBE=""
CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
# CONFIG_DRM_I915_SELFTEST is not set
CONFIG_DRM_I915_STOP_TIMEOUT=100
# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
CONFIG_DRM_I915_TIMESLICE_DURATION=1
CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
CONFIG_DRM_I915_USERPTR=y
# CONFIG_DRM_I915_WERROR is not set
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_PANEL=y
CONFIG_DRM_PANEL_BRIDGE=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_TTM=y
CONFIG_DRM_TTM_HELPER=y
CONFIG_DRM_VIRTIO_GPU=y
CONFIG_DRM_VRAM_HELPER=y
CONFIG_EFI=y
CONFIG_EFIVAR_FS=m
# CONFIG_EFI_BOOTLOADER_CONTROL is not set
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH is not set
# CONFIG_EFI_COCO_SECRET is not set
# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
# CONFIG_EFI_DISABLE_RUNTIME is not set
CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_ESRT=y
# CONFIG_EFI_FAKE_MEMMAP is not set
CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
# CONFIG_EFI_PGT_DUMP is not set
# CONFIG_EFI_RCI2_TABLE is not set
CONFIG_EFI_RUNTIME_MAP=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_STUB=y
# CONFIG_EFI_TEST is not set
# CONFIG_EFI_VARS is not set
# CONFIG_EL3 is not set
CONFIG_FAILOVER=y
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_EFI=y
CONFIG_FB_HYPERV=y
# CONFIG_FB_I810 is not set
CONFIG_FB_SIMPLE=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_VESA is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_FONT_SUPPORT=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FREEZER=y
CONFIG_FW_CACHE=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_PENDING_IRQ=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_GIGABYTE_WMI is not set
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIO_CDEV=y
CONFIG_GUP_GET_PTE_LOW_HIGH=y
CONFIG_HALTPOLL_CPUIDLE=y
CONFIG_HDMI=y
CONFIG_HIBERNATE_CALLBACKS=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HID_GENERIC=y
CONFIG_HID_HYPERV_MOUSE=y
# CONFIG_HIGHMEM4G is not set
CONFIG_HIGHMEM64G=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_ACPI=y
# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
# CONFIG_HOTPLUG_PCI_COMPAQ is not set
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_IBM is not set
CONFIG_HOTPLUG_PCI_PCIE=y
# CONFIG_HOTPLUG_PCI_SHPC is not set
CONFIG_HOTPLUG_SMT=y
CONFIG_HPET=y
CONFIG_HPET_MMAP=y
# CONFIG_HP_ACCEL is not set
# CONFIG_HUAWEI_WMI is not set
CONFIG_HVC_DRIVER=y
CONFIG_HVC_IRQ=y
CONFIG_HVC_XEN=y
CONFIG_HVC_XEN_FRONTEND=y
CONFIG_HWMON=y
CONFIG_HWMON_VID=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_HYPERV=y
CONFIG_HYPERVISOR_GUEST=y
CONFIG_HYPERV_BALLOON=y
CONFIG_HYPERV_KEYBOARD=y
CONFIG_HYPERV_NET=y
CONFIG_HYPERV_STORAGE=y
# CONFIG_HYPERV_TESTING is not set
CONFIG_HYPERV_TIMER=y
CONFIG_HYPERV_UTILS=y
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_AMD_MP2 is not set
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_HID_ACPI is not set
# CONFIG_I2C_MULTI_INSTANTIATE is not set
# CONFIG_I8K is not set
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
CONFIG_INPUT_MOUSE=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
CONFIG_INTEL_GTT=y
CONFIG_INTEL_IDLE=y
# CONFIG_INTEL_IPS is not set
# CONFIG_INTEL_MEI_HDCP is not set
# CONFIG_INTEL_MEI_PXP is not set
# CONFIG_INTEL_MENLOW is not set
CONFIG_INTEL_PCH_THERMAL=y
# CONFIG_INTEL_SAR_INT1092 is not set
# CONFIG_INTEL_SCU_PLATFORM is not set
CONFIG_INTEL_SOC_DTS_IOSF_CORE=y
CONFIG_INTEL_SOC_DTS_THERMAL=y
# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
# CONFIG_INTEL_WMI_THUNDERBOLT is not set
CONFIG_INTERVAL_TREE=y
CONFIG_IOSF_MBI=y
# CONFIG_IOSF_MBI_DEBUG is not set
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_ISA=y
CONFIG_ISAPNP=y
CONFIG_ISA_BUS_API=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_ISO9660_FS=y
# CONFIG_JOLIET is not set
CONFIG_KCMP=y
CONFIG_KVM=y
CONFIG_KVM_AMD=y
CONFIG_KVM_ASYNC_PF=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_KVM_GUEST=y
CONFIG_KVM_INTEL=y
CONFIG_KVM_MMIO=y
CONFIG_KVM_VFIO=y
# CONFIG_KVM_XEN is not set
CONFIG_KVM_XFER_TO_GUEST_WORK=y
# CONFIG_LANCE is not set
# CONFIG_LG_LAPTOP is not set
CONFIG_LIBNVDIMM=y
CONFIG_LOCK_SPIN_ON_OWNER=y
# CONFIG_M686 is not set
# CONFIG_MDA_CONSOLE is not set
CONFIG_MEMORY_BALLOON=y
CONFIG_MEMREGION=y
CONFIG_MFD_CORE=y
CONFIG_MFD_INTEL_LPSS=y
CONFIG_MFD_INTEL_LPSS_ACPI=y
# CONFIG_MFD_INTEL_PMC_BXT is not set
# CONFIG_MIXCOMWD is not set
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PCI=y
# CONFIG_MMC_SDHCI_PLTFM is not set
# CONFIG_MMC_WBSD is not set
CONFIG_MMU_NOTIFIER=y
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_CYAPA is not set
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
# CONFIG_MOUSE_PS2_BYD is not set
# CONFIG_MOUSE_PS2_CYPRESS is not set
# CONFIG_MOUSE_PS2_ELANTECH is not set
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_VMMOUSE is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_VSXXXAA is not set
CONFIG_MPENTIUM4=y
# CONFIG_MSI_WMI is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
# CONFIG_MXM_WMI is not set
CONFIG_ND_BLK=y
CONFIG_ND_BTT=y
CONFIG_ND_CLAIM=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NET_FAILOVER=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NO_HZ=y
CONFIG_NR_CPUS=4
CONFIG_NR_CPUS_DEFAULT=8
CONFIG_NR_CPUS_RANGE_BEGIN=2
CONFIG_NR_CPUS_RANGE_END=8
# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
CONFIG_PADATA=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_REPORTING=y
CONFIG_PAGE_TABLE_ISOLATION=y
CONFIG_PARAVIRT=y
CONFIG_PARAVIRT_CLOCK=y
# CONFIG_PARAVIRT_DEBUG is not set
CONFIG_PARAVIRT_SPINLOCKS=y
CONFIG_PATA_AMD=y
CONFIG_PATA_ATIIXP=y
CONFIG_PATA_MPIIX=y
CONFIG_PATA_OLDPIIX=y
CONFIG_PATA_PLATFORM=y
CONFIG_PATA_SC1200=y
CONFIG_PATA_TIMINGS=y
CONFIG_PATA_VIA=y
# CONFIG_PCENGINES_APU2 is not set
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_PME=y
CONFIG_PCI_MMCONFIG=y
CONFIG_PCI_XEN=y
# CONFIG_PCWATCHDOG is not set
# CONFIG_PEAQ_WMI is not set
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ALDERLAKE=y
CONFIG_PINCTRL_BAYTRAIL=y
CONFIG_PINCTRL_BROXTON=y
CONFIG_PINCTRL_CANNONLAKE=y
CONFIG_PINCTRL_CHERRYVIEW=y
CONFIG_PINCTRL_DENVERTON=y
CONFIG_PINCTRL_ELKHARTLAKE=y
CONFIG_PINCTRL_EMMITSBURG=y
CONFIG_PINCTRL_GEMINILAKE=y
CONFIG_PINCTRL_INTEL=y
CONFIG_PINCTRL_JASPERLAKE=y
CONFIG_PINCTRL_LAKEFIELD=y
CONFIG_PINCTRL_LEWISBURG=y
CONFIG_PINCTRL_LYNXPOINT=y
CONFIG_PINCTRL_METEORLAKE=y
CONFIG_PINCTRL_SUNRISEPOINT=y
CONFIG_PINCTRL_TIGERLAKE=y
CONFIG_PM=y
# CONFIG_PMIC_OPREGION is not set
CONFIG_PM_CLK=y
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
CONFIG_PNP=y
CONFIG_PNPACPI=y
# CONFIG_PNPBIOS is not set
CONFIG_PNP_DEBUG_MESSAGES=y
CONFIG_PPS=y
CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PROC_EVENTS=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_KVM=y
CONFIG_PTP_1588_CLOCK_VMW=y
CONFIG_PVH=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RAS=y
CONFIG_RELAY=y
CONFIG_RELOCATABLE=y
CONFIG_RESET_ATTACK_MITIGATION=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SAMSUNG_Q10 is not set
CONFIG_SATA_AHCI=y
CONFIG_SATA_VIA=y
# CONFIG_SCHED_CORE is not set
CONFIG_SCHED_INFO=y
CONFIG_SCHED_SMT=y
# CONFIG_SCSI_FDOMAIN_ISA is not set
CONFIG_SCSI_VIRTIO=y
# CONFIG_SENSORS_ASUS_EC is not set
# CONFIG_SENSORS_ASUS_WMI is not set
CONFIG_SENSORS_CORETEMP=y
CONFIG_SENSORS_FAM15H_POWER=y
CONFIG_SENSORS_I5500=y
CONFIG_SENSORS_K8TEMP=y
CONFIG_SENSORS_K10TEMP=y
CONFIG_SENSORS_VIA_CPUTEMP=y
CONFIG_SERIAL_8250_PNP=y
CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
CONFIG_SMP=y
# CONFIG_SND_HDA_CTL_DEV_ID is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
# CONFIG_SND_SOC_AMD_ACP6x is not set
# CONFIG_SND_SOC_AMD_ACP_COMMON is not set
# CONFIG_SND_SOC_AMD_PS is not set
# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set
# CONFIG_SND_SOC_INTEL_AVS is not set
CONFIG_SOCK_RX_QUEUE_MAPPING=y
# CONFIG_SURFACE_PLATFORMS is not set
CONFIG_SWIOTLB=y
CONFIG_SYNC_FILE=y
# CONFIG_SYSTEM76_ACPI is not set
CONFIG_SYS_HYPERVISOR=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
# CONFIG_THINKPAD_LMI is not set
# CONFIG_TOSHIBA_BT_RFKILL is not set
# CONFIG_TOSHIBA_WMI is not set
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
# CONFIG_UCLAMP_TASK is not set
CONFIG_UCS2_STRING=y
CONFIG_USB_STORAGE=y
CONFIG_USER_RETURN_NOTIFIER=y
CONFIG_VHOST=y
CONFIG_VHOST_IOTLB=y
CONFIG_VHOST_NET=y
# CONFIG_VIDEO_IPU3_CIO2 is not set
CONFIG_VIRTIO=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_BLK=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_PCI_LIB=y
# CONFIG_VIRTIO_PMEM is not set
CONFIG_VIRTUALIZATION=y
CONFIG_VMAP_PFN=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WDT is not set
# CONFIG_WIRELESS_HOTKEY is not set
# CONFIG_WMI_BMOF is not set
CONFIG_X86_32_SMP=y
CONFIG_X86_ACPI_CPUFREQ=y
# CONFIG_X86_ACPI_CPUFREQ_CPB is not set
CONFIG_X86_AMD_FREQ_SENSITIVITY=y
CONFIG_X86_AMD_PLATFORM_DEVICE=y
CONFIG_X86_AMD_PSTATE=y
# CONFIG_X86_AMD_PSTATE_UT is not set
# CONFIG_X86_BIGSMP is not set
CONFIG_X86_CPUID=y
# CONFIG_X86_E_POWERSAVER is not set
CONFIG_X86_HV_CALLBACK_VECTOR=y
CONFIG_X86_INTEL_LPSS=y
CONFIG_X86_INTEL_PSTATE=y
CONFIG_X86_INTERNODE_CACHE_SHIFT=7
CONFIG_X86_L1_CACHE_SHIFT=7
# CONFIG_X86_LONGHAUL is not set
CONFIG_X86_NEED_RELOCS=y
CONFIG_X86_PAE=y
# CONFIG_X86_PCC_CPUFREQ is not set
CONFIG_X86_PKG_TEMP_THERMAL=y
# CONFIG_X86_PMEM_LEGACY is not set
CONFIG_X86_PM_TIMER=y
# CONFIG_X86_POWERNOW_K8 is not set
CONFIG_XEN=y
CONFIG_XENFS=y
CONFIG_XEN_ACPI=y
CONFIG_XEN_AUTO_XLATE=y
# CONFIG_XEN_BACKEND is not set
CONFIG_XEN_BALLOON=y
CONFIG_XEN_BLKDEV_FRONTEND=y
CONFIG_XEN_COMPAT_XENFS=y
CONFIG_XEN_DEBUG_FS=y
CONFIG_XEN_DEV_EVTCHN=y
CONFIG_XEN_FBDEV_FRONTEND=y
CONFIG_XEN_GNTDEV=y
CONFIG_XEN_GRANT_DEV_ALLOC=y
CONFIG_XEN_NETDEV_FRONTEND=y
CONFIG_XEN_PRIVCMD=y
CONFIG_XEN_PVH=y
CONFIG_XEN_PVHVM=y
CONFIG_XEN_PVHVM_GUEST=y
CONFIG_XEN_PVHVM_SMP=y
CONFIG_XEN_SAVE_RESTORE=y
CONFIG_XEN_SCSI_FRONTEND=y
CONFIG_XEN_SYS_HYPERVISOR=y
CONFIG_XEN_VIRTIO=y
# CONFIG_XEN_VIRTIO_FORCE_GRANT is not set
CONFIG_XEN_WDT=y
CONFIG_XEN_XENBUS_FRONTEND=y
# CONFIG_XIAOMI_WMI is not set
CONFIG_XPS=y
# CONFIG_YOGABOOK_WMI is not set
CONFIG_ZLIB_DEFLATE=y

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# CONFIG_3C515 is not set
CONFIG_8139CP=y
CONFIG_8139TOO=y
CONFIG_8139TOO_8129=y
CONFIG_8139TOO_PIO=y
# CONFIG_8139TOO_TUNE_TWISTER is not set
# CONFIG_8139_OLD_RX_RESET is not set
# CONFIG_ACER_WMI is not set
CONFIG_ACPI=y
CONFIG_ACPI_AC=y
# CONFIG_ACPI_BATTERY is not set
# CONFIG_ACPI_CMPC is not set
# CONFIG_ACPI_CONTAINER is not set
CONFIG_ACPI_CPU_FREQ_PSS=y
# CONFIG_ACPI_DEBUG is not set
# CONFIG_ACPI_DEBUGGER is not set
# CONFIG_ACPI_DOCK is not set
# CONFIG_ACPI_DPTF is not set
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_FAN=y
CONFIG_ACPI_HOTPLUG_IOAPIC=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
# CONFIG_ACPI_PCI_SLOT is not set
CONFIG_ACPI_PROCESSOR=y
# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
CONFIG_ACPI_PROCESSOR_CSTATE=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
# CONFIG_ACPI_SBS is not set
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
CONFIG_ACPI_THERMAL=y
# CONFIG_ACPI_TINY_POWER_BUTTON is not set
# CONFIG_ACPI_WMI is not set
# CONFIG_ADV_SWBUTTON is not set
CONFIG_ALIX=y
# CONFIG_AMD_PMC is not set
# CONFIG_AMD_PMF is not set
CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
# CONFIG_ASUS_TF103C_DOCK is not set
# CONFIG_ATA_PIIX is not set
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CS5535_CLOCK_EVENT_SRC=y
CONFIG_CS5535_MFGPT=y
CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7
# CONFIG_CS89x0_ISA is not set
CONFIG_DMA_ACPI=y
# CONFIG_EL3 is not set
CONFIG_GEODE_WDT=y
CONFIG_GEOS=y
# CONFIG_GIGABYTE_WMI is not set
CONFIG_GPIO_ACPI=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CS5535=y
# CONFIG_HPET is not set
# CONFIG_HP_ACCEL is not set
CONFIG_HWMON=y
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_ALGOPCA=y
CONFIG_I2C_ALGOPCF=y
# CONFIG_I2C_AMD_MP2 is not set
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_HID_ACPI is not set
# CONFIG_I2C_MULTI_INSTANTIATE is not set
# CONFIG_I8K is not set
# CONFIG_INTEL_IPS is not set
# CONFIG_INTEL_MENLOW is not set
# CONFIG_INTEL_SAR_INT1092 is not set
# CONFIG_INTEL_SCU_PLATFORM is not set
# CONFIG_INTEL_SOC_DTS_THERMAL is not set
# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
# CONFIG_INTEL_WMI_THUNDERBOLT is not set
CONFIG_IOSF_MBI=y
# CONFIG_IOSF_MBI_DEBUG is not set
CONFIG_ISA=y
# CONFIG_ISAPNP is not set
CONFIG_ISA_BUS_API=y
# CONFIG_ISCSI_IBFT is not set
# CONFIG_LANCE is not set
CONFIG_LEDS_GPIO=y
# CONFIG_M686 is not set
# CONFIG_MDA_CONSOLE is not set
CONFIG_MFD_CORE=y
CONFIG_MFD_CS5535=y
# CONFIG_MFD_INTEL_LPSS_ACPI is not set
# CONFIG_MFD_INTEL_PMC_BXT is not set
CONFIG_MGEODEGX1=y
# CONFIG_MIXCOMWD is not set
# CONFIG_MSI_WMI is not set
# CONFIG_MXM_WMI is not set
CONFIG_NATSEMI=y
CONFIG_NET5501=y
CONFIG_NSC_GPIO=y
# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
CONFIG_PATA_CS5520=y
CONFIG_PATA_CS5530=y
CONFIG_PATA_CS5535=y
CONFIG_PATA_CS5536=y
CONFIG_PATA_SC1200=y
CONFIG_PC8736x_GPIO=y
# CONFIG_PCENGINES_APU2 is not set
CONFIG_PCI_MMCONFIG=y
# CONFIG_PCWATCHDOG is not set
# CONFIG_PEAQ_WMI is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_ALDERLAKE is not set
# CONFIG_PINCTRL_BAYTRAIL is not set
# CONFIG_PINCTRL_BROXTON is not set
# CONFIG_PINCTRL_CANNONLAKE is not set
# CONFIG_PINCTRL_CHERRYVIEW is not set
# CONFIG_PINCTRL_DENVERTON is not set
# CONFIG_PINCTRL_ELKHARTLAKE is not set
# CONFIG_PINCTRL_EMMITSBURG is not set
# CONFIG_PINCTRL_GEMINILAKE is not set
# CONFIG_PINCTRL_JASPERLAKE is not set
# CONFIG_PINCTRL_LAKEFIELD is not set
# CONFIG_PINCTRL_LEWISBURG is not set
# CONFIG_PINCTRL_LYNXPOINT is not set
# CONFIG_PINCTRL_METEORLAKE is not set
# CONFIG_PINCTRL_SUNRISEPOINT is not set
# CONFIG_PINCTRL_TIGERLAKE is not set
# CONFIG_PMIC_OPREGION is not set
CONFIG_PNP=y
CONFIG_PNPACPI=y
# CONFIG_PNPBIOS is not set
CONFIG_PNP_DEBUG_MESSAGES=y
CONFIG_RTC_I2C_AND_SPI=y
# CONFIG_SAMSUNG_Q10 is not set
CONFIG_SC1200_WDT=y
# CONFIG_SCSI_FDOMAIN_ISA is not set
CONFIG_SCx200_ACB=y
CONFIG_SCx200_WDT=y
# CONFIG_SENSORS_ASUS_EC is not set
# CONFIG_SENSORS_ASUS_WMI is not set
CONFIG_SENSORS_LM90=y
CONFIG_SERIAL_8250_PNP=y
CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
# CONFIG_SND_HDA_CTL_DEV_ID is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
# CONFIG_SND_SOC_AMD_ACP6x is not set
# CONFIG_SND_SOC_AMD_ACP_COMMON is not set
# CONFIG_SND_SOC_AMD_PS is not set
# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set
# CONFIG_SND_SOC_INTEL_AVS is not set
# CONFIG_SURFACE_PLATFORMS is not set
# CONFIG_SYSTEM76_ACPI is not set
# CONFIG_THINKPAD_LMI is not set
# CONFIG_TOSHIBA_BT_RFKILL is not set
# CONFIG_TOSHIBA_WMI is not set
# CONFIG_USB_UHCI_HCD is not set
CONFIG_VIA_RHINE=y
CONFIG_VIA_RHINE_MMIO=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WDT is not set
# CONFIG_WIRELESS_HOTKEY is not set
# CONFIG_WMI_BMOF is not set
# CONFIG_X86_ACPI_CPUFREQ is not set
CONFIG_X86_ALIGNMENT_16=y
# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
# CONFIG_X86_AMD_PSTATE is not set
# CONFIG_X86_AMD_PSTATE_UT is not set
CONFIG_X86_CPUID=y
# CONFIG_X86_E_POWERSAVER is not set
CONFIG_X86_INTEL_LPSS=y
# CONFIG_X86_LONGHAUL is not set
# CONFIG_X86_MCE is not set
CONFIG_X86_MINIMUM_CPU_FAMILY=5
# CONFIG_X86_PCC_CPUFREQ is not set
CONFIG_X86_PM_TIMER=y
CONFIG_X86_REBOOTFIXUPS=y
# CONFIG_XIAOMI_WMI is not set
# CONFIG_YOGABOOK_WMI is not set

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# CONFIG_3C515 is not set
# CONFIG_ACER_WMI is not set
CONFIG_ACPI=y
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
# CONFIG_ACPI_CMPC is not set
# CONFIG_ACPI_CONTAINER is not set
CONFIG_ACPI_CPU_FREQ_PSS=y
# CONFIG_ACPI_DEBUG is not set
# CONFIG_ACPI_DEBUGGER is not set
# CONFIG_ACPI_DOCK is not set
# CONFIG_ACPI_DPTF is not set
# CONFIG_ACPI_EC_DEBUGFS is not set
# CONFIG_ACPI_FAN is not set
CONFIG_ACPI_HOTPLUG_IOAPIC=y
# CONFIG_ACPI_I2C_OPREGION is not set
CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
# CONFIG_ACPI_PCI_SLOT is not set
CONFIG_ACPI_PROCESSOR=y
# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
CONFIG_ACPI_PROCESSOR_CSTATE=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
# CONFIG_ACPI_SBS is not set
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
CONFIG_ACPI_THERMAL=y
# CONFIG_ACPI_TOSHIBA is not set
CONFIG_ACPI_VIDEO=y
# CONFIG_ACPI_WMI is not set
# CONFIG_ADV_SWBUTTON is not set
CONFIG_AGP=y
# CONFIG_AGP_ALI is not set
# CONFIG_AGP_AMD is not set
# CONFIG_AGP_AMD64 is not set
# CONFIG_AGP_ATI is not set
# CONFIG_AGP_EFFICEON is not set
CONFIG_AGP_INTEL=y
# CONFIG_AGP_NVIDIA is not set
# CONFIG_AGP_SIS is not set
# CONFIG_AGP_SWORKS is not set
# CONFIG_AGP_VIA is not set
# CONFIG_AMD_PMC is not set
# CONFIG_AMD_PMF is not set
CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
# CONFIG_ASUS_TF103C_DOCK is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BLK_DEV_SR=y
CONFIG_CDROM=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
# CONFIG_CS89x0_ISA is not set
CONFIG_DMA_ACPI=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DRM=y
CONFIG_DRM_AMDGPU=y
# CONFIG_DRM_AMD_DC is not set
CONFIG_DRM_BOCHS=y
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
CONFIG_DRM_I915=y
CONFIG_DRM_I915_CAPTURE_ERROR=y
CONFIG_DRM_I915_COMPRESS_ERROR=y
# CONFIG_DRM_I915_DEBUG is not set
# CONFIG_DRM_I915_DEBUG_GUC is not set
# CONFIG_DRM_I915_DEBUG_MMIO is not set
# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
CONFIG_DRM_I915_FENCE_TIMEOUT=10000
CONFIG_DRM_I915_FORCE_PROBE=""
CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
# CONFIG_DRM_I915_SELFTEST is not set
CONFIG_DRM_I915_STOP_TIMEOUT=100
# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
CONFIG_DRM_I915_TIMESLICE_DURATION=1
CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
CONFIG_DRM_I915_USERPTR=y
# CONFIG_DRM_I915_WERROR is not set
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_PANEL=y
CONFIG_DRM_PANEL_BRIDGE=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_RADEON=y
CONFIG_DRM_SCHED=y
CONFIG_DRM_TTM=y
CONFIG_DRM_TTM_HELPER=y
CONFIG_DRM_VRAM_HELPER=y
# CONFIG_EL3 is not set
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_I810 is not set
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_VESA is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_FONT_SUPPORT=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_GIGABYTE_WMI is not set
CONFIG_HDMI=y
CONFIG_HID_BATTERY_STRENGTH=y
# CONFIG_HIGHMEM4G is not set
CONFIG_HPET=y
CONFIG_HPET_MMAP=y
# CONFIG_HP_ACCEL is not set
# CONFIG_HUAWEI_WMI is not set
CONFIG_HWMON=y
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_AMD_MP2 is not set
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_HID_ACPI is not set
# CONFIG_I2C_MULTI_INSTANTIATE is not set
# CONFIG_I8K is not set
CONFIG_INPUT_MOUSE=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INTEL_GTT=y
CONFIG_INTEL_IDLE=y
# CONFIG_INTEL_IPS is not set
# CONFIG_INTEL_MEI_HDCP is not set
# CONFIG_INTEL_MEI_PXP is not set
# CONFIG_INTEL_MENLOW is not set
# CONFIG_INTEL_SAR_INT1092 is not set
# CONFIG_INTEL_SCU_PLATFORM is not set
# CONFIG_INTEL_SOC_DTS_THERMAL is not set
# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
# CONFIG_INTEL_WMI_THUNDERBOLT is not set
CONFIG_INTERVAL_TREE=y
CONFIG_IOSF_MBI=y
# CONFIG_IOSF_MBI_DEBUG is not set
CONFIG_ISA=y
CONFIG_ISAPNP=y
CONFIG_ISA_BUS_API=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_ISO9660_FS=y
# CONFIG_JOLIET is not set
CONFIG_KCMP=y
# CONFIG_LANCE is not set
# CONFIG_LG_LAPTOP is not set
CONFIG_M586MMX=y
# CONFIG_M686 is not set
# CONFIG_MDA_CONSOLE is not set
CONFIG_MFD_CORE=y
CONFIG_MFD_INTEL_LPSS=y
CONFIG_MFD_INTEL_LPSS_ACPI=y
# CONFIG_MFD_INTEL_PMC_BXT is not set
# CONFIG_MIXCOMWD is not set
CONFIG_MMU_NOTIFIER=y
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_CYAPA is not set
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
# CONFIG_MOUSE_PS2_BYD is not set
# CONFIG_MOUSE_PS2_CYPRESS is not set
# CONFIG_MOUSE_PS2_ELANTECH is not set
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MSI_WMI is not set
# CONFIG_MXM_WMI is not set
CONFIG_NOHIGHMEM=y
CONFIG_NO_HZ=y
# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
CONFIG_PATA_AMD=y
CONFIG_PATA_ATIIXP=y
CONFIG_PATA_LEGACY=y
CONFIG_PATA_MPIIX=y
CONFIG_PATA_OLDPIIX=y
CONFIG_PATA_PLATFORM=y
CONFIG_PATA_SC1200=y
CONFIG_PATA_SIS=y
CONFIG_PATA_TIMINGS=y
CONFIG_PATA_VIA=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCI_MMCONFIG=y
# CONFIG_PCWATCHDOG is not set
# CONFIG_PEAQ_WMI is not set
# CONFIG_PMIC_OPREGION is not set
CONFIG_PNP=y
CONFIG_PNPACPI=y
# CONFIG_PNPBIOS is not set
CONFIG_PNP_DEBUG_MESSAGES=y
CONFIG_RAS=y
CONFIG_RELAY=y
CONFIG_RTC_I2C_AND_SPI=y
# CONFIG_SAMSUNG_Q10 is not set
CONFIG_SATA_AHCI=y
# CONFIG_SCSI_FDOMAIN_ISA is not set
# CONFIG_SENSORS_ASUS_EC is not set
# CONFIG_SENSORS_ASUS_WMI is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
# CONFIG_SND_HDA_CTL_DEV_ID is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
# CONFIG_SND_SOC_AMD_ACP6x is not set
# CONFIG_SND_SOC_AMD_ACP_COMMON is not set
# CONFIG_SND_SOC_AMD_PS is not set
# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set
# CONFIG_SND_SOC_INTEL_AVS is not set
# CONFIG_SURFACE_PLATFORMS is not set
CONFIG_SYNC_FILE=y
# CONFIG_SYSTEM76_ACPI is not set
# CONFIG_THINKPAD_LMI is not set
# CONFIG_TOSHIBA_BT_RFKILL is not set
# CONFIG_TOSHIBA_WMI is not set
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_IPU3_CIO2 is not set
CONFIG_VMAP_PFN=y
# CONFIG_WDT is not set
# CONFIG_WIRELESS_HOTKEY is not set
# CONFIG_WMI_BMOF is not set
CONFIG_X86_ACPI_CPUFREQ=y
# CONFIG_X86_ACPI_CPUFREQ_CPB is not set
CONFIG_X86_ALIGNMENT_16=y
# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set
# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
# CONFIG_X86_AMD_PSTATE is not set
# CONFIG_X86_AMD_PSTATE_UT is not set
# CONFIG_X86_E_POWERSAVER is not set
CONFIG_X86_F00F_BUG=y
# CONFIG_X86_INTEL_LPSS is not set
# CONFIG_X86_LONGHAUL is not set
CONFIG_X86_MINIMUM_CPU_FAMILY=5
# CONFIG_X86_PAE is not set
# CONFIG_X86_PCC_CPUFREQ is not set
CONFIG_X86_PM_TIMER=y
# CONFIG_X86_POWERNOW_K8 is not set
# CONFIG_XIAOMI_WMI is not set
# CONFIG_YOGABOOK_WMI is not set
CONFIG_ZLIB_DEFLATE=y

13
target/linux/x86/patches-6.1/100-fix_cs5535_clockevt.patch Normal file
View File

@ -0,0 +1,13 @@
--- a/drivers/clocksource/timer-cs5535.c
+++ b/drivers/clocksource/timer-cs5535.c
@@ -127,7 +127,9 @@ static irqreturn_t mfgpt_tick(int irq, v
cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,
MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
- cs5535_clockevent.event_handler(&cs5535_clockevent);
+ if (cs5535_clockevent.event_handler)
+ cs5535_clockevent.event_handler(&cs5535_clockevent);
+
return IRQ_HANDLED;
}

280
target/linux/x86/patches-6.1/103-pcengines_apu6_platform.patch Normal file
View File

@ -0,0 +1,280 @@
From 970d9af9015a387bb81841faf05dcc1a171eb97a Mon Sep 17 00:00:00 2001
From: Philip Prindeville <philipp@redfish-solutions.com>
Date: Sun, 1 Jan 2023 15:25:04 -0700
Subject: [PATCH v3 1/1] x86: Support APU5 in PCEngines platform driver
To: platform-driver-x86@vger.kernel.org, linux-x86_64@vger.kernel.org
Cc: Ed Wildgoose <lists@wildgooses.com>, Andres Salomon <dilinger@queued.net>, Andreas Eberlein <foodeas@aeberlein.de>, Paul Spooren <paul@spooren.de>
PCEngines make a number of SBC. APU5 has 5 mpcie slots + MSATA.
It also has support for 3x LTE modems with 6x SIM slots (pairs with a
SIM switch device). Each mpcie slot for modems has a reset GPIO
To ensure that the naming is sane between APU2-6 the GPIOS are
renamed to be modem1-reset, modem2-reset, etc. This is significant
because the slots that can be reset change between APU2 and APU3/4
GPIO for simswap is moved to the end of the list as it could be dropped
for APU2 boards (but causes no harm to leave it in, hardware could be
added to a future rev of the board).
Structure of the GPIOs for APU5 is extremely similar to APU2-4, but
many lines are moved around and there are simply more
modems/resets/sim-swap lines to breakout.
Also added APU6, which is essentially APU4 with a different ethernet
interface and SFP cage on eth0.
Revision history:
v1: originally titled, "apu6: add apu6 variation to apu2 driver family"
this dealt only with detecting the APUv6, which is otherwise identical
to the v4 excepting the SFP cage on eth0.
v2: at Ed's request, merged with his previous pull-request titled
"x86: Support APU5 in PCEngines platform driver", and some cleanup
to that changeset (including dropping the table "apu5_driver_data"
which did not have a defined type "struct apu_driver_data"), but got
mistitled when the Subject of that commit got accidentally dropped.
v3: retitled to match Ed's previous pull-request.
Cc: platform-driver-x86@vger.kernel.org
Cc: linux-x86_64@vger.kernel.org
Reviewed-by: Andreas Eberlein <foodeas@aeberlein.de>
Reviewed-by: Paul Spooren <paul@spooren.de>
Signed-off-by: Ed Wildgoose <lists@wildgooses.com>
Sighed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
---
drivers/leds/leds-apu.c | 2 +-
drivers/platform/x86/Kconfig | 4 +-
drivers/platform/x86/pcengines-apuv2.c | 118 ++++++++++++++++++++++---
3 files changed, 107 insertions(+), 17 deletions(-)
--- a/drivers/leds/leds-apu.c
+++ b/drivers/leds/leds-apu.c
@@ -183,7 +183,7 @@ static int __init apu_led_init(void)
if (!(dmi_match(DMI_SYS_VENDOR, "PC Engines") &&
(dmi_match(DMI_PRODUCT_NAME, "APU") || dmi_match(DMI_PRODUCT_NAME, "apu1")))) {
- pr_err("No PC Engines APUv1 board detected. For APUv2,3 support, enable CONFIG_PCENGINES_APU2\n");
+ pr_err("No PC Engines APUv1 board detected. For APUv2,3,4,5,6 support, enable CONFIG_PCENGINES_APU2\n");
return -ENODEV;
}
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -698,7 +698,7 @@ config XO1_RFKILL
laptop.
config PCENGINES_APU2
- tristate "PC Engines APUv2/3 front button and LEDs driver"
+ tristate "PC Engines APUv2/3/4/5/6 front button and LEDs driver"
depends on INPUT && INPUT_KEYBOARD && GPIOLIB
depends on LEDS_CLASS
select GPIO_AMD_FCH
@@ -706,7 +706,7 @@ config PCENGINES_APU2
select LEDS_GPIO
help
This driver provides support for the front button and LEDs on
- PC Engines APUv2/APUv3 board.
+ PC Engines APUv2/APUv3/APUv4/APUv5/APUv6 board.
To compile this driver as a module, choose M here: the module
will be called pcengines-apuv2.
--- a/drivers/platform/x86/pcengines-apuv2.c
+++ b/drivers/platform/x86/pcengines-apuv2.c
@@ -1,10 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * PC-Engines APUv2/APUv3 board platform driver
+ * PC-Engines APUv2-6 board platform driver
* for GPIO buttons and LEDs
*
* Copyright (C) 2018 metux IT consult
+ * Copyright (C) 2022 Ed Wildgoose <lists@wildgooses.com>
+ * Copyright (C) 2022 Philip Prindeville <philipp@redfish-solutions.com>
* Author: Enrico Weigelt <info@metux.net>
*/
@@ -22,38 +24,70 @@
#include <linux/platform_data/gpio/gpio-amd-fch.h>
/*
- * NOTE: this driver only supports APUv2/3 - not APUv1, as this one
+ * NOTE: this driver only supports APUv2-6 - not APUv1, as this one
* has completely different register layouts.
*/
+/*
+ * There are a number of APU variants, with differing features
+ * APU2 has SIM slots 1/2 mapping to mPCIe sockets 1/2
+ * APU3/4 moved SIM slot 1 to mPCIe socket 3, ie logically reversed
+ * However, most APU3/4 have a SIM switch which we default on to reverse
+ * the order and keep physical SIM order matching physical modem order
+ * APU6 is approximately the same as APU4 with different ethernet layout
+ *
+ * APU5 has 3x SIM sockets, all with a SIM switch
+ * several GPIOs are shuffled (see schematic), including MODESW
+ */
+
/* Register mappings */
#define APU2_GPIO_REG_LED1 AMD_FCH_GPIO_REG_GPIO57
#define APU2_GPIO_REG_LED2 AMD_FCH_GPIO_REG_GPIO58
#define APU2_GPIO_REG_LED3 AMD_FCH_GPIO_REG_GPIO59_DEVSLP1
#define APU2_GPIO_REG_MODESW AMD_FCH_GPIO_REG_GPIO32_GE1
#define APU2_GPIO_REG_SIMSWAP AMD_FCH_GPIO_REG_GPIO33_GE2
-#define APU2_GPIO_REG_MPCIE2 AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
-#define APU2_GPIO_REG_MPCIE3 AMD_FCH_GPIO_REG_GPIO51
+#define APU2_GPIO_REG_RESETM1 AMD_FCH_GPIO_REG_GPIO51
+#define APU2_GPIO_REG_RESETM2 AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
+
+#define APU5_GPIO_REG_MODESW AMT_FCH_GPIO_REG_GEVT22
+#define APU5_GPIO_REG_SIMSWAP1 AMD_FCH_GPIO_REG_GPIO68
+#define APU5_GPIO_REG_SIMSWAP2 AMD_FCH_GPIO_REG_GPIO32_GE1
+#define APU5_GPIO_REG_SIMSWAP3 AMD_FCH_GPIO_REG_GPIO33_GE2
+#define APU5_GPIO_REG_RESETM1 AMD_FCH_GPIO_REG_GPIO51
+#define APU5_GPIO_REG_RESETM2 AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
+#define APU5_GPIO_REG_RESETM3 AMD_FCH_GPIO_REG_GPIO64
/* Order in which the GPIO lines are defined in the register list */
#define APU2_GPIO_LINE_LED1 0
#define APU2_GPIO_LINE_LED2 1
#define APU2_GPIO_LINE_LED3 2
#define APU2_GPIO_LINE_MODESW 3
-#define APU2_GPIO_LINE_SIMSWAP 4
-#define APU2_GPIO_LINE_MPCIE2 5
-#define APU2_GPIO_LINE_MPCIE3 6
+#define APU2_GPIO_LINE_RESETM1 4
+#define APU2_GPIO_LINE_RESETM2 5
+#define APU2_GPIO_LINE_SIMSWAP 6
+
+#define APU5_GPIO_LINE_LED1 0
+#define APU5_GPIO_LINE_LED2 1
+#define APU5_GPIO_LINE_LED3 2
+#define APU5_GPIO_LINE_MODESW 3
+#define APU5_GPIO_LINE_RESETM1 4
+#define APU5_GPIO_LINE_RESETM2 5
+#define APU5_GPIO_LINE_RESETM3 6
+#define APU5_GPIO_LINE_SIMSWAP1 7
+#define APU5_GPIO_LINE_SIMSWAP2 8
+#define APU5_GPIO_LINE_SIMSWAP3 9
+
-/* GPIO device */
+/* GPIO device - APU2/3/4/6 */
static int apu2_gpio_regs[] = {
[APU2_GPIO_LINE_LED1] = APU2_GPIO_REG_LED1,
[APU2_GPIO_LINE_LED2] = APU2_GPIO_REG_LED2,
[APU2_GPIO_LINE_LED3] = APU2_GPIO_REG_LED3,
[APU2_GPIO_LINE_MODESW] = APU2_GPIO_REG_MODESW,
+ [APU2_GPIO_LINE_RESETM1] = APU2_GPIO_REG_RESETM1,
+ [APU2_GPIO_LINE_RESETM2] = APU2_GPIO_REG_RESETM2,
[APU2_GPIO_LINE_SIMSWAP] = APU2_GPIO_REG_SIMSWAP,
- [APU2_GPIO_LINE_MPCIE2] = APU2_GPIO_REG_MPCIE2,
- [APU2_GPIO_LINE_MPCIE3] = APU2_GPIO_REG_MPCIE3,
};
static const char * const apu2_gpio_names[] = {
@@ -61,9 +95,9 @@ static const char * const apu2_gpio_name
[APU2_GPIO_LINE_LED2] = "front-led2",
[APU2_GPIO_LINE_LED3] = "front-led3",
[APU2_GPIO_LINE_MODESW] = "front-button",
+ [APU2_GPIO_LINE_RESETM1] = "modem1-reset",
+ [APU2_GPIO_LINE_RESETM2] = "modem2-reset",
[APU2_GPIO_LINE_SIMSWAP] = "simswap",
- [APU2_GPIO_LINE_MPCIE2] = "mpcie2_reset",
- [APU2_GPIO_LINE_MPCIE3] = "mpcie3_reset",
};
static const struct amd_fch_gpio_pdata board_apu2 = {
@@ -72,6 +106,40 @@ static const struct amd_fch_gpio_pdata b
.gpio_names = apu2_gpio_names,
};
+/* GPIO device - APU5 */
+
+static int apu5_gpio_regs[] = {
+ [APU5_GPIO_LINE_LED1] = APU2_GPIO_REG_LED1,
+ [APU5_GPIO_LINE_LED2] = APU2_GPIO_REG_LED2,
+ [APU5_GPIO_LINE_LED3] = APU2_GPIO_REG_LED3,
+ [APU5_GPIO_LINE_MODESW] = APU5_GPIO_REG_MODESW,
+ [APU5_GPIO_LINE_RESETM1] = APU5_GPIO_REG_RESETM1,
+ [APU5_GPIO_LINE_RESETM2] = APU5_GPIO_REG_RESETM2,
+ [APU5_GPIO_LINE_RESETM3] = APU5_GPIO_REG_RESETM3,
+ [APU5_GPIO_LINE_SIMSWAP1] = APU5_GPIO_REG_SIMSWAP1,
+ [APU5_GPIO_LINE_SIMSWAP2] = APU5_GPIO_REG_SIMSWAP2,
+ [APU5_GPIO_LINE_SIMSWAP3] = APU5_GPIO_REG_SIMSWAP3,
+};
+
+static const char * const apu5_gpio_names[] = {
+ [APU5_GPIO_LINE_LED1] = "front-led1",
+ [APU5_GPIO_LINE_LED2] = "front-led2",
+ [APU5_GPIO_LINE_LED3] = "front-led3",
+ [APU5_GPIO_LINE_MODESW] = "front-button",
+ [APU5_GPIO_LINE_RESETM1] = "modem1-reset",
+ [APU5_GPIO_LINE_RESETM2] = "modem2-reset",
+ [APU5_GPIO_LINE_RESETM3] = "modem3-reset",
+ [APU5_GPIO_LINE_SIMSWAP1] = "simswap1",
+ [APU5_GPIO_LINE_SIMSWAP2] = "simswap2",
+ [APU5_GPIO_LINE_SIMSWAP3] = "simswap3",
+};
+
+static const struct amd_fch_gpio_pdata board_apu5 = {
+ .gpio_num = ARRAY_SIZE(apu5_gpio_regs),
+ .gpio_reg = apu5_gpio_regs,
+ .gpio_names = apu5_gpio_names,
+};
+
/* GPIO LEDs device */
static const struct gpio_led apu2_leds[] = {
@@ -215,6 +283,24 @@ static const struct dmi_system_id apu_gp
},
.driver_data = (void *)&board_apu2,
},
+ /* APU5 w/ mainline BIOS */
+ {
+ .ident = "apu5",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+ DMI_MATCH(DMI_BOARD_NAME, "apu5")
+ },
+ .driver_data = (void *)&board_apu5,
+ },
+ /* APU6 w/ mainline BIOS */
+ {
+ .ident = "apu6",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+ DMI_MATCH(DMI_BOARD_NAME, "apu6")
+ },
+ .driver_data = (void *)&board_apu2,
+ },
{}
};
@@ -249,7 +335,7 @@ static int __init apu_board_init(void)
id = dmi_first_match(apu_gpio_dmi_table);
if (!id) {
- pr_err("failed to detect APU board via DMI\n");
+ pr_err("No APU board detected via DMI\n");
return -ENODEV;
}
@@ -288,8 +374,12 @@ module_init(apu_board_init);
module_exit(apu_board_exit);
MODULE_AUTHOR("Enrico Weigelt, metux IT consult <info@metux.net>");
-MODULE_DESCRIPTION("PC Engines APUv2/APUv3 board GPIO/LEDs/keys driver");
+MODULE_DESCRIPTION("PC Engines APUv2-6 board GPIO/LEDs/keys driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(dmi, apu_gpio_dmi_table);
MODULE_ALIAS("platform:pcengines-apuv2");
+MODULE_ALIAS("platform:pcengines-apuv3");
+MODULE_ALIAS("platform:pcengines-apuv4");
+MODULE_ALIAS("platform:pcengines-apuv5");
+MODULE_ALIAS("platform:pcengines-apuv6");
MODULE_SOFTDEP("pre: platform:" AMD_FCH_GPIO_DRIVER_NAME " platform:leds-gpio platform:gpio_keys_polled");

5
target/sdk/Makefile
View File

@ -86,9 +86,10 @@ KERNEL_FILES := $(patsubst $(TOPDIR)/%,%,$(wildcard $(addprefix $(LINUX_DIR)/,$(
#
USERSPACE_UTILS_FILES := \
tools/build \
tools/power/cpupower \
tools/scripts \
tools/usb/usbip \
tools/spi
tools/spi \
tools/usb/usbip
USERSPACE_FILES := $(patsubst $(TOPDIR)/%,%,$(wildcard $(addprefix $(LINUX_DIR)/,$(USERSPACE_UTILS_FILES))))

1
toolchain/binutils/Makefile
View File

@ -12,6 +12,7 @@ BIN_VERSION:=$(PKG_VERSION)
PKG_SOURCE_URL:=@GNU/binutils/
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_CPE_ID:=cpe:/a:gnu:binutils
TAR_OPTIONS += --exclude='*.rej'

1
toolchain/gcc/common.mk
View File

@ -28,6 +28,7 @@ GCC_DIR:=$(PKG_NAME)-$(PKG_VERSION)
PKG_SOURCE_URL:=@GNU/gcc/gcc-$(PKG_VERSION)
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_CPE_ID:=cpe:/a:gnu:gcc
ifeq ($(PKG_VERSION),11.3.0)
PKG_HASH:=b47cf2818691f5b1e21df2bb38c795fac2cfbd640ede2d0a5e1c89e338a3ac39

1
toolchain/gdb/Makefile
View File

@ -13,6 +13,7 @@ PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNU/gdb
PKG_HASH:=0e1793bf8f2b54d53f46dea84ccfd446f48f81b297b28c4f7fc017b818d69fed
PKG_CPE_ID:=cpe:/a:gnu:gdb
GDB_DIR:=$(PKG_NAME)-$(PKG_VERSION)
HOST_BUILD_DIR:=$(BUILD_DIR_TOOLCHAIN)/$(GDB_DIR)

1
toolchain/glibc/common.mk
View File

@ -16,6 +16,7 @@ PKG_SOURCE_VERSION:=7c32cb7dd88cf100b0b412163896e30aa2ee671a
PKG_MIRROR_HASH:=92afa3672e4af0c3ba9d360e9aaac60c094a0aad9334ef78a1fd2ee49f5e1b64
PKG_SOURCE_URL:=https://sourceware.org/git/glibc.git
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.xz
PKG_CPE_ID:=cpe:/a:gnu:glibc
HOST_BUILD_DIR:=$(BUILD_DIR_TOOLCHAIN)/$(PKG_SOURCE_SUBDIR)
CUR_BUILD_DIR:=$(HOST_BUILD_DIR)-$(VARIANT)

1
toolchain/kernel-headers/Makefile
View File

@ -17,6 +17,7 @@ include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=linux
PKG_VERSION:=$(LINUX_VERSION)
PKG_SOURCE:=$(LINUX_SOURCE)
PKG_CPE_ID:=cpe:/o:linux:linux_kernel
ifneq ($(call qstrip,$(CONFIG_KERNEL_GIT_CLONE_URI)),)
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=$(call qstrip,$(CONFIG_KERNEL_GIT_CLONE_URI))

1
toolchain/nasm/Makefile
View File

@ -10,6 +10,7 @@ PKG_VERSION:=2.16.01
PKG_SOURCE_URL:=https://www.nasm.us/pub/nasm/releasebuilds/$(PKG_VERSION)/
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_HASH:=c77745f4802375efeee2ec5c0ad6b7f037ea9c87c92b149a9637ff099f162558
PKG_CPE_ID:=cpe:/a:nasm:nasm
HOST_BUILD_PARALLEL:=1

1
tools/7z/Makefile
View File

@ -7,6 +7,7 @@ PKG_SOURCE_VERSION:=2301
PKG_SOURCE:=$(PKG_NAME)$(PKG_SOURCE_VERSION)-src.tar.xz
PKG_SOURCE_URL:=https://7-zip.org/a/
PKG_HASH:=356071007360e5a1824d9904993e8b2480b51b570e8c9faf7c0f58ebe4bf9f74
PKG_CPE_ID:=cpe:/a:7-zip:7zip
# This builds the 7zr variant which supports only 7z, so no non-LGPL code should be included
PKG_LICENSE:=LGPL-2.1-or-later

1
tools/bison/Makefile
View File

@ -12,6 +12,7 @@ PKG_VERSION:=3.8.2
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNU/$(PKG_NAME)
PKG_HASH:=9bba0214ccf7f1079c5d59210045227bcf619519840ebfa80cd3849cff5a5bf2
PKG_CPE_ID:=cpe:/a:gnu:bison
HOST_BUILD_PARALLEL:=1

1
tools/gmp/Makefile
View File

@ -12,6 +12,7 @@ PKG_VERSION:=6.2.1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNU/gmp/
PKG_HASH:=fd4829912cddd12f84181c3451cc752be224643e87fac497b69edddadc49b4f2
PKG_CPE_ID:=cpe:/a:gmplib:gmp
HOST_FIXUP:=autoreconf

1
tools/liblzo/Makefile
View File

@ -17,6 +17,7 @@ PKG_HASH:=c0f892943208266f9b6543b3ae308fab6284c5c90e627931446fb49b4221a072
PKG_LICENSE:=GPL-2.0-or-later
PKG_LICENSE_FILES:=COPYING
PKG_CPE_ID:=cpe:/a:lzo_project:lzo
CMAKE_BINARY_SUBDIR:=openwrt-build

1
tools/llvm-bpf/Makefile
View File

@ -13,6 +13,7 @@ PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).src.tar.xz
PKG_SOURCE_URL:=https://github.com/llvm/llvm-project/releases/download/llvmorg-$(PKG_VERSION)
PKG_HASH:=8b5fcb24b4128cf04df1b0b9410ce8b1a729cb3c544e6da885d234280dedeac6
PKG_CPE_ID:=cpe:/a:llvm:llvm
HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/$(PKG_NAME)-$(PKG_VERSION).src

1
tools/lz4/Makefile
View File

@ -16,6 +16,7 @@ PKG_HASH:=0b0e3aa07c8c063ddf40b082bdf7e37a1562bda40a0ff5272957f3e987e0e54b
PKG_LICENSE:=BSD-2-Clause
PKG_LICENSE_FILES:=LICENSE lib/LICENSE
PKG_CPE_ID:=cpe:/a:lz4_project:lz4
include $(INCLUDE_DIR)/host-build.mk
include $(INCLUDE_DIR)/meson.mk

1
tools/mtd-utils/Makefile
View File

@ -13,6 +13,7 @@ PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://infraroot.at/pub/mtd/
PKG_HASH:=386e27fd121699b6b729bc2e8e04dda987b31cca6b16e12fb6cc6dcf26449f46
PKG_CPE_ID:=cpe:/a:mtd-utils_project:mtd-utils
PKG_FIXUP:=autoreconf

2
tools/sed/Makefile
View File

@ -12,6 +12,8 @@ PKG_VERSION:=4.9
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNU/$(PKG_NAME)
PKG_HASH:=6e226b732e1cd739464ad6862bd1a1aba42d7982922da7a53519631d24975181
PKG_CPE_ID:=cpe:/a:gnu:sed
export SED:=
HOST_BUILD_PARALLEL:=1

1
tools/zip/Makefile
View File

@ -17,6 +17,7 @@ PKG_HASH:=f0e8bb1f9b7eb0b01285495a2699df3a4b766784c1765a8f1aeedf63c0806369
PKG_LICENSE:=BSD-4-Clause
PKG_LICENSE_FILES:=LICENSE
PKG_CPE_ID:=cpe:/a:zip_project:zip
HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/$(PKG_NAME)-$(PKG_VERSION)/zip$(PKG_REV)
HOST_BUILD_PARALLEL:=1