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cd75f703c2
These patches have been accepted for linux v6.18. e57723fe536f net: dsa: b53: properly bound ARL searches for < 4 ARL bin chips 674b34c4c770 net: dsa: b53: fix ageing time for BCM53101 89eb9a62aed7 net: dsa: b53: fix reserved register access in b53_fdb_dump() 61730ac10ba9 net: dsa: b53: mmap: Implement bcm63268 gphy power control 7f95f04fe190 net: dsa: b53: mmap: Add gphy port to phy info for bcm63268 5ac00023852d net: dsa: b53: mmap: Implement bcm63xx ephy power control e8e13073dff7 net: dsa: b53: mmap: Add register layout for bcm6368 c251304ab021 net: dsa: b53: mmap: Add register layout for bcm6318 aed2aaa3c963 net: dsa: b53: mmap: Add syscon reference and register layout for bcm63268 fcf02a462fab net: dsa: b53: Define chip IDs for more bcm63xx SoCs be7a79145d85 net: dsa: b53: Add phy_enable(), phy_disable() methods 762e7e174da9 net: dsa: tag_brcm: do not mark link local traffic as offloaded Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
112 lines
4.5 KiB
Diff
112 lines
4.5 KiB
Diff
From d9fa3835bb8913757c74af96fa8db0d621e2e980 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Mon, 9 Jun 2025 11:18:24 +0200
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Subject: [PATCH] net: dsa: b53: bcm531x5: fix cpu rgmii mode interpretation
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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b53_adjust_531x5_rgmii() incorrectly enable delays in rgmii mode, but
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disables them in rgmii-id mode. Only rgmii-txid is correctly handled.
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Fix this by correctly enabling rx delay in rgmii-rxid and rgmii-id
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modes, and tx delay in rgmii-txid and rgmii-id modes.
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Since b53_adjust_531x5_rgmii() is only called for fixed-link ports,
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these are usually used as the CPU port, connected to a MAC. This means
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the chip is assuming the role of the PHY and enabling delays is
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expected.
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Since this has the potential to break existing setups, add a config
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options to treat rgmii as rgmii-id, and enable it by default.
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I only made the quirk fixup rgmii to rgmii-id, but not rgmii-id to
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rgmii, or no delays for rgmii-rxid. My reasoning is that
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a) Boards not requiring internal delays are probably rather seldom, so I
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considered the likelyhood requiring/wrongly specifying rgmii-id when
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they need rgmii as very unlikely.
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And if they understand the difference enough to know to use the
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"wrong" mode, they would have hopefully noticed the discrepancy and
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reported the issue by now.
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b) I don't want to require new users to wrongly use rgmii to get
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rgmii-id behavior with the quirk enabled.
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Fixes: 967dd82ffc52 ("net: dsa: b53: Add support for Broadcom RoboSwitch")
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Reported-by: Álvaro Fernández Rojas <noltari@gmail.com>
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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drivers/net/dsa/b53/Kconfig | 10 ++++++++++
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drivers/net/dsa/b53/b53_common.c | 33 +++++++++++++++++++++++---------
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2 files changed, 34 insertions(+), 9 deletions(-)
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--- a/drivers/net/dsa/b53/Kconfig
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+++ b/drivers/net/dsa/b53/Kconfig
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@@ -47,3 +47,13 @@ config B53_SERDES
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default ARCH_BCM_NSP
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help
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Select to enable support for SerDes on e.g: Northstar Plus SoCs.
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+
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+config B53_QUIRK_IMP_RGMII_IMPLIES_DELAYS
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+ bool "Treat RGMII as RGMII-ID for CPU port"
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+ depends on B53
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+ default y
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+ help
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+ Select to enable RGMII delays also in RGMII (no ID) mode for the CPU
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+ port to mirror old driver behavior.
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+ Enable this if your board wrongly uses RGMII instead of RGMII-ID as
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+ the phy interface, but actually requires internal delays enabled.
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--- a/drivers/net/dsa/b53/b53_common.c
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+++ b/drivers/net/dsa/b53/b53_common.c
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@@ -1447,6 +1447,16 @@ static void b53_adjust_531x5_rgmii(struc
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else
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off = B53_RGMII_CTRL_P(port);
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+ if (IS_ENABLED(CONFIG_B53_QUIRK_IMP_RGMII_IMPLIES_DELAYS) &&
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+ interface == PHY_INTERFACE_MODE_RGMII) {
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+ /* Older driver versions incorrectly applied delays in
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+ * PHY_INTERFACE_MODE_RGMII mode.
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+ *
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+ * So fixup the interface to match the old behavior.
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+ */
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+ interface = PHY_INTERFACE_MODE_RGMII_ID;
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+ }
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+
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/* Configure the port RGMII clock delay by DLL disabled and
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* tx_clk aligned timing (restoring to reset defaults)
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*/
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@@ -1458,19 +1468,24 @@ static void b53_adjust_531x5_rgmii(struc
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* account for this internal delay that is inserted, otherwise
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* the switch won't be able to receive correctly.
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*
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+ * PHY_INTERFACE_MODE_RGMII_RXID means RX internal delay, make
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+ * sure that we enable the port RX clock internal sampling delay
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+ * to account for this internal delay that is inserted, otherwise
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+ * the switch won't be able to send correctly.
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+ *
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+ * PHY_INTERFACE_MODE_RGMII_ID means both RX and TX internal delay,
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+ * make sure that we enable delays for both.
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+ *
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* PHY_INTERFACE_MODE_RGMII means that we are not introducing
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* any delay neither on transmission nor reception, so the
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- * BCM53125 must also be configured accordingly to account for
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- * the lack of delay and introduce
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- *
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- * The BCM53125 switch has its RX clock and TX clock control
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- * swapped, hence the reason why we modify the TX clock path in
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- * the "RGMII" case
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+ * BCM53125 must also be configured accordingly.
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*/
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- if (interface == PHY_INTERFACE_MODE_RGMII_TXID)
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+ if (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
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+ interface == PHY_INTERFACE_MODE_RGMII_ID)
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rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
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- if (interface == PHY_INTERFACE_MODE_RGMII)
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- rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
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+ if (interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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+ interface == PHY_INTERFACE_MODE_RGMII_ID)
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+ rgmii_ctrl |= RGMII_CTRL_DLL_RXC;
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if (dev->chip_id != BCM53115_DEVICE_ID)
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rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
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