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cd75f703c2
These patches have been accepted for linux v6.18. e57723fe536f net: dsa: b53: properly bound ARL searches for < 4 ARL bin chips 674b34c4c770 net: dsa: b53: fix ageing time for BCM53101 89eb9a62aed7 net: dsa: b53: fix reserved register access in b53_fdb_dump() 61730ac10ba9 net: dsa: b53: mmap: Implement bcm63268 gphy power control 7f95f04fe190 net: dsa: b53: mmap: Add gphy port to phy info for bcm63268 5ac00023852d net: dsa: b53: mmap: Implement bcm63xx ephy power control e8e13073dff7 net: dsa: b53: mmap: Add register layout for bcm6368 c251304ab021 net: dsa: b53: mmap: Add register layout for bcm6318 aed2aaa3c963 net: dsa: b53: mmap: Add syscon reference and register layout for bcm63268 fcf02a462fab net: dsa: b53: Define chip IDs for more bcm63xx SoCs be7a79145d85 net: dsa: b53: Add phy_enable(), phy_disable() methods 762e7e174da9 net: dsa: tag_brcm: do not mark link local traffic as offloaded Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
101 lines
2.9 KiB
Diff
101 lines
2.9 KiB
Diff
From 5ac00023852d960528a0c1d10ae6c17893fc4113 Mon Sep 17 00:00:00 2001
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From: Kyle Hendry <kylehendrydev@gmail.com>
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Date: Wed, 23 Jul 2025 20:52:46 -0700
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Subject: [PATCH] net: dsa: b53: mmap: Implement bcm63xx ephy power control
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Implement the phy enable/disable calls for b53 mmap, and
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set the power down registers in the ephy control register
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appropriately.
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Signed-off-by: Kyle Hendry <kylehendrydev@gmail.com>
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Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Link: https://patch.msgid.link/20250724035300.20497-8-kylehendrydev@gmail.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/dsa/b53/b53_mmap.c | 50 ++++++++++++++++++++++++++++++++++
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1 file changed, 50 insertions(+)
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--- a/drivers/net/dsa/b53/b53_mmap.c
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+++ b/drivers/net/dsa/b53/b53_mmap.c
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@@ -24,9 +24,12 @@
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/b53.h>
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+#include <linux/regmap.h>
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#include "b53_priv.h"
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+#define BCM63XX_EPHY_REG 0x3C
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+
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struct b53_phy_info {
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u32 ephy_enable_mask;
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u32 ephy_port_mask;
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@@ -38,6 +41,7 @@ struct b53_mmap_priv {
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void __iomem *regs;
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struct regmap *gpio_ctrl;
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const struct b53_phy_info *phy_info;
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+ u32 phys_enabled;
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};
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static const u32 bcm6318_ephy_offsets[] = {4, 5, 6, 7};
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@@ -266,6 +270,50 @@ static int b53_mmap_phy_write16(struct b
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return -EIO;
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}
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+static int bcm63xx_ephy_set(struct b53_device *dev, int port, bool enable)
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+{
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+ struct b53_mmap_priv *priv = dev->priv;
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+ const struct b53_phy_info *info = priv->phy_info;
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+ struct regmap *gpio_ctrl = priv->gpio_ctrl;
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+ u32 mask, val;
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+
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+ if (enable) {
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+ mask = (info->ephy_enable_mask << info->ephy_offset[port])
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+ | BIT(info->ephy_bias_bit);
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+ val = 0;
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+ } else {
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+ mask = (info->ephy_enable_mask << info->ephy_offset[port]);
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+ if (!((priv->phys_enabled & ~BIT(port)) & info->ephy_port_mask))
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+ mask |= BIT(info->ephy_bias_bit);
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+ val = mask;
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+ }
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+ return regmap_update_bits(gpio_ctrl, BCM63XX_EPHY_REG, mask, val);
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+}
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+
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+static void b53_mmap_phy_enable(struct b53_device *dev, int port)
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+{
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+ struct b53_mmap_priv *priv = dev->priv;
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+ int ret = 0;
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+
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+ if (priv->phy_info && (BIT(port) & priv->phy_info->ephy_port_mask))
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+ ret = bcm63xx_ephy_set(dev, port, true);
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+
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+ if (!ret)
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+ priv->phys_enabled |= BIT(port);
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+}
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+
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+static void b53_mmap_phy_disable(struct b53_device *dev, int port)
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+{
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+ struct b53_mmap_priv *priv = dev->priv;
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+ int ret = 0;
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+
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+ if (priv->phy_info && (BIT(port) & priv->phy_info->ephy_port_mask))
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+ ret = bcm63xx_ephy_set(dev, port, false);
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+
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+ if (!ret)
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+ priv->phys_enabled &= ~BIT(port);
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+}
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+
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static const struct b53_io_ops b53_mmap_ops = {
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.read8 = b53_mmap_read8,
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.read16 = b53_mmap_read16,
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@@ -279,6 +327,8 @@ static const struct b53_io_ops b53_mmap_
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.write64 = b53_mmap_write64,
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.phy_read16 = b53_mmap_phy_read16,
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.phy_write16 = b53_mmap_phy_write16,
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+ .phy_enable = b53_mmap_phy_enable,
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+ .phy_disable = b53_mmap_phy_disable,
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};
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static int b53_mmap_probe_of(struct platform_device *pdev,
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