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cd75f703c2
These patches have been accepted for linux v6.18. e57723fe536f net: dsa: b53: properly bound ARL searches for < 4 ARL bin chips 674b34c4c770 net: dsa: b53: fix ageing time for BCM53101 89eb9a62aed7 net: dsa: b53: fix reserved register access in b53_fdb_dump() 61730ac10ba9 net: dsa: b53: mmap: Implement bcm63268 gphy power control 7f95f04fe190 net: dsa: b53: mmap: Add gphy port to phy info for bcm63268 5ac00023852d net: dsa: b53: mmap: Implement bcm63xx ephy power control e8e13073dff7 net: dsa: b53: mmap: Add register layout for bcm6368 c251304ab021 net: dsa: b53: mmap: Add register layout for bcm6318 aed2aaa3c963 net: dsa: b53: mmap: Add syscon reference and register layout for bcm63268 fcf02a462fab net: dsa: b53: Define chip IDs for more bcm63xx SoCs be7a79145d85 net: dsa: b53: Add phy_enable(), phy_disable() methods 762e7e174da9 net: dsa: tag_brcm: do not mark link local traffic as offloaded Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
78 lines
2.4 KiB
Diff
78 lines
2.4 KiB
Diff
From 61730ac10ba90c52563861a0119504f6a9be9868 Mon Sep 17 00:00:00 2001
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From: Kyle Hendry <kylehendrydev@gmail.com>
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Date: Wed, 13 Aug 2025 17:25:28 -0700
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Subject: [PATCH] net: dsa: b53: mmap: Implement bcm63268 gphy power control
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Add check for gphy in enable/disable phy calls and set power bits
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in gphy control register.
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Signed-off-by: Kyle Hendry <kylehendrydev@gmail.com>
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Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Link: https://patch.msgid.link/20250814002530.5866-3-kylehendrydev@gmail.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/dsa/b53/b53_mmap.c | 33 +++++++++++++++++++++++++++++----
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1 file changed, 29 insertions(+), 4 deletions(-)
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--- a/drivers/net/dsa/b53/b53_mmap.c
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+++ b/drivers/net/dsa/b53/b53_mmap.c
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@@ -29,6 +29,10 @@
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#include "b53_priv.h"
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#define BCM63XX_EPHY_REG 0x3C
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+#define BCM63268_GPHY_REG 0x54
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+
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+#define GPHY_CTRL_LOW_PWR BIT(3)
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+#define GPHY_CTRL_IDDQ_BIAS BIT(0)
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struct b53_phy_info {
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u32 gphy_port_mask;
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@@ -292,13 +296,30 @@ static int bcm63xx_ephy_set(struct b53_d
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return regmap_update_bits(gpio_ctrl, BCM63XX_EPHY_REG, mask, val);
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}
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+static int bcm63268_gphy_set(struct b53_device *dev, bool enable)
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+{
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+ struct b53_mmap_priv *priv = dev->priv;
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+ struct regmap *gpio_ctrl = priv->gpio_ctrl;
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+ u32 mask = GPHY_CTRL_IDDQ_BIAS | GPHY_CTRL_LOW_PWR;
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+ u32 val = 0;
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+
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+ if (!enable)
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+ val = mask;
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+
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+ return regmap_update_bits(gpio_ctrl, BCM63268_GPHY_REG, mask, val);
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+}
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+
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static void b53_mmap_phy_enable(struct b53_device *dev, int port)
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{
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struct b53_mmap_priv *priv = dev->priv;
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int ret = 0;
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- if (priv->phy_info && (BIT(port) & priv->phy_info->ephy_port_mask))
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- ret = bcm63xx_ephy_set(dev, port, true);
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+ if (priv->phy_info) {
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+ if (BIT(port) & priv->phy_info->ephy_port_mask)
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+ ret = bcm63xx_ephy_set(dev, port, true);
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+ else if (BIT(port) & priv->phy_info->gphy_port_mask)
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+ ret = bcm63268_gphy_set(dev, true);
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+ }
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if (!ret)
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priv->phys_enabled |= BIT(port);
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@@ -309,8 +330,12 @@ static void b53_mmap_phy_disable(struct
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struct b53_mmap_priv *priv = dev->priv;
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int ret = 0;
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- if (priv->phy_info && (BIT(port) & priv->phy_info->ephy_port_mask))
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- ret = bcm63xx_ephy_set(dev, port, false);
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+ if (priv->phy_info) {
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+ if (BIT(port) & priv->phy_info->ephy_port_mask)
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+ ret = bcm63xx_ephy_set(dev, port, false);
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+ else if (BIT(port) & priv->phy_info->gphy_port_mask)
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+ ret = bcm63268_gphy_set(dev, false);
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+ }
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if (!ret)
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priv->phys_enabled &= ~BIT(port);
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