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081cfb3a24
Mediatek PHY patch has been merged upstream. Reintroduce them to backport directory as the same PHY is also needed for Airoha target. All the affected patch automatically refreshed. Link: https://github.com/openwrt/openwrt/pull/19816 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
89 lines
3.1 KiB
Diff
89 lines
3.1 KiB
Diff
From b544223bec9f710256543eadc1b8b8344f80d665 Mon Sep 17 00:00:00 2001
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From: "SkyLake.Huang" <skylake.huang@mediatek.com>
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Date: Thu, 17 Oct 2024 11:22:11 +0800
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Subject: [PATCH 1/3] net: phy: mediatek-ge-soc: Fix coding style
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This patch fixes spelling errors, re-arrange vars with
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reverse Xmas tree and remove unnecessary parens in
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mediatek-ge-soc.c.
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Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
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Reviewed-by: Simon Horman <horms@kernel.org>
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Signed-off-by: Andrew Lunn <andrew@lunn.ch>
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---
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drivers/net/phy/mediatek-ge-soc.c | 36 ++++++++++++++++---------------
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1 file changed, 19 insertions(+), 17 deletions(-)
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--- a/drivers/net/phy/mediatek-ge-soc.c
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+++ b/drivers/net/phy/mediatek-ge-soc.c
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@@ -408,16 +408,17 @@ static int tx_offset_cal_efuse(struct ph
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static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
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{
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- int i;
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- int bias[16] = {};
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- const int vals_9461[16] = { 7, 1, 4, 7,
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- 7, 1, 4, 7,
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- 7, 1, 4, 7,
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- 7, 1, 4, 7 };
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const int vals_9481[16] = { 10, 6, 6, 10,
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10, 6, 6, 10,
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10, 6, 6, 10,
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10, 6, 6, 10 };
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+ const int vals_9461[16] = { 7, 1, 4, 7,
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+ 7, 1, 4, 7,
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+ 7, 1, 4, 7,
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+ 7, 1, 4, 7 };
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+ int bias[16] = {};
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+ int i;
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+
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switch (phydev->drv->phy_id) {
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case MTK_GPHY_ID_MT7981:
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/* We add some calibration to efuse values
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@@ -1069,10 +1070,10 @@ static int start_cal(struct phy_device *
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static int mt798x_phy_calibration(struct phy_device *phydev)
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{
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+ struct nvmem_cell *cell;
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int ret = 0;
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- u32 *buf;
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size_t len;
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- struct nvmem_cell *cell;
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+ u32 *buf;
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cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
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if (IS_ERR(cell)) {
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@@ -1210,14 +1211,15 @@ static int mt798x_phy_led_brightness_set
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return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
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}
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-static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
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- BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
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- BIT(TRIGGER_NETDEV_LINK) |
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- BIT(TRIGGER_NETDEV_LINK_10) |
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- BIT(TRIGGER_NETDEV_LINK_100) |
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- BIT(TRIGGER_NETDEV_LINK_1000) |
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- BIT(TRIGGER_NETDEV_RX) |
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- BIT(TRIGGER_NETDEV_TX));
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+static const unsigned long supported_triggers =
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+ BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
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+ BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
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+ BIT(TRIGGER_NETDEV_LINK) |
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+ BIT(TRIGGER_NETDEV_LINK_10) |
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+ BIT(TRIGGER_NETDEV_LINK_100) |
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+ BIT(TRIGGER_NETDEV_LINK_1000) |
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+ BIT(TRIGGER_NETDEV_RX) |
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+ BIT(TRIGGER_NETDEV_TX);
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static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
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unsigned long rules)
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@@ -1415,7 +1417,7 @@ static int mt7988_phy_probe_shared(struc
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* LED_C and LED_D respectively. At the same time those pins are used to
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* bootstrap configuration of the reference clock source (LED_A),
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* DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
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- * In practise this is done using a LED and a resistor pulling the pin
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+ * In practice this is done using a LED and a resistor pulling the pin
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* either to GND or to VIO.
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* The detected value at boot time is accessible at run-time using the
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* TPBANK0 register located in the gpio base of the pinctrl, in order
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