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081cfb3a24
Mediatek PHY patch has been merged upstream. Reintroduce them to backport directory as the same PHY is also needed for Airoha target. All the affected patch automatically refreshed. Link: https://github.com/openwrt/openwrt/pull/19816 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
74 lines
2.7 KiB
Diff
74 lines
2.7 KiB
Diff
From 40d33d6d3c90eb104c66e05cdc00db61268c93f9 Mon Sep 17 00:00:00 2001
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From: Sky Huang <skylake.huang@mediatek.com>
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Date: Thu, 13 Feb 2025 16:05:51 +0800
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Subject: [PATCH 3/5] net: phy: mediatek: Add token ring set bit operation
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support
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Previously in mtk-ge-soc.c, we set some register bits via token
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ring, which were implemented in three __phy_write().
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Now we can do the same thing via __mtk_tr_set_bits() helper.
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Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Link: https://patch.msgid.link/20250213080553.921434-4-SkyLake.Huang@mediatek.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/phy/mediatek/mtk-ge-soc.c | 10 ++++++----
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drivers/net/phy/mediatek/mtk-phy-lib.c | 7 +++++++
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drivers/net/phy/mediatek/mtk.h | 2 ++
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3 files changed, 15 insertions(+), 4 deletions(-)
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--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
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+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
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@@ -62,6 +62,10 @@
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/* MasDSPreadyTime */
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#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7)
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+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */
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+/* EnabRandUpdTrig */
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+#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER BIT(8)
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+
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/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
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/* ResetSyncOffset */
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#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8)
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@@ -789,10 +793,8 @@ static void mt798x_phy_common_finetune(s
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FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) |
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FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18));
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- /* EnabRandUpdTrig = 1 */
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- __phy_write(phydev, 0x11, 0x2f00);
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- __phy_write(phydev, 0x12, 0xe);
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- __phy_write(phydev, 0x10, 0x8fb0);
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+ __mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18,
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+ ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER);
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__mtk_tr_modify(phydev, 0x0, 0x7, 0x15,
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NORMAL_MSE_LO_THRESH_MASK,
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--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
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+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
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@@ -69,6 +69,13 @@ void mtk_tr_modify(struct phy_device *ph
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}
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EXPORT_SYMBOL_GPL(mtk_tr_modify);
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+void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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+ u8 data_addr, u32 set)
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+{
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+ __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, 0, set);
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+}
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+EXPORT_SYMBOL_GPL(__mtk_tr_set_bits);
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+
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int mtk_phy_read_page(struct phy_device *phydev)
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{
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return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
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--- a/drivers/net/phy/mediatek/mtk.h
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+++ b/drivers/net/phy/mediatek/mtk.h
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@@ -72,6 +72,8 @@ void __mtk_tr_modify(struct phy_device *
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u8 data_addr, u32 mask, u32 set);
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void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr, u32 mask, u32 set);
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+void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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+ u8 data_addr, u32 set);
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int mtk_phy_read_page(struct phy_device *phydev);
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int mtk_phy_write_page(struct phy_device *phydev, int page);
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