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7656e74a95
The "old" QCA8084 PHY driver does not implement 10g-qxgmii support. This is blocking several devices which use the QCA8084 form being merged. Qualcomm has provided updated drivers for the MAC (ppe), PCS, and PHY via github. We only need to update the PHY driver. Update the QCA8084 PHY driver using the patches provided by Qualcomm. Re-organize the patches so that the changes go into the existing patches. The SERDES functionality is new, so it gets new patches. This is sufficient to enable 10g-qxgmii on ipq95xx platforms. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/20721 Signed-off-by: Robert Marko <robimarko@gmail.com>
126 lines
3.7 KiB
Diff
126 lines
3.7 KiB
Diff
From cea8043def0c0867370c2efd5a1cd73bf4d3e5ba Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Wed, 29 Nov 2023 15:21:22 +0800
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Subject: [PATCH] net: phy: qca808x: Add register access support routines for
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QCA8084
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QCA8084 integrates clock controller and security control modules
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besides of the PHY and PCS. The 32bit registers in these modules
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are accessed using special MDIO sequences to read or write these
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registers.
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The MDIO address of PHY and PCS are configured by writing to the
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security control register. The package mode for QCA8084 is also
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configured in a similar manner.
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Change-Id: I9317307ef9bbc738a6adcbc3ea1be8e6528d711e
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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drivers/net/phy/qcom/qca808x.c | 88 ++++++++++++++++++++++++++++++++++
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1 file changed, 88 insertions(+)
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--- a/drivers/net/phy/qcom/qca808x.c
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+++ b/drivers/net/phy/qcom/qca808x.c
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@@ -111,6 +111,22 @@
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#define QCA8084_MMD7_IPG_OP 0x901d
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#define QCA8084_IPG_10_TO_11_EN BIT(0)
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+/* QCA8084 includes secure control module, which supports customizing the
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+ * MDIO address of PHY device and PCS device and configuring package mode
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+ * for the interface mode of PCS. The register of secure control is accessed
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+ * by MDIO bus with the special MDIO sequences, where the 32 bits register
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+ * address is split into 3 MDIO operations with 16 bits address.
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+ */
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+#define QCA8084_HIGH_ADDR_PREFIX 0x18
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+#define QCA8084_LOW_ADDR_PREFIX 0x10
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+
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+/* Bottom two bits of REG must be zero */
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+#define QCA8084_MII_REG_MASK GENMASK(4, 0)
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+#define QCA8084_MII_PHY_ADDR_MASK GENMASK(7, 5)
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+#define QCA8084_MII_PAGE_MASK GENMASK(23, 8)
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+#define QCA8084_MII_SW_ADDR_MASK GENMASK(31, 24)
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+#define QCA8084_MII_REG_DATA_UPPER_16_BITS BIT(1)
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+
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MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
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MODULE_LICENSE("GPL");
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@@ -119,6 +135,78 @@ struct qca808x_priv {
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int led_polarity_mode;
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};
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+static int __qca8084_set_page(struct mii_bus *bus, u16 sw_addr, u16 page)
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+{
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+ return __mdiobus_write(bus, QCA8084_HIGH_ADDR_PREFIX | (sw_addr >> 5),
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+ sw_addr & 0x1f, page);
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+}
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+
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+static int __qca8084_mii_read(struct mii_bus *bus, u16 addr, u16 reg, u32 *val)
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+{
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+ int ret, data;
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+
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+ ret = __mdiobus_read(bus, addr, reg);
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+ if (ret < 0)
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+ return ret;
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+
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+ data = ret;
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+ ret = __mdiobus_read(bus, addr,
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+ reg | QCA8084_MII_REG_DATA_UPPER_16_BITS);
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+ if (ret < 0)
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+ return ret;
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+
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+ *val = data | ret << 16;
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+
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+ return 0;
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+}
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+
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+static int __qca8084_mii_write(struct mii_bus *bus, u16 addr, u16 reg, u32 val)
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+{
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+ int ret;
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+
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+ ret = __mdiobus_write(bus, addr, reg, lower_16_bits(val));
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+ if (!ret)
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+ ret = __mdiobus_write(bus, addr,
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+ reg | QCA8084_MII_REG_DATA_UPPER_16_BITS,
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+ upper_16_bits(val));
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+
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+ return ret;
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+}
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+
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+static int qca8084_mii_modify(struct phy_device *phydev, u32 regaddr,
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+ u32 clear, u32 set)
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+{
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+ u16 reg, addr, page, sw_addr;
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+ struct mii_bus *bus;
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+ u32 val;
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+ int ret;
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+
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+ bus = phydev->mdio.bus;
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+ mutex_lock(&bus->mdio_lock);
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+
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+ reg = FIELD_GET(QCA8084_MII_REG_MASK, regaddr);
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+ addr = FIELD_GET(QCA8084_MII_PHY_ADDR_MASK, regaddr);
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+ page = FIELD_GET(QCA8084_MII_PAGE_MASK, regaddr);
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+ sw_addr = FIELD_GET(QCA8084_MII_SW_ADDR_MASK, regaddr);
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+
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+ ret = __qca8084_set_page(bus, sw_addr, page);
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+ if (ret < 0)
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+ goto qca8084_mii_modify_exit;
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+
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+ ret = __qca8084_mii_read(bus, QCA8084_LOW_ADDR_PREFIX | addr,
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+ reg, &val);
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+ if (ret < 0)
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+ goto qca8084_mii_modify_exit;
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+
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+ val &= ~clear;
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+ val |= set;
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+ ret = __qca8084_mii_write(bus, QCA8084_LOW_ADDR_PREFIX | addr,
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+ reg, val);
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+qca8084_mii_modify_exit:
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+ mutex_unlock(&bus->mdio_lock);
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+ return ret;
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+};
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+
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static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
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{
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int ret;
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