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https://github.com/VIKINGYFY/immortalwrt.git
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b8742b1ae0
Changes: * removed upstreamed patches, * rebased local patches, * fix en7581_evb/an7583_evb booting issues * enable position independent code Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Link: https://github.com/openwrt/openwrt/pull/20400 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
227 lines
6.8 KiB
Diff
227 lines
6.8 KiB
Diff
From 23031ad51d55361be507b83307f55995e0204188 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Tue, 29 Apr 2025 13:33:35 +0200
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Subject: [PATCH 4/6] reset: airoha: Add support for Airoha AN7583 reset
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Adapt the Airoha reset driver to support Airoha AN7583 node structure.
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In AN7583 the register is exposed by the parent syscon hence a different
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logic needs to be applied. Also the reset line differ from AN7581 hence
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a dedicated table is needed.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/reset/reset-airoha.c | 94 ++++++++++++++++++-
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.../dt-bindings/reset/airoha,an7583-reset.h | 61 ++++++++++++
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2 files changed, 153 insertions(+), 2 deletions(-)
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create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h
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--- a/drivers/reset/reset-airoha.c
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+++ b/drivers/reset/reset-airoha.c
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@@ -11,8 +11,10 @@
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#include <linux/io.h>
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#include <reset-uclass.h>
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#include <regmap.h>
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+#include <syscon.h>
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#include <dt-bindings/reset/airoha,en7581-reset.h>
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+#include <dt-bindings/reset/airoha,an7583-reset.h>
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#define RST_NR_PER_BANK 32
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@@ -22,6 +24,7 @@
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struct airoha_reset_priv {
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const u16 *bank_ofs;
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const u16 *idx_map;
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+ int num_rsts;
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struct regmap *map;
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};
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@@ -88,6 +91,59 @@ static const u16 en7581_rst_map[] = {
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[EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
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};
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+static const u16 an7583_rst_map[] = {
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+ /* RST_CTRL2 */
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+ [AN7583_XPON_PHY_RST] = 0,
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+ [AN7583_GPON_OLT_RST] = 1,
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+ [AN7583_CPU_TIMER2_RST] = 2,
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+ [AN7583_HSUART_RST] = 3,
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+ [AN7583_UART4_RST] = 4,
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+ [AN7583_UART5_RST] = 5,
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+ [AN7583_I2C2_RST] = 6,
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+ [AN7583_XSI_MAC_RST] = 7,
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+ [AN7583_XSI_PHY_RST] = 8,
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+ [AN7583_NPU_RST] = 9,
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+ [AN7583_TRNG_MSTART_RST] = 12,
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+ [AN7583_DUAL_HSI0_RST] = 13,
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+ [AN7583_DUAL_HSI1_RST] = 14,
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+ [AN7583_DUAL_HSI0_MAC_RST] = 16,
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+ [AN7583_DUAL_HSI1_MAC_RST] = 17,
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+ [AN7583_WDMA_RST] = 19,
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+ [AN7583_WOE0_RST] = 20,
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+ [AN7583_HSDMA_RST] = 22,
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+ [AN7583_TDMA_RST] = 24,
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+ [AN7583_EMMC_RST] = 25,
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+ [AN7583_SOE_RST] = 26,
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+ [AN7583_XFP_MAC_RST] = 28,
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+ [AN7583_MDIO0] = 30,
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+ [AN7583_MDIO1] = 31,
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+ /* RST_CTRL1 */
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+ [AN7583_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
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+ [AN7583_FE_PDMA_RST] = RST_NR_PER_BANK + 1,
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+ [AN7583_FE_QDMA_RST] = RST_NR_PER_BANK + 2,
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+ [AN7583_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4,
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+ [AN7583_CRYPTO_RST] = RST_NR_PER_BANK + 6,
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+ [AN7583_TIMER_RST] = RST_NR_PER_BANK + 8,
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+ [AN7583_PCM1_RST] = RST_NR_PER_BANK + 11,
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+ [AN7583_UART_RST] = RST_NR_PER_BANK + 12,
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+ [AN7583_GPIO_RST] = RST_NR_PER_BANK + 13,
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+ [AN7583_GDMA_RST] = RST_NR_PER_BANK + 14,
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+ [AN7583_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
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+ [AN7583_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
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+ [AN7583_SFC_RST] = RST_NR_PER_BANK + 18,
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+ [AN7583_UART2_RST] = RST_NR_PER_BANK + 19,
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+ [AN7583_GDMP_RST] = RST_NR_PER_BANK + 20,
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+ [AN7583_FE_RST] = RST_NR_PER_BANK + 21,
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+ [AN7583_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
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+ [AN7583_GSW_RST] = RST_NR_PER_BANK + 23,
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+ [AN7583_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
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+ [AN7583_PCIE0_RST] = RST_NR_PER_BANK + 26,
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+ [AN7583_PCIE1_RST] = RST_NR_PER_BANK + 27,
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+ [AN7583_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
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+ [AN7583_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
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+ [AN7583_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
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+};
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+
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static int airoha_reset_update(struct airoha_reset_priv *priv,
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unsigned long id, bool assert)
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{
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@@ -135,7 +191,7 @@ static int airoha_reset_xlate(struct reset_ctl *reset_ctl,
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{
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struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
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- if (args->args[0] >= ARRAY_SIZE(en7581_rst_map))
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+ if (args->args[0] >= priv->num_rsts)
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return -EINVAL;
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reset_ctl->id = priv->idx_map[args->args[0]];
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@@ -150,7 +206,7 @@ static struct reset_ops airoha_reset_ops = {
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.rst_status = airoha_reset_status,
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};
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-static int airoha_reset_probe(struct udevice *dev)
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+static int an7581_reset_probe(struct udevice *dev)
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{
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struct airoha_reset_priv *priv = dev_get_priv(dev);
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int ret;
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@@ -161,10 +217,44 @@ static int airoha_reset_probe(struct udevice *dev)
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priv->bank_ofs = en7581_rst_ofs;
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priv->idx_map = en7581_rst_map;
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+ priv->num_rsts = ARRAY_SIZE(en7581_rst_map);
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+
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+ return 0;
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+}
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+
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+static int an7583_reset_probe(struct udevice *dev)
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+{
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+ struct airoha_reset_priv *priv = dev_get_priv(dev);
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+ ofnode pnode, scu_node = dev_ofnode(dev);
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+
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+ pnode = ofnode_get_parent(scu_node);
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+ if (!ofnode_valid(pnode))
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+ return -EINVAL;
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+
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+ priv->map = syscon_node_to_regmap(pnode);
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+ if (IS_ERR(priv->map))
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+ return PTR_ERR(priv->map);
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+
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+ priv->bank_ofs = en7581_rst_ofs;
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+ priv->idx_map = an7583_rst_map;
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+ priv->num_rsts = ARRAY_SIZE(an7583_rst_map);
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return 0;
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}
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+static int airoha_reset_probe(struct udevice *dev)
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+{
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+ if (ofnode_device_is_compatible(dev_ofnode(dev),
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+ "airoha,en7581-scu"))
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+ return an7581_reset_probe(dev);
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+
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+ if (ofnode_device_is_compatible(dev_ofnode(dev),
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+ "airoha,an7583-scu"))
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+ return an7583_reset_probe(dev);
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+
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+ return -ENODEV;
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+}
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+
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U_BOOT_DRIVER(airoha_reset) = {
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.name = "airoha-reset",
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.id = UCLASS_RESET,
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--- /dev/null
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+++ b/include/dt-bindings/reset/airoha,an7583-reset.h
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@@ -0,0 +1,61 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/*
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+ * Copyright (c) 2024 AIROHA Inc
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+ * Author: Christian Marangi <ansuelsmth@gmail.com>
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+ */
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+
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+#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_
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+#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_
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+
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+/* RST_CTRL2 */
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+#define AN7583_XPON_PHY_RST 0
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+#define AN7583_GPON_OLT_RST 1
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+#define AN7583_CPU_TIMER2_RST 2
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+#define AN7583_HSUART_RST 3
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+#define AN7583_UART4_RST 4
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+#define AN7583_UART5_RST 5
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+#define AN7583_I2C2_RST 6
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+#define AN7583_XSI_MAC_RST 7
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+#define AN7583_XSI_PHY_RST 8
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+#define AN7583_NPU_RST 9
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+#define AN7583_TRNG_MSTART_RST 10
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+#define AN7583_DUAL_HSI0_RST 11
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+#define AN7583_DUAL_HSI1_RST 12
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+#define AN7583_DUAL_HSI0_MAC_RST 13
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+#define AN7583_DUAL_HSI1_MAC_RST 14
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+#define AN7583_WDMA_RST 15
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+#define AN7583_WOE0_RST 16
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+#define AN7583_HSDMA_RST 17
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+#define AN7583_TDMA_RST 18
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+#define AN7583_EMMC_RST 19
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+#define AN7583_SOE_RST 20
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+#define AN7583_XFP_MAC_RST 21
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+#define AN7583_MDIO0 22
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+#define AN7583_MDIO1 23
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+/* RST_CTRL1 */
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+#define AN7583_PCM1_ZSI_ISI_RST 24
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+#define AN7583_FE_PDMA_RST 25
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+#define AN7583_FE_QDMA_RST 26
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+#define AN7583_PCM_SPIWP_RST 27
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+#define AN7583_CRYPTO_RST 28
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+#define AN7583_TIMER_RST 29
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+#define AN7583_PCM1_RST 30
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+#define AN7583_UART_RST 31
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+#define AN7583_GPIO_RST 32
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+#define AN7583_GDMA_RST 33
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+#define AN7583_I2C_MASTER_RST 34
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+#define AN7583_PCM2_ZSI_ISI_RST 35
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+#define AN7583_SFC_RST 36
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+#define AN7583_UART2_RST 37
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+#define AN7583_GDMP_RST 38
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+#define AN7583_FE_RST 39
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+#define AN7583_USB_HOST_P0_RST 40
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+#define AN7583_GSW_RST 41
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+#define AN7583_SFC2_PCM_RST 42
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+#define AN7583_PCIE0_RST 43
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+#define AN7583_PCIE1_RST 44
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+#define AN7583_CPU_TIMER_RST 45
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+#define AN7583_PCIE_HB_RST 46
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+#define AN7583_XPON_MAC_RST 47
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+
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+#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ */
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