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EcoNet EN75xx is a big endian MIPS platform used in XPON (fiber), DSL, and SIM (3g/4g) applications. Complete GPL vender SDKs exist for this platform, but are based on Linux 2.6. The bulk of this submission has already been accepted upstream: https://patchwork.kernel.org/project/linux-mips/list/?series=960479&state=* This platform uses a bootloader that is derived from old TrendChip code. This bootloader implements a frustratingly complex Bad Block Table which is implemented here in en75_bmt.c This BMT is not upstreamed because it depends on mtk_bmt framework which likewise is not upstreamed. This BMT system rewrites block indexes in flash and if the bootloader considers it to be corrupted, it will attempt to automatically rebuild on boot. So without implementing the algorithm, you can't safely use the disk at all. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Link: https://github.com/openwrt/openwrt/pull/19021 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
99 lines
3.1 KiB
Diff
99 lines
3.1 KiB
Diff
From 9773c540441c6ae15aefb49e67142e94369dbbc0 Mon Sep 17 00:00:00 2001
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From: Caleb James DeLisle <cjd@cjdns.fr>
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Date: Sun, 30 Mar 2025 17:02:58 +0000
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Subject: [PATCH] dt-bindings: interrupt-controller: Add EcoNet EN751221 INTC
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Document the device tree binding for the interrupt controller in the
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EcoNet EN751221 MIPS SoC.
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Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
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Link: https://lore.kernel.org/all/20250330170306.2584136-3-cjd@cjdns.fr
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---
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.../econet,en751221-intc.yaml | 78 +++++++++++++++++++
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1 file changed, 78 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
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@@ -0,0 +1,78 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: EcoNet EN751221 Interrupt Controller
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+
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+maintainers:
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+ - Caleb James DeLisle <cjd@cjdns.fr>
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+
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+description:
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+ The EcoNet EN751221 Interrupt Controller is a simple interrupt controller
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+ designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can
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+ be routed to either VPE but not both, so to support per-CPU interrupts, a
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+ secondary IRQ number is allocated to control masking/unmasking on VPE#1. For
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+ lack of a better term we call these "shadow interrupts". The assignment of
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+ shadow interrupts is defined by the SoC integrator when wiring the interrupt
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+ lines, so they are configurable in the device tree.
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+
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+allOf:
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+ - $ref: /schemas/interrupt-controller.yaml#
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+
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+properties:
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+ compatible:
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+ const: econet,en751221-intc
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+
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+ reg:
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+ maxItems: 1
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+
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+ "#interrupt-cells":
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+ const: 1
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+
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+ interrupt-controller: true
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+
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+ interrupts:
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+ maxItems: 1
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+ description: Interrupt line connecting this controller to its parent.
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+
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+ econet,shadow-interrupts:
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+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
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+ description:
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+ An array of interrupt number pairs where each pair represents a shadow
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+ interrupt relationship. The first number in each pair is the primary IRQ,
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+ and the second is its shadow IRQ used for VPE#1 control. For example,
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+ <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but
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+ when VPE#1 requests IRQ 8, it will manipulate the IRQ 3 mask bit.
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+ minItems: 1
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+ maxItems: 20
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+ items:
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+ items:
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+ - description: primary per-CPU IRQ
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+ - description: shadow IRQ number
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+
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+required:
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+ - compatible
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+ - reg
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+ - interrupt-controller
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+ - "#interrupt-cells"
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+ - interrupts
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ interrupt-controller@1fb40000 {
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+ compatible = "econet,en751221-intc";
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+ reg = <0x1fb40000 0x100>;
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+
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+
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+ interrupt-parent = <&cpuintc>;
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+ interrupts = <2>;
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+
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+ econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
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+ };
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+...
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