mirror of
https://github.com/LiBwrt-op/ipq50xx.git
synced 2025-12-16 15:01:44 +00:00
qca-ssdk: add support for ipq50xx
The codename fir IPQ50xx is Maple (abbreviated as 'MP'), so let's pass the codename to allow the QCA-SSDK to build for the IPQ50xx SoC. Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by:George Moussalem <george.moussalem@outlook.com>
This commit is contained in:
George Moussalem
Shi JiaYang
parent
389d8bd58a
commit
ddafb9d2a0
@ -47,6 +47,7 @@ MAKE_FLAGS+= \
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SoC=$(CONFIG_TARGET_SUBTARGET) \
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SHELL="$(BASH)" \
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PTP_FEATURE=disable SWCONFIG_FEATURE=disable \
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IN_MP_PHY=FALSE \
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ISISC_ENABLE=disable MHT_ENABLE=disable \
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IN_QCA803X_PHY=FALSE IN_QCA808X_PHY=FALSE \
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IN_MALIBU_PHY=FALSE \
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@ -60,6 +61,9 @@ ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq60xx")
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MAKE_FLAGS+= CHIP_TYPE=CPPE
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endif
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ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq50xx")
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MAKE_FLAGS+= CHIP_TYPE=MP
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endif
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define Build/Compile
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+$(MAKE) $(PKG_JOBS) $(MAKE_FLAGS) -C $(PKG_BUILD_DIR) $(LNX_CONFIG_OPTS)
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@ -0,0 +1,121 @@
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From 15847e1f56b7f9423095cd96fd9d524a41bee814 Mon Sep 17 00:00:00 2001
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From: hzy <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 15:24:07 +0800
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Subject: [PATCH 1/2] hsl_phy: split MP_PHY config
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Signed-off-by: hzy <hzyitc@outlook.com>
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---
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config | 1 +
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make/linux_opt.mk | 5 +++++
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src/adpt/mp/adpt_mp_portctrl.c | 4 ++++
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src/hsl/phy/Makefile | 8 +-------
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src/hsl/phy/hsl_phy.c | 4 ++--
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5 files changed, 13 insertions(+), 9 deletions(-)
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diff --git a/config b/config
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index 99d99dff..1f74e4f8 100644
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--- a/config
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+++ b/config
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@@ -299,6 +299,7 @@ else ifeq (DESS, $(CHIP_TYPE))
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else ifeq (MP, $(CHIP_TYPE))
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IN_QCA803X_PHY=TRUE
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IN_QCA808X_PHY=TRUE
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+ IN_MP_PHY=TRUE
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IN_SFP_PHY=TRUE
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IN_SFP=TRUE
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else ifeq (APPE, $(CHIP_TYPE))
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diff --git a/make/linux_opt.mk b/make/linux_opt.mk
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index 6936b754..66b08ef5 100644
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--- a/make/linux_opt.mk
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+++ b/make/linux_opt.mk
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@@ -183,6 +183,11 @@ endif
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ifeq (TRUE, $(IN_QCA808X_PHY))
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MODULE_CFLAG += -DIN_QCA808X_PHY
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endif
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+
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+ifeq (TRUE, $(IN_MP_PHY))
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+ MODULE_CFLAG += -DIN_MP_PHY
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+endif
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+
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ifeq (TRUE, $(IN_SFP_PHY))
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MODULE_CFLAG += -DIN_SFP_PHY
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endif
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diff --git a/src/adpt/mp/adpt_mp_portctrl.c b/src/adpt/mp/adpt_mp_portctrl.c
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index 2c983fff..db60fc72 100644
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--- a/src/adpt/mp/adpt_mp_portctrl.c
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+++ b/src/adpt/mp/adpt_mp_portctrl.c
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@@ -92,12 +92,15 @@ static sw_error_t
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adpt_mp_port_reset_set(a_uint32_t dev_id, a_uint32_t port_id)
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{
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sw_error_t rv = 0;
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+#ifdef IN_MP_PHY
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a_uint32_t phy_addr;
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hsl_phy_ops_t *phy_drv;
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+#endif
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ADPT_DEV_ID_CHECK(dev_id);
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if (port_id == SSDK_PHYSICAL_PORT1) {
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+#ifdef IN_MP_PHY
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/*internal gephy reset*/
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SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id,
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port_id));
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@@ -107,6 +110,7 @@ adpt_mp_port_reset_set(a_uint32_t dev_id, a_uint32_t port_id)
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SW_RTN_ON_ERROR (rv);
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rv = phy_drv->phy_function_reset(dev_id, phy_addr, PHY_FIFO_RESET);
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SW_RTN_ON_ERROR (rv);
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+#endif
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} else if (port_id == SSDK_PHYSICAL_PORT2) {
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rv = adpt_mp_uniphy_adapter_port_reset(dev_id, port_id);
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} else {
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diff --git a/src/hsl/phy/Makefile b/src/hsl/phy/Makefile
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index 68d0679f..0eae9377 100755
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--- a/src/hsl/phy/Makefile
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+++ b/src/hsl/phy/Makefile
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@@ -23,7 +23,7 @@ ifeq (ISIS, $(CHIP_TYPE))
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SRC_LIST = f1_phy.c
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endif
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-ifeq (MP, $(CHIP_TYPE))
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+ifeq (TRUE, $(IN_MP_PHY))
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SRC_LIST = mpge_phy.c
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ifeq (TRUE, $(IN_LED))
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SRC_LIST += mpge_led.c
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@@ -40,12 +40,6 @@ endif
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ifeq (ALL_CHIP, $(CHIP_TYPE))
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SRC_LIST = f1_phy.c f2_phy.c malibu_phy.c
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-ifneq (,$(filter MP, $(SUPPORT_CHIP)))
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- SRC_LIST += mpge_phy.c
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-ifeq (TRUE, $(IN_LED))
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- SRC_LIST += mpge_led.c
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-endif
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-endif
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endif
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ifeq (NONHK_CHIP, $(CHIP_TYPE))
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diff --git a/src/hsl/phy/hsl_phy.c b/src/hsl/phy/hsl_phy.c
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index f2cf90e2..efab2343 100644
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--- a/src/hsl/phy/hsl_phy.c
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+++ b/src/hsl/phy/hsl_phy.c
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@@ -28,7 +28,7 @@
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#if defined(ATHENA) ||defined(SHIVA) ||defined(HORUS)
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#include <f2_phy.h>
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#endif
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-#ifdef MP
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+#ifdef IN_MP_PHY
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#include "mpge_phy.h"
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#endif
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#ifdef IN_MALIBU_PHY
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@@ -94,7 +94,7 @@ phy_driver_instance_t ssdk_phy_driver[] =
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#else
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{SFP_PHY_CHIP, {0}, NULL, NULL, NULL},
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#endif
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- #ifdef MP
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+ #ifdef IN_MP_PHY
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{MPGE_PHY_CHIP, {0}, NULL, mpge_phy_init, NULL},
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#else
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{MPGE_PHY_CHIP, {0}, NULL, NULL, NULL},
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--
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2.40.1
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@ -0,0 +1,30 @@
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From 01fb404dbda1872ad99cea88bf43313bed30200a Mon Sep 17 00:00:00 2001
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From: hzy <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 15:24:07 +0800
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Subject: [PATCH 2/2] init: MP: allow to ignore reset controlls
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Signed-off-by: hzy <hzyitc@outlook.com>
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---
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src/init/ssdk_clk.c | 6 ++----
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1 file changed, 2 insertions(+), 4 deletions(-)
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diff --git a/src/init/ssdk_clk.c b/src/init/ssdk_clk.c
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index 71e59452..bc244c6e 100644
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--- a/src/init/ssdk_clk.c
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+++ b/src/init/ssdk_clk.c
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@@ -1282,10 +1282,8 @@ ssdk_mp_reset_init(void)
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for (i = 0; i < MP_BCR_RST_MAX; i++) {
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rst = of_reset_control_get(rst_node, mp_rst_ids[i]);
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- if (IS_ERR(rst)) {
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- SSDK_ERROR("%s not exist!\n", mp_rst_ids[i]);
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- return;
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- }
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+ if (IS_ERR(rst))
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+ continue;
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ssdk_gcc_reset(rst, SSDK_RESET_ASSERT);
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msleep(200);
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ssdk_gcc_reset(rst, SSDK_RESET_DEASSERT);
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--
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2.40.1
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@ -0,0 +1,76 @@
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From a4378eb29c7b9dd95601d20f507a2220457f8ede Mon Sep 17 00:00:00 2001
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From: hzy <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 15:24:07 +0800
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Subject: [PATCH 1/2] MP: fix build issues
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Signed-off-by: hzy <hzyitc@outlook.com>
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---
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config | 30 +-----------------------------
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src/adpt/mp/adpt_mp_portctrl.c | 3 ++-
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2 files changed, 3 insertions(+), 30 deletions(-)
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diff --git a/config b/config
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index 1f74e4f8..58d67648 100644
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--- a/config
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+++ b/config
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@@ -374,6 +374,7 @@ ifneq (, $(filter MPPE APPE HPPE CPPE ALL_CHIP, $(CHIP_TYPE)))
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endif
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ifneq (, $(filter MP, $(CHIP_TYPE)))
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+ IN_VSI=TRUE
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IN_UNIPHY=TRUE
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endif
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@@ -436,35 +437,6 @@ endif
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# SDK Features According To Specfic Switch #
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#############################################
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ifeq (MP, $(CHIP_TYPE))
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- ifeq (disable, $(ISISC_ENABLE))
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- IN_ACL=FALSE
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- IN_FDB=FALSE
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- IN_IGMP=FALSE
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- IN_LEAKY=FALSE
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- IN_LED=FALSE
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- IN_MIRROR=FALSE
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- IN_MISC=FALSE
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- IN_PORTVLAN=FALSE
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- IN_QOS=FALSE
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- IN_RATE=FALSE
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- IN_STP=FALSE
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- IN_VLAN=FALSE
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- IN_REDUCED_ACL=FALSE
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- IN_COSMAP=FALSE
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- IN_IP=FALSE
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- IN_NAT=FALSE
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- IN_FLOW=FALSE
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- IN_TRUNK=FALSE
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- IN_RSS_HASH=FALSE
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- IN_SEC=FALSE
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- IN_QM=FALSE
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- IN_PPPOE=FALSE
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- IN_VSI=FALSE
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- IN_SERVCODE=FALSE
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- IN_BM=FALSE
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- IN_SHAPER=FALSE
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- IN_POLICER=FALSE
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- endif
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IN_CTRLPKT=TRUE
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endif
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diff --git a/src/adpt/mp/adpt_mp_portctrl.c b/src/adpt/mp/adpt_mp_portctrl.c
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index db60fc72..c230e214 100644
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--- a/src/adpt/mp/adpt_mp_portctrl.c
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+++ b/src/adpt/mp/adpt_mp_portctrl.c
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@@ -45,7 +45,8 @@ _adpt_mp_gcc_mac_clock_set(a_uint32_t dev_id,
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static a_bool_t
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_adpt_mp_port_phy_connected (a_uint32_t dev_id, fal_port_t port_id)
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{
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- ADPT_DEV_ID_CHECK(dev_id);
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+ if (dev_id >= SW_MAX_NR_DEV)
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+ return A_FALSE;
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/* force port which connect s17c or other device chip*/
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if (hsl_port_feature_get(dev_id, port_id, PHY_F_FORCE | PHY_F_SFP)) {
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--
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2.40.1
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@ -0,0 +1,53 @@
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From a90a9f3e2a21cb87c2cbf2ddb999846aa614e88a Mon Sep 17 00:00:00 2001
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From: hzy <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 15:24:07 +0800
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Subject: [PATCH 2/2] init: replace ioremap_nocache() with ioremap()
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Signed-off-by: hzy <hzyitc@outlook.com>
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---
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src/init/ssdk_clk.c | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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diff --git a/src/init/ssdk_clk.c b/src/init/ssdk_clk.c
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index bc244c6e..dc45691e 100644
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--- a/src/init/ssdk_clk.c
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+++ b/src/init/ssdk_clk.c
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@@ -1183,7 +1183,7 @@ ssdk_mp_tcsr_get(a_uint32_t tcsr_offset, a_uint32_t *tcsr_val)
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{
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void __iomem *tcsr_base = NULL;
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- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
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+ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
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if (!tcsr_base)
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{
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SSDK_ERROR("Failed to map tcsr eth address!\n");
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@@ -1200,7 +1200,7 @@ ssdk_mp_tcsr_set(a_uint32_t tcsr_offset, a_uint32_t tcsr_val)
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{
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void __iomem *tcsr_base = NULL;
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- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
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+ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
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if (!tcsr_base)
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{
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SSDK_ERROR("Failed to map tcsr eth address!\n");
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@@ -1248,7 +1248,7 @@ ssdk_mp_cmnblk_stable_check(void)
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a_uint32_t reg_val;
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int i, loops = 20;
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- pll_lock = ioremap_nocache(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE);
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+ pll_lock = ioremap(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE);
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if (!pll_lock) {
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SSDK_ERROR("Failed to map CMN PLL LOCK register!\n");
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return A_FALSE;
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@@ -1303,7 +1303,7 @@ static void ssdk_cmnblk_pll_src_set(enum cmnblk_pll_src_type pll_source)
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void __iomem *cmn_pll_src_base = NULL;
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a_uint32_t reg_val;
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- cmn_pll_src_base = ioremap_nocache(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE);
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+ cmn_pll_src_base = ioremap(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE);
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if (!cmn_pll_src_base) {
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SSDK_ERROR("Failed to map cmn pll source address!\n");
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return;
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--
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2.40.1
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@ -0,0 +1,61 @@
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From ce9e56a436e486690097cfbdda2d0c11b60db4c2 Mon Sep 17 00:00:00 2001
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From: Ziyang Huang <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 16:40:12 +0800
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Subject: [PATCH 2/2] clk: gcc-ipq5018: hack for qca-ssdk
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Signed-off-by: hzy <hzyitc@outlook.com>
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---
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drivers/clk/qcom/gcc-ipq5018.c | 16 ++++++++--------
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1 file changed, 8 insertions(+), 8 deletions(-)
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diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
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index 4a8511d5f3a5..3d65b7dce59d 100644
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--- a/drivers/clk/qcom/gcc-ipq5018.c
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+++ b/drivers/clk/qcom/gcc-ipq5018.c
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@@ -335,8 +335,8 @@ static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = {
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static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
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{ .index = DT_XO },
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- { .index = DT_GEPHY_RX_CLK },
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- { .index = DT_GEPHY_TX_CLK },
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+ { .name = "gephy_gcc_rx", .index = -1 },
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+ { .name = "gephy_gcc_tx", .index = -1 },
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{ .hw = &ubi32_pll.clkr.hw },
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{ .hw = &gpll0.clkr.hw },
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};
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@@ -351,8 +351,8 @@ static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_
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static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
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{ .index = DT_XO },
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- { .index = DT_GEPHY_TX_CLK },
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- { .index = DT_GEPHY_RX_CLK },
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+ { .name = "gephy_gcc_tx", .index = -1 },
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+ { .name = "gephy_gcc_rx", .index = -1 },
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{ .hw = &ubi32_pll.clkr.hw },
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{ .hw = &gpll0.clkr.hw },
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};
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@@ -367,8 +367,8 @@ static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_
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static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
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{ .index = DT_XO },
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- { .index = DT_UNIPHY_RX_CLK },
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- { .index = DT_UNIPHY_TX_CLK },
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+ { .name = "uniphy_gcc_rx", .index = -1 },
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+ { .name = "uniphy_gcc_tx", .index = -1 },
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{ .hw = &ubi32_pll.clkr.hw },
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{ .hw = &gpll0.clkr.hw },
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};
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@@ -383,8 +383,8 @@ static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll
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static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
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{ .index = DT_XO },
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- { .index = DT_UNIPHY_TX_CLK },
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- { .index = DT_UNIPHY_RX_CLK },
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+ { .name = "uniphy_gcc_tx", .index = -1 },
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+ { .name = "uniphy_gcc_rx", .index = -1 },
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{ .hw = &ubi32_pll.clkr.hw },
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{ .hw = &gpll0.clkr.hw },
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};
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--
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2.40.1
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