mirror of
https://github.com/LiBwrt-op/ipq50xx.git
synced 2025-12-16 15:01:44 +00:00
2113d94260
Add QCN6122 platform support. QCN6122 is a hybrid bus type device which is enumerated as a PCIe device by Q6 and enumerates as AHB device on host. It uses qgic interrupts to notify events to host driver. Used qgic api to convert MSI interrupt to qgic interrupt. Added qmi message to learn bar address from QCN6122. The patch set is refactored and based on below downstream patch: https://git.codelinaro.org/clo/qsdk/oss/system/feeds/wlan-open/-/blob/NHSS.QSDK.12.4.5.r2/mac80211/patches/232-ath11k-qcn6122-support.patch Signed-off-by: Sowmiya Sree Elavalagan <ssreeela@codeaurora.org> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com
70 lines
3.8 KiB
Diff
70 lines
3.8 KiB
Diff
--- a/drivers/net/wireless/ath/ath11k/core.c
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+++ b/drivers/net/wireless/ath/ath11k/core.c
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@@ -820,6 +820,7 @@ static struct ath11k_hw_params ath11k_hw
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.hal_params = &ath11k_hw_hal_params_ipq8074,
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.max_radios = MAX_RADIOS_5018,
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.bdf_addr = 0x4D200000,
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+ .hw_ops = &qcn6122_ops,
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.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
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.regs = &qcn6122_regs,
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.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN6122,
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--- a/drivers/net/wireless/ath/ath11k/hw.c
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+++ b/drivers/net/wireless/ath/ath11k/hw.c
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@@ -1181,6 +1181,46 @@ const struct ath11k_hw_ops ipq5018_ops =
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.get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
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};
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+const struct ath11k_hw_ops qcn6122_ops = {
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+ .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
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+ .wmi_init_config = ath11k_init_wmi_config_ipq8074,
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+ .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
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+ .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
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+ .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid,
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+ .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2,
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+ .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable,
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+ .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu,
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+ .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu,
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+ .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes,
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+ .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status,
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+ .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid,
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+ .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type,
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+ .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type,
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+ .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl,
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+ .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support,
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+ .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld,
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+ .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid,
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+ .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no,
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+ .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len,
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+ .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi,
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+ .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs,
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+ .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw,
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+ .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq,
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+ .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type,
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+ .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss,
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+ .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid,
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+ .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id,
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+ .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end,
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+ .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag,
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+ .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
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+ .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
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+ .reo_setup = ath11k_hw_ipq5018_reo_setup,
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+ .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
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+ .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
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+ .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
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+ .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
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+};
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+
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#define ATH11K_TX_RING_MASK_0 BIT(0)
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#define ATH11K_TX_RING_MASK_1 BIT(1)
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#define ATH11K_TX_RING_MASK_2 BIT(2)
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--- a/drivers/net/wireless/ath/ath11k/hw.h
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+++ b/drivers/net/wireless/ath/ath11k/hw.h
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@@ -284,6 +284,7 @@ extern const struct ath11k_hw_ops qcn907
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extern const struct ath11k_hw_ops wcn6855_ops;
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extern const struct ath11k_hw_ops wcn6750_ops;
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extern const struct ath11k_hw_ops ipq5018_ops;
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+extern const struct ath11k_hw_ops qcn6122_ops;
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extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
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extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
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