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kernel: bump 6.x to latest HEAD
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coolsnowwolf
parent
3bd4d058ca
commit
4f1774d9f9
@ -1,2 +1,2 @@
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LINUX_VERSION-6.12 = .56
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LINUX_KERNEL_HASH-6.12.56 = 55432b2af352f7bf3053c348d8549df2f2deeaa4a361c65d638c2f3b2ca7ec96
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LINUX_VERSION-6.12 = .58
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LINUX_KERNEL_HASH-6.12.58 = 5f1c4c546660a6a81046fdfa6195306bad2c8d17c0d69876dc100a85ad4613ac
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@ -1,2 +1,2 @@
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LINUX_VERSION-6.6 = .115
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LINUX_KERNEL_HASH-6.6.115 = 0a98c05e8d0f6b49fad71b8d779410a0811ea5ae17d81744fe30718633fd9047
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LINUX_VERSION-6.6 = .116
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LINUX_KERNEL_HASH-6.6.116 = a9a59742c29be284c205dc87cbe9b065f9688488132c8f5a6057a5539230a51d
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@ -1,48 +0,0 @@
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From 8680ecfcb4570e5f68a7b1bc237dfdfcf65b389e Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Thu, 21 Dec 2023 18:01:59 +0000
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Subject: [PATCH] media: i2c: adv7180: Use MEDIA_BUS_FMT_UYVY8_1X16 for CSI2
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output
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CSI2 devices are meant to use the 1Xnn formats rather than 2Xnn
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such as MEDIA_BUS_FMT_UYVY8_2X8.
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For devices with ADV7180_FLAG_MIPI_CSI2 set, use
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MEDIA_BUS_FMT_UYVY8_1X16.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/media/i2c/adv7180.c | 12 ++++++++++--
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1 file changed, 10 insertions(+), 2 deletions(-)
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--- a/drivers/media/i2c/adv7180.c
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+++ b/drivers/media/i2c/adv7180.c
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@@ -737,10 +737,15 @@ static int adv7180_enum_mbus_code(struct
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struct v4l2_subdev_state *sd_state,
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struct v4l2_subdev_mbus_code_enum *code)
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{
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+ struct adv7180_state *state = to_state(sd);
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+
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if (code->index != 0)
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return -EINVAL;
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- code->code = MEDIA_BUS_FMT_UYVY8_2X8;
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+ if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
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+ code->code = MEDIA_BUS_FMT_UYVY8_1X16;
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+ else
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+ code->code = MEDIA_BUS_FMT_UYVY8_2X8;
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return 0;
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}
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@@ -750,7 +755,10 @@ static int adv7180_mbus_fmt(struct v4l2_
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{
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struct adv7180_state *state = to_state(sd);
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- fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
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+ if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
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+ fmt->code = MEDIA_BUS_FMT_UYVY8_1X16;
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+ else
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+ fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
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fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
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fmt->width = 720;
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fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
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@ -1,98 +0,0 @@
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From 7e58b9c99676d641ef76edd9c097f1c3c4e6c464 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Thu, 21 Dec 2023 18:03:34 +0000
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Subject: [PATCH] media: i2c: adv7180: Add support for V4L2_CID_LINK_FREQ
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For CSI2 receivers that need to know the link frequency,
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add it as a control to the driver.
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Interlaced modes are 216Mbp/s or 108MHz, whilst going through
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the I2P to deinterlace gives 432Mb/s or 216MHz.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/media/i2c/adv7180.c | 32 +++++++++++++++++++++++++++++++-
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1 file changed, 31 insertions(+), 1 deletion(-)
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--- a/drivers/media/i2c/adv7180.c
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+++ b/drivers/media/i2c/adv7180.c
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@@ -189,6 +189,16 @@
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/* Initial number of frames to skip to avoid possible garbage */
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#define ADV7180_NUM_OF_SKIP_FRAMES 2
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+enum adv7180_link_freq_idx {
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+ INTERLACED_IDX,
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+ I2P_IDX,
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+};
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+
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+static const s64 adv7180_link_freqs[] = {
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+ [INTERLACED_IDX] = 108000000,
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+ [I2P_IDX] = 216000000,
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+};
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+
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static int dbg_input;
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module_param(dbg_input, int, 0644);
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MODULE_PARM_DESC(dbg_input, "Input number (0-31)");
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@@ -229,6 +239,7 @@ struct adv7180_state {
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const struct adv7180_chip_info *chip_info;
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enum v4l2_field field;
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bool force_bt656_4;
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+ struct v4l2_ctrl *link_freq;
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};
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#define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
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struct adv7180_state, \
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@@ -630,6 +641,9 @@ static int adv7180_s_ctrl(struct v4l2_ct
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if (ret)
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return ret;
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+ if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY)
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+ goto unlock;
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+
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val = ctrl->val;
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switch (ctrl->id) {
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case V4L2_CID_BRIGHTNESS:
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@@ -671,6 +685,7 @@ static int adv7180_s_ctrl(struct v4l2_ct
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ret = -EINVAL;
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}
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+unlock:
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mutex_unlock(&state->mutex);
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return ret;
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}
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@@ -691,7 +706,7 @@ static const struct v4l2_ctrl_config adv
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static int adv7180_init_controls(struct adv7180_state *state)
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{
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- v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
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+ v4l2_ctrl_handler_init(&state->ctrl_hdl, 5);
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v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
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V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
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@@ -717,6 +732,17 @@ static int adv7180_init_controls(struct
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test_pattern_menu);
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}
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+ if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
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+ state->link_freq =
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+ v4l2_ctrl_new_int_menu(&state->ctrl_hdl,
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+ &adv7180_ctrl_ops,
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+ V4L2_CID_LINK_FREQ,
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+ ARRAY_SIZE(adv7180_link_freqs) - 1,
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+ 0, adv7180_link_freqs);
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+ if (state->link_freq)
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+ state->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
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+ }
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+
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state->sd.ctrl_handler = &state->ctrl_hdl;
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if (state->ctrl_hdl.error) {
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int err = state->ctrl_hdl.error;
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@@ -849,6 +875,10 @@ static int adv7180_set_pad_format(struct
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adv7180_set_power(state, false);
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adv7180_set_field_mode(state);
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adv7180_set_power(state, true);
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+ if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
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+ __v4l2_ctrl_s_ctrl(state->link_freq,
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+ (state->field == V4L2_FIELD_NONE) ?
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+ I2P_IDX : INTERLACED_IDX);
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}
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} else {
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framefmt = v4l2_subdev_state_get_format(sd_state, 0);
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@ -1,125 +0,0 @@
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From 9989fcd49c52500a2bf1f6d49411690dec45d2dc Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marko=20M=C3=A4kel=C3=A4?= <marko.makela@iki.fi>
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Date: Sat, 2 Aug 2025 12:47:08 +0300
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Subject: [PATCH] clk: qcom: gcc-ipq6018: rework nss_port5 clock to multiple
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conf
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Rework nss_port5 to use the new multiple configuration implementation
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and correctly fix the clocks for this port under some corner case.
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In OpenWrt, this patch avoids intermittent dmesg errors of the form
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nss_port5_rx_clk_src: rcg didn't update its configuration.
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This is a mechanical, straightforward port of
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commit e88f03230dc07aa3293b6aeb078bd27370bb2594
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("clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf")
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to gcc-ipq6018, with two conflicts resolved: different frequency of the
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P_XO clock source, and only 5 Ethernet ports.
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This was originally developed by JiaY-shi <shi05275@163.com>.
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Link: https://lore.kernel.org/all/20231220221724.3822-4-ansuelsmth@gmail.com/
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Signed-off-by: Marko Mäkelä <marko.makela@iki.fi>
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Tested-by: Marko Mäkelä <marko.makela@iki.fi>
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---
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drivers/clk/qcom/gcc-ipq6018.c | 60 +++++++++++++++++++++-------------
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1 file changed, 38 insertions(+), 22 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq6018.c
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+++ b/drivers/clk/qcom/gcc-ipq6018.c
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@@ -511,15 +511,23 @@ static struct clk_rcg2 apss_ahb_clk_src
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},
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};
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-static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
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- F(24000000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
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- F(25000000, P_UNIPHY0_RX, 5, 0, 0),
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- F(78125000, P_UNIPHY1_RX, 4, 0, 0),
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- F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
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- F(125000000, P_UNIPHY0_RX, 1, 0, 0),
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- F(156250000, P_UNIPHY1_RX, 2, 0, 0),
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- F(312500000, P_UNIPHY1_RX, 1, 0, 0),
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+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
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+ C(P_UNIPHY1_RX, 12.5, 0, 0),
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+ C(P_UNIPHY0_RX, 5, 0, 0),
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+};
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+
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+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
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+ C(P_UNIPHY1_RX, 2.5, 0, 0),
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+ C(P_UNIPHY0_RX, 1, 0, 0),
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+};
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+
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+static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
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+ FMS(24000000, P_XO, 1, 0, 0),
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+ FM(25000000, ftbl_nss_port5_rx_clk_src_25),
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+ FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
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+ FM(125000000, ftbl_nss_port5_rx_clk_src_125),
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+ FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
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+ FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
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{ }
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};
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@@ -547,26 +555,34 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32
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static struct clk_rcg2 nss_port5_rx_clk_src = {
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.cmd_rcgr = 0x68060,
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- .freq_tbl = ftbl_nss_port5_rx_clk_src,
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+ .freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
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.hid_width = 5,
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.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "nss_port5_rx_clk_src",
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.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
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.num_parents = 7,
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- .ops = &clk_rcg2_ops,
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+ .ops = &clk_rcg2_fm_ops,
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},
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};
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-static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
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- F(24000000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
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- F(25000000, P_UNIPHY0_TX, 5, 0, 0),
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- F(78125000, P_UNIPHY1_TX, 4, 0, 0),
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- F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
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- F(125000000, P_UNIPHY0_TX, 1, 0, 0),
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- F(156250000, P_UNIPHY1_TX, 2, 0, 0),
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- F(312500000, P_UNIPHY1_TX, 1, 0, 0),
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+static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
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+ C(P_UNIPHY1_TX, 12.5, 0, 0),
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+ C(P_UNIPHY0_TX, 5, 0, 0),
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+};
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+
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+static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
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+ C(P_UNIPHY1_TX, 2.5, 0, 0),
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+ C(P_UNIPHY0_TX, 1, 0, 0),
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+};
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+
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+static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
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+ FMS(24000000, P_XO, 1, 0, 0),
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+ FM(25000000, ftbl_nss_port5_tx_clk_src_25),
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+ FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
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+ FM(125000000, ftbl_nss_port5_tx_clk_src_125),
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+ FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
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+ FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
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{ }
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};
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@@ -594,14 +610,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32
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static struct clk_rcg2 nss_port5_tx_clk_src = {
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.cmd_rcgr = 0x68068,
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- .freq_tbl = ftbl_nss_port5_tx_clk_src,
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+ .freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
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.hid_width = 5,
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.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "nss_port5_tx_clk_src",
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.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
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.num_parents = 7,
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- .ops = &clk_rcg2_ops,
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+ .ops = &clk_rcg2_fm_ops,
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},
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};
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