diff --git a/target/linux/bcm53xx/Makefile b/target/linux/bcm53xx/Makefile index dc9dc5cb4..8f11a293f 100644 --- a/target/linux/bcm53xx/Makefile +++ b/target/linux/bcm53xx/Makefile @@ -12,7 +12,7 @@ CPU_TYPE:=cortex-a9 SUBTARGETS:=generic KERNEL_PATCHVER:=6.6 -KERNEL_TESTING_PATCHVER:=6.1 +KERNEL_TESTING_PATCHVER:=5.4 define Target/Description Build firmware images for Broadcom based BCM47xx/53xx routers with ARM CPU, *not* MIPS. diff --git a/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm-nsp-ax.dtsi b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm-nsp-ax.dtsi new file mode 100644 index 000000000..77bc508fd --- /dev/null +++ b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm-nsp-ax.dtsi @@ -0,0 +1,71 @@ + +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom Northstar Plus Ax stepping-specific bindings. + * Notable differences from B0+ are the secondary-boot-reg and + * lack of DMA coherency. + */ + +&cpu1 { + secondary-boot-reg = <0xffff042c>; +}; + +&dma { + /delete-property/ dma-coherent; +}; + +&sdio { + /delete-property/ dma-coherent; +}; + +&amac0 { + /delete-property/ dma-coherent; +}; + +&amac1 { + /delete-property/ dma-coherent; +}; + +&amac2 { + /delete-property/ dma-coherent; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&mailbox { + /delete-property/ dma-coherent; +}; + +&xhci { + /delete-property/ dma-coherent; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&ohci0 { + /delete-property/ dma-coherent; +}; + +&i2c0 { + /delete-property/ dma-coherent; +}; + +&sata { + /delete-property/ dma-coherent; +}; + +&pcie0 { + /delete-property/ dma-coherent; +}; + +&pcie1 { + /delete-property/ dma-coherent; +}; + +&pcie2 { + /delete-property/ dma-coherent; +}; diff --git a/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm-nsp.dtsi b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm-nsp.dtsi new file mode 100644 index 000000000..11866cf82 --- /dev/null +++ b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm-nsp.dtsi @@ -0,0 +1,685 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,nsp"; + model = "Broadcom Northstar Plus SoC"; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + ethernet0 = &amac0; + ethernet1 = &amac1; + ethernet2 = &amac2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + enable-method = "brcm,bcm-nsp-smp"; + secondary-boot-reg = <0xffff0fec>; + reg = <0x1>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + mpcore-bus@19000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x00023000>; + #address-cells = <1>; + #size-cells = <1>; + + a9pll: arm_clk@0 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x00000 0x1000>; + }; + + timer@20200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20200 0x100>; + interrupts = ; + clocks = <&periph_clk>; + }; + + twd-timer@20600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20600 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + twd-watchdog@20620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x20620 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: l2-cache@22000 { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + cache-level = <2>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + + axi: axi@18000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x18000000 0x0011c40c>; + #address-cells = <1>; + #size-cells = <1>; + + gpioa: gpio@20 { + compatible = "brcm,nsp-gpio-a"; + reg = <0x0020 0x70>, + <0x3f1c4 0x1c>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <32>; + interrupt-controller; + interrupts = ; + gpio-ranges = <&pinctrl 0 0 32>; + }; + + uart0: serial@300 { + compatible = "ns16550a"; + reg = <0x0300 0x100>; + interrupts = ; + clocks = <&osc>; + status = "disabled"; + }; + + uart1: serial@400 { + compatible = "ns16550a"; + reg = <0x0400 0x100>; + interrupts = ; + clocks = <&osc>; + status = "disabled"; + }; + + dma: dma@20000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&iprocslow>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + sdio: mmc@21000 { + compatible = "brcm,sdhci-iproc-cygnus"; + reg = <0x21000 0x100>; + interrupts = ; + sdhci,auto-cmd12; + clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>; + dma-coherent; + status = "disabled"; + }; + + amac0: ethernet@22000 { + compatible = "brcm,nsp-amac"; + reg = <0x022000 0x1000>, + <0x110000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; + dma-coherent; + status = "disabled"; + }; + + amac1: ethernet@23000 { + compatible = "brcm,nsp-amac"; + reg = <0x023000 0x1000>, + <0x111000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; + dma-coherent; + status = "disabled"; + }; + + amac2: ethernet@24000 { + compatible = "brcm,nsp-amac"; + reg = <0x024000 0x1000>, + <0x112000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; + dma-coherent; + status = "disabled"; + }; + + mailbox: mailbox@25c00 { + compatible = "brcm,iproc-fa2-mbox"; + reg = <0x25c00 0x400>; + interrupts = ; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + dma-coherent; + }; + + nand_controller: nand-controller@26000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x026000 0x600>, + <0x11b408 0x600>, + <0x026f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + + qspi: spi@27200 { + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; + reg = <0x027200 0x184>, + <0x027000 0x124>, + <0x11c408 0x004>, + <0x0273a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", + "intr_status_reg"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overhead", + "mspi_done", + "mspi_halted"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + xhci: usb@29000 { + compatible = "generic-xhci"; + reg = <0x29000 0x1000>; + interrupts = ; + phys = <&usb3_phy>; + phy-names = "usb3-phy"; + dma-coherent; + status = "disabled"; + }; + + ehci0: usb@2a000 { + compatible = "generic-ehci"; + reg = <0x2a000 0x100>; + interrupts = ; + dma-coherent; + status = "disabled"; + }; + + ohci0: usb@2b000 { + compatible = "generic-ohci"; + reg = <0x2b000 0x100>; + interrupts = ; + dma-coherent; + status = "disabled"; + }; + + crypto@2f000 { + compatible = "brcm,spum-nsp-crypto"; + reg = <0x2f000 0x900>; + mboxes = <&mailbox 0>; + }; + + gpiob: gpio@30000 { + compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio"; + reg = <0x30000 0x50>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <4>; + interrupt-controller; + interrupts = ; + }; + + pwm: pwm@31000 { + compatible = "brcm,iproc-pwm"; + reg = <0x31000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + + mdio: mdio@32000 { + compatible = "brcm,iproc-mdio"; + reg = <0x32000 0x8>; + #size-cells = <0>; + #address-cells = <1>; + }; + + mdio-mux@32000 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + reg = <0x32000 0x4>; + mux-mask = <0x200>; + #address-cells = <1>; + #size-cells = <0>; + mdio-parent-bus = <&mdio>; + + mdio_int: mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio_ext: mdio@200 { + reg = <0x200>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + rng: rng@33000 { + compatible = "brcm,bcm-nsp-rng"; + reg = <0x33000 0x14>; + }; + + ccbtimer0: timer@34000 { + compatible = "arm,sp804"; + reg = <0x34000 0x1000>; + interrupts = , + ; + clocks = <&iprocslow>; + clock-names = "apb_pclk"; + }; + + ccbtimer1: timer@35000 { + compatible = "arm,sp804"; + reg = <0x35000 0x1000>; + interrupts = , + ; + clocks = <&iprocslow>; + clock-names = "apb_pclk"; + }; + + srab: srab@36000 { + compatible = "brcm,nsp-srab"; + reg = <0x36000 0x1000>, + <0x3f308 0x8>, + <0x3f410 0xc>; + reg-names = "srab", "mux_config", "sgmii"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "link_state_p0", + "link_state_p1", + "link_state_p2", + "link_state_p3", + "link_state_p4", + "link_state_p5", + "link_state_p7", + "link_state_p8", + "phy", + "ts", + "imp_sleep_timer_p5", + "imp_sleep_timer_p7", + "imp_sleep_timer_p8"; + status = "disabled"; + + /* ports are defined in board DTS */ + }; + + i2c0: i2c@38000 { + compatible = "brcm,iproc-i2c"; + reg = <0x38000 0x50>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + dma-coherent; + status = "disabled"; + }; + + watchdog@39000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x39000 0x1000>; + interrupts = ; + clocks = <&iprocslow>, <&iprocslow>; + clock-names = "wdogclk", "apb_pclk"; + }; + + lcpll0: lcpll0@3f100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x3f100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", "sdio", + "ddr_phy"; + }; + + genpll: genpll@3f140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x3f140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", "ethernetclk", + "usbclk", "iprocfast", "sata1", + "sata2"; + }; + + pinctrl: pinctrl@3f1c0 { + compatible = "brcm,nsp-pinmux"; + reg = <0x3f1c0 0x04>, + <0x30028 0x04>, + <0x3f408 0x04>; + }; + + thermal: thermal@3f2c0 { + compatible = "brcm,ns-thermal"; + reg = <0x3f2c0 0x10>; + #thermal-sensor-cells = <0>; + }; + + sata_phy: sata_phy@40100 { + compatible = "brcm,iproc-nsp-sata-phy"; + reg = <0x40100 0x340>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + + sata_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + sata_phy1: sata-phy@1 { + reg = <1>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + sata: ahci@41000 { + compatible = "brcm,bcm-nsp-ahci"; + reg-names = "ahci", "top-ctrl"; + reg = <0x41000 0x1000>, <0x40020 0x1c>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + dma-coherent; + status = "disabled"; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy0>; + phy-names = "sata-phy"; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy1>; + phy-names = "sata-phy"; + }; + }; + + usb3_phy: usb3-phy@104000 { + compatible = "brcm,ns-bx-usb3-phy"; + reg = <0x104000 0x1000>, + <0x032000 0x1000>; + reg-names = "dmp", "ccb-mii"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; + + dma-coherent; + status = "disabled"; + + msi-parent = <&msi0>; + msi0: msi-controller { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + brcm,pcie-msi-inten; + }; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; + + dma-coherent; + status = "disabled"; + + msi-parent = <&msi1>; + msi1: msi-controller { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + brcm,pcie-msi-inten; + }; + }; + + pcie2: pcie@18014000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18014000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + + linux,pci-domain = <2>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; + + dma-coherent; + status = "disabled"; + + msi-parent = <&msi2>; + msi2: msi-controller { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + brcm,pcie-msi-inten; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + coefficients = <(-556) 418000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; +}; diff --git a/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm53015-meraki-mr26.dts b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm53015-meraki-mr26.dts new file mode 100644 index 000000000..08abfdc63 --- /dev/null +++ b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm53015-meraki-mr26.dts @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Meraki MR26 / Codename: Venom + * + * Copyright (C) 2022 Christian Lamparter + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include + +/ { + compatible = "meraki,mr26", "brcm,bcm53015", "brcm,bcm4708"; + model = "Meraki MR26"; + + memory@0 { + reg = <0x00000000 0x08000000>; + device_type = "memory"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_FAULT; + color = ; + gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; + panic-indicator; + }; + led-1 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + key-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + clock-frequency = <50000000>; + /delete-property/ clocks; +}; + +&uart1 { + status = "disabled"; +}; + +&gmac0 { + status = "okay"; + + nvmem-cells = <&macaddr_board_config_66>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + status = "disabled"; +}; +&gmac2 { + status = "disabled"; +}; +&gmac3 { + status = "disabled"; +}; + +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <0x1>; + #size-cells = <0x1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x200000>; + read-only; + }; + + partition@200000 { + label = "u-boot-env"; + reg = <0x200000 0x200000>; + /* empty */ + }; + + partition@400000 { + label = "u-boot-backup"; + reg = <0x400000 0x200000>; + /* empty */ + }; + + partition@600000 { + label = "u-boot-env-backup"; + reg = <0x600000 0x200000>; + /* empty */ + }; + + partition@800000 { + compatible = "linux,ubi"; + label = "ubi"; + reg = <0x800000 0x7780000>; + + volumes { + ubi-volume-board-config { + volname = "board-config"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_board_config_66: macaddr@66 { + reg = <0x66 0x6>; + }; + }; + }; + }; + }; + }; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "poe"; + }; + + port@5 { + label = "cpu"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@7 { + status = "disabled"; + }; + + port@8 { + status = "disabled"; + }; + }; +}; + +&i2c0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_i2c>; + + clock-frequency = <100000>; + + ina219@40 { + compatible = "ti,ina219"; /* PoE power */ + reg = <0x40>; + shunt-resistor = <60000>; /* = 60 mOhms */ + }; + + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + pagesize = <32>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + /* it's empty */ + }; +}; + +&thermal { + status = "disabled"; + /* does not work, reads 418 degree Celsius */ +}; diff --git a/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi new file mode 100644 index 000000000..c54451dde --- /dev/null +++ b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65 series (Alamo). + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +#include "bcm958625-meraki-mx6x-common.dtsi" + +/ { + keys { + compatible = "gpio-keys-polled"; + autorepeat; + poll-interval = <20>; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* green:wan1-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <0>; + color = ; + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* green:wan1-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <1>; + color = ; + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* green:wan2-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <2>; + color = ; + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* green:wan2-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <3>; + color = ; + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* amber:power */ + function = LED_FUNCTION_FAULT; + color = ; + gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + /* white:status */ + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&axi { + mdio-mux@3f1c0 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + reg = <0x3f1c0 0x4>; + mux-mask = <0x2000>; + mdio-parent-bus = <&mdio_ext>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + phy_port6: phy@0 { + reg = <0>; + }; + + phy_port7: phy@1 { + reg = <1>; + }; + + phy_port8: phy@2 { + reg = <2>; + }; + + phy_port9: phy@3 { + reg = <3>; + }; + + phy_port10: phy@4 { + reg = <4>; + }; + + switch@10 { + compatible = "qca,qca8337"; + reg = <0x10>; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + ethernet = <&sgmii1>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-txclk-falling-edge; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan8"; + phy-handle = <&phy_port6>; + }; + + port@2 { + reg = <2>; + label = "lan9"; + phy-handle = <&phy_port7>; + }; + + port@3 { + reg = <3>; + label = "lan10"; + phy-handle = <&phy_port8>; + }; + + port@4 { + reg = <4>; + label = "lan11"; + phy-handle = <&phy_port9>; + }; + + port@5 { + reg = <5>; + label = "lan12"; + phy-handle = <&phy_port10>; + }; + }; + }; + }; + + mdio-mii@2000 { + reg = <0x2000>; + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + + switch@10 { + compatible = "qca,qca8337"; + reg = <0x10>; + dsa,member = <2 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + ethernet = <&sgmii0>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-txclk-falling-edge; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan3"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan4"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan5"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan6"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "lan7"; + phy-handle = <&phy_port5>; + }; + }; + }; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + dsa,member = <0 0>; + + ports { + port@0 { + label = "wan1"; + reg = <0>; + }; + + port@1 { + label = "wan2"; + reg = <1>; + }; + + sgmii0: port@4 { + label = "sw0"; + reg = <4>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + sgmii1: port@5 { + label = "sw1"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@8 { + ethernet = <&amac2>; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi new file mode 100644 index 000000000..1830844c8 --- /dev/null +++ b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin). + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +#include "bcm958625-meraki-mx6x-common.dtsi" + +/ { + + keys { + compatible = "gpio-keys-polled"; + autorepeat; + poll-interval = <20>; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* green:lan1-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <0>; + color = ; + gpios = <&gpioa 19 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* green:lan1-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <1>; + color = ; + gpios = <&gpioa 18 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* green:lan2-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <2>; + color = ; + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* green:lan2-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <3>; + color = ; + gpios = <&gpioa 20 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* green:lan3-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <4>; + color = ; + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; + }; + + led-5 { + /* green:lan3-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <5>; + color = ; + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; + }; + + led-6 { + /* green:lan4-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <6>; + color = ; + gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; + }; + + led-7 { + /* green:lan4-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <7>; + color = ; + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; + }; + + led-8 { + /* green:wan-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <8>; + color = ; + gpios = <&gpioa 30 GPIO_ACTIVE_LOW>; + }; + + led-9 { + /* green:wan-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <9>; + color = ; + gpios = <&gpioa 29 GPIO_ACTIVE_LOW>; + }; + + led-a { + /* amber:power */ + function = LED_FUNCTION_FAULT; + color = ; + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + }; + + led-b { + /* white:status */ + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + port@0 { + label = "lan1"; + reg = <0>; + }; + + port@1 { + label = "lan2"; + reg = <1>; + }; + + port@2 { + label = "lan3"; + reg = <2>; + }; + + port@3 { + label = "lan4"; + reg = <3>; + }; + + port@4 { + label = "wan"; + reg = <4>; + }; + + port@8 { + ethernet = <&amac2>; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts new file mode 100644 index 000000000..9944566c1 --- /dev/null +++ b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" +#include "bcm-nsp-ax.dtsi" + +/ { + model = "Cisco Meraki MX64(A0)"; + compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-mx64.dts b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-mx64.dts new file mode 100644 index 000000000..06939438e --- /dev/null +++ b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-mx64.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64"; + compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-mx65.dts b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-mx65.dts new file mode 100644 index 000000000..d1b684dcd --- /dev/null +++ b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-mx65.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-alamo.dtsi" + +/ { + model = "Cisco Meraki MX65"; + compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi new file mode 100644 index 000000000..7e71aecb7 --- /dev/null +++ b/target/linux/bcm53xx/files-5.4/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +#include "bcm-nsp.dtsi" +#include +#include +#include + +/ { + pwm-leds { + compatible = "pwm-leds"; + + led-1 { + function = LED_FUNCTION_INDICATOR; + color = ; + pwms = <&pwm 1 50000 0>; + max-brightness = <255>; + }; + + led-2 { + function = LED_FUNCTION_POWER; + color = ; + pwms = <&pwm 2 50000 0>; + max-brightness = <255>; + }; + + led-3 { + function = LED_FUNCTION_INDICATOR; + color = ; + pwms = <&pwm 3 50000 0>; + max-brightness = <255>; + }; + }; +}; + +&amac2 { + status = "okay"; + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; + }; + }; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "shmoo"; + reg = <0x80000 0x80000>; + read-only; + }; + + partition@100000 { + label = "bootkernel1"; + reg = <0x100000 0x300000>; + }; + + partition@400000 { + label = "nvram"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "bootkernel2"; + reg = <0x500000 0x300000>; + }; + + partition@800000 { + label = "ubi"; + reg = <0x800000 0x3f700000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_leds>; + + pwm_leds: pwm_leds { + function = "pwm"; + groups = "pwm1_grp", "pwm2_grp", "pwm3_grp"; + }; +}; + +&pwm { + status = "okay"; +}; + +&uart0 { + clock-frequency = <62500000>; + status = "okay"; +}; diff --git a/target/linux/bcm53xx/image/Makefile b/target/linux/bcm53xx/image/Makefile index 509ee3937..75f744381 100644 --- a/target/linux/bcm53xx/image/Makefile +++ b/target/linux/bcm53xx/image/Makefile @@ -127,7 +127,11 @@ define Build/dwl8610ap-image mv $@.new $@ endef +ifdef CONFIG_LINUX_5_4 +DTS_DIR := $(DTS_DIR) +else DTS_DIR := $(DTS_DIR)/broadcom +endif DEVICE_VARS += ASUS_PRODUCTID DEVICE_VARS += BUFFALO_TAG_PLATFORM BUFFALO_TAG_VERSION BUFFALO_TAG_MINOR diff --git a/target/linux/bcm53xx/patches-5.4/180-usb-xhci-add-support-for-performing-fake-doorbell.patch b/target/linux/bcm53xx/patches-5.4/180-usb-xhci-add-support-for-performing-fake-doorbell.patch index a988d2775..e5609b87c 100644 --- a/target/linux/bcm53xx/patches-5.4/180-usb-xhci-add-support-for-performing-fake-doorbell.patch +++ b/target/linux/bcm53xx/patches-5.4/180-usb-xhci-add-support-for-performing-fake-doorbell.patch @@ -78,7 +78,7 @@ it on BCM4708 family. + } + + /* Free virt device */ -+ xhci_free_virt_device(xhci, slot_id); ++ xhci_disable_and_free_slot(xhci, slot_id); + + /* We're done if controller is already running */ + if (readl(&xhci->op_regs->command) & CMD_RUN) diff --git a/target/linux/bcm53xx/patches-5.4/701-b53-add-Tenda-AC9-switch-reset-workaround.patch b/target/linux/bcm53xx/patches-5.4/701-b53-add-Tenda-AC9-switch-reset-workaround.patch new file mode 100644 index 000000000..1b4cf5f85 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.4/701-b53-add-Tenda-AC9-switch-reset-workaround.patch @@ -0,0 +1,39 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 30 Jul 2025 12:37:12 +0000 +Subject: [PATCH] b53: add Tenda AC9 switch reset workaround +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Avoid switch reset to keep it in a working state. + +Signed-off-by: Rafał Miłecki +--- + drivers/net/phy/b53/b53_priv.h | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/net/phy/b53/b53_priv.h ++++ b/drivers/net/phy/b53/b53_priv.h +@@ -21,6 +21,7 @@ + + #include + #include ++#include + #include + + struct b53_device; +@@ -318,6 +319,14 @@ static inline int b53_write64(struct b53 + + static inline int b53_switch_get_reset_gpio(struct b53_device *dev) + { ++ /* ++ * Tenda AC9 comes with gpio2=robo_reset but performing switch reset ++ * leaves it in a non-working state. It seems b53 swconfig driver misses ++ * some initialization bit. ++ */ ++ if (of_machine_is_compatible("tenda,ac9")) ++ return -ENOENT; ++ + #ifdef CONFIG_BCM47XX + enum bcm47xx_board board = bcm47xx_board_get(); + diff --git a/target/linux/generic/backport-5.4/906-v6.15-policy-range-validation.patch b/target/linux/generic/backport-5.4/906-v6.15-policy-range-validation.patch new file mode 100644 index 000000000..a833e8391 --- /dev/null +++ b/target/linux/generic/backport-5.4/906-v6.15-policy-range-validation.patch @@ -0,0 +1,148 @@ +--- a/include/net/netlink.h ++++ b/include/net/netlink.h +@@ -184,16 +184,29 @@ + NLA_EXACT_LEN, + NLA_EXACT_LEN_WARN, + NLA_MIN_LEN, ++ NLA_BE16, ++ NLA_BE32, ++ NLA_SINT, ++ NLA_UINT, + __NLA_TYPE_MAX, + }; + + #define NLA_TYPE_MAX (__NLA_TYPE_MAX - 1) + ++struct netlink_range_validation { ++ u64 min, max; ++}; ++ ++struct netlink_range_validation_signed { ++ s64 min, max; ++}; ++ + enum nla_policy_validation { + NLA_VALIDATE_NONE, + NLA_VALIDATE_RANGE, + NLA_VALIDATE_MIN, + NLA_VALIDATE_MAX, ++ NLA_VALIDATE_RANGE_PTR, + NLA_VALIDATE_FUNCTION, + }; + +@@ -252,6 +265,51 @@ + * nested attributes directly inside, while an array has + * the nested attributes at another level down and the + * attributes directly in the nesting don't matter. ++ * NLA_UINT, ++ * NLA_U8, ++ * NLA_U16, ++ * NLA_U32, ++ * NLA_U64, ++ * NLA_BE16, ++ * NLA_BE32, ++ * NLA_SINT, ++ * NLA_S8, ++ * NLA_S16, ++ * NLA_S32, ++ * NLA_S64 The `min' and `max' fields are used depending on the ++ * validation_type field, if that is min/max/range then ++ * the min, max or both are used (respectively) to check ++ * the value of the integer attribute. ++ * Note that in the interest of code simplicity and ++ * struct size both limits are s16, so you cannot ++ * enforce a range that doesn't fall within the range ++ * of s16 - do that using the NLA_POLICY_FULL_RANGE() ++ * or NLA_POLICY_FULL_RANGE_SIGNED() macros instead. ++ * Use the NLA_POLICY_MIN(), NLA_POLICY_MAX() and ++ * NLA_POLICY_RANGE() macros. ++ * NLA_UINT, ++ * NLA_U8, ++ * NLA_U16, ++ * NLA_U32, ++ * NLA_U64 If the validation_type field instead is set to ++ * NLA_VALIDATE_RANGE_PTR, `range' must be a pointer ++ * to a struct netlink_range_validation that indicates ++ * the min/max values. ++ * Use NLA_POLICY_FULL_RANGE(). ++ * NLA_SINT, ++ * NLA_S8, ++ * NLA_S16, ++ * NLA_S32, ++ * NLA_S64 If the validation_type field instead is set to ++ * NLA_VALIDATE_RANGE_PTR, `range_signed' must be a ++ * pointer to a struct netlink_range_validation_signed ++ * that indicates the min/max values. ++ * Use NLA_POLICY_FULL_RANGE_SIGNED(). ++ * ++ * NLA_BINARY If the validation type is like the ones for integers ++ * above, then the min/max length (not value like for ++ * integers) of the attribute is enforced. ++ * + * All other Unused - but note that it's a union + * + * Meaning of `min' and `max' fields, use via NLA_POLICY_MIN, NLA_POLICY_MAX +@@ -317,6 +375,14 @@ + * was added to enforce strict validation from thereon. + */ + u16 strict_start_type; ++ ++ /* private: use NLA_POLICY_*() to set */ ++ const u32 bitfield32_valid; ++ const u32 mask; ++ const char *reject_message; ++ const struct nla_policy *nested_policy; ++ const struct netlink_range_validation *range; ++ const struct netlink_range_validation_signed *range_signed; + }; + }; + +@@ -337,17 +403,48 @@ + #define NLA_POLICY_NESTED_ARRAY(policy) \ + _NLA_POLICY_NESTED_ARRAY(ARRAY_SIZE(policy) - 1, policy) + ++#define __NLA_IS_UINT_TYPE(tp) \ ++ (tp == NLA_U8 || tp == NLA_U16 || tp == NLA_U32 || \ ++ tp == NLA_U64 || tp == NLA_UINT || \ ++ tp == NLA_BE16 || tp == NLA_BE32) ++#define __NLA_IS_SINT_TYPE(tp) \ ++ (tp == NLA_S8 || tp == NLA_S16 || tp == NLA_S32 || tp == NLA_S64 || \ ++ tp == NLA_SINT) ++ + #define __NLA_ENSURE(condition) BUILD_BUG_ON_ZERO(!(condition)) + #define NLA_ENSURE_INT_TYPE(tp) \ + (__NLA_ENSURE(tp == NLA_S8 || tp == NLA_U8 || \ + tp == NLA_S16 || tp == NLA_U16 || \ + tp == NLA_S32 || tp == NLA_U32 || \ + tp == NLA_S64 || tp == NLA_U64) + tp) ++#define NLA_ENSURE_UINT_OR_BINARY_TYPE(tp) \ ++ (__NLA_ENSURE(__NLA_IS_UINT_TYPE(tp) || \ ++ tp == NLA_MSECS || \ ++ tp == NLA_BINARY) + tp) ++#define NLA_ENSURE_SINT_TYPE(tp) \ ++ (__NLA_ENSURE(__NLA_IS_SINT_TYPE(tp)) + tp) ++#define NLA_ENSURE_INT_OR_BINARY_TYPE(tp) \ ++ (__NLA_ENSURE(__NLA_IS_UINT_TYPE(tp) || \ ++ __NLA_IS_SINT_TYPE(tp) || \ ++ tp == NLA_MSECS || \ ++ tp == NLA_BINARY) + tp) + #define NLA_ENSURE_NO_VALIDATION_PTR(tp) \ + (__NLA_ENSURE(tp != NLA_BITFIELD32 && \ + tp != NLA_REJECT && \ + tp != NLA_NESTED && \ + tp != NLA_NESTED_ARRAY) + tp) ++ ++#define NLA_POLICY_FULL_RANGE(tp, _range) { \ ++ .type = NLA_ENSURE_UINT_OR_BINARY_TYPE(tp), \ ++ .validation_type = NLA_VALIDATE_RANGE_PTR, \ ++ .range = _range, \ ++} ++ ++#define NLA_POLICY_FULL_RANGE_SIGNED(tp, _range) { \ ++ .type = NLA_ENSURE_SINT_TYPE(tp), \ ++ .validation_type = NLA_VALIDATE_RANGE_PTR, \ ++ .range_signed = _range, \ ++} + + #define NLA_POLICY_RANGE(tp, _min, _max) { \ + .type = NLA_ENSURE_INT_TYPE(tp), \