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qualcommax: update nss configuration

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This commit is contained in:
coolsnowwolf 2025-08-03 18:30:20 +08:00
parent 014d1373c8
commit 99acf0dbd8
3 changed files with 130 additions and 134 deletions
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66
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-nss.dtsi
View File

@ -22,42 +22,42 @@
nss0: nss@40000000 { nss0: nss@40000000 {
compatible = "qcom,nss"; compatible = "qcom,nss";
interrupts = <0 402 0x1>, <0 401 0x1>, <0 400 0x1>, interrupts = <0 402 0x1>, <0 401 0x1>, <0 400 0x1>,
<0 399 0x1>, <0 398 0x1>, <0 397 0x1>, <0 399 0x1>, <0 398 0x1>, <0 397 0x1>,
<0 396 0x1>, <0 395 0x1>, <0 394 0x1>, <0 396 0x1>, <0 395 0x1>, <0 394 0x1>,
<0 393 0x1>; <0 393 0x1>;
reg = <0x0 0x39000000 0x0 0x1000>, <0x0 0x0b111000 0x0 0x1000>; reg = <0x0 0x39000000 0x0 0x1000>, <0x0 0x0b111000 0x0 0x1000>;
reg-names = "nphys", "qgic-phys"; reg-names = "nphys", "qgic-phys";
clocks = <&gcc GCC_NSS_NOC_CLK>, clocks = <&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>, <&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CFG_CLK>, <&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CFG_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>, <&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>, <&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>, <&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_MEM_NOC_UBI32_CLK>, <&gcc GCC_MEM_NOC_UBI32_CLK>,
<&gcc GCC_NSS_CE_AXI_CLK>, <&gcc GCC_NSS_CE_AXI_CLK>,
<&gcc GCC_NSS_CE_APB_CLK>, <&gcc GCC_NSS_CE_APB_CLK>,
<&gcc GCC_NSSNOC_CE_AXI_CLK>, <&gcc GCC_NSSNOC_CE_AXI_CLK>,
<&gcc GCC_NSSNOC_CE_APB_CLK>, <&gcc GCC_NSSNOC_CE_APB_CLK>,
<&gcc GCC_NSSNOC_UBI0_AHB_CLK>, <&gcc GCC_NSSNOC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_CORE_CLK>, <&gcc GCC_UBI0_CORE_CLK>,
<&gcc GCC_UBI0_AHB_CLK>, <&gcc GCC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_AXI_CLK>, <&gcc GCC_UBI0_AXI_CLK>,
<&gcc GCC_UBI0_NC_AXI_CLK>, <&gcc GCC_UBI0_NC_AXI_CLK>,
<&gcc GCC_UBI0_UTCM_CLK>, <&gcc GCC_UBI0_UTCM_CLK>,
<&gcc GCC_SNOC_NSSNOC_CLK>; <&gcc GCC_SNOC_NSSNOC_CLK>;
clock-names = "nss-noc-clk", "nss-ptp-ref-clk", clock-names = "nss-noc-clk", "nss-ptp-ref-clk",
"nss-csr-clk", "nss-cfg-clk", "nss-csr-clk", "nss-cfg-clk",
"nss-nssnoc-qosgen-ref-clk", "nss-nssnoc-qosgen-ref-clk",
"nss-nssnoc-snoc-clk", "nss-nssnoc-snoc-clk",
"nss-nssnoc-timeout-ref-clk", "nss-nssnoc-timeout-ref-clk",
"nss-mem-noc-ubi32-clk", "nss-mem-noc-ubi32-clk",
"nss-ce-axi-clk", "nss-ce-apb-clk", "nss-ce-axi-clk", "nss-ce-apb-clk",
"nss-nssnoc-ce-axi-clk", "nss-nssnoc-ce-axi-clk",
"nss-nssnoc-ce-apb-clk", "nss-nssnoc-ce-apb-clk",
"nss-nssnoc-ahb-clk", "nss-nssnoc-ahb-clk",
"nss-core-clk", "nss-ahb-clk", "nss-core-clk", "nss-ahb-clk",
"nss-axi-clk", "nss-nc-axi-clk", "nss-axi-clk", "nss-nc-axi-clk",
"nss-utcm-clk", "nss-snoc-nssnoc-clk"; "nss-utcm-clk", "nss-snoc-nssnoc-clk";
qcom,id = <0>; qcom,id = <0>;
qcom,num-queue = <4>; qcom,num-queue = <4>;
qcom,num-irq = <10>; qcom,num-irq = <10>;
@ -184,8 +184,6 @@
reg_offset = <0x80000>; reg_offset = <0x80000>;
qcom,ifpp-enabled; qcom,ifpp-enabled;
qcom,ipue-enabled; qcom,ipue-enabled;
qcom,ofpp-enabled;
qcom,opue-enabled;
}; };
}; };
}; };

2
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ap8220.dts
View File

@ -244,7 +244,7 @@
partition@0 { partition@0 {
label = "rootfs"; label = "rootfs";
reg = <0x0000000 0x8000000>; reg = <0x0 0x0>;
}; };
}; };
}; };

196
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nss.dtsi
View File

@ -22,57 +22,57 @@
nss0: nss@40000000 { nss0: nss@40000000 {
compatible = "qcom,nss"; compatible = "qcom,nss";
interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 379 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 380 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 381 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 382 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 383 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 384 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 385 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 385 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 386 IRQ_TYPE_EDGE_RISING>; <GIC_SPI 386 IRQ_TYPE_EDGE_RISING>;
reg = <0x39000000 0x1000>, reg = <0x39000000 0x1000>,
<0x38000000 0x30000>, <0x38000000 0x30000>,
<0x0b111000 0x1000>; <0x0b111000 0x1000>;
reg-names = "nphys", "vphys", "qgic-phys"; reg-names = "nphys", "vphys", "qgic-phys";
clocks = <&gcc GCC_NSS_NOC_CLK>, clocks = <&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>, <&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CSR_CLK>,
<&gcc GCC_NSS_CFG_CLK>, <&gcc GCC_NSS_CFG_CLK>,
<&gcc GCC_NSS_IMEM_CLK>, <&gcc GCC_NSS_IMEM_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>, <&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>, <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>, <&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>, <&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_NSS_CE_AXI_CLK>, <&gcc GCC_NSS_CE_AXI_CLK>,
<&gcc GCC_NSS_CE_APB_CLK>, <&gcc GCC_NSS_CE_APB_CLK>,
<&gcc GCC_NSSNOC_CE_AXI_CLK>, <&gcc GCC_NSSNOC_CE_AXI_CLK>,
<&gcc GCC_NSSNOC_CE_APB_CLK>, <&gcc GCC_NSSNOC_CE_APB_CLK>,
<&gcc GCC_NSSNOC_UBI0_AHB_CLK>, <&gcc GCC_NSSNOC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_CORE_CLK>, <&gcc GCC_UBI0_CORE_CLK>,
<&gcc GCC_UBI0_AHB_CLK>, <&gcc GCC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_AXI_CLK>, <&gcc GCC_UBI0_AXI_CLK>,
<&gcc GCC_UBI0_MPT_CLK>, <&gcc GCC_UBI0_MPT_CLK>,
<&gcc GCC_UBI0_NC_AXI_CLK>; <&gcc GCC_UBI0_NC_AXI_CLK>;
clock-names = "nss-noc-clk", clock-names = "nss-noc-clk",
"nss-ptp-ref-clk", "nss-ptp-ref-clk",
"nss-csr-clk", "nss-csr-clk",
"nss-cfg-clk", "nss-cfg-clk",
"nss-imem-clk", "nss-imem-clk",
"nss-nssnoc-qosgen-ref-clk", "nss-nssnoc-qosgen-ref-clk",
"nss-mem-noc-nss-axi-clk", "nss-mem-noc-nss-axi-clk",
"nss-nssnoc-snoc-clk", "nss-nssnoc-snoc-clk",
"nss-nssnoc-timeout-ref-clk", "nss-nssnoc-timeout-ref-clk",
"nss-ce-axi-clk", "nss-ce-axi-clk",
"nss-ce-apb-clk", "nss-ce-apb-clk",
"nss-nssnoc-ce-axi-clk", "nss-nssnoc-ce-axi-clk",
"nss-nssnoc-ce-apb-clk", "nss-nssnoc-ce-apb-clk",
"nss-nssnoc-ahb-clk", "nss-nssnoc-ahb-clk",
"nss-core-clk", "nss-core-clk",
"nss-ahb-clk", "nss-ahb-clk",
"nss-axi-clk", "nss-axi-clk",
"nss-mpt-clk", "nss-mpt-clk",
"nss-nc-axi-clk"; "nss-nc-axi-clk";
qcom,id = <0>; qcom,id = <0>;
qcom,num-queue = <4>; qcom,num-queue = <4>;
qcom,num-irq = <10>; qcom,num-irq = <10>;
@ -113,56 +113,56 @@
nss1: nss@40800000 { nss1: nss@40800000 {
compatible = "qcom,nss"; compatible = "qcom,nss";
interrupts = <GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, interrupts = <GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 391 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 391 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 392 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 392 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 393 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 394 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 394 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 395 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 395 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 396 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 396 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 397 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 397 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 398 IRQ_TYPE_EDGE_RISING>; <GIC_SPI 398 IRQ_TYPE_EDGE_RISING>;
reg = <0x39400000 0x1000>, reg = <0x39400000 0x1000>,
<0x38030000 0x30000>, <0x38030000 0x30000>,
<0x0b111000 0x1000>; <0x0b111000 0x1000>;
reg-names = "nphys", "vphys", "qgic-phys"; reg-names = "nphys", "vphys", "qgic-phys";
clocks = <&gcc GCC_NSS_NOC_CLK>, clocks = <&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>, <&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CSR_CLK>,
<&gcc GCC_NSS_CFG_CLK>, <&gcc GCC_NSS_CFG_CLK>,
<&gcc GCC_NSS_IMEM_CLK>, <&gcc GCC_NSS_IMEM_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>, <&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>, <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>, <&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>, <&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_NSS_CE_AXI_CLK>, <&gcc GCC_NSS_CE_AXI_CLK>,
<&gcc GCC_NSS_CE_APB_CLK>, <&gcc GCC_NSS_CE_APB_CLK>,
<&gcc GCC_NSSNOC_CE_AXI_CLK>, <&gcc GCC_NSSNOC_CE_AXI_CLK>,
<&gcc GCC_NSSNOC_CE_APB_CLK>, <&gcc GCC_NSSNOC_CE_APB_CLK>,
<&gcc GCC_NSSNOC_UBI1_AHB_CLK>, <&gcc GCC_NSSNOC_UBI1_AHB_CLK>,
<&gcc GCC_UBI1_CORE_CLK>, <&gcc GCC_UBI1_CORE_CLK>,
<&gcc GCC_UBI1_AHB_CLK>, <&gcc GCC_UBI1_AHB_CLK>,
<&gcc GCC_UBI1_AXI_CLK>, <&gcc GCC_UBI1_AXI_CLK>,
<&gcc GCC_UBI1_MPT_CLK>, <&gcc GCC_UBI1_MPT_CLK>,
<&gcc GCC_UBI1_NC_AXI_CLK>; <&gcc GCC_UBI1_NC_AXI_CLK>;
clock-names = "nss-noc-clk", clock-names = "nss-noc-clk",
"nss-ptp-ref-clk", "nss-ptp-ref-clk",
"nss-csr-clk", "nss-csr-clk",
"nss-cfg-clk", "nss-cfg-clk",
"nss-imem-clk", "nss-imem-clk",
"nss-nssnoc-qosgen-ref-clk", "nss-nssnoc-qosgen-ref-clk",
"nss-mem-noc-nss-axi-clk", "nss-mem-noc-nss-axi-clk",
"nss-nssnoc-snoc-clk", "nss-nssnoc-snoc-clk",
"nss-nssnoc-timeout-ref-clk", "nss-nssnoc-timeout-ref-clk",
"nss-ce-axi-clk", "nss-ce-axi-clk",
"nss-ce-apb-clk", "nss-ce-apb-clk",
"nss-nssnoc-ce-axi-clk", "nss-nssnoc-ce-axi-clk",
"nss-nssnoc-ce-apb-clk", "nss-nssnoc-ce-apb-clk",
"nss-nssnoc-ahb-clk", "nss-nssnoc-ahb-clk",
"nss-core-clk", "nss-core-clk",
"nss-ahb-clk", "nss-ahb-clk",
"nss-axi-clk", "nss-axi-clk",
"nss-mpt-clk", "nss-mpt-clk",
"nss-nc-axi-clk"; "nss-nc-axi-clk";
qcom,id = <1>; qcom,id = <1>;
qcom,num-queue = <4>; qcom,num-queue = <4>;
qcom,num-irq = <9>; qcom,num-irq = <9>;
@ -181,10 +181,10 @@
nss_crypto: qcom,nss_crypto { nss_crypto: qcom,nss_crypto {
compatible = "qcom,nss-crypto"; compatible = "qcom,nss-crypto";
#address-cells = <1>;
#size-cells = <1>;
qcom,max-contexts = <64>; qcom,max-contexts = <64>;
qcom,max-context-size = <32>; qcom,max-context-size = <32>;
#address-cells = <1>;
#size-cells = <1>;
ranges; ranges;
eip197_node { eip197_node {
@ -192,11 +192,11 @@
reg-names = "crypto_pbase"; reg-names = "crypto_pbase";
reg = <0x39800000 0x7ffff>; reg = <0x39800000 0x7ffff>;
clocks = <&gcc GCC_NSS_CRYPTO_CLK>, clocks = <&gcc GCC_NSS_CRYPTO_CLK>,
<&gcc GCC_NSSNOC_CRYPTO_CLK>, <&gcc GCC_NSSNOC_CRYPTO_CLK>,
<&gcc GCC_CRYPTO_PPE_CLK>; <&gcc GCC_CRYPTO_PPE_CLK>;
clock-names = "crypto_clk", clock-names = "crypto_clk",
"crypto_nocclk", "crypto_nocclk",
"crypto_ppeclk"; "crypto_ppeclk";
clock-frequency = /bits/ 64 <600000000 600000000 300000000>; clock-frequency = /bits/ 64 <600000000 600000000 300000000>;
qcom,dma-mask = <0xff>; qcom,dma-mask = <0xff>;
qcom,transform-enabled; qcom,transform-enabled;
@ -263,8 +263,6 @@
reg_offset = <0x80000>; reg_offset = <0x80000>;
qcom,ifpp-enabled; qcom,ifpp-enabled;
qcom,ipue-enabled; qcom,ipue-enabled;
qcom,ofpp-enabled;
qcom,opue-enabled;
}; };
}; };
}; };