mirror of
https://github.com/Heleguo/lede.git
synced 2025-12-16 19:01:32 +00:00
rockchip: sync rk3528 support with upstream
This commit is contained in:
aiamadeus
parent
07d0c1621f
commit
d339d73f03
@ -371,7 +371,6 @@
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mmc-pwrseq = <&sdio_pwrseq>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
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post-power-on-delay-ms = <50>;
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non-removable;
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sd-uhs-sdr104;
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status = "okay";
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@ -395,9 +394,6 @@
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
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rockchip,default-sample-phase = <90>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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vmmc-supply = <&vcc3v3_sd>;
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vqmmc-supply = <&vccio_sd>;
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@ -119,25 +119,25 @@
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vdd_arm: vdd-arm {
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compatible = "pwm-regulator";
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pwms = <&pwm1 0 5000 1>;
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pwm-supply = <&vcc5v0_sys>;
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regulator-name = "vdd_arm";
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regulator-min-microvolt = <746000>;
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regulator-max-microvolt = <1201000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-settling-time-up-us = <250>;
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pwm-supply = <&vcc5v0_sys>;
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};
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vdd_logic: vdd-logic {
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compatible = "pwm-regulator";
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pwms = <&pwm2 0 5000 1>;
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pwm-supply = <&vcc5v0_sys>;
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regulator-name = "vdd_logic";
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regulator-min-microvolt = <705000>;
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regulator-max-microvolt = <1006000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-settling-time-up-us = <250>;
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pwm-supply = <&vcc5v0_sys>;
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};
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};
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@ -266,9 +266,6 @@
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
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rockchip,default-sample-phase = <90>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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vmmc-supply = <&vcc3v3_sd>;
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vqmmc-supply = <&vccio_sd>;
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@ -131,25 +131,25 @@
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vdd_arm: vdd-arm {
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compatible = "pwm-regulator";
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pwms = <&pwm1 0 5000 1>;
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pwm-supply = <&vcc5v0_sys>;
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regulator-name = "vdd_arm";
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regulator-min-microvolt = <746000>;
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regulator-max-microvolt = <1201000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-settling-time-up-us = <250>;
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pwm-supply = <&vcc5v0_sys>;
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};
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vdd_logic: vdd-logic {
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compatible = "pwm-regulator";
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pwms = <&pwm2 0 5000 1>;
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pwm-supply = <&vcc5v0_sys>;
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regulator-name = "vdd_logic";
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regulator-min-microvolt = <705000>;
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regulator-max-microvolt = <1006000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-settling-time-up-us = <250>;
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pwm-supply = <&vcc5v0_sys>;
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};
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};
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@ -287,9 +287,6 @@
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
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rockchip,default-sample-phase = <90>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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vmmc-supply = <&vcc3v3_sd>;
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vqmmc-supply = <&vccio_sd>;
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@ -311,9 +311,6 @@
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
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rockchip,default-sample-phase = <90>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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vmmc-supply = <&vcc_3v3>;
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vqmmc-supply = <&vccio_sd>;
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@ -41,7 +41,6 @@
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serial7 = &uart7;
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spi0 = &spi0;
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spi1 = &spi1;
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spi2 = &sfc;
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};
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cpus {
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@ -137,31 +136,31 @@
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <825000 825000 1100000>;
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opp-microvolt = <850000 850000 1100000>;
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clock-latency-ns = <40000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <825000 825000 1100000>;
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opp-microvolt = <850000 850000 1100000>;
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clock-latency-ns = <40000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <962500 962500 1100000>;
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opp-microvolt = <925000 925000 1100000>;
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clock-latency-ns = <40000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <1012500 1012500 1100000>;
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opp-microvolt = <975000 975000 1100000>;
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clock-latency-ns = <40000>;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1062500 1062500 1100000>;
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opp-microvolt = <1037500 1037500 1100000>;
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clock-latency-ns = <40000>;
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};
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@ -258,7 +257,8 @@
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};
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pcie2x1: pcie@fe4f0000 {
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compatible = "rockchip,rk3528-pcie", "rockchip,rk3568-pcie";
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compatible = "rockchip,rk3528-pcie",
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"rockchip,rk3568-pcie";
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reg = <0x0 0xfe000000 0x0 0x400000>,
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<0x0 0xfe4f0000 0x0 0x010000>,
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<0x0 0xfc000000 0x0 0x100000>;
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@ -272,13 +272,10 @@
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interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err";
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bus-range = <0x0 0xff>;
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clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
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<&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>,
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<&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>,
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<&cru PCLK_PCIE_PHY>;
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clock-names = "aclk", "hclk_slv",
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"hclk_dbi", "pclk_cru",
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"aux", "pclk",
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"pipe";
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<&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>,
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<&cru CLK_PCIE_AUX>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk", "aux";
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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@ -297,9 +294,8 @@
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ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x00100000
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0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x01e00000
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0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
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resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>,
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<&cru SRST_PRESETN_CRU_PCIE>;
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reset-names = "pwr", "periph", "preset_cru";
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resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>;
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reset-names = "pwr", "pipe";
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#address-cells = <3>;
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#size-cells = <2>;
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status = "disabled";
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@ -686,14 +682,14 @@
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compatible = "rockchip,rk3528-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff9c0000 0x0 0x1000>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>, <&cru SCLK_IN_SPI0>;
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clock-names = "spiclk", "apb_pclk", "sclk_in";
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dmas = <&dmac 25>, <&dmac 24>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_csn0 &spi0_csn1 &spi0_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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@ -701,14 +697,14 @@
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compatible = "rockchip,rk3528-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff9d0000 0x0 0x1000>;
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>, <&cru SCLK_IN_SPI1>;
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clock-names = "spiclk", "apb_pclk", "sclk_in";
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dmas = <&dmac 31>, <&dmac 30>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_csn0 &spi1_csn1 &spi1_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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@ -917,8 +913,8 @@
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reg = <0x0 0xffa90000 0x0 0x10>;
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clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
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clock-names = "pwm", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0m0_pins>;
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pinctrl-names = "active";
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -928,8 +924,8 @@
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reg = <0x0 0xffa90010 0x0 0x10>;
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clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
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clock-names = "pwm", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1m0_pins>;
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pinctrl-names = "active";
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -939,8 +935,8 @@
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reg = <0x0 0xffa90020 0x0 0x10>;
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clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
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clock-names = "pwm", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm2m0_pins>;
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pinctrl-names = "active";
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -950,8 +946,8 @@
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reg = <0x0 0xffa90030 0x0 0x10>;
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clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
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clock-names = "pwm", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm3m0_pins>;
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pinctrl-names = "active";
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -961,8 +957,8 @@
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reg = <0x0 0xffa98000 0x0 0x10>;
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clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
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clock-names = "pwm", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm4m0_pins>;
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pinctrl-names = "active";
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -972,8 +968,8 @@
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reg = <0x0 0xffa98010 0x0 0x10>;
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clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
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clock-names = "pwm", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm5m0_pins>;
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pinctrl-names = "active";
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -983,8 +979,8 @@
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reg = <0x0 0xffa98020 0x0 0x10>;
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clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
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clock-names = "pwm", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm6m0_pins>;
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pinctrl-names = "active";
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -994,8 +990,8 @@
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reg = <0x0 0xffa98030 0x0 0x10>;
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clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
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clock-names = "pwm", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm7m0_pins>;
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pinctrl-names = "active";
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -1084,7 +1080,8 @@
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};
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pdm: pdm@ffbb0000 {
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compatible = "rockchip,rk3528-pdm", "rockchip,rk3568-pdm";
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compatible = "rockchip,rk3528-pdm",
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"rockchip,rk3568-pdm";
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reg = <0x0 0xffbb0000 0x0 0x1000>;
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clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
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clock-names = "pdm_clk", "pdm_hclk";
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@ -1102,7 +1099,8 @@
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};
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spdif: spdif@ffbc0000 {
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compatible = "rockchip,rk3528-spdif", "rockchip,rk3568-spdif";
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compatible = "rockchip,rk3528-spdif",
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"rockchip,rk3568-spdif";
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reg = <0x0 0xffbc0000 0x0 0x1000>;
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interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "mclk", "hclk";
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@ -1,19 +0,0 @@
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--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
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+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@@ -307,9 +307,13 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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- ret = reset_control_assert(rockchip->rst);
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- if (ret)
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- return ret;
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+ if (of_machine_is_compatible("rockchip,rk3528")) {
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+ dev_warn(dev, "RockChip refuses to admit it's a bug\n");
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+ } else {
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+ ret = reset_control_assert(rockchip->rst);
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+ if (ret)
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+ return ret;
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+ }
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/* DON'T MOVE ME: must be enable before PHY init */
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rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
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@ -1,19 +0,0 @@
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--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
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+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@@ -521,9 +521,13 @@ static int rockchip_pcie_probe(struct pl
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if (ret)
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return ret;
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- ret = reset_control_assert(rockchip->rst);
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- if (ret)
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- return ret;
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+ if (of_machine_is_compatible("rockchip,rk3528")) {
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+ dev_warn(dev, "RockChip refuses to admit it's a bug\n");
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+ } else {
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+ ret = reset_control_assert(rockchip->rst);
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+ if (ret)
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+ return ret;
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+ }
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/* DON'T MOVE ME: must be enable before PHY init */
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rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
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@ -1,19 +0,0 @@
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--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
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+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@@ -307,9 +307,13 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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- ret = reset_control_assert(rockchip->rst);
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- if (ret)
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- return ret;
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+ if (of_machine_is_compatible("rockchip,rk3528")) {
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+ dev_warn(dev, "RockChip refuses to admit it's a bug\n");
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+ } else {
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+ ret = reset_control_assert(rockchip->rst);
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+ if (ret)
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+ return ret;
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+ }
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/* DON'T MOVE ME: must be enable before PHY init */
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rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
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