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https://github.com/Heleguo/lede.git
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rockchip: add FriendlyElec NanoPi R76S (RK3576) support
This commit is contained in:
coolsnowwolf
parent
0dad298caf
commit
f2f51b561c
@ -42,7 +42,8 @@ define U-Boot/evb-rk3576
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BUILD_SUBTARGET:=armv8
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NAME:=RK3576 Evaluation
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BUILD_DEVICES:= \
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armsom_sige5
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armsom_sige5 \
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friendlyarm_nanopi-r76s
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DEPENDS:=+PACKAGE_u-boot-evb-rk3576:rkbin-rk3576
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ATF:=rk3576_bl31_v1.12.elf
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DDR:=rk3576_ddr_lp4_2112MHz_lp5_2736MHz_v1.08.bin
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@ -41,6 +41,11 @@ friendlyarm,nanopi-r6s)
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ucidef_set_led_netdev "lan1" "LAN1" "green:lan-1" "eth2"
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ucidef_set_led_netdev "lan2" "LAN2" "green:lan-2" "eth0"
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;;
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friendlyarm,nanopi-r76s)
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ucidef_set_led_default "power" "POWER" "red:power" "1"
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ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1"
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ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0"
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;;
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hinlink,opc-h28k)
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ucidef_set_led_netdev "wan" "WAN" "blue:wan" "eth1"
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ucidef_set_led_netdev "lan" "LAN" "amber:lan" "eth0"
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@ -38,6 +38,7 @@ rockchip_setup_interfaces()
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firefly,rk3568-roc-pc|\
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friendlyarm,nanopi-r3s|\
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friendlyarm,nanopi-r5c|\
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friendlyarm,nanopi-r76s|\
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friendlyarm,nanopc-t6|\
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hinlink,opc-h28k|\
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mmbox,anas3035|\
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@ -141,6 +142,7 @@ rockchip_setup_macs()
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friendlyarm,nanopi-r5s|\
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friendlyarm,nanopi-r6c|\
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friendlyarm,nanopi-r6s|\
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friendlyarm,nanopi-r76s|\
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sharevdi,guangmiao-g4c)
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wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1)
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lan_mac=$(macaddr_add "$wan_mac" +1)
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@ -1,814 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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thermal_zones: thermal-zones {
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/* sensor near the center of the SoC */
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package_thermal: package-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsadc 0>;
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trips {
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package_crit: package-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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/* sensor for cluster1 (big Cortex-A72 cores) */
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bigcore_thermal: bigcore-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsadc 1>;
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trips {
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bigcore_alert: bigcore-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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bigcore_crit: bigcore-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&bigcore_alert>;
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cooling-device =
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<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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/* sensor for cluster0 (little Cortex-A53 cores) */
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littlecore_thermal: littlecore-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsadc 2>;
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trips {
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littlecore_alert: littlecore-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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littlecore_crit: littlecore-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&littlecore_alert>;
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cooling-device =
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<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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gpu_thermal: gpu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsadc 3>;
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trips {
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gpu_alert: gpu-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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gpu_crit: gpu-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&gpu_alert>;
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cooling-device =
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<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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npu_thermal: npu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsadc 4>;
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trips {
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npu_crit: npu-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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ddr_thermal: ddr-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsadc 5>;
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trips {
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ddr_crit: ddr-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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};
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soc {
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hdptxphy_grf: syscon@26032000 {
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compatible = "rockchip,rk3576-hdptxphy-grf", "syscon";
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reg = <0x0 0x26032000 0x0 0x100>;
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clocks = <&cru PCLK_PMUPHY_ROOT>;
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};
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pcie0: pcie@2a200000 {
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compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xf>;
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clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
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<&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
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<&cru CLK_PCIE0_AUX>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux";
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device_type = "pci";
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interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie0_intc 0>,
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<0 0 0 2 &pcie0_intc 1>,
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<0 0 0 3 &pcie0_intc 2>,
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<0 0 0 4 &pcie0_intc 3>;
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linux,pci-domain = <0>;
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num-ib-windows = <8>;
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num-viewport = <8>;
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num-ob-windows = <2>;
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max-link-speed = <2>;
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num-lanes = <1>;
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phys = <&combphy0_ps PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3576_PD_PHP>;
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ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
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0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
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0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
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reg = <0x0 0x22000000 0x0 0x00400000>,
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<0x0 0x2a200000 0x0 0x00010000>,
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<0x0 0x20000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
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reset-names = "pwr", "pipe";
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status = "disabled";
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pcie0_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
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};
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};
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pcie1: pcie@2a210000 {
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compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x20 0x2f>;
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clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
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<&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
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<&cru CLK_PCIE1_AUX>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux";
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device_type = "pci";
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interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie1_intc 0>,
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<0 0 0 2 &pcie1_intc 1>,
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<0 0 0 3 &pcie1_intc 2>,
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<0 0 0 4 &pcie1_intc 3>;
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linux,pci-domain = <1>;
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num-ib-windows = <8>;
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num-viewport = <8>;
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num-ob-windows = <2>;
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max-link-speed = <2>;
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num-lanes = <1>;
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phys = <&combphy1_psu PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3576_PD_SUBPHP>;
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ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
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0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
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0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
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reg = <0x0 0x22400000 0x0 0x00400000>,
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<0x0 0x2a210000 0x0 0x00010000>,
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<0x0 0x21000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
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reset-names = "pwr", "pipe";
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status = "disabled";
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pcie1_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
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};
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};
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vop: vop@27d00000 {
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compatible = "rockchip,rk3576-vop";
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reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
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reg-names = "vop", "gamma-lut";
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interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys",
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"vp0",
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"vp1",
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"vp2";
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clocks = <&cru ACLK_VOP>,
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<&cru HCLK_VOP>,
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<&cru DCLK_VP0>,
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<&cru DCLK_VP1>,
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<&cru DCLK_VP2>,
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<&hdptxphy>;
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clock-names = "aclk",
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"hclk",
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"dclk_vp0",
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"dclk_vp1",
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"dclk_vp2",
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"pll_hdmiphy0";
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iommus = <&vop_mmu>;
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power-domains = <&power RK3576_PD_VOP>;
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rockchip,grf = <&sys_grf>;
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rockchip,pmu = <&pmu>;
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status = "disabled";
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vop_out: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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vp0: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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vp1: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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vp2: port@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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};
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};
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vop_mmu: iommu@27d07e00 {
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compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
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reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>;
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interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vop_mmu";
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clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
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clock-names = "aclk", "iface";
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#iommu-cells = <0>;
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power-domains = <&power RK3576_PD_VOP>;
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status = "disabled";
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};
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hdmi: hdmi@27da0000 {
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compatible = "rockchip,rk3576-dw-hdmi-qp";
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reg = <0x0 0x27da0000 0x0 0x20000>;
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clocks = <&cru PCLK_HDMITX0>,
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<&cru CLK_HDMITX0_EARC>,
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<&cru CLK_HDMITX0_REF>,
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<&cru MCLK_SAI6_8CH>,
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<&cru CLK_HDMITXHDP>,
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<&cru HCLK_VO0_ROOT>;
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clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
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interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "avp", "cec", "earc", "main", "hpd";
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phys = <&hdptxphy>;
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phy-names = "hdmi";
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>;
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power-domains = <&power RK3576_PD_VO0>;
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resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>;
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reset-names = "ref", "hdp";
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rockchip,grf = <&ioc_grf>;
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rockchip,vo-grf = <&vo0_grf>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_in: port@0 {
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reg = <0>;
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};
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hdmi_out: port@1 {
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reg = <1>;
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};
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};
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};
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hdptxphy: hdmiphy@2b000000 {
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compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy";
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reg = <0x0 0x2b000000 0x0 0x2000>;
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clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>;
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clock-names = "ref", "apb";
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#clock-cells = <0>;
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resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>,
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<&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>;
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reset-names = "apb", "init", "cmn", "lane";
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rockchip,grf = <&hdptxphy_grf>;
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#phy-cells = <0>;
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status = "disabled";
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};
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tsadc: tsadc@2ae70000 {
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compatible = "rockchip,rk3576-tsadc";
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reg = <0x0 0x2ae70000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
||||
clock-names = "tsadc", "apb_pclk";
|
||||
assigned-clocks = <&cru CLK_TSADC>;
|
||||
assigned-clock-rates = <2000000>;
|
||||
resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
|
||||
reset-names = "tsadc-apb", "tsadc";
|
||||
#thermal-sensor-cells = <1>;
|
||||
rockchip,hw-tshut-temp = <120000>;
|
||||
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tsadc@0 {
|
||||
reg = <0>;
|
||||
nvmem-cells = <&soc_tsadc_trim_l>, <&soc_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
};
|
||||
tsadc@1 {
|
||||
reg = <1>;
|
||||
nvmem-cells = <&bigcore_tsadc_trim_l>, <&bigcore_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
};
|
||||
tsadc@2 {
|
||||
reg = <2>;
|
||||
nvmem-cells = <&litcore_tsadc_trim_l>, <&litcore_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
};
|
||||
tsadc@3 {
|
||||
reg = <3>;
|
||||
nvmem-cells = <&ddr_tsadc_trim_l>, <&ddr_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
};
|
||||
tsadc@4 {
|
||||
reg = <4>;
|
||||
nvmem-cells = <&npu_tsadc_trim_l>, <&npu_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
};
|
||||
tsadc@5 {
|
||||
reg = <5>;
|
||||
nvmem-cells = <&gpu_tsadc_trim_l>, <&gpu_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
};
|
||||
};
|
||||
|
||||
pwm0_2ch_0: pwm@27330000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x27330000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#pwm-cells = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0m0_ch0>;
|
||||
clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
||||
clock-names = "pwm", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0_2ch_1: pwm@27331000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x27331000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#pwm-cells = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0m0_ch1>;
|
||||
clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
||||
clock-names = "pwm", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1_6ch_0: pwm@2add0000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2add0000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
clock-names = "pwm", "pclk", "osc";
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1m0_ch0>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1_6ch_1: pwm@2add1000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2add1000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
clock-names = "pwm", "pclk", "osc";
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1m0_ch1>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1_6ch_2: pwm@2add2000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2add2000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
clock-names = "pwm", "pclk", "osc";
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1m0_ch2>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1_6ch_3: pwm@2add3000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2add3000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
clock-names = "pwm", "pclk", "osc";
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1m0_ch3>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1_6ch_4: pwm@2add4000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2add4000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
clock-names = "pwm", "pclk", "osc";
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1m0_ch4>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1_6ch_5: pwm@2add5000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2add5000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
clock-names = "pwm", "pclk", "osc";
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1m0_ch5>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_0: pwm@2ade0000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade0000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch0>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_1: pwm@2ade1000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade1000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch1>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_2: pwm@2ade2000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade2000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch2>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_3: pwm@2ade3000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade3000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch3>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_4: pwm@2ade4000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade4000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch4>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_5: pwm@2ade5000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade5000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch5>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_6: pwm@2ade6000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade6000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch6>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_7: pwm@2ade7000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade7000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch7>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai0: sai@2a600000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x2a600000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac0 0>, <&dmac0 1>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3576_PD_AUDIO>;
|
||||
resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>;
|
||||
reset-names = "m", "h";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sai0m0_lrck
|
||||
&sai0m0_sclk
|
||||
&sai0m0_sdi0
|
||||
&sai0m0_sdi1
|
||||
&sai0m0_sdi2
|
||||
&sai0m0_sdi3
|
||||
&sai0m0_sdo0
|
||||
&sai0m0_sdo1
|
||||
&sai0m0_sdo2
|
||||
&sai0m0_sdo3>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai1: sai@2a610000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x2a610000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac0 2>, <&dmac0 3>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3576_PD_AUDIO>;
|
||||
resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>;
|
||||
reset-names = "m", "h";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sai1m0_lrck
|
||||
&sai1m0_sclk
|
||||
&sai1m0_sdi0
|
||||
&sai1m0_sdo0
|
||||
&sai1m0_sdo1
|
||||
&sai1m0_sdo2
|
||||
&sai1m0_sdo3>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai2: sai@2a620000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x2a620000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac1 0>, <&dmac1 1>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3576_PD_AUDIO>;
|
||||
resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>;
|
||||
reset-names = "m", "h";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sai2m0_lrck
|
||||
&sai2m0_sclk
|
||||
&sai2m0_sdi
|
||||
&sai2m0_sdo>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai3: sai@2a630000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x2a630000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac1 2>, <&dmac1 3>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3576_PD_AUDIO>;
|
||||
resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>;
|
||||
reset-names = "m", "h";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sai3m0_lrck
|
||||
&sai3m0_sclk
|
||||
&sai3m0_sdi
|
||||
&sai3m0_sdo>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai4: sai@2a640000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x2a640000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac2 0>, <&dmac2 1>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3576_PD_AUDIO>;
|
||||
resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>;
|
||||
reset-names = "m", "h";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sai4m0_lrck
|
||||
&sai4m0_sclk
|
||||
&sai4m0_sdi
|
||||
&sai4m0_sdo>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai5: sai@27d40000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x27d40000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac2 3>;
|
||||
dma-names = "rx";
|
||||
power-domains = <&power RK3576_PD_VO0>;
|
||||
resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>;
|
||||
reset-names = "m", "h";
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI5";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai6: sai@27d50000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x27d50000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac2 4>, <&dmac2 5>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3576_PD_VO0>;
|
||||
resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>;
|
||||
reset-names = "m", "h";
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI6";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&otp {
|
||||
bigcore_tsadc_trim_l: bigcore-tsadc-trim-l@24 {
|
||||
reg = <0x24 0x1>;
|
||||
};
|
||||
bigcore_tsadc_trim_h: bigcore-tsadc-trim-h@25 {
|
||||
reg = <0x25 0x1>;
|
||||
bits = <0 2>;
|
||||
};
|
||||
litcore_tsadc_trim_l: litcore-tsadc-trim-l@26 {
|
||||
reg = <0x26 0x1>;
|
||||
};
|
||||
litcore_tsadc_trim_h: litcore-tsadc-trim-h@27 {
|
||||
reg = <0x27 0x1>;
|
||||
bits = <0 2>;
|
||||
};
|
||||
ddr_tsadc_trim_l: ddr-tsadc-trim-l@28 {
|
||||
reg = <0x28 0x1>;
|
||||
};
|
||||
ddr_tsadc_trim_h: ddr-tsadc-trim-h@29 {
|
||||
reg = <0x29 0x1>;
|
||||
bits = <0 2>;
|
||||
};
|
||||
npu_tsadc_trim_l: npu-tsadc-trim-l@2a {
|
||||
reg = <0x2a 0x1>;
|
||||
};
|
||||
npu_tsadc_trim_h: npu-tsadc-trim-h@2b {
|
||||
reg = <0x2b 0x1>;
|
||||
bits = <0 2>;
|
||||
};
|
||||
gpu_tsadc_trim_l: gpu-tsadc-trim-l@2c {
|
||||
reg = <0x2c 0x1>;
|
||||
};
|
||||
gpu_tsadc_trim_h: gpu-tsadc-trim-h@2d {
|
||||
reg = <0x2d 0x1>;
|
||||
bits = <0 2>;
|
||||
};
|
||||
soc_tsadc_trim_l: soc-tsadc-trim-l@64 {
|
||||
reg = <0x64 0x1>;
|
||||
};
|
||||
soc_tsadc_trim_h: soc-tsadc-trim-h@65 {
|
||||
reg = <0x65 0x1>;
|
||||
bits = <0 2>;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,956 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3576.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec NanoPi R76S";
|
||||
compatible = "friendlyarm,nanopi-r76s", "rockchip,rk3576";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdmmc;
|
||||
mmc1 = &sdio;
|
||||
|
||||
led-boot = &sys_led;
|
||||
led-failsafe = &sys_led;
|
||||
led-running = &sys_led;
|
||||
led-upgrade = &sys_led;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial0:1500000n8";
|
||||
};
|
||||
|
||||
gpio_keys: gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
|
||||
button@1 {
|
||||
debounce-interval = <50>;
|
||||
gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
|
||||
label = "reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
hdmi-pwr-supply = <&vcc_5v0_hdmi>;
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
sys_led: led-sys {
|
||||
gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
label = "red:power";
|
||||
linux,default-trigger = "heartbeat";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sys_led_pin>;
|
||||
};
|
||||
|
||||
wan_led: led-wan {
|
||||
gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wan";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wan_led_pin>;
|
||||
};
|
||||
|
||||
lan_led: led-lan {
|
||||
gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan";
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
usbc_vin0 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&saradc 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb_otg0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_device>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_otg0_pwren_h>;
|
||||
};
|
||||
|
||||
vcc12v_dcin: regulator-vcc12v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc1v2_ufs_vccq_s0";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc1v8_ufs_vccq2_s0";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_1v8_s3>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie20: vcc3v3-pcie20 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie20";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_3v3_s3>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&hym8563>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_reg_on>;
|
||||
post-power-on-delay-ms = <200>;
|
||||
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_rtc_s5";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd_s0_pwren>;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc_3v3_sd_s0";
|
||||
vin-supply = <&vcc_3v3_s3>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc5v0_device: regulator-vcc5v0-device {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_device";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc_sys: regulator-vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v1_nldo_s3";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_1v8_s0: regulator-vcc-1v8-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v8_s0";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_1v8_s3>;
|
||||
};
|
||||
|
||||
vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_2v0_pldo_s3";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_3v3_s0: regulator-vcc-3v3-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3_s0";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_3v3_s3>;
|
||||
};
|
||||
|
||||
vcc_5v0_hdmi: regulator-vcc-5v0-hdmi {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_con_en>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc_5v0_hdmi";
|
||||
vin-supply = <&vcc_sys>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ufs_s0: regulator-vcc-ufs-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_ufs_s0";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big_s0>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_big_s0>;
|
||||
};
|
||||
|
||||
&cpu_b2 {
|
||||
cpu-supply = <&vdd_cpu_big_s0>;
|
||||
};
|
||||
|
||||
&cpu_b3 {
|
||||
cpu-supply = <&vdd_cpu_big_s0>;
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1_psu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdptxphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
rk806: pmic@23 {
|
||||
compatible = "rockchip,rk806";
|
||||
reg = <0x23>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
|
||||
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
|
||||
system-power-controller;
|
||||
|
||||
vcc1-supply = <&vcc_sys>;
|
||||
vcc2-supply = <&vcc_sys>;
|
||||
vcc3-supply = <&vcc_sys>;
|
||||
vcc4-supply = <&vcc_sys>;
|
||||
vcc5-supply = <&vcc_sys>;
|
||||
vcc6-supply = <&vcc_sys>;
|
||||
vcc7-supply = <&vcc_sys>;
|
||||
vcc8-supply = <&vcc_sys>;
|
||||
vcc9-supply = <&vcc_sys>;
|
||||
vcc10-supply = <&vcc_sys>;
|
||||
vcc11-supply = <&vcc_2v0_pldo_s3>;
|
||||
vcc12-supply = <&vcc_sys>;
|
||||
vcc13-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcc14-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcca-supply = <&vcc_sys>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs2_null: dvs2-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs3_null: dvs3-null-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs1_slp: dvs1-slp-pins {
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun1";
|
||||
};
|
||||
|
||||
rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun2";
|
||||
};
|
||||
|
||||
rk806_dvs1_rst: dvs1-rst-pins {
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun3";
|
||||
};
|
||||
|
||||
rk806_dvs2_slp: dvs2-slp-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun1";
|
||||
};
|
||||
|
||||
rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun2";
|
||||
};
|
||||
|
||||
rk806_dvs2_rst: dvs2-rst-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun3";
|
||||
};
|
||||
|
||||
rk806_dvs2_dvs: dvs2-dvs-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun4";
|
||||
};
|
||||
|
||||
rk806_dvs2_gpio: dvs2-gpio-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun5";
|
||||
};
|
||||
|
||||
rk806_dvs3_slp: dvs3-slp-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun1";
|
||||
};
|
||||
|
||||
rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun2";
|
||||
};
|
||||
|
||||
rk806_dvs3_rst: dvs3-rst-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun3";
|
||||
};
|
||||
|
||||
rk806_dvs3_dvs: dvs3-dvs-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun4";
|
||||
};
|
||||
|
||||
rk806_dvs3_gpio: dvs3-gpio-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun5";
|
||||
};
|
||||
|
||||
regulators {
|
||||
vdd_cpu_big_s0: dcdc-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_cpu_big_s0";
|
||||
regulator-enable-ramp-delay = <400>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu_s0: dcdc-reg2 {
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_npu_s0";
|
||||
regulator-enable-ramp-delay = <400>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_lit_s0: dcdc-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_cpu_lit_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s3: dcdc-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_3v3_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu_s0: dcdc-reg5 {
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_gpu_s0";
|
||||
regulator-enable-ramp-delay = <400>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <850000>;
|
||||
};
|
||||
};
|
||||
|
||||
vddq_ddr_s0: dcdc-reg6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vddq_ddr_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_logic_s0: dcdc-reg7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-name = "vdd_logic_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_s3: dcdc-reg8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd2_ddr_s3: dcdc-reg9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vdd2_ddr_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr_s0: dcdc-reg10 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-name = "vdd_ddr_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8_s0: pldo-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pldo2_s0: pldo-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pldo2_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_1v2_s0: pldo-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-name = "vdda_1v2_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_3v3_s0: pldo-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcca_3v3_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd_s0: pldo-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pldo6_s3: pldo-reg6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pldo6_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_s3: nldo-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-name = "vdd_0v75_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_ddr_pll_s0: nldo-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-name = "vdda_ddr_pll_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v75_hdmi_s0: nldo-reg3 {
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <837500>;
|
||||
regulator-max-microvolt = <837500>;
|
||||
regulator-name = "vdda0v75_hdmi_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v85_s0: nldo-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-name = "vdda_0v85_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v75_s0: nldo-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-name = "vdda_0v75_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
|
||||
hym8563: rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "hym8563";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rtc_int_l>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie0_reset>;
|
||||
reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie20>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_1: pcie@1,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x0 0x0 0x2b 0x200>;
|
||||
label = "eth0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie1_reset>;
|
||||
reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie20>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_2: pcie@10,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x0 0x0 0x2b 0x200>;
|
||||
label = "eth1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
gpio-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
sys_led_pin: sys-led-pin {
|
||||
rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wan_led_pin: wan-led-pin {
|
||||
rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
lan_led_pin: lan-led-pin {
|
||||
rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
usb {
|
||||
usb3_host_pwren_h: usb3-host-pwren-h {
|
||||
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
usb_otg0_pwren_h: usb-otg0-pwren-h {
|
||||
rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie0_reset: pcie0-reset {
|
||||
rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
pcie1_reset: pcie1-reset {
|
||||
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
rtc_int_l: rtc-int-l {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sd_s0_pwren: sd-s0-pwren {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
hdmi {
|
||||
hdmi_con_en: hdmi-con-en {
|
||||
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_wake_host: wifi-wake-host {
|
||||
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
wifi_reg_on: wifi-reg-on {
|
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
bt_reg_on: bt-reg-on {
|
||||
rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
host_wake_bt: host-wake-bt {
|
||||
rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
bt_wake_host: bt-wake-host {
|
||||
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
max-frequency = <200000000>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_3v3_sd_s0>;
|
||||
vqmmc-supply = <&vccio_sd_s0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio {
|
||||
max-frequency = <200000000>;
|
||||
no-sd;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1m0_bus4 &sdmmc1m0_clk &sdmmc1m0_cmd>;
|
||||
sd-uhs-sdr104;
|
||||
wakeup-source;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
max-frequency = <200000000>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
full-pwr-cycle-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "realtek,rtl8822cs-bt";
|
||||
enable-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
host-wake-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
device-wake-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbdp_phy {
|
||||
rockchip,dp-lane-mux = <2 3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_drd0_dwc3 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status= "okay";
|
||||
};
|
||||
@ -14,10 +14,9 @@
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3576.dtsi"
|
||||
#include "rk3576-extra.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ariaboard photonicat2";
|
||||
model = "Ariaboard Photonicat 2";
|
||||
compatible = "ariaboard,photonicat2", "rockchip,rk3576";
|
||||
|
||||
aliases {
|
||||
|
||||
@ -24,7 +24,7 @@ TARGET_DEVICES += ariaboard_photonicat
|
||||
|
||||
define Device/ariaboard_photonicat2
|
||||
DEVICE_VENDOR := Ariaboard
|
||||
DEVICE_MODEL := Photonicat2
|
||||
DEVICE_MODEL := Photonicat 2
|
||||
SOC := rk3576
|
||||
DEVICE_DTS := rockchip/rk3576-photonicat2
|
||||
UBOOT_DEVICE_NAME := evb-rk3576
|
||||
@ -274,6 +274,17 @@ define Device/friendlyarm_nanopi-r6s
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r6s
|
||||
|
||||
define Device/friendlyarm_nanopi-r76s
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R76S
|
||||
SOC := rk3576
|
||||
DEVICE_DTS := rockchip/rk3576-nanopi-r76s
|
||||
UBOOT_DEVICE_NAME := evb-rk3576
|
||||
DEVICE_PACKAGES := kmod-gpio-button-hotplug kmod-r8125
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script rk3576 | pine64-img | gzip | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r76s
|
||||
|
||||
define Device/firefly_station-p2
|
||||
DEVICE_VENDOR := Firefly
|
||||
DEVICE_MODEL := Station P2
|
||||
|
||||
@ -0,0 +1,98 @@
|
||||
From 32a0fc710f946d0bd5081aa6bbf140dd128d8d32 Mon Sep 17 00:00:00 2001
|
||||
From: Andy Yan <andy.yan@rock-chips.com>
|
||||
Date: Tue, 31 Dec 2024 17:57:18 +0800
|
||||
Subject: [PATCH 41/75] arm64: dts: rockchip: Add vop for rk3576
|
||||
|
||||
Add VOP and VOP_MMU found on rk3576.
|
||||
|
||||
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
|
||||
Link: https://lore.kernel.org/r/20241231095728.253943-2-andyshrk@163.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 68 ++++++++++++++++++++++++
|
||||
1 file changed, 68 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
@@ -393,6 +393,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ display_subsystem: display-subsystem {
|
||||
+ compatible = "rockchip,display-subsystem";
|
||||
+ ports = <&vop_out>;
|
||||
+ };
|
||||
+
|
||||
firmware {
|
||||
scmi: scmi {
|
||||
compatible = "arm,scmi-smc";
|
||||
@@ -937,6 +942,69 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ vop: vop@27d00000 {
|
||||
+ compatible = "rockchip,rk3576-vop";
|
||||
+ reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
|
||||
+ reg-names = "vop", "gamma-lut";
|
||||
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "sys",
|
||||
+ "vp0",
|
||||
+ "vp1",
|
||||
+ "vp2";
|
||||
+ clocks = <&cru ACLK_VOP>,
|
||||
+ <&cru HCLK_VOP>,
|
||||
+ <&cru DCLK_VP0>,
|
||||
+ <&cru DCLK_VP1>,
|
||||
+ <&cru DCLK_VP2>;
|
||||
+ clock-names = "aclk",
|
||||
+ "hclk",
|
||||
+ "dclk_vp0",
|
||||
+ "dclk_vp1",
|
||||
+ "dclk_vp2";
|
||||
+ iommus = <&vop_mmu>;
|
||||
+ power-domains = <&power RK3576_PD_VOP>;
|
||||
+ rockchip,grf = <&sys_grf>;
|
||||
+ rockchip,pmu = <&pmu>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ vop_out: ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ vp0: port@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+
|
||||
+ vp1: port@1 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+
|
||||
+ vp2: port@2 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vop_mmu: iommu@27d07e00 {
|
||||
+ compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
|
||||
+ reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>;
|
||||
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
||||
+ clock-names = "aclk", "iface";
|
||||
+ #iommu-cells = <0>;
|
||||
+ power-domains = <&power RK3576_PD_VOP>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
qos_hdcp1: qos@27f02000 {
|
||||
compatible = "rockchip,rk3576-qos", "syscon";
|
||||
reg = <0x0 0x27f02000 0x0 0x20>;
|
||||
@ -0,0 +1,95 @@
|
||||
From 9b2fa20fda167aa15770f53fba6da12fcd4d93a1 Mon Sep 17 00:00:00 2001
|
||||
From: Andy Yan <andy.yan@rock-chips.com>
|
||||
Date: Tue, 31 Dec 2024 17:57:19 +0800
|
||||
Subject: [PATCH 42/75] arm64: dts: rockchip: Add hdmi for rk3576
|
||||
|
||||
Add hdmi and it's phy dt node for rk3576.
|
||||
|
||||
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
|
||||
Link: https://lore.kernel.org/r/20241231095728.253943-3-andyshrk@163.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 58 ++++++++++++++++++++++++
|
||||
1 file changed, 58 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
@@ -625,6 +625,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ hdptxphy_grf: syscon@26032000 {
|
||||
+ compatible = "rockchip,rk3576-hdptxphy-grf", "syscon";
|
||||
+ reg = <0x0 0x26032000 0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
vo1_grf: syscon@26036000 {
|
||||
compatible = "rockchip,rk3576-vo1-grf", "syscon";
|
||||
reg = <0x0 0x26036000 0x0 0x100>;
|
||||
@@ -1005,6 +1010,46 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ hdmi: hdmi@27da0000 {
|
||||
+ compatible = "rockchip,rk3576-dw-hdmi-qp";
|
||||
+ reg = <0x0 0x27da0000 0x0 0x20000>;
|
||||
+ clocks = <&cru PCLK_HDMITX0>,
|
||||
+ <&cru CLK_HDMITX0_EARC>,
|
||||
+ <&cru CLK_HDMITX0_REF>,
|
||||
+ <&cru MCLK_SAI6_8CH>,
|
||||
+ <&cru CLK_HDMITXHDP>,
|
||||
+ <&cru HCLK_VO0_ROOT>;
|
||||
+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
|
||||
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
|
||||
+ phys = <&hdptxphy>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>;
|
||||
+ power-domains = <&power RK3576_PD_VO0>;
|
||||
+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>;
|
||||
+ reset-names = "ref", "hdp";
|
||||
+ rockchip,grf = <&ioc_grf>;
|
||||
+ rockchip,vo-grf = <&vo0_grf>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ hdmi_in: port@0 {
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+
|
||||
+ hdmi_out: port@1 {
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
qos_hdcp1: qos@27f02000 {
|
||||
compatible = "rockchip,rk3576-qos", "syscon";
|
||||
reg = <0x0 0x27f02000 0x0 0x20>;
|
||||
@@ -1887,6 +1932,19 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ hdptxphy: hdmiphy@2b000000 {
|
||||
+ compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy";
|
||||
+ reg = <0x0 0x2b000000 0x0 0x2000>;
|
||||
+ clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>;
|
||||
+ clock-names = "ref", "apb";
|
||||
+ resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>,
|
||||
+ <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>;
|
||||
+ reset-names = "apb", "init", "cmn", "lane";
|
||||
+ rockchip,grf = <&hdptxphy_grf>;
|
||||
+ #phy-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
sram: sram@3ff88000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x0 0x3ff88000 0x0 0x78000>;
|
||||
@ -0,0 +1,135 @@
|
||||
From 5712039aed02e19d13cf30c56e6963b6ec686e2e Mon Sep 17 00:00:00 2001
|
||||
From: Kever Yang <kever.yang@rock-chips.com>
|
||||
Date: Mon, 14 Apr 2025 22:51:10 +0800
|
||||
Subject: [PATCH 47/75] arm64: dts: rockchip: Add rk3576 pcie nodes
|
||||
|
||||
rk3576 has two pcie controllers, both are pcie2x1 work with
|
||||
naneng-combphy.
|
||||
|
||||
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
|
||||
Tested-by: Shawn Lin <Shawn.lin@rock-chips.com>
|
||||
Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
|
||||
Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20250414145110.11275-3-kever.yang@rock-chips.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 108 +++++++++++++++++++++++
|
||||
1 file changed, 108 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
@@ -1240,6 +1240,114 @@
|
||||
reg = <0x0 0x27f22100 0x0 0x20>;
|
||||
};
|
||||
|
||||
+ pcie0: pcie@2a200000 {
|
||||
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
|
||||
+ reg = <0x0 0x22000000 0x0 0x00400000>,
|
||||
+ <0x0 0x2a200000 0x0 0x00010000>,
|
||||
+ <0x0 0x20000000 0x0 0x00100000>;
|
||||
+ reg-names = "dbi", "apb", "config";
|
||||
+ bus-range = <0x0 0xf>;
|
||||
+ clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
|
||||
+ <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
|
||||
+ <&cru CLK_PCIE0_AUX>;
|
||||
+ clock-names = "aclk_mst", "aclk_slv",
|
||||
+ "aclk_dbi", "pclk",
|
||||
+ "aux";
|
||||
+ device_type = "pci";
|
||||
+ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 7>;
|
||||
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
|
||||
+ <0 0 0 2 &pcie0_intc 1>,
|
||||
+ <0 0 0 3 &pcie0_intc 2>,
|
||||
+ <0 0 0 4 &pcie0_intc 3>;
|
||||
+ linux,pci-domain = <0>;
|
||||
+ max-link-speed = <2>;
|
||||
+ num-ib-windows = <8>;
|
||||
+ num-viewport = <8>;
|
||||
+ num-ob-windows = <2>;
|
||||
+ num-lanes = <1>;
|
||||
+ phys = <&combphy0_ps PHY_TYPE_PCIE>;
|
||||
+ phy-names = "pcie-phy";
|
||||
+ power-domains = <&power RK3576_PD_PHP>;
|
||||
+ ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
|
||||
+ 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
|
||||
+ 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
|
||||
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
|
||||
+ reset-names = "pwr", "pipe";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ pcie0_intc: legacy-interrupt-controller {
|
||||
+ interrupt-controller;
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie1: pcie@2a210000 {
|
||||
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
|
||||
+ reg = <0x0 0x22400000 0x0 0x00400000>,
|
||||
+ <0x0 0x2a210000 0x0 0x00010000>,
|
||||
+ <0x0 0x21000000 0x0 0x00100000>;
|
||||
+ reg-names = "dbi", "apb", "config";
|
||||
+ bus-range = <0x20 0x2f>;
|
||||
+ clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
|
||||
+ <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
|
||||
+ <&cru CLK_PCIE1_AUX>;
|
||||
+ clock-names = "aclk_mst", "aclk_slv",
|
||||
+ "aclk_dbi", "pclk",
|
||||
+ "aux";
|
||||
+ device_type = "pci";
|
||||
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 7>;
|
||||
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
|
||||
+ <0 0 0 2 &pcie1_intc 1>,
|
||||
+ <0 0 0 3 &pcie1_intc 2>,
|
||||
+ <0 0 0 4 &pcie1_intc 3>;
|
||||
+ linux,pci-domain = <0>;
|
||||
+ max-link-speed = <2>;
|
||||
+ num-ib-windows = <8>;
|
||||
+ num-viewport = <8>;
|
||||
+ num-ob-windows = <2>;
|
||||
+ num-lanes = <1>;
|
||||
+ phys = <&combphy1_psu PHY_TYPE_PCIE>;
|
||||
+ phy-names = "pcie-phy";
|
||||
+ power-domains = <&power RK3576_PD_SUBPHP>;
|
||||
+ ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
|
||||
+ 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
|
||||
+ 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
|
||||
+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
|
||||
+ reset-names = "pwr", "pipe";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ pcie1_intc: legacy-interrupt-controller {
|
||||
+ interrupt-controller;
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
gmac0: ethernet@2a220000 {
|
||||
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0x2a220000 0x0 0x10000>;
|
||||
@ -0,0 +1,243 @@
|
||||
From fbcc9ab6cf70d046c5f112aa9d4d90c924b50f5c Mon Sep 17 00:00:00 2001
|
||||
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
|
||||
Date: Tue, 6 May 2025 12:42:40 +0200
|
||||
Subject: [PATCH 66/75] arm64: dts: rockchip: Add RK3576 SAI nodes
|
||||
|
||||
The RK3576 SoC has 10 SAI controllers in total. Five of them are in the
|
||||
video output power domains, and are used for digital audio output along
|
||||
with the video signal of those, e.g. HDMI audio.
|
||||
|
||||
The other five, SAI0 through SAI4, are exposed externally. SAI0 and SAI1
|
||||
are capable of 8-channel audio, whereas SAI2, SAI3 and SAI4 are limited
|
||||
to two channels. These five are in the audio power domain.
|
||||
|
||||
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-1-a8b5f5733ceb@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 200 +++++++++++++++++++++++
|
||||
1 file changed, 200 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
@@ -1010,6 +1010,41 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ sai5: sai@27d40000 {
|
||||
+ compatible = "rockchip,rk3576-sai";
|
||||
+ reg = <0x0 0x27d40000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>;
|
||||
+ clock-names = "mclk", "hclk";
|
||||
+ dmas = <&dmac2 3>;
|
||||
+ dma-names = "rx";
|
||||
+ power-domains = <&power RK3576_PD_VO0>;
|
||||
+ resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>;
|
||||
+ reset-names = "m", "h";
|
||||
+ rockchip,sai-rx-route = <0 1 2 3>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ sound-name-prefix = "SAI5";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ sai6: sai@27d50000 {
|
||||
+ compatible = "rockchip,rk3576-sai";
|
||||
+ reg = <0x0 0x27d50000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>;
|
||||
+ clock-names = "mclk", "hclk";
|
||||
+ dmas = <&dmac2 4>, <&dmac2 5>;
|
||||
+ dma-names = "tx", "rx";
|
||||
+ power-domains = <&power RK3576_PD_VO0>;
|
||||
+ resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>;
|
||||
+ reset-names = "m", "h";
|
||||
+ rockchip,sai-rx-route = <0 1 2 3>;
|
||||
+ rockchip,sai-tx-route = <0 1 2 3>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ sound-name-prefix = "SAI6";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
hdmi: hdmi@27da0000 {
|
||||
compatible = "rockchip,rk3576-dw-hdmi-qp";
|
||||
reg = <0x0 0x27da0000 0x0 0x20000>;
|
||||
@@ -1050,6 +1085,57 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ sai7: sai@27ed0000 {
|
||||
+ compatible = "rockchip,rk3576-sai";
|
||||
+ reg = <0x0 0x27ed0000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>;
|
||||
+ clock-names = "mclk", "hclk";
|
||||
+ dmas = <&dmac2 19>;
|
||||
+ dma-names = "tx";
|
||||
+ power-domains = <&power RK3576_PD_VO1>;
|
||||
+ resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>;
|
||||
+ reset-names = "m", "h";
|
||||
+ rockchip,sai-tx-route = <0 1 2 3>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ sound-name-prefix = "SAI7";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ sai8: sai@27ee0000 {
|
||||
+ compatible = "rockchip,rk3576-sai";
|
||||
+ reg = <0x0 0x27ee0000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>;
|
||||
+ clock-names = "mclk", "hclk";
|
||||
+ dmas = <&dmac1 7>;
|
||||
+ dma-names = "tx";
|
||||
+ power-domains = <&power RK3576_PD_VO1>;
|
||||
+ resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>;
|
||||
+ reset-names = "m", "h";
|
||||
+ rockchip,sai-tx-route = <0 1 2 3>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ sound-name-prefix = "SAI8";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ sai9: sai@27ef0000 {
|
||||
+ compatible = "rockchip,rk3576-sai";
|
||||
+ reg = <0x0 0x27ef0000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>;
|
||||
+ clock-names = "mclk", "hclk";
|
||||
+ dmas = <&dmac0 26>;
|
||||
+ dma-names = "tx";
|
||||
+ power-domains = <&power RK3576_PD_VO1>;
|
||||
+ resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>;
|
||||
+ reset-names = "m", "h";
|
||||
+ rockchip,sai-tx-route = <0 1 2 3>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ sound-name-prefix = "SAI9";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
qos_hdcp1: qos@27f02000 {
|
||||
compatible = "rockchip,rk3576-qos", "syscon";
|
||||
reg = <0x0 0x27f02000 0x0 0x20>;
|
||||
@@ -1604,6 +1690,120 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ sai0: sai@2a600000 {
|
||||
+ compatible = "rockchip,rk3576-sai";
|
||||
+ reg = <0x0 0x2a600000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>;
|
||||
+ clock-names = "mclk", "hclk";
|
||||
+ dmas = <&dmac0 0>, <&dmac0 1>;
|
||||
+ dma-names = "tx", "rx";
|
||||
+ power-domains = <&power RK3576_PD_AUDIO>;
|
||||
+ resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>;
|
||||
+ reset-names = "m", "h";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sai0m0_lrck
|
||||
+ &sai0m0_sclk
|
||||
+ &sai0m0_sdi0
|
||||
+ &sai0m0_sdi1
|
||||
+ &sai0m0_sdi2
|
||||
+ &sai0m0_sdi3
|
||||
+ &sai0m0_sdo0
|
||||
+ &sai0m0_sdo1
|
||||
+ &sai0m0_sdo2
|
||||
+ &sai0m0_sdo3>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ sound-name-prefix = "SAI0";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ sai1: sai@2a610000 {
|
||||
+ compatible = "rockchip,rk3576-sai";
|
||||
+ reg = <0x0 0x2a610000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>;
|
||||
+ clock-names = "mclk", "hclk";
|
||||
+ dmas = <&dmac0 2>, <&dmac0 3>;
|
||||
+ dma-names = "tx", "rx";
|
||||
+ power-domains = <&power RK3576_PD_AUDIO>;
|
||||
+ resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>;
|
||||
+ reset-names = "m", "h";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sai1m0_lrck
|
||||
+ &sai1m0_sclk
|
||||
+ &sai1m0_sdi0
|
||||
+ &sai1m0_sdo0
|
||||
+ &sai1m0_sdo1
|
||||
+ &sai1m0_sdo2
|
||||
+ &sai1m0_sdo3>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ sound-name-prefix = "SAI1";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ sai2: sai@2a620000 {
|
||||
+ compatible = "rockchip,rk3576-sai";
|
||||
+ reg = <0x0 0x2a620000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>;
|
||||
+ clock-names = "mclk", "hclk";
|
||||
+ dmas = <&dmac1 0>, <&dmac1 1>;
|
||||
+ dma-names = "tx", "rx";
|
||||
+ power-domains = <&power RK3576_PD_AUDIO>;
|
||||
+ resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>;
|
||||
+ reset-names = "m", "h";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sai2m0_lrck
|
||||
+ &sai2m0_sclk
|
||||
+ &sai2m0_sdi
|
||||
+ &sai2m0_sdo>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ sound-name-prefix = "SAI2";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ sai3: sai@2a630000 {
|
||||
+ compatible = "rockchip,rk3576-sai";
|
||||
+ reg = <0x0 0x2a630000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>;
|
||||
+ clock-names = "mclk", "hclk";
|
||||
+ dmas = <&dmac1 2>, <&dmac1 3>;
|
||||
+ dma-names = "tx", "rx";
|
||||
+ power-domains = <&power RK3576_PD_AUDIO>;
|
||||
+ resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>;
|
||||
+ reset-names = "m", "h";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sai3m0_lrck
|
||||
+ &sai3m0_sclk
|
||||
+ &sai3m0_sdi
|
||||
+ &sai3m0_sdo>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ sound-name-prefix = "SAI3";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ sai4: sai@2a640000 {
|
||||
+ compatible = "rockchip,rk3576-sai";
|
||||
+ reg = <0x0 0x2a640000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>;
|
||||
+ clock-names = "mclk", "hclk";
|
||||
+ dmas = <&dmac2 0>, <&dmac2 1>;
|
||||
+ dma-names = "tx", "rx";
|
||||
+ power-domains = <&power RK3576_PD_AUDIO>;
|
||||
+ resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>;
|
||||
+ reset-names = "m", "h";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sai4m0_lrck
|
||||
+ &sai4m0_sclk
|
||||
+ &sai4m0_sdi
|
||||
+ &sai4m0_sdo>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ sound-name-prefix = "SAI4";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
gic: interrupt-controller@2a701000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0x0 0x2a701000 0 0x10000>,
|
||||
@ -0,0 +1,50 @@
|
||||
From cb28aa830204ac64f3fd916cab46a1f6fd3834ce Mon Sep 17 00:00:00 2001
|
||||
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
|
||||
Date: Tue, 6 May 2025 12:42:41 +0200
|
||||
Subject: [PATCH 67/75] arm64: dts: rockchip: Add RK3576 HDMI audio
|
||||
|
||||
The RK3576 SoC now has upstream support for HDMI.
|
||||
|
||||
Add an HDMI audio node, which uses SAI6 as its audio controller
|
||||
according to downstream.
|
||||
|
||||
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-2-a8b5f5733ceb@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 17 +++++++++++++++++
|
||||
1 file changed, 17 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
@@ -413,6 +413,22 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ hdmi_sound: hdmi-sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,name = "HDMI";
|
||||
+ simple-audio-card,format = "i2s";
|
||||
+ simple-audio-card,mclk-fs = <256>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&hdmi>;
|
||||
+ };
|
||||
+
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&sai6>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
pmu_a53: pmu-a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@@ -1069,6 +1085,7 @@
|
||||
reset-names = "ref", "hdp";
|
||||
rockchip,grf = <&ioc_grf>;
|
||||
rockchip,vo-grf = <&vo0_grf>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
@ -0,0 +1,257 @@
|
||||
From 21c8255aaea87b2098b20f45e335a0d544c42ad6 Mon Sep 17 00:00:00 2001
|
||||
From: Heiko Stuebner <heiko@sntech.de>
|
||||
Date: Mon, 19 May 2025 00:04:43 +0200
|
||||
Subject: [PATCH 70/75] arm64: dts: rockchip: fix rk3576 pcie unit addresses
|
||||
|
||||
The rk3576 pcie nodes currently use the apb register as their unit address
|
||||
which is the second reg area defined in the binding.
|
||||
|
||||
As can be seen by the dtc warnings like
|
||||
|
||||
../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1346.24-1398.5: Warning (simple_bus_reg): /soc/pcie@2a200000: simple-bus unit address format error, expected "22000000"
|
||||
../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1400.24-1452.5: Warning (simple_bus_reg): /soc/pcie@2a210000: simple-bus unit address format error, expected "22400000"
|
||||
|
||||
using the first reg area as the unit address seems to be preferred.
|
||||
This is the dbi area per the binding, so adapt the unit address accordingly
|
||||
and move the nodes to their new position.
|
||||
|
||||
Reported-by: kernel test robot <lkp@intel.com>
|
||||
Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://lore.kernel.org/r/20250518220449.2722673-2-heiko@sntech.de
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 216 +++++++++++------------
|
||||
1 file changed, 108 insertions(+), 108 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
@@ -466,6 +466,114 @@
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
+ pcie0: pcie@22000000 {
|
||||
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
|
||||
+ reg = <0x0 0x22000000 0x0 0x00400000>,
|
||||
+ <0x0 0x2a200000 0x0 0x00010000>,
|
||||
+ <0x0 0x20000000 0x0 0x00100000>;
|
||||
+ reg-names = "dbi", "apb", "config";
|
||||
+ bus-range = <0x0 0xf>;
|
||||
+ clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
|
||||
+ <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
|
||||
+ <&cru CLK_PCIE0_AUX>;
|
||||
+ clock-names = "aclk_mst", "aclk_slv",
|
||||
+ "aclk_dbi", "pclk",
|
||||
+ "aux";
|
||||
+ device_type = "pci";
|
||||
+ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 7>;
|
||||
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
|
||||
+ <0 0 0 2 &pcie0_intc 1>,
|
||||
+ <0 0 0 3 &pcie0_intc 2>,
|
||||
+ <0 0 0 4 &pcie0_intc 3>;
|
||||
+ linux,pci-domain = <0>;
|
||||
+ max-link-speed = <2>;
|
||||
+ num-ib-windows = <8>;
|
||||
+ num-viewport = <8>;
|
||||
+ num-ob-windows = <2>;
|
||||
+ num-lanes = <1>;
|
||||
+ phys = <&combphy0_ps PHY_TYPE_PCIE>;
|
||||
+ phy-names = "pcie-phy";
|
||||
+ power-domains = <&power RK3576_PD_PHP>;
|
||||
+ ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
|
||||
+ 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
|
||||
+ 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
|
||||
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
|
||||
+ reset-names = "pwr", "pipe";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ pcie0_intc: legacy-interrupt-controller {
|
||||
+ interrupt-controller;
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie1: pcie@22400000 {
|
||||
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
|
||||
+ reg = <0x0 0x22400000 0x0 0x00400000>,
|
||||
+ <0x0 0x2a210000 0x0 0x00010000>,
|
||||
+ <0x0 0x21000000 0x0 0x00100000>;
|
||||
+ reg-names = "dbi", "apb", "config";
|
||||
+ bus-range = <0x20 0x2f>;
|
||||
+ clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
|
||||
+ <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
|
||||
+ <&cru CLK_PCIE1_AUX>;
|
||||
+ clock-names = "aclk_mst", "aclk_slv",
|
||||
+ "aclk_dbi", "pclk",
|
||||
+ "aux";
|
||||
+ device_type = "pci";
|
||||
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 7>;
|
||||
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
|
||||
+ <0 0 0 2 &pcie1_intc 1>,
|
||||
+ <0 0 0 3 &pcie1_intc 2>,
|
||||
+ <0 0 0 4 &pcie1_intc 3>;
|
||||
+ linux,pci-domain = <0>;
|
||||
+ max-link-speed = <2>;
|
||||
+ num-ib-windows = <8>;
|
||||
+ num-viewport = <8>;
|
||||
+ num-ob-windows = <2>;
|
||||
+ num-lanes = <1>;
|
||||
+ phys = <&combphy1_psu PHY_TYPE_PCIE>;
|
||||
+ phy-names = "pcie-phy";
|
||||
+ power-domains = <&power RK3576_PD_SUBPHP>;
|
||||
+ ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
|
||||
+ 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
|
||||
+ 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
|
||||
+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
|
||||
+ reset-names = "pwr", "pipe";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ pcie1_intc: legacy-interrupt-controller {
|
||||
+ interrupt-controller;
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb_drd0_dwc3: usb@23000000 {
|
||||
compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
|
||||
reg = <0x0 0x23000000 0x0 0x400000>;
|
||||
@@ -1343,114 +1451,6 @@
|
||||
reg = <0x0 0x27f22100 0x0 0x20>;
|
||||
};
|
||||
|
||||
- pcie0: pcie@2a200000 {
|
||||
- compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
|
||||
- reg = <0x0 0x22000000 0x0 0x00400000>,
|
||||
- <0x0 0x2a200000 0x0 0x00010000>,
|
||||
- <0x0 0x20000000 0x0 0x00100000>;
|
||||
- reg-names = "dbi", "apb", "config";
|
||||
- bus-range = <0x0 0xf>;
|
||||
- clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
|
||||
- <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
|
||||
- <&cru CLK_PCIE0_AUX>;
|
||||
- clock-names = "aclk_mst", "aclk_slv",
|
||||
- "aclk_dbi", "pclk",
|
||||
- "aux";
|
||||
- device_type = "pci";
|
||||
- interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
|
||||
- #interrupt-cells = <1>;
|
||||
- interrupt-map-mask = <0 0 0 7>;
|
||||
- interrupt-map = <0 0 0 1 &pcie0_intc 0>,
|
||||
- <0 0 0 2 &pcie0_intc 1>,
|
||||
- <0 0 0 3 &pcie0_intc 2>,
|
||||
- <0 0 0 4 &pcie0_intc 3>;
|
||||
- linux,pci-domain = <0>;
|
||||
- max-link-speed = <2>;
|
||||
- num-ib-windows = <8>;
|
||||
- num-viewport = <8>;
|
||||
- num-ob-windows = <2>;
|
||||
- num-lanes = <1>;
|
||||
- phys = <&combphy0_ps PHY_TYPE_PCIE>;
|
||||
- phy-names = "pcie-phy";
|
||||
- power-domains = <&power RK3576_PD_PHP>;
|
||||
- ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
|
||||
- 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
|
||||
- 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
|
||||
- resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
|
||||
- reset-names = "pwr", "pipe";
|
||||
- #address-cells = <3>;
|
||||
- #size-cells = <2>;
|
||||
- status = "disabled";
|
||||
-
|
||||
- pcie0_intc: legacy-interrupt-controller {
|
||||
- interrupt-controller;
|
||||
- #address-cells = <0>;
|
||||
- #interrupt-cells = <1>;
|
||||
- interrupt-parent = <&gic>;
|
||||
- interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- pcie1: pcie@2a210000 {
|
||||
- compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
|
||||
- reg = <0x0 0x22400000 0x0 0x00400000>,
|
||||
- <0x0 0x2a210000 0x0 0x00010000>,
|
||||
- <0x0 0x21000000 0x0 0x00100000>;
|
||||
- reg-names = "dbi", "apb", "config";
|
||||
- bus-range = <0x20 0x2f>;
|
||||
- clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
|
||||
- <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
|
||||
- <&cru CLK_PCIE1_AUX>;
|
||||
- clock-names = "aclk_mst", "aclk_slv",
|
||||
- "aclk_dbi", "pclk",
|
||||
- "aux";
|
||||
- device_type = "pci";
|
||||
- interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
|
||||
- #interrupt-cells = <1>;
|
||||
- interrupt-map-mask = <0 0 0 7>;
|
||||
- interrupt-map = <0 0 0 1 &pcie1_intc 0>,
|
||||
- <0 0 0 2 &pcie1_intc 1>,
|
||||
- <0 0 0 3 &pcie1_intc 2>,
|
||||
- <0 0 0 4 &pcie1_intc 3>;
|
||||
- linux,pci-domain = <0>;
|
||||
- max-link-speed = <2>;
|
||||
- num-ib-windows = <8>;
|
||||
- num-viewport = <8>;
|
||||
- num-ob-windows = <2>;
|
||||
- num-lanes = <1>;
|
||||
- phys = <&combphy1_psu PHY_TYPE_PCIE>;
|
||||
- phy-names = "pcie-phy";
|
||||
- power-domains = <&power RK3576_PD_SUBPHP>;
|
||||
- ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
|
||||
- 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
|
||||
- 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
|
||||
- resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
|
||||
- reset-names = "pwr", "pipe";
|
||||
- #address-cells = <3>;
|
||||
- #size-cells = <2>;
|
||||
- status = "disabled";
|
||||
-
|
||||
- pcie1_intc: legacy-interrupt-controller {
|
||||
- interrupt-controller;
|
||||
- #address-cells = <0>;
|
||||
- #interrupt-cells = <1>;
|
||||
- interrupt-parent = <&gic>;
|
||||
- interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
gmac0: ethernet@2a220000 {
|
||||
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0x2a220000 0x0 0x10000>;
|
||||
@ -0,0 +1,32 @@
|
||||
From 94cee2066340d3cda16df9596061fd16ef930cb3 Mon Sep 17 00:00:00 2001
|
||||
From: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
Date: Tue, 3 Jun 2025 10:35:40 +0800
|
||||
Subject: [PATCH 73/75] arm64: dts: rockchip: fix rk3576 pcie1 linux,pci-domain
|
||||
|
||||
pcie0 already used 0 as its pci-domain, so pcie1 will fail to
|
||||
allocate the same pci-domain if both of them are used.
|
||||
|
||||
rk-pcie 2a210000.pcie: PCIe Link up, LTSSM is 0x130011
|
||||
rk-pcie 2a210000.pcie: PCIe Gen.2 x1 link up
|
||||
rk-pcie 2a210000.pcie: Scanning root bridge failed
|
||||
rk-pcie 2a210000.pcie: failed to initialize host
|
||||
|
||||
Fixes: d4b9fc2af45d ("arm64: dts: rockchip: Add rk3576 pcie nodes")
|
||||
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
Link: https://lore.kernel.org/r/1748918140-212263-1-git-send-email-shawn.lin@rock-chips.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
@@ -615,7 +615,7 @@
|
||||
<0 0 0 2 &pcie1_intc 1>,
|
||||
<0 0 0 3 &pcie1_intc 2>,
|
||||
<0 0 0 4 &pcie1_intc 3>;
|
||||
- linux,pci-domain = <0>;
|
||||
+ linux,pci-domain = <1>;
|
||||
max-link-speed = <2>;
|
||||
num-ib-windows = <8>;
|
||||
num-viewport = <8>;
|
||||
@ -0,0 +1,35 @@
|
||||
From c8224fac4bbf1602bb08a6d473a186df258084d7 Mon Sep 17 00:00:00 2001
|
||||
From: sbwml <admin@cooluc.com>
|
||||
Date: Sat, 19 Jul 2025 18:31:51 +0800
|
||||
Subject: [PATCH 74/75] arm64: dts: rockchip: add RK3576 sdio node
|
||||
|
||||
Signed-off-by: sbwml <admin@cooluc.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 16 ++++++++++++++++
|
||||
1 file changed, 16 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
@@ -1695,6 +1695,22 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ sdio: mmc@2a320000 {
|
||||
+ compatible = "rockchip,rk3576-dw-mshc";
|
||||
+ reg = <0x0 0x2a320000 0x0 0x4000>;
|
||||
+ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>;
|
||||
+ clock-names = "biu", "ciu";
|
||||
+ fifo-depth = <0x100>;
|
||||
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>;
|
||||
+ pinctrl-names = "default";
|
||||
+ power-domains = <&power RK3576_PD_SDGMAC>;
|
||||
+ resets = <&cru SRST_H_SDIO>;
|
||||
+ reset-names = "reset";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
sdhci: mmc@2a330000 {
|
||||
compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc";
|
||||
reg = <0x0 0x2a330000 0x0 0x10000>;
|
||||
@ -0,0 +1,222 @@
|
||||
The RK3576 SoC features three distinct PWM controllers, with variable
|
||||
numbers of channels. Add each channel as a separate node to the SoC's
|
||||
device tree, as they don't really overlap in register ranges.
|
||||
|
||||
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 192 +++++++++++++++++++++++++++++++
|
||||
1 file changed, 192 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
index ebb5fc8bb8b1363127b9d3782801c4a79b678a92..b6ba1d5569b3d961707b182eb5f960939de67c84 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
@@ -809,6 +809,30 @@
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
+
|
||||
+ pwm0_2ch_0: pwm@...30000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x27330000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm0m0_ch0>;
|
||||
+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm0_2ch_1: pwm@...31000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x27331000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm0m0_ch1>;
|
||||
+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
|
||||
uart1: serial@27310000 {
|
||||
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
|
||||
@@ -2179,6 +2203,174 @@
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&uart9m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm1_6ch_0: pwm@...d0000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2add0000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
+ clock-names = "pwm", "pclk", "osc";
|
||||
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm1m0_ch0>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm1_6ch_1: pwm@...d1000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2add1000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
+ clock-names = "pwm", "pclk", "osc";
|
||||
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm1m0_ch1>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm1_6ch_2: pwm@...d2000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2add2000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
+ clock-names = "pwm", "pclk", "osc";
|
||||
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm1m0_ch2>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm1_6ch_3: pwm@...d3000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2add3000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
+ clock-names = "pwm", "pclk", "osc";
|
||||
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm1m0_ch3>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm1_6ch_4: pwm@...d4000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2add4000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
+ clock-names = "pwm", "pclk", "osc";
|
||||
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm1m0_ch4>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm1_6ch_5: pwm@...d5000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2add5000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
+ clock-names = "pwm", "pclk", "osc";
|
||||
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm1m0_ch5>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm2_8ch_0: pwm@...e0000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2ade0000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm2m0_ch0>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm2_8ch_1: pwm@...e1000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2ade1000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm2m0_ch1>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm2_8ch_2: pwm@...e2000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2ade2000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm2m0_ch2>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm2_8ch_3: pwm@...e3000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2ade3000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm2m0_ch3>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm2_8ch_4: pwm@...e4000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2ade4000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm2m0_ch4>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm2_8ch_5: pwm@...e5000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2ade5000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm2m0_ch5>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm2_8ch_6: pwm@...e6000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2ade6000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm2m0_ch6>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm2_8ch_7: pwm@...e7000 {
|
||||
+ compatible = "rockchip,rk3576-pwm";
|
||||
+ reg = <0x0 0x2ade7000 0x0 0x1000>;
|
||||
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm2m0_ch7>;
|
||||
+ #pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
--
|
||||
2.49.0
|
||||
@ -0,0 +1,264 @@
|
||||
From 9e1942cc352cc9a697e37d64459616bd920f2eda Mon Sep 17 00:00:00 2001
|
||||
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
|
||||
Date: Tue, 25 Feb 2025 13:56:45 +0100
|
||||
Subject: [PATCH 1/4] arm64: dts: rockchip: Add thermal nodes to RK3576
|
||||
|
||||
Add the TSADC node to the RK3576. Additionally, add everything the TSADC
|
||||
needs to function, i.e. thermal zones, their trip points and maps, as
|
||||
well as adjust the CPU cooling-cells property.
|
||||
|
||||
The polling-delay properties are set to 0 as we do have interrupts for
|
||||
this TSADC on this particular SoC.
|
||||
|
||||
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 164 ++++++++++++++++++++++-
|
||||
1 file changed, 162 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
|
||||
@@ -11,6 +11,7 @@
|
||||
#include <dt-bindings/power/rockchip,rk3576-power.h>
|
||||
#include <dt-bindings/reset/rockchip,rk3576-cru.h>
|
||||
#include <dt-bindings/soc/rockchip,boot-mode.h>
|
||||
+#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3576";
|
||||
@@ -113,9 +114,9 @@
|
||||
capacity-dmips-mhz = <485>;
|
||||
clocks = <&scmi_clk SCMI_ARMCLK_L>;
|
||||
operating-points-v2 = <&cluster0_opp_table>;
|
||||
- #cooling-cells = <2>;
|
||||
dynamic-power-coefficient = <120>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
+ #cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu_l1: cpu@1 {
|
||||
@@ -127,6 +128,7 @@
|
||||
clocks = <&scmi_clk SCMI_ARMCLK_L>;
|
||||
operating-points-v2 = <&cluster0_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
+ #cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu_l2: cpu@2 {
|
||||
@@ -138,6 +140,7 @@
|
||||
clocks = <&scmi_clk SCMI_ARMCLK_L>;
|
||||
operating-points-v2 = <&cluster0_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
+ #cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu_l3: cpu@3 {
|
||||
@@ -149,6 +152,7 @@
|
||||
clocks = <&scmi_clk SCMI_ARMCLK_L>;
|
||||
operating-points-v2 = <&cluster0_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
+ #cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu_b0: cpu@100 {
|
||||
@@ -159,9 +163,9 @@
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&scmi_clk SCMI_ARMCLK_B>;
|
||||
operating-points-v2 = <&cluster1_opp_table>;
|
||||
- #cooling-cells = <2>;
|
||||
dynamic-power-coefficient = <320>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
+ #cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu_b1: cpu@101 {
|
||||
@@ -173,6 +177,7 @@
|
||||
clocks = <&scmi_clk SCMI_ARMCLK_B>;
|
||||
operating-points-v2 = <&cluster1_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
+ #cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu_b2: cpu@102 {
|
||||
@@ -184,6 +189,7 @@
|
||||
clocks = <&scmi_clk SCMI_ARMCLK_B>;
|
||||
operating-points-v2 = <&cluster1_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
+ #cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu_b3: cpu@103 {
|
||||
@@ -195,6 +201,7 @@
|
||||
clocks = <&scmi_clk SCMI_ARMCLK_B>;
|
||||
operating-points-v2 = <&cluster1_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
+ #cooling-cells = <2>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
@@ -520,6 +527,143 @@
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
+ thermal_zones: thermal-zones {
|
||||
+ /* sensor near the center of the SoC */
|
||||
+ package_thermal: package-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 0>;
|
||||
+
|
||||
+ trips {
|
||||
+ package_crit: package-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* sensor for cluster1 (big Cortex-A72 cores) */
|
||||
+ bigcore_thermal: bigcore-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 1>;
|
||||
+
|
||||
+ trips {
|
||||
+ bigcore_alert: bigcore-alert {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+
|
||||
+ bigcore_crit: bigcore-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&bigcore_alert>;
|
||||
+ cooling-device =
|
||||
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* sensor for cluster0 (little Cortex-A53 cores) */
|
||||
+ littlecore_thermal: littlecore-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 2>;
|
||||
+
|
||||
+ trips {
|
||||
+ littlecore_alert: littlecore-alert {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+
|
||||
+ littlecore_crit: littlecore-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&littlecore_alert>;
|
||||
+ cooling-device =
|
||||
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpu_thermal: gpu-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 3>;
|
||||
+
|
||||
+ trips {
|
||||
+ gpu_alert: gpu-alert {
|
||||
+ temperature = <85000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+
|
||||
+ gpu_crit: gpu-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&gpu_alert>;
|
||||
+ cooling-device =
|
||||
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ npu_thermal: npu-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 4>;
|
||||
+
|
||||
+ trips {
|
||||
+ npu_crit: npu-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ddr_thermal: ddr-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsadc 5>;
|
||||
+
|
||||
+ trips {
|
||||
+ ddr_crit: ddr-crit {
|
||||
+ temperature = <115000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
@@ -2301,6 +2445,22 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ tsadc: tsadc@2ae70000 {
|
||||
+ compatible = "rockchip,rk3576-tsadc";
|
||||
+ reg = <0x0 0x2ae70000 0x0 0x400>;
|
||||
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
||||
+ clock-names = "tsadc", "apb_pclk";
|
||||
+ assigned-clocks = <&cru CLK_TSADC>;
|
||||
+ assigned-clock-rates = <2000000>;
|
||||
+ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
|
||||
+ reset-names = "tsadc-apb", "tsadc";
|
||||
+ #thermal-sensor-cells = <1>;
|
||||
+ rockchip,hw-tshut-temp = <120000>;
|
||||
+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
||||
+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
||||
+ };
|
||||
+
|
||||
i2c9: i2c@2ae80000 {
|
||||
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0x2ae80000 0x0 0x1000>;
|
||||
Loading…
Reference in New Issue
Block a user