diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 2f0004f34..625367983 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,10 +5,10 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2020.07 -PKG_RELEASE:=3 +PKG_VERSION:=2021.01 +PKG_RELEASE:=1 -PKG_HASH:=c1f5bf9ee6bb6e648edbf19ce2ca9452f614b08a9f886f1a566aa42e8cf05f6a +PKG_HASH:=b407e1510a74e863b8b5cb42a24625344f0e0c2fc7582d8c866bd899367d0454 PKG_MAINTAINER:=Tobias Maedel @@ -38,22 +38,12 @@ endef # RK3399 boards -define U-Boot/nanopi-r4s-1gb-rk3399 +define U-Boot/nanopi-r4s-rk3399 BUILD_SUBTARGET:=armv8 - NAME:=NanoPi R4S 1GB + NAME:=NanoPi R4S BUILD_DEVICES:= \ - friendlyarm_nanopi-r4s-1gb - DEPENDS:=+PACKAGE_u-boot-nanopi-r4s-1gb-rk3399:arm-trusted-firmware-rockchip - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip - ATF:=rk3399_bl31.elf -endef - -define U-Boot/nanopi-r4s-4gb-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=NanoPi R4S 4GB - BUILD_DEVICES:= \ - friendlyarm_nanopi-r4s-4gb - DEPENDS:=+PACKAGE_u-boot-nanopi-r4s-4gb-rk3399:arm-trusted-firmware-rockchip + friendlyarm_nanopi-r4s + DEPENDS:=+PACKAGE_u-boot-nanopi-r4s-rk3399:arm-trusted-firmware-rockchip PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip ATF:=rk3399_bl31.elf endef @@ -79,8 +69,7 @@ define U-Boot/rockpro64-rk3399 endef UBOOT_TARGETS := \ - nanopi-r4s-1gb-rk3399 \ - nanopi-r4s-4gb-rk3399 \ + nanopi-r4s-rk3399 \ rock-pi-4-rk3399 \ rockpro64-rk3399 \ nanopi-r2s-rk3328 diff --git a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch index 4161c46ce..bd401103e 100644 --- a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch +++ b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch @@ -17,7 +17,7 @@ Signed-off-by: David Bauer --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl -@@ -320,12 +320,6 @@ PHONY += dts_dir +@@ -321,12 +321,6 @@ PHONY += dts_dir dts_dir: $(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts) diff --git a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch index bc65fb69e..60416a688 100644 --- a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch +++ b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -1,6 +1,6 @@ -From 67f4c228c2bf515386cd54073104dc2e6eae85ea Mon Sep 17 00:00:00 2001 +From 4189a8db90ca7edc16cf9509576ca2e74f028c1c Mon Sep 17 00:00:00 2001 From: David Bauer -Date: Fri, 10 Jul 2020 14:58:30 +0200 +Date: Thu, 7 Jan 2021 00:05:46 +0100 Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S This adds support for the NanoPi R2S from FriendlyArm. @@ -17,18 +17,18 @@ WAN - LAN - SYS LED Signed-off-by: David Bauer --- arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 34 +++ - arch/arm/dts/rk3328-nanopi-r2s.dts | 334 +++++++++++++++++++++ + arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 40 +++ + arch/arm/dts/rk3328-nanopi-r2s.dts | 370 +++++++++++++++++++++ board/rockchip/evb_rk3328/MAINTAINERS | 7 + - configs/nanopi-r2s-rk3328_defconfig | 99 ++++++ - 5 files changed, 475 insertions(+) + configs/nanopi-r2s-rk3328_defconfig | 98 ++++++ + 5 files changed, 516 insertions(+) create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts create mode 100644 configs/nanopi-r2s-rk3328_defconfig --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ +@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ @@ -38,7 +38,7 @@ Signed-off-by: David Bauer rk3328-rock-pi-e.dtb --- /dev/null +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi -@@ -0,0 +1,34 @@ +@@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd @@ -73,9 +73,15 @@ Signed-off-by: David Bauer +&vcc_sd { + u-boot,dm-spl; +}; ++ ++&gmac2io { ++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++}; --- /dev/null +++ b/arch/arm/dts/rk3328-nanopi-r2s.dts -@@ -0,0 +1,334 @@ +@@ -0,0 +1,370 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 David Bauer @@ -88,92 +94,91 @@ Signed-off-by: David Bauer +#include "rk3328.dtsi" + +/ { -+ model = "FriendlyARM NanoPi R2S"; ++ model = "FriendlyElec NanoPi R2S"; + compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + -+ gmac_clkin: external-gmac-clock { ++ gmac_clk: gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + -+ vcc_sd: sdmmc-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&reset_button_pin>; + pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0m1_gpio>; -+ regulator-name = "vcc_sd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_io>; -+ }; + -+ vcc_sdio: sdmmcio-regulator { -+ compatible = "regulator-gpio"; -+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ states = <1800000 0x1 -+ 3300000 0x0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio_vcc_pin>; -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_sdio"; -+ regulator-settling-time-us = <5000>; -+ regulator-type = "voltage"; -+ vin-supply = <&vcc_io>; -+ }; -+ -+ vcc_sys: vcc-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; ++ reset { ++ label = "reset"; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <50>; ++ }; + }; + + leds { + compatible = "gpio-leds"; -+ ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names = "default"; -+ pinctrl-0 = <&led_pins>; + -+ sys { -+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r2s:red:sys"; -+ }; -+ -+ lan { ++ lan_led: led-0 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:lan"; + }; + -+ wan { ++ sys_led: led-1 { ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r2s:red:sys"; ++ }; ++ ++ wan_led: led-2 { + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:wan"; + }; + }; + -+ gpio_keys { -+ compatible = "gpio-keys-polled"; -+ poll-interval = <100>; -+ ++ vcc_io_sdio: sdmmcio-regulator { ++ compatible = "regulator-gpio"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&sdio_vcc_pin>; + pinctrl-names = "default"; -+ pinctrl-0 = <&button_pins>; ++ regulator-name = "vcc_io_sdio"; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-settling-time-us = <5000>; ++ regulator-type = "voltage"; ++ startup-delay-us = <2000>; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ vin-supply = <&vcc_io_33>; ++ }; + -+ reset { -+ label = "Reset Button"; -+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <50>; -+ }; ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&sdmmc0m1_gpio>; ++ pinctrl-names = "default"; ++ regulator-name = "vcc_sd"; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_io_33>; ++ }; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; + }; +}; + @@ -195,19 +200,16 @@ Signed-off-by: David Bauer + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; ++ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; + clock_in_out = "input"; -+ phy-supply = <&vcc_io>; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; -+ pinctrl-names = "default"; ++ phy-supply = <&vcc_io_33>; + pinctrl-0 = <&rgmiim1_pins>; -+ snps,aal; -+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+ tx_delay = <0x24>; ++ pinctrl-names = "default"; + rx_delay = <0x18>; ++ snps,aal; ++ tx_delay = <0x24>; + status = "okay"; + + mdio { @@ -215,8 +217,15 @@ Signed-off-by: David Bauer + #address-cells = <1>; + #size-cells = <0>; + -+ rtl8211e: ethernet-phy@0 { -+ reg = <0>; ++ rtl8211e: ethernet-phy@1 { ++ compatible = "ethernet-phy-id001c.c915", ++ "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -224,35 +233,36 @@ Signed-off-by: David Bauer +&i2c1 { + status = "okay"; + -+ rk805: rk805@18 { ++ rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; -+ interrupt-parent = <&gpio2>; -+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; -+ pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; ++ pinctrl-names = "default"; + rockchip,system-power-controller; + wakeup-source; + -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc5-supply = <&vcc_io>; -+ vcc6-supply = <&vcc_sys>; ++ vcc1-supply = <&vdd_5v>; ++ vcc2-supply = <&vdd_5v>; ++ vcc3-supply = <&vdd_5v>; ++ vcc4-supply = <&vdd_5v>; ++ vcc5-supply = <&vcc_io_33>; ++ vcc6-supply = <&vdd_5v>; + + regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; ++ vdd_log: DCDC_REG1 { ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; -+ regulator-always-on; -+ regulator-boot-on; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; @@ -261,11 +271,12 @@ Signed-off-by: David Bauer + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; ++ regulator-always-on; ++ regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; -+ regulator-always-on; -+ regulator-boot-on; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; @@ -276,17 +287,19 @@ Signed-off-by: David Bauer + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; ++ + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + -+ vcc_io: DCDC_REG4 { -+ regulator-name = "vcc_io"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; ++ vcc_io_33: DCDC_REG4 { ++ regulator-name = "vcc_io_33"; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; @@ -295,10 +308,11 @@ Signed-off-by: David Bauer + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; @@ -307,10 +321,11 @@ Signed-off-by: David Bauer + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; @@ -319,10 +334,11 @@ Signed-off-by: David Bauer + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; @@ -333,35 +349,46 @@ Signed-off-by: David Bauer +}; + +&io_domains { -+ status = "okay"; -+ -+ vccio1-supply = <&vcc_io>; ++ pmuio-supply = <&vcc_io_33>; ++ vccio1-supply = <&vcc_io_33>; + vccio2-supply = <&vcc18_emmc>; -+ vccio3-supply = <&vcc_sdio>; ++ vccio3-supply = <&vcc_io_sdio>; + vccio4-supply = <&vcc_18>; -+ vccio5-supply = <&vcc_io>; -+ vccio6-supply = <&vcc_io>; -+ pmuio-supply = <&vcc_io>; ++ vccio5-supply = <&vcc_io_33>; ++ vccio6-supply = <&vcc_io_33>; ++ status = "okay"; +}; + +&pinctrl { -+ leds { -+ led_pins: led-pins { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, -+ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, -+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ button { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + -+ button { -+ button_pins: button-pins { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ ethernet-phy { ++ eth_phy_reset_pin: eth-phy-reset-pin { ++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { -+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + @@ -372,16 +399,22 @@ Signed-off-by: David Bauer + }; +}; + ++&pwm2 { ++ status = "okay"; ++}; ++ +&sdmmc { + bus-width = <4>; -+ cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; -+ max-frequency = <150000000>; ++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; -+ vqmmc-supply = <&vcc_sdio>; ++ vqmmc-supply = <&vcc_io_sdio>; + status = "okay"; +}; + @@ -391,16 +424,25 @@ Signed-off-by: David Bauer + status = "okay"; +}; + ++&u2phy { ++ status = "okay"; ++}; ++ ++&u2phy_host { ++ status = "okay"; ++}; ++ ++&u2phy_otg { ++ status = "okay"; ++}; ++ +&uart2 { + status = "okay"; +}; + -+&u2phy { ++&usb20_otg { + status = "okay"; -+ -+ u2phy_host: host-port { -+ status = "okay"; -+ }; ++ dr_mode = "host"; +}; + +&usb_host0_ehci { @@ -428,7 +470,7 @@ Signed-off-by: David Bauer M: Chen-Yu Tsai --- /dev/null +++ b/configs/nanopi-r2s-rk3328_defconfig -@@ -0,0 +1,99 @@ +@@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 @@ -443,7 +485,7 @@ Signed-off-by: David Bauer +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SMBIOS_PRODUCT_NAME="nanopi_r2s_rk3328" ++CONFIG_SYSINFO=y +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +# CONFIG_ANDROID_BOOT_IMAGE is not set @@ -527,4 +569,3 @@ Signed-off-by: David Bauer +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -+CONFIG_SMBIOS_MANUFACTURER="pine64" diff --git a/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch b/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch new file mode 100644 index 000000000..f63081835 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch @@ -0,0 +1,27 @@ +From 2114d68b3c755ec8043ae9e43ac8e9753e0cec84 Mon Sep 17 00:00:00 2001 +From: Marty Jones +Date: Sun, 17 Jan 2021 15:26:09 -0500 +Subject: [PATCH] rockpro64: disable CONFIG_USE_PREBOOT + +On commit https://github.com/u-boot/u-boot/commit/f81f9f0ebac596bae7f27db095f4f0272b606cc3 +CONFIG_USE_PREBOOT was enabled on the RockPro64. + +When the board is booting, U-Boot hangs as soon as it disables the USB +controller. This is a workaround until a final solution is deployed +upstream. + +Signed-off-by: Marty Jones +--- + configs/rockpro64-rk3399_defconfig | 1 - + 1 file changed, 1 deletion(-) + +--- a/configs/rockpro64-rk3399_defconfig ++++ b/configs/rockpro64-rk3399_defconfig +@@ -12,7 +12,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI_SUPPORT=y + CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" + CONFIG_DEBUG_UART=y +-CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_MISC_INIT_R=y diff --git a/package/boot/uboot-rockchip/patches/101-rockchip-rk3328-fix-nanopi-r2s-failed-to-boot-on-som.patch b/package/boot/uboot-rockchip/patches/101-rockchip-rk3328-fix-nanopi-r2s-failed-to-boot-on-som.patch deleted file mode 100644 index be417adcf..000000000 --- a/package/boot/uboot-rockchip/patches/101-rockchip-rk3328-fix-nanopi-r2s-failed-to-boot-on-som.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Yuan Tao -Date: Sun, 9 Aug 2020 09:02:55 +0800 -Subject: [PATCH] rockchip: rk3328: fix nanopi-r2s failed to boot on some sd cards - -Issues: -When booting on some SD cards an error message appears as: -"spl: mmc init failed with error: -95" - -Solutions: -Add regulator-boot-on parameters to vcc_sd. -Add startup-delay-us parameters to vcc_sdio. -This will improve the problem that in some SD cards are failing to boot up. - -Tested environment: -SD Card: Netac Extreme P500 Pro 32GB - -Signed-off-by: Yuan Tao ---- - ---- a/arch/arm/dts/rk3328-nanopi-r2s.dts -+++ b/arch/arm/dts/rk3328-nanopi-r2s.dts -@@ -32,6 +32,7 @@ - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -+ regulator-boot-on; - vin-supply = <&vcc_io>; - }; - -@@ -49,6 +50,7 @@ - regulator-name = "vcc_sdio"; - regulator-settling-time-us = <5000>; - regulator-type = "voltage"; -+ startup-delay-us = <2000>; - vin-supply = <&vcc_io>; - }; - diff --git a/package/boot/uboot-rockchip/patches/200-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/200-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch deleted file mode 100644 index 57911fa12..000000000 --- a/package/boot/uboot-rockchip/patches/200-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch +++ /dev/null @@ -1,411 +0,0 @@ -From 0aa583056cb1727fc09f4feca670d57634eb5605 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Sat, 19 Dec 2020 11:49:33 +0000 -Subject: [PATCH] rockchip: rk3399: Add support for FriendlyARM NanoPi R4S - -This adds support for the NanoPi R4S from FriendlyArm. - -Rockchip RK3399 SoC -1GB DDR3 or 4GB LPDDR4 RAM -Gigabit Ethernet (WAN) -Gigabit Ethernet (PCIe) (LAN) -USB 3.0 Host Port x 2 -MicroSD slot -Reset button -WAN - LAN - SYS LED - -Signed-off-by: Tianling Shen -Co-authored-by: Marty Jones -Signed-off-by: Marty Jones ---- - arch/arm/dts/Makefile | 2 + - .../arm/dts/rk3399-nanopi-r4s-1gb-u-boot.dtsi | 9 ++ - arch/arm/dts/rk3399-nanopi-r4s-1gb.dts | 27 + - .../arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi | 9 ++ - arch/arm/dts/rk3399-nanopi-r4s-4gb.dts | 27 + - arch/arm/dts/rk3399-nanopi-r4s.dtsi | 122 ++++++++++++++++++ - board/rockchip/evb_rk3399/MAINTAINERS | 14 ++ - configs/nanopi-r4s-1gb-rk3399_defconfig | 61 ++++++++ - configs/nanopi-r4s-4gb-rk3399_defconfig | 62 ++++++++ - 9 files changed, 333 insertions(+) - create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-1gb-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-1gb.dts - create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-4gb.dts - create mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dtsi - create mode 100644 configs/nanopi-r4s-1gb-rk3399_defconfig - create mode 100644 configs/nanopi-r4s-4gb-rk3399_defconfig - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -130,6 +130,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - rk3399-nanopi-m4.dtb \ - rk3399-nanopi-m4-2gb.dtb \ - rk3399-nanopi-neo4.dtb \ -+ rk3399-nanopi-r4s-1gb.dtb \ -+ rk3399-nanopi-r4s-4gb.dtb \ - rk3399-orangepi.dtb \ - rk3399-pinebook-pro.dtb \ - rk3399-puma-haikou.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3399-nanopi-r4s-1gb-u-boot.dtsi -@@ -0,0 +1,9 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd -+ * (C) Copyright 2020 Marty Jones -+ * (C) Copyright 2020 Tianling Shen -+ */ -+ -+#include "rk3399-nanopi4-u-boot.dtsi" -+#include "rk3399-sdram-ddr3-1600.dtsi" ---- /dev/null -+++ b/arch/arm/dts/rk3399-nanopi-r4s-1gb.dts -@@ -0,0 +1,27 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3399-nanopi-r4s.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPi R4S (1GB)"; -+ compatible = "friendlyarm,nanopi-r4s-1gb", "rockchip,rk3399"; -+}; -+ -+&leds { -+ /delete-node/ status; -+ -+ lan_led: led-0 { -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r4s-1gb:green:lan"; -+ }; -+ -+ sys_led: led-1 { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r4s-1gb:red:sys"; -+ }; -+ -+ wan_led: led-2 { -+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r4s-1gb:green:wan"; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi -@@ -0,0 +1,9 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd -+ * (C) Copyright 2020 Marty Jones -+ * (C) Copyright 2020 Tianling Shen -+ */ -+ -+#include "rk3399-nanopi4-u-boot.dtsi" -+#include "rk3399-sdram-lpddr4-100.dtsi" ---- /dev/null -+++ b/arch/arm/dts/rk3399-nanopi-r4s-4gb.dts -@@ -0,0 +1,27 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3399-nanopi-r4s.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPi R4S (4GB)"; -+ compatible = "friendlyarm,nanopi-r4s-4gb", "rockchip,rk3399"; -+}; -+ -+&leds { -+ /delete-node/ status; -+ -+ lan_led: led-0 { -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r4s-4gb:green:lan"; -+ }; -+ -+ sys_led: led-1 { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r4s-4gb:red:sys"; -+ }; -+ -+ wan_led: led-2 { -+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r4s-4gb:green:wan"; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3399-nanopi-r4s.dtsi -@@ -0,0 +1,122 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Marty Jones -+ * Copyright (c) 2020 Tianling Shen -+ */ -+ -+/dts-v1/; -+#include "rk3399-nanopi4.dtsi" -+ -+/ { -+ aliases { -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; -+ ethernet1 = &r8169; -+ }; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ /* FIXME: adjust leveles for the connected fan */ -+ cooling-levels = <0 12 18 255>; -+ #cooling-cells = <2>; -+ fan-supply = <&vdd_5v>; -+ pwms = <&pwm1 0 50000 0>; -+ }; -+}; -+ -+&cpu_thermal { -+ trips { -+ cpu_warm: cpu_warm { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_hot: cpu_hot { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map2 { -+ trip = <&cpu_warm>; -+ cooling-device = <&fan THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map3 { -+ trip = <&cpu_hot>; -+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ -+&emmc_phy { -+ status = "disabled"; -+}; -+ -+&fusb0 { -+ status = "disabled"; -+}; -+ -+&leds_gpio { -+ rockchip,pins = -+ <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, -+ <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, -+ <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+}; -+ -+&pcie0 { -+ max-link-speed = <1>; -+ num-lanes = <1>; -+ vpcie3v3-supply = <&vcc3v3_sys>; -+ -+ pcie@0 { -+ reg = <0x00000000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ r8169: pcie@0,0 { -+ reg = <0x000000 0 0 0 0>; -+ local-mac-address = [ 00 00 00 00 00 00 ]; -+ }; -+ }; -+}; -+ -+&sdhci { -+ status = "disabled"; -+}; -+ -+&sdio0 { -+ status = "disabled"; -+}; -+ -+&sdmmc { -+ host-index-min = <1>; -+}; -+ -+&u2phy0_host { -+ phy-supply = <&vdd_5v>; -+}; -+ -+&u2phy1_host { -+ status = "disabled"; -+}; -+ -+&usbdrd_dwc3_0 { -+ dr_mode = "host"; -+}; -+ -+&vcc3v3_sys { -+ vin-supply = <&vcc5v0_sys>; -+}; ---- a/board/rockchip/evb_rk3399/MAINTAINERS -+++ b/board/rockchip/evb_rk3399/MAINTAINERS -@@ -55,6 +55,20 @@ S: Maintained - F: configs/nanopi-neo4-rk3399_defconfig - F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi - -+NANOPI-R4S-1GB -+M: Marty Jones -+M: Tianling Shen -+S: Maintained -+F: configs/nanopi-r4s-1gb-rk3399_defconfig -+F: arch/arm/dts/rk3399-nanopi-r4s-1gb-u-boot.dtsi -+ -+NANOPI-R4S-4GB -+M: Marty Jones -+M: Tianling Shen -+S: Maintained -+F: configs/nanopi-r4s-4gb-rk3399_defconfig -+F: arch/arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi -+ - ORANGEPI-RK3399 - M: Jagan Teki - S: Maintained ---- /dev/null -+++ b/configs/nanopi-r4s-1gb-rk3399_defconfig -@@ -0,0 +1,61 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_EVB_RK3399=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s-1gb.dtb" -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s-1gb" -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_ASIX88179=y -+CONFIG_USB_ETHER_MCS7830=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y ---- /dev/null -+++ b/configs/nanopi-r4s-4gb-rk3399_defconfig -@@ -0,0 +1,62 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_EVB_RK3399=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s-4gb.dtb" -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s-4gb" -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM_RK3399_LPDDR4=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_ASIX88179=y -+CONFIG_USB_ETHER_MCS7830=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y - diff --git a/package/boot/uboot-rockchip/patches/200-rockchip-rk3399-split-nanopi-r4-rk3399-out-of-evb_rk.patch b/package/boot/uboot-rockchip/patches/200-rockchip-rk3399-split-nanopi-r4-rk3399-out-of-evb_rk.patch new file mode 100644 index 000000000..d8a118dd2 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/200-rockchip-rk3399-split-nanopi-r4-rk3399-out-of-evb_rk.patch @@ -0,0 +1,509 @@ +From a765bb2678b6d1666caafef0fcf88fba88b5b26f Mon Sep 17 00:00:00 2001 +From: hmz007 +Date: Fri, 18 Dec 2020 17:10:35 +0800 +Subject: [PATCH] rockchip: rk3399: split nanopi-r4-rk3399 out of evb_rk3399 + +nanopi-r4-rk3399 board has multiple DDR types. Currently we don't have any code +are compatible with these devices. Since multiple DDR types is specific to +nanopi-r4-rk3399 board, split it into its own board file and add code +support here. + +Signed-off-by: hmz007 +[Improved commit message and Kconfig description] +Signed-off-by: Tianling Shen +--- + arch/arm/mach-rockchip/rk3399/Kconfig | 15 +++ + board/friendlyarm/nanopi4/Kconfig | 15 +++ + board/friendlyarm/nanopi4/MAINTAINERS | 5 + + board/friendlyarm/nanopi4/Makefile | 8 ++ + board/friendlyarm/nanopi4/hwrev.c | 185 ++++++++++++++++++++++++++ + board/friendlyarm/nanopi4/hwrev.h | 27 ++++ + board/friendlyarm/nanopi4/nanopi4.c | 148 +++++++++++++++++++++ + drivers/clk/rockchip/clk_rk3399.c | 2 + + include/configs/nanopi4.h | 24 ++++ + 9 files changed, 429 insertions(+) + create mode 100644 board/friendlyarm/nanopi4/Kconfig + create mode 100644 board/friendlyarm/nanopi4/MAINTAINERS + create mode 100644 board/friendlyarm/nanopi4/Makefile + create mode 100644 board/friendlyarm/nanopi4/hwrev.c + create mode 100644 board/friendlyarm/nanopi4/hwrev.h + create mode 100644 board/friendlyarm/nanopi4/nanopi4.c + create mode 100644 include/configs/nanopi4.h + +--- a/arch/arm/mach-rockchip/rk3399/Kconfig ++++ b/arch/arm/mach-rockchip/rk3399/Kconfig +@@ -109,6 +109,20 @@ config TARGET_ROC_PC_RK3399 + * wide voltage input(5V-15V), dual cell battery + * Wifi/BT accessible via expansion board M.2 + ++config TARGET_NANOPI4_RK3399 ++ bool "FriendlyElec NanoPi4 board" ++ help ++ NanoPi4 is SBC produced by FriendlyElec. Key features: ++ ++ * Rockchip RK3399 ++ * 1/2/4GB Dual-Channel DDR3/LPDDR4 ++ * SD card slot ++ * Gigabit ethernet ++ * PCIe ++ * USB 3.0, 2.0 ++ * USB Type C power ++ * GPIO expansion ports ++ + endchoice + + config ROCKCHIP_BOOT_MODE_REG +@@ -152,6 +166,7 @@ config SYS_BOOTCOUNT_ADDR + endif # BOOTCOUNT_LIMIT + + source "board/firefly/roc-pc-rk3399/Kconfig" ++source "board/friendlyarm/nanopi4/Kconfig" + source "board/google/gru/Kconfig" + source "board/pine64/pinebook-pro-rk3399/Kconfig" + source "board/pine64/rockpro64_rk3399/Kconfig" +--- /dev/null ++++ b/board/friendlyarm/nanopi4/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_NANOPI4_RK3399 ++ ++config SYS_BOARD ++ default "nanopi4" ++ ++config SYS_VENDOR ++ default "friendlyarm" ++ ++config SYS_CONFIG_NAME ++ default "nanopi4" ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ ++endif +--- /dev/null ++++ b/board/friendlyarm/nanopi4/MAINTAINERS +@@ -0,0 +1,5 @@ ++NanoPi 4 Series ++M: FriendlyElec ++S: Maintained ++F: board/friendlyarm/nanopi4/ ++F: include/configs/nanopi4.h +--- /dev/null ++++ b/board/friendlyarm/nanopi4/Makefile +@@ -0,0 +1,8 @@ ++# ++# Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd. ++# (http://www.friendlyarm.com) ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y += nanopi4.o hwrev.o +--- /dev/null ++++ b/board/friendlyarm/nanopi4/hwrev.c +@@ -0,0 +1,185 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * ID info: ++ * ID : Volts : ADC value : Bucket ++ * == ===== ========= =========== ++ * 0 : 0.102V: 58 : 0 - 81 ++ * 1 : 0.211V: 120 : 82 - 150 ++ * 2 : 0.319V: 181 : 151 - 211 ++ * 3 : 0.427V: 242 : 212 - 274 ++ * 4 : 0.542V: 307 : 275 - 342 ++ * 5 : 0.666V: 378 : 343 - 411 ++ * 6 : 0.781V: 444 : 412 - 477 ++ * 7 : 0.900V: 511 : 478 - 545 ++ * 8 : 1.023V: 581 : 546 - 613 ++ * 9 : 1.137V: 646 : 614 - 675 ++ * 10 : 1.240V: 704 : 676 - 733 ++ * 11 : 1.343V: 763 : 734 - 795 ++ * 12 : 1.457V: 828 : 796 - 861 ++ * 13 : 1.576V: 895 : 862 - 925 ++ * 14 : 1.684V: 956 : 926 - 989 ++ * 15 : 1.800V: 1023 : 990 - 1023 ++ */ ++static const int id_readings[] = { ++ 81, 150, 211, 274, 342, 411, 477, 545, ++ 613, 675, 733, 795, 861, 925, 989, 1023 ++}; ++ ++static int cached_board_id = -1; ++ ++#define SARADC_BASE 0xFF100000 ++#define SARADC_DATA (SARADC_BASE + 0) ++#define SARADC_CTRL (SARADC_BASE + 8) ++ ++static u32 get_saradc_value(int chn) ++{ ++ int timeout = 0; ++ u32 adc_value = 0; ++ ++ writel(0, SARADC_CTRL); ++ udelay(2); ++ ++ writel(0x28 | chn, SARADC_CTRL); ++ udelay(50); ++ ++ timeout = 0; ++ do { ++ if (readl(SARADC_CTRL) & 0x40) { ++ adc_value = readl(SARADC_DATA) & 0x3FF; ++ goto stop_adc; ++ } ++ ++ udelay(10); ++ } while (timeout++ < 100); ++ ++stop_adc: ++ writel(0, SARADC_CTRL); ++ ++ return adc_value; ++} ++ ++static uint32_t get_adc_index(int chn) ++{ ++ int i; ++ int adc_reading; ++ ++ if (cached_board_id != -1) ++ return cached_board_id; ++ ++ adc_reading = get_saradc_value(chn); ++ for (i = 0; i < ARRAY_SIZE(id_readings); i++) { ++ if (adc_reading <= id_readings[i]) { ++ debug("ADC reading %d, ID %d\n", adc_reading, i); ++ cached_board_id = i; ++ return i; ++ } ++ } ++ ++ /* should die for impossible value */ ++ return 0; ++} ++ ++/* ++ * Board revision list: ++ * 0b00 - NanoPC-T4 ++ * 0b01 - NanoPi M4 ++ * ++ * Extended by ADC_IN4 ++ * Group A: ++ * 0x04 - NanoPi NEO4 ++ * 0x06 - SOC-RK3399 ++ * 0x07 - SOC-RK3399 V2 ++ * 0x09 - NanoPi R4S 1GB ++ * 0x0A - NanoPi R4S 4GB ++ * ++ * Group B: ++ * 0x21 - NanoPi M4 Ver2.0 ++ * 0x22 - NanoPi M4B ++ */ ++static int pcb_rev = -1; ++ ++void bd_hwrev_init(void) ++{ ++#define GPIO4_BASE 0xff790000 ++ struct rockchip_gpio_regs *regs = (void *)GPIO4_BASE; ++ ++#ifdef CONFIG_SPL_BUILD ++ struct udevice *dev; ++ ++ if (uclass_get_device_by_driver(UCLASS_CLK, ++ DM_GET_DRIVER(clk_rk3399), &dev)) ++ return; ++#endif ++ ++ if (pcb_rev >= 0) ++ return; ++ ++ /* D1, D0: input mode */ ++ clrbits_le32(®s->swport_ddr, (0x3 << 24)); ++ pcb_rev = (readl(®s->ext_port) >> 24) & 0x3; ++ ++ if (pcb_rev == 0x3) { ++ /* Revision group A: 0x04 ~ 0x13 */ ++ pcb_rev = 0x4 + get_adc_index(4); ++ ++ } else if (pcb_rev == 0x1) { ++ int idx = get_adc_index(4); ++ ++ /* Revision group B: 0x21 ~ 0x2f */ ++ if (idx > 0) { ++ pcb_rev = 0x20 + idx; ++ } ++ } ++} ++ ++#ifdef CONFIG_SPL_BUILD ++static struct board_ddrtype { ++ int rev; ++ const char *type; ++} ddrtypes[] = { ++ { 0x00, "lpddr3-samsung-4GB-1866" }, ++ { 0x01, "lpddr3-samsung-4GB-1866" }, ++ { 0x04, "ddr3-1866" }, ++ { 0x06, "ddr3-1866" }, ++ { 0x07, "lpddr4-100" }, ++ { 0x09, "ddr3-1866" }, ++ { 0x0a, "lpddr4-100" }, ++ { 0x21, "lpddr4-100" }, ++ { 0x22, "ddr3-1866" }, ++}; ++ ++const char *rk3399_get_ddrtype(void) { ++ int i; ++ ++ bd_hwrev_init(); ++ printf("Board: rev%02x\n", pcb_rev); ++ ++ for (i = 0; i < ARRAY_SIZE(ddrtypes); i++) { ++ if (ddrtypes[i].rev == pcb_rev) ++ return ddrtypes[i].type; ++ } ++ ++ /* fallback to first subnode (ie, first included dtsi) */ ++ return NULL; ++} ++#endif ++ ++/* To override __weak symbols */ ++u32 get_board_rev(void) ++{ ++ return pcb_rev; ++} ++ +--- /dev/null ++++ b/board/friendlyarm/nanopi4/hwrev.h +@@ -0,0 +1,27 @@ ++/* ++ * Copyright (C) Guangzhou FriendlyARM Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, you can access it online at ++ * http://www.gnu.org/licenses/gpl-2.0.html. ++ */ ++ ++#ifndef __BD_HW_REV_H__ ++#define __BD_HW_REV_H__ ++ ++extern void bd_hwrev_config_gpio(void); ++extern void bd_hwrev_init(void); ++extern u32 get_board_rev(void); ++ ++#endif /* __BD_HW_REV_H__ */ +--- /dev/null ++++ b/board/friendlyarm/nanopi4/nanopi4.c +@@ -0,0 +1,148 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_MISC_INIT_R ++static void setup_iodomain(void) ++{ ++ struct rk3399_grf_regs *grf = ++ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ ++ /* BT565 and AUDIO is in 1.8v domain */ ++ rk_setreg(&grf->io_vsel, BIT(0) | BIT(1)); ++} ++ ++static int __maybe_unused mac_read_from_generic_eeprom(u8 *addr) ++{ ++ struct udevice *i2c_dev; ++ int ret; ++ ++ /* Microchip 24AA02xxx EEPROMs with EUI-48 Node Identity */ ++ ret = i2c_get_chip_for_busnum(2, 0x51, 1, &i2c_dev); ++ if (!ret) ++ ret = dm_i2c_read(i2c_dev, 0xfa, addr, 6); ++ ++ return ret; ++} ++ ++static void setup_macaddr(void) ++{ ++#if CONFIG_IS_ENABLED(CMD_NET) ++ int ret; ++ const char *cpuid = env_get("cpuid#"); ++ u8 hash[SHA256_SUM_LEN]; ++ int size = sizeof(hash); ++ u8 mac_addr[6]; ++ int from_eeprom = 0; ++ int lockdown = 0; ++ ++#ifndef CONFIG_ENV_IS_NOWHERE ++ lockdown = env_get_yesno("lockdown") == 1; ++#endif ++ if (lockdown && env_get("ethaddr")) ++ return; ++ ++ ret = mac_read_from_generic_eeprom(mac_addr); ++ if (!ret && is_valid_ethaddr(mac_addr)) { ++ eth_env_set_enetaddr("ethaddr", mac_addr); ++ from_eeprom = 1; ++ } ++ ++ if (!cpuid) { ++ debug("%s: could not retrieve 'cpuid#'\n", __func__); ++ return; ++ } ++ ++ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); ++ if (ret) { ++ debug("%s: failed to calculate SHA256\n", __func__); ++ return; ++ } ++ ++ /* Copy 6 bytes of the hash to base the MAC address on */ ++ memcpy(mac_addr, hash, 6); ++ ++ /* Make this a valid MAC address and set it */ ++ mac_addr[0] &= 0xfe; /* clear multicast bit */ ++ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ ++ ++ if (from_eeprom) { ++ eth_env_set_enetaddr("eth1addr", mac_addr); ++ } else { ++ eth_env_set_enetaddr("ethaddr", mac_addr); ++ ++ if (lockdown && env_get("eth1addr")) ++ return; ++ ++ /* Ugly, copy another 4 bytes to generate a similar address */ ++ memcpy(mac_addr + 2, hash + 8, 4); ++ if (!memcmp(hash + 2, hash + 8, 4)) ++ mac_addr[5] ^= 0xff; ++ ++ eth_env_set_enetaddr("eth1addr", mac_addr); ++ } ++#endif ++ ++ return; ++} ++ ++int misc_init_r(void) ++{ ++ const u32 cpuid_offset = 0x7; ++ const u32 cpuid_length = 0x10; ++ u8 cpuid[cpuid_length]; ++ int ret; ++ ++ setup_iodomain(); ++ ++ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); ++ if (ret) ++ return ret; ++ ++ ret = rockchip_cpuid_set(cpuid, cpuid_length); ++ if (ret) ++ return ret; ++ ++ setup_macaddr(); ++ bd_hwrev_init(); ++ ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_SERIAL_TAG ++void get_board_serial(struct tag_serialnr *serialnr) ++{ ++ char *serial_string; ++ u64 serial = 0; ++ ++ serial_string = env_get("serial#"); ++ ++ if (serial_string) ++ serial = simple_strtoull(serial_string, NULL, 16); ++ ++ serialnr->high = (u32)(serial >> 32); ++ serialnr->low = (u32)(serial & 0xffffffff); ++} ++#endif +diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c +index 22c373a623..38975c0c65 100644 +--- a/drivers/clk/rockchip/clk_rk3399.c ++++ b/drivers/clk/rockchip/clk_rk3399.c +@@ -1351,6 +1351,8 @@ static void rkclk_init(struct rockchip_cru *cru) + pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | + hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | + HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); ++ ++ rk3399_saradc_set_clk(cru, 1000000); + } + #endif + +--- /dev/null ++++ b/include/configs/nanopi4.h +@@ -0,0 +1,24 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * (C) Copyright 2016 Rockchip Electronics Co., Ltd ++ */ ++ ++#ifndef __CONFIG_NANOPI4_H__ ++#define __CONFIG_NANOPI4_H__ ++ ++#define ROCKCHIP_DEVICE_SETTINGS \ ++ "stdin=serial,usbkbd\0" \ ++ "stdout=serial,vidconsole\0" \ ++ "stderr=serial,vidconsole\0" ++ ++#include ++ ++#define SDRAM_BANK_SIZE (2UL << 30) ++ ++#define CONFIG_SERIAL_TAG ++#define CONFIG_REVISION_TAG ++ ++#endif diff --git a/package/boot/uboot-rockchip/patches/201-ram-rk3399-Add-support-for-multiple-DDR-types.patch b/package/boot/uboot-rockchip/patches/201-ram-rk3399-Add-support-for-multiple-DDR-types.patch new file mode 100644 index 000000000..b624bcc76 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/201-ram-rk3399-Add-support-for-multiple-DDR-types.patch @@ -0,0 +1,256 @@ +From a9447b7b60a3c5195d0fabbe5aa9c32d047ec997 Mon Sep 17 00:00:00 2001 +From: hmz007 +Date: Sat, 19 Dec 2020 19:39:14 +0800 +Subject: [PATCH] ram: rk3399: Add support for multiple DDR types + +Move rockchip,sdram-params to named subnode to include +multiple sdram parameters, and then read the parameters +(by subnode name, first subnode or current node) before +rk3399_dmc_init(). + +Signed-off-by: hmz007 +--- + arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi | 6 ++- + arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi | 5 +- + arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi | 6 ++- + .../arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi | 3 ++ + .../arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi | 3 ++ + .../rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi | 3 ++ + arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 3 ++ + drivers/ram/rockchip/sdram_rk3399.c | 49 +++++++++++++++---- + 8 files changed, 64 insertions(+), 14 deletions(-) + +--- a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi ++++ b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi +@@ -4,7 +4,9 @@ + */ + + &dmc { +- rockchip,sdram-params = < ++ ddr3-1333 { ++ u-boot,dm-pre-reloc; ++ rockchip,sdram-params = < + 0x1 + 0xa + 0x3 +@@ -1536,5 +1538,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +- +--- a/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi ++++ b/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi +@@ -4,7 +4,9 @@ + */ + + &dmc { +- rockchip,sdram-params = < ++ ddr3-1600 { ++ u-boot,dm-pre-reloc; ++ rockchip,sdram-params = < + 0x1 + 0xa + 0x3 +@@ -1536,4 +1538,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +--- a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi ++++ b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi +@@ -4,7 +4,9 @@ + */ + + &dmc { +- rockchip,sdram-params = < ++ ddr3-1866 { ++ u-boot,dm-pre-reloc; ++ rockchip,sdram-params = < + 0x1 + 0xa + 0x3 +@@ -1536,5 +1538,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +- +--- a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi ++++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi +@@ -5,6 +5,8 @@ + */ + + &dmc { ++ lpddr3-2GB-1600 { ++ u-boot,dm-pre-reloc; + rockchip,sdram-params = < + 0x1 + 0xa +@@ -1537,4 +1539,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +--- a/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi ++++ b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi +@@ -4,6 +4,8 @@ + */ + + &dmc { ++ lpddr3-4GB-1600 { ++ u-boot,dm-pre-reloc; + rockchip,sdram-params = < + 0x2 + 0xa +@@ -1536,4 +1538,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +--- a/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi ++++ b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi +@@ -4,6 +4,8 @@ + */ + + &dmc { ++ lpddr3-samsung-4GB-1866 { ++ u-boot,dm-pre-reloc; + rockchip,sdram-params = < + 0x2 + 0xa +@@ -1543,4 +1545,5 @@ + 0x01010000 /* DENALI_PHY_957_DATA */ + 0x00000000 /* DENALI_PHY_958_DATA */ + >; ++ }; + }; +--- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi ++++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi +@@ -6,6 +6,8 @@ + */ + + &dmc { ++ lpddr4-100 { ++ u-boot,dm-pre-reloc; + rockchip,sdram-params = < + 0x2 + 0xa +@@ -1538,4 +1540,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +--- a/drivers/ram/rockchip/sdram_rk3399.c ++++ b/drivers/ram/rockchip/sdram_rk3399.c +@@ -1625,7 +1625,6 @@ static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride) + rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10); + } + +-#if !defined(CONFIG_RAM_RK3399_LPDDR4) + static int data_training_first(struct dram_info *dram, u32 channel, u8 rank, + struct rk3399_sdram_params *params) + { +@@ -1715,8 +1714,8 @@ void modify_param(const struct chan_info *chan, + clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24); + clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1); + } +-#else + ++#if defined(CONFIG_RAM_RK3399_LPDDR4) + struct rk3399_sdram_params dfs_cfgs_lpddr4[] = { + #include "sdram-rk3399-lpddr4-400.inc" + #include "sdram-rk3399-lpddr4-800.inc" +@@ -3011,20 +3010,40 @@ static int sdram_init(struct dram_info *dram, + return 0; + } + ++__weak const char *rk3399_get_ddrtype(void) ++{ ++ return NULL; ++} ++ + static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev) + { + #if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_dmc_plat *plat = dev_get_platdata(dev); ++ ofnode node = { .np = NULL }; ++ const char *name; + int ret; + +- ret = dev_read_u32_array(dev, "rockchip,sdram-params", +- (u32 *)&plat->sdram_params, +- sizeof(plat->sdram_params) / sizeof(u32)); ++ name = rk3399_get_ddrtype(); ++ if (name) ++ node = dev_read_subnode(dev, name); ++ if (!ofnode_valid(node)) { ++ debug("Failed to read subnode %s\n", name); ++ node = dev_read_first_subnode(dev); ++ } ++ ++ /* fallback to current node */ ++ if (!ofnode_valid(node)) ++ node = dev_ofnode(dev); ++ ++ ret = ofnode_read_u32_array(node, "rockchip,sdram-params", ++ (u32 *)&plat->sdram_params, ++ sizeof(plat->sdram_params) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,sdram-params %d\n", + __func__, ret); + return ret; + } ++ + ret = regmap_init_mem(dev_ofnode(dev), &plat->map); + if (ret) + printf("%s: regmap failed %d\n", __func__, ret); +@@ -3051,18 +3070,20 @@ static int conv_of_platdata(struct udevice *dev) + #endif + + static const struct sdram_rk3399_ops rk3399_ops = { +-#if !defined(CONFIG_RAM_RK3399_LPDDR4) + .data_training_first = data_training_first, + .set_rate_index = switch_to_phy_index1, + .modify_param = modify_param, + .get_phy_index_params = get_phy_index_params, +-#else ++}; ++ ++#if defined(CONFIG_RAM_RK3399_LPDDR4) ++static const struct sdram_rk3399_ops lpddr4_ops = { + .data_training_first = lpddr4_mr_detect, + .set_rate_index = lpddr4_set_rate, + .modify_param = lpddr4_modify_param, + .get_phy_index_params = lpddr4_get_phy_index_params, +-#endif + }; ++#endif + + static int rk3399_dmc_init(struct udevice *dev) + { +@@ -3081,7 +3102,17 @@ static int rk3399_dmc_init(struct udevice *dev) + return ret; + #endif + +- priv->ops = &rk3399_ops; ++ if (params->base.dramtype == LPDDR4) { ++#if defined(CONFIG_RAM_RK3399_LPDDR4) ++ priv->ops = &lpddr4_ops; ++#else ++ printf("LPDDR4 support is disable\n"); ++ return -EINVAL; ++#endif ++ } else { ++ priv->ops = &rk3399_ops; ++ } ++ + priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); diff --git a/package/boot/uboot-rockchip/patches/202-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/202-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 000000000..74c7c3f4a --- /dev/null +++ b/package/boot/uboot-rockchip/patches/202-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,313 @@ +From 8dc76bbce30c3f63f290f008f8410c00fee13c9a Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Fri, 8 Jan 2021 05:55:50 +0000 +Subject: [PATCH] rockchip: rk3399: Add support for FriendlyARM NanoPi R4S + +This adds support for the NanoPi R4S from FriendlyArm. + +Rockchip RK3399 SoC +1GB DDR3 or 4GB LPDDR4 RAM +Gigabit Ethernet (WAN) +Gigabit Ethernet (PCIe) (LAN) +USB 3.0 Host Port x 2 +MicroSD slot +Reset button +WAN - LAN - SYS LED + +Signed-off-by: Tianling Shen +Co-authored-by: Jensen Huang +Signed-off-by: Jensen Huang +Co-authored-by: Marty Jones +Signed-off-by: Marty Jones +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 9 ++ + arch/arm/dts/rk3399-nanopi-r4s.dts | 178 +++++++++++++++++++++ + board/friendlyarm/nanopi4/MAINTAINERS | 6 + + configs/nanopi-r4s-rk3399_defconfig | 63 ++++++++ + 5 files changed, 257 insertions(+) + create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dts + create mode 100644 configs/nanopi-r4s-rk3399_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -132,6 +132,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ + rk3399-nanopi-m4.dtb \ + rk3399-nanopi-m4-2gb.dtb \ + rk3399-nanopi-neo4.dtb \ ++ rk3399-nanopi-r4s.dtb \ + rk3399-orangepi.dtb \ + rk3399-pinebook-pro.dtb \ + rk3399-puma-haikou.dtb \ +--- /dev/null ++++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi +@@ -0,0 +1,9 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2020 Jensen Huang ++ */ ++ ++#include "rk3399-nanopi4-u-boot.dtsi" ++#include "rk3399-sdram-lpddr4-100.dtsi" ++#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" ++#include "rk3399-sdram-ddr3-1866.dtsi" +--- /dev/null ++++ b/arch/arm/dts/rk3399-nanopi-r4s.dts +@@ -0,0 +1,178 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 Jensen Huang ++ * Copyright (c) 2020 Marty Jones ++ * Copyright (c) 2020 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3399-nanopi4.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R4S"; ++ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; ++ ++ aliases { ++ led-boot = &sys_led; ++ led-failsafe = &sys_led; ++ led-running = &sys_led; ++ led-upgrade = &sys_led; ++ }; ++ ++ /delete-node/ gpio-leds; ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; ++ pinctrl-names = "default"; ++ ++ lan_led: led-0 { ++ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r4s:green:lan"; ++ }; ++ ++ sys_led: led-1 { ++ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r4s:red:sys"; ++ }; ++ ++ wan_led: led-2 { ++ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r4s:green:wan"; ++ }; ++ }; ++ ++ /delete-node/ gpio-keys; ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&reset_button_pin>; ++ ++ reset { ++ debounce-interval = <50>; ++ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ label = "reset"; ++ linux,code = ; ++ }; ++ }; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ /* ++ * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels ++ * work out to 0, ~1200, ~3000, and 5000RPM respectively. ++ */ ++ cooling-levels = <0 12 18 255>; ++ #cooling-cells = <2>; ++ fan-supply = <&vdd_5v>; ++ pwms = <&pwm1 0 50000 0>; ++ }; ++}; ++ ++&cpu_thermal { ++ trips { ++ cpu_warm: cpu_warm { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_hot: cpu_hot { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map2 { ++ trip = <&cpu_warm>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map3 { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ ++&emmc_phy { ++ status = "disabled"; ++}; ++ ++&fusb0 { ++ status = "disabled"; ++}; ++ ++&pcie0 { ++ max-link-speed = <1>; ++ num-lanes = <1>; ++ vpcie3v3-supply = <&vcc3v3_sys>; ++ ++ pcie@0 { ++ reg = <0x00000000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ }; ++}; ++ ++&pinctrl { ++ /delete-node/ gpio-leds; ++ gpio-leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ /delete-node/ rockchip-key; ++ rockchip-key { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&sdhci { ++ status = "disabled"; ++}; ++ ++&sdio0 { ++ status = "disabled"; ++}; ++ ++&sdmmc { ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++}; ++ ++&u2phy0_host { ++ phy-supply = <&vdd_5v>; ++}; ++ ++&u2phy1_host { ++ status = "disabled"; ++}; ++ ++&usbdrd_dwc3_0 { ++ dr_mode = "host"; ++}; ++ ++&vcc3v3_sys { ++ vin-supply = <&vcc5v0_sys>; ++}; +--- a/board/friendlyarm/nanopi4/MAINTAINERS ++++ b/board/friendlyarm/nanopi4/MAINTAINERS +@@ -3,3 +3,9 @@ M: FriendlyElec + S: Maintained + F: board/friendlyarm/nanopi4/ + F: include/configs/nanopi4.h ++ ++NANOPI-R4S ++M: Tianling Shen ++S: Maintained ++F: configs/nanopi-r4s-rk3399_defconfig ++F: arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi +--- /dev/null ++++ b/configs/nanopi-r4s-rk3399_defconfig +@@ -0,0 +1,63 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_NANOPI4_RK3399=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" ++CONFIG_DEBUG_UART=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" ++CONFIG_MISC_INIT_R=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_TPL=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=1 ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM_RK3399_LPDDR4=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_DM_VIDEO=y ++CONFIG_DISPLAY=y ++CONFIG_VIDEO_ROCKCHIP=y ++CONFIG_DISPLAY_ROCKCHIP_HDMI=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c index fa42c1a76..17e1e302a 100644 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c +++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c @@ -4,20 +4,15 @@ * This file was generated by dtoc from a .dtb (device tree binary) file. */ +/* Allow use of U_BOOT_DEVICE() in this file */ +#define DT_PLATDATA_C + #include #include #include -static const struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DEVICE(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .platdata = &dtv_syscon_at_ff100000, - .platdata_size = sizeof(dtv_syscon_at_ff100000), -}; - -static const struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { +/* Node /clock-controller@ff440000 index 0 */ +static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { .reg = {0xff440000, 0x1000}, .rockchip_grf = 0x3a, }; @@ -25,94 +20,11 @@ U_BOOT_DEVICE(clock_controller_at_ff440000) = { .name = "rockchip_rk3328_cru", .platdata = &dtv_clock_controller_at_ff440000, .platdata_size = sizeof(dtv_clock_controller_at_ff440000), + .parent_idx = -1, }; -static const struct dtd_rockchip_rk3328_uart dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {&dtv_clock_controller_at_ff440000, {40}}, - {&dtv_clock_controller_at_ff440000, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DEVICE(serial_at_ff130000) = { - .name = "rockchip_rk3328_uart", - .platdata = &dtv_serial_at_ff130000, - .platdata_size = sizeof(dtv_serial_at_ff130000), -}; - -static const struct dtd_rockchip_rk3328_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_mmc_highspeed = true, - .cap_sd_highspeed = true, - .clocks = { - {&dtv_clock_controller_at_ff440000, {317}}, - {&dtv_clock_controller_at_ff440000, {33}}, - {&dtv_clock_controller_at_ff440000, {74}}, - {&dtv_clock_controller_at_ff440000, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DEVICE(mmc_at_ff500000) = { - .name = "rockchip_rk3328_dw_mshc", - .platdata = &dtv_mmc_at_ff500000, - .platdata_size = sizeof(dtv_mmc_at_ff500000), -}; - -static const struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = { - .ranges = true, - .rockchip_grf = 0x3a, -}; -U_BOOT_DEVICE(pinctrl) = { - .name = "rockchip_rk3328_pinctrl", - .platdata = &dtv_pinctrl, - .platdata_size = sizeof(dtv_pinctrl), -}; - -static const struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = { - .clocks = { - {&dtv_clock_controller_at_ff440000, {200}},}, - .gpio_controller = true, - .interrupt_controller = true, - .interrupts = {0x0, 0x33, 0x4}, - .reg = {0xff210000, 0x100}, -}; -U_BOOT_DEVICE(gpio0_at_ff210000) = { - .name = "rockchip_gpio_bank", - .platdata = &dtv_gpio0_at_ff210000, - .platdata_size = sizeof(dtv_gpio0_at_ff210000), -}; - -static const struct dtd_regulator_fixed dtv_sdmmc_regulator = { - .gpio = {0x60, 0x1e, 0x1}, - .pinctrl_0 = 0x61, - .pinctrl_names = "default", - .regulator_max_microvolt = 0x325aa0, - .regulator_min_microvolt = 0x325aa0, - .regulator_name = "vcc_sd", - .vin_supply = 0x1c, -}; -U_BOOT_DEVICE(sdmmc_regulator) = { - .name = "regulator_fixed", - .platdata = &dtv_sdmmc_regulator, - .platdata_size = sizeof(dtv_sdmmc_regulator), -}; - -static const struct dtd_rockchip_rk3328_dmc dtv_dmc = { +/* Node /dmc index 1 */ +static struct dtd_rockchip_rk3328_dmc dtv_dmc = { .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, 0xff720000, 0x1000, 0xff798000, 0x1000}, .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, @@ -145,5 +57,118 @@ U_BOOT_DEVICE(dmc) = { .name = "rockchip_rk3328_dmc", .platdata = &dtv_dmc, .platdata_size = sizeof(dtv_dmc), + .parent_idx = -1, }; +/* Node /pinctrl/gpio0@ff210000 index 2 */ +static struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = { + .clocks = { + {0, {200}},}, + .gpio_controller = true, + .interrupt_controller = true, + .interrupts = {0x0, 0x33, 0x4}, + .reg = {0xff210000, 0x100}, +}; +U_BOOT_DEVICE(gpio0_at_ff210000) = { + .name = "rockchip_gpio_bank", + .platdata = &dtv_gpio0_at_ff210000, + .platdata_size = sizeof(dtv_gpio0_at_ff210000), + .parent_idx = 4, +}; + +/* Node /mmc@ff500000 index 3 */ +static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { + .bus_width = 0x4, + .cap_sd_highspeed = true, + .clocks = { + {0, {317}}, + {0, {33}}, + {0, {74}}, + {0, {78}},}, + .disable_wp = true, + .fifo_depth = 0x100, + .interrupts = {0x0, 0xc, 0x4}, + .max_frequency = 0x8f0d180, + .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, + .pinctrl_names = "default", + .reg = {0xff500000, 0x4000}, + .sd_uhs_sdr104 = true, + .sd_uhs_sdr12 = true, + .sd_uhs_sdr25 = true, + .sd_uhs_sdr50 = true, + .u_boot_spl_fifo_mode = true, + .vmmc_supply = 0x4b, + .vqmmc_supply = 0x1e, +}; +U_BOOT_DEVICE(mmc_at_ff500000) = { + .name = "rockchip_rk3288_dw_mshc", + .platdata = &dtv_mmc_at_ff500000, + .platdata_size = sizeof(dtv_mmc_at_ff500000), + .parent_idx = -1, +}; + +/* Node /pinctrl index 4 */ +static struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = { + .ranges = true, + .rockchip_grf = 0x3a, +}; +U_BOOT_DEVICE(pinctrl) = { + .name = "rockchip_rk3328_pinctrl", + .platdata = &dtv_pinctrl, + .platdata_size = sizeof(dtv_pinctrl), + .parent_idx = -1, +}; + +/* Node /sdmmc-regulator index 5 */ +static struct dtd_regulator_fixed dtv_sdmmc_regulator = { + .gpio = {0x61, 0x1e, 0x1}, + .pinctrl_0 = 0x67, + .pinctrl_names = "default", + .regulator_boot_on = true, + .regulator_max_microvolt = 0x325aa0, + .regulator_min_microvolt = 0x325aa0, + .regulator_name = "vcc_sd", + .vin_supply = 0x1c, +}; +U_BOOT_DEVICE(sdmmc_regulator) = { + .name = "regulator_fixed", + .platdata = &dtv_sdmmc_regulator, + .platdata_size = sizeof(dtv_sdmmc_regulator), + .parent_idx = -1, +}; + +/* Node /serial@ff130000 index 6 */ +static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { + .clock_frequency = 0x16e3600, + .clocks = { + {0, {40}}, + {0, {212}},}, + .dma_names = {"tx", "rx"}, + .dmas = {0x10, 0x6, 0x10, 0x7}, + .interrupts = {0x0, 0x39, 0x4}, + .pinctrl_0 = 0x26, + .pinctrl_names = "default", + .reg = {0xff130000, 0x100}, + .reg_io_width = 0x4, + .reg_shift = 0x2, +}; +U_BOOT_DEVICE(serial_at_ff130000) = { + .name = "ns16550_serial", + .platdata = &dtv_serial_at_ff130000, + .platdata_size = sizeof(dtv_serial_at_ff130000), + .parent_idx = -1, +}; + +/* Node /syscon@ff100000 index 7 */ +static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { + .reg = {0xff100000, 0x1000}, +}; +U_BOOT_DEVICE(syscon_at_ff100000) = { + .name = "rockchip_rk3328_grf", + .platdata = &dtv_syscon_at_ff100000, + .platdata_size = sizeof(dtv_syscon_at_ff100000), + .parent_idx = -1, +}; + +void dm_populate_phandle_data(void) { +} diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h index 88291627b..847b121a3 100644 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h +++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h @@ -6,10 +6,23 @@ #include #include +struct dtd_ns16550_serial { + fdt32_t clock_frequency; + struct phandle_1_arg clocks[2]; + const char * dma_names[2]; + fdt32_t dmas[4]; + fdt32_t interrupts[3]; + fdt32_t pinctrl_0; + const char * pinctrl_names; + fdt64_t reg[2]; + fdt32_t reg_io_width; + fdt32_t reg_shift; +}; struct dtd_regulator_fixed { fdt32_t gpio[3]; fdt32_t pinctrl_0; const char * pinctrl_names; + bool regulator_boot_on; fdt32_t regulator_max_microvolt; fdt32_t regulator_min_microvolt; const char * regulator_name; @@ -22,17 +35,8 @@ struct dtd_rockchip_gpio_bank { fdt32_t interrupts[3]; fdt64_t reg[2]; }; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_dw_mshc { +struct dtd_rockchip_rk3288_dw_mshc { fdt32_t bus_width; - bool cap_mmc_highspeed; bool cap_sd_highspeed; struct phandle_1_arg clocks[4]; bool disable_wp; @@ -42,10 +46,22 @@ struct dtd_rockchip_rk3328_dw_mshc { fdt32_t pinctrl_0[4]; const char * pinctrl_names; fdt64_t reg[2]; + bool sd_uhs_sdr104; + bool sd_uhs_sdr12; + bool sd_uhs_sdr25; + bool sd_uhs_sdr50; bool u_boot_spl_fifo_mode; fdt32_t vmmc_supply; fdt32_t vqmmc_supply; }; +struct dtd_rockchip_rk3328_cru { + fdt64_t reg[2]; + fdt32_t rockchip_grf; +}; +struct dtd_rockchip_rk3328_dmc { + fdt64_t reg[12]; + fdt32_t rockchip_sdram_params[196]; +}; struct dtd_rockchip_rk3328_grf { fdt64_t reg[2]; }; @@ -53,20 +69,3 @@ struct dtd_rockchip_rk3328_pinctrl { bool ranges; fdt32_t rockchip_grf; }; -struct dtd_rockchip_rk3328_uart { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -#define dtd_syscon dtd_rockchip_rk3328_cru -#define dtd_simple_mfd dtd_rockchip_rk3328_grf -#define dtd_snps_dw_apb_uart dtd_rockchip_rk3328_uart -#define dtd_rockchip_cru dtd_rockchip_rk3328_cru -#define dtd_rockchip_rk3288_dw_mshc dtd_rockchip_rk3328_dw_mshc diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network old mode 100755 new mode 100644 index ab594324c..4849b877e --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -9,8 +9,7 @@ rockchip_setup_interfaces() case "$board" in friendlyarm,nanopi-r2s|\ - friendlyarm,nanopi-r4s-1gb|\ - friendlyarm,nanopi-r4s-4gb) + friendlyarm,nanopi-r4s) ucidef_set_interfaces_lan_wan 'eth1' 'eth0' ;; *) @@ -19,9 +18,9 @@ rockchip_setup_interfaces() esac } -nanopi_generate_mac() +nanopi_r2s_generate_mac() { - local sd_hash=$(sha256sum /sys/devices/platform/*.dwmmc/mmc_host/mmc0/mmc0:*/cid) + local sd_hash=$(sha256sum /sys/devices/platform/ff500000.dwmmc/mmc_host/mmc0/mmc0:*/cid) local mac_base=$(macaddr_canonicalize "$(echo "${sd_hash}" | dd bs=1 count=12 2>/dev/null)") echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${mac_base}")")" } @@ -34,10 +33,12 @@ rockchip_setup_macs() local label_mac="" case "$board" in - friendlyarm,nanopi-r2s|\ - friendlyarm,nanopi-r4s-1gb|\ - friendlyarm,nanopi-r4s-4gb) - wan_mac=$(nanopi_generate_mac) + friendlyarm,nanopi-r2s) + wan_mac=$(nanopi_r2s_generate_mac) + lan_mac=$(macaddr_add "$wan_mac" +1) + ;; + friendlyarm,nanopi-r4s) + wan_mac=$(cat /sys/class/net/eth0/address) lan_mac=$(macaddr_add "$wan_mac" +1) ;; esac diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index 688f23b02..9e4a4cf4f 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -6,7 +6,7 @@ get_device_irq() { local device="$1" local line=$(grep -m 1 "${device}\$" /proc/interrupts) - echo $(echo ${line} | sed 's/:.*//') + echo ${line} | sed 's/:.*//' } set_interface_core() { @@ -26,8 +26,7 @@ friendlyarm,nanopi-r2s) set_interface_core 2 "eth0" set_interface_core 4 "eth1" "xhci-hcd:usb3" ;; -friendlyarm,nanopi-r4s-1gb|\ -friendlyarm,nanopi-r4s-4gb) +friendlyarm,nanopi-r4s) set_interface_core 10 "eth0" set_interface_core 20 "eth1" ;; diff --git a/target/linux/rockchip/armv8/config-5.4 b/target/linux/rockchip/armv8/config-5.4 index e9a972338..74e779ead 100644 --- a/target/linux/rockchip/armv8/config-5.4 +++ b/target/linux/rockchip/armv8/config-5.4 @@ -1,14 +1,24 @@ -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_ARCH_HAS_RELR=y -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_64BIT=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_ARCH_MMAP_RND_BITS_MAX=33 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARC_EMAC_CORE=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y CONFIG_ARM64_CNP=y +CONFIG_ARM64_CONT_SHIFT=4 # CONFIG_ARM64_ERRATUM_1165522 is not set # CONFIG_ARM64_ERRATUM_1286807 is not set # CONFIG_ARM64_ERRATUM_1418040 is not set @@ -23,9 +33,16 @@ CONFIG_ARM64_ERRATUM_858921=y CONFIG_ARM64_HW_AFDBM=y CONFIG_ARM64_LSE_ATOMICS=y CONFIG_ARM64_MODULE_PLTS=y +CONFIG_ARM64_PAGE_SHIFT=12 CONFIG_ARM64_PAN=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PTR_AUTH=y CONFIG_ARM64_RAS_EXTN=y +CONFIG_ARM64_SSBD=y +CONFIG_ARM64_SVE=y # CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_TAGGED_ADDR_ABI=y CONFIG_ARM64_UAO=y CONFIG_ARM64_VA_BITS=48 # CONFIG_ARM64_VA_BITS_39 is not set @@ -33,12 +50,19 @@ CONFIG_ARM64_VA_BITS_48=y CONFIG_ARM64_VHE=y CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y # CONFIG_ARMV8_DEPRECATED is not set +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_GIC=y CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_MHU=y CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_RK3399_DMC_DEVFREQ is not set # CONFIG_ARM_SCMI_PROTOCOL is not set CONFIG_ARM_SCPI_CPUFREQ=y @@ -47,6 +71,7 @@ CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_ARM_SMMU=y CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y CONFIG_ARM_SMMU_V3=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_GPIO=y CONFIG_BACKLIGHT_PWM=y @@ -67,7 +92,9 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y # CONFIG_CAVIUM_TX2_ERRATUM_219 is not set CONFIG_CHARGER_GPIO=y +CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y CONFIG_CMA=y CONFIG_CMA_ALIGNMENT=8 CONFIG_CMA_AREAS=7 @@ -78,6 +105,7 @@ CONFIG_CMA_SIZE_MBYTES=5 CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MIN is not set # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_SCPI=y CONFIG_COMPAT=y @@ -107,6 +135,7 @@ CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_ISOLATION=y CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y CONFIG_CRASH_CORE=y CONFIG_CRASH_DUMP=y @@ -115,70 +144,114 @@ CONFIG_CRC16=y CONFIG_CRC32_SLICEBY8=y CONFIG_CRC_T10DIF=y CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRCT10DIF=y +# CONFIG_CRYPTO_DEV_ROCKCHIP is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEVFREQ_GOV_PASSIVE is not set CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_USERSPACE=y -CONFIG_DEVFREQ_THERMAL=y +# CONFIG_DEVFREQ_THERMAL is not set CONFIG_DEVMEM=y # CONFIG_DEVPORT is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DMADEVICES=y CONFIG_DMA_CMA=y +CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_ENGINE=y CONFIG_DMA_OF=y +CONFIG_DMA_REMAP=y CONFIG_DMA_SHARED_BUFFER=y CONFIG_DNOTIFY=y +CONFIG_DRM_RCAR_WRITEBACK=y +CONFIG_DTC=y CONFIG_DT_IDLE_STATES=y CONFIG_DUMMY_CONSOLE=y CONFIG_DWMAC_DWC_QOS_ETH=y CONFIG_DWMAC_GENERIC=y CONFIG_DWMAC_ROCKCHIP=y +CONFIG_EDAC_SUPPORT=y CONFIG_EMAC_ROCKCHIP=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_ENERGY_MODEL=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXTCON=y +CONFIG_F2FS_FS=y CONFIG_FANOTIFY=y CONFIG_FHANDLE=y CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y # CONFIG_FLATMEM_MANUAL is not set # CONFIG_FORTIFY_SOURCE is not set +CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y CONFIG_FS_POSIX_ACL=y # CONFIG_FUJITSU_ERRATUM_010001 is not set +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GPIOLIB=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_GENERIC=y CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_HANDLE_DOMAIN_IRQ=y # CONFIG_HARDENED_USERCOPY is not set +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_SCHED_AVG_IRQ=y -CONFIG_HAVE_UID16=y CONFIG_HID=y CONFIG_HID_GENERIC=y +CONFIG_HOLES_IN_ZONE=y CONFIG_HOTPLUG_CPU=y CONFIG_HOTPLUG_PCI=y # CONFIG_HOTPLUG_PCI_CPCI is not set @@ -189,15 +262,17 @@ CONFIG_HUGETLB_PAGE=y CONFIG_HWMON=y CONFIG_HWSPINLOCK=y CONFIG_HW_CONSOLE=y -# CONFIG_HZ_PERIODIC is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ROCKCHIP=y +CONFIG_HZ=250 +CONFIG_HZ_250=y CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_COMPAT=y -CONFIG_I2C_GPIO=y CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_RK3X=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_INDIRECT_PIO=y CONFIG_INPUT=y CONFIG_INPUT_EVDEV=y @@ -216,11 +291,15 @@ CONFIG_IOMMU_IO_PGTABLE=y CONFIG_IOMMU_IO_PGTABLE_LPAE=y # CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set CONFIG_IOMMU_SUPPORT=y -# CONFIG_IONIC is not set # CONFIG_IO_STRICT_DEVMEM is not set CONFIG_IO_URING=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_MSI_IOMMU=y CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y CONFIG_JBD2=y CONFIG_JFFS2_ZLIB=y CONFIG_JUMP_LABEL=y @@ -234,29 +313,31 @@ CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y CONFIG_LEDS_SYSCON=y CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=16 CONFIG_LIBCRC32C=y +CONFIG_LIBFDT=y CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_LOG_BUF_SHIFT=19 CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_SERIAL=y CONFIG_MAILBOX=y # CONFIG_MAILBOX_TEST is not set CONFIG_MANDATORY_FILE_LOCKING=y -CONFIG_MDIO_BITBANG=y CONFIG_MDIO_BUS=y CONFIG_MDIO_BUS_MUX=y CONFIG_MDIO_BUS_MUX_GPIO=y CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_GPIO=y +CONFIG_MEMFD_CREATE=y CONFIG_MEMORY_ISOLATION=y CONFIG_MFD_CORE=y CONFIG_MFD_RK808=y CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y CONFIG_MMC=y CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_MINORS=32 @@ -275,6 +356,7 @@ CONFIG_MMC_SDHCI_OF_DWCMSHC=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y # CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_RELA=y CONFIG_MQ_IOSCHED_DEADLINE=y # CONFIG_MTD_CFI is not set CONFIG_MTD_CMDLINE_PARTS=y @@ -282,29 +364,44 @@ CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NLS=y CONFIG_NLS_ISO8859_1=y CONFIG_NOP_USB_XCEIV=y CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=256 CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_NVME_CORE=y # CONFIG_NVME_MULTIPATH is not set # CONFIG_NVME_TCP is not set # CONFIG_OCTEONTX2_AF is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y CONFIG_OF_GPIO=y CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y +CONFIG_OF_NET=y CONFIG_OF_OVERLAY=y CONFIG_OF_RESOLVE=y CONFIG_OLD_SIGSUSPEND3=y # CONFIG_OVERLAY_FS_XINO_AUTO is not set +CONFIG_PADATA=y CONFIG_PAGE_POOL=y # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 # CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_PERCPU=y CONFIG_PCI=y CONFIG_PCIEAER=y CONFIG_PCIEASPM=y @@ -326,6 +423,7 @@ CONFIG_PCI_STUB=y CONFIG_PGTABLE_LEVELS=4 CONFIG_PHYLIB=y CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_PHY_ROCKCHIP_DP=y CONFIG_PHY_ROCKCHIP_EMMC=y # CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set @@ -347,6 +445,8 @@ CONFIG_PM_GENERIC_DOMAINS=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_PM_OPP=y CONFIG_POWER_AVS=y +CONFIG_POWER_RESET=y +CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_HWMON=y CONFIG_PREEMPT=y CONFIG_PREEMPTION=y @@ -356,13 +456,14 @@ CONFIG_PREEMPT_RCU=y CONFIG_PRINTK_TIME=y # CONFIG_PRINT_QUOTA_WARNING is not set CONFIG_PROC_PAGE_MONITOR=y -# CONFIG_PROC_STRIPPED is not set CONFIG_PROC_VMCORE=y CONFIG_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_PWM_SYSFS=y # CONFIG_QFMT_V1 is not set # CONFIG_QFMT_V2 is not set +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y CONFIG_QUOTA=y CONFIG_QUOTACTL=y # CONFIG_QUOTA_NETLINK_INTERFACE is not set @@ -370,12 +471,15 @@ CONFIG_RAID_ATTRS=y CONFIG_RANDOMIZE_BASE=y CONFIG_RANDOMIZE_MODULE_REGION_FULL=y CONFIG_RAS=y +CONFIG_RATIONAL=y # CONFIG_RAVE_SP_CORE is not set CONFIG_RCU_CPU_STALL_TIMEOUT=21 # CONFIG_RCU_EXPERT is not set +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_TRACE=y -# CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_REALTEK_PHY=y +CONFIG_REFCOUNT_FULL=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_IRQ=y @@ -388,6 +492,7 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK808=y CONFIG_RELOCATABLE=y CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y CONFIG_ROCKCHIP_EFUSE=y CONFIG_ROCKCHIP_GRF=y CONFIG_ROCKCHIP_IODOMAIN=y @@ -397,12 +502,15 @@ CONFIG_ROCKCHIP_PHY=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ROCKCHIP_THERMAL=y CONFIG_ROCKCHIP_TIMER=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_RK808=y CONFIG_RTC_I2C_AND_SPI=y CONFIG_RTC_NVMEM=y # CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_SCHED_MC=y CONFIG_SCSI=y # CONFIG_SCSI_LOWLEVEL is not set @@ -417,6 +525,7 @@ CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_EXAR=y CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_RUNTIME_UARTS=4 @@ -433,12 +542,16 @@ CONFIG_SERIO_LIBPS2=y CONFIG_SG_POOL=y CONFIG_SIMPLE_PM_BUS=y CONFIG_SLUB_DEBUG=y +CONFIG_SMP=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y CONFIG_SPI=y CONFIG_SPI_BITBANG=y +CONFIG_SPI_DYNAMIC=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y CONFIG_SPI_ROCKCHIP=y @@ -449,6 +562,7 @@ CONFIG_SQUASHFS_DECOMP_SINGLE=y CONFIG_SQUASHFS_FILE_CACHE=y # CONFIG_SQUASHFS_FILE_DIRECT is not set CONFIG_SRAM=y +CONFIG_SRCU=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y # CONFIG_STAGING is not set @@ -458,11 +572,13 @@ CONFIG_STMMAC_PLATFORM=y CONFIG_STRICT_DEVMEM=y # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_SWAP is not set +CONFIG_SWIOTLB=y CONFIG_SWPHY=y CONFIG_SYNC_FILE=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_SYSFS_SYSCALL=y CONFIG_SYSVIPC_COMPAT=y -CONFIG_TASKS_RCU=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y # CONFIG_TEXTSEARCH is not set CONFIG_THERMAL=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y @@ -472,12 +588,16 @@ CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -# CONFIG_TMPFS_XATTR is not set +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y CONFIG_TRACE_CLOCK=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set CONFIG_TRANSPARENT_HUGE_PAGECACHE=y +CONFIG_TREE_SRCU=y CONFIG_TYPEC=y # CONFIG_TYPEC_DP_ALTMODE is not set CONFIG_TYPEC_FUSB302=y @@ -488,6 +608,7 @@ CONFIG_TYPEC_TCPM=y # CONFIG_UCLAMP_TASK is not set # CONFIG_UEVENT_HELPER is not set CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNMAP_KERNEL_AT_EL0=y CONFIG_USB=y CONFIG_USB_COMMON=y CONFIG_USB_DWC3=y @@ -512,15 +633,18 @@ CONFIG_USB_XHCI_PLATFORM=y # CONFIG_USERIO is not set # CONFIG_VFIO is not set # CONFIG_VIRTIO_MENU is not set +CONFIG_VMAP_STACK=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_VT=y CONFIG_VT_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y # CONFIG_WATCHDOG is not set CONFIG_XARRAY_MULTI=y +CONFIG_XPS=y CONFIG_XXHASH=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_BCJ=y CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/rockchip/config-default b/target/linux/rockchip/config-default index 1b2d5e190..966ecc085 100644 --- a/target/linux/rockchip/config-default +++ b/target/linux/rockchip/config-default @@ -122,8 +122,6 @@ CONFIG_DTC=y CONFIG_EDAC_SUPPORT=y CONFIG_EFI_EARLYCON=y CONFIG_F2FS_FS=y -CONFIG_F2FS_FS_XATTR=y -CONFIG_F2FS_STAT_FS=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_FONT_8x16=y CONFIG_FONT_AUTOSELECT=y diff --git a/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c b/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c index 718762f99..bdc3578d4 100644 --- a/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c +++ b/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c @@ -257,7 +257,7 @@ static int rk_rng_probe(struct platform_device *pdev) rk_rng->rng.cleanup = rk_rng_cleanup, #endif rk_rng->rng.read = rk_rng->soc_data->rk_rng_read; - rk_rng->rng.quality = 999; + rk_rng->rng.quality = 1000; rk_rng->clk_bulks = devm_kzalloc(&pdev->dev, sizeof(*rk_rng->clk_bulks) * diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 8c511ad39..8ae162765 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -1,9 +1,6 @@ -# +# SPDX-License-Identifier: GPL-2.0-only +# # Copyright (C) 2020 Tobias Maedel -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# define Device/friendlyarm_nanopi-r2s DEVICE_VENDOR := FriendlyARM @@ -11,7 +8,7 @@ define Device/friendlyarm_nanopi-r2s SOC := rk3328 UBOOT_DEVICE_NAME := nanopi-r2s-rk3328 IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-img | gzip | append-metadata - DEVICE_PACKAGES := kmod-usb-net kmod-usb-net-rtl8152 + DEVICE_PACKAGES := kmod-usb-net-rtl8152 endef TARGET_DEVICES += friendlyarm_nanopi-r2s @@ -19,23 +16,11 @@ define Device/friendlyarm_nanopi-r4s DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi R4S SOC := rk3399 + UBOOT_DEVICE_NAME := nanopi-r4s-rk3399 IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-img | gzip | append-metadata - DEVICE_PACKAGES := kmod-r8168 + DEVICE_PACKAGES := kmod-r8168 -urngd endef - -define Device/friendlyarm_nanopi-r4s-1gb - $(Device/friendlyarm_nanopi-r4s) - DEVICE_MODEL += 1GB - UBOOT_DEVICE_NAME := nanopi-r4s-1gb-rk3399 -endef -TARGET_DEVICES += friendlyarm_nanopi-r4s-1gb - -define Device/friendlyarm_nanopi-r4s-4gb - $(Device/friendlyarm_nanopi-r4s) - DEVICE_MODEL += 4GB - UBOOT_DEVICE_NAME := nanopi-r4s-4gb-rk3399 -endef -TARGET_DEVICES += friendlyarm_nanopi-r4s-4gb +TARGET_DEVICES += friendlyarm_nanopi-r4s define Device/pine64_rockpro64 DEVICE_VENDOR := Pine64 @@ -43,5 +28,17 @@ define Device/pine64_rockpro64 SOC := rk3399 UBOOT_DEVICE_NAME := rockpro64-rk3399 IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := -urngd endef TARGET_DEVICES += pine64_rockpro64 + +define Device/radxa_rock-pi-4 + DEVICE_VENDOR := Radxa + DEVICE_MODEL := ROCK Pi 4 + SOC := rk3399 + SUPPORTED_DEVICES := radxa,rockpi4 + UBOOT_DEVICE_NAME := rock-pi-4-rk3399 + IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata + DEVICE_PACKAGES:= -urngd +endef +TARGET_DEVICES += radxa_rock-pi-4 diff --git a/target/linux/rockchip/patches-5.4/008-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/rockchip/patches-5.4/002-net-usb-r8152-add-LED-configuration-from-OF.patch similarity index 100% rename from target/linux/rockchip/patches-5.4/008-net-usb-r8152-add-LED-configuration-from-OF.patch rename to target/linux/rockchip/patches-5.4/002-net-usb-r8152-add-LED-configuration-from-OF.patch diff --git a/target/linux/rockchip/patches-5.4/009-dt-bindings-net-add-RTL8152-binding-documentation.patch b/target/linux/rockchip/patches-5.4/003-dt-bindings-net-add-RTL8152-binding-documentation.patch similarity index 100% rename from target/linux/rockchip/patches-5.4/009-dt-bindings-net-add-RTL8152-binding-documentation.patch rename to target/linux/rockchip/patches-5.4/003-dt-bindings-net-add-RTL8152-binding-documentation.patch diff --git a/target/linux/rockchip/patches-5.4/004-arm64-dts-rockchip-Add-txpbl-node-for-RK3399-RK3328.patch b/target/linux/rockchip/patches-5.4/004-arm64-dts-rockchip-Add-txpbl-node-for-RK3399-RK3328.patch index 8a33b4bc1..83ce8f1ef 100644 --- a/target/linux/rockchip/patches-5.4/004-arm64-dts-rockchip-Add-txpbl-node-for-RK3399-RK3328.patch +++ b/target/linux/rockchip/patches-5.4/004-arm64-dts-rockchip-Add-txpbl-node-for-RK3399-RK3328.patch @@ -26,7 +26,7 @@ Signed-off-by: Heiko Stuebner --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -872,6 +872,7 @@ +@@ -857,6 +857,7 @@ resets = <&cru SRST_GMAC2IO_A>; reset-names = "stmmaceth"; rockchip,grf = <&grf>; @@ -34,7 +34,7 @@ Signed-off-by: Heiko Stuebner status = "disabled"; }; -@@ -893,6 +894,7 @@ +@@ -878,6 +879,7 @@ reset-names = "stmmaceth", "mac-phy"; phy-mode = "rmii"; phy-handle = <&phy>; diff --git a/target/linux/rockchip/patches-5.4/006-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch b/target/linux/rockchip/patches-5.4/005-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch similarity index 100% rename from target/linux/rockchip/patches-5.4/006-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch rename to target/linux/rockchip/patches-5.4/005-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch diff --git a/target/linux/rockchip/patches-5.4/007-rockchip-rk3328-fix-NanoPi-R2S-GMAC-clock-name.patch b/target/linux/rockchip/patches-5.4/006-rockchip-rk3328-fix-NanoPi-R2S-GMAC-clock-name.patch similarity index 100% rename from target/linux/rockchip/patches-5.4/007-rockchip-rk3328-fix-NanoPi-R2S-GMAC-clock-name.patch rename to target/linux/rockchip/patches-5.4/006-rockchip-rk3328-fix-NanoPi-R2S-GMAC-clock-name.patch diff --git a/target/linux/rockchip/patches-5.4/005-arm64-dts-rockchip-Add-RK3328-idle-state.patch b/target/linux/rockchip/patches-5.4/007-arm64-dts-rockchip-Add-RK3328-idle-state.patch similarity index 92% rename from target/linux/rockchip/patches-5.4/005-arm64-dts-rockchip-Add-RK3328-idle-state.patch rename to target/linux/rockchip/patches-5.4/007-arm64-dts-rockchip-Add-RK3328-idle-state.patch index a65f04011..874d4ddd4 100644 --- a/target/linux/rockchip/patches-5.4/005-arm64-dts-rockchip-Add-RK3328-idle-state.patch +++ b/target/linux/rockchip/patches-5.4/007-arm64-dts-rockchip-Add-RK3328-idle-state.patch @@ -14,8 +14,6 @@ Signed-off-by: Heiko Stuebner arch/arm64/boot/dts/rockchip/rk3328.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 91306ebed4da2..c9ff1188bd7b1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -41,6 +41,7 @@ @@ -69,6 +67,3 @@ index 91306ebed4da2..c9ff1188bd7b1 100644 l2: l2-cache0 { compatible = "cache"; }; --- -cgit 1.2.3-1.el7 - diff --git a/target/linux/rockchip/patches-5.4/002-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch b/target/linux/rockchip/patches-5.4/008-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch similarity index 83% rename from target/linux/rockchip/patches-5.4/002-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch rename to target/linux/rockchip/patches-5.4/008-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch index 5d0d6b3a3..7ea18e41a 100644 --- a/target/linux/rockchip/patches-5.4/002-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch +++ b/target/linux/rockchip/patches-5.4/008-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch @@ -15,8 +15,6 @@ Link: https://lore.kernel.org/r/20191212061702.BFE2D6E85603@corona.crabdance.com drivers/thermal/rockchip_thermal.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) -diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c -index 9ed8085bb7924..7c1a8bccdcba6 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -58,6 +58,8 @@ enum adc_sort_mode { @@ -28,7 +26,7 @@ index 9ed8085bb7924..7c1a8bccdcba6 100644 /** * The max sensors is two in rockchip SoCs. * Two sensors: CPU and GPU sensor. -@@ -1331,8 +1333,15 @@ static int rockchip_thermal_probe(struct platform_device *pdev) +@@ -1321,8 +1323,15 @@ static int rockchip_thermal_probe(struct thermal->chip->control(thermal->regs, true); @@ -45,7 +43,7 @@ index 9ed8085bb7924..7c1a8bccdcba6 100644 platform_set_drvdata(pdev, thermal); -@@ -1354,6 +1363,7 @@ static int rockchip_thermal_remove(struct platform_device *pdev) +@@ -1344,6 +1353,7 @@ static int rockchip_thermal_remove(struc for (i = 0; i < thermal->chip->chn_num; i++) { struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; @@ -53,6 +51,3 @@ index 9ed8085bb7924..7c1a8bccdcba6 100644 rockchip_thermal_toggle_sensor(sensor, false); } --- -cgit 1.2.3-1.el7 - diff --git a/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch index 7f9af85b1..7b3b50ffd 100644 --- a/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch +++ b/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch @@ -5,7 +5,7 @@ Subject: [PATCH] rockchip: use system LED for OpenWrt Use the SYS LED on the casing for showing system status. -This patch is kept seperate from the NanoPi R2S support patch, as i plan +This patch is kept separate from the NanoPi R2S support patch, as i plan on submitting the device support upstream. Signed-off-by: David Bauer diff --git a/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch b/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch index f6d5f518e..621b25abc 100644 --- a/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch +++ b/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch @@ -26,7 +26,7 @@ use-case. You've been warned. --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -970,6 +970,33 @@ +@@ -955,6 +955,33 @@ status = "disabled"; }; diff --git a/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch index aa8f72e84..37dcb8894 100644 --- a/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch +++ b/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch @@ -32,7 +32,7 @@ Signed-off-by: David Bauer }; &cpu0 { -@@ -318,6 +330,12 @@ +@@ -320,6 +332,12 @@ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; @@ -45,7 +45,7 @@ Signed-off-by: David Bauer }; &pwm2 { -@@ -373,3 +391,12 @@ +@@ -375,3 +393,12 @@ &usb_host0_ohci { status = "okay"; }; diff --git a/target/linux/rockchip/patches-5.4/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.4/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch index 473c26501..e318f3136 100644 --- a/target/linux/rockchip/patches-5.4/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch +++ b/target/linux/rockchip/patches-5.4/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch @@ -14,7 +14,7 @@ Signed-off-by: David Bauer --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -399,4 +399,11 @@ +@@ -401,4 +401,11 @@ &usbdrd_dwc3 { dr_mode = "host"; status = "okay"; diff --git a/target/linux/rockchip/patches-5.4/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch b/target/linux/rockchip/patches-5.4/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch index a6dfff786..1abab5e2e 100644 --- a/target/linux/rockchip/patches-5.4/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch +++ b/target/linux/rockchip/patches-5.4/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch @@ -1,7 +1,7 @@ -From 75b1c522cc33fa9b79077802a49803c874f647b1 Mon Sep 17 00:00:00 2001 -From: Marty Jones -Date: Tue, 15 Dec 2020 12:58:37 -0500 -Subject: [PATCH] rockchip: use USB host by default on rk3399-rock-pi-4 +From e12f67fe83446432ef16704c22ec23bd1dbcd094 Mon Sep 17 00:00:00 2001 +From: Vicente Bergas +Date: Tue, 1 Dec 2020 16:41:32 +0100 +Subject: arm64: dts: rockchip: use USB host by default on rk3399-rock-pi-4 Based on the board schematics at https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf @@ -15,7 +15,6 @@ So, use host mode as it corresponds for a Type-A receptacle. Signed-off-by: Vicente Bergas Link: https://lore.kernel.org/r/20201201154132.1286-4-vicencb@gmail.com Signed-off-by: Heiko Stuebner -Signed-off-by: Marty Jones --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/rockchip/patches-5.4/108-rfc-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-5.4/105-mmc-core-set-initial-signal-voltage-on-power-off.patch similarity index 100% rename from target/linux/rockchip/patches-5.4/108-rfc-mmc-core-set-initial-signal-voltage-on-power-off.patch rename to target/linux/rockchip/patches-5.4/105-mmc-core-set-initial-signal-voltage-on-power-off.patch diff --git a/target/linux/rockchip/patches-5.4/200-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch b/target/linux/rockchip/patches-5.4/200-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch index c487e7438..70bc881c3 100644 --- a/target/linux/rockchip/patches-5.4/200-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch +++ b/target/linux/rockchip/patches-5.4/200-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -1,6 +1,6 @@ -From e46d311ad024821f4c892fead65e5b157fb98a6b Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Sat, 19 Dec 2020 11:57:26 +0000 +From 11c2b38cf0a04b0edb3eabae24fb1484489725e2 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Fri, 8 Jan 2021 07:12:30 +0000 Subject: [PATCH] rockchip: rk3399: Add support for FriendlyARM NanoPi R4S This adds support for the NanoPi R4S from FriendlyArm. @@ -14,109 +14,85 @@ MicroSD slot Reset button WAN - LAN - SYS LED -Signed-off-by: Tianling Shen +Signed-off-by: Tianling Shen +Co-authored-by: Jensen Huang +Signed-off-by: Jensen Huang Co-authored-by: Marty Jones Signed-off-by: Marty Jones --- - arch/arm64/boot/dts/rockchip/Makefile | 2 + - .../dts/rockchip/rk3399-nanopi-r4s-1gb.dts | 27 + - .../dts/rockchip/rk3399-nanopi-r4s-4gb.dts | 27 + - .../boot/dts/rockchip/rk3399-nanopi-r4s.dtsi | 122 ++++++++++++++++++ - 4 files changed, 178 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-1gb.dts - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-4gb.dts - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 178 ++++++++++++++++++ + 2 files changed, 179 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -25,6 +25,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb +@@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-le dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s-1gb.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s-4gb.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb --- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-1gb.dts -@@ -0,0 +1,27 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3399-nanopi-r4s.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPi R4S (1GB)"; -+ compatible = "friendlyarm,nanopi-r4s-1gb", "rockchip,rk3399"; -+}; -+ -+&leds { -+ /delete-node/ status; -+ -+ lan_led: led-0 { -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r4s-1gb:green:lan"; -+ }; -+ -+ sys_led: led-1 { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r4s-1gb:red:sys"; -+ }; -+ -+ wan_led: led-2 { -+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r4s-1gb:green:wan"; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-4gb.dts -@@ -0,0 +1,27 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3399-nanopi-r4s.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPi R4S (4GB)"; -+ compatible = "friendlyarm,nanopi-r4s-4gb", "rockchip,rk3399"; -+}; -+ -+&leds { -+ /delete-node/ status; -+ -+ lan_led: led-0 { -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r4s-4gb:green:lan"; -+ }; -+ -+ sys_led: led-1 { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r4s-4gb:red:sys"; -+ }; -+ -+ wan_led: led-2 { -+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r4s-4gb:green:wan"; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi -@@ -0,0 +1,122 @@ ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +@@ -0,0 +1,178 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* ++ * Copyright (c) 2020 Jensen Huang + * Copyright (c) 2020 Marty Jones -+ * Copyright (c) 2020 Tianling Shen ++ * Copyright (c) 2020 Tianling Shen + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { ++ model = "FriendlyElec NanoPi R4S"; ++ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; ++ + aliases { + led-boot = &sys_led; + led-failsafe = &sys_led; + led-running = &sys_led; + led-upgrade = &sys_led; -+ ethernet1 = &r8169; ++ }; ++ ++ /delete-node/ gpio-leds; ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; ++ pinctrl-names = "default"; ++ ++ lan_led: led-0 { ++ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r4s:green:lan"; ++ }; ++ ++ sys_led: led-1 { ++ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r4s:red:sys"; ++ }; ++ ++ wan_led: led-2 { ++ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r4s:green:wan"; ++ }; ++ }; ++ ++ /delete-node/ gpio-keys; ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&reset_button_pin>; ++ ++ reset { ++ debounce-interval = <50>; ++ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ label = "reset"; ++ linux,code = ; ++ }; + }; + + vdd_5v: vdd-5v { @@ -128,7 +104,10 @@ Signed-off-by: Marty Jones + + fan: pwm-fan { + compatible = "pwm-fan"; -+ /* FIXME: adjust leveles for the connected fan */ ++ /* ++ * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels ++ * work out to 0, ~1200, ~3000, and 5000RPM respectively. ++ */ + cooling-levels = <0 12 18 255>; + #cooling-cells = <2>; + fan-supply = <&vdd_5v>; @@ -172,13 +151,6 @@ Signed-off-by: Marty Jones + status = "disabled"; +}; + -+&leds_gpio { -+ rockchip,pins = -+ <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, -+ <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, -+ <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+}; -+ +&pcie0 { + max-link-speed = <1>; + num-lanes = <1>; @@ -188,10 +160,29 @@ Signed-off-by: Marty Jones + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ }; ++}; + -+ r8169: pcie@0,0 { -+ reg = <0x000000 0 0 0 0>; -+ local-mac-address = [ 00 00 00 00 00 00 ]; ++&pinctrl { ++ /delete-node/ gpio-leds; ++ gpio-leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ /delete-node/ rockchip-key; ++ rockchip-key { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; @@ -205,7 +196,9 @@ Signed-off-by: Marty Jones +}; + +&sdmmc { -+ host-index-min = <1>; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; +}; + +&u2phy0_host { @@ -223,4 +216,3 @@ Signed-off-by: Marty Jones +&vcc3v3_sys { + vin-supply = <&vcc5v0_sys>; +}; - diff --git a/target/linux/rockchip/patches-5.4/104-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch b/target/linux/rockchip/patches-5.4/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch similarity index 96% rename from target/linux/rockchip/patches-5.4/104-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch rename to target/linux/rockchip/patches-5.4/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch index 30dbcc17a..28798047f 100644 --- a/target/linux/rockchip/patches-5.4/104-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch +++ b/target/linux/rockchip/patches-5.4/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch @@ -9,7 +9,7 @@ Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -163,6 +163,10 @@ +@@ -165,6 +165,10 @@ }; }; diff --git a/target/linux/rockchip/patches-5.4/105-char-add-support-for-rockchip-hardware-random-number.patch b/target/linux/rockchip/patches-5.4/801-char-add-support-for-rockchip-hardware-random-number.patch similarity index 100% rename from target/linux/rockchip/patches-5.4/105-char-add-support-for-rockchip-hardware-random-number.patch rename to target/linux/rockchip/patches-5.4/801-char-add-support-for-rockchip-hardware-random-number.patch diff --git a/target/linux/rockchip/patches-5.4/106-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-5.4/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch similarity index 97% rename from target/linux/rockchip/patches-5.4/106-arm64-dts-rockchip-add-hardware-random-number-genera.patch rename to target/linux/rockchip/patches-5.4/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch index 75e283ab3..970e798f5 100644 --- a/target/linux/rockchip/patches-5.4/106-arm64-dts-rockchip-add-hardware-random-number-genera.patch +++ b/target/linux/rockchip/patches-5.4/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch @@ -11,7 +11,7 @@ Signed-off-by: wevsty --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -279,6 +279,17 @@ +@@ -264,6 +264,17 @@ status = "disabled"; }; @@ -31,7 +31,7 @@ Signed-off-by: wevsty reg = <0x0 0xff100000 0x0 0x1000>; --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1879,6 +1879,16 @@ +@@ -1882,6 +1882,16 @@ }; }; diff --git a/target/linux/rockchip/patches-5.4/003-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch b/target/linux/rockchip/patches-5.4/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch similarity index 100% rename from target/linux/rockchip/patches-5.4/003-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch rename to target/linux/rockchip/patches-5.4/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch