Mux the MT7530 switch's phy0/4 to the SoC's gmac1 on devices where RGMII2
pins are available. This achieves 2 Gbps total bandwidth to the CPU using
the second RGMII.
The ports called "wan" are muxed where possible. On a minority of devices,
this is not possible. Those cases:
mt7621_ampedwireless_ally-r1900k.dts: lan3
mt7621_ubnt_edgerouter-x.dts: eth0
mt7621_gnubee_gb-pc1.dts: ethblue
mt7621_linksys_re6500.dts: lan1
mt7621_netgear_wac104.dts: lan4
mt7621_tplink_eap235-wall-v1.dts: lan0
mt7621_tplink_eap615-wall-v1.dts: lan0
mt7621_ubnt_usw-flex.dts: lan1
The "wan" port is just what the vendor designated on the board/plastic
chasis of the device. On a technical level, there is no difference between
a lan and wan port on MT7621AT, MT7621DAT and MT7621ST SoCs. Prefer
connecting to WAN via the port described above for these devices to benefit
the feature brought with this patch.
mt7621_d-team_newifi-d2.dts cannot benefit this feature, although it looks
like it should, because the rgmii2 pins are wired to unused components.
Tested on a range of devices documented on the GitHub PR.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
These devices do not use rgmii2 as gpio, therefore remove rgmii2 pin group
from state-default. Remove overwriting the ethernet node for these devices.
Move claiming the rgmii2 group from mt7621_zyxel_nwa-ax.dtsi to
mt7621_zyxel_nwa50ax.dts as it's only the latter using rgmii2 pins as gpio.
Remove duplicate ethernet overwrite from mt7621_tplink_archer-x6-v3.dtsi.
Claim rgmii2 group as gpio on mt7621_bolt_arion.dts as it uses an rgmii2
pin, 26, as gpio.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Change switch port labels to ethblack & ethblue.
Change lan1 & lan2 LEDs to ethblack_act & ethblue_act and fix GPIO pins.
Add the external phy with ethyellow label on the GB-PC2 devicetree.
Do not claim rgmii2 as gpio, it's used for ethernet with rgmii2 function.
Enable ICPlus PHY driver for IP1001 which GB-PC2 has got.
Update interface name and change netdev function.
Enable lzma compression to make up for the increased size of the kernel.
Make spi flash bindings on par with mainline Linux to fix read errors.
Tested on GB-PC2 by Petr.
Tested-by: Petr Louda <petr.louda@outlook.cz>
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
MAC address retrieval was switched to more generic upstream (5.13) NVMEM
based solution in commit 06bb4a5018cd ("ramips: convert mtd-mac-address
to nvmem implementation") , but NVMEM subsystem wasn't enabled in the
kernel, so fix it now.
Fixes: 06bb4a5018cd ("ramips: convert mtd-mac-address to nvmem implementation")
Signed-off-by: David Bauer <mail@david-bauer.net>
Signed-off-by: Petr Štetiar <ynezz@true.cz> [commit message]
All patches automatically rebased.
Signed-off-by: John Audia <therealgraysky@proton.me>
Signed-off-by: John Audia <therealgraysky@proton.me>
Co-authored-by: John Audia <therealgraysky@proton.me>
According to MediaTek MT7688 Datasheet v1.4, as well as the MT7628
counterpart, the memory controller reset bit (MC_RST) is 10, not 20.
Reset bit 20 is used for for UART 2 (UART2_RST).
Please note: Due to the lack of hardware, I was not able to test this
change.
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
set_port_link is required by swconfig to setup link mode.
Here we implemented set_port_link by touching MII PHY registers.
For autoneg enabled case, we set advertise registers to let
autoneg reach the target mode and then retrigger autoneg. For
non autoneg case, we set BMCR register to force PHY enter
desired mode.
This patch have been tested on both MT7620 and MT7621.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
For a TX->TX connected external phy to transmit/receive data, the rgmii2
pin group needs to be claimed with gpio function, at least for EdgeRouter X
SFP. We already claim the pin group under the pinctrl node with gpio
function on the gpio node on mt7621_ubnt_edgerouter-x.dtsi.
However, we should claim a pin group under its consumer node. It's the
ethernet node in this case, which we already claim the rgmii2 pin group
under it on mt7621.dtsi. Therefore, set the function as gpio on the rgmii2
node for EdgeRouter X SFP and get rid of claiming the rgmii2 pin group
under the pinctrl node. With this change, we also get to remove a
definition from mt7621_ubnt_edgerouter-x.dtsi which is specific to
EdgeRouter X SFP.
This change is tested on an EdgeRouter X SFP.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Some K2P comes with the worse boards with GD25Q128 (may be A2), which
only works with 50MHz frequency and less. Reduce spi frequency so that
these routers can boot.
remove m25p,fast-read because it isn't needed for 50MHz SPI.
Signed-off-by: Aviana Cruz <gwencroft@proton.me>
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Add the missing pinctrl properties on the ethernet node.
GMAC1 will start working with this change.
Link: https://lore.kernel.org/netdev/83a35aa3-6cb8-2bc4-2ff4-64278bbcd8c8@arinc9.com/
Overwrite pinctrl-0 property without rgmii2_pins on devicetrees which use
the rgmii2 pins as GPIO (22 - 33).
Give gpio function to rgmii2 pin group on mt7621_tplink_archer-x6-v3.dtsi
which uses GPIO 28.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
[Rebase to current source code]
Signed-off-by: AmadeusGhost <amadeus@openjmu.xyz>
Flow control needs to be enabled on both sides to work.
It is already enabled on gmac0, enable it on port@6 too.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Tested-by: Sungbo Eo <mans0n@gorani.run>
Remove reg property from ports node to fix this warning:
Warning (unit_address_vs_reg): /ethernet@1e100000/mdio-bus/switch@1f/ports: node has a reg or ranges property, but no unit name
Another warning surfaces afterwards. Remove #address-cells and #size-cells
from switch@1f node to fix this warning:
Warning (avoid_unnecessary_addr_size): /ethernet@1e100000/mdio-bus/switch@1f: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
