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Compared to MT7988 (NETSYSv3) the Ethernet Frame Engine of MT7987 has been slighly updated (NETSYSv3.1), among other things the packet scheduler (shaper) has apparently been reworked. Import patches for basic support of the Ethernet Frame Engine of the MT7987 SoC. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
90 lines
3.1 KiB
Diff
90 lines
3.1 KiB
Diff
From be193994deca7cc3ca6ddedc6efd06182b032f21 Mon Sep 17 00:00:00 2001
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From: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
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Date: Tue, 6 May 2025 12:53:37 +0800
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Subject: [PATCH] net: pcs: mtk-lynxi: add phya tx rx clock path
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In NETSYSv3.1, the SGMII hardware introduces a new clock path from PHYA.
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Consequently, users can switch the SGMII PCS to this new clock source
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for better performance on the MT7987.
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Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
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---
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--- a/drivers/net/pcs/pcs-mtk-lynxi.c
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+++ b/drivers/net/pcs/pcs-mtk-lynxi.c
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@@ -25,6 +25,7 @@
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#define SGMSYS_PCS_CONTROL_1 0x0
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#define SGMII_BMCR GENMASK(15, 0)
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#define SGMII_BMSR GENMASK(31, 16)
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+#define SGMII_REF_CK_SEL BIT(24)
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#define SGMSYS_PCS_DEVICE_ID 0x4
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#define SGMII_LYNXI_DEV_ID 0x4d544950
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@@ -52,6 +53,8 @@
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#define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2)
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#define SGMII_DUPLEX_HALF BIT(4)
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#define SGMII_REMOTE_FAULT_DIS BIT(8)
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+#define SGMII_TRXBUF_THR_MASK GENMASK(31, 16)
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+#define SGMII_TRXBUF_THR(x) FIELD_PREP(SGMII_TRXBUF_THR_MASK, (x))
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/* Register to reset SGMII design */
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#define SGMSYS_RESERVED_0 0x34
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@@ -166,7 +169,7 @@ static int mtk_pcs_lynxi_config(struct p
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{
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struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
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bool mode_changed = false, changed;
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- unsigned int rgc3, sgm_mode, bmcr = 0;
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+ unsigned int rgc3, sgm_mode, bmcr = 0, trxbuf_thr = 0x3112;
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int advertise, link_timer;
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advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
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@@ -193,6 +196,12 @@ static int mtk_pcs_lynxi_config(struct p
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bmcr = BMCR_ANENABLE;
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}
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+ /* Configure SGMII PCS clock source */
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+ if (mpcs->flags & MTK_SGMII_FLAG_PHYA_TRX_CK) {
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+ bmcr |= SGMII_REF_CK_SEL;
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+ trxbuf_thr = 0x2111;
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+ }
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+
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if (mpcs->interface != interface) {
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link_timer = phylink_get_link_timer_ns(interface);
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if (link_timer < 0)
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@@ -235,12 +244,14 @@ static int mtk_pcs_lynxi_config(struct p
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/* Update the sgmsys mode register */
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regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
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+ SGMII_TRXBUF_THR_MASK |
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SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN |
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- SGMII_IF_MODE_SGMII, sgm_mode);
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+ SGMII_IF_MODE_SGMII,
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+ SGMII_TRXBUF_THR(trxbuf_thr) | sgm_mode);
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/* Update the BMCR */
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regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
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- BMCR_ANENABLE, bmcr);
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+ SGMII_REF_CK_SEL | BMCR_ANENABLE, bmcr);
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/* Release PHYA power down state
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* Only removing bit SGMII_PHYA_PWD isn't enough.
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@@ -413,6 +424,9 @@ static int mtk_pcs_lynxi_probe(struct pl
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if (of_property_read_bool(np->parent, "mediatek,pnswap"))
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flags |= MTK_SGMII_FLAG_PN_SWAP;
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+ if (of_property_read_bool(np->parent, "mediatek,phya_trx_ck"))
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+ flags |= MTK_SGMII_FLAG_PHYA_TRX_CK;
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+
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if (of_parse_phandle(np->parent, "resets", 0)) {
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mpcs->rstc = of_reset_control_get_shared(np->parent, NULL);
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if (IS_ERR(mpcs->rstc))
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--- a/include/linux/pcs/pcs-mtk-lynxi.h
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+++ b/include/linux/pcs/pcs-mtk-lynxi.h
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@@ -6,6 +6,7 @@
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#include <linux/regmap.h>
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#define MTK_SGMII_FLAG_PN_SWAP BIT(0)
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+#define MTK_SGMII_FLAG_PHYA_TRX_CK BIT(2)
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struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
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struct regmap *regmap,
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u32 ana_rgc3, u32 flags);
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