From 959e15c8fbc0595fdfd3e62ab10f91d1952ddf14 Mon Sep 17 00:00:00 2001 From: Sean Khan Date: Thu, 31 Jul 2025 18:16:30 -0400 Subject: [PATCH] workflow: auto close non-english issues --- .github/ISSUE_TEMPLATE/bug-report.yml | 74 + .github/ISSUE_TEMPLATE/config.yml | 2 + .../auto-close-non-english-issues.yml | 94 + LICENSE | 339 + README.md | 10 + firmware/aq-fw-download/Makefile | 26 + firmware/aq-fw-download/src/Makefile | 14 + firmware/aq-fw-download/src/include/AQ_API.h | 246 + .../src/include/AQ_PhyInterface.h | 171 + .../src/include/AQ_PlatformRoutines.h | 71 + .../aq-fw-download/src/include/AQ_RegMacro.h | 323 + .../src/include/AQ_ReturnCodes.h | 113 + firmware/aq-fw-download/src/include/AQ_User.h | 97 + .../APPIA/AQ_APPIA_Global_registers.h | 5581 +++++++ .../APPIA/AQ_APPIA_Global_registers_Defines.h | 2134 +++ .../AQ_APPIA_Global_registers_reversed.h | 5581 +++++++ .../include/registerMap/AQ_RegGroupMaxSizes.h | 387 + .../src/include/registerMap/AQ_RegMaps.h | 69 + .../registerMap/HHD/AQ_HHD_Global_registers.h | 12123 ++++++++++++++++ .../HHD/AQ_HHD_Global_registers_Defines.h | 4413 ++++++ .../HHD/AQ_HHD_Global_registers_reversed.h | 12123 ++++++++++++++++ firmware/aq-fw-download/src/mdioBootLoadCLD.c | 193 + firmware/aq-fw-download/src/src/AQ_API.c | 1021 ++ .../aq-fw-download/src/src/AQ_PhyInterface.c | 141 + firmware/nss-eip-firmware/Makefile | 34 + firmware/nss-eip-firmware/src/.gitkeep | 0 firmware/nss-eip-firmware/src/ifpp.bin | Bin 0 -> 12272 bytes firmware/nss-eip-firmware/src/ipue.bin | Bin 0 -> 6116 bytes firmware/nss-eip-firmware/src/ofpp.bin | Bin 0 -> 6128 bytes firmware/nss-eip-firmware/src/opue.bin | Bin 0 -> 4068 bytes firmware/nss-firmware/Makefile | 169 + nss-ifb/Makefile | 48 + nss-ifb/README.md | 45 + nss-ifb/src/Makefile | 3 + nss-ifb/src/nss_ifb.c | 304 + nss-userspace-oss/Makefile | 112 + nss-userspace-oss/libnl-nss/Makefile | 46 + nss-userspace-oss/libnl-nss/src/Makefile | 35 + .../libnl-nss/src/include/nss_nlbase.h | 71 + .../libnl-nss/src/include/nss_nldtls_api.h | 119 + .../libnl-nss/src/include/nss_nlipv4_api.h | 253 + .../libnl-nss/src/include/nss_nlipv6_api.h | 253 + .../libnl-nss/src/include/nss_nlist_api.h | 220 + .../libnl-nss/src/include/nss_nlmcast_api.h | 102 + .../libnl-nss/src/include/nss_nlsock_api.h | 197 + .../libnl-nss/src/nss_nldtls_api.c | 138 + .../libnl-nss/src/nss_nlipv4_api.c | 176 + .../libnl-nss/src/nss_nlipv6_api.c | 176 + .../libnl-nss/src/nss_nlmcast_api.c | 146 + nss-userspace-oss/libnl-nss/src/nss_nlsock.c | 498 + .../nssinfo/patches/001-fix-warnings.patch | 35 + .../patches/000-create-makefile.patch | 32 + ...evert-Add-timestamp-support-to-udpst.patch | 24 + .../patches/001-nssinfo-fix-warnings.patch | 29 + .../002-libnl-modularize-makefile.patch | 48 + .../patches/002-nss-switch-to-nl-tiny.patch | 40 + .../patches/0030-fix-build.patch | 303 + qca-mcs/Makefile | 68 + qca-mcs/patches/0001-kernel-5.10-compat.patch | 18 + qca-mcs/patches/0002-kernel-6.6.29.patch | 14 + .../0003-fix-header-guard-gcc-15.patch | 11 + qca-mcs/patches/0004-kernel-6.12.patch | 120 + qca-nss-cfi/Makefile | 100 + ...ead-add-downstream-crypto_tfm_alg_fl.patch | 28 + .../0007-cryptoapi-v2.0-fix-crash.patch | 26 + ...9-cryptoapi-v2.0-support-kernel-6.12.patch | 134 + qca-nss-clients/Config.in | 55 + qca-nss-clients/Makefile | 895 ++ qca-nss-clients/files/qca-nss-ipsec | 231 + qca-nss-clients/files/qca-nss-mirred.init | 28 + qca-nss-clients/files/qca-nss-netlink.init | 31 + qca-nss-clients/files/qca-nss-ovpn.init | 104 + .../0001-kernel-5.15-support-qdisc.patch | 153 + .../0002-kernel-5.4-support-gre.patch | 31 + .../0003-kernel-5.4-support-ipsec.patch | 29 + .../0004-kernel-5.4-support-dtls.patch | 11 + .../0005-vlanmgr-fix-compile-error.patch | 59 + .../0006-match-fix-compile-error.patch | 25 + .../0007-bridge-fix-compile-error.patch | 29 + .../0008-profiler-fix-compile-error.patch | 61 + .../0009-gre-fix-compile-error.patch | 17 + .../patches-11.4/0010-fix-portifmgr.patch | 35 + ...lsmgr-fix-SHA-header-include-in-5.15.patch | 48 + ...0012-dtlsmgr-fix-debug-print-in-5.15.patch | 36 + ...lsmgr-fix-SHA-header-include-in-5.15.patch | 32 + ...pnmgr-fix-SHA-header-include-in-5.15.patch | 32 + ...5-tunipip6-fix-compile-error-in-5.15.patch | 11 + .../0017-tlsmgr-fix-debug-print-in-5.15.patch | 34 + .../0018-kernel-6.1-support.patch | 300 + ...shmgr-fix-uninitialized-and-implicit.patch | 225 + .../0020-capwapmgr-fix-compile-error.patch | 169 + .../0022-netlink-modularize-makefile.patch | 447 + .../0023-mirror-fix-makefile.patch | 10 + .../patches-11.4/0024-switch-to-wifili.patch | 93 + ...5-nss-clients-add-kernel-6.6-support.patch | 274 + .../0026-qdisc-backport-12.4.patch | 330 + .../0027-bridge-backport-12.5.patch | 303 + .../0027-capwapmgr-backport-12.5.patch | 51 + .../0027-map-t-backport-12.5.patch | 169 + .../0027-match-backport-12.5.patch | 92 + .../0027-pptp-backport-12.5.patch | 31 + .../0027-vlan-backport-12.5.patch | 525 + .../0028-dtlsmgr-use-eth_hw_addr_set.patch | 13 + .../0029-dtlsmgr-properly-update-stats.patch | 13 + .../0030-fixup-compiler-errors.patch | 464 + .../0031-kernel-6.12-support.patch | 875 ++ .../0032-match-fix-procfs-read-write.patch | 406 + .../0033-qdisc-backport-12.5.patch | 377 + .../0034-ipsecmgr-backport-12.5.patch | 540 + .../0035-netlink-backport-12.5.patch | 1441 ++ .../0036-vxlanmgr-backport-12.5.patch | 357 + .../0037-netlink-reorganize-log-level.patch | 1102 ++ .../0001-kernel-5.15-support-qdisc.patch | 153 + .../patches/0002-kernel-5.4-support-gre.patch | 31 + .../0003-kernel-5.4-support-ipsec.patch | 29 + .../0004-kernel-5.4-support-dtls.patch | 11 + .../0005-vlanmgr-fix-compile-error.patch | 59 + .../0006-match-fix-compile-error.patch | 25 + .../0007-bridge-fix-compile-error.patch | 29 + .../0008-profiler-fix-compile-error.patch | 61 + .../patches/0010-fix-portifmgr.patch | 35 + ...lsmgr-fix-SHA-header-include-in-5.15.patch | 48 + ...0012-dtlsmgr-fix-debug-print-in-5.15.patch | 36 + ...lsmgr-fix-SHA-header-include-in-5.15.patch | 32 + ...pnmgr-fix-SHA-header-include-in-5.15.patch | 32 + ...5-tunipip6-fix-compile-error-in-5.15.patch | 11 + ...6-vxlanmgr-fix-compile-error-in-5.15.patch | 11 + .../0017-tlsmgr-fix-debug-print-in-5.15.patch | 34 + .../patches/0018-kernel-6.1-support.patch | 277 + ...shmgr-fix-uninitialized-and-implicit.patch | 238 + .../0020-capwapmgr-fix-compile-error.patch | 169 + .../0022-netlink-modularize-makefile.patch | 539 + .../patches/0024-switch-to-wifili.patch | 93 + ...5-nss-clients-add-kernel-6.6-support.patch | 274 + .../0028-dtlsmgr-use-eth_hw_addr_set.patch | 13 + .../0029-dtlsmgr-properly-update-stats.patch | 13 + .../patches/0030-fixup-compiler-errors.patch | 473 + .../patches/0031-kernel-6.12-support.patch | 875 ++ .../0032-match-fix-procfs-read-write.patch | 406 + .../0033-ipsecmgr-fix-compile-error.patch | 334 + qca-nss-crypto/Makefile | 90 + ...replace-ioremap_nocache-with-ioremap.patch | 94 + .../0004-nss-crypto-support-kernel-6.12.patch | 429 + qca-nss-drv/Config.in | 271 + qca-nss-drv/Makefile | 364 + qca-nss-drv/files/qca-nss-drv.debug | 89 + qca-nss-drv/files/qca-nss-drv.hotplug | 70 + qca-nss-drv/files/qca-nss-drv.init | 143 + qca-nss-drv/files/qca-nss-drv.uci | 3 + qca-nss-drv/files/skb_recycler.init | 92 + qca-nss-drv/files/skb_recycler.uci | 6 + ...replace-ioremap_nocache-with-ioremap.patch | 178 + ...ol-fab-scaling-from-package-Makefile.patch | 31 + .../0005-fix-NULL-pointer-exception.patch | 11 + ...6-Fix-Kernel-Panic-dma-with-NULL-dev.patch | 30 + ...ts-enum-int-compilation-error-GCC-13.patch | 11 + .../0007-Exported-set-nexthop-function.patch | 23 + ...s_wifili_if-compilation-error-GCC-13.patch | 11 + .../0009-kernel-5.15-support.patch | 85 + .../0010-nss-drv-dynamic-interface-desc.patch | 18 + ...ork-getting-the-reserved-memory-size.patch | 114 + .../0012-Makefile-modularize-driver.patch | 188 + .../0012-nss-drv-quiet-messages.patch | 103 + .../0013-backport-12.4-docs.patch | 983 ++ .../patches-11.4/0013-backport-12.4.patch | 1209 ++ .../0013-nss-drv-remove-legacy-wifi.patch | 12 + .../0014-Add-kernel-6.1-support.patch | 183 + ...014-nss-drv-avoid-recreating-virt_if.patch | 14 + .../patches-11.4/0015-nss-drv-fix-igs.patch | 40 + ...6-nss-drv-add-support-for-kernel-6.6.patch | 824 ++ ...-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch | 558 + .../0017-nss-drv-remove-gmac-stat.patch | 39 + ...-nss-drv-wifili-add-exported-symbols.patch | 18 + ...0018-nss-drv-more-uniform-kernel-msg.patch | 88 + ...-mac80211-disable-signal-redirection.patch | 11 + .../0019-nss-drv-reorg-irq-logic.patch | 353 + .../0022-nss-drv-display-fw-version.patch | 78 + .../0022-nss-drv-set-addr-to-const.patch | 88 + .../patches-11.4/0023-add-boot-delay.patch | 60 + ...nss-drv-add-missing-wifili-err-codes.patch | 76 + .../0024-fix-mesh-stats-naming.patch | 39 + .../0025-fix-missing-macro-gre_tunnel.patch | 14 + .../0025-nss_rps-fix-procfs-read-write.patch | 205 + ...-nss-drv-add-support-for-kernel-6.12.patch | 800 + .../0026-treewide-fix-compiler-warnings.patch | 102 + ...Makefile-set-rearrange-arch-features.patch | 75 + .../0027-nss-drv-fix-null-ptr-log.patch | 46 + ...12.5-fix-greredir-stats-partial-copy.patch | 170 + .../0028-nss_ppe_vp-fix-create-destroy.patch | 57 + ...5-baseline-stats-write-functionality.patch | 1677 +++ .../0030-backport-11.5-pn_mq_en.patch | 241 + .../0030-backport-12.5-ipq50xx-fixes.patch | 161 + ...replace-ioremap_nocache-with-ioremap.patch | 153 + ...-nss-drv-add-support-for-kernel-5.15.patch | 49 + ...0003-DMA-Fix-NULL-pointer-exceptions.patch | 28 + ...-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch | 564 + ...ork-getting-the-reserved-memory-size.patch | 114 + ...ts-enum-int-compilation-error-GCC-13.patch | 11 + ...s_wifili_if-compilation-error-GCC-13.patch | 11 + .../patches/0008-Add-kernel-6.1-support.patch | 183 + .../0010-nss-drv-dynamic-interface-desc.patch | 18 + .../0011-nss-drv-move-only-for-ipq806x.patch | 57 + .../patches/0012-nss-drv-quiet-messages.patch | 37 + .../0013-nss-drv-remove-legacy-wifi.patch | 33 + ...014-nss-drv-avoid-recreating-virt_if.patch | 14 + .../patches/0015-nss-drv-fix-igs.patch | 40 + ...6-nss-drv-add-support-for-kernel-6.6.patch | 251 + ...-nss-drv-wifili-add-exported-symbols.patch | 18 + ...0018-nss-drv-more-uniform-kernel-msg.patch | 88 + ...-mac80211-disable-signal-redirection.patch | 11 + .../0019-nss-drv-reorg-irq-logic.patch | 353 + .../0020-nss-drv-display-fw-version.patch | 79 + .../patches/0022-nss-drv-limit-fw-12.2.patch | 201 + .../0022-nss-drv-set-addr-to-const.patch | 88 + qca-nss-drv/patches/0023-add-boot-delay.patch | 60 + .../patches/0024-fix-mesh-stats-naming.patch | 39 + .../0025-nss_rps-fix-procfs-read-write.patch | 195 + ...-nss-drv-add-support-for-kernel-6.12.patch | 808 + .../0026-nss_gre-fix-missing-macro.patch | 14 + .../0026-treewide-fix-compiler-warnings.patch | 102 + ...Makefile-set-rearrange-arch-features.patch | 75 + .../0027-nss-drv-fix-null-ptr-log.patch | 46 + .../0028-nss_ppe_vp-fix-create-destroy.patch | 57 + qca-nss-ecm/Makefile | 196 + qca-nss-ecm/files/disable_offloads.hotplug | 17 + qca-nss-ecm/files/disable_offloads.sh | 227 + qca-nss-ecm/files/ecm_dump.sh | 95 + qca-nss-ecm/files/on-demand-down | 6 + qca-nss-ecm/files/qca-nss-ecm.defaults | 25 + qca-nss-ecm/files/qca-nss-ecm.firewall | 34 + qca-nss-ecm/files/qca-nss-ecm.init | 220 + qca-nss-ecm/files/qca-nss-ecm.sysctl | 3 + qca-nss-ecm/files/qca-nss-ecm.uci | 9 + ...de-componentize-the-module-even-more.patch | 330 + ...olve-the-cpu-high-load-regarding-ecm.patch | 55 + ...ide-rework-notifier-changes-for-5.15.patch | 87 + ...tagram-drop-static-for-EXPORT_SYMBOL.patch | 50 + ...dp_get_timeouts-and-use-standard-ups.patch | 63 + ...-ppp-generic-function-calls-for-5.15.patch | 20 + .../0011-ecm_classifier-move-defs.patch | 22 + .../0012-ecm_add-check-for-pppoe.patch | 42 + ...reewide-export-ipv4-and-ipv6-symbols.patch | 99 + .../0015-ecm-add-support-for-kernel-6.6.patch | 14 + ...6-ecm-conditionally-check-mlo-device.patch | 14 + ...ecm-interface-fix-fortify_memcpy_chk.patch | 53 + .../patches/0018-ecm-compat-nss-12_5.patch | 34 + .../0020-remove-check-mlo-device.patch | 14 + ...-fix-read-write-tcp-udp-denied-ports.patch | 79 + .../0022-fix-undefined-dev-for-tunipip6.patch | 11 + ...0023-nss-ecm-add-kernel-6.12-support.patch | 482 + ...4-ecm-add-wildcard-opt-to-del-denied.patch | 145 + qca-nss-macsec/Makefile | 85 + .../0001-change-warning-to-debug.patch | 19 + qca-ssdk-shell/Makefile | 51 + ...02-qca-ssdk-shell-fix-ioctl-segfault.patch | 93 + .../0003-qca-ssdk-shell-fix-tmpbool.patch | 11 + ...0004-qca-ssdk-shell-fix-build-gcc-15.patch | 215 + .../0005-qca-ssdk-shell-fix-make.patch | 46 + ...a-ssdk-shell-remove-unused-chip-code.patch | 612 + 259 files changed, 82506 insertions(+) create mode 100644 .github/ISSUE_TEMPLATE/bug-report.yml create mode 100644 .github/ISSUE_TEMPLATE/config.yml create mode 100644 .github/workflows/auto-close-non-english-issues.yml create mode 100644 LICENSE create mode 100644 README.md create mode 100755 firmware/aq-fw-download/Makefile create mode 100755 firmware/aq-fw-download/src/Makefile create mode 100755 firmware/aq-fw-download/src/include/AQ_API.h create mode 100755 firmware/aq-fw-download/src/include/AQ_PhyInterface.h create mode 100755 firmware/aq-fw-download/src/include/AQ_PlatformRoutines.h create mode 100755 firmware/aq-fw-download/src/include/AQ_RegMacro.h create mode 100755 firmware/aq-fw-download/src/include/AQ_ReturnCodes.h create mode 100755 firmware/aq-fw-download/src/include/AQ_User.h create mode 100755 firmware/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h create mode 100755 firmware/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h create mode 100755 firmware/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h create mode 100755 firmware/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h create mode 100755 firmware/aq-fw-download/src/include/registerMap/AQ_RegMaps.h create mode 100755 firmware/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h create mode 100755 firmware/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h create mode 100755 firmware/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h create mode 100755 firmware/aq-fw-download/src/mdioBootLoadCLD.c create mode 100755 firmware/aq-fw-download/src/src/AQ_API.c create mode 100755 firmware/aq-fw-download/src/src/AQ_PhyInterface.c create mode 100644 firmware/nss-eip-firmware/Makefile create mode 100644 firmware/nss-eip-firmware/src/.gitkeep create mode 100644 firmware/nss-eip-firmware/src/ifpp.bin create mode 100644 firmware/nss-eip-firmware/src/ipue.bin create mode 100644 firmware/nss-eip-firmware/src/ofpp.bin create mode 100644 firmware/nss-eip-firmware/src/opue.bin create mode 100644 firmware/nss-firmware/Makefile create mode 100644 nss-ifb/Makefile create mode 100644 nss-ifb/README.md create mode 100644 nss-ifb/src/Makefile create mode 100644 nss-ifb/src/nss_ifb.c create mode 100644 nss-userspace-oss/Makefile create mode 100644 nss-userspace-oss/libnl-nss/Makefile create mode 100644 nss-userspace-oss/libnl-nss/src/Makefile create mode 100644 nss-userspace-oss/libnl-nss/src/include/nss_nlbase.h create mode 100644 nss-userspace-oss/libnl-nss/src/include/nss_nldtls_api.h create mode 100644 nss-userspace-oss/libnl-nss/src/include/nss_nlipv4_api.h create mode 100644 nss-userspace-oss/libnl-nss/src/include/nss_nlipv6_api.h create mode 100644 nss-userspace-oss/libnl-nss/src/include/nss_nlist_api.h create mode 100644 nss-userspace-oss/libnl-nss/src/include/nss_nlmcast_api.h create mode 100644 nss-userspace-oss/libnl-nss/src/include/nss_nlsock_api.h create mode 100644 nss-userspace-oss/libnl-nss/src/nss_nldtls_api.c create mode 100644 nss-userspace-oss/libnl-nss/src/nss_nlipv4_api.c create mode 100644 nss-userspace-oss/libnl-nss/src/nss_nlipv6_api.c create mode 100644 nss-userspace-oss/libnl-nss/src/nss_nlmcast_api.c create mode 100644 nss-userspace-oss/libnl-nss/src/nss_nlsock.c create mode 100644 nss-userspace-oss/nssinfo/patches/001-fix-warnings.patch create mode 100644 nss-userspace-oss/patches/000-create-makefile.patch create mode 100644 nss-userspace-oss/patches/001-libnl-nss-revert-Add-timestamp-support-to-udpst.patch create mode 100644 nss-userspace-oss/patches/001-nssinfo-fix-warnings.patch create mode 100644 nss-userspace-oss/patches/002-libnl-modularize-makefile.patch create mode 100644 nss-userspace-oss/patches/002-nss-switch-to-nl-tiny.patch create mode 100644 nss-userspace-oss/patches/0030-fix-build.patch create mode 100644 qca-mcs/Makefile create mode 100644 qca-mcs/patches/0001-kernel-5.10-compat.patch create mode 100644 qca-mcs/patches/0002-kernel-6.6.29.patch create mode 100644 qca-mcs/patches/0003-fix-header-guard-gcc-15.patch create mode 100644 qca-mcs/patches/0004-kernel-6.12.patch create mode 100644 qca-nss-cfi/Makefile create mode 100644 qca-nss-cfi/patches/0004-cryptoapi-v2.0-aead-add-downstream-crypto_tfm_alg_fl.patch create mode 100644 qca-nss-cfi/patches/0007-cryptoapi-v2.0-fix-crash.patch create mode 100644 qca-nss-cfi/patches/0009-cryptoapi-v2.0-support-kernel-6.12.patch create mode 100644 qca-nss-clients/Config.in create mode 100644 qca-nss-clients/Makefile create mode 100755 qca-nss-clients/files/qca-nss-ipsec create mode 100644 qca-nss-clients/files/qca-nss-mirred.init create mode 100644 qca-nss-clients/files/qca-nss-netlink.init create mode 100644 qca-nss-clients/files/qca-nss-ovpn.init create mode 100644 qca-nss-clients/patches-11.4/0001-kernel-5.15-support-qdisc.patch create mode 100644 qca-nss-clients/patches-11.4/0002-kernel-5.4-support-gre.patch create mode 100644 qca-nss-clients/patches-11.4/0003-kernel-5.4-support-ipsec.patch create mode 100644 qca-nss-clients/patches-11.4/0004-kernel-5.4-support-dtls.patch create mode 100644 qca-nss-clients/patches-11.4/0005-vlanmgr-fix-compile-error.patch create mode 100644 qca-nss-clients/patches-11.4/0006-match-fix-compile-error.patch create mode 100644 qca-nss-clients/patches-11.4/0007-bridge-fix-compile-error.patch create mode 100644 qca-nss-clients/patches-11.4/0008-profiler-fix-compile-error.patch create mode 100644 qca-nss-clients/patches-11.4/0009-gre-fix-compile-error.patch create mode 100644 qca-nss-clients/patches-11.4/0010-fix-portifmgr.patch create mode 100644 qca-nss-clients/patches-11.4/0011-dtlsmgr-fix-SHA-header-include-in-5.15.patch create mode 100644 qca-nss-clients/patches-11.4/0012-dtlsmgr-fix-debug-print-in-5.15.patch create mode 100644 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qca-ssdk-shell/patches/0002-qca-ssdk-shell-fix-ioctl-segfault.patch create mode 100644 qca-ssdk-shell/patches/0003-qca-ssdk-shell-fix-tmpbool.patch create mode 100644 qca-ssdk-shell/patches/0004-qca-ssdk-shell-fix-build-gcc-15.patch create mode 100644 qca-ssdk-shell/patches/0005-qca-ssdk-shell-fix-make.patch create mode 100644 qca-ssdk-shell/patches/0006-qca-ssdk-shell-remove-unused-chip-code.patch diff --git a/.github/ISSUE_TEMPLATE/bug-report.yml b/.github/ISSUE_TEMPLATE/bug-report.yml new file mode 100644 index 0000000..5126012 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/bug-report.yml @@ -0,0 +1,74 @@ +--- +name: NSS Build Support Request +description: Use this template to report issues or request support for building NSS + packages. +body: + - type: markdown + attributes: + value: | + ### What is the issue? + Please provide a clear and concise description of the issue or the problem you are encountering. + + - type: textarea + id: issue_description + attributes: + label: Issue Description + description: Briefly describe the issue or the problem you are trying to solve. + placeholder: e.g., Error encountered during build, missing package, etc. + validations: + required: true + + - type: dropdown + id: openwrt_fork + attributes: + label: 1. Which OpenWrt NSS fork are you using? + description: Select the OpenWrt NSS fork you are building from. + options: + - qosmio/openwrt-ipq + - other + validations: + required: true + + - type: dropdown + id: branch + attributes: + label: 2. If you selected 'qosmio/openwrt-ipq', what branch are you building + from? + description: If you selected 'other', you can skip this. + options: + - main-nss + - 24.10-nss + + - type: input + id: custom_repo + attributes: + label: 3. If you selected 'other', what is the full repository? + description: Enter the full repository in the format `user/repo`. If you selected + 'qosmio/openwrt-ipq', you can skip this. + placeholder: user/repo + + - type: input + id: device_name + attributes: + label: 4. What is the exact device you are building for? + description: Provide the specific device name according to CONFIG_TARGET_PROFILE. + placeholder: e.g., DEVICE_linksys_mr7500 + validations: + required: true + + - type: markdown + attributes: + value: |- + ### 5. Attach your `.config` output: + Run the following command and attach the output below + ```bash + grep -Pi 'NSS_(?!DRV)|^(?!#)CONFIG_TARGET_(SUBTARGET|PROFILE|qualcommax)|^(?!#)CONFIG_(PACKAGE_kmod-qca-)|MEM_PROFILE' .config + ``` + + - type: textarea + id: config_output + attributes: + label: .config + render: ini + validations: + required: true diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml new file mode 100644 index 0000000..8005e32 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/config.yml @@ -0,0 +1,2 @@ +blank_issues_enabled: false +contact_links: [] diff --git a/.github/workflows/auto-close-non-english-issues.yml b/.github/workflows/auto-close-non-english-issues.yml new file mode 100644 index 0000000..dc2a9f9 --- /dev/null +++ b/.github/workflows/auto-close-non-english-issues.yml @@ -0,0 +1,94 @@ +--- +name: Auto Close Non-English Issues + +on: + issues: + types: + - opened + - edited + workflow_dispatch: + +jobs: + detect-language: + runs-on: ubuntu-latest + steps: + - name: Check out repository + uses: actions/checkout@v4 + + - name: Set up Node.js + uses: actions/setup-node@v4 + with: + node-version: '22' + + - name: Install dependencies + run: npm install franc-min + + - name: Detect language and close if not English + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + run: |- + # Create a script to detect language that NEVER exits with non-zero + echo "const franc = require('franc-min').franc || require('franc-min'); + + const text = process.argv[2] || ''; + + try { + const lang = franc(text, { minLength: 10 }); + if (lang !== 'eng') { + console.log(\`Text: \${text}\`); + console.log(\`Language detected: \${lang}. This is not English.\`); + console.log('NON_ENGLISH'); + } else { + console.log('Language detected: English.'); + console.log('ENGLISH'); + } + } catch (error) { + console.error('Error detecting language:', error.message); + console.log('ERROR'); + }" > detect.js + + + # Parse issue title, body, and number + ISSUE_TITLE=$(jq -r '.issue.title' "$GITHUB_EVENT_PATH") + ISSUE_BODY=$(jq -r '.issue.body' "$GITHUB_EVENT_PATH") + ISSUE_NUMBER=${{ github.event.issue.number }} + + + # Debug title, body, and number + echo "Debug: ISSUE_TITLE='$ISSUE_TITLE'" + echo "Debug: ISSUE_BODY='$ISSUE_BODY'" + echo "Debug: ISSUE_NUMBER='$ISSUE_NUMBER'" + + + # Function to check language and close issue if needed + check_and_close() { + local text="$1" + local field_name="$2" + + if [ -n "$text" ] && [ "$text" != "null" ]; then + echo "Checking $field_name..." + + + # Run detection and capture the output + result=$(node detect.js "$text" | tail -1) + + if [ "$result" = "NON_ENGLISH" ]; then + echo "$field_name is not in English. Closing issue..." + gh issue comment "$ISSUE_NUMBER" --body "Sorry, please open issues in English only. The $field_name was detected as non-English. This issue will be closed automatically." + gh issue close "$ISSUE_NUMBER" + echo "Issue closed successfully due to non-English content." + fi + else + echo "$field_name is empty or null, skipping..." + fi + } + + + # Check title first + check_and_close "$ISSUE_TITLE" "title" + + + # Check body second + check_and_close "$ISSUE_BODY" "body" + + echo "Workflow completed successfully." diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..d159169 --- /dev/null +++ b/LICENSE @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. 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Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/README.md b/README.md new file mode 100644 index 0000000..4ba9fb6 --- /dev/null +++ b/README.md @@ -0,0 +1,10 @@ +# nss-packages +Qualcomm networking packages feed for OpenWrt + +These packages provide drivers for wired networking and offloading features for the following SoC-s: +* IPQ807x +* IPQ60xx (Untested) +* IPQ50xx (Untested) + +Note that these require kernel patches which are part of the main OpenWrt tree, this is only the package +feed. diff --git a/firmware/aq-fw-download/Makefile b/firmware/aq-fw-download/Makefile new file mode 100755 index 0000000..60f5882 --- /dev/null +++ b/firmware/aq-fw-download/Makefile @@ -0,0 +1,26 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=aq-fw-download +PKG_RELEASE:=$(AUTORELEASE) + +PKG_FLAGS:=nonshared + +include $(INCLUDE_DIR)/package.mk + +define Package/aq-fw-download + SECTION:=firmware + CATEGORY:=Firmware + DEPENDS:=@TARGET_qualcommax + TITLE:=Aquantia FW downloader utitlity +endef + +define Package/aq-fw-download/description + Aquantia FW downloader utitlity +endef + +define Package/aq-fw-download/install + $(INSTALL_DIR) $(1)/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/aq-fw-download $(1)/sbin/aq-fw-download +endef + +$(eval $(call BuildPackage,aq-fw-download)) diff --git a/firmware/aq-fw-download/src/Makefile b/firmware/aq-fw-download/src/Makefile new file mode 100755 index 0000000..dc141be --- /dev/null +++ b/firmware/aq-fw-download/src/Makefile @@ -0,0 +1,14 @@ +ifndef CFLAGS +CFLAGS = -O2 -g +endif +INCLUDES=-Iinclude -Iinclude/registerMap \ + -Iinclude/registerMap/APPIA \ + -Iinclude/registerMap/HHD + +all: aq-fw-download + +%.o: %.c + $(CC) $(INCLUDES) $(CFLAGS) -c -o $@ $^ + +aq-fw-download: mdioBootLoadCLD.o src/AQ_PhyInterface.o src/AQ_API.o + $(CC) $(LDFLAGS) -o $@ $^ $(LIBS) diff --git a/firmware/aq-fw-download/src/include/AQ_API.h b/firmware/aq-fw-download/src/include/AQ_API.h new file mode 100755 index 0000000..9a0b4c2 --- /dev/null +++ b/firmware/aq-fw-download/src/include/AQ_API.h @@ -0,0 +1,246 @@ +/* +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ + +/*! \file + This file contains the AQ_API function and datatype declarations. */ + + +#ifndef AQ_API_TOKEN +#define AQ_API_TOKEN + +#include + +#include "AQ_User.h" +#include "AQ_ReturnCodes.h" + +/******************************************************************* + General +*******************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! This typedef defines the bool datatype which takes the values +true and false.*/ +typedef enum {False = 0, True = 1} AQ_boolean; + + +/*@}*/ + + +/******************************************************************* + Device Identity +*******************************************************************/ + +/*! \defgroup deviceIdentity Device Identity +All AQ_API functions accept a parameter identifying the target PHY that +should be acted upon. */ +/*@{*/ + + +/*! This enumeration is used to describe the different types of + Aquantia PHY.*/ +typedef enum +{ + /*! 1/2/4-port package, 40nm architechture.*/ + AQ_DEVICE_APPIA, + /*! 1/2/4-port package, 28nm architechture.*/ + AQ_DEVICE_HHD +} AQ_API_Device; + +/*! This structure is used to specify a particular Aquantia PHY port + within the system.*/ +typedef struct +{ + /*! The type of Aquantia PHY*/ + AQ_API_Device device; + /*! Uniquely identifies the port within the system. AQ_Port must be + defined to whatever data type is suitable for the platform. + AQ_API functions will never do anything with PHY_ID other than + pass it down to the platform's PHY register read/write + functions.*/ + AQ_Port PHY_ID; +} AQ_API_Port; + +/*@}*/ + + +/*! This function boot-loads the instruction and data memory (IRAM and + DRAM) of a set of Aquantia PHYs from a .cld format image file (the + same image file used to burn the FLASH). During boot-load of each + Aquantia PHY, the processor is halted, and after programming is + complete the processor is released. Note that calling this + function leaves the daisy-chain disabled to prevent RAM over- + write. To exit MDIO boot-load mode, use the function + AQ_API_EnableDaisyChain. + Unlike most of the other functions in this API, this function can + operate on a group of PHYs simultaneously. This is referred to as + gang-loading. To facilitate this, this function takes as + parameters 3 parallel arrays: PHY_IDs, provisioningAddresses, and + resultCodes. The length of these arrays must be identical, and is + specified by the num_PHY_IDs parameter. + In order to check the integrity of the boot-load operation, a + CRC-16 value is calculated over the IRAM and DRAM. After the image + has been loaded, this value is directly compared against each + PHY's Mailbox CRC-16 in 1E.0201. + The value of register 1E.C441 must be the same for all the boot- + loaded PHYs. This will be checked before the boot-load is + performed, and if a non-uniform value is read from any of the + PHYs, the function will fail before any writes are performed. + A separate result code is returned for each of the boot-loaded + PHYs, in the OUT parameter, resultCodes. + Individual Port Return codes: + AQ_RET_BOOTLOAD_PROVADDR_OOR: The specified provisioning address + was outside of the permitted range. + AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS: The values of the register(s) + that must be uniform across the ports being bootloaded were not + uniform. + AQ_RET_BOOTLOAD_CRC_MISMATCH: The image was completely loaded into + memory, but the after the port exited bootload the running + checksum that was read from the uP memory mailbox was not the + expected value. This indicates that the memory has potentially + been corrupted, and the PHY should be reset before trying the + bootload again. + Overall Return codes (the return value from the function call): + AQ_RET_OK: all ports were successfully bootloaded. + AQ_RET_ERROR: One or more ports were not successfully bootloaded. + */ +AQ_Retcode AQ_API_WriteBootLoadImage +( + /*! An array identifying the target PHY ports.*/ + AQ_API_Port** ports, + /*! The length of the arrays ports, provisioningAddresses, and + resultCodes. These are parallel arrays, and must all be of the + same length.*/ + unsigned int numPorts, + /*! The provisioning addresses of each of the PHYs specified in + ports. This can range from 0 through 47, and is also known as + the daisy-chain address or the hop-count. If the PHYs are + connected to a FLASH using the daisy-chain, this is the distance + from the PHY to the FLASH, and is used to identify customized + provisioning for each PHY from the provisioning data within the + image. Otherwise, it is an arbitrary number. The length of this + array must match the length of ports.*/ + unsigned int* provisioningAddresses, + /*! OUT: The result code indicating success or failure of boot- + loading each of the PHYs specified in ports.*/ + AQ_Retcode* resultCodes, + /*! A pointer to the size of the image (in bytes) that is being + loaded into the Aquantia PHY.*/ + uint32_t* imageSizePointer, + /*! The image being loaded into the Aquantia PHY. This is the same + regardless of whether the target is internal RAM or FLASH.*/ + uint8_t* image, + /*! The 5-bit address to be used during the gang-loading operation. + During the boot-loading process, each of the PHYs specified in + ports will be changed such that they are addressed on the MDIO + bus at gangloadAddress. This allows all the PHYs to be loaded + simultaneously. Before returning, each PHY will be moved back to + its original MDIO address. If ports contains only a single + element, callers will probably want to use the PHY's original + MDIO address for this parameter.*/ + uint8_t gangload_MDIO_address, + /*! The address of the PHYs while in gangload mode. This is + ultimately some combination of the system address and the + gangload MDIO address, specified by gangload_MDIO_address. For + most platforms, gangload_MDIO_address and gangload_PHY_ID should + have the same value.*/ + AQ_API_Port* gangloadPort +); + +/*! This function boot-loads the instruction and data memory (IRAM and + DRAM) of a set of Aquantia PHYs from a .cld format image file (the + same image file used to burn the FLASH), as well as a separately + provided provisioning table image file.The provisioning table + image allows additional provisioning to be provided, beyond what + is built in to the .cld image. If provTableSizePointer or + provTableImage are NULL, this function behaves like + AQ_API_WriteBootLoadImage. + Aside from the additional provisioing table, this function behaves + exactly the same as AQ_API_WriteBootLoadImage. For additional + documentation and information on return codes, refer to + AQ_API_WriteBootLoadImage. + Individual Port Return codes (same as AQ_API_WriteBootLoadImage, + plus): + AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE: The supplied provisioning + table image does not fit within the alloted space.*/ +AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable +( + /*! An array identifying the target PHY ports.*/ + AQ_API_Port** ports, + /*! The length of the arrays ports, provisioningAddresses, and + resultCodes. These are parallel arrays, and must all be of the + same length.*/ + unsigned int numPorts, + /*! The provisioning addresses of each of the PHYs specified in + ports. This can range from 0 through 47, and is also known as + the daisy-chain address or the hop-count. If the PHYs are + connected to a FLASH using the daisy-chain, this is the distance + from the PHY to the FLASH, and is used to identify customized + provisioning for each PHY from the provisioning data within the + image. Otherwise, it is an arbitrary number. The length of this + array must match the length of ports.*/ + unsigned int* provisioningAddresses, + /*! OUT: The result code indicating success or failure of boot- + loading each of the PHYs specified in ports.*/ + AQ_Retcode* resultCodes, + /*! A pointer to the size of the image (in bytes) that is being + loaded into the Aquantia PHY.*/ + uint32_t* imageSizePointer, + /*! The image being loaded into the Aquantia PHY. This is the same + regardless of whether the target is internal RAM or FLASH.*/ + uint8_t* image, + /*! The 5-bit address to be used during the gang-loading operation. + During the boot-loading process, each of the PHYs specified in + ports will be changed such that they are addressed on the MDIO + bus at gangloadAddress. This allows all the PHYs to be loaded + simultaneously. Before returning, each PHY will be moved back to + its original MDIO address. If ports contains only a single + element, callers will probably want to use the PHY's original + MDIO address for this parameter.*/ + uint8_t gangload_MDIO_address, + /*! The address of the PHYs while in gangload mode. This is + ultimately some combination of the system address and the + gangload MDIO address, specified by gangload_MDIO_address. For + most platforms, gangload_MDIO_address and gangload_PHY_ID should + have the same value.*/ + AQ_API_Port* gangloadPort, + /*! A pointer to the size of the provTableImage (in bytes) that is + being loaded into the Aquantia PHY.*/ + uint32_t* provTableSizePointer, + /*! The additional provisioning table image being loaded into the + Aquantia PHY.*/ + uint8_t* provTableImage +); + +/*! Calling this function disables boot-loading and enables the daisy- + chain. This would typically be called after using MDIO boot- + loading on a daisy-chain enabled PHY. Re-enabling the daisy-chain + after performing an MDIO bootload will cause the PHY to reboot + from FLASH.*/ +AQ_Retcode AQ_API_EnableDaisyChain +( + /*! The target PHY port.*/ + AQ_API_Port* port +); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/firmware/aq-fw-download/src/include/AQ_PhyInterface.h b/firmware/aq-fw-download/src/include/AQ_PhyInterface.h new file mode 100755 index 0000000..66eb817 --- /dev/null +++ b/firmware/aq-fw-download/src/include/AQ_PhyInterface.h @@ -0,0 +1,171 @@ +/* AQ_PhyInterface.h */ + +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* Declares the base PHY register read and write functions that are +* called by the API functions. The platform integrator must provide +* the implementation of these routines. +* +***********************************************************************/ + + +/*! \file + * Declares the base PHY register read and write functions that are + * called by the API functions. The platform integrator must provide + * the implementation of these routines. */ + + +#ifndef AQ_PHY_INTERFACE_TOKEN +#define AQ_PHY_INTERFACE_TOKEN + + +#include "AQ_API.h" +#include "AQ_User.h" + + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************* + MDIO Access Functions +*******************************************************************/ + +/*! \defgroup mdioAccessFunctions MDIO Access Functions +The MDIO access functions are required by the API to access the register space +of each Aquantia PHY deployed in a system. The body of these functions needs to +be written by the system designer, as the method of accessing the PHY will +be unique to the target system. They are designed to be generic read and +write access functions, as the MDIO addressing scheme relies on each +MMD to maintain a 16 bit address pointer that determines the register where +the next read or write is coming from. Consequently, various levels of +optimization of the MDIO interface are possible: from re-writing the MMD +address pointer on every transaction, to storing shadow copies of the MMD +address pointers and only updating the MMD address pointer as necessary. +Thus these functions leave the MDIO optimization to the system engineer. + */ +/*@{*/ + + +/*! Provides generic synchronous PHY register write functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this write operation. + * It will be assumed that the write has been completed by the time this + * function returns.*/ +void AQ_API_MDIO_Write +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being written. */ + unsigned int address, + /*! The 16-bits of data to write to the specified PHY register. */ + unsigned int data +); + +/*! Provides generic synchronous PHY register read functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this read operation.*/ +unsigned int AQ_API_MDIO_Read +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being read. */ + unsigned int address +); + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + +/*! Provides generic asynchronous/buffered PHY register write functionality. + * It is the responsibility of the system designer to provide the specific + * MDIO address pointer updates, etc. in order to accomplish this write + * operation. The write need not necessarily have been completed by the time + * this function returns. All register reads and writes to a particular PHY_ID + * that are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead + * MUST be performed in the order that the calls are made. */ +void AQ_API_MDIO_BlockWrite +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being written. */ + unsigned int address, + /*! The 16-bits of data to write to the specified PHY register. */ + unsigned int data +); + +/*! Provides generic asynchronous/buffered PHY register read functionality. + * It is the responsibility of the system designer to provide the specific + * MDIO address pointer updates, etc. in order to accomplish this read + * operation. All register reads and writes to a particular PHY_ID that + * are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead + * MUST be performed in the order that the calls are made. The register value + * may subsequently be fetched by calling AQ_API_MDIO_BlockOperationExecute.*/ +void AQ_API_MDIO_BlockRead +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being read. */ + unsigned int address +); + +/* Retrieve the results of all PHY register reads to PHY_ID previously + * requested via calls to AQ_API_MDIO_BlockRead. The read and write + * operations previously performed by calls to AQ_API_MDIO_BlockRead and + * AQ_API_MDIO_BlockRead must have all been completed by the time this + * function returns, in the order that the calls were performed. The + * return value is an array representing the fetched results of all + * pending calls to AQ_API_MDIO_BlockRead, in the order that the calls + * were performed. Callers should track the number of pending block + * reads to determine the size of the returned array. */ +unsigned int * AQ_API_MDIO_BlockOperationExecute +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID +); + +/* Returns the maximum number of asynchronous/buffered PHY register + * read/write operations. Callers will call AQ_API_MDIO_BlockOperationExecute + * before issuing additional calls to AQ_API_MDIO_BlockWrite or + * AQ_API_MDIO_BlockRead to avoid a buffer overflow. */ +unsigned int AQ_API_MDIO_MaxBlockOperations +( +); + +#endif + +/*@}*/ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/firmware/aq-fw-download/src/include/AQ_PlatformRoutines.h b/firmware/aq-fw-download/src/include/AQ_PlatformRoutines.h new file mode 100755 index 0000000..9a16d64 --- /dev/null +++ b/firmware/aq-fw-download/src/include/AQ_PlatformRoutines.h @@ -0,0 +1,71 @@ +/*AQ_PlatformRoutines.h*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* Declares the platform interface functions that will be called by AQ_API +* functions. The platform integrator must provide the implementation of +* these functions. +* +************************************************************************************/ + +/*! \file + * Declares the platform interface functions that will be called by AQ_API + * functions. The platform integrator must provide the implementation of + * these functions. */ + + +#ifndef AQ_PHY_PLATFORMROUTINES_TOKEN +#define AQ_PHY_PLATFORMROUTINES_TOKEN + +#include + +#include "AQ_API.h" +#include "AQ_User.h" +#include "AQ_ReturnCodes.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************* + Time Delay +*******************************************************************/ + +/*! \defgroup delay Time Delay + @{ +*/ + +/*! Returns after at least milliseconds have elapsed. This must be implemented + * in a platform-approriate way. AQ_API functions will call this function to + * block for the specified period of time. If necessary, PHY register reads + * may be performed on port to busy-wait. */ +void AQ_API_Wait +( + uint32_t milliseconds, /*!< The delay in milliseconds */ + AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ +); + +/*@}*/ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/firmware/aq-fw-download/src/include/AQ_RegMacro.h b/firmware/aq-fw-download/src/include/AQ_RegMacro.h new file mode 100755 index 0000000..8dcca52 --- /dev/null +++ b/firmware/aq-fw-download/src/include/AQ_RegMacro.h @@ -0,0 +1,323 @@ +/* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ +/*! \file + This file contains macros for accessing the AQ PHYs' registers + using the device-specific register map data structures and definitions. +*/ + +#ifndef AQ_REG_MACRO_TOKEN +#define AQ_REG_MACRO_TOKEN + +#include "AQ_PhyInterface.h" + + +#define AQ_API_ReadRegister(id,reg,wd) AQ_API_ReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd) + +#define AQ_API_ReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_ReadRegister_Devs_ ## devices(id,reg,wd) + +#define AQ_API_ReadRegister_Devs_APPIA(id,reg,wd) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + (0)) + +#define AQ_API_ReadRegister_Devs_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + (0)) + +#define AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + (0))) + +#define AQ_API_ReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) + + +#define AQ_API_WriteRegister(id,reg,wd,value) AQ_API_WriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value) + +#define AQ_API_WriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_WriteRegister_Devs_ ## devices(id,reg,wd,value) + +#define AQ_API_WriteRegister_Devs_APPIA(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_WriteRegister_Devs_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0))) + +#define AQ_API_WriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) + + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + +#define AQ_API_BlockReadRegister(id,reg,wd) AQ_API_BlockReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd) + +#define AQ_API_BlockReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_BlockReadRegister_Devs_ ## devices(id,reg,wd) + +#define AQ_API_BlockReadRegister_Devs_APPIA(id,reg,wd) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + ((void)0)) + +#define AQ_API_BlockReadRegister_Devs_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + ((void)0)) + +#define AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + ((void)0))) + +#define AQ_API_BlockReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) + + +#define AQ_API_BlockWriteRegister(id,reg,wd,value) AQ_API_BlockWriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value) + +#define AQ_API_BlockWriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_ ## devices(id,reg,wd,value) + +#define AQ_API_BlockWriteRegister_Devs_APPIA(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_BlockWriteRegister_Devs_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0))) + +#define AQ_API_BlockWriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) + + +#endif + +#define AQ_API_Variable(reg) AQ_API_Variable_DeviceRestricted(APPIA_HHD,reg) + +#define AQ_API_Variable_DeviceRestricted(devices,reg) AQ_API_Variable_Devs_ ## devices(reg) + +#define AQ_API_Variable_Devs_APPIA(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \ + +#define AQ_API_Variable_Devs_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \ + +#define AQ_API_Variable_Devs_APPIA_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \ + reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \ + +#define AQ_API_Variable_Devs_HHD_APPIA(reg) AQ_API_Variable_Devs_APPIA_HHD(reg) + + +#define AQ_API_DeclareLocalStruct(reg,localvar) AQ_API_DeclareLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar) + +#define AQ_API_DeclareLocalStruct_DeviceRestricted(devices,reg,localvar) AQ_API_DeclareLocalStruct_Devs_ ## devices(reg,localvar) + +#define AQ_API_DeclareLocalStruct_Devs_APPIA(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \ + +#define AQ_API_DeclareLocalStruct_Devs_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \ + +#define AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \ + reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \ + +#define AQ_API_DeclareLocalStruct_Devs_HHD_APPIA(reg,localvar) AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) + + +#define AQ_API_Set(id,reg,field,value) AQ_API_Set_DeviceRestricted(APPIA_HHD,id,reg,field,value) + +#define AQ_API_Set_DeviceRestricted(devices,id,reg,field,value) AQ_API_Set_Devs_ ## devices(id,reg,field,value) + +#define AQ_API_Set_Devs_APPIA(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \ + if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \ + { \ + _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \ + } \ + break; \ + default: break; \ + } \ +} + +#define AQ_API_Set_Devs_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \ + if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \ + { \ + _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \ + } \ + break; \ + default: break; \ + } \ +} + +#define AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \ + if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \ + { \ + _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \ + } \ + break; \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \ + if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \ + { \ + _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \ + } \ + break; \ + default: break; \ + } \ +} + +#define AQ_API_Set_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) + + +#define AQ_API_Get(id,reg,field,value) AQ_API_Get_DeviceRestricted(APPIA_HHD,id,reg,field,value) + +#define AQ_API_Get_DeviceRestricted(devices,id,reg,field,value) AQ_API_Get_Devs_ ## devices(id,reg,field,value) + +#define AQ_API_Get_Devs_APPIA(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \ + value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \ + break; \ + default: value = 0; break; \ + } \ +} + +#define AQ_API_Get_Devs_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \ + value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \ + break; \ + default: value = 0; break; \ + } \ +} + +#define AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \ + value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \ + break; \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \ + value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \ + break; \ + default: value = 0; break; \ + } \ +} + +#define AQ_API_Get_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) + + +#define AQ_API_BitfieldOfLocalStruct(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field) + +#define AQ_API_BitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field) + +#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \ + (0)) + +#define AQ_API_BitfieldOfLocalStruct_Devs_HHD(reg,localvar,field) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \ + (0)) + +#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \ + (0))) + +#define AQ_API_BitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) + + +#define AQ_API_AssignBitfieldOfLocalStruct(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field,value) + +#define AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field,value) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field,value) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \ + (0)) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD(reg,localvar,field,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \ + (0)) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \ + (0))) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) + + +#define AQ_API_WordOfLocalStruct(localvar,wd) AQ_API_WordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd) + +#define AQ_API_WordOfLocalStruct_DeviceRestricted(devices,localvar,wd) AQ_API_WordOfLocalStruct_Devs_ ## devices(localvar,wd) + +#define AQ_API_WordOfLocalStruct_Devs_APPIA(localvar,wd) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \ + (0)) + +#define AQ_API_WordOfLocalStruct_Devs_HHD(localvar,wd) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \ + (0)) + +#define AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \ + (0))) + +#define AQ_API_WordOfLocalStruct_Devs_HHD_APPIA(localvar,wd) AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) + + +#define AQ_API_AssignWordOfLocalStruct(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd,value) + +#define AQ_API_AssignWordOfLocalStruct_DeviceRestricted(devices,localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_ ## devices(localvar,wd,value) + +#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA(localvar,wd,value) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \ + (0)) + +#define AQ_API_AssignWordOfLocalStruct_Devs_HHD(localvar,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \ + (0)) + +#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \ + (0))) + +#define AQ_API_AssignWordOfLocalStruct_Devs_HHD_APPIA(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) + + +#endif + diff --git a/firmware/aq-fw-download/src/include/AQ_ReturnCodes.h b/firmware/aq-fw-download/src/include/AQ_ReturnCodes.h new file mode 100755 index 0000000..bff083b --- /dev/null +++ b/firmware/aq-fw-download/src/include/AQ_ReturnCodes.h @@ -0,0 +1,113 @@ +/* AQ_ReturnCodes.h */ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file defines the AQ_API functions' integral return codes. +* +* +************************************************************************************/ + +/*! \file + This file defines the AQ_API functions' integral return codes. +*/ + +#ifndef AQ_RETURNCODES_TOKEN +#define AQ_RETURNCODES_TOKEN + + +/*! \defgroup ReturnCodes + @{ +*/ + +/*! Most AQ_API functions return AQ_Retcode to report success or failure. + * The values used are defined as preprocessor symbols in AQ_ReturnCodes.h. + * Callers should prefer to test the return values by equivalence to these + * symbols, rather than using the integer values directly, as these may + * not be stable across releases. The set of possible return codes that may + * be returned by a particular API function can be found in the function's + * documentation, as well as information on how to interpret each of the + * possible return codes. */ +typedef unsigned int AQ_Retcode; + +/*! \defgroup Success + @{ */ +#define AQ_RET_OK 0 +/*@}*/ + + +/*! \defgroup GeneralErrors + @{ */ +#define AQ_RET_ERROR 100 +#define AQ_RET_UP_BUSY_TIMEOUT 101 +/*@}*/ + +/*! \defgroup FunctionSpecificResults + @{ */ +#define AQ_RET_FLASH_READY 200 +#define AQ_RET_FLASH_READINESS_TIMEOUT 204 + +#define AQ_RET_FLASHINTF_READY 201 +#define AQ_RET_FLASHINTF_NOTREADY 202 +#define AQ_RET_FLASHINTF_READINESS_TIMEOUT 203 + +#define AQ_RET_FLASH_TYPE_UNKNOWN 205 +#define AQ_RET_FLASH_TYPE_BAD 206 + +#define AQ_RET_FLASH_IMAGE_CORRUPT 207 +#define AQ_RET_FLASH_IMAGE_TOO_LARGE 208 +#define AQ_RET_FLASH_IMAGE_MISMATCH 209 + +#define AQ_RET_FLASH_PAGE_SIZE_CHANGED 210 + +#define AQ_RET_BOOTLOAD_PROVADDR_OOR 211 +#define AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS 212 +#define AQ_RET_BOOTLOAD_CRC_MISMATCH 213 +#define AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE 228 + +#define AQ_RET_LOOPBACK_BAD_ENTRY_STATE 214 + +#define AQ_RET_DEBUGTRACE_FREEZE_TIMEOUT 215 +#define AQ_RET_DEBUGTRACE_UNFREEZE_TIMEOUT 216 + +#define AQ_RET_CABLEDIAG_ALREADY_RUNNING 217 +#define AQ_RET_CABLEDIAG_STILL_RUNNING 218 +#define AQ_RET_CABLEDIAG_BAD_PAIRSTATUS 219 +#define AQ_RET_CABLEDIAG_RESULTS_ALREDY_COLLECTED 220 +#define AQ_RET_CABLEDIAG_BAD_NUM_SAMPLES 221 +#define AQ_RET_CABLEDIAG_REPORTEDPAIR_MISMATCH 222 +#define AQ_RET_CABLEDIAG_REPORTEDPAIR_OOR 223 +#define AQ_RET_CABLEDIAG_STARTED_PAIR_B 224 +#define AQ_RET_CABLEDIAG_STARTED_PAIR_C 225 +#define AQ_RET_CABLEDIAG_STARTED_PAIR_D 226 +#define AQ_RET_CABLEDIAG_TXENABLE_MISMATCH 227 + +#define AQ_RET_SERDESEYE_BAD_SERDES_MODE 229 +#define AQ_RET_SERDESEYE_BAD_MEAS_COUNT 230 +#define AQ_RET_SERDESEYE_MEAS_TIMEOUT 231 +#define AQ_RET_SERDESEYE_LANE_OOR 232 +#define AQ_RET_SERDESEYE_COORD_OOR 233 + +#define AQ_RET_PIFMAILBOX_ERROR 234 +#define AQ_RET_PIFMAILBOX_TIMEOUT 235 + +#define AQ_RET_SEC_TABLE_INDEX_OOR 236 +/*@}*/ + +/*@}*/ + +#endif diff --git a/firmware/aq-fw-download/src/include/AQ_User.h b/firmware/aq-fw-download/src/include/AQ_User.h new file mode 100755 index 0000000..c7526a7 --- /dev/null +++ b/firmware/aq-fw-download/src/include/AQ_User.h @@ -0,0 +1,97 @@ +/*AQ_User.h*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file contains preprocessor symbol definitions and type definitions +* for the platform-integrator controlled compile-time AQ_API options. +* +************************************************************************************/ + +/*! \file + This file contains preprocessor symbol definitions and type definitions + for the platform-integrator controlled compile-time AQ_API options. +*/ + +#ifndef AQ_USER_TOKEN +#define AQ_USER_TOKEN + +/*! \defgroup User User Definitions +This module contains the definitions used to configure AQ_API behavior as desired. */ +/*@{*/ + + +/*! Specify the proper data type for AQ_Port. This will depend on the + * platform-specific implementation of the PHY register read/write functions.*/ +typedef unsigned int AQ_Port; + + +/*! If defined, AQ_API functions will print various error and info messages + * to stdout. If not, nothing will be printed and AQ_API.c will NOT include + * stdio.h. */ +#define AQ_VERBOSE + + +/*! If defined, the PHY interface supports block (asynchronous) read/write + * operation. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is defined, then + * the API will call the block-operation functions and so implementations + * for each must be provided. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is not + * defined, they will not be called, and need not be implemented. */ +#undef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + + +/*! If defined, time.h exists, and so the associated functions wil be used to + * compute the elapsed time spent in a polling loop, to ensure that the + * maximum time-out period will not be exceeded. If not defined, then + * AQ_MDIO_READS_PER_SECOND will be used to calculate the minimum possible + * elapsed time. */ +#define AQ_TIME_T_EXISTS + + +/*! The maximum number of synchronous PHY register reads that can be performed + * per second. A worst case number can be derived as follows: + * + * AQ_MDIO_READS_PER_SECOND = MDIO Clock Frequency / 64 + * + * If using MDIO preamble suppression, multiply this number by 2 + * + * For instance, if a 5MHz MDIO clock is being used without preamble supression + * AQ_MDIO_READS_PER_SECOND = 78125 + * + * If AQ_TIME_T_EXISTS is defined, this will be ignored and need not be + * defined. If AQ_TIME_T_EXISTS is not defined, this must be defined. */ +#define AQ_MDIO_READS_PER_SECOND 78125 + + +/*! If defined, after writing to one of the registers that can trigger a + * processor-intensive MDIO operation, AQ_API functions will poll the + * the "processor intensive MDIO operation in progress" bit and wait for it + * to be zero before proceeding. */ +#define AQ_ENABLE_UP_BUSY_CHECKS + + +/*! If defined, the register map header files containing reverse-packed + * structs will be included. If not, the register map header files containing + * non-reverse-packed structs will be included. The proper choice is typically + * a function of the endianness of the platform; on big-endian systems the + * reverse-packed structs should be used, and on little-endian systems the + * non-reverse-packed structs should be used. */ +/*#define AQ_REVERSED_BITFIELD_ORDERING*/ + +/*@}*/ +#endif + diff --git a/firmware/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h b/firmware/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h new file mode 100755 index 0000000..a9485f5 --- /dev/null +++ b/firmware/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h @@ -0,0 +1,5581 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from LSbit to MSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_APPIA_GLOBAL_REGS_HEADER +#define AQ_APPIA_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved0 : 2; + /*! \brief 1E.0000.E R/WSC Hard Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.hardReset + + Default = 0x0 + + 1 = Global hard reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global hard reset, equivalent to pulling the reset pin low. This is a level sensitive pin that connects into the power-on reset generation circuitry to initiate a complete power-on reset. */ + unsigned int hardReset : 1; /* 1E.0000.E R/WSC Default = 0x0 */ + /* 1 = Global hard reset + 0 = Normal operation + */ + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global soft reset on all of the digital logic, including the microprocessor. Upon completion of the reset sequence, this bit is set back to 0. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_APPIA.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_APPIA.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_APPIA.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_APPIA.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_APPIA.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Identification: 1E.0021 */ +/* Global Chip Identification: 1E.0021 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Identification */ + union + { + struct + { + /*! \brief 1E.0021.F:0 RO Chip Identification [F:0] + AQ_GlobalChipIdentification_APPIA.u0.bits_0.chipIdentification + + + + Hardware Chip ID + + Notes: + This value is a hard-coded chip ID */ + unsigned int chipIdentification : 16; /* 1E.0021.F:0 RO */ + /* Hardware Chip ID */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipIdentification_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Revision: 1E.0022 */ +/* Global Chip Revision: 1E.0022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Revision */ + union + { + struct + { + /*! \brief 1E.0022.F:0 RO Chip Revision [F:0] + AQ_GlobalChipRevision_APPIA.u0.bits_0.chipRevision + + + + Hardware Chip Revision + + Notes: + This value is a hard-coded chip revision */ + unsigned int chipRevision : 16; /* 1E.0022.F:0 RO */ + /* Hardware Chip Revision */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipRevision_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_APPIA.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_APPIA.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + unsigned int reserved0 : 8; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_APPIA.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved2 : 8; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occured and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_APPIA.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_APPIA.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalMailboxInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad1 + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad1 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch P + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch P */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_APPIA.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. The PIF slave bus for inbound requests will still be active. This bit is muliplexed with the "MDIO Boot Load" pin with the See uP Run Stall Override bit as the select. When the "MDIO Boot Load" pin is asserted, the uP will be in Run Stall mode after reset. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_APPIA.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_APPIA.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved1 : 14; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_APPIA.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_APPIA.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_APPIA.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C433.1:0 R/WPD LED #3 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_3ActivityStretch : 2; /* 1E.C433.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C433.2 R/WPD LED #3 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_3TransmitActivity : 1; /* 1E.C433.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C433.3 R/WPD LED #3 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_3ReceiveActivity : 1; /* 1E.C433.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C433.4 R/WPD LED #3 Connecting + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_3Connecting : 1; /* 1E.C433.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C433.5 R/WPD LED #3 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_3_100Mb_sLinkEstablished : 1; /* 1E.C433.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C433.6 R/WPD LED #3 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_3_1Gb_sLinkEstablished : 1; /* 1E.C433.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C433.7 R/WPD LED #3 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_3_10Gb_sLinkEstablished : 1; /* 1E.C433.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C433.8 R/WPD LED #3 Manual Set + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_3ManualSet : 1; /* 1E.C433.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C434.1:0 R/WPD LED #4 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_4ActivityStretch : 2; /* 1E.C434.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C434.2 R/WPD LED #4 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_4TransmitActivity : 1; /* 1E.C434.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C434.3 R/WPD LED #4 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_4ReceiveActivity : 1; /* 1E.C434.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C434.4 R/WPD LED #4 Connecting + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_4Connecting : 1; /* 1E.C434.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C434.5 R/WPD LED #4 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_4_100Mb_sLinkEstablished : 1; /* 1E.C434.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C434.6 R/WPD LED #4 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_4_1Gb_sLinkEstablished : 1; /* 1E.C434.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C434.7 R/WPD LED #4 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_4_10Gb_sLinkEstablished : 1; /* 1E.C434.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C434.8 R/WPD LED #4 Manual Set + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_4ManualSet : 1; /* 1E.C434.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C435.1:0 R/WPD LED #5 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_5ActivityStretch : 2; /* 1E.C435.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C435.2 R/WPD LED #5 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_5TransmitActivity : 1; /* 1E.C435.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C435.3 R/WPD LED #5 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_5ReceiveActivity : 1; /* 1E.C435.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C435.4 R/WPD LED #5 Connecting + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_5Connecting : 1; /* 1E.C435.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C435.5 R/WPD LED #5 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_5_100Mb_sLinkEstablished : 1; /* 1E.C435.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C435.6 R/WPD LED #5 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_5_1Gb_sLinkEstablished : 1; /* 1E.C435.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C435.7 R/WPD LED #5 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_5_10Gb_sLinkEstablished : 1; /* 1E.C435.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C435.8 R/WPD LED #5 Manual Set + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_5ManualSet : 1; /* 1E.C435.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_APPIA.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + */ + unsigned int reserved0 : 15; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C438.0 R/WPD LED #0 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_0ManualActiveSelect : 1; /* 1E.C438.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C438.1 R/WPD LED #0 Active High Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #0 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_0ActiveHighSelect : 1; /* 1E.C438.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C438.2 R/WPD LED #0 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_0DriveThreeStateSelect : 1; /* 1E.C438.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C439.0 R/WPD LED #1 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_1ManualActiveSelect : 1; /* 1E.C439.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C439.1 R/WPD LED #1 Active High Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #1 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_1ActiveHighSelect : 1; /* 1E.C439.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C439.2 R/WPD LED #1 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_1DriveThreeStateSelect : 1; /* 1E.C439.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43A.0 R/WPD LED #2 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_2ManualActiveSelect : 1; /* 1E.C43A.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43A.1 R/WPD LED #2 Active High Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #2 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_2ActiveHighSelect : 1; /* 1E.C43A.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43A.2 R/WPD LED #2 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_2DriveThreeStateSelect : 1; /* 1E.C43A.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43B.0 R/WPD LED #3 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_3ManualActiveSelect : 1; /* 1E.C43B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43B.1 R/WPD LED #3 Active High Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #3 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_3ActiveHighSelect : 1; /* 1E.C43B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43B.2 R/WPD LED #3 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_3DriveThreeStateSelect : 1; /* 1E.C43B.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43C.0 R/WPD LED #4 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_4ManualActiveSelect : 1; /* 1E.C43C.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43C.1 R/WPD LED #4 Active High Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #4 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_4ActiveHighSelect : 1; /* 1E.C43C.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43C.2 R/WPD LED #4 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_4DriveThreeStateSelect : 1; /* 1E.C43C.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43D.0 R/WPD LED #5 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_5ManualActiveSelect : 1; /* 1E.C43D.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43D.1 R/WPD LED #5 Active High Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #5 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_5ActiveHighSelect : 1; /* 1E.C43D.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43D.2 R/WPD LED #5 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_5DriveThreeStateSelect : 1; /* 1E.C43D.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_13; + uint16_t word_13; + } u13; +} AQ_GlobalLedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C440.0 RO Gang Load MDIO Write Only + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioWriteOnly + + + + 1 = MDIO gang load enable + + + Notes: + This bit enables gang load operation with the address specified in Bits 8:4. */ + unsigned int gangLoadMdioWriteOnly : 1; /* 1E.C440.0 RO */ + /* 1 = MDIO gang load enable + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C440.8:4 R/WPD Gang Load MDIO Address [4:0] + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioAddress + + Provisionable Default = 0x00 + + MDIO Address to be used during gang load operation + + + Notes: + Gang load operation is used to load data into multiple PHYs all connected to the same MDIO bus. The address for gang load operation is provided by these bits (8:4), and enabling is done by writing Bit 0. Disabling of gang load mode is done by writing the See MDIO Address Reset (1E.C441.2) bit. These will revert the PHY's MDIO address back to the address provided by the MDIO Address pins. During gang load operation, MDIO reads are disabled to prevent bus contention. */ + unsigned int gangLoadMdioAddress : 5; /* 1E.C440.8:4 R/WPD Provisionable Default = 0x00 */ + /* MDIO Address to be used during gang load operation + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved2 : 2; + /*! \brief 1E.C441.2 R/WSC MDIO Address Reset + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioAddressReset + + Default = 0x0 + + 1 = Load MDIO Address with the address on the MDIO address pins + + + Notes: + Used to reset the address after gang load and enable MDIO reads again. */ + unsigned int mdioAddressReset : 1; /* 1E.C441.2 R/WSC Default = 0x0 */ + /* 1 = Load MDIO Address with the address on the MDIO address pins + */ + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + + + Notes: + When set, this bit enables gang-load operation on address zero, simultaneous with normal MDIO operation. Obviously, this requires that no PHY use address 0 as its normal operating address. As well, reads on MDIO Address 0 are disabled to prevent bus contention. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_APPIA.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted adn the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + unsigned int reserved0 : 15; + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalGeneralProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes. + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes. + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes. + + + Notes: + This sets the length of the dummy field used in some maunfacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes. + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved0 : 5; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + + + Notes: + When the this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + */ + unsigned int reserved0 : 7; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the dasiy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the flash. This bit will override the clock divide configuration from the flash with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + + */ + unsigned int reserved0 : 14; + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalNvrProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved2 : 4; + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + /*! \brief 1E.C470.5 R/WSC Initiate Component Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateComponentDiagnostics + + Default = 0x0 + + 1 = Perform component diagnostics + + + Notes: + Perform component diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the component diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateComponentDiagnostics : 1; /* 1E.C470.5 R/WSC Default = 0x0 */ + /* 1 = Perform component diagnostics + */ + unsigned int reserved1 : 2; + unsigned int reserved0 : 5; + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + /*! \brief 1E.C471.F:7 R/WPD Reserved Provisioning 2 [8:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.reservedProvisioning_2 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_2 : 9; /* 1E.C471.F:7 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + unsigned int reserved1 : 4; + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + /*! \brief 1E.C472.7 R/WPD Tunable External LVDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalLvddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalLvddPowerSupplyPresent : 1; /* 1E.C472.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + */ + unsigned int reserved0 : 6; + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + /*! \brief 1E.C472.F R/WPD Enable LVDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableLvddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableLvddPowerSupplyTuning : 1; /* 1E.C472.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C474.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_APPIA.u4.bits_4.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. + */ + unsigned int trainingSNR : 8; /* 1E.C474.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + unsigned int reserved0 : 8; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved1 : 2; + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + unsigned int reserved0 : 2; + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalReservedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairDStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair D, of running either cable diagnostics or component diagnostics. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairCStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair C, of running either cable diagnostics or component diagnostics. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairBStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair B, of running either cable diagnostics or component diagnostics. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairAStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair A, of running either cable diagnostics or component diagnostics. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u6.bits_6.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C808.F:0 RO Reserved 2[F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u8.bits_8.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 16; /* 1E.C808.F:0 RO */ + /* Reserved for future use + */ + } bits_8; + uint16_t word_8; + } u8; +} AQ_GlobalCableDiagnosticStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_APPIA.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_APPIA.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_APPIA.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autoneg, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_APPIA.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved2 : 1; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_APPIA.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C840.E:D RO MDIO Boot Load [1:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.mdioBootLoad + + + + Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + + + Notes: + NOTES: + + PHY #0 is the primary PHY, and PHY #1 is the secondary PHY + + PHY #1 is always in Slave Daisy Chain Boot from Flash when set to 0x2 or 0x3. */ + unsigned int mdioBootLoad : 2; /* 1E.C840.E:D RO */ + /* Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_APPIA.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_APPIA.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different Tensilica core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8004: Failed to set operating voltages via PMBus. This only occurs when the processor has control over power supply voltage via an attached PMBus device and there is a protocol error on the I2C bus: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Primary Status: 1E.C851 */ +/* Global Primary Status: 1E.C851 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Primary Status */ + union + { + struct + { + /*! \brief 1E.C851.0 RO Primary Status + AQ_GlobalPrimaryStatus_APPIA.u0.bits_0.primaryStatus + + + + 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + + */ + unsigned int primaryStatus : 1; /* 1E.C851.0 RO */ + /* 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPrimaryStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_4 + + + + Reserved for future use + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_3 + + + + Reserved for future use + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_8 + + + + Reserved for future use + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_7 + + + + Reserved for future use + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_6 + + + + Reserved for future use + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_5 + + + + Reserved for future use + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved for future use + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_12 + + + + Reserved for future use + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_11 + + + + Reserved for future use + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_10 + + + + Reserved for future use + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_9 + + + + Reserved for future use + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved for future use + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_16 + + + + Reserved for future use + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_15 + + + + Reserved for future use + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_14 + + + + Reserved for future use + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_13 + + + + Reserved for future use + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved for future use + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.reservedStatus_0 + + + + Reserved for future use + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.7:0 ROSPD ROM Revision [7:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.romRevision + + Provisionable Default = 0x00 + + ROM Revision Number + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int romRevision : 8; /* 1E.C885.7:0 ROSPD Provisionable Default = 0x00 */ + /* ROM Revision Number + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW[F:0] + AQ_GlobalReservedStatus_APPIA.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalReservedStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_APPIA.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_APPIA.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC01.0 LH Diagnostic Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.diagnosticAlarm + + + + 1 = Alarm triggered by a write to 1E.C470.7 + + + Notes: + A diagnostic alarm use to test system alarm circuitry */ + unsigned int diagnosticAlarm : 1; /* 1E.CC01.0 LH */ + /* 1 = Alarm triggered by a write to 1E.C470.7 + */ + unsigned int reserved1 : 6; + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_APPIA.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + /*! \brief 1E.CC01.C:8 LH Reserved Alarms [4:0] + AQ_GlobalAlarms_APPIA.u1.bits_1.reservedAlarms + + + + Reserved for future use + + */ + unsigned int reservedAlarms : 5; /* 1E.CC01.C:8 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + + Notes: + This alarm is performed by H/W. */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_APPIA.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_APPIA.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_APPIA.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_APPIA.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_APPIA.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.C:8 R/WPD Reserved Alarms Mask [4:0] + AQ_GlobalInterruptMask_APPIA.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x00 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 5; /* 1E.D401.C:8 R/WPD Provisionable Default = 0x00 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_APPIA; + +#endif +/*@}*/ +/*@}*/ diff --git a/firmware/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h b/firmware/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h new file mode 100755 index 0000000..9c7bb5c --- /dev/null +++ b/firmware/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h @@ -0,0 +1,2134 @@ +/*! \file +* This file contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ + +/*! \defgroup Global_registers_Defines Global Registers Defines +* This module contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/regMapParser/src/gencheaders.py $ +* +* $Revision: #10 $ +* +* $DateTime: 2014/04/08 16:55:58 $ +* +* $Author: joshd $ +* +* $Label: $ +* +* Description: +* +* This file contains the compiler assist macros for the registers contained in the Global Registers block. +* +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_APPIA_GLOBAL_REGS_DEFINES_HEADER +#define AQ_APPIA_GLOBAL_REGS_DEFINES_HEADER + + +/*-----------------------------------------------------------------------------*/ +/*Access macro definitions */ +/*-----------------------------------------------------------------------------*/ +/*! \brief Base register address of structure AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_baseRegisterAddress 0x0000 +/*! \brief MMD address of structure AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure softReset in AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_softReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure softReset in AQ_GlobalStandardControl_1_APPIA */ +#define bits_AQ_GlobalStandardControl_1_APPIA_softReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure softReset in AQ_GlobalStandardControl_1_APPIA */ +#define word_AQ_GlobalStandardControl_1_APPIA_softReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_hardReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ +#define bits_AQ_GlobalStandardControl_1_APPIA_hardReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ +#define word_AQ_GlobalStandardControl_1_APPIA_hardReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_lowPower 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ +#define bits_AQ_GlobalStandardControl_1_APPIA_lowPower u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ +#define word_AQ_GlobalStandardControl_1_APPIA_lowPower u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_baseRegisterAddress 0x0002 +/*! \brief MMD address of structure AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define bits_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define word_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define bits_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define word_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_baseRegisterAddress 0x0005 +/*! \brief MMD address of structure AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_baseRegisterAddress 0x0006 +/*! \brief MMD address of structure AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardStatus_2_APPIA */ +#define AQ_GlobalStandardStatus_2_APPIA_baseRegisterAddress 0x0008 +/*! \brief MMD address of structure AQ_GlobalStandardStatus_2_APPIA */ +#define AQ_GlobalStandardStatus_2_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ +#define AQ_GlobalStandardStatus_2_APPIA_devicePresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ +#define bits_AQ_GlobalStandardStatus_2_APPIA_devicePresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ +#define word_AQ_GlobalStandardStatus_2_APPIA_devicePresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_baseRegisterAddress 0x000E +/*! \brief MMD address of structure AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define bits_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define word_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define bits_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define word_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_baseRegisterAddress 0x0020 +/*! \brief MMD address of structure AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define bits_AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define word_AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define bits_AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define word_AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChipIdentification_APPIA */ +#define AQ_GlobalChipIdentification_APPIA_baseRegisterAddress 0x0021 +/*! \brief MMD address of structure AQ_GlobalChipIdentification_APPIA */ +#define AQ_GlobalChipIdentification_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ +#define AQ_GlobalChipIdentification_APPIA_chipIdentification 0 +/*! \brief Preprocessor variable to relate field to bit position in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ +#define bits_AQ_GlobalChipIdentification_APPIA_chipIdentification u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ +#define word_AQ_GlobalChipIdentification_APPIA_chipIdentification u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChipRevision_APPIA */ +#define AQ_GlobalChipRevision_APPIA_baseRegisterAddress 0x0022 +/*! \brief MMD address of structure AQ_GlobalChipRevision_APPIA */ +#define AQ_GlobalChipRevision_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure chipRevision in AQ_GlobalChipRevision_APPIA */ +#define AQ_GlobalChipRevision_APPIA_chipRevision 0 +/*! \brief Preprocessor variable to relate field to bit position in structure chipRevision in AQ_GlobalChipRevision_APPIA */ +#define bits_AQ_GlobalChipRevision_APPIA_chipRevision u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure chipRevision in AQ_GlobalChipRevision_APPIA */ +#define word_AQ_GlobalChipRevision_APPIA_chipRevision u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_baseRegisterAddress 0x0100 +/*! \brief MMD address of structure AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_freezeNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_freezeNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_freezeNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_resetNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_resetNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_resetNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrBurst 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrBurst u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrBurst u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrOpcode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrOpcode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrOpcode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrDataLSW u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_baseRegisterAddress 0x0200 +/*! \brief MMD address of structure AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_baseRegisterAddress 0x0300 +/*! \brief MMD address of structure AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define bits_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define word_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define bits_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define word_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_baseRegisterAddress 0xC000 +/*! \brief MMD address of structure AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upReset in AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_upReset 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upReset in AQ_GlobalControl_APPIA */ +#define bits_AQ_GlobalControl_APPIA_upReset u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upReset in AQ_GlobalControl_APPIA */ +#define word_AQ_GlobalControl_APPIA_upReset u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStallOverride in AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_upRunStallOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStallOverride in AQ_GlobalControl_APPIA */ +#define bits_AQ_GlobalControl_APPIA_upRunStallOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStallOverride in AQ_GlobalControl_APPIA */ +#define word_AQ_GlobalControl_APPIA_upRunStallOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStall in AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_upRunStall 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStall in AQ_GlobalControl_APPIA */ +#define bits_AQ_GlobalControl_APPIA_upRunStall u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStall in AQ_GlobalControl_APPIA */ +#define word_AQ_GlobalControl_APPIA_upRunStall u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalResetControl_APPIA */ +#define AQ_GlobalResetControl_APPIA_baseRegisterAddress 0xC006 +/*! \brief MMD address of structure AQ_GlobalResetControl_APPIA */ +#define AQ_GlobalResetControl_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ +#define AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ +#define bits_AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ +#define word_AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDiagnosticProvisioning_APPIA */ +#define AQ_GlobalDiagnosticProvisioning_APPIA_baseRegisterAddress 0xC400 +/*! \brief MMD address of structure AQ_GlobalDiagnosticProvisioning_APPIA */ +#define AQ_GlobalDiagnosticProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ +#define AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ +#define bits_AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ +#define word_AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_baseRegisterAddress 0xC420 +/*! \brief MMD address of structure AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_reserved_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_reserved_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_reserved_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold u4.word_4 + +/*! \brief Base register address of structure AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_baseRegisterAddress 0xC430 +/*! \brief MMD address of structure AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ManualSet 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ManualSet u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ManualSet u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0Connecting 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0Connecting u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0Connecting u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ManualSet 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ManualSet u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ManualSet u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1Connecting 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1Connecting u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1Connecting u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ManualSet 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ManualSet u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ManualSet u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2Connecting 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2Connecting u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2Connecting u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ManualSet 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ManualSet u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ManualSet u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3Connecting 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3Connecting u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3Connecting u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ManualSet 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ManualSet u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ManualSet u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4Connecting 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4Connecting u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4Connecting u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ManualSet 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ManualSet u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ManualSet u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5Connecting 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5Connecting u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5Connecting u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_ledOperationMode 7 +/*! \brief Preprocessor variable to relate field to bit position in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_ledOperationMode u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_ledOperationMode u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect 8 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect 8 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect 8 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect 9 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect 9 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect 9 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect 10 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect 10 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect 10 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect 11 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect 11 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect 11 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect 12 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect 12 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect 12 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect 13 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect 13 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect 13 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect u13.word_13 + +/*! \brief Base register address of structure AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_baseRegisterAddress 0xC440 +/*! \brief MMD address of structure AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset 2 +/*! \brief Preprocessor variable to relate field to bit position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_baseRegisterAddress 0xC450 +/*! \brief MMD address of structure AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDataLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDataLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDataLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_baseRegisterAddress 0xC470 +/*! \brief MMD address of structure AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue 1 +/*! \brief Preprocessor variable to relate field to bit position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent 2 +/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent 2 +/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_trainingSNR 4 +/*! \brief Preprocessor variable to relate field to bit position in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_trainingSNR u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_trainingSNR u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 5 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_baseRegisterAddress 0xC800 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 6 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 8 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 u8.word_8 + +/*! \brief Base register address of structure AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_baseRegisterAddress 0xC820 +/*! \brief MMD address of structure AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure temperature in AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_temperature 0 +/*! \brief Preprocessor variable to relate field to bit position in structure temperature in AQ_GlobalThermalStatus_APPIA */ +#define bits_AQ_GlobalThermalStatus_APPIA_temperature u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure temperature in AQ_GlobalThermalStatus_APPIA */ +#define word_AQ_GlobalThermalStatus_APPIA_temperature u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_temperatureReady 1 +/*! \brief Preprocessor variable to relate field to bit position in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ +#define bits_AQ_GlobalThermalStatus_APPIA_temperatureReady u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ +#define word_AQ_GlobalThermalStatus_APPIA_temperatureReady u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_baseRegisterAddress 0xC830 +/*! \brief MMD address of structure AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress 1 +/*! \brief Preprocessor variable to relate field to bit position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_baseRegisterAddress 0xC840 +/*! \brief MMD address of structure AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_mdioBootLoad 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_mdioBootLoad u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_mdioBootLoad u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_packageConnectivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_packageConnectivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_packageConnectivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure txEnable in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_txEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnable in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_txEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure txEnable in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_txEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_ledPullupState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_ledPullupState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_ledPullupState u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDaisyChainStatus_APPIA */ +#define AQ_GlobalDaisyChainStatus_APPIA_baseRegisterAddress 0xC842 +/*! \brief MMD address of structure AQ_GlobalDaisyChainStatus_APPIA */ +#define AQ_GlobalDaisyChainStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ +#define AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ +#define bits_AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ +#define word_AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalFaultMessage_APPIA */ +#define AQ_GlobalFaultMessage_APPIA_baseRegisterAddress 0xC850 +/*! \brief MMD address of structure AQ_GlobalFaultMessage_APPIA */ +#define AQ_GlobalFaultMessage_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure message in AQ_GlobalFaultMessage_APPIA */ +#define AQ_GlobalFaultMessage_APPIA_message 0 +/*! \brief Preprocessor variable to relate field to bit position in structure message in AQ_GlobalFaultMessage_APPIA */ +#define bits_AQ_GlobalFaultMessage_APPIA_message u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure message in AQ_GlobalFaultMessage_APPIA */ +#define word_AQ_GlobalFaultMessage_APPIA_message u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalPrimaryStatus_APPIA */ +#define AQ_GlobalPrimaryStatus_APPIA_baseRegisterAddress 0xC851 +/*! \brief MMD address of structure AQ_GlobalPrimaryStatus_APPIA */ +#define AQ_GlobalPrimaryStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ +#define AQ_GlobalPrimaryStatus_APPIA_primaryStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ +#define bits_AQ_GlobalPrimaryStatus_APPIA_primaryStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ +#define word_AQ_GlobalPrimaryStatus_APPIA_primaryStatus u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_baseRegisterAddress 0xC880 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_baseRegisterAddress 0xC884 +/*! \brief MMD address of structure AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_reservedStatus_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ +#define bits_AQ_GlobalStatus_APPIA_reservedStatus_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ +#define word_AQ_GlobalStatus_APPIA_reservedStatus_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure cableLength in AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_cableLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure cableLength in AQ_GlobalStatus_APPIA */ +#define bits_AQ_GlobalStatus_APPIA_cableLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure cableLength in AQ_GlobalStatus_APPIA */ +#define word_AQ_GlobalStatus_APPIA_cableLength u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_baseRegisterAddress 0xC885 +/*! \brief MMD address of structure AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure romRevision in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_romRevision 0 +/*! \brief Preprocessor variable to relate field to bit position in structure romRevision in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_romRevision u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure romRevision in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_romRevision u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_baseRegisterAddress 0xCC00 +/*! \brief MMD address of structure AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_highTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_highTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_highTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_lowTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_lowTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_lowTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_highTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_highTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_highTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_lowTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_lowTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_lowTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompleted in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_resetCompleted 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompleted in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_resetCompleted u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompleted in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_resetCompleted u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFault in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_deviceFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFault in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_deviceFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFault in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_deviceFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmA 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmA u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmA u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmB 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmB u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmB u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmC 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmC u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmC u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmD 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmD u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmD u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_smartPower_downEntered 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_smartPower_downEntered u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_smartPower_downEntered u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_xenpakAlarm 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_xenpakAlarm u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_xenpakAlarm u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarms 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarms u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarms u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_diagnosticAlarm 1 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_diagnosticAlarm u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_diagnosticAlarm u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_nvrOperationComplete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_nvrOperationComplete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_nvrOperationComplete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mailboxOperation_Complete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mailboxOperation_Complete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mailboxOperation_Complete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityError in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_upDramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityError in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_upDramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityError in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_upDramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityError in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_upIramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityError in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_upIramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityError in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_upIramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_txEnableStateChange 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_txEnableStateChange u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_txEnableStateChange u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mdioMMD_Error 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mdioMMD_Error u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mdioMMD_Error u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mdioTimeoutError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mdioTimeoutError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mdioTimeoutError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_watchdogTimerAlarm 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_watchdogTimerAlarm u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_watchdogTimerAlarm u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_baseRegisterAddress 0xD400 +/*! \brief MMD address of structure AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_resetCompletedMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_resetCompletedMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_resetCompletedMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_deviceFaultMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_deviceFaultMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_deviceFaultMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_baseRegisterAddress 0xFC00 +/*! \brief MMD address of structure AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_baseRegisterAddress 0xFC01 +/*! \brief MMD address of structure AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_baseRegisterAddress 0xFF00 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_baseRegisterAddress 0xFF01 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask u0.word_0 +#endif +/*@}*/ +/*@}*/ diff --git a/firmware/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h b/firmware/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h new file mode 100755 index 0000000..89e02c3 --- /dev/null +++ b/firmware/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h @@ -0,0 +1,5581 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from MSbit to LSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_APPIA_GLOBAL_REGS_HEADER +#define AQ_APPIA_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global soft reset on all of the digital logic, including the microprocessor. Upon completion of the reset sequence, this bit is set back to 0. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + /*! \brief 1E.0000.E R/WSC Hard Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.hardReset + + Default = 0x0 + + 1 = Global hard reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global hard reset, equivalent to pulling the reset pin low. This is a level sensitive pin that connects into the power-on reset generation circuitry to initiate a complete power-on reset. */ + unsigned int hardReset : 1; /* 1E.0000.E R/WSC Default = 0x0 */ + /* 1 = Global hard reset + 0 = Normal operation + */ + unsigned int reserved0 : 2; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_APPIA.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_APPIA.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + unsigned int reserved0 : 13; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_APPIA.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_APPIA.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_APPIA.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Identification: 1E.0021 */ +/* Global Chip Identification: 1E.0021 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Identification */ + union + { + struct + { + /*! \brief 1E.0021.F:0 RO Chip Identification [F:0] + AQ_GlobalChipIdentification_APPIA.u0.bits_0.chipIdentification + + + + Hardware Chip ID + + Notes: + This value is a hard-coded chip ID */ + unsigned int chipIdentification : 16; /* 1E.0021.F:0 RO */ + /* Hardware Chip ID */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipIdentification_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Revision: 1E.0022 */ +/* Global Chip Revision: 1E.0022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Revision */ + union + { + struct + { + /*! \brief 1E.0022.F:0 RO Chip Revision [F:0] + AQ_GlobalChipRevision_APPIA.u0.bits_0.chipRevision + + + + Hardware Chip Revision + + Notes: + This value is a hard-coded chip revision */ + unsigned int chipRevision : 16; /* 1E.0022.F:0 RO */ + /* Hardware Chip Revision */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipRevision_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_APPIA.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_APPIA.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_APPIA.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + */ + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occured and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved2 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_APPIA.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_APPIA.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalMailboxInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad1 + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad1 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch P + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch P */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_APPIA.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_APPIA.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_APPIA.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. The PIF slave bus for inbound requests will still be active. This bit is muliplexed with the "MDIO Boot Load" pin with the See uP Run Stall Override bit as the select. When the "MDIO Boot Load" pin is asserted, the uP will be in Run Stall mode after reset. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_APPIA.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved1 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_APPIA.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_APPIA.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C433.8 R/WPD LED #3 Manual Set + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_3ManualSet : 1; /* 1E.C433.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C433.7 R/WPD LED #3 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_3_10Gb_sLinkEstablished : 1; /* 1E.C433.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C433.6 R/WPD LED #3 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_3_1Gb_sLinkEstablished : 1; /* 1E.C433.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C433.5 R/WPD LED #3 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_3_100Mb_sLinkEstablished : 1; /* 1E.C433.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C433.4 R/WPD LED #3 Connecting + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_3Connecting : 1; /* 1E.C433.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C433.3 R/WPD LED #3 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_3ReceiveActivity : 1; /* 1E.C433.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C433.2 R/WPD LED #3 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_3TransmitActivity : 1; /* 1E.C433.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C433.1:0 R/WPD LED #3 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_3ActivityStretch : 2; /* 1E.C433.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C434.8 R/WPD LED #4 Manual Set + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_4ManualSet : 1; /* 1E.C434.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C434.7 R/WPD LED #4 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_4_10Gb_sLinkEstablished : 1; /* 1E.C434.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C434.6 R/WPD LED #4 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_4_1Gb_sLinkEstablished : 1; /* 1E.C434.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C434.5 R/WPD LED #4 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_4_100Mb_sLinkEstablished : 1; /* 1E.C434.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C434.4 R/WPD LED #4 Connecting + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_4Connecting : 1; /* 1E.C434.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C434.3 R/WPD LED #4 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_4ReceiveActivity : 1; /* 1E.C434.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C434.2 R/WPD LED #4 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_4TransmitActivity : 1; /* 1E.C434.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C434.1:0 R/WPD LED #4 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_4ActivityStretch : 2; /* 1E.C434.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C435.8 R/WPD LED #5 Manual Set + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_5ManualSet : 1; /* 1E.C435.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C435.7 R/WPD LED #5 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_5_10Gb_sLinkEstablished : 1; /* 1E.C435.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C435.6 R/WPD LED #5 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_5_1Gb_sLinkEstablished : 1; /* 1E.C435.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C435.5 R/WPD LED #5 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_5_100Mb_sLinkEstablished : 1; /* 1E.C435.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C435.4 R/WPD LED #5 Connecting + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_5Connecting : 1; /* 1E.C435.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C435.3 R/WPD LED #5 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_5ReceiveActivity : 1; /* 1E.C435.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C435.2 R/WPD LED #5 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_5TransmitActivity : 1; /* 1E.C435.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C435.1:0 R/WPD LED #5 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_5ActivityStretch : 2; /* 1E.C435.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_APPIA.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C438.2 R/WPD LED #0 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_0DriveThreeStateSelect : 1; /* 1E.C438.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C438.1 R/WPD LED #0 Active High Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #0 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_0ActiveHighSelect : 1; /* 1E.C438.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C438.0 R/WPD LED #0 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_0ManualActiveSelect : 1; /* 1E.C438.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C439.2 R/WPD LED #1 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_1DriveThreeStateSelect : 1; /* 1E.C439.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C439.1 R/WPD LED #1 Active High Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #1 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_1ActiveHighSelect : 1; /* 1E.C439.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C439.0 R/WPD LED #1 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_1ManualActiveSelect : 1; /* 1E.C439.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43A.2 R/WPD LED #2 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_2DriveThreeStateSelect : 1; /* 1E.C43A.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43A.1 R/WPD LED #2 Active High Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #2 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_2ActiveHighSelect : 1; /* 1E.C43A.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43A.0 R/WPD LED #2 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_2ManualActiveSelect : 1; /* 1E.C43A.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43B.2 R/WPD LED #3 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_3DriveThreeStateSelect : 1; /* 1E.C43B.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43B.1 R/WPD LED #3 Active High Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #3 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_3ActiveHighSelect : 1; /* 1E.C43B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43B.0 R/WPD LED #3 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_3ManualActiveSelect : 1; /* 1E.C43B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43C.2 R/WPD LED #4 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_4DriveThreeStateSelect : 1; /* 1E.C43C.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43C.1 R/WPD LED #4 Active High Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #4 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_4ActiveHighSelect : 1; /* 1E.C43C.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43C.0 R/WPD LED #4 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_4ManualActiveSelect : 1; /* 1E.C43C.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43D.2 R/WPD LED #5 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_5DriveThreeStateSelect : 1; /* 1E.C43D.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43D.1 R/WPD LED #5 Active High Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #5 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_5ActiveHighSelect : 1; /* 1E.C43D.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43D.0 R/WPD LED #5 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_5ManualActiveSelect : 1; /* 1E.C43D.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_13; + uint16_t word_13; + } u13; +} AQ_GlobalLedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C440.8:4 R/WPD Gang Load MDIO Address [4:0] + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioAddress + + Provisionable Default = 0x00 + + MDIO Address to be used during gang load operation + + + Notes: + Gang load operation is used to load data into multiple PHYs all connected to the same MDIO bus. The address for gang load operation is provided by these bits (8:4), and enabling is done by writing Bit 0. Disabling of gang load mode is done by writing the See MDIO Address Reset (1E.C441.2) bit. These will revert the PHY's MDIO address back to the address provided by the MDIO Address pins. During gang load operation, MDIO reads are disabled to prevent bus contention. */ + unsigned int gangLoadMdioAddress : 5; /* 1E.C440.8:4 R/WPD Provisionable Default = 0x00 */ + /* MDIO Address to be used during gang load operation + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C440.0 RO Gang Load MDIO Write Only + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioWriteOnly + + + + 1 = MDIO gang load enable + + + Notes: + This bit enables gang load operation with the address specified in Bits 8:4. */ + unsigned int gangLoadMdioWriteOnly : 1; /* 1E.C440.0 RO */ + /* 1 = MDIO gang load enable + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + + + Notes: + When set, this bit enables gang-load operation on address zero, simultaneous with normal MDIO operation. Obviously, this requires that no PHY use address 0 as its normal operating address. As well, reads on MDIO Address 0 are disabled to prevent bus contention. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + */ + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + /*! \brief 1E.C441.2 R/WSC MDIO Address Reset + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioAddressReset + + Default = 0x0 + + 1 = Load MDIO Address with the address on the MDIO address pins + + + Notes: + Used to reset the address after gang load and enable MDIO reads again. */ + unsigned int mdioAddressReset : 1; /* 1E.C441.2 R/WSC Default = 0x0 */ + /* 1 = Load MDIO Address with the address on the MDIO address pins + */ + unsigned int reserved2 : 2; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_APPIA.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted adn the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalGeneralProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 5; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes. + + + Notes: + This sets the length of the dummy field used in some maunfacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes. + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes. + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + + + Notes: + When the this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + */ + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the flash. This bit will override the clock divide configuration from the flash with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + + */ + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the dasiy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalNvrProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + unsigned int reserved0 : 5; + unsigned int reserved1 : 2; + /*! \brief 1E.C470.5 R/WSC Initiate Component Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateComponentDiagnostics + + Default = 0x0 + + 1 = Perform component diagnostics + + + Notes: + Perform component diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the component diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateComponentDiagnostics : 1; /* 1E.C470.5 R/WSC Default = 0x0 */ + /* 1 = Perform component diagnostics + */ + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + unsigned int reserved2 : 4; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C471.F:7 R/WPD Reserved Provisioning 2 [8:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.reservedProvisioning_2 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_2 : 9; /* 1E.C471.F:7 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C472.F R/WPD Enable LVDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableLvddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableLvddPowerSupplyTuning : 1; /* 1E.C472.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + */ + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + unsigned int reserved0 : 6; + /*! \brief 1E.C472.7 R/WPD Tunable External LVDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalLvddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalLvddPowerSupplyPresent : 1; /* 1E.C472.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + */ + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + unsigned int reserved1 : 4; + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.C474.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_APPIA.u4.bits_4.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. + */ + unsigned int trainingSNR : 8; /* 1E.C474.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + unsigned int reserved1 : 2; + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalReservedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairAStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair A, of running either cable diagnostics or component diagnostics. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairBStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair B, of running either cable diagnostics or component diagnostics. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairCStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair C, of running either cable diagnostics or component diagnostics. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairDStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair D, of running either cable diagnostics or component diagnostics. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u6.bits_6.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C808.F:0 RO Reserved 2[F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u8.bits_8.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 16; /* 1E.C808.F:0 RO */ + /* Reserved for future use + */ + } bits_8; + uint16_t word_8; + } u8; +} AQ_GlobalCableDiagnosticStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_APPIA.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_APPIA.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_APPIA.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autoneg, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C840.E:D RO MDIO Boot Load [1:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.mdioBootLoad + + + + Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + + + Notes: + NOTES: + + PHY #0 is the primary PHY, and PHY #1 is the secondary PHY + + PHY #1 is always in Slave Daisy Chain Boot from Flash when set to 0x2 or 0x3. */ + unsigned int mdioBootLoad : 2; /* 1E.C840.E:D RO */ + /* Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_APPIA.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved2 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_APPIA.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_APPIA.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_APPIA.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different Tensilica core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8004: Failed to set operating voltages via PMBus. This only occurs when the processor has control over power supply voltage via an attached PMBus device and there is a protocol error on the I2C bus: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Primary Status: 1E.C851 */ +/* Global Primary Status: 1E.C851 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Primary Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C851.0 RO Primary Status + AQ_GlobalPrimaryStatus_APPIA.u0.bits_0.primaryStatus + + + + 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + + */ + unsigned int primaryStatus : 1; /* 1E.C851.0 RO */ + /* 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPrimaryStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_3 + + + + Reserved for future use + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_4 + + + + Reserved for future use + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_5 + + + + Reserved for future use + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_6 + + + + Reserved for future use + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_7 + + + + Reserved for future use + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_8 + + + + Reserved for future use + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_9 + + + + Reserved for future use + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_10 + + + + Reserved for future use + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_11 + + + + Reserved for future use + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_12 + + + + Reserved for future use + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_13 + + + + Reserved for future use + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_14 + + + + Reserved for future use + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_15 + + + + Reserved for future use + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_16 + + + + Reserved for future use + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.reservedStatus_0 + + + + Reserved for future use + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.7:0 ROSPD ROM Revision [7:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.romRevision + + Provisionable Default = 0x00 + + ROM Revision Number + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int romRevision : 8; /* 1E.C885.7:0 ROSPD Provisionable Default = 0x00 */ + /* ROM Revision Number + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW[F:0] + AQ_GlobalReservedStatus_APPIA.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalReservedStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_APPIA.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_APPIA.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_APPIA.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + + Notes: + This alarm is performed by H/W. */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.C:8 LH Reserved Alarms [4:0] + AQ_GlobalAlarms_APPIA.u1.bits_1.reservedAlarms + + + + Reserved for future use + + */ + unsigned int reservedAlarms : 5; /* 1E.CC01.C:8 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_APPIA.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + unsigned int reserved1 : 6; + /*! \brief 1E.CC01.0 LH Diagnostic Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.diagnosticAlarm + + + + 1 = Alarm triggered by a write to 1E.C470.7 + + + Notes: + A diagnostic alarm use to test system alarm circuitry */ + unsigned int diagnosticAlarm : 1; /* 1E.CC01.0 LH */ + /* 1 = Alarm triggered by a write to 1E.C470.7 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_APPIA.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_APPIA.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_APPIA.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_APPIA.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.C:8 R/WPD Reserved Alarms Mask [4:0] + AQ_GlobalInterruptMask_APPIA.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x00 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 5; /* 1E.D401.C:8 R/WPD Provisionable Default = 0x00 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_APPIA; + +#endif +/*@}*/ +/*@}*/ diff --git a/firmware/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h b/firmware/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h new file mode 100755 index 0000000..08e2558 --- /dev/null +++ b/firmware/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h @@ -0,0 +1,387 @@ +/* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ +#ifndef AQ_REG_GROUP_MAX_SIZES +#define AQ_REG_GROUP_MAX_SIZES + +#define AQ_Autonegotiation10GBaseT_ControlRegister_BiggestVersion AQ_Autonegotiation10GBaseT_ControlRegister_HHD +#define AQ_Autonegotiation10GBaseT_StatusRegister_BiggestVersion AQ_Autonegotiation10GBaseT_StatusRegister_HHD +#define AQ_AutonegotiationAdvertisementRegister_BiggestVersion AQ_AutonegotiationAdvertisementRegister_HHD +#define AQ_AutonegotiationEeeAdvertisementRegister_BiggestVersion AQ_AutonegotiationEeeAdvertisementRegister_HHD +#define AQ_AutonegotiationEeeLinkPartnerAbilityRegister_BiggestVersion AQ_AutonegotiationEeeLinkPartnerAbilityRegister_HHD +#define AQ_AutonegotiationExtendedNextPageTransmitRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageTransmitRegister_HHD +#define AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_HHD +#define AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_HHD +#define AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_HHD +#define AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_HHD +#define AQ_AutonegotiationReceiveLinkPartnerStatus_BiggestVersion AQ_AutonegotiationReceiveLinkPartnerStatus_HHD +#define AQ_AutonegotiationReceiveReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReceiveReservedVendorProvisioning_APPIA +#define AQ_AutonegotiationReceiveReservedVendorStatus_BiggestVersion AQ_AutonegotiationReceiveReservedVendorStatus_HHD +#define AQ_AutonegotiationReceiveVendorAlarms_BiggestVersion AQ_AutonegotiationReceiveVendorAlarms_HHD +#define AQ_AutonegotiationReceiveVendorInterruptMask_BiggestVersion AQ_AutonegotiationReceiveVendorInterruptMask_HHD +#define AQ_AutonegotiationReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReservedVendorProvisioning_HHD +#define AQ_AutonegotiationReservedVendorStatus_BiggestVersion AQ_AutonegotiationReservedVendorStatus_HHD +#define AQ_AutonegotiationStandardControl_1_BiggestVersion AQ_AutonegotiationStandardControl_1_HHD +#define AQ_AutonegotiationStandardDeviceIdentifier_BiggestVersion AQ_AutonegotiationStandardDeviceIdentifier_HHD +#define AQ_AutonegotiationStandardDevicesInPackage_BiggestVersion AQ_AutonegotiationStandardDevicesInPackage_HHD +#define AQ_AutonegotiationStandardInterruptMask_BiggestVersion AQ_AutonegotiationStandardInterruptMask_HHD +#define AQ_AutonegotiationStandardPackageIdentifier_BiggestVersion AQ_AutonegotiationStandardPackageIdentifier_HHD +#define AQ_AutonegotiationStandardStatus_1_BiggestVersion AQ_AutonegotiationStandardStatus_1_HHD +#define AQ_AutonegotiationStandardStatus_2_BiggestVersion AQ_AutonegotiationStandardStatus_2_HHD +#define AQ_AutonegotiationTransmitVendorAlarms_BiggestVersion AQ_AutonegotiationTransmitVendorAlarms_APPIA +#define AQ_AutonegotiationTransmitVendorInterruptMask_BiggestVersion AQ_AutonegotiationTransmitVendorInterruptMask_HHD +#define AQ_AutonegotiationVendorGlobalInterruptFlags_BiggestVersion AQ_AutonegotiationVendorGlobalInterruptFlags_HHD +#define AQ_AutonegotiationVendorProvisioning_BiggestVersion AQ_AutonegotiationVendorProvisioning_HHD +#define AQ_AutonegotiationVendorStatus_BiggestVersion AQ_AutonegotiationVendorStatus_HHD +#define AQ_GbePhyExtendedWolControl_BiggestVersion AQ_GbePhyExtendedWolControl_HHD +#define AQ_GbePhySgmii0RxStatus_BiggestVersion AQ_GbePhySgmii0RxStatus_HHD +#define AQ_GbePhySgmii0TxStatus_BiggestVersion AQ_GbePhySgmii0TxStatus_HHD +#define AQ_GbePhySgmii1RxStatus_BiggestVersion AQ_GbePhySgmii1RxStatus_HHD +#define AQ_GbePhySgmii1TxStatus_BiggestVersion AQ_GbePhySgmii1TxStatus_HHD +#define AQ_GbePhySgmii1WolStatus_BiggestVersion AQ_GbePhySgmii1WolStatus_HHD +#define AQ_GbePhySgmiiRxAlarms_BiggestVersion AQ_GbePhySgmiiRxAlarms_HHD +#define AQ_GbePhySgmiiRxInterruptMask_BiggestVersion AQ_GbePhySgmiiRxInterruptMask_HHD +#define AQ_GbePhySgmiiTestControl_BiggestVersion AQ_GbePhySgmiiTestControl_HHD +#define AQ_GbePhySgmiiTxAlarms_BiggestVersion AQ_GbePhySgmiiTxAlarms_HHD +#define AQ_GbePhySgmiiTxInterruptMask_BiggestVersion AQ_GbePhySgmiiTxInterruptMask_HHD +#define AQ_GbePhySgmiiWolStatus_BiggestVersion AQ_GbePhySgmiiWolStatus_HHD +#define AQ_GbePhyVendorGlobalInterruptFlags_BiggestVersion AQ_GbePhyVendorGlobalInterruptFlags_HHD +#define AQ_GbePhyWolControl_BiggestVersion AQ_GbePhyWolControl_HHD +#define AQ_GbePhysgmii1WolStatus_BiggestVersion AQ_GbePhysgmii1WolStatus_APPIA +#define AQ_GbeReservedProvisioning_BiggestVersion AQ_GbeReservedProvisioning_HHD +#define AQ_GbeStandardDeviceIdentifier_BiggestVersion AQ_GbeStandardDeviceIdentifier_HHD +#define AQ_GbeStandardDevicesInPackage_BiggestVersion AQ_GbeStandardDevicesInPackage_HHD +#define AQ_GbeStandardPackageIdentifier_BiggestVersion AQ_GbeStandardPackageIdentifier_HHD +#define AQ_GbeStandardStatus_2_BiggestVersion AQ_GbeStandardStatus_2_HHD +#define AQ_GbeStandardVendorDevicesInPackage_BiggestVersion AQ_GbeStandardVendorDevicesInPackage_HHD +#define AQ_GlobalAlarms_BiggestVersion AQ_GlobalAlarms_HHD +#define AQ_GlobalCableDiagnosticImpedance_BiggestVersion AQ_GlobalCableDiagnosticImpedance_HHD +#define AQ_GlobalCableDiagnosticStatus_BiggestVersion AQ_GlobalCableDiagnosticStatus_APPIA +#define AQ_GlobalChipIdentification_BiggestVersion AQ_GlobalChipIdentification_APPIA +#define AQ_GlobalChipRevision_BiggestVersion AQ_GlobalChipRevision_APPIA +#define AQ_GlobalChip_wideStandardInterruptFlags_BiggestVersion AQ_GlobalChip_wideStandardInterruptFlags_HHD +#define AQ_GlobalChip_wideVendorInterruptFlags_BiggestVersion AQ_GlobalChip_wideVendorInterruptFlags_HHD +#define AQ_GlobalControl_BiggestVersion AQ_GlobalControl_HHD +#define AQ_GlobalDaisyChainStatus_BiggestVersion AQ_GlobalDaisyChainStatus_HHD +#define AQ_GlobalDiagnosticProvisioning_BiggestVersion AQ_GlobalDiagnosticProvisioning_HHD +#define AQ_GlobalEeeProvisioning_BiggestVersion AQ_GlobalEeeProvisioning_HHD +#define AQ_GlobalFaultMessage_BiggestVersion AQ_GlobalFaultMessage_HHD +#define AQ_GlobalFirmwareID_BiggestVersion AQ_GlobalFirmwareID_HHD +#define AQ_GlobalGeneralProvisioning_BiggestVersion AQ_GlobalGeneralProvisioning_HHD +#define AQ_GlobalGeneralStatus_BiggestVersion AQ_GlobalGeneralStatus_HHD +#define AQ_GlobalInterruptChip_wideStandardMask_BiggestVersion AQ_GlobalInterruptChip_wideStandardMask_HHD +#define AQ_GlobalInterruptChip_wideVendorMask_BiggestVersion AQ_GlobalInterruptChip_wideVendorMask_HHD +#define AQ_GlobalInterruptMask_BiggestVersion AQ_GlobalInterruptMask_HHD +#define AQ_GlobalLedProvisioning_BiggestVersion AQ_GlobalLedProvisioning_HHD +#define AQ_GlobalMailboxInterface_BiggestVersion AQ_GlobalMailboxInterface_HHD +#define AQ_GlobalMicroprocessorScratchPad_BiggestVersion AQ_GlobalMicroprocessorScratchPad_HHD +#define AQ_GlobalNvrInterface_BiggestVersion AQ_GlobalNvrInterface_HHD +#define AQ_GlobalNvrProvisioning_BiggestVersion AQ_GlobalNvrProvisioning_HHD +#define AQ_GlobalPinStatus_BiggestVersion AQ_GlobalPinStatus_HHD +#define AQ_GlobalPrimaryStatus_BiggestVersion AQ_GlobalPrimaryStatus_APPIA +#define AQ_GlobalReservedProvisioning_BiggestVersion AQ_GlobalReservedProvisioning_HHD +#define AQ_GlobalReservedStatus_BiggestVersion AQ_GlobalReservedStatus_HHD +#define AQ_GlobalResetControl_BiggestVersion AQ_GlobalResetControl_HHD +#define AQ_GlobalSmbus_0Provisioning_BiggestVersion AQ_GlobalSmbus_0Provisioning_HHD +#define AQ_GlobalSmbus_1Provisioning_BiggestVersion AQ_GlobalSmbus_1Provisioning_HHD +#define AQ_GlobalStandardControl_1_BiggestVersion AQ_GlobalStandardControl_1_HHD +#define AQ_GlobalStandardDeviceIdentifier_BiggestVersion AQ_GlobalStandardDeviceIdentifier_HHD +#define AQ_GlobalStandardDevicesInPackage_BiggestVersion AQ_GlobalStandardDevicesInPackage_HHD +#define AQ_GlobalStandardPackageIdentifier_BiggestVersion AQ_GlobalStandardPackageIdentifier_HHD +#define AQ_GlobalStandardStatus_2_BiggestVersion AQ_GlobalStandardStatus_2_HHD +#define AQ_GlobalStandardVendorDevicesInPackage_BiggestVersion AQ_GlobalStandardVendorDevicesInPackage_HHD +#define AQ_GlobalStatus_BiggestVersion AQ_GlobalStatus_HHD +#define AQ_GlobalThermalProvisioning_BiggestVersion AQ_GlobalThermalProvisioning_HHD +#define AQ_GlobalThermalStatus_BiggestVersion AQ_GlobalThermalStatus_HHD +#define AQ_Kr0AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationAdvertisementWord_HHD +#define AQ_Kr0AutonegotiationControl_BiggestVersion AQ_Kr0AutonegotiationControl_HHD +#define AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_Kr0AutonegotiationStatus_BiggestVersion AQ_Kr0AutonegotiationStatus_HHD +#define AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_HHD +#define AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_Kr1AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationAdvertisementWord_HHD +#define AQ_Kr1AutonegotiationControl_BiggestVersion AQ_Kr1AutonegotiationControl_HHD +#define AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_Kr1AutonegotiationStatus_BiggestVersion AQ_Kr1AutonegotiationStatus_HHD +#define AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_HHD +#define AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_MsmLineFifoControlRegister_BiggestVersion AQ_MsmLineFifoControlRegister_HHD +#define AQ_MsmLineGeneralControlRegister_BiggestVersion AQ_MsmLineGeneralControlRegister_HHD +#define AQ_MsmLineGeneralStatusRegister_BiggestVersion AQ_MsmLineGeneralStatusRegister_HHD +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD +#define AQ_MsmLineRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineRxBroadcastFramesCounterRegister_HHD +#define AQ_MsmLineRxErrorsCounterRegister_BiggestVersion AQ_MsmLineRxErrorsCounterRegister_HHD +#define AQ_MsmLineRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmLineRxFcsErrorsCounterRegister_HHD +#define AQ_MsmLineRxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineRxGoodFramesCounterRegister_HHD +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD +#define AQ_MsmLineRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineRxMulticastFramesCounterRegister_HHD +#define AQ_MsmLineRxOctetsCounterRegister_BiggestVersion AQ_MsmLineRxOctetsCounterRegister_HHD +#define AQ_MsmLineRxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineRxPauseFramesCounterRegister_HHD +#define AQ_MsmLineRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmLineRxTooLongErrorsCounterRegister_HHD +#define AQ_MsmLineRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineRxUnicastFramesCounterRegister_HHD +#define AQ_MsmLineRxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineRxVlanFramesCounterRegister_HHD +#define AQ_MsmLineTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineTxBroadcastFramesCounterRegister_HHD +#define AQ_MsmLineTxErrorsCounterRegister_BiggestVersion AQ_MsmLineTxErrorsCounterRegister_HHD +#define AQ_MsmLineTxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineTxGoodFramesCounterRegister_HHD +#define AQ_MsmLineTxIpgControlRegister_BiggestVersion AQ_MsmLineTxIpgControlRegister_HHD +#define AQ_MsmLineTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineTxMulticastFramesCounterRegister_HHD +#define AQ_MsmLineTxOctetsCounterRegister_BiggestVersion AQ_MsmLineTxOctetsCounterRegister_HHD +#define AQ_MsmLineTxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineTxPauseFramesCounterRegister_HHD +#define AQ_MsmLineTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineTxUnicastFramesCounterRegister_HHD +#define AQ_MsmLineTxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineTxVlanFramesCounterRegister_HHD +#define AQ_MsmSystemFifoControlRegister_BiggestVersion AQ_MsmSystemFifoControlRegister_HHD +#define AQ_MsmSystemGeneralControlRegister_BiggestVersion AQ_MsmSystemGeneralControlRegister_HHD +#define AQ_MsmSystemGeneralStatusRegister_BiggestVersion AQ_MsmSystemGeneralStatusRegister_HHD +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD +#define AQ_MsmSystemRxErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxErrorsCounterRegister_HHD +#define AQ_MsmSystemRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxFcsErrorsCounterRegister_HHD +#define AQ_MsmSystemRxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemRxGoodFramesCounterRegister_HHD +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD +#define AQ_MsmSystemRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxMulticastFramesCounterRegister_HHD +#define AQ_MsmSystemRxOctetsCounterRegister_BiggestVersion AQ_MsmSystemRxOctetsCounterRegister_HHD +#define AQ_MsmSystemRxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemRxPauseFramesCounterRegister_HHD +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD +#define AQ_MsmSystemRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxUnicastFramesCounterRegister_HHD +#define AQ_MsmSystemRxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemRxVlanFramesCounterRegister_HHD +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD +#define AQ_MsmSystemTxErrorsCounterRegister_BiggestVersion AQ_MsmSystemTxErrorsCounterRegister_HHD +#define AQ_MsmSystemTxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemTxGoodFramesCounterRegister_HHD +#define AQ_MsmSystemTxIpgControlRegister_BiggestVersion AQ_MsmSystemTxIpgControlRegister_HHD +#define AQ_MsmSystemTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxMulticastFramesCounterRegister_HHD +#define AQ_MsmSystemTxOctetsCounterRegister_BiggestVersion AQ_MsmSystemTxOctetsCounterRegister_HHD +#define AQ_MsmSystemTxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemTxPauseFramesCounterRegister_HHD +#define AQ_MsmSystemTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxUnicastFramesCounterRegister_HHD +#define AQ_MsmSystemTxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemTxVlanFramesCounterRegister_HHD +#define AQ_MssEgressControlRegister_BiggestVersion AQ_MssEgressControlRegister_HHD +#define AQ_MssEgressEccInterruptStatusRegister_BiggestVersion AQ_MssEgressEccInterruptStatusRegister_HHD +#define AQ_MssEgressInterruptMaskRegister_BiggestVersion AQ_MssEgressInterruptMaskRegister_HHD +#define AQ_MssEgressInterruptStatusRegister_BiggestVersion AQ_MssEgressInterruptStatusRegister_HHD +#define AQ_MssEgressLutAddressControlRegister_BiggestVersion AQ_MssEgressLutAddressControlRegister_HHD +#define AQ_MssEgressLutControlRegister_BiggestVersion AQ_MssEgressLutControlRegister_HHD +#define AQ_MssEgressLutDataControlRegister_BiggestVersion AQ_MssEgressLutDataControlRegister_HHD +#define AQ_MssEgressMtuSizeControlRegister_BiggestVersion AQ_MssEgressMtuSizeControlRegister_HHD +#define AQ_MssEgressPnControlRegister_BiggestVersion AQ_MssEgressPnControlRegister_HHD +#define AQ_MssEgressSaExpiredStatusRegister_BiggestVersion AQ_MssEgressSaExpiredStatusRegister_HHD +#define AQ_MssEgressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssEgressSaThresholdExpiredStatusRegister_HHD +#define AQ_MssEgressVlanControlRegister_BiggestVersion AQ_MssEgressVlanControlRegister_HHD +#define AQ_MssEgressVlanTpid_0Register_BiggestVersion AQ_MssEgressVlanTpid_0Register_HHD +#define AQ_MssEgressVlanTpid_1Register_BiggestVersion AQ_MssEgressVlanTpid_1Register_HHD +#define AQ_MssIngressControlRegister_BiggestVersion AQ_MssIngressControlRegister_HHD +#define AQ_MssIngressEccInterruptStatusRegister_BiggestVersion AQ_MssIngressEccInterruptStatusRegister_HHD +#define AQ_MssIngressInterruptMaskRegister_BiggestVersion AQ_MssIngressInterruptMaskRegister_HHD +#define AQ_MssIngressInterruptStatusRegister_BiggestVersion AQ_MssIngressInterruptStatusRegister_HHD +#define AQ_MssIngressLutAddressControlRegister_BiggestVersion AQ_MssIngressLutAddressControlRegister_HHD +#define AQ_MssIngressLutControlRegister_BiggestVersion AQ_MssIngressLutControlRegister_HHD +#define AQ_MssIngressLutDataControlRegister_BiggestVersion AQ_MssIngressLutDataControlRegister_HHD +#define AQ_MssIngressMtuSizeControlRegister_BiggestVersion AQ_MssIngressMtuSizeControlRegister_HHD +#define AQ_MssIngressSaControlRegister_BiggestVersion AQ_MssIngressSaControlRegister_HHD +#define AQ_MssIngressSaExpiredStatusRegister_BiggestVersion AQ_MssIngressSaExpiredStatusRegister_HHD +#define AQ_MssIngressSaIcvErrorStatusRegister_BiggestVersion AQ_MssIngressSaIcvErrorStatusRegister_HHD +#define AQ_MssIngressSaReplayErrorStatusRegister_BiggestVersion AQ_MssIngressSaReplayErrorStatusRegister_HHD +#define AQ_MssIngressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssIngressSaThresholdExpiredStatusRegister_HHD +#define AQ_MssIngressVlanControlRegister_BiggestVersion AQ_MssIngressVlanControlRegister_HHD +#define AQ_MssIngressVlanTpid_0Register_BiggestVersion AQ_MssIngressVlanTpid_0Register_HHD +#define AQ_MssIngressVlanTpid_1Register_BiggestVersion AQ_MssIngressVlanTpid_1Register_HHD +#define AQ_Pcs10GBaseT_Status_BiggestVersion AQ_Pcs10GBaseT_Status_APPIA +#define AQ_Pcs10G_Status_BiggestVersion AQ_Pcs10G_Status_HHD +#define AQ_Pcs10G_base_rPcsTest_patternControl_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternControl_HHD +#define AQ_Pcs10G_base_rPcsTest_patternErrorCounter_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternErrorCounter_HHD +#define AQ_Pcs10G_base_rTestPatternSeedA_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedA_HHD +#define AQ_Pcs10G_base_rTestPatternSeedB_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedB_HHD +#define AQ_PcsEeeCapabilityRegister_BiggestVersion AQ_PcsEeeCapabilityRegister_HHD +#define AQ_PcsEeeWakeErrorCounter_BiggestVersion AQ_PcsEeeWakeErrorCounter_HHD +#define AQ_PcsReceiveStandardInterruptMask_BiggestVersion AQ_PcsReceiveStandardInterruptMask_APPIA +#define AQ_PcsReceiveVendorAlarms_BiggestVersion AQ_PcsReceiveVendorAlarms_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_HHD +#define AQ_PcsReceiveVendorCrc_8ErrorCounter_BiggestVersion AQ_PcsReceiveVendorCrc_8ErrorCounter_HHD +#define AQ_PcsReceiveVendorDebug_BiggestVersion AQ_PcsReceiveVendorDebug_HHD +#define AQ_PcsReceiveVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsErrorFrameCounter_HHD +#define AQ_PcsReceiveVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsNoErrorFrameCounter_HHD +#define AQ_PcsReceiveVendorInterruptMask_BiggestVersion AQ_PcsReceiveVendorInterruptMask_HHD +#define AQ_PcsReceiveVendorProvisioning_BiggestVersion AQ_PcsReceiveVendorProvisioning_HHD +#define AQ_PcsReceiveVendorState_BiggestVersion AQ_PcsReceiveVendorState_HHD +#define AQ_PcsReceiveVendorUncorrectedFrameCounter_BiggestVersion AQ_PcsReceiveVendorUncorrectedFrameCounter_HHD +#define AQ_PcsReceiveXfi0Provisioning_BiggestVersion AQ_PcsReceiveXfi0Provisioning_HHD +#define AQ_PcsReceiveXfi0VendorState_BiggestVersion AQ_PcsReceiveXfi0VendorState_HHD +#define AQ_PcsReceiveXfi1Provisioning_BiggestVersion AQ_PcsReceiveXfi1Provisioning_HHD +#define AQ_PcsReceiveXfi1VendorState_BiggestVersion AQ_PcsReceiveXfi1VendorState_HHD +#define AQ_PcsSerdesMuxSwapTxrxRegister_BiggestVersion AQ_PcsSerdesMuxSwapTxrxRegister_HHD +#define AQ_PcsStandardControl_1_BiggestVersion AQ_PcsStandardControl_1_HHD +#define AQ_PcsStandardControl_2_BiggestVersion AQ_PcsStandardControl_2_HHD +#define AQ_PcsStandardDeviceIdentifier_BiggestVersion AQ_PcsStandardDeviceIdentifier_HHD +#define AQ_PcsStandardDevicesInPackage_BiggestVersion AQ_PcsStandardDevicesInPackage_HHD +#define AQ_PcsStandardInterruptMask_BiggestVersion AQ_PcsStandardInterruptMask_HHD +#define AQ_PcsStandardPackageIdentifier_BiggestVersion AQ_PcsStandardPackageIdentifier_HHD +#define AQ_PcsStandardSpeedAbility_BiggestVersion AQ_PcsStandardSpeedAbility_HHD +#define AQ_PcsStandardStatus_1_BiggestVersion AQ_PcsStandardStatus_1_HHD +#define AQ_PcsStandardStatus_2_BiggestVersion AQ_PcsStandardStatus_2_HHD +#define AQ_PcsTransmitReservedVendorProvisioning_BiggestVersion AQ_PcsTransmitReservedVendorProvisioning_HHD +#define AQ_PcsTransmitVendorAlarms_BiggestVersion AQ_PcsTransmitVendorAlarms_APPIA +#define AQ_PcsTransmitVendorDebug_BiggestVersion AQ_PcsTransmitVendorDebug_HHD +#define AQ_PcsTransmitVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsErrorFrameCounter_HHD +#define AQ_PcsTransmitVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsNoErrorFrameCounter_HHD +#define AQ_PcsTransmitVendorInterruptMask_BiggestVersion AQ_PcsTransmitVendorInterruptMask_APPIA +#define AQ_PcsTransmitVendorProvisioning_BiggestVersion AQ_PcsTransmitVendorProvisioning_HHD +#define AQ_PcsTransmitXfi0VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi0VendorProvisioning_HHD +#define AQ_PcsTransmitXfi0VendorState_BiggestVersion AQ_PcsTransmitXfi0VendorState_HHD +#define AQ_PcsTransmitXfi1VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi1VendorProvisioning_HHD +#define AQ_PcsTransmitXfi1VendorState_BiggestVersion AQ_PcsTransmitXfi1VendorState_HHD +#define AQ_PcsTransmitXfiVendorProvisioning_BiggestVersion AQ_PcsTransmitXfiVendorProvisioning_HHD +#define AQ_PcsTransmitXgsVendorState_BiggestVersion AQ_PcsTransmitXgsVendorState_HHD +#define AQ_PcsVendorGlobalInterruptFlags_BiggestVersion AQ_PcsVendorGlobalInterruptFlags_HHD +#define AQ_PhyXS_EeeCapabilityRegister_BiggestVersion AQ_PhyXS_EeeCapabilityRegister_HHD +#define AQ_PhyXS_EeeWakeErrorCounter_BiggestVersion AQ_PhyXS_EeeWakeErrorCounter_HHD +#define AQ_PhyXS_Receive_xauiTx_PcsStatus_BiggestVersion AQ_PhyXS_Receive_xauiTx_PcsStatus_HHD +#define AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_HHD +#define AQ_PhyXS_Receive_xauiTx_VendorAlarms_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorAlarms_HHD +#define AQ_PhyXS_Receive_xauiTx_VendorDebug_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorDebug_HHD +#define AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_HHD +#define AQ_PhyXS_SerdesConfiguration_BiggestVersion AQ_PhyXS_SerdesConfiguration_HHD +#define AQ_PhyXS_SerdesLane_0Configuration_BiggestVersion AQ_PhyXS_SerdesLane_0Configuration_HHD +#define AQ_PhyXS_SerdesLane_1Configuration_BiggestVersion AQ_PhyXS_SerdesLane_1Configuration_HHD +#define AQ_PhyXS_SerdesLane_2Configuration_BiggestVersion AQ_PhyXS_SerdesLane_2Configuration_HHD +#define AQ_PhyXS_SerdesLane_3Configuration_BiggestVersion AQ_PhyXS_SerdesLane_3Configuration_HHD +#define AQ_PhyXS_SerdesLut_BiggestVersion AQ_PhyXS_SerdesLut_HHD +#define AQ_PhyXS_StandardControl_1_BiggestVersion AQ_PhyXS_StandardControl_1_HHD +#define AQ_PhyXS_StandardDeviceIdentifier_BiggestVersion AQ_PhyXS_StandardDeviceIdentifier_HHD +#define AQ_PhyXS_StandardDevicesInPackage_BiggestVersion AQ_PhyXS_StandardDevicesInPackage_HHD +#define AQ_PhyXS_StandardPackageIdentifier_BiggestVersion AQ_PhyXS_StandardPackageIdentifier_HHD +#define AQ_PhyXS_StandardSpeedAbility_BiggestVersion AQ_PhyXS_StandardSpeedAbility_HHD +#define AQ_PhyXS_StandardStatus_1_BiggestVersion AQ_PhyXS_StandardStatus_1_HHD +#define AQ_PhyXS_StandardStatus_2_BiggestVersion AQ_PhyXS_StandardStatus_2_HHD +#define AQ_PhyXS_StandardXGXS_LaneStatus_BiggestVersion AQ_PhyXS_StandardXGXS_LaneStatus_HHD +#define AQ_PhyXS_StandardXGXS_TestControl_BiggestVersion AQ_PhyXS_StandardXGXS_TestControl_HHD +#define AQ_PhyXS_SystemInterfaceConnectionStatus_BiggestVersion AQ_PhyXS_SystemInterfaceConnectionStatus_HHD +#define AQ_PhyXS_Transmit_xauiRx_PcsStatus_BiggestVersion AQ_PhyXS_Transmit_xauiRx_PcsStatus_HHD +#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_HHD +#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_HHD +#define AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_HHD +#define AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_BiggestVersion AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_HHD +#define AQ_PhyXS_Transmit_xauiRx_VendorAlarms_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorAlarms_HHD +#define AQ_PhyXS_Transmit_xauiRx_VendorDebug_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorDebug_HHD +#define AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_HHD +#define AQ_PhyXS_VendorGlobalInterruptFlags_BiggestVersion AQ_PhyXS_VendorGlobalInterruptFlags_HHD +#define AQ_PifMailboxControl_BiggestVersion AQ_PifMailboxControl_HHD +#define AQ_Pma10GBaseT_FastRetrainStatusAndControl_BiggestVersion AQ_Pma10GBaseT_FastRetrainStatusAndControl_HHD +#define AQ_Pma10GBaseT_PairSwapAndPolarityStatus_BiggestVersion AQ_Pma10GBaseT_PairSwapAndPolarityStatus_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_HHD +#define AQ_Pma10GBaseT_SkewDelay_BiggestVersion AQ_Pma10GBaseT_SkewDelay_HHD +#define AQ_Pma10GBaseT_Status_BiggestVersion AQ_Pma10GBaseT_Status_HHD +#define AQ_Pma10GBaseT_TestModes_BiggestVersion AQ_Pma10GBaseT_TestModes_HHD +#define AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_BiggestVersion AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_HHD +#define AQ_PmaReceiveReservedVendorProvisioning_BiggestVersion AQ_PmaReceiveReservedVendorProvisioning_HHD +#define AQ_PmaReceiveReservedVendorState_BiggestVersion AQ_PmaReceiveReservedVendorState_HHD +#define AQ_PmaReceiveVendorState_BiggestVersion AQ_PmaReceiveVendorState_HHD +#define AQ_PmaStandardControl_1_BiggestVersion AQ_PmaStandardControl_1_HHD +#define AQ_PmaStandardControl_2_BiggestVersion AQ_PmaStandardControl_2_HHD +#define AQ_PmaStandardDeviceIdentifier_BiggestVersion AQ_PmaStandardDeviceIdentifier_HHD +#define AQ_PmaStandardDevicesInPackage_BiggestVersion AQ_PmaStandardDevicesInPackage_HHD +#define AQ_PmaStandardPackageIdentifier_BiggestVersion AQ_PmaStandardPackageIdentifier_HHD +#define AQ_PmaStandardSpeedAbility_BiggestVersion AQ_PmaStandardSpeedAbility_HHD +#define AQ_PmaStandardStatus_1_BiggestVersion AQ_PmaStandardStatus_1_HHD +#define AQ_PmaStandardStatus_2_BiggestVersion AQ_PmaStandardStatus_2_HHD +#define AQ_PmaTransmitReservedVendorProvisioning_BiggestVersion AQ_PmaTransmitReservedVendorProvisioning_HHD +#define AQ_PmaTransmitStandardInterruptMask_BiggestVersion AQ_PmaTransmitStandardInterruptMask_HHD +#define AQ_PmaTransmitVendorAlarms_BiggestVersion AQ_PmaTransmitVendorAlarms_HHD +#define AQ_PmaTransmitVendorDebug_BiggestVersion AQ_PmaTransmitVendorDebug_HHD +#define AQ_PmaTransmitVendorLASI_InterruptMask_BiggestVersion AQ_PmaTransmitVendorLASI_InterruptMask_HHD +#define AQ_PmaVendorGlobalInterruptFlags_BiggestVersion AQ_PmaVendorGlobalInterruptFlags_HHD +#define AQ_PmdStandard10G_ExtendedAbilityRegister_BiggestVersion AQ_PmdStandard10G_ExtendedAbilityRegister_HHD +#define AQ_PmdStandardSignalDetect_BiggestVersion AQ_PmdStandardSignalDetect_HHD +#define AQ_PmdStandardTransmitDisableControl_BiggestVersion AQ_PmdStandardTransmitDisableControl_HHD +#define AQ_Sgmii0WolStatus_BiggestVersion AQ_Sgmii0WolStatus_HHD +#define AQ_TimesyncPcsCapability_BiggestVersion AQ_TimesyncPcsCapability_HHD +#define AQ_TimesyncPcsReceivePathDataDelay_BiggestVersion AQ_TimesyncPcsReceivePathDataDelay_HHD +#define AQ_TimesyncPcsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPcsTransmitPathDataDelay_HHD +#define AQ_TimesyncPhyXsCapability_BiggestVersion AQ_TimesyncPhyXsCapability_HHD +#define AQ_TimesyncPhyXsReceivePathDataDelay_BiggestVersion AQ_TimesyncPhyXsReceivePathDataDelay_HHD +#define AQ_TimesyncPhyXsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPhyXsTransmitPathDataDelay_HHD +#define AQ_TimesyncPmaCapability_BiggestVersion AQ_TimesyncPmaCapability_HHD +#define AQ_TimesyncPmaReceivePathDataDelay_BiggestVersion AQ_TimesyncPmaReceivePathDataDelay_HHD +#define AQ_TimesyncPmaTransmitPathDataDelay_BiggestVersion AQ_TimesyncPmaTransmitPathDataDelay_HHD +#define AQ_XenpakBasic_ApsLoading_BiggestVersion AQ_XenpakBasic_ApsLoading_HHD +#define AQ_XenpakBasic_ApsVoltage_BiggestVersion AQ_XenpakBasic_ApsVoltage_HHD +#define AQ_XenpakBasic_BitRate_BiggestVersion AQ_XenpakBasic_BitRate_HHD +#define AQ_XenpakBasic_Checksum_BiggestVersion AQ_XenpakBasic_Checksum_HHD +#define AQ_XenpakBasic_ConnectorType_BiggestVersion AQ_XenpakBasic_ConnectorType_HHD +#define AQ_XenpakBasic_DomCapability_BiggestVersion AQ_XenpakBasic_DomCapability_HHD +#define AQ_XenpakBasic_Encoding_BiggestVersion AQ_XenpakBasic_Encoding_HHD +#define AQ_XenpakBasic_Low_powerStartupCapability_BiggestVersion AQ_XenpakBasic_Low_powerStartupCapability_HHD +#define AQ_XenpakBasic_PackageIdentifier_BiggestVersion AQ_XenpakBasic_PackageIdentifier_HHD +#define AQ_XenpakBasic_Protocol_BiggestVersion AQ_XenpakBasic_Protocol_HHD +#define AQ_XenpakBasic_Reserved_0x11_BiggestVersion AQ_XenpakBasic_Reserved_0x11_HHD +#define AQ_XenpakBasic_Reserved_0x19_BiggestVersion AQ_XenpakBasic_Reserved_0x19_HHD +#define AQ_XenpakBasic_Reserved_0x7c_BiggestVersion AQ_XenpakBasic_Reserved_0x7c_HHD +#define AQ_XenpakBasic_StandardsComplianceCodes_BiggestVersion AQ_XenpakBasic_StandardsComplianceCodes_HHD +#define AQ_XenpakBasic_TransceiverType_BiggestVersion AQ_XenpakBasic_TransceiverType_HHD +#define AQ_XenpakBasic_VendorDateCode_BiggestVersion AQ_XenpakBasic_VendorDateCode_HHD +#define AQ_XenpakBasic_VendorIdentifier_BiggestVersion AQ_XenpakBasic_VendorIdentifier_HHD +#define AQ_XenpakBasic_VendorName_BiggestVersion AQ_XenpakBasic_VendorName_HHD +#define AQ_XenpakBasic_VendorPartNumber_BiggestVersion AQ_XenpakBasic_VendorPartNumber_HHD +#define AQ_XenpakBasic_VendorPartRevisionNumber_BiggestVersion AQ_XenpakBasic_VendorPartRevisionNumber_HHD +#define AQ_XenpakBasic_VendorSerialNumber_BiggestVersion AQ_XenpakBasic_VendorSerialNumber_HHD +#define AQ_XenpakBasic__3_3vLoading_BiggestVersion AQ_XenpakBasic__3_3vLoading_HHD +#define AQ_XenpakBasic__5vLoading_BiggestVersion AQ_XenpakBasic__5vLoading_HHD +#define AQ_XenpakControl_BiggestVersion AQ_XenpakControl_HHD +#define AQ_XenpakCustomer_Reserved_0x7e_BiggestVersion AQ_XenpakCustomer_Reserved_0x7e_HHD +#define AQ_XenpakDom_Alarms_BiggestVersion AQ_XenpakDom_Alarms_HHD +#define AQ_XenpakDom_Capability_BiggestVersion AQ_XenpakDom_Capability_HHD +#define AQ_XenpakDom_ControlAndStatus_BiggestVersion AQ_XenpakDom_ControlAndStatus_HHD +#define AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_HHD +#define AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_HHD +#define AQ_XenpakDom_HighTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdLSW_HHD +#define AQ_XenpakDom_HighTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdMSW_HHD +#define AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_HHD +#define AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_HHD +#define AQ_XenpakDom_LowTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdLSW_HHD +#define AQ_XenpakDom_LowTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdMSW_HHD +#define AQ_XenpakDom_Status_BiggestVersion AQ_XenpakDom_Status_HHD +#define AQ_XenpakDom_TemperatureLSW_BiggestVersion AQ_XenpakDom_TemperatureLSW_HHD +#define AQ_XenpakDom_TemperatureMSW_BiggestVersion AQ_XenpakDom_TemperatureMSW_HHD +#define AQ_XenpakDom_TxControl_BiggestVersion AQ_XenpakDom_TxControl_HHD +#define AQ_XenpakHeader_BasicMemoryStartAddress_BiggestVersion AQ_XenpakHeader_BasicMemoryStartAddress_HHD +#define AQ_XenpakHeader_CustomerMemoryOffset_BiggestVersion AQ_XenpakHeader_CustomerMemoryOffset_HHD +#define AQ_XenpakHeader_ExtendedVendorMemoryOffset_BiggestVersion AQ_XenpakHeader_ExtendedVendorMemoryOffset_HHD +#define AQ_XenpakHeader_MemoryUsed_BiggestVersion AQ_XenpakHeader_MemoryUsed_HHD +#define AQ_XenpakHeader_NvrSize_BiggestVersion AQ_XenpakHeader_NvrSize_HHD +#define AQ_XenpakHeader_VendorMemoryStartAddress_BiggestVersion AQ_XenpakHeader_VendorMemoryStartAddress_HHD +#define AQ_XenpakHeader_XenpakMsaVersionSupported_BiggestVersion AQ_XenpakHeader_XenpakMsaVersionSupported_HHD +#define AQ_XenpakLASI__Control_BiggestVersion AQ_XenpakLASI__Control_HHD +#define AQ_XenpakLASI__Status_BiggestVersion AQ_XenpakLASI__Status_HHD +#define AQ_XenpakRxAlarm_Control_BiggestVersion AQ_XenpakRxAlarm_Control_HHD +#define AQ_XenpakRxAlarm_Status_BiggestVersion AQ_XenpakRxAlarm_Status_HHD +#define AQ_XenpakTxAlarm_Control_BiggestVersion AQ_XenpakTxAlarm_Control_HHD +#define AQ_XenpakTxAlarm_Status_BiggestVersion AQ_XenpakTxAlarm_Status_HHD +#define AQ_XenpakVendor_Reserved_0xae_BiggestVersion AQ_XenpakVendor_Reserved_0xae_HHD + +#endif diff --git a/firmware/aq-fw-download/src/include/registerMap/AQ_RegMaps.h b/firmware/aq-fw-download/src/include/registerMap/AQ_RegMaps.h new file mode 100755 index 0000000..52a24e3 --- /dev/null +++ b/firmware/aq-fw-download/src/include/registerMap/AQ_RegMaps.h @@ -0,0 +1,69 @@ +/*AQ_RegMaps.h*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file contains includes all appropriate Aquantia PHY device-specific +* register map headers. +* +************************************************************************************/ + +/*! \file +* This file contains includes all appropriate Aquantia PHY device-specific +* register map headers. + */ + +#ifndef AQ_REGISTERMAPS_HEADER +#define AQ_REGISTERMAPS_HEADER + +#include "AQ_User.h" +#include "AQ_RegGroupMaxSizes.h" + + +#ifndef AQ_REVERSED_BITFIELD_ORDERING +/* + * Include non-reversed header files (bitfields ordered from LSbit to MSbit) + */ + +/* APPIA */ +#include "AQ_APPIA_Global_registers.h" + +#include "AQ_APPIA_Global_registers_Defines.h" + +/* HHD */ +#include "AQ_HHD_Global_registers.h" + +#include "AQ_HHD_Global_registers_Defines.h" + +#else +/* + * Include reversed header files (bitfields ordered from MSbit to LSbit) + */ + +/* APPIA */ +#include "AQ_APPIA_Global_registers_reversed.h" + +#include "AQ_APPIA_Global_registers_Defines.h" + +/* HHD */ +#include "AQ_HHD_Global_registers_reversed.h" + +#include "AQ_HHD_Global_registers_Defines.h" + +#endif + +#endif diff --git a/firmware/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h b/firmware/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h new file mode 100755 index 0000000..e0a2fa2 --- /dev/null +++ b/firmware/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h @@ -0,0 +1,12123 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from LSbit to MSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_HHD_GLOBAL_REGS_HEADER +#define AQ_HHD_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_HHD.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_HHD.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Resets the entire PHY. + Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_HHD.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_HHD.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_HHD.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_HHD.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_HHD.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_HHD.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_HHD.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + unsigned int reserved0 : 8; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_HHD.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_HHD.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_HHD.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved2 : 8; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_HHD.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_HHD.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_HHD.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved1 : 1; + /*! \brief 1E.0206.1 R/W uP Mailbox CRC Read Enable + AQ_GlobalMailboxInterface_HHD.u6.bits_6.upMailboxCrcReadEnable + + Default = 0x0 + + 1 = Update uP mailbox CRC on read + + */ + unsigned int upMailboxCrcReadEnable : 1; /* 1E.0206.1 R/W Default = 0x0 */ + /* 1 = Update uP mailbox CRC on read + */ + unsigned int reserved0 : 14; + } bits_6; + uint16_t word_6; + } u6; +} AQ_GlobalMailboxInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Control Register: 1E.5002 */ +/* MSS Egress Control Register: 1E.5002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Control Register */ + union + { + struct + { + /*! \brief 1E.5002.0 R/W MSS Egress Soft Reset + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssEgressSoftReset : 1; /* 1E.5002.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.5002.1 R/W MSS Egress Drop KAY Packet + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropKayPacket + + Default = 0x0 + + 1 = Drop KAY packet + + + Notes: + Decides whether KAY packets have to be dropped */ + unsigned int mssEgressDropKayPacket : 1; /* 1E.5002.1 R/W Default = 0x0 */ + /* 1 = Drop KAY packet + */ + /*! \brief 1E.5002.2 R/W MSS Egress Drop EGPRC LUT Miss + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropEgprcLutMiss + + Default = 0x0 + + 1 = Drop Egress Classification LUT miss packets + + + + Notes: + Decides whether Egress Pre-Security Classification (EGPRC) LUT miss packets are to be dropped */ + unsigned int mssEgressDropEgprcLutMiss : 1; /* 1E.5002.2 R/W Default = 0x0 */ + /* 1 = Drop Egress Classification LUT miss packets + + */ + /*! \brief 1E.5002.3 R/W MSS Egress GCM Start + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressGcmStart + + Default = 0x0 + + 1 = Start GCM + + + + Notes: + Indicates GCM to start */ + unsigned int mssEgressGcmStart : 1; /* 1E.5002.3 R/W Default = 0x0 */ + /* 1 = Start GCM + + */ + /*! \brief 1E.5002.4 R/W MSS Egresss GCM Test Mode + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgresssGcmTestMode + + Default = 0x0 + + 1 = Enable GCM test mode + + + + Notes: + Enables GCM test mode */ + unsigned int mssEgresssGcmTestMode : 1; /* 1E.5002.4 R/W Default = 0x0 */ + /* 1 = Enable GCM test mode + + */ + /*! \brief 1E.5002.5 R/W MSS Egress Unmatched Use SC 0 + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressUnmatchedUseSc_0 + + Default = 0x0 + + 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + + + Notes: + Use SC-Index 0 as default SC for unmatched packets. Otherwise the packets are treated as uncontrolled packets. */ + unsigned int mssEgressUnmatchedUseSc_0 : 1; /* 1E.5002.5 R/W Default = 0x0 */ + /* 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + */ + /*! \brief 1E.5002.6 R/W MSS Egress Drop Invalid SA/SC Packets + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropInvalidSa_scPackets + + Default = 0x0 + + 1 = Drop invalid SA/SC packets + + + + Notes: + Enables dropping of invalid SA/SC packets. */ + unsigned int mssEgressDropInvalidSa_scPackets : 1; /* 1E.5002.6 R/W Default = 0x0 */ + /* 1 = Drop invalid SA/SC packets + + */ + /*! \brief 1E.5002.7 R/W MSS Egress Explicit SECTag Report Short Length + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExplicitSectagReportShortLength + + Default = 0x0 + + Reserved + + + + Notes: + Unused. */ + unsigned int mssEgressExplicitSectagReportShortLength : 1; /* 1E.5002.7 R/W Default = 0x0 */ + /* Reserved + + */ + /*! \brief 1E.5002.8 R/W MSS Egress External Classification Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExternalClassificationEnable + + Default = 0x0 + + 1 = Drop EGPRC miss packets + + + + Notes: + If set, internal classification is bypassed. Should always be set to 0. */ + unsigned int mssEgressExternalClassificationEnable : 1; /* 1E.5002.8 R/W Default = 0x0 */ + /* 1 = Drop EGPRC miss packets + + */ + /*! \brief 1E.5002.9 R/W MSS Egress ICV LSB 8 Bytes Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssEgressIcvLsb_8BytesEnable : 1; /* 1E.5002.9 R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + /*! \brief 1E.5002.A R/W MSS Egress High Priority + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssEgressHighPriority : 1; /* 1E.5002.A R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + + */ + /*! \brief 1E.5002.B R/W MSS Egress Clear Counter + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearCounter + + Default = 0x0 + + 1 = Clear all MIB counters + + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssEgressClearCounter : 1; /* 1E.5002.B R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + + */ + /*! \brief 1E.5002.C R/W MSS Egress Clear Global Time + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + + Notes: + Clear global time. */ + unsigned int mssEgressClearGlobalTime : 1; /* 1E.5002.C R/W Default = 0x0 */ + /* 1 = Clear global time + + */ + /*! \brief 1E.5002.F:D R/W MSS Egress Ethertype Explicit SECTag LSB [2:0] + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressEthertypeExplicitSectagLsb + + Default = 0x0 + + Ethertype for explicit SECTag bits 2:0. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagLsb : 3; /* 1E.5002.F:D R/W Default = 0x0 */ + /* Ethertype for explicit SECTag bits 2:0. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Control Register */ + union + { + struct + { + /*! \brief 1E.5003.C:0 R/W MSS Egress Ethertype Explicit SECTag MSB [F:3] + AQ_MssEgressControlRegister_HHD.u1.bits_1.mssEgressEthertypeExplicitSectagMsb + + Default = 0x0000 + + Ethertype for explicit SECTag bits 15:3. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagMsb : 13; /* 1E.5003.C:0 R/W Default = 0x0000 */ + /* Ethertype for explicit SECTag bits 15:3. + */ + unsigned int reserved0 : 3; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/* MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.5008.F:0 R/W MSS Egress VLAN STag TPID [F:0] + AQ_MssEgressVlanTpid_0Register_HHD.u0.bits_0.mssEgressVlanStagTpid + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanStagTpid : 16; /* 1E.5008.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 1 Register: 1E.500A */ +/* MSS Egress VLAN TPID 1 Register: 1E.500A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.500A.F:0 R/W MSS Egress VLAN QTag TPID [F:0] + AQ_MssEgressVlanTpid_1Register_HHD.u0.bits_0.mssEgressVlanQtagTpid + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanQtagTpid : 16; /* 1E.500A.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN Control Register: 1E.500C */ +/* MSS Egress VLAN Control Register: 1E.500C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500C.F:0 R/W MSS Egress VLAN UP Map Table [F:0] + AQ_MssEgressVlanControlRegister_HHD.u0.bits_0.mssEgressVlanUpMapTable + + Default = 0x0000 + + UP Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTable : 16; /* 1E.500C.F:0 R/W Default = 0x0000 */ + /* UP Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500D.7:0 R/W MSS Egress VLAN UP Map Table MSW [17:10] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTableMSW : 8; /* 1E.500D.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + /*! \brief 1E.500D.A:8 R/W MSS Egress VLAN UP Default [2:0] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssEgressVlanUpDefault : 3; /* 1E.500D.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.500D.B R/W MSS Egress VLAN STag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssEgressVlanStagUpParseEnable : 1; /* 1E.500D.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.500D.C R/W MSS Egress VLAN QTag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssEgressVlanQtagUpParseEnable : 1; /* 1E.500D.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.500D.D R/W MSS Egress VLAN QinQ Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssEgressVlanQinqParseEnable : 1; /* 1E.500D.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.500D.E R/W MSS Egress VLAN STag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See SEC Egress TPID 0 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanStagParseEnable : 1; /* 1E.500D.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.500D.F R/W MSS Egress VLAN QTag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See SEC Egress TPID 1 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanQtagParseEnable : 1; /* 1E.500D.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress PN Control Register: 1E.500E */ +/* MSS Egress PN Control Register: 1E.500E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500E.F:0 R/W MSS Egress SA PN Threshold LSW [F:0] + AQ_MssEgressPnControlRegister_HHD.u0.bits_0.mssEgressSaPnThresholdLSW + + Default = 0x0000 + + PN threshold bits 15:0 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdLSW : 16; /* 1E.500E.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500F.F:0 R/W MSS Egress SA PN Threshold MSW [1F:10] + AQ_MssEgressPnControlRegister_HHD.u1.bits_1.mssEgressSaPnThresholdMSW + + Default = 0x0000 + + PN threshold bits 31:16 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdMSW : 16; /* 1E.500F.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressPnControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress MTU Size Control Register: 1E.5010 */ +/* MSS Egress MTU Size Control Register: 1E.5010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5010.F:0 R/W MSS Egress Controlled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u0.bits_0.mssEgressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssEgressControlledPacketMtuSize : 16; /* 1E.5010.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5011.F:0 R/W MSS Egress Uncontrolled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u1.bits_1.mssEgressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssEgressUncontrolledPacketMtuSize : 16; /* 1E.5011.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Status Register: 1E.505C */ +/* MSS Egress Interrupt Status Register: 1E.505C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.505C.0 COW MSS Egress Master Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMasterInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssEgressMasterInterrupt : 1; /* 1E.505C.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.1 COW MSS Egress SA Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterrupt : 1; /* 1E.505C.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.2 COW MSS Egress SA Threshold Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredInterrupt : 1; /* 1E.505C.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.3 COW MSS Egress MIB Saturation Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterrupt : 1; /* 1E.505C.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.4 COW MSS Egress ECC Error Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterrupt : 1; /* 1E.505C.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + unsigned int reserved0 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Mask Register: 1E.505E */ +/* MSS Egress Interrupt Mask Register: 1E.505E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + /*! \brief 1E.505E.0 COW MSS Egress Master Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. */ + unsigned int mssEgressMasterInterruptEnable : 1; /* 1E.505E.0 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.1 COW MSS Egress SA Expired Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterruptEnable : 1; /* 1E.505E.1 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.2 COW MSS Egress SA Expired Threshold Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredThresholdInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaExpiredThresholdInterruptEnable : 1; /* 1E.505E.2 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.3 COW MSS Egress MIB Saturation Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterruptEnable : 1; /* 1E.505E.3 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.4 COW MSS Egress ECC Error Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterruptEnable : 1; /* 1E.505E.4 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + unsigned int reserved0 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Expired Status Register: 1E.5060 */ +/* MSS Egress SA Expired Status Register: 1E.5060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5060.F:0 COW MSS Egress SA Expired LSW [F:0] + AQ_MssEgressSaExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredLSW : 16; /* 1E.5060.F:0 COW Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5061.F:0 COW MSS Egress SA Expired MSW [1F:10] + AQ_MssEgressSaExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredMSW : 16; /* 1E.5061.F:0 COW Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/* MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5062.F:0 COW MSS Egress SA Threshold Expired LSW [F:0] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredLSW : 16; /* 1E.5062.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5063.F:0 COW MSS Egress SA Threshold Expired MSW [1F:10] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredMSW : 16; /* 1E.5063.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/* MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5064.F:0 COW MSS Egress SA ECC Error Interrupt LSW [F:0] + AQ_MssEgressEccInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptLSW : 16; /* 1E.5064.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5065.F:0 COW MSS Egress SA ECC Error Interrupt MSW [1F:10] + AQ_MssEgressEccInterruptStatusRegister_HHD.u1.bits_1.mssEgressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptMSW : 16; /* 1E.5065.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Address Control Register: 1E.5080 */ +/* MSS Egress LUT Address Control Register: 1E.5080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.5080.8:0 R/W MSS Egress LUT Address [8:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssEgressLutAddress : 9; /* 1E.5080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + unsigned int reserved0 : 3; + /*! \brief 1E.5080.F:C R/W MSS Egress LUT Select [3:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Egress MAC Control FIlter (CTLF) LUT + 0x1 : Egress Classification LUT + 0x2 : Egress SC/SA LUT + 0x3 : Egress SMIB */ + unsigned int mssEgressLutSelect : 4; /* 1E.5080.F:C R/W Default = 0x0 */ + /* LUT select + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Control Register: 1E.5081 */ +/* MSS Egress LUT Control Register: 1E.5081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Control Register */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.5081.E R/W MSS Egress LUT Read + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutRead : 1; /* 1E.5081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + /*! \brief 1E.5081.F R/W MSS Egress LUT Write + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutWrite : 1; /* 1E.5081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Data Control Register: 1E.50A0 */ +/* MSS Egress LUT Data Control Register: 1E.50A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A0.F:0 R/W MSS Egress LUT Data 0 [F:0] + AQ_MssEgressLutDataControlRegister_HHD.u0.bits_0.mssEgressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssEgressLutData_0 : 16; /* 1E.50A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A1.F:0 R/W MSS Egress LUT Data 1 [1F:10] + AQ_MssEgressLutDataControlRegister_HHD.u1.bits_1.mssEgressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssEgressLutData_1 : 16; /* 1E.50A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A2.F:0 R/W MSS Egress LUT Data 2 [2F:20] + AQ_MssEgressLutDataControlRegister_HHD.u2.bits_2.mssEgressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssEgressLutData_2 : 16; /* 1E.50A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A3.F:0 R/W MSS Egress LUT Data 3 [3F:30] + AQ_MssEgressLutDataControlRegister_HHD.u3.bits_3.mssEgressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssEgressLutData_3 : 16; /* 1E.50A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A4.F:0 R/W MSS Egress LUT Data 4 [4F:40] + AQ_MssEgressLutDataControlRegister_HHD.u4.bits_4.mssEgressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssEgressLutData_4 : 16; /* 1E.50A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A5.F:0 R/W MSS Egress LUT Data 5 [5F:50] + AQ_MssEgressLutDataControlRegister_HHD.u5.bits_5.mssEgressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssEgressLutData_5 : 16; /* 1E.50A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A6.F:0 R/W MSS Egress LUT Data 6 [6F:60] + AQ_MssEgressLutDataControlRegister_HHD.u6.bits_6.mssEgressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssEgressLutData_6 : 16; /* 1E.50A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A7.F:0 R/W MSS Egress LUT Data 7 [7F:70] + AQ_MssEgressLutDataControlRegister_HHD.u7.bits_7.mssEgressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssEgressLutData_7 : 16; /* 1E.50A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A8.F:0 R/W MSS Egress LUT Data 8 [8F:80] + AQ_MssEgressLutDataControlRegister_HHD.u8.bits_8.mssEgressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssEgressLutData_8 : 16; /* 1E.50A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A9.F:0 R/W MSS Egress LUT Data 9 [9F:90] + AQ_MssEgressLutDataControlRegister_HHD.u9.bits_9.mssEgressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssEgressLutData_9 : 16; /* 1E.50A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AA.F:0 R/W MSS Egress LUT Data 10 [AF:A0] + AQ_MssEgressLutDataControlRegister_HHD.u10.bits_10.mssEgressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssEgressLutData_10 : 16; /* 1E.50AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AB.F:0 R/W MSS Egress LUT Data 11 [BF:B0] + AQ_MssEgressLutDataControlRegister_HHD.u11.bits_11.mssEgressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssEgressLutData_11 : 16; /* 1E.50AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AC.F:0 R/W MSS Egress LUT Data 12 [CF:C0] + AQ_MssEgressLutDataControlRegister_HHD.u12.bits_12.mssEgressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssEgressLutData_12 : 16; /* 1E.50AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AD.F:0 R/W MSS Egress LUT Data 13 [DF:D0] + AQ_MssEgressLutDataControlRegister_HHD.u13.bits_13.mssEgressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssEgressLutData_13 : 16; /* 1E.50AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AE.F:0 R/W MSS Egress LUT Data 14 [EF:E0] + AQ_MssEgressLutDataControlRegister_HHD.u14.bits_14.mssEgressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssEgressLutData_14 : 16; /* 1E.50AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AF.F:0 R/W MSS Egress LUT Data 15 [FF:F0] + AQ_MssEgressLutDataControlRegister_HHD.u15.bits_15.mssEgressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssEgressLutData_15 : 16; /* 1E.50AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B0.F:0 R/W MSS Egress LUT Data 16 [10F:100] + AQ_MssEgressLutDataControlRegister_HHD.u16.bits_16.mssEgressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssEgressLutData_16 : 16; /* 1E.50B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B1.F:0 R/W MSS Egress LUT Data 17 [11F:110] + AQ_MssEgressLutDataControlRegister_HHD.u17.bits_17.mssEgressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssEgressLutData_17 : 16; /* 1E.50B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B2.F:0 R/W MSS Egress LUT Data 18 [12F:120] + AQ_MssEgressLutDataControlRegister_HHD.u18.bits_18.mssEgressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssEgressLutData_18 : 16; /* 1E.50B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B3.F:0 R/W MSS Egress LUT Data 19 [13F:130] + AQ_MssEgressLutDataControlRegister_HHD.u19.bits_19.mssEgressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssEgressLutData_19 : 16; /* 1E.50B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B4.F:0 R/W MSS Egress LUT Data 20 [14F:140] + AQ_MssEgressLutDataControlRegister_HHD.u20.bits_20.mssEgressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssEgressLutData_20 : 16; /* 1E.50B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B5.F:0 R/W MSS Egress LUT Data 21 [15F:150] + AQ_MssEgressLutDataControlRegister_HHD.u21.bits_21.mssEgressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssEgressLutData_21 : 16; /* 1E.50B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B6.F:0 R/W MSS Egress LUT Data 22 [16F:160] + AQ_MssEgressLutDataControlRegister_HHD.u22.bits_22.mssEgressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssEgressLutData_22 : 16; /* 1E.50B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B7.F:0 R/W MSS Egress LUT Data 23 [17F:170] + AQ_MssEgressLutDataControlRegister_HHD.u23.bits_23.mssEgressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssEgressLutData_23 : 16; /* 1E.50B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; + /*! \brief Union for bit and word level access of word 24 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B8.F:0 R/W MSS Egress LUT Data 24 [18F:180] + AQ_MssEgressLutDataControlRegister_HHD.u24.bits_24.mssEgressLutData_24 + + Default = 0x0000 + + LUT data bits 399:384 + + */ + unsigned int mssEgressLutData_24 : 16; /* 1E.50B8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 399:384 + */ + } bits_24; + uint16_t word_24; + } u24; + /*! \brief Union for bit and word level access of word 25 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B9.F:0 R/W MSS Egress LUT Data 25 [19F:190] + AQ_MssEgressLutDataControlRegister_HHD.u25.bits_25.mssEgressLutData_25 + + Default = 0x0000 + + LUT data bits 415:400 + + */ + unsigned int mssEgressLutData_25 : 16; /* 1E.50B9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 415:400 + */ + } bits_25; + uint16_t word_25; + } u25; + /*! \brief Union for bit and word level access of word 26 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BA.F:0 R/W MSS Egress LUT Data 26 [1AF:1A0] + AQ_MssEgressLutDataControlRegister_HHD.u26.bits_26.mssEgressLutData_26 + + Default = 0x0000 + + LUT data bits 431:416 + + */ + unsigned int mssEgressLutData_26 : 16; /* 1E.50BA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 431:416 + */ + } bits_26; + uint16_t word_26; + } u26; + /*! \brief Union for bit and word level access of word 27 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BB.F:0 R/W MSS Egress LUT Data 27 [1BF:1B0] + AQ_MssEgressLutDataControlRegister_HHD.u27.bits_27.mssEgressLutData_27 + + Default = 0x0000 + + LUT data bits 447:432 + + */ + unsigned int mssEgressLutData_27 : 16; /* 1E.50BB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 447:432 + */ + } bits_27; + uint16_t word_27; + } u27; +} AQ_MssEgressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Control Register: 1E.6004 */ +/* MSM System General Control Register: 1E.6004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Control Register */ + union + { + struct + { + /*! \brief 1E.6004.0 R/W MSM System Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmSystemTxEnable : 1; /* 1E.6004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + /*! \brief 1E.6004.1 R/W MSM System Rx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmSystemRxEnable : 1; /* 1E.6004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + unsigned int reserved0 : 1; + /*! \brief 1E.6004.3 R/W MSM System WAN Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmSystemWanMode : 1; /* 1E.6004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + /*! \brief 1E.6004.4 R/W MSM System Promiscuous Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmSystemPromiscuousMode : 1; /* 1E.6004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.6004.5 R/W MSM System PAD Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmSystemPadEnable : 1; /* 1E.6004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.6004.6 R/W MSM System CRC Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmSystemCrcForward : 1; /* 1E.6004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.6004.7 R/W MSM System Pause Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmSystemPauseForward : 1; /* 1E.6004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.6004.8 R/W MSM System Pause Ignore + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmSystemPauseIgnore : 1; /* 1E.6004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.6004.9 R/W MSM System Tx Address Insert Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmSystemTxAddressInsertEnable : 1; /* 1E.6004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.6004.A R/W MSM System Tx CRC Append + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmSystemTxCrcAppend : 1; /* 1E.6004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.6004.B R/W MSM System Tx Pad Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmSystemTxPadEnable : 1; /* 1E.6004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.6004.C R/WSC MSM System Soft Reset + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmSystemSoftReset : 1; /* 1E.6004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.6004.D R/W MSM System Control Frame Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmSystemControlFrameEnable : 1; /* 1E.6004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.6004.E R/W MSM System Rx Error Discard + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmSystemRxErrorDiscard : 1; /* 1E.6004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.6004.F R/W MSM System PHY Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmSystemPhyTxEnable : 1; /* 1E.6004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Control Register */ + union + { + struct + { + /*! \brief 1E.6005.0 R/W MSM System Force Send IDLE + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmSystemForceSendIdle : 1; /* 1E.6005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + /*! \brief 1E.6005.1 R/W MSM System Length Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmSystemLengthCheckDisable : 1; /* 1E.6005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.6005.2 R/W MSM System IDLE Column Count Extend + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmSystemIdleColumnCountExtend : 1; /* 1E.6005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.6005.3 R/W MSM System Priority Flow Control Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemPriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmSystemPriorityFlowControlEnable : 1; /* 1E.6005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + unsigned int reserved2 : 1; + /*! \brief 1E.6005.5 R/W MSM System SFD Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmSystemSfdCheckDisable : 1; /* 1E.6005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved1 : 1; + /*! \brief 1E.6005.7 R/W MSM System Tx Low Power IDLE Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmSystemTxLowPowerIdleEnable : 1; /* 1E.6005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System FIFO Control Register: 1E.600E */ +/* MSM System FIFO Control Register: 1E.600E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.600E.7:0 R/W MSM System Rx FIFO Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u0.bits_0.msmSystemRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoFullThreshold : 8; /* 1E.600E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.600F.7:0 R/W MSM System Rx FIFO Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u1.bits_1.msmSystemRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoEmptyThreshold : 8; /* 1E.600F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6010.5:0 R/W MSM System Tx FIFO Full Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u2.bits_2.msmSystemTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoFullThreshold : 6; /* 1E.6010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + unsigned int reserved0 : 10; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6011.5:0 R/W MSM System Tx FIFO Empty Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u3.bits_3.msmSystemTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoEmptyThreshold : 6; /* 1E.6011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + unsigned int reserved0 : 10; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6012.7:0 ROS MSM System Rx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u4.bits_4.msmSystemRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostFullThreshold : 8; /* 1E.6012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6013.7:0 ROS MSM System Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u5.bits_5.msmSystemRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostEmptyThreshold : 8; /* 1E.6013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6014.7:0 ROS MSM System Tx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u6.bits_6.msmSystemTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostFullThreshold : 8; /* 1E.6014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6015.7:0 ROS MSM System Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u7.bits_7.msmSystemTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostEmptyThreshold : 8; /* 1E.6015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmSystemFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Status Register: 1E.6020 */ +/* MSM System General Status Register: 1E.6020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Status Register */ + union + { + struct + { + /*! \brief 1E.6020.0 BLH MSM System Rx Local Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxLocalFault : 1; /* 1E.6020.0 BLH */ + /* Rx local fault detected */ + /*! \brief 1E.6020.1 BLH MSM System Rx Remote Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxRemoteFault : 1; /* 1E.6020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.6020.2 RO MSM System PHY Loss of Signal + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemPhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmSystemPhyLossOfSignal : 1; /* 1E.6020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.6020.3 R/W MSM System Timestamp Available + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmSystemTimestampAvailable : 1; /* 1E.6020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.6020.4 RO MSM System Rx Low Power IDLE + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmSystemRxLowPowerIdle : 1; /* 1E.6020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.6020.5 RO MSM System Tx FIFO Empty + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmSystemTxFifoEmpty : 1; /* 1E.6020.5 RO */ + /* Tx FIFO empty */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx IPG Control Register: 1E.6022 */ +/* MSM System Tx IPG Control Register: 1E.6022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.6022.5:0 R/W MSM System Tx IPG Length [5:0] + AQ_MsmSystemTxIpgControlRegister_HHD.u0.bits_0.msmSystemTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmSystemTxIpgLength : 6; /* 1E.6022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.6023.F:0 MSM System Tx IPG Reserved + AQ_MsmSystemTxIpgControlRegister_HHD.u1.bits_1.msmSystemTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmSystemTxIpgReserved : 16; /* 1E.6023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Good Frames Counter Register: 1E.6040 */ +/* MSM System Tx Good Frames Counter Register: 1E.6040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6040.F:0 ROS MSM System Tx Good Frames Counter 0 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_0 : 16; /* 1E.6040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6041.F:0 ROS MSM System Tx Good Frames Counter 1 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_1 : 16; /* 1E.6041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Good Frames Counter Register: 1E.6044 */ +/* MSM System Rx Good Frames Counter Register: 1E.6044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6044.F:0 ROS MSM System Rx Good Frames Counter 0 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_0 : 16; /* 1E.6044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6045.F:0 ROS MSM System Rx Good Frames Counter 1 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_1 : 16; /* 1E.6045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/* MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6048.F:0 ROS MSM System FCS Error Counter 0 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmSystemFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_0 : 16; /* 1E.6048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6049.F:0 ROS MSM System FCS Error Counter 1 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmSystemFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_1 : 16; /* 1E.6049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/* MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604C.F:0 ROS MSM System Alignment Error Counter 0 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmSystemAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_0 : 16; /* 1E.604C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604D.F:0 ROS MSM System Alignment Error Counter 1 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmSystemAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_1 : 16; /* 1E.604D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/* MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6050.F:0 ROS MSM System Tx Pause Frames Counter 0 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_0 : 16; /* 1E.6050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6051.F:0 ROS MSM System Tx Pause Frames Counter 1 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_1 : 16; /* 1E.6051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/* MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6054.F:0 ROS MSM System Rx Pause Frames Counter 0 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_0 : 16; /* 1E.6054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6055.F:0 ROS MSM System Rx Pause Frames Counter 1 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_1 : 16; /* 1E.6055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/* MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6058.F:0 ROS MSM System Rx Too Long Errors Counter 0 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_0 : 16; /* 1E.6058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6059.F:0 ROS MSM System Rx Too Long Errors Counter 1 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_1 : 16; /* 1E.6059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/* MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605C.F:0 ROS MSM System Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_0 : 16; /* 1E.605C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605D.F:0 ROS MSM System Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_1 : 16; /* 1E.605D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/* MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6060.F:0 ROS MSM System Tx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_0 : 16; /* 1E.6060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6061.F:0 ROS MSM System Tx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_1 : 16; /* 1E.6061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/* MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6064.F:0 ROS MSM System Rx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_0 : 16; /* 1E.6064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6065.F:0 ROS MSM System Rx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_1 : 16; /* 1E.6065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Octets Counter Register: 1E.6068 */ +/* MSM System Tx Octets Counter Register: 1E.6068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6068.F:0 ROS MSM System Tx Octets Counter 0 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u0.bits_0.msmSystemTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_0 : 16; /* 1E.6068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6069.F:0 ROS MSM System Tx Octets Counter 1 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u1.bits_1.msmSystemTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_1 : 16; /* 1E.6069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606A.F:0 ROS MSM System Tx Octets Counter 2 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u2.bits_2.msmSystemTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_2 : 16; /* 1E.606A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606B.F:0 ROS MSM System Tx Octets Counter 3 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u3.bits_3.msmSystemTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_3 : 16; /* 1E.606B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmSystemTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Octets Counter Register: 1E.606C */ +/* MSM System Rx Octets Counter Register: 1E.606C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606C.F:0 ROS MSM System Rx Octets Counter 0 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u0.bits_0.msmSystemRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_0 : 16; /* 1E.606C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606D.F:0 ROS MSM System Rx Octets Counter 1 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u1.bits_1.msmSystemRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_1 : 16; /* 1E.606D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/* MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6070.F:0 ROS MSM System Rx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_0 : 16; /* 1E.6070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6071.F:0 ROS MSM System Rx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_1 : 16; /* 1E.6071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/* MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6074.F:0 ROS MSM System Rx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_0 : 16; /* 1E.6074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6075.F:0 ROS MSM System Rx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_1 : 16; /* 1E.6075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/* MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6078.F:0 ROS MSM System Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_0 : 16; /* 1E.6078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6079.F:0 ROS MSM System Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_1 : 16; /* 1E.6079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Errors Counter Register: 1E.607C */ +/* MSM System Tx Errors Counter Register: 1E.607C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607C.F:0 ROS MSM System Tx Errors Counter 0 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u0.bits_0.msmSystemTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_0 : 16; /* 1E.607C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607D.F:0 ROS MSM System Tx Errors Counter 1 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u1.bits_1.msmSystemTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_1 : 16; /* 1E.607D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/* MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6084.F:0 ROS MSM System Tx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_0 : 16; /* 1E.6084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6085.F:0 ROS MSM System Tx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_1 : 16; /* 1E.6085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/* MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6088.F:0 ROS MSM System Tx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_0 : 16; /* 1E.6088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6089.F:0 ROS MSM System Tx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_1 : 16; /* 1E.6089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/* MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608C.F:0 ROS MSM System Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_0 : 16; /* 1E.608C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608D.F:0 ROS MSM System Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_1 : 16; /* 1E.608D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Errors Counter Register: 1E.60C8 */ +/* MSM System Rx Errors Counter Register: 1E.60C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C8.F:0 ROS MSM System Rx Errors Counter 0 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_0 : 16; /* 1E.60C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C9.F:0 ROS MSM System Rx Errors Counter 1 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_1 : 16; /* 1E.60C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/* MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.8006.F:0 R/W MSS Ingress VLAN STag [F:0] + AQ_MssIngressVlanTpid_0Register_HHD.u0.bits_0.mssIngressVlanStag + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanStag : 16; /* 1E.8006.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/* MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.8008.F:0 R/W MSS Ingress VLAN QTag [F:0] + AQ_MssIngressVlanTpid_1Register_HHD.u0.bits_0.mssIngressVlanQtag + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanQtag : 16; /* 1E.8008.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN Control Register: 1E.800A */ +/* MSS Ingress VLAN Control Register: 1E.800A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800A.F:0 R/W MSS Ingress VLAN UP Map Table LSW [F:0] + AQ_MssIngressVlanControlRegister_HHD.u0.bits_0.mssIngressVlanUpMapTableLSW + + Default = 0x0000 + + Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableLSW : 16; /* 1E.800A.F:0 R/W Default = 0x0000 */ + /* Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800B.7:0 R/W MSS Ingress VLAN UP Map Table MSW [17:10] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableMSW : 8; /* 1E.800B.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + /*! \brief 1E.800B.A:8 R/W MSS Ingress VLAN UP Default [2:0] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssIngressVlanUpDefault : 3; /* 1E.800B.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.800B.B R/W MSS Ingress VLAN STag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssIngressVlanStagUpParseEnable : 1; /* 1E.800B.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.800B.C R/W MSS Ingress VLAN QTag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssIngressVlanQtagUpParseEnable : 1; /* 1E.800B.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.800B.D R/W MSS Ingress VLAN QinQ Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssIngressVlanQinqParseEnable : 1; /* 1E.800B.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.800B.E R/W MSS Ingress VLAN STag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See MSS Ingress VLAN Stag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanStagParseEnable : 1; /* 1E.800B.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.800B.F R/W MSS Ingress VLAN QTag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See MSS Ingress VLAN QTag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanQtagParseEnable : 1; /* 1E.800B.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress MTU Size Control Register: 1E.800C */ +/* MSS Ingress MTU Size Control Register: 1E.800C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800C.F:0 R/W MSS Ingress Controlled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u0.bits_0.mssIngressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssIngressControlledPacketMtuSize : 16; /* 1E.800C.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800D.F:0 R/W MSS Ingress Uncontrolled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u1.bits_1.mssIngressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssIngressUncontrolledPacketMtuSize : 16; /* 1E.800D.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Control Register: 1E.800E */ +/* MSS Ingress Control Register: 1E.800E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Control Register */ + union + { + struct + { + /*! \brief 1E.800E.0 R/W MSS Ingress Soft Reset + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssIngressSoftReset : 1; /* 1E.800E.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.800E.1 R/W MSS Ingress Operation Point To Point + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressOperationPointToPoint + + Default = 0x0 + + 1 = Enable the SCI for authorization default + + + Notes: + The default SCI for authorization is configured in See MSS Ingress SCI Default [F:0] See MSS Ingress SCI Default [1F:10] , See MSS Ingress SCI Default [2F:20] , and See MSS Ingress SCI Default [3F:30] . */ + unsigned int mssIngressOperationPointToPoint : 1; /* 1E.800E.1 R/W Default = 0x0 */ + /* 1 = Enable the SCI for authorization default + */ + /*! \brief 1E.800E.2 R/W MSS Ingress Create SCI + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCreateSci + + Default = 0x0 + + 0 = SCI from IGPRC LUT + + + Notes: + If the SCI is not in the packet and this bit is set to 0, the SCI will be taken from the IGPRC LUT. */ + unsigned int mssIngressCreateSci : 1; /* 1E.800E.2 R/W Default = 0x0 */ + /* 0 = SCI from IGPRC LUT + */ + /*! \brief 1E.800E.3 R/W MSS Ingress Mask Short Length Error + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressMaskShortLengthError + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressMaskShortLengthError : 1; /* 1E.800E.3 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.4 R/W MSS Ingress Drop Kay Packet + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropKayPacket + + Default = 0x0 + + 1 = Drop KaY packets + + + Notes: + Decides whether KaY packets have to be dropped */ + unsigned int mssIngressDropKayPacket : 1; /* 1E.800E.4 R/W Default = 0x0 */ + /* 1 = Drop KaY packets + */ + /*! \brief 1E.800E.5 R/W MSS Ingress Drop IGPRC Miss + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropIgprcMiss + + Default = 0x0 + + 1 = Drop IGPRC miss packets + + + Notes: + Decides whether Ingress Pre-Security Classification (IGPRC) LUT miss packets are to be dropped */ + unsigned int mssIngressDropIgprcMiss : 1; /* 1E.800E.5 R/W Default = 0x0 */ + /* 1 = Drop IGPRC miss packets + */ + /*! \brief 1E.800E.6 R/W MSS Ingress Check ICV + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCheckIcv + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressCheckIcv : 1; /* 1E.800E.6 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.7 R/W MSS Ingress Clear Global Time + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + Notes: + Clear global time */ + unsigned int mssIngressClearGlobalTime : 1; /* 1E.800E.7 R/W Default = 0x0 */ + /* 1 = Clear global time + */ + /*! \brief 1E.800E.8 R/W MSS Ingress Clear Count + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearCount + + Default = 0x0 + + 1 = Clear all MIB counters + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssIngressClearCount : 1; /* 1E.800E.8 R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + */ + /*! \brief 1E.800E.9 R/W MSS Ingress High Priority + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssIngressHighPriority : 1; /* 1E.800E.9 R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + */ + /*! \brief 1E.800E.A R/W MSS Ingress Remove SECTag + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressRemoveSectag + + Default = 0x0 + + 1 = Enable removal of SECTag + + + Notes: + If this bit is set and either of the following two conditions occurs, the SECTag will be removed. + Controlled packet and either the SA or SC is invalid. + IGPRC miss. */ + unsigned int mssIngressRemoveSectag : 1; /* 1E.800E.A R/W Default = 0x0 */ + /* 1 = Enable removal of SECTag + */ + /*! \brief 1E.800E.C:B R/W MSS Ingress Global Validate Frames [1:0] + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressGlobalValidateFrames + + Default = 0x0 + + Default validate frames configuration + + + Notes: + If the SC is invalid or if an IGPRC miss packet condition occurs, this default will be used for the validate frames configuration instead of the validate frame entry in the Ingress SC Table (IGSCT). */ + unsigned int mssIngressGlobalValidateFrames : 2; /* 1E.800E.C:B R/W Default = 0x0 */ + /* Default validate frames configuration + */ + /*! \brief 1E.800E.D R/W MSS Ingress ICV LSB 8 Bytes Enable + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssIngressIcvLsb_8BytesEnable : 1; /* 1E.800E.D R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + unsigned int reserved0 : 2; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Control Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Control Register: 1E.8010 */ +/* MSS Ingress SA Control Register: 1E.8010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8010.F:0 R/W MSS Ingress SA Threshold LSW [F:0] + AQ_MssIngressSaControlRegister_HHD.u0.bits_0.mssIngressSaThresholdLSW + + Default = 0x0000 + + SA threshold bits 15:0 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdLSW : 16; /* 1E.8010.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8011.F:0 R/W MSS Ingress SA Threshold MSW [1F:10] + AQ_MssIngressSaControlRegister_HHD.u1.bits_1.mssIngressSaThresholdMSW + + Default = 0x0000 + + SA threshold bits 31:16 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdMSW : 16; /* 1E.8011.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Status Register: 1E.802E */ +/* MSS Ingress Interrupt Status Register: 1E.802E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.802E.0 COW MSS Master Ingress Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssMasterIngressInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssMasterIngressInterrupt : 1; /* 1E.802E.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.1 COW MSS Ingress SA Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssIngressSaExpiredInterrupt : 1; /* 1E.802E.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.2 COW MSS Ingress SA Threshold Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssIngressSaThresholdExpiredInterrupt : 1; /* 1E.802E.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.3 COW MSS Ingress ICV Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIcvErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressIcvErrorInterrupt : 1; /* 1E.802E.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.4 COW MSS Ingress Replay Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressReplayErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressReplayErrorInterrupt : 1; /* 1E.802E.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.5 COW MSS Ingress MIB Saturation Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssIngressMibSaturationInterrupt : 1; /* 1E.802E.5 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.6 COW MSS Ingress ECC Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressEccErrorInterrupt : 1; /* 1E.802E.6 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.7 COW MSS Ingress TCI E/C Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This error occurs when the TCI E bit is 1 and the TCI C bit is 0. The packet is not dropped, uncontrolled, or untagged. */ + unsigned int mssIngressTciE_cErrorInterrupt : 1; /* 1E.802E.7 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.8 COW MSS Ingress IGPOC Miss Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIgpocMissInterrupt + + Default = 0x0 + + 1 = Interrupt + + */ + unsigned int mssIngressIgpocMissInterrupt : 1; /* 1E.802E.8 COW Default = 0x0 */ + /* 1 = Interrupt + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Mask Register: 1E.8030 */ +/* MSS Ingress Interrupt Mask Register: 1E.8030 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + /*! \brief 1E.8030.0 R/W MSS Ingress Master Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMasterInterruptEnable : 1; /* 1E.8030.0 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.1 R/W MSS Ingress SA Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaExpiredInterruptEnable : 1; /* 1E.8030.1 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.2 R/W MSS Ingress SA Threshold Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaThresholdExpiredInterruptEnable : 1; /* 1E.8030.2 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.3 R/W MSS Ingress ICV Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIcvErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIcvErrorInterruptEnable : 1; /* 1E.8030.3 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.4 R/W MSS Ingress Replay Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressReplayErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressReplayErrorInterruptEnable : 1; /* 1E.8030.4 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.5 R/W MSS Ingress MIB Saturation Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMibSaturationInterruptEnable : 1; /* 1E.8030.5 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.6 R/W MSS Ingress ECC Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressEccErrorInterruptEnable : 1; /* 1E.8030.6 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.7 R/W MSS Ingress TCI E/C Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressTciE_cErrorInterruptEnable : 1; /* 1E.8030.7 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.8 R/W MSS Ingress IGPOC Miss Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIgpocMissInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIgpocMissInterruptEnable : 1; /* 1E.8030.8 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/* MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8032.F:0 COW MSS Ingress SA ICV Error LSW [F:0] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u0.bits_0.mssIngressSaIcvErrorLSW + + Default = 0x0000 + + SA ICV error bits 15:0 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorLSW : 16; /* 1E.8032.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8033.F:0 COW MSS Ingress SA ICV Error MSW [1F:10] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u1.bits_1.mssIngressSaIcvErrorMSW + + Default = 0x0000 + + SA ICV error bits 31:16 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorMSW : 16; /* 1E.8033.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaIcvErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/* MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8034.F:0 COW MSS Ingress SA Replay Error LSW [F:0] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u0.bits_0.mssIngressSaReplayErrorLSW + + Default = 0x0000 + + SA replay error bits 15:0 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorLSW : 16; /* 1E.8034.F:0 COW Default = 0x0000 */ + /* SA replay error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8035.F:0 COW MSS Ingress SA Replay Error MSW [1F:10] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u1.bits_1.mssIngressSaReplayErrorMSW + + Default = 0x0000 + + SA replay error bits 31:16 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorMSW : 16; /* 1E.8035.F:0 COW Default = 0x0000 */ + /* SA replay error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaReplayErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Expired Status Register: 1E.8036 */ +/* MSS Ingress SA Expired Status Register: 1E.8036 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8036.F:0 ROS MSS Ingress SA Expired LSW [F:0] + AQ_MssIngressSaExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredLSW : 16; /* 1E.8036.F:0 ROS Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8037.F:0 ROS MSS Ingress SA Expired MSW [1F:10] + AQ_MssIngressSaExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredMSW : 16; /* 1E.8037.F:0 ROS Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/* MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8038.F:0 ROS MSS Ingress SA Threshold Expired LSW [F:0] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredLSW : 16; /* 1E.8038.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8039.F:0 ROS MSS Ingress SA Threshold Expired MSW [1F:10] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredMSW : 16; /* 1E.8039.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/* MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803A.F:0 R/W MSS Ingress SA ECC Error Interrupt LSW [F:0] + AQ_MssIngressEccInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptLSW : 16; /* 1E.803A.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803B.F:0 R/W MSS Ingress SA ECC Error Interrupt MSW [1F:10] + AQ_MssIngressEccInterruptStatusRegister_HHD.u1.bits_1.mssIngressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptMSW : 16; /* 1E.803B.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Address Control Register: 1E.8080 */ +/* MSS Ingress LUT Address Control Register: 1E.8080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.8080.8:0 R/W MSS Ingress LUT Address [8:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssIngressLutAddress : 9; /* 1E.8080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + unsigned int reserved0 : 3; + /*! \brief 1E.8080.F:C R/W MSS Ingress LUT Select [3:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Ingress Pre-Security MAC Control FIlter (IGPRCTLF) LUT + 0x1 : Ingress Pre-Security Classification LUT (IGPRC) + 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT + 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT + 0x4 : Ingress Post-Security Classification LUT (IGPOC) + 0x5 : Ingress Post-Security MAC Control Filter (IGPOCTLF) LUT + 0x6 : Ingress MIB (IGMIB) */ + unsigned int mssIngressLutSelect : 4; /* 1E.8080.F:C R/W Default = 0x0 */ + /* LUT select + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Control Register: 1E.8081 */ +/* MSS Ingress LUT Control Register: 1E.8081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Control Register */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.8081.E R/W MSS Ingress LUT Read + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutRead : 1; /* 1E.8081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + /*! \brief 1E.8081.F R/W MSS Ingress LUT Write + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutWrite : 1; /* 1E.8081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Data Control Register: 1E.80A0 */ +/* MSS Ingress LUT Data Control Register: 1E.80A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A0.F:0 R/W MSS Ingress LUT Data 0 [F:0] + AQ_MssIngressLutDataControlRegister_HHD.u0.bits_0.mssIngressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssIngressLutData_0 : 16; /* 1E.80A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A1.F:0 R/W MSS Ingress LUT Data 1 [1F:10] + AQ_MssIngressLutDataControlRegister_HHD.u1.bits_1.mssIngressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssIngressLutData_1 : 16; /* 1E.80A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A2.F:0 R/W MSS Ingress LUT Data 2 [2F:20] + AQ_MssIngressLutDataControlRegister_HHD.u2.bits_2.mssIngressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssIngressLutData_2 : 16; /* 1E.80A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A3.F:0 R/W MSS Ingress LUT Data 3 [3F:30] + AQ_MssIngressLutDataControlRegister_HHD.u3.bits_3.mssIngressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssIngressLutData_3 : 16; /* 1E.80A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A4.F:0 R/W MSS Ingress LUT Data 4 [4F:40] + AQ_MssIngressLutDataControlRegister_HHD.u4.bits_4.mssIngressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssIngressLutData_4 : 16; /* 1E.80A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A5.F:0 R/W MSS Ingress LUT Data 5 [5F:50] + AQ_MssIngressLutDataControlRegister_HHD.u5.bits_5.mssIngressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssIngressLutData_5 : 16; /* 1E.80A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A6.F:0 R/W MSS Ingress LUT Data 6 [6F:60] + AQ_MssIngressLutDataControlRegister_HHD.u6.bits_6.mssIngressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssIngressLutData_6 : 16; /* 1E.80A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A7.F:0 R/W MSS Ingress LUT Data 7 [7F:70] + AQ_MssIngressLutDataControlRegister_HHD.u7.bits_7.mssIngressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssIngressLutData_7 : 16; /* 1E.80A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A8.F:0 R/W MSS Ingress LUT Data 8 [8F:80] + AQ_MssIngressLutDataControlRegister_HHD.u8.bits_8.mssIngressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssIngressLutData_8 : 16; /* 1E.80A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A9.F:0 R/W MSS Ingress LUT Data 9 [9F:90] + AQ_MssIngressLutDataControlRegister_HHD.u9.bits_9.mssIngressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssIngressLutData_9 : 16; /* 1E.80A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AA.F:0 R/W MSS Ingress LUT Data 10 [AF:A0] + AQ_MssIngressLutDataControlRegister_HHD.u10.bits_10.mssIngressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssIngressLutData_10 : 16; /* 1E.80AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AB.F:0 R/W MSS Ingress LUT Data 11 [BF:B0] + AQ_MssIngressLutDataControlRegister_HHD.u11.bits_11.mssIngressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssIngressLutData_11 : 16; /* 1E.80AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AC.F:0 R/W MSS Ingress LUT Data 12 [CF:C0] + AQ_MssIngressLutDataControlRegister_HHD.u12.bits_12.mssIngressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssIngressLutData_12 : 16; /* 1E.80AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AD.F:0 R/W MSS Ingress LUT Data 13 [DF:D0] + AQ_MssIngressLutDataControlRegister_HHD.u13.bits_13.mssIngressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssIngressLutData_13 : 16; /* 1E.80AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AE.F:0 R/W MSS Ingress LUT Data 14 [EF:E0] + AQ_MssIngressLutDataControlRegister_HHD.u14.bits_14.mssIngressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssIngressLutData_14 : 16; /* 1E.80AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AF.F:0 R/W MSS Ingress LUT Data 15 [FF:F0] + AQ_MssIngressLutDataControlRegister_HHD.u15.bits_15.mssIngressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssIngressLutData_15 : 16; /* 1E.80AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B0.F:0 R/W MSS Ingress LUT Data 16 [10F:100] + AQ_MssIngressLutDataControlRegister_HHD.u16.bits_16.mssIngressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssIngressLutData_16 : 16; /* 1E.80B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B1.F:0 R/W MSS Ingress LUT Data 17 [11F:110] + AQ_MssIngressLutDataControlRegister_HHD.u17.bits_17.mssIngressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssIngressLutData_17 : 16; /* 1E.80B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B2.F:0 R/W MSS Ingress LUT Data 18 [12F:120] + AQ_MssIngressLutDataControlRegister_HHD.u18.bits_18.mssIngressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssIngressLutData_18 : 16; /* 1E.80B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B3.F:0 R/W MSS Ingress LUT Data 19 [13F:130] + AQ_MssIngressLutDataControlRegister_HHD.u19.bits_19.mssIngressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssIngressLutData_19 : 16; /* 1E.80B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B4.F:0 R/W MSS Ingress LUT Data 20 [14F:140] + AQ_MssIngressLutDataControlRegister_HHD.u20.bits_20.mssIngressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssIngressLutData_20 : 16; /* 1E.80B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B5.F:0 R/W MSS Ingress LUT Data 21 [15F:150] + AQ_MssIngressLutDataControlRegister_HHD.u21.bits_21.mssIngressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssIngressLutData_21 : 16; /* 1E.80B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B6.F:0 R/W MSS Ingress LUT Data 22 [16F:160] + AQ_MssIngressLutDataControlRegister_HHD.u22.bits_22.mssIngressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssIngressLutData_22 : 16; /* 1E.80B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B7.F:0 R/W MSS Ingress LUT Data 23 [17F:170] + AQ_MssIngressLutDataControlRegister_HHD.u23.bits_23.mssIngressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssIngressLutData_23 : 16; /* 1E.80B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; +} AQ_MssIngressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Control Register: 1E.9004 */ +/* MSM Line General Control Register: 1E.9004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Control Register */ + union + { + struct + { + /*! \brief 1E.9004.0 R/W MSM Line Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmLineTxEnable : 1; /* 1E.9004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + /*! \brief 1E.9004.1 R/W MSM Line Rx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmLineRxEnable : 1; /* 1E.9004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + unsigned int reserved0 : 1; + /*! \brief 1E.9004.3 R/W MSM Line WAN Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmLineWanMode : 1; /* 1E.9004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + /*! \brief 1E.9004.4 R/W MSM Line Promiscuous Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmLinePromiscuousMode : 1; /* 1E.9004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.9004.5 R/W MSM Line PAD Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmLinePadEnable : 1; /* 1E.9004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.9004.6 R/W MSM Line CRC Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmLineCrcForward : 1; /* 1E.9004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.9004.7 R/W MSM Line Pause Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmLinePauseForward : 1; /* 1E.9004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.9004.8 R/W MSM Line Pause Ignore + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmLinePauseIgnore : 1; /* 1E.9004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.9004.9 R/W MSM Line Tx Address Insert Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmLineTxAddressInsertEnable : 1; /* 1E.9004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.9004.A R/W MSM Line Tx CRC Append + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmLineTxCrcAppend : 1; /* 1E.9004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.9004.B R/W MSM Line Tx Pad Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmLineTxPadEnable : 1; /* 1E.9004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.9004.C R/WSC MSM Line Soft Reset + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmLineSoftReset : 1; /* 1E.9004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.9004.D R/W MSM Line Control Frame Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmLineControlFrameEnable : 1; /* 1E.9004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.9004.E R/W MSM Line Rx Error Discard + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmLineRxErrorDiscard : 1; /* 1E.9004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.9004.F R/W MSM Line PHY Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmLinePhyTxEnable : 1; /* 1E.9004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Control Register */ + union + { + struct + { + /*! \brief 1E.9005.0 R/W MSM Line Force Send IDLE + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmLineForceSendIdle : 1; /* 1E.9005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + /*! \brief 1E.9005.1 R/W MSM Line Length Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmLineLengthCheckDisable : 1; /* 1E.9005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.9005.2 R/W MSM Line IDLE Column Count Extend + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmLineIdleColumnCountExtend : 1; /* 1E.9005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.9005.3 R/W MSM Line Priority Flow Control Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLinePriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmLinePriorityFlowControlEnable : 1; /* 1E.9005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + unsigned int reserved2 : 1; + /*! \brief 1E.9005.5 R/W MSM Line SFD Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmLineSfdCheckDisable : 1; /* 1E.9005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved1 : 1; + /*! \brief 1E.9005.7 R/W MSM Line Tx Low Power IDLE Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmLineTxLowPowerIdleEnable : 1; /* 1E.9005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line FIFO Control Register: 1E.900E */ +/* MSM Line FIFO Control Register: 1E.900E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.900E.7:0 R/W MSM Line Rx FIFO Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u0.bits_0.msmLineRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoFullThreshold : 8; /* 1E.900E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.900F.7:0 R/W MSM Line Rx FIFO Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u1.bits_1.msmLineRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoEmptyThreshold : 8; /* 1E.900F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9010.5:0 R/W MSM Line Tx FIFO Full Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u2.bits_2.msmLineTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoFullThreshold : 6; /* 1E.9010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + unsigned int reserved0 : 10; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9011.5:0 R/W MSM Line Tx FIFO Empty Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u3.bits_3.msmLineTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoEmptyThreshold : 6; /* 1E.9011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + unsigned int reserved0 : 10; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9012.7:0 ROS MSM Line Rx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u4.bits_4.msmLineRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostFullThreshold : 8; /* 1E.9012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9013.7:0 ROS MSM Line Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u5.bits_5.msmLineRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostEmptyThreshold : 8; /* 1E.9013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9014.7:0 ROS MSM Line Tx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u6.bits_6.msmLineTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostFullThreshold : 8; /* 1E.9014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9015.7:0 ROS MSM Line Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u7.bits_7.msmLineTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostEmptyThreshold : 8; /* 1E.9015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmLineFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Status Register: 1E.9020 */ +/* MSM Line General Status Register: 1E.9020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Status Register */ + union + { + struct + { + /*! \brief 1E.9020.0 BLH MSM Line Rx Local Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxLocalFault : 1; /* 1E.9020.0 BLH */ + /* Rx local fault detected */ + /*! \brief 1E.9020.1 BLH MSM Line Rx Remote Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxRemoteFault : 1; /* 1E.9020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.9020.2 RO MSM Line PHY Loss of Signal + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLinePhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmLinePhyLossOfSignal : 1; /* 1E.9020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.9020.3 R/W MSM Line Timestamp Available + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmLineTimestampAvailable : 1; /* 1E.9020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.9020.4 RO MSM Line Rx Low Power IDLE + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmLineRxLowPowerIdle : 1; /* 1E.9020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.9020.5 RO MSM Line Tx FIFO Empty + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmLineTxFifoEmpty : 1; /* 1E.9020.5 RO */ + /* Tx FIFO empty */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx IPG Control Register: 1E.9022 */ +/* MSM Line Tx IPG Control Register: 1E.9022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.9022.5:0 R/W MSM Line Tx IPG Length [5:0] + AQ_MsmLineTxIpgControlRegister_HHD.u0.bits_0.msmLineTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmLineTxIpgLength : 6; /* 1E.9022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.9023.F:0 MSM Line Tx IPG Reserved + AQ_MsmLineTxIpgControlRegister_HHD.u1.bits_1.msmLineTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmLineTxIpgReserved : 16; /* 1E.9023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/* MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9040.F:0 ROS MSM Line Tx Good Frames Counter 0 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_0 : 16; /* 1E.9040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9041.F:0 ROS MSM Line Tx Good Frames Counter 1 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_1 : 16; /* 1E.9041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/* MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9044.F:0 ROS MSM Line Rx Good Frames Counter 0 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_0 : 16; /* 1E.9044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9045.F:0 ROS MSM Line Rx Good Frames Counter 1 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_1 : 16; /* 1E.9045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/* MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9048.F:0 ROS MSM Line FCS Error Counter 0 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmLineFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_0 : 16; /* 1E.9048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9049.F:0 ROS MSM Line FCS Error Counter 1 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmLineFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_1 : 16; /* 1E.9049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/* MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904C.F:0 ROS MSM Line Alignment Error Counter 0 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmLineAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_0 : 16; /* 1E.904C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904D.F:0 ROS MSM Line Alignment Error Counter 1 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmLineAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_1 : 16; /* 1E.904D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/* MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9050.F:0 ROS MSM Line Tx Pause Frames Counter 0 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_0 : 16; /* 1E.9050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9051.F:0 ROS MSM Line Tx Pause Frames Counter 1 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_1 : 16; /* 1E.9051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/* MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9054.F:0 ROS MSM Line Rx Pause Frames Counter 0 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_0 : 16; /* 1E.9054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9055.F:0 ROS MSM Line Rx Pause Frames Counter 1 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_1 : 16; /* 1E.9055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/* MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9058.F:0 ROS MSM Line Rx Too Long Errors Counter 0 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmLineRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_0 : 16; /* 1E.9058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9059.F:0 ROS MSM Line Rx Too Long Errors Counter 1 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmLineRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_1 : 16; /* 1E.9059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/* MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905C.F:0 ROS MSM Line Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmLineRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_0 : 16; /* 1E.905C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905D.F:0 ROS MSM Line Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmLineRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_1 : 16; /* 1E.905D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/* MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9060.F:0 ROS MSM Line Tx VLAN Frames Counter 0 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_0 : 16; /* 1E.9060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9061.F:0 ROS MSM Line Tx VLAN Frames Counter 1 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_1 : 16; /* 1E.9061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/* MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9064.F:0 ROS MSM Line Rx VLAN Frames Counter 0 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_0 : 16; /* 1E.9064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9065.F:0 ROS MSM Line Rx VLAN Frames Counter 1 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_1 : 16; /* 1E.9065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Octets Counter Register: 1E.9068 */ +/* MSM Line Tx Octets Counter Register: 1E.9068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9068.F:0 ROS MSM Line Tx Octets Counter 0 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u0.bits_0.msmLineTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_0 : 16; /* 1E.9068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9069.F:0 ROS MSM Line Tx Octets Counter 1 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u1.bits_1.msmLineTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_1 : 16; /* 1E.9069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906A.F:0 ROS MSM Line Tx Octets Counter 2 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u2.bits_2.msmLineTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_2 : 16; /* 1E.906A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906B.F:0 ROS MSM Line Tx Octets Counter 3 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u3.bits_3.msmLineTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_3 : 16; /* 1E.906B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmLineTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Octets Counter Register: 1E.906C */ +/* MSM Line Rx Octets Counter Register: 1E.906C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906C.F:0 ROS MSM Line Rx Octets Counter 0 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u0.bits_0.msmLineRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_0 : 16; /* 1E.906C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906D.F:0 ROS MSM Line Rx Octets Counter 1 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u1.bits_1.msmLineRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_1 : 16; /* 1E.906D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/* MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9070.F:0 ROS MSM Line Rx Unicast Frames Counter 0 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_0 : 16; /* 1E.9070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9071.F:0 ROS MSM Line Rx Unicast Frames Counter 1 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_1 : 16; /* 1E.9071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/* MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9074.F:0 ROS MSM Line Rx Multicast Frames Counter 0 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_0 : 16; /* 1E.9074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9075.F:0 ROS MSM Line Rx Multicast Frames Counter 1 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_1 : 16; /* 1E.9075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/* MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9078.F:0 ROS MSM Line Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_0 : 16; /* 1E.9078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9079.F:0 ROS MSM Line Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_1 : 16; /* 1E.9079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Errors Counter Register: 1E.907C */ +/* MSM Line Tx Errors Counter Register: 1E.907C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907C.F:0 ROS MSM Line Tx Errors Counter 0 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u0.bits_0.msmLineTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_0 : 16; /* 1E.907C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907D.F:0 ROS MSM Line Tx Errors Counter 1 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u1.bits_1.msmLineTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_1 : 16; /* 1E.907D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/* MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9084.F:0 ROS MSM Line Tx Unicast Frames Counter 0 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_0 : 16; /* 1E.9084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9085.F:0 ROS MSM Line Tx Unicast Frames Counter 1 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_1 : 16; /* 1E.9085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/* MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9088.F:0 ROS MSM Line Tx Multicast Frames Counter 0 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_0 : 16; /* 1E.9088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9089.F:0 ROS MSM Line Tx Multicast Frames Counter 1 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_1 : 16; /* 1E.9089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/* MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908C.F:0 ROS MSM Line Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_0 : 16; /* 1E.908C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908D.F:0 ROS MSM Line Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_1 : 16; /* 1E.908D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Errors Counter Register: 1E.90C8 */ +/* MSM Line Rx Errors Counter Register: 1E.90C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C8.F:0 ROS MSM Line Rx Errors Counter 0 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u0.bits_0.msmLineRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_0 : 16; /* 1E.90C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C9.F:0 ROS MSM Line Rx Errors Counter 1 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u1.bits_1.msmLineRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_1 : 16; /* 1E.90C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_HHD.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_HHD.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. Pin no longer brought out as deprecated. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_HHD.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved1 : 14; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_HHD.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_HHD.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_HHD.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C430.D:9 R/WPD Reserved Provisioning C430 [4:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.reservedProvisioningC430 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC430 : 5; /* 1E.C430.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + unsigned int reserved0 : 2; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C431.D:9 R/WPD Reserved Provisioning C431 [4:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.reservedProvisioningC431 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC431 : 5; /* 1E.C431.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + unsigned int reserved0 : 2; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C432.D:9 R/WPD Reserved Provisioning C432 [4:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.reservedProvisioningC432 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC432 : 5; /* 1E.C432.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + unsigned int reserved0 : 2; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_HHD.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + */ + unsigned int reserved0 : 15; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_14; + uint16_t word_14; + } u14; +} AQ_GlobalLedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved3 : 2; + unsigned int reserved2 : 1; + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + + + Notes: + When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_HHD.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + unsigned int reserved0 : 15; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C447.4:0 R/WPD MDIO Broadcast Address Configuration [4:0] + AQ_GlobalGeneralProvisioning_HHD.u7.bits_7.mdioBroadcastAddressConfiguration + + Provisionable Default = 0x1F + + Broadcast address + + + Notes: + Allows setting the broadcast address. By default this is set to 0x1F */ + unsigned int mdioBroadcastAddressConfiguration : 5; /* 1E.C447.4:0 R/WPD Provisionable Default = 0x1F */ + /* Broadcast address + */ + unsigned int reserved0 : 11; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C449.6:0 R/W MDIO Preamble Length [6:0] + AQ_GlobalGeneralProvisioning_HHD.u9.bits_9.mdioPreambleLength + + Default = 0x02 + + MDIO Preamble Length + + */ + unsigned int mdioPreambleLength : 7; /* 1E.C449.6:0 R/W Default = 0x02 */ + /* MDIO Preamble Length + */ + unsigned int reserved0 : 9; + } bits_9; + uint16_t word_9; + } u9; +} AQ_GlobalGeneralProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the dummy field used in some manufacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved0 : 5; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + + + Notes: + When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + */ + unsigned int reserved0 : 7; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + */ + unsigned int reserved0 : 14; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved1 : 4; + /*! \brief 1E.C453.4 R/W NVR Reset + AQ_GlobalNvrProvisioning_HHD.u3.bits_3.nvrReset + + Default = 0x0 + + 1 = Reset SPI + + */ + unsigned int nvrReset : 1; /* 1E.C453.4 R/W Default = 0x0 */ + /* 1 = Reset SPI + */ + unsigned int reserved0 : 11; + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalNvrProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved2 : 4; + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. + + NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + unsigned int reserved1 : 3; + unsigned int reserved0 : 5; + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + unsigned int reserved0 : 9; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + /*! \brief 1E.C472.5:2 R/WPD External VDD Change Request [3:0] + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.externalVddChangeRequest + + Provisionable Default = 0x0 + + The amount of VDD change requested by firmware, in mV (2's complement value). + + */ + unsigned int externalVddChangeRequest : 4; /* 1E.C472.5:2 R/WPD Provisionable Default = 0x0 */ + /* The amount of VDD change requested by firmware, in mV (2's complement value). + */ + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + This bit must be set if tuning of external power supply is desired. */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + unsigned int reserved1 : 7; + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + unsigned int reserved0 : 1; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C473.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. */ + unsigned int trainingSNR : 8; /* 1E.C473.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + /*! \brief 1E.C473.A:8 R/WPD Rate Transition Request [2:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.rateTransitionRequest + + Provisionable Default = 0x0 + + 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + + */ + unsigned int rateTransitionRequest : 3; /* 1E.C473.A:8 R/WPD Provisionable Default = 0x0 */ + /* 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + */ + unsigned int reserved0 : 5; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C474.0 R/W NVR Daisy Chain Kickstart + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.nvrDaisyChainKickstart + + Default = 0x0 + + 1 = Kickstart the Daisy Chain + + + Notes: + When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. */ + unsigned int nvrDaisyChainKickstart : 1; /* 1E.C474.0 R/W Default = 0x0 */ + /* 1 = Kickstart the Daisy Chain + */ + /*! \brief 1E.C474.F:1 R/WPD Reserved Provisioning 5 [F:1] + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.reservedProvisioning_5 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_5 : 15; /* 1E.C474.F:1 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved1 : 2; + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Internal reserved - do not modify + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Internal reserved - do not modify + */ + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + unsigned int reserved0 : 2; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C478.A:0 R/WPD Reserved Provisioning 9 [A:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.reservedProvisioning_9 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_9 : 11; /* 1E.C478.A:0 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + /*! \brief 1E.C478.E:B R/WPD DTE Drop Reporting Timer [3:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteDropReportingTimer + + Provisionable Default = 0x0 + + Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + + + Notes: + These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. */ + unsigned int dteDropReportingTimer : 4; /* 1E.C478.E:B R/WPD Provisionable Default = 0x0 */ + /* Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + */ + /*! \brief 1E.C478.F R/WPD DTE Enable + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteEnable + + Provisionable Default = 0x0 + + 1 = Enable DTE + 0 = Disable DTE + + */ + unsigned int dteEnable : 1; /* 1E.C478.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable DTE + 0 = Disable DTE + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C479.E:0 R/WPD Reserved Provisioning 10 [E:0] + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.reservedProvisioning_10 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_10 : 15; /* 1E.C479.E:0 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + /*! \brief 1E.C479.F R/WPD Power Up Stall + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.powerUpStall + + Provisionable Default = 0x0 + + 1 = Stall FW at Power Up + 0 = Unstall the FW + + + Notes: + This bit needs to be provisioned in Power Up Init for firmware to stall. */ + unsigned int powerUpStall : 1; /* 1E.C479.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Stall FW at Power Up + 0 = Unstall the FW + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47A.1:0 R/WPD Rate [1:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.rate + + Provisionable Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + + + Notes: + These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int rate : 2; /* 1E.C47A.1:0 R/WPD Provisionable Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + */ + /*! \brief 1E.C47A.2 R/WPD Reserved Provisioning 11a + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11a + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11a : 1; /* 1E.C47A.2 R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.3 R/WPD System I/F Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.systemI_fPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int systemI_fPacketGeneration : 1; /* 1E.C47A.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C47A.4 R/WPD Look-Aside Port Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.look_asidePortPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. + + NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int look_asidePortPacketGeneration : 1; /* 1E.C47A.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C47A.5 R/WPD MDI Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.mdiPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int mdiPacketGeneration : 1; /* 1E.C47A.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C47A.A:6 R/WPD Reserved Provisioning 11 [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11 + + Provisionable Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11 : 5; /* 1E.C47A.A:6 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.F:B R/WPD Loopback Control [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.loopbackControl + + Provisionable Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. + */ + unsigned int loopbackControl : 5; /* 1E.C47A.F:B R/WPD Provisionable Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47B.0 R/WPD Enable PTP + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enablePtp + + Provisionable Default = 0x0 + + 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enablePtp : 1; /* 1E.C47B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + */ + /*! \brief 1E.C47B.1 R/WPD Enable MACSec + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enableMacsec + + Provisionable Default = 0x0 + + 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enableMacsec : 1; /* 1E.C47B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + */ + /*! \brief 1E.C47B.F:2 R/WPD Reserved Provisioning 12 [D:0] + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.reservedProvisioning_12 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_12 : 14; /* 1E.C47B.F:2 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + } bits_11; + uint16_t word_11; + } u11; +} AQ_GlobalReservedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief PIF Mailbox Control: 1E.C47C */ +/* PIF Mailbox Control: 1E.C47C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47C.F:0 R/WPDuP PIF Mailbox Address [F:0] + AQ_PifMailboxControl_HHD.u0.bits_0.pifMailboxAddress + + Provisionable Default = 0x0000 + + The least 16 bits of the PIF address to read or write. + + */ + unsigned int pifMailboxAddress : 16; /* 1E.C47C.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The least 16 bits of the PIF address to read or write. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47D.F:0 R/WPDuP PIF Mailbox Data [F:0] + AQ_PifMailboxControl_HHD.u1.bits_1.pifMailboxData + + Provisionable Default = 0x0000 + + The data to be written, or that had been read. + + */ + unsigned int pifMailboxData : 16; /* 1E.C47D.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The data to be written, or that had been read. + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47E.7:0 R/WPDuP PIF Mailbox MMD [7:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxMMD + + Provisionable Default = 0x00 + + MMD (upper 8 bits) of the PID address to read or write. + + */ + unsigned int pifMailboxMMD : 8; /* 1E.C47E.7:0 R/WPDuP Provisionable Default = 0x00 */ + /* MMD (upper 8 bits) of the PID address to read or write. + */ + /*! \brief 1E.C47E.B:8 R/WPDuP PIF Mailbox Command Type [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxCommandType + + Provisionable Default = 0x0 + + 0 = No Action + 1 = Read + 2 = Write + + + Notes: + System SW writes non-zero value to start a PIF command. */ + unsigned int pifMailboxCommandType : 4; /* 1E.C47E.B:8 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = No Action + 1 = Read + 2 = Write + */ + /*! \brief 1E.C47E.F:C R/WPD Reserved PIF Mailbox Control 3 [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.reservedPifMailboxControl_3 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_3 : 4; /* 1E.C47E.F:C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47F.3:0 R/WPDuP PIF Mailbox Command Status [3:0] + AQ_PifMailboxControl_HHD.u3.bits_3.pifMailboxCommandStatus + + Provisionable Default = 0x0 + + 0 = Idle + 1 = Command completed + 2 = Command did not complete + + + Notes: + System SW should write 0 before writing Command Type to clear completion status */ + unsigned int pifMailboxCommandStatus : 4; /* 1E.C47F.3:0 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = Idle + 1 = Command completed + 2 = Command did not complete + */ + /*! \brief 1E.C47F.F:4 R/WPD Reserved PIF Mailbox Control 4 [B:0] + AQ_PifMailboxControl_HHD.u3.bits_3.reservedPifMailboxControl_4 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_4 : 12; /* 1E.C47F.F:4 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_PifMailboxControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 0 Provisioning: 1E.C485 */ +/* Global SMBus 0 Provisioning: 1E.C485 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 0 Provisioning */ + union + { + struct + { + unsigned int reserved1 : 1; + /*! \brief 1E.C485.7:1 R/W SMB 0 Slave Address [7:1] + AQ_GlobalSmbus_0Provisioning_HHD.u0.bits_0.smb_0SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_0SlaveAddress : 7; /* 1E.C485.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_0Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 1 Provisioning: 1E.C495 */ +/* Global SMBus 1 Provisioning: 1E.C495 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 1 Provisioning */ + union + { + struct + { + unsigned int reserved1 : 1; + /*! \brief 1E.C495.7:1 R/W SMB 1 Slave Address [7:1] + AQ_GlobalSmbus_1Provisioning_HHD.u0.bits_0.smb_1SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_1SlaveAddress : 7; /* 1E.C495.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_1Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global EEE Provisioning: 1E.C4A0 */ +/* Global EEE Provisioning: 1E.C4A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global EEE Provisioning */ + union + { + struct + { + /*! \brief 1E.C4A0.0 R/WPD EEE Mode + AQ_GlobalEeeProvisioning_HHD.u0.bits_0.eeeMode + + Provisionable Default = 0x0 + + 1 = EEE mode of operation + + + Notes: + EEE mode of operation (0=disable, 1=enable, default:0) */ + unsigned int eeeMode : 1; /* 1E.C4A0.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = EEE mode of operation + */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalEeeProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairDStatus + + + + [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + Notes: + This register summarizes the worst impairment on Pair D. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairCStatus + + + + [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + Notes: + This register summarizes the worst impairment on Pair C. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairBStatus + + + + [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + Notes: + This register summarizes the worst impairment on Pair B. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairAStatus + + + + [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + Notes: + This register summarizes the worst impairment on Pair A. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u6.bits_6.reserved_1 + + + + Reserved for future use + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_GlobalCableDiagnosticStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_HHD.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_HHD.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_HHD.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes + 1E.C470.4, Cable diagnostics + 1E.C47A.F:B, Loopback Control + 1E.C47A.4:2, Packet generation */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_HHD.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + unsigned int reserved4 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_HHD.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_HHD.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved2 : 3; + /*! \brief 1E.C840.D RO DC_MASTER_N + AQ_GlobalPinStatus_HHD.u0.bits_0.dcMasterN + + + + Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH + */ + unsigned int dcMasterN : 1; /* 1E.C840.D RO */ + /* Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH */ + unsigned int reserved1 : 1; + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_HHD.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_HHD.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_4 + + + + Reserved + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_3 + + + + Reserved + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_2 + + + + Reserved + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_1 + + + + Reserved + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_8 + + + + Reserved + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_7 + + + + Reserved + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_6 + + + + Reserved + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_5 + + + + Reserved + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_12 + + + + Reserved + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_11 + + + + Reserved + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_10 + + + + Reserved + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_9 + + + + Reserved + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_16 + + + + Reserved + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_15 + + + + Reserved + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_14 + + + + Reserved + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_13 + + + + Reserved + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.reservedStatus_0 + + + + Reserved + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.3:0 ROSPD Provisioning ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.provisioningID + + Provisionable Default = 0x0 + + Provisioning ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int provisioningID : 4; /* 1E.C885.3:0 ROSPD Provisionable Default = 0x0 */ + /* Provisioning ID + */ + /*! \brief 1E.C885.7:4 ROSPD Firmware Build ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.firmwareBuildID + + Provisionable Default = 0x0 + + Firmware Build ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int firmwareBuildID : 4; /* 1E.C885.7:4 ROSPD Provisionable Default = 0x0 */ + /* Firmware Build ID + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW [F:0] + AQ_GlobalReservedStatus_HHD.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C887.D:0 RO Reserved Status 3 [D:0] + AQ_GlobalReservedStatus_HHD.u2.bits_2.reservedStatus_3 + + + + Reserved for future use + + */ + unsigned int reservedStatus_3 : 14; /* 1E.C887.D:0 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C887.E ROS Power Up Stall Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.powerUpStallStatus + + Default = 0x0 + + 1 = FW is stalled at power up + 0 = Firmware is unstalled + + */ + unsigned int powerUpStallStatus : 1; /* 1E.C887.E ROS Default = 0x0 */ + /* 1 = FW is stalled at power up + 0 = Firmware is unstalled + */ + /*! \brief 1E.C887.F ROS DTE Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.dteStatus + + Default = 0x0 + + 1 = Need power + 0 = Don't need power + + */ + unsigned int dteStatus : 1; /* 1E.C887.F ROS Default = 0x0 */ + /* 1 = Need power + 0 = Don't need power + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C888.1:0 RO Rate [1:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.rate + + Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + + + Notes: + These bits report the selected rate for the loopback and packet generation. */ + unsigned int rate : 2; /* 1E.C888.1:0 RO Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + */ + /*! \brief 1E.C888.2 RO Reserved Status 4a + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4a + + Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedStatus_4a : 1; /* 1E.C888.2 RO Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.3 RO System I/F Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.systemI_fPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. */ + unsigned int systemI_fPacketGenerationStatus : 1; /* 1E.C888.3 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C888.4 RO Look-Aside Port Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.look_asidePortPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. */ + unsigned int look_asidePortPacketGenerationStatus : 1; /* 1E.C888.4 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C888.5 RO MDI Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.mdiPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. */ + unsigned int mdiPacketGenerationStatus : 1; /* 1E.C888.5 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C888.A:6 RO Reserved Status 4 [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4 + + Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedStatus_4 : 5; /* 1E.C888.A:6 RO Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.F:B RO Loopback Status [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.loopbackStatus + + Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. + + */ + unsigned int loopbackStatus : 5; /* 1E.C888.F:B RO Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalReservedStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_HHD.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_HHD.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + unsigned int reserved2 : 1; + unsigned int reserved1 : 6; + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_HHD.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + /*! \brief 1E.CC01.A:8 LH Reserved Alarms [2:0] + AQ_GlobalAlarms_HHD.u1.bits_1.reservedAlarms + + + + Reserved + + + */ + unsigned int reservedAlarms : 3; /* 1E.CC01.A:8 LH */ + /* Reserved + + */ + /*! \brief 1E.CC01.B LH DTE Status Change + AQ_GlobalAlarms_HHD.u1.bits_1.dteStatusChange + + + + 1 = DTE status change + + + Notes: + Change in 1E.C887[F]. */ + unsigned int dteStatusChange : 1; /* 1E.CC01.B LH */ + /* 1 = DTE status change + */ + /*! \brief 1E.CC01.C LH IP Phone Detect + AQ_GlobalAlarms_HHD.u1.bits_1.ipPhoneDetect + + + + 1 = IP Phone Detect + + + Notes: + Assertion of this bit means that the presence of an IP Phone has been detected. */ + unsigned int ipPhoneDetect : 1; /* 1E.CC01.C LH */ + /* 1 = IP Phone Detect + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_HHD.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_HHD.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_HHD.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_HHD.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_HHD.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_HHD.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_HHD.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_HHD.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.A:8 R/WPD Reserved Alarms Mask [2:0] + AQ_GlobalInterruptMask_HHD.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 3; /* 1E.D401.A:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.B R/WPD DTE Status Change Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.dteStatusChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int dteStatusChangeMask : 1; /* 1E.D401.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.C R/WPD IP Phone Detect Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.ipPhoneDetectMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int ipPhoneDetectMask : 1; /* 1E.D401.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_HHD.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_HHD; + +#endif +/*@}*/ +/*@}*/ diff --git a/firmware/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h b/firmware/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h new file mode 100755 index 0000000..d9a4429 --- /dev/null +++ b/firmware/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h @@ -0,0 +1,4413 @@ +/*! \file +* This file contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ + +/*! \defgroup Global_registers_Defines Global Registers Defines +* This module contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/regMapParser/src/gencheaders.py $ +* +* $Revision: #10 $ +* +* $DateTime: 2014/04/08 16:55:58 $ +* +* $Author: joshd $ +* +* $Label: $ +* +* Description: +* +* This file contains the compiler assist macros for the registers contained in the Global Registers block. +* +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_HHD_GLOBAL_REGS_DEFINES_HEADER +#define AQ_HHD_GLOBAL_REGS_DEFINES_HEADER + + +/*-----------------------------------------------------------------------------*/ +/*Access macro definitions */ +/*-----------------------------------------------------------------------------*/ +/*! \brief Base register address of structure AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_baseRegisterAddress 0x0000 +/*! \brief MMD address of structure AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure softReset in AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_softReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure softReset in AQ_GlobalStandardControl_1_HHD */ +#define bits_AQ_GlobalStandardControl_1_HHD_softReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure softReset in AQ_GlobalStandardControl_1_HHD */ +#define word_AQ_GlobalStandardControl_1_HHD_softReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowPower in AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_lowPower 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowPower in AQ_GlobalStandardControl_1_HHD */ +#define bits_AQ_GlobalStandardControl_1_HHD_lowPower u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowPower in AQ_GlobalStandardControl_1_HHD */ +#define word_AQ_GlobalStandardControl_1_HHD_lowPower u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_baseRegisterAddress 0x0002 +/*! \brief MMD address of structure AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define bits_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define word_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define bits_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define word_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_baseRegisterAddress 0x0005 +/*! \brief MMD address of structure AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_tcPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_tcPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_tcPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_wisPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_wisPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_wisPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_baseRegisterAddress 0x0006 +/*! \brief MMD address of structure AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardStatus_2_HHD */ +#define AQ_GlobalStandardStatus_2_HHD_baseRegisterAddress 0x0008 +/*! \brief MMD address of structure AQ_GlobalStandardStatus_2_HHD */ +#define AQ_GlobalStandardStatus_2_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ +#define AQ_GlobalStandardStatus_2_HHD_devicePresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ +#define bits_AQ_GlobalStandardStatus_2_HHD_devicePresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ +#define word_AQ_GlobalStandardStatus_2_HHD_devicePresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_baseRegisterAddress 0x000E +/*! \brief MMD address of structure AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define bits_AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define word_AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define bits_AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define word_AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_baseRegisterAddress 0x0020 +/*! \brief MMD address of structure AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define bits_AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define word_AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define bits_AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define word_AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_baseRegisterAddress 0x0100 +/*! \brief MMD address of structure AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_freezeNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_freezeNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_freezeNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_resetNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_resetNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_resetNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrBurst 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrBurst u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrBurst u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrOpcode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrOpcode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrOpcode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrDataLSW u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_baseRegisterAddress 0x0200 +/*! \brief MMD address of structure AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable 6 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable u6.word_6 + +/*! \brief Base register address of structure AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_baseRegisterAddress 0x0300 +/*! \brief MMD address of structure AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define bits_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define word_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define bits_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define word_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_baseRegisterAddress 0x5002 +/*! \brief MMD address of structure AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressClearCounter 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressClearCounter u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressClearCounter u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressHighPriority 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressHighPriority u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressHighPriority u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressGcmStart 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressGcmStart u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressGcmStart u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressSoftReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressVlanTpid_0Register_HHD */ +#define AQ_MssEgressVlanTpid_0Register_HHD_baseRegisterAddress 0x5008 +/*! \brief MMD address of structure AQ_MssEgressVlanTpid_0Register_HHD */ +#define AQ_MssEgressVlanTpid_0Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ +#define AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ +#define bits_AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ +#define word_AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressVlanTpid_1Register_HHD */ +#define AQ_MssEgressVlanTpid_1Register_HHD_baseRegisterAddress 0x500A +/*! \brief MMD address of structure AQ_MssEgressVlanTpid_1Register_HHD */ +#define AQ_MssEgressVlanTpid_1Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ +#define AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ +#define bits_AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ +#define word_AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_baseRegisterAddress 0x500C +/*! \brief MMD address of structure AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_baseRegisterAddress 0x500E +/*! \brief MMD address of structure AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ +#define bits_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ +#define word_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ +#define bits_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ +#define word_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_baseRegisterAddress 0x5010 +/*! \brief MMD address of structure AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define word_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define word_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_baseRegisterAddress 0x505C +/*! \brief MMD address of structure AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_baseRegisterAddress 0x505E +/*! \brief MMD address of structure AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_baseRegisterAddress 0x5060 +/*! \brief MMD address of structure AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_baseRegisterAddress 0x5062 +/*! \brief MMD address of structure AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_baseRegisterAddress 0x5064 +/*! \brief MMD address of structure AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_baseRegisterAddress 0x5080 +/*! \brief MMD address of structure AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ +#define bits_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ +#define word_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ +#define bits_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ +#define word_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_baseRegisterAddress 0x5081 +/*! \brief MMD address of structure AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ +#define bits_AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ +#define word_AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ +#define bits_AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ +#define word_AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_baseRegisterAddress 0x50A0 +/*! \brief MMD address of structure AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 4 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 5 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 6 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 7 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 8 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 9 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 10 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 11 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 12 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 13 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 14 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 u14.bits_14 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 u14.word_14 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 15 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 u15.bits_15 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 u15.word_15 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 16 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 u16.bits_16 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 u16.word_16 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 17 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 u17.bits_17 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 u17.word_17 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 18 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 u18.bits_18 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 u18.word_18 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 19 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 u19.bits_19 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 u19.word_19 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 20 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 u20.bits_20 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 u20.word_20 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 21 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 u21.bits_21 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 u21.word_21 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 22 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 u22.bits_22 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 u22.word_22 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 23 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 u23.bits_23 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 u23.word_23 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 24 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 u24.bits_24 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 u24.word_24 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 25 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 u25.bits_25 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 u25.word_25 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 26 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 u26.bits_26 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 u26.word_26 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 27 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 u27.bits_27 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 u27.word_27 + +/*! \brief Base register address of structure AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_baseRegisterAddress 0x6004 +/*! \brief MMD address of structure AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_baseRegisterAddress 0x600E +/*! \brief MMD address of structure AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold 5 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold 6 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold 7 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold u7.word_7 + +/*! \brief Base register address of structure AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_baseRegisterAddress 0x6020 +/*! \brief MMD address of structure AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault u0.word_0 + +/*! \brief Base register address of structure AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_baseRegisterAddress 0x6022 +/*! \brief MMD address of structure AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define bits_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define word_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define bits_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define word_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x6040 +/*! \brief MMD address of structure AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x6044 +/*! \brief MMD address of structure AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_baseRegisterAddress 0x6048 +/*! \brief MMD address of structure AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_baseRegisterAddress 0x604C +/*! \brief MMD address of structure AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x6050 +/*! \brief MMD address of structure AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x6054 +/*! \brief MMD address of structure AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_baseRegisterAddress 0x6058 +/*! \brief MMD address of structure AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_baseRegisterAddress 0x605C +/*! \brief MMD address of structure AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x6060 +/*! \brief MMD address of structure AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x6064 +/*! \brief MMD address of structure AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_baseRegisterAddress 0x6068 +/*! \brief MMD address of structure AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 u3.word_3 + +/*! \brief Base register address of structure AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_baseRegisterAddress 0x606C +/*! \brief MMD address of structure AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x6070 +/*! \brief MMD address of structure AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x6074 +/*! \brief MMD address of structure AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x6078 +/*! \brief MMD address of structure AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_baseRegisterAddress 0x607C +/*! \brief MMD address of structure AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x6084 +/*! \brief MMD address of structure AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x6088 +/*! \brief MMD address of structure AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x608C +/*! \brief MMD address of structure AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_baseRegisterAddress 0x60C8 +/*! \brief MMD address of structure AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressVlanTpid_0Register_HHD */ +#define AQ_MssIngressVlanTpid_0Register_HHD_baseRegisterAddress 0x8006 +/*! \brief MMD address of structure AQ_MssIngressVlanTpid_0Register_HHD */ +#define AQ_MssIngressVlanTpid_0Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ +#define AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ +#define bits_AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ +#define word_AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressVlanTpid_1Register_HHD */ +#define AQ_MssIngressVlanTpid_1Register_HHD_baseRegisterAddress 0x8008 +/*! \brief MMD address of structure AQ_MssIngressVlanTpid_1Register_HHD */ +#define AQ_MssIngressVlanTpid_1Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ +#define AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ +#define bits_AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ +#define word_AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_baseRegisterAddress 0x800A +/*! \brief MMD address of structure AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_baseRegisterAddress 0x800C +/*! \brief MMD address of structure AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define word_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define word_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_baseRegisterAddress 0x800E +/*! \brief MMD address of structure AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressHighPriority 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressHighPriority u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressHighPriority u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressClearCount 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressClearCount u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressClearCount u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressCreateSci 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressCreateSci u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressCreateSci u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressSoftReset u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_baseRegisterAddress 0x8010 +/*! \brief MMD address of structure AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ +#define bits_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ +#define word_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ +#define bits_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ +#define word_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_baseRegisterAddress 0x802E +/*! \brief MMD address of structure AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_baseRegisterAddress 0x8030 +/*! \brief MMD address of structure AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_baseRegisterAddress 0x8032 +/*! \brief MMD address of structure AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_baseRegisterAddress 0x8034 +/*! \brief MMD address of structure AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_baseRegisterAddress 0x8036 +/*! \brief MMD address of structure AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_baseRegisterAddress 0x8038 +/*! \brief MMD address of structure AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_baseRegisterAddress 0x803A +/*! \brief MMD address of structure AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_baseRegisterAddress 0x8080 +/*! \brief MMD address of structure AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ +#define bits_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ +#define word_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ +#define bits_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ +#define word_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_baseRegisterAddress 0x8081 +/*! \brief MMD address of structure AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ +#define bits_AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ +#define word_AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ +#define bits_AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ +#define word_AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_baseRegisterAddress 0x80A0 +/*! \brief MMD address of structure AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 4 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 5 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 6 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 7 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 8 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 9 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 10 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 11 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 12 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 13 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 14 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 u14.bits_14 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 u14.word_14 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 15 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 u15.bits_15 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 u15.word_15 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 16 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 u16.bits_16 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 u16.word_16 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 17 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 u17.bits_17 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 u17.word_17 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 18 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 u18.bits_18 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 u18.word_18 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 19 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 u19.bits_19 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 u19.word_19 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 20 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 u20.bits_20 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 u20.word_20 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 21 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 u21.bits_21 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 u21.word_21 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 22 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 u22.bits_22 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 u22.word_22 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 23 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 u23.bits_23 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 u23.word_23 + +/*! \brief Base register address of structure AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_baseRegisterAddress 0x9004 +/*! \brief MMD address of structure AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_baseRegisterAddress 0x900E +/*! \brief MMD address of structure AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold 5 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold 6 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold 7 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold u7.word_7 + +/*! \brief Base register address of structure AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_baseRegisterAddress 0x9020 +/*! \brief MMD address of structure AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault u0.word_0 + +/*! \brief Base register address of structure AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_baseRegisterAddress 0x9022 +/*! \brief MMD address of structure AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ +#define bits_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ +#define word_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ +#define bits_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ +#define word_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x9040 +/*! \brief MMD address of structure AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x9044 +/*! \brief MMD address of structure AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_baseRegisterAddress 0x9048 +/*! \brief MMD address of structure AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_baseRegisterAddress 0x904C +/*! \brief MMD address of structure AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x9050 +/*! \brief MMD address of structure AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x9054 +/*! \brief MMD address of structure AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_baseRegisterAddress 0x9058 +/*! \brief MMD address of structure AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_baseRegisterAddress 0x905C +/*! \brief MMD address of structure AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x9060 +/*! \brief MMD address of structure AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x9064 +/*! \brief MMD address of structure AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_baseRegisterAddress 0x9068 +/*! \brief MMD address of structure AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 u3.word_3 + +/*! \brief Base register address of structure AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_baseRegisterAddress 0x906C +/*! \brief MMD address of structure AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x9070 +/*! \brief MMD address of structure AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x9074 +/*! \brief MMD address of structure AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x9078 +/*! \brief MMD address of structure AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_baseRegisterAddress 0x907C +/*! \brief MMD address of structure AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x9084 +/*! \brief MMD address of structure AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x9088 +/*! \brief MMD address of structure AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x908C +/*! \brief MMD address of structure AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_baseRegisterAddress 0x90C8 +/*! \brief MMD address of structure AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_baseRegisterAddress 0xC000 +/*! \brief MMD address of structure AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upReset in AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_upReset 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upReset in AQ_GlobalControl_HHD */ +#define bits_AQ_GlobalControl_HHD_upReset u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upReset in AQ_GlobalControl_HHD */ +#define word_AQ_GlobalControl_HHD_upReset u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStallOverride in AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_upRunStallOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStallOverride in AQ_GlobalControl_HHD */ +#define bits_AQ_GlobalControl_HHD_upRunStallOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStallOverride in AQ_GlobalControl_HHD */ +#define word_AQ_GlobalControl_HHD_upRunStallOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStall in AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_upRunStall 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStall in AQ_GlobalControl_HHD */ +#define bits_AQ_GlobalControl_HHD_upRunStall u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStall in AQ_GlobalControl_HHD */ +#define word_AQ_GlobalControl_HHD_upRunStall u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalResetControl_HHD */ +#define AQ_GlobalResetControl_HHD_baseRegisterAddress 0xC006 +/*! \brief MMD address of structure AQ_GlobalResetControl_HHD */ +#define AQ_GlobalResetControl_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ +#define AQ_GlobalResetControl_HHD_globalMMD_ResetDisable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ +#define bits_AQ_GlobalResetControl_HHD_globalMMD_ResetDisable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ +#define word_AQ_GlobalResetControl_HHD_globalMMD_ResetDisable u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDiagnosticProvisioning_HHD */ +#define AQ_GlobalDiagnosticProvisioning_HHD_baseRegisterAddress 0xC400 +/*! \brief MMD address of structure AQ_GlobalDiagnosticProvisioning_HHD */ +#define AQ_GlobalDiagnosticProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ +#define AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ +#define bits_AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ +#define word_AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_baseRegisterAddress 0xC420 +/*! \brief MMD address of structure AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_reserved_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_reserved_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_reserved_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold u4.word_4 + +/*! \brief Base register address of structure AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_baseRegisterAddress 0xC430 +/*! \brief MMD address of structure AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0ManualSet 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0ManualSet u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0ManualSet u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0Connecting 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0Connecting u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0Connecting u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1ManualSet 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1ManualSet u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1ManualSet u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1Connecting 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1Connecting u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1Connecting u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2ManualSet 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2ManualSet u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2ManualSet u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2Connecting 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2Connecting u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2Connecting u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_ledOperationMode 7 +/*! \brief Preprocessor variable to relate field to bit position in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_ledOperationMode u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_ledOperationMode u7.word_7 + +/*! \brief Base register address of structure AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_baseRegisterAddress 0xC440 +/*! \brief MMD address of structure AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_daisyChainReset 2 +/*! \brief Preprocessor variable to relate field to bit position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_daisyChainReset u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_daisyChainReset u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration 7 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength 9 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength u9.word_9 + +/*! \brief Base register address of structure AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_baseRegisterAddress 0xC450 +/*! \brief MMD address of structure AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDataLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDataLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDataLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDummyLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDummyLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDummyLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrAddressLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrAddressLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrAddressLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrClockDivide 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrClockDivide u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrClockDivide u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrReset 3 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrReset u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrReset u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_baseRegisterAddress 0xC470 +/*! \brief MMD address of structure AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue 1 +/*! \brief Preprocessor variable to relate field to bit position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent 2 +/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest 2 +/*! \brief Preprocessor variable to relate field to bit position in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest 3 +/*! \brief Preprocessor variable to relate field to bit position in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_trainingSNR 3 +/*! \brief Preprocessor variable to relate field to bit position in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_trainingSNR u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_trainingSNR u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 4 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart 4 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 5 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_dteEnable 8 +/*! \brief Preprocessor variable to relate field to bit position in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_dteEnable u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_dteEnable u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer 8 +/*! \brief Preprocessor variable to relate field to bit position in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 8 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_powerUpStall 9 +/*! \brief Preprocessor variable to relate field to bit position in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_powerUpStall u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_powerUpStall u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 9 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_loopbackControl 10 +/*! \brief Preprocessor variable to relate field to bit position in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_loopbackControl u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_loopbackControl u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 10 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration 10 +/*! \brief Preprocessor variable to relate field to bit position in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration 10 +/*! \brief Preprocessor variable to relate field to bit position in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration 10 +/*! \brief Preprocessor variable to relate field to bit position in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a 10 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure rate in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_rate 10 +/*! \brief Preprocessor variable to relate field to bit position in structure rate in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_rate u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure rate in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_rate u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 11 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableMacsec 11 +/*! \brief Preprocessor variable to relate field to bit position in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableMacsec u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableMacsec u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enablePtp 11 +/*! \brief Preprocessor variable to relate field to bit position in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enablePtp u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enablePtp u11.word_11 + +/*! \brief Base register address of structure AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_baseRegisterAddress 0xC47C +/*! \brief MMD address of structure AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxAddress u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxData in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxData 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxData in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxData u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxData in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxData u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxCommandType 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxCommandType u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxCommandType u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxMMD 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxMMD u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxMMD u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxCommandStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxCommandStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxCommandStatus u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalSmbus_0Provisioning_HHD */ +#define AQ_GlobalSmbus_0Provisioning_HHD_baseRegisterAddress 0xC485 +/*! \brief MMD address of structure AQ_GlobalSmbus_0Provisioning_HHD */ +#define AQ_GlobalSmbus_0Provisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ +#define AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ +#define bits_AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ +#define word_AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalSmbus_1Provisioning_HHD */ +#define AQ_GlobalSmbus_1Provisioning_HHD_baseRegisterAddress 0xC495 +/*! \brief MMD address of structure AQ_GlobalSmbus_1Provisioning_HHD */ +#define AQ_GlobalSmbus_1Provisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ +#define AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ +#define bits_AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ +#define word_AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalEeeProvisioning_HHD */ +#define AQ_GlobalEeeProvisioning_HHD_baseRegisterAddress 0xC4A0 +/*! \brief MMD address of structure AQ_GlobalEeeProvisioning_HHD */ +#define AQ_GlobalEeeProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ +#define AQ_GlobalEeeProvisioning_HHD_eeeMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ +#define bits_AQ_GlobalEeeProvisioning_HHD_eeeMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ +#define word_AQ_GlobalEeeProvisioning_HHD_eeeMode u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_baseRegisterAddress 0xC800 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 6 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 u7.word_7 + +/*! \brief Base register address of structure AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_baseRegisterAddress 0xC820 +/*! \brief MMD address of structure AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure temperature in AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_temperature 0 +/*! \brief Preprocessor variable to relate field to bit position in structure temperature in AQ_GlobalThermalStatus_HHD */ +#define bits_AQ_GlobalThermalStatus_HHD_temperature u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure temperature in AQ_GlobalThermalStatus_HHD */ +#define word_AQ_GlobalThermalStatus_HHD_temperature u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_temperatureReady 1 +/*! \brief Preprocessor variable to relate field to bit position in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ +#define bits_AQ_GlobalThermalStatus_HHD_temperatureReady u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ +#define word_AQ_GlobalThermalStatus_HHD_temperatureReady u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_baseRegisterAddress 0xC830 +/*! \brief MMD address of structure AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress 1 +/*! \brief Preprocessor variable to relate field to bit position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_baseRegisterAddress 0xC840 +/*! \brief MMD address of structure AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure dcMasterN in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_dcMasterN 0 +/*! \brief Preprocessor variable to relate field to bit position in structure dcMasterN in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_dcMasterN u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure dcMasterN in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_dcMasterN u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_packageConnectivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_packageConnectivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_packageConnectivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure txEnable in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_txEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnable in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_txEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure txEnable in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_txEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure ledPullupState in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_ledPullupState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure ledPullupState in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_ledPullupState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure ledPullupState in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_ledPullupState u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDaisyChainStatus_HHD */ +#define AQ_GlobalDaisyChainStatus_HHD_baseRegisterAddress 0xC842 +/*! \brief MMD address of structure AQ_GlobalDaisyChainStatus_HHD */ +#define AQ_GlobalDaisyChainStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ +#define AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ +#define bits_AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ +#define word_AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalFaultMessage_HHD */ +#define AQ_GlobalFaultMessage_HHD_baseRegisterAddress 0xC850 +/*! \brief MMD address of structure AQ_GlobalFaultMessage_HHD */ +#define AQ_GlobalFaultMessage_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure message in AQ_GlobalFaultMessage_HHD */ +#define AQ_GlobalFaultMessage_HHD_message 0 +/*! \brief Preprocessor variable to relate field to bit position in structure message in AQ_GlobalFaultMessage_HHD */ +#define bits_AQ_GlobalFaultMessage_HHD_message u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure message in AQ_GlobalFaultMessage_HHD */ +#define word_AQ_GlobalFaultMessage_HHD_message u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_baseRegisterAddress 0xC880 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_baseRegisterAddress 0xC884 +/*! \brief MMD address of structure AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_reservedStatus_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ +#define bits_AQ_GlobalStatus_HHD_reservedStatus_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ +#define word_AQ_GlobalStatus_HHD_reservedStatus_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure cableLength in AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_cableLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure cableLength in AQ_GlobalStatus_HHD */ +#define bits_AQ_GlobalStatus_HHD_cableLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure cableLength in AQ_GlobalStatus_HHD */ +#define word_AQ_GlobalStatus_HHD_cableLength u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_baseRegisterAddress 0xC885 +/*! \brief MMD address of structure AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_nearlySecondsMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_nearlySecondsMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_nearlySecondsMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_xenpakNvrStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_xenpakNvrStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_xenpakNvrStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_firmwareBuildID 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_firmwareBuildID u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_firmwareBuildID u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure provisioningID in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_provisioningID 0 +/*! \brief Preprocessor variable to relate field to bit position in structure provisioningID in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_provisioningID u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure provisioningID in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_provisioningID u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_nearlySecondsLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_nearlySecondsLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_nearlySecondsLSW u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure dteStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_dteStatus 2 +/*! \brief Preprocessor variable to relate field to bit position in structure dteStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_dteStatus u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure dteStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_dteStatus u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_powerUpStallStatus 2 +/*! \brief Preprocessor variable to relate field to bit position in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_powerUpStallStatus u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_powerUpStallStatus u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_reservedStatus_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_loopbackStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_loopbackStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_loopbackStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_reservedStatus_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_4 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_reservedStatus_4a 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_4a u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_4a u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure rate in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_rate 3 +/*! \brief Preprocessor variable to relate field to bit position in structure rate in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_rate u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure rate in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_rate u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_baseRegisterAddress 0xCC00 +/*! \brief MMD address of structure AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_highTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_highTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_highTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_lowTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_lowTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_lowTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_highTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_highTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_highTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_lowTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_lowTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_lowTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompleted in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_resetCompleted 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompleted in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_resetCompleted u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompleted in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_resetCompleted u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFault in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_deviceFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFault in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_deviceFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFault in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_deviceFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmA 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmA u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmA u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmB 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmB u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmB u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmC 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmC u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmC u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmD 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmD u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmD u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_smartPower_downEntered 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_smartPower_downEntered u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_smartPower_downEntered u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_xenpakAlarm 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_xenpakAlarm u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_xenpakAlarm u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_ipPhoneDetect 1 +/*! \brief Preprocessor variable to relate field to bit position in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_ipPhoneDetect u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_ipPhoneDetect u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure dteStatusChange in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_dteStatusChange 1 +/*! \brief Preprocessor variable to relate field to bit position in structure dteStatusChange in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_dteStatusChange u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure dteStatusChange in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_dteStatusChange u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarms in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarms 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarms in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarms u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarms in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarms u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_nvrOperationComplete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_nvrOperationComplete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_nvrOperationComplete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mailboxOperation_Complete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mailboxOperation_Complete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mailboxOperation_Complete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityError in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_upDramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityError in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_upDramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityError in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_upDramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityError in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_upIramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityError in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_upIramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityError in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_upIramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_txEnableStateChange 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_txEnableStateChange u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_txEnableStateChange u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mdioMMD_Error 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mdioMMD_Error u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mdioMMD_Error u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mdioTimeoutError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mdioTimeoutError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mdioTimeoutError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_watchdogTimerAlarm 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_watchdogTimerAlarm u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_watchdogTimerAlarm u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_baseRegisterAddress 0xD400 +/*! \brief MMD address of structure AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_resetCompletedMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_resetCompletedMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_resetCompletedMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_deviceFaultMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_deviceFaultMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_deviceFaultMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmAMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmAMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmAMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmBMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmBMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmBMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmCMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmCMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmCMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmDMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmDMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmDMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_xenpakAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_xenpakAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_xenpakAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_dteStatusChangeMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_dteStatusChangeMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_dteStatusChangeMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmsMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmsMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmsMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_upDramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_upDramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_upDramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_upIramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_upIramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_upIramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_baseRegisterAddress 0xFC00 +/*! \brief MMD address of structure AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_baseRegisterAddress 0xFC01 +/*! \brief MMD address of structure AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_baseRegisterAddress 0xFF00 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_baseRegisterAddress 0xFF01 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask u0.word_0 +#endif +/*@}*/ +/*@}*/ diff --git a/firmware/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h b/firmware/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h new file mode 100755 index 0000000..f6fe998 --- /dev/null +++ b/firmware/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h @@ -0,0 +1,12123 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from MSbit to LSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_HHD_GLOBAL_REGS_HEADER +#define AQ_HHD_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_HHD.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Resets the entire PHY. + Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_HHD.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_HHD.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_HHD.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + unsigned int reserved0 : 13; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_HHD.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_HHD.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_HHD.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_HHD.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_HHD.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_HHD.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_HHD.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_HHD.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + + */ + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_HHD.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved2 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_HHD.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_HHD.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.0206.1 R/W uP Mailbox CRC Read Enable + AQ_GlobalMailboxInterface_HHD.u6.bits_6.upMailboxCrcReadEnable + + Default = 0x0 + + 1 = Update uP mailbox CRC on read + + */ + unsigned int upMailboxCrcReadEnable : 1; /* 1E.0206.1 R/W Default = 0x0 */ + /* 1 = Update uP mailbox CRC on read + */ + unsigned int reserved1 : 1; + } bits_6; + uint16_t word_6; + } u6; +} AQ_GlobalMailboxInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Control Register: 1E.5002 */ +/* MSS Egress Control Register: 1E.5002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Control Register */ + union + { + struct + { + /*! \brief 1E.5002.F:D R/W MSS Egress Ethertype Explicit SECTag LSB [2:0] + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressEthertypeExplicitSectagLsb + + Default = 0x0 + + Ethertype for explicit SECTag bits 2:0. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagLsb : 3; /* 1E.5002.F:D R/W Default = 0x0 */ + /* Ethertype for explicit SECTag bits 2:0. + */ + /*! \brief 1E.5002.C R/W MSS Egress Clear Global Time + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + + Notes: + Clear global time. */ + unsigned int mssEgressClearGlobalTime : 1; /* 1E.5002.C R/W Default = 0x0 */ + /* 1 = Clear global time + + */ + /*! \brief 1E.5002.B R/W MSS Egress Clear Counter + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearCounter + + Default = 0x0 + + 1 = Clear all MIB counters + + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssEgressClearCounter : 1; /* 1E.5002.B R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + + */ + /*! \brief 1E.5002.A R/W MSS Egress High Priority + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssEgressHighPriority : 1; /* 1E.5002.A R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + + */ + /*! \brief 1E.5002.9 R/W MSS Egress ICV LSB 8 Bytes Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssEgressIcvLsb_8BytesEnable : 1; /* 1E.5002.9 R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + /*! \brief 1E.5002.8 R/W MSS Egress External Classification Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExternalClassificationEnable + + Default = 0x0 + + 1 = Drop EGPRC miss packets + + + + Notes: + If set, internal classification is bypassed. Should always be set to 0. */ + unsigned int mssEgressExternalClassificationEnable : 1; /* 1E.5002.8 R/W Default = 0x0 */ + /* 1 = Drop EGPRC miss packets + + */ + /*! \brief 1E.5002.7 R/W MSS Egress Explicit SECTag Report Short Length + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExplicitSectagReportShortLength + + Default = 0x0 + + Reserved + + + + Notes: + Unused. */ + unsigned int mssEgressExplicitSectagReportShortLength : 1; /* 1E.5002.7 R/W Default = 0x0 */ + /* Reserved + + */ + /*! \brief 1E.5002.6 R/W MSS Egress Drop Invalid SA/SC Packets + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropInvalidSa_scPackets + + Default = 0x0 + + 1 = Drop invalid SA/SC packets + + + + Notes: + Enables dropping of invalid SA/SC packets. */ + unsigned int mssEgressDropInvalidSa_scPackets : 1; /* 1E.5002.6 R/W Default = 0x0 */ + /* 1 = Drop invalid SA/SC packets + + */ + /*! \brief 1E.5002.5 R/W MSS Egress Unmatched Use SC 0 + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressUnmatchedUseSc_0 + + Default = 0x0 + + 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + + + Notes: + Use SC-Index 0 as default SC for unmatched packets. Otherwise the packets are treated as uncontrolled packets. */ + unsigned int mssEgressUnmatchedUseSc_0 : 1; /* 1E.5002.5 R/W Default = 0x0 */ + /* 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + */ + /*! \brief 1E.5002.4 R/W MSS Egresss GCM Test Mode + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgresssGcmTestMode + + Default = 0x0 + + 1 = Enable GCM test mode + + + + Notes: + Enables GCM test mode */ + unsigned int mssEgresssGcmTestMode : 1; /* 1E.5002.4 R/W Default = 0x0 */ + /* 1 = Enable GCM test mode + + */ + /*! \brief 1E.5002.3 R/W MSS Egress GCM Start + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressGcmStart + + Default = 0x0 + + 1 = Start GCM + + + + Notes: + Indicates GCM to start */ + unsigned int mssEgressGcmStart : 1; /* 1E.5002.3 R/W Default = 0x0 */ + /* 1 = Start GCM + + */ + /*! \brief 1E.5002.2 R/W MSS Egress Drop EGPRC LUT Miss + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropEgprcLutMiss + + Default = 0x0 + + 1 = Drop Egress Classification LUT miss packets + + + + Notes: + Decides whether Egress Pre-Security Classification (EGPRC) LUT miss packets are to be dropped */ + unsigned int mssEgressDropEgprcLutMiss : 1; /* 1E.5002.2 R/W Default = 0x0 */ + /* 1 = Drop Egress Classification LUT miss packets + + */ + /*! \brief 1E.5002.1 R/W MSS Egress Drop KAY Packet + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropKayPacket + + Default = 0x0 + + 1 = Drop KAY packet + + + Notes: + Decides whether KAY packets have to be dropped */ + unsigned int mssEgressDropKayPacket : 1; /* 1E.5002.1 R/W Default = 0x0 */ + /* 1 = Drop KAY packet + */ + /*! \brief 1E.5002.0 R/W MSS Egress Soft Reset + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssEgressSoftReset : 1; /* 1E.5002.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Control Register */ + union + { + struct + { + unsigned int reserved0 : 3; + /*! \brief 1E.5003.C:0 R/W MSS Egress Ethertype Explicit SECTag MSB [F:3] + AQ_MssEgressControlRegister_HHD.u1.bits_1.mssEgressEthertypeExplicitSectagMsb + + Default = 0x0000 + + Ethertype for explicit SECTag bits 15:3. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagMsb : 13; /* 1E.5003.C:0 R/W Default = 0x0000 */ + /* Ethertype for explicit SECTag bits 15:3. + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/* MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.5008.F:0 R/W MSS Egress VLAN STag TPID [F:0] + AQ_MssEgressVlanTpid_0Register_HHD.u0.bits_0.mssEgressVlanStagTpid + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanStagTpid : 16; /* 1E.5008.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 1 Register: 1E.500A */ +/* MSS Egress VLAN TPID 1 Register: 1E.500A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.500A.F:0 R/W MSS Egress VLAN QTag TPID [F:0] + AQ_MssEgressVlanTpid_1Register_HHD.u0.bits_0.mssEgressVlanQtagTpid + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanQtagTpid : 16; /* 1E.500A.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN Control Register: 1E.500C */ +/* MSS Egress VLAN Control Register: 1E.500C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500C.F:0 R/W MSS Egress VLAN UP Map Table [F:0] + AQ_MssEgressVlanControlRegister_HHD.u0.bits_0.mssEgressVlanUpMapTable + + Default = 0x0000 + + UP Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTable : 16; /* 1E.500C.F:0 R/W Default = 0x0000 */ + /* UP Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500D.F R/W MSS Egress VLAN QTag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See SEC Egress TPID 1 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanQtagParseEnable : 1; /* 1E.500D.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + /*! \brief 1E.500D.E R/W MSS Egress VLAN STag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See SEC Egress TPID 0 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanStagParseEnable : 1; /* 1E.500D.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.500D.D R/W MSS Egress VLAN QinQ Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssEgressVlanQinqParseEnable : 1; /* 1E.500D.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.500D.C R/W MSS Egress VLAN QTag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssEgressVlanQtagUpParseEnable : 1; /* 1E.500D.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.500D.B R/W MSS Egress VLAN STag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssEgressVlanStagUpParseEnable : 1; /* 1E.500D.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.500D.A:8 R/W MSS Egress VLAN UP Default [2:0] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssEgressVlanUpDefault : 3; /* 1E.500D.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.500D.7:0 R/W MSS Egress VLAN UP Map Table MSW [17:10] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTableMSW : 8; /* 1E.500D.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress PN Control Register: 1E.500E */ +/* MSS Egress PN Control Register: 1E.500E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500E.F:0 R/W MSS Egress SA PN Threshold LSW [F:0] + AQ_MssEgressPnControlRegister_HHD.u0.bits_0.mssEgressSaPnThresholdLSW + + Default = 0x0000 + + PN threshold bits 15:0 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdLSW : 16; /* 1E.500E.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500F.F:0 R/W MSS Egress SA PN Threshold MSW [1F:10] + AQ_MssEgressPnControlRegister_HHD.u1.bits_1.mssEgressSaPnThresholdMSW + + Default = 0x0000 + + PN threshold bits 31:16 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdMSW : 16; /* 1E.500F.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressPnControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress MTU Size Control Register: 1E.5010 */ +/* MSS Egress MTU Size Control Register: 1E.5010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5010.F:0 R/W MSS Egress Controlled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u0.bits_0.mssEgressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssEgressControlledPacketMtuSize : 16; /* 1E.5010.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5011.F:0 R/W MSS Egress Uncontrolled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u1.bits_1.mssEgressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssEgressUncontrolledPacketMtuSize : 16; /* 1E.5011.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Status Register: 1E.505C */ +/* MSS Egress Interrupt Status Register: 1E.505C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.505C.4 COW MSS Egress ECC Error Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterrupt : 1; /* 1E.505C.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.3 COW MSS Egress MIB Saturation Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterrupt : 1; /* 1E.505C.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.2 COW MSS Egress SA Threshold Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredInterrupt : 1; /* 1E.505C.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.1 COW MSS Egress SA Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterrupt : 1; /* 1E.505C.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.0 COW MSS Egress Master Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMasterInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssEgressMasterInterrupt : 1; /* 1E.505C.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Mask Register: 1E.505E */ +/* MSS Egress Interrupt Mask Register: 1E.505E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.505E.4 COW MSS Egress ECC Error Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterruptEnable : 1; /* 1E.505E.4 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.3 COW MSS Egress MIB Saturation Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterruptEnable : 1; /* 1E.505E.3 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.2 COW MSS Egress SA Expired Threshold Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredThresholdInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaExpiredThresholdInterruptEnable : 1; /* 1E.505E.2 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.1 COW MSS Egress SA Expired Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterruptEnable : 1; /* 1E.505E.1 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.0 COW MSS Egress Master Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. */ + unsigned int mssEgressMasterInterruptEnable : 1; /* 1E.505E.0 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Expired Status Register: 1E.5060 */ +/* MSS Egress SA Expired Status Register: 1E.5060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5060.F:0 COW MSS Egress SA Expired LSW [F:0] + AQ_MssEgressSaExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredLSW : 16; /* 1E.5060.F:0 COW Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5061.F:0 COW MSS Egress SA Expired MSW [1F:10] + AQ_MssEgressSaExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredMSW : 16; /* 1E.5061.F:0 COW Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/* MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5062.F:0 COW MSS Egress SA Threshold Expired LSW [F:0] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredLSW : 16; /* 1E.5062.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5063.F:0 COW MSS Egress SA Threshold Expired MSW [1F:10] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredMSW : 16; /* 1E.5063.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/* MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5064.F:0 COW MSS Egress SA ECC Error Interrupt LSW [F:0] + AQ_MssEgressEccInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptLSW : 16; /* 1E.5064.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5065.F:0 COW MSS Egress SA ECC Error Interrupt MSW [1F:10] + AQ_MssEgressEccInterruptStatusRegister_HHD.u1.bits_1.mssEgressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptMSW : 16; /* 1E.5065.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Address Control Register: 1E.5080 */ +/* MSS Egress LUT Address Control Register: 1E.5080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.5080.F:C R/W MSS Egress LUT Select [3:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Egress MAC Control FIlter (CTLF) LUT + 0x1 : Egress Classification LUT + 0x2 : Egress SC/SA LUT + 0x3 : Egress SMIB */ + unsigned int mssEgressLutSelect : 4; /* 1E.5080.F:C R/W Default = 0x0 */ + /* LUT select + */ + unsigned int reserved0 : 3; + /*! \brief 1E.5080.8:0 R/W MSS Egress LUT Address [8:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssEgressLutAddress : 9; /* 1E.5080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Control Register: 1E.5081 */ +/* MSS Egress LUT Control Register: 1E.5081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Control Register */ + union + { + struct + { + /*! \brief 1E.5081.F R/W MSS Egress LUT Write + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutWrite : 1; /* 1E.5081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + /*! \brief 1E.5081.E R/W MSS Egress LUT Read + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutRead : 1; /* 1E.5081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Data Control Register: 1E.50A0 */ +/* MSS Egress LUT Data Control Register: 1E.50A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A0.F:0 R/W MSS Egress LUT Data 0 [F:0] + AQ_MssEgressLutDataControlRegister_HHD.u0.bits_0.mssEgressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssEgressLutData_0 : 16; /* 1E.50A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A1.F:0 R/W MSS Egress LUT Data 1 [1F:10] + AQ_MssEgressLutDataControlRegister_HHD.u1.bits_1.mssEgressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssEgressLutData_1 : 16; /* 1E.50A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A2.F:0 R/W MSS Egress LUT Data 2 [2F:20] + AQ_MssEgressLutDataControlRegister_HHD.u2.bits_2.mssEgressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssEgressLutData_2 : 16; /* 1E.50A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A3.F:0 R/W MSS Egress LUT Data 3 [3F:30] + AQ_MssEgressLutDataControlRegister_HHD.u3.bits_3.mssEgressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssEgressLutData_3 : 16; /* 1E.50A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A4.F:0 R/W MSS Egress LUT Data 4 [4F:40] + AQ_MssEgressLutDataControlRegister_HHD.u4.bits_4.mssEgressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssEgressLutData_4 : 16; /* 1E.50A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A5.F:0 R/W MSS Egress LUT Data 5 [5F:50] + AQ_MssEgressLutDataControlRegister_HHD.u5.bits_5.mssEgressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssEgressLutData_5 : 16; /* 1E.50A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A6.F:0 R/W MSS Egress LUT Data 6 [6F:60] + AQ_MssEgressLutDataControlRegister_HHD.u6.bits_6.mssEgressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssEgressLutData_6 : 16; /* 1E.50A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A7.F:0 R/W MSS Egress LUT Data 7 [7F:70] + AQ_MssEgressLutDataControlRegister_HHD.u7.bits_7.mssEgressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssEgressLutData_7 : 16; /* 1E.50A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A8.F:0 R/W MSS Egress LUT Data 8 [8F:80] + AQ_MssEgressLutDataControlRegister_HHD.u8.bits_8.mssEgressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssEgressLutData_8 : 16; /* 1E.50A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A9.F:0 R/W MSS Egress LUT Data 9 [9F:90] + AQ_MssEgressLutDataControlRegister_HHD.u9.bits_9.mssEgressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssEgressLutData_9 : 16; /* 1E.50A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AA.F:0 R/W MSS Egress LUT Data 10 [AF:A0] + AQ_MssEgressLutDataControlRegister_HHD.u10.bits_10.mssEgressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssEgressLutData_10 : 16; /* 1E.50AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AB.F:0 R/W MSS Egress LUT Data 11 [BF:B0] + AQ_MssEgressLutDataControlRegister_HHD.u11.bits_11.mssEgressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssEgressLutData_11 : 16; /* 1E.50AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AC.F:0 R/W MSS Egress LUT Data 12 [CF:C0] + AQ_MssEgressLutDataControlRegister_HHD.u12.bits_12.mssEgressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssEgressLutData_12 : 16; /* 1E.50AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AD.F:0 R/W MSS Egress LUT Data 13 [DF:D0] + AQ_MssEgressLutDataControlRegister_HHD.u13.bits_13.mssEgressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssEgressLutData_13 : 16; /* 1E.50AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AE.F:0 R/W MSS Egress LUT Data 14 [EF:E0] + AQ_MssEgressLutDataControlRegister_HHD.u14.bits_14.mssEgressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssEgressLutData_14 : 16; /* 1E.50AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AF.F:0 R/W MSS Egress LUT Data 15 [FF:F0] + AQ_MssEgressLutDataControlRegister_HHD.u15.bits_15.mssEgressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssEgressLutData_15 : 16; /* 1E.50AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B0.F:0 R/W MSS Egress LUT Data 16 [10F:100] + AQ_MssEgressLutDataControlRegister_HHD.u16.bits_16.mssEgressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssEgressLutData_16 : 16; /* 1E.50B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B1.F:0 R/W MSS Egress LUT Data 17 [11F:110] + AQ_MssEgressLutDataControlRegister_HHD.u17.bits_17.mssEgressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssEgressLutData_17 : 16; /* 1E.50B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B2.F:0 R/W MSS Egress LUT Data 18 [12F:120] + AQ_MssEgressLutDataControlRegister_HHD.u18.bits_18.mssEgressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssEgressLutData_18 : 16; /* 1E.50B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B3.F:0 R/W MSS Egress LUT Data 19 [13F:130] + AQ_MssEgressLutDataControlRegister_HHD.u19.bits_19.mssEgressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssEgressLutData_19 : 16; /* 1E.50B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B4.F:0 R/W MSS Egress LUT Data 20 [14F:140] + AQ_MssEgressLutDataControlRegister_HHD.u20.bits_20.mssEgressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssEgressLutData_20 : 16; /* 1E.50B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B5.F:0 R/W MSS Egress LUT Data 21 [15F:150] + AQ_MssEgressLutDataControlRegister_HHD.u21.bits_21.mssEgressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssEgressLutData_21 : 16; /* 1E.50B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B6.F:0 R/W MSS Egress LUT Data 22 [16F:160] + AQ_MssEgressLutDataControlRegister_HHD.u22.bits_22.mssEgressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssEgressLutData_22 : 16; /* 1E.50B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B7.F:0 R/W MSS Egress LUT Data 23 [17F:170] + AQ_MssEgressLutDataControlRegister_HHD.u23.bits_23.mssEgressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssEgressLutData_23 : 16; /* 1E.50B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; + /*! \brief Union for bit and word level access of word 24 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B8.F:0 R/W MSS Egress LUT Data 24 [18F:180] + AQ_MssEgressLutDataControlRegister_HHD.u24.bits_24.mssEgressLutData_24 + + Default = 0x0000 + + LUT data bits 399:384 + + */ + unsigned int mssEgressLutData_24 : 16; /* 1E.50B8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 399:384 + */ + } bits_24; + uint16_t word_24; + } u24; + /*! \brief Union for bit and word level access of word 25 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B9.F:0 R/W MSS Egress LUT Data 25 [19F:190] + AQ_MssEgressLutDataControlRegister_HHD.u25.bits_25.mssEgressLutData_25 + + Default = 0x0000 + + LUT data bits 415:400 + + */ + unsigned int mssEgressLutData_25 : 16; /* 1E.50B9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 415:400 + */ + } bits_25; + uint16_t word_25; + } u25; + /*! \brief Union for bit and word level access of word 26 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BA.F:0 R/W MSS Egress LUT Data 26 [1AF:1A0] + AQ_MssEgressLutDataControlRegister_HHD.u26.bits_26.mssEgressLutData_26 + + Default = 0x0000 + + LUT data bits 431:416 + + */ + unsigned int mssEgressLutData_26 : 16; /* 1E.50BA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 431:416 + */ + } bits_26; + uint16_t word_26; + } u26; + /*! \brief Union for bit and word level access of word 27 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BB.F:0 R/W MSS Egress LUT Data 27 [1BF:1B0] + AQ_MssEgressLutDataControlRegister_HHD.u27.bits_27.mssEgressLutData_27 + + Default = 0x0000 + + LUT data bits 447:432 + + */ + unsigned int mssEgressLutData_27 : 16; /* 1E.50BB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 447:432 + */ + } bits_27; + uint16_t word_27; + } u27; +} AQ_MssEgressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Control Register: 1E.6004 */ +/* MSM System General Control Register: 1E.6004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Control Register */ + union + { + struct + { + /*! \brief 1E.6004.F R/W MSM System PHY Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmSystemPhyTxEnable : 1; /* 1E.6004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + /*! \brief 1E.6004.E R/W MSM System Rx Error Discard + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmSystemRxErrorDiscard : 1; /* 1E.6004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.6004.D R/W MSM System Control Frame Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmSystemControlFrameEnable : 1; /* 1E.6004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.6004.C R/WSC MSM System Soft Reset + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmSystemSoftReset : 1; /* 1E.6004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.6004.B R/W MSM System Tx Pad Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmSystemTxPadEnable : 1; /* 1E.6004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.6004.A R/W MSM System Tx CRC Append + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmSystemTxCrcAppend : 1; /* 1E.6004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.6004.9 R/W MSM System Tx Address Insert Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmSystemTxAddressInsertEnable : 1; /* 1E.6004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.6004.8 R/W MSM System Pause Ignore + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmSystemPauseIgnore : 1; /* 1E.6004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.6004.7 R/W MSM System Pause Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmSystemPauseForward : 1; /* 1E.6004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.6004.6 R/W MSM System CRC Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmSystemCrcForward : 1; /* 1E.6004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.6004.5 R/W MSM System PAD Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmSystemPadEnable : 1; /* 1E.6004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.6004.4 R/W MSM System Promiscuous Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmSystemPromiscuousMode : 1; /* 1E.6004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.6004.3 R/W MSM System WAN Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmSystemWanMode : 1; /* 1E.6004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + unsigned int reserved0 : 1; + /*! \brief 1E.6004.1 R/W MSM System Rx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmSystemRxEnable : 1; /* 1E.6004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + /*! \brief 1E.6004.0 R/W MSM System Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmSystemTxEnable : 1; /* 1E.6004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6005.7 R/W MSM System Tx Low Power IDLE Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmSystemTxLowPowerIdleEnable : 1; /* 1E.6005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved1 : 1; + /*! \brief 1E.6005.5 R/W MSM System SFD Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmSystemSfdCheckDisable : 1; /* 1E.6005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved2 : 1; + /*! \brief 1E.6005.3 R/W MSM System Priority Flow Control Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemPriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmSystemPriorityFlowControlEnable : 1; /* 1E.6005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + /*! \brief 1E.6005.2 R/W MSM System IDLE Column Count Extend + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmSystemIdleColumnCountExtend : 1; /* 1E.6005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.6005.1 R/W MSM System Length Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmSystemLengthCheckDisable : 1; /* 1E.6005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.6005.0 R/W MSM System Force Send IDLE + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmSystemForceSendIdle : 1; /* 1E.6005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System FIFO Control Register: 1E.600E */ +/* MSM System FIFO Control Register: 1E.600E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.600E.7:0 R/W MSM System Rx FIFO Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u0.bits_0.msmSystemRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoFullThreshold : 8; /* 1E.600E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.600F.7:0 R/W MSM System Rx FIFO Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u1.bits_1.msmSystemRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoEmptyThreshold : 8; /* 1E.600F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6010.5:0 R/W MSM System Tx FIFO Full Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u2.bits_2.msmSystemTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoFullThreshold : 6; /* 1E.6010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6011.5:0 R/W MSM System Tx FIFO Empty Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u3.bits_3.msmSystemTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoEmptyThreshold : 6; /* 1E.6011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6012.7:0 ROS MSM System Rx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u4.bits_4.msmSystemRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostFullThreshold : 8; /* 1E.6012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6013.7:0 ROS MSM System Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u5.bits_5.msmSystemRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostEmptyThreshold : 8; /* 1E.6013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6014.7:0 ROS MSM System Tx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u6.bits_6.msmSystemTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostFullThreshold : 8; /* 1E.6014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6015.7:0 ROS MSM System Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u7.bits_7.msmSystemTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostEmptyThreshold : 8; /* 1E.6015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmSystemFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Status Register: 1E.6020 */ +/* MSM System General Status Register: 1E.6020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Status Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6020.5 RO MSM System Tx FIFO Empty + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmSystemTxFifoEmpty : 1; /* 1E.6020.5 RO */ + /* Tx FIFO empty */ + /*! \brief 1E.6020.4 RO MSM System Rx Low Power IDLE + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmSystemRxLowPowerIdle : 1; /* 1E.6020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.6020.3 R/W MSM System Timestamp Available + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmSystemTimestampAvailable : 1; /* 1E.6020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.6020.2 RO MSM System PHY Loss of Signal + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemPhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmSystemPhyLossOfSignal : 1; /* 1E.6020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.6020.1 BLH MSM System Rx Remote Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxRemoteFault : 1; /* 1E.6020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.6020.0 BLH MSM System Rx Local Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxLocalFault : 1; /* 1E.6020.0 BLH */ + /* Rx local fault detected */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx IPG Control Register: 1E.6022 */ +/* MSM System Tx IPG Control Register: 1E.6022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx IPG Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6022.5:0 R/W MSM System Tx IPG Length [5:0] + AQ_MsmSystemTxIpgControlRegister_HHD.u0.bits_0.msmSystemTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmSystemTxIpgLength : 6; /* 1E.6022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.6023.F:0 MSM System Tx IPG Reserved + AQ_MsmSystemTxIpgControlRegister_HHD.u1.bits_1.msmSystemTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmSystemTxIpgReserved : 16; /* 1E.6023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Good Frames Counter Register: 1E.6040 */ +/* MSM System Tx Good Frames Counter Register: 1E.6040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6040.F:0 ROS MSM System Tx Good Frames Counter 0 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_0 : 16; /* 1E.6040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6041.F:0 ROS MSM System Tx Good Frames Counter 1 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_1 : 16; /* 1E.6041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Good Frames Counter Register: 1E.6044 */ +/* MSM System Rx Good Frames Counter Register: 1E.6044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6044.F:0 ROS MSM System Rx Good Frames Counter 0 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_0 : 16; /* 1E.6044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6045.F:0 ROS MSM System Rx Good Frames Counter 1 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_1 : 16; /* 1E.6045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/* MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6048.F:0 ROS MSM System FCS Error Counter 0 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmSystemFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_0 : 16; /* 1E.6048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6049.F:0 ROS MSM System FCS Error Counter 1 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmSystemFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_1 : 16; /* 1E.6049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/* MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604C.F:0 ROS MSM System Alignment Error Counter 0 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmSystemAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_0 : 16; /* 1E.604C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604D.F:0 ROS MSM System Alignment Error Counter 1 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmSystemAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_1 : 16; /* 1E.604D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/* MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6050.F:0 ROS MSM System Tx Pause Frames Counter 0 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_0 : 16; /* 1E.6050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6051.F:0 ROS MSM System Tx Pause Frames Counter 1 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_1 : 16; /* 1E.6051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/* MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6054.F:0 ROS MSM System Rx Pause Frames Counter 0 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_0 : 16; /* 1E.6054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6055.F:0 ROS MSM System Rx Pause Frames Counter 1 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_1 : 16; /* 1E.6055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/* MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6058.F:0 ROS MSM System Rx Too Long Errors Counter 0 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_0 : 16; /* 1E.6058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6059.F:0 ROS MSM System Rx Too Long Errors Counter 1 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_1 : 16; /* 1E.6059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/* MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605C.F:0 ROS MSM System Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_0 : 16; /* 1E.605C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605D.F:0 ROS MSM System Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_1 : 16; /* 1E.605D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/* MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6060.F:0 ROS MSM System Tx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_0 : 16; /* 1E.6060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6061.F:0 ROS MSM System Tx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_1 : 16; /* 1E.6061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/* MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6064.F:0 ROS MSM System Rx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_0 : 16; /* 1E.6064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6065.F:0 ROS MSM System Rx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_1 : 16; /* 1E.6065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Octets Counter Register: 1E.6068 */ +/* MSM System Tx Octets Counter Register: 1E.6068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6068.F:0 ROS MSM System Tx Octets Counter 0 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u0.bits_0.msmSystemTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_0 : 16; /* 1E.6068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6069.F:0 ROS MSM System Tx Octets Counter 1 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u1.bits_1.msmSystemTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_1 : 16; /* 1E.6069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606A.F:0 ROS MSM System Tx Octets Counter 2 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u2.bits_2.msmSystemTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_2 : 16; /* 1E.606A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606B.F:0 ROS MSM System Tx Octets Counter 3 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u3.bits_3.msmSystemTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_3 : 16; /* 1E.606B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmSystemTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Octets Counter Register: 1E.606C */ +/* MSM System Rx Octets Counter Register: 1E.606C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606C.F:0 ROS MSM System Rx Octets Counter 0 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u0.bits_0.msmSystemRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_0 : 16; /* 1E.606C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606D.F:0 ROS MSM System Rx Octets Counter 1 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u1.bits_1.msmSystemRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_1 : 16; /* 1E.606D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/* MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6070.F:0 ROS MSM System Rx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_0 : 16; /* 1E.6070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6071.F:0 ROS MSM System Rx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_1 : 16; /* 1E.6071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/* MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6074.F:0 ROS MSM System Rx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_0 : 16; /* 1E.6074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6075.F:0 ROS MSM System Rx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_1 : 16; /* 1E.6075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/* MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6078.F:0 ROS MSM System Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_0 : 16; /* 1E.6078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6079.F:0 ROS MSM System Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_1 : 16; /* 1E.6079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Errors Counter Register: 1E.607C */ +/* MSM System Tx Errors Counter Register: 1E.607C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607C.F:0 ROS MSM System Tx Errors Counter 0 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u0.bits_0.msmSystemTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_0 : 16; /* 1E.607C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607D.F:0 ROS MSM System Tx Errors Counter 1 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u1.bits_1.msmSystemTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_1 : 16; /* 1E.607D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/* MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6084.F:0 ROS MSM System Tx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_0 : 16; /* 1E.6084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6085.F:0 ROS MSM System Tx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_1 : 16; /* 1E.6085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/* MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6088.F:0 ROS MSM System Tx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_0 : 16; /* 1E.6088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6089.F:0 ROS MSM System Tx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_1 : 16; /* 1E.6089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/* MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608C.F:0 ROS MSM System Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_0 : 16; /* 1E.608C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608D.F:0 ROS MSM System Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_1 : 16; /* 1E.608D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Errors Counter Register: 1E.60C8 */ +/* MSM System Rx Errors Counter Register: 1E.60C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C8.F:0 ROS MSM System Rx Errors Counter 0 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_0 : 16; /* 1E.60C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C9.F:0 ROS MSM System Rx Errors Counter 1 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_1 : 16; /* 1E.60C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/* MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.8006.F:0 R/W MSS Ingress VLAN STag [F:0] + AQ_MssIngressVlanTpid_0Register_HHD.u0.bits_0.mssIngressVlanStag + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanStag : 16; /* 1E.8006.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/* MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.8008.F:0 R/W MSS Ingress VLAN QTag [F:0] + AQ_MssIngressVlanTpid_1Register_HHD.u0.bits_0.mssIngressVlanQtag + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanQtag : 16; /* 1E.8008.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN Control Register: 1E.800A */ +/* MSS Ingress VLAN Control Register: 1E.800A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800A.F:0 R/W MSS Ingress VLAN UP Map Table LSW [F:0] + AQ_MssIngressVlanControlRegister_HHD.u0.bits_0.mssIngressVlanUpMapTableLSW + + Default = 0x0000 + + Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableLSW : 16; /* 1E.800A.F:0 R/W Default = 0x0000 */ + /* Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800B.F R/W MSS Ingress VLAN QTag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See MSS Ingress VLAN QTag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanQtagParseEnable : 1; /* 1E.800B.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + /*! \brief 1E.800B.E R/W MSS Ingress VLAN STag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See MSS Ingress VLAN Stag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanStagParseEnable : 1; /* 1E.800B.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.800B.D R/W MSS Ingress VLAN QinQ Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssIngressVlanQinqParseEnable : 1; /* 1E.800B.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.800B.C R/W MSS Ingress VLAN QTag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssIngressVlanQtagUpParseEnable : 1; /* 1E.800B.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.800B.B R/W MSS Ingress VLAN STag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssIngressVlanStagUpParseEnable : 1; /* 1E.800B.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.800B.A:8 R/W MSS Ingress VLAN UP Default [2:0] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssIngressVlanUpDefault : 3; /* 1E.800B.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.800B.7:0 R/W MSS Ingress VLAN UP Map Table MSW [17:10] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableMSW : 8; /* 1E.800B.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress MTU Size Control Register: 1E.800C */ +/* MSS Ingress MTU Size Control Register: 1E.800C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800C.F:0 R/W MSS Ingress Controlled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u0.bits_0.mssIngressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssIngressControlledPacketMtuSize : 16; /* 1E.800C.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800D.F:0 R/W MSS Ingress Uncontrolled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u1.bits_1.mssIngressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssIngressUncontrolledPacketMtuSize : 16; /* 1E.800D.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Control Register: 1E.800E */ +/* MSS Ingress Control Register: 1E.800E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Control Register */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.800E.D R/W MSS Ingress ICV LSB 8 Bytes Enable + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssIngressIcvLsb_8BytesEnable : 1; /* 1E.800E.D R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + /*! \brief 1E.800E.C:B R/W MSS Ingress Global Validate Frames [1:0] + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressGlobalValidateFrames + + Default = 0x0 + + Default validate frames configuration + + + Notes: + If the SC is invalid or if an IGPRC miss packet condition occurs, this default will be used for the validate frames configuration instead of the validate frame entry in the Ingress SC Table (IGSCT). */ + unsigned int mssIngressGlobalValidateFrames : 2; /* 1E.800E.C:B R/W Default = 0x0 */ + /* Default validate frames configuration + */ + /*! \brief 1E.800E.A R/W MSS Ingress Remove SECTag + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressRemoveSectag + + Default = 0x0 + + 1 = Enable removal of SECTag + + + Notes: + If this bit is set and either of the following two conditions occurs, the SECTag will be removed. + Controlled packet and either the SA or SC is invalid. + IGPRC miss. */ + unsigned int mssIngressRemoveSectag : 1; /* 1E.800E.A R/W Default = 0x0 */ + /* 1 = Enable removal of SECTag + */ + /*! \brief 1E.800E.9 R/W MSS Ingress High Priority + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssIngressHighPriority : 1; /* 1E.800E.9 R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + */ + /*! \brief 1E.800E.8 R/W MSS Ingress Clear Count + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearCount + + Default = 0x0 + + 1 = Clear all MIB counters + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssIngressClearCount : 1; /* 1E.800E.8 R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + */ + /*! \brief 1E.800E.7 R/W MSS Ingress Clear Global Time + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + Notes: + Clear global time */ + unsigned int mssIngressClearGlobalTime : 1; /* 1E.800E.7 R/W Default = 0x0 */ + /* 1 = Clear global time + */ + /*! \brief 1E.800E.6 R/W MSS Ingress Check ICV + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCheckIcv + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressCheckIcv : 1; /* 1E.800E.6 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.5 R/W MSS Ingress Drop IGPRC Miss + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropIgprcMiss + + Default = 0x0 + + 1 = Drop IGPRC miss packets + + + Notes: + Decides whether Ingress Pre-Security Classification (IGPRC) LUT miss packets are to be dropped */ + unsigned int mssIngressDropIgprcMiss : 1; /* 1E.800E.5 R/W Default = 0x0 */ + /* 1 = Drop IGPRC miss packets + */ + /*! \brief 1E.800E.4 R/W MSS Ingress Drop Kay Packet + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropKayPacket + + Default = 0x0 + + 1 = Drop KaY packets + + + Notes: + Decides whether KaY packets have to be dropped */ + unsigned int mssIngressDropKayPacket : 1; /* 1E.800E.4 R/W Default = 0x0 */ + /* 1 = Drop KaY packets + */ + /*! \brief 1E.800E.3 R/W MSS Ingress Mask Short Length Error + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressMaskShortLengthError + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressMaskShortLengthError : 1; /* 1E.800E.3 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.2 R/W MSS Ingress Create SCI + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCreateSci + + Default = 0x0 + + 0 = SCI from IGPRC LUT + + + Notes: + If the SCI is not in the packet and this bit is set to 0, the SCI will be taken from the IGPRC LUT. */ + unsigned int mssIngressCreateSci : 1; /* 1E.800E.2 R/W Default = 0x0 */ + /* 0 = SCI from IGPRC LUT + */ + /*! \brief 1E.800E.1 R/W MSS Ingress Operation Point To Point + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressOperationPointToPoint + + Default = 0x0 + + 1 = Enable the SCI for authorization default + + + Notes: + The default SCI for authorization is configured in See MSS Ingress SCI Default [F:0] See MSS Ingress SCI Default [1F:10] , See MSS Ingress SCI Default [2F:20] , and See MSS Ingress SCI Default [3F:30] . */ + unsigned int mssIngressOperationPointToPoint : 1; /* 1E.800E.1 R/W Default = 0x0 */ + /* 1 = Enable the SCI for authorization default + */ + /*! \brief 1E.800E.0 R/W MSS Ingress Soft Reset + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssIngressSoftReset : 1; /* 1E.800E.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Control Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Control Register: 1E.8010 */ +/* MSS Ingress SA Control Register: 1E.8010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8010.F:0 R/W MSS Ingress SA Threshold LSW [F:0] + AQ_MssIngressSaControlRegister_HHD.u0.bits_0.mssIngressSaThresholdLSW + + Default = 0x0000 + + SA threshold bits 15:0 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdLSW : 16; /* 1E.8010.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8011.F:0 R/W MSS Ingress SA Threshold MSW [1F:10] + AQ_MssIngressSaControlRegister_HHD.u1.bits_1.mssIngressSaThresholdMSW + + Default = 0x0000 + + SA threshold bits 31:16 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdMSW : 16; /* 1E.8011.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Status Register: 1E.802E */ +/* MSS Ingress Interrupt Status Register: 1E.802E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.802E.8 COW MSS Ingress IGPOC Miss Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIgpocMissInterrupt + + Default = 0x0 + + 1 = Interrupt + + */ + unsigned int mssIngressIgpocMissInterrupt : 1; /* 1E.802E.8 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.7 COW MSS Ingress TCI E/C Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This error occurs when the TCI E bit is 1 and the TCI C bit is 0. The packet is not dropped, uncontrolled, or untagged. */ + unsigned int mssIngressTciE_cErrorInterrupt : 1; /* 1E.802E.7 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.6 COW MSS Ingress ECC Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressEccErrorInterrupt : 1; /* 1E.802E.6 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.5 COW MSS Ingress MIB Saturation Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssIngressMibSaturationInterrupt : 1; /* 1E.802E.5 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.4 COW MSS Ingress Replay Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressReplayErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressReplayErrorInterrupt : 1; /* 1E.802E.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.3 COW MSS Ingress ICV Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIcvErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressIcvErrorInterrupt : 1; /* 1E.802E.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.2 COW MSS Ingress SA Threshold Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssIngressSaThresholdExpiredInterrupt : 1; /* 1E.802E.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.1 COW MSS Ingress SA Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssIngressSaExpiredInterrupt : 1; /* 1E.802E.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.0 COW MSS Master Ingress Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssMasterIngressInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssMasterIngressInterrupt : 1; /* 1E.802E.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Mask Register: 1E.8030 */ +/* MSS Ingress Interrupt Mask Register: 1E.8030 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.8030.8 R/W MSS Ingress IGPOC Miss Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIgpocMissInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIgpocMissInterruptEnable : 1; /* 1E.8030.8 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.7 R/W MSS Ingress TCI E/C Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressTciE_cErrorInterruptEnable : 1; /* 1E.8030.7 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.6 R/W MSS Ingress ECC Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressEccErrorInterruptEnable : 1; /* 1E.8030.6 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.5 R/W MSS Ingress MIB Saturation Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMibSaturationInterruptEnable : 1; /* 1E.8030.5 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.4 R/W MSS Ingress Replay Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressReplayErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressReplayErrorInterruptEnable : 1; /* 1E.8030.4 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.3 R/W MSS Ingress ICV Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIcvErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIcvErrorInterruptEnable : 1; /* 1E.8030.3 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.2 R/W MSS Ingress SA Threshold Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaThresholdExpiredInterruptEnable : 1; /* 1E.8030.2 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.1 R/W MSS Ingress SA Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaExpiredInterruptEnable : 1; /* 1E.8030.1 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.0 R/W MSS Ingress Master Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMasterInterruptEnable : 1; /* 1E.8030.0 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/* MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8032.F:0 COW MSS Ingress SA ICV Error LSW [F:0] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u0.bits_0.mssIngressSaIcvErrorLSW + + Default = 0x0000 + + SA ICV error bits 15:0 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorLSW : 16; /* 1E.8032.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8033.F:0 COW MSS Ingress SA ICV Error MSW [1F:10] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u1.bits_1.mssIngressSaIcvErrorMSW + + Default = 0x0000 + + SA ICV error bits 31:16 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorMSW : 16; /* 1E.8033.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaIcvErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/* MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8034.F:0 COW MSS Ingress SA Replay Error LSW [F:0] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u0.bits_0.mssIngressSaReplayErrorLSW + + Default = 0x0000 + + SA replay error bits 15:0 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorLSW : 16; /* 1E.8034.F:0 COW Default = 0x0000 */ + /* SA replay error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8035.F:0 COW MSS Ingress SA Replay Error MSW [1F:10] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u1.bits_1.mssIngressSaReplayErrorMSW + + Default = 0x0000 + + SA replay error bits 31:16 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorMSW : 16; /* 1E.8035.F:0 COW Default = 0x0000 */ + /* SA replay error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaReplayErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Expired Status Register: 1E.8036 */ +/* MSS Ingress SA Expired Status Register: 1E.8036 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8036.F:0 ROS MSS Ingress SA Expired LSW [F:0] + AQ_MssIngressSaExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredLSW : 16; /* 1E.8036.F:0 ROS Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8037.F:0 ROS MSS Ingress SA Expired MSW [1F:10] + AQ_MssIngressSaExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredMSW : 16; /* 1E.8037.F:0 ROS Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/* MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8038.F:0 ROS MSS Ingress SA Threshold Expired LSW [F:0] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredLSW : 16; /* 1E.8038.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8039.F:0 ROS MSS Ingress SA Threshold Expired MSW [1F:10] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredMSW : 16; /* 1E.8039.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/* MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803A.F:0 R/W MSS Ingress SA ECC Error Interrupt LSW [F:0] + AQ_MssIngressEccInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptLSW : 16; /* 1E.803A.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803B.F:0 R/W MSS Ingress SA ECC Error Interrupt MSW [1F:10] + AQ_MssIngressEccInterruptStatusRegister_HHD.u1.bits_1.mssIngressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptMSW : 16; /* 1E.803B.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Address Control Register: 1E.8080 */ +/* MSS Ingress LUT Address Control Register: 1E.8080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.8080.F:C R/W MSS Ingress LUT Select [3:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Ingress Pre-Security MAC Control FIlter (IGPRCTLF) LUT + 0x1 : Ingress Pre-Security Classification LUT (IGPRC) + 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT + 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT + 0x4 : Ingress Post-Security Classification LUT (IGPOC) + 0x5 : Ingress Post-Security MAC Control Filter (IGPOCTLF) LUT + 0x6 : Ingress MIB (IGMIB) */ + unsigned int mssIngressLutSelect : 4; /* 1E.8080.F:C R/W Default = 0x0 */ + /* LUT select + */ + unsigned int reserved0 : 3; + /*! \brief 1E.8080.8:0 R/W MSS Ingress LUT Address [8:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssIngressLutAddress : 9; /* 1E.8080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Control Register: 1E.8081 */ +/* MSS Ingress LUT Control Register: 1E.8081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Control Register */ + union + { + struct + { + /*! \brief 1E.8081.F R/W MSS Ingress LUT Write + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutWrite : 1; /* 1E.8081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + /*! \brief 1E.8081.E R/W MSS Ingress LUT Read + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutRead : 1; /* 1E.8081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Data Control Register: 1E.80A0 */ +/* MSS Ingress LUT Data Control Register: 1E.80A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A0.F:0 R/W MSS Ingress LUT Data 0 [F:0] + AQ_MssIngressLutDataControlRegister_HHD.u0.bits_0.mssIngressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssIngressLutData_0 : 16; /* 1E.80A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A1.F:0 R/W MSS Ingress LUT Data 1 [1F:10] + AQ_MssIngressLutDataControlRegister_HHD.u1.bits_1.mssIngressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssIngressLutData_1 : 16; /* 1E.80A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A2.F:0 R/W MSS Ingress LUT Data 2 [2F:20] + AQ_MssIngressLutDataControlRegister_HHD.u2.bits_2.mssIngressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssIngressLutData_2 : 16; /* 1E.80A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A3.F:0 R/W MSS Ingress LUT Data 3 [3F:30] + AQ_MssIngressLutDataControlRegister_HHD.u3.bits_3.mssIngressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssIngressLutData_3 : 16; /* 1E.80A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A4.F:0 R/W MSS Ingress LUT Data 4 [4F:40] + AQ_MssIngressLutDataControlRegister_HHD.u4.bits_4.mssIngressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssIngressLutData_4 : 16; /* 1E.80A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A5.F:0 R/W MSS Ingress LUT Data 5 [5F:50] + AQ_MssIngressLutDataControlRegister_HHD.u5.bits_5.mssIngressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssIngressLutData_5 : 16; /* 1E.80A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A6.F:0 R/W MSS Ingress LUT Data 6 [6F:60] + AQ_MssIngressLutDataControlRegister_HHD.u6.bits_6.mssIngressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssIngressLutData_6 : 16; /* 1E.80A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A7.F:0 R/W MSS Ingress LUT Data 7 [7F:70] + AQ_MssIngressLutDataControlRegister_HHD.u7.bits_7.mssIngressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssIngressLutData_7 : 16; /* 1E.80A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A8.F:0 R/W MSS Ingress LUT Data 8 [8F:80] + AQ_MssIngressLutDataControlRegister_HHD.u8.bits_8.mssIngressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssIngressLutData_8 : 16; /* 1E.80A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A9.F:0 R/W MSS Ingress LUT Data 9 [9F:90] + AQ_MssIngressLutDataControlRegister_HHD.u9.bits_9.mssIngressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssIngressLutData_9 : 16; /* 1E.80A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AA.F:0 R/W MSS Ingress LUT Data 10 [AF:A0] + AQ_MssIngressLutDataControlRegister_HHD.u10.bits_10.mssIngressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssIngressLutData_10 : 16; /* 1E.80AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AB.F:0 R/W MSS Ingress LUT Data 11 [BF:B0] + AQ_MssIngressLutDataControlRegister_HHD.u11.bits_11.mssIngressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssIngressLutData_11 : 16; /* 1E.80AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AC.F:0 R/W MSS Ingress LUT Data 12 [CF:C0] + AQ_MssIngressLutDataControlRegister_HHD.u12.bits_12.mssIngressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssIngressLutData_12 : 16; /* 1E.80AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AD.F:0 R/W MSS Ingress LUT Data 13 [DF:D0] + AQ_MssIngressLutDataControlRegister_HHD.u13.bits_13.mssIngressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssIngressLutData_13 : 16; /* 1E.80AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AE.F:0 R/W MSS Ingress LUT Data 14 [EF:E0] + AQ_MssIngressLutDataControlRegister_HHD.u14.bits_14.mssIngressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssIngressLutData_14 : 16; /* 1E.80AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AF.F:0 R/W MSS Ingress LUT Data 15 [FF:F0] + AQ_MssIngressLutDataControlRegister_HHD.u15.bits_15.mssIngressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssIngressLutData_15 : 16; /* 1E.80AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B0.F:0 R/W MSS Ingress LUT Data 16 [10F:100] + AQ_MssIngressLutDataControlRegister_HHD.u16.bits_16.mssIngressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssIngressLutData_16 : 16; /* 1E.80B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B1.F:0 R/W MSS Ingress LUT Data 17 [11F:110] + AQ_MssIngressLutDataControlRegister_HHD.u17.bits_17.mssIngressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssIngressLutData_17 : 16; /* 1E.80B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B2.F:0 R/W MSS Ingress LUT Data 18 [12F:120] + AQ_MssIngressLutDataControlRegister_HHD.u18.bits_18.mssIngressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssIngressLutData_18 : 16; /* 1E.80B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B3.F:0 R/W MSS Ingress LUT Data 19 [13F:130] + AQ_MssIngressLutDataControlRegister_HHD.u19.bits_19.mssIngressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssIngressLutData_19 : 16; /* 1E.80B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B4.F:0 R/W MSS Ingress LUT Data 20 [14F:140] + AQ_MssIngressLutDataControlRegister_HHD.u20.bits_20.mssIngressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssIngressLutData_20 : 16; /* 1E.80B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B5.F:0 R/W MSS Ingress LUT Data 21 [15F:150] + AQ_MssIngressLutDataControlRegister_HHD.u21.bits_21.mssIngressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssIngressLutData_21 : 16; /* 1E.80B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B6.F:0 R/W MSS Ingress LUT Data 22 [16F:160] + AQ_MssIngressLutDataControlRegister_HHD.u22.bits_22.mssIngressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssIngressLutData_22 : 16; /* 1E.80B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B7.F:0 R/W MSS Ingress LUT Data 23 [17F:170] + AQ_MssIngressLutDataControlRegister_HHD.u23.bits_23.mssIngressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssIngressLutData_23 : 16; /* 1E.80B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; +} AQ_MssIngressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Control Register: 1E.9004 */ +/* MSM Line General Control Register: 1E.9004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Control Register */ + union + { + struct + { + /*! \brief 1E.9004.F R/W MSM Line PHY Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmLinePhyTxEnable : 1; /* 1E.9004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + /*! \brief 1E.9004.E R/W MSM Line Rx Error Discard + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmLineRxErrorDiscard : 1; /* 1E.9004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.9004.D R/W MSM Line Control Frame Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmLineControlFrameEnable : 1; /* 1E.9004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.9004.C R/WSC MSM Line Soft Reset + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmLineSoftReset : 1; /* 1E.9004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.9004.B R/W MSM Line Tx Pad Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmLineTxPadEnable : 1; /* 1E.9004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.9004.A R/W MSM Line Tx CRC Append + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmLineTxCrcAppend : 1; /* 1E.9004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.9004.9 R/W MSM Line Tx Address Insert Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmLineTxAddressInsertEnable : 1; /* 1E.9004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.9004.8 R/W MSM Line Pause Ignore + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmLinePauseIgnore : 1; /* 1E.9004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.9004.7 R/W MSM Line Pause Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmLinePauseForward : 1; /* 1E.9004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.9004.6 R/W MSM Line CRC Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmLineCrcForward : 1; /* 1E.9004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.9004.5 R/W MSM Line PAD Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmLinePadEnable : 1; /* 1E.9004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.9004.4 R/W MSM Line Promiscuous Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmLinePromiscuousMode : 1; /* 1E.9004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.9004.3 R/W MSM Line WAN Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmLineWanMode : 1; /* 1E.9004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + unsigned int reserved0 : 1; + /*! \brief 1E.9004.1 R/W MSM Line Rx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmLineRxEnable : 1; /* 1E.9004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + /*! \brief 1E.9004.0 R/W MSM Line Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmLineTxEnable : 1; /* 1E.9004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9005.7 R/W MSM Line Tx Low Power IDLE Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmLineTxLowPowerIdleEnable : 1; /* 1E.9005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved1 : 1; + /*! \brief 1E.9005.5 R/W MSM Line SFD Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmLineSfdCheckDisable : 1; /* 1E.9005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved2 : 1; + /*! \brief 1E.9005.3 R/W MSM Line Priority Flow Control Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLinePriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmLinePriorityFlowControlEnable : 1; /* 1E.9005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + /*! \brief 1E.9005.2 R/W MSM Line IDLE Column Count Extend + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmLineIdleColumnCountExtend : 1; /* 1E.9005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.9005.1 R/W MSM Line Length Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmLineLengthCheckDisable : 1; /* 1E.9005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.9005.0 R/W MSM Line Force Send IDLE + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmLineForceSendIdle : 1; /* 1E.9005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line FIFO Control Register: 1E.900E */ +/* MSM Line FIFO Control Register: 1E.900E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.900E.7:0 R/W MSM Line Rx FIFO Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u0.bits_0.msmLineRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoFullThreshold : 8; /* 1E.900E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.900F.7:0 R/W MSM Line Rx FIFO Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u1.bits_1.msmLineRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoEmptyThreshold : 8; /* 1E.900F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9010.5:0 R/W MSM Line Tx FIFO Full Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u2.bits_2.msmLineTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoFullThreshold : 6; /* 1E.9010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9011.5:0 R/W MSM Line Tx FIFO Empty Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u3.bits_3.msmLineTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoEmptyThreshold : 6; /* 1E.9011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9012.7:0 ROS MSM Line Rx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u4.bits_4.msmLineRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostFullThreshold : 8; /* 1E.9012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9013.7:0 ROS MSM Line Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u5.bits_5.msmLineRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostEmptyThreshold : 8; /* 1E.9013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9014.7:0 ROS MSM Line Tx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u6.bits_6.msmLineTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostFullThreshold : 8; /* 1E.9014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9015.7:0 ROS MSM Line Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u7.bits_7.msmLineTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostEmptyThreshold : 8; /* 1E.9015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmLineFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Status Register: 1E.9020 */ +/* MSM Line General Status Register: 1E.9020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Status Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9020.5 RO MSM Line Tx FIFO Empty + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmLineTxFifoEmpty : 1; /* 1E.9020.5 RO */ + /* Tx FIFO empty */ + /*! \brief 1E.9020.4 RO MSM Line Rx Low Power IDLE + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmLineRxLowPowerIdle : 1; /* 1E.9020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.9020.3 R/W MSM Line Timestamp Available + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmLineTimestampAvailable : 1; /* 1E.9020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.9020.2 RO MSM Line PHY Loss of Signal + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLinePhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmLinePhyLossOfSignal : 1; /* 1E.9020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.9020.1 BLH MSM Line Rx Remote Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxRemoteFault : 1; /* 1E.9020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.9020.0 BLH MSM Line Rx Local Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxLocalFault : 1; /* 1E.9020.0 BLH */ + /* Rx local fault detected */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx IPG Control Register: 1E.9022 */ +/* MSM Line Tx IPG Control Register: 1E.9022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx IPG Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9022.5:0 R/W MSM Line Tx IPG Length [5:0] + AQ_MsmLineTxIpgControlRegister_HHD.u0.bits_0.msmLineTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmLineTxIpgLength : 6; /* 1E.9022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.9023.F:0 MSM Line Tx IPG Reserved + AQ_MsmLineTxIpgControlRegister_HHD.u1.bits_1.msmLineTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmLineTxIpgReserved : 16; /* 1E.9023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/* MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9040.F:0 ROS MSM Line Tx Good Frames Counter 0 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_0 : 16; /* 1E.9040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9041.F:0 ROS MSM Line Tx Good Frames Counter 1 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_1 : 16; /* 1E.9041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/* MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9044.F:0 ROS MSM Line Rx Good Frames Counter 0 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_0 : 16; /* 1E.9044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9045.F:0 ROS MSM Line Rx Good Frames Counter 1 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_1 : 16; /* 1E.9045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/* MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9048.F:0 ROS MSM Line FCS Error Counter 0 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmLineFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_0 : 16; /* 1E.9048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9049.F:0 ROS MSM Line FCS Error Counter 1 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmLineFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_1 : 16; /* 1E.9049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/* MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904C.F:0 ROS MSM Line Alignment Error Counter 0 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmLineAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_0 : 16; /* 1E.904C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904D.F:0 ROS MSM Line Alignment Error Counter 1 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmLineAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_1 : 16; /* 1E.904D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/* MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9050.F:0 ROS MSM Line Tx Pause Frames Counter 0 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_0 : 16; /* 1E.9050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9051.F:0 ROS MSM Line Tx Pause Frames Counter 1 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_1 : 16; /* 1E.9051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/* MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9054.F:0 ROS MSM Line Rx Pause Frames Counter 0 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_0 : 16; /* 1E.9054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9055.F:0 ROS MSM Line Rx Pause Frames Counter 1 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_1 : 16; /* 1E.9055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/* MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9058.F:0 ROS MSM Line Rx Too Long Errors Counter 0 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmLineRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_0 : 16; /* 1E.9058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9059.F:0 ROS MSM Line Rx Too Long Errors Counter 1 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmLineRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_1 : 16; /* 1E.9059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/* MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905C.F:0 ROS MSM Line Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmLineRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_0 : 16; /* 1E.905C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905D.F:0 ROS MSM Line Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmLineRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_1 : 16; /* 1E.905D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/* MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9060.F:0 ROS MSM Line Tx VLAN Frames Counter 0 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_0 : 16; /* 1E.9060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9061.F:0 ROS MSM Line Tx VLAN Frames Counter 1 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_1 : 16; /* 1E.9061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/* MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9064.F:0 ROS MSM Line Rx VLAN Frames Counter 0 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_0 : 16; /* 1E.9064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9065.F:0 ROS MSM Line Rx VLAN Frames Counter 1 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_1 : 16; /* 1E.9065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Octets Counter Register: 1E.9068 */ +/* MSM Line Tx Octets Counter Register: 1E.9068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9068.F:0 ROS MSM Line Tx Octets Counter 0 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u0.bits_0.msmLineTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_0 : 16; /* 1E.9068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9069.F:0 ROS MSM Line Tx Octets Counter 1 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u1.bits_1.msmLineTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_1 : 16; /* 1E.9069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906A.F:0 ROS MSM Line Tx Octets Counter 2 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u2.bits_2.msmLineTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_2 : 16; /* 1E.906A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906B.F:0 ROS MSM Line Tx Octets Counter 3 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u3.bits_3.msmLineTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_3 : 16; /* 1E.906B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmLineTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Octets Counter Register: 1E.906C */ +/* MSM Line Rx Octets Counter Register: 1E.906C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906C.F:0 ROS MSM Line Rx Octets Counter 0 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u0.bits_0.msmLineRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_0 : 16; /* 1E.906C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906D.F:0 ROS MSM Line Rx Octets Counter 1 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u1.bits_1.msmLineRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_1 : 16; /* 1E.906D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/* MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9070.F:0 ROS MSM Line Rx Unicast Frames Counter 0 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_0 : 16; /* 1E.9070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9071.F:0 ROS MSM Line Rx Unicast Frames Counter 1 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_1 : 16; /* 1E.9071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/* MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9074.F:0 ROS MSM Line Rx Multicast Frames Counter 0 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_0 : 16; /* 1E.9074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9075.F:0 ROS MSM Line Rx Multicast Frames Counter 1 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_1 : 16; /* 1E.9075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/* MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9078.F:0 ROS MSM Line Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_0 : 16; /* 1E.9078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9079.F:0 ROS MSM Line Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_1 : 16; /* 1E.9079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Errors Counter Register: 1E.907C */ +/* MSM Line Tx Errors Counter Register: 1E.907C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907C.F:0 ROS MSM Line Tx Errors Counter 0 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u0.bits_0.msmLineTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_0 : 16; /* 1E.907C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907D.F:0 ROS MSM Line Tx Errors Counter 1 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u1.bits_1.msmLineTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_1 : 16; /* 1E.907D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/* MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9084.F:0 ROS MSM Line Tx Unicast Frames Counter 0 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_0 : 16; /* 1E.9084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9085.F:0 ROS MSM Line Tx Unicast Frames Counter 1 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_1 : 16; /* 1E.9085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/* MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9088.F:0 ROS MSM Line Tx Multicast Frames Counter 0 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_0 : 16; /* 1E.9088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9089.F:0 ROS MSM Line Tx Multicast Frames Counter 1 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_1 : 16; /* 1E.9089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/* MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908C.F:0 ROS MSM Line Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_0 : 16; /* 1E.908C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908D.F:0 ROS MSM Line Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_1 : 16; /* 1E.908D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Errors Counter Register: 1E.90C8 */ +/* MSM Line Rx Errors Counter Register: 1E.90C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C8.F:0 ROS MSM Line Rx Errors Counter 0 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u0.bits_0.msmLineRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_0 : 16; /* 1E.90C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C9.F:0 ROS MSM Line Rx Errors Counter 1 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u1.bits_1.msmLineRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_1 : 16; /* 1E.90C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_HHD.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_HHD.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. Pin no longer brought out as deprecated. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_HHD.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_HHD.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved1 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_HHD.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_HHD.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C430.D:9 R/WPD Reserved Provisioning C430 [4:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.reservedProvisioningC430 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC430 : 5; /* 1E.C430.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C431.D:9 R/WPD Reserved Provisioning C431 [4:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.reservedProvisioningC431 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC431 : 5; /* 1E.C431.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C432.D:9 R/WPD Reserved Provisioning C432 [4:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.reservedProvisioningC432 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC432 : 5; /* 1E.C432.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_HHD.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_14; + uint16_t word_14; + } u14; +} AQ_GlobalLedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + + + Notes: + When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + */ + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + unsigned int reserved2 : 1; + unsigned int reserved3 : 2; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_HHD.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.C447.4:0 R/WPD MDIO Broadcast Address Configuration [4:0] + AQ_GlobalGeneralProvisioning_HHD.u7.bits_7.mdioBroadcastAddressConfiguration + + Provisionable Default = 0x1F + + Broadcast address + + + Notes: + Allows setting the broadcast address. By default this is set to 0x1F */ + unsigned int mdioBroadcastAddressConfiguration : 5; /* 1E.C447.4:0 R/WPD Provisionable Default = 0x1F */ + /* Broadcast address + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 9; + /*! \brief 1E.C449.6:0 R/W MDIO Preamble Length [6:0] + AQ_GlobalGeneralProvisioning_HHD.u9.bits_9.mdioPreambleLength + + Default = 0x02 + + MDIO Preamble Length + + */ + unsigned int mdioPreambleLength : 7; /* 1E.C449.6:0 R/W Default = 0x02 */ + /* MDIO Preamble Length + */ + } bits_9; + uint16_t word_9; + } u9; +} AQ_GlobalGeneralProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 5; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the dummy field used in some manufacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + + + Notes: + When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + */ + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + */ + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.C453.4 R/W NVR Reset + AQ_GlobalNvrProvisioning_HHD.u3.bits_3.nvrReset + + Default = 0x0 + + 1 = Reset SPI + + */ + unsigned int nvrReset : 1; /* 1E.C453.4 R/W Default = 0x0 */ + /* 1 = Reset SPI + */ + unsigned int reserved1 : 4; + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalNvrProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + unsigned int reserved0 : 5; + unsigned int reserved1 : 3; + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. + + NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + unsigned int reserved2 : 4; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 9; + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + unsigned int reserved1 : 7; + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + This bit must be set if tuning of external power supply is desired. */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + /*! \brief 1E.C472.5:2 R/WPD External VDD Change Request [3:0] + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.externalVddChangeRequest + + Provisionable Default = 0x0 + + The amount of VDD change requested by firmware, in mV (2's complement value). + + */ + unsigned int externalVddChangeRequest : 4; /* 1E.C472.5:2 R/WPD Provisionable Default = 0x0 */ + /* The amount of VDD change requested by firmware, in mV (2's complement value). + */ + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 5; + /*! \brief 1E.C473.A:8 R/WPD Rate Transition Request [2:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.rateTransitionRequest + + Provisionable Default = 0x0 + + 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + + */ + unsigned int rateTransitionRequest : 3; /* 1E.C473.A:8 R/WPD Provisionable Default = 0x0 */ + /* 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + */ + /*! \brief 1E.C473.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. */ + unsigned int trainingSNR : 8; /* 1E.C473.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C474.F:1 R/WPD Reserved Provisioning 5 [F:1] + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.reservedProvisioning_5 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_5 : 15; /* 1E.C474.F:1 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + /*! \brief 1E.C474.0 R/W NVR Daisy Chain Kickstart + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.nvrDaisyChainKickstart + + Default = 0x0 + + 1 = Kickstart the Daisy Chain + + + Notes: + When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. */ + unsigned int nvrDaisyChainKickstart : 1; /* 1E.C474.0 R/W Default = 0x0 */ + /* 1 = Kickstart the Daisy Chain + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Internal reserved - do not modify + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Internal reserved - do not modify + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + unsigned int reserved1 : 2; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C478.F R/WPD DTE Enable + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteEnable + + Provisionable Default = 0x0 + + 1 = Enable DTE + 0 = Disable DTE + + */ + unsigned int dteEnable : 1; /* 1E.C478.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable DTE + 0 = Disable DTE + */ + /*! \brief 1E.C478.E:B R/WPD DTE Drop Reporting Timer [3:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteDropReportingTimer + + Provisionable Default = 0x0 + + Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + + + Notes: + These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. */ + unsigned int dteDropReportingTimer : 4; /* 1E.C478.E:B R/WPD Provisionable Default = 0x0 */ + /* Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + */ + /*! \brief 1E.C478.A:0 R/WPD Reserved Provisioning 9 [A:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.reservedProvisioning_9 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_9 : 11; /* 1E.C478.A:0 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C479.F R/WPD Power Up Stall + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.powerUpStall + + Provisionable Default = 0x0 + + 1 = Stall FW at Power Up + 0 = Unstall the FW + + + Notes: + This bit needs to be provisioned in Power Up Init for firmware to stall. */ + unsigned int powerUpStall : 1; /* 1E.C479.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Stall FW at Power Up + 0 = Unstall the FW + */ + /*! \brief 1E.C479.E:0 R/WPD Reserved Provisioning 10 [E:0] + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.reservedProvisioning_10 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_10 : 15; /* 1E.C479.E:0 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47A.F:B R/WPD Loopback Control [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.loopbackControl + + Provisionable Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. + */ + unsigned int loopbackControl : 5; /* 1E.C47A.F:B R/WPD Provisionable Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + /*! \brief 1E.C47A.A:6 R/WPD Reserved Provisioning 11 [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11 + + Provisionable Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11 : 5; /* 1E.C47A.A:6 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.5 R/WPD MDI Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.mdiPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int mdiPacketGeneration : 1; /* 1E.C47A.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C47A.4 R/WPD Look-Aside Port Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.look_asidePortPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. + + NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int look_asidePortPacketGeneration : 1; /* 1E.C47A.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C47A.3 R/WPD System I/F Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.systemI_fPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int systemI_fPacketGeneration : 1; /* 1E.C47A.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C47A.2 R/WPD Reserved Provisioning 11a + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11a + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11a : 1; /* 1E.C47A.2 R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.1:0 R/WPD Rate [1:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.rate + + Provisionable Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + + + Notes: + These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int rate : 2; /* 1E.C47A.1:0 R/WPD Provisionable Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47B.F:2 R/WPD Reserved Provisioning 12 [D:0] + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.reservedProvisioning_12 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_12 : 14; /* 1E.C47B.F:2 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + /*! \brief 1E.C47B.1 R/WPD Enable MACSec + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enableMacsec + + Provisionable Default = 0x0 + + 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enableMacsec : 1; /* 1E.C47B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + */ + /*! \brief 1E.C47B.0 R/WPD Enable PTP + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enablePtp + + Provisionable Default = 0x0 + + 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enablePtp : 1; /* 1E.C47B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + */ + } bits_11; + uint16_t word_11; + } u11; +} AQ_GlobalReservedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief PIF Mailbox Control: 1E.C47C */ +/* PIF Mailbox Control: 1E.C47C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47C.F:0 R/WPDuP PIF Mailbox Address [F:0] + AQ_PifMailboxControl_HHD.u0.bits_0.pifMailboxAddress + + Provisionable Default = 0x0000 + + The least 16 bits of the PIF address to read or write. + + */ + unsigned int pifMailboxAddress : 16; /* 1E.C47C.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The least 16 bits of the PIF address to read or write. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47D.F:0 R/WPDuP PIF Mailbox Data [F:0] + AQ_PifMailboxControl_HHD.u1.bits_1.pifMailboxData + + Provisionable Default = 0x0000 + + The data to be written, or that had been read. + + */ + unsigned int pifMailboxData : 16; /* 1E.C47D.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The data to be written, or that had been read. + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47E.F:C R/WPD Reserved PIF Mailbox Control 3 [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.reservedPifMailboxControl_3 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_3 : 4; /* 1E.C47E.F:C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C47E.B:8 R/WPDuP PIF Mailbox Command Type [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxCommandType + + Provisionable Default = 0x0 + + 0 = No Action + 1 = Read + 2 = Write + + + Notes: + System SW writes non-zero value to start a PIF command. */ + unsigned int pifMailboxCommandType : 4; /* 1E.C47E.B:8 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = No Action + 1 = Read + 2 = Write + */ + /*! \brief 1E.C47E.7:0 R/WPDuP PIF Mailbox MMD [7:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxMMD + + Provisionable Default = 0x00 + + MMD (upper 8 bits) of the PID address to read or write. + + */ + unsigned int pifMailboxMMD : 8; /* 1E.C47E.7:0 R/WPDuP Provisionable Default = 0x00 */ + /* MMD (upper 8 bits) of the PID address to read or write. + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47F.F:4 R/WPD Reserved PIF Mailbox Control 4 [B:0] + AQ_PifMailboxControl_HHD.u3.bits_3.reservedPifMailboxControl_4 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_4 : 12; /* 1E.C47F.F:4 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + /*! \brief 1E.C47F.3:0 R/WPDuP PIF Mailbox Command Status [3:0] + AQ_PifMailboxControl_HHD.u3.bits_3.pifMailboxCommandStatus + + Provisionable Default = 0x0 + + 0 = Idle + 1 = Command completed + 2 = Command did not complete + + + Notes: + System SW should write 0 before writing Command Type to clear completion status */ + unsigned int pifMailboxCommandStatus : 4; /* 1E.C47F.3:0 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = Idle + 1 = Command completed + 2 = Command did not complete + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_PifMailboxControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 0 Provisioning: 1E.C485 */ +/* Global SMBus 0 Provisioning: 1E.C485 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 0 Provisioning */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.C485.7:1 R/W SMB 0 Slave Address [7:1] + AQ_GlobalSmbus_0Provisioning_HHD.u0.bits_0.smb_0SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_0SlaveAddress : 7; /* 1E.C485.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved1 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_0Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 1 Provisioning: 1E.C495 */ +/* Global SMBus 1 Provisioning: 1E.C495 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 1 Provisioning */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.C495.7:1 R/W SMB 1 Slave Address [7:1] + AQ_GlobalSmbus_1Provisioning_HHD.u0.bits_0.smb_1SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_1SlaveAddress : 7; /* 1E.C495.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved1 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_1Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global EEE Provisioning: 1E.C4A0 */ +/* Global EEE Provisioning: 1E.C4A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global EEE Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C4A0.0 R/WPD EEE Mode + AQ_GlobalEeeProvisioning_HHD.u0.bits_0.eeeMode + + Provisionable Default = 0x0 + + 1 = EEE mode of operation + + + Notes: + EEE mode of operation (0=disable, 1=enable, default:0) */ + unsigned int eeeMode : 1; /* 1E.C4A0.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = EEE mode of operation + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalEeeProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairAStatus + + + + [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + Notes: + This register summarizes the worst impairment on Pair A. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairBStatus + + + + [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + Notes: + This register summarizes the worst impairment on Pair B. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairCStatus + + + + [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + Notes: + This register summarizes the worst impairment on Pair C. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairDStatus + + + + [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + Notes: + This register summarizes the worst impairment on Pair D. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u6.bits_6.reserved_1 + + + + Reserved for future use + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_GlobalCableDiagnosticStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_HHD.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_HHD.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_HHD.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes + 1E.C470.4, Cable diagnostics + 1E.C47A.F:B, Loopback Control + 1E.C47A.4:2, Packet generation */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + unsigned int reserved0 : 1; + unsigned int reserved1 : 1; + /*! \brief 1E.C840.D RO DC_MASTER_N + AQ_GlobalPinStatus_HHD.u0.bits_0.dcMasterN + + + + Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH + */ + unsigned int dcMasterN : 1; /* 1E.C840.D RO */ + /* Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH */ + unsigned int reserved2 : 3; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_HHD.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_HHD.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved4 : 1; + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_HHD.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_HHD.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_HHD.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_1 + + + + Reserved + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_2 + + + + Reserved + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_3 + + + + Reserved + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_4 + + + + Reserved + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved + */ + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_5 + + + + Reserved + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_6 + + + + Reserved + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_7 + + + + Reserved + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_8 + + + + Reserved + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved + */ + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_9 + + + + Reserved + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_10 + + + + Reserved + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_11 + + + + Reserved + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_12 + + + + Reserved + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved + */ + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_13 + + + + Reserved + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_14 + + + + Reserved + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_15 + + + + Reserved + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_16 + + + + Reserved + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved + */ + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.reservedStatus_0 + + + + Reserved + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved + */ + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.7:4 ROSPD Firmware Build ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.firmwareBuildID + + Provisionable Default = 0x0 + + Firmware Build ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int firmwareBuildID : 4; /* 1E.C885.7:4 ROSPD Provisionable Default = 0x0 */ + /* Firmware Build ID + */ + /*! \brief 1E.C885.3:0 ROSPD Provisioning ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.provisioningID + + Provisionable Default = 0x0 + + Provisioning ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int provisioningID : 4; /* 1E.C885.3:0 ROSPD Provisionable Default = 0x0 */ + /* Provisioning ID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW [F:0] + AQ_GlobalReservedStatus_HHD.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C887.F ROS DTE Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.dteStatus + + Default = 0x0 + + 1 = Need power + 0 = Don't need power + + */ + unsigned int dteStatus : 1; /* 1E.C887.F ROS Default = 0x0 */ + /* 1 = Need power + 0 = Don't need power + */ + /*! \brief 1E.C887.E ROS Power Up Stall Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.powerUpStallStatus + + Default = 0x0 + + 1 = FW is stalled at power up + 0 = Firmware is unstalled + + */ + unsigned int powerUpStallStatus : 1; /* 1E.C887.E ROS Default = 0x0 */ + /* 1 = FW is stalled at power up + 0 = Firmware is unstalled + */ + /*! \brief 1E.C887.D:0 RO Reserved Status 3 [D:0] + AQ_GlobalReservedStatus_HHD.u2.bits_2.reservedStatus_3 + + + + Reserved for future use + + */ + unsigned int reservedStatus_3 : 14; /* 1E.C887.D:0 RO */ + /* Reserved for future use + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C888.F:B RO Loopback Status [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.loopbackStatus + + Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. + + */ + unsigned int loopbackStatus : 5; /* 1E.C888.F:B RO Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + /*! \brief 1E.C888.A:6 RO Reserved Status 4 [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4 + + Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedStatus_4 : 5; /* 1E.C888.A:6 RO Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.5 RO MDI Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.mdiPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. */ + unsigned int mdiPacketGenerationStatus : 1; /* 1E.C888.5 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C888.4 RO Look-Aside Port Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.look_asidePortPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. */ + unsigned int look_asidePortPacketGenerationStatus : 1; /* 1E.C888.4 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C888.3 RO System I/F Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.systemI_fPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. */ + unsigned int systemI_fPacketGenerationStatus : 1; /* 1E.C888.3 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C888.2 RO Reserved Status 4a + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4a + + Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedStatus_4a : 1; /* 1E.C888.2 RO Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.1:0 RO Rate [1:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.rate + + Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + + + Notes: + These bits report the selected rate for the loopback and packet generation. */ + unsigned int rate : 2; /* 1E.C888.1:0 RO Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalReservedStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_HHD.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_HHD.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_HHD.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_HHD.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.C LH IP Phone Detect + AQ_GlobalAlarms_HHD.u1.bits_1.ipPhoneDetect + + + + 1 = IP Phone Detect + + + Notes: + Assertion of this bit means that the presence of an IP Phone has been detected. */ + unsigned int ipPhoneDetect : 1; /* 1E.CC01.C LH */ + /* 1 = IP Phone Detect + */ + /*! \brief 1E.CC01.B LH DTE Status Change + AQ_GlobalAlarms_HHD.u1.bits_1.dteStatusChange + + + + 1 = DTE status change + + + Notes: + Change in 1E.C887[F]. */ + unsigned int dteStatusChange : 1; /* 1E.CC01.B LH */ + /* 1 = DTE status change + */ + /*! \brief 1E.CC01.A:8 LH Reserved Alarms [2:0] + AQ_GlobalAlarms_HHD.u1.bits_1.reservedAlarms + + + + Reserved + + + */ + unsigned int reservedAlarms : 3; /* 1E.CC01.A:8 LH */ + /* Reserved + + */ + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_HHD.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + unsigned int reserved1 : 6; + unsigned int reserved2 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_HHD.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_HHD.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_HHD.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_HHD.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_HHD.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_HHD.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.C R/WPD IP Phone Detect Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.ipPhoneDetectMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int ipPhoneDetectMask : 1; /* 1E.D401.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.B R/WPD DTE Status Change Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.dteStatusChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int dteStatusChangeMask : 1; /* 1E.D401.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.A:8 R/WPD Reserved Alarms Mask [2:0] + AQ_GlobalInterruptMask_HHD.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 3; /* 1E.D401.A:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_HHD.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_HHD; + +#endif +/*@}*/ +/*@}*/ diff --git a/firmware/aq-fw-download/src/mdioBootLoadCLD.c b/firmware/aq-fw-download/src/mdioBootLoadCLD.c new file mode 100755 index 0000000..a8e09d8 --- /dev/null +++ b/firmware/aq-fw-download/src/mdioBootLoadCLD.c @@ -0,0 +1,193 @@ +/* mdioBootLoadCLD.c */ + +/************************************************************************************ +* Copyright (c) 2015 Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/flashUtilities/src/mdioBootLoadCLD.c $ +* +* $Revision: #12 $ +* +* $DateTime: 2014/05/19 15:34:49 $ +* +* $Author: joshd $ +* +* $Label: $ +* +************************************************************************************/ + +/*! \file +This file contains the main (int, char**) file for the mdioBootLoadCLD program, which burns a flash image into a target +Aquantia PHY using the AQ_API. This program calls the API function:

+ + uint8_t AQ_API_WriteBootLoadImage (uint8_t PHY_ID, uint8_t *image, uint16_t *crc16)

+ +to boot load a cld flash image into an Aquantia PHY */ + +/*! \addtogroup mdioBootLoad +@{ +*/ + + + +/*! \def DEBUG +Uncomment this to compile in debug mode. This sets the source to an arbitrary file, defined by DEBUG_FILENAME, +and an arbitrary PHY_ID, defined by DEBUG_PHY_ID. */ +/* #define DEBUG */ + +/*! The debug source file name */ +#define DEBUG_FILENAME "HelloWorld.cld" + +/*! The debug PHY ID */ +#define DEBUG_PHY_ID 0 + + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "AQ_API.h" +#include "AQ_PhyInterface.h" + +int sock; +char devname[7]; + +int sock_init() +{ + if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) < 0) { + fprintf(stderr, "Error creating socket: %s\n", strerror(errno)); + return -1; + } + + return 0; +} + +int main ( int argc, char **argp) +{ + /* declare local variables */ + FILE *pFile; + uint8_t* image; + uint8_t byte; + unsigned int PHY_ID; + AQ_Retcode resultCode; + AQ_Retcode resultCodes[4]; + uint32_t i; + uint32_t imageSize; + char sourceFileName[1000]; + AQ_API_Port targetPort0; + AQ_API_Port* targetPorts[1]; + AQ_API_Port broadcastPort; + unsigned int provisioningAddresses[1] = {0}; + uint32_t reg1, reg2; + + targetPorts[0] = &targetPort0; + + if(argc < 4) { + fprintf (stderr, "enter file name/netdev name/phy address\n"); + return (101); + } + + /*Copy the file name from command line arg*/ + if (strlcpy (sourceFileName, argp[1], sizeof(sourceFileName)) >= sizeof(sourceFileName)) { + fprintf (stderr, "Filename: %s too long \n", argp[1]); + return (101); + } + /*Copy the interface name from command line arg*/ + strlcpy (devname, argp[2], sizeof(devname)); + /*Get PHY Address from command line arg*/ + PHY_ID = (unsigned int)strtoul(argp[3], NULL, 0); + + /* FIXME: set port and device type */ + targetPort0.device = AQ_DEVICE_HHD; + targetPort0.PHY_ID = PHY_ID; + + broadcastPort.device = AQ_DEVICE_HHD; + broadcastPort.PHY_ID = PHY_ID; + + /* open the source in binary read mode */ + pFile = fopen(sourceFileName, "rb"); + if (pFile == NULL) + { + fprintf (stderr, "Unable to open source file %s\n", sourceFileName); + return (101); + } + fseek (pFile, 0, SEEK_END); + imageSize = ftell (pFile); + + image = (uint8_t*) malloc (imageSize * sizeof(uint8_t)); + fseek (pFile, 0, SEEK_SET); + + /* load the file */ + for (i = 0; i < imageSize; i++) + { + byte = (uint8_t) fgetc (pFile); + image[i] = byte; + } + fclose(pFile); + + + if (sock_init() < 0) + { + fprintf (stderr, "Unable to initialize interface\n"); + return (200); + } + + /* Write in the Auantia phy scratch pad register, + * read back the same reg and match the values written. + */ + AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x300, 0xdead); + AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x301, 0xbeaf); + reg1 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x300); + reg2 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x301); + if(reg1 != 0xdead && reg2 != 0xbeaf) { + fprintf (stderr, "Scratchpad Read/Write test fail\n"); + return (101); + } + + /* call the boot-load function */ + resultCode = AQ_API_WriteBootLoadImage(targetPorts, 1, provisioningAddresses, resultCodes, &imageSize, image, PHY_ID, &broadcastPort); + + switch (resultCode) + { + case 0: + printf("Image load good - mailbox CRC-16 matches\n"); + free (image); + close(sock); + return 0; + + case 1: + fprintf (stderr, "CRC-16 on file is bad\n"); + free (image); + close(sock); + return 1; + + case 2: + fprintf (stderr, "CRC-16 check on image load failed (mailbox CRC-16 check)\n"); + free (image); + close(sock); + return 2; + + default: + fprintf (stderr, "Invalid return code\n"); + free (image); + close(sock); + } + return 12; +} +/*@}*/ diff --git a/firmware/aq-fw-download/src/src/AQ_API.c b/firmware/aq-fw-download/src/src/AQ_API.c new file mode 100755 index 0000000..89e7334 --- /dev/null +++ b/firmware/aq-fw-download/src/src/AQ_API.c @@ -0,0 +1,1021 @@ +/*AQ_API.c*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file contains the code for all of the API functions defined in AQ_API.h +* +************************************************************************************/ + + +/*! \file +* This file contains the code for all of the API functions defined in AQ_API.h + */ + +#include +#include + +#include "AQ_API.h" +#include "AQ_User.h" +#include "AQ_RegMacro.h" +#include "AQ_PlatformRoutines.h" +#include "AQ_RegMaps.h" +#include "AQ_ReturnCodes.h" + +#ifdef AQ_VERBOSE + #include + #include +#endif + + +#ifndef AQ_TIME_T_EXISTS + #ifndef AQ_MDIO_READS_PER_SECOND + #error AQ_MDIO_READS_PER_SECOND in AQ_User.h must be defined, as AQ_TIME_T_EXISTS is currently undefined! + #endif +#endif + +#ifdef AQ_TIME_T_EXISTS + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef AQ_ENABLE_UP_BUSY_CHECKS + #ifdef AQ_VERBOSE + #define AQ_API_UP_BUSY_PRINT_STATEMENT printf("uP-busy check timed out.\n"); + #else + #define AQ_API_UP_BUSY_PRINT_STATEMENT /* nothing */ + #endif + + #ifdef AQ_TIME_T_EXISTS + #define AQ_API_UP_BUSY_TIMEOUT (CLOCKS_PER_SEC / 10) + + #define AQ_API_DECLARE_UP_BUSY_VARS AQ_API_Variable(AQ_GlobalGeneralStatus) \ + uint16_t uPbusy; \ + clock_t startTime; \ + AQ_boolean uPBusyTimeoutOccurred = False; + + #define AQ_API_CHECK_UP_NOT_BUSY AQ_API_Wait(1, port); \ + startTime = clock(); \ + do \ + { \ + AQ_API_Get(port->PHY_ID, AQ_GlobalGeneralStatus, processorIntensiveMdioOperationIn_Progress, uPbusy); \ + if ((clock() - startTime) > AQ_API_UP_BUSY_TIMEOUT) \ + { \ + AQ_API_UP_BUSY_PRINT_STATEMENT \ + uPBusyTimeoutOccurred = True; \ + break; \ + } \ + } while (uPbusy != 0); + #else + #define AQ_API_UP_BUSY_MAX_CHECKS (AQ_MDIO_READS_PER_SECOND * 5) + + #define AQ_API_DECLARE_UP_BUSY_VARS AQ_API_Variable(AQ_GlobalGeneralStatus) \ + uint16_t uPbusy; \ + uint32_t numChecks; \ + AQ_boolean uPBusyTimeoutOccurred = False; + + #define AQ_API_CHECK_UP_NOT_BUSY AQ_API_Wait(1, port); \ + numChecks = 0; \ + do \ + { \ + AQ_API_Get(port->PHY_ID, AQ_GlobalGeneralStatus, processorIntensiveMdioOperationIn_Progress, uPbusy); \ + if (numChecks++ > AQ_API_UP_BUSY_MAX_CHECKS) \ + { \ + AQ_API_UP_BUSY_PRINT_STATEMENT \ + uPBusyTimeoutOccurred = True; \ + break; \ + } \ + } while (uPbusy != 0); + #endif + + /* If a uP busy timeout occurred, return the corresponding return code; otherwise, return + * retval. retval should be a return code defined in AQ_ReturnCodes. */ + #define AQ_API_RETURN_UP_BUSY(retval) return (uPBusyTimeoutOccurred ? AQ_RET_UP_BUSY_TIMEOUT : retval); + +#else + #define AQ_API_DECLARE_UP_BUSY_VARS /* nothing */ + #define AQ_API_CHECK_UP_NOT_BUSY /* nothing */ + #define AQ_API_RETURN_UP_BUSY(retval) return retval; +#endif + + +/*! FW image version string maximum length. */ +#define AQ_VERSION_STRING_SIZE 0x40 + +/*! The byte offset from top of DRAM to the FW image version string. */ +#define AQ_VERSION_STRING_BLOCK_OFFSET 0x0200 + +/*! The byte address, in processor memory, of the start of the IRAM segment. */ +#define AQ_IRAM_BASE_ADDRESS 0x40000000 + +/*! The byte address, in processor memory, of the start of the DRAM segment. */ +#define AQ_DRAM_BASE_ADDRESS 0x3FFE0000 + +/*! The byte offset from the top of the PHY image to the header content (HHD devices). */ +#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300 + +/*! The byte offset from the top of the PHY image to the header content (APPIA devices). */ +#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_APPIA 0 + +/*! The offset, from the start of DRAM, where the provisioning block begins. */ +#define AQ_PHY_IMAGE_PROVTABLE_OFFSET 0x680 + +/*! The offset, from the start of DRAM, where the provisioning block's ending address is recorded. */ +#define AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET 0x028C + +/*! The size of the space alloted within the PHY image for the provisioning table. */ +#define AQ_PHY_IMAGE_PROVTABLE_MAXSIZE 0x800 + +/*! The maximum number of polling cycles ever required before the FLASH interface is ready. */ +#define AQ_FLASH_INTERFACE_MAX_POLL_COUNT 20 + +/*! The maximum number of ports that can be MDIO bootloaded at once. */ +#define AQ_MAX_NUM_PHY_IDS 48 + +/*! The maximum allowed number of times to poll for debug-trace-freeze acknowledgement. */ +#define AQ_MAX_FREEZE_CHECKS 2000 + +/*! The maximum size of the debug trace buffer. */ +#define AQ_MAX_TRACE_BUFFER_LENGTH 8192 + +/*! The maximum allowed number of times to poll for SERDES Rx eye measurement done. */ +#define AQ_SERDESEYE_MAX_DONE_CHECKS 50 + +/*! The maximum allowed number of times to poll for PIF mailbox status. */ +#define MAX_NUM_COMMAND_STATUS_POLLS 700 + +/* REGDOC_START */ + + +/********************************************************************************************************************** +* MDIO Boot Load +**********************************************************************************************************************/ + +const uint16_t AQ_CRC16Table[256] = {0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0}; + +/*! \addtogroup writingImages + @{ +*/ + +/*! Prepare the specified port for MDIO bootloading. Disables the daisy-chain, + * and explicitly sets the port's provisioningAddress. */ +void AQ_API_EnableMDIO_BootLoadMode +( + /*! The target PHY port.*/ + AQ_API_Port* port, + /*! The provisioning address to use when the FW starts and applies the + * bootloaded image's provisioned values. */ + unsigned int provisioningAddress +) +{ + AQ_API_Variable(AQ_GlobalNvrProvisioning) + + AQ_API_DeclareLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning) + + + /* disable the daisy-chain */ + /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C452.0) */ + AQ_API_Set(port->PHY_ID, AQ_GlobalNvrProvisioning, nvrDaisyChainDisable, 1); + + /* override the hop-count */ + AQ_API_AssignWordOfLocalStruct(globalReservedProvisioning, 1, + /* REGDOC: Read register (HHD/APPIA: 1E.C470 + 1) */ + AQ_API_ReadRegister(port->PHY_ID, AQ_GlobalReservedProvisioning, 1)); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C471.5:0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning, + daisy_chainHop_countOverrideValue, provisioningAddress); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C471.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning, + enableDaisy_chainHop_countOverride, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.C470 + 1) */ + AQ_API_WriteRegister(port->PHY_ID, AQ_GlobalReservedProvisioning, 1, + AQ_API_WordOfLocalStruct(globalReservedProvisioning, 1)); + + return; +} + + +/*! Prepare the specified port for MDIO bootloading, and set the temporary MDIO + * address to be used during the bootload process. Disables the daisy-chain, + * and explicitly sets the port's provisioningAddress. */ +void AQ_API_EnableGangLoadMode +( + /*! The target PHY port.*/ + AQ_API_Port* port, + /*! The provisioning address to use when the FW starts and applies the + * bootloaded image's provisioned values. */ + unsigned int provisioningAddress, + /*! The PHY's MDIO address will be changed to this value during the + * bootload process. */ + unsigned int gangLoadAddress +) +{ + /*AQ_API_Variable_DeviceRestricted(APPIA, AQ_GlobalGeneralProvisioning)*/ + AQ_API_Variable(AQ_GlobalGeneralProvisioning) + + + /* Get ready for MDIO bootloading. */ + AQ_API_EnableMDIO_BootLoadMode(port, provisioningAddress); + + /* Enable gangload mode. After doing this, the PHY will be + * addressable at the MDIO address indicated by gangLoadAddress. + * Now that the PHY is in gangload mode, MDIO reads are prohibited + * until AQ_API_DisableGangLoadMode is called. */ + if (AQ_DEVICE_APPIA == port->device) + { + /* REGDOC: Read-Modify-Write bitfield (APPIA: 1E.C440.8:4) */ + AQ_API_Set_DeviceRestricted(APPIA, port->PHY_ID, AQ_GlobalGeneralProvisioning, + gangLoadMdioAddress, gangLoadAddress); + } + else if (AQ_DEVICE_HHD == port->device) + { + /* REGDOC: Read-Modify-Write bitfield (HHD: 1E.C447.4:0) */ + AQ_API_Set_DeviceRestricted(HHD, port->PHY_ID, AQ_GlobalGeneralProvisioning, + mdioBroadcastAddressConfiguration, gangLoadAddress); + /* REGDOC: Read-Modify-Write bitfield (HHD: 1E.C441.E) */ + AQ_API_Set_DeviceRestricted(HHD, port->PHY_ID, AQ_GlobalGeneralProvisioning, + mdioBroadcastModeEnable, 1); + } + + return; +} + + +/*! Restore the PHY's MDIO address to the pin-specified value. Should be + * called when MDIO bootloading is complete, to return to normal MDIO + * addressing. + * This is a gang-load function, hence write-only! */ +void AQ_API_DisableGangLoadMode +( + /*! The target PHY port.*/ + AQ_API_Port* port, + /*! The value to write to of AQ_GlobalGeneralProvisioning.u1.word_1. */ + uint16_t origVal_GGP1 +) +{ + AQ_API_DeclareLocalStruct(AQ_GlobalGeneralProvisioning, globalGeneralProvisioning) + + + /* Restore the original value of globalGeneralProvisioning.u1, and set + * the MDIO address reset bit. This will cause the MDIO address to be + * reset to the value indicated by the pins. */ + AQ_API_AssignWordOfLocalStruct(globalGeneralProvisioning, 1, origVal_GGP1); + if (AQ_DEVICE_APPIA == port->device) + { + /* REGDOC: Assign to local representation of bitfield (APPIA: 1E.C441.2) */ + AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA, AQ_GlobalGeneralProvisioning, + globalGeneralProvisioning, mdioAddressReset, 1); + } + else if (AQ_DEVICE_HHD == port->device) + { + /* REGDOC: Assign to local representation of bitfield (HHD: 1E.C441.E) */ + AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(HHD, AQ_GlobalGeneralProvisioning, + globalGeneralProvisioning, mdioBroadcastModeEnable, 0); + } + /* REGDOC: Write register (HHD/APPIA: 1E.C440 + 1) */ + AQ_API_WriteRegister(port->PHY_ID, AQ_GlobalGeneralProvisioning, 1, + AQ_API_WordOfLocalStruct(globalGeneralProvisioning, 1)); + + /* The PHY has now exited gang-load mode. */ + return; +} + + +AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable +( + AQ_API_Port** ports, + unsigned int numPorts, + unsigned int* provisioningAddresses, + AQ_Retcode* resultCodes, + uint32_t* imageSizePointer, + uint8_t* image, + uint8_t gangload_MDIO_address, + AQ_API_Port* gangloadPort, + uint32_t* provTableSizePointer, + uint8_t* provTableImage +) +{ + /*------------------------------------- NOTE!!!!!!!!!! ----------------------------------------------------------*/ + /* This function uses word level writes here as in gang-load mode we cannot do a read in a read-modify-write */ + /* operation */ + /*---------------------------------------------------------------------------------------------------------------*/ + + AQ_API_Variable_DeviceRestricted(APPIA, AQ_GlobalPinStatus) + + AQ_API_DeclareLocalStruct(AQ_GlobalControl, globalControl) + AQ_API_DeclareLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface) + + AQ_API_Port* port; + uint32_t primaryHeaderPtr = 0x00000000; + uint32_t primaryIramPtr = 0x00000000; + uint32_t primaryDramPtr = 0x00000000; + uint32_t primaryIramSize = 0x00000000; + uint32_t primaryDramSize = 0x00000000; + uint32_t terminatorPtr = 0x00000000; + uint32_t phyImageHeaderContentOffset; + uint32_t i; + uint32_t j; + uint32_t imageSize; + uint32_t provTableImageSize = 0; + uint32_t bytePointer; + uint32_t byteSize; + uint32_t dWordSize; +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + uint32_t countPendingOps; /* A count of block MDIO operation pending... necessary to keep a count + in order to ensure we don't exceed the maximum pending operations. */ +#endif + uint16_t msw; + uint16_t lsw; + uint16_t crc16Calculated; + uint16_t provTableCrc16Calculated; + uint16_t fileCRC; + uint16_t provTableFileCRC; + uint16_t mailboxCRC; + uint16_t mailboxWrite; + uint16_t bootLoadMode; + uint16_t recordedGGP1Values[AQ_MAX_NUM_PHY_IDS]; /* When entering/exiting gangload mode, we record and restore + the AQ_GlobalGeneralProvisioning.u1 register values. */ + + + /* store the CRC-16 for the image, which is the last two bytes */ + imageSize = *imageSizePointer; + fileCRC = image[imageSize-2] << 8 | image[imageSize-1]; + + /*------------------------------------- Check the image integrity ------------------------------------------------*/ + crc16Calculated = 0x0000; + for (i = 0; i < imageSize-2; i++) + { + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ image[i]]; + } + + if (crc16Calculated != fileCRC) + { + #ifdef AQ_VERBOSE + printf ("CRC check failed on image file (expected 0x%X, found 0x%X)\n", + fileCRC, crc16Calculated); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "bad image". */ + resultCodes[j] = AQ_RET_FLASH_IMAGE_CORRUPT; + } + return AQ_RET_ERROR; + } +#ifdef AQ_VERBOSE + else + { + printf ("CRC check good on image file (0x%04X)\n", crc16Calculated); + } +#endif + + /*-------------------------------- Check the provisioning table image integrity ----------------------------------*/ + if (provTableSizePointer != NULL && provTableImage != NULL) + { + provTableImageSize = (*provTableSizePointer) - 2; + provTableFileCRC = provTableImage[provTableImageSize + 1] << 8 | + provTableImage[provTableImageSize]; + + provTableCrc16Calculated = 0x0000; + for (i = 0; i < provTableImageSize; i++) + { + provTableCrc16Calculated = ((provTableCrc16Calculated & 0xFF) << 8) ^ + AQ_CRC16Table[(provTableCrc16Calculated >> 8) ^ provTableImage[i]]; + } + + if (provTableCrc16Calculated != provTableFileCRC) + { + #ifdef AQ_VERBOSE + printf ("CRC check failed on provisioning table file (expected 0x%X, found 0x%X)\n", + provTableFileCRC, provTableCrc16Calculated); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "bad image". */ + resultCodes[j] = AQ_RET_FLASH_IMAGE_CORRUPT; + } + return AQ_RET_ERROR; + } + #ifdef AQ_VERBOSE + else + { + printf ("CRC check good on provisioning table file (0x%04X)\n", + provTableCrc16Calculated); + } + #endif + } + + /*------------------------ Check that all provisioning addresses are in the proper range. ------------------------*/ + for (j = 0; j < numPorts; j++) + { + if (provisioningAddresses[j] > 47) + { + #ifdef AQ_VERBOSE + printf ("Provisioning address out of range 0-47 (index %u: %d)\n", j, provisioningAddresses[j]); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "provisioning address out-of-range". */ + resultCodes[j] = AQ_RET_BOOTLOAD_PROVADDR_OOR; + } + return AQ_RET_ERROR; + } + } + + /*--------------------------- Store 1E.C441 values for later use. Enforce uniformity. ---------------------------*/ + for (j = 0; j < numPorts; j++) + { + /* Record the original value of AQ_GlobalGeneralProvisioning.u1.word_1, + * so that we can restore it later after exiting gangload mode. */ + port = ports[j]; + /* REGDOC: Read register (HHD/APPIA: 1E.C440 + 1) */ + recordedGGP1Values[j] = AQ_API_ReadRegister(port->PHY_ID, AQ_GlobalGeneralProvisioning, 1); + + /* If any of the PHYs' GGP1 values don't match the others, set the appropriate + * error code and return. */ + if (j > 0 && recordedGGP1Values[j] != recordedGGP1Values[0]) + { + #ifdef AQ_VERBOSE + printf ("Non-uniform value of 1E.C441 found (expected 0x%X, found 0x%X)\n", + recordedGGP1Values[0], recordedGGP1Values[j]); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "non-uniform GGP1 values". */ + resultCodes[j] = AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS; + } + return AQ_RET_ERROR; + } + } + + /*--------------------------- Put each PHY into gangload mode at the specified address ---------------------------*/ + for (j = 0; j < numPorts; j++) + { + AQ_API_EnableGangLoadMode(ports[j], provisioningAddresses[j], gangload_MDIO_address); + } + /* Set up the port context for using device-restricted macros while in + * gangload mode. */ + port = gangloadPort; + + /*------------------------------------- Stall the uP ------------------------------------------------------------*/ + AQ_API_AssignWordOfLocalStruct(globalControl, 1, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + + /*------------------------------------- Initialize the mailbox write command -------------------------------------*/ + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 0, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.E) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, upMailboxWriteMode, 1); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, upMailboxExecuteOperation, 1); + mailboxWrite = AQ_API_WordOfLocalStruct(globalMailboxInterface, 0); + + /*------------------------------------- Read the segment addresses and sizes -------------------------------------*/ + primaryHeaderPtr = (((image[0x9] & 0x0F) << 8) | image[0x8]) << 12; + + if (AQ_DEVICE_APPIA == port->device) + phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_APPIA; + else /* HHD */ + phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD; + + primaryIramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4]; + primaryIramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7]; + primaryDramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA]; + primaryDramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD]; + + if (AQ_DEVICE_HHD == port->device) + { + primaryIramPtr += primaryHeaderPtr; + primaryDramPtr += primaryHeaderPtr; + } + +#ifdef AQ_VERBOSE + printf ("\nSegment Addresses and Sizes as read from the PHY ROM image header:\n\n"); + printf ("Primary Iram Address: 0x%x\n", primaryIramPtr); + printf ("Primary Iram Size: 0x%x\n", primaryIramSize); + printf ("Primary Dram Address: 0x%x\n", primaryDramPtr); + printf ("Primary Dram Size: 0x%x\n\n", primaryDramSize); +#endif + + /*----------------------------- Merge the provisioning table into the main image ---------------------------------*/ + if (provTableSizePointer != NULL && provTableImage != NULL) + { + /* Locate the terminator of the built-in provisioning table */ + terminatorPtr = primaryDramPtr + + ((image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET + 1] << 8) | + image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET]); + + #ifdef AQ_VERBOSE + printf("Supplied Provisioning Table At Address: 0x%x\n\n", terminatorPtr); + #endif + + /* Check that the supplied provisioning table will fit within the alloted + * space. */ + if (terminatorPtr - (primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_OFFSET) + + provTableImageSize > AQ_PHY_IMAGE_PROVTABLE_MAXSIZE) + { + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "provisioning + * table too large". */ + resultCodes[j] = AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE; + } + return AQ_RET_ERROR; + } + + /* Write the supplied provisioning table into the image, starting at the + * terminator address. */ + for (i = 0; i < provTableImageSize; i++) + { + image[terminatorPtr + i] = provTableImage[i]; + } + } + + /*------------------------------------- Load IRAM and DRAM -------------------------------------------------------*/ + /* clear the mailbox CRC */ + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 0, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.C) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, resetUpMailboxCrc, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, + AQ_API_WordOfLocalStruct(globalMailboxInterface, 0)); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, 0x0000); + + crc16Calculated = 0; /* This is to calculate what was written through the mailbox */ + + /* load the IRAM */ +#ifdef AQ_VERBOSE + printf ("\nLoading IRAM:\n\n"); +#endif + + /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord + boundaries, so the 2 LSbits of the block start are always zero. */ + msw = (uint16_t) (AQ_IRAM_BASE_ADDRESS >> 16); + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 3, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0203.1:0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, + upMailboxAddressLSW , (AQ_IRAM_BASE_ADDRESS & 0xFFFF) >> 2); + lsw = AQ_API_WordOfLocalStruct(globalMailboxInterface, 3); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 2) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 2, msw); /* MSW */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 3) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 3, lsw); /* LSW */ + + + /* set block size so that there are from 0-3 bytes remaining */ + byteSize = primaryIramSize; + dWordSize = byteSize >> 2; + + bytePointer = primaryIramPtr; +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + countPendingOps = 0; +#endif + for (i = 0; i < dWordSize; i++) + { + /* write 4 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + + #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + + countPendingOps += 3; + /* Check if we've filled our output buffer, and if so, flush. */ + if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3 ) + { + AQ_API_MDIO_BlockOperationExecute (gangloadPort->PHY_ID); + countPendingOps = 0; + } + #else + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + #endif + + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + + #ifdef AQ_VERBOSE + if (i && ((i % 512) == 0)) printf(" Byte: %X:\n", i << 2); + #endif + } + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + /* flush the output buffer one last time. */ + AQ_API_MDIO_BlockOperationExecute(gangloadPort->PHY_ID); + countPendingOps = 0; +#endif + + /* Note: this final write right-justifies non-dWord data in the final dWord */ + switch (byteSize & 0x3) + { + case 0x1: + /* write 1 byte of data */ + lsw = image[bytePointer++]; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x2: + /* write 2 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x3: + /* write 3 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = image[bytePointer++]; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + } + + if (byteSize & 0x3) + { + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + } + + /* load the DRAM */ +#ifdef AQ_VERBOSE + printf ("\nCRC-16 after loading IRAM: 0x%X\n", crc16Calculated); + printf ("\nLoading DRAM:\n\n"); +#endif + + /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord + boundaries, so the 2 LSbits of the block start are always zero. */ + msw = (uint16_t) (AQ_DRAM_BASE_ADDRESS >> 16); + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 3, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0203.1:0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, + upMailboxAddressLSW, (AQ_DRAM_BASE_ADDRESS & 0xFFFF) >> 2); + lsw = AQ_API_WordOfLocalStruct(globalMailboxInterface, 3); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 2) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 2, msw); /* MSW */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 3) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 3, lsw); /* LSW */ + + + /* set block size so that there are from 0-3 bytes remaining */ + byteSize = primaryDramSize; + dWordSize = byteSize >> 2; + + bytePointer = primaryDramPtr; + for (i = 0; i < dWordSize; i++) + { + /* write 4 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + + #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + + countPendingOps += 3; + /* Check if we've filled our output buffer, and if so, flush. */ + if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3 ) + { + AQ_API_MDIO_BlockOperationExecute (gangloadPort->PHY_ID); + countPendingOps = 0; + } + #else + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + #endif + + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + + #ifdef AQ_VERBOSE + if (i && ((i % 512) == 0)) printf(" Byte: %X:\n", i << 2); + #endif + } + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + /* flush the output buffer one last time. */ + AQ_API_MDIO_BlockOperationExecute(gangloadPort->PHY_ID); + countPendingOps = 0; +#endif + + /* Note: this final write right-justifies non-dWord data in the final dWord */ + switch (byteSize & 0x3) + { + case 0x1: + /* write 1 byte of data */ + lsw = image[bytePointer++]; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x2: + /* write 2 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x3: + /* write 3 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = image[bytePointer++]; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + } + + if (byteSize & 0x3) + { + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + } + + /*------------------------------------- Exit gangload mode -------------------------------------------------------*/ + AQ_API_DisableGangLoadMode(gangloadPort, recordedGGP1Values[0]); + + /*------------------------------------- Check mailbox CRCs -------------------------------------------------------*/ + /* check to make sure the mailbox CRC matches the calculated CRC */ + /*foundMailboxCRCMismatch = False;*/ + for (j = 0; j < numPorts; j++) + { + /* REGDOC: Read register (HHD/APPIA: 1E.0200 + 1) */ + mailboxCRC = AQ_API_ReadRegister(ports[j]->PHY_ID,AQ_GlobalMailboxInterface, 1); + if (mailboxCRC != crc16Calculated) + { + #ifdef AQ_VERBOSE + printf("\n%uth port: Mailbox CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", + j, mailboxCRC, crc16Calculated); + #endif + /* Note that we can't just return here, because we still need to + * release the uPs for the other PHYs that might have been + * bootloaded successfully. */ + resultCodes[j] = AQ_RET_BOOTLOAD_CRC_MISMATCH; + } + #ifdef AQ_VERBOSE + else + { + printf("\n%uth port: Image load good - mailbox CRC-16 matches (0x%X)\n", + j, mailboxCRC); + resultCodes[j] = AQ_RET_OK; + } + #endif + } + + /*------------------------------------- Clear any resets ---------------------------------------------------------*/ + for (j = 0; j < numPorts; j++) + { + /* REGDOC: Write register (HHD/APPIA: 1E.0000) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalStandardControl_1, 0, 0x0000); + } + + /*------------------------------------- Release the uP -----------------------------------------------------------*/ + AQ_API_AssignWordOfLocalStruct(globalControl, 1, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 1); + for (j = 0; j < numPorts; j++) + { + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 0); + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + } + + /* Need to wait at least 100us. */ + AQ_API_Wait(1, ports[0]); + + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 0); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 0); + for (j = 0; j < numPorts; j++) + { + if (AQ_DEVICE_APPIA == port->device) + { + /* If the BOOT_LD pins are set to MDIO boot load mode, we can't clear the + * uP run stall override bit. If we did, the uP would stall. */ + /* REGDOC: Read bitfield (APPIA: 1E.C840.E:D) */ + AQ_API_Get_DeviceRestricted(APPIA, j, AQ_GlobalPinStatus, mdioBootLoad, bootLoadMode); + if (bootLoadMode == 0x1) + { + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + } + else + { + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 0); + } + } + else + { + /* For post-APPIA devices, always set the uP stall override bit to + * smooth over any packaging differences WRT the boot load pin. */ + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + } + + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + } + + /* NOTE!!! We can't re-enable the daisy-chain here, as this will overwrite the IRAM and DRAM with the FLASH contents*/ + + /* If any of the ports was not bootloaded successfully, return AQ_RET_ERROR */ + for (j = 0; j < numPorts; j++) + { + if (resultCodes[j] != AQ_RET_OK) + return AQ_RET_ERROR; + } + + /* All ports were bootloaded successfully. */ + return AQ_RET_OK; +} + + +AQ_Retcode AQ_API_WriteBootLoadImage +( + AQ_API_Port** ports, + unsigned int numPorts, + unsigned int* provisioningAddresses, + AQ_Retcode* resultCodes, + uint32_t* imageSizePointer, + uint8_t* image, + uint8_t gangload_MDIO_address, + AQ_API_Port* gangloadPort +) +{ + return AQ_API_WriteBootLoadImageWithProvTable(ports, numPorts, + provisioningAddresses, resultCodes, imageSizePointer, image, + gangload_MDIO_address, gangloadPort, NULL, NULL); +} + + +AQ_Retcode AQ_API_EnableDaisyChain +( + /*! The target PHY port.*/ + AQ_API_Port* port +) +{ + + /* declare local variables */ + AQ_API_Variable(AQ_GlobalNvrProvisioning) + AQ_API_Variable(AQ_GlobalReservedProvisioning) + + /* disable the hop-count override */ + /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C471.6) */ + AQ_API_Set(port->PHY_ID, AQ_GlobalReservedProvisioning, enableDaisy_chainHop_countOverride, 0); + + /* enable the daisy-chain */ + /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C452.0) */ + AQ_API_Set(port->PHY_ID, AQ_GlobalNvrProvisioning, nvrDaisyChainDisable, 0); + + return AQ_RET_OK; +} + +/*@}*/ + + +#ifdef __cplusplus +} +#endif diff --git a/firmware/aq-fw-download/src/src/AQ_PhyInterface.c b/firmware/aq-fw-download/src/src/AQ_PhyInterface.c new file mode 100755 index 0000000..6a8fce1 --- /dev/null +++ b/firmware/aq-fw-download/src/src/AQ_PhyInterface.c @@ -0,0 +1,141 @@ +/* AQ_PhyInterface.c */ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Revision: #12 $ +* +* $DateTime: 2015/02/25 15:34:49 $ +* +* $Label: $ +* +************************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "AQ_PhyInterface.h" +#include "AQ_PlatformRoutines.h" + +#define MII_ADDR_C45 (0x8000) + +extern int sock; +extern char devname[7]; + +static struct ifreq ifr; + +/*! Provides generic synchronous PHY register write functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this write operation. + * It will be assumed that the write has been completed by the time this + * function returns.*/ +void AQ_API_MDIO_Write( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being written. */ + unsigned int address, + /*! The 16-bits of data to write to the specified PHY register. */ + unsigned int data) +{ + struct mii_ioctl_data mii; + + /* + * Frame the control structures + * and send the ioctl to kernel. + */ + memset(&ifr, 0, sizeof(ifr)); + strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name)); + memset(&mii, 0, sizeof(mii)); + memcpy(&mii, &ifr.ifr_data, sizeof(mii)); + mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD; + mii.reg_num = address; + mii.val_in = data; + memcpy(&ifr.ifr_data, &mii, sizeof(mii)); + + if (ioctl(sock, SIOCSMIIREG, &ifr) < 0) { + fprintf(stderr, "SIOCSMIIREG on %s failed: %s\n", ifr.ifr_name, + strerror(errno)); + } + + return; +} + +/*! Provides generic synchronous PHY register read functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this read operation.*/ +unsigned int AQ_API_MDIO_Read +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being read. */ + unsigned int address) +{ + struct mii_ioctl_data mii; + + /* + * Frame the control structures + * and send the ioctl to kernel. + */ + memset(&ifr, 0, sizeof(ifr)); + strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name)); + memset(&mii, 0, sizeof(mii)); + memcpy(&mii, &ifr.ifr_data, sizeof(mii)); + mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD; + mii.reg_num = address; + memcpy(&ifr.ifr_data, &mii, sizeof(mii)); + + if (ioctl(sock, SIOCGMIIREG, &ifr) < 0) { + fprintf(stderr, "SIOCGMIIREG on %s failed: %s\n", ifr.ifr_name, + strerror(errno)); + return -1; + } else { + memcpy(&mii, &ifr.ifr_data, sizeof(mii)); + } + + + return mii.val_out; +} + +/*! Returns after at least milliseconds have elapsed. This must be implemented + * * in a platform-approriate way. AQ_API functions will call this function to + * * block for the specified period of time. If necessary, PHY register reads + * * may be performed on port to busy-wait. */ +void AQ_API_Wait( + uint32_t milliseconds, /*!< The delay in milliseconds */ + AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ ) +{ + unsigned long long mirco = milliseconds *1000; + usleep(mirco); +} diff --git a/firmware/nss-eip-firmware/Makefile b/firmware/nss-eip-firmware/Makefile new file mode 100644 index 0000000..3603e7e --- /dev/null +++ b/firmware/nss-eip-firmware/Makefile @@ -0,0 +1,34 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=nss-eip-firmware +PKG_VERSION=2.5.7 +PKG_RELEASE:=$(AUTORELEASE) + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/package.mk + +define Package/nss-eip-firmware + SECTION:=firmware + CATEGORY:=Firmware + TITLE:=NSS EIP-197 firmware + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_qualcommax_ipq60xx) +endef + +define Build/Compile + +endef + +define Package/nss-eip-firmware/install + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + 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CONFIG_NSS_FIRMWARE_VERSION_12_2 \ + CONFIG_NSS_FIRMWARE_VERSION_12_5 + +include $(INCLUDE_DIR)/package.mk + +RSTRIP:=: +STRIP:=: + +NSS_PROFILE:=R + +define Package/nss-firmware-common + TITLE:=NSS firmware + SECTION:=firmware + CATEGORY:=Firmware + URL:=$(PKG_SOURCE_URL) + DEPENDS:=@TARGET_qualcommax +endef + +define Package/nss-firmware +$(call Package/nss-firmware-common,$(1)) + DEPENDS+= +TARGET_qualcommax_ipq807x:nss-firmware-ipq807x \ + +TARGET_qualcommax_ipq60xx:nss-firmware-ipq60xx \ + +TARGET_qualcommax_ipq50xx:nss-firmware-ipq50xx +endef + +define Package/nss-firmware-ipq807x +$(call Package/nss-firmware-common,$(1)) + IPQ_PLATFORM=IPQ8074 + NSS_SOC:=HK +endef + +define Package/nss-firmware-ipq60xx +$(call Package/nss-firmware-common,$(1)) + IPQ_PLATFORM=IPQ6018 + CONFLICTS=nss-firmware-ipq807x + NSS_SOC:=CP +endef + +define Package/nss-firmware-ipq50xx +$(call Package/nss-firmware-common,$(1)) + IPQ_PLATFORM=IPQ5018 + CONFLICTS=nss-firmware-ipq807x nss-firmware-ipq60xx + NSS_SOC:=MP +endef + +define Package/nss-firmware/config + menu "NSS Firmware Version" + + comment "Select NSS firmware version" + + choice + prompt "Version" + default NSS_FIRMWARE_VERSION_11_4 + + config NSS_FIRMWARE_VERSION_12_5 + bool "NSS Firmware 12.5 Release 210" + help + This version does NOT work with NSS MESH (802.11s) + + config NSS_FIRMWARE_VERSION_12_2 + bool "NSS Firmware 12.2 Release 161" + help + This version does NOT work with NSS MESH (802.11s) + + config NSS_FIRMWARE_VERSION_12_1 + bool "NSS Firmware 12.1 Release 003" + help + This version does NOT work with NSS MESH (802.11s) + + config NSS_FIRMWARE_VERSION_11_4 + bool "NSS Firmware 11.4.0.5 Release 6" + help + This version WORKS with NSS MESH (802.11s) + endchoice + endmenu +endef + +define nss-firmware-version +ifneq ($(CONFIG_NSS_FIRMWARE_VERSION_11_4),) + override NSS_MAJOR=11 + override NSS_MINOR=4 + override NSS_REL=6 + override VERSION_PATH=$(PKG_BUILD_DIR)/QCA_Networking_2021.SPF_11.4/CS +else ifneq ($(CONFIG_NSS_FIRMWARE_VERSION_12_1),) + override NSS_MAJOR=12 + override NSS_MINOR=1 + override NSS_REL=003 + override VERSION_PATH=$(PKG_BUILD_DIR)/QCA_Networking_2022.SPF_12.1/ED1 +else ifneq ($(CONFIG_NSS_FIRMWARE_VERSION_12_2),) + override NSS_MAJOR=12 + override NSS_MINOR=2 + ifeq ($(1),IPQ5018) + override NSS_REL=156 + else + override NSS_REL=161 + endif + override VERSION_PATH=$(PKG_BUILD_DIR)/QCA_Networking_2022.SPF_12.2/ED1 +else + override NSS_MAJOR=12 + override NSS_MINOR=5 + override NSS_REL=210 + override VERSION_PATH=$(PKG_BUILD_DIR)/QCA_Networking_2024.SPF_12.5/ED1 +endif +endef + +define Build/Compile +endef + +define Package/nss-firmware-common/install + $(eval $(call nss-firmware-version,$(IPQ_PLATFORM))) + $(INSTALL_DIR) $(PKG_BUILD_DIR)/$(IPQ_PLATFORM) + $(TAR) --strip-components=1 -C $(PKG_BUILD_DIR)/$(IPQ_PLATFORM) -xf \ + $(VERSION_PATH)/$(IPQ_PLATFORM).ATH.$(NSS_MAJOR).$(NSS_MINOR)/BIN-NSS*.$(NSS_MAJOR).$(NSS_MINOR)*-$(NSS_REL)*$(NSS_PROFILE).tar.bz2 + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/$(IPQ_PLATFORM)/retail_router0.bin \ + $(1)/lib/firmware/qca-nss0-retail.bin +ifeq ($(NSS_SOC),HK) + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/$(IPQ_PLATFORM)/retail_router1.bin \ + $(1)/lib/firmware/qca-nss1-retail.bin +endif +endef + +define Package/nss-firmware-ipq807x/install + $(call Package/nss-firmware-common/install,$(1)) +endef + +define Package/nss-firmware-ipq60xx/install + $(call Package/nss-firmware-common/install,$(1)) +endef + +define Package/nss-firmware-ipq50xx/install + $(call Package/nss-firmware-common/install,$(1)) +endef + +define Package/nss-firmware/install + true +endef + +$(eval $(call BuildPackage,nss-firmware-ipq807x)) +$(eval $(call BuildPackage,nss-firmware-ipq60xx)) +$(eval $(call BuildPackage,nss-firmware-ipq50xx)) +$(eval $(call BuildPackage,nss-firmware)) diff --git a/nss-ifb/Makefile b/nss-ifb/Makefile new file mode 100644 index 0000000..35abb59 --- /dev/null +++ b/nss-ifb/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2008-2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=nss-ifb +PKG_RELEASE:=1 + +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/nss-ifb + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS IFB Interface + DEPENDS:=@TARGET_qualcommax +kmod-qca-nss-drv + FILES:=$(PKG_BUILD_DIR)/nss-ifb.ko + KCONFIG:= +endef + +define KernelPackage/nss-ifb/description + Kernel module to register a NSS aware IFB interface. +endef + +EXTRA_KCONFIG:= \ + CONFIG_NET_CLS=y + +EXTRA_CFLAGS:= \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv + +MAKE_OPTS:= \ + $(KERNEL_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + $(EXTRA_KCONFIG) + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" \ + $(MAKE_OPTS) \ + modules +endef + +$(eval $(call KernelPackage,nss-ifb)) diff --git a/nss-ifb/README.md b/nss-ifb/README.md new file mode 100644 index 0000000..a0af7a5 --- /dev/null +++ b/nss-ifb/README.md @@ -0,0 +1,45 @@ +NSS Physical Interface Ingress Driver +===================================== + +This driver redirect NSS physical interface (namely GMACs) ingress traffic to itself +and sends it back to the Linux network stack (as the source GMACs packets) as it's +egress traffic. + +This allows the NSS QDISC drivers to manage the egress traffic of this driver's +NSS virtual interface. + +This driver will create a single network interface named 'nssifb'. The default +source interface is defined as 'eth0'. It can be changed using the following module +parameter path: + +/sys/module/nss-ifb/parameter/nss_src_dev + +To change the source NSS physical interface to 'eth1', use the following command: + +printf eth1 > /sys/module/nss-ifb/parameter/nss_src_dev + +You need to change the source interface first before bringing up the 'nssifb' +interface. Changing it after the interface is up will have no effect. You need +to bring down the interface and bring it back up to have the changes take effect. + +CPU load imposed on the Krait CPUs appears negligible with this driver intercepting +the physical interface's ingress traffic. Full line speed of the GMAC interface +could still be achieved. + +The commands below shows an example to shape ingress traffic to 500 Mbps and egress +to 200 Mbps for the 'eth0' interface. + +# Load the module if it's not loaded +modprobe nss-ifb + +# Bring up the nssifb interface to active ingress redirect +ip link set up nssifb + +# Shape ingress traffic to 500 Mbit with chained NSSFQ_CODEL +tc qdisc add dev nssifb root handle 1: nsstbl rate 500Mbit burst 1Mb +tc qdisc add dev nssifb parent 1: handle 10: nssfq_codel limit 10240 flows 1024 quantum 1514 target 5ms interval 100ms set_default + +# Shape egress traffic to 200 Mbit with chained NSSFQ_CODEL +tc qdisc add dev eth0 root handle 1: nsstbl rate 200Mbit burst 1Mb +tc qdisc add dev eth0 parent 1: handle 10: nssfq_codel limit 10240 flows 1024 quantum 1514 target 5ms interval 100ms set_default + diff --git a/nss-ifb/src/Makefile b/nss-ifb/src/Makefile new file mode 100644 index 0000000..332b9b4 --- /dev/null +++ b/nss-ifb/src/Makefile @@ -0,0 +1,3 @@ +obj-m += nss-ifb.o + +nss-ifb-objs := nss_ifb.o diff --git a/nss-ifb/src/nss_ifb.c b/nss-ifb/src/nss_ifb.c new file mode 100644 index 0000000..18c017f --- /dev/null +++ b/nss-ifb/src/nss_ifb.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/* + * This driver is adapted from the Linux /drivers/net/ifb.c file. + * + * Redirect QCA NSS physical interface ingress traffic to this driver's + * virtual interface. This will allow ingress traffic shaping using the + * QCA NSS shaper. + */ + +#include + +#define TX_Q_LIMIT 32 + +struct nss_ifb_dev_private { + struct nss_virt_if_handle *nssctx; + struct net_device *nss_src_dev; + uint32_t nss_src_if_num; + char nss_src_dev_name[32]; +}; + +char nss_dev_name_array[32] = "eth0"; +char *nss_dev_name = nss_dev_name_array; +module_param(nss_dev_name, charp, 0644); +MODULE_PARM_DESC(nss_dev_name, "NSS physical interface source device name"); + +/* + * Virtual interface egress packet callback. + * + * We send it back to the Linux network stack. + */ +static void nss_ifb_data_cb(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi) +{ + struct nss_ifb_dev_private *dp = netdev_priv(netdev); + + skb->protocol = eth_type_trans(skb, dp->nss_src_dev); + skb->ip_summed = CHECKSUM_UNNECESSARY; + + napi_gro_receive(napi, skb); +} + +/* + * Virtual interface ingress packet callback. + * + * We just send it back to the NSS firmware to let the shaper work on it. + */ +static void nss_ifb_xmit_cb(struct net_device *netdev, struct sk_buff *skb) +{ + struct nss_ifb_dev_private *dp = netdev_priv(netdev); + int ret; + + ret = nss_virt_if_tx_buf(dp->nssctx, skb); + if (unlikely(ret)) { + pr_warn("Failed [%d] to send skb [len: %d, protocol: 0x%X] to NSS!\n", + ret, skb->len, ntohs(skb->protocol)); + } +} + +static void nss_ifb_stats64(struct net_device *dev, + struct rtnl_link_stats64 *stats) +{ + +} + +static int nss_ifb_dev_init(struct net_device *dev) +{ + struct nss_ifb_dev_private *dp = netdev_priv(dev); + + dp->nssctx = nss_virt_if_create_sync_nexthop(dev, NSS_ETH_RX_INTERFACE, NSS_ETH_RX_INTERFACE); + if (!dp->nssctx) { + dp->nssctx = NULL; + pr_warn("Could not create a NSS virtual interface for dev [%s]\n", + dev->name); + + return -ENODEV; + } + pr_info("Created a NSS virtual interface for dev [%s]\n", dev->name); + + nss_virt_if_register(dp->nssctx, nss_ifb_data_cb, dev); + pr_info("NSS IFB data callback registered\n"); + + nss_virt_if_xmit_callback_register(dp->nssctx, nss_ifb_xmit_cb); + pr_info("NSS IFB transmit callback registered\n"); + + return 0; +} + +static void nss_ifb_dev_uninit(struct net_device *dev) +{ + struct nss_ifb_dev_private *dp = netdev_priv(dev); + int ret; + + nss_virt_if_xmit_callback_unregister(dp->nssctx); + pr_info("NSS IFB transmit callback unregistered\n"); + + ret = nss_virt_if_destroy_sync(dp->nssctx); + if (ret == NSS_TX_SUCCESS) { + pr_info("NSS virtual interface destroyed for dev [%s]\n", dev->name); + } + else { + pr_warn("Unable to destroy NSS virtual interface for dev [%s], error[%d]\n", + dev->name, ret); + } + dp->nssctx = NULL; +} + +static netdev_tx_t nss_ifb_xmit(struct sk_buff *skb, struct net_device *dev) +{ + return NETDEV_TX_OK; +} + +static int nss_ifb_close(struct net_device *dev) +{ + struct nss_ifb_dev_private *dp = netdev_priv(dev); + struct nss_ctx_instance *nss_ctx; + struct net_device *src_dev; + uint32_t src_if_num; + int ret; + + nss_ctx = dp->nssctx->nss_ctx; + src_dev = dp->nss_src_dev; + src_if_num = dp->nss_src_if_num; + + ret = nss_phys_if_set_nexthop(nss_ctx, src_if_num, NSS_ETH_RX_INTERFACE); + if (ret != NSS_TX_SUCCESS) { + pr_warn("%p: Failed to reset next hop for net device [%s].\n", + nss_ctx, src_dev->name); + } + else { + pr_info("%p: Reset nexthop successful for net device [%s].\n", + nss_ctx, src_dev->name); + } + + dev_put(src_dev); + dp->nss_src_dev = NULL; + dp->nss_src_if_num = -1; + + return 0; +} + +static int nss_ifb_open(struct net_device *dev) +{ + struct nss_ifb_dev_private *dp = netdev_priv(dev); + struct net_device *src_dev; + uint32_t src_if_num; + uint32_t nh_if_num; + nss_tx_status_t nss_tx_status; + struct nss_ctx_instance *nss_ctx; + + nss_ctx = dp->nssctx->nss_ctx; + nh_if_num = dp->nssctx->if_num_n2h; + + strcpy(dp->nss_src_dev_name, nss_dev_name); + + src_dev = dev_get_by_name(&init_net, dp->nss_src_dev_name); + if (!src_dev) { + pr_warn("%p: Cannot find the net device [%s]\n", + nss_ctx, dp->nss_src_dev_name); + + return -ENODEV; + } + pr_info("%p: Found net device [%s]\n", nss_ctx, dp->nss_src_dev_name); + + src_if_num = nss_cmn_get_interface_number_by_dev(src_dev); + if (src_if_num < 0) { + pr_warn("%p: Invalid interface number:%d\n", nss_ctx, src_if_num); + dev_put(src_dev); + + return -ENODEV; + } + pr_info("%p: Net device [%s] has NSS intf_num [%d]\n", + nss_ctx, dp->nss_src_dev_name, src_if_num); + + nss_tx_status = nss_phys_if_set_nexthop(nss_ctx, src_if_num, nh_if_num); + if (nss_tx_status != NSS_TX_SUCCESS) { + pr_warn("%p: Sending message failed, cannot change nexthop for [%s]\n", + nss_ctx, dp->nss_src_dev_name); + } + else { + pr_info("Nexthop successfully set for [%s] to [%s]\n", + dp->nss_src_dev_name, dev->name); + } + + dp->nss_src_dev = src_dev; + dp->nss_src_if_num = src_if_num; + + return 0; +} + +static const struct net_device_ops nss_ifb_netdev_ops = { + .ndo_open = nss_ifb_open, + .ndo_stop = nss_ifb_close, + .ndo_get_stats64 = nss_ifb_stats64, + .ndo_start_xmit = nss_ifb_xmit, + .ndo_validate_addr = eth_validate_addr, + .ndo_init = nss_ifb_dev_init, + .ndo_uninit = nss_ifb_dev_uninit, +}; + +#define IFB_FEATURES (NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST | \ + NETIF_F_TSO_ECN | NETIF_F_TSO | NETIF_F_TSO6 | \ + NETIF_F_GSO_ENCAP_ALL | \ + NETIF_F_HIGHDMA | NETIF_F_HW_VLAN_CTAG_TX | \ + NETIF_F_HW_VLAN_STAG_TX) + +static void nss_ifb_dev_free(struct net_device *dev) +{ + +} + +static void nss_ifb_setup(struct net_device *dev) +{ + /* Initialize the device structure. */ + dev->netdev_ops = &nss_ifb_netdev_ops; + + /* Fill in device structure with ethernet-generic values. */ + ether_setup(dev); + dev->tx_queue_len = TX_Q_LIMIT; + + dev->features |= IFB_FEATURES; + dev->hw_features |= dev->features; + dev->hw_enc_features |= dev->features; + dev->vlan_features |= IFB_FEATURES & ~(NETIF_F_HW_VLAN_CTAG_TX | + NETIF_F_HW_VLAN_STAG_TX); + + dev->flags |= IFF_NOARP; + dev->flags &= ~IFF_MULTICAST; + dev->priv_flags &= ~IFF_TX_SKB_SHARING; + netif_keep_dst(dev); + eth_hw_addr_random(dev); + dev->needs_free_netdev = true; + dev->priv_destructor = nss_ifb_dev_free; + + dev->min_mtu = 0; + dev->max_mtu = 0; +} + +static int nss_ifb_validate(struct nlattr *tb[], struct nlattr *data[], + struct netlink_ext_ack *extack) +{ + if (tb[IFLA_ADDRESS]) { + if (nla_len(tb[IFLA_ADDRESS]) != ETH_ALEN) + return -EINVAL; + if (!is_valid_ether_addr(nla_data(tb[IFLA_ADDRESS]))) + return -EADDRNOTAVAIL; + } + return 0; +} + +static struct rtnl_link_ops nss_ifb_link_ops __read_mostly = { + .kind = "nss_ifb", + .priv_size = sizeof(struct nss_ifb_dev_private), + .setup = nss_ifb_setup, + .validate = nss_ifb_validate, +}; + +static int __init nss_ifb_init_module(void) +{ + struct net_device *dev; + int err; + + down_write(&pernet_ops_rwsem); + rtnl_lock(); + err = __rtnl_link_register(&nss_ifb_link_ops); + if (err < 0) + goto out; + + dev = alloc_netdev(sizeof(struct nss_ifb_dev_private), "nssifb", + NET_NAME_UNKNOWN, nss_ifb_setup); + + if (dev) { + dev->rtnl_link_ops = &nss_ifb_link_ops; + err = register_netdevice(dev); + } + else { + err = -ENOMEM; + } + + if (err) + __rtnl_link_unregister(&nss_ifb_link_ops); + +out: + rtnl_unlock(); + up_write(&pernet_ops_rwsem); + + if (!err) + pr_info("NSS IFB module loaded.\n"); + else + pr_warn("Failed to load NSS IFB module.\n"); + + return err; +} + +static void __exit nss_ifb_cleanup_module(void) +{ + rtnl_link_unregister(&nss_ifb_link_ops); + + pr_info("NSS IFB module unloaded.\n"); +} + +module_init(nss_ifb_init_module); +module_exit(nss_ifb_cleanup_module); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_RTNL_LINK("nss_ifb"); diff --git a/nss-userspace-oss/Makefile b/nss-userspace-oss/Makefile new file mode 100644 index 0000000..b61ef65 --- /dev/null +++ b/nss-userspace-oss/Makefile @@ -0,0 +1,112 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=nss-userspace-oss +PKG_RELEASE:=2 + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/nss-userspace.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2024-11-27 +PKG_SOURCE_VERSION:=7233e22 +PKG_MIRROR_HASH:=03dea072feb18916f32798f7bfd8c8811733e0681c4e9e1d77dd895f121de734 +QSDK_VERSION:=13.0 +PKG_VERSION:=$(QSDK_VERSION).$(subst -,.,$(PKG_SOURCE_DATE))~$(PKG_SOURCE_VERSION) + +PKG_BUILD_PARALLEL:=1 +PKG_FLAGS:=nonshared +PKG_BUILD_FLAGS:=gc-sections lto + +PKG_CONFIG_DEPENDS:= \ + CONFIG_NSS_NLCAPWAP_ENABLE \ + CONFIG_NSS_NLDTLS_ENABLE \ + CONFIG_NSS_NLGRE_REDIR_ENABLE \ + CONFIG_NSS_NLIPSEC_ENABLE \ + CONFIG_NSS_NLQRFS_ENABLE \ + CONFIG_NSS_NLUDP_ST_ENABLE + +include $(INCLUDE_DIR)/package.mk + +define Package/nss-userspace + TITLE:=Userspace utilities for NSS +endef + +define Package/libnl-nss +$(call Package/nss-userspace) + SECTION:=Libs + CATEGORY:=Libraries + TITLE += (libnl-nss) + DEPENDS:=+libpthread +libnl-tiny +kmod-qca-nss-drv-netlink +endef + +define Package/libnl-nss/description + A framework in the userspace that establishes communication between userspace applications and the kernel. +endef + +define Package/nssinfo +$(call Package/nss-userspace) + SECTION:=Utils + CATEGORY:=Utilities + TITLE += (nssinfo) + DEPENDS:=+libncurses +libnl-nss +endef + +define Package/nssinfo/description + A userspace utility for fetching stats from NSS. +endef + +TARGET_CFLAGS += $(FPIC) -D_GNU_SOURCE=1 + +TARGET_CPPFLAGS:= \ + -I$(STAGING_DIR)/usr/include/qca-nss-clients \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(STAGING_DIR)/usr/include/libnl-tiny \ + -I$(STAGING_DIR)/usr/include/libnl-nss + +ifneq ($(CONFIG_PACKAGE_libnl-nss),) +MAKE_FLAGS+=BUILD_LIBNSS=y + +ifdef CONFIG_NSS_NLUDP_ST_ENABLE +MAKE_FLAGS+=udp_st=y +endif + +ifdef CONFIG_NSS_NLQRFS_ENABLE +MAKE_FLAGS+=qrfs=y +endif + +ifdef CONFIG_NSS_NLGRE_REDIR_ENABLE +MAKE_FLAGS+=gre_redir=y +endif + +ifdef CONFIG_NSS_NLIPSEC_ENABLE +MAKE_FLAGS+=ipsec=y +endif + +ifdef CONFIG_NSS_NLDTLS_ENABLE +MAKE_FLAGS+=dtls=y +endif + +ifdef CONFIG_NSS_NLCAPWAP_ENABLE +MAKE_FLAGS+=capwap=y +endif +endif + +ifneq ($(CONFIG_PACKAGE_nssinfo),) +MAKE_FLAGS+=BUILD_NSSINFO=y +endif + +define Build/libnl-nss/InstallDev + $(INSTALL_DIR) $(STAGING_DIR)/usr/include/libnl-nss + $(CP) $(PKG_BUILD_DIR)/lib/include/* $(STAGING_DIR)/usr/include/libnl-nss +endef + +define Package/libnl-nss/install + $(INSTALL_DIR) $(1)/usr/lib + $(INSTALL_DATA) $(PKG_BUILD_DIR)/lib/obj/libnl-nss.so $(1)/usr/lib +endef + +define Package/nssinfo/install + $(INSTALL_DIR) $(1)/usr/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/nssinfo/obj/nssinfo $(1)/usr/sbin/ +endef + +$(eval $(call BuildPackage,nssinfo)) +$(eval $(call BuildPackage,libnl-nss)) diff --git a/nss-userspace-oss/libnl-nss/Makefile b/nss-userspace-oss/libnl-nss/Makefile new file mode 100644 index 0000000..ede067c --- /dev/null +++ b/nss-userspace-oss/libnl-nss/Makefile @@ -0,0 +1,46 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=libnl-nss +PKG_RELEASE:=1 +PKG_BUILD_DEPENDS:=libnl + +include $(INCLUDE_DIR)/package.mk + +define Package/libnl-nss + SECTION:=Libs + CATEGORY:=Libraries + TITLE:=Framework to communicate between userspace applications and the kernel. + DEPENDS:=+libpthread +libnl +@NSS_DRV_CRYPTO_ENABLE +kmod-qca-nss-drv-netlink +endef + +define Package/libnl-nss/description + A framework in the userspace that establishes communication between userspace applications and the kernel. +endef + +TOOL_CFLAGS:= -I$(STAGING_DIR)/usr/include/qca-nss-clients \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(STAGING_DIR)/usr/include/libnl3 + +TOOL_LDFLAGS:= -L$(STAGING_DIR)/lib + +define Build/Compile + $(MAKE) -C $(PKG_BUILD_DIR) \ + CC="$(TARGET_CC)" \ + AR="$(TARGET_AR) " \ + CFLAGS="$(TOOL_CFLAGS)" \ + LD_LIBRARY_PATH="$(TOOL_LDFLAGS)" +endef + +define Build/InstallDev + $(INSTALL_DIR) $(STAGING_DIR)/usr/include/libnl-nss + $(CP) $(PKG_BUILD_DIR)/obj/libnl-nss.so $(STAGING_DIR)/usr/lib + $(CP) $(PKG_BUILD_DIR)/include/* $(STAGING_DIR)/usr/include/libnl-nss +endef + +define Package/libnl-nss/install + $(INSTALL_DIR) $(1)/lib + $(INSTALL_DATA) $(PKG_BUILD_DIR)/obj/libnl-nss.so $(1)/lib +endef + +# $(eval $(call BuildPackage,libnl-nss)) diff --git a/nss-userspace-oss/libnl-nss/src/Makefile b/nss-userspace-oss/libnl-nss/src/Makefile new file mode 100644 index 0000000..ad9e3f9 --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/Makefile @@ -0,0 +1,35 @@ +MKDIR = @mkdir -p $(@D) +SRCPATH = ./ +OBJPATH = obj + +BINARY = $(OBJPATH)/libnl-nss.so +SOURCES = $(wildcard $(SRCPATH)/*.c) +OBJECTS = $(SOURCES:$(SRCPATH)/%.c=$(OBJPATH)/%.o) +HEADERS = $(wildcard $(SRCPATH)/*.h) + +INCLUDE += -I./include +LDFLAGS = -lnl-3 -lnl-genl-3 +EXTRA_CFLAGS = -Wall -Werror -fPIC -Wl,-z,relro -Wl,-z,now +EXTRA_LDFLAGS = -pie -Wl,-z,relro -Wl,-z,now + +all: release + +release: $(BINARY) + +$(OBJPATH)/%.o: $(SRCPATH)/%.c $(HEADERS) + $(MKDIR) + @echo [CC] $@ + @$(CC) -c $(CFLAGS) $(INCLUDE) $(EXTRA_CFLAGS) -o $@ $< + +$(BINARY): $(OBJECTS) + @echo $(BINARY) + @echo [LD] $@ + @$(CC) -shared -o $@ $^ $(LDFLAGS) $(LDLIBS) + +clean: + @echo [Clean] + @rm -f $(OBJECTS) + @rm -f $(BINARY) + @rm -rf $(OBJPATH) + +.PHONY: clean diff --git a/nss-userspace-oss/libnl-nss/src/include/nss_nlbase.h b/nss-userspace-oss/libnl-nss/src/include/nss_nlbase.h new file mode 100644 index 0000000..ffc2222 --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/include/nss_nlbase.h @@ -0,0 +1,71 @@ +/* + ************************************************************************** + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#ifndef __NSS_NLBASE_H__ +#define __NSS_NLBASE_H__ + +/* + * TODO: Remove inter-dependencies between the header files. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Generic Netlink header */ +#include +#include +#include + +#if !defined (likely) || !defined (unlikely) +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) +#endif + +/* NSS headers */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#endif /* __NSS_NLBASE_H__ */ diff --git a/nss-userspace-oss/libnl-nss/src/include/nss_nldtls_api.h b/nss-userspace-oss/libnl-nss/src/include/nss_nldtls_api.h new file mode 100644 index 0000000..608eea5 --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/include/nss_nldtls_api.h @@ -0,0 +1,119 @@ +/* + ************************************************************************** + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#ifndef __NSS_NLDTLS_API_H__ +#define __NSS_NLDTLS_API_H__ + +/** @addtogroup chapter_nldtls + This chapter describes Data Transport Layer Security (DTLS) APIs in the user space. + These APIs are wrapper functions for DTLS family specific operations. + */ + +/** @addtogroup nss_nldtls_datatypes @{ */ + +/** + * Response callback for DTLS. + * + * @param[in] user_ctx User context (provided at socket open). + * @param[in] rule DTLS rule. + * @param[in] resp_ctx User data per callback. + * + * @return + * None. + */ +typedef void (*nss_nldtls_resp_t)(void *user_ctx, struct nss_nldtls_rule *rule, void *resp_ctx); + +/** + * Event callback for DTLS. + * + * @param[in] user_ctx User context (provided at socket open). + * @param[in] rule DTLS rule. + * + * @return + * None. + */ +typedef void (*nss_nldtls_event_t)(void *user_ctx, struct nss_nldtls_rule *rule); + +/** + * NSS NL DTLS response. + */ +struct nss_nldtls_resp { + void *data; /**< Response context. */ + nss_nldtls_resp_t cb; /**< Response callback. */ +}; + +/** + * NSS NL DTLS context. + */ +struct nss_nldtls_ctx { + struct nss_nlsock_ctx sock; /**< NSS socket context. */ + nss_nldtls_event_t event; /**< NSS event callback function. */ +}; + +/** @} *//* end_addtogroup nss_nldtls_datatypes */ +/** @addtogroup nss_nldtls_functions @{ */ + +/** + * Opens NSS NL DTLS socket. + * + * @param[in] ctx NSS NL socket context allocated by the caller. + * @param[in] user_ctx User context stored per socket. + * @param[in] event_cb Event callback handler. + * + * @return + * Status of the open call. + */ +int nss_nldtls_sock_open(struct nss_nldtls_ctx *ctx, void *user_ctx, nss_nldtls_event_t event_cb); + +/** + * Closes NSS NL DTLS socket. + * + * @param[in] ctx NSS NL context. + * + * @return + * None. + */ +void nss_nldtls_sock_close(struct nss_nldtls_ctx *ctx); + +/** + * Send a DTLS rule synchronously to NSS NL NETLINK. + * + * @param[in] ctx NSS DTLS NL context. + * @param[in] rule DTLS rule. + * @param[in] cb Response callback handler. + * @param[in] data Data received from sender. + * + * @return + * Send status: + * - 0 -- Success. + * - Negative version error (-ve) -- Failure. + */ +int nss_nldtls_sock_send(struct nss_nldtls_ctx *ctx, struct nss_nldtls_rule *rule, nss_nldtls_resp_t cb, void *data); + +/** + * Initializes create rule message. + * + * @param[in] rule DTLS rule. + * @param[in] type Type of command. + * + * @return + * None. + */ +void nss_nldtls_init_rule(struct nss_nldtls_rule *rule, enum nss_nldtls_cmd_type type); + +/** @} *//* end_addtogroup nss_nldtls_functions */ + +#endif /* __NSS_NLDTLS_API_H__ */ diff --git a/nss-userspace-oss/libnl-nss/src/include/nss_nlipv4_api.h b/nss-userspace-oss/libnl-nss/src/include/nss_nlipv4_api.h new file mode 100644 index 0000000..edc55e9 --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/include/nss_nlipv4_api.h @@ -0,0 +1,253 @@ +/* + ************************************************************************** + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#ifndef __NSS_NLIPV4_API_H__ +#define __NSS_NLIPV4_API_H__ + +#define NSS_IPV4_RULE_CREATE_IDENTIFIER_VALID 0x1000 /**< Identifier is valid. */ + +/** @addtogroup chapter_nlipv4 + This chapter describes IPv4 APIs in the user space. + These APIs are wrapper functions for IPv4 family specific operations. +*/ + +/** @addtogroup nss_nlipv4_datatypes @{ */ + +/** + * Response callback for IPv4. + * + * @param[in] user_ctx User context (provided at socket open). + * @param[in] rule IPv4 rule. + * @param[in] resp_ctx User data per callback. + * + * @return + * None. + */ +typedef void (*nss_nlipv4_resp_t)(void *user_ctx, struct nss_nlipv4_rule *rule, void *resp_ctx); + +/** + * Event callback for IPv4. + * + * @param[in] user_ctx User context (provided at socket open). + * @param[in] rule IPv4 rule. + * + * @return + * None. + */ +typedef void (*nss_nlipv4_event_t)(void *user_ctx, struct nss_nlipv4_rule *rule); + +/** + * NSS NL IPv4 response. + */ +struct nss_nlipv4_resp { + void *data; /**< Response context. */ + nss_nlipv4_resp_t cb; /**< Response callback. */ +}; + +/** + * NSS NL IPv4 context. + */ +struct nss_nlipv4_ctx { + struct nss_nlsock_ctx sock; /**< NSS socket context. */ + nss_nlipv4_event_t event; /**< NSS event callback function. */ +}; + +/** @} *//* end_addtogroup nss_nlipv4_datatypes */ +/** @addtogroup nss_nlipv4_functions @{ */ + +/** + * Opens NSS NL IPv4 socket. + * + * @param[in] ctx NSS NL socket context allocated by the caller. + * @param[in] user_ctx User context stored per socket. + * @param[in] event_cb Event callback handler. + * + * @return + * Status of the open call. + */ +int nss_nlipv4_sock_open(struct nss_nlipv4_ctx *ctx, void *user_ctx, nss_nlipv4_event_t event_cb); + +/** + * Closes NSS NL IPv4 socket. + * + * @param[in] ctx NSS NL context. + * + * @return + * None. + */ +void nss_nlipv4_sock_close(struct nss_nlipv4_ctx *ctx); + +/** + * Sends an IPv4 rule synchronously to NSS NETLINK. + * + * @param[in] ctx NSS NL IPv4 context. + * @param[in] rule IPv4 rule. + * @param[in] cb Response callback handler. + * @param[in] data Response data per callback. + * + * @return + * Send status: + * - 0 -- Success. + * - Negative version error (-ve) -- Failure. + */ +int nss_nlipv4_sock_send(struct nss_nlipv4_ctx *ctx, struct nss_nlipv4_rule *rule, nss_nlipv4_resp_t cb, void *data); + +/** + * Initializes IPv4 rule message. + * + * @param[in] rule IPv4 rule. + * @param[in] type Command type. + * + * @return + * None. + */ +void nss_nlipv4_init_rule(struct nss_nlipv4_rule *rule, enum nss_ipv4_message_types type); + +/** + * Initializes connection rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv4_init_conn_rule(struct nss_ipv4_rule_create_msg *create) +{ + create->valid_flags |= NSS_IPV4_RULE_CREATE_CONN_VALID; +} + +/** + * Enables route flow. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv4_init_route_flow_rule(struct nss_ipv4_rule_create_msg *create) +{ + create->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_ROUTED; +} + +/** + * Enables bridge flow. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv4_init_bridge_flow_rule(struct nss_ipv4_rule_create_msg *create) +{ + create->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_BRIDGE_FLOW; +} + +/** + * Initializes TCP protocol rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv4_init_tcp_rule(struct nss_ipv4_rule_create_msg *create) +{ + create->valid_flags |= NSS_IPV4_RULE_CREATE_TCP_VALID; +} + +/** + * Initializes PPPoE rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv4_init_pppoe_rule(struct nss_ipv4_rule_create_msg *create) +{ + create->valid_flags |= NSS_IPV4_RULE_CREATE_PPPOE_VALID; +} + +/** + * Initializes QoS rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv4_init_qos_rule(struct nss_ipv4_rule_create_msg *create) +{ + create->valid_flags |= NSS_IPV4_RULE_CREATE_QOS_VALID; +} + +/** + * Initializes DSCP rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv4_init_dscp_rule(struct nss_ipv4_rule_create_msg *create) +{ + create->valid_flags |= NSS_IPV4_RULE_CREATE_DSCP_MARKING_VALID; +} + +/** + * Initializes VLAN rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv4_init_vlan_rule(struct nss_ipv4_rule_create_msg *create) +{ + struct nss_ipv4_vlan_rule *primary; + struct nss_ipv4_vlan_rule *secondary; + + primary = &create->vlan_primary_rule; + secondary = &create->vlan_secondary_rule; + + create->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID; + + /* + * set the tags to default values + */ + primary->ingress_vlan_tag = NSS_NLIPV4_VLAN_ID_NOT_CONFIGURED; + primary->egress_vlan_tag = NSS_NLIPV4_VLAN_ID_NOT_CONFIGURED; + + secondary->ingress_vlan_tag = NSS_NLIPV4_VLAN_ID_NOT_CONFIGURED; + secondary->egress_vlan_tag = NSS_NLIPV4_VLAN_ID_NOT_CONFIGURED; +} + +/** + * Initializes Identifier rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv4_init_identifier_rule(struct nss_ipv4_rule_create_msg *create) +{ + create->valid_flags |= NSS_IPV4_RULE_CREATE_IDENTIFIER_VALID; +} + +/** @} *//* end_addtogroup nss_nlipv4_functions */ + +#endif /* __NSS_NLIPV4_API_H__ */ diff --git a/nss-userspace-oss/libnl-nss/src/include/nss_nlipv6_api.h b/nss-userspace-oss/libnl-nss/src/include/nss_nlipv6_api.h new file mode 100644 index 0000000..a503421 --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/include/nss_nlipv6_api.h @@ -0,0 +1,253 @@ +/* + ************************************************************************** + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#ifndef __NSS_NLIPV6_API_H__ +#define __NSS_NLIPV6_API_H__ + +#define NSS_IPV6_RULE_CREATE_IDENTIFIER_VALID 0x1000 /**< Identifier is valid. */ + +/** @addtogroup chapter_nlipv6 + This chapter describes IPv6 APIs in the user space. + These APIs are wrapper functions for IPv6 family specific operations. +*/ + +/** @addtogroup nss_nlipv6_datatypes @{ */ + +/** + * Response callback for IPv6. + * + * @param[in] user_ctx User context (provided at socket open). + * @param[in] rule IPv6 rule. + * @param[in] resp_ctx user data per callback. + * + * @return + * None. + */ +typedef void (*nss_nlipv6_resp_t)(void *user_ctx, struct nss_nlipv6_rule *rule, void *resp_ctx); + +/** + * Event callback for IPv6. + * + * @param[in] user_ctx User context (provided at socket open). + * @param[in] rule IPv6 Rule. + * + * @return + * None. + */ +typedef void (*nss_nlipv6_event_t)(void *user_ctx, struct nss_nlipv6_rule *rule); + +/** + * NSS NL IPv6 response. + */ +struct nss_nlipv6_resp { + void *data; /**< Response context. */ + nss_nlipv6_resp_t cb; /**< Response callback. */ +}; + +/** + * NSS NL IPv6 context. + */ +struct nss_nlipv6_ctx { + struct nss_nlsock_ctx sock; /**< NSS socket context. */ + nss_nlipv6_event_t event; /**< NSS event callback function. */ +}; + +/** @} *//* end_addtogroup nss_nlipv6_datatypes */ +/** @addtogroup nss_nlipv6_functions @{ */ + +/** + * Opens NSS NL IPv6 socket. + * + * @param[in] ctx NSS NL socket context allocated by the caller. + * @param[in] user_ctx User context stored per socket. + * @param[in] event_cb Event callback handler. + * + * @return + * Status of the open call. + */ +int nss_nlipv6_sock_open(struct nss_nlipv6_ctx *ctx, void *user_ctx, nss_nlipv6_event_t event_cb); + +/** + * Closes NSS NL IPv6 socket. + * + * @param[in] ctx NSS NL context. + * + * @return + * None. + */ +void nss_nlipv6_sock_close(struct nss_nlipv6_ctx *ctx); + +/** + * Sends an IPv6 rule synchronously to NSS NETLINK. + * + * @param[in] ctx NSS IPv6 NL context. + * @param[in] rule IPv6 rule. + * @param[in] cb Response callback handler. + * @param[in] data Response data per callback. + * + * @return + * Send status: + * - 0 -- Success. + * - Negative version error (-ve) -- Failure. + */ +int nss_nlipv6_sock_send(struct nss_nlipv6_ctx *ctx, struct nss_nlipv6_rule *rule, nss_nlipv6_resp_t cb, void *data); + +/** + * Initializes rule message. + * + * @param[in] rule IPv6 rule. + * @param[in] type Command type. + * + * @return + * None. + */ +void nss_nlipv6_init_rule(struct nss_nlipv6_rule *rule, enum nss_ipv6_message_types type); + +/** + * Initializes connection rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv6_init_conn_rule(struct nss_ipv6_rule_create_msg *create) +{ + create->valid_flags |= NSS_IPV6_RULE_CREATE_CONN_VALID; +} + +/** + * Enables route flow. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv6_init_route_flow_rule(struct nss_ipv6_rule_create_msg *create) +{ + create->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_ROUTED; +} + +/** + * Enables bridge flow. + * + * @param[in] create create message. + * + * @return + * None. + */ +static inline void nss_nlipv6_init_bridge_flow_rule(struct nss_ipv6_rule_create_msg *create) +{ + create->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_BRIDGE_FLOW; +} + +/** + * Initializes TCP protocol rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv6_init_tcp_rule(struct nss_ipv6_rule_create_msg *create) +{ + create->valid_flags |= NSS_IPV6_RULE_CREATE_TCP_VALID; +} + +/** + * Initializes PPPoE rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv6_init_pppoe_rule(struct nss_ipv6_rule_create_msg *create) +{ + create->valid_flags |= NSS_IPV6_RULE_CREATE_PPPOE_VALID; +} + +/** + * Initializes QoS rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv6_init_qos_rule(struct nss_ipv6_rule_create_msg *create) +{ + create->valid_flags |= NSS_IPV6_RULE_CREATE_QOS_VALID; +} + +/** + * Initializes DSCP rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv6_init_dscp_rule(struct nss_ipv6_rule_create_msg *create) +{ + create->valid_flags |= NSS_IPV6_RULE_CREATE_DSCP_MARKING_VALID; +} + +/** + * Initializes VLAN rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv6_init_vlan_rule(struct nss_ipv6_rule_create_msg *create) +{ + struct nss_ipv6_vlan_rule *primary; + struct nss_ipv6_vlan_rule *secondary; + + primary = &create->vlan_primary_rule; + secondary = &create->vlan_secondary_rule; + + create->valid_flags |= NSS_IPV6_RULE_CREATE_VLAN_VALID; + + /* + * set the tags to default values + */ + primary->ingress_vlan_tag = NSS_NLIPV6_VLAN_ID_NOT_CONFIGURED; + primary->egress_vlan_tag = NSS_NLIPV6_VLAN_ID_NOT_CONFIGURED; + + secondary->ingress_vlan_tag = NSS_NLIPV6_VLAN_ID_NOT_CONFIGURED; + secondary->egress_vlan_tag = NSS_NLIPV6_VLAN_ID_NOT_CONFIGURED; +} + +/** + * Initializes Identifier rule for create message. + * + * @param[in] create Creates message. + * + * @return + * None. + */ +static inline void nss_nlipv6_init_identifier_rule(struct nss_ipv6_rule_create_msg *create) +{ + create->valid_flags |= NSS_IPV6_RULE_CREATE_IDENTIFIER_VALID; +} + +/** @} *//* end_addtogroup nss_nlipv6_functions */ + +#endif /* __NSS_NLIPV6_API_H__ */ diff --git a/nss-userspace-oss/libnl-nss/src/include/nss_nlist_api.h b/nss-userspace-oss/libnl-nss/src/include/nss_nlist_api.h new file mode 100644 index 0000000..6b8bb05 --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/include/nss_nlist_api.h @@ -0,0 +1,220 @@ +/* + ************************************************************************** + * Copyright (c) 2019,2021 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#ifndef __NSS_NLIST_H__ +#define __NSS_NLIST_H__ + +/** @addtogroup chapter_nlist + This chapter describes Netlink list APIs in the user space. +*/ + +/** @ingroup nss_nlist_datatypes + * List node + */ +struct nss_nlist { + struct nss_nlist *next; /**< Next node. */ + struct nss_nlist *prev; /**< Previous node. */ +}; + +/** @addtogroup nss_nlist_functions @{ */ + +/** + * Initializes the list node. + * + * @param[in] node List node. + * + * @return + * None. + */ +static inline void nss_nlist_init(struct nss_nlist *node) +{ + node->next = node->prev = node; +} + +/** + * Gets the previous node. + * + * @param[in] node Previous node. + * + * @return + * Previous node or head node. + */ +static inline struct nss_nlist *nss_nlist_prev(struct nss_nlist *node) +{ + return node->prev; +} + +/** + * Gets the next node. + * + * @param[in] node Next node. + * + * @return + * Next node or head node. + */ +static inline struct nss_nlist *nss_nlist_next(struct nss_nlist *node) +{ + return node->next; +} + +/** + * Initializes the head node. + * + * @param[in] head Head of list. + * + * @return + * None. + */ +static inline void nss_nlist_init_head(struct nss_nlist *head) +{ + nss_nlist_init(head); +} + +/** + * Returns first node in the list. + * + * @param[in] head List head. + * + * @return + * First node. + */ +static inline struct nss_nlist *nss_nlist_first(struct nss_nlist *head) +{ + return nss_nlist_next(head); +} + +/** + * Returns last node in the list. + * + * @param[in] head List head. + * + * @return + * Last node. + */ +static inline struct nss_nlist *nss_nlist_last(struct nss_nlist *head) +{ + return nss_nlist_prev(head); +} + +/** + * Checks if list is empty. + * + * @param[in] head List head. + * + * @return + * TRUE if empty. + */ +static inline bool nss_nlist_isempty(struct nss_nlist *head) +{ + struct nss_nlist *first = nss_nlist_first(head); + + return first == head; +} + +/** + * Checks if corresponding node is the last node. + * + * @param[in] head Head node. + * @param[in] node Node to check. + * + * @return + * TRUE if it is the last node. + */ +static inline bool nss_nlist_islast(struct nss_nlist *head, struct nss_nlist *node) +{ + struct nss_nlist *last = nss_nlist_last(head); + + return last == node; +} + +/** + * Adds node to head of the list. + * + * @param[in] head List head. + * @param[in] node Node to add. + * + * @return + * None. + */ +static inline void nss_nlist_add_head(struct nss_nlist *head, struct nss_nlist *node) +{ + struct nss_nlist *first = nss_nlist_first(head); + + node->prev = head; + node->next = first; + + first->prev = node; + head->next = node; + +} + +/** + * Adds node to tail of the list. + * + * @param[in] head List head. + * @param[in] node Node to add. + * + * @return + * None. + */ +static inline void nss_nlist_add_tail(struct nss_nlist *head, struct nss_nlist *node) +{ + struct nss_nlist *last = nss_nlist_last(head); + + node->next = head; + node->prev = last; + + last->next = node; + head->prev = node; +} + +/** + * Unlinks node from the list. + * + * @param[in] node Node to unlink. + * + * @return + * None. + */ +static inline void nss_nlist_unlink(struct nss_nlist *node) +{ + struct nss_nlist *prev = nss_nlist_prev(node); + struct nss_nlist *next = nss_nlist_next(node); + + prev->next = next; + next->prev = prev; + + nss_nlist_init(node); +} + +/** @} *//* end_addtogroup nss_nlist_functions */ + +/** @ingroup nss_nlist_macros + * Lists node iterator. + * + * @hideinitializer + * @param[in] _tmp Temporary node for assignment. + * @param[in] _head Head node to start. + * + * @return + * None. + */ +#define nss_nlist_iterate(_tmp, _head) \ + for ((_tmp) = nss_nlist_first((_head)); \ + !nss_nlist_islast((_head), (_tmp)); \ + (_tmp) = nss_nlist_next((_tmp)) + +#endif /* __NSS_NLIST_H__ */ diff --git a/nss-userspace-oss/libnl-nss/src/include/nss_nlmcast_api.h b/nss-userspace-oss/libnl-nss/src/include/nss_nlmcast_api.h new file mode 100644 index 0000000..8fcf5d8 --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/include/nss_nlmcast_api.h @@ -0,0 +1,102 @@ +/* + ************************************************************************** + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#ifndef __NSS_NLMCAST_API_H__ +#define __NSS_NLMCAST_API_H__ + +/** @addtogroup chapter_nlmcast + This chapter describes multicast APIs in the user space. + These APIs are wrapper functions for multicast specific operations. +*/ + +/** @addtogroup nss_nlmcast_datatypes @{ */ + +/** + * Event callback for multicast. + * + * @param[in] cmd Command received in generic Netlink header. + * @param[in] data Data received in Netlink message. + */ +typedef void (*nss_nlmcast_event_t)(int cmd, void *data); + +/** + * NSS multicast context. + */ +struct nss_nlmcast_ctx { + struct nss_nlsock_ctx sock; /**< NSS socket context. */ + nss_nlmcast_event_t event; /**< NSS event callback function. */ +}; + +/** @} *//* end_addtogroup nss_nlmcast_datatypes */ +/** @addtogroup nss_nlmcast_functions @{ */ + +/** + * Listens to NSS NL multicast event data. + * + * @param[in] ctx Multicast context. + * + * @return + * Listen status. + */ +int nss_nlmcast_sock_listen(struct nss_nlmcast_ctx *ctx); + +/** + * Subscribe the multicast group to receive responses. + * + * @param[in] ctx Multicast context. + * @param[in] grp_name NSS NL group name. + * + * @return + * Subscription status. + */ +int nss_nlmcast_sock_join_grp(struct nss_nlmcast_ctx *ctx, char *grp_name); + +/** + * Unsubscribe the multicast group to stop receiving responses. + * + * @param[in] ctx Multicast context. + * @param[in] grp_name NSS NL group name. + * + * @return + * Status of the operation. + */ +int nss_nlmcast_sock_leave_grp(struct nss_nlmcast_ctx *ctx, char *grp_name); + +/** + * Opens a socket for listening to NSS NL event data. + * + * @param[in] ctx Multicast context. + * @param[in] cb Callback function. + * @param[in] family_name NSS NL family name. + * + * @return + * Status of the operation. + */ +int nss_nlmcast_sock_open(struct nss_nlmcast_ctx *ctx, nss_nlmcast_event_t cb, const char *family_name); + +/** + * Closes socket. + * + * @param[in] ctx Multicast context. + * + * @return + * None. + */ +void nss_nlmcast_sock_close(struct nss_nlmcast_ctx *ctx); + +/** @} *//* end_addtogroup nss_nlmcast_functions */ + +#endif /* __NSS_NLMCAST_API_H__ */ diff --git a/nss-userspace-oss/libnl-nss/src/include/nss_nlsock_api.h b/nss-userspace-oss/libnl-nss/src/include/nss_nlsock_api.h new file mode 100644 index 0000000..7a42071 --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/include/nss_nlsock_api.h @@ -0,0 +1,197 @@ +/* + ************************************************************************** + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#ifndef __NSS_NLSOCK_API_H__ +#define __NSS_NLSOCK_API_H__ + +/** @addtogroup chapter_nlsocket + This chapter describes socket APIs for direct use. + + @note1hang + Use these APIs(s) only if there are no available helpers for the specific family. +*/ + +/** + * @ingroup nss_nlsocket_datatypes + * NSS NL socket context. + */ +struct nss_nlsock_ctx { + /* Public, caller must populate using helpers */ + const char *family_name; /**< Family name. */ + void *user_ctx; /**< Socket user context. */ + + /* Private, maintained by the library */ + pthread_t thread; /**< Response sync. */ + pthread_spinlock_t lock; /**< Context lock. */ + int ref_cnt; /**< References to the socket. */ + + struct nl_sock *nl_sk; /**< Linux NL socket. */ + struct nl_cb *nl_cb; /**< NSS NL callback context. */ + + pid_t pid; /**< Process ID associated with the socket. */ + int family_id; /**< Family identifier. */ + int grp_id; /**< Group indentifier. */ + bool is_avail; /**< Indicates if the socket is available to send or listen. */ +}; + +/** @addtogroup nss_nlsocket_macros @{ */ + +/** + * Prints error log. + * + * @param[in] arg Argument to be printed + */ +#define nss_nlsock_log_error(arg, ...) printf("NSS_NLERROR(%s[%d]):"arg, __func__, __LINE__, ##__VA_ARGS__) + +/** + * Prints arguments + * + * @param[in] arg Argument to be printed + */ +#define nss_nlsock_log_info(arg, ...) printf("NSS_NLINFO(%s[%d]):"arg, __func__, __LINE__, ##__VA_ARGS__) + +/** @} *//* end_addtogroup nss_nlsocket_macros */ + +/** @addtogroup nss_nlsocket_functions @{ */ + +/** + * Sets family name. + * + * @param[in] sock Socket context. + * @param[in] name Family name. + * + * @return + * None. + */ +static inline void nss_nlsock_set_family(struct nss_nlsock_ctx *sock, const char *name) +{ + sock->family_name = name; +} + +/** + * Sets user context. + * + * @param[in] sock Socket context. + * @param[in] user User context. + * + * @return + * None. + */ +static inline void nss_nlsock_set_user_ctx(struct nss_nlsock_ctx *sock, void *user) +{ + sock->user_ctx = user; +} + +/** + * Extracts NSS NL message data. + * + * @param[in] msg NL message. + * + * @return + * Pointer to start of NSS NL message. + */ +static inline void *nss_nlsock_get_data(struct nl_msg *msg) +{ + struct genlmsghdr *genl_hdr = nlmsg_data((nlmsg_hdr(msg))); + + return genlmsg_data(genl_hdr); +} + +/** + * Opens NSS NL family socket. + * + * @param[in] sock Socket context to be allocated by the caller. + * @param[in] cb Callback function for response. + * + * @return + * Status of the operation. + * + * @note The underlying entity should set the sock->family name for the socket to open. + */ +int nss_nlsock_open(struct nss_nlsock_ctx *sock, nl_recvmsg_msg_cb_t cb); + +/** + * Closes NSS NL family socket. + * + * @param[in] sock Socket context. + * + * @return + * None. + */ +void nss_nlsock_close(struct nss_nlsock_ctx *sock); + +/** + * Sends NSS NL message synchronously. + * + * @param[in] sock Socket context. + * @param[in] cm Common message header. + * @param[in] data Message data. + * @param[in] has_resp Determines if response is needed from kernel. + * + * @detdesc The function blocks until ack/error is received from the kernel + * and also blocks for the message response from the kernel if is_resp is TRUE + + * @return + * Status of the send operation. + */ +int nss_nlsock_send(struct nss_nlsock_ctx *sock, struct nss_nlcmn *cm, void *data, bool has_resp); + +/** + * Listens to asynchronous events from kernel. + * + * @param[in] sock Socket context. + * + * @return + * Listen status. + */ +int nss_nlsock_listen(struct nss_nlsock_ctx *sock); + +/** + * Subscribes to multicast group. + * + * @param[in] sock Socket context. + * @param[in] grp_name NSS NL group name. + * + * @return + * Subscription status. + */ +int nss_nlsock_join_grp(struct nss_nlsock_ctx *sock, char *grp_name); + +/** + * Unsubscribes from multicast group. + * + * @param[in] sock Socket context. + * @param[in] grp_name NSS NL group name. + * + * @return + * Status of the operation. + */ +int nss_nlsock_leave_grp(struct nss_nlsock_ctx *sock, char *grp_name); + +/** + * Opens a socket for listening to NSS NL event data. + * + * @param[in] sock Socket context. + * @param[in] cb Callback function. + * + * @return + * Status of the operation. + */ +int nss_nlsock_open_mcast(struct nss_nlsock_ctx *sock, nl_recvmsg_msg_cb_t cb); + +/** @} *//* end_addtogroup nss_nlsocket_functions */ + +#endif /* __NSS_NLSOCK_API_H__ */ diff --git a/nss-userspace-oss/libnl-nss/src/nss_nldtls_api.c b/nss-userspace-oss/libnl-nss/src/nss_nldtls_api.c new file mode 100644 index 0000000..4ad42ef --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/nss_nldtls_api.c @@ -0,0 +1,138 @@ +/* + ************************************************************************** + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#include +#include +#include + +/* + * nss_nldtls_sock_cb() + * Callback func for dtls netlink socket + */ +int nss_nldtls_sock_cb(struct nl_msg *msg, void *arg) +{ + pid_t pid = getpid(); + + struct nss_nldtls_rule *rule = nss_nlsock_get_data(msg); + + if (!rule) { + nss_nlsock_log_error("%d:failed to get NSS NL dtls header\n", pid); + return NL_SKIP; + } + + uint8_t cmd = nss_nlcmn_get_cmd(&rule->cm); + + switch (cmd) { + case NSS_NLDTLS_CMD_TYPE_CREATE_TUN: + case NSS_NLDTLS_CMD_TYPE_DESTROY_TUN: + case NSS_NLDTLS_CMD_TYPE_UPDATE_CONFIG: + case NSS_NLDTLS_CMD_TYPE_TX_PKTS: + return NL_OK; + + default: + nss_nlsock_log_error("%d:unsupported message cmd type(%d)\n", pid, cmd); + return NL_SKIP; + } +} + +/* + * nss_nldtls_sock_open() + * Opens the NSS dtls NL socket for usage + */ +int nss_nldtls_sock_open(struct nss_nldtls_ctx *ctx, void *user_ctx, nss_nldtls_event_t event_cb) +{ + pid_t pid = getpid(); + int error; + + if (!ctx) { + nss_nlsock_log_error("%d: invalid parameters passed\n", pid); + return -EINVAL; + } + + memset(ctx, 0, sizeof(*ctx)); + + nss_nlsock_set_family(&ctx->sock, NSS_NLDTLS_FAMILY); + nss_nlsock_set_user_ctx(&ctx->sock, user_ctx); + + /* + * try opening the socket with Linux + */ + error = nss_nlsock_open(&ctx->sock, nss_nldtls_sock_cb); + if (error) { + nss_nlsock_log_error("%d:unable to open NSS dtls socket, error(%d)\n", pid, error); + goto fail; + } + + return 0; +fail: + memset(ctx, 0, sizeof(*ctx)); + return error; +} + +/* + * nss_nldtls_sock_close() + * Close the NSS dtls NL socket + */ +void nss_nldtls_sock_close(struct nss_nldtls_ctx *ctx) +{ + nss_nlsock_close(&ctx->sock); + memset(ctx, 0, sizeof(struct nss_nldtls_ctx)); +} + +/* + * nss_nldtls_sock_send() + * Send the dtls message synchronously through the socket + */ +int nss_nldtls_sock_send(struct nss_nldtls_ctx *ctx, struct nss_nldtls_rule *rule, nss_nldtls_resp_t cb, void *data) +{ + int32_t family_id = ctx->sock.family_id; + struct nss_nldtls_resp *resp; + pid_t pid = getpid(); + bool has_resp = false; + int error = 0; + + if (!rule) { + nss_nlsock_log_error("%d:invalid NSS dtls rule\n", pid); + return -EINVAL; + } + + if (cb) { + nss_nlcmn_set_cb_owner(&rule->cm, family_id); + + resp = nss_nlcmn_get_cb_data(&rule->cm, family_id); + assert(resp); + + resp->data = data; + resp->cb = cb; + has_resp = true; + } + + error = nss_nlsock_send(&ctx->sock, &rule->cm, rule, has_resp); + if (error) { + nss_nlsock_log_error("%d:failed to send NSS dtls rule, error(%d)\n", pid, error); + } + + return error; +} + +/* + * nss_nldtls_init_rule() + * Initialize the dtls rule + */ +void nss_nldtls_init_rule(struct nss_nldtls_rule *rule, enum nss_nldtls_cmd_type type) +{ + nss_nldtls_rule_init(rule, type); +} diff --git a/nss-userspace-oss/libnl-nss/src/nss_nlipv4_api.c b/nss-userspace-oss/libnl-nss/src/nss_nlipv4_api.c new file mode 100644 index 0000000..0088d72 --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/nss_nlipv4_api.c @@ -0,0 +1,176 @@ +/* + ************************************************************************** + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#include +#include +#include + +/* + * nss_nlipv4_sock_cb() + * NSS NL IPv4 callback + */ +int nss_nlipv4_sock_cb(struct nl_msg *msg, void *arg) +{ + pid_t pid = getpid(); + + struct nss_nlipv4_ctx *ctx = (struct nss_nlipv4_ctx *)arg; + struct nss_nlsock_ctx *sock = &ctx->sock; + + struct nss_nlipv4_rule *rule = nss_nlsock_get_data(msg); + if (!rule) { + nss_nlsock_log_error("%d:failed to get NSS NL IPv4 header\n", pid); + return NL_SKIP; + } + + uint8_t cmd = nss_nlcmn_get_cmd(&rule->cm); + + switch (cmd) { + case NSS_IPV4_TX_CREATE_RULE_MSG: + case NSS_IPV4_TX_DESTROY_RULE_MSG: + { + void *cb_data = nss_nlcmn_get_cb_data(&rule->cm, sock->family_id); + if (!cb_data) { + return NL_SKIP; + } + + /* + * Note: The callback user can modify the CB content so it + * needs to locally save the response data for further use + * after the callback is completed + */ + struct nss_nlipv4_resp resp; + memcpy(&resp, cb_data, sizeof(struct nss_nlipv4_resp)); + + /* + * clear the ownership of the CB so that callback user can + * use it if needed + */ + nss_nlcmn_clr_cb_owner(&rule->cm); + + if (!resp.cb) { + nss_nlsock_log_info("%d:no IPv4 response callback for cmd(%d)\n", pid, cmd); + return NL_SKIP; + } + + resp.cb(sock->user_ctx, rule, resp.data); + + return NL_OK; + } + + case NSS_IPV4_RX_CONN_STATS_SYNC_MSG: + { + nss_nlipv4_event_t event = ctx->event; + + assert(event); + event(sock->user_ctx, rule); + + return NL_OK; + } + + default: + nss_nlsock_log_error("%d:unsupported message cmd type(%d)\n", pid, cmd); + return NL_SKIP; + } +} + +/* + * nss_nlipv4_sock_open() + * this opens the NSS IPv4 NL socket for usage + */ +int nss_nlipv4_sock_open(struct nss_nlipv4_ctx *ctx, void *user_ctx, nss_nlipv4_event_t event_cb) +{ + pid_t pid = getpid(); + int error; + + if (!ctx) { + nss_nlsock_log_error("%d: invalid parameters passed\n", pid); + return -EINVAL; + } + + memset(ctx, 0, sizeof(*ctx)); + + nss_nlsock_set_family(&ctx->sock, NSS_NLIPV4_FAMILY); + nss_nlsock_set_user_ctx(&ctx->sock, user_ctx); + + /* + * try opening the socket with Linux + */ + error = nss_nlsock_open(&ctx->sock, nss_nlipv4_sock_cb); + if (error) { + nss_nlsock_log_error("%d:unable to open NSS IPv4 socket, error(%d)\n", pid, error); + goto fail; + } + + return 0; +fail: + memset(ctx, 0, sizeof(*ctx)); + return error; +} + +/* + * nss_nlipv4_sock_close() + * close the NSS IPv4 NL socket + */ +void nss_nlipv4_sock_close(struct nss_nlipv4_ctx *ctx) +{ + nss_nlsock_close(&ctx->sock); +} + +/* + * nss_nlipv4_sock_send() + * register callback and send the IPv4 message synchronously through the socket + */ +int nss_nlipv4_sock_send(struct nss_nlipv4_ctx *ctx, struct nss_nlipv4_rule *rule, nss_nlipv4_resp_t cb, void *data) +{ + int32_t family_id = ctx->sock.family_id; + struct nss_nlipv4_resp *resp; + pid_t pid = getpid(); + bool has_resp = false; + int error; + + if (!rule) { + nss_nlsock_log_error("%d:invalid NSS IPv4 rule\n", pid); + return -ENOMEM; + } + + if (cb) { + nss_nlcmn_set_cb_owner(&rule->cm, family_id); + + resp = nss_nlcmn_get_cb_data(&rule->cm, family_id); + assert(resp); + + resp->data = data; + resp->cb = cb; + has_resp = true; + } + + error = nss_nlsock_send(&ctx->sock, &rule->cm, rule, has_resp); + if (error) { + nss_nlsock_log_error("%d:failed to send NSS IPv4 rule, error(%d)\n", pid, error); + return error; + } + + return 0; +} + +/* + * nss_nlipv4_init_rule() + * init the rule message + */ +void nss_nlipv4_init_rule(struct nss_nlipv4_rule *rule, enum nss_ipv4_message_types type) +{ + nss_nlipv4_rule_init(rule, type); +} diff --git a/nss-userspace-oss/libnl-nss/src/nss_nlipv6_api.c b/nss-userspace-oss/libnl-nss/src/nss_nlipv6_api.c new file mode 100644 index 0000000..fa0bbf2 --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/nss_nlipv6_api.c @@ -0,0 +1,176 @@ +/* + ************************************************************************** + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#include +#include +#include + +/* + * nss_nlipv6_sock_cb() + * NSS NL IPv6 callback + */ +int nss_nlipv6_sock_cb(struct nl_msg *msg, void *arg) +{ + pid_t pid = getpid(); + + struct nss_nlipv6_ctx *ctx = (struct nss_nlipv6_ctx *)arg; + struct nss_nlsock_ctx *sock = &ctx->sock; + + struct nss_nlipv6_rule *rule = nss_nlsock_get_data(msg); + if (!rule) { + nss_nlsock_log_error("%d:failed to get NSS NL IPv6 header\n", pid); + return NL_SKIP; + } + + uint8_t cmd = nss_nlcmn_get_cmd(&rule->cm); + + switch (cmd) { + case NSS_IPV6_TX_CREATE_RULE_MSG: + case NSS_IPV6_TX_DESTROY_RULE_MSG: + { + void *cb_data = nss_nlcmn_get_cb_data(&rule->cm, sock->family_id); + if (!cb_data) { + return NL_SKIP; + } + + /* + * Note: The callback user can modify the CB content so it + * needs to locally save the response data for further use + * after the callback is completed + */ + struct nss_nlipv6_resp resp; + memcpy(&resp, cb_data, sizeof(struct nss_nlipv6_resp)); + + /* + * clear the ownership of the CB so that callback user can + * use it if needed + */ + nss_nlcmn_clr_cb_owner(&rule->cm); + + if (!resp.cb) { + nss_nlsock_log_info("%d:no IPv6 response callback for cmd(%d)\n", pid, cmd); + return NL_SKIP; + } + + resp.cb(sock->user_ctx, rule, resp.data); + + return NL_OK; + } + + case NSS_IPV6_RX_CONN_STATS_SYNC_MSG: + { + nss_nlipv6_event_t event = ctx->event; + + assert(event); + event(sock->user_ctx, rule); + + return NL_OK; + } + + default: + nss_nlsock_log_error("%d:unsupported message cmd type(%d)\n", pid, cmd); + return NL_SKIP; + } +} + +/* + * nss_nlipv6_sock_open() + * this opens the NSS IPv6 NL socket for usage + */ +int nss_nlipv6_sock_open(struct nss_nlipv6_ctx *ctx, void *user_ctx, nss_nlipv6_event_t event_cb) +{ + pid_t pid = getpid(); + int error; + + if (!ctx) { + nss_nlsock_log_error("%d: invalid parameters passed\n", pid); + return -EINVAL; + } + + memset(ctx, 0, sizeof(*ctx)); + + nss_nlsock_set_family(&ctx->sock, NSS_NLIPV6_FAMILY); + nss_nlsock_set_user_ctx(&ctx->sock, user_ctx); + + /* + * try opening the socket with Linux + */ + error = nss_nlsock_open(&ctx->sock, nss_nlipv6_sock_cb); + if (error) { + nss_nlsock_log_error("%d:unable to open NSS IPv6 socket, error(%d)\n", pid, error); + goto fail; + } + + return 0; +fail: + memset(ctx, 0, sizeof(*ctx)); + return error; +} + +/* + * nss_nlipv6_sock_close() + * close the NSS IPv6 NL socket + */ +void nss_nlipv6_sock_close(struct nss_nlipv6_ctx *ctx) +{ + nss_nlsock_close(&ctx->sock); +} + +/* + * nss_nlipv6_sock_send() + * register callback and send the IPv6 message synchronously through the socket + */ +int nss_nlipv6_sock_send(struct nss_nlipv6_ctx *ctx, struct nss_nlipv6_rule *rule, nss_nlipv6_resp_t cb, void *data) +{ + int32_t family_id = ctx->sock.family_id; + struct nss_nlipv6_resp *resp; + pid_t pid = getpid(); + bool has_resp = false; + int error; + + if (!rule) { + nss_nlsock_log_error("%d:invalid NSS IPv6 rule\n", pid); + return -ENOMEM; + } + + if (cb) { + nss_nlcmn_set_cb_owner(&rule->cm, family_id); + + resp = nss_nlcmn_get_cb_data(&rule->cm, family_id); + assert(resp); + + resp->data = data; + resp->cb = cb; + has_resp = true; + } + + error = nss_nlsock_send(&ctx->sock, &rule->cm, rule, has_resp); + if (error) { + nss_nlsock_log_error("%d:failed to send NSS IPv6 rule, error(%d)\n", pid, error); + return error; + } + + return 0; +} + +/* + * nss_nlipv6_init_rule() + * init the rule message + */ +void nss_nlipv6_init_rule(struct nss_nlipv6_rule *rule, enum nss_ipv6_message_types type) +{ + nss_nlipv6_rule_init(rule, type); +} diff --git a/nss-userspace-oss/libnl-nss/src/nss_nlmcast_api.c b/nss-userspace-oss/libnl-nss/src/nss_nlmcast_api.c new file mode 100644 index 0000000..7646440 --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/nss_nlmcast_api.c @@ -0,0 +1,146 @@ +/* + ************************************************************************** + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#include +#include +#include + +/* + * nss_nlmcast_sock_cb() + * NSS NL mcast callback. + */ +static int nss_nlmcast_sock_cb(struct nl_msg *msg, void *arg) +{ + struct nss_nlmcast_ctx *ctx = (struct nss_nlmcast_ctx *)arg; + struct genlmsghdr *genl_hdr = nlmsg_data((nlmsg_hdr(msg))); + uint8_t cmd = genl_hdr->cmd; + + void *data = nss_nlsock_get_data(msg); + if (!data) { + nss_nlsock_log_error("%d:failed to get NSS NL msg header\n", getpid()); + return NL_SKIP; + } + + nss_nlmcast_event_t event = ctx->event; + assert(event); + event(cmd, data); + return NL_OK; +} + +/* + * nss_nlmcast_sock_open() + * Open the NL socket for listening to MCAST events from kernel. + */ +int nss_nlmcast_sock_open(struct nss_nlmcast_ctx *ctx, nss_nlmcast_event_t event_cb, const char *family_name) +{ + int error; + + if (!ctx || !event_cb) { + nss_nlsock_log_error("Invalid parameters passed\n"); + return -EINVAL; + } + + memset(ctx, 0, sizeof(*ctx)); + + nss_nlsock_set_family(&ctx->sock, family_name); + + /* + * Subscribe to the NSS NL Multicast group. + */ + error = nss_nlsock_open_mcast(&ctx->sock, nss_nlmcast_sock_cb); + if (error) { + nss_nlsock_log_error("Unable to create socket, error(%d)\n", error); + return error; + } + + ctx->event = event_cb; + return 0; +} + +/* + * nss_nlmcast_sock_close() + * Close the NL socket. + */ +void nss_nlmcast_sock_close(struct nss_nlmcast_ctx *ctx) +{ + nss_nlsock_close(&ctx->sock); +} + +/* + * nss_nlmcast_sock_join_grp() + * Subscribe for MCAST group from kernel. + */ +int nss_nlmcast_sock_join_grp(struct nss_nlmcast_ctx *ctx, char *grp_name) +{ + int error; + + if (!ctx || !grp_name) { + nss_nlsock_log_error("Invalid parameters passed\n"); + return -EINVAL; + } + + error = nss_nlsock_join_grp(&ctx->sock, grp_name); + if (error) { + nss_nlsock_log_error("Unable to subscribe for mcast group, error(%d)\n", error); + return error; + } + + return 0; +} + +/* + * nss_nlmcast_sock_leave_grp() + * Unsubscribe for MCAST group from kernel. + */ +int nss_nlmcast_sock_leave_grp(struct nss_nlmcast_ctx *ctx, char *grp_name) +{ + int error; + + if (!ctx || !grp_name) { + nss_nlsock_log_error("Invalid parameters passed\n"); + return -EINVAL; + } + + error = nss_nlsock_leave_grp(&ctx->sock, grp_name); + if (error) { + nss_nlsock_log_error("Unable to unsubscribe for mcast group, error(%d)\n", error); + return error; + } + + return 0; +} + +/* + * nss_nlmcast_sock_listen() + * Listen for MCAST events from kernel + */ +int nss_nlmcast_sock_listen(struct nss_nlmcast_ctx *ctx) +{ + int error; + + if (!ctx) { + nss_nlsock_log_error("Invalid parameters passed\n"); + return -EINVAL; + } + + error = nss_nlsock_listen(&ctx->sock); + if (error) { + nss_nlsock_log_error("Unable to listen to mcast events, error(%d)\n", error); + return error; + } + + return 0; +} diff --git a/nss-userspace-oss/libnl-nss/src/nss_nlsock.c b/nss-userspace-oss/libnl-nss/src/nss_nlsock.c new file mode 100644 index 0000000..451982f --- /dev/null +++ b/nss-userspace-oss/libnl-nss/src/nss_nlsock.c @@ -0,0 +1,498 @@ +/* + ************************************************************************** + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +/* + * @file netlink socket handler + */ + +#include +#include + +/* + * nss_nlsock_deinit() + * de-initialize the socket + */ +static void nss_nlsock_deinit(struct nss_nlsock_ctx *sock) +{ + assert(sock); + + nl_cb_put(sock->nl_cb); + sock->nl_cb = NULL; + + nl_socket_free(sock->nl_sk); + sock->nl_sk = NULL; +} + +/* + * nss_nlsock_init() + * initialize the socket and callback + */ +static int nss_nlsock_init(struct nss_nlsock_ctx *sock, nl_recvmsg_msg_cb_t cb) +{ + int error; + + assert(sock); + + /* + * Initialize spinlock + */ + error = pthread_spin_init(&sock->lock, PTHREAD_PROCESS_PRIVATE); + if (error) { + nss_nlsock_log_error("Failed to init spinlock for family(%s), error %d\n", sock->family_name, error); + return error; + } + + sock->pid = getpid(); + + /* + * create callback + */ + sock->nl_cb = nl_cb_alloc(NL_CB_CUSTOM); + if (!sock->nl_cb) { + nss_nlsock_log_error("%d:failed to alloc callback for family(%s)\n",sock->pid, sock->family_name); + goto fail1; + } + + /* + * register callback + */ + nl_cb_set(sock->nl_cb, NL_CB_VALID, NL_CB_CUSTOM, cb, sock); + + /* + * Create netlink socket + */ + sock->nl_sk = nl_socket_alloc_cb(sock->nl_cb); + if (!sock->nl_sk) { + nss_nlsock_log_error("%d:failed to alloc socket for family(%s)\n", sock->pid, sock->family_name); + goto fail2; + } + + sock->ref_cnt = 1; + + /* + * is_avail is set to indicate the socket is available for send/listen + */ + sock->is_avail = true; + return 0; + +fail2: + nl_cb_put(sock->nl_cb); + sock->nl_cb = NULL; +fail1: + pthread_spin_destroy(&sock->lock); + sock->lock = (pthread_spinlock_t)0; + return -ENOMEM; +} + +/* + * nss_nlsock_deref() + * decrement the reference count and free socket resources if '0' + */ +static inline void nss_nlsock_deref(struct nss_nlsock_ctx *sock) +{ + assert(sock->ref_cnt > 0); + + pthread_spin_lock(&sock->lock); + if (--sock->ref_cnt) { + pthread_spin_unlock(&sock->lock); + return; + } + + /* + * When there are no more references on the socket, + * deinitialize the socket and destroy the spin lock + * created during nss_nlsock_init + */ + nss_nlsock_deinit(sock); + pthread_spin_unlock(&sock->lock); + + pthread_spin_destroy(&sock->lock); + sock->lock = (pthread_spinlock_t)0; +} + +/* + * nss_nlsock_ref() + * Increment the reference count. + * + * if ref_cnt == 0, return false + * if ref_cnt != 0, increment the socket reference count and return true + */ +static inline bool nss_nlsock_ref(struct nss_nlsock_ctx *sock) +{ + /* + * if ref count is 0, it means there are no references + * on the socket and so return false. Socket will eventually be + * freed by nss_nlsock_deinit else increment the ref count + */ + pthread_spin_lock(&sock->lock); + if (sock->ref_cnt == 0) { + pthread_spin_unlock(&sock->lock); + return false; + } + + sock->ref_cnt++; + pthread_spin_unlock(&sock->lock); + + return true; +} + +/* + * nss_nlsock_listen_callback() + * listen to responses from the netlink socket + * + * The API keeps listening for the responses on the netlink socket + * until socket close is initiated and there are no more + * responses on the socket + */ +static void *nss_nlsock_listen_callback(void *arg) +{ + struct nss_nlsock_ctx *sock = (struct nss_nlsock_ctx *)arg; + assert(sock); + + /* + * drain responses on the socket + */ + for (;;) { + /* + * if, socket is freed then break out + */ + if (!nss_nlsock_ref(sock)) { + break; + } + + /* + * get or block for pending messages + */ + nl_recvmsgs(sock->nl_sk, sock->nl_cb); + nss_nlsock_deref(sock); + } + + return NULL; +} + +/* + * nss_nlsock_msg_init() + * Initialize parameters to send message down the socket + */ +static int nss_nlsock_msg_init(struct nss_nlsock_ctx *sock, struct nss_nlcmn *cm, void *data, struct nl_msg *msg) +{ + int pid = sock->pid; + void *user_hdr; + uint32_t ver; + uint8_t cmd; + int len; + + ver = nss_nlcmn_get_ver(cm); + len = nss_nlcmn_get_len(cm); + cmd = nss_nlcmn_get_cmd(cm); + + /* + * create space for user header + */ + user_hdr = genlmsg_put(msg, pid, NL_AUTO_SEQ, sock->family_id, len, 0, cmd, ver); + if (!user_hdr) { + nss_nlsock_log_error("%d:failed to put message header of len(%d)\n", pid, len); + return -ENOMEM; + + } + + memcpy(user_hdr, data, len); + return 0; +} + +/* + * nss_nlsock_leave_grp() + * nl socket unsubscribe for the multicast group + */ +int nss_nlsock_leave_grp(struct nss_nlsock_ctx *sock, char *grp_name) +{ + int error; + + assert(sock->ref_cnt > 0); + + /* + * Resolve the group + */ + sock->grp_id = genl_ctrl_resolve_grp(sock->nl_sk, sock->family_name, grp_name); + if (sock->grp_id < 0) { + nss_nlsock_log_error("failed to resolve group(%s)\n", grp_name); + return -EINVAL; + } + + /* + * Unsubscribe for the mcast async events + */ + error = nl_socket_drop_memberships(sock->nl_sk, sock->grp_id, 0); + if (error < 0) { + nss_nlsock_log_error("failed to deregister grp(%s)\n", grp_name); + return error; + } + + return 0; +} + +/* + * nss_nlsock_join_grp() + * nl socket subscribe for the multicast group + */ +int nss_nlsock_join_grp(struct nss_nlsock_ctx *sock, char *grp_name) +{ + int error; + + assert(sock->ref_cnt > 0); + + /* + * Resolve the group + */ + sock->grp_id = genl_ctrl_resolve_grp(sock->nl_sk, sock->family_name, grp_name); + if (sock->grp_id < 0) { + nss_nlsock_log_error("failed to resolve group(%s)\n", grp_name); + return -EINVAL; + } + + /* + * Subscribe for the mcast async events + */ + error = nl_socket_add_memberships(sock->nl_sk, sock->grp_id, 0); + if (error < 0) { + nss_nlsock_log_error("failed to register grp(%s)\n", grp_name); + return error; + } + + return 0; +} + +/* + * nss_nlsock_open_mcast() + * Open the socket for async events + */ +int nss_nlsock_open_mcast(struct nss_nlsock_ctx *sock, nl_recvmsg_msg_cb_t cb) +{ + int error; + assert(sock); + + error = nss_nlsock_init(sock, cb); + if (error) { + nss_nlsock_log_error("%d:failed to initialize socket(%s)\n", sock->pid, sock->family_name); + return error; + } + + /* + * Disable seq number and auto ack checks for sockets listening for mcast events + */ + nl_socket_disable_seq_check(sock->nl_sk); + nl_socket_disable_auto_ack(sock->nl_sk); + + /* + * Connect the socket with the netlink bus + */ + if (genl_connect(sock->nl_sk)) { + nss_nlsock_log_error("%d:failed to connect socket for family(%s)\n", sock->pid, sock->family_name); + error = -EBUSY; + goto free_sock; + } + return 0; + +free_sock: + nss_nlsock_deref(sock); + return error; +} + +/* + * nss_nlsock_send() + * send a message synchronously through the socket + */ +int nss_nlsock_send(struct nss_nlsock_ctx *sock, struct nss_nlcmn *cm, void *data, bool has_resp) +{ + int pid = sock->pid; + struct nl_msg *msg; + int error; + + /* + * return -EBUSY if the socket is currently unavailable for sending message + */ + pthread_spin_lock(&sock->lock); + if (!sock->is_avail) { + pthread_spin_unlock(&sock->lock); + return -EBUSY; + } + + /* + * To indicate the socket is unavailable until the current thread completes the send/listen. + * This is to prevent other threads from simultaneous send/listen. + */ + sock->is_avail = false; + pthread_spin_unlock(&sock->lock); + + /* + * allocate new message buffer + */ + msg = nlmsg_alloc(); + if (!msg) { + nss_nlsock_log_error("%d:failed to allocate message buffer\n", pid); + sock->is_avail = true; + return -ENOMEM; + } + + /* + * Holds a reference on the socket until msg is sent down to the kernel + */ + if (!nss_nlsock_ref(sock)) { + nss_nlsock_log_error("%d:failed to get NL socket\n", pid); + nlmsg_free(msg); + sock->is_avail = true; + return -EINVAL; + } + + /* + * Initialize message parameters + */ + error = nss_nlsock_msg_init(sock, cm, data, msg); + if (error) { + nss_nlsock_log_error("%d:failed to initialize message structure (family:%s, error:%d)\n", + pid, sock->family_name, error); + nss_nlsock_deref(sock); + nlmsg_free(msg); + sock->is_avail = true; + return error; + } + + /* + * If has_resp is true and msg is sent to FW, then there will be two + * netlink messages coming from kernel - FW response and ACK + * If msg fails in netlink, then error will be returned from kernel. + * If has_resp is false, then there is only one netlink message + * coming from kernel: either ACK or error + * In case firmware response is sent before nl_recvmsgs is invoked, + * the response will be queued until the listener is available. + */ + error = nl_send_sync(sock->nl_sk, msg); + if (error < 0) { + nss_nlsock_log_error("%d:failed to send (family:%s, error:%d)\n", pid, sock->family_name, error); + nss_nlsock_deref(sock); + sock->is_avail = true; + return error; + } + + if (has_resp) { + nl_recvmsgs(sock->nl_sk, sock->nl_cb); + } + + nss_nlsock_deref(sock); + sock->is_avail = true; + return 0; +} + +/* + * nss_nlsock_listen() + * listen for async events on the socket + */ +int nss_nlsock_listen(struct nss_nlsock_ctx *sock) +{ + int error; + + assert(sock->ref_cnt > 0); + + /* + * return -EBUSY if the socket is currently unavailable for listening + */ + if (!sock->is_avail) { + return -EBUSY; + } + + /* + * To indicate the socket is unavailable until the current thread completes the send/listen. + * This is to prevent other threads from simultaneous send/listen. + */ + sock->is_avail = false; + + /* + * Create an async thread for clearing the pending resp on the socket asynchronously + */ + error = pthread_create(&sock->thread, NULL, nss_nlsock_listen_callback, sock); + if (error) { + nss_nlsock_log_error("%d:failed to create sync thread for family(%s)\n", sock->pid, sock->family_name); + return error; + } + + return 0; +} + +/* + * nss_nlsock_close() + * close the allocated socket and all associated memory + */ +void nss_nlsock_close(struct nss_nlsock_ctx *sock) +{ + assert(sock); + assert(sock->nl_sk); + assert(sock->ref_cnt > 0); + + /* + * put the reference down for the socket + */ + nss_nlsock_deref(sock); + + /* + * wait for the async thread to complete + */ + if (sock->thread) { + pthread_join(sock->thread, NULL); + sock->thread = NULL; + } +} + +/* + * nss_nlsock_open() + * open a socket for unicast communication with the generic netlink framework + */ +int nss_nlsock_open(struct nss_nlsock_ctx *sock, nl_recvmsg_msg_cb_t cb) +{ + int error = 0; + assert(sock); + + error = nss_nlsock_init(sock, cb); + if (error) { + nss_nlsock_log_error("%d:failed to initialize socket(%s)\n", sock->pid, sock->family_name); + return error; + } + + /* + * Connect the socket with the netlink bus + */ + if (genl_connect(sock->nl_sk)) { + nss_nlsock_log_error("%d:failed to connect socket for family(%s)\n", sock->pid, sock->family_name); + error = -EBUSY; + goto free_sock; + } + + /* + * resolve the family + */ + sock->family_id = genl_ctrl_resolve(sock->nl_sk, sock->family_name); + if (sock->family_id <= 0) { + nss_nlsock_log_error("%d:failed to resolve family(%s)\n", sock->pid, sock->family_name); + error = -EINVAL; + goto free_sock; + } + + return 0; + +free_sock: + + nss_nlsock_deref(sock); + return error; +} diff --git a/nss-userspace-oss/nssinfo/patches/001-fix-warnings.patch b/nss-userspace-oss/nssinfo/patches/001-fix-warnings.patch new file mode 100644 index 0000000..071ed09 --- /dev/null +++ b/nss-userspace-oss/nssinfo/patches/001-fix-warnings.patch @@ -0,0 +1,35 @@ +--- a/src/nssinfo.c ++++ b/src/nssinfo.c +@@ -160,7 +160,7 @@ void nssinfo_print_all(char *node, char + break; + } + +- nssinfo_stats_print("%s_%-*s = %-20llu %-s\n", ++ nssinfo_stats_print("%s_%-*s = %-20lu %-s\n", + node, maxlen, stats_info[i].stats_name, stats_val[i], type); + } + } +@@ -277,12 +277,12 @@ void nssinfo_node_stats_destroy(pthread_ + static char* nssinfo_add_comma(uint64_t num) + { + if (num < 1000) { +- snprintf(buf, sizeof(buf), "%llu", num); ++ snprintf(buf, sizeof(buf), "%lu", num); + return buf; + } + + nssinfo_add_comma(num/1000); +- snprintf(buf + strlen(buf), sizeof(buf[NSSINFO_STR_LEN] + strlen(buf)), ",%03llu", num % 1000); ++ snprintf(buf + strlen(buf), sizeof(buf[NSSINFO_STR_LEN] + strlen(buf)), ",%03lu", num % 1000); + return buf; + } + +@@ -293,7 +293,7 @@ static char* nssinfo_add_comma(uint64_t + static char* nssinfo_add_suffix(uint64_t num) + { + if (num < 1000) { +- snprintf(buf, sizeof(buf), "%llu", num); ++ snprintf(buf, sizeof(buf), "%lu", num); + return buf; + } + diff --git a/nss-userspace-oss/patches/000-create-makefile.patch b/nss-userspace-oss/patches/000-create-makefile.patch new file mode 100644 index 0000000..8e77c38 --- /dev/null +++ b/nss-userspace-oss/patches/000-create-makefile.patch @@ -0,0 +1,32 @@ +--- /dev/null ++++ b/Makefile +@@ -0,0 +1,28 @@ ++# Define the build directories based on flags ++DIRS-y := ++DIRS-$(BUILD_LIBNSS) += lib ++DIRS-$(BUILD_NSSINFO) += nssinfo ++DIRS-$(BUILD_NETFN) += netfn ++DIRS-$(BUILD_LIBPPE) += ppe/ppenl_lib ++DIRS-$(BUILD_PPECFG) += ppe/ppecfg ++ ++# Main targets ++all: $(DIRS-y) ++ @echo "Build complete" ++ ++# Pattern rule to build each directory ++$(DIRS-y): ++ $(MAKE) -C $@ ++ ++nssinfo: lib ++ ++ppe/ppecfg: ppe/ppenl_lib ++ ++clean: ++ @for dir in $(DIRS-y); do \ ++ if [ -d $$dir ]; then \ ++ $(MAKE) -C $$dir clean; \ ++ fi \ ++ done ++ ++.PHONY: all clean $(DIRS-y) +\ No newline at end of file diff --git a/nss-userspace-oss/patches/001-libnl-nss-revert-Add-timestamp-support-to-udpst.patch b/nss-userspace-oss/patches/001-libnl-nss-revert-Add-timestamp-support-to-udpst.patch new file mode 100644 index 0000000..a6a4b32 --- /dev/null +++ b/nss-userspace-oss/patches/001-libnl-nss-revert-Add-timestamp-support-to-udpst.patch @@ -0,0 +1,24 @@ +--- a/lib/nss_nludp_st_api.c ++++ b/lib/nss_nludp_st_api.c +@@ -1,12 +1,9 @@ + /* + ************************************************************************** + * Copyright (c) 2021, The Linux Foundation. All rights reserved. +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. +- * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +- * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -52,8 +49,6 @@ int nss_nludp_st_sock_cb(struct nl_msg * + case NSS_UDP_ST_STOP_MSG: + case NSS_UDP_ST_TX_CREATE_MSG: + case NSS_UDP_ST_TX_DESTROY_MSG: +- case NSS_UDP_ST_TX_UPDATE_RATE_MSG: +- case NSS_UDP_ST_RX_MODE_SET_MSG: + case NSS_UDP_ST_RESET_STATS_MSG: + { + void *cb_data = nss_nlcmn_get_cb_data(&rule->cm, sock->family_id); diff --git a/nss-userspace-oss/patches/001-nssinfo-fix-warnings.patch b/nss-userspace-oss/patches/001-nssinfo-fix-warnings.patch new file mode 100644 index 0000000..215d975 --- /dev/null +++ b/nss-userspace-oss/patches/001-nssinfo-fix-warnings.patch @@ -0,0 +1,29 @@ +--- a/nssinfo/src/nssinfo.c ++++ b/nssinfo/src/nssinfo.c +@@ -176,8 +176,6 @@ void nssinfo_print_all(char *node, char + } + } + nssinfo_stats_print("\n"); +- +- return; + } + + /* +@@ -278,7 +276,6 @@ void nssinfo_node_stats_destroy(pthread_ + p = next; + } + +- return; + } + + /* +@@ -293,7 +290,8 @@ static char* nssinfo_add_comma(uint64_t + } + + nssinfo_add_comma(num/1000); +- snprintf(buf + strlen(buf), sizeof(buf + strlen(buf)), ",%03lu", num % 1000); ++ snprintf(buf + strlen(buf), sizeof(buf[NSSINFO_STR_LEN] + strlen(buf)), ",%03lu", ++ num % 1000); + return buf; + } + diff --git a/nss-userspace-oss/patches/002-libnl-modularize-makefile.patch b/nss-userspace-oss/patches/002-libnl-modularize-makefile.patch new file mode 100644 index 0000000..ca1f314 --- /dev/null +++ b/nss-userspace-oss/patches/002-libnl-modularize-makefile.patch @@ -0,0 +1,48 @@ +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -4,13 +4,44 @@ OBJPATH = obj + + BINARY = $(OBJPATH)/libnl-nss.so + SOURCES = $(wildcard $(SRCPATH)/*.c) +-OBJECTS = $(SOURCES:$(SRCPATH)/%.c=$(OBJPATH)/%.o) + HEADERS = $(wildcard $(SRCPATH)/*.h) + + INCLUDE += -I./include + EXTRA_CFLAGS = -Wall -Werror -fPIC -Wl,-z,relro -Wl,-z,now + EXTRA_LDFLAGS = -pie -Wl,-z,relro -Wl,-z,now + ++# Base objects that are always needed ++BASE_OBJS = ipv4_api ipv6_api mcast_api sock ++ ++# Feature objects that depend on flags ++FEATURE_OBJS = ++ ++ifeq ($(capwap),y) ++ FEATURE_OBJS += capwap_api ++endif ++ifeq ($(dtls),y) ++ FEATURE_OBJS += dtls_api ++endif ++ifeq ($(gre_redir),y) ++ FEATURE_OBJS += gre_redir_api ++endif ++ifeq ($(ipsec),y) ++ FEATURE_OBJS += ipsec_api ++endif ++ifeq ($(qrfs),y) ++ FEATURE_OBJS += qrfs_api ++endif ++ifeq ($(udp_st),y) ++ FEATURE_OBJS += udp_st_api ++endif ++ ++# All objects to build ++OBJS = $(BASE_OBJS) $(FEATURE_OBJS) ++ ++# Convert to actual object file paths ++OBJECTS = $(patsubst %,$(OBJPATH)/nss_nl%.o,$(OBJS)) ++HEADERS = $(wildcard $(SRCPATH)/*.h) ++ + all: release + + release: $(BINARY) diff --git a/nss-userspace-oss/patches/002-nss-switch-to-nl-tiny.patch b/nss-userspace-oss/patches/002-nss-switch-to-nl-tiny.patch new file mode 100644 index 0000000..d99d1cb --- /dev/null +++ b/nss-userspace-oss/patches/002-nss-switch-to-nl-tiny.patch @@ -0,0 +1,40 @@ +--- a/lib/nss_nlsock.c ++++ b/lib/nss_nlsock.c +@@ -379,7 +379,7 @@ int nss_nlsock_send(struct nss_nlsock_ct + * In case firmware response is sent before nl_recvmsgs is invoked, + * the response will be queued until the listener is available. + */ +- error = nl_send_sync(sock->nl_sk, msg); ++ error = nl_send_auto_complete(sock->nl_sk, msg); + if (error < 0) { + nss_nlsock_log_error("%d:failed to send (family:%s, error:%d)\n", pid, sock->family_name, error); + nss_nlsock_deref(sock); +@@ -387,6 +387,17 @@ int nss_nlsock_send(struct nss_nlsock_ct + return error; + } + ++ /* ++ * Wait for ACK response from netlink ++ */ ++ /* error = nl_wait_for_ack(sock->nl_sk); */ ++ /* if (error < 0) { */ ++ /* nss_nlsock_log_error("%d:failed to get ACK (family:%s, error:%d)\n", pid, sock->family_name, error); */ ++ /* nss_nlsock_deref(sock); */ ++ /* sock->is_avail = true; */ ++ /* return error; */ ++ /* } */ ++ + if (has_resp) { + nl_recvmsgs(sock->nl_sk, sock->nl_cb); + } +--- a/nssinfo/Makefile ++++ b/nssinfo/Makefile +@@ -10,7 +10,7 @@ OBJECTS = $(SOURCES:$(SRCDIR)/src/%.c=$( + + INCLUDE += -I../lib/include + EXTRA_CFLAGS = -Wall -Werror -UENABLE_DEBUG +-LDFLAGS = -lnl-genl-3 -lnl-nss -lncurses -lglib-2.0 ++LDFLAGS = -lnl-nss -lnl-tiny -lncurses + LDLIBS = -L../lib/obj + + all: release diff --git a/nss-userspace-oss/patches/0030-fix-build.patch b/nss-userspace-oss/patches/0030-fix-build.patch new file mode 100644 index 0000000..999de96 --- /dev/null +++ b/nss-userspace-oss/patches/0030-fix-build.patch @@ -0,0 +1,303 @@ +--- a/lib/nss_nlmcast_api.c ++++ b/lib/nss_nlmcast_api.c +@@ -94,7 +94,7 @@ int nss_nlmcast_sock_join_grp(struct nss + + error = nss_nlsock_join_grp(&ctx->sock, grp_name); + if (error) { +- nss_nlsock_log_error("Unable to subscribe for mcast group, error(%d)\n", error); ++ /* nss_nlsock_log_error("Unable to subscribe for mcast group, error(%d)\n", error); */ + return error; + } + +--- a/lib/nss_nlsock.c ++++ b/lib/nss_nlsock.c +@@ -221,15 +221,23 @@ int nss_nlsock_leave_grp(struct nss_nlso + { + int error; + +- assert(sock->ref_cnt > 0); ++ /* Skip if socket is invalid */ ++ if (!sock || !sock->nl_sk) { ++ return 0; ++ } ++ ++ /* Safety check: Don't assert on ref_cnt */ ++ if (sock->ref_cnt <= 0) { ++ return 0; ++ } + + /* + * Resolve the group + */ + sock->grp_id = genl_ctrl_resolve_grp(sock->nl_sk, sock->family_name, grp_name); + if (sock->grp_id < 0) { +- nss_nlsock_log_error("failed to resolve group(%s)\n", grp_name); +- return -EINVAL; ++ /* Don't report error, just return success since we can't leave a group that doesn't exist */ ++ return 0; + } + + /* +@@ -259,7 +267,7 @@ int nss_nlsock_join_grp(struct nss_nlsoc + */ + sock->grp_id = genl_ctrl_resolve_grp(sock->nl_sk, sock->family_name, grp_name); + if (sock->grp_id < 0) { +- nss_nlsock_log_error("failed to resolve group(%s)\n", grp_name); ++ /* nss_nlsock_log_error("failed to resolve group(%s)\n", grp_name); */ + return -EINVAL; + } + +--- a/nssinfo/src/nssinfo.c ++++ b/nssinfo/src/nssinfo.c +@@ -20,12 +20,25 @@ + #include + #include "nssinfo.h" + ++/* Keyboard control definitions */ ++#define KEY_QUIT 'q' ++// stop fucking using KEY_HELP as it conflicts with the help key in ncurses ++#define KEY_HELP_ 'h' ++#define KEY_VERBOSE 'v' ++#define KEY_LIST_STATS '?' ++ + static pthread_t nssinfo_display_thread; /* Display statistics thread */ + static char buf[NSSINFO_STR_LEN]; /* Formatted stats buffer */ + bool display_all_stats; /* Display all stats per sub-system */ + int invalid_input; /* Identify invalid input */ + FILE *output_file; /* Output file pointer */ + FILE *flow_file; /* Flow file pointer */ ++static volatile bool quit_requested = false; /* Flag to indicate quit request */ ++ ++/* Forward declarations for new functions */ ++static void nssinfo_display_help(void); ++static void nssinfo_list_available_stats(void); ++static void nssinfo_handle_keyboard_input(void); + + /* Array of pointers to node stats */ + struct node *nodes[NSS_MAX_CORES][NSS_MAX_NET_INTERFACES]; +@@ -350,6 +363,16 @@ static void *nssinfo_stats_display(void + pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS, NULL); + + for (;;) { ++ /* Check for keyboard input */ ++ if (!output_file) { ++ nssinfo_handle_keyboard_input(); ++ ++ /* Check if quit was requested */ ++ if (quit_requested) { ++ break; ++ } ++ } ++ + nssinfo_stats_print("\t\t\t%s\n", mesg); + + /* +@@ -505,6 +528,8 @@ done: + invalid_input = 0; + sleep(arguments.rate); + } ++ ++ return NULL; + } + + /* +@@ -607,11 +632,16 @@ static void nssinfo_notify_callback(int + if (cmd < NSS_NLCMN_SUBSYS_MAX && nssinfo_subsystem_array[cmd].is_inited) { + nssinfo_subsystem_array[cmd].notify(data); + } else { +- nssinfo_error("Unknown message type %d\n", cmd); ++ /* Silently ignore unknown message types */ ++ if (arguments.verbose) { ++ nssinfo_warn("Ignoring unknown message type %d\n", cmd); ++ } + } + } + + /* ++ * nssinfo_deinit() ++ * Release all resources + */ + static void nssinfo_deinit(struct nss_nlmcast_ctx *ctx) + { +@@ -639,10 +669,11 @@ static void nssinfo_deinit(struct nss_nl + + /* + * Release resources used by each subsystem ++ * Only deinitialize subsystems that were successfully initialized + */ + for (i = 0; i < NSS_NLCMN_SUBSYS_MAX; i++) { +- deinit = nssinfo_subsystem_array[i].deinit; +- if (deinit) { ++ if (nssinfo_subsystem_array[i].is_inited && nssinfo_subsystem_array[i].deinit) { ++ deinit = nssinfo_subsystem_array[i].deinit; + deinit(ctx); + } + } +@@ -671,16 +702,25 @@ int nssinfo_init(void) + + /* + * Initialize all the subsystems and subscribe for mcast groups. ++ * Don't exit on subsystem initialization failures - these are expected ++ * if certain kernel modules aren't loaded. + */ + for (i = 0; i < NSS_NLCMN_SUBSYS_MAX; i++) { + init = nssinfo_subsystem_array[i].init; + if (init) { + error = init(&ctx); + if (error) { +- nssinfo_error("%s init failed, error(%d)\n", nssinfo_subsystem_array[i].subsystem_name, error); ++ /* Mark as not initialized so we won't try to use it later */ ++ nssinfo_subsystem_array[i].is_inited = 0; ++ ++ /* Only log warnings in verbose mode */ ++ if (arguments.verbose) { ++ nssinfo_warn("%s init failed, error(%d) - subsystem may not be available\n", ++ nssinfo_subsystem_array[i].subsystem_name, error); ++ } ++ } + } + } +- } + + /* + * Listen for MCAST events from kernel. +@@ -700,7 +740,7 @@ int nssinfo_init(void) + } + + /* +- * Install CTRL-C handler ++ * Install CTRL-C handler and other signal handlers + */ + struct sigaction new_action; + new_action.sa_handler = nssinfo_termination_handler; +@@ -721,3 +761,91 @@ end: + nssinfo_deinit(&ctx); + return error; + } ++ ++/* ++ * nssinfo_display_help() ++ * Display help information for keyboard controls ++ */ ++static void nssinfo_display_help(void) ++{ ++ clear(); ++ mvprintw(0, 0, "NSSINFO Keyboard Controls Help"); ++ mvprintw(2, 0, "q - Quit the application"); ++ mvprintw(3, 0, "h - Display this help screen"); ++ mvprintw(4, 0, "v - Toggle verbose mode"); ++ mvprintw(5, 0, "? - List available statistics"); ++ mvprintw(7, 0, "Press any key to return to stats display..."); ++ refresh(); ++ ++ /* Wait for key press before returning to stats display */ ++ nodelay(stdscr, FALSE); ++ getch(); ++ nodelay(stdscr, TRUE); ++ clear(); ++} ++ ++/* ++ * nssinfo_list_available_stats() ++ * Display list of available statistics modules ++ */ ++static void nssinfo_list_available_stats(void) ++{ ++ int i, row = 0; ++ ++ clear(); ++ mvprintw(row++, 0, "Available Statistics Modules:"); ++ row++; ++ ++ for (i = 0; i < NSS_NLCMN_SUBSYS_MAX; i++) { ++ if (nssinfo_subsystem_array[i].is_inited) { ++ mvprintw(row++, 2, "- %s", nssinfo_subsystem_array[i].subsystem_name); ++ } ++ } ++ ++ mvprintw(row + 2, 0, "Press any key to return to stats display..."); ++ refresh(); ++ ++ /* Wait for key press before returning to stats display */ ++ nodelay(stdscr, FALSE); ++ getch(); ++ nodelay(stdscr, TRUE); ++ clear(); ++} ++ ++/* ++ * nssinfo_handle_keyboard_input() ++ * Process keyboard input for interactive controls ++ */ ++static void nssinfo_handle_keyboard_input(void) ++{ ++ int ch = getch(); ++ ++ if (ch == ERR) { ++ /* No input available */ ++ return; ++ } ++ ++ switch (ch) { ++ case KEY_QUIT: ++ /* Set quit flag to exit application gracefully */ ++ quit_requested = true; ++ raise(SIGINT); /* Signal to terminate */ ++ break; ++ ++ case KEY_HELP_: ++ nssinfo_display_help(); ++ break; ++ ++ case KEY_VERBOSE: ++ /* Toggle verbose mode */ ++ arguments.verbose = !arguments.verbose; ++ break; ++ ++ case KEY_LIST_STATS: ++ nssinfo_list_available_stats(); ++ break; ++ ++ default: ++ break; ++ } ++} +--- a/nssinfo/src/nssinfo_lso_rx.c ++++ b/nssinfo/src/nssinfo_lso_rx.c +@@ -43,7 +43,7 @@ static void nssinfo_lso_rx_stats_display + lso_rx_node = nodes[core][NSS_LSO_RX_INTERFACE]; + if (!lso_rx_node) { + pthread_mutex_unlock(&lso_rx_lock); +- nssinfo_error("%s is not running on the NPU\n", input); ++ /* nssinfo_error("%s is not running on the NPU\n", input); */ + return; + } + +--- a/nssinfo/Makefile ++++ b/nssinfo/Makefile +@@ -10,8 +10,8 @@ OBJECTS = $(SOURCES:$(SRCDIR)/src/%.c=$( + + INCLUDE += -I../lib/include + EXTRA_CFLAGS = -Wall -Werror -UENABLE_DEBUG +-LDFLAGS = -lnl-nss -lnl-tiny -lncurses +-LDLIBS = -L../lib/obj ++LDFLAGS = -lnl-tiny -lncurses ++LDLIBS = -L../lib/obj -Wl,-rpath,\$$ORIGIN/../lib:\$$ORIGIN/../../lib/obj -lnl-nss + + all: release + +@@ -20,12 +20,12 @@ release: $(BINARY) + $(OBJPATH)/%.o: $(SRCPATH)/%.c $(HEADERS) + $(MKDIR) + @echo [CC] $@ +- @$(CC) -c $(CFLAGS) $(EXTRA_CFLAGS) $(INCLUDE) -o $@ $< ++ $(CC) -c $(CFLAGS) $(EXTRA_CFLAGS) $(INCLUDE) -o $@ $< + + $(BINARY): $(OBJECTS) + @echo $(BINARY) + @echo [LD] $@ +- @$(CC) -o $@ $^ $(LDFLAGS) $(LDLIBS) ++ $(CC) -o $@ $^ $(LDFLAGS) $(LDLIBS) + clean: + @echo [Clean] + @rm -f $(OBJECTS) diff --git a/qca-mcs/Makefile b/qca-mcs/Makefile new file mode 100644 index 0000000..6c4a2b0 --- /dev/null +++ b/qca-mcs/Makefile @@ -0,0 +1,68 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-mcs +PKG_RELEASE:=2 + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-mcs.git +PKG_SOURCE_DATE:=2024-09-04 +PKG_SOURCE_PROTO:=git +PKG_SOURCE_VERSION:=e1c59f7 +PKG_MIRROR_HASH:=a88bc7747f5564acc574f252b63fdf0b401254bf6584e0cbbac44e171dcddcb6 +QSDK_VERSION:=12.5 +PKG_VERSION:=$(QSDK_VERSION).$(subst -,.,$(PKG_SOURCE_DATE))~$(PKG_SOURCE_VERSION) + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-mcs + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + URL:=http://www.qca.qualcomm.com + MAINTAINER:=Qualcomm Atheros, Inc. + TITLE:=QCA Multicast Snooping Support + DEPENDS:=+@KERNEL_IPV6_MROUTE +@KERNEL_IP_MROUTE + KCONFIG:=CONFIG_NETFILTER=y + FILES:=$(PKG_BUILD_DIR)/qca-mcs.ko + AUTOLOAD:=$(call AutoLoad,41,qca-mcs) +endef + +define KernelPackage/qca-mcs/Description + This package installs the IGMP/MLD Snooping Module +endef + +QCA_MC_SNOOPING_HEADERS= \ + $(PKG_BUILD_DIR)/mc_api.h \ + $(PKG_BUILD_DIR)/mc_ecm.h \ + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-mcs + $(foreach header_file,$(QCA_MC_SNOOPING_HEADERS), $(CP) $(header_file) $(1)/usr/include/qca-mcs;) + $(foreach header_file,$(QCA_MC_SNOOPING_HEADERS), $(CP) $(header_file) $(1)/usr/include/;) +endef + +EXTRA_CFLAGS+=-Wno-implicit-fallthrough + +QCA_MC_SNOOPING_MAKE_OPTS:= \ + $(KERNEL_MAKE_FLAGS) \ + CONFIG_SUPPORT_MLD=y \ + MDIR=$(PKG_BUILD_DIR) \ + KBUILDPATH=$(LINUX_DIR) \ + KERNELPATH=$(LINUX_SRC_DIR) \ + KERNELRELEASE=$(LINUX_RELEASE) + +define Build/Compile + +$(MAKE) -C $(LINUX_DIR) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + KBUILDPATH=$(LINUX_DIR) \ + $(PKG_MAKE_FLAGS) \ + M=$(PKG_BUILD_DIR) \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + $(strip $(QCA_MC_SNOOPING_MAKE_OPTS)) \ + modules +endef + +$(eval $(call KernelPackage,qca-mcs)) diff --git a/qca-mcs/patches/0001-kernel-5.10-compat.patch b/qca-mcs/patches/0001-kernel-5.10-compat.patch new file mode 100644 index 0000000..55faa26 --- /dev/null +++ b/qca-mcs/patches/0001-kernel-5.10-compat.patch @@ -0,0 +1,18 @@ +--- a/mc_snooping.c ++++ b/mc_snooping.c +@@ -3105,7 +3105,6 @@ static void mc_mdb_cleanup(unsigned long + os_hlist_for_each_entry_rcu(mdb, mdbh, &mc->hash[i], hlist) { + struct mc_port_group *pg; + struct hlist_node *pgh; +- struct net_device *port; + unsigned long expire_time = mc->membership_interval; + + if (hlist_empty(&mdb->pslist)) { +@@ -3140,7 +3139,6 @@ static void mc_mdb_cleanup(unsigned long + else if (time_before(this_timer, next_timer)) + next_timer = this_timer; + } +- port = pg->port; + } + } + } diff --git a/qca-mcs/patches/0002-kernel-6.6.29.patch b/qca-mcs/patches/0002-kernel-6.6.29.patch new file mode 100644 index 0000000..4358ec2 --- /dev/null +++ b/qca-mcs/patches/0002-kernel-6.6.29.patch @@ -0,0 +1,14 @@ +--- a/mc_osdep.h ++++ b/mc_osdep.h +@@ -24,7 +24,11 @@ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) + static inline int os_br_pass_frame_up(struct sk_buff *skb) + { ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 29)) ++ return br_pass_frame_up(skb, false); ++#else + return br_pass_frame_up(skb); ++#endif + } + #else + static inline int os_br_pass_frame_up(struct sk_buff *skb) diff --git a/qca-mcs/patches/0003-fix-header-guard-gcc-15.patch b/qca-mcs/patches/0003-fix-header-guard-gcc-15.patch new file mode 100644 index 0000000..9d67b29 --- /dev/null +++ b/qca-mcs/patches/0003-fix-header-guard-gcc-15.patch @@ -0,0 +1,11 @@ +--- a/mc_ovs.h ++++ b/mc_ovs.h +@@ -14,7 +14,7 @@ + */ + + #ifndef _MC_OVS_H_ +-#define _MC_OVS_H ++#define _MC_OVS_H_ + + int mc_ovs_init(void); + void mc_ovs_exit(void); diff --git a/qca-mcs/patches/0004-kernel-6.12.patch b/qca-mcs/patches/0004-kernel-6.12.patch new file mode 100644 index 0000000..f5313db --- /dev/null +++ b/qca-mcs/patches/0004-kernel-6.12.patch @@ -0,0 +1,120 @@ +--- a/mc_forward.c ++++ b/mc_forward.c +@@ -29,6 +29,9 @@ + #include "mc_snooping.h" + #include "mc_osdep.h" + ++int mc_forward_init(void) __maybe_unused; ++void mc_forward_exit(void) __maybe_unused; ++ + static void mc_retag(void *iph, __be16 etype, __be32 dscp) + { + __be32 _dscp = MC_DSCP(dscp); +--- a/mc_netfilter.c ++++ b/mc_netfilter.c +@@ -26,6 +26,7 @@ + #include "mc_private.h" + #include "mc_api.h" + #include "mc_osdep.h" ++#include "mc_netfilter.h" + + /* mc_br_port_get + * get bridge port by ifindex +@@ -49,15 +50,15 @@ static struct net_bridge_port *mc_br_por + /* mc_pre_routing_hook + * prerouting hook + */ +-static unsigned int mc_pre_routing_hook(void *priv, ++unsigned int mc_pre_routing_hook(void *priv, + struct sk_buff *skb, + const struct nf_hook_state *state) + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)) +-static unsigned int mc_pre_routing_hook(const struct nf_hook_ops *ops, struct sk_buff *skb, ++unsigned int mc_pre_routing_hook(const struct nf_hook_ops *ops, struct sk_buff *skb, + const struct net_device *in, const struct net_device *out, + int(*okfn)(struct sk_buff *)) + #else +-static unsigned int mc_pre_routing_hook(unsigned int hooknum, struct sk_buff *skb, ++unsigned int mc_pre_routing_hook(unsigned int hooknum, struct sk_buff *skb, + const struct net_device *in, const struct net_device *out, + int(*okfn)(struct sk_buff *)) + #endif +@@ -233,15 +234,15 @@ static bool mc_is_report_or_leave(struct + /* mc_forward_hook + * forward hook to the linux kernel + */ +-static unsigned int mc_forward_hook(void *priv, ++unsigned int mc_forward_hook(void *priv, + struct sk_buff *skb, + const struct nf_hook_state *state) + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)) +-static unsigned int mc_forward_hook(const struct nf_hook_ops *ops, struct sk_buff *skb, ++unsigned int mc_forward_hook(const struct nf_hook_ops *ops, struct sk_buff *skb, + const struct net_device *in, const struct net_device *out, + int(*okfn)(struct sk_buff *)) + #else +-static unsigned int mc_forward_hook(unsigned int hooknum, struct sk_buff *skb, ++unsigned int mc_forward_hook(unsigned int hooknum, struct sk_buff *skb, + const struct net_device *in, const struct net_device *out, + int(*okfn)(struct sk_buff *)) + #endif +--- a/mc_netfilter.h ++++ b/mc_netfilter.h +@@ -23,7 +23,15 @@ void mc_netfilter_exit(void); + #include + #include + +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)) ++unsigned int mc_pre_routing_hook(void *priv, ++ struct sk_buff *skb, ++ const struct nf_hook_state *state); ++ ++unsigned int mc_forward_hook(void *priv, ++ struct sk_buff *skb, ++ const struct nf_hook_state *state); ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)) + unsigned int mc_pre_routing_hook(const struct nf_hook_ops *ops, struct sk_buff *skb, + const struct net_device *in, const struct net_device *out, + int(*okfn)(struct sk_buff *)); +--- a/mc_snooping.c ++++ b/mc_snooping.c +@@ -15,6 +15,7 @@ + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + ++#include + #include + #include + #include +@@ -28,7 +29,11 @@ + #include + #include + #include ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 12, 0)) ++#include ++#else + #include ++#endif + #include + #include + #include +@@ -3240,7 +3245,6 @@ static void mc_acl_table_init(struct mc_ + mc->mld_acl.pattern_count = 4; + #endif + +- return; + } + + /* mc_event_delay +--- a/mc_snooping.h ++++ b/mc_snooping.h +@@ -44,6 +44,8 @@ void mc_detach(struct net_device *dev); + + int mc_has_more_instance(void); + ++int mc_proc_create_snooper_entry(void); ++ + extern void mc_nbp_change(struct mc_struct *mc, struct net_device *dev, int event); + + extern void mc_fdb_change(__u8 *mac, int change); diff --git a/qca-nss-cfi/Makefile b/qca-nss-cfi/Makefile new file mode 100644 index 0000000..effecf9 --- /dev/null +++ b/qca-nss-cfi/Makefile @@ -0,0 +1,100 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-cfi +PKG_RELEASE:=3 + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-cfi.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2025-04-04 +PKG_SOURCE_VERSION:=ff11dae +PKG_MIRROR_HASH:=050a9c7f4177099bd60168b68ddc9eff5d62b62992858c89d514b428da93cba2 +QSDK_VERSION:=12.5 +PKG_VERSION:=$(QSDK_VERSION).$(subst -,.,$(PKG_SOURCE_DATE))~$(PKG_SOURCE_VERSION) + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +ifneq (, $(findstring $(CONFIG_TARGET_SUBTARGET), "ipq807x" "ipq60xx" "ipq50xx")) +# 4.4/5.4 + ipq807x/ipq60xx/ipq50xx + CFI_OCF_DIR:=ocf/v2.0 + CFI_CRYPTOAPI_DIR:=cryptoapi/v2.0 +else +# 4.4 Kernel + ipq806x + CFI_CRYPTOAPI_DIR:=cryptoapi/v1.1 + CFI_OCF_DIR:=ocf/v1.0 + CFI_IPSEC_DIR:=ipsec/v1.0 +endif + +define KernelPackage/qca-nss-cfi-cryptoapi + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Cryptographic API modules + DEPENDS:=@TARGET_qualcommax +kmod-qca-nss-crypto +kmod-crypto-authenc @BROKEN + TITLE:=Kernel driver for NSS cfi +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-cfi-cryptoapi),) + FILES:=$(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/qca-nss-cfi-cryptoapi.ko + AUTOLOAD:=$(call AutoLoad,59,qca-nss-cfi-cryptoapi) +endif +endef + +define KernelPackage/qca-nss-cfi-cryptoapi/Description +This package contains a NSS cfi driver for QCA chipset +endef + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-cfi-cryptoapi),) + +ifeq ($(CONFIG_TARGET_BOARD), "qualcommax") + SOC:=$(CONFIG_TARGET_SUBTARGET) +endif + +EXTRA_CFLAGS+= \ + -DCONFIG_NSS_DEBUG_LEVEL=4 \ + -I$(LINUX_DIR)/crypto/ocf \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv + +ifneq (, $(findstring $(CONFIG_TARGET_SUBTARGET), "ipq807x" "ipq60xx" "ipq50xx")) +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-clients +endif + +MAKE_OPTS+= \ + cryptoapi=y \ + NSS_CRYPTOAPI_ABLK=n \ + NSS_CRYPTOAPI_SKCIPHER=y + +MAKE_OPTS+= \ + CFI_CRYPTOAPI_DIR=$(CFI_CRYPTOAPI_DIR) \ + CFI_IPSEC_DIR=$(CFI_IPSEC_DIR) \ + SoC=$(SOC) + +define Build/Compile + +$(KERNEL_MAKE) \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + $(strip $(MAKE_OPTS)) \ + $(PKG_JOBS) \ + modules +endef + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-nss-cfi + $(CP) $(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/../exports/* $(1)/usr/include/qca-nss-cfi + $(CP) $(PKG_BUILD_DIR)/include/* $(1)/usr/include/qca-nss-cfi +endef + +else + +define Build/Compile + : +endef + +define Build/Install + : +endef + +endif + +$(eval $(call KernelPackage,qca-nss-cfi-cryptoapi)) diff --git a/qca-nss-cfi/patches/0004-cryptoapi-v2.0-aead-add-downstream-crypto_tfm_alg_fl.patch b/qca-nss-cfi/patches/0004-cryptoapi-v2.0-aead-add-downstream-crypto_tfm_alg_fl.patch new file mode 100644 index 0000000..a872321 --- /dev/null +++ b/qca-nss-cfi/patches/0004-cryptoapi-v2.0-aead-add-downstream-crypto_tfm_alg_fl.patch @@ -0,0 +1,28 @@ +From 8db77add1a794bdee8eef0a351e40bf1cdf6dfa9 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 22 Jan 2023 22:09:51 +0100 +Subject: [PATCH 4/5] cryptoapi: v2.0: aead: add downstream + crypto_tfm_alg_flags + +crypto_tfm_alg_flags newer made it upstream, but as a temporary stopgap +until a better solution is figured out lets add it. + +Signed-off-by: Robert Marko +--- + cryptoapi/v2.0/nss_cryptoapi_aead.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/cryptoapi/v2.0/nss_cryptoapi_aead.c ++++ b/cryptoapi/v2.0/nss_cryptoapi_aead.c +@@ -61,6 +61,11 @@ + #include + #include "nss_cryptoapi_private.h" + ++static inline u32 crypto_tfm_alg_flags(struct crypto_tfm *tfm) ++{ ++ return tfm->__crt_alg->cra_flags & ~CRYPTO_ALG_TYPE_MASK; ++} ++ + /* + * nss_cryptoapi_aead_ctx2session() + * Cryptoapi function to get the session ID for an AEAD diff --git a/qca-nss-cfi/patches/0007-cryptoapi-v2.0-fix-crash.patch b/qca-nss-cfi/patches/0007-cryptoapi-v2.0-fix-crash.patch new file mode 100644 index 0000000..719c21e --- /dev/null +++ b/qca-nss-cfi/patches/0007-cryptoapi-v2.0-fix-crash.patch @@ -0,0 +1,26 @@ +--- a/cryptoapi/v2.0/nss_cryptoapi_aead.c ++++ b/cryptoapi/v2.0/nss_cryptoapi_aead.c +@@ -97,9 +97,9 @@ int nss_cryptoapi_aead_init(struct crypt + bool need_fallback; + + BUG_ON(!ctx); +- NSS_CRYPTOAPI_SET_MAGIC(ctx); + + memset(ctx, 0, sizeof(struct nss_cryptoapi_ctx)); ++ NSS_CRYPTOAPI_SET_MAGIC(ctx); + + ctx->user = g_cryptoapi.user; + ctx->stats.init++; +--- a/cryptoapi/v2.0/nss_cryptoapi_skcipher.c ++++ b/cryptoapi/v2.0/nss_cryptoapi_skcipher.c +@@ -74,9 +74,9 @@ int nss_cryptoapi_skcipher_init(struct c + struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(base); + + BUG_ON(!ctx); +- NSS_CRYPTOAPI_SET_MAGIC(ctx); + + memset(ctx, 0, sizeof(struct nss_cryptoapi_ctx)); ++ NSS_CRYPTOAPI_SET_MAGIC(ctx); + + ctx->user = g_cryptoapi.user; + ctx->stats.init++; diff --git a/qca-nss-cfi/patches/0009-cryptoapi-v2.0-support-kernel-6.12.patch b/qca-nss-cfi/patches/0009-cryptoapi-v2.0-support-kernel-6.12.patch new file mode 100644 index 0000000..ba97ceb --- /dev/null +++ b/qca-nss-cfi/patches/0009-cryptoapi-v2.0-support-kernel-6.12.patch @@ -0,0 +1,134 @@ +--- a/cryptoapi/v2.0/nss_cryptoapi.c ++++ b/cryptoapi/v2.0/nss_cryptoapi.c +@@ -38,6 +38,9 @@ + #include + #include + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 10, 0)) ++#include ++#endif + #include + #include + #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 6, 0)) +@@ -1849,6 +1852,12 @@ static struct ahash_alg cryptoapi_ahash_ + }, + }; + ++/*------------------------------------------------------------- ++ * Prototypes ++ *------------------------------------------------------------- ++ */ ++bool nss_cryptoapi_is_registered(void); ++ + /* + * nss_cryptoapi_copy_reverse() + * Reverse copy +@@ -1946,7 +1955,7 @@ struct nss_cryptoapi_algo_info *nss_cryp + * nss_cryptoapi_cra_name_lookup() + * Lookup the associated algorithm in NSS for the given transformation by name + */ +-struct nss_cryptoapi_algo_info *nss_cryptoapi_cra_name_lookup(const char *cra_name) ++static struct nss_cryptoapi_algo_info *nss_cryptoapi_cra_name_lookup(const char *cra_name) + { + struct nss_cryptoapi_algo_info *info = g_algo_info; + int i; +@@ -2117,7 +2126,7 @@ skip_iv: + * nss_cryptoapi_ctx_stats_read() + * CryptoAPI context statistics read function + */ +-ssize_t nss_cryptoapi_ctx_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos) ++static ssize_t nss_cryptoapi_ctx_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos) + { + struct nss_cryptoapi_ctx *ctx = fp->private_data; + struct nss_cryptoapi_stats *stats = &ctx->stats; +@@ -2169,7 +2178,7 @@ ssize_t nss_cryptoapi_ctx_stats_read(str + * nss_cryptoapi_ctx_info_read() + * CryptoAPI context info read function + */ +-ssize_t nss_cryptoapi_ctx_info_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos) ++static ssize_t nss_cryptoapi_ctx_info_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos) + { + struct nss_cryptoapi_ctx *ctx = fp->private_data; + ssize_t max_buf_len; +@@ -2244,7 +2253,7 @@ void nss_cryptoapi_add_ctx2debugfs(struc + * nss_cryptoapi_attach_user() + * register crypto core with the cryptoapi CFI + */ +-void nss_cryptoapi_attach_user(void *app_data, struct nss_crypto_user *user) ++static void nss_cryptoapi_attach_user(void *app_data, struct nss_crypto_user *user) + { + struct skcipher_alg *skcipher = cryptoapi_skcipher_algs; + struct aead_alg *aead = cryptoapi_aead_algs; +@@ -2312,7 +2321,7 @@ void nss_cryptoapi_attach_user(void *app + * nss_cryptoapi_detach_user() + * Unregister crypto core with cryptoapi CFI layer + */ +-void nss_cryptoapi_detach_user(void *app_data, struct nss_crypto_user *user) ++static void nss_cryptoapi_detach_user(void *app_data, struct nss_crypto_user *user) + { + struct skcipher_alg *skcipher = cryptoapi_skcipher_algs; + struct aead_alg *aead = cryptoapi_aead_algs; +@@ -2378,7 +2387,7 @@ EXPORT_SYMBOL(nss_cryptoapi_is_registere + * nss_cryptoapi_init() + * Initializing crypto core layer + */ +-int nss_cryptoapi_init(void) ++static int nss_cryptoapi_init(void) + { + nss_cfi_info("module loaded %s\n", NSS_CFI_BUILD_ID); + +@@ -2408,7 +2417,7 @@ int nss_cryptoapi_init(void) + * nss_cryptoapi_exit() + * De-Initialize cryptoapi CFI layer + */ +-void nss_cryptoapi_exit(void) ++static void nss_cryptoapi_exit(void) + { + if (g_cryptoapi.user) + nss_crypto_unregister_user(g_cryptoapi.user); +--- a/cryptoapi/v2.0/nss_cryptoapi_aead.c ++++ b/cryptoapi/v2.0/nss_cryptoapi_aead.c +@@ -386,7 +386,7 @@ int nss_cryptoapi_aead_setauthsize(struc + * nss_cryptoapi_aead_done() + * Cipher/Auth encrypt request completion callback function + */ +-void nss_cryptoapi_aead_done(void *app_data, struct nss_crypto_hdr *ch, uint8_t status) ++static void nss_cryptoapi_aead_done(void *app_data, struct nss_crypto_hdr *ch, uint8_t status) + { + struct aead_request *req = (struct aead_request *)app_data; + struct crypto_aead *aead = crypto_aead_reqtfm(req); +--- a/cryptoapi/v2.0/nss_cryptoapi_ahash.c ++++ b/cryptoapi/v2.0/nss_cryptoapi_ahash.c +@@ -87,6 +87,12 @@ extern struct nss_cryptoapi g_cryptoapi; + + #endif /* NSS_CFI_DEBUG */ + ++/*------------------------------------------------------------- ++ * Prototype ++ *------------------------------------------------------------- ++ */ ++int nss_cryptoapi_ahash_ctx2session(struct crypto_ahash *ahash, uint32_t *sid); ++ + /* + * nss_cryptoapi_ahash_ctx2session() + * Cryptoapi function to get the session ID for an AHASH +@@ -234,7 +240,7 @@ int nss_cryptoapi_ahash_setkey(struct cr + * nss_cryptoapi_ahash_done() + * Hash request completion callback function + */ +-void nss_cryptoapi_ahash_done(void *app_data, struct nss_crypto_hdr *ch, uint8_t status) ++static void nss_cryptoapi_ahash_done(void *app_data, struct nss_crypto_hdr *ch, uint8_t status) + { + struct ahash_request *req = app_data; + struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(req->base.tfm); +--- a/cryptoapi/v2.0/nss_cryptoapi_skcipher.c ++++ b/cryptoapi/v2.0/nss_cryptoapi_skcipher.c +@@ -201,7 +201,7 @@ int nss_cryptoapi_skcipher_setkey(struct + * nss_cryptoapi_skcipher_done() + * Cipher operation completion callback function + */ +-void nss_cryptoapi_skcipher_done(void *app_data, struct nss_crypto_hdr *ch, uint8_t status) ++static void nss_cryptoapi_skcipher_done(void *app_data, struct nss_crypto_hdr *ch, uint8_t status) + { + struct skcipher_request *req = app_data; + struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(req->base.tfm); diff --git a/qca-nss-clients/Config.in b/qca-nss-clients/Config.in new file mode 100644 index 0000000..53d4064 --- /dev/null +++ b/qca-nss-clients/Config.in @@ -0,0 +1,55 @@ +config NSS_NLCAPWAP_ENABLE + bool + depends on PACKAGE_kmod-qca-nss-drv-netlink + default y if NSS_DRV_CAPWAP_ENABLE + help + NSS Netlink CAPWAP support. This is automatically + selected when NSS CAPWAP driver is enabled. + +config NSS_NLDTLS_ENABLE + bool + depends on PACKAGE_kmod-qca-nss-drv-netlink + default y if NSS_DRV_DTLS_ENABLE + help + NSS Netlink DTLS support. This is automatically + selected when NSS DTLS driver is enabled. + +config NSS_NLGRE_REDIR_ENABLE + bool + depends on PACKAGE_kmod-qca-nss-drv-netlink + default y if NSS_DRV_GRE_REDIR_ENABLE + help + NSS Netlink GRE Redirect support. This is automatically + selected when NSS GRE Redirect driver is enabled. + +config NSS_NLIPSEC_ENABLE + bool + depends on PACKAGE_kmod-qca-nss-drv-netlink + default y if NSS_DRV_IPSEC_ENABLE + help + NSS Netlink IPsec support. This is automatically + selected when NSS IPsec driver is enabled. + +config NSS_NLQRFS_ENABLE + bool + depends on PACKAGE_kmod-qca-nss-drv-netlink + default y if NSS_DRV_QRFS_ENABLE + help + NSS Netlink QRFS support. This is automatically + selected when NSS QRFS driver is enabled. + +config NSS_NLUDP_ST_ENABLE + bool + depends on PACKAGE_kmod-qca-nss-drv-netlink + default y if NSS_DRV_UDP_ST_ENABLE + help + NSS Netlink UDP Speed Test support. This is automatically + selected when NSS UDP Speed Test driver is enabled. + +config NSS_NLLSO_RX + bool + depends on PACKAGE_kmod-qca-nss-drv-netlink + default y if NSS_DRV_LSO_RX_ENABLE + help + NSS Netlink IP LSO RX support. This is automatically + selected when NSS IP LSO RX driver is enabled. diff --git a/qca-nss-clients/Makefile b/qca-nss-clients/Makefile new file mode 100644 index 0000000..f172027 --- /dev/null +++ b/qca-nss-clients/Makefile @@ -0,0 +1,895 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-clients +PKG_RELEASE:=8 + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-clients.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2024-09-11 +PKG_SOURCE_VERSION:=51be82d +PKG_MIRROR_HASH:=876c3898cb4723fccd4a1c870324724dd7c4061ac89ec88db2226fd749c18b38 +QSDK_VERSION:=12.5 +PKG_VERSION:=$(QSDK_VERSION).$(subst -,.,$(PKG_SOURCE_DATE))~$(PKG_SOURCE_VERSION) + +PKG_BUILD_PARALLEL:=1 + +PKG_CONFIG_DEPENDS:=\ + CONFIG_NSS_DRV_BRIDGE_ENABLE \ + CONFIG_NSS_DRV_C2C_ENABLE \ + CONFIG_NSS_DRV_CAPWAP_ENABLE \ + CONFIG_NSS_DRV_CLMAP_ENABLE \ + CONFIG_NSS_DRV_DTLS_ENABLE \ + CONFIG_NSS_DRV_GRE_ENABLE \ + CONFIG_NSS_DRV_GRE_REDIR_ENABLE \ + CONFIG_NSS_DRV_IGS_ENABLE \ + CONFIG_NSS_DRV_IPSEC_ENABLE \ + CONFIG_NSS_DRV_IPV4_REASM_ENABLE \ + CONFIG_NSS_DRV_IPV6_ENABLE \ + CONFIG_NSS_DRV_IPV6_REASM_ENABLE \ + CONFIG_NSS_DRV_L2TP_ENABLE \ + CONFIG_NSS_DRV_LAG_ENABLE \ + CONFIG_NSS_DRV_LSO_RX_ENABLE \ + CONFIG_NSS_DRV_MAPT_ENABLE \ + CONFIG_NSS_DRV_MATCH_ENABLE \ + CONFIG_NSS_DRV_MIRROR_ENABLE \ + CONFIG_NSS_DRV_OAM_ENABLE \ + CONFIG_NSS_DRV_QVPN_ENABLE \ + CONFIG_NSS_DRV_PPPOE_ENABLE \ + CONFIG_NSS_DRV_PPTP_ENABLE \ + CONFIG_NSS_DRV_PVXLAN_ENABLE \ + CONFIG_NSS_DRV_QRFS_ENABLE \ + CONFIG_NSS_DRV_RMNET_ENABLE \ + CONFIG_NSS_DRV_SHAPER_ENABLE \ + CONFIG_NSS_DRV_TLS_ENABLE \ + CONFIG_NSS_DRV_TSTAMP_ENABLE \ + CONFIG_NSS_DRV_TUN6RD_ENABLE \ + CONFIG_NSS_DRV_TUNIPIP6_ENABLE \ + CONFIG_NSS_DRV_VLAN_ENABLE \ + CONFIG_NSS_DRV_VXLAN_ENABLE \ + CONFIG_NSS_DRV_WIFIOFFLOAD_ENABLE \ + CONFIG_NSS_DRV_WIFI_MESH_ENABLE \ + CONFIG_NSS_DRV_WIFI_LEGACY_ENABLE \ + CONFIG_NSS_FIRMWARE_VERSION_11_4 + +ifeq ($(CONFIG_NSS_FIRMWARE_VERSION_11_4),y) +PKG_SOURCE_DATE:=2021-08-17 +PKG_SOURCE_VERSION:=c4049d1 +PKG_MIRROR_HASH:=5346ff2a8a89f6d671543f22e13594343b27bf81e709f07af46ade03a7614900 +PATCH_DIR:=$(CURDIR)/patches-11.4 +QSDK_VERSION:=11.4.0.5 +PKG_VERSION:=$(QSDK_VERSION).$(subst -,.,$(PKG_SOURCE_DATE))~$(PKG_SOURCE_VERSION) +endif + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq807x") + SOC="ipq807x_64" + subtarget:=$(CONFIG_TARGET_SUBTARGET) +else ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq60xx") + SOC="ipq60xx_64" + subtarget:=$(CONFIG_TARGET_SUBTARGET) +else ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq50xx") + SOC="ipq50xx_64" + subtarget:=$(CONFIG_TARGET_SUBTARGET) +else + SOC=$(CONFIG_TARGET_BOARD) +endif + +ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64" "ipq50xx" "ipq50xx_64")) +# DTLS Manager v2.0 for Hawkeye/Cypress + DTLSMGR_DIR:=v2.0 +# IPsec Manager v2.0 for Hawkeye/Cypress + IPSECMGR_DIR:=v2.0 +# KLIPS plugin + # IPSECMGR_KLIPS:= $(PKG_BUILD_DIR)/ipsecmgr/$(IPSECMGR_DIR)/plugins/klips/qca-nss-ipsec-klips.ko +endif + +define KernelPackage/qca-nss-drv-tun6rd + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS connection manager for 6rd tunnels + DEPENDS:=@(TARGET_qualcommax||TARGET_ipq806x) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_TUN6RD_ENABLE \ + +6rd \ + +kmod-sit + FILES:=$(PKG_BUILD_DIR)/qca-nss-tun6rd.ko + AUTOLOAD:=$(call AutoLoad,60,qca-nss-tun6rd) +endef + +define KernelPackage/qca-nss-drv-tun6rd/description +Kernel modules for NSS connection manager - Support for 6rd tunnel +endef + +define KernelPackage/qca-nss-drv-dtlsmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS connection manager for DTLS sessions + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_qualcommax_ipq60xx) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_DTLS_ENABLE \ + +kmod-qca-nss-cfi-cryptoapi \ + @BROKEN + FILES:=$(PKG_BUILD_DIR)/dtls/$(DTLSMGR_DIR)/qca-nss-dtlsmgr.ko +endef + +define KernelPackage/qca-nss-drv-dtls/description +Kernel modules for NSS connection manager - Support for DTLS sessions +endef + +define KernelPackage/qca-nss-drv-tlsmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS connection manager for TLS sessions + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_qualcommax_ipq60xx) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_TLS_ENABLE \ + +kmod-qca-nss-cfi-cryptoapi \ + @BROKEN + FILES:=$(PKG_BUILD_DIR)/tls/qca-nss-tlsmgr.ko +endef + +define KernelPackage/qca-nss-drv-tls/description +Kernel modules for NSS connection manager - Support for TLS sessions +endef + +define KernelPackage/qca-nss-drv-l2tpv2 + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS connection manager for L2TPv2 protocol + DEPENDS:=@(TARGET_qualcommax||TARGET_ipq806x) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_L2TP_ENABLE \ + +kmod-l2tp \ + +kmod-ppp + FILES:=$(PKG_BUILD_DIR)/l2tp/l2tpv2/qca-nss-l2tpv2.ko + KCONFIG:=CONFIG_L2TP=y + AUTOLOAD:=$(call AutoLoad,51,qca-nss-l2tpv2) +endef + +define KernelPackage/qca-nss-drv-l2tp/description +Kernel modules for NSS connection manager - Support for l2tp tunnel +endef + +define KernelPackage/qca-nss-drv-pptp + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS connection manager for PPTP protocol + DEPENDS:=@(TARGET_qualcommax||TARGET_ipq806x) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_PPTP_ENABLE \ + +kmod-pptp + FILES:=$(PKG_BUILD_DIR)/pptp/qca-nss-pptp.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-pptp) +endef + +define KernelPackage/qca-nss-drv-pptp/description +Kernel modules for NSS connection manager - Support for PPTP tunnel +endef + +define KernelPackage/qca-nss-drv-pppoe + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS connection manager for PPPoE protocol + DEPENDS:=@(TARGET_qualcommax||TARGET_ipq806x) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_PPPOE_ENABLE \ + +kmod-bonding \ + +kmod-ppp \ + +kmod-pppoe + FILES:=$(PKG_BUILD_DIR)/pppoe/qca-nss-pppoe.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-pppoe) +endef + +define KernelPackage/qca-nss-drv-pppoe/Description +Kernel modules for NSS connection manager - Support for PPPoE +endef + +define KernelPackage/qca-nss-drv-map-t + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS connection manager for MAP-T protocol + DEPENDS:=@TARGET_qualcommax \ + +kmod-qca-nss-drv \ + +@NSS_DRV_MAPT_ENABLE \ + +kmod-nat46 + FILES:=$(PKG_BUILD_DIR)/map/map-t/qca-nss-map-t.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-map-t) +endef + +define KernelPackage/qca-nss-drv-map-t/description +Kernel modules for NSS connection manager - Support for MAP-T +endef + +define KernelPackage/qca-nss-drv-gre + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS connection manager for GRE protocol + DEPENDS:=@(TARGET_qualcommax||TARGET_ipq806x) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_GRE_ENABLE \ + +kmod-gre6 + FILES:=$(PKG_BUILD_DIR)/gre/qca-nss-gre.ko $(PKG_BUILD_DIR)/gre/test/qca-nss-gre-test.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-gre) +endef + +define KernelPackage/qca-nss-drv-gre/description +Kernel modules for NSS connection manager - Support for GRE +endef + +define KernelPackage/qca-nss-drv-tunipip6 + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS connection manager for IPIP6 tunnels + DEPENDS:=@(TARGET_qualcommax||TARGET_ipq806x) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_TUNIPIP6_ENABLE \ + +kmod-ip6-tunnel \ + +kmod-iptunnel6 + FILES:=$(PKG_BUILD_DIR)/tunipip6/qca-nss-tunipip6.ko + AUTOLOAD:=$(call AutoLoad,60,qca-nss-tunipip6) +endef + +define KernelPackage/qca-nss-drv-tunipip6/description +Kernel modules for NSS connection manager +Add support for DS-lite and ipip6 tunnel +endef + +define KernelPackage/qca-nss-drv-profile + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Profiler for QCA NSS driver (IPQ806x) + DEPENDS:=@TARGET_ipq806x \ + +kmod-qca-nss-drv + FILES:=$(PKG_BUILD_DIR)/profiler/qca-nss-profile-drv.ko +endef + +define KernelPackage/qca-nss-drv-profile/Description +This package contains a NSS driver profiler for QCA chipset +endef + +define KernelPackage/qca-nss-drv-ipsecmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS connection manager for IPSEC protocol + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_qualcommax_ipq60xx) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_IPSEC_ENABLE \ + +kmod-qca-nss-cfi-cryptoapi \ + +PACKAGE_kmod-qca-nss-drv-l2tpv2:kmod-qca-nss-drv-l2tpv2 \ + @BROKEN + FILES:=$(PKG_BUILD_DIR)/ipsecmgr/$(IPSECMGR_DIR)/qca-nss-ipsecmgr.ko + AUTOLOAD:=$(call AutoLoad,60,qca-nss-ipsecmgr) +endef + +define KernelPackage/qca-nss-drv-ipsecmgr/Description +Kernel module for NSS IPsec offload manager +endef + +define KernelPackage/qca-nss-drv-ipsecmgr-klips + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (ipsec klips) + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_qualcommax_ipq60xx) \ + @LINUX_5_4 \ + +kmod-qca-nss-drv-ipsecmgr \ + +kmod-qca-nss-cfi-cryptoapi \ + +PACKAGE_kmod-qca-nss-drv-vxlanmgr:kmod-qca-nss-drv-vxlanmgr \ + @BROKEN + FILES:=$(PKG_BUILD_DIR)/ipsecmgr/$(IPSECMGR_DIR)/plugins/klips/qca-nss-ipsec-klips.ko +endef + +define KernelPackage/qca-nss-drv-ipsecmgr-klips/Description +NSS Kernel module for IPsec klips offload +endef + +define KernelPackage/qca-nss-drv-ipsecmgr-xfrm + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (ipsec xfrm) + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_qualcommax_ipq60xx) \ + +kmod-qca-nss-drv-ipsecmgr \ + +kmod-qca-nss-ecm \ + +PACKAGE_kmod-qca-nss-drv-vxlanmgr:kmod-qca-nss-drv-vxlanmgr \ + +kmod-ipsec \ + @BROKEN + FILES:=$(PKG_BUILD_DIR)/ipsecmgr/$(IPSECMGR_DIR)/plugins/xfrm/qca-nss-ipsec-xfrm.ko +endef + +define KernelPackage/qca-nss-drv-ipsecmgr-xfrm/Description +NSS Kernel module for IPsec xfrm offload +endef + +define KernelPackage/qca-nss-drv-capwapmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS CAPWAP manager for QCA NSS + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_qualcommax_ipq60xx) \ + +kmod-qca-nss-drv \ + +kmod-qca-nss-drv-dtlsmgr \ + +@NSS_DRV_TRUSTSEC_ENABLE \ + +@NSS_DRV_CAPWAP_ENABLE \ + @BROKEN + FILES:=$(PKG_BUILD_DIR)/capwapmgr/qca-nss-capwapmgr.ko +endef + +define KernelPackage/qca-nss-drv-capwapmgr/Description +This package contains a NSS CAPWAP manager +endef + +define KernelPackage/qca-nss-drv-bridge-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS bridge manager + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_qualcommax_ipq60xx) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_BRIDGE_ENABLE \ + +kmod-qca-nss-drv-vlan-mgr \ + +kmod-bonding +ifneq ($(CONFIG_PACKAGE_kmod-qca-ovsmgr),) + DEPENDS+=kmod-qca-ovsmgr +endif + FILES:=$(PKG_BUILD_DIR)/bridge/qca-nss-bridge-mgr.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-bridge-mgr) +endef + +define KernelPackage/qca-nss-drv-bridge-mgr/Description +Kernel modules for NSS bridge manager +endef + +define KernelPackage/qca-nss-drv-vlan-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS vlan manager + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_qualcommax_ipq60xx) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_VLAN_ENABLE \ + +kmod-bonding + FILES:=$(PKG_BUILD_DIR)/vlan/qca-nss-vlan.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-vlan) +endef + +define KernelPackage/qca-nss-drv-vlan-mgr/Description +Kernel modules for NSS vlan manager +endef + +define KernelPackage/qca-nss-drv-qdisc + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Qdisc for configuring shapers in NSS + DEPENDS:=@(TARGET_qualcommax||TARGET_ipq806x) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_SHAPER_ENABLE \ + +@NSS_DRV_IGS_ENABLE \ + +!TARGET_qualcommax_ipq50xx:kmod-qca-nss-drv-bridge-mgr + FILES:=$(PKG_BUILD_DIR)/nss_qdisc/qca-nss-qdisc.ko + KCONFIG:=CONFIG_NET_CLS_ACT=y +endef + +define KernelPackage/qca-nss-drv-qdisc/Description +Linux qdisc that aids in configuring shapers in the NSS +endef + +define KernelPackage/qca-nss-drv-igs + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS connection manager to perform ingress shaping + DEPENDS:=@(TARGET_qualcommax||TARGET_ipq806x) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_IGS_ENABLE \ + +kmod-qca-nss-drv-qdisc \ + +kmod-ifb \ + +kmod-nf-conntrack \ + +kmod-sched-core + FILES:=$(PKG_BUILD_DIR)/nss_qdisc/igs/act_nssmirred.ko +endef + +define KernelPackage/qca-nss-drv-igs/description +Linux action that helps in offloading traffic to an IFB interface to perform ingress shaping. +endef + +define KernelPackage/qca-nss-drv-lag-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS LAG (link aggregation) manager + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_qualcommax_ipq60xx) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_LAG_ENABLE \ + +kmod-qca-nss-drv-vlan-mgr \ + +kmod-bonding + FILES:=$(PKG_BUILD_DIR)/lag/qca-nss-lag-mgr.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-lag-mgr) +endef + +define KernelPackage/qca-nss-drv-lag-mgr/description +Kernel modules for NSS LAG manager +endef + +define KernelPackage/qca-nss-drv-netlink + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS NETLINK manager for QCA NSS driver + DEPENDS:=@TARGET_qualcommax \ + +kmod-qca-nss-drv \ + +@NSS_DRV_IPV6_ENABLE \ + +@NSS_DRV_WIFIOFFLOAD_ENABLE \ + +@NSS_DRV_UDP_ST_ENABLE:NSS_DRV_RMNET_ENABLE \ + +@NSS_DRV_C2C_ENABLE:NSS_DRV_C2C_ENABLE \ + +PACKAGE_kmod-qca-nss-drv-capwapmgr:kmod-qca-nss-drv-capwapmgr \ + +PACKAGE_kmod-qca-nss-drv-dtlsmgr:kmod-qca-nss-drv-dtlsmgr \ + +PACKAGE_kmod-qca-nss-drv-gre:kmod-qca-nss-drv-gre \ + +PACKAGE_kmod-qca-nss-drv-ipsecmgr-xfrm:kmod-qca-nss-drv-ipsecmgr \ + +PACKAGE_kmod-qca-nss-drv-igs:kmod-qca-nss-drv-igs \ + +PACKAGE_kmod-qca-nss-drv-l2tpv2:kmod-qca-nss-drv-l2tpv2 \ + +PACKAGE_kmod-qca-nss-drv-lag-mgr:kmod-qca-nss-drv-lag-mgr \ + +PACKAGE_kmod-qca-nss-drv-map-t:kmod-qca-nss-drv-map-t \ + +PACKAGE_kmod-qca-nss-drv-match:kmod-qca-nss-drv-match \ + +PACKAGE_kmod-qca-nss-drv-mirror:kmod-qca-nss-drv-mirror \ + +PACKAGE_kmod-qca-nss-drv-pppoe:kmod-qca-nss-drv-pppoe \ + +PACKAGE_kmod-qca-nss-drv-pptp:kmod-qca-nss-drv-pptp \ + +PACKAGE_kmod-qca-nss-drv-qdisc:kmod-qca-nss-drv-qdisc \ + +PACKAGE_kmod-qca-nss-drv-tun6rd:kmod-qca-nss-drv-tun6rd \ + +PACKAGE_kmod-qca-nss-drv-tunipip6:kmod-qca-nss-drv-tunipip6 \ + +PACKAGE_kmod-qca-nss-drv-vxlanmgr:kmod-qca-nss-drv-vxlanmgr \ + +@(PACKAGE_kmod-qca-nss-drv-gre):NSS_DRV_GRE_REDIR_ENABLE + FILES:=$(PKG_BUILD_DIR)/netlink/qca-nss-netlink.ko +endef + +define KernelPackage/qca-nss-drv-netlink/Description +Kernel module for NSS netlink manager +endef + +define KernelPackage/qca-nss-drv-netlink/config + source "$(SOURCE)/Config.in" +endef + +define KernelPackage/qca-nss-drv-ovpn-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS OpenVPN manager + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_qualcommax_ipq60xx) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_QVPN_ENABLE \ + +kmod-qca-nss-cfi-cryptoapi \ + +kmod-nf-conntrack \ + +kmod-tun \ + @BROKEN + FILES:=$(PKG_BUILD_DIR)/openvpn/src/qca-nss-ovpn-mgr.ko +endef + +define KernelPackage/qca-nss-drv-ovpn-mgr/description +Kernel module for NSS OpenVPN manager +endef + +define KernelPackage/qca-nss-drv-ovpn-link + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for interfacing NSS OpenVPN manager with ECM + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_qualcommax_ipq60xx) \ + +kmod-qca-nss-drv-ovpn-mgr \ + +kmod-qca-nss-ecm \ + @BROKEN + FILES:=$(PKG_BUILD_DIR)/openvpn/plugins/qca-nss-ovpn-link.ko +endef + +define KernelPackage/qca-nss-drv-ovpn-link/description +This module registers with ECM and communicates with NSS OpenVPN manager for supporting OpenVPN offload. +endef + +define KernelPackage/qca-nss-drv-pvxlanmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS connection manager for PVxLANs + DEPENDS:=@TARGET_qualcommax \ + +kmod-qca-nss-drv \ + +@NSS_DRV_PVXLAN_ENABLE \ + +kmod-vxlan \ + @BROKEN + FILES:=$(PKG_BUILD_DIR)/pvxlanmgr/qca-nss-pvxlanmgr.ko +endef + +define KernelPackage/qca-nss-drv-pvxlanmgr/description +NSS kernel module for managing Paravirtualized Extensible LAN (PVxLAN) connections +endef + +define KernelPackage/qca-nss-drv-eogremgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS EOGRE manager for QCA NSS driver + DEPENDS:=@TARGET_qualcommax \ + +kmod-qca-nss-drv \ + +kmod-qca-nss-drv-gre + FILES:=$(PKG_BUILD_DIR)/eogremgr/qca-nss-eogremgr.ko +endef + +define KernelPackage/qca-nss-drv-eogremgr/description +Kernel module for managing NSS EoGRE +endef + +define KernelPackage/qca-nss-drv-clmapmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS clmap manager for QCA NSS driver + DEPENDS:=@TARGET_qualcommax \ + +kmod-qca-nss-drv \ + +@NSS_DRV_CLMAP_ENABLE \ + +kmod-qca-nss-drv-eogremgr \ + @BROKEN + FILES:=$(PKG_BUILD_DIR)/clmapmgr/qca-nss-clmapmgr.ko +endef + +define KernelPackage/qca-nss-drv-clmapmgr/description +Kernel module for managing NSS clmap +endef + +define KernelPackage/qca-nss-drv-vxlanmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS VxLAN manager for QCA NSS driver + DEPENDS:=@TARGET_qualcommax \ + +kmod-qca-nss-drv \ + +@NSS_DRV_VXLAN_ENABLE \ + +kmod-vxlan + FILES:=$(PKG_BUILD_DIR)/vxlanmgr/qca-nss-vxlanmgr.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-vxlanmgr) +endef + +define KernelPackage/qca-nss-drv-vxlanmgr/description +Kernel module for managing NSS VxLAN +endef + +define KernelPackage/qca-nss-drv-match + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS Match for QCA NSS driver + DEPENDS:=@TARGET_qualcommax \ + +kmod-qca-nss-drv \ + +@NSS_DRV_MATCH_ENABLE \ + +@NSS_DRV_WIFIOFFLOAD_ENABLE + FILES:=$(PKG_BUILD_DIR)/match/qca-nss-match.ko +endef + +define KernelPackage/qca-nss-drv-match/description +Kernel module for managing NSS Match +endef + +define KernelPackage/qca-nss-drv-mirror + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Module for mirroring packets from NSS to host + DEPENDS:=@TARGET_qualcommax \ + +kmod-qca-nss-drv \ + +@NSS_DRV_MIRROR_ENABLE + FILES:=$(PKG_BUILD_DIR)/mirror/qca-nss-mirror.ko +endef + +define KernelPackage/qca-nss-drv-mirror/Description +Kernel module for managing NSS Mirror +endef + +define KernelPackage/qca-nss-drv-mscs + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Module to interface wlan host driver and ECM MSCS classifier. + DEPENDS:=@TARGET_qualcommbe \ + +kmod-qca-nss-drv \ + +@NSS_DRV_WIFIOFFLOAD_ENABLE + FILES:=$(PKG_BUILD_DIR)/mscs/qca-nss-mscs.ko +endef + +define KernelPackage/qca-nss-drv-mscs/Description +Kernel module for Mirrored Stream Classification Signalling(MSCS) NSS client +endef + +define KernelPackage/qca-nss-drv-wifi-meshmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS WiFi-Mesh manager for QCA NSS driver + DEPENDS:=@TARGET_qualcommax \ + +kmod-qca-nss-drv \ + +@NSS_DRV_WIFI_MESH_ENABLE + FILES:=$(PKG_BUILD_DIR)/wifi_meshmgr/qca-nss-wifi-meshmgr.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-wifi-meshmgr) +endef + +define KernelPackage/qca-nss-drv-wifi-meshmgr/Description +Kernel module for WiFi Mesh manager +endef + +define Build/InstallDev/qca-nss-clients + $(INSTALL_DIR) $(1)/usr/include/qca-nss-clients + $(CP) $(PKG_BUILD_DIR)/netlink/include/* $(1)/usr/include/qca-nss-clients/ + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-clients/ +endef + +define Build/InstallDev + $(call Build/InstallDev/qca-nss-clients,$(1)) +endef + +define KernelPackage/qca-nss-drv-ovpn-mgr/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-nss-ovpn.init $(1)/etc/init.d/qca-nss-ovpn +endef + +define KernelPackage/qca-nss-drv-ipsecmgr-klips/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-nss-ipsec $(1)/etc/init.d/qca-nss-ipsec +endef + +define KernelPackage/qca-nss-drv-ipsecmgr-xfrm/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-nss-ipsec $(1)/etc/init.d/qca-nss-ipsec +endef + +define KernelPackage/qca-nss-drv-netlink/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-nss-netlink.init $(1)/etc/init.d/qca-nss-netlink +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-cfi \ + -I$(STAGING_DIR)/usr/include/qca-nss-ecm \ + -I$(STAGING_DIR)/usr/include/qca-ssdk \ + -I$(STAGING_DIR)/usr/include/qca-ssdk/fal \ + -I$(STAGING_DIR)/usr/include/nat46 + +# Build individual packages if selected +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-profile),) +NSS_CLIENTS_MAKE_OPTS+=profile=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-capwapmgr),) +NSS_CLIENTS_MAKE_OPTS+=capwapmgr=y +EXTRA_CFLAGS += -DNSS_CAPWAPMGR_ONE_NETDEV +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-tun6rd),) +NSS_CLIENTS_MAKE_OPTS+=tun6rd=m +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-dtlsmgr),) +NSS_CLIENTS_MAKE_OPTS+=dtlsmgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-tlsmgr),) +EXTRA_CFLAGS+= -I$(PKG_BUILD_DIR)/exports +NSS_CLIENTS_MAKE_OPTS+=tlsmgr=m +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-l2tpv2),) +NSS_CLIENTS_MAKE_OPTS+=l2tpv2=y +EXTRA_CFLAGS += -DNSS_L2TPV2_ENABLED +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pptp),) +NSS_CLIENTS_MAKE_OPTS+=pptp=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-map-t),) +NSS_CLIENTS_MAKE_OPTS+=map-t=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-tunipip6),) +NSS_CLIENTS_MAKE_OPTS+=tunipip6=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-qdisc),) +NSS_CLIENTS_MAKE_OPTS+=qdisc=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-igs),) +NSS_CLIENTS_MAKE_OPTS+=igs=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ipsecmgr),) +EXTRA_CFLAGS+= -I$(PKG_BUILD_DIR)/exports +NSS_CLIENTS_MAKE_OPTS+=ipsecmgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ipsecmgr-klips),) +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-ecm +NSS_CLIENTS_MAKE_OPTS+=ipsecmgr-klips=m +# Enable netdev based binding from L2TP to IPsec if KLIPS is enabled +EXTRA_CFLAGS+= -DNSS_L2TP_IPSEC_BIND_BY_NETDEV +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ipsecmgr-xfrm),) +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-ecm +NSS_CLIENTS_MAKE_OPTS+=ipsecmgr-xfrm=m +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-bridge-mgr),) +NSS_CLIENTS_MAKE_OPTS+=bridge-mgr=y +#enable OVS bridge if ovsmgr is enabled +ifneq ($(CONFIG_PACKAGE_kmod-qca-ovsmgr),) +NSS_CLIENTS_MAKE_OPTS+= NSS_BRIDGE_MGR_OVS_ENABLE=y +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-ovsmgr +endif +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vlan-mgr),) +NSS_CLIENTS_MAKE_OPTS+=vlan-mgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-lag-mgr),) +NSS_CLIENTS_MAKE_OPTS+=lag-mgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-gre),) +EXTRA_CFLAGS+= -I$(PKG_BUILD_DIR)/exports +NSS_CLIENTS_MAKE_OPTS+=gre=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pppoe),) +NSS_CLIENTS_MAKE_OPTS+=pppoe=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-netlink),) +NSS_CLIENTS_MAKE_OPTS+=netlink=y + +ifdef CONFIG_NSS_DRV_C2C_ENABLE +NSS_CLIENTS_MAKE_OPTS+=CONFIG_NSS_NLC2C=y +endif + +ifdef CONFIG_NSS_DRV_UDP_ST_ENABLE +NSS_CLIENTS_MAKE_OPTS+=CONFIG_NSS_NLUDP_ST=y +endif + +ifdef CONFIG_NSS_DRV_QRFS_ENABLE +NSS_CLIENTS_MAKE_OPTS+=CONFIG_NSS_NLQRFS=y +endif + +ifdef CONFIG_NSS_DRV_GRE_REDIR_ENABLE +NSS_CLIENTS_MAKE_OPTS+=CONFIG_NSS_NLGRE_REDIR_FAMILY=y +endif + +ifdef CONFIG_NSS_DRV_IPV4_REASM_ENABLE +NSS_CLIENTS_MAKE_OPTS+=CONFIG_NSS_NLIPV4_REASM=y +endif + +ifdef CONFIG_NSS_DRV_IPV6_REASM_ENABLE +NSS_CLIENTS_MAKE_OPTS+=CONFIG_NSS_NLIPV6_REASM=y +endif + +ifdef CONFIG_NSS_DRV_LSO_RX_ENABLE +NSS_CLIENTS_MAKE_OPTS+=CONFIG_NSS_NLLSO_RX=y +endif + +ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),256) +EXTRA_CFLAGS+= -DNSS_NETLINK_UDP_ST_NO_RMNET_SUPPORT +else ifeq ($(CONFIG_LOWMEM_FLASH),y) +EXTRA_CFLAGS+= -DNSS_NETLINK_UDP_ST_NO_RMNET_SUPPORT +endif + +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ovpn-mgr),) +NSS_CLIENTS_MAKE_OPTS+=ovpn-mgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ovpn-link),) +NSS_CLIENTS_MAKE_OPTS+=ovpn-link=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pvxlanmgr),) +# The memset() call in nss_pvxlanmgr_get_tunnel_stats +# triggers a compilation error with GCC 13, most likely +# it is a false positive, disable the warning for now. +EXTRA_CFLAGS+= -Wno-stringop-overread +NSS_CLIENTS_MAKE_OPTS+=pvxlanmgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-eogremgr),) +NSS_CLIENTS_MAKE_OPTS+=eogremgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-clmapmgr),) +NSS_CLIENTS_MAKE_OPTS+=clmapmgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vxlanmgr),) +NSS_CLIENTS_MAKE_OPTS+=vxlanmgr=y +EXTRA_CFLAGS += -DNSS_VXLAN_ENABLED +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-match),) +NSS_CLIENTS_MAKE_OPTS+=match=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-mirror),) +NSS_CLIENTS_MAKE_OPTS+=mirror=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-mscs),) +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-wifi \ + -I$(STAGING_DIR)/usr/include/qca-nss-ecm +NSS_CLIENTS_MAKE_OPTS+=mscs=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-wifi-meshmgr),) +NSS_CLIENTS_MAKE_OPTS+=wifi-meshmgr=y +endif + +EXTRA_CFLAGS+= \ + -Wno-missing-prototypes \ + -Wno-missing-declarations \ + -Wno-empty-body + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" $(strip $(NSS_CLIENTS_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS) -include $(PKG_BUILD_DIR)/compat.h" \ + DTLSMGR_DIR="$(DTLSMGR_DIR)" \ + IPSECMGR_DIR="$(IPSECMGR_DIR)" \ + SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv-profile)) +$(eval $(call KernelPackage,qca-nss-drv-capwapmgr)) +$(eval $(call KernelPackage,qca-nss-drv-tun6rd)) +$(eval $(call KernelPackage,qca-nss-drv-dtlsmgr)) +$(eval $(call KernelPackage,qca-nss-drv-l2tpv2)) +$(eval $(call KernelPackage,qca-nss-drv-pptp)) +$(eval $(call KernelPackage,qca-nss-drv-pppoe)) +$(eval $(call KernelPackage,qca-nss-drv-map-t)) +$(eval $(call KernelPackage,qca-nss-drv-tunipip6)) +$(eval $(call KernelPackage,qca-nss-drv-qdisc)) +$(eval $(call KernelPackage,qca-nss-drv-igs)) +$(eval $(call KernelPackage,qca-nss-drv-netlink)) +$(eval $(call KernelPackage,qca-nss-drv-ipsecmgr)) +$(eval $(call KernelPackage,qca-nss-drv-ipsecmgr-klips)) +$(eval $(call KernelPackage,qca-nss-drv-ipsecmgr-xfrm)) +$(eval $(call KernelPackage,qca-nss-drv-bridge-mgr)) +$(eval $(call KernelPackage,qca-nss-drv-vlan-mgr)) +$(eval $(call KernelPackage,qca-nss-drv-lag-mgr)) +$(eval $(call KernelPackage,qca-nss-drv-gre)) +# $(eval $(call KernelPackage,qca-nss-drv-ovpn-mgr)) +# $(eval $(call KernelPackage,qca-nss-drv-ovpn-link)) +$(eval $(call KernelPackage,qca-nss-drv-pvxlanmgr)) +$(eval $(call KernelPackage,qca-nss-drv-eogremgr)) +$(eval $(call KernelPackage,qca-nss-drv-clmapmgr)) +$(eval $(call KernelPackage,qca-nss-drv-vxlanmgr)) +$(eval $(call KernelPackage,qca-nss-drv-match)) +$(eval $(call KernelPackage,qca-nss-drv-tlsmgr)) +$(eval $(call KernelPackage,qca-nss-drv-mirror)) +$(eval $(call KernelPackage,qca-nss-drv-mscs)) +$(eval $(call KernelPackage,qca-nss-drv-wifi-meshmgr)) diff --git a/qca-nss-clients/files/qca-nss-ipsec b/qca-nss-clients/files/qca-nss-ipsec new file mode 100755 index 0000000..21eea7c --- /dev/null +++ b/qca-nss-clients/files/qca-nss-ipsec @@ -0,0 +1,231 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2018-2019, 2021 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +NSS_IPSEC_LOG_FILE=/tmp/.nss_ipsec_log +NSS_IPSEC_LOG_STR_ECM="ECM_Loaded" +NSS_IPSEC_OL_FILE=/tmp/qca_nss_ipsec_ol + +ecm_load () { + if [ ! -d /sys/module/ecm ]; then + /etc/init.d/qca-nss-ecm start + if [ -d /sys/module/ecm ]; then + echo ${NSS_IPSEC_LOG_STR_ECM} >> ${NSS_IPSEC_LOG_FILE} + fi + fi +} + +ecm_unload () { + if [ -f /tmp/.nss_ipsec_log ]; then + str=`grep ${NSS_IPSEC_LOG_STR_ECM} ${NSS_IPSEC_LOG_FILE}` + if [[ $str == ${NSS_IPSEC_LOG_STR_ECM} ]]; then + /etc/init.d/qca-nss-ecm stop + `sed 's/${NSS_IPSEC_LOG_STR_ECM}/ /g' $NSS_IPSEC_LOG_FILE > $NSS_IPSEC_LOG_FILE` + fi + fi +} + +ecm_disable() { + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +kernel_version_check_5_4() { + major_ver=$(uname -r | awk -F '.' '{print $1}') + minor_ver=$(uname -r | awk -F '.' '{print $2}') + if [ $major_ver -lt 5 ] || ([ $major_ver -eq 5 ] && [ $minor_ver -lt 4 ] ); then + return 1 + else + return 0 + fi +} + +kernel_version_check_5_15() { + major_ver=$(uname -r | awk -F '.' '{print $1}') + minor_ver=$(uname -r | awk -F '.' '{print $2}') + if [ $major_ver -lt 5 ] || ([ $major_ver -eq 5 ] && [ $minor_ver -lt 15 ] ); then + return 1 + else + return 0 + fi +} + +start_klips() { + if kernel_version_check_5_4; then + echo "Kernel 5.4 doesn't support klips stack." + return $? + fi + + if kernel_version_check_5_15; then + echo "Kernel 5.15 doesn't support klips stack." + return $? + fi + + touch $NSS_IPSEC_OL_FILE + ecm_load + + local kernel_version=$(uname -r) + + insmod /lib/modules/${kernel_version}/qca-nss-ipsec-klips.ko + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + rm $NSS_IPSEC_OL_FILE + return + fi + + /etc/init.d/ipsec start + sleep 2 + ipsec eroute + + ecm_enable +} + +stop_klips() { + if kernel_version_check_5_4; then + echo "Kernel 5.4 doesn't support klips stack." + return $? + fi + + if kernel_version_check_5_15; then + echo "Kernel 5.15 doesn't support klips stack." + return $? + fi + + ecm_disable + + /etc/init.d/ipsec stop + rmmod qca-nss-ipsec-klips + rm $NSS_IPSEC_OL_FILE + + ecm_unload +} + +start_xfrm() { + touch $NSS_IPSEC_OL_FILE + ecm_load + + local kernel_version=$(uname -r) + + # load all NETKEY modules first. + for mod in xfrm_ipcomp ipcomp xfrm6_tunnel ipcomp6 xfrm6_mode_tunnel xfrm6_mode_beet xfrm6_mode_ro \ + xfrm6_mode_transport xfrm4_mode_transport xfrm4_mode_tunnel \ + xfrm4_tunnel xfrm4_mode_beet esp4 esp6 ah4 ah6 af_key + do + insmod $mod 2> /dev/null + done + + # Now load the xfrm plugin + insmod /lib/modules/${kernel_version}/qca-nss-ipsec-xfrm.ko + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + rm $NSS_IPSEC_OL_FILE + return + fi + + /etc/init.d/ipsec start + sleep 2 + + ecm_enable +} + +stop_xfrm() { + ecm_disable + + #Shutdown Pluto first. Then only plugin can be removed. + plutopid=/var/run/pluto/pluto.pid + if [ -f $plutopid ]; then + pid=`cat $plutopid` + if [ ! -z "$pid" ]; then + ipsec whack --shutdown | grep -v "002"; + if [ -s $plutopid ]; then + echo "Attempt to shut Pluto down failed! Trying kill:" + kill $pid; + sleep 5; + fi + fi + rm -rf $plutopid + fi + ip xfrm state flush; + ip xfrm policy flush; + sleep 2 + + #Now we can remove the plugin + retries=5 + while [ -d /sys/module/qca_nss_ipsec_xfrm ] + do + rmmod qca-nss-ipsec-xfrm + if [ "$?" -eq 0 ]; then + rm $NSS_IPSEC_OL_FILE + break + fi + + if [ ${retries} -eq 0 ]; then + echo "Failed to unload qca-nss-ipsec-xfrm plugin!" + exit + fi + + echo "XFRM plugin unload failed; retrying ${retries} times" + sleep 1 + retries=`expr ${retries} - 1` + done + + /etc/init.d/ipsec stop + ecm_unload +} + +start() { + local protostack=`uci -q get ipsec.setup.protostack` + if [ "$protostack" = "klips" ]; then + start_klips + return $? + fi + + start_xfrm + return $? +} + +stop() { + local protostack=`uci -q get ipsec.setup.protostack` + if [ "$protostack" = "klips" ]; then + stop_klips + return $? + fi + + stop_xfrm + return $? +} + +restart() { + stop + start +} diff --git a/qca-nss-clients/files/qca-nss-mirred.init b/qca-nss-clients/files/qca-nss-mirred.init new file mode 100644 index 0000000..259aaa0 --- /dev/null +++ b/qca-nss-clients/files/qca-nss-mirred.init @@ -0,0 +1,28 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +start() { + insmod act_nssmirred.ko +} + +stop() { + rmmod act_nssmirred.ko +} + +restart() { + stop + start +} diff --git a/qca-nss-clients/files/qca-nss-netlink.init b/qca-nss-clients/files/qca-nss-netlink.init new file mode 100644 index 0000000..8d38ad3 --- /dev/null +++ b/qca-nss-clients/files/qca-nss-netlink.init @@ -0,0 +1,31 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2023, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +start() { + modprobe qca-nss-netlink + + echo 2048 > /proc/sys/dev/nss/n2hcfg/n2h_queue_limit_core0 + echo 2048 > /proc/sys/dev/nss/n2hcfg/n2h_queue_limit_core1 +} + +stop() { + rmmod qca-nss-netlink.ko +} + +restart() { + stop + start +} diff --git a/qca-nss-clients/files/qca-nss-ovpn.init b/qca-nss-clients/files/qca-nss-ovpn.init new file mode 100644 index 0000000..2a235fd --- /dev/null +++ b/qca-nss-clients/files/qca-nss-ovpn.init @@ -0,0 +1,104 @@ +#!/bin/sh /etc/rc.common +# shellcheck disable=3043,2034,2166 +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +# START=26 +USE_PROCD=1 + +ecm_disable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +check_enabled() { + local enabled + total_enabled=${total_enabled:-0} + config_get_bool enabled "$1" enabled 0 + [ "$enabled" = "1" ] && total_enabled=$((total_enabled + 1)) +} + +mod_action() { + local action="$1" + + if [ "$action" != "load" -a "$action" != "unload" ]; then + echo "Invalid action: $action, must be load or unload" + return + fi + + shift + local modules="$*" + + [ -z "$modules" ] && { + echo "No modules specified" + return + } + + for i in $modules; do + [ -n "$i" ] && { + if [ "$action" = "unload" ]; then + grep -q -w "$i" /proc/modules && { + rmmod "$i" || echo "Failed to unload $i" + } + else + modprobe "$i" 2> /dev/null || { + echo "Failed to load $i" + return + } + fi + } + done +} + +start_service() { + config_load openvpn + config_foreach check_enabled openvpn + + [ "$total_enabled" = "0" ] && return + + ecm_disable + + /etc/init.d/openvpn stop 2> /dev/null + + mod_action unload qca_nss_ovpn_link qca_nss_ovpn_mgr + mod_action load qca_nss_ovpn_link qca_nss_ovpn_mgr ovpn_dco_v2 + + ecm_enable + + /etc/init.d/openvpn start 2> /dev/null +} + +stop_service() { + ecm_disable + + /etc/init.d/openvpn stop 2> /dev/null + mod_action unload qca_nss_ovpn_link qca_nss_ovpn_mgr + + ecm_enable +} diff --git a/qca-nss-clients/patches-11.4/0001-kernel-5.15-support-qdisc.patch b/qca-nss-clients/patches-11.4/0001-kernel-5.15-support-qdisc.patch new file mode 100644 index 0000000..4426466 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0001-kernel-5.15-support-qdisc.patch @@ -0,0 +1,153 @@ +--- a/nss_qdisc/igs/nss_mirred.c ++++ b/nss_qdisc/igs/nss_mirred.c +@@ -82,20 +82,24 @@ static const struct nla_policy nss_mirre + * nss_mirred_init() + * Initialize the nss mirred action. + */ +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) + static int nss_mirred_init(struct net *net, struct nlattr *nla, +- struct nlattr *est, struct tc_action *tc_act, int ovr, +- int bind) ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) ++ struct nlattr *est, struct tc_action *tc_act, int ovr, ++ int bind) ++{ ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) ++ struct nlattr *est, struct tc_action **tc_act, int ovr, ++ int bind, bool rtnl_held, struct tcf_proto *tp, ++ u32 flags, struct netlink_ext_ack *extack) + { + #else +-static int nss_mirred_init(struct net *net, struct nlattr *nla, +- struct nlattr *est, struct tc_action **tc_act, int ovr, +- int bind, bool rtnl_held, struct tcf_proto *tp, +- struct netlink_ext_ack *extack) ++ struct nlattr *est, struct tc_action **tc_act, ++ struct tcf_proto *tp, u32 flags, struct netlink_ext_ack *extack) + { ++ bool bind = flags & TCA_ACT_FLAGS_BIND; ++#endif + struct tc_action_net *tn = net_generic(net, nss_mirred_net_id); + u32 index; +-#endif + struct nlattr *arr[TC_NSS_MIRRED_MAX + 1]; + struct tc_nss_mirred *parm; + struct nss_mirred_tcf *act; +@@ -239,8 +243,13 @@ static int nss_mirred_init(struct net *n + } + + if (!ret) { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)) + ret = tcf_idr_create(tn, index, est, tc_act, &nss_mirred_act_ops, + bind, true); ++#else ++ ret = tcf_idr_create(tn, index, est, tc_act, &nss_mirred_act_ops, ++ bind, true, 0); ++#endif + if (ret) { + tcf_idr_cleanup(tn, index); + return ret; +--- a/nss_qdisc/nss_bf.c ++++ b/nss_qdisc/nss_bf.c +@@ -70,7 +70,7 @@ static inline struct nss_bf_class_data * + */ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0)) + static int nss_bf_change_class(struct Qdisc *sch, u32 classid, u32 parentid, +- struct nlattr **tca, unsigned long *arg) ++ struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack) + { + struct netlink_ext_ack *extack = NULL; + #else +@@ -296,7 +296,11 @@ static void nss_bf_destroy_class(struct + * nss_bf_delete_class() + * Detaches a class from operation, but does not destroy it. + */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) ++static int nss_bf_delete_class(struct Qdisc *sch, unsigned long arg, struct netlink_ext_ack *extack) ++#else + static int nss_bf_delete_class(struct Qdisc *sch, unsigned long arg) ++#endif + { + struct nss_bf_sched_data *q = qdisc_priv(sch); + struct nss_bf_class_data *cl = (struct nss_bf_class_data *)arg; +--- a/nss_qdisc/nss_htb.c ++++ b/nss_qdisc/nss_htb.c +@@ -278,7 +278,7 @@ static int nss_htb_ppe_change_class(stru + */ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0)) + static int nss_htb_change_class(struct Qdisc *sch, u32 classid, u32 parentid, +- struct nlattr **tca, unsigned long *arg) ++ struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack) + { + struct netlink_ext_ack *extack = NULL; + #else +@@ -522,7 +522,11 @@ static void nss_htb_destroy_class(struct + * nss_htb_delete_class() + * Detaches a class from operation, but does not destroy it. + */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) ++static int nss_htb_delete_class(struct Qdisc *sch, unsigned long arg, struct netlink_ext_ack *extack) ++#else + static int nss_htb_delete_class(struct Qdisc *sch, unsigned long arg) ++#endif + { + struct nss_htb_sched_data *q = qdisc_priv(sch); + struct nss_htb_class_data *cl = (struct nss_htb_class_data *)arg; +--- a/nss_qdisc/nss_qdisc.c ++++ b/nss_qdisc/nss_qdisc.c +@@ -1144,15 +1144,16 @@ unsigned int nss_qdisc_drop(struct Qdisc + { + struct nss_qdisc *nq = qdisc_priv(sch); + unsigned int ret; ++ struct sk_buff *to_free = qdisc_peek_head(sch); + + if (!nq->is_virtual) { +- ret = __qdisc_queue_drop_head(sch, &sch->q); ++ ret = __qdisc_queue_drop_head(sch, &sch->q, &to_free); + } else { + spin_lock_bh(&nq->bounce_protection_lock); + /* + * This function is safe to call within locks + */ +- ret = __qdisc_queue_drop_head(sch, &sch->q); ++ ret = __qdisc_queue_drop_head(sch, &sch->q, &to_free); + spin_unlock_bh(&nq->bounce_protection_lock); + } + +@@ -1206,10 +1207,10 @@ static bool nss_qdisc_iterate_fl(struct + return 0; + } + +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) +- status = tc_classify(skb, tcf, &res, false); +-#else ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) + status = tcf_classify(skb, tcf, &res, false); ++#else ++ status = tcf_classify(skb, NULL, tcf, &res, false); + #endif + if ((status == TC_ACT_STOLEN) || (status == TC_ACT_QUEUED)) { + return 1; +--- a/nss_qdisc/nss_wrr.c ++++ b/nss_qdisc/nss_wrr.c +@@ -230,7 +230,7 @@ static int nss_wrr_ppe_change_class(stru + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0)) + static int nss_wrr_change_class(struct Qdisc *sch, u32 classid, u32 parentid, +- struct nlattr **tca, unsigned long *arg) ++ struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack) + { + struct netlink_ext_ack *extack = NULL; + #else +@@ -406,7 +406,11 @@ failure: + return -EINVAL; + } + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) ++static int nss_wrr_delete_class(struct Qdisc *sch, unsigned long arg, struct netlink_ext_ack *extack) ++#else + static int nss_wrr_delete_class(struct Qdisc *sch, unsigned long arg) ++#endif + { + struct nss_wrr_sched_data *q = qdisc_priv(sch); + struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)arg; diff --git a/qca-nss-clients/patches-11.4/0002-kernel-5.4-support-gre.patch b/qca-nss-clients/patches-11.4/0002-kernel-5.4-support-gre.patch new file mode 100644 index 0000000..7ed66bd --- /dev/null +++ b/qca-nss-clients/patches-11.4/0002-kernel-5.4-support-gre.patch @@ -0,0 +1,31 @@ +--- a/gre/nss_connmgr_gre_v6.c ++++ b/gre/nss_connmgr_gre_v6.c +@@ -95,7 +95,8 @@ static int nss_connmgr_gre_v6_get_mac_ad + /* + * Find src MAC address + */ +- local_dev = (struct net_device *)ipv6_dev_find(&init_net, &src_addr, 1); ++ local_dev = NULL; ++ local_dev = (struct net_device *)ipv6_dev_find(&init_net, &src_addr, local_dev); + if (!local_dev) { + nss_connmgr_gre_warning("Unable to find local dev for %pI6", src_ip); + return GRE_ERR_NO_LOCAL_NETDEV; +--- a/gre/test/nss_connmgr_gre_test.c ++++ b/gre/test/nss_connmgr_gre_test.c +@@ -229,10 +229,12 @@ static int nss_connmgr_gre_test_open_pro + /* + * Proc ops + */ +-static const struct file_operations nss_connmgr_gre_test_proc_ops = { +- .open = nss_connmgr_gre_test_open_proc, +- .write = nss_connmgr_gre_test_write_proc, +- .read = seq_read, ++static const struct proc_ops nss_connmgr_gre_test_proc_ops = { ++ .proc_open = nss_connmgr_gre_test_open_proc, ++ .proc_read = seq_read, ++ .proc_lseek = seq_lseek, ++ .proc_release = single_release, ++ .proc_write = nss_connmgr_gre_test_write_proc, + }; + + /* diff --git a/qca-nss-clients/patches-11.4/0003-kernel-5.4-support-ipsec.patch b/qca-nss-clients/patches-11.4/0003-kernel-5.4-support-ipsec.patch new file mode 100644 index 0000000..de43b4d --- /dev/null +++ b/qca-nss-clients/patches-11.4/0003-kernel-5.4-support-ipsec.patch @@ -0,0 +1,29 @@ +--- a/ipsecmgr/v1.0/nss_ipsecmgr.c ++++ b/ipsecmgr/v1.0/nss_ipsecmgr.c +@@ -377,7 +377,7 @@ free: + * nss_ipsecmgr_tunnel_stats() + * get tunnel statistics + */ +-static struct rtnl_link_stats64 *nss_ipsecmgr_tunnel_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) ++void nss_ipsecmgr_tunnel_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) + { + struct nss_ipsecmgr_priv *priv = netdev_priv(dev); + +@@ -389,8 +389,6 @@ static struct rtnl_link_stats64 *nss_ips + read_lock_bh(&ipsecmgr_ctx->lock); + memcpy(stats, &priv->stats, sizeof(struct rtnl_link_stats64)); + read_unlock_bh(&ipsecmgr_ctx->lock); +- +- return stats; + } + + /* +@@ -442,7 +440,7 @@ static void nss_ipsecmgr_tunnel_setup(st + dev->header_ops = NULL; + dev->netdev_ops = &nss_ipsecmgr_tunnel_ops; + +- dev->destructor = nss_ipsecmgr_tunnel_free; ++ dev->priv_destructor = nss_ipsecmgr_tunnel_free; + + /* + * get the MAC address from the ethernet device diff --git a/qca-nss-clients/patches-11.4/0004-kernel-5.4-support-dtls.patch b/qca-nss-clients/patches-11.4/0004-kernel-5.4-support-dtls.patch new file mode 100644 index 0000000..ae9c914 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0004-kernel-5.4-support-dtls.patch @@ -0,0 +1,11 @@ +--- a/dtls/v1.0/nss_connmgr_dtls_netdev.c ++++ b/dtls/v1.0/nss_connmgr_dtls_netdev.c +@@ -160,7 +160,7 @@ static void nss_dtlsmgr_dev_setup(struct + dev->ethtool_ops = NULL; + dev->header_ops = NULL; + dev->netdev_ops = &nss_dtlsmgr_session_ops; +- dev->destructor = NULL; ++ dev->priv_destructor = NULL; + + memcpy(dev->dev_addr, "\xaa\xbb\xcc\xdd\xee\xff", dev->addr_len); + memset(dev->broadcast, 0xff, dev->addr_len); diff --git a/qca-nss-clients/patches-11.4/0005-vlanmgr-fix-compile-error.patch b/qca-nss-clients/patches-11.4/0005-vlanmgr-fix-compile-error.patch new file mode 100644 index 0000000..8cdc4ad --- /dev/null +++ b/qca-nss-clients/patches-11.4/0005-vlanmgr-fix-compile-error.patch @@ -0,0 +1,59 @@ +--- a/vlan/nss_vlan_mgr.c ++++ b/vlan/nss_vlan_mgr.c +@@ -821,8 +821,10 @@ static struct nss_vlan_pvt *nss_vlan_mgr + */ + static void nss_vlan_mgr_instance_free(struct nss_vlan_pvt *v) + { ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT + int32_t i; + int ret = 0; ++#endif + + spin_lock(&vlan_mgr_ctx.lock); + BUG_ON(--v->refs); +@@ -980,8 +982,11 @@ static int nss_vlan_mgr_register_event(s + int ret; + #endif + uint32_t vlan_tag; ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT + struct net_device *slave; +- int32_t port, port_if; ++ int32_t port; ++#endif ++ int32_t port_if; + struct vlan_dev_priv *vlan; + struct net_device *real_dev; + bool is_bond_master = false; +@@ -1355,8 +1360,10 @@ return_with_error: + int nss_vlan_mgr_join_bridge(struct net_device *dev, uint32_t bridge_vsi) + { + struct nss_vlan_pvt *v = nss_vlan_mgr_instance_find_and_ref(dev); ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT + struct net_device *real_dev; + int ret; ++#endif + + if (!v) + return 0; +@@ -1416,8 +1423,10 @@ EXPORT_SYMBOL(nss_vlan_mgr_join_bridge); + int nss_vlan_mgr_leave_bridge(struct net_device *dev, uint32_t bridge_vsi) + { + struct nss_vlan_pvt *v = nss_vlan_mgr_instance_find_and_ref(dev); ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT + struct net_device *real_dev; + int ret; ++#endif + + if (!v) + return 0; +--- a/vlan/Makefile ++++ b/vlan/Makefile +@@ -8,7 +8,7 @@ ifeq ($(SoC),$(filter $(SoC),ipq807x ipq + ccflags-y += -DNSS_VLAN_MGR_PPE_SUPPORT + endif + +-ccflags-y += -DNSS_VLAN_MGR_DEBUG_LEVEL=0 ++ccflags-y += -DNSS_VLAN_MGR_DEBUG_LEVEL=4 + ccflags-y += -Wall -Werror + + ifneq (,$(filter $(CONFIG_BONDING),y m)) diff --git a/qca-nss-clients/patches-11.4/0006-match-fix-compile-error.patch b/qca-nss-clients/patches-11.4/0006-match-fix-compile-error.patch new file mode 100644 index 0000000..ad3ad0b --- /dev/null +++ b/qca-nss-clients/patches-11.4/0006-match-fix-compile-error.patch @@ -0,0 +1,25 @@ +--- a/match/nss_match_priv.h ++++ b/match/nss_match_priv.h +@@ -29,19 +29,19 @@ + /* + * Statically compile messages at different levels + */ +-#if (NSS_match_DEBUG_LEVEL < 2) ++#if (NSS_MATCH_DEBUG_LEVEL < 2) + #define nss_match_warn(s, ...) + #else + #define nss_match_warn(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) + #endif + +-#if (NSS_match_DEBUG_LEVEL < 3) ++#if (NSS_MATCH_DEBUG_LEVEL < 3) + #define nss_match_info(s, ...) + #else + #define nss_match_info(s, ...) pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) + #endif + +-#if (NSS_match_DEBUG_LEVEL < 4) ++#if (NSS_MATCH_DEBUG_LEVEL < 4) + #define nss_match_trace(s, ...) + #else + #define nss_match_trace(s, ...) pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) diff --git a/qca-nss-clients/patches-11.4/0007-bridge-fix-compile-error.patch b/qca-nss-clients/patches-11.4/0007-bridge-fix-compile-error.patch new file mode 100644 index 0000000..1f439e4 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0007-bridge-fix-compile-error.patch @@ -0,0 +1,29 @@ +--- a/bridge/nss_bridge_mgr.c ++++ b/bridge/nss_bridge_mgr.c +@@ -1062,8 +1062,10 @@ int nss_bridge_mgr_register_br(struct ne + */ + b_pvt->ifnum = ifnum; + b_pvt->mtu = dev->mtu; ++#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT) + b_pvt->wan_if_num = -1; + b_pvt->wan_if_enabled = false; ++#endif + ether_addr_copy(b_pvt->dev_addr, dev->dev_addr); + spin_lock(&br_mgr_ctx.lock); + list_add(&b_pvt->list, &br_mgr_ctx.list); +@@ -1125,6 +1127,7 @@ static int nss_bridge_mgr_bond_slave_cha + return NOTIFY_DONE; + } + ++#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT) + /* + * Add or remove the slave based based on linking event + */ +@@ -1139,6 +1142,7 @@ static int nss_bridge_mgr_bond_slave_cha + cu_info->upper_dev->name, master->name); + } + } ++#endif + + return NOTIFY_DONE; + } diff --git a/qca-nss-clients/patches-11.4/0008-profiler-fix-compile-error.patch b/qca-nss-clients/patches-11.4/0008-profiler-fix-compile-error.patch new file mode 100644 index 0000000..8b6d92c --- /dev/null +++ b/qca-nss-clients/patches-11.4/0008-profiler-fix-compile-error.patch @@ -0,0 +1,61 @@ +--- a/profiler/profile.c ++++ b/profiler/profile.c +@@ -31,6 +31,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -937,12 +938,26 @@ static ssize_t debug_if(struct file *fil + return count; + } + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0) ++#define HAVE_PROC_OPS ++#endif ++ ++#ifdef HAVE_PROC_OPS ++static const struct proc_ops profile_fops = { ++ .proc_open = profile_open, ++ .proc_read = profile_read, ++ .proc_lseek = seq_lseek, ++ .proc_release = profile_release, ++ .proc_write = debug_if, ++}; ++#else + static const struct file_operations profile_fops = { + .open = profile_open, + .read = profile_read, + .release = profile_release, + .write = debug_if, + }; ++#endif + + /* + * showing sample status on Linux console +@@ -971,6 +986,15 @@ static ssize_t profile_rate_write(struct + return 0; + } + ++#ifdef HAVE_PROC_OPS ++static const struct proc_ops profile_rate_fops = { ++ .proc_open = profile_rate_open, ++ .proc_read = seq_read, ++ .proc_lseek = seq_lseek, ++ .proc_release = single_release, ++ .proc_write = profile_rate_write, ++}; ++#else + static const struct file_operations profile_rate_fops = { + .open = profile_rate_open, + .read = seq_read, +@@ -978,6 +1002,7 @@ static const struct file_operations prof + .release = single_release, + .write = profile_rate_write, + }; ++#endif + + /* + * hexdump diff --git a/qca-nss-clients/patches-11.4/0009-gre-fix-compile-error.patch b/qca-nss-clients/patches-11.4/0009-gre-fix-compile-error.patch new file mode 100644 index 0000000..e833327 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0009-gre-fix-compile-error.patch @@ -0,0 +1,17 @@ +--- a/gre/nss_connmgr_gre_v4.c ++++ b/gre/nss_connmgr_gre_v4.c +@@ -172,14 +172,6 @@ int nss_connmgr_gre_v4_set_config(struct + } + } + +- /* +- * IP address validate +- */ +- if ((cfg->src_ip == 0) || (cfg->dest_ip == 0)) { +- nss_connmgr_gre_warning("Source ip/Destination IP is invalid"); +- return GRE_ERR_INVALID_IP; +- } +- + memset(t, 0, sizeof(struct ip_tunnel)); + + priv->pad_len = (cfg->add_padding) ? GRE_HDR_PAD_LEN : 0; diff --git a/qca-nss-clients/patches-11.4/0010-fix-portifmgr.patch b/qca-nss-clients/patches-11.4/0010-fix-portifmgr.patch new file mode 100644 index 0000000..343f17b --- /dev/null +++ b/qca-nss-clients/patches-11.4/0010-fix-portifmgr.patch @@ -0,0 +1,35 @@ +--- a/portifmgr/nss_portifmgr.c ++++ b/portifmgr/nss_portifmgr.c +@@ -187,16 +187,20 @@ drop: + } + + /* +- * nss_portifmgr_get_stats() ++ * nss_portifmgr_get_stats64() + * Netdev get stats function to get port stats + */ +-static struct rtnl_link_stats64 *nss_portifmgr_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) ++/* ++ * nss_nlgre_redir_cmn_dev_stats64 ++ * Report packet statistics to linux ++ */ ++static void nss_portifmgr_get_stats64(struct net_device *dev, ++ struct rtnl_link_stats64 *stats) + { + struct nss_portifmgr_priv *priv = (struct nss_portifmgr_priv *)netdev_priv(dev); + BUG_ON(priv == NULL); + + nss_portid_get_stats(priv->if_num, stats); +- return stats; + } + + /* +@@ -225,7 +229,7 @@ static const struct net_device_ops nss_p + .ndo_start_xmit = nss_portifmgr_start_xmit, + .ndo_set_mac_address = eth_mac_addr, + .ndo_change_mtu = nss_portifmgr_change_mtu, +- .ndo_get_stats64 = nss_portifmgr_get_stats, ++ .ndo_get_stats64 = nss_portifmgr_get_stats64, + }; + + /* diff --git a/qca-nss-clients/patches-11.4/0011-dtlsmgr-fix-SHA-header-include-in-5.15.patch b/qca-nss-clients/patches-11.4/0011-dtlsmgr-fix-SHA-header-include-in-5.15.patch new file mode 100644 index 0000000..a095a53 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0011-dtlsmgr-fix-SHA-header-include-in-5.15.patch @@ -0,0 +1,48 @@ +--- a/dtls/v2.0/nss_dtlsmgr.c ++++ b/dtls/v2.0/nss_dtlsmgr.c +@@ -38,7 +38,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + #include + #include + +--- a/dtls/v2.0/nss_dtlsmgr_ctx.c ++++ b/dtls/v2.0/nss_dtlsmgr_ctx.c +@@ -40,7 +40,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + #include + #include + +--- a/dtls/v2.0/nss_dtlsmgr_ctx_dev.c ++++ b/dtls/v2.0/nss_dtlsmgr_ctx_dev.c +@@ -36,7 +36,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + + #include + #include diff --git a/qca-nss-clients/patches-11.4/0012-dtlsmgr-fix-debug-print-in-5.15.patch b/qca-nss-clients/patches-11.4/0012-dtlsmgr-fix-debug-print-in-5.15.patch new file mode 100644 index 0000000..89936db --- /dev/null +++ b/qca-nss-clients/patches-11.4/0012-dtlsmgr-fix-debug-print-in-5.15.patch @@ -0,0 +1,36 @@ +--- a/dtls/v2.0/nss_dtlsmgr_private.h ++++ b/dtls/v2.0/nss_dtlsmgr_private.h +@@ -36,9 +36,9 @@ + /* + * Compile messages for dynamic enable/disable + */ +-#define nss_dtlsmgr_warn(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) +-#define nss_dtlsmgr_info(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) +-#define nss_dtlsmgr_trace(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) ++#define nss_dtlsmgr_warn(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); ++#define nss_dtlsmgr_info(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); ++#define nss_dtlsmgr_trace(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); + #else + + /* +@@ -46,17 +46,17 @@ + */ + #define nss_dtlsmgr_warn(s, ...) { \ + if (NSS_DTLSMGR_DEBUG_LEVEL > NSS_DTLSMGR_DEBUG_LEVEL_ERROR) \ +- pr_warn("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) \ ++ pr_warn("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); \ + } + + #define nss_dtlsmgr_info(s, ...) { \ + if (NSS_DTLSMGR_DEBUG_LEVEL > NSS_DTLSMGR_DEBUG_LEVEL_WARN) \ +- pr_notice("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) \ ++ pr_notice("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); \ + } + + #define nss_dtlsmgr_trace(s, ...) { \ + if (NSS_DTLSMGR_DEBUG_LEVEL > NSS_DTLSMGR_DEBUG_LEVEL_INFO) \ +- pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) \ ++ pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); \ + } + + #endif /* CONFIG_DYNAMIC_DEBUG */ diff --git a/qca-nss-clients/patches-11.4/0013-tlsmgr-fix-SHA-header-include-in-5.15.patch b/qca-nss-clients/patches-11.4/0013-tlsmgr-fix-SHA-header-include-in-5.15.patch new file mode 100644 index 0000000..f3cee73 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0013-tlsmgr-fix-SHA-header-include-in-5.15.patch @@ -0,0 +1,32 @@ +--- a/tls/nss_tlsmgr_crypto.c ++++ b/tls/nss_tlsmgr_crypto.c +@@ -41,7 +41,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + #include + #include + #include +--- a/tls/nss_tlsmgr_tun.c ++++ b/tls/nss_tlsmgr_tun.c +@@ -35,7 +35,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + + #include + #include diff --git a/qca-nss-clients/patches-11.4/0014-ovpnmgr-fix-SHA-header-include-in-5.15.patch b/qca-nss-clients/patches-11.4/0014-ovpnmgr-fix-SHA-header-include-in-5.15.patch new file mode 100644 index 0000000..0b8cd17 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0014-ovpnmgr-fix-SHA-header-include-in-5.15.patch @@ -0,0 +1,32 @@ +--- a/openvpn/src/nss_ovpnmgr_crypto.c ++++ b/openvpn/src/nss_ovpnmgr_crypto.c +@@ -28,7 +28,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + #include + + #include +--- a/openvpn/src/nss_ovpnmgr_route.c ++++ b/openvpn/src/nss_ovpnmgr_route.c +@@ -34,7 +34,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + #include + + #include diff --git a/qca-nss-clients/patches-11.4/0015-tunipip6-fix-compile-error-in-5.15.patch b/qca-nss-clients/patches-11.4/0015-tunipip6-fix-compile-error-in-5.15.patch new file mode 100644 index 0000000..2db2d62 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0015-tunipip6-fix-compile-error-in-5.15.patch @@ -0,0 +1,11 @@ +--- a/tunipip6/nss_connmgr_tunipip6.c ++++ b/tunipip6/nss_connmgr_tunipip6.c +@@ -257,7 +257,7 @@ static void nss_tunipip6_decap_exception + struct iphdr *iph; + struct rtable *rt; + int cpu; +- int8_t ver = skb->data[0] >> 4; ++ __attribute__((unused)) int8_t ver = skb->data[0] >> 4; + + nss_tunipip6_trace("%px: received - %d bytes name %s ver %x\n", + dev, skb->len, dev->name, ver); diff --git a/qca-nss-clients/patches-11.4/0017-tlsmgr-fix-debug-print-in-5.15.patch b/qca-nss-clients/patches-11.4/0017-tlsmgr-fix-debug-print-in-5.15.patch new file mode 100644 index 0000000..4fbdecb --- /dev/null +++ b/qca-nss-clients/patches-11.4/0017-tlsmgr-fix-debug-print-in-5.15.patch @@ -0,0 +1,34 @@ +--- a/tls/nss_tlsmgr_priv.h ++++ b/tls/nss_tlsmgr_priv.h +@@ -28,7 +28,7 @@ + #define NSS_TLSMGR_DEBUG_LEVEL_INFO 3 + #define NSS_TLSMGR_DEBUG_LEVEL_TRACE 4 + +-#define nss_tlsmgr_info_always(s, ...) pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) ++#define nss_tlsmgr_info_always(s, ...) pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); + + #define nss_tlsmgr_error(s, ...) do { \ + if (net_ratelimit()) { \ +@@ -43,18 +43,18 @@ + } while (0) + + #if defined(CONFIG_DYNAMIC_DEBUG) +-#define nss_tlsmgr_info(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) +-#define nss_tlsmgr_trace(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) ++#define nss_tlsmgr_info(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); ++#define nss_tlsmgr_trace(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); + #else + + #define nss_tlsmgr_info(s, ...) { \ + if (NSS_TLSMGR_DEBUG_LEVEL > NSS_TLSMGR_DEBUG_LEVEL_WARN) \ +- pr_notice("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) \ ++ pr_notice("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); \ + } + + #define nss_tlsmgr_trace(s, ...) { \ + if (NSS_TLSMGR_DEBUG_LEVEL > NSS_TLSMGR_DEBUG_LEVEL_INFO) \ +- pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) \ ++ pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); \ + } + + #endif /* CONFIG_DYNAMIC_DEBUG */ diff --git a/qca-nss-clients/patches-11.4/0018-kernel-6.1-support.patch b/qca-nss-clients/patches-11.4/0018-kernel-6.1-support.patch new file mode 100644 index 0000000..212bda3 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0018-kernel-6.1-support.patch @@ -0,0 +1,300 @@ +--- a/gre/test/nss_connmgr_gre_test.c ++++ b/gre/test/nss_connmgr_gre_test.c +@@ -223,7 +223,7 @@ static int nss_connmgr_gre_test_show_pro + */ + static int nss_connmgr_gre_test_open_proc(struct inode *inode, struct file *filp) + { +- return single_open(filp, nss_connmgr_gre_test_show_proc, PDE_DATA(inode)); ++ return single_open(filp, nss_connmgr_gre_test_show_proc, pde_data(inode)); + } + + /* +--- a/gre/nss_connmgr_gre.c ++++ b/gre/nss_connmgr_gre.c +@@ -279,10 +279,10 @@ static struct rtnl_link_stats64 *nss_con + #else + start = u64_stats_fetch_begin_irq(&tstats->syncp); + #endif +- rx_packets = tstats->rx_packets; +- tx_packets = tstats->tx_packets; +- rx_bytes = tstats->rx_bytes; +- tx_bytes = tstats->tx_bytes; ++ rx_packets = u64_stats_read(&tstats->rx_packets); ++ tx_packets = u64_stats_read(&tstats->tx_packets); ++ rx_bytes = u64_stats_read(&tstats->rx_bytes); ++ tx_bytes = u64_stats_read(&tstats->tx_bytes); + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) + } while (u64_stats_fetch_retry_bh(&tstats->syncp, start)); + #else +@@ -697,11 +697,11 @@ static void nss_connmgr_gre_event_receiv + tstats = this_cpu_ptr(dev->tstats); + u64_stats_update_begin(&tstats->syncp); + if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER) { +- tstats->tx_packets += stats->tx_packets; +- tstats->tx_bytes += stats->tx_bytes; ++ u64_stats_add(&tstats->tx_packets, stats->tx_packets); ++ u64_stats_add(&tstats->tx_bytes, stats->tx_bytes); + } else if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER) { +- tstats->rx_packets += stats->rx_packets; +- tstats->rx_bytes += stats->rx_bytes; ++ u64_stats_add(&tstats->rx_packets, stats->rx_packets); ++ u64_stats_add(&tstats->rx_bytes, stats->rx_bytes); + } + u64_stats_update_end(&tstats->syncp); + dev->stats.rx_dropped += nss_cmn_rx_dropped_sum(stats); +--- a/tunipip6/nss_connmgr_tunipip6.c ++++ b/tunipip6/nss_connmgr_tunipip6.c +@@ -353,11 +353,11 @@ static void nss_tunipip6_update_dev_stat + + memset(&stats, 0, sizeof(stats)); + if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER) { +- stats.tx_packets = sync_stats->node_stats.tx_packets; +- stats.tx_bytes = sync_stats->node_stats.tx_bytes; ++ u64_stats_set(&stats.tx_packets, sync_stats->node_stats.tx_packets); ++ u64_stats_set(&stats.tx_bytes, sync_stats->node_stats.tx_bytes); + } else if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER) { +- stats.rx_packets = sync_stats->node_stats.rx_packets; +- stats.rx_bytes = sync_stats->node_stats.rx_bytes; ++ u64_stats_set(&stats.rx_packets, sync_stats->node_stats.rx_packets); ++ u64_stats_set(&stats.rx_bytes, sync_stats->node_stats.rx_bytes); + } else { + nss_tunipip6_warning("%px: Invalid interface type received from NSS\n", dev); + return; +--- a/nss_qdisc/igs/nss_mirred.c ++++ b/nss_qdisc/igs/nss_mirred.c +@@ -317,7 +317,7 @@ static int nss_mirred_act(struct sk_buff + * Update the last use of action. + */ + tcf_lastuse_update(&act->tcf_tm); +- bstats_cpu_update(this_cpu_ptr(act->common.cpu_bstats), skb); ++ bstats_update(this_cpu_ptr(act->common.cpu_bstats), skb); + + rcu_read_lock(); + retval = READ_ONCE(act->tcf_action); +--- a/nss_qdisc/nss_qdisc.h ++++ b/nss_qdisc/nss_qdisc.h +@@ -188,7 +188,7 @@ struct nss_qdisc { + /* Shaper configure callback for reading shaper specific + * responses (e.g. memory size). + */ +- struct gnet_stats_basic_packed bstats; /* Basic class statistics */ ++ struct gnet_stats_basic_sync bstats; /* Basic class statistics */ + struct gnet_stats_queue qstats; /* Qstats for use by classes */ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0)) + atomic_t refcnt; /* Reference count for class use */ +@@ -445,7 +445,7 @@ extern void nss_qdisc_stop_basic_stats_p + * Wrapper around gnet_stats_copy_basic() + */ + extern int nss_qdisc_gnet_stats_copy_basic(struct Qdisc *sch, +- struct gnet_dump *d, struct gnet_stats_basic_packed *b); ++ struct gnet_dump *d, struct gnet_stats_basic_sync *b); + + /* + * nss_qdisc_gnet_stats_copy_queue() +--- a/nss_qdisc/igs/nss_ifb.c ++++ b/nss_qdisc/igs/nss_ifb.c +@@ -544,8 +544,10 @@ static void nss_ifb_update_dev_stats(str + * post shaping. Therefore IFB interface's stats should be updated + * with NSS firmware's IFB TX stats only. + */ +- stats.rx_packets = stats.tx_packets = node_stats->tx_packets; +- stats.rx_bytes = stats.tx_bytes = node_stats->tx_bytes; ++ u64_stats_set(&stats.rx_packets, node_stats->tx_packets); ++ u64_stats_set(&stats.tx_packets, node_stats->tx_packets); ++ u64_stats_set(&stats.rx_bytes, node_stats->tx_bytes); ++ u64_stats_set(&stats.tx_bytes, node_stats->tx_bytes); + dev->stats.rx_dropped = dev->stats.tx_dropped += sync_stats->igs_stats.tx_dropped; + u64_stats_update_end(&stats.syncp); + +--- a/nss_qdisc/nss_qdisc.c ++++ b/nss_qdisc/nss_qdisc.c +@@ -14,6 +14,7 @@ + ************************************************************************** + */ + ++#include "net/gen_stats.h" + #include + #include "nss_qdisc.h" + #include "nss_fifo.h" +@@ -2173,7 +2174,7 @@ int __nss_qdisc_init(struct Qdisc *sch, + * This is to prevent mixing NSS and PPE qdisc with linux qdisc. + */ + if ((parent != TC_H_ROOT) && (root->ops->owner != THIS_MODULE)) { +- nss_qdisc_warning("NSS qdisc %px (type %d) used along with non-nss qdiscs," ++ nss_qdisc_info("NSS qdisc %px (type %d) used along with non-nss qdiscs," + " or the interface is currently down", nq->qdisc, nq->type); + } + +@@ -2562,7 +2563,7 @@ static void nss_qdisc_basic_stats_callba + { + struct nss_qdisc *nq = (struct nss_qdisc *)app_data; + struct Qdisc *qdisc = nq->qdisc; +- struct gnet_stats_basic_packed *bstats; ++ struct gnet_stats_basic_sync *bstats; + struct gnet_stats_queue *qstats; + struct nss_shaper_node_stats_response *response; + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0)) +@@ -2601,8 +2602,8 @@ static void nss_qdisc_basic_stats_callba + * Update qdisc->bstats + */ + spin_lock_bh(&nq->lock); +- bstats->bytes += (__u64)response->sn_stats.delta.dequeued_bytes; +- bstats->packets += response->sn_stats.delta.dequeued_packets; ++ u64_stats_add(&bstats->bytes, (__u64)response->sn_stats.delta.dequeued_bytes); ++ u64_stats_add(&bstats->packets, response->sn_stats.delta.dequeued_packets); + + /* + * Update qdisc->qstats +@@ -2762,12 +2763,14 @@ void nss_qdisc_stop_basic_stats_polling( + * Wrapper around gnet_stats_copy_basic() + */ + int nss_qdisc_gnet_stats_copy_basic(struct Qdisc *sch, struct gnet_dump *d, +- struct gnet_stats_basic_packed *b) ++ struct gnet_stats_basic_sync *b) + { + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 18, 0)) + return gnet_stats_copy_basic(d, b); + #elif (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0)) + return gnet_stats_copy_basic(d, NULL, b); ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 16, 0)) ++ return gnet_stats_copy_basic(d, NULL, b, true); + #else + return gnet_stats_copy_basic(qdisc_root_sleeping_running(sch), d, NULL, b); + #endif +@@ -2798,7 +2801,6 @@ static int nss_qdisc_if_event_cb(struct + struct net_device *br; + struct Qdisc *br_qdisc; + int if_num, br_num; +- struct nss_qdisc *nq; + + dev = nss_qdisc_get_dev(ptr); + if (!dev) { +@@ -2841,8 +2843,6 @@ static int nss_qdisc_if_event_cb(struct + break; + } + +- nq = (struct nss_qdisc *)qdisc_priv(br_qdisc); +- + /* + * Call attach or detach according as per event type. + */ +--- a/vxlanmgr/nss_vxlanmgr_tunnel.c ++++ b/vxlanmgr/nss_vxlanmgr_tunnel.c +@@ -465,8 +465,8 @@ static void nss_vxlanmgr_tunnel_inner_st + + tstats = this_cpu_ptr(dev->tstats); + u64_stats_update_begin(&tstats->syncp); +- tstats->tx_packets += stats->node_stats.tx_packets; +- tstats->tx_bytes += stats->node_stats.tx_bytes; ++ u64_stats_add(&tstats->tx_packets, stats->node_stats.tx_packets); ++ u64_stats_add(&tstats->tx_bytes, stats->node_stats.tx_bytes); + u64_stats_update_end(&tstats->syncp); + netdev_stats->tx_dropped += dropped; + dev_put(dev); +@@ -503,8 +503,8 @@ static void nss_vxlanmgr_tunnel_outer_st + + tstats = this_cpu_ptr(dev->tstats); + u64_stats_update_begin(&tstats->syncp); +- tstats->rx_packets += stats->node_stats.tx_packets; +- tstats->rx_bytes += stats->node_stats.tx_bytes; ++ u64_stats_add(&tstats->rx_packets, stats->node_stats.tx_packets); ++ u64_stats_add(&tstats->rx_bytes, stats->node_stats.tx_bytes); + u64_stats_update_end(&tstats->syncp); + netdev_stats->rx_dropped += dropped; + dev_put(dev); +--- a/pvxlanmgr/nss_pvxlanmgr.c ++++ b/pvxlanmgr/nss_pvxlanmgr.c +@@ -177,7 +177,7 @@ static struct rtnl_link_stats64 *nss_pvx + * Netdev seems to be incrementing rx_dropped because we don't give IP header. + * So reset it as it's of no use for us. + */ +- atomic_long_set(&dev->rx_dropped, 0); ++ atomic_long_set(&(dev)->stats.__rx_dropped, 0); + priv = netdev_priv(dev); + memset(stats, 0, sizeof(struct rtnl_link_stats64)); + memcpy(stats, &priv->stats, sizeof(struct rtnl_link_stats64)); +@@ -305,9 +305,9 @@ static void nss_pvxlanmgr_dummy_netdev_s + dev->priv_destructor = NULL; + #endif + +- memcpy(dev->dev_addr, "\x00\x00\x00\x00\x00\x00", dev->addr_len); +- memset(dev->broadcast, 0xff, dev->addr_len); +- memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); ++ const uint8_t mac_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; ++ eth_hw_addr_set(dev, mac_addr); ++ eth_broadcast_addr(dev->broadcast); + } + + /* +--- a/clmapmgr/nss_clmapmgr.c ++++ b/clmapmgr/nss_clmapmgr.c +@@ -103,7 +103,7 @@ static struct rtnl_link_stats64 *nss_clm + * Netdev seems to be incrementing rx_dropped because we don't give IP header. + * So reset it as it's of no use for us. + */ +- atomic_long_set(&dev->rx_dropped, 0); ++ atomic_long_set(&(dev)->stats.__rx_dropped, 0); + priv = netdev_priv(dev); + memset(stats, 0, sizeof(struct rtnl_link_stats64)); + memcpy(stats, &priv->stats, sizeof(struct rtnl_link_stats64)); +--- a/tls/nss_tlsmgr_tun.c ++++ b/tls/nss_tlsmgr_tun.c +@@ -185,7 +185,7 @@ static void nss_tlsmgr_tun_setup(struct + /* + * Get the MAC address from the ethernet device + */ +- random_ether_addr(dev->dev_addr); ++ eth_random_addr((u8 *) dev->dev_addr); + + memset(dev->broadcast, 0xff, dev->addr_len); + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); +--- a/netlink/nss_nlgre_redir_cmn.c ++++ b/netlink/nss_nlgre_redir_cmn.c +@@ -384,7 +384,7 @@ static int nss_nlgre_redir_cmn_set_mac_a + return -EINVAL; + } + +- memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); ++ memcpy((void *) dev->dev_addr, addr->sa_data, ETH_ALEN); + return 0; + } + +--- a/nss_connmgr_tun6rd.c ++++ b/nss_connmgr_tun6rd.c +@@ -101,10 +101,10 @@ static void nss_tun6rd_update_dev_stats( + + u64_stats_init(&stats.syncp); + u64_stats_update_begin(&stats.syncp); +- stats.rx_packets = sync_stats->node_stats.rx_packets; +- stats.rx_bytes = sync_stats->node_stats.rx_bytes; +- stats.tx_packets = sync_stats->node_stats.tx_packets; +- stats.tx_bytes = sync_stats->node_stats.tx_bytes; ++ u64_stats_set(&stats.rx_packets, sync_stats->node_stats.rx_packets); ++ u64_stats_set(&stats.rx_bytes, sync_stats->node_stats.rx_bytes); ++ u64_stats_set(&stats.tx_packets, sync_stats->node_stats.tx_packets); ++ u64_stats_set(&stats.tx_bytes, sync_stats->node_stats.tx_bytes); + u64_stats_update_end(&stats.syncp); + #else + struct nss_tun6rd_stats stats; +--- a/ipsecmgr/v1.0/nss_ipsecmgr.c ++++ b/ipsecmgr/v1.0/nss_ipsecmgr.c +@@ -445,7 +445,7 @@ static void nss_ipsecmgr_tunnel_setup(st + /* + * get the MAC address from the ethernet device + */ +- random_ether_addr(dev->dev_addr); ++ eth_random_addr((u8 *) dev->dev_addr); + + memset(dev->broadcast, 0xff, dev->addr_len); + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); +--- a/ipsecmgr/v2.0/nss_ipsecmgr_tunnel.c ++++ b/ipsecmgr/v2.0/nss_ipsecmgr_tunnel.c +@@ -445,7 +445,7 @@ static void nss_ipsecmgr_tunnel_setup(st + /* + * Get the MAC address from the ethernet device + */ +- random_ether_addr(dev->dev_addr); ++ eth_random_addr((u8 *) dev->dev_addr); + + memset(dev->broadcast, 0xff, dev->addr_len); + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); diff --git a/qca-nss-clients/patches-11.4/0019-wifi-meshmgr-fix-uninitialized-and-implicit.patch b/qca-nss-clients/patches-11.4/0019-wifi-meshmgr-fix-uninitialized-and-implicit.patch new file mode 100644 index 0000000..6f3160a --- /dev/null +++ b/qca-nss-clients/patches-11.4/0019-wifi-meshmgr-fix-uninitialized-and-implicit.patch @@ -0,0 +1,225 @@ +--- a/wifi_meshmgr/nss_wifi_meshmgr.c ++++ b/wifi_meshmgr/nss_wifi_meshmgr.c +@@ -49,7 +49,7 @@ static bool nss_wifi_meshmgr_verify_if_n + */ + static nss_wifi_meshmgr_status_t nss_wifi_meshmgr_tx_msg(struct nss_wifi_mesh_msg *msg) + { +- return nss_wifi_mesh_tx_msg(wmgr_ctx.nss_ctx, msg); ++ return (nss_wifi_meshmgr_status_t)nss_wifi_mesh_tx_msg(wmgr_ctx.nss_ctx, msg); + } + + /* +@@ -126,7 +126,7 @@ static void nss_wifi_meshmgr_cleanup(str + * Unregister and dealloc decap DI. + */ + nss_unregister_wifi_mesh_if(decap_ifnum); +- nss_status = nss_dynamic_interface_dealloc_node(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER); ++ nss_status = (nss_wifi_meshmgr_status_t)nss_dynamic_interface_dealloc_node(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER); + if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) { + nss_wifi_meshmgr_warn("%px: Failed to dealloc decap: %d\n", &wmgr_ctx, nss_status); + } +@@ -135,7 +135,7 @@ static void nss_wifi_meshmgr_cleanup(str + * Unregister and dealloc encap DI. + */ + nss_unregister_wifi_mesh_if(encap_ifnum); +- nss_status = nss_dynamic_interface_dealloc_node(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER); ++ nss_status = (nss_wifi_meshmgr_status_t)nss_dynamic_interface_dealloc_node(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER); + if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) { + nss_wifi_meshmgr_warn("%px: Failed to dealloc encap: %d\n", &wmgr_ctx, nss_status); + } +@@ -257,10 +257,10 @@ static void nss_wifi_meshmgr_tx_msg_cb(v + /* + * FIXME: The wmesh_ctx can be invalid if the memory goes away with the caller being timedout. + */ +- wmesh_ctx->response = NSS_WIFI_MESHMGR_SUCCESS; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_SUCCESS; + if (ncm->response != NSS_CMN_RESPONSE_ACK) { + nss_wifi_meshmgr_warn("%px: WiFi-Mesh error response %d error_code: %u\n", &wmgr_ctx, ncm->response, error_code); +- wmesh_ctx->response = nss_wifi_meshmgr_remap_error(error_code); ++ wmesh_ctx->response = (nss_tx_status_t)nss_wifi_meshmgr_remap_error(error_code); + } + + complete(&wmesh_ctx->complete); +@@ -289,10 +289,10 @@ static nss_wifi_meshmgr_status_t nss_wif + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- status = wmesh_ctx->response; ++ status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + return status; + } +@@ -324,7 +324,7 @@ nss_wifi_meshmgr_status_t nss_wifi_meshm + return NSS_WIFI_MESHMGR_FAILURE; + } + +- nss_status = nss_wifi_mesh_tx_buf(wmgr_ctx.nss_ctx, os_buf, encap_ifnum); ++ nss_status = (nss_wifi_meshmgr_status_t)nss_wifi_mesh_tx_buf(wmgr_ctx.nss_ctx, os_buf, encap_ifnum); + nss_wifi_meshmgr_ref_dec(wmesh_ctx); + return nss_status; + } +@@ -548,10 +548,10 @@ nss_wifi_meshmgr_dump_mesh_path_sync(nss + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -643,10 +643,10 @@ nss_wifi_meshmgr_dump_mesh_proxy_path_sy + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -715,7 +715,7 @@ nss_wifi_meshmgr_assoc_link_vap(nss_wifi + /* + * Send the link vap mesage to the NSS synchronously. + */ +- nss_status = nss_wifi_vdev_tx_msg(wmgr_ctx.nss_ctx, wifivdevmsg); ++ nss_status = (nss_wifi_meshmgr_status_t)nss_wifi_vdev_tx_msg(wmgr_ctx.nss_ctx, wifivdevmsg); + if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) { + nss_wifi_meshmgr_warn("%px: Mesh link vap association failed: %d.\n", &wmgr_ctx, nss_status); + } +@@ -761,10 +761,10 @@ nss_wifi_meshmgr_assoc_link_vap_sync(nss + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -886,10 +886,10 @@ nss_wifi_meshmgr_mesh_config_update_sync + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -985,10 +985,10 @@ nss_wifi_meshmgr_mesh_proxy_path_delete_ + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1084,10 +1084,10 @@ nss_wifi_meshmgr_mesh_proxy_path_update_ + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1183,10 +1183,10 @@ nss_wifi_meshmgr_mesh_proxy_path_add_syn + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1282,10 +1282,10 @@ nss_wifi_meshmgr_mesh_path_delete_sync(n + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1381,10 +1381,10 @@ nss_wifi_meshmgr_mesh_path_add_sync(nss_ + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + nss_wifi_meshmgr_ref_dec(wmesh_ctx); + return nss_status; +@@ -1479,10 +1479,10 @@ nss_wifi_meshmgr_mesh_path_update_sync(n + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1578,10 +1578,10 @@ nss_wifi_meshmgr_mesh_path_exception_syn + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1795,7 +1795,7 @@ nss_wifi_mesh_handle_t nss_wifi_meshmgr_ + int32_t encap_ifnum, decap_ifnum; + uint32_t features = 0; + nss_wifi_mesh_handle_t mesh_handle; +- nss_wifi_meshmgr_status_t nss_status; ++ nss_wifi_meshmgr_status_t nss_status = NSS_WIFI_MESHMGR_SUCCESS; + struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx; + + spin_lock_bh(&wmgr_ctx.ref_lock); diff --git a/qca-nss-clients/patches-11.4/0020-capwapmgr-fix-compile-error.patch b/qca-nss-clients/patches-11.4/0020-capwapmgr-fix-compile-error.patch new file mode 100644 index 0000000..c8606fa --- /dev/null +++ b/qca-nss-clients/patches-11.4/0020-capwapmgr-fix-compile-error.patch @@ -0,0 +1,169 @@ +--- a/capwapmgr/nss_capwapmgr.c ++++ b/capwapmgr/nss_capwapmgr.c +@@ -331,7 +331,7 @@ static struct rtnl_link_stats64 *nss_cap + * Netdev seems to be incrementing rx_dropped because we don't give IP header. + * So reset it as it's of no use for us. + */ +- atomic_long_set(&dev->rx_dropped, 0); ++ dev->stats.rx_dropped = 0; + + memset(stats, 0, sizeof (struct rtnl_link_stats64)); + nss_capwapmgr_fill_up_stats(stats, &global.tunneld); +@@ -376,7 +376,6 @@ static const struct net_device_ops nss_c + .ndo_stop = nss_capwapmgr_close, + .ndo_start_xmit = nss_capwapmgr_start_xmit, + .ndo_set_mac_address = eth_mac_addr, +- .ndo_change_mtu = eth_change_mtu, + .ndo_get_stats64 = nss_capwapmgr_dev_tunnel_stats, + }; + +@@ -400,7 +399,7 @@ static void nss_capwapmgr_dummpy_netdev_ + #else + dev->priv_destructor = NULL; + #endif +- memcpy(dev->dev_addr, "\x00\x00\x00\x00\x00\x00", dev->addr_len); ++ memcpy((u8 *)dev->dev_addr, "\x00\x00\x00\x00\x00\x00", dev->addr_len); + memset(dev->broadcast, 0xff, dev->addr_len); + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); + } +@@ -569,7 +568,7 @@ static struct nss_capwapmgr_tunnel *nss_ + * nss_capwapmgr_netdev_create() + * API to create a CAPWAP netdev + */ +-struct net_device *nss_capwapmgr_netdev_create() ++struct net_device *nss_capwapmgr_netdev_create(void) + { + struct nss_capwapmgr_priv *priv; + struct nss_capwapmgr_response *r; +@@ -1168,7 +1167,7 @@ static nss_capwapmgr_status_t nss_capwap + /* + * Call NSS driver + */ +- status = nss_capwap_tx_msg(ctx, msg); ++ status = (nss_capwapmgr_status_t)nss_capwap_tx_msg(ctx, msg); + if (status != NSS_CAPWAPMGR_SUCCESS) { + up(&r->sem); + dev_put(dev); +@@ -1209,7 +1208,7 @@ static nss_capwapmgr_status_t nss_capwap + struct nss_ctx_instance *ctx = nss_capwap_get_ctx(); + struct nss_capwap_msg capwapmsg; + struct nss_capwap_rule_msg *capwapcfg; +- nss_tx_status_t status; ++ nss_capwapmgr_status_t status; + + nss_capwapmgr_info("%px: ctx: CAPWAP Rule src_port: 0x%d dest_port:0x%d\n", ctx, + ntohl(msg->encap.src_port), ntohl(msg->encap.dest_port)); +@@ -1274,7 +1273,7 @@ static nss_capwapmgr_status_t nss_capwap + nss_capwapmgr_msg_event_receive, dev); + + status = nss_capwapmgr_tx_msg_sync(ctx, dev, &capwapmsg); +- if (status != NSS_TX_SUCCESS) { ++ if (status != NSS_CAPWAPMGR_SUCCESS) { + nss_capwapmgr_warn("%px: ctx: create encap data tunnel error %d \n", ctx, status); + return status; + } +@@ -1286,10 +1285,10 @@ static nss_capwapmgr_status_t nss_capwap + * nss_capwapmgr_tx_msg_enable_tunnel() + * Common function to send CAPWAP tunnel enable msg + */ +-static nss_tx_status_t nss_capwapmgr_tx_msg_enable_tunnel(struct nss_ctx_instance *ctx, struct net_device *dev, uint32_t if_num, uint32_t sibling_if_num) ++static nss_capwapmgr_status_t nss_capwapmgr_tx_msg_enable_tunnel(struct nss_ctx_instance *ctx, struct net_device *dev, uint32_t if_num, uint32_t sibling_if_num) + { + struct nss_capwap_msg capwapmsg; +- nss_tx_status_t status; ++ nss_capwapmgr_status_t status; + + /* + * Prepare the tunnel configuration parameter to send to NSS FW +@@ -1303,7 +1302,7 @@ static nss_tx_status_t nss_capwapmgr_tx_ + nss_capwap_msg_init(&capwapmsg, if_num, NSS_CAPWAP_MSG_TYPE_ENABLE_TUNNEL, sizeof(struct nss_capwap_enable_tunnel_msg), nss_capwapmgr_msg_event_receive, dev); + + status = nss_capwapmgr_tx_msg_sync(ctx, dev, &capwapmsg); +- if (status != NSS_TX_SUCCESS) { ++ if (status != NSS_CAPWAPMGR_SUCCESS) { + nss_capwapmgr_warn("%px: ctx: CMD: %d Tunnel error : %d \n", ctx, NSS_CAPWAP_MSG_TYPE_ENABLE_TUNNEL, status); + } + +@@ -1315,7 +1314,7 @@ static nss_tx_status_t nss_capwapmgr_tx_ + * Common function for CAPWAP tunnel operation messages without + * any message data structures. + */ +-static nss_tx_status_t nss_capwapmgr_tunnel_action(struct nss_ctx_instance *ctx, struct net_device *dev, uint32_t if_num, nss_capwap_msg_type_t cmd) ++static nss_capwapmgr_status_t nss_capwapmgr_tunnel_action(struct nss_ctx_instance *ctx, struct net_device *dev, uint32_t if_num, nss_capwap_msg_type_t cmd) + { + struct nss_capwap_msg capwapmsg; + nss_tx_status_t status; +@@ -1330,12 +1329,12 @@ static nss_tx_status_t nss_capwapmgr_tun + */ + nss_capwap_msg_init(&capwapmsg, if_num, cmd, 0, nss_capwapmgr_msg_event_receive, dev); + +- status = nss_capwapmgr_tx_msg_sync(ctx, dev, &capwapmsg); ++ status = (nss_tx_status_t)nss_capwapmgr_tx_msg_sync(ctx, dev, &capwapmsg); + if (status != NSS_TX_SUCCESS) { + nss_capwapmgr_warn("%px: ctx: CMD: %d Tunnel error : %d \n", ctx, cmd, status); + } + +- return status; ++ return (nss_capwapmgr_status_t)status; + } + + /* +@@ -1460,7 +1459,6 @@ EXPORT_SYMBOL(nss_capwapmgr_update_path_ + */ + nss_capwapmgr_status_t nss_capwapmgr_update_dest_mac_addr(struct net_device *dev, uint8_t tunnel_id, uint8_t *mac_addr) + { +- struct nss_capwapmgr_priv *priv; + struct nss_capwapmgr_tunnel *t; + nss_tx_status_t nss_status; + nss_capwapmgr_status_t status = NSS_CAPWAPMGR_SUCCESS; +@@ -1476,7 +1474,6 @@ nss_capwapmgr_status_t nss_capwapmgr_upd + } + + +- priv = netdev_priv(dev); + nss_capwapmgr_info("%px: %d: tunnel update mac Addr is being called\n", dev, tunnel_id); + + /* +@@ -1523,7 +1520,6 @@ EXPORT_SYMBOL(nss_capwapmgr_update_dest_ + */ + nss_capwapmgr_status_t nss_capwapmgr_update_src_interface(struct net_device *dev, uint8_t tunnel_id, uint32_t src_interface_num) + { +- struct nss_capwapmgr_priv *priv; + struct nss_capwapmgr_tunnel *t; + nss_tx_status_t nss_status; + uint32_t outer_trustsec_enabled, dtls_enabled, forward_if_num, src_interface_num_temp; +@@ -1537,7 +1533,6 @@ nss_capwapmgr_status_t nss_capwapmgr_upd + } + + +- priv = netdev_priv(dev); + nss_capwapmgr_info("%px: %d: tunnel update source interface is being called\n", dev, tunnel_id); + outer_trustsec_enabled = t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_OUTER_TRUSTSEC_ENABLED; + dtls_enabled = t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_DTLS_ENABLED; +@@ -1576,7 +1571,7 @@ nss_capwapmgr_status_t nss_capwapmgr_upd + /* + * Destroy the IP rule only if it already exist. + */ +- if (t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) { ++ if (NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) { + struct nss_ipv4_destroy v4_destroy; + v4_destroy.protocol = IPPROTO_UDP; + v4_destroy.src_ip = t->ip_rule.v4.src_ip; +@@ -1606,7 +1601,7 @@ nss_capwapmgr_status_t nss_capwapmgr_upd + /* + * Destroy the IP rule only if it already exist. + */ +- if (t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) { ++ if (NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) { + struct nss_ipv6_destroy v6_destroy; + + if (t->capwap_rule.which_udp == NSS_CAPWAP_TUNNEL_UDP) { +@@ -1750,7 +1745,7 @@ nss_capwapmgr_status_t nss_capwapmgr_dsc + uint8_t rule_nr = NSS_CAPWAPMGR_RULE_NR; + uint8_t list_id, v4_rule_id, v6_rule_id; + uint8_t lid, rid, i, j; +- int8_t err, fail_dscp; ++ uint8_t err, fail_dscp; + int8_t uid = -1; + + nss_capwapmgr_info("Setting priority %u for dscp %u mask %u\n", pri, dscp_value, dscp_mask); diff --git a/qca-nss-clients/patches-11.4/0022-netlink-modularize-makefile.patch b/qca-nss-clients/patches-11.4/0022-netlink-modularize-makefile.patch new file mode 100644 index 0000000..cc5c6d5 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0022-netlink-modularize-makefile.patch @@ -0,0 +1,447 @@ +--- a/netlink/Makefile ++++ b/netlink/Makefile +@@ -10,45 +10,78 @@ ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BU + + ccflags-y += -DCONFIG_NSS_NLIPV4=1 + ccflags-y += -DCONFIG_NSS_NLIPV6=1 +-ccflags-y += -DCONFIG_NSS_NLOAM=1 +-ccflags-y += -DCONFIG_NSS_NLGRE_REDIR_FAMILY=1 ++ccflags-y += -DCONFIG_NSS_NLOAM=$(strip $(if $(filter $(oam), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLGRE_REDIR_FAMILY=$(strip $(if $(filter $(CONFIG_NSS_NLGRE_REDIR_FAMILY), y), 1 , 0)) + ccflags-y += -DCONFIG_NSS_NLETHRX=1 + ccflags-y += -DCONFIG_NSS_NLDYNAMIC_INTERFACE=1 + ccflags-y += -DCONFIG_NSS_NLN2H=1 +-ccflags-y += -DCONFIG_NSS_NLIPV4_REASM=1 +-ccflags-y += -DCONFIG_NSS_NLIPV6_REASM=1 ++ccflags-y += -DCONFIG_NSS_NLIPV4_REASM=$(strip $(if $(filter $(CONFIG_NSS_NLIPV4_REASM), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLIPV6_REASM=$(strip $(if $(filter $(CONFIG_NSS_NLIPV6_REASM), y), 1 , 0)) + ccflags-y += -DCONFIG_NSS_NLWIFILI=1 +-ccflags-y += -DCONFIG_NSS_NLLSO_RX=1 +-ccflags-y += -DCONFIG_NSS_NLMAP_T=1 +-ccflags-y += -DCONFIG_NSS_NLPPPOE=1 +-ccflags-y += -DCONFIG_NSS_NLL2TPV2=1 +-ccflags-y += -DCONFIG_NSS_NLPPTP=1 ++ccflags-y += -DCONFIG_NSS_NLLSO_RX=$(strip $(if $(filter $(CONFIG_NSS_NLLSO_RX), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLMAP_T=$(strip $(if $(filter $(map-t), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLPPPOE=$(strip $(if $(filter $(pppoe), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLL2TPV2=$(strip $(if $(filter $(l2tp), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLPPTP=$(strip $(if $(filter $(pptp), y), 1 , 0)) + ccflags-y += -DCONFIG_NSS_NLCAPWAP=${CAPWAP_ENABLED} + ccflags-y += -DCONFIG_NSS_NLIPSEC=${IPSEC_ENABLED} + ccflags-y += -DCONFIG_NSS_NLDTLS=${DTLS_ENABLED} +-ccflags-y += -DCONFIG_NSS_NLUDP_ST=1 ++ccflags-y += -DCONFIG_NSS_NLUDP_ST=$(strip $(if $(filter $(CONFIG_NSS_NLUDP_ST), y), 1 , 0)) + + qca-nss-netlink-objs := nss_nl.o ++ ++ifneq (,$(filter $(gre), y)) + qca-nss-netlink-objs += nss_nlgre_redir_family.o + qca-nss-netlink-objs += nss_nlgre_redir_cmd.o + qca-nss-netlink-objs += nss_nlgre_redir_cmn.o + qca-nss-netlink-objs += nss_nlgre_redir.o + qca-nss-netlink-objs += nss_nlgre_redir_lag.o ++endif ++ + qca-nss-netlink-objs += nss_nlipv4.o + qca-nss-netlink-objs += nss_nlipv6.o ++ ++ifneq (,$(filter $(oam), y)) + qca-nss-netlink-objs += nss_nloam.o ++endif ++ + qca-nss-netlink-objs += nss_nlethrx.o + qca-nss-netlink-objs += nss_nldynamic_interface.o + qca-nss-netlink-objs += nss_nln2h.o ++ ++ifneq (,$(filter $(CONFIG_NSS_NLIPV4_REASM), y)) + qca-nss-netlink-objs += nss_nlipv4_reasm.o ++endif ++ifneq (,$(filter $(CONFIG_NSS_NLIPV6_REASM), y)) + qca-nss-netlink-objs += nss_nlipv6_reasm.o ++endif ++ + qca-nss-netlink-objs += nss_nlwifili.o ++ ++ifneq (,$(filter $(CONFIG_NSS_NLLSO_RX), y)) + qca-nss-netlink-objs += nss_nllso_rx.o ++endif ++ ++ifneq (,$(filter $(map-t), y)) + qca-nss-netlink-objs += nss_nlmap_t.o ++endif ++ifneq (,$(filter $(pppoe), y)) + qca-nss-netlink-objs += nss_nlpppoe.o ++endif ++ ++ifneq (,$(filter $(l2tp), y)) + qca-nss-netlink-objs += nss_nll2tpv2.o ++endif ++ ++ifneq (,$(filter $(pptp), y)) + qca-nss-netlink-objs += nss_nlpptp.o ++endif ++ ++ifeq ($(SoC),$(filter $(SoC),ipq95xx ipq50xx ipq807x_64)) ++ifneq (,$(filter $(CONFIG_NSS_NLUDP_ST), y)) + qca-nss-netlink-objs += nss_nludp_st.o ++endif ++endif + + ifneq (,$(filter $(capwapmgr), y)) + qca-nss-netlink-objs += nss_nlcapwap.o +@@ -62,14 +95,11 @@ ifneq (,$(filter $(ipsecmgr), y)) + qca-nss-netlink-objs += nss_nlipsec.o + endif + ++ccflags-y += -DCONFIG_NSS_NLC2C_TX=$(strip $(if $(filter $(CONFIG_NSS_NLC2C), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLC2C_RX=$(strip $(if $(filter $(CONFIG_NSS_NLC2C), y), 1 , 0)) + ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64)) +-ccflags-y += -DCONFIG_NSS_NLC2C_TX=1 +-ccflags-y += -DCONFIG_NSS_NLC2C_RX=1 +-qca-nss-netlink-objs += nss_nlc2c_tx.o +-qca-nss-netlink-objs += nss_nlc2c_rx.o +-else +-ccflags-y += -DCONFIG_NSS_NLC2C_TX=0 +-ccflags-y += -DCONFIG_NSS_NLC2C_RX=0 ++qca-nss-netlink-objs += $(strip $(if $(filter $(CONFIG_NSS_NLC2C), y), nss_nlc2c_tx.o,)) ++qca-nss-netlink-objs += $(strip $(if $(filter $(CONFIG_NSS_NLC2C), y), nss_nlc2c_rx.o,)) + endif + + ifeq ($(SoC),$(filter $(SoC),ipq60xx ipq60xx_64 ipq807x ipq807x_64)) +--- a/netlink/nss_nludp_st.h ++++ b/netlink/nss_nludp_st.h +@@ -23,10 +23,9 @@ + #ifndef __NSS_NLUDP_ST_H + #define __NSS_NLUDP_ST_H + ++#if defined(CONFIG_NSS_NLUDP_ST) && CONFIG_NSS_NLUDP_ST > 0 + bool nss_nludp_st_init(void); + bool nss_nludp_st_exit(void); +- +-#if defined(CONFIG_NSS_NLUDP_ST) + #define NSS_NLUDP_ST_INIT nss_nludp_st_init + #define NSS_NLUDP_ST_EXIT nss_nludp_st_exit + #else +--- a/netlink/nss_nldynamic_interface.h ++++ b/netlink/nss_nldynamic_interface.h +@@ -26,7 +26,7 @@ + bool nss_nldynamic_interface_init(void); + bool nss_nldynamic_interface_exit(void); + +-#if defined(CONFIG_NSS_NLDYNAMIC_INTERFACE) ++#if defined(CONFIG_NSS_NLDYNAMIC_INTERFACE) && CONFIG_NSS_NLDYNAMIC_INTERFACE > 0 + #define NSS_NLDYNAMIC_INTERFACE_INIT nss_nldynamic_interface_init + #define NSS_NLDYNAMIC_INTERFACE_EXIT nss_nldynamic_interface_exit + #else +--- a/netlink/nss_nlethrx.h ++++ b/netlink/nss_nlethrx.h +@@ -26,7 +26,7 @@ + bool nss_nlethrx_init(void); + bool nss_nlethrx_exit(void); + +-#if defined(CONFIG_NSS_NLETHRX) ++#if defined(CONFIG_NSS_NLETHRX) && CONFIG_NSS_NLETHRX > 0 + #define NSS_NLETHRX_INIT nss_nlethrx_init + #define NSS_NLETHRX_EXIT nss_nlethrx_exit + #else +--- a/netlink/nss_nlgre_redir_family.h ++++ b/netlink/nss_nlgre_redir_family.h +@@ -33,7 +33,7 @@ bool nss_nlgre_redir_family_init(void); + */ + bool nss_nlgre_redir_family_exit(void); + +-#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY) ++#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY) && CONFIG_NSS_NLGRE_REDIR_FAMILY > 0 + #define NSS_NLGRE_REDIR_FAMILY_INIT nss_nlgre_redir_family_init + #define NSS_NLGRE_REDIR_FAMILY_EXIT nss_nlgre_redir_family_exit + #else +--- a/netlink/nss_nlipv4.c ++++ b/netlink/nss_nlipv4.c +@@ -336,6 +336,7 @@ static int nss_nlipv4_verify_conn_rule(s + tuple->return_ident, tuple->flow_ident); + break; + ++#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY) && CONFIG_NSS_NLGRE_REDIR_FAMILY > 0 + case NSS_NL_IFTYPE_TUNNEL_GRE: + /* + * Currently this implementation is only for gre_redir +@@ -349,6 +350,7 @@ static int nss_nlipv4_verify_conn_rule(s + + conn->flow_mtu = nss_nlgre_redir_cmd_get_mtu(flow_dev, NSS_GRE_REDIR_IP_HDR_TYPE_IPV4, conn->flow_interface_num); + break; ++#endif /*!CONFIG_NSS_NLGRE_REDIR_FAMILY */ + + case NSS_NL_IFTYPE_VLAN: + conn->flow_interface_num = nss_cmn_get_interface_number_by_dev(vlan_dev_real_dev(flow_dev)); +@@ -396,6 +398,7 @@ static int nss_nlipv4_verify_conn_rule(s + tuple->return_ident, tuple->flow_ident); + break; + ++#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY) && CONFIG_NSS_NLGRE_REDIR_FAMILY > 0 + case NSS_NL_IFTYPE_TUNNEL_GRE: + conn->return_interface_num = nss_nlgre_redir_cmd_get_ifnum(return_dev, tuple->protocol); + if (conn->return_interface_num < 0 ) { +@@ -406,6 +409,7 @@ static int nss_nlipv4_verify_conn_rule(s + + conn->return_mtu = nss_nlgre_redir_cmd_get_mtu(return_dev, NSS_GRE_REDIR_IP_HDR_TYPE_IPV4, conn->return_interface_num); + break; ++#endif /*!CONFIG_NSS_NLGRE_REDIR_FAMILY */ + + case NSS_NL_IFTYPE_VLAN: + conn->return_interface_num = nss_cmn_get_interface_number_by_dev(vlan_dev_real_dev(return_dev)); +@@ -480,6 +484,7 @@ static int nss_nlipv4_verify_tcp_rule(st + return 0; + } + ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + /* + * nss_nlipv4_verify_pppoe_rule() + * verify and override pppoe rule entries +@@ -505,6 +510,7 @@ static int nss_nlipv4_verify_pppoe_rule( + */ + return 0; + } ++#endif + + /* + * nss_nlipv4_verify_qos_rule() +@@ -777,6 +783,7 @@ static int nss_nlipv4_ops_create_rule(st + goto done; + } + ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + /* + * check pppoe rule + */ +@@ -785,6 +792,7 @@ static int nss_nlipv4_ops_create_rule(st + nss_nl_error("%d:invalid pppoe rule information passed\n", pid); + goto done; + } ++#endif + + /* + * check qos rule +--- a/netlink/nss_nlipv4.h ++++ b/netlink/nss_nlipv4.h +@@ -24,7 +24,7 @@ + bool nss_nlipv4_init(void); + bool nss_nlipv4_exit(void); + +-#if defined(CONFIG_NSS_NLIPV4) ++#if defined(CONFIG_NSS_NLIPV4) && CONFIG_NSS_NLIPV4 > 0 + #define NSS_NLIPV4_INIT nss_nlipv4_init + #define NSS_NLIPV4_EXIT nss_nlipv4_exit + #else +--- a/netlink/nss_nlipv4_reasm.h ++++ b/netlink/nss_nlipv4_reasm.h +@@ -26,7 +26,7 @@ + bool nss_nlipv4_reasm_init(void); + bool nss_nlipv4_reasm_exit(void); + +-#if defined(CONFIG_NSS_NLIPV4_REASM) ++#if defined(CONFIG_NSS_NLIPV4_REASM) && CONFIG_NSS_NLIPV4_REASM > 0 + #define NSS_NLIPV4_REASM_INIT nss_nlipv4_reasm_init + #define NSS_NLIPV4_REASM_EXIT nss_nlipv4_reasm_exit + #else +--- a/netlink/nss_nlipv6.c ++++ b/netlink/nss_nlipv6.c +@@ -353,6 +353,7 @@ static int nss_nlipv6_verify_conn_rule(s + tuple->return_ident, tuple->flow_ident); + break; + ++#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY) && CONFIG_NSS_NLGRE_REDIR_FAMILY > 0 + case NSS_NL_IFTYPE_TUNNEL_GRE: + conn->flow_interface_num = nss_nlgre_redir_cmd_get_ifnum(flow_dev, tuple->protocol); + if (conn->flow_interface_num < 0 ) { +@@ -363,6 +364,7 @@ static int nss_nlipv6_verify_conn_rule(s + + conn->flow_mtu = nss_nlgre_redir_cmd_get_mtu(flow_dev, NSS_GRE_REDIR_IP_HDR_TYPE_IPV6, conn->flow_interface_num); + break; ++#endif /* !CONFIG_NSS_NLGRE_REDIR_FAMILY */ + + case NSS_NL_IFTYPE_VLAN: + conn->flow_interface_num = nss_cmn_get_interface_number_by_dev(vlan_dev_real_dev(flow_dev)); +@@ -411,6 +413,7 @@ static int nss_nlipv6_verify_conn_rule(s + tuple->return_ident, tuple->flow_ident); + break; + ++#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY) && CONFIG_NSS_NLGRE_REDIR_FAMILY > 0 + case NSS_NL_IFTYPE_TUNNEL_GRE: + conn->return_interface_num = nss_nlgre_redir_cmd_get_ifnum(return_dev, tuple->protocol); + if (conn->return_interface_num < 0 ) { +@@ -421,6 +424,7 @@ static int nss_nlipv6_verify_conn_rule(s + + conn->return_mtu = nss_nlgre_redir_cmd_get_mtu(return_dev, NSS_GRE_REDIR_IP_HDR_TYPE_IPV6, conn->return_interface_num); + break; ++#endif /* !CONFIG_NSS_NLGRE_REDIR_FAMILY */ + + case NSS_NL_IFTYPE_VLAN: + conn->return_interface_num = nss_cmn_get_interface_number_by_dev(vlan_dev_real_dev(return_dev)); +@@ -486,6 +490,7 @@ static int nss_nlipv6_verify_tcp_rule(st + return 0; + } + ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + /* + * nss_nlipv6_verify_pppoe_rule() + * verify and override pppoe rule entries +@@ -510,6 +515,7 @@ static int nss_nlipv6_verify_pppoe_rule( + */ + return 0; + } ++#endif + + /* + * nss_nlipv6_verify_igs_rule() +@@ -771,6 +777,7 @@ static int nss_nlipv6_ops_create_rule(st + goto done; + } + ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + /* + * check pppoe rule + */ +@@ -779,6 +786,7 @@ static int nss_nlipv6_ops_create_rule(st + nss_nl_error("%d:invalid pppoe rule information passed\n", pid); + goto done; + } ++#endif + + /* + * check qos rule +--- a/netlink/nss_nlipv6.h ++++ b/netlink/nss_nlipv6.h +@@ -26,7 +26,7 @@ + bool nss_nlipv6_init(void); + bool nss_nlipv6_exit(void); + +-#if defined(CONFIG_NSS_NLIPV6) ++#if defined(CONFIG_NSS_NLIPV6) && CONFIG_NSS_NLIPV6 > 0 + #define NSS_NLIPV6_INIT nss_nlipv6_init + #define NSS_NLIPV6_EXIT nss_nlipv6_exit + #else +--- a/netlink/nss_nlipv6_reasm.h ++++ b/netlink/nss_nlipv6_reasm.h +@@ -26,7 +26,7 @@ + bool nss_nlipv6_reasm_init(void); + bool nss_nlipv6_reasm_exit(void); + +-#if defined(CONFIG_NSS_NLIPV6_REASM) ++#if defined(CONFIG_NSS_NLIPV6_REASM) && CONFIG_NSS_NLIPV6_REASM > 0 + #define NSS_NLIPV6_REASM_INIT nss_nlipv6_reasm_init + #define NSS_NLIPV6_REASM_EXIT nss_nlipv6_reasm_exit + #else +--- a/netlink/nss_nll2tpv2.h ++++ b/netlink/nss_nll2tpv2.h +@@ -26,7 +26,7 @@ + bool nss_nll2tpv2_init(void); + bool nss_nll2tpv2_exit(void); + +-#if defined(CONFIG_NSS_NLL2TPV2) ++#if defined(CONFIG_NSS_NLL2TPV2) && CONFIG_NSS_NLL2TPV2 > 0 + #define NSS_NLL2TPV2_INIT nss_nll2tpv2_init + #define NSS_NLL2TPV2_EXIT nss_nll2tpv2_exit + #else +--- a/netlink/nss_nllso_rx.h ++++ b/netlink/nss_nllso_rx.h +@@ -26,7 +26,7 @@ + bool nss_nllso_rx_init(void); + bool nss_nllso_rx_exit(void); + +-#if defined(CONFIG_NSS_NLLSO_RX) ++#if defined(CONFIG_NSS_NLLSO_RX) && CONFIG_NSS_NLLSO_RX > 0 + #define NSS_NLLSO_RX_INIT nss_nllso_rx_init + #define NSS_NLLSO_RX_EXIT nss_nllso_rx_exit + #else +--- a/netlink/nss_nlmap_t.h ++++ b/netlink/nss_nlmap_t.h +@@ -26,7 +26,7 @@ + bool nss_nlmap_t_init(void); + bool nss_nlmap_t_exit(void); + +-#if defined(CONFIG_NSS_NLMAP_T) ++#if defined(CONFIG_NSS_NLMAP_T) && CONFIG_NSS_NLMAP_T > 0 + #define NSS_NLMAP_T_INIT nss_nlmap_t_init + #define NSS_NLMAP_T_EXIT nss_nlmap_t_exit + #else +--- a/netlink/nss_nln2h.h ++++ b/netlink/nss_nln2h.h +@@ -26,7 +26,7 @@ + bool nss_nln2h_init(void); + bool nss_nln2h_exit(void); + +-#if defined(CONFIG_NSS_NLN2H) ++#if defined(CONFIG_NSS_NLN2H) && CONFIG_NSS_NLN2H > 0 + #define NSS_NLN2H_INIT nss_nln2h_init + #define NSS_NLN2H_EXIT nss_nln2h_exit + #else +--- a/netlink/nss_nloam.h ++++ b/netlink/nss_nloam.h +@@ -25,7 +25,7 @@ + bool nss_nloam_init(void); + bool nss_nloam_exit(void); + +-#if defined(CONFIG_NSS_NLOAM) ++#if defined(CONFIG_NSS_NLOAM) && CONFIG_NSS_NLOAM > 0 + #define NSS_NLOAM_INIT nss_nloam_init + #define NSS_NLOAM_EXIT nss_nloam_exit + #else +--- a/netlink/nss_nlpppoe.h ++++ b/netlink/nss_nlpppoe.h +@@ -26,7 +26,7 @@ + bool nss_nlpppoe_init(void); + bool nss_nlpppoe_exit(void); + +-#if defined(CONFIG_NSS_NLPPPOE) ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + #define NSS_NLPPPOE_INIT nss_nlpppoe_init + #define NSS_NLPPPOE_EXIT nss_nlpppoe_exit + #else +--- a/netlink/nss_nlpptp.h ++++ b/netlink/nss_nlpptp.h +@@ -26,7 +26,7 @@ + bool nss_nlpptp_init(void); + bool nss_nlpptp_exit(void); + +-#if defined(CONFIG_NSS_NLPPTP) ++#if defined(CONFIG_NSS_NLPPTP) && CONFIG_NSS_NLPPTP > 0 + #define NSS_NLPPTP_INIT nss_nlpptp_init + #define NSS_NLPPTP_EXIT nss_nlpptp_exit + #else +--- a/netlink/nss_nlwifili.h ++++ b/netlink/nss_nlwifili.h +@@ -26,7 +26,7 @@ + bool nss_nlwifili_init(void); + bool nss_nlwifili_exit(void); + +-#if defined(CONFIG_NSS_NLWIFILI) ++#if defined(CONFIG_NSS_NLWIFILI) && CONFIG_NSS_NLWIFILI > 0 + #define NSS_NLWIFILI_INIT nss_nlwifili_init + #define NSS_NLWIFILI_EXIT nss_nlwifili_exit + #else +--- a/netlink/nss_nl.c ++++ b/netlink/nss_nl.c +@@ -287,15 +287,14 @@ static struct nss_nl_family family_handl + .valid = CONFIG_NSS_NLPPTP /* 1 or 0 */ + }, + { +- /* +- * NSS_NLUDP_ST +- */ +- .name = NSS_NLUDP_ST_FAMILY, /* udp_st */ +- .entry = NSS_NLUDP_ST_INIT, /* init */ +- .exit = NSS_NLUDP_ST_EXIT, /* exit */ +- .valid = CONFIG_NSS_NLUDP_ST /* 1 or 0 */ +- }, +- ++ /* ++ * NSS_NLUDP_ST ++ */ ++ .name = NSS_NLUDP_ST_FAMILY, /* udp_st */ ++ .entry = NSS_NLUDP_ST_INIT, /* init */ ++ .exit = NSS_NLUDP_ST_EXIT, /* exit */ ++ .valid = CONFIG_NSS_NLUDP_ST /* 1 or 0 */ ++ } + }; + + #define NSS_NL_FAMILY_HANDLER_SZ ARRAY_SIZE(family_handlers) diff --git a/qca-nss-clients/patches-11.4/0023-mirror-fix-makefile.patch b/qca-nss-clients/patches-11.4/0023-mirror-fix-makefile.patch new file mode 100644 index 0000000..a6c51af --- /dev/null +++ b/qca-nss-clients/patches-11.4/0023-mirror-fix-makefile.patch @@ -0,0 +1,10 @@ +--- a/mirror/Makefile ++++ b/mirror/Makefile +@@ -1,6 +1,6 @@ + # Makefile for NSS MIRROR + +-ccflags-y += $(NSS_CCFLAGS) -I$(obj)/../../exports ++ccflags-y += $(NSS_CCFLAGS) -I$(obj)/../exports + ccflags-y += -DNSS_MIRROR_DEBUG_LEVEL=2 + ccflags-y += -Wall -Werror + diff --git a/qca-nss-clients/patches-11.4/0024-switch-to-wifili.patch b/qca-nss-clients/patches-11.4/0024-switch-to-wifili.patch new file mode 100644 index 0000000..53832f3 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0024-switch-to-wifili.patch @@ -0,0 +1,93 @@ +--- a/match/nss_match_cmd.c ++++ b/match/nss_match_cmd.c +@@ -460,10 +460,10 @@ static int nss_match_cmd_procfs_reset_ne + char *cmd_buf = nss_match_data; + nss_tx_status_t nss_tx_status; + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); +- struct nss_ctx_instance *wifi_nss_ctx = nss_wifi_get_context(); ++ struct nss_ctx_instance *wifili_nss_ctx = nss_wifili_get_context(); + +- if (!nss_ctx || !wifi_nss_ctx) { +- pr_warn("%px: NSS Context not found. wifi_nss_ctx: %px. Reset nexthop failed", nss_ctx, wifi_nss_ctx); ++ if (!nss_ctx || !wifili_nss_ctx) { ++ pr_warn("%px: NSS Context not found. wifili_nss_ctx: %px. Reset nexthop failed", nss_ctx, wifili_nss_ctx); + return -ENOMEM; + } + +@@ -495,9 +495,9 @@ static int nss_match_cmd_procfs_reset_ne + * nss_phys_if_reset_nexthop: Used for physical interfaces. + * nss_if_reset_nexthop: used for VAP interfaces. + */ +- type = nss_dynamic_interface_get_type(wifi_nss_ctx, if_num); ++ type = nss_dynamic_interface_get_type(wifili_nss_ctx, if_num); + if (type == NSS_DYNAMIC_INTERFACE_TYPE_VAP) { +- nss_tx_status = nss_if_reset_nexthop(wifi_nss_ctx, if_num); ++ nss_tx_status = nss_if_reset_nexthop(wifili_nss_ctx, if_num); + } else if (if_num < NSS_MAX_PHYSICAL_INTERFACES) { + nss_tx_status = nss_phys_if_reset_nexthop(nss_ctx, if_num); + } else { +@@ -528,7 +528,7 @@ static int nss_match_cmd_procfs_set_if_n + uint32_t nh_if_num; + int table_id; + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); +- struct nss_ctx_instance *wifi_nss_ctx = nss_wifi_get_context(); ++ struct nss_ctx_instance *wifili_nss_ctx = nss_wifili_get_context(); + char *dev_name, *nexthop_msg; + char *cmd_buf = NULL; + size_t count = *lenp; +@@ -539,8 +539,8 @@ static int nss_match_cmd_procfs_set_if_n + return ret; + } + +- if (!nss_ctx || !wifi_nss_ctx) { +- pr_warn("%px: NSS Context not found. wifi_nss_ctx: %px. Set nexthop failed", nss_ctx, wifi_nss_ctx); ++ if (!nss_ctx || !wifili_nss_ctx) { ++ pr_warn("%px: NSS Context not found. wifili_nss_ctx: %px. Set nexthop failed", nss_ctx, wifili_nss_ctx); + return -ENOMEM; + } + +@@ -607,9 +607,9 @@ static int nss_match_cmd_procfs_set_if_n + * nss_phys_if_set_nexthop: Used for physical interfaces. + * nss_if_set_nexthop: used for VAP interfaces. + */ +- type = nss_dynamic_interface_get_type(wifi_nss_ctx, if_num); ++ type = nss_dynamic_interface_get_type(wifili_nss_ctx, if_num); + if (type == NSS_DYNAMIC_INTERFACE_TYPE_VAP) { +- nss_tx_status = nss_if_set_nexthop(wifi_nss_ctx, if_num, nh_if_num); ++ nss_tx_status = nss_if_set_nexthop(wifili_nss_ctx, if_num, nh_if_num); + } else if (if_num < NSS_MAX_PHYSICAL_INTERFACES) { + nss_tx_status = nss_phys_if_set_nexthop(nss_ctx, if_num, nh_if_num); + } else { +--- a/gre/nss_connmgr_gre.c ++++ b/gre/nss_connmgr_gre.c +@@ -1672,7 +1672,7 @@ int nss_connmgr_gre_set_wifi_next_hop(st + return GRE_ERR_NEXT_NODE_UNREG_IN_AE; + } + +- ctx = nss_wifi_get_context(); ++ ctx = nss_wifili_get_context(); + status = nss_wifi_vdev_set_next_hop(ctx, ifnumber, NSS_GRE_INTERFACE); + if (status != NSS_TX_SUCCESS) { + nss_connmgr_gre_info("%px: wifi drv api failed to set next hop\n", wifi_vdev); +--- a/mirror/nss_mirror_ctl.c ++++ b/mirror/nss_mirror_ctl.c +@@ -480,7 +480,7 @@ static int nss_mirror_ctl_parse_enable_i + type = nss_dynamic_interface_get_type(nss_ctx, if_num); + + if (type == NSS_DYNAMIC_INTERFACE_TYPE_VAP) { +- status = nss_wifi_vdev_set_next_hop(nss_wifi_get_context(), if_num, mirror_if_num); ++ status = nss_wifi_vdev_set_next_hop(nss_wifili_get_context(), if_num, mirror_if_num); + } else if (if_num < NSS_MAX_PHYSICAL_INTERFACES) { + status = nss_phys_if_set_nexthop(nss_ctx, if_num, mirror_if_num); + } else { +--- a/netlink/nss_nlgre_redir_cmn.c ++++ b/netlink/nss_nlgre_redir_cmn.c +@@ -905,7 +905,7 @@ int nss_nlgre_redir_cmn_set_next_hop(uin + } + + nss_nl_info("%px: next hop interface number is %d\n", nss_ctx, next_dev_ifnum); +- ctx = nss_wifi_get_context(); ++ ctx = nss_wifili_get_context(); + + ret = nss_wifi_vdev_set_next_hop(ctx, ifnumber, next_dev_ifnum); + if (ret != NSS_TX_SUCCESS) { diff --git a/qca-nss-clients/patches-11.4/0025-nss-clients-add-kernel-6.6-support.patch b/qca-nss-clients/patches-11.4/0025-nss-clients-add-kernel-6.6-support.patch new file mode 100644 index 0000000..f24f9fc --- /dev/null +++ b/qca-nss-clients/patches-11.4/0025-nss-clients-add-kernel-6.6-support.patch @@ -0,0 +1,274 @@ +--- a/bridge/nss_bridge_mgr.c ++++ b/bridge/nss_bridge_mgr.c +@@ -1329,7 +1329,6 @@ static struct notifier_block nss_bridge_ + .notifier_call = nss_bridge_mgr_netdevice_event, + }; + +-#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT) + /* + * nss_bridge_mgr_is_physical_dev() + * Check if the device is on physical device. +@@ -1558,25 +1557,6 @@ static struct ctl_table nss_bridge_mgr_t + { } + }; + +-static struct ctl_table nss_bridge_mgr_dir[] = { +- { +- .procname = "bridge_mgr", +- .mode = 0555, +- .child = nss_bridge_mgr_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_bridge_mgr_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_bridge_mgr_dir, +- }, +- { } +-}; +-#endif +- + /* + * nss_bridge_mgr_init_module() + * bridge_mgr module init function +@@ -1596,7 +1576,7 @@ int __init nss_bridge_mgr_init_module(vo + #if defined(NSS_BRIDGE_MGR_PPE_SUPPORT) + br_mgr_ctx.wan_if_num = -1; + br_fdb_update_register_notify(&nss_bridge_mgr_fdb_update_notifier); +- br_mgr_ctx.nss_bridge_mgr_header = register_sysctl_table(nss_bridge_mgr_root_dir); ++ br_mgr_ctx.nss_bridge_mgr_header = register_sysctl("nss/bridge_mgr", nss_bridge_mgr_table); + + /* + * Enable ACL rule to enable L2 exception. This is needed if PPE Virtual ports is added to bridge. +--- a/gre/nss_connmgr_gre.c ++++ b/gre/nss_connmgr_gre.c +@@ -277,7 +277,7 @@ static struct rtnl_link_stats64 *nss_con + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) + start = u64_stats_fetch_begin_bh(&tstats->syncp); + #else +- start = u64_stats_fetch_begin_irq(&tstats->syncp); ++ start = u64_stats_fetch_begin(&tstats->syncp); + #endif + rx_packets = u64_stats_read(&tstats->rx_packets); + tx_packets = u64_stats_read(&tstats->tx_packets); +@@ -286,7 +286,7 @@ static struct rtnl_link_stats64 *nss_con + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) + } while (u64_stats_fetch_retry_bh(&tstats->syncp, start)); + #else +- } while (u64_stats_fetch_retry_irq(&tstats->syncp, start)); ++ } while (u64_stats_fetch_retry(&tstats->syncp, start)); + #endif + + tot->rx_packets += rx_packets; +--- a/vlan/nss_vlan_mgr.c ++++ b/vlan/nss_vlan_mgr.c +@@ -1544,30 +1544,6 @@ static struct ctl_table nss_vlan_table[] + }; + + /* +- * nss_vlan sysctl dir +- */ +-static struct ctl_table nss_vlan_dir[] = { +- { +- .procname = "vlan_client", +- .mode = 0555, +- .child = nss_vlan_table, +- }, +- { } +-}; +- +-/* +- * nss_vlan systel root dir +- */ +-static struct ctl_table nss_vlan_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_vlan_dir, +- }, +- { } +-}; +- +-/* + * nss_vlan_mgr_add_bond_slave() + * Add new slave port to bond_vlan + */ +@@ -1906,7 +1882,7 @@ int __init nss_vlan_mgr_init_module(void + vlan_mgr_ctx.stpid = ETH_P_8021Q; + + #ifdef NSS_VLAN_MGR_PPE_SUPPORT +- vlan_mgr_ctx.sys_hdr = register_sysctl_table(nss_vlan_root_dir); ++ vlan_mgr_ctx.sys_hdr = register_sysctl("nss/vlan_client", nss_vlan_table); + if (!vlan_mgr_ctx.sys_hdr) { + nss_vlan_mgr_warn("Unabled to register sysctl table for vlan manager\n"); + return -EFAULT; +--- a/match/nss_match_cmd.c ++++ b/match/nss_match_cmd.c +@@ -692,33 +692,6 @@ static struct ctl_table nss_match_table[ + { } + }; + +-static struct ctl_table nss_match_root_dir[] = { +- { +- .procname = "match", +- .mode = 0555, +- .child = nss_match_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_match_nss_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_match_root_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_match_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_match_nss_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_match_ctl_header; + + /* +@@ -726,7 +699,7 @@ static struct ctl_table_header *nss_matc + * Register command line interface for match. + */ + bool nss_match_ctl_register(void) { +- nss_match_ctl_header = register_sysctl_table(nss_match_root); ++ nss_match_ctl_header = register_sysctl("dev/nss/match", nss_match_table); + if (!nss_match_ctl_header) { + nss_match_warn("Unable to register command line interface.\n"); + return false; +--- a/tunipip6/nss_connmgr_tunipip6_sysctl.c ++++ b/tunipip6/nss_connmgr_tunipip6_sysctl.c +@@ -449,33 +449,6 @@ static struct ctl_table nss_tunipip6_tab + { } + }; + +-static struct ctl_table nss_tunipip6_root_dir[] = { +- { +- .procname = "ipip6", +- .mode = 0555, +- .child = nss_tunipip6_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_tunipip6_nss_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_tunipip6_root_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_tunipip6_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_tunipip6_nss_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_tunipip6_ctl_header; + + /* +@@ -483,7 +456,7 @@ static struct ctl_table_header *nss_tuni + * Register command line interface for tunipip6. + */ + bool nss_tunipip6_sysctl_register(void) { +- nss_tunipip6_ctl_header = register_sysctl_table(nss_tunipip6_root); ++ nss_tunipip6_ctl_header = register_sysctl("drv/nss/ipip6", nss_tunipip6_table); + if (!nss_tunipip6_ctl_header) { + return false; + } +--- a/mirror/nss_mirror_ctl.c ++++ b/mirror/nss_mirror_ctl.c +@@ -919,48 +919,12 @@ static struct ctl_table nss_mirror_table + }; + + /* +- * nss mirror dir +- */ +-static struct ctl_table nss_mirror_root_dir[] = { +- { +- .procname = "mirror", +- .mode = 0555, +- .child = nss_mirror_table, +- }, +- { } +-}; +- +-/* +- * nss mirror sysctl nss root dir +- */ +-static struct ctl_table nss_mirror_nss_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_mirror_root_dir, +- }, +- { } +-}; +- +-/* +- * nss mirror sysctl root dir +- */ +-static struct ctl_table nss_mirror_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_mirror_nss_root_dir, +- }, +- { } +-}; +- +-/* + * nss_mirror_ctl_register() + * Register command line interface for mirror. + */ + int nss_mirror_ctl_register(void) + { +- nss_mirror_ctl_header = register_sysctl_table(nss_mirror_root); ++ nss_mirror_ctl_header = register_sysctl("dev/nss/mirror", nss_mirror_table); + if (!nss_mirror_ctl_header) { + nss_mirror_warn("Creating sysctl directory table header for mirror failed\n"); + return -1; +--- a/l2tp/l2tpv2/nss_connmgr_l2tpv2.c ++++ b/l2tp/l2tpv2/nss_connmgr_l2tpv2.c +@@ -1036,7 +1036,7 @@ int __init nss_connmgr_l2tpv2_init_modul + } + #endif + #if defined(NSS_L2TP_IPSEC_BIND_BY_NETDEV) +- ctl_tbl_hdr = register_sysctl_table(nss_connmgr_l2tpv2_sysroot); ++ ctl_tbl_hdr = register_sysctl("dev/nss/l2tpv2", nss_connmgr_l2tpv2_table); + if (!ctl_tbl_hdr) { + nss_connmgr_l2tpv2_info("Unable to register sysctl table for L2TP conn mgr\n"); + return -EFAULT; +--- a/netlink/nss_nl.c ++++ b/netlink/nss_nl.c +@@ -462,7 +462,11 @@ struct nss_nlcmn *nss_nl_get_msg(struct + /* + * validate the common message header version & magic + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 6, 0)) + cm = info->userhdr; ++#else ++ cm = genl_info_userhdr(info); ++#endif + if (nss_nlcmn_chk_ver(cm, family->version) == false) { + nss_nl_error("%d, %s: version mismatch (%d)\n", pid, family->name, cm->version); + return NULL; diff --git a/qca-nss-clients/patches-11.4/0026-qdisc-backport-12.4.patch b/qca-nss-clients/patches-11.4/0026-qdisc-backport-12.4.patch new file mode 100644 index 0000000..a16fc4c --- /dev/null +++ b/qca-nss-clients/patches-11.4/0026-qdisc-backport-12.4.patch @@ -0,0 +1,330 @@ +--- a/nss_qdisc/nss_bf.c ++++ b/nss_qdisc/nss_bf.c +@@ -331,10 +331,19 @@ static int nss_bf_delete_class(struct Qd + qdisc_class_hash_remove(&q->clhash, &cl->cl_common); + refcnt = nss_qdisc_atomic_sub_return(&cl->nq); + sch_tree_unlock(sch); ++ ++ /* ++ * For 5.4 and above kernels, calling nss_htb_destroy_class ++ * explicitly as there is no put_class which would have called ++ * nss_bf_destroy_class when refcnt becomes zero. ++ */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) ++ nss_bf_destroy_class(sch, cl); ++#else + if (!refcnt) { + nss_qdisc_error("Reference count should not be zero for class %px\n", cl); + } +- ++#endif + return 0; + } + +@@ -634,6 +643,11 @@ static int nss_bf_change_qdisc(struct Qd + */ + static void nss_bf_reset_class(struct nss_bf_class_data *cl) + { ++ if (cl->qdisc == &noop_qdisc) { ++ nss_qdisc_trace("Class %x has no child qdisc to reset\n", cl->nq.qos_tag); ++ return; ++ } ++ + nss_qdisc_reset(cl->qdisc); + nss_qdisc_info("Nssbf class resetted %px\n", cl->qdisc); + } +--- a/nss_qdisc/nss_htb.c ++++ b/nss_qdisc/nss_htb.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2014-2017, 2019-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2014-2017, 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -574,10 +574,16 @@ static int nss_htb_delete_class(struct Q + /* + * If we are root class, we dont have to update our parent. + * We simply deduct refcnt and return. ++ * For 5.4 and above kernels, calling nss_htb_destroy_class ++ * explicitly as there is no put_class which would have called ++ * nss_htb_destroy_class when refcnt becomes zero. + */ + if (!cl->parent) { + refcnt = nss_qdisc_atomic_sub_return(&cl->nq); + sch_tree_unlock(sch); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) ++ nss_htb_destroy_class(sch, cl); ++#endif + return 0; + } + +@@ -596,6 +602,14 @@ static int nss_htb_delete_class(struct Q + refcnt = nss_qdisc_atomic_sub_return(&cl->nq); + sch_tree_unlock(sch); + ++ /* ++ * For 5.4 and above kernels, calling nss_htb_destroy_class ++ * explicitly as there is no put_class which would have called ++ * nss_htb_destroy_class when refcnt becomes zero. ++ */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) ++ nss_htb_destroy_class(sch, cl); ++#endif + return 0; + } + +@@ -898,6 +912,11 @@ static int nss_htb_change_qdisc(struct Q + */ + static void nss_htb_reset_class(struct nss_htb_class_data *cl) + { ++ if (cl->qdisc == &noop_qdisc) { ++ nss_qdisc_trace("Class %x has no child qdisc to reset\n", cl->nq.qos_tag); ++ return; ++ } ++ + nss_qdisc_reset(cl->qdisc); + nss_qdisc_trace("htb class %x reset\n", cl->nq.qos_tag); + } +--- a/nss_qdisc/nss_qdisc.c ++++ b/nss_qdisc/nss_qdisc.c +@@ -30,9 +30,6 @@ + + void *nss_qdisc_ctx; /* Shaping context for nss_qdisc */ + +-#define NSS_QDISC_COMMAND_TIMEOUT (10*HZ) /* We set 10sec to be the command */ +- /* timeout value for messages */ +- + /* + * Defines related to root hash maintenance + */ +@@ -40,6 +37,53 @@ void *nss_qdisc_ctx; /* Shaping contex + #define NSS_QDISC_ROOT_HASH_MASK (NSS_QDISC_ROOT_HASH_SIZE - 1) + + /* ++ * nss_qdisc_get_interface_msg() ++ * Returns the correct message that needs to be sent down to the NSS interface. ++ */ ++int nss_qdisc_get_interface_msg(bool is_bridge, uint32_t msg_type) ++{ ++ /* ++ * We re-assign the message based on whether this is for the I shaper ++ * or the B shaper. The is_bridge flag tells if we are on a bridge interface. ++ */ ++ if (is_bridge) { ++ switch (msg_type) { ++ case NSS_QDISC_IF_SHAPER_ASSIGN: ++ return NSS_IF_BSHAPER_ASSIGN; ++ case NSS_QDISC_IF_SHAPER_UNASSIGN: ++ return NSS_IF_BSHAPER_UNASSIGN; ++ case NSS_QDISC_IF_SHAPER_CONFIG: ++ return NSS_IF_BSHAPER_CONFIG; ++ default: ++ nss_qdisc_info("Unknown message type for a bridge - type %d", msg_type); ++ return -1; ++ } ++ } else { ++ switch (msg_type) { ++ case NSS_QDISC_IF_SHAPER_ASSIGN: ++ return NSS_IF_ISHAPER_ASSIGN; ++ case NSS_QDISC_IF_SHAPER_UNASSIGN: ++ return NSS_IF_ISHAPER_UNASSIGN; ++ case NSS_QDISC_IF_SHAPER_CONFIG: ++ return NSS_IF_ISHAPER_CONFIG; ++ default: ++ nss_qdisc_info("Unknown message type for an interface - type %d", msg_type); ++ return -1; ++ } ++ } ++} ++ ++/* ++ * nss_qdisc_msg_init() ++ * Initialize the qdisc specific message ++ */ ++void nss_qdisc_msg_init(struct nss_if_msg *nim, uint16_t if_num, uint32_t msg_type, uint32_t len, ++ nss_if_msg_callback_t cb, void *app_data) ++{ ++ nss_cmn_msg_init(&nim->cm, if_num, msg_type, len, (void *)cb, app_data); ++} ++ ++/* + * nss_qdisc_interface_is_virtual() + * Return true if it is redirect or bridge interface. + */ +@@ -122,53 +166,6 @@ static int nss_qdisc_ppe_init(struct Qdi + #endif + + /* +- * nss_qdisc_msg_init() +- * Initialize the qdisc specific message +- */ +-static void nss_qdisc_msg_init(struct nss_if_msg *nim, uint16_t if_num, uint32_t msg_type, uint32_t len, +- nss_if_msg_callback_t cb, void *app_data) +-{ +- nss_cmn_msg_init(&nim->cm, if_num, msg_type, len, (void*)cb, app_data); +-} +- +-/* +- * nss_qdisc_get_interface_msg() +- * Returns the correct message that needs to be sent down to the NSS interface. +- */ +-static inline int nss_qdisc_get_interface_msg(bool is_bridge, uint32_t msg_type) +-{ +- /* +- * We re-assign the message based on whether this is for the I shaper +- * or the B shaper. The is_bridge flag tells if we are on a bridge interface. +- */ +- if (is_bridge) { +- switch(msg_type) { +- case NSS_QDISC_IF_SHAPER_ASSIGN: +- return NSS_IF_BSHAPER_ASSIGN; +- case NSS_QDISC_IF_SHAPER_UNASSIGN: +- return NSS_IF_BSHAPER_UNASSIGN; +- case NSS_QDISC_IF_SHAPER_CONFIG: +- return NSS_IF_BSHAPER_CONFIG; +- default: +- nss_qdisc_info("Unknown message type for a bridge - type %d", msg_type); +- return -1; +- } +- } else { +- switch(msg_type) { +- case NSS_QDISC_IF_SHAPER_ASSIGN: +- return NSS_IF_ISHAPER_ASSIGN; +- case NSS_QDISC_IF_SHAPER_UNASSIGN: +- return NSS_IF_ISHAPER_UNASSIGN; +- case NSS_QDISC_IF_SHAPER_CONFIG: +- return NSS_IF_ISHAPER_CONFIG; +- default: +- nss_qdisc_info("Unknown message type for an interface - type %d", msg_type); +- return -1; +- } +- } +-} +- +-/* + * nss_qdisc_attach_bshaper_callback() + * Call back funtion for bridge shaper attach to an interface. + */ +@@ -613,7 +610,6 @@ static void nss_qdisc_root_cleanup_free_ + nss_qdisc_info("Root qdisc %px (type %d) free SUCCESS - response " + "type: %d\n", nq->qdisc, nq->type, + nim->msg.shaper_configure.config.response_type); +- + nss_qdisc_root_cleanup_shaper_unassign(nq); + } + +@@ -1168,8 +1164,15 @@ unsigned int nss_qdisc_drop(struct Qdisc + */ + void nss_qdisc_reset(struct Qdisc *sch) + { +- struct nss_qdisc *nq = qdisc_priv(sch); ++ struct nss_qdisc *nq; + ++ if(!(sch->flags & TCQ_F_NSS)) { ++ qdisc_reset_queue(sch); ++ nss_qdisc_info("Qdisc %px resetting non NSS qdisc\n", sch); ++ return; ++ } ++ ++ nq = qdisc_priv(sch); + nss_qdisc_info("Qdisc %px (type %d) resetting\n", + sch, nq->type); + +@@ -1891,6 +1894,7 @@ int nss_qdisc_configure(struct nss_qdisc + return 0; + } + ++ + /* + * nss_qdisc_register_configure_callback() + * Register shaper configure callback, which gets invoked on receiving a response. +@@ -2117,6 +2121,8 @@ int __nss_qdisc_init(struct Qdisc *sch, + */ + if ((sch->parent == TC_H_ROOT) && (!nq->is_class)) { + nss_qdisc_info("Qdisc %px (type %d) is root\n", nq->qdisc, nq->type); ++ nss_qdisc_info("Qdisc %px dev-name %s qdisc_dev(sch)->qdisc %px, qdisc_dev(sch)->qdisc->handle %x\n", qdisc_dev(sch), qdisc_dev(sch)->name, qdisc_dev(sch)->qdisc, qdisc_dev(sch)->qdisc->handle); ++ nss_qdisc_info("Qdisc %px (sch %px) is root, sch->handle %x\n", nq->qdisc, sch, sch->handle); + nq->is_root = true; + root = sch; + } else { +--- a/nss_qdisc/nss_qdisc.h ++++ b/nss_qdisc/nss_qdisc.h +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2014-2018, 2020 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -41,6 +41,9 @@ + #define NSS_QDISC_DEBUG_LEVEL_INFO 3 + #define NSS_QDISC_DEBUG_LEVEL_TRACE 4 + ++#define NSS_QDISC_COMMAND_TIMEOUT (10*HZ) /* We set 10sec to be the command */ ++ /* timeout value for messages */ ++ + /* + * Debug message for module init and exit + */ +@@ -486,3 +489,15 @@ extern unsigned long nss_qdisc_tcf_bind( + * Unbind the filter from the qdisc. + */ + extern void nss_qdisc_tcf_unbind(struct Qdisc *sch, unsigned long arg); ++ ++/* ++ * nss_qdisc_get_interface_msg() ++ * Returns the correct message that needs to be sent down to the NSS interface. ++ */ ++extern int nss_qdisc_get_interface_msg(bool is_bridge, uint32_t msg_type); ++ ++/* ++ * nss_qdisc_msg_init() ++ * Initialize the qdisc specific message ++ */ ++extern void nss_qdisc_msg_init(struct nss_if_msg *nim, uint16_t if_num, uint32_t msg_type, uint32_t len, nss_if_msg_callback_t cb, void *app_data); +--- a/nss_qdisc/nss_wrr.c ++++ b/nss_qdisc/nss_wrr.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2014-2017, 2019-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2014-2017, 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -442,10 +442,19 @@ static int nss_wrr_delete_class(struct Q + refcnt = nss_qdisc_atomic_sub_return(&cl->nq); + + sch_tree_unlock(sch); ++ ++ /* ++ * For 5.4 and above kernels, calling nss_htb_destroy_class ++ * explicitly as there is no put_class which would have called ++ * nss_wrr_destroy_class when refcnt becomes zero. ++ */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) ++ nss_wrr_destroy_class(sch, cl); ++#else + if (!refcnt) { + nss_qdisc_error("Reference count should not be zero for class %px\n", cl); + } +- ++#endif + return 0; + } + +@@ -764,6 +773,11 @@ static int nss_wrr_change_qdisc(struct Q + + static void nss_wrr_reset_class(struct nss_wrr_class_data *cl) + { ++ if (cl->qdisc == &noop_qdisc) { ++ nss_qdisc_trace("Class %x has no child qdisc to reset\n", cl->nq.qos_tag); ++ return; ++ } ++ + nss_qdisc_reset(cl->qdisc); + nss_qdisc_info("Nsswrr class resetted %px\n", cl->qdisc); + } diff --git a/qca-nss-clients/patches-11.4/0027-bridge-backport-12.5.patch b/qca-nss-clients/patches-11.4/0027-bridge-backport-12.5.patch new file mode 100644 index 0000000..1841b76 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0027-bridge-backport-12.5.patch @@ -0,0 +1,303 @@ +--- a/bridge/nss_bridge_mgr.c ++++ b/bridge/nss_bridge_mgr.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -49,6 +52,11 @@ static bool ovs_enabled = false; + static struct nss_bridge_mgr_context br_mgr_ctx; + + /* ++ * Module parameter to enable/disable FDB learning. ++ */ ++static bool fdb_disabled = false; ++ ++/* + * nss_bridge_mgr_create_instance() + * Create a bridge instance. + */ +@@ -415,6 +423,37 @@ static int nss_bridge_mgr_del_bond_slave + } + + /* ++ * nss_bridge_mgr_bond_fdb_join() ++ * Update FDB state when a bond interface joining bridge. ++ */ ++static int nss_bridge_mgr_bond_fdb_join(struct nss_bridge_pvt *b_pvt) ++{ ++ /* ++ * If already other bond devices are attached to bridge, ++ * only increment bond_slave_num, ++ */ ++ spin_lock(&br_mgr_ctx.lock); ++ if (b_pvt->bond_slave_num) { ++ b_pvt->bond_slave_num++; ++ spin_unlock(&br_mgr_ctx.lock); ++ return NOTIFY_DONE; ++ } ++ b_pvt->bond_slave_num = 1; ++ spin_unlock(&br_mgr_ctx.lock); ++ ++ /* ++ * This is the first bond device being attached to bridge. In order to enforce Linux ++ * bond slave selection in bridge flows involving bond interfaces, we need to disable ++ * fdb learning on this bridge master to allow flow based bridging. ++ */ ++ if (nss_bridge_mgr_disable_fdb_learning(b_pvt) < 0) { ++ return NOTIFY_BAD; ++ } ++ ++ return NOTIFY_DONE; ++} ++ ++/* + * nss_bridge_mgr_bond_master_join() + * Add a bond interface to bridge + */ +@@ -447,28 +486,7 @@ static int nss_bridge_mgr_bond_master_jo + } + } + +- /* +- * If already other bond devices are attached to bridge, +- * only increment bond_slave_num, +- */ +- spin_lock(&br_mgr_ctx.lock); +- if (b_pvt->bond_slave_num) { +- b_pvt->bond_slave_num++; +- spin_unlock(&br_mgr_ctx.lock); +- return NOTIFY_DONE; +- } +- spin_unlock(&br_mgr_ctx.lock); +- +- /* +- * This is the first bond device being attached to bridge. In order to enforce Linux +- * bond slave selection in bridge flows involving bond interfaces, we need to disable +- * fdb learning on this bridge master to allow flow based bridging. +- */ +- if (!nss_bridge_mgr_disable_fdb_learning(b_pvt)) { +- spin_lock(&br_mgr_ctx.lock); +- b_pvt->bond_slave_num = 1; +- spin_unlock(&br_mgr_ctx.lock); +- ++ if (nss_bridge_mgr_bond_fdb_join(b_pvt) == NOTIFY_DONE) { + return NOTIFY_DONE; + } + +@@ -488,6 +506,41 @@ cleanup: + } + + /* ++ * nss_bridge_mgr_bond_fdb_leave() ++ * Update FDB state when a bond interface leaving bridge. ++ */ ++static int nss_bridge_mgr_bond_fdb_leave(struct nss_bridge_pvt *b_pvt) ++{ ++ ++ nss_bridge_mgr_assert(b_pvt->bond_slave_num == 0); ++ ++ /* ++ * If more than one bond devices are attached to bridge, ++ * only decrement the bond_slave_num ++ */ ++ spin_lock(&br_mgr_ctx.lock); ++ if (b_pvt->bond_slave_num > 1) { ++ b_pvt->bond_slave_num--; ++ spin_unlock(&br_mgr_ctx.lock); ++ return NOTIFY_DONE; ++ } ++ b_pvt->bond_slave_num = 0; ++ spin_unlock(&br_mgr_ctx.lock); ++ ++ /* ++ * The last bond interface is removed from bridge, we can switch back to FDB ++ * learning mode. ++ */ ++ if (!fdb_disabled && (nss_bridge_mgr_enable_fdb_learning(b_pvt) < 0)) { ++ nss_bridge_mgr_warn("%px: Failed to enable fdb learning. fdb_disabled: %d\n", b_pvt, fdb_disabled); ++ return NOTIFY_BAD; ++ } ++ ++ return NOTIFY_DONE; ++} ++ ++ ++/* + * nss_bridge_mgr_bond_master_leave() + * Remove a bond interface from bridge + */ +@@ -516,27 +569,7 @@ static int nss_bridge_mgr_bond_master_le + } + } + +- /* +- * If more than one bond devices are attached to bridge, +- * only decrement the bond_slave_num +- */ +- spin_lock(&br_mgr_ctx.lock); +- if (b_pvt->bond_slave_num > 1) { +- b_pvt->bond_slave_num--; +- spin_unlock(&br_mgr_ctx.lock); +- return NOTIFY_DONE; +- } +- spin_unlock(&br_mgr_ctx.lock); +- +- /* +- * The last bond interface is removed from bridge, we can switch back to FDB +- * learning mode. +- */ +- if (!nss_bridge_mgr_enable_fdb_learning(b_pvt)) { +- spin_lock(&br_mgr_ctx.lock); +- b_pvt->bond_slave_num = 0; +- spin_unlock(&br_mgr_ctx.lock); +- ++ if (nss_bridge_mgr_bond_fdb_leave(b_pvt) == NOTIFY_DONE) { + return NOTIFY_DONE; + } + +@@ -803,9 +836,10 @@ int nss_bridge_mgr_join_bridge(struct ne + } + + /* +- * Add the bond_master to bridge. ++ * Update FDB state of the bridge. No need to add individual interfaces of bond to the bridge. ++ * VLAN interface verifies that all interfaces are physical so, no need to verify again. + */ +- if (nss_bridge_mgr_bond_master_join(real_dev, br) != NOTIFY_DONE) { ++ if (nss_bridge_mgr_bond_fdb_join(br) != NOTIFY_DONE) { + nss_bridge_mgr_warn("%px: Slaves of bond interface %s join bridge failed\n", br, real_dev->name); + nss_bridge_tx_leave_msg(br->ifnum, dev); + nss_vlan_mgr_leave_bridge(dev, br->vsi); +@@ -905,9 +939,10 @@ int nss_bridge_mgr_leave_bridge(struct n + } + + /* +- * Remove the bond_master from bridge. ++ * Update FDB state of the bridge. No need to add individual interfaces of bond to the bridge. ++ * VLAN interface verifies that all interfaces are physical so, no need to verify again. + */ +- if (nss_bridge_mgr_bond_master_leave(real_dev, br) != NOTIFY_DONE) { ++ if (nss_bridge_mgr_bond_fdb_leave(br) != NOTIFY_DONE) { + nss_bridge_mgr_warn("%px: Slaves of bond interface %s leave bridge failed\n", br, real_dev->name); + nss_vlan_mgr_join_bridge(dev, br->vsi); + nss_bridge_tx_join_msg(br->ifnum, dev); +@@ -1017,44 +1052,45 @@ int nss_bridge_mgr_register_br(struct ne + + b_pvt->dev = dev; + ++#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT) ++ err = ppe_vsi_alloc(NSS_BRIDGE_MGR_SWITCH_ID, &vsi_id); ++ if (err) { ++ nss_bridge_mgr_warn("%px: failed to alloc bridge vsi, error = %d\n", b_pvt, err); ++ goto fail; ++ } ++ ++ b_pvt->vsi = vsi_id; ++#endif ++ + ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_BRIDGE); + if (ifnum < 0) { + nss_bridge_mgr_warn("%px: failed to alloc bridge di\n", b_pvt); +- nss_bridge_mgr_delete_instance(b_pvt); +- return -EFAULT; ++ goto fail_1; + } + + if (!nss_bridge_register(ifnum, dev, NULL, NULL, 0, b_pvt)) { + nss_bridge_mgr_warn("%px: failed to register bridge di to NSS\n", b_pvt); +- goto fail; ++ goto fail_2; + } + + #if defined(NSS_BRIDGE_MGR_PPE_SUPPORT) +- err = ppe_vsi_alloc(NSS_BRIDGE_MGR_SWITCH_ID, &vsi_id); +- if (err) { +- nss_bridge_mgr_warn("%px: failed to alloc bridge vsi, error = %d\n", b_pvt, err); +- goto fail_1; +- } +- +- b_pvt->vsi = vsi_id; +- + err = nss_bridge_tx_vsi_assign_msg(ifnum, vsi_id); + if (err != NSS_TX_SUCCESS) { + nss_bridge_mgr_warn("%px: failed to assign vsi msg, error = %d\n", b_pvt, err); +- goto fail_2; ++ goto fail_3; + } + #endif + + err = nss_bridge_tx_set_mac_addr_msg(ifnum, dev->dev_addr); + if (err != NSS_TX_SUCCESS) { + nss_bridge_mgr_warn("%px: failed to set mac_addr msg, error = %d\n", b_pvt, err); +- goto fail_3; ++ goto fail_4; + } + + err = nss_bridge_tx_set_mtu_msg(ifnum, dev->mtu); + if (err != NSS_TX_SUCCESS) { + nss_bridge_mgr_warn("%px: failed to set mtu msg, error = %d\n", b_pvt, err); +- goto fail_3; ++ goto fail_4; + } + + /* +@@ -1076,31 +1112,35 @@ int nss_bridge_mgr_register_br(struct ne + * Disable FDB learning if OVS is enabled for + * all bridges (including Linux bridge). + */ +- if (ovs_enabled) { ++ if (ovs_enabled || fdb_disabled) { + nss_bridge_mgr_disable_fdb_learning(b_pvt); + } + #endif + return 0; + +-fail_3: ++fail_4: + #if defined(NSS_BRIDGE_MGR_PPE_SUPPORT) + if (nss_bridge_tx_vsi_unassign_msg(ifnum, vsi_id) != NSS_TX_SUCCESS) { + nss_bridge_mgr_warn("%px: failed to unassign vsi\n", b_pvt); + } +- +-fail_2: +- ppe_vsi_free(NSS_BRIDGE_MGR_SWITCH_ID, vsi_id); +- +-fail_1: ++fail_3: + #endif ++ + nss_bridge_unregister(ifnum); + +-fail: ++fail_2: + if (nss_dynamic_interface_dealloc_node(ifnum, NSS_DYNAMIC_INTERFACE_TYPE_BRIDGE) != NSS_TX_SUCCESS) { + nss_bridge_mgr_warn("%px: failed to dealloc bridge di\n", b_pvt); + } + ++fail_1: ++#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT) ++ ppe_vsi_free(NSS_BRIDGE_MGR_SWITCH_ID, vsi_id); ++fail: ++#endif ++ + nss_bridge_mgr_delete_instance(b_pvt); ++ + return -EFAULT; + } + +@@ -1626,3 +1666,6 @@ MODULE_DESCRIPTION("NSS bridge manager") + + module_param(ovs_enabled, bool, 0644); + MODULE_PARM_DESC(ovs_enabled, "OVS bridge is enabled"); ++ ++module_param(fdb_disabled, bool, 0644); ++MODULE_PARM_DESC(fdb_disabled, "fdb learning is disabled"); diff --git a/qca-nss-clients/patches-11.4/0027-capwapmgr-backport-12.5.patch b/qca-nss-clients/patches-11.4/0027-capwapmgr-backport-12.5.patch new file mode 100644 index 0000000..7728875 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0027-capwapmgr-backport-12.5.patch @@ -0,0 +1,51 @@ +commit 2396944e41307a90e9159107fd225e44980a5b2f +Author: Cemil Coskun +AuthorDate: Tue Aug 9 21:25:13 2022 -0700 +Commit: Cemil Coskun +CommitDate: Tue Aug 9 21:27:58 2022 -0700 + +[qca-nss-clients] In capwapmgr use source MAC address + +Currently, interface MAC address is used while sending packets in capwapmgr. +Update that to use the MAC address in the rule. + +Change-Id: I2ba9df7beab39a9584a1159db3a3f3c337c219aa +Signed-off-by: Cemil Coskun + +--- a/capwapmgr/nss_capwapmgr.c ++++ b/capwapmgr/nss_capwapmgr.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -866,6 +869,10 @@ static nss_tx_status_t nss_capwapmgr_cre + memcpy(nircm->conn_rule.return_mac, unic->dest_mac, 6); + } + ++ nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID; ++ nircm->src_mac_rule.mac_valid_flags |=NSS_IPV4_SRC_MAC_FLOW_VALID; ++ memcpy(nircm->src_mac_rule.flow_src_mac, nircm->conn_rule.return_mac, 6); ++ + /* + * Copy over the DSCP rule parameters + */ +@@ -1001,6 +1008,10 @@ static nss_tx_status_t nss_capwapmgr_cre + memcpy(nircm->conn_rule.return_mac, unic->dest_mac, 6); + nircm->valid_flags |= NSS_IPV6_RULE_CREATE_CONN_VALID; + ++ nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID; ++ nircm->src_mac_rule.mac_valid_flags |=NSS_IPV6_SRC_MAC_FLOW_VALID; ++ memcpy(nircm->src_mac_rule.flow_src_mac, nircm->conn_rule.return_mac, 6); ++ + /* + * Copy over the DSCP rule parameters + */ diff --git a/qca-nss-clients/patches-11.4/0027-map-t-backport-12.5.patch b/qca-nss-clients/patches-11.4/0027-map-t-backport-12.5.patch new file mode 100644 index 0000000..aff02cf --- /dev/null +++ b/qca-nss-clients/patches-11.4/0027-map-t-backport-12.5.patch @@ -0,0 +1,169 @@ +--- a/map/map-t/nss_connmgr_map_t.c ++++ b/map/map-t/nss_connmgr_map_t.c +@@ -531,7 +531,7 @@ static void nss_connmgr_map_t_decap_exce + /* + * nss_connmgr_map_t_encap_exception() + * Exception handler registered to NSS for handling map_t ipv4 pkts +- * Translates ipv4 packet back to ipv6 and send to nat46 device directly. ++ * Send the translated ipv4 packets to the stack directly. + */ + static void nss_connmgr_map_t_encap_exception(struct net_device *dev, + struct sk_buff *skb, +@@ -539,23 +539,7 @@ static void nss_connmgr_map_t_encap_exce + + { + struct iphdr *ip4_hdr; +- struct ipv6hdr *ip6_hdr; +- uint8_t v6saddr[16], v6daddr[16]; +- struct tcphdr *tcph = NULL; +- struct udphdr *udph = NULL; +- struct iphdr ip4_hdr_r; +- __be16 sport, dport; +- uint8_t nexthdr, hop_limit, tos; +- int payload_len; +- bool df_bit = false; +- uint16_t append_hdr_sz = 0; +- uint16_t identifier; +- uint32_t l4_csum, orig_csum; +- uint16_t csum; + +- /* +- * Discard L2 header. +- */ + skb_pull(skb, sizeof(struct ethhdr)); + skb_reset_mac_header(skb); + skb_reset_network_header(skb); +@@ -563,123 +547,24 @@ static void nss_connmgr_map_t_encap_exce + ip4_hdr = ip_hdr(skb); + skb_set_transport_header(skb, ip4_hdr->ihl * 4); + +- if (ip4_hdr->protocol == IPPROTO_TCP) { +- tcph = tcp_hdr(skb); +- l4_csum = tcph->check; +- sport = tcph->source; +- dport = tcph->dest; +- } else if (ip4_hdr->protocol == IPPROTO_UDP) { +- udph = udp_hdr(skb); +- orig_csum = l4_csum = udph->check; +- sport = udph->source; +- dport = udph->dest; +- } else { +- nss_connmgr_map_t_warning("%px: Unsupported protocol, free it up\n", dev); +- dev_kfree_skb_any(skb); +- return; +- } +- +- /* +- * Undo the checksum of the IPv4 source and destinationIPv4 address. +- */ +- csum = ip_compute_csum(&ip4_hdr->saddr, 2 * sizeof(ip4_hdr->saddr)); +- l4_csum += ((~csum) & 0xFFFF); +- +- /*` +- * IPv6 packet is xlated to ipv4 packet by acceleration engine. But there is no ipv4 rule. +- * Call xlate_4_to_6() [ which is exported by nat46.ko ] to find original ipv6 src and ipv6 dest address. +- * These functions is designed for packets from lan to wan. Since this packet is from wan, need to call +- * this function with parameters reversed. ipv4_hdr_r is used for reversing ip addresses. +- */ +- ip4_hdr_r.daddr = ip4_hdr->saddr; +- ip4_hdr_r.saddr = ip4_hdr->daddr; +- +- if (unlikely(!xlate_4_to_6(dev, &ip4_hdr_r, dport, sport, v6saddr, v6daddr))) { /* exception happened after packet got xlated */ +- nss_connmgr_map_t_warning("%px: Martian ipv4 packet !!..free it. (saddr = 0x%x daddr = 0x%x sport = %d dport = %d)\n", dev,\ +- ip4_hdr->saddr, ip4_hdr->daddr, sport, dport); +- dev_kfree_skb_any(skb); +- return; +- } +- +- nexthdr = ip4_hdr->protocol; +- payload_len = ntohs(ip4_hdr->tot_len) - sizeof(struct iphdr); +- hop_limit = ip4_hdr->ttl; +- tos = ip4_hdr->tos; +- identifier = ntohs(ip4_hdr->id); +- +- if (ip4_hdr->frag_off & htons(IP_DF)) { +- df_bit = true; +- } else if (map_t_flags & MAPT_FLAG_ADD_DUMMY_HDR) { +- append_hdr_sz = sizeof(struct frag_hdr); +- } +- +- if (!pskb_may_pull(skb, sizeof(struct ipv6hdr) + append_hdr_sz - sizeof(struct iphdr))) { +- nss_connmgr_map_t_warning("%px: Not enough headroom for ipv6 packet...Freeing the packet\n", dev); +- dev_kfree_skb_any(skb); +- return; +- } +- +- skb_push(skb, sizeof(struct ipv6hdr) + append_hdr_sz - sizeof(struct iphdr)); +- skb_reset_network_header(skb); +- skb_reset_mac_header(skb); +- +- skb->protocol = htons(ETH_P_IPV6); +- +- ip6_hdr = ipv6_hdr(skb); +- memset(ip6_hdr, 0, sizeof(struct ipv6hdr)); +- +- ip6_hdr->version = 6; +- ip6_hdr->payload_len = htons(payload_len + append_hdr_sz); +- ip6_hdr->hop_limit = hop_limit; +- +- nss_connmgr_map_t_ipv6_set_tclass(ip6_hdr, tos); +- memcpy(&ip6_hdr->daddr, v6saddr, sizeof(struct in6_addr)); +- memcpy(&ip6_hdr->saddr, v6daddr, sizeof(struct in6_addr)); +- +- if (unlikely(df_bit) || !(map_t_flags & MAPT_FLAG_ADD_DUMMY_HDR)) { +- ip6_hdr->nexthdr = nexthdr; +- } else { +- struct frag_hdr tmp_fh, *fh; +- const __be32 *fh_addr = skb_header_pointer(skb, sizeof(struct ipv6hdr), sizeof(struct frag_hdr), &tmp_fh); +- if (!fh_addr) { +- nss_connmgr_map_t_warning("%px: Not able to offset to frag header\n", dev); +- dev_kfree_skb_any(skb); +- return; +- } +- fh = (struct frag_hdr *)fh_addr; +- memset(fh, 0, sizeof(struct frag_hdr)); +- fh->identification = htonl(identifier); +- fh->nexthdr = nexthdr; +- ip6_hdr->nexthdr = NEXTHDR_FRAGMENT; +- } +- +- skb_set_transport_header(skb, sizeof(struct ipv6hdr) + append_hdr_sz); +- + /* +- * Add the checksum of the IPv6 source and destination address. ++ * IP Header checksum is not generated yet, calculate it now. + */ +- l4_csum += ip_compute_csum(ip6_hdr->saddr.s6_addr16, 2 * sizeof(ip6_hdr->saddr)); +- /* +- * Fold the 32 bits checksum to 16 bits +- */ +- l4_csum = (l4_csum & 0x0000FFFF) + (l4_csum >> 16); +- l4_csum = (l4_csum & 0x0000FFFF) + (l4_csum >> 16); +- +- if (nexthdr == IPPROTO_TCP) { +- tcph->check = (uint16_t)l4_csum; +- } else { +- udph->check = (orig_csum == 0)? 0:(uint16_t)l4_csum; +- } ++ ip4_hdr->check = 0; ++ ip4_hdr->check = ip_fast_csum((unsigned char *)ip4_hdr, ip4_hdr->ihl); + ++ skb->protocol = htons(ETH_P_IP); + skb->pkt_type = PACKET_HOST; + skb->skb_iif = dev->ifindex; + skb->ip_summed = CHECKSUM_NONE; + skb->dev = dev; + +- nss_connmgr_map_t_trace("%p: ipv4 packet exceptioned after v6 ---> v4 xlate, created original ipv6 packet\n", dev); +- nss_connmgr_map_t_trace("%p: Calculted ipv6 params: src_addr=%pI6, dest_addr=%pI6, payload_len=%d, checksum=%x\n", dev, v6saddr, v6daddr, payload_len, l4_csum); +- +- dev_queue_xmit(skb); ++ nss_connmgr_map_t_trace("%px: ipv4 packet exceptioned after v6/v4xlat src=%pI4 dest=%pI4 proto=%d\n", ++ dev, &ip4_hdr->saddr, &ip4_hdr->daddr, ip4_hdr->protocol); ++ /* ++ * Go through Linux network stack. ++ */ ++ netif_receive_skb(skb); + return; + } + diff --git a/qca-nss-clients/patches-11.4/0027-match-backport-12.5.patch b/qca-nss-clients/patches-11.4/0027-match-backport-12.5.patch new file mode 100644 index 0000000..91da364 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0027-match-backport-12.5.patch @@ -0,0 +1,92 @@ +--- a/match/nss_match_l2.c ++++ b/match/nss_match_l2.c +@@ -1,6 +1,7 @@ + /* + ******************************************************************************* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above +@@ -133,7 +134,7 @@ static int nss_match_l2_cmd_parse(char * + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); + int ret = 0; + uint32_t mask_val[4] = {0}; +- uint32_t actions = 0, if_num = 0, setprio = 0, nexthop = 0; ++ uint32_t actions = 0, if_num = 0, setprio = NSS_MAX_NUM_PRI, nexthop = 0; + uint16_t smac[3] = {0}, dmac[3] = {0}, mask_id = 0, ethertype = 0; + uint8_t mac_addr_tmp[6]; + char tmp[4]; +@@ -340,22 +341,22 @@ static int nss_match_l2_cmd_parse(char * + + switch(actions) { + case NSS_MATCH_ACTION_SETPRIO: +- if (nexthop || !setprio || setprio >= NSS_MAX_NUM_PRI) { ++ if (nexthop || setprio >= NSS_MAX_NUM_PRI) { + goto fail; + } + break; + case NSS_MATCH_ACTION_FORWARD: +- if (setprio || !nexthop) { ++ if (!(setprio == NSS_MAX_NUM_PRI) || !nexthop) { + goto fail; + } + break; + case NSS_MATCH_ACTION_SETPRIO | NSS_MATCH_ACTION_FORWARD: +- if (!setprio || !nexthop || setprio >= NSS_MAX_NUM_PRI) { ++ if (!nexthop || setprio >= NSS_MAX_NUM_PRI) { + goto fail; + } + break; + case NSS_MATCH_ACTION_DROP: +- if (setprio || nexthop) { ++ if (!(setprio == NSS_MAX_NUM_PRI) || nexthop) { + goto fail; + } + break; +--- a/match/nss_match_vow.c ++++ b/match/nss_match_vow.c +@@ -1,6 +1,6 @@ + /* + ******************************************************************************* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above +@@ -122,7 +122,7 @@ static int nss_match_vow_cmd_parse(char + char *token, *param, *value; + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); + int ret = 0; +- uint32_t actions = 0, if_num = 0, dscp = 0, outer_prio = 0, inner_prio = 0, setprio = 0, nexthop = 0; ++ uint32_t actions = 0, if_num = 0, dscp = 0, outer_prio = 0, inner_prio = 0, setprio = NSS_MAX_NUM_PRI, nexthop = 0; + uint16_t mask_id = 0; + uint32_t mask_val = 0; + +@@ -301,22 +301,22 @@ static int nss_match_vow_cmd_parse(char + + switch(actions) { + case NSS_MATCH_ACTION_SETPRIO: +- if (nexthop || !setprio || setprio >= NSS_MAX_NUM_PRI) { ++ if (nexthop || setprio >= NSS_MAX_NUM_PRI) { + goto fail; + } + break; + case NSS_MATCH_ACTION_FORWARD: +- if (setprio || !nexthop) { ++ if (!(setprio == NSS_MAX_NUM_PRI) || !nexthop) { + goto fail; + } + break; + case NSS_MATCH_ACTION_SETPRIO | NSS_MATCH_ACTION_FORWARD: +- if (!setprio || !nexthop || setprio >= NSS_MAX_NUM_PRI) { ++ if (!nexthop || setprio >= NSS_MAX_NUM_PRI) { + goto fail; + } + break; + case NSS_MATCH_ACTION_DROP: +- if (setprio || nexthop) { ++ if (!(setprio == NSS_MAX_NUM_PRI) || nexthop) { + goto fail; + } + break; diff --git a/qca-nss-clients/patches-11.4/0027-pptp-backport-12.5.patch b/qca-nss-clients/patches-11.4/0027-pptp-backport-12.5.patch new file mode 100644 index 0000000..edddc63 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0027-pptp-backport-12.5.patch @@ -0,0 +1,31 @@ +--- a/pptp/nss_connmgr_pptp.c ++++ b/pptp/nss_connmgr_pptp.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2015-2018, 2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -272,13 +275,12 @@ static void nss_connmgr_pptp_event_recei + + if_type = nss_dynamic_interface_get_type(nss_pptp_get_context(), tnlmsg->cm.interface); + +- if (if_type == NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER) { ++ if ((if_type == NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER) && sync_stats->node_stats.rx_packets) { + ppp_update_stats(netdev, + (unsigned long)sync_stats->node_stats.rx_packets, + (unsigned long)sync_stats->node_stats.rx_bytes, + 0, 0, 0, 0, 0, 0); +- } else { +- ++ } else if ((if_type == NSS_DYNAMIC_INTERFACE_TYPE_PPTP_INNER) && sync_stats->node_stats.tx_packets) { + ppp_update_stats(netdev, 0, 0, + (unsigned long)sync_stats->node_stats.tx_packets, + (unsigned long)sync_stats->node_stats.tx_bytes, diff --git a/qca-nss-clients/patches-11.4/0027-vlan-backport-12.5.patch b/qca-nss-clients/patches-11.4/0027-vlan-backport-12.5.patch new file mode 100644 index 0000000..343ff54 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0027-vlan-backport-12.5.patch @@ -0,0 +1,525 @@ +--- a/vlan/nss_vlan_mgr.c ++++ b/vlan/nss_vlan_mgr.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -154,15 +157,6 @@ static struct nss_vlan_pvt *nss_vlan_mgr + return NULL; + } + +-/* +- * nss_vlan_mgr_instance_deref() +- */ +-static void nss_vlan_mgr_instance_deref(struct nss_vlan_pvt *v) +-{ +- spin_lock(&vlan_mgr_ctx.lock); +- BUG_ON(!(--v->refs)); +- spin_unlock(&vlan_mgr_ctx.lock); +-} + + #ifdef NSS_VLAN_MGR_PPE_SUPPORT + /* +@@ -365,22 +359,16 @@ static void nss_vlan_mgr_port_role_event + * nss_vlan_mgr_bond_configure_ppe() + * Configure PPE for bond device + */ +-static int nss_vlan_mgr_bond_configure_ppe(struct nss_vlan_pvt *v, struct net_device *bond_dev) ++static int nss_vlan_mgr_bond_configure_ppe(struct nss_vlan_pvt *v, struct net_device *bond_dev, uint32_t vsi) + { +- uint32_t vsi; + int ret = 0; + struct net_device *slave; + int32_t port; + int vlan_mgr_bond_port_role = -1; + +- if (ppe_vsi_alloc(NSS_VLAN_MGR_SWITCH_ID, &vsi)) { +- nss_vlan_mgr_warn("%s: failed to allocate VSI for bond vlan device", bond_dev->name); +- return -1; +- } +- + if (nss_vlan_tx_vsi_attach_msg(v->nss_if, vsi) != NSS_TX_SUCCESS) { + nss_vlan_mgr_warn("%s: failed to attach VSI to bond vlan interface\n", bond_dev->name); +- goto free_vsi; ++ return -1; + } + + /* +@@ -393,7 +381,7 @@ static int nss_vlan_mgr_bond_configure_p + if (!NSS_VLAN_PHY_PORT_CHK(port)) { + rcu_read_unlock(); + nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave->name, port); +- goto free_vsi; ++ return -1; + } + + /* +@@ -409,7 +397,7 @@ static int nss_vlan_mgr_bond_configure_p + * In case the bond interface has no slaves, we do not want to proceed further + */ + if (vlan_mgr_bond_port_role == -1) { +- goto free_vsi; ++ return -1; + } + + /* +@@ -436,6 +424,12 @@ static int nss_vlan_mgr_bond_configure_p + rcu_read_lock(); + for_each_netdev_in_bond_rcu(bond_dev, slave) { + port = nss_cmn_get_interface_number_by_dev(slave); ++ if (!NSS_VLAN_PHY_PORT_CHK(port)) { ++ rcu_read_unlock(); ++ nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave->name, port); ++ return -1; ++ } ++ + ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1], v->ppe_svid, v->ppe_cvid, vsi); + if (ret != SW_OK) { + rcu_read_unlock(); +@@ -471,6 +465,12 @@ static int nss_vlan_mgr_bond_configure_p + rcu_read_lock(); + for_each_netdev_in_bond_rcu(bond_dev, slave) { + port = nss_cmn_get_interface_number_by_dev(slave); ++ if (!NSS_VLAN_PHY_PORT_CHK(port)) { ++ rcu_read_unlock(); ++ nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave->name, port); ++ return -1; ++ } ++ + v->eg_xlt_rule.port_bitmap |= (1 << v->port[port - 1]); + ret = fal_port_vlan_trans_adv_add(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1], + FAL_PORT_VLAN_EGRESS, &v->eg_xlt_rule, &v->eg_xlt_action); +@@ -490,6 +490,11 @@ static int nss_vlan_mgr_bond_configure_p + for_each_netdev_in_bond_rcu(bond_dev, slave) { + fal_port_qinq_role_t mode; + port = nss_cmn_get_interface_number_by_dev(slave); ++ if (!NSS_VLAN_PHY_PORT_CHK(port)) { ++ rcu_read_unlock(); ++ nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave->name, port); ++ return -1; ++ } + + /* + * If double tag, we should set physical port as core port +@@ -513,13 +518,18 @@ static int nss_vlan_mgr_bond_configure_p + ret = NSS_VLAN_PORT_ROLE_CHANGED; + } + +- v->ppe_vsi = vsi; + return ret; + + delete_egress_rule: + rcu_read_lock(); + for_each_netdev_in_bond_rcu(bond_dev, slave) { + port = nss_cmn_get_interface_number_by_dev(slave); ++ if (!NSS_VLAN_PHY_PORT_CHK(port)) { ++ rcu_read_unlock(); ++ nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave->name, port); ++ return -1; ++ } ++ + ret = fal_port_vlan_trans_adv_del(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1], + FAL_PORT_VLAN_EGRESS, + &v->eg_xlt_rule, &v->eg_xlt_action); +@@ -533,6 +543,12 @@ delete_ingress_rule: + rcu_read_lock(); + for_each_netdev_in_bond_rcu(bond_dev, slave) { + port = nss_cmn_get_interface_number_by_dev(slave); ++ if (!NSS_VLAN_PHY_PORT_CHK(port)) { ++ rcu_read_unlock(); ++ nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave->name, port); ++ return -1; ++ } ++ + ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1], v->ppe_svid, v->ppe_cvid, PPE_VSI_INVALID); + if (ret != SW_OK) { + nss_vlan_mgr_warn("%px: Failed to delete ingress translation rule for port:%d, error: %d\n", v, v->port[port - 1], ret); +@@ -545,30 +561,19 @@ detach_vsi: + nss_vlan_mgr_warn("%px: Failed to detach vsi %d\n", v, vsi); + } + +-free_vsi: +- if (ppe_vsi_free(NSS_VLAN_MGR_SWITCH_ID, vsi)) { +- nss_vlan_mgr_warn("%px: Failed to free VLAN VSI\n", v); +- } +- + return -1; + } + /* + * nss_vlan_mgr_configure_ppe() + * Configure PPE for physical devices + */ +-static int nss_vlan_mgr_configure_ppe(struct nss_vlan_pvt *v, struct net_device *dev) ++static int nss_vlan_mgr_configure_ppe(struct nss_vlan_pvt *v, struct net_device *dev, uint32_t vsi) + { +- uint32_t vsi; + int ret = 0; + +- if (ppe_vsi_alloc(NSS_VLAN_MGR_SWITCH_ID, &vsi)) { +- nss_vlan_mgr_warn("%s: failed to allocate VSI for vlan device", dev->name); +- return -1; +- } +- + if (nss_vlan_tx_vsi_attach_msg(v->nss_if, vsi) != NSS_TX_SUCCESS) { + nss_vlan_mgr_warn("%s: failed to attach VSI to vlan interface\n", dev->name); +- goto free_vsi; ++ return -1; + } + + /* +@@ -652,7 +657,6 @@ static int nss_vlan_mgr_configure_ppe(st + ret = NSS_VLAN_PORT_ROLE_CHANGED; + } + +- v->ppe_vsi = vsi; + return ret; + + delete_egress_rule: +@@ -674,16 +678,119 @@ detach_vsi: + nss_vlan_mgr_warn("%px: Failed to detach vsi %d\n", v, vsi); + } + +-free_vsi: +- if (ppe_vsi_free(NSS_VLAN_MGR_SWITCH_ID, vsi)) { +- nss_vlan_mgr_warn("%px: Failed to free VLAN VSI\n", v); +- } +- + return -1; + } + #endif + + /* ++ * nss_vlan_mgr_instance_free() ++ * Destroy vlan instance ++ */ ++static void nss_vlan_mgr_instance_free(struct nss_vlan_pvt *v) ++{ ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT ++ int32_t i; ++ int ret = 0; ++#endif ++ ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT ++ if (v->ppe_vsi) { ++ /* ++ * Detach VSI ++ */ ++ if (nss_vlan_tx_vsi_detach_msg(v->nss_if, v->ppe_vsi)) { ++ nss_vlan_mgr_warn("%px: Failed to detach vsi %d\n", v, v->ppe_vsi); ++ } ++ ++ /* ++ * Delete ingress vlan translation rule ++ */ ++ for (i = 0; i < NSS_VLAN_PHY_PORT_MAX; i++) { ++ if (!v->port[i]) ++ continue; ++ ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[i], v->ppe_svid, v->ppe_cvid, PPE_VSI_INVALID); ++ if (ret != SW_OK) ++ nss_vlan_mgr_warn("%px: Failed to delete old ingress translation rule, error: %d\n", v, ret); ++ } ++ ++ /* ++ * Delete egress vlan translation rule ++ */ ++ v->eg_xlt_rule.port_bitmap = 0; ++ for (i = 0; i < NSS_VLAN_PHY_PORT_MAX; i++) { ++ if (!v->port[i]) ++ continue; ++ v->eg_xlt_rule.port_bitmap |= (1 << v->port[i]); ++ ret = fal_port_vlan_trans_adv_del(NSS_VLAN_MGR_SWITCH_ID, v->port[i], ++ FAL_PORT_VLAN_EGRESS, ++ &v->eg_xlt_rule, &v->eg_xlt_action); ++ if (ret != SW_OK) { ++ nss_vlan_mgr_warn("%px: Failed to delete vlan translation rule, error:%d\n", v, ret); ++ } ++ } ++ ++ /* ++ * We will always have a VSI since this is allocated in beginning ++ * of the code. ++ */ ++ if (ppe_vsi_free(NSS_VLAN_MGR_SWITCH_ID, v->ppe_vsi)) { ++ nss_vlan_mgr_warn("%px: Failed to free VLAN VSI\n", v); ++ } ++ } ++ ++ /* ++ * Need to change the physical port role. While adding ++ * eth0.10.20/bond0.10.20, the role of the physical port(s) changed ++ * from EDGE to CORE. So, while removing eth0.10.20/bond0.10.20, the ++ * role of the physical port(s) should be changed from CORE to EDGE. ++ */ ++ for (i = 0; i < NSS_VLAN_PHY_PORT_MAX; i++) { ++ if (v->port[i]) { ++ if (nss_vlan_mgr_calculate_new_port_role(v->port[i], i)) { ++ nss_vlan_mgr_port_role_event(v->port[i], i); ++ } ++ } ++ } ++#endif ++ ++ if (v->nss_if) { ++ nss_unregister_vlan_if(v->nss_if); ++ if (nss_dynamic_interface_dealloc_node(v->nss_if, NSS_DYNAMIC_INTERFACE_TYPE_VLAN) != NSS_TX_SUCCESS) ++ nss_vlan_mgr_warn("%px: Failed to dealloc vlan dynamic interface\n", v); ++ } ++ ++ kfree(v); ++} ++ ++/* ++ * nss_vlan_mgr_instance_deref() ++ */ ++static void nss_vlan_mgr_instance_deref(struct nss_vlan_pvt *v) ++{ ++ struct nss_vlan_pvt *parent = NULL; ++ spin_lock(&vlan_mgr_ctx.lock); ++ BUG_ON(v->refs == 0); ++ v->refs--; ++ ++ if (v->refs) { ++ spin_unlock(&vlan_mgr_ctx.lock); ++ return; ++ } ++ ++ if (!list_empty(&v->list)) { ++ list_del(&v->list); ++ } ++ ++ spin_unlock(&vlan_mgr_ctx.lock); ++ ++ parent = v->parent; ++ nss_vlan_mgr_instance_free(v); ++ ++ if (parent) ++ nss_vlan_mgr_instance_deref(parent); ++} ++ ++/* + * nss_vlan_mgr_create_instance() + * Create vlan instance + */ +@@ -816,95 +923,6 @@ static struct nss_vlan_pvt *nss_vlan_mgr + } + + /* +- * nss_vlan_mgr_instance_free() +- * Destroy vlan instance +- */ +-static void nss_vlan_mgr_instance_free(struct nss_vlan_pvt *v) +-{ +-#ifdef NSS_VLAN_MGR_PPE_SUPPORT +- int32_t i; +- int ret = 0; +-#endif +- +- spin_lock(&vlan_mgr_ctx.lock); +- BUG_ON(--v->refs); +- if (!list_empty(&v->list)) { +- list_del(&v->list); +- } +- spin_unlock(&vlan_mgr_ctx.lock); +- +-#ifdef NSS_VLAN_MGR_PPE_SUPPORT +- if (v->ppe_vsi) { +- /* +- * Detach VSI +- */ +- if (nss_vlan_tx_vsi_detach_msg(v->nss_if, v->ppe_vsi)) { +- nss_vlan_mgr_warn("%px: Failed to detach vsi %d\n", v, v->ppe_vsi); +- } +- +- /* +- * Delete ingress vlan translation rule +- */ +- for (i = 0; i < NSS_VLAN_PHY_PORT_MAX; i++) { +- if (!v->port[i]) +- continue; +- ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[i], v->ppe_svid, v->ppe_cvid, PPE_VSI_INVALID); +- if (ret != SW_OK) +- nss_vlan_mgr_warn("%px: Failed to delete old ingress translation rule, error: %d\n", v, ret); +- } +- +- /* +- * Delete egress vlan translation rule +- */ +- v->eg_xlt_rule.port_bitmap = 0; +- for (i = 0; i < NSS_VLAN_PHY_PORT_MAX; i++) { +- if (!v->port[i]) +- continue; +- v->eg_xlt_rule.port_bitmap |= (1 << v->port[i]); +- ret = fal_port_vlan_trans_adv_del(NSS_VLAN_MGR_SWITCH_ID, v->port[i], +- FAL_PORT_VLAN_EGRESS, +- &v->eg_xlt_rule, &v->eg_xlt_action); +- if (ret != SW_OK) { +- nss_vlan_mgr_warn("%px: Failed to delete vlan translation rule, error:%d\n", v, ret); +- } +- } +- +- /* +- * Free PPE VSI +- */ +- if (ppe_vsi_free(NSS_VLAN_MGR_SWITCH_ID, v->ppe_vsi)) { +- nss_vlan_mgr_warn("%px: Failed to free VLAN VSI\n", v); +- } +- } +- +- /* +- * Need to change the physical port role. While adding +- * eth0.10.20/bond0.10.20, the role of the physical port(s) changed +- * from EDGE to CORE. So, while removing eth0.10.20/bond0.10.20, the +- * role of the physical port(s) should be changed from CORE to EDGE. +- */ +- for (i = 0; i < NSS_VLAN_PHY_PORT_MAX; i++) { +- if (v->port[i]) { +- if (nss_vlan_mgr_calculate_new_port_role(v->port[i], i)) { +- nss_vlan_mgr_port_role_event(v->port[i], i); +- } +- } +- } +-#endif +- +- if (v->nss_if) { +- nss_unregister_vlan_if(v->nss_if); +- if (nss_dynamic_interface_dealloc_node(v->nss_if, NSS_DYNAMIC_INTERFACE_TYPE_VLAN) != NSS_TX_SUCCESS) +- nss_vlan_mgr_warn("%px: Failed to dealloc vlan dynamic interface\n", v); +- } +- +- if (v->parent) +- nss_vlan_mgr_instance_deref(v->parent); +- +- kfree(v); +-} +- +-/* + * nss_vlan_mgr_changemtu_event() + */ + static int nss_vlan_mgr_changemtu_event(struct netdev_notifier_info *info) +@@ -979,6 +997,7 @@ static int nss_vlan_mgr_register_event(s + struct nss_vlan_pvt *v; + int if_num; + #ifdef NSS_VLAN_MGR_PPE_SUPPORT ++ uint32_t vsi; + int ret; + #endif + uint32_t vlan_tag; +@@ -995,19 +1014,25 @@ static int nss_vlan_mgr_register_event(s + if (!v) + return NOTIFY_DONE; + ++ /* ++ * Allocate the VSI here. ++ */ ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT ++ if (ppe_vsi_alloc(NSS_VLAN_MGR_SWITCH_ID, &vsi)) { ++ nss_vlan_mgr_warn("%s: failed to allocate VSI for vlan device", dev->name); ++ return NOTIFY_DONE; ++ } ++#endif ++ + if_num = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_VLAN); + if (if_num < 0) { + nss_vlan_mgr_warn("%s: failed to alloc NSS dynamic interface\n", dev->name); +- nss_vlan_mgr_instance_free(v); +- return NOTIFY_DONE; ++ goto vsi_alloc_free; + } + + if (!nss_register_vlan_if(if_num, NULL, dev, 0, v)) { + nss_vlan_mgr_warn("%s: failed to register NSS dynamic interface", dev->name); +- if (nss_dynamic_interface_dealloc_node(if_num, NSS_DYNAMIC_INTERFACE_TYPE_VLAN) != NSS_TX_SUCCESS) +- nss_vlan_mgr_warn("%px: Failed to dealloc vlan dynamic interface\n", v); +- nss_vlan_mgr_instance_free(v); +- return NOTIFY_DONE; ++ goto free_dynamic_interface; + } + v->nss_if = if_num; + +@@ -1021,26 +1046,25 @@ static int nss_vlan_mgr_register_event(s + + #ifdef NSS_VLAN_MGR_PPE_SUPPORT + if (!is_bond_master) +- ret = nss_vlan_mgr_configure_ppe(v, dev); ++ ret = nss_vlan_mgr_configure_ppe(v, dev, vsi); + else +- ret = nss_vlan_mgr_bond_configure_ppe(v, real_dev); ++ ret = nss_vlan_mgr_bond_configure_ppe(v, real_dev, vsi); + + if (ret < 0) { +- nss_vlan_mgr_instance_free(v); +- return NOTIFY_DONE; ++ goto vlan_instance_free; + } ++ ++ v->ppe_vsi = vsi; + #endif + + if (nss_vlan_tx_set_mac_addr_msg(v->nss_if, v->dev_addr) != NSS_TX_SUCCESS) { + nss_vlan_mgr_warn("%s: failed to set mac_addr msg\n", dev->name); +- nss_vlan_mgr_instance_free(v); +- return NOTIFY_DONE; ++ goto vlan_instance_free; + } + + if (nss_vlan_tx_set_mtu_msg(v->nss_if, v->mtu) != NSS_TX_SUCCESS) { + nss_vlan_mgr_warn("%s: failed to set mtu msg\n", dev->name); +- nss_vlan_mgr_instance_free(v); +- return NOTIFY_DONE; ++ goto vlan_instance_free; + } + + vlan_tag = (v->tpid << NSS_VLAN_TPID_SHIFT | v->vid); +@@ -1049,8 +1073,7 @@ static int nss_vlan_mgr_register_event(s + (v->parent ? v->parent->nss_if : port_if), + port_if) != NSS_TX_SUCCESS) { + nss_vlan_mgr_warn("%s: failed to add vlan in nss\n", dev->name); +- nss_vlan_mgr_instance_free(v); +- return NOTIFY_DONE; ++ goto vlan_instance_free; + } + + spin_lock(&vlan_mgr_ctx.lock); +@@ -1078,6 +1101,21 @@ static int nss_vlan_mgr_register_event(s + } + #endif + return NOTIFY_DONE; ++ ++free_dynamic_interface: ++ if (nss_dynamic_interface_dealloc_node(if_num, NSS_DYNAMIC_INTERFACE_TYPE_VLAN) != NSS_TX_SUCCESS) ++ nss_vlan_mgr_warn("%px: Failed to dealloc vlan dynamic interface\n", v); ++ ++vsi_alloc_free: ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT ++ if (ppe_vsi_free(NSS_VLAN_MGR_SWITCH_ID, v->ppe_vsi)) { ++ nss_vlan_mgr_warn("%px: Failed to free VLAN VSI\n", v); ++ } ++#endif ++ ++vlan_instance_free: ++ nss_vlan_mgr_instance_free(v); ++ return NOTIFY_DONE; + } + + /* +@@ -1102,9 +1140,9 @@ static int nss_vlan_mgr_unregister_event + nss_vlan_mgr_instance_deref(v); + + /* +- * Free instance ++ * Release reference take during register_event + */ +- nss_vlan_mgr_instance_free(v); ++ nss_vlan_mgr_instance_deref(v); + + return NOTIFY_DONE; + } diff --git a/qca-nss-clients/patches-11.4/0028-dtlsmgr-use-eth_hw_addr_set.patch b/qca-nss-clients/patches-11.4/0028-dtlsmgr-use-eth_hw_addr_set.patch new file mode 100644 index 0000000..20a1e8e --- /dev/null +++ b/qca-nss-clients/patches-11.4/0028-dtlsmgr-use-eth_hw_addr_set.patch @@ -0,0 +1,13 @@ +--- a/dtls/v2.0/nss_dtlsmgr_ctx_dev.c ++++ b/dtls/v2.0/nss_dtlsmgr_ctx_dev.c +@@ -532,7 +532,8 @@ void nss_dtlsmgr_ctx_dev_setup(struct ne + #else + dev->priv_destructor = nss_dtlsmgr_ctx_dev_free; + #endif +- memcpy(dev->dev_addr, "\xaa\xbb\xcc\xdd\xee\xff", dev->addr_len); +- memset(dev->broadcast, 0xff, dev->addr_len); ++ const uint8_t mac_addr[ETH_ALEN] = { 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff }; ++ eth_hw_addr_set(dev, mac_addr); ++ eth_broadcast_addr(dev->broadcast); + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); + } diff --git a/qca-nss-clients/patches-11.4/0029-dtlsmgr-properly-update-stats.patch b/qca-nss-clients/patches-11.4/0029-dtlsmgr-properly-update-stats.patch new file mode 100644 index 0000000..832d35e --- /dev/null +++ b/qca-nss-clients/patches-11.4/0029-dtlsmgr-properly-update-stats.patch @@ -0,0 +1,13 @@ +--- a/dtls/v2.0/nss_dtlsmgr_ctx_dev.c ++++ b/dtls/v2.0/nss_dtlsmgr_ctx_dev.c +@@ -236,6 +236,10 @@ void nss_dtlsmgr_ctx_dev_rx_inner(struct + skb->skb_iif = dev->ifindex; + skb->dev = dev; + ++ // Update the statistics ++ stats->rx_packets++; ++ stats->rx_bytes += skb->len; ++ + ctx->data_cb(ctx->app_data, skb); + dev_put(dev); + } diff --git a/qca-nss-clients/patches-11.4/0030-fixup-compiler-errors.patch b/qca-nss-clients/patches-11.4/0030-fixup-compiler-errors.patch new file mode 100644 index 0000000..d861a74 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0030-fixup-compiler-errors.patch @@ -0,0 +1,464 @@ +--- a/match/nss_match.c ++++ b/match/nss_match.c +@@ -76,9 +76,10 @@ static nss_match_status_t nss_match_veri + * nss_match_sync_callback() + * Sync callback for syncing stats. + */ +-static void nss_match_sync_callback(void *app_data, struct nss_match_msg *nmm) ++static void nss_match_sync_callback(void *app_data, struct nss_cmn_msg *cmm) + { + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); ++ struct nss_match_msg *nmm = (struct nss_match_msg *)cmm; + + switch (nmm->cm.type) { + case NSS_MATCH_STATS_SYNC: +--- a/nss_qdisc/nss_ppe.c ++++ b/nss_qdisc/nss_ppe.c +@@ -348,8 +348,8 @@ static void nss_ppe_queue_disable(struct + /* + * Disable queue enqueue, dequeue and flush the queue. + */ +- fal_qm_enqueue_ctrl_set(0, npq->q.ucast_qid, false); +- fal_scheduler_dequeue_ctrl_set(0, npq->q.ucast_qid, false); ++ fal_qm_enqueue_ctrl_set(0, npq->q.ucast_qid, 0); ++ fal_scheduler_dequeue_ctrl_set(0, npq->q.ucast_qid, 0); + fal_queue_flush(0, port_num, npq->q.ucast_qid); + + nss_qdisc_info("Disable SSDK level0 queue scheduler successful\n"); +@@ -370,8 +370,8 @@ static void nss_ppe_queue_enable(struct + /* + * Enable queue enqueue and dequeue. + */ +- fal_qm_enqueue_ctrl_set(0, npq->q.ucast_qid, true); +- fal_scheduler_dequeue_ctrl_set(0, npq->q.ucast_qid, true); ++ fal_qm_enqueue_ctrl_set(0, npq->q.ucast_qid, 1); ++ fal_scheduler_dequeue_ctrl_set(0, npq->q.ucast_qid, 1); + + nss_qdisc_info("Enable SSDK level0 queue scheduler successful\n"); + } +@@ -535,14 +535,14 @@ static void nss_ppe_all_queue_disable(ui + * Disable queue enqueue, dequeue and flush the queue. + */ + for (offset = 0; offset < nss_ppe_max_get(port_num, NSS_PPE_UCAST_QUEUE); offset++) { +- fal_qm_enqueue_ctrl_set(0, qid + offset, false); +- fal_scheduler_dequeue_ctrl_set(0, qid + offset, false); ++ fal_qm_enqueue_ctrl_set(0, qid + offset, 0); ++ fal_scheduler_dequeue_ctrl_set(0, qid + offset, 0); + fal_queue_flush(0, port_num, qid + offset); + } + + for (offset = 0; offset < nss_ppe_max_get(port_num, NSS_PPE_MCAST_QUEUE); offset++) { +- fal_qm_enqueue_ctrl_set(0, mcast_qid + offset, false); +- fal_scheduler_dequeue_ctrl_set(0, mcast_qid + offset, false); ++ fal_qm_enqueue_ctrl_set(0, mcast_qid + offset, 0); ++ fal_scheduler_dequeue_ctrl_set(0, mcast_qid + offset, 0); + fal_queue_flush(0, port_num, mcast_qid + offset); + } + +@@ -563,13 +563,13 @@ static void nss_ppe_all_queue_enable(uin + * Enable queue enqueue and dequeue. + */ + for (offset = 0; offset < nss_ppe_max_get(port_num, NSS_PPE_UCAST_QUEUE); offset++) { +- fal_qm_enqueue_ctrl_set(0, qid + offset, true); +- fal_scheduler_dequeue_ctrl_set(0, qid + offset, true); ++ fal_qm_enqueue_ctrl_set(0, qid + offset, 1); ++ fal_scheduler_dequeue_ctrl_set(0, qid + offset, 1); + } + + for (offset = 0; offset < nss_ppe_max_get(port_num, NSS_PPE_MCAST_QUEUE); offset++) { +- fal_qm_enqueue_ctrl_set(0, mcast_qid + offset, true); +- fal_scheduler_dequeue_ctrl_set(0, mcast_qid + offset, true); ++ fal_qm_enqueue_ctrl_set(0, mcast_qid + offset, 1); ++ fal_scheduler_dequeue_ctrl_set(0, mcast_qid + offset, 1); + } + + nss_qdisc_info("Enable SSDK level0 queue scheduler successful\n"); +@@ -608,7 +608,7 @@ static int nss_ppe_l1_queue_scheduler_co + l1cfg.e_pri = NSS_PPE_PRIORITY_MAX - npq->scheduler.priority; + l1cfg.c_drr_id = npq->l1c_drrid; + l1cfg.e_drr_id = npq->l1e_drrid; +- l1cfg.drr_frame_mode = NSS_PPE_FRAME_CRC; ++ l1cfg.drr_frame_mode = (fal_qos_drr_frame_mode_t)NSS_PPE_FRAME_CRC; + + nss_qdisc_trace("SSDK level1 configuration: Port:%d, l0spid:%d, c_drrid:%d, c_pri:%d, c_drr_wt:%d, e_drrid:%d, e_pri:%d, e_drr_wt:%d, l1spid:%d\n", + port_num, npq->l0spid, l1cfg.c_drr_id, l1cfg.c_pri, l1cfg.c_drr_wt, l1cfg.e_drr_id, l1cfg.e_pri, l1cfg.e_drr_wt, l1cfg.sp_id); +@@ -893,7 +893,7 @@ static int nss_ppe_l0_queue_scheduler_co + l0cfg.e_pri = NSS_PPE_PRIORITY_MAX - npq->scheduler.priority; + l0cfg.c_drr_id = npq->l0c_drrid; + l0cfg.e_drr_id = npq->l0e_drrid; +- l0cfg.drr_frame_mode = NSS_PPE_FRAME_CRC; ++ l0cfg.drr_frame_mode = (fal_qos_drr_frame_mode_t)NSS_PPE_FRAME_CRC; + + nss_qdisc_trace("SSDK level0 configuration: Port:%d, ucast_qid:%d, c_drrid:%d, c_pri:%d, c_drr_wt:%d, e_drrid:%d, e_pri:%d, e_drr_wt:%d, l0spid:%d\n", + port_num, npq->q.ucast_qid, l0cfg.c_drr_id, l0cfg.c_pri, l0cfg.c_drr_wt, l0cfg.e_drr_id, l0cfg.e_pri, l0cfg.e_drr_wt, l0cfg.sp_id); +@@ -1018,7 +1018,7 @@ static int nss_ppe_port_shaper_set(struc + cfg.c_shaper_en = 1; + cfg.cbs = npq->shaper.cburst; + cfg.cir = (npq->shaper.crate / 1000) * 8; +- cfg.shaper_frame_mode = NSS_PPE_FRAME_CRC; ++ cfg.shaper_frame_mode = (fal_shaper_frame_mode_t)NSS_PPE_FRAME_CRC; + + /* + * Take HW scaling into consideration +@@ -1100,7 +1100,7 @@ static int nss_ppe_flow_shaper_set(struc + cfg.e_shaper_en = 1; + cfg.ebs = npq->shaper.cburst; + cfg.eir = ((npq->shaper.crate / 1000) * 8) - cfg.cir; +- cfg.shaper_frame_mode = NSS_PPE_FRAME_CRC; ++ cfg.shaper_frame_mode = (fal_shaper_frame_mode_t)NSS_PPE_FRAME_CRC; + + /* + * Take HW scaling into consideration +@@ -1184,7 +1184,7 @@ static int nss_ppe_queue_shaper_set(stru + cfg.e_shaper_en = 1; + cfg.ebs = npq->shaper.cburst; + cfg.eir = ((npq->shaper.crate / 1000) * 8) - cfg.cir; +- cfg.shaper_frame_mode = NSS_PPE_FRAME_CRC; ++ cfg.shaper_frame_mode = (fal_shaper_frame_mode_t)NSS_PPE_FRAME_CRC; + + /* + * Take HW scaling into consideration +@@ -1252,7 +1252,6 @@ static void nss_ppe_attach_free(uint32_t + spin_unlock_bh(&ppe_port->lock); + + nss_qdisc_info("port:%d, type:%d, res:%px\n", port, res->type, res); +- return; + } + + /* +@@ -2338,7 +2337,7 @@ int nss_ppe_init(struct Qdisc *sch, stru + * nothing useful and thus we don't allocate any resource". + */ + nss_qdisc_trace("Qdisc parent = %px, handle=%x\n", nq->parent, nq->parent->qos_tag); +- if ((nq->parent->npq.sub_type == NSS_SHAPER_CONFIG_PPE_SN_TYPE_HTB)) { ++ if (nq->parent->npq.sub_type == NSS_SHAPER_CONFIG_PPE_SN_TYPE_HTB) { + nq->npq.level = nq->parent->npq.level; + } else { + nq->npq.level = nq->parent->npq.level - 1; +--- a/nss_qdisc/nss_ppe_mc.c ++++ b/nss_qdisc/nss_ppe_mc.c +@@ -32,8 +32,8 @@ int nss_ppe_mcast_queue_reset(struct nss + return 0; + } + +- fal_qm_enqueue_ctrl_set(0, npq->q.mcast_qid, false); +- fal_scheduler_dequeue_ctrl_set(0, npq->q.mcast_qid, false); ++ fal_qm_enqueue_ctrl_set(0, npq->q.mcast_qid, 0); ++ fal_scheduler_dequeue_ctrl_set(0, npq->q.mcast_qid, 0); + fal_queue_flush(0, port_num, npq->q.mcast_qid); + + /* +@@ -153,8 +153,8 @@ int nss_ppe_mcast_queue_set(struct nss_q + } + } + +- fal_qm_enqueue_ctrl_set(0, npq->q.mcast_qid, true); +- fal_scheduler_dequeue_ctrl_set(0, npq->q.mcast_qid, true); ++ fal_qm_enqueue_ctrl_set(0, npq->q.mcast_qid, 1); ++ fal_scheduler_dequeue_ctrl_set(0, npq->q.mcast_qid, 1); + + nss_qdisc_info("SSDK multicast queue configuration successful for port:%d\n", port_num); + return 0; +@@ -164,4 +164,4 @@ fail: + npq->q.mcast_qid = 0; + npq->q.mcast_valid = 0; + return -EINVAL; +-} +\ No newline at end of file ++} +--- a/nss_qdisc/nss_wred.c ++++ b/nss_qdisc/nss_wred.c +@@ -296,7 +296,7 @@ static int nss_wred_change(struct Qdisc + + nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag; + nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.limit = qopt->limit; +- nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.weight_mode = qopt->weight_mode; ++ nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.weight_mode = (nss_shaper_config_wred_weight_mode_t)qopt->weight_mode; + nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.weight_mode_value = qopt->weight_mode_value; + nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.rap.min = qopt->rap.min; + nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.rap.max = qopt->rap.max; +--- a/openvpn/plugins/nss_ovpn_sk.c ++++ b/openvpn/plugins/nss_ovpn_sk.c +@@ -156,7 +156,7 @@ static int nss_ovpn_sk_crypto_key_add(st + return -EFAULT; + } + +- crypto_cfg.algo = crypto_info.config.algo; ++ crypto_cfg.algo = (enum nss_ovpnmgr_algo)crypto_info.config.algo; + crypto_cfg.encrypt.cipher_keylen = crypto_info.config.cipher_key_size; + crypto_cfg.encrypt.hmac_keylen = crypto_info.config.hmac_key_size; + crypto_cfg.decrypt.cipher_keylen = crypto_info.config.cipher_key_size; +@@ -364,7 +364,7 @@ static int nss_ovpn_sk_tun_add(struct so + tun_hdr.dst_port = tun_data.tun_hdr.dst_port; + tun_hdr.hop_limit = tun_data.tun_hdr.hop_limit; + +- crypto_cfg.algo = tun_data.crypto.config.algo; ++ crypto_cfg.algo = (enum nss_ovpnmgr_algo)tun_data.crypto.config.algo; + crypto_cfg.encrypt.cipher_keylen = tun_data.crypto.config.cipher_key_size; + crypto_cfg.encrypt.hmac_keylen = tun_data.crypto.config.hmac_key_size; + crypto_cfg.decrypt.cipher_keylen = tun_data.crypto.config.cipher_key_size; +@@ -442,7 +442,7 @@ static int nss_ovpn_sk_tun_add(struct so + * nss_ovpn_sk_app_dereg() + * Deregister application. + */ +-static int nss_ovpn_sk_app_dereg(struct socket *sock, unsigned long argp) ++static int nss_ovpn_sk_app_dereg(struct socket *sock) + { + struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk; + int ret; +@@ -491,7 +491,7 @@ static int nss_ovpn_sk_app_reg(struct so + return -EFAULT; + } + +- ret = nss_ovpnmgr_app_add(pinfo->dev, app.app_mode, (void *)sock); ++ ret = nss_ovpnmgr_app_add(pinfo->dev, (enum nss_ovpnmgr_app_mode)app.app_mode, (void *)sock); + if (ret) { + nss_ovpn_sk_warn("%px: Failed to register application, pid=%u\n", sock, app.pid); + dev_put(pinfo->dev); +@@ -689,7 +689,7 @@ static int nss_ovpn_sk_recvmsg(struct so + return -EINVAL; + } + +- skb = skb_recv_datagram(sk, flags, MSG_DONTWAIT, &ret); ++ skb = skb_recv_datagram(sk, flags, &ret); + if (!skb) { + nss_ovpn_sk_warn("%px: There are no packets in the queue.\n", sock); + return -ENOBUFS; +@@ -740,7 +740,7 @@ static int nss_ovpn_sk_ioctl(struct sock + case NSS_OVPN_SK_SIOC_APP_REG: + return nss_ovpn_sk_app_reg(sock, argp); + case NSS_OVPN_SK_SIOC_APP_DEREG: +- return nss_ovpn_sk_app_dereg(sock, argp); ++ return nss_ovpn_sk_app_dereg(sock); + case NSS_OVPN_SK_SIOC_TUN_ADD: + return nss_ovpn_sk_tun_add(sock, argp); + case NSS_OVPN_SK_SIOC_TUN_DEL: +@@ -773,15 +773,12 @@ static const struct proto_ops nss_ovpn_s + .ioctl = nss_ovpn_sk_ioctl, + .listen = sock_no_listen, + .shutdown = sock_no_shutdown, +- .getsockopt = sock_no_getsockopt, + .mmap = sock_no_mmap, +- .sendpage = sock_no_sendpage, + .sendmsg = nss_ovpn_sk_sendmsg, + .recvmsg = nss_ovpn_sk_recvmsg, + .poll = datagram_poll, + .bind = sock_no_bind, + .release = nss_ovpn_sk_release, +- .setsockopt = sock_no_setsockopt, + .accept = sock_no_accept, + }; + +--- a/pvxlanmgr/nss_pvxlanmgr.c ++++ b/pvxlanmgr/nss_pvxlanmgr.c +@@ -180,7 +180,7 @@ static struct rtnl_link_stats64 *nss_pvx + atomic_long_set(&(dev)->stats.__rx_dropped, 0); + priv = netdev_priv(dev); + memset(stats, 0, sizeof(struct rtnl_link_stats64)); +- memcpy(stats, &priv->stats, sizeof(struct rtnl_link_stats64)); ++ *stats = priv->stats; + dev_put(dev); + + return stats; +@@ -408,7 +408,7 @@ nss_pvxlanmgr_status_t nss_pvxlanmgr_net + if (ret != NSS_TX_SUCCESS) { + nss_pvxlanmgr_warn("%px: Tunnel disable failed: %d\n", dev, ret); + dev_put(dev); +- return ret; ++ return (nss_pvxlanmgr_status_t)ret; + } + + ret = nss_pvxlanmgr_tunnel_tx_msg_disable(priv->pvxlan_ctx, priv->if_num_outer); +@@ -416,11 +416,11 @@ nss_pvxlanmgr_status_t nss_pvxlanmgr_net + nss_pvxlanmgr_warn("%px: Tunnel disable failed: %d\n", dev, ret); + nss_pvxlanmgr_tunnel_tx_msg_enable(priv->pvxlan_ctx, priv->if_num_host_inner, priv->if_num_outer); + dev_put(dev); +- return ret; ++ return (nss_pvxlanmgr_status_t)ret; + } + + dev_put(dev); +- return ret; ++ return (nss_pvxlanmgr_status_t)ret; + } + EXPORT_SYMBOL(nss_pvxlanmgr_netdev_disable); + +@@ -440,7 +440,7 @@ nss_pvxlanmgr_status_t nss_pvxlanmgr_net + if (ret != NSS_TX_SUCCESS) { + nss_pvxlanmgr_warn("%px: Tunnel enable failed: %d\n", dev, ret); + dev_put(dev); +- return ret; ++ return (nss_pvxlanmgr_status_t)ret; + } + + ret = nss_pvxlanmgr_tunnel_tx_msg_enable(priv->pvxlan_ctx, priv->if_num_outer, priv->if_num_host_inner); +@@ -448,11 +448,11 @@ nss_pvxlanmgr_status_t nss_pvxlanmgr_net + nss_pvxlanmgr_warn("%px: Tunnel enable failed: %d\n", dev, ret); + nss_pvxlanmgr_tunnel_tx_msg_disable(priv->pvxlan_ctx, priv->if_num_host_inner); + dev_put(dev); +- return ret; ++ return (nss_pvxlanmgr_status_t)ret; + } + + dev_put(dev); +- return ret; ++ return (nss_pvxlanmgr_status_t)ret; + } + EXPORT_SYMBOL(nss_pvxlanmgr_netdev_enable); + +@@ -524,7 +524,7 @@ EXPORT_SYMBOL(nss_pvxlanmgr_netdev_destr + * nss_pvxlanmgr_netdev_create() + * API to create a Pvxlan netdev + */ +-struct net_device *nss_pvxlanmgr_netdev_create() ++struct net_device *nss_pvxlanmgr_netdev_create(void) + { + struct nss_pvxlanmgr_priv *priv; + struct net_device *dev; +--- a/pvxlanmgr/nss_pvxlanmgr_tunnel.c ++++ b/pvxlanmgr/nss_pvxlanmgr_tunnel.c +@@ -67,7 +67,7 @@ static inline nss_pvxlanmgr_status_t nss + } + + dev_put(dev); +- return status; ++ return (nss_pvxlanmgr_status_t)status; + } + + /* +@@ -110,7 +110,7 @@ static inline nss_pvxlanmgr_status_t nss + } + + dev_put(dev); +- return status; ++ return (nss_pvxlanmgr_status_t)status; + } + + /* +@@ -138,7 +138,7 @@ static nss_pvxlanmgr_status_t nss_pvxlan + status = nss_pvxlanmgr_tunnel_tx_msg(ctx, &pvxlanmsg, if_num, NSS_PVXLAN_MSG_TYPE_TUNNEL_DESTROY_RULE, sizeof(struct nss_pvxlan_rule_msg)); + if (status != NSS_TX_SUCCESS) { + nss_pvxlanmgr_warn("%px: ctx: create encap data tunnel error %d\n", ctx, status); +- return status; ++ return (nss_pvxlanmgr_status_t)status; + } + + return NSS_PVXLANMGR_SUCCESS; +@@ -169,7 +169,7 @@ static nss_pvxlanmgr_status_t nss_pvxlan + status = nss_pvxlanmgr_tunnel_tx_msg(ctx, &pvxlanmsg, if_num, NSS_PVXLAN_MSG_TYPE_TUNNEL_CREATE_RULE, sizeof(struct nss_pvxlan_rule_msg)); + if (status != NSS_TX_SUCCESS) { + nss_pvxlanmgr_warn("%px: ctx: create encap data tunnel error %d\n", ctx, status); +- return status; ++ return (nss_pvxlanmgr_status_t)status; + } + + return NSS_PVXLANMGR_SUCCESS; +@@ -482,7 +482,7 @@ nss_pvxlanmgr_status_t nss_pvxlanmgr_tun + if_num_outer = priv->if_num_outer; + + status = nss_pvxlanmgr_tunnel_pvxlan_rule_create(priv->pvxlan_ctx, if_num_host_inner, &pvxlan_rule); +- nss_pvxlanmgr_info("%px: dynamic interface if_num is :%d and pvxlan tunnel status:%d\n", dev, if_num_host_inner, status); ++ nss_pvxlanmgr_info("%px: dynamic interface if_num is :%d, if_num_outer :%d, and pvxlan tunnel status:%d\n", dev, if_num_host_inner, if_num_outer, status); + if (status != NSS_PVXLANMGR_SUCCESS) { + nss_pvxlanmgr_warn("%px: %d: PVXLAN rule create failed with status: %d\n", dev, if_num_host_inner, status); + dev_put(dev); +@@ -586,7 +586,7 @@ nss_pvxlanmgr_status_t nss_pvxlanmgr_tun + if_num_outer = priv->if_num_outer; + + status = nss_pvxlanmgr_tunnel_pvxlan_rule_create(priv->pvxlan_ctx, if_num_host_inner, &pvxlan_rule); +- nss_pvxlanmgr_info("%px: dynamic interface if_num is :%d and pvxlan tunnel status:%d\n", dev, if_num_host_inner, status); ++ nss_pvxlanmgr_info("%px: dynamic interface if_num is :%d, if_num_outer :%d, and pvxlan tunnel status:%d\n", dev, if_num_host_inner, if_num_outer, status); + if (status != NSS_PVXLANMGR_SUCCESS) { + nss_pvxlanmgr_warn("%px: %d: PVXLAN rule create failed with status: %d\n", dev, if_num_host_inner, status); + dev_put(dev); +--- a/tls/nss_tlsmgr_crypto.c ++++ b/tls/nss_tlsmgr_crypto.c +@@ -250,7 +250,7 @@ nss_tlsmgr_status_t nss_tlsmgr_crypto_up + status = nss_tls_tx_msg_sync(ctx->nss_ctx, ctx->ifnum, msg_type, sizeof(*ntcu), &ntm); + if (status != NSS_TX_SUCCESS) { + nss_tlsmgr_warn("%px: Failed to configure decap, status:%d, error:%d", ctx, status, ntm.cm.error); +- return false; ++ return (nss_tlsmgr_status_t)false; + } + + /* +@@ -361,7 +361,7 @@ nss_tlsmgr_status_t nss_tlsmgr_crypto_up + if (status != NSS_TX_SUCCESS) { + nss_tlsmgr_crypto_free(crypto); + nss_tlsmgr_warn("%px: Failed to configure decap, status:%d, error:%d", ctx, status, ntm.cm.error); +- return false; ++ return (nss_tlsmgr_status_t)false; + } + + /* +--- a/vlan/nss_vlan_mgr.c ++++ b/vlan/nss_vlan_mgr.c +@@ -448,8 +448,8 @@ static int nss_vlan_mgr_bond_configure_p + /* + * Fields for match + */ +- v->eg_xlt_rule.vsi_valid = true; /* Use vsi as search key*/ +- v->eg_xlt_rule.vsi_enable = true; /* Use vsi as search key*/ ++ v->eg_xlt_rule.vsi_valid = 1; /* Use vsi as search key*/ ++ v->eg_xlt_rule.vsi_enable = 1; /* Use vsi as search key*/ + v->eg_xlt_rule.vsi = vsi; /* Use vsi as search key*/ + v->eg_xlt_rule.s_tagged = 0x7; /* Accept tagged/untagged/priority tagged svlan */ + v->eg_xlt_rule.c_tagged = 0x7; /* Accept tagged/untagged/priority tagged cvlan */ +@@ -612,8 +612,8 @@ static int nss_vlan_mgr_configure_ppe(st + /* + * Fields for match + */ +- v->eg_xlt_rule.vsi_valid = true; /* Use vsi as search key*/ +- v->eg_xlt_rule.vsi_enable = true; /* Use vsi as search key*/ ++ v->eg_xlt_rule.vsi_valid = 1; /* Use vsi as search key*/ ++ v->eg_xlt_rule.vsi_enable = 1; /* Use vsi as search key*/ + v->eg_xlt_rule.vsi = vsi; /* Use vsi as search key*/ + v->eg_xlt_rule.s_tagged = 0x7; /* Accept tagged/untagged/priority tagged svlan */ + v->eg_xlt_rule.c_tagged = 0x7; /* Accept tagged/untagged/priority tagged cvlan */ +@@ -1805,8 +1805,8 @@ void nss_vlan_mgr_add_vlan_rule(struct n + /* + * Fields for match + */ +- eg_xlt_rule.vsi_valid = true; /* Use vsi as search key */ +- eg_xlt_rule.vsi_enable = true; /* Use vsi as search key */ ++ eg_xlt_rule.vsi_valid = 1; /* Use vsi as search key */ ++ eg_xlt_rule.vsi_enable = 1; /* Use vsi as search key */ + eg_xlt_rule.vsi = bridge_vsi; /* Use vsi as search key */ + eg_xlt_rule.s_tagged = 0x7; /* Accept tagged/untagged/priority tagged svlan */ + eg_xlt_rule.c_tagged = 0x7; /* Accept tagged/untagged/priority tagged cvlan */ +@@ -1873,8 +1873,8 @@ void nss_vlan_mgr_del_vlan_rule(struct n + /* + * Fields for match + */ +- eg_xlt_rule.vsi_valid = true; /* Use vsi as search key */ +- eg_xlt_rule.vsi_enable = true; /* Use vsi as search key */ ++ eg_xlt_rule.vsi_valid = 1; /* Use vsi as search key */ ++ eg_xlt_rule.vsi_enable = 1; /* Use vsi as search key */ + eg_xlt_rule.vsi = bridge_vsi; /* Use vsi as search key */ + eg_xlt_rule.s_tagged = 0x7; /* Accept tagged/untagged/priority tagged svlan */ + eg_xlt_rule.c_tagged = 0x7; /* Accept tagged/untagged/priority tagged cvlan */ +--- a/wifi_meshmgr/nss_wifi_meshmgr.c ++++ b/wifi_meshmgr/nss_wifi_meshmgr.c +@@ -1637,9 +1637,6 @@ nss_wifi_meshmgr_config_mesh_exception(n + break; + + case NSS_WIFI_MESH_US_MESH_PROXY_NOT_FOUND: +- ifnum = decap_ifnum; +- break; +- + case NSS_WIFI_MESH_US_MESH_PATH_NOT_FOUND: + ifnum = decap_ifnum; + break; +@@ -1702,10 +1699,10 @@ nss_wifi_meshmgr_config_mesh_exception_s + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); diff --git a/qca-nss-clients/patches-11.4/0031-kernel-6.12-support.patch b/qca-nss-clients/patches-11.4/0031-kernel-6.12-support.patch new file mode 100644 index 0000000..9f1402f --- /dev/null +++ b/qca-nss-clients/patches-11.4/0031-kernel-6.12-support.patch @@ -0,0 +1,875 @@ +--- a/Makefile ++++ b/Makefile +@@ -10,6 +10,9 @@ qca-nss-tun6rd-objs := nss_connmgr_tun6r + ccflags-y += -DNSS_TUN6RD_DEBUG_LEVEL=0 + ccflags-y += -Wall -Werror + ++# Kernel 6.12 compatibility ++ccflags-y += -Wno-missing-prototypes -include $(src)/compat.h ++ + KERNELVERSION := $(word 1, $(subst ., ,$(KERNELVERSION))).$(word 2, $(subst ., ,$(KERNELVERSION))) + + obj-$(bridge-mgr)+= bridge/ +--- a/bridge/nss_bridge_mgr.c ++++ b/bridge/nss_bridge_mgr.c +@@ -1486,7 +1486,7 @@ static struct notifier_block nss_bridge_ + * nss_bridge_mgr_wan_inf_add_handler + * Marks an interface as a WAN interface for special handling by bridge. + */ +-static int nss_bridge_mgr_wan_intf_add_handler(struct ctl_table *table, ++static int nss_bridge_mgr_wan_intf_add_handler(compat_const struct ctl_table *table, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -1535,7 +1535,7 @@ static int nss_bridge_mgr_wan_intf_add_h + * nss_bridge_mgr_wan_inf_del_handler + * Un-marks an interface as a WAN interface. + */ +-static int nss_bridge_mgr_wan_intf_del_handler(struct ctl_table *table, ++static int nss_bridge_mgr_wan_intf_del_handler(compat_const struct ctl_table *table, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -1593,8 +1593,7 @@ static struct ctl_table nss_bridge_mgr_t + .maxlen = sizeof(char) * IFNAMSIZ, + .mode = 0644, + .proc_handler = &nss_bridge_mgr_wan_intf_del_handler, +- }, +- { } ++ } + }; + + /* +--- a/dtls/v2.0/nss_dtlsmgr_ctx_dev.c ++++ b/dtls/v2.0/nss_dtlsmgr_ctx_dev.c +@@ -284,7 +284,11 @@ void nss_dtlsmgr_ctx_dev_rx_outer(struct + skb_set_transport_header(skb, sizeof(struct iphdr)); + + iph = ip_hdr(skb); ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + nss_dtlsmgr_warn("%px: No IPv4 route or out dev", dev); + dev_kfree_skb_any(skb); +--- a/gre/nss_connmgr_gre.c ++++ b/gre/nss_connmgr_gre.c +@@ -40,6 +40,12 @@ + #define MAX_RETRY_COUNT 100 + #define MAX_WIFI_HEADROOM 66 + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 10, 0) ++#define TUNNEL_CSUM IP_TUNNEL_CSUM_BIT ++#define TUNNEL_SEQ IP_TUNNEL_SEQ_BIT ++#define TUNNEL_KEY IP_TUNNEL_KEY_BIT ++#endif ++ + /* + * GRE connection manager context structure + */ +@@ -186,7 +192,12 @@ static int nss_connmgr_gre_dev_init(stru + if ((dev->priv_flags_ext & IFF_EXT_GRE_V4_TAP) || (dev->type == ARPHRD_IPGRE)) { + dev->needed_headroom = sizeof(struct iphdr) + sizeof(struct ethhdr) + MAX_WIFI_HEADROOM + append; + dev->mtu = ETH_DATA_LEN - sizeof(struct iphdr) - append; ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA; ++#else ++ dev->features |= NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA; ++ dev->netns_local = true; ++#endif + dev->hw_features |= NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA; + return 0; + } +@@ -200,7 +211,11 @@ static int nss_connmgr_gre_dev_init(stru + dev->mtu = IPV6_MIN_MTU; + } + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + dev->features |= NETIF_F_NETNS_LOCAL; ++#else ++ dev->netns_local = true; ++#endif + return 0; + } + +@@ -211,7 +226,6 @@ static int nss_connmgr_gre_dev_init(stru + static void nss_connmgr_gre_dev_uninit(struct net_device *dev) + { + free_percpu(dev->tstats); +- return; + } + + /* +@@ -578,7 +592,6 @@ static void nss_connmgr_gre_tap_inner_ex + */ + skb->protocol = eth_type_trans(skb, dev); + netif_receive_skb(skb); +- return; + } + + /* +@@ -724,10 +737,10 @@ static void nss_connmgr_gre_make_name(st + { + switch (cfg->mode) { + case GRE_MODE_TUN: +- strlcpy(name, "tun-%d", IFNAMSIZ); ++ strscpy(name, "tun-%d", IFNAMSIZ); + break; + case GRE_MODE_TAP: +- strlcpy(name, "tap-%d", IFNAMSIZ); ++ strscpy(name, "tap-%d", IFNAMSIZ); + break; + default: + break; +@@ -757,7 +770,7 @@ static struct net_device *__nss_connmgr_ + int ret = -1, retry, next_if_num_inner = 0, next_if_num_outer = 0; + + if (cfg->name) { +- strlcpy(name, cfg->name, IFNAMSIZ); ++ strscpy(name, cfg->name, IFNAMSIZ); + } else { + nss_connmgr_gre_make_name(cfg, name); + } +--- a/gre/nss_connmgr_gre_v4.c ++++ b/gre/nss_connmgr_gre_v4.c +@@ -45,7 +45,11 @@ static struct net_device *nss_connmgr_gr + struct net_device *dev; + uint32_t ip_addr __attribute__ ((unused)) = ntohl(dest_ip); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, htonl(dest_ip), 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, htonl(dest_ip), 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + nss_connmgr_gre_warning("Unable to lookup route for %pI4\n", &ip_addr); + return NULL; +@@ -87,7 +91,11 @@ static int nss_connmgr_gre_v4_get_mac_ad + dev_put(local_dev); + nss_connmgr_gre_info("Src MAC address for %pI4 is %pM\n", &laddr, src_mac); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, raddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, raddr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + nss_connmgr_gre_warning("route look up failed for %pI4\n", &raddr); + return GRE_ERR_RADDR_ROUTE_LOOKUP; +@@ -208,9 +216,9 @@ int nss_connmgr_gre_v4_set_config(struct + t->parms.o_key = cfg->okey; + } + +- nss_connmgr_gre_set_gre_flags(cfg, &t->parms.o_flags, &t->parms.i_flags); ++ nss_connmgr_gre_set_gre_flags(cfg, (uint16_t *)&t->parms.o_flags, (uint16_t *)&t->parms.i_flags); + +- strlcpy(t->parms.name, dev->name, IFNAMSIZ); ++ strscpy(t->parms.name, dev->name, IFNAMSIZ); + t->dev = dev; + return GRE_SUCCESS; + } +@@ -322,8 +330,13 @@ int nss_connmgr_gre_v4_get_config(struct + memcpy(cmsg->src_ip, &src_ip, 4); + memcpy(cmsg->dest_ip, &dest_ip, 4); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + cmsg->flags |= nss_connmgr_gre_get_nss_config_flags(t->parms.o_flags, + t->parms.i_flags, ++#else ++ cmsg->flags |= nss_connmgr_gre_get_nss_config_flags(*t->parms.o_flags, ++ *t->parms.i_flags, ++#endif + iphdr->tos, iphdr->ttl, + iphdr->frag_off); + +--- a/ipsecmgr/v1.0/nss_ipsecmgr.c ++++ b/ipsecmgr/v1.0/nss_ipsecmgr.c +@@ -526,7 +526,11 @@ static struct net_device *nss_ipsecmgr_t + } + + if (!is_encap) { ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph->saddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph->saddr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + return NULL; + } +--- a/ipsecmgr/v1.0/nss_ipsecmgr_flow.c ++++ b/ipsecmgr/v1.0/nss_ipsecmgr_flow.c +@@ -915,7 +915,11 @@ bool nss_ipsecmgr_flow_process_pmtu(stru + if (unlikely(skb_dst(skb))) + goto send_icmp; + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, ip_hdr(skb)->daddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, ip_hdr(skb)->daddr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + return false; + } +--- a/ipsecmgr/v2.0/nss_ipsecmgr_ctx.c ++++ b/ipsecmgr/v2.0/nss_ipsecmgr_ctx.c +@@ -230,7 +230,11 @@ static void nss_ipsecmgr_ctx_notify_ipv4 + * flow that coming in for the first time. We should query + * the Linux to see the associated NETDEV + */ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph->saddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph->saddr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + dev_kfree_skb_any(skb); + ctx->hstats.v4_notify_drop++; +@@ -258,7 +262,11 @@ static void nss_ipsecmgr_ctx_route_ipv4( + struct iphdr *iph = ip_hdr(skb); + struct rtable *rt; + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_ipsecmgr_warn("%pK: No route, drop packet.\n", skb); + dev_kfree_skb_any(skb); +--- a/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.c ++++ b/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.c +@@ -149,7 +149,11 @@ static void nss_ipsec_xfrm_tunnel_rx_out + if (ip_hdr(skb)->version == IPVERSION) { + struct iphdr *iph = ip_hdr(skb); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + struct rtable *rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0); ++#else ++ struct rtable *rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_ipsec_xfrm_warn("%px: Failed to handle ipv4 exception after encap; No route\n", skb); + goto drop; +@@ -285,7 +289,11 @@ struct nss_ipsec_xfrm_tunnel *nss_ipsec_ + + switch (family) { + case AF_INET: ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, remote->a4, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, remote->a4, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + nss_ipsec_xfrm_err("%p:Failed to allocate tunnel; No IPv4 dst found\n", drv); + return NULL; +--- a/l2tp/l2tpv2/nss_connmgr_l2tpv2.c ++++ b/l2tp/l2tpv2/nss_connmgr_l2tpv2.c +@@ -319,7 +319,7 @@ static struct nss_connmgr_l2tpv2_session + */ + dev_hold(dev); + l2tpv2_session_data->dev = dev; +- strlcpy(session->ifname, dev->name, IFNAMSIZ); ++ strscpy(session->ifname, dev->name, IFNAMSIZ); + + /* + * There is no need for protecting simultaneous addition & +@@ -417,7 +417,11 @@ static void nss_connmgr_l2tpv2_exception + /* + * set skb_iif + */ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph_inner->saddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph_inner->saddr, 0, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_connmgr_l2tpv2_warning("Martian packets !!!"); + } else { +@@ -865,7 +869,7 @@ EXPORT_SYMBOL(l2tpmgr_unregister_ipsecmg + * nss_connmgr_l2tpv2_proc_handler() + * Read and write handler for sysctl. + */ +-static int nss_connmgr_l2tpv2_proc_handler(struct ctl_table *ctl, ++static int nss_connmgr_l2tpv2_proc_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -985,8 +989,7 @@ static struct ctl_table nss_connmgr_l2tp + .maxlen = L2TP_SYSCTL_STR_LEN_MAX, + .mode = 0644, + .proc_handler = &nss_connmgr_l2tpv2_proc_handler, +- }, +- { } ++ } + }; + + /* +@@ -997,8 +1000,7 @@ static struct ctl_table nss_connmgr_l2tp + .procname = "l2tpv2", + .mode = 0555, + .child = nss_connmgr_l2tpv2_table, +- }, +- { } ++ } + }; + + /* +@@ -1009,8 +1011,7 @@ static struct ctl_table nss_connmgr_l2tp + .procname = "nss", + .mode = 0555, + .child = nss_connmgr_l2tpv2_dir, +- }, +- { } ++ } + }; + #endif + +--- a/l2tp/l2tpv2/nss_l2tpv2_stats.c ++++ b/l2tp/l2tpv2/nss_l2tpv2_stats.c +@@ -129,7 +129,11 @@ void nss_l2tpv2_update_dev_stats(struct + dev_put(dev); + return; + } ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) + session = l2tp_tunnel_get_session(tunnel, data.l2tpv2.session.session_id); ++#else ++ session = l2tp_v2_session_get(dev_net(dev), data.l2tpv2.tunnel.tunnel_id, data.l2tpv2.session.session_id); ++#endif + if (!session) { + tunnel_put(tunnel); + dev_put(dev); +--- a/match/nss_match_cmd.c ++++ b/match/nss_match_cmd.c +@@ -124,7 +124,7 @@ static enum nss_match_profile_type nss_m + * nss_match_cmd_procfs_config_handler() + * Handles command input by user to create and configure match instance. + */ +-static int nss_match_cmd_procfs_config_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_match_cmd_procfs_config_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + char *command_str, *token, *param, *value; + char *input_msg, *input_msg_orig; +@@ -451,7 +451,7 @@ fail: + * nss_match_cmd_procfs_reset_nexthop + * Reset to default nexthop of an interface + */ +-static int nss_match_cmd_procfs_reset_nexthop(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_match_cmd_procfs_reset_nexthop(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct net_device *dev; + uint32_t if_num, type = 0; +@@ -521,7 +521,7 @@ static int nss_match_cmd_procfs_reset_ne + * Set next hop of an interface to a match instance. + * Only VAP and physical interfaces are supported as of now. + */ +-static int nss_match_cmd_procfs_set_if_nexthop(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_match_cmd_procfs_set_if_nexthop(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct net_device *dev; + uint32_t if_num, type = 0; +@@ -632,7 +632,7 @@ static int nss_match_cmd_procfs_set_if_n + * nss_match_cmd_procfs_read_help() + * Display help for commands. + */ +-static int nss_match_cmd_procfs_read_help(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_match_cmd_procfs_read_help(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret = proc_dointvec(ctl, write, buffer, lenp, ppos); + +@@ -688,8 +688,7 @@ static struct ctl_table nss_match_table[ + .maxlen = sizeof(nss_match_data), + .mode = 0400, + .proc_handler = &nss_match_cmd_procfs_read_help, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_match_ctl_header; +--- a/mirror/nss_mirror_ctl.c ++++ b/mirror/nss_mirror_ctl.c +@@ -132,7 +132,7 @@ static int nss_mirror_ctl_get_netdev_by_ + { + char dev_name[IFNAMSIZ] = {0}; + +- strlcpy(dev_name, name, IFNAMSIZ); ++ strscpy(dev_name, name, IFNAMSIZ); + if (dev_name[strlen(dev_name) - 1] == '\n') { + dev_name[strlen(dev_name) - 1] = '\0'; + } +@@ -357,7 +357,7 @@ static int nss_mirror_ctl_parse_display_ + return -1; + } + +- strlcpy(dev_name, value, IFNAMSIZ); ++ strscpy(dev_name, value, IFNAMSIZ); + if (dev_name[strlen(dev_name) - 1] == '\n') { + dev_name[strlen(dev_name) - 1] = '\0'; + } +@@ -754,7 +754,7 @@ static int32_t nss_mirror_ctl_parse_cmd( + * nss_mirror_ctl_config_handler() + * Mirror sysctl config handler. + */ +-static int nss_mirror_ctl_config_handler(struct ctl_table *ctl, int write, ++static int nss_mirror_ctl_config_handler(compat_const struct ctl_table *ctl, int write, + void __user *buf, size_t *lenp, loff_t *ppos) + { + char *buffer, *pfree; +@@ -914,8 +914,7 @@ static struct ctl_table nss_mirror_table + .maxlen = sizeof(nss_mirror_config_data), + .mode = 0644, + .proc_handler = &nss_mirror_ctl_config_handler, +- }, +- { } ++ } + }; + + /* +--- a/netlink/nss_nlipv4.c ++++ b/netlink/nss_nlipv4.c +@@ -129,7 +129,11 @@ static struct neighbour *nss_nlipv4_get_ + /* + * search for route entry + */ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, ip_addr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, ip_addr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + return NULL; + } +--- a/netlink/nss_nludp_st.c ++++ b/netlink/nss_nludp_st.c +@@ -446,7 +446,11 @@ static struct neighbour *nss_nludp_st_ge + /* + * search for route entry + */ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, ip_addr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, ip_addr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + return NULL; + } +--- a/nss_qdisc/nss_bf.c ++++ b/nss_qdisc/nss_bf.c +@@ -385,7 +385,11 @@ static int nss_bf_graft_class(struct Qdi + */ + nss_qdisc_info("Grafting old: %px with new: %px\n", *old, new); + if (*old != &noop_qdisc) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 8, 0) + struct nss_qdisc *nq_old = (struct nss_qdisc *)qdisc_priv(*old); ++#else ++ struct nss_qdisc *nq_old = (struct nss_qdisc *)qdisc_priv(((struct Qdisc *)(*old))); ++#endif + nss_qdisc_info("Detaching old: %px\n", *old); + nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag; + if (nss_qdisc_node_detach(&cl->nq, nq_old, &nim_detach, +--- a/nss_qdisc/nss_qdisc.c ++++ b/nss_qdisc/nss_qdisc.c +@@ -375,7 +375,9 @@ static int nss_qdisc_refresh_bshaper_ass + br_update.port_list_count = 0; + br_update.unassign_count = 0; + +- read_lock(&dev_base_lock); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0)) ++ read_lock(&dev_base_lock); ++#endif + dev = first_net_device(&init_net); + + while(dev) { +@@ -422,7 +424,10 @@ static int nss_qdisc_refresh_bshaper_ass + nextdev: + dev = next_net_device(dev); + } +- read_unlock(&dev_base_lock); ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0)) ++ read_unlock(&dev_base_lock); ++#endif + + nss_qdisc_info("List count %d\n", br_update.port_list_count); + +--- a/nss_qdisc/nss_tbl.c ++++ b/nss_qdisc/nss_tbl.c +@@ -360,7 +360,11 @@ static int nss_tbl_graft(struct Qdisc *s + + nss_qdisc_info("Grafting old: %px with new: %px\n", *old, new); + if (*old != &noop_qdisc) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 8, 0) + struct nss_qdisc *nq_old = (struct nss_qdisc *)qdisc_priv(*old); ++#else ++ struct nss_qdisc *nq_old = (struct nss_qdisc *)qdisc_priv(((struct Qdisc *)(*old))); ++#endif + nss_qdisc_info("Detaching old: %px\n", *old); + nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag; + if (nss_qdisc_node_detach(&q->nq, nq_old, &nim_detach, +--- a/openvpn/plugins/nss_ovpn_sk.c ++++ b/openvpn/plugins/nss_ovpn_sk.c +@@ -225,7 +225,11 @@ static int nss_ovpn_sk_update_ipv4_tuple + { + struct rtable *rt; + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(dev_net(pinfo->dev), tun_data->tun_hdr.dst_ip[0], 0, 0, 0); ++#else ++ rt = ip_route_output(dev_net(pinfo->dev), tun_data->tun_hdr.dst_ip[0], 0, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_ovpn_sk_warn("%px: Failed to find IPv4 route.\n", pinfo); + return -EINVAL; +--- a/openvpn/src/nss_ovpnmgr_tun.c ++++ b/openvpn/src/nss_ovpnmgr_tun.c +@@ -69,7 +69,11 @@ static void nss_ovpnmgr_tun_ipv4_forward + skb_reset_network_header(skb); + iph = ip_hdr(skb); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(dev_net(app->dev), iph->daddr, iph->saddr, 0, 0); ++#else ++ rt = ip_route_output(dev_net(app->dev), iph->daddr, iph->saddr, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_ovpnmgr_warn("%px: Failed to find IPv4 route.\n", skb); + tun->outer.stats.host_pkt_drop++; +--- a/openvpn/src/nss_ovpnmgr_app.c ++++ b/openvpn/src/nss_ovpnmgr_app.c +@@ -51,7 +51,11 @@ static struct net_device *nss_ovpnmgr_ap + struct rtable *rt4; + + if (rt->ip_version == IPVERSION) { ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt4 = ip_route_output(&init_net, rt->ip_addr[0], 0, 0, 0); ++#else ++ rt4 = ip_route_output(&init_net, rt->ip_addr[0], 0, 0, 0, 0); ++#endif + if (IS_ERR(rt4)) { + return NULL; + } +--- a/tunipip6/nss_connmgr_tunipip6.c ++++ b/tunipip6/nss_connmgr_tunipip6.c +@@ -174,7 +174,11 @@ static void nss_tunipip6_encap_exception + nss_tunipip6_info("%px: received - %d bytes name %s ver %x\n", + skb, skb->len, dev->name, iph->version); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph->daddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph->daddr, 0, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_tunipip6_info("%px: Failed to find IPv4 route for dest %pI4 src %pI4\n", skb, &iph->daddr, &iph->saddr); + dev_kfree_skb_any(skb); +@@ -283,7 +287,11 @@ static void nss_tunipip6_decap_exception + iph = ip_hdr(skb); + nss_tunipip6_assert(iph->version == 4); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph->daddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph->daddr, 0, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_tunipip6_info("%px: Failed to find IPv4 route for %pI4\n", skb, &iph->daddr); + dev_kfree_skb_any(skb); +--- a/tunipip6/nss_connmgr_tunipip6_sysctl.c ++++ b/tunipip6/nss_connmgr_tunipip6_sysctl.c +@@ -52,7 +52,7 @@ enum nss_tunipip6_sysctl_mode { + }; + + +-static int nss_tunipip6_data_parser(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos, enum nss_tunipip6_sysctl_mode mode) ++static int nss_tunipip6_data_parser(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos, enum nss_tunipip6_sysctl_mode mode) + { + char dev_name[NETDEV_STR_LEN] = {0}, ipv6_prefix_str[PREFIX_STR_LEN] = {0}, ipv6_suffix_str[PREFIX_STR_LEN] = {0}, ipv4_prefix_str[PREFIX_STR_LEN] = {0}; + uint32_t ipv6_prefix[4], ipv6_prefix_len, ipv6_suffix[4], ipv6_suffix_len, ipv4_prefix, ipv4_prefix_len, ea_len, psid_offset; +@@ -108,7 +108,7 @@ static int nss_tunipip6_data_parser(stru + */ + + if (!strcmp(param, "netdev")) { +- strlcpy(dev_name, value, 30); ++ strscpy(dev_name, value, 30); + dev = dev_get_by_name(&init_net, dev_name); + if (!dev) { + kfree(pfree); +@@ -147,7 +147,7 @@ static int nss_tunipip6_data_parser(stru + } + + if (!strcmp(param, "ipv4_prefix")) { +- strlcpy(ipv4_prefix_str, value, 30); ++ strscpy(ipv4_prefix_str, value, 30); + ret = in4_pton(ipv4_prefix_str, -1, (uint8_t *)&ipv4_prefix, -1, NULL); + if (ret != 1) { + kfree(pfree); +@@ -173,7 +173,7 @@ static int nss_tunipip6_data_parser(stru + } + + if (!strcmp(param, "ipv6_prefix")) { +- strlcpy(ipv6_prefix_str, value, 100); ++ strscpy(ipv6_prefix_str, value, 100); + ret = in6_pton(ipv6_prefix_str, -1, (uint8_t *)&ipv6_prefix, -1, NULL); + if (ret != 1) { + kfree(pfree); +@@ -199,7 +199,7 @@ static int nss_tunipip6_data_parser(stru + } + + if (!strcmp(param, "ipv6_suffix")) { +- strlcpy(ipv6_suffix_str, value, 100); ++ strscpy(ipv6_suffix_str, value, 100); + ret = in6_pton(ipv6_suffix_str, -1, (uint8_t *)&ipv6_suffix, -1, NULL); + if (ret != 1) { + kfree(pfree); +@@ -368,27 +368,27 @@ fail: + return 0; + } + +-static int nss_tunipip6_cmd_procfs_add_maprule(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_tunipip6_cmd_procfs_add_maprule(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + return nss_tunipip6_data_parser(ctl, write, buffer, lenp, ppos, NSS_TUNIPIP6_SYSCTL_ADD_MAPRULE); + } + +-static int nss_tunipip6_cmd_procfs_del_maprule(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_tunipip6_cmd_procfs_del_maprule(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + return nss_tunipip6_data_parser(ctl, write, buffer, lenp, ppos, NSS_TUNIPIP6_SYSCTL_DEL_MAPRULE); + } + +-static int nss_tunipip6_cmd_procfs_flush_fmr_rule(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_tunipip6_cmd_procfs_flush_fmr_rule(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + return nss_tunipip6_data_parser(ctl, write, buffer, lenp, ppos, NSS_TUNIPIP6_SYSCTL_FLUSH_FMR_RULE); + } + +-static int nss_tunipip6_cmd_procfs_enable_frag_id(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_tunipip6_cmd_procfs_enable_frag_id(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + return nss_tunipip6_data_parser(ctl, write, buffer, lenp, ppos, NSS_TUNIPIP6_SYSCTL_FRAG_ID); + } + +-static int nss_tunipip6_cmd_procfs_read_help(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_tunipip6_cmd_procfs_read_help(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret = proc_dointvec(ctl, write, buffer, lenp, ppos); + +@@ -445,8 +445,7 @@ static struct ctl_table nss_tunipip6_tab + .maxlen = sizeof(nss_tunipip6_data), + .mode = 0400, + .proc_handler = &nss_tunipip6_cmd_procfs_read_help, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_tunipip6_ctl_header; +--- a/vlan/nss_vlan_mgr.c ++++ b/vlan/nss_vlan_mgr.c +@@ -1549,7 +1549,7 @@ static int nss_vlan_mgr_update_ppe_tpid( + * nss_vlan_mgr_tpid_proc_handler() + * Sets customer TPID and service TPID + */ +-static int nss_vlan_mgr_tpid_proc_handler(struct ctl_table *ctl, ++static int nss_vlan_mgr_tpid_proc_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -1577,8 +1577,7 @@ static struct ctl_table nss_vlan_table[] + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_vlan_mgr_tpid_proc_handler, +- }, +- { } ++ } + }; + + /* +--- a/nss_qdisc/nss_htb.c ++++ b/nss_qdisc/nss_htb.c +@@ -647,7 +647,11 @@ static int nss_htb_graft_class(struct Qd + nss_qdisc_info("grafting old: %x with new: %x\n", (*old)->handle, new->handle); + if (*old != &noop_qdisc) { + nss_qdisc_trace("detaching old: %x\n", (*old)->handle); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) + nq_old = qdisc_priv(*old); ++#else ++ nq_old = qdisc_priv(((struct Qdisc *)(*old))); ++#endif + nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag; + nim_detach.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_detach.child_qos_tag = nq_old->qos_tag; + if (nss_qdisc_node_detach(&cl->nq, nq_old, &nim_detach, +--- a/nss_qdisc/nss_wrr.c ++++ b/nss_qdisc/nss_wrr.c +@@ -492,7 +492,11 @@ static int nss_wrr_graft_class(struct Qd + */ + nss_qdisc_info("Grafting old: %px with new: %px\n", *old, new); + if (*old != &noop_qdisc) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 8, 0) + struct nss_qdisc *nq_child = qdisc_priv(*old); ++#else ++ struct nss_qdisc *nq_child = qdisc_priv(((struct Qdisc *)(*old))); ++#endif + nss_qdisc_info("Detaching old: %px\n", *old); + nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag; + if (nss_qdisc_node_detach(&cl->nq, nq_child, &nim_detach, +--- a/gre/test/nss_connmgr_gre_test.c ++++ b/gre/test/nss_connmgr_gre_test.c +@@ -143,7 +143,7 @@ static ssize_t nss_connmgr_gre_test_writ + * parameter parsing for delete command + */ + if (!strcmp(param, "dev")) { +- strlcpy(dev_name, value, IFNAMSIZ); ++ strscpy(dev_name, value, IFNAMSIZ); + dev_name_valid = true; + break; + } +@@ -153,19 +153,19 @@ static ssize_t nss_connmgr_gre_test_writ + * tap create command + */ + if (!strcmp(param, "next_dev")) { +- strlcpy(dev_name, value, IFNAMSIZ); ++ strscpy(dev_name, value, IFNAMSIZ); + dev_name_valid = true; + continue; + } + + if (!strcmp(param, "saddr")) { +- strlcpy(saddr, value, 20); ++ strscpy(saddr, value, 20); + saddr_valid = true; + continue; + } + + if (!strcmp(param, "daddr")) { +- strlcpy(daddr, value, 20); ++ strscpy(daddr, value, 20); + daddr_valid = true; + continue; + } +--- a/clmapmgr/nss_clmapmgr.c ++++ b/clmapmgr/nss_clmapmgr.c +@@ -185,7 +185,7 @@ static void nss_clmapmgr_setup(struct ne + { + char name[IFNAMSIZ] = {0}; + +- strlcpy(name, "nssclmap%d", IFNAMSIZ); ++ strscpy(name, "nssclmap%d", IFNAMSIZ); + memcpy(dev->name, name, IFNAMSIZ); + dev->netdev_ops = &nss_clmapmgr_ops; + eth_hw_addr_random(dev); +--- a/portifmgr/nss_portifmgr.c ++++ b/portifmgr/nss_portifmgr.c +@@ -266,7 +266,7 @@ struct net_device *nss_portifmgr_create_ + ndev->vlan_features |= NSS_PORTIFMGR_SUPPORTED_FEATURES; + ndev->wanted_features |= NSS_PORTIFMGR_SUPPORTED_FEATURES; + ndev->mtu = real_dev->mtu - NSS_PORTIFMGR_EXTRA_HEADER_SIZE; +- strlcpy(ndev->name, name, IFNAMSIZ); ++ strscpy(ndev->name, name, IFNAMSIZ); + + /* + * Setup temp mac address, this can be changed with ifconfig later +--- a/profiler/profile.c ++++ b/profiler/profile.c +@@ -138,7 +138,7 @@ int profile_register_performance_counter + } + + profile_counter[i] = counter; +- strlcpy(profile_name[i], name, PROFILE_COUNTER_NAME_LENGTH); ++ strscpy(profile_name[i], name, PROFILE_COUNTER_NAME_LENGTH); + profile_name[i][PROFILE_COUNTER_NAME_LENGTH - 1] = 0; + + return 1; +@@ -317,7 +317,7 @@ static int profile_make_stats_packet(cha + counter_ptr = (struct profile_counter *)ptr; + for (n = 0; n < profile_num_counters; ++n) { + counter_ptr->value = htonl(*profile_counter[n]); +- strlcpy(counter_ptr->name, profile_name[n], ++ strscpy(counter_ptr->name, profile_name[n], + PROFILE_COUNTER_NAME_LENGTH); + counter_ptr++; + } +--- a/gre/nss_connmgr_gre_v6.c ++++ b/gre/nss_connmgr_gre_v6.c +@@ -322,9 +322,9 @@ int nss_connmgr_gre_v6_set_config(struct + t->parms.o_key = cfg->okey; + } + +- nss_connmgr_gre_set_gre_flags(cfg, &t->parms.o_flags, &t->parms.i_flags); ++ nss_connmgr_gre_set_gre_flags(cfg, (uint16_t *)&t->parms.o_flags, (uint16_t *)&t->parms.i_flags); + +- strlcpy(t->parms.name, dev->name, IFNAMSIZ); ++ strscpy(t->parms.name, dev->name, IFNAMSIZ); + t->dev = dev; + return GRE_SUCCESS; + } +@@ -359,8 +359,13 @@ int nss_connmgr_gre_v6_get_config(struct + /* + * IPv6 outer tos field is always inherited from inner IP header. + */ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + cmsg->flags |= nss_connmgr_gre_get_nss_config_flags(t->parms.o_flags, + t->parms.i_flags, ++#else ++ cmsg->flags |= nss_connmgr_gre_get_nss_config_flags(*t->parms.o_flags, ++ *t->parms.i_flags, ++#endif + t->parms.flowinfo, + t->parms.hop_limit, 0); + +--- /dev/null ++++ b/compat.h +@@ -0,0 +1,15 @@ ++// compat.h ++#ifndef _COMPAT_H ++#define _COMPAT_H ++ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 10, 0) ++#include ++#define compat_const const ++#define strlcpy strscpy ++#else ++#define compat_const ++#endif ++ ++#endif /* _COMPAT_H */ +--- a/nss_qdisc/nss_prio.c ++++ b/nss_qdisc/nss_prio.c +@@ -350,7 +350,11 @@ static int nss_prio_graft(struct Qdisc * + + nss_qdisc_info("Grafting old: %px with new: %px\n", *old, new); + if (*old != &noop_qdisc) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 8, 0) + struct nss_qdisc *nq_old = qdisc_priv(*old); ++#else ++ struct nss_qdisc *nq_old = qdisc_priv(((struct Qdisc *)(*old))); ++#endif + nss_qdisc_info("Detaching old: %px\n", *old); + nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag; + +--- a/netlink/nss_nldtls.c ++++ b/netlink/nss_nldtls.c +@@ -1090,7 +1090,7 @@ static ssize_t nss_nldtls_tunnel_stats_r + list_for_each_entry(entry, &gbl_ctx.dtls_list_head, list) { + spin_lock_bh(&gbl_ctx.lock); + memcpy(&stats, &entry->stats, sizeof(stats)); +- strlcpy(dev_name, entry->dev_name, IFNAMSIZ); ++ strscpy(dev_name, entry->dev_name, IFNAMSIZ); + spin_unlock_bh(&gbl_ctx.lock); + + size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n--------------------------------"); +--- a/netlink/nss_nlipsec.c ++++ b/netlink/nss_nlipsec.c +@@ -391,7 +391,7 @@ static int nss_nlipsec_op_create_tunnel( + * the tunnel I/F name into the same rule and send it + * as part of the response for the create operation + */ +- strlcpy(nl_rule->ifname, dev->name, IFNAMSIZ); ++ strscpy(nl_rule->ifname, dev->name, IFNAMSIZ); + + /* + * Send to userspace diff --git a/qca-nss-clients/patches-11.4/0032-match-fix-procfs-read-write.patch b/qca-nss-clients/patches-11.4/0032-match-fix-procfs-read-write.patch new file mode 100644 index 0000000..3361a95 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0032-match-fix-procfs-read-write.patch @@ -0,0 +1,406 @@ +--- a/match/nss_match_cmd.c ++++ b/match/nss_match_cmd.c +@@ -127,29 +127,30 @@ static enum nss_match_profile_type nss_m + static int nss_match_cmd_procfs_config_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + char *command_str, *token, *param, *value; +- char *input_msg, *input_msg_orig; ++ char *input_msg, *pos; + nss_match_cmd_t command; + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); + size_t count = *lenp; + int ret = proc_dostring(ctl, write, buffer, lenp, ppos); ++ char cmd_buf[100] = {0}; /* Use a fixed buffer size matching nss_match_data */ + + if (!write) { + return ret; + } + +- input_msg = (char *)kzalloc(count + 1, GFP_KERNEL); +- if (!input_msg) { +- nss_match_warn("%px: Dynamic allocation falied while writing input message from file", ctl); +- return -ENOMEM; ++ if (count >= sizeof(cmd_buf)) { ++ nss_match_warn("%px: Input too large: %zu\n", ctl, count); ++ return -EINVAL; + } + +- input_msg_orig = input_msg; +- if (copy_from_user(input_msg, buffer, count)) { +- kfree(input_msg); +- nss_match_warn("%px: Cannot copy user's entry to kernel memory\n", ctl); +- return -EFAULT; ++ memcpy(cmd_buf, buffer, count); ++ cmd_buf[count] = '\0'; /* Ensure null termination */ ++ ++ if ((pos = strrchr(cmd_buf, '\n')) != NULL) { ++ *pos = '\0'; + } + ++ input_msg = cmd_buf; + command_str = strsep(&input_msg, " "); + command = nss_match_cmd_parse(command_str); + +@@ -161,20 +162,17 @@ static int nss_match_cmd_procfs_config_h + profile_type = nss_match_cmd_get_profile_type(input_msg); + if (profile_type == NSS_MATCH_PROFILE_TYPE_NONE) { + pr_warn("%px: Please provide a valid profile type\n", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + + table_id = nss_match_instance_create(); + if (table_id <= 0) { + pr_warn("%px: Cannot create a new match instance\n", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + + nss_match_db_profile_type_add(profile_type, table_id); + pr_warn("%px: New match instance created, table_id = %d\n", ctl, table_id); +- kfree(input_msg_orig); + return count; + } + +@@ -194,32 +192,27 @@ static int nss_match_cmd_procfs_config_h + ret = sscanf(value, "%u", &table_id); + if (!ret) { + pr_warn("%px: Cannot convert to integer. Wrong input!!", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + } + + if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) { + pr_warn("%px: Invalid table_id %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (nss_match_db_table_validate(table_id)) { + pr_warn("%px: Table is already configured, %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (nss_match_db_parse_cmd(table_id, input_msg, &input_mask_param, NSS_MATCH_ADD_MASK)) { +- kfree(input_msg_orig); + return -EINVAL; + } + + nss_match_db_mask_add(&input_mask_param.msg.configure_msg, table_id); + pr_warn("%px: Mask added to instance successfully. %d", ctl, table_id); + +- kfree(input_msg_orig); + return count; + } + +@@ -240,43 +233,36 @@ static int nss_match_cmd_procfs_config_h + ret = sscanf(value, "%u", &table_id); + if (!ret) { + pr_warn("%px: Cannot convert to integer. Wrong input!!", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + } + + if ((table_id == 0) || (table_id > NSS_MATCH_INSTANCE_MAX)) { + pr_warn("%px: Invalid table_id %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (nss_match_db_table_validate(table_id)) { + pr_warn("%px: Table is already configured, %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (!nss_match_db_instance_config_get(&config_msg, &if_num, table_id)) { + pr_warn("%px: Unable to fetch stored configuration %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (if_num < 0) { + nss_match_warn("%px: Incorrect interface number: %d\n", ctl, if_num); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (nss_match_cmd_enable_instance(&config_msg, if_num, table_id)) { + pr_warn("%px: Failed to enable table %d\n", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + pr_warn("%px: Table %d enabled successfully\n", ctl, table_id); +- kfree(input_msg_orig); + return count; + } + +@@ -298,14 +284,12 @@ static int nss_match_cmd_procfs_config_h + ret = sscanf(value, "%u", &table_id); + if (!ret) { + pr_warn("%px: Cannot convert to integer. Wrong input!!", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + } + + if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) { + pr_warn("%px: Invalid table_id: %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + +@@ -313,7 +297,6 @@ static int nss_match_cmd_procfs_config_h + + if (nss_match_db_parse_cmd(table_id, input_msg, &input_rule_param, NSS_MATCH_ADD_RULE)) { + pr_warn("%px: Wrong input", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + +@@ -325,12 +308,10 @@ static int nss_match_cmd_procfs_config_h + + if (rule_id < 0) { + pr_warn("%px: Failed to add rule into table %d.\n", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + pr_warn("%px: Rule added to table %d successfully with rule_id: %d\n", ctl, table_id, rule_id); +- kfree(input_msg_orig); + return count; + } + +@@ -352,7 +333,6 @@ static int nss_match_cmd_procfs_config_h + if (!(strncasecmp(param, "rule_id", strlen("rule_id")))) { + if (!sscanf(token, "%hu", &rule_id)) { + pr_warn("%px: Cannot convert to integer. Wrong input\n", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + continue; +@@ -361,36 +341,30 @@ static int nss_match_cmd_procfs_config_h + if (!strncasecmp(param, "table_id", strlen("table_id"))) { + if (!sscanf(token, "%u", &table_id)) { + pr_warn("%px: Cannot convert to integer. Wrong input!!", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + continue; + } + +- kfree(input_msg_orig); + return -EINVAL; + } + + if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) { + pr_warn("%px: Invalid table_id: %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (rule_id == 0 || rule_id > NSS_MATCH_INSTANCE_RULE_MAX) { + pr_warn("%px: Invalid rule_id: %d", ctl, rule_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (nss_match_rule_delete(nss_ctx, rule_id, table_id)) { + pr_warn("%px: Failed to delete rule from table %d.\n", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + pr_warn("%px: Rule deleted from table %d successfully\n", ctl, table_id); +- kfree(input_msg_orig); + return count; + } + +@@ -410,39 +384,33 @@ static int nss_match_cmd_procfs_config_h + ret = sscanf(token, "%u", &table_id); + if (!ret) { + pr_warn("%px: Cannot convert to integer. Wrong input!!", input_msg); +- kfree(input_msg_orig); + return -EINVAL; + } + } + + if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) { + pr_warn("%px: Invalid table_id: %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (nss_match_instance_destroy(table_id)) { + pr_warn("%px: Failed to destroy table %d\n", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + pr_warn("%px: Table %d destroyed successfully.\n", ctl, table_id); +- kfree(input_msg_orig); + return count; + } + + default: + { + pr_warn("%px: Input command is not as per syntax, Please enter a valid command", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + } + + fail: + pr_warn("%px: Wrong input, check help. (cat /proc/sys/dev/nss/match/help)", ctl); +- kfree(input_msg_orig); + return ret; + + } +@@ -456,11 +424,12 @@ static int nss_match_cmd_procfs_reset_ne + struct net_device *dev; + uint32_t if_num, type = 0; + int ret; +- char *dev_name; +- char *cmd_buf = nss_match_data; ++ char *pos; ++ char cmd_buf[IFNAMSIZ] = {0}; + nss_tx_status_t nss_tx_status; + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); + struct nss_ctx_instance *wifili_nss_ctx = nss_wifili_get_context(); ++ size_t count = *lenp; + + if (!nss_ctx || !wifili_nss_ctx) { + pr_warn("%px: NSS Context not found. wifili_nss_ctx: %px. Reset nexthop failed", nss_ctx, wifili_nss_ctx); +@@ -473,19 +442,30 @@ static int nss_match_cmd_procfs_reset_ne + return ret; + } + ++ if (count >= sizeof(cmd_buf)) { ++ nss_match_warn("%px: Input too large: %zu\n", ctl, count); ++ return -EINVAL; ++ } ++ ++ memcpy(cmd_buf, buffer, count); ++ cmd_buf[count] = '\0'; /* Ensure null termination */ ++ ++ if ((pos = strrchr(cmd_buf, '\n')) != NULL) { ++ *pos = '\0'; ++ } ++ + /* + * Parse and read the devname from command. + */ +- dev_name = strsep(&cmd_buf, "\0"); +- dev = dev_get_by_name(&init_net, dev_name); ++ dev = dev_get_by_name(&init_net, cmd_buf); + if (!dev) { +- pr_warn("%px: Cannot find the net device: %s. Reset nexthop failed.\n", nss_ctx, dev_name); ++ pr_warn("%px: Cannot find the net device: %s. Reset nexthop failed.\n", nss_ctx, cmd_buf); + return -ENODEV; + } + + if_num = nss_cmn_get_interface_number_by_dev(dev); + if (if_num < 0) { +- pr_warn("%px: Invalid if_num for interface: %s. Reset nexthop failed.\n", nss_ctx, dev_name); ++ pr_warn("%px: Invalid if_num for interface: %s. Reset nexthop failed.\n", nss_ctx, cmd_buf); + dev_put(dev); + return -ENODEV; + } +@@ -529,7 +509,7 @@ static int nss_match_cmd_procfs_set_if_n + int table_id; + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); + struct nss_ctx_instance *wifili_nss_ctx = nss_wifili_get_context(); +- char *dev_name, *nexthop_msg; ++ char *dev_name, *pos; + char *cmd_buf = NULL; + size_t count = *lenp; + nss_tx_status_t nss_tx_status; +@@ -544,31 +524,28 @@ static int nss_match_cmd_procfs_set_if_n + return -ENOMEM; + } + +- cmd_buf = (char *)kzalloc(count + 1, GFP_KERNEL); +- nexthop_msg = cmd_buf; +- if (!cmd_buf) { +- pr_warn("%px: Cannot allocate buffer to read input", nss_ctx); +- return -ENOMEM; ++ if (count >= sizeof(cmd_buf)) { ++ nss_match_warn("%px: Input too large: %zu\n", ctl, count); ++ return -EINVAL; + } + +- if (copy_from_user(cmd_buf, buffer, count)) { +- kfree(nexthop_msg); +- pr_warn("%px: Cannot copy user's entry to kernel memory\n", nss_ctx); +- return -EFAULT; ++ memcpy(cmd_buf, buffer, count); ++ cmd_buf[count] = '\0'; /* Ensure null termination */ ++ ++ if ((pos = strrchr(cmd_buf, '\n')) != NULL) { ++ *pos = '\0'; + } + + dev_name = strsep(&cmd_buf, " "); + dev = dev_get_by_name(&init_net, dev_name); + if (!dev) { + pr_warn("%px: Cannot find the net device\n", nss_ctx); +- kfree(nexthop_msg); + return -ENODEV; + } + + if_num = nss_cmn_get_interface_number_by_dev(dev); + if (if_num < 0) { + pr_warn("%px: Invalid interface number:%d\n", nss_ctx, if_num); +- kfree(nexthop_msg); + dev_put(dev); + return -ENODEV; + } +@@ -576,20 +553,17 @@ static int nss_match_cmd_procfs_set_if_n + if (isdigit(cmd_buf[0])) { + if (!sscanf(cmd_buf, "%u", &nh_if_num)) { + pr_warn("%px, Failed to write the nexthop if_num token to integer\n", nss_ctx); +- kfree(nexthop_msg); + dev_put(dev); + return -EFAULT; + } + } else { + pr_warn("%px: Invalid nexthop interface number.\n", nss_ctx); +- kfree(nexthop_msg); + dev_put(dev); + return -ENODEV; + } + + if (nh_if_num < 0) { + pr_warn("%px: Invalid nexthop interface number:%d\n", nss_ctx, if_num); +- kfree(nexthop_msg); + dev_put(dev); + return -ENODEV; + } +@@ -597,7 +571,6 @@ static int nss_match_cmd_procfs_set_if_n + table_id = nss_match_get_table_id_by_ifnum(nh_if_num); + if (table_id <= 0 || table_id > NSS_MATCH_INSTANCE_MAX) { + pr_warn("Invalid match interface. Failed to set %d as nexthop.\n", nh_if_num); +- kfree(nexthop_msg); + dev_put(dev); + return -EFAULT; + } +@@ -614,7 +587,6 @@ static int nss_match_cmd_procfs_set_if_n + nss_tx_status = nss_phys_if_set_nexthop(nss_ctx, if_num, nh_if_num); + } else { + pr_warn("Invalid interface to set nexthop. Failed to set nexthop on if_num %d.\n", if_num); +- kfree(nexthop_msg); + dev_put(dev); + return -EFAULT; + } +@@ -623,7 +595,6 @@ static int nss_match_cmd_procfs_set_if_n + pr_warn("%px: Sending message failed, cannot change nexthop\n", nss_ctx); + } + +- kfree(nexthop_msg); + dev_put(dev); + return ret; + } diff --git a/qca-nss-clients/patches-11.4/0033-qdisc-backport-12.5.patch b/qca-nss-clients/patches-11.4/0033-qdisc-backport-12.5.patch new file mode 100644 index 0000000..72d3453 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0033-qdisc-backport-12.5.patch @@ -0,0 +1,377 @@ +From fa3a58742c4721221cb9a5ab11c65b6d60b77477 Mon Sep 17 00:00:00 2001 +From: Aniruddha Bhat Anemajalu +Date: Tue, 11 Jan 2022 11:22:08 -0800 +Subject: [PATCH] [qca-nss-clients] Check for qdisc before deleting the class + +Do not allow deleting the class before deleting the underlying Qdisc. + +Change-Id: I40f611cb1a5342ed58b4b1abcf1254d8a981a760 +Signed-off-by: Aniruddha Bhat Anemajalu +--- + nss_qdisc/nss_bf.c | 14 ++++++++++---- + nss_qdisc/nss_htb.c | 11 ++++++++--- + nss_qdisc/nss_wrr.c | 14 ++++++++++---- + 3 files changed, 28 insertions(+), 11 deletions(-) + +--- a/nss_qdisc/nss_bf.c ++++ b/nss_qdisc/nss_bf.c +@@ -1,9 +1,13 @@ + /* + ************************************************************************** + * Copyright (c) 2014-2017, 2019-2020, The Linux Foundation. All rights reserved. ++ * ++ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -309,11 +313,14 @@ static int nss_bf_delete_class(struct Qd + struct nss_qdisc *nq_child = (struct nss_qdisc *)qdisc_priv(cl->qdisc); + + /* +- * Since all classes are leaf nodes in our case, we dont have to make +- * that check. ++ * If the class is the root class or has qdiscs attached, we do not ++ * support deleting it. + */ +- if (cl == &q->root) ++ if ((cl == &q->root) || (cl->qdisc != &noop_qdisc)) { ++ nss_qdisc_warning("Cannot delete bf class %x as it is the root " ++ "class or has child qdisc attached\n", cl->nq.qos_tag); + return -EBUSY; ++ } + + /* + * The message to NSS should be sent to the parent of this class +@@ -327,7 +334,6 @@ static int nss_bf_delete_class(struct Qd + } + + sch_tree_lock(sch); +- qdisc_reset(cl->qdisc); + qdisc_class_hash_remove(&q->clhash, &cl->cl_common); + refcnt = nss_qdisc_atomic_sub_return(&cl->nq); + sch_tree_unlock(sch); +--- a/nss_qdisc/nss_htb.c ++++ b/nss_qdisc/nss_htb.c +@@ -1,9 +1,13 @@ + /* + ************************************************************************** + * Copyright (c) 2014-2017, 2019-2021, The Linux Foundation. All rights reserved. ++ * ++ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -534,10 +538,12 @@ static int nss_htb_delete_class(struct Q + int refcnt; + + /* +- * If the class still has child nodes, then we do not ++ * If the class still has child nodes or qdiscs, then we do not + * support deleting it. + */ +- if (cl->children) { ++ if ((cl->children) || (cl->qdisc != &noop_qdisc)) { ++ nss_qdisc_warning("Cannot delete htb class %x with child nodes " ++ "or qdisc attached\n", cl->nq.qos_tag); + return -EBUSY; + } + +@@ -568,7 +574,6 @@ static int nss_htb_delete_class(struct Q + } + + sch_tree_lock(sch); +- qdisc_reset(cl->qdisc); + qdisc_class_hash_remove(&q->clhash, &cl->sch_common); + + /* +--- a/nss_qdisc/nss_wrr.c ++++ b/nss_qdisc/nss_wrr.c +@@ -1,9 +1,13 @@ + /* + ************************************************************************** + * Copyright (c) 2014-2017, 2019-2021, The Linux Foundation. All rights reserved. ++ * ++ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -418,11 +422,14 @@ static int nss_wrr_delete_class(struct Q + int refcnt; + + /* +- * Since all classes are leaf nodes in our case, we dont have to make +- * that check. ++ * If the class is a root class or has a child qdisc attached ++ * we do not support deleting it. + */ +- if (cl == &q->root) ++ if ((cl == &q->root) || (cl->qdisc != &noop_qdisc)) { ++ nss_qdisc_warning("Cannot delete wrr class %x as it is the " ++ "root class or has a child qdisc attached\n", cl->nq.qos_tag); + return -EBUSY; ++ } + + /* + * The message to NSS should be sent to the parent of this class +@@ -436,7 +443,6 @@ static int nss_wrr_delete_class(struct Q + } + + sch_tree_lock(sch); +- qdisc_reset(cl->qdisc); + qdisc_class_hash_remove(&q->clhash, &cl->cl_common); + + refcnt = nss_qdisc_atomic_sub_return(&cl->nq); +--- a/nss_qdisc/nss_ppe.c ++++ b/nss_qdisc/nss_ppe.c +@@ -1,7 +1,11 @@ + /* + ************************************************************************** + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. ++ * ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +@@ -28,12 +32,9 @@ + /* + * Max Resources per port + * +- * Currently, we are using only one multicast queue. + * In case of Loopback port, the resources are reserved + * for qdisc functionality. + */ +-#define NSS_PPE_MCAST_QUEUE_MAX 1 +- + #define NSS_PPE_LOOPBACK_L0_SP_MAX 1 + #define NSS_PPE_LOOPBACK_L0_CDRR_MAX 16 + #define NSS_PPE_LOOPBACK_L0_EDRR_MAX 16 +@@ -126,7 +127,7 @@ static struct nss_ppe_res *nss_ppe_res_e + + spin_lock_bh(&ppe_port->lock); + for (i = max; i > 0; i--) { +- res = kzalloc(sizeof(struct nss_ppe_res), GFP_KERNEL); ++ res = kzalloc(sizeof(struct nss_ppe_res), GFP_ATOMIC); + if (!res) { + nss_qdisc_error("Free queue list allocation failed for port %u\n", port); + goto fail; +@@ -275,9 +276,10 @@ int nss_ppe_port_res_alloc(void) + ppe_qdisc_port[i].base[NSS_PPE_UCAST_QUEUE] = cfg.ucastq_start; + + /* +- * Even though we reserve more mcast queues in the device tree, we only use 1 in qdiscs. ++ * Even though we reserve more mcast queues in the device tree, we only use 1 in qdiscs ++ * for the default queue. + */ +- ppe_qdisc_port[i].max[NSS_PPE_MCAST_QUEUE] = NSS_PPE_MCAST_QUEUE_MAX; ++ ppe_qdisc_port[i].max[NSS_PPE_MCAST_QUEUE] = cfg.mcastq_num; + ppe_qdisc_port[i].base[NSS_PPE_MCAST_QUEUE] = cfg.mcastq_start; + + ppe_qdisc_port[i].max[NSS_PPE_L0_CDRR] = cfg.l0cdrr_num; +@@ -576,6 +578,36 @@ static void nss_ppe_all_queue_enable(uin + } + + /* ++ * nss_ppe_assigned_queue_enable() ++ * Enables all level L0 queues corresponding to a port in SSDK. ++ */ ++static void nss_ppe_assigned_queue_enable(uint32_t port_num) ++{ ++ uint32_t qid = nss_ppe_base_get(port_num, NSS_PPE_UCAST_QUEUE); ++ uint32_t mcast_qid = nss_ppe_base_get(port_num, NSS_PPE_MCAST_QUEUE); ++ struct nss_ppe_res *res; ++ struct nss_ppe_port *ppe_port = &ppe_qdisc_port[port_num]; ++ ++ spin_lock_bh(&ppe_port->lock); ++ res = ppe_port->res_used[NSS_PPE_UCAST_QUEUE]; ++ while (res) { ++ fal_qm_enqueue_ctrl_set(0, qid + res->offset, 1); ++ fal_scheduler_dequeue_ctrl_set(0, qid + res->offset, 1); ++ res = res->next; ++ } ++ ++ res = ppe_port->res_used[NSS_PPE_MCAST_QUEUE]; ++ while (res) { ++ fal_qm_enqueue_ctrl_set(0, mcast_qid + res->offset, 1); ++ fal_scheduler_dequeue_ctrl_set(0, mcast_qid + res->offset, 1); ++ res = res->next; ++ } ++ ++ spin_unlock_bh(&ppe_port->lock); ++ nss_qdisc_info("Enable SSDK level0 queue scheduler successful\n"); ++} ++ ++/* + * nss_ppe_l1_queue_scheduler_configure() + * Configures Level 1 queue scheduler in SSDK. + */ +@@ -585,11 +617,6 @@ static int nss_ppe_l1_queue_scheduler_co + uint32_t port_num = nss_ppe_port_num_get(nq); + struct nss_ppe_qdisc *npq = &nq->npq; + +- if (npq->scheduler.drr_weight >= NSS_PPE_DRR_WEIGHT_MAX) { +- nss_qdisc_warning("DRR weight:%d should be less than 1024\n", npq->scheduler.drr_weight); +- return -EINVAL; +- } +- + /* + * Disable all queues and set Level 1 SSDK configuration + * We need to disable and flush the queues before +@@ -597,6 +624,15 @@ static int nss_ppe_l1_queue_scheduler_co + */ + nss_ppe_all_queue_disable(port_num); + ++ if (npq->scheduler.drr_weight >= NSS_PPE_DRR_WEIGHT_MAX) { ++ /* ++ * Currently assigned queues are enabled back by ++ * caller ++ */ ++ nss_qdisc_warning("DRR weight:%d should be less than 1024\n", npq->scheduler.drr_weight); ++ return -EINVAL; ++ } ++ + memset(&l1cfg, 0, sizeof(l1cfg)); + l1cfg.sp_id = port_num; + +@@ -614,11 +650,10 @@ static int nss_ppe_l1_queue_scheduler_co + port_num, npq->l0spid, l1cfg.c_drr_id, l1cfg.c_pri, l1cfg.c_drr_wt, l1cfg.e_drr_id, l1cfg.e_pri, l1cfg.e_drr_wt, l1cfg.sp_id); + if (fal_queue_scheduler_set(0, npq->l0spid, NSS_PPE_FLOW_LEVEL - 1, port_num, &l1cfg) != 0) { + nss_qdisc_error("SSDK level1 queue scheduler configuration failed\n"); +- nss_ppe_all_queue_enable(port_num); + return -EINVAL; + } + +- nss_ppe_all_queue_enable(port_num); ++ nss_ppe_assigned_queue_enable(port_num); + + nss_qdisc_info("SSDK level1 queue scheduler configuration successful\n"); + return 0; +@@ -672,6 +707,7 @@ static int nss_ppe_l1_queue_scheduler_se + if (nss_ppe_l1_queue_scheduler_configure(nq) != 0) { + nss_qdisc_error("SSDK level1 queue scheduler configuration failed\n"); + nss_ppe_l1_res_free(nq); ++ nss_ppe_assigned_queue_enable(nss_ppe_port_num_get(nq)); + return -EINVAL; + } + +@@ -758,11 +794,13 @@ static int nss_ppe_l0_queue_scheduler_de + port_num, npq->q.ucast_qid, l0cfg.c_drr_id, l0cfg.c_pri, l0cfg.c_drr_wt, l0cfg.e_drr_id, l0cfg.e_pri, l0cfg.e_drr_wt, l0cfg.sp_id); + if (fal_queue_scheduler_set(0, npq->q.ucast_qid, NSS_PPE_QUEUE_LEVEL - 1, port_num, &l0cfg) != 0) { + nss_qdisc_error("SSDK level0 queue scheduler configuration failed\n"); +- nss_ppe_all_queue_enable(port_num); ++ nss_ppe_assigned_queue_enable(port_num); + return -EINVAL; + } + +- nss_ppe_all_queue_enable(port_num); ++ /* ++ * Assinged queues are enabled after the current resource is freed. ++ */ + + nss_qdisc_info("SSDK level0 queue scheduler configuration successful\n"); + return 0; +@@ -781,9 +819,11 @@ static int nss_ppe_l0_queue_scheduler_re + + if (nss_ppe_l0_res_free(nq) != 0) { + nss_qdisc_error("Level0 scheduler resources de-allocation failed\n"); ++ nss_ppe_assigned_queue_enable(nss_ppe_port_num_get(nq)); + return -EINVAL; + } + ++ nss_ppe_assigned_queue_enable(nss_ppe_port_num_get(nq)); + nss_qdisc_info("SSDK level0 queue scheduler configuration successful\n"); + return 0; + } +@@ -871,11 +911,6 @@ static int nss_ppe_l0_queue_scheduler_co + uint32_t port_num = nss_ppe_port_num_get(nq); + struct nss_ppe_qdisc *npq = &nq->npq; + +- if (npq->scheduler.drr_weight >= NSS_PPE_DRR_WEIGHT_MAX) { +- nss_qdisc_warning("DRR weight:%d should be less than 1024\n", npq->scheduler.drr_weight); +- return -EINVAL; +- } +- + /* + * Disable all queues and set Level 0 SSDK configuration + * We need to disable and flush the queues before +@@ -883,6 +918,15 @@ static int nss_ppe_l0_queue_scheduler_co + */ + nss_ppe_all_queue_disable(port_num); + ++ if (npq->scheduler.drr_weight >= NSS_PPE_DRR_WEIGHT_MAX) { ++ /* ++ * Currently assigned queues are enabled back by ++ * caller ++ */ ++ nss_qdisc_warning("DRR weight:%d should be less than 1024\n", npq->scheduler.drr_weight); ++ return -EINVAL; ++ } ++ + memset(&l0cfg, 0, sizeof(l0cfg)); + l0cfg.sp_id = npq->l0spid; + l0cfg.c_drr_wt = npq->scheduler.drr_weight ? npq->scheduler.drr_weight : 1; +@@ -899,7 +943,6 @@ static int nss_ppe_l0_queue_scheduler_co + port_num, npq->q.ucast_qid, l0cfg.c_drr_id, l0cfg.c_pri, l0cfg.c_drr_wt, l0cfg.e_drr_id, l0cfg.e_pri, l0cfg.e_drr_wt, l0cfg.sp_id); + if (fal_queue_scheduler_set(0, npq->q.ucast_qid, NSS_PPE_QUEUE_LEVEL - 1, port_num, &l0cfg) != 0) { + nss_qdisc_error("SSDK level0 queue scheduler configuration failed\n"); +- nss_ppe_all_queue_enable(port_num); + return -EINVAL; + } + +@@ -917,12 +960,11 @@ static int nss_ppe_l0_queue_scheduler_co + port_num, npq->q.mcast_qid, l0cfg.c_drr_id, l0cfg.c_pri, l0cfg.c_drr_wt, l0cfg.e_drr_id, l0cfg.e_pri, l0cfg.e_drr_wt, l0cfg.sp_id); + if (fal_queue_scheduler_set(0, npq->q.mcast_qid, NSS_PPE_QUEUE_LEVEL - 1, port_num, &l0cfg) != 0) { + nss_qdisc_error("SSDK level0 multicast queue scheduler configuration failed\n"); +- nss_ppe_all_queue_enable(port_num); + return -EINVAL; + } + } + +- nss_ppe_all_queue_enable(port_num); ++ nss_ppe_assigned_queue_enable(port_num); + + nss_qdisc_info("SSDK level0 queue scheduler configuration successful\n"); + return 0; +@@ -955,6 +997,7 @@ static int nss_ppe_l0_queue_scheduler_se + if (nss_ppe_l0_queue_scheduler_configure(nq) != 0) { + nss_qdisc_error("SSDK level0 queue scheduler configuration failed\n"); + nss_ppe_l0_res_free(nq); ++ nss_ppe_assigned_queue_enable(nss_ppe_port_num_get(nq)); + return -EINVAL; + } + +@@ -1381,7 +1424,7 @@ static int nss_ppe_default_conf_set(uint + */ + if (fal_port_scheduler_cfg_reset(0, port_num) != 0) { + nss_qdisc_error("SSDK reset default queue configuration failed\n"); +- nss_ppe_all_queue_enable(port_num); ++ nss_ppe_assigned_queue_enable(port_num); + return -EINVAL; + } + +@@ -1960,7 +2003,7 @@ void nss_ppe_all_queue_enable_hybrid(str + || (nq->type == NSS_SHAPER_NODE_TYPE_BF) + || (nq->type == NSS_SHAPER_NODE_TYPE_WRED)) { + uint32_t port_num = nss_ppe_port_num_get(nq); +- nss_ppe_all_queue_enable(port_num); ++ nss_ppe_assigned_queue_enable(port_num); + nss_qdisc_info("Queues in hybrid mode enabled successfully for Qdisc %px (type %d)\n", nq, nq->type); + } + } diff --git a/qca-nss-clients/patches-11.4/0034-ipsecmgr-backport-12.5.patch b/qca-nss-clients/patches-11.4/0034-ipsecmgr-backport-12.5.patch new file mode 100644 index 0000000..cb2b4ee --- /dev/null +++ b/qca-nss-clients/patches-11.4/0034-ipsecmgr-backport-12.5.patch @@ -0,0 +1,540 @@ +--- a/ipsecmgr/v2.0/plugins/klips/nss_ipsec_klips.c ++++ b/ipsecmgr/v2.0/plugins/klips/nss_ipsec_klips.c +@@ -142,7 +142,6 @@ static int nss_ipsec_klips_offload_esp(s + static struct net_protocol esp_protocol = { + .handler = nss_ipsec_klips_offload_esp, + .no_policy = 1, +- .netns_ok = 1, + }; + + /* +@@ -300,7 +299,7 @@ static struct nss_ipsec_klips_tun *nss_i + * Read/write lock needs to taken by the caller since sa + * table is looked up here + */ +- BUG_ON(write_can_lock(&tunnel_map.lock)); ++ lockdep_assert_held_write(&tunnel_map.lock); + + if (!klips_dev) { + return NULL; +@@ -383,7 +382,7 @@ static struct nss_ipsec_klips_tun *nss_i + * Read/write lock needs to be taken by the caller since tunnel + * table is looked up here + */ +- BUG_ON(write_can_lock(&tunnel_map.lock)); ++ lockdep_assert_held_write(&tunnel_map.lock); + + for (i = 0, tun = tunnel_map.tbl; i < tunnel_map.max; i++, tun++) { + if (!tun->klips_dev) { +@@ -434,7 +433,7 @@ static struct nss_ipsec_klips_sa *nss_ip + * Read/write lock needs to taken by the caller since sa + * table is looked up here + */ +- BUG_ON(write_can_lock(&tunnel_map.lock)); ++ lockdep_assert_held_write(&tunnel_map.lock); + + list_for_each_entry_safe(sa, tmp, head, list) { + if (sa->sid == crypto_idx) +@@ -458,7 +457,7 @@ static void nss_ipsec_klips_sa_flush(str + * Read/write lock needs to taken by the caller since sa + * table is modified here + */ +- BUG_ON(write_can_lock(&tunnel_map.lock)); ++ lockdep_assert_held_write(&tunnel_map.lock); + + list_for_each_entry_safe(sa, tmp, head, list) { + list_del_init(&sa->list); +@@ -1220,7 +1219,7 @@ static void nss_ipsec_klips_register_nat + /* + * write lock is needed as we are modifying tunnel entry. + */ +- BUG_ON(write_can_lock(&tunnel_map.lock)); ++ lockdep_assert_held_write(&tunnel_map.lock); + + sock_hold(sk); + tun->sk_encap_rcv = udp_sk(sk)->encap_rcv; +@@ -1237,7 +1236,7 @@ static void nss_ipsec_klips_unregister_n + /* + * write lock is needed as we are modifying tunnel entry. + */ +- BUG_ON(write_can_lock(&tunnel_map.lock)); ++ lockdep_assert_held_write(&tunnel_map.lock); + + xchg(&udp_sk(tun->sk)->encap_rcv, tun->sk_encap_rcv); + sock_put(tun->sk); +--- a/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm.c ++++ b/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm.c +@@ -1,5 +1,6 @@ + /* Copyright (c) 2021, The Linux Foundation. All rights reserved. + * ++ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. +@@ -254,7 +255,7 @@ static void nss_ipsec_xfrm_flush_flow_by + + for (count = NSS_IPSEC_XFRM_FLOW_DB_MAX; count--; db_head++) { + list_for_each_entry_safe(flow, tmp, db_head, list_entry) { +- if (flow->sa == sa) { ++ if (READ_ONCE(flow->sa) == sa) { + list_del_init(&flow->list_entry); + list_add(&flow->list_entry, &free_head); + } +@@ -1222,6 +1223,7 @@ drop: + return -EINVAL; + } + ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 4, 0)) + /* + * nss_ipsec_xfrm_v4_output_finish() + * This is called for non-offloaded transformations after the NF_POST routing hooks +@@ -1243,9 +1245,8 @@ static int nss_ipsec_xfrm_v4_output_fini + */ + static int nss_ipsec_xfrm_v4_extract_input(struct xfrm_state *x, struct sk_buff *skb) + { +- struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; +- + nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb); ++ struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + return drv->xsa.v4->extract_input(x, skb); + } + +@@ -1257,11 +1258,12 @@ static int nss_ipsec_xfrm_v4_extract_inp + */ + static int nss_ipsec_xfrm_v4_extract_output(struct xfrm_state *x, struct sk_buff *skb) + { +- struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + + nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb); ++ struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + return drv->xsa.v4->extract_output(x, skb); + } ++#endif + + /* + * nss_ipsec_xfrm_v4_transport_finish() +@@ -1360,14 +1362,14 @@ fallback: + * nss_ipsec_xfrm_esp_init_state() + * Initialize IPsec xfrm state of type ESP. + */ +-static int nss_ipsec_xfrm_esp_init_state(struct xfrm_state *x) ++static int nss_ipsec_xfrm_esp_init_state(struct xfrm_state *x, struct netlink_ext_ack *extac) + { + struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + struct nss_ipsec_xfrm_tunnel *tun = NULL; + struct nss_ipsec_xfrm_sa *sa = NULL; + xfrm_address_t remote = {0}; + xfrm_address_t local = {0}; +- struct net_device *local_dev; ++ struct net_device *local_dev = NULL; + bool new_tun = 0; + size_t ip_addr_len; + +@@ -1375,7 +1377,7 @@ static int nss_ipsec_xfrm_esp_init_state + local_dev = ip_dev_find(&init_net, x->id.daddr.a4); + ip_addr_len = sizeof(local.a4); + } else { +- local_dev = ipv6_dev_find(&init_net, &x->id.daddr.in6, 1); ++ local_dev = ipv6_dev_find(&init_net, &x->id.daddr.in6, local_dev); + ip_addr_len = sizeof(local.a6); + } + +@@ -1716,6 +1718,7 @@ drop: + return -EINVAL; + } + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + /* + * nss_ipsec_xfrm_v6_output_finish() + * This is called for non-offloaded transformations after the NF_POST routing hooks +@@ -1737,9 +1740,9 @@ static int nss_ipsec_xfrm_v6_output_fini + */ + static int nss_ipsec_xfrm_v6_extract_input(struct xfrm_state *x, struct sk_buff *skb) + { +- struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + + nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb); ++ struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + return drv->xsa.v6->extract_input(x, skb); + } + +@@ -1751,11 +1754,11 @@ static int nss_ipsec_xfrm_v6_extract_inp + */ + static int nss_ipsec_xfrm_v6_extract_output(struct xfrm_state *x, struct sk_buff *skb) + { +- struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; +- + nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb); ++ struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + return drv->xsa.v6->extract_output(x, skb); + } ++#endif + + /* + * nss_ipsec_xfrm_v6_transport_finish() +@@ -1783,22 +1786,25 @@ void nss_ipsec_xfrm_v6_local_error(struc + return drv->xsa.v6->local_error(skb, mtu); + } + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + /* + * nss_ipsec_xfrm_v6_esp_hdr_offset() + * Invoked by stack for IPv6 transport mode in encap. + * Redirect to the native version. + */ +-static int nss_ipsec_xfrm_v6_esp_hdr_offset(struct xfrm_state *x, struct sk_buff *skb, u8 **prevhdr) ++static int nss_ipsec_xfrm_v6_esp_hdr_offset(struct xfrm_state *x, struct sk_buff *skb, u8 **prevhdr) + { +- struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + + nss_ipsec_xfrm_trace("%px: Redirect to native esp6 stack\n", skb); +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) +- return drv->xsa.v6->type_map[IPPROTO_ESP]->hdr_offset(x, skb, prevhdr); +-#else +- return drv->xsa.v6->type_esp->hdr_offset(x, skb, prevhdr); +-#endif ++ ++ struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) ++ return drv->xsa.v6->type_map[IPPROTO_ESP]->hdr_offset(x, skb, prevhdr); ++ #else ++ return drv->xsa.v6->type_esp->hdr_offset(x, skb, prevhdr); ++ #endif + } ++#endif + + /* + * nss_ipsec_xfrm_esp6_rcv() +@@ -1949,7 +1955,6 @@ static void nss_ipsec_xfrm_state_delete( + nss_ipsec_xfrm_del_tun(drv, tun); + } + +- return; + } + + /* +@@ -2018,9 +2023,11 @@ static struct xfrm_state_afinfo xfrm_v4_ + .init_temprop = nss_ipsec_xfrm_v4_init_param, + #endif + .output = nss_ipsec_xfrm_v4_output, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + .output_finish = nss_ipsec_xfrm_v4_output_finish, + .extract_input = nss_ipsec_xfrm_v4_extract_input, + .extract_output = nss_ipsec_xfrm_v4_extract_output, ++#endif + .transport_finish = nss_ipsec_xfrm_v4_transport_finish, + .local_error = nss_ipsec_xfrm_v4_local_error, + }; +@@ -2065,7 +2072,6 @@ struct xfrm_mode xfrm_v6_mode_map[XFRM_M + * IPv4 xfrm_type ESP object. + */ + static const struct xfrm_type xfrm_v4_type = { +- .description = "NSS ESP4", + .owner = THIS_MODULE, + .proto = IPPROTO_ESP, + .flags = XFRM_TYPE_REPLAY_PROT, +@@ -2101,9 +2107,11 @@ static struct xfrm_state_afinfo xfrm_v6_ + .state_sort = nss_ipsec_xfrm_v6_sort_state, + #endif + .output = nss_ipsec_xfrm_v6_output, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + .output_finish = nss_ipsec_xfrm_v6_output_finish, + .extract_input = nss_ipsec_xfrm_v6_extract_input, + .extract_output = nss_ipsec_xfrm_v6_extract_output, ++#endif + .transport_finish = nss_ipsec_xfrm_v6_transport_finish, + .local_error = nss_ipsec_xfrm_v6_local_error, + }; +@@ -2112,7 +2120,6 @@ static struct xfrm_state_afinfo xfrm_v6_ + * IPv6 xfrm_type ESP object. + */ + static const struct xfrm_type xfrm_v6_type = { +- .description = "NSS ESP6", + .owner = THIS_MODULE, + .proto = IPPROTO_ESP, + .flags = XFRM_TYPE_REPLAY_PROT, +@@ -2121,7 +2128,9 @@ static const struct xfrm_type xfrm_v6_ty + .get_mtu = nss_ipsec_xfrm_esp_get_mtu, + .input = nss_ipsec_xfrm_esp_input, + .output = nss_ipsec_xfrm_esp_output, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + .hdr_offset = nss_ipsec_xfrm_v6_esp_hdr_offset, ++#endif + }; + + /* +@@ -2207,7 +2216,6 @@ static void nss_ipsec_xfrm_restore_afinf + } + + xfrm_unregister_type(base, family); +- + xfrm_state_update_afinfo(family, afinfo); + } + +@@ -2292,14 +2300,10 @@ static void nss_ipsec_xfrm_override_afin + */ + int __init nss_ipsec_xfrm_init_module(void) + { +- + rwlock_init(&g_ipsec_xfrm.lock); +- + nss_ipsec_xfrm_init_tun_db(&g_ipsec_xfrm); + nss_ipsec_xfrm_init_flow_db(&g_ipsec_xfrm); +- + init_completion(&g_ipsec_xfrm.complete); +- + net_get_random_once(&g_ipsec_xfrm.hash_nonce, sizeof(g_ipsec_xfrm.hash_nonce)); + + /* +@@ -2327,7 +2331,6 @@ int __init nss_ipsec_xfrm_init_module(vo + nss_ipsec_xfrm_override_afinfo(&g_ipsec_xfrm, AF_INET6); + + ecm_interface_ipsec_register_callbacks(&xfrm_ecm_ipsec_cb); +- ecm_notifier_register_connection_notify(&xfrm_ecm_notifier); + + #if defined(NSS_L2TPV2_ENABLED) + l2tpmgr_register_ipsecmgr_callback_by_ipaddr(&xfrm_l2tp); +@@ -2336,6 +2339,7 @@ int __init nss_ipsec_xfrm_init_module(vo + /* + * Register for xfrm events + */ ++ ecm_notifier_register_connection_notify(&xfrm_ecm_notifier); + xfrm_register_km(&nss_ipsec_xfrm_mgr); + + /* +@@ -2346,6 +2350,7 @@ int __init nss_ipsec_xfrm_init_module(vo + return 0; + + unreg_v4_handler: ++ xfrm4_protocol_deregister(&xfrm4_proto, IPPROTO_ESP); + xfrm6_protocol_deregister(&xfrm6_proto, IPPROTO_ESP); + return -EAGAIN; + } +--- a/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_sa.c ++++ b/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_sa.c +@@ -55,13 +55,15 @@ struct nss_ipsec_xfrm_algo { + static struct nss_ipsec_xfrm_algo xfrm_algo[] = { + {.cipher_name = "cbc(aes)", .auth_name = "hmac(sha1)", .algo = NSS_IPSECMGR_ALGO_AES_CBC_SHA1_HMAC}, + {.cipher_name = "cbc(des3_ede)", .auth_name = "hmac(sha1)", .algo = NSS_IPSECMGR_ALGO_3DES_CBC_SHA1_HMAC}, ++#ifndef NSS_IPSEC_XFRM_IPQ50XX + {.cipher_name = "cbc(aes)", .auth_name = "hmac(md5)", .algo = NSS_IPSECMGR_ALGO_AES_CBC_MD5_HMAC}, + {.cipher_name = "cbc(des3_ede)", .auth_name = "hmac(md5)", .algo = NSS_IPSECMGR_ALGO_3DES_CBC_MD5_HMAC}, + {.cipher_name = "rfc4106(gcm(aes))", .auth_name = "rfc4106(gcm(aes))", .algo = NSS_IPSECMGR_ALGO_AES_GCM_GMAC_RFC4106}, + {.cipher_name = "ecb(cipher_null)", .auth_name = "hmac(sha1)", .algo = NSS_IPSECMGR_ALGO_NULL_CIPHER_SHA1_HMAC}, ++ {.cipher_name = "ecb(cipher_null)", .auth_name = "hmac(sha256)", .algo = NSS_IPSECMGR_ALGO_NULL_CIPHER_SHA256_HMAC}, ++#endif + {.cipher_name = "cbc(aes)", .auth_name = "hmac(sha256)", .algo = NSS_IPSECMGR_ALGO_AES_CBC_SHA256_HMAC}, + {.cipher_name = "cbc(des3_ede)", .auth_name = "hmac(sha256)", .algo = NSS_IPSECMGR_ALGO_3DES_CBC_SHA256_HMAC}, +- {.cipher_name = "ecb(cipher_null)", .auth_name = "hmac(sha256)", .algo = NSS_IPSECMGR_ALGO_NULL_CIPHER_SHA256_HMAC}, + }; + + /* +@@ -181,7 +183,7 @@ static bool nss_ipsec_xfrm_sa_init_crypt + */ + static void nss_ipsec_xfrm_sa_init_tuple(struct nss_ipsec_xfrm_sa *sa, struct xfrm_state *x) + { +- struct net_device *local_dev; ++ struct net_device *local_dev = NULL; + + sa->type = NSS_IPSECMGR_SA_TYPE_ENCAP; + sa->tuple.spi_index = ntohl(x->id.spi); +@@ -215,7 +217,7 @@ static void nss_ipsec_xfrm_sa_init_tuple + sa->tuple.dest_ip[2] = ntohl(x->id.daddr.a6[2]); + sa->tuple.dest_ip[3] = ntohl(x->id.daddr.a6[3]); + +- local_dev = ipv6_dev_find(&init_net, (struct in6_addr *)x->id.daddr.a6, 1); ++ local_dev = ipv6_dev_find(&init_net, (struct in6_addr *)x->id.daddr.a6, local_dev); + } + + /* +--- a/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.c ++++ b/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.c +@@ -130,7 +130,6 @@ err: + drop: + atomic64_inc(&drv->stats.inner_drop); + dev_kfree_skb_any(skb); +- return; + } + + /* +@@ -194,7 +193,6 @@ static void nss_ipsec_xfrm_tunnel_rx_out + drop: + dev_kfree_skb_any(skb); + atomic64_inc(&drv->stats.outer_drop); +- return; + } + + /* +--- a/ipsecmgr/v2.0/nss_ipsecmgr.c ++++ b/ipsecmgr/v2.0/nss_ipsecmgr.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -278,11 +278,11 @@ static int __init nss_ipsecmgr_init(void + */ + nss_ipsecmgr_configure(&ipsecmgr_drv->cfg_work.work); + +- write_lock(&ipsecmgr_drv->lock); ++ write_lock_bh(&ipsecmgr_drv->lock); + list_add(&tun->list, &ipsecmgr_drv->tun_db); + + ipsecmgr_drv->max_mtu = dev->mtu; +- write_unlock(&ipsecmgr_drv->lock); ++ write_unlock_bh(&ipsecmgr_drv->lock); + + nss_ipsecmgr_info("NSS IPsec manager loaded: %s\n", NSS_CLIENT_BUILD_ID); + return 0; +--- a/ipsecmgr/v2.0/nss_ipsecmgr_flow.c ++++ b/ipsecmgr/v2.0/nss_ipsecmgr_flow.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -149,10 +149,10 @@ static bool nss_ipsecmgr_flow_update_db( + + hash_idx = nss_ipsecmgr_flow_tuple2hash(&flow->state.tuple, NSS_IPSECMGR_FLOW_MAX); + +- write_lock(&ipsecmgr_drv->lock); ++ write_lock_bh(&ipsecmgr_drv->lock); + sa = nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, sa_tuple); + if (!sa) { +- write_unlock(&ipsecmgr_drv->lock); ++ write_unlock_bh(&ipsecmgr_drv->lock); + nss_ipsecmgr_trace("%px: failed to find SA during flow update", flow); + return false; + } +@@ -163,7 +163,7 @@ static bool nss_ipsecmgr_flow_update_db( + */ + nss_ipsecmgr_ref_add(&flow->ref, &sa->ref); + list_add(&flow->list, &ipsecmgr_drv->flow_db[hash_idx]); +- write_unlock(&ipsecmgr_drv->lock); ++ write_unlock_bh(&ipsecmgr_drv->lock); + return true; + } + +--- a/ipsecmgr/v2.0/nss_ipsecmgr_tunnel.c ++++ b/ipsecmgr/v2.0/nss_ipsecmgr_tunnel.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -273,7 +273,7 @@ static void nss_ipsecmgr_tunnel_mtu_upda + uint16_t max_mtu = 0; + bool update_mtu = false; + +- write_lock(&ipsecmgr_drv->lock); ++ write_lock_bh(&ipsecmgr_drv->lock); + list_for_each_entry(tun, head, list) { + if (tun->dev->mtu > max_mtu) + max_mtu = tun->dev->mtu; +@@ -284,7 +284,7 @@ static void nss_ipsecmgr_tunnel_mtu_upda + update_mtu = true; + } + +- write_unlock(&ipsecmgr_drv->lock); ++ write_unlock_bh(&ipsecmgr_drv->lock); + + #ifdef NSS_IPSECMGR_PPE_SUPPORT + /* +@@ -627,9 +627,9 @@ struct net_device *nss_ipsecmgr_tunnel_a + #endif + } + +- write_lock(&ipsecmgr_drv->lock); ++ write_lock_bh(&ipsecmgr_drv->lock); + list_add(&tun->list, &ipsecmgr_drv->tun_db); +- write_unlock(&ipsecmgr_drv->lock); ++ write_unlock_bh(&ipsecmgr_drv->lock); + + nss_ipsecmgr_tunnel_mtu(dev, skb_dev ? skb_dev->mtu : dev->mtu); + +--- a/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_flow.c ++++ b/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_flow.c +@@ -1,4 +1,5 @@ + /* Copyright (c) 2021, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above +@@ -50,9 +51,9 @@ static void nss_ipsec_xfrm_flow_final(st + /* + * Release reference to the parent SA. + */ +- if (flow->sa) { +- nss_ipsec_xfrm_sa_deref(flow->sa); +- flow->sa = NULL; ++ if (READ_ONCE(flow->sa)) { ++ nss_ipsec_xfrm_sa_deref(READ_ONCE(flow->sa)); ++ WRITE_ONCE(flow->sa, NULL); + } + + if (flow->pol) { +@@ -194,7 +195,7 @@ struct nss_ipsec_xfrm_flow *nss_ipsec_xf + */ + bool nss_ipsec_xfrm_flow_update(struct nss_ipsec_xfrm_flow *flow, struct nss_ipsec_xfrm_sa *sa) + { +- struct nss_ipsec_xfrm_sa *flow_sa = flow->sa; ++ struct nss_ipsec_xfrm_sa *flow_sa = READ_ONCE(flow->sa); + enum nss_ipsecmgr_status status; + + /* +@@ -213,12 +214,14 @@ bool nss_ipsec_xfrm_flow_update(struct n + return true; + } + ++ if (cmpxchg(&flow->sa, flow_sa, sa) != flow_sa) { ++ nss_ipsec_xfrm_info("%p: Flow migrated to newer SA by other CPU\n", flow); ++ return false; ++ } + +- nss_ipsec_xfrm_info("%p: Flow migrated from SA %p to SA %p\n", flow, flow_sa, sa); +- +- xchg(&flow->sa, nss_ipsec_xfrm_sa_ref(sa)); ++ nss_ipsec_xfrm_sa_ref(sa); + nss_ipsec_xfrm_sa_deref(flow_sa); +- ++ nss_ipsec_xfrm_info("%p: Flow migrated from SA %p to SA %p\n", flow, flow_sa, sa); + return true; + } + +@@ -236,7 +239,7 @@ void nss_ipsec_xfrm_flow_dealloc(struct + + atomic64_inc(&drv->stats.flow_dealloced); + +- sa = flow->sa; ++ sa = READ_ONCE(flow->sa); + BUG_ON(!sa); + + tun = sa->tun; +@@ -282,7 +285,7 @@ struct nss_ipsec_xfrm_flow *nss_ipsec_xf + flow->tuple.sport, flow->tuple.dport); + } + +- flow->sa = nss_ipsec_xfrm_sa_ref(sa); ++ WRITE_ONCE(flow->sa, nss_ipsec_xfrm_sa_ref(sa)); + + status = nss_ipsecmgr_flow_add(sa->tun->dev, &flow->tuple, &sa->tuple); + if ((status != NSS_IPSECMGR_DUPLICATE_FLOW) && (status != NSS_IPSECMGR_OK)) { +--- a/ipsecmgr/v2.0/plugins/xfrm/Makefile ++++ b/ipsecmgr/v2.0/plugins/xfrm/Makefile +@@ -14,3 +14,7 @@ ccflags-y += -I$(obj)/ + ccflags-y += -DNSS_IPSEC_XFRM_DEBUG_LEVEL=3 + ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)" + ccflags-y += -Wall -Werror ++ ++ifeq ($(SoC),$(filter $(SoC),ipq50xx ipq50xx_64)) ++ccflags-y += -DNSS_IPSEC_XFRM_IPQ50XX ++endif diff --git a/qca-nss-clients/patches-11.4/0035-netlink-backport-12.5.patch b/qca-nss-clients/patches-11.4/0035-netlink-backport-12.5.patch new file mode 100644 index 0000000..646b73a --- /dev/null +++ b/qca-nss-clients/patches-11.4/0035-netlink-backport-12.5.patch @@ -0,0 +1,1441 @@ +--- a/netlink/Makefile ++++ b/netlink/Makefile +@@ -22,6 +22,7 @@ ccflags-y += -DCONFIG_NSS_NLLSO_RX=$(str + ccflags-y += -DCONFIG_NSS_NLMAP_T=$(strip $(if $(filter $(map-t), y), 1 , 0)) + ccflags-y += -DCONFIG_NSS_NLPPPOE=$(strip $(if $(filter $(pppoe), y), 1 , 0)) + ccflags-y += -DCONFIG_NSS_NLL2TPV2=$(strip $(if $(filter $(l2tp), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLQRFS=$(strip $(if $(filter $(CONFIG_NSS_NLQRFS), y), 1 , 0)) + ccflags-y += -DCONFIG_NSS_NLPPTP=$(strip $(if $(filter $(pptp), y), 1 , 0)) + ccflags-y += -DCONFIG_NSS_NLCAPWAP=${CAPWAP_ENABLED} + ccflags-y += -DCONFIG_NSS_NLIPSEC=${IPSEC_ENABLED} +@@ -83,6 +84,10 @@ qca-nss-netlink-objs += nss_nludp_st.o + endif + endif + ++ifneq (,$(filter $(CONFIG_NSS_NLQRFS), y)) ++qca-nss-netlink-objs += nss_nlqrfs.o ++endif ++ + ifneq (,$(filter $(capwapmgr), y)) + qca-nss-netlink-objs += nss_nlcapwap.o + endif +--- /dev/null ++++ b/netlink/include/nss_nlqrfs_if.h +@@ -0,0 +1,59 @@ ++/* ++ ************************************************************************** ++ * Copyright (c) 2021, The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for ++ * any purpose with or without fee is hereby granted, provided that the ++ * above copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT ++ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ ************************************************************************** ++ */ ++ ++/* ++ * @file nss_nlqrfs_if.h ++ * NSS Netlink qrfs headers ++ */ ++#ifndef __NSS_NLQRFS_IF_H ++#define __NSS_NLQRFS_IF_H ++#include "nss_qrfs.h" ++ ++/** ++ * QRFS Family ++ */ ++#define NSS_NLQRFS_FAMILY "nss_nlqrfs" ++#define NSS_NLQRFS_MCAST_GRP "nss_nlqrfs_mc" ++ ++/** ++ * struct nss_nlqrfs_rule ++ * QRFS rule structure. ++ */ ++struct nss_nlqrfs_rule { ++ struct nss_nlcmn cm; /**< Common message header. */ ++ char gmac_ifname[IFNAMSIZ]; /**< GMAC interface name. */ ++ struct nss_qrfs_flow_rule_msg msg; /**< QRFS Configure flow rule message. */ ++}; ++ ++/** ++ * nss_nlqrfs_rule_init ++ * NETLINK qrfs message init. ++ * ++ * @param[in] rule NSS Netlink QRFS rule. ++ * @param[in] type QRFS message type. ++ * ++ * @return ++ * None. ++ */ ++static inline void nss_nlqrfs_rule_init(struct nss_nlqrfs_rule *rule, enum nss_qrfs_msg_types type) ++{ ++ nss_nlcmn_set_ver(&rule->cm, NSS_NL_VER); ++ nss_nlcmn_init_cmd(&rule->cm, sizeof(struct nss_nlqrfs_rule), type); ++} ++ ++#endif /* __NSS_NLQRFS_IF_H */ +--- a/netlink/nss_nl.c ++++ b/netlink/nss_nl.c +@@ -77,6 +77,8 @@ + #include "nss_nlpptp_if.h" + #include "nss_nludp_st.h" + #include "nss_nludp_st_if.h" ++#include "nss_nlqrfs.h" ++#include "nss_nlqrfs_if.h" + + /* + * nss_nl.c +@@ -294,7 +296,16 @@ static struct nss_nl_family family_handl + .entry = NSS_NLUDP_ST_INIT, /* init */ + .exit = NSS_NLUDP_ST_EXIT, /* exit */ + .valid = CONFIG_NSS_NLUDP_ST /* 1 or 0 */ +- } ++ }, ++ { ++ /* ++ * NSS_NLQRFS ++ */ ++ .name = NSS_NLQRFS_FAMILY, /* qrfs */ ++ .entry = NSS_NLQRFS_INIT, /* init */ ++ .exit = NSS_NLQRFS_EXIT, /* exit */ ++ .valid = CONFIG_NSS_NLQRFS /* 1 or 0 */ ++ }, + }; + + #define NSS_NL_FAMILY_HANDLER_SZ ARRAY_SIZE(family_handlers) +--- a/netlink/nss_nldtls.c ++++ b/netlink/nss_nldtls.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** +- * Copyright (c) 2015-2016,2018-2020 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2015-2016,2018-2021 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -446,7 +449,7 @@ static void nss_nldtls_data_callback(voi + * nss_nldtls_create_session() + * Create a DTLS session through dtlsmgr driver API. + */ +-static struct net_device *nss_nldtls_create_session(struct nss_nldtls_rule *nl_rule, uint32_t flags) ++static struct net_device *nss_nldtls_create_session(struct nss_nldtls_rule *nl_rule) + { + struct nss_nldtls_tun_ctx *dtls_tun_data; + struct nss_dtlsmgr_config dcfg; +@@ -463,7 +466,7 @@ static struct net_device *nss_nldtls_cre + + memset(&dcfg, 0, sizeof(struct nss_dtlsmgr_config)); + algo = nl_rule->msg.create.encap.cfg.crypto.algo; +- dcfg.flags = flags | (NSS_DTLSMGR_ENCAP_METADATA | NSS_DTLSMGR_HDR_CAPWAP); ++ dcfg.flags = nl_rule->msg.create.flags | NSS_DTLSMGR_ENCAP_METADATA; + if (algo == NSS_DTLSMGR_ALGO_AES_GCM) + dcfg.flags |= NSS_DTLSMGR_CIPHER_MODE_GCM; + +@@ -605,7 +608,11 @@ static int nss_nldtls_create_ipv4_rule_e + ipv4.dest_port = nl_rule->msg.create.encap.cfg.sport; + ipv4.dest_port_xlate = nl_rule->msg.create.encap.cfg.sport; + +- ipv4.protocol = IPPROTO_UDP; ++ if (nl_rule->msg.create.flags & NSS_DTLSMGR_HDR_UDPLITE) ++ ipv4.protocol = IPPROTO_UDPLITE; ++ else ++ ipv4.protocol = IPPROTO_UDP; ++ + ipv4.in_vlan_tag[0] = NSS_NLDTLS_VLAN_INVALID; + ipv4.out_vlan_tag[0] = NSS_NLDTLS_VLAN_INVALID; + ipv4.in_vlan_tag[1] = NSS_NLDTLS_VLAN_INVALID; +@@ -613,6 +620,8 @@ static int nss_nldtls_create_ipv4_rule_e + + memcpy(&ipv4.src_mac[0], &nl_rule->msg.create.gmac_ifmac[0], sizeof(ipv4.src_mac)); + ++ dev_put(ndev); ++ + /* + * Create an ipv4 rule entry + */ +@@ -654,7 +663,11 @@ static int nss_nldtls_create_ipv6_rule_e + */ + memcpy(ipv6.src_ip, nl_rule->msg.create.encap.cfg.dip, sizeof(ipv6.src_ip)); + memcpy(ipv6.dest_ip, nl_rule->msg.create.encap.cfg.sip, sizeof(ipv6.dest_ip)); +- ipv6.protocol = IPPROTO_UDP; ++ ++ if (nl_rule->msg.create.flags & NSS_DTLSMGR_HDR_UDPLITE) ++ ipv6.protocol = IPPROTO_UDPLITE; ++ else ++ ipv6.protocol = IPPROTO_UDP; + + ipv6.in_vlan_tag[0] = NSS_NLDTLS_VLAN_INVALID; + ipv6.in_vlan_tag[1] = NSS_NLDTLS_VLAN_INVALID; +@@ -663,6 +676,8 @@ static int nss_nldtls_create_ipv6_rule_e + + memcpy(&ipv6.src_mac[0], &nl_rule->msg.create.gmac_ifmac[0], sizeof(ipv6.src_mac)); + ++ dev_put(ndev); ++ + /* + * Create an ipv6 rule entry + */ +@@ -729,7 +744,7 @@ static int nss_nldtls_ops_create_tun(str + * Create tunnel based on ip version + */ + if (nl_rule->msg.create.ip_version == NSS_NLDTLS_IP_VERS_4) { +- dtls_dev = nss_nldtls_create_session(nl_rule, NSS_NLDTLS_IPV4_SESSION); ++ dtls_dev = nss_nldtls_create_session(nl_rule); + if (!dtls_dev) { + nss_nl_error("%px: Unable to create dtls session for v4\n", skb); + return -EINVAL; +@@ -748,7 +763,7 @@ static int nss_nldtls_ops_create_tun(str + atomic_inc(&gbl_ctx.num_tun); + nss_nl_info("%px: Successfully created ipv4 dtls tunnel\n", skb); + } else { +- dtls_dev = nss_nldtls_create_session(nl_rule, NSS_DTLSMGR_HDR_IPV6); ++ dtls_dev = nss_nldtls_create_session(nl_rule); + if (!dtls_dev) { + nss_nl_error("%px: Unable to create dtls session for v6\n", skb); + return -EINVAL; +@@ -871,6 +886,7 @@ static int nss_nldtls_ops_update_config( + key_len = nl_rule->msg.update_config.config_update.crypto.cipher_key.len; + if (key_len > NSS_NLDTLS_CIPHER_KEY_MAX) { + nss_nl_error("Invalid cipher length: %u\n", key_len); ++ dev_put(dev); + return -EINVAL; + } + +@@ -878,6 +894,7 @@ static int nss_nldtls_ops_update_config( + key_len = nl_rule->msg.update_config.config_update.crypto.auth_key.len; + if (key_len > NSS_NLDTLS_AUTH_KEY_MAX) { + nss_nl_error("Invalid authentication length: %u\n", key_len); ++ dev_put(dev); + return -EINVAL; + } + +@@ -885,6 +902,7 @@ static int nss_nldtls_ops_update_config( + key_len = nl_rule->msg.update_config.config_update.crypto.nonce.len; + if (key_len > NSS_NLDTLS_NONCE_SIZE_MAX) { + nss_nl_error("Invalid nonce length: %u\n", key_len); ++ dev_put(dev); + return -EINVAL; + } + +--- a/netlink/nss_nlipsec.c ++++ b/netlink/nss_nlipsec.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2015-2016,2018-2021 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -225,7 +228,7 @@ static void nss_nlipsec_process_event(vo + /* + * Initialize the NETLINK common header + */ +- nss_nlipsec_rule_init(nl_rule, ev->type); ++ nss_nlipsec_rule_init(nl_rule, (enum nss_nlipsec_cmd)ev->type); + + /* + * Copy the contents of the sync message into the NETLINK message +@@ -508,6 +511,8 @@ static struct nss_nlipsec_rule *nss_nlip + dev_put(*dev); + return NULL; + } ++ ++ dev_put(*dev); + return nl_rule; + } + +--- /dev/null ++++ b/netlink/nss_nlqrfs.c +@@ -0,0 +1,203 @@ ++/* ++ ************************************************************************** ++ * Copyright (c) 2021, The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for ++ * any purpose with or without fee is hereby granted, provided that the ++ * above copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT ++ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ ************************************************************************** ++ */ ++ ++/* ++ * nss_nlqrfs.c ++ * NSS Netlink qrfs Handler ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "nss_nl.h" ++#include "nss_nlcmn_if.h" ++#include "nss_nlqrfs_if.h" ++#include ++ ++/* ++ * prototypes ++ */ ++static int nss_nlqrfs_ops_add_rule(struct sk_buff *skb, struct genl_info *info); ++static int nss_nlqrfs_ops_del_rule(struct sk_buff *skb, struct genl_info *info); ++ ++/* ++ * multicast group for sending message status & events ++ */ ++static const struct genl_multicast_group nss_nlqrfs_mcgrp[] = { ++ {.name = NSS_NLQRFS_MCAST_GRP}, ++}; ++ ++/* ++ * operation table called by the generic netlink layer based on the command ++ */ ++static struct genl_ops nss_nlqrfs_ops[] = { ++ {.cmd = NSS_QRFS_MSG_FLOW_ADD, .doit = nss_nlqrfs_ops_add_rule,}, ++ {.cmd = NSS_QRFS_MSG_FLOW_DELETE, .doit = nss_nlqrfs_ops_del_rule,}, ++}; ++ ++/* ++ * qrfs family definition ++ */ ++static struct genl_family nss_nlqrfs_family = { ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0)) ++ .id = GENL_ID_GENERATE, /* Auto generate ID */ ++#endif ++ .name = NSS_NLQRFS_FAMILY, /* family name string */ ++ .hdrsize = sizeof(struct nss_nlqrfs_rule), /* NSS NETLINK qrfs rule */ ++ .version = NSS_NL_VER, /* Set it to NSS_NLQRFS version */ ++ .maxattr = NSS_QRFS_MSG_MAX, /* Maximum commands supported */ ++ .netnsok = true, ++ .pre_doit = NULL, ++ .post_doit = NULL, ++ .ops = nss_nlqrfs_ops, ++ .n_ops = ARRAY_SIZE(nss_nlqrfs_ops), ++ .mcgrps = nss_nlqrfs_mcgrp, ++ .n_mcgrps = ARRAY_SIZE(nss_nlqrfs_mcgrp) ++}; ++ ++/* ++ * nss_nlqrfs_ops_cfg_rule ++ * Handler for unconfiguring rules ++ */ ++static int nss_nlqrfs_ops_cfg_rule(struct sk_buff *skb, struct genl_info *info, bool action) ++{ ++ struct nss_nlqrfs_rule *nl_rule; ++ struct nss_qrfs_flow_rule_msg *nrm; ++ struct nss_nlcmn *nl_cm; ++ int ret = 0; ++ ++ /* ++ * Extract the message payload ++ */ ++ if (action) { ++ nl_cm = nss_nl_get_msg(&nss_nlqrfs_family, info, NSS_QRFS_MSG_FLOW_ADD); ++ nss_nl_info("add flow rule\n"); ++ } else { ++ nl_cm = nss_nl_get_msg(&nss_nlqrfs_family, info, NSS_QRFS_MSG_FLOW_DELETE); ++ nss_nl_info("delete flow rule\n"); ++ } ++ ++ if (!nl_cm) { ++ nss_nl_error("%px: Unable to extract configure rule data\n", skb); ++ return -EINVAL; ++ } ++ ++ /* ++ * Message validation required before accepting the configuration ++ */ ++ nl_rule = container_of(nl_cm, struct nss_nlqrfs_rule, cm); ++ nrm = &nl_rule->msg; ++ ++ if (nrm->ip_version == 4) { ++ nss_nl_trace("src_ip:%pl4h src_port:%u dst_ip:%pl4h dst_port:%u protocol:%u version:%u cpu:%u\n", ++ nrm->src_addr, nrm->src_port, nrm->dst_addr, nrm->dst_port, nrm->protocol, ++ nrm->ip_version, nrm->cpu); ++ } else if (nrm->ip_version == 6) { ++ nss_nl_trace("src_ip:%pl6 src_port:%u dst_ip:%pl6 dst_port:%u protocol:%u version:%u cpu:%u\n", ++ nrm->src_addr, nrm->src_port, nrm->dst_addr, nrm->dst_port, nrm->protocol, ++ nrm->ip_version, nrm->cpu); ++ } else { ++ nss_nl_trace("Unsupported IP version field\n"); ++ return -EINVAL; ++ } ++ ++ if (action) { ++ nss_qrfs_configure_flow_rule(nrm->dst_addr, nrm->src_addr, nrm->dst_port, nrm->src_port, ++ nrm->ip_version, nrm->protocol, nrm->cpu, NSS_QRFS_MSG_FLOW_ADD); ++ } else { ++ nss_qrfs_configure_flow_rule(nrm->dst_addr, nrm->src_addr, nrm->dst_port, nrm->src_port, ++ nrm->ip_version, nrm->protocol, nrm->cpu, NSS_QRFS_MSG_FLOW_DELETE); ++ } ++ ++ nss_nl_trace("%s flow rule finished\n", action? "add" : "delete"); ++ ++ return ret; ++} ++ ++/* ++ * nss_nlqrfs_ops_add_rule() ++ * Handler for Adding rules ++ */ ++static int nss_nlqrfs_ops_add_rule(struct sk_buff *skb, struct genl_info *info) ++{ ++ return nss_nlqrfs_ops_cfg_rule(skb, info, true); ++} ++ ++/* ++ * nss_nlqrfs_ops_del_rule() ++ * Handler for deleting rules ++ */ ++static int nss_nlqrfs_ops_del_rule(struct sk_buff *skb, struct genl_info *info) ++{ ++ return nss_nlqrfs_ops_cfg_rule(skb, info, false); ++} ++ ++/* ++ * nss_nlqrfs_exit() ++ * handler exit ++ */ ++bool nss_nlqrfs_exit(void) ++{ ++ int error; ++ ++ nss_nl_info_always("Exit NSS netlink qrfs handler\n"); ++ ++ /* ++ * unregister the ops family ++ */ ++ error = genl_unregister_family(&nss_nlqrfs_family); ++ if (error) { ++ nss_nl_info_always("unable to unregister qrfs NETLINK family\n"); ++ return false; ++ } ++ ++ return true; ++} ++ ++/* ++ * nss_nlqrfs_init() ++ * handler init ++ */ ++bool nss_nlqrfs_init(void) ++{ ++ int error; ++ ++ nss_nl_info_always("Init NSS netlink qrfs handler\n"); ++ ++ /* ++ * register Netlink ops with the family ++ */ ++ error = genl_register_family(&nss_nlqrfs_family); ++ if (error) { ++ nss_nl_info_always("Error: unable to register qrfs family\n"); ++ return false; ++ } ++ ++ return true; ++} +--- /dev/null ++++ b/netlink/nss_nlqrfs.h +@@ -0,0 +1,37 @@ ++/* ++ ************************************************************************** ++ * Copyright (c) 2021, The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for ++ * any purpose with or without fee is hereby granted, provided that the ++ * above copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT ++ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ ************************************************************************** ++ */ ++ ++/* ++ * nss_nlqrfs.h ++ * NSS Netlink qrfs API definitions ++ */ ++#ifndef __NSS_NLQRFS_H ++#define __NSS_NLQRFS_H ++ ++bool nss_nlqrfs_init(void); ++bool nss_nlqrfs_exit(void); ++ ++#if defined(CONFIG_NSS_NLQRFS) && CONFIG_NSS_NLQRFS > 0 ++#define NSS_NLQRFS_INIT nss_nlqrfs_init ++#define NSS_NLQRFS_EXIT nss_nlqrfs_exit ++#else ++#define NSS_NLQRFS_INIT 0 ++#define NSS_NLQRFS_EXIT 0 ++#endif /* !CONFIG_NSS_NLQRFS */ ++ ++#endif /* __NSS_NLQRFS_H */ +--- a/netlink/nss_nludp_st.c ++++ b/netlink/nss_nludp_st.c +@@ -1,6 +1,7 @@ + /* + ************************************************************************** + * Copyright (c) 2021, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the +@@ -31,6 +32,9 @@ + #include + #include + #include ++#include ++#include ++#include + + #include + #include +@@ -40,6 +44,8 @@ + #include "nss_nludp_st_if.h" + #include "nss_nludp_st.h" + ++#define NSS_NLUDP_ST_VLAN_ID_NOT_CONFIGURED 0xFFF ++ + /* + * prototypes + */ +@@ -196,7 +202,6 @@ static int nss_nludp_st_ops_start(struct + struct nss_ctx_instance *nss_ctx; + struct nss_udp_st_msg num; + struct sk_buff *resp; +- uint32_t pid; + nss_tx_status_t status; + + /* +@@ -208,7 +213,6 @@ static int nss_nludp_st_ops_start(struct + return -EINVAL; + } + +- pid = nl_cm->pid; + /* + * Message validation required before accepting the configuration + */ +@@ -259,7 +263,6 @@ static int nss_nludp_st_ops_reset_stats( + struct nss_ctx_instance *nss_ctx; + struct nss_udp_st_msg num; + struct sk_buff *resp; +- uint32_t pid; + nss_tx_status_t status; + + /* +@@ -271,7 +274,6 @@ static int nss_nludp_st_ops_reset_stats( + return -EINVAL; + } + +- pid = nl_cm->pid; + /* + * Message validation required before accepting the configuration + */ +@@ -320,7 +322,6 @@ static int nss_nludp_st_ops_tx_destroy(s + struct nss_ctx_instance *nss_ctx; + struct nss_udp_st_msg num; + struct sk_buff *resp; +- uint32_t pid; + nss_tx_status_t status; + + /* +@@ -332,7 +333,6 @@ static int nss_nludp_st_ops_tx_destroy(s + return -EINVAL; + } + +- pid = nl_cm->pid; + /* + * Message validation required before accepting the configuration + */ +@@ -381,7 +381,6 @@ static int nss_nludp_st_ops_tx_create(st + struct nss_ctx_instance *nss_ctx; + struct nss_udp_st_msg num; + struct sk_buff *resp; +- uint32_t pid; + nss_tx_status_t status; + + /* +@@ -393,7 +392,6 @@ static int nss_nludp_st_ops_tx_create(st + return -EINVAL; + } + +- pid = nl_cm->pid; + /* + * Message validation required before accepting the configuration + */ +@@ -571,6 +569,7 @@ static struct neighbour *nss_nludp_st_ge + rt = rt6_lookup(&init_net, &daddr, NULL, 0, NULL, 0); + #endif + if (!rt) { ++ nss_nl_warn("rt6 info lookup failed\n"); + return NULL; + } + +@@ -587,21 +586,20 @@ static struct neighbour *nss_nludp_st_ge + } + dst_release(dst); + ++ nss_nl_warn("dst neigh info lookup failed\n"); + return NULL; + } + + /* + * nss_nludp_st_get_addr_hton() +- * Convert the ipv6 address from host order to network order. ++ * Convert the ipv6 address from NSS host order to Linux network order. + */ + static inline void nss_nludp_st_get_addr_hton(uint32_t src[4], uint32_t dst[4]) + { +- nss_nludp_st_swap_addr_ipv6(src, dst); +- +- dst[0] = htonl(dst[0]); +- dst[1] = htonl(dst[1]); +- dst[2] = htonl(dst[2]); +- dst[3] = htonl(dst[3]); ++ dst[0] = htonl(src[0]); ++ dst[1] = htonl(src[1]); ++ dst[2] = htonl(src[2]); ++ dst[3] = htonl(src[3]); + } + + /* +@@ -731,6 +729,277 @@ static int nss_nludp_st_destroy_ipv4_rul + } + + /* ++ * nss_nludp_st_vlan_next_dev_get_and_hold() ++ * Gets and hold the next device of the VLAN. ++ * ++ * It should be a physical ethernet interface. ++ */ ++static struct net_device *nss_nludp_st_vlan_next_dev_get_and_hold(struct net_device *dev) ++{ ++ struct net_device *next_dev; ++ ++ next_dev = vlan_dev_next_dev(dev); ++ if (!next_dev) { ++ nss_nl_warn("%px: VLAN device's (%s) next dev is NULL\n", dev, dev->name); ++ return NULL; ++ } ++ ++ if (is_vlan_dev(next_dev) || next_dev->type != ARPHRD_ETHER) { ++ nss_nl_warn("%px: QinQ or non-ethernet VLAN master (%s) is not supported\n", dev, next_dev->name); ++ return NULL; ++ } ++ dev_hold(next_dev); ++ return next_dev; ++} ++ ++/* ++ * nss_nludp_st_ipv4_rawip_iface_config() ++ * Configure the WAN interface as RmNet for IPv4 protocol. ++ */ ++static int nss_nludp_st_ipv4_rawip_iface_config(struct net_device *dev, struct nss_ipv4_rule_create_msg *nircm) ++{ ++#ifdef NSS_NETLINK_UDP_ST_NO_RMNET_SUPPORT ++ nss_nl_warn("%px: RAWIP is disabled\n", dev); ++ return -EINVAL; ++#else ++ nircm->conn_rule.return_interface_num = nss_rmnet_rx_get_ifnum(dev); ++ memset(nircm->conn_rule.return_mac, 0, ETH_ALEN); ++ ether_addr_copy((uint8_t *)nircm->conn_rule.flow_mac, dev->dev_addr); ++ nss_nl_info("%px: Speedtest RmNet WAN interface %s is configured\n", dev, dev->name); ++ return 0; ++#endif ++} ++ ++/* ++ * nss_nludp_st_ipv4_eth_iface_config() ++ * Configure the WAN interface as Ethernet for IPv4 protocol. ++ */ ++static int nss_nludp_st_ipv4_eth_iface_config(struct net_device *dev, struct nss_ipv4_rule_create_msg *nircm) ++{ ++ if (nss_nludp_st_get_macaddr_ipv4(nircm->tuple.return_ip, (uint8_t *)&nircm->conn_rule.return_mac)) { ++ nss_nl_warn("%px: Error in updating the return MAC Address\n", dev); ++ return -EINVAL; ++ } ++ ether_addr_copy((uint8_t *)nircm->conn_rule.flow_mac, dev->dev_addr); ++ nircm->conn_rule.return_interface_num = nss_cmn_get_interface_number_by_dev(dev); ++ if (nircm->conn_rule.return_interface_num < 0) { ++ nss_nl_warn("%px: Unable to get the NSS interface number of %s\n", dev, dev->name); ++ return -EINVAL; ++ } ++ nss_nl_info("%px: Speedtest Ethernet WAN interface %s is configured\n", dev, dev->name); ++ return 0; ++} ++ ++/* ++ * nss_nludp_st_ipv4_set_vlan_tags() ++ * Sets the VLAN tags for IPv4 protocol. ++ */ ++static void nss_nludp_st_ipv4_set_vlan_tags(struct net_device *dev, struct nss_ipv4_rule_create_msg *nircm) ++{ ++ /* ++ * Get the primary VLAN info and set in the rule. ++ */ ++ uint16_t vlan_tag = vlan_dev_vlan_id(dev); ++ uint16_t vlan_tpid = ntohs(vlan_dev_vlan_proto(dev)); ++ ++ nircm->vlan_primary_rule.egress_vlan_tag = (vlan_tpid << 16) | vlan_tag; ++ nircm->vlan_primary_rule.ingress_vlan_tag = NSS_NLUDP_ST_VLAN_ID_NOT_CONFIGURED; ++ nircm->vlan_secondary_rule.egress_vlan_tag = NSS_NLUDP_ST_VLAN_ID_NOT_CONFIGURED; ++ nircm->vlan_secondary_rule.ingress_vlan_tag = NSS_NLUDP_ST_VLAN_ID_NOT_CONFIGURED; ++} ++ ++/* ++ * nss_nludp_st_ipv4_vlan_iface_config() ++ * Configure the WAN interface as VLAN for IPv4 protocol. ++ */ ++static int nss_nludp_st_ipv4_vlan_iface_config(struct net_device *dev, struct nss_ipv4_rule_create_msg *nircm) ++{ ++ struct net_device *next_dev; ++ int ret; ++ ++ next_dev = nss_nludp_st_vlan_next_dev_get_and_hold(dev); ++ if (!next_dev) { ++ nss_nl_warn("%px: Unable to get VLAN device's (%s) next dev\n", dev, dev->name); ++ return -ENODEV; ++ } ++ ++ /* ++ * Single VLAN, next_dev should be a physical device. ++ * Copy the real device's number (eth0). ++ */ ++ nircm->conn_rule.return_interface_num = nss_cmn_get_interface_number_by_dev(next_dev); ++ if (nircm->conn_rule.return_interface_num < 0) { ++ nss_nl_warn("%px: Unable to get the NSS interface number of %s\n", dev, next_dev->name); ++ ret = -EINVAL; ++ goto fail; ++ } ++ dev_put(next_dev); ++ ++ /* ++ * Get the return IP address's MAC address. ++ */ ++ if (nss_nludp_st_get_macaddr_ipv4(nircm->tuple.return_ip, (uint8_t *)&nircm->conn_rule.return_mac)) { ++ nss_nl_warn("%px: Error in updating the return MAC Address\n", dev); ++ return -EINVAL; ++ } ++ ++ /* ++ * Get the primary VLAN info and set in the rule. ++ */ ++ nss_nludp_st_ipv4_set_vlan_tags(dev, nircm); ++ nircm->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID; ++ ++ ether_addr_copy((uint8_t *)nircm->conn_rule.flow_mac, dev->dev_addr); ++ ++ /* ++ * Success. Fall through for release resources ++ */ ++ nss_nl_info("%px: Speedtest VLAN WAN interface %s is configured\n", dev, dev->name); ++ return 0; ++fail: ++ dev_put(next_dev); ++ return ret; ++} ++ ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 ++/* ++ * nss_nludp_st_pppoe_get_chan_and_info() ++ * Gets the PPPoE channel information. ++ */ ++static inline bool nss_nludp_st_pppoe_get_chan_and_info(struct net_device *dev, struct ppp_channel **ppp_chan, struct pppoe_opt *info) ++{ ++ int channel_count; ++ int channel_protocol; ++ ++ channel_count = ppp_hold_channels(dev, ppp_chan, 1); ++ if (channel_count != 1) { ++ nss_nl_warn("%px: Unable to get the channel for device: %s\n", dev, dev->name); ++ return false; ++ } ++ ++ channel_protocol = ppp_channel_get_protocol(ppp_chan[0]); ++ if (channel_protocol != PX_PROTO_OE) { ++ nss_nl_warn("%px: PPP channel protocol is not PPPoE for device: %s\n", dev, dev->name); ++ ppp_release_channels(ppp_chan, 1); ++ return false; ++ } ++ ++ if (pppoe_channel_addressing_get(ppp_chan[0], info)) { ++ nss_nl_warn("%px: Unable to get the PPPoE session information for device: %s\n", dev, dev->name); ++ ppp_release_channels(ppp_chan, 1); ++ return false; ++ } ++ ++ return true; ++} ++ ++/* ++ * nss_nludp_st_ipv4_pppoe_iface_config() ++ * Configure the WAN interface as PPPoE for IPv4 protocol. ++ */ ++static int nss_nludp_st_ipv4_pppoe_iface_config(struct net_device *dev, struct nss_ipv4_rule_create_msg *nircm) ++{ ++ struct pppoe_opt info; ++ struct ppp_channel *ppp_chan[1]; ++ int ret = -EINVAL; ++ ++ if (!nss_nludp_st_pppoe_get_chan_and_info(dev, ppp_chan, &info)) { ++ nss_nl_warn("%px: Unable to get PPPoE channel and info for device: %s\n", dev, dev->name); ++ return ret; ++ } ++ ++ /* ++ * Check if the next device is a VLAN (eth0-eth0.100-pppoe-wan ++ */ ++ if (is_vlan_dev(info.dev)) { ++ /* ++ * Next device is a VLAN device (eth0.100). ++ */ ++ struct net_device *next_dev; ++ ++ /* ++ * Check if we have a single VLAN device. ++ */ ++ next_dev = nss_nludp_st_vlan_next_dev_get_and_hold(info.dev); ++ if (!next_dev) { ++ nss_nl_warn("%px: Unable to get PPPoE's VLAN device's (%s) next dev\n", dev, info.dev->name); ++ ret = -ENODEV; ++ goto fail; ++ } ++ ++ /* ++ * PPPoE + VLAN (eth0-eth0.100-pppoe-wan) ++ * Copy the physical interface number (eth0) ++ */ ++ nircm->conn_rule.return_interface_num = nss_cmn_get_interface_number_by_dev(next_dev); ++ if (nircm->conn_rule.return_interface_num < 0) { ++ nss_nl_warn("%px: Unable to get the NSS interface number of %s\n", dev, next_dev->name); ++ dev_put(next_dev); ++ goto fail; ++ } ++ dev_put(next_dev); ++ ++ /* ++ * Get the primary VLAN info and set in the rule. ++ */ ++ nss_nludp_st_ipv4_set_vlan_tags(info.dev, nircm); ++ nircm->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID; ++ } else { ++ /* ++ * PPPoE interface can be created on linux bridge, OVS bridge and LAG devices. ++ * udp_st doesn't support these hierarchies. ++ */ ++ if ((info.dev->priv_flags & (IFF_EBRIDGE | IFF_OPENVSWITCH)) ++ || ((info.dev->flags & IFF_MASTER) && (info.dev->priv_flags & IFF_BONDING))) { ++ nss_nl_warn("%px: PPPoE over bridge and LAG interfaces are not supported, dev: %s info.dev: %s\n", ++ dev, dev->name, info.dev->name); ++ goto fail; ++ } ++ ++ /* ++ * PPPoE only (eth0-pppoe-wan) ++ * Copy the physical interface number (eth0) ++ */ ++ nircm->conn_rule.return_interface_num = nss_cmn_get_interface_number_by_dev(info.dev); ++ if (nircm->conn_rule.return_interface_num < 0) { ++ nss_nl_warn("%px: Unable to get the PPPoE's physical interface's (%s) NSS interface number\n", ++ dev, info.dev->name); ++ goto fail; ++ } ++ } ++ ++ /* ++ * For PPPoE connections, the other end's MAC address is PPPoE session's remote MAC address ++ */ ++ ether_addr_copy((uint8_t *)nircm->conn_rule.return_mac, info.pa.remote); ++ ether_addr_copy((uint8_t *)nircm->conn_rule.flow_mac, info.dev->dev_addr); ++ ++ /* ++ * Check if NSS has a valid dynamic interface number for PPPoE interface. ++ * If there is not, NSS cannot handle PPPoE flows in fast path. ++ */ ++ nircm->pppoe_rule.return_if_num = nss_cmn_get_interface_number_by_dev(dev); ++ if (nircm->pppoe_rule.return_if_num < 0) { ++ nss_nl_warn("%px: Unable to get the PPPoE interfaces (%s) dynamic interface number\n", dev, dev->name); ++ goto fail; ++ } ++ nircm->pppoe_rule.return_if_exist = 1; ++ nircm->valid_flags |= NSS_IPV4_RULE_CREATE_PPPOE_VALID; ++ ++ /* ++ * Success. Fall through for release resources ++ */ ++ ret = 0; ++ nss_nl_info("%px: Speedtest PPPoE WAN interface %s is configured\n", dev, dev->name); ++fail: ++ dev_put(info.dev); ++ ppp_release_channels(ppp_chan, 1); ++ return ret; ++} ++#endif ++ ++ ++/* + * nss_nludp_st_create_ipv4_rule() + * Create a nss entry to accelerate the given IPv4 connection + */ +@@ -742,7 +1011,9 @@ static int nss_nludp_st_create_ipv4_rule + struct net_device *net_dev; + struct nss_ipv4_nexthop *nexthop; + struct sk_buff *resp; ++ struct nss_ipv4_src_mac_rule *src_mac; + nss_tx_status_t status; ++ int ret = 0; + + nss_ctx = nss_ipv4_get_mgr(); + if (!nss_ctx) { +@@ -801,8 +1072,6 @@ static int nss_nludp_st_create_ipv4_rule + * Copy over the connection rules and set the CONN_VALID flag + */ + nircm->conn_rule.flow_interface_num = NSS_UDP_ST_INTERFACE; +- nircm->conn_rule.return_interface_num = nss_cmn_get_interface_number_by_dev(net_dev); +- memcpy(nircm->conn_rule.flow_mac, net_dev->dev_addr, 6); + + /* + * Set the MTU values of the flows. +@@ -811,12 +1080,51 @@ static int nss_nludp_st_create_ipv4_rule + nircm->conn_rule.return_mtu = net_dev->mtu; + + /* +- * Update the return MAC address +- */ +- if (nss_nludp_st_get_macaddr_ipv4(nircm->tuple.return_ip, (uint8_t *)&nircm->conn_rule.return_mac)) { +- nss_nl_info("Error in Updating the Return MAC Address \n"); +- dev_put(net_dev); +- return -EINVAL; ++ * Supported WAN interface hierarchies: ++ * ++ * rmnet <-> DUT (5G interface) ++ * eth0-eth0.100 <-> DUT (single VLAN) ++ * eth0-pppoe-wan <-> DUT ( PPPoE only) ++ * eth0-eth0.100-pppoe-wan <-> DUT (PPPoE over VLAN) ++ * eth0 <-> DUT (simple physical interface) ++ */ ++ switch (net_dev->type) { ++ case ARPHRD_RAWIP: ++ ret = nss_nludp_st_ipv4_rawip_iface_config(net_dev, nircm); ++ break; ++ ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 ++ case ARPHRD_PPP: ++ ret = nss_nludp_st_ipv4_pppoe_iface_config(net_dev, nircm); ++ break; ++#endif ++ ++ case ARPHRD_ETHER: ++ /* ++ * Bridge and LAG interfaces are not supported. ++ */ ++ if ((net_dev->priv_flags & (IFF_EBRIDGE | IFF_OPENVSWITCH)) ++ || ((net_dev->flags & IFF_MASTER) && (net_dev->priv_flags & IFF_BONDING))) { ++ nss_nl_warn("%px: Bridge and LAG interfaces are not supported, dev: %s\n", skb, net_dev->name); ++ ret = -EINVAL; ++ break; ++ } ++ ++ if (is_vlan_dev(net_dev)) { ++ ret = nss_nludp_st_ipv4_vlan_iface_config(net_dev, nircm); ++ } else { ++ ret = nss_nludp_st_ipv4_eth_iface_config(net_dev, nircm); ++ } ++ break; ++ default: ++ nss_nl_warn("%px: unsupported speedtest interface: %s\n", skb, net_dev->name); ++ ret = -EINVAL; ++ break; ++ } ++ ++ ++ if (ret < 0) { ++ goto done; + } + + nircm->valid_flags |= NSS_IPV4_RULE_CREATE_CONN_VALID; +@@ -825,15 +1133,27 @@ static int nss_nludp_st_create_ipv4_rule + nexthop->flow_nexthop = nircm->conn_rule.flow_interface_num; + nexthop->return_nexthop = nircm->conn_rule.return_interface_num; + +- nss_nl_info("flow_nexthop:%d return_nexthop:%d\n", nexthop->flow_nexthop, nexthop->return_nexthop); ++ nss_nl_info("%px: flow_nexthop:%d return_nexthop:%d\n", skb, nexthop->flow_nexthop, nexthop->return_nexthop); ++ ++ /* ++ * We want acceleration engine to choose the source MAC address which we ++ * have given to it instead of using the underlying physical interface's MAC address. ++ */ ++ src_mac = &nircm->src_mac_rule; ++ ++ memcpy(src_mac->flow_src_mac, nircm->conn_rule.return_mac, ETH_ALEN); ++ memcpy(src_mac->return_src_mac, nircm->conn_rule.flow_mac, ETH_ALEN); ++ ++ nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID; ++ src_mac->mac_valid_flags |= (NSS_IPV4_SRC_MAC_FLOW_VALID | NSS_IPV4_SRC_MAC_RETURN_VALID); + + status = nss_ipv4_tx(nss_ctx, &nim); + if (status != NSS_TX_SUCCESS) { +- nss_nl_info("%px: Create IPv4 message failed %d\n", nss_ctx, status); ++ nss_nl_info("%px: Create IPv4 message failed %d\n", skb, status); + } +- ++done: + dev_put(net_dev); +- return 0; ++ return ret; + } + + /* +@@ -868,7 +1188,7 @@ static int nss_nludp_st_destroy_ipv6_rul + } + + memset(&nim, 0, sizeof(struct nss_ipv6_msg)); +- nss_ipv6_msg_init(&nim, ++ nss_ipv6_msg_init(&nim, + NSS_IPV6_RX_INTERFACE, + NSS_IPV6_TX_DESTROY_RULE_MSG, + sizeof(struct nss_ipv6_rule_destroy_msg), +@@ -896,6 +1216,221 @@ static int nss_nludp_st_destroy_ipv6_rul + } + + /* ++ * nss_nludp_st_ipv6_rawip_iface_config() ++ * Configure the WAN interface as RmNet for IPv6 protocol. ++ */ ++static int nss_nludp_st_ipv6_rawip_iface_config(struct net_device *dev, struct nss_ipv6_rule_create_msg *nircm) ++{ ++#ifdef NSS_NETLINK_UDP_ST_NO_RMNET_SUPPORT ++ nss_nl_warn("%px: RAWIP is disabled\n", dev); ++ return -EINVAL; ++#else ++ nircm->conn_rule.return_interface_num = nss_rmnet_rx_get_ifnum(dev); ++ memset(nircm->conn_rule.return_mac, 0, ETH_ALEN); ++ ether_addr_copy((uint8_t *)nircm->conn_rule.flow_mac, dev->dev_addr); ++ nss_nl_info("%px: Speedtest RmNet WAN interface %s is configured\n", dev, dev->name); ++ return 0; ++#endif ++} ++ ++/* ++ * nss_nludp_st_ipv6_eth_iface_config() ++ * Configure the WAN interface as Ethernet for IPv6 protocol. ++ */ ++static int nss_nludp_st_ipv6_eth_iface_config(struct net_device *dev, struct nss_ipv6_rule_create_msg *nircm) ++{ ++ if (nss_nludp_st_get_macaddr_ipv6(nircm->tuple.return_ip, (uint8_t *)&nircm->conn_rule.return_mac)) { ++ nss_nl_warn("%px: Error in updating the return MAC Address\n", dev); ++ return -EINVAL; ++ } ++ ether_addr_copy((uint8_t *)nircm->conn_rule.flow_mac, dev->dev_addr); ++ nircm->conn_rule.return_interface_num = nss_cmn_get_interface_number_by_dev(dev); ++ if (nircm->conn_rule.return_interface_num < 0) { ++ nss_nl_warn("%px: Unable to get the NSS interface number of %s\n", dev, dev->name); ++ return -EINVAL; ++ } ++ nss_nl_info("%px: Speedtest Ethernet WAN interface %s is configured\n", dev, dev->name); ++ return 0; ++} ++ ++/* ++ * nss_nludp_st_ipv6_set_vlan_tags() ++ * Sets the VLAN tags for IPv6 protocol. ++ */ ++static void nss_nludp_st_ipv6_set_vlan_tags(struct net_device *dev, struct nss_ipv6_rule_create_msg *nircm) ++{ ++ /* ++ * Get the primary VLAN info and set in the rule. ++ */ ++ uint16_t vlan_tag = vlan_dev_vlan_id(dev); ++ uint16_t vlan_tpid = ntohs(vlan_dev_vlan_proto(dev)); ++ ++ nircm->vlan_primary_rule.egress_vlan_tag = (vlan_tpid << 16) | vlan_tag; ++ nircm->vlan_primary_rule.ingress_vlan_tag = NSS_NLUDP_ST_VLAN_ID_NOT_CONFIGURED; ++ nircm->vlan_secondary_rule.egress_vlan_tag = NSS_NLUDP_ST_VLAN_ID_NOT_CONFIGURED; ++ nircm->vlan_secondary_rule.ingress_vlan_tag = NSS_NLUDP_ST_VLAN_ID_NOT_CONFIGURED; ++} ++ ++/* ++ * nss_nludp_st_ipv6_vlan_iface_config() ++ * Configure the WAN interface as VLAN for IPv6 protocol. ++ */ ++static int nss_nludp_st_ipv6_vlan_iface_config(struct net_device *dev, struct nss_ipv6_rule_create_msg *nircm) ++{ ++ struct net_device *next_dev; ++ int ret; ++ ++ next_dev = nss_nludp_st_vlan_next_dev_get_and_hold(dev); ++ if (!next_dev) { ++ nss_nl_warn("%px: Unable to get VLAN device's (%s) next dev\n", dev, dev->name); ++ return -ENODEV; ++ } ++ ++ /* ++ * Single VLAN, next_dev should be a physical device. ++ * Copy the real device's number (eth0). ++ */ ++ nircm->conn_rule.return_interface_num = nss_cmn_get_interface_number_by_dev(next_dev); ++ if (nircm->conn_rule.return_interface_num < 0) { ++ nss_nl_warn("%px: Unable to get the NSS interface number of %s\n", dev, next_dev->name); ++ ret = -EINVAL; ++ goto fail; ++ } ++ dev_put(next_dev); ++ ++ /* ++ * Get the return IP address's MAC address. ++ */ ++ if (nss_nludp_st_get_macaddr_ipv6(nircm->tuple.return_ip, (uint8_t *)&nircm->conn_rule.return_mac)) { ++ nss_nl_warn("%px: Error in updating the return MAC Address\n", dev); ++ return -EINVAL; ++ } ++ ++ /* ++ * Get the primary VLAN info and set in the rule. ++ */ ++ nss_nludp_st_ipv6_set_vlan_tags(dev, nircm); ++ nircm->valid_flags |= NSS_IPV6_RULE_CREATE_VLAN_VALID; ++ ++ ether_addr_copy((uint8_t *)nircm->conn_rule.flow_mac, dev->dev_addr); ++ ++ /* ++ * Success. Fall through for release resources ++ */ ++ nss_nl_info("%px: Speedtest VLAN WAN interface %s is configured\n", dev, dev->name); ++ return 0; ++fail: ++ dev_put(next_dev); ++ return ret; ++} ++ ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 ++/* ++ * nss_nludp_st_ipv6_pppoe_iface_config() ++ * Configure the WAN interface as PPPoE for IPv6 protocol. ++ */ ++static int nss_nludp_st_ipv6_pppoe_iface_config(struct net_device *dev, struct nss_ipv6_rule_create_msg *nircm) ++{ ++ struct pppoe_opt info; ++ struct ppp_channel *ppp_chan[1]; ++ int ret = -EINVAL; ++ ++ if (!nss_nludp_st_pppoe_get_chan_and_info(dev, ppp_chan, &info)) { ++ nss_nl_warn("%px: Unable to get PPPoE channel and info for device: %s\n", dev, dev->name); ++ return ret; ++ } ++ ++ /* ++ * Check if the next device is a VLAN (eth0-eth0.100-pppoe-wan ++ */ ++ if (is_vlan_dev(info.dev)) { ++ /* ++ * Next device is a VLAN device (eth0.100). ++ */ ++ struct net_device *next_dev; ++ ++ /* ++ * Check if we have a single VLAN device. ++ */ ++ next_dev = nss_nludp_st_vlan_next_dev_get_and_hold(info.dev); ++ if (!next_dev) { ++ nss_nl_warn("%px: Unable to get PPPoE's VLAN device's (%s) next dev\n", dev, info.dev->name); ++ ret = -ENODEV; ++ goto fail; ++ } ++ ++ /* ++ * PPPoE + VLAN (eth0-eth0.100-pppoe-wan) ++ * Copy the physical interface number (eth0) ++ */ ++ nircm->conn_rule.return_interface_num = nss_cmn_get_interface_number_by_dev(next_dev); ++ if (nircm->conn_rule.return_interface_num < 0) { ++ nss_nl_warn("%px: Unable to get the NSS interface number of %s\n", dev, next_dev->name); ++ dev_put(next_dev); ++ goto fail; ++ } ++ dev_put(next_dev); ++ ++ /* ++ * Get the primary VLAN info and set in the rule. ++ */ ++ nss_nludp_st_ipv6_set_vlan_tags(info.dev, nircm); ++ nircm->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID; ++ } else { ++ /* ++ * PPPoE interface can be created on linux bridge, OVS bridge and LAG devices. ++ * udp_st doesn't support these hierarchies. ++ */ ++ if ((info.dev->priv_flags & (IFF_EBRIDGE | IFF_OPENVSWITCH)) ++ || ((info.dev->flags & IFF_MASTER) && (info.dev->priv_flags & IFF_BONDING))) { ++ nss_nl_warn("%px: PPPoE over bridge and LAG interfaces are not supported, dev: %s info.dev: %s\n", ++ dev, dev->name, info.dev->name); ++ goto fail; ++ } ++ ++ /* ++ * PPPoE only (eth0-pppoe-wan) ++ * Copy the physical interface number (eth0) ++ */ ++ nircm->conn_rule.return_interface_num = nss_cmn_get_interface_number_by_dev(info.dev); ++ if (nircm->conn_rule.return_interface_num < 0) { ++ nss_nl_warn("%px: Unable to get the PPPoE's physical interface's (%s) NSS interface number\n", ++ dev, info.dev->name); ++ goto fail; ++ } ++ } ++ ++ /* ++ * For PPPoE connections, the other end's MAC address is PPPoE session's remote MAC address ++ */ ++ ether_addr_copy((uint8_t *)nircm->conn_rule.return_mac, info.pa.remote); ++ ether_addr_copy((uint8_t *)nircm->conn_rule.flow_mac, info.dev->dev_addr); ++ ++ /* ++ * Check if NSS has a valid dynamic interface number for PPPoE interface. ++ * If there is not, NSS cannot handle PPPoE flows in fast path. ++ */ ++ nircm->pppoe_rule.return_if_num = nss_cmn_get_interface_number_by_dev(dev); ++ if (nircm->pppoe_rule.return_if_num < 0) { ++ nss_nl_warn("%px: Unable to get the PPPoE interfaces (%s) dynamic interface number\n", dev, dev->name); ++ goto fail; ++ } ++ nircm->pppoe_rule.return_if_exist = 1; ++ nircm->valid_flags |= NSS_IPV6_RULE_CREATE_PPPOE_VALID; ++ ++ /* ++ * Success. Fall through for release resources ++ */ ++ ret = 0; ++ nss_nl_info("%px: Speedtest PPPoE WAN interface %s is configured\n", dev, dev->name); ++fail: ++ dev_put(info.dev); ++ ppp_release_channels(ppp_chan, 1); ++ return ret; ++} ++#endif ++ ++/* + * nss_nludp_st_create_ipv6_rule() + * Create a nss entry to accelerate the given IPV6 connection + */ +@@ -907,7 +1442,9 @@ static int nss_nludp_st_create_ipv6_rule + struct net_device *net_dev; + struct nss_ipv6_nexthop *nexthop; + struct sk_buff *resp; ++ struct nss_ipv6_src_mac_rule *src_mac; + nss_tx_status_t status; ++ int ret = 0; + + nss_ctx = nss_ipv6_get_mgr(); + if (!nss_ctx) { +@@ -962,16 +1499,59 @@ static int nss_nludp_st_create_ipv6_rule + * Copy over the connection rules and set CONN_VALID flag + */ + nircm->conn_rule.flow_interface_num = NSS_UDP_ST_INTERFACE; +- nircm->conn_rule.return_interface_num = nss_cmn_get_interface_number_by_dev(net_dev); +- memcpy(nircm->conn_rule.flow_mac, net_dev->dev_addr, 6); + + /* +- * Update the return MAC address ++ * Set the MTU values of the flows. + */ +- if (nss_nludp_st_get_macaddr_ipv6(nircm->tuple.return_ip, (uint8_t *)&nircm->conn_rule.return_mac)) { +- nss_nl_info("Error in Updating the Return MAC Address \n"); +- dev_put(net_dev); +- return -EINVAL; ++ nircm->conn_rule.flow_mtu = NSS_NLUDP_ST_MAX_MTU; ++ nircm->conn_rule.return_mtu = net_dev->mtu; ++ ++ /* ++ * Supported WAN interface hierarchies: ++ * ++ * rmnet <-> DUT (5G interface) ++ * eth0-eth0.100 <-> DUT (single VLAN) ++ * eth0-pppoe-wan <-> DUT ( PPPoE only) ++ * eth0-eth0.100-pppoe-wan <-> DUT (PPPoE over VLAN) ++ * eth0 <-> DUT (simple physical interface) ++ */ ++ switch (net_dev->type) { ++ case ARPHRD_RAWIP: ++ ret = nss_nludp_st_ipv6_rawip_iface_config(net_dev, nircm); ++ break; ++ ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 ++ case ARPHRD_PPP: ++ ret = nss_nludp_st_ipv6_pppoe_iface_config(net_dev, nircm); ++ break; ++#endif ++ ++ case ARPHRD_ETHER: ++ /* ++ * Bridge and LAG interfaces are not supported. ++ */ ++ if ((net_dev->priv_flags & (IFF_EBRIDGE | IFF_OPENVSWITCH)) ++ || ((net_dev->flags & IFF_MASTER) && (net_dev->priv_flags & IFF_BONDING))) { ++ nss_nl_warn("%px: Bridge and LAG interfaces are not supported, dev: %s\n", skb, net_dev->name); ++ ret = -EINVAL; ++ break; ++ } ++ ++ if (is_vlan_dev(net_dev)) { ++ ret = nss_nludp_st_ipv6_vlan_iface_config(net_dev, nircm); ++ } else { ++ ret = nss_nludp_st_ipv6_eth_iface_config(net_dev, nircm); ++ } ++ break; ++ ++ default: ++ nss_nl_warn("%px: unsupported speedtest interface: %s\n", skb, net_dev->name); ++ ret = -EINVAL; ++ break; ++ } ++ ++ if (ret < 0) { ++ goto done; + } + + nircm->valid_flags |= NSS_IPV6_RULE_CREATE_CONN_VALID; +@@ -982,14 +1562,25 @@ static int nss_nludp_st_create_ipv6_rule + + nss_nl_info("flow_nexthop:%d return_nexthop:%d\n", nexthop->flow_nexthop, nexthop->return_nexthop); + ++ /* ++ * We want acceleration engine to choose the source MAC address which we ++ * have given to it instead of using the underlying physical interface's MAC address. ++ */ ++ src_mac = &nircm->src_mac_rule; ++ ++ memcpy(src_mac->flow_src_mac, nircm->conn_rule.return_mac, ETH_ALEN); ++ memcpy(src_mac->return_src_mac, nircm->conn_rule.flow_mac, ETH_ALEN); ++ ++ nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID; ++ src_mac->mac_valid_flags |= (NSS_IPV6_SRC_MAC_FLOW_VALID | NSS_IPV6_SRC_MAC_RETURN_VALID); ++ + status = nss_ipv6_tx(nss_ctx, &nim); + if (status != NSS_TX_SUCCESS) { + nss_nl_info("%px: Create IPv6 message failed %d\n", nss_ctx, status); +- return -EPERM; + } +- ++done: + dev_put(net_dev); +- return 0; ++ return ret; + } + + /* +@@ -1089,6 +1680,7 @@ static int nss_nludp_st_ops_uncfg_rule(s + { + struct nss_nludp_st_rule *nl_rule; + struct nss_nlcmn *nl_cm; ++ struct nss_udp_st_cfg *uncfg; + int ret = 0; + + /* +@@ -1104,6 +1696,15 @@ static int nss_nludp_st_ops_uncfg_rule(s + * Message validation required before accepting the configuration + */ + nl_rule = container_of(nl_cm, struct nss_nludp_st_rule, cm); ++ uncfg = &nl_rule->num.msg.uncfg; ++ ++ /* ++ * Convert the ipv6 address to NSS foramt. ++ */ ++ if (uncfg->ip_version == NSS_UDP_ST_FLAG_IPV6) { ++ nss_nludp_st_swap_addr_ipv6(uncfg->src_ip.ip.ipv6, uncfg->src_ip.ip.ipv6); ++ nss_nludp_st_swap_addr_ipv6(uncfg->dest_ip.ip.ipv6, uncfg->dest_ip.ip.ipv6); ++ } + + /* + * Unconfigure udp_st only for the transmit node. +@@ -1118,13 +1719,13 @@ static int nss_nludp_st_ops_uncfg_rule(s + /* + * Destroy rule based on ip version + */ +- if (nl_rule->num.msg.uncfg.ip_version == NSS_UDP_ST_FLAG_IPV4) { ++ if (uncfg->ip_version == NSS_UDP_ST_FLAG_IPV4) { + ret = nss_nludp_st_destroy_ipv4_rule(skb, nl_rule); +- } else if (nl_rule->num.msg.uncfg.ip_version == NSS_UDP_ST_FLAG_IPV6) { ++ } else if (uncfg->ip_version == NSS_UDP_ST_FLAG_IPV6) { + ret = nss_nludp_st_destroy_ipv6_rule(skb, nl_rule); + } else { + goto fail; +- } ++ } + + if (ret < 0) { + nss_nl_error("%px: Unable to delete a rule entry for ipv%d.\n", skb, nl_rule->num.msg.uncfg.ip_version); +@@ -1150,6 +1751,7 @@ static int nss_nludp_st_ops_cfg_rule(str + { + struct nss_nludp_st_rule *nl_rule; + struct nss_nlcmn *nl_cm; ++ struct nss_udp_st_cfg *cfg; + int ret = 0; + + /* +@@ -1165,6 +1767,15 @@ static int nss_nludp_st_ops_cfg_rule(str + * Message validation required before accepting the configuration + */ + nl_rule = container_of(nl_cm, struct nss_nludp_st_rule, cm); ++ cfg = &nl_rule->num.msg.cfg; ++ ++ /* ++ * Convert the ipv6 address to NSS foramt. ++ */ ++ if (cfg->ip_version == NSS_UDP_ST_FLAG_IPV6) { ++ nss_nludp_st_swap_addr_ipv6(cfg->src_ip.ip.ipv6, cfg->src_ip.ip.ipv6); ++ nss_nludp_st_swap_addr_ipv6(cfg->dest_ip.ip.ipv6, cfg->dest_ip.ip.ipv6); ++ } + + /* + * Configures udp_st only for the transmit node. +@@ -1179,9 +1790,9 @@ static int nss_nludp_st_ops_cfg_rule(str + /* + * Create rule based on ip version + */ +- if (nl_rule->num.msg.cfg.ip_version == NSS_UDP_ST_FLAG_IPV4) { ++ if (cfg->ip_version == NSS_UDP_ST_FLAG_IPV4) { + ret = nss_nludp_st_create_ipv4_rule(skb, nl_rule); +- } else if (nl_rule->num.msg.cfg.ip_version == NSS_UDP_ST_FLAG_IPV6) { ++ } else if (cfg->ip_version == NSS_UDP_ST_FLAG_IPV6) { + ret = nss_nludp_st_create_ipv6_rule(skb, nl_rule); + } else { + goto fail; diff --git a/qca-nss-clients/patches-11.4/0036-vxlanmgr-backport-12.5.patch b/qca-nss-clients/patches-11.4/0036-vxlanmgr-backport-12.5.patch new file mode 100644 index 0000000..829ce4d --- /dev/null +++ b/qca-nss-clients/patches-11.4/0036-vxlanmgr-backport-12.5.patch @@ -0,0 +1,357 @@ +From 580a9ff682ea4e19cb30720662aeecb1ab5df859 Mon Sep 17 00:00:00 2001 +From: Apoorv Gupta +Date: Mon, 12 Jul 2021 18:12:43 +0530 +Subject: [PATCH] [qca-nss-clients] Options not supported with VxLAN + +Flows through VxLAN tunnel should not be accelerated +if the following options are used, + 1. RSC(route short-circuit), + 2. GPE(Generic Protocol Extension) + +Change-Id: I183d24925e1a99ae49a9f1f6011bb7f08eab92f2 +Signed-off-by: Apoorv Gupta +--- + vxlanmgr/nss_vxlanmgr_tunnel.c | 22 +++++++++++++++++++--- + 1 file changed, 19 insertions(+), 3 deletions(-) + +--- a/vxlanmgr/nss_vxlanmgr_tunnel.c ++++ b/vxlanmgr/nss_vxlanmgr_tunnel.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -91,18 +91,23 @@ static uint16_t nss_vxlanmgr_tunnel_flag + uint16_t flags = 0; + uint32_t priv_flags = priv->flags; + ++ if (priv_flags & VXLAN_F_RSC) ++ return flags; + if (priv_flags & VXLAN_F_GBP) + flags |= NSS_VXLAN_RULE_FLAG_GBP_ENABLED; +- if (priv_flags & VXLAN_F_IPV6) ++ ++ if (priv_flags & VXLAN_F_IPV6) { + flags |= NSS_VXLAN_RULE_FLAG_IPV6; +- else if (!(priv_flags & VXLAN_F_IPV6)) ++ if (!(priv_flags & VXLAN_F_UDP_ZERO_CSUM6_TX)) ++ flags |= NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED; ++ } else { + flags |= NSS_VXLAN_RULE_FLAG_IPV4; ++ if (priv_flags & VXLAN_F_UDP_CSUM) ++ flags |= NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED; ++ } ++ + if (priv->cfg.tos == 1) + flags |= NSS_VXLAN_RULE_FLAG_INHERIT_TOS; +- if (priv_flags & VXLAN_F_UDP_CSUM) +- flags |= NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED; +- else if (!(priv_flags & VXLAN_F_UDP_ZERO_CSUM6_TX)) +- flags |= NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED; + + return (flags | NSS_VXLAN_RULE_FLAG_UDP); + } +@@ -113,18 +118,25 @@ static uint16_t nss_vxlanmgr_tunnel_flag + struct vxlan_config *cfg = &priv->cfg; + uint32_t priv_flags = cfg->flags; + ++ if (priv_flags & VXLAN_F_RSC) ++ return flags; ++ if (priv_flags & VXLAN_F_GPE) ++ return flags; + if (priv_flags & VXLAN_F_GBP) + flags |= NSS_VXLAN_RULE_FLAG_GBP_ENABLED; +- if (priv_flags & VXLAN_F_IPV6) ++ ++ if (priv_flags & VXLAN_F_IPV6) { + flags |= NSS_VXLAN_RULE_FLAG_IPV6; +- else if (!(priv_flags & VXLAN_F_IPV6)) ++ if (!(priv_flags & VXLAN_F_UDP_ZERO_CSUM6_TX)) ++ flags |= NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED; ++ } else { + flags |= NSS_VXLAN_RULE_FLAG_IPV4; ++ if (!(priv_flags & VXLAN_F_UDP_ZERO_CSUM_TX)) ++ flags |= NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED; ++ } ++ + if (cfg->tos == 1) + flags |= NSS_VXLAN_RULE_FLAG_INHERIT_TOS; +- if (priv_flags & VXLAN_F_UDP_ZERO_CSUM_TX) +- flags |= NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED; +- else if (!(priv_flags & VXLAN_F_UDP_ZERO_CSUM6_TX)) +- flags |= NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED; + + return (flags | NSS_VXLAN_RULE_FLAG_UDP); + } +@@ -436,7 +448,8 @@ static struct notifier_block nss_vxlanmg + + /* + * nss_vxlanmgr_tunnel_inner_stats() +- * Update vxlan netdev stats with inner node stats ++ * Update vxlan netdev stats with inner node stats. ++ * Note: Reference on the netdevice is expected to be held by the caller at the time this function is called. + */ + static void nss_vxlanmgr_tunnel_inner_stats(struct nss_vxlanmgr_tun_ctx *tun_ctx, struct nss_vxlan_msg *nvm) + { +@@ -450,7 +463,6 @@ static void nss_vxlanmgr_tunnel_inner_st + stats = &nvm->msg.stats; + dev = tun_ctx->dev; + +- dev_hold(dev); + netdev_stats = (struct net_device_stats *)&dev->stats; + + /* +@@ -469,7 +481,6 @@ static void nss_vxlanmgr_tunnel_inner_st + u64_stats_add(&tstats->tx_bytes, stats->node_stats.tx_bytes); + u64_stats_update_end(&tstats->syncp); + netdev_stats->tx_dropped += dropped; +- dev_put(dev); + } + + /* +@@ -514,7 +525,7 @@ static void nss_vxlanmgr_tunnel_outer_st + * nss_vxlanmgr_tunnel_fdb_update() + * Update vxlan fdb entries + */ +-static void nss_vxlanmgr_tunnel_fdb_update(struct nss_vxlanmgr_tun_ctx *tun_ctx, struct nss_vxlan_msg *nvm) ++static void nss_vxlanmgr_tunnel_fdb_update(struct net_device *dev, uint32_t vni, struct nss_vxlan_msg *nvm) + { + uint8_t *mac; + uint16_t i, nentries; +@@ -523,13 +534,10 @@ static void nss_vxlanmgr_tunnel_fdb_upda + + db_stats = &nvm->msg.db_stats; + nentries = db_stats->cnt; +- priv = netdev_priv(tun_ctx->dev); +- +- dev_hold(tun_ctx->dev); ++ priv = netdev_priv(dev); + + if (nentries > NSS_VXLAN_MACDB_ENTRIES_PER_MSG) { +- nss_vxlanmgr_warn("%px: No more than 20 entries allowed per message.\n", tun_ctx->dev); +- dev_put(tun_ctx->dev); ++ nss_vxlanmgr_warn("%px: No more than 20 entries allowed per message.\n", dev); + return; + } + +@@ -539,11 +547,10 @@ static void nss_vxlanmgr_tunnel_fdb_upda + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 5, 7)) + vxlan_fdb_update_mac(priv, mac); + #else +- vxlan_fdb_update_mac(priv, mac, tun_ctx->vni); ++ vxlan_fdb_update_mac(priv, mac, vni); + #endif + } + } +- dev_put(tun_ctx->dev); + } + + /* +@@ -555,20 +562,29 @@ static void nss_vxlanmgr_tunnel_inner_no + struct net_device *dev = (struct net_device *)app_data; + struct nss_vxlanmgr_tun_ctx *tun_ctx; + struct nss_vxlan_msg *nvm; ++ uint32_t vni; + + if (!ncm) { + nss_vxlanmgr_info("%px: NULL msg received.\n", dev); + return; + } + ++ if (!dev) { ++ nss_vxlanmgr_info("%px: NULL device received.\n", dev); ++ return; ++ } ++ + spin_lock_bh(&vxlan_ctx.tun_lock); ++ dev_hold(dev); + tun_ctx = nss_vxlanmgr_tunnel_ctx_dev_get(dev); + if (!tun_ctx) { + spin_unlock_bh(&vxlan_ctx.tun_lock); + nss_vxlanmgr_warn("%px: Invalid tunnel context\n", dev); ++ dev_put(dev); + return; + } + ++ vni = tun_ctx->vni; + nvm = (struct nss_vxlan_msg *)ncm; + switch (nvm->cm.type) { + case NSS_VXLAN_MSG_TYPE_STATS_SYNC: +@@ -576,14 +592,24 @@ static void nss_vxlanmgr_tunnel_inner_no + nss_vxlanmgr_tun_stats_sync(tun_ctx, nvm); + break; + case NSS_VXLAN_MSG_TYPE_MACDB_STATS: +- nss_vxlanmgr_tunnel_fdb_update(tun_ctx, nvm); + nss_vxlanmgr_tun_macdb_stats_sync(tun_ctx, nvm); +- break; +- default: ++ ++ /* ++ * Release the lock before updating the Linux FDB entry. ++ * This will ensure there is no deadlock when a potential ++ * MAC add event occurs at same time, which needs to hold ++ * the kernel's hash lock followed by the tunnel ctx lock. ++ */ + spin_unlock_bh(&vxlan_ctx.tun_lock); +- nss_vxlanmgr_info("%px: Unknown Event from NSS", dev); ++ ++ nss_vxlanmgr_tunnel_fdb_update(dev, vni, nvm); ++ dev_put(dev); + return; ++ default: ++ nss_vxlanmgr_info("%px: Unknown Event from NSS", dev); + } ++ ++ dev_put(dev); + spin_unlock_bh(&vxlan_ctx.tun_lock); + } + +@@ -829,7 +855,7 @@ done: + */ + int nss_vxlanmgr_tunnel_destroy(struct net_device *dev) + { +- uint32_t inner_ifnum, outer_ifnum; ++ uint32_t inner_ifnum, outer_ifnum, tun_count; + struct nss_vxlanmgr_tun_ctx *tun_ctx; + struct nss_vxlan_msg vxlanmsg; + nss_tx_status_t ret; +@@ -866,16 +892,21 @@ int nss_vxlanmgr_tunnel_destroy(struct n + + nss_vxlanmgr_tun_stats_deinit(tun_ctx); + nss_vxlanmgr_tun_stats_dentry_remove(tun_ctx); ++ dev_put(tun_ctx->dev); + kfree(tun_ctx); + +- if (!vxlan_ctx.tun_count) { +- /* +- * Unregister fdb notifier chain if +- * all vxlan tunnels are destroyed. +- */ ++ /* ++ * Unregister fdb notifier chain if ++ * all vxlan tunnels are destroyed. ++ */ ++ spin_lock_bh(&vxlan_ctx.tun_lock); ++ tun_count = vxlan_ctx.tun_count; ++ spin_unlock_bh(&vxlan_ctx.tun_lock); ++ if (!tun_count) { + vxlan_fdb_unregister_notify(&nss_vxlanmgr_tunnel_fdb_notifier); + } +- nss_vxlanmgr_info("%px: VxLAN interface count is #%d\n", dev, vxlan_ctx.tun_count); ++ ++ nss_vxlanmgr_info("%px: VxLAN interface count is #%d\n", dev, tun_count); + + memset(&vxlanmsg, 0, sizeof(struct nss_vxlan_msg)); + ret = nss_vxlanmgr_tunnel_tx_msg_sync(vxlan_ctx.nss_ctx, +@@ -929,6 +960,7 @@ int nss_vxlanmgr_tunnel_create(struct ne + struct nss_vxlan_rule_msg *vxlan_cfg; + struct nss_ctx_instance *nss_ctx; + uint32_t inner_ifnum, outer_ifnum; ++ uint16_t parse_flags; + nss_tx_status_t ret; + + spin_lock_bh(&vxlan_ctx.tun_lock); +@@ -939,7 +971,20 @@ int nss_vxlanmgr_tunnel_create(struct ne + } + spin_unlock_bh(&vxlan_ctx.tun_lock); + ++ /* ++ * The reference to the dev will be released in nss_vxlanmgr_tunnel_destroy() ++ */ + dev_hold(dev); ++ priv = netdev_priv(dev); ++ parse_flags = nss_vxlanmgr_tunnel_flags_parse(priv); ++ ++ /* ++ * Check if the tunnel is supported. ++ */ ++ if (!parse_flags) { ++ nss_vxlanmgr_warn("%px: Tunnel offload not supported\n", dev); ++ goto ctx_alloc_fail; ++ } + + tun_ctx = kzalloc(sizeof(struct nss_vxlanmgr_tun_ctx), GFP_ATOMIC); + if (!tun_ctx) { +@@ -988,12 +1033,11 @@ int nss_vxlanmgr_tunnel_create(struct ne + memset(&vxlanmsg, 0, sizeof(struct nss_vxlan_msg)); + vxlan_cfg = &vxlanmsg.msg.vxlan_create; + +- priv = netdev_priv(dev); + vxlan_cfg->vni = vxlan_get_vni(priv); +- vxlan_cfg->tunnel_flags = nss_vxlanmgr_tunnel_flags_parse(priv); ++ vxlan_cfg->tunnel_flags = parse_flags; + vxlan_cfg->src_port_min = priv->cfg.port_min; + vxlan_cfg->src_port_max = priv->cfg.port_max; +- vxlan_cfg->dest_port = priv->cfg.dst_port; ++ vxlan_cfg->dest_port = ntohs(priv->cfg.dst_port); + vxlan_cfg->tos = priv->cfg.tos; + vxlan_cfg->ttl = (priv->cfg.ttl ? priv->cfg.ttl : IPDEFTTL); + +@@ -1059,7 +1103,6 @@ int nss_vxlanmgr_tunnel_create(struct ne + spin_unlock_bh(&vxlan_ctx.tun_lock); + nss_vxlanmgr_info("%px: VxLAN interface count is #%d\n", dev, vxlan_ctx.tun_count); + +- dev_put(dev); + return NOTIFY_DONE; + + config_fail: +--- a/vxlanmgr/nss_vxlanmgr_tun_stats.c ++++ b/vxlanmgr/nss_vxlanmgr_tun_stats.c +@@ -89,7 +89,7 @@ static int nss_vxlanmgr_tun_stats_show(s + seq_printf(m, "\t\tflow_label = %u\n", tun_ctx->flow_label); + seq_printf(m, "\t\tsrc_port_min = %u\n", tun_ctx->src_port_min); + seq_printf(m, "\t\tsrc_port_max = %u\n", tun_ctx->src_port_max); +- seq_printf(m, "\t\tdest_port = %u\n", ntohs(tun_ctx->dest_port)); ++ seq_printf(m, "\t\tdest_port = %u\n", tun_ctx->dest_port); + seq_printf(m, "\t\ttos = %u\n", tun_ctx->tos); + seq_printf(m, "\t\tttl = %u\n", tun_ctx->ttl); + +@@ -173,6 +173,7 @@ void nss_vxlanmgr_tun_stats_update(uint6 + /* + * nss_vxlanmgr_tun_macdb_stats_sync() + * Sync function for vxlan fdb entries ++ * Note: Reference on the netdevice is expected to be held by the caller at the time this function is called. + */ + void nss_vxlanmgr_tun_macdb_stats_sync(struct nss_vxlanmgr_tun_ctx *tun_ctx, struct nss_vxlan_msg *nvm) + { +@@ -183,11 +184,8 @@ void nss_vxlanmgr_tun_macdb_stats_sync(s + db_stats = &nvm->msg.db_stats; + nentries = db_stats->cnt; + +- dev_hold(tun_ctx->dev); +- + if (nentries > NSS_VXLAN_MACDB_ENTRIES_PER_MSG) { + nss_vxlanmgr_warn("%px: No more than 20 entries allowed per message.\n", tun_ctx->dev); +- dev_put(tun_ctx->dev); + return; + } + +@@ -203,7 +201,6 @@ void nss_vxlanmgr_tun_macdb_stats_sync(s + } + } + } +- dev_put(tun_ctx->dev); + } + + /* +@@ -299,7 +296,7 @@ bool nss_vxlanmgr_tun_stats_dentry_creat + * nss_vxlanmgr_tun_stats_dentry_deinit() + * Cleanup the debugfs tree. + */ +-void nss_vxlanmgr_tun_stats_dentry_deinit() ++void nss_vxlanmgr_tun_stats_dentry_deinit(void) + { + debugfs_remove_recursive(vxlan_ctx.dentry); + } +@@ -308,7 +305,7 @@ void nss_vxlanmgr_tun_stats_dentry_deini + * nss_vxlanmgr_tun_stats_dentry_init() + * Create VxLAN tunnel statistics debugfs entry. + */ +-bool nss_vxlanmgr_tun_stats_dentry_init() ++bool nss_vxlanmgr_tun_stats_dentry_init(void) + { + /* + * initialize debugfs. diff --git a/qca-nss-clients/patches-11.4/0037-netlink-reorganize-log-level.patch b/qca-nss-clients/patches-11.4/0037-netlink-reorganize-log-level.patch new file mode 100644 index 0000000..38638e9 --- /dev/null +++ b/qca-nss-clients/patches-11.4/0037-netlink-reorganize-log-level.patch @@ -0,0 +1,1102 @@ +--- a/netlink/Makefile ++++ b/netlink/Makefile +@@ -5,7 +5,7 @@ DTLS_ENABLED := $(strip $(if $(filter $( + ccflags-y := -Wall -Werror + ccflags-y += -I$(obj)/include + ccflags-y += -I$(obj)/../exports +-ccflags-y += -DNSS_NL_DEBUG_LEVEL=4 ++ccflags-y += -DNSS_NL_DEBUG_LEVEL=2 + ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)" + + ccflags-y += -DCONFIG_NSS_NLIPV4=1 +--- a/netlink/nss_nl.c ++++ b/netlink/nss_nl.c +@@ -527,12 +527,12 @@ static int __init nss_nl_init(void) + * Check if the family exists + */ + if (!family->valid || !family->entry) { +- nss_nl_info_always("skipping family:%s\n", family->name); +- nss_nl_info_always("valid = %d, entry = %d\n", family->valid, !!family->entry); ++ nss_nl_info("skipping family:%s\n", family->name); ++ nss_nl_info("valid = %d, entry = %d\n", family->valid, !!family->entry); + continue; + } + +- nss_nl_info_always("attaching family:%s\n", family->name); ++ nss_nl_info("attaching family:%s\n", family->name); + + family->entry(); + } +@@ -557,7 +557,7 @@ static void __exit nss_nl_exit(void) + return; + } + #endif +- nss_nl_info_always("NSS Netlink manager unloaded\n"); ++ nss_nl_info("NSS Netlink manager unloaded\n"); + + /* + * initialize the handler families +@@ -569,12 +569,12 @@ static void __exit nss_nl_exit(void) + * Check if the family exists + */ + if (!family->valid || !family->exit) { +- nss_nl_info_always("skipping family:%s\n", family->name); +- nss_nl_info_always("valid = %d, exit = %d\n", family->valid, !!family->exit); ++ nss_nl_info("skipping family:%s\n", family->name); ++ nss_nl_info("valid = %d, exit = %d\n", family->valid, !!family->exit); + continue; + } + +- nss_nl_info_always("detaching family:%s\n", family->name); ++ nss_nl_info("detaching family:%s\n", family->name); + + family->exit(); + } +--- a/netlink/nss_nlc2c_rx.c ++++ b/netlink/nss_nlc2c_rx.c +@@ -126,14 +126,14 @@ bool nss_nlc2c_rx_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink c2c_rx handler\n"); ++ nss_nl_info("Init NSS netlink c2c_rx handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nlc2c_rx_family); + if (error) { +- nss_nl_info_always("Error: unable to register c2c_rx family\n"); ++ nss_nl_error("Error: unable to register c2c_rx family\n"); + return false; + } + +@@ -142,7 +142,7 @@ bool nss_nlc2c_rx_init(void) + */ + ret = nss_c2c_rx_stats_register_notifier(&nss_c2c_rx_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context \n"); ++ nss_nl_error("Error: retreiving the NSS Context \n"); + genl_unregister_family(&nss_nlc2c_rx_family); + return false; + } +@@ -158,7 +158,7 @@ bool nss_nlc2c_rx_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink c2c_rx handler\n"); ++ nss_nl_info("Exit NSS netlink c2c_rx handler\n"); + + /* + * Unregister the device callback handler for c2c_rx +@@ -170,7 +170,7 @@ bool nss_nlc2c_rx_exit(void) + */ + error = genl_unregister_family(&nss_nlc2c_rx_family); + if (error) { +- nss_nl_info_always("unable to unregister c2c_rx NETLINK family\n"); ++ nss_nl_error("unable to unregister c2c_rx NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nlc2c_tx.c ++++ b/netlink/nss_nlc2c_tx.c +@@ -126,14 +126,14 @@ bool nss_nlc2c_tx_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink c2c_tx handler\n"); ++ nss_nl_info("Init NSS netlink c2c_tx handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nlc2c_tx_family); + if (error) { +- nss_nl_info_always("Error: unable to register c2c_tx family\n"); ++ nss_nl_error("Error: unable to register c2c_tx family\n"); + return false; + } + +@@ -142,7 +142,7 @@ bool nss_nlc2c_tx_init(void) + */ + ret = nss_c2c_tx_stats_register_notifier(&nss_c2c_tx_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context \n"); ++ nss_nl_error("Error: retreiving the NSS Context \n"); + genl_unregister_family(&nss_nlc2c_tx_family); + return false; + } +@@ -158,7 +158,7 @@ bool nss_nlc2c_tx_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink c2c_tx handler\n"); ++ nss_nl_info("Exit NSS netlink c2c_tx handler\n"); + + /* + * Unregister the device callback handler for c2c_tx +@@ -170,7 +170,7 @@ bool nss_nlc2c_tx_exit(void) + */ + error = genl_unregister_family(&nss_nlc2c_tx_family); + if (error) { +- nss_nl_info_always("unable to unregister c2c_tx NETLINK family\n"); ++ nss_nl_error("unable to unregister c2c_tx NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nlcapwap.c ++++ b/netlink/nss_nlcapwap.c +@@ -1495,7 +1495,7 @@ bool nss_nlcapwap_init(void) + { + int err; + +- nss_nl_info_always("Init NSS netlink capwap handler\n"); ++ nss_nl_info("Init NSS netlink capwap handler\n"); + + /* + * Initialize atomic variable +@@ -1507,7 +1507,7 @@ bool nss_nlcapwap_init(void) + */ + global_ctx.capwap_dev = nss_capwapmgr_get_netdev(); + if (!global_ctx.capwap_dev) { +- nss_nl_info_always("Failed to find the CAPWAP device\n"); ++ nss_nl_error("Failed to find the CAPWAP device\n"); + } + + /* +@@ -1515,12 +1515,12 @@ bool nss_nlcapwap_init(void) + */ + global_ctx.dentry = debugfs_create_dir("nlcapwap", NULL); + if (!global_ctx.dentry) { +- nss_nl_info_always("Cannot create nlcapwap directory\n"); ++ nss_nl_error("Cannot create nlcapwap directory\n"); + return false; + } + + if (!debugfs_create_file("stats", 0400, global_ctx.dentry, NULL, &nss_nlcapwap_stats_ops)) { +- nss_nl_info_always("Cannot create nlcapwap dentry file\n"); ++ nss_nl_error("Cannot create nlcapwap dentry file\n"); + return false; + } + +@@ -1529,7 +1529,7 @@ bool nss_nlcapwap_init(void) + */ + err = genl_register_family(&nss_nlcapwap_family); + if (err) { +- nss_nl_info_always("Error: %d unable to register capwap family\n", err); ++ nss_nl_error("Error: %d unable to register capwap family\n", err); + goto free; + } + +@@ -1538,7 +1538,7 @@ bool nss_nlcapwap_init(void) + */ + err = nss_capwap_stats_register_notifier(&nss_capwap_stats_notifier_nb); + if (err) { +- nss_nl_info_always("Error: %d unable to register capwap stats notifier\n", err); ++ nss_nl_error("Error: %d unable to register capwap stats notifier\n", err); + goto free_family; + } + +@@ -1579,14 +1579,14 @@ bool nss_nlcapwap_exit(void) + int err; + int i; + +- nss_nl_info_always("Exit NSS netlink capwap handler\n"); ++ nss_nl_info("Exit NSS netlink capwap handler\n"); + + /* + * unregister the ops family so that we don't receive any new requests + */ + err = genl_unregister_family(&nss_nlcapwap_family); + if (err) { +- nss_nl_info_always("Error: %d unable to unregister capwap NETLINK family\n", err); ++ nss_nl_error("Error: %d unable to unregister capwap NETLINK family\n", err); + return false; + } + +--- a/netlink/nss_nldtls.c ++++ b/netlink/nss_nldtls.c +@@ -1159,14 +1159,14 @@ bool nss_nldtls_init(void) + { + int err; + +- nss_nl_info_always("Init NSS netlink dtls handler\n"); ++ nss_nl_info("Init NSS netlink dtls handler\n"); + + /* + * register NETLINK ops with the family + */ + err = genl_register_family(&nss_nldtls_family); + if (err) { +- nss_nl_info_always("Error: %d unable to register gre_redir family\n", err); ++ nss_nl_error("Error: %d unable to register gre_redir family\n", err); + genl_unregister_family(&nss_nldtls_family); + return false; + } +@@ -1176,12 +1176,12 @@ bool nss_nldtls_init(void) + */ + gbl_ctx.dentry = debugfs_create_dir("nldtls", NULL); + if (!gbl_ctx.dentry) { +- nss_nl_info_always("Cannot create nldtls directory\n"); ++ nss_nl_error("Cannot create nldtls directory\n"); + goto free_family; + } + + if (!debugfs_create_file("stats", 0400, gbl_ctx.dentry, NULL, &nss_nldtls_stats_ops)) { +- nss_nl_info_always("Cannot create nldtls dentry file\n"); ++ nss_nl_error("Cannot create nldtls dentry file\n"); + goto free_debugfs; + } + +@@ -1205,7 +1205,7 @@ bool nss_nldtls_exit(void) + struct net_device *dev; + int err; + +- nss_nl_info_always("Exit NSS netlink dtls handler\n"); ++ nss_nl_info("Exit NSS netlink dtls handler\n"); + + /* + * Destroy all active tunnel before exiting +@@ -1218,14 +1218,14 @@ bool nss_nldtls_exit(void) + } + } + +- nss_nl_info_always("All active tunnels destroyed\n"); ++ nss_nl_info("All active tunnels destroyed\n"); + + /* + * unregister the ops family + */ + err = genl_unregister_family(&nss_nldtls_family); + if (err) { +- nss_nl_info_always("Error: %d unable to unregister dtls NETLINK family\n", err); ++ nss_nl_error("Error: %d unable to unregister dtls NETLINK family\n", err); + return false; + } + +--- a/netlink/nss_nldynamic_interface.c ++++ b/netlink/nss_nldynamic_interface.c +@@ -126,14 +126,14 @@ bool nss_nldynamic_interface_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink dynamic_interface handler\n"); ++ nss_nl_info("Init NSS netlink dynamic_interface handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nldynamic_interface_family); + if (error) { +- nss_nl_info_always("Error: unable to register dynamic_interface family\n"); ++ nss_nl_error("Error: unable to register dynamic_interface family\n"); + return false; + } + +@@ -142,7 +142,7 @@ bool nss_nldynamic_interface_init(void) + */ + ret = nss_dynamic_interface_stats_register_notifier(&nss_dynamic_interface_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context \n"); ++ nss_nl_error("Error: retreiving the NSS Context \n"); + genl_unregister_family(&nss_nldynamic_interface_family); + return false; + } +@@ -158,7 +158,7 @@ bool nss_nldynamic_interface_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink dynamic_interface handler\n"); ++ nss_nl_info("Exit NSS netlink dynamic_interface handler\n"); + + /* + * Unregister the device callback handler for dynamic interface +@@ -170,7 +170,7 @@ bool nss_nldynamic_interface_exit(void) + */ + error = genl_unregister_family(&nss_nldynamic_interface_family); + if (error) { +- nss_nl_info_always("unable to unregister dynamic_interface NETLINK family\n"); ++ nss_nl_error("unable to unregister dynamic_interface NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nledma.c ++++ b/netlink/nss_nledma.c +@@ -131,14 +131,14 @@ bool nss_nledma_init(void) + { + int error, ret; + +- nss_nl_info_always("Init NSS netlink Edma handler\n"); ++ nss_nl_info("Init NSS netlink Edma handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nledma_family); + if (error) { +- nss_nl_info_always("Error: unable to register Edma family\n"); ++ nss_nl_error("Error: unable to register Edma family\n"); + return false; + } + +@@ -147,7 +147,7 @@ bool nss_nledma_init(void) + */ + ret = nss_edma_stats_register_notifier(&nss_edma_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context\n"); ++ nss_nl_error("Error: retreiving the NSS Context\n"); + genl_unregister_family(&nss_nledma_family); + return false; + } +@@ -163,7 +163,7 @@ bool nss_nledma_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink Edma handler\n"); ++ nss_nl_info("Exit NSS netlink Edma handler\n"); + + /* + * Unregister the device callback handler for edma +@@ -175,7 +175,7 @@ bool nss_nledma_exit(void) + */ + error = genl_unregister_family(&nss_nledma_family); + if (error) { +- nss_nl_info_always("unable to unregister Edma NETLINK family\n"); ++ nss_nl_error("unable to unregister Edma NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nlethrx.c ++++ b/netlink/nss_nlethrx.c +@@ -126,14 +126,14 @@ bool nss_nlethrx_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink eth_rx handler\n"); ++ nss_nl_info("Init NSS netlink eth_rx handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nlethrx_family); + if (error) { +- nss_nl_info_always("Error: unable to register eth_rx family\n"); ++ nss_nl_error("Error: unable to register eth_rx family\n"); + return false; + } + +@@ -142,7 +142,7 @@ bool nss_nlethrx_init(void) + */ + ret = nss_eth_rx_stats_register_notifier(&nss_eth_rx_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context \n"); ++ nss_nl_error("Error: retreiving the NSS Context \n"); + genl_unregister_family(&nss_nlethrx_family); + return false; + } +@@ -158,7 +158,7 @@ bool nss_nlethrx_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink eth_rx handler\n"); ++ nss_nl_info("Exit NSS netlink eth_rx handler\n"); + + /* + * Unregister the device callback handler for ethrx +@@ -170,7 +170,7 @@ bool nss_nlethrx_exit(void) + */ + error = genl_unregister_family(&nss_nlethrx_family); + if (error) { +- nss_nl_info_always("unable to unregister eth_rx NETLINK family\n"); ++ nss_nl_error("unable to unregister eth_rx NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nlgre_redir_family.c ++++ b/netlink/nss_nlgre_redir_family.c +@@ -34,14 +34,14 @@ + bool nss_nlgre_redir_family_init(void) + { + int err; +- nss_nl_info_always("Init NSS netlink gre_redir handler\n"); ++ nss_nl_info("Init NSS netlink gre_redir handler\n"); + + /* + * register NETLINK ops with the family + */ + err = genl_register_family(&nss_nlgre_redir_cmd_family); + if (err) { +- nss_nl_info_always("Error: %d unable to register gre_redir family\n", err); ++ nss_nl_error("Error: %d unable to register gre_redir family\n", err); + return false; + } + +@@ -55,14 +55,14 @@ bool nss_nlgre_redir_family_init(void) + bool nss_nlgre_redir_family_exit(void) + { + int err; +- nss_nl_info_always("Exit NSS netlink gre_redir handler\n"); ++ nss_nl_info("Exit NSS netlink gre_redir handler\n"); + + /* + * unregister the ops family + */ + err = genl_unregister_family(&nss_nlgre_redir_cmd_family); + if (err) { +- nss_nl_info_always("Error: %d unable to unregister gre_redir NETLINK family\n", err); ++ nss_nl_error("Error: %d unable to unregister gre_redir NETLINK family\n", err); + return false; + } + +--- a/netlink/nss_nlipsec.c ++++ b/netlink/nss_nlipsec.c +@@ -707,7 +707,7 @@ bool nss_nlipsec_init(void) + int error; + int i; + +- nss_nl_info_always("Init NSS netlink IPsec handler\n"); ++ nss_nl_info("Init NSS netlink IPsec handler\n"); + + /* + * Initialize reference table +@@ -723,7 +723,7 @@ bool nss_nlipsec_init(void) + */ + error = genl_register_family(&nss_nlipsec_family); + if (error != 0) { +- nss_nl_info_always("Error: unable to register IPsec family\n"); ++ nss_nl_error("Error: unable to register IPsec family\n"); + return false; + } + +@@ -738,14 +738,14 @@ bool nss_nlipsec_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink IPsec handler\n"); ++ nss_nl_info("Exit NSS netlink IPsec handler\n"); + + /* + * unregister the ops family + */ + error = genl_unregister_family(&nss_nlipsec_family); + if (error != 0) { +- nss_nl_info_always("Unregister IPsec NETLINK family failed\n"); ++ nss_nl_error("Unregister IPsec NETLINK family failed\n"); + return false; + } + +--- a/netlink/nss_nlipv4.c ++++ b/netlink/nss_nlipv4.c +@@ -966,14 +966,14 @@ bool nss_nlipv4_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink IPv4 handler\n"); ++ nss_nl_info("Init NSS netlink IPv4 handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nlipv4_family); + if (error != 0) { +- nss_nl_info_always("Error: unable to register IPv4 family\n"); ++ nss_nl_error("Error: unable to register IPv4 family\n"); + return false; + } + +@@ -982,7 +982,7 @@ bool nss_nlipv4_init(void) + */ + gbl_ctx.nss = nss_ipv4_get_mgr(); + if (!gbl_ctx.nss) { +- nss_nl_info_always("Error: retreiving the NSS Context \n"); ++ nss_nl_error("Error: retreiving the NSS Context \n"); + goto unreg_family; + } + +@@ -991,7 +991,7 @@ bool nss_nlipv4_init(void) + */ + ret = nss_ipv4_stats_register_notifier(&nss_ipv4_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context \n"); ++ nss_nl_error("Error: retreiving the NSS Context \n"); + goto unreg_family; + } + +@@ -1014,14 +1014,14 @@ bool nss_nlipv4_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink IPv4 handler\n"); ++ nss_nl_info("Exit NSS netlink IPv4 handler\n"); + + /* + * unregister the ops family + */ + error = genl_unregister_family(&nss_nlipv4_family); + if (error != 0) { +- nss_nl_info_always("unable to unregister IPv4 NETLINK family\n"); ++ nss_nl_error("unable to unregister IPv4 NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nlipv4_reasm.c ++++ b/netlink/nss_nlipv4_reasm.c +@@ -126,14 +126,14 @@ bool nss_nlipv4_reasm_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink ipv4_reasm handler\n"); ++ nss_nl_info("Init NSS netlink ipv4_reasm handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nlipv4_reasm_family); + if (error) { +- nss_nl_info_always("Error: unable to register ipv4_reasm family\n"); ++ nss_nl_error("Error: unable to register ipv4_reasm family\n"); + return false; + } + +@@ -142,7 +142,7 @@ bool nss_nlipv4_reasm_init(void) + */ + ret = nss_ipv4_reasm_stats_register_notifier(&nss_ipv4_reasm_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context \n"); ++ nss_nl_error("Error: retreiving the NSS Context \n"); + genl_unregister_family(&nss_nlipv4_reasm_family); + return false; + } +@@ -158,7 +158,7 @@ bool nss_nlipv4_reasm_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink ipv4_reasm handler\n"); ++ nss_nl_info("Exit NSS netlink ipv4_reasm handler\n"); + + /* + * Unregister the device callback handler for ipv4_reasm +@@ -170,7 +170,7 @@ bool nss_nlipv4_reasm_exit(void) + */ + error = genl_unregister_family(&nss_nlipv4_reasm_family); + if (error) { +- nss_nl_info_always("unable to unregister ipv4_reasm NETLINK family\n"); ++ nss_nl_error("unable to unregister ipv4_reasm NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nlipv6.c ++++ b/netlink/nss_nlipv6.c +@@ -967,14 +967,14 @@ bool nss_nlipv6_init(void) + { + int error, ret; + +- nss_nl_info_always("Init NSS netlink IPV6 handler\n"); ++ nss_nl_info("Init NSS netlink IPV6 handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nlipv6_family); + if (error != 0) { +- nss_nl_info_always("Error: unable to register IPV6 family\n"); ++ nss_nl_error("Error: unable to register IPV6 family\n"); + return false; + } + +@@ -983,7 +983,7 @@ bool nss_nlipv6_init(void) + */ + gbl_ctx.nss = nss_ipv6_get_mgr(); + if (!gbl_ctx.nss) { +- nss_nl_info_always("Error: retreiving the NSS Context \n"); ++ nss_nl_error("Error: retreiving the NSS Context \n"); + goto unreg_family; + } + +@@ -992,7 +992,7 @@ bool nss_nlipv6_init(void) + */ + ret = nss_ipv6_stats_register_notifier(&nss_ipv6_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context \n"); ++ nss_nl_error("Error: retreiving the NSS Context \n"); + goto unreg_family; + } + +@@ -1015,7 +1015,7 @@ bool nss_nlipv6_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink IPV6 handler\n"); ++ nss_nl_info("Exit NSS netlink IPV6 handler\n"); + + /* + * Unregister the device callback handler for ipv6 +@@ -1027,7 +1027,7 @@ bool nss_nlipv6_exit(void) + */ + error = genl_unregister_family(&nss_nlipv6_family); + if (error != 0) { +- nss_nl_info_always("unable to unregister IPV6 NETLINK family\n"); ++ nss_nl_error("unable to unregister IPV6 NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nlipv6_reasm.c ++++ b/netlink/nss_nlipv6_reasm.c +@@ -126,14 +126,14 @@ bool nss_nlipv6_reasm_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink ipv6_reasm handler\n"); ++ nss_nl_info("Init NSS netlink ipv6_reasm handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nlipv6_reasm_family); + if (error) { +- nss_nl_info_always("Error: unable to register ipv6_reasm family\n"); ++ nss_nl_error("Error: unable to register ipv6_reasm family\n"); + return false; + } + +@@ -142,7 +142,7 @@ bool nss_nlipv6_reasm_init(void) + */ + ret = nss_ipv6_reasm_stats_register_notifier(&nss_ipv6_reasm_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context\n"); ++ nss_nl_error("Error: retreiving the NSS Context\n"); + genl_unregister_family(&nss_nlipv6_reasm_family); + return false; + } +@@ -158,7 +158,7 @@ bool nss_nlipv6_reasm_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink ipv6_reasm handler\n"); ++ nss_nl_info("Exit NSS netlink ipv6_reasm handler\n"); + + /* + * Unregister the device callback handler for ipv6_reasm +@@ -170,7 +170,7 @@ bool nss_nlipv6_reasm_exit(void) + */ + error = genl_unregister_family(&nss_nlipv6_reasm_family); + if (error) { +- nss_nl_info_always("unable to unregister ipv6_reasm NETLINK family\n"); ++ nss_nl_error("unable to unregister ipv6_reasm NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nll2tpv2.c ++++ b/netlink/nss_nll2tpv2.c +@@ -127,14 +127,14 @@ bool nss_nll2tpv2_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink l2tpv2 handler\n"); ++ nss_nl_info("Init NSS netlink l2tpv2 handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nll2tpv2_family); + if (error) { +- nss_nl_info_always("Error: unable to register l2tpv2 family\n"); ++ nss_nl_error("Error: unable to register l2tpv2 family\n"); + return false; + } + +@@ -143,7 +143,7 @@ bool nss_nll2tpv2_init(void) + */ + ret = nss_l2tpv2_stats_register_notifier(&nss_l2tpv2_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context\n"); ++ nss_nl_error("Error: retreiving the NSS Context\n"); + genl_unregister_family(&nss_nll2tpv2_family); + return false; + } +@@ -159,7 +159,7 @@ bool nss_nll2tpv2_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink l2tpv2 handler\n"); ++ nss_nl_info("Exit NSS netlink l2tpv2 handler\n"); + + /* + * Unregister the device callback handler for l2tpv2 +@@ -171,7 +171,7 @@ bool nss_nll2tpv2_exit(void) + */ + error = genl_unregister_family(&nss_nll2tpv2_family); + if (error) { +- nss_nl_info_always("unable to unregister l2tpv2 NETLINK family\n"); ++ nss_nl_error("unable to unregister l2tpv2 NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nllso_rx.c ++++ b/netlink/nss_nllso_rx.c +@@ -127,14 +127,14 @@ bool nss_nllso_rx_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink lso_rx handler\n"); ++ nss_nl_info("Init NSS netlink lso_rx handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nllso_rx_family); + if (error) { +- nss_nl_info_always("Error: unable to register lso_rx family\n"); ++ nss_nl_error("Error: unable to register lso_rx family\n"); + return false; + } + +@@ -143,7 +143,7 @@ bool nss_nllso_rx_init(void) + */ + ret = nss_lso_rx_stats_register_notifier(&nss_lso_rx_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context\n"); ++ nss_nl_error("Error: retreiving the NSS Context\n"); + genl_unregister_family(&nss_nllso_rx_family); + return false; + } +@@ -159,7 +159,7 @@ bool nss_nllso_rx_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink lso_rx handler\n"); ++ nss_nl_info("Exit NSS netlink lso_rx handler\n"); + + /* + * Unregister the device callback handler for lso_rx +@@ -171,7 +171,7 @@ bool nss_nllso_rx_exit(void) + */ + error = genl_unregister_family(&nss_nllso_rx_family); + if (error) { +- nss_nl_info_always("unable to unregister lso_rx NETLINK family\n"); ++ nss_nl_error("unable to unregister lso_rx NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nlmap_t.c ++++ b/netlink/nss_nlmap_t.c +@@ -127,14 +127,14 @@ bool nss_nlmap_t_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink map_t handler\n"); ++ nss_nl_info("Init NSS netlink map_t handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nlmap_t_family); + if (error) { +- nss_nl_info_always("Error: unable to register map_t family\n"); ++ nss_nl_error("Error: unable to register map_t family\n"); + return false; + } + +@@ -143,7 +143,7 @@ bool nss_nlmap_t_init(void) + */ + ret = nss_map_t_stats_register_notifier(&nss_map_t_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context\n"); ++ nss_nl_error("Error: retreiving the NSS Context\n"); + genl_unregister_family(&nss_nlmap_t_family); + return false; + } +@@ -159,7 +159,7 @@ bool nss_nlmap_t_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink map_t handler\n"); ++ nss_nl_info("Exit NSS netlink map_t handler\n"); + + /* + * Unregister the device callback handler for map_t +@@ -171,7 +171,7 @@ bool nss_nlmap_t_exit(void) + */ + error = genl_unregister_family(&nss_nlmap_t_family); + if (error) { +- nss_nl_info_always("unable to unregister map_t NETLINK family\n"); ++ nss_nl_error("unable to unregister map_t NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nln2h.c ++++ b/netlink/nss_nln2h.c +@@ -126,14 +126,14 @@ bool nss_nln2h_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink n2h handler\n"); ++ nss_nl_info("Init NSS netlink n2h handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nln2h_family); + if (error) { +- nss_nl_info_always("Error: unable to register n2h family\n"); ++ nss_nl_error("Error: unable to register n2h family\n"); + return false; + } + +@@ -142,7 +142,7 @@ bool nss_nln2h_init(void) + */ + ret = nss_n2h_stats_register_notifier(&nss_n2h_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context\n"); ++ nss_nl_error("Error: retreiving the NSS Context\n"); + genl_unregister_family(&nss_nln2h_family); + return false; + } +@@ -158,7 +158,7 @@ bool nss_nln2h_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink n2h handler\n"); ++ nss_nl_info("Exit NSS netlink n2h handler\n"); + + /* + * Unregister the device callback handler for n2h +@@ -170,7 +170,7 @@ bool nss_nln2h_exit(void) + */ + error = genl_unregister_family(&nss_nln2h_family); + if (error) { +- nss_nl_info_always("unable to unregister n2h NETLINK family\n"); ++ nss_nl_error("unable to unregister n2h NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nloam.c ++++ b/netlink/nss_nloam.c +@@ -348,7 +348,7 @@ bool nss_nloam_init(void) + */ + error = genl_register_family(&nss_nloam_family); + if (error != 0) { +- nss_nl_info_always("unable to register OAM family\n"); ++ nss_nl_error("unable to register OAM family\n"); + return false; + } + +@@ -375,7 +375,7 @@ unreg_ops: + */ + bool nss_nloam_exit(void) + { +- nss_nl_info_always("Uninitiallizing the NSS netlink oam handler\n"); ++ nss_nl_info("Disabling NSS netlink oam handler\n"); + + /* + * Unregister the device callback handler for oam +--- a/netlink/nss_nlpppoe.c ++++ b/netlink/nss_nlpppoe.c +@@ -127,14 +127,14 @@ bool nss_nlpppoe_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink pppoe handler\n"); ++ nss_nl_info("Init NSS netlink pppoe handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nlpppoe_family); + if (error) { +- nss_nl_info_always("Error: unable to register pppoe family\n"); ++ nss_nl_error("Error: unable to register pppoe family\n"); + return false; + } + +@@ -143,7 +143,7 @@ bool nss_nlpppoe_init(void) + */ + ret = nss_pppoe_stats_register_notifier(&nss_pppoe_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context\n"); ++ nss_nl_error("Error: retreiving the NSS Context\n"); + genl_unregister_family(&nss_nlpppoe_family); + return false; + } +@@ -159,7 +159,7 @@ bool nss_nlpppoe_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink pppoe handler\n"); ++ nss_nl_info("Exit NSS netlink pppoe handler\n"); + + /* + * Unregister the device callback handler for pppoe +@@ -171,7 +171,7 @@ bool nss_nlpppoe_exit(void) + */ + error = genl_unregister_family(&nss_nlpppoe_family); + if (error) { +- nss_nl_info_always("unable to unregister pppoe NETLINK family\n"); ++ nss_nl_error("unable to unregister pppoe NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nlpptp.c ++++ b/netlink/nss_nlpptp.c +@@ -127,14 +127,14 @@ bool nss_nlpptp_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink pptp handler\n"); ++ nss_nl_info("Init NSS netlink pptp handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nlpptp_family); + if (error) { +- nss_nl_info_always("Error: unable to register pptp family\n"); ++ nss_nl_error("Error: unable to register pptp family\n"); + return false; + } + +@@ -143,7 +143,7 @@ bool nss_nlpptp_init(void) + */ + ret = nss_pptp_stats_register_notifier(&nss_pptp_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context\n"); ++ nss_nl_error("Error: retreiving the NSS Context\n"); + genl_unregister_family(&nss_nlpptp_family); + return false; + } +@@ -159,7 +159,7 @@ bool nss_nlpptp_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink pptp handler\n"); ++ nss_nl_info("Exit NSS netlink pptp handler\n"); + + /* + * Unregister the device callback handler for pptp +@@ -171,7 +171,7 @@ bool nss_nlpptp_exit(void) + */ + error = genl_unregister_family(&nss_nlpptp_family); + if (error) { +- nss_nl_info_always("unable to unregister pptp NETLINK family\n"); ++ nss_nl_error("unable to unregister pptp NETLINK family\n"); + return false; + } + +--- a/netlink/nss_nlqrfs.c ++++ b/netlink/nss_nlqrfs.c +@@ -166,14 +166,14 @@ bool nss_nlqrfs_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink qrfs handler\n"); ++ nss_nl_info("Exit NSS netlink qrfs handler\n"); + + /* + * unregister the ops family + */ + error = genl_unregister_family(&nss_nlqrfs_family); + if (error) { +- nss_nl_info_always("unable to unregister qrfs NETLINK family\n"); ++ nss_nl_error("unable to unregister qrfs NETLINK family\n"); + return false; + } + +@@ -188,14 +188,14 @@ bool nss_nlqrfs_init(void) + { + int error; + +- nss_nl_info_always("Init NSS netlink qrfs handler\n"); ++ nss_nl_info("Init NSS netlink qrfs handler\n"); + + /* + * register Netlink ops with the family + */ + error = genl_register_family(&nss_nlqrfs_family); + if (error) { +- nss_nl_info_always("Error: unable to register qrfs family\n"); ++ nss_nl_error("Error: unable to register qrfs family\n"); + return false; + } + +--- a/netlink/nss_nludp_st.c ++++ b/netlink/nss_nludp_st.c +@@ -1822,14 +1822,14 @@ bool nss_nludp_st_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink udp_st handler\n"); ++ nss_nl_info("Exit NSS netlink udp_st handler\n"); + + /* + * unregister the ops family + */ + error = genl_unregister_family(&nss_nludp_st_family); + if (error) { +- nss_nl_info_always("unable to unregister udp_st NETLINK family\n"); ++ nss_nl_error("unable to unregister udp_st NETLINK family\n"); + return false; + } + +@@ -1844,14 +1844,14 @@ bool nss_nludp_st_init(void) + { + int error; + +- nss_nl_info_always("Init NSS netlink udp_st handler\n"); ++ nss_nl_info("Init NSS netlink udp_st handler\n"); + + /* + * register Netlink ops with the family + */ + error = genl_register_family(&nss_nludp_st_family); + if (error) { +- nss_nl_info_always("Error: unable to register udp_st family\n"); ++ nss_nl_error("Error: unable to register udp_st family\n"); + return false; + } + +--- a/netlink/nss_nlwifili.c ++++ b/netlink/nss_nlwifili.c +@@ -127,14 +127,14 @@ bool nss_nlwifili_init(void) + { + int error,ret; + +- nss_nl_info_always("Init NSS netlink wifili handler\n"); ++ nss_nl_info("Init NSS netlink wifili handler\n"); + + /* + * register NETLINK ops with the family + */ + error = genl_register_family(&nss_nlwifili_family); + if (error) { +- nss_nl_info_always("Error: unable to register wifili family\n"); ++ nss_nl_error("Error: unable to register wifili family\n"); + return false; + } + +@@ -143,7 +143,7 @@ bool nss_nlwifili_init(void) + */ + ret = nss_wifili_stats_register_notifier(&nss_wifili_stats_notifier_nb); + if (ret) { +- nss_nl_info_always("Error: retreiving the NSS Context\n"); ++ nss_nl_error("Error: retreiving the NSS Context\n"); + genl_unregister_family(&nss_nlwifili_family); + return false; + } +@@ -159,7 +159,7 @@ bool nss_nlwifili_exit(void) + { + int error; + +- nss_nl_info_always("Exit NSS netlink wifili handler\n"); ++ nss_nl_info("Exit NSS netlink wifili handler\n"); + + /* + * Unregister the device callback handler for wifili +@@ -171,7 +171,7 @@ bool nss_nlwifili_exit(void) + */ + error = genl_unregister_family(&nss_nlwifili_family); + if (error) { +- nss_nl_info_always("unable to unregister wifili NETLINK family\n"); ++ nss_nl_error("unable to unregister wifili NETLINK family\n"); + return false; + } + diff --git a/qca-nss-clients/patches/0001-kernel-5.15-support-qdisc.patch b/qca-nss-clients/patches/0001-kernel-5.15-support-qdisc.patch new file mode 100644 index 0000000..a7976b8 --- /dev/null +++ b/qca-nss-clients/patches/0001-kernel-5.15-support-qdisc.patch @@ -0,0 +1,153 @@ +--- a/nss_qdisc/igs/nss_mirred.c ++++ b/nss_qdisc/igs/nss_mirred.c +@@ -82,20 +82,24 @@ static const struct nla_policy nss_mirre + * nss_mirred_init() + * Initialize the nss mirred action. + */ +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) + static int nss_mirred_init(struct net *net, struct nlattr *nla, +- struct nlattr *est, struct tc_action *tc_act, int ovr, +- int bind) ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) ++ struct nlattr *est, struct tc_action *tc_act, int ovr, ++ int bind) ++{ ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) ++ struct nlattr *est, struct tc_action **tc_act, int ovr, ++ int bind, bool rtnl_held, struct tcf_proto *tp, ++ u32 flags, struct netlink_ext_ack *extack) + { + #else +-static int nss_mirred_init(struct net *net, struct nlattr *nla, +- struct nlattr *est, struct tc_action **tc_act, int ovr, +- int bind, bool rtnl_held, struct tcf_proto *tp, +- struct netlink_ext_ack *extack) ++ struct nlattr *est, struct tc_action **tc_act, ++ struct tcf_proto *tp, u32 flags, struct netlink_ext_ack *extack) + { ++ bool bind = flags & TCA_ACT_FLAGS_BIND; ++#endif + struct tc_action_net *tn = net_generic(net, nss_mirred_net_id); + u32 index; +-#endif + struct nlattr *arr[TC_NSS_MIRRED_MAX + 1]; + struct tc_nss_mirred *parm; + struct nss_mirred_tcf *act; +@@ -239,8 +243,13 @@ static int nss_mirred_init(struct net *n + } + + if (!ret) { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)) + ret = tcf_idr_create(tn, index, est, tc_act, &nss_mirred_act_ops, + bind, true); ++#else ++ ret = tcf_idr_create(tn, index, est, tc_act, &nss_mirred_act_ops, ++ bind, true, 0); ++#endif + if (ret) { + tcf_idr_cleanup(tn, index); + return ret; +--- a/nss_qdisc/nss_bf.c ++++ b/nss_qdisc/nss_bf.c +@@ -74,7 +74,7 @@ static inline struct nss_bf_class_data * + */ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0)) + static int nss_bf_change_class(struct Qdisc *sch, u32 classid, u32 parentid, +- struct nlattr **tca, unsigned long *arg) ++ struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack) + { + struct netlink_ext_ack *extack = NULL; + #else +@@ -290,7 +290,11 @@ static void nss_bf_destroy_class(struct + * nss_bf_delete_class() + * Detaches a class from operation, but does not destroy it. + */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) ++static int nss_bf_delete_class(struct Qdisc *sch, unsigned long arg, struct netlink_ext_ack *extack) ++#else + static int nss_bf_delete_class(struct Qdisc *sch, unsigned long arg) ++#endif + { + struct nss_bf_sched_data *q = qdisc_priv(sch); + struct nss_bf_class_data *cl = (struct nss_bf_class_data *)arg; +--- a/nss_qdisc/nss_htb.c ++++ b/nss_qdisc/nss_htb.c +@@ -282,7 +282,7 @@ static int nss_htb_ppe_change_class(stru + */ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0)) + static int nss_htb_change_class(struct Qdisc *sch, u32 classid, u32 parentid, +- struct nlattr **tca, unsigned long *arg) ++ struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack) + { + struct netlink_ext_ack *extack = NULL; + #else +@@ -516,7 +516,11 @@ static void nss_htb_destroy_class(struct + * nss_htb_delete_class() + * Detaches a class from operation, but does not destroy it. + */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) ++static int nss_htb_delete_class(struct Qdisc *sch, unsigned long arg, struct netlink_ext_ack *extack) ++#else + static int nss_htb_delete_class(struct Qdisc *sch, unsigned long arg) ++#endif + { + struct nss_htb_sched_data *q = qdisc_priv(sch); + struct nss_htb_class_data *cl = (struct nss_htb_class_data *)arg; +--- a/nss_qdisc/nss_qdisc.c ++++ b/nss_qdisc/nss_qdisc.c +@@ -1140,15 +1140,16 @@ unsigned int nss_qdisc_drop(struct Qdisc + { + struct nss_qdisc *nq = qdisc_priv(sch); + unsigned int ret; ++ struct sk_buff *to_free = qdisc_peek_head(sch); + + if (!nq->is_virtual) { +- ret = __qdisc_queue_drop_head(sch, &sch->q); ++ ret = __qdisc_queue_drop_head(sch, &sch->q, &to_free); + } else { + spin_lock_bh(&nq->bounce_protection_lock); + /* + * This function is safe to call within locks + */ +- ret = __qdisc_queue_drop_head(sch, &sch->q); ++ ret = __qdisc_queue_drop_head(sch, &sch->q, &to_free); + spin_unlock_bh(&nq->bounce_protection_lock); + } + +@@ -1209,10 +1210,10 @@ static bool nss_qdisc_iterate_fl(struct + return 0; + } + +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) +- status = tc_classify(skb, tcf, &res, false); +-#else ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) + status = tcf_classify(skb, tcf, &res, false); ++#else ++ status = tcf_classify(skb, NULL, tcf, &res, false); + #endif + if ((status == TC_ACT_STOLEN) || (status == TC_ACT_QUEUED)) { + return 1; +--- a/nss_qdisc/nss_wrr.c ++++ b/nss_qdisc/nss_wrr.c +@@ -229,7 +229,7 @@ static int nss_wrr_ppe_change_class(stru + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0)) + static int nss_wrr_change_class(struct Qdisc *sch, u32 classid, u32 parentid, +- struct nlattr **tca, unsigned long *arg) ++ struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack) + { + struct netlink_ext_ack *extack = NULL; + #else +@@ -400,7 +400,11 @@ failure: + return -EINVAL; + } + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) ++static int nss_wrr_delete_class(struct Qdisc *sch, unsigned long arg, struct netlink_ext_ack *extack) ++#else + static int nss_wrr_delete_class(struct Qdisc *sch, unsigned long arg) ++#endif + { + struct nss_wrr_sched_data *q = qdisc_priv(sch); + struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)arg; diff --git a/qca-nss-clients/patches/0002-kernel-5.4-support-gre.patch b/qca-nss-clients/patches/0002-kernel-5.4-support-gre.patch new file mode 100644 index 0000000..7ed66bd --- /dev/null +++ b/qca-nss-clients/patches/0002-kernel-5.4-support-gre.patch @@ -0,0 +1,31 @@ +--- a/gre/nss_connmgr_gre_v6.c ++++ b/gre/nss_connmgr_gre_v6.c +@@ -95,7 +95,8 @@ static int nss_connmgr_gre_v6_get_mac_ad + /* + * Find src MAC address + */ +- local_dev = (struct net_device *)ipv6_dev_find(&init_net, &src_addr, 1); ++ local_dev = NULL; ++ local_dev = (struct net_device *)ipv6_dev_find(&init_net, &src_addr, local_dev); + if (!local_dev) { + nss_connmgr_gre_warning("Unable to find local dev for %pI6", src_ip); + return GRE_ERR_NO_LOCAL_NETDEV; +--- a/gre/test/nss_connmgr_gre_test.c ++++ b/gre/test/nss_connmgr_gre_test.c +@@ -229,10 +229,12 @@ static int nss_connmgr_gre_test_open_pro + /* + * Proc ops + */ +-static const struct file_operations nss_connmgr_gre_test_proc_ops = { +- .open = nss_connmgr_gre_test_open_proc, +- .write = nss_connmgr_gre_test_write_proc, +- .read = seq_read, ++static const struct proc_ops nss_connmgr_gre_test_proc_ops = { ++ .proc_open = nss_connmgr_gre_test_open_proc, ++ .proc_read = seq_read, ++ .proc_lseek = seq_lseek, ++ .proc_release = single_release, ++ .proc_write = nss_connmgr_gre_test_write_proc, + }; + + /* diff --git a/qca-nss-clients/patches/0003-kernel-5.4-support-ipsec.patch b/qca-nss-clients/patches/0003-kernel-5.4-support-ipsec.patch new file mode 100644 index 0000000..de43b4d --- /dev/null +++ b/qca-nss-clients/patches/0003-kernel-5.4-support-ipsec.patch @@ -0,0 +1,29 @@ +--- a/ipsecmgr/v1.0/nss_ipsecmgr.c ++++ b/ipsecmgr/v1.0/nss_ipsecmgr.c +@@ -377,7 +377,7 @@ free: + * nss_ipsecmgr_tunnel_stats() + * get tunnel statistics + */ +-static struct rtnl_link_stats64 *nss_ipsecmgr_tunnel_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) ++void nss_ipsecmgr_tunnel_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) + { + struct nss_ipsecmgr_priv *priv = netdev_priv(dev); + +@@ -389,8 +389,6 @@ static struct rtnl_link_stats64 *nss_ips + read_lock_bh(&ipsecmgr_ctx->lock); + memcpy(stats, &priv->stats, sizeof(struct rtnl_link_stats64)); + read_unlock_bh(&ipsecmgr_ctx->lock); +- +- return stats; + } + + /* +@@ -442,7 +440,7 @@ static void nss_ipsecmgr_tunnel_setup(st + dev->header_ops = NULL; + dev->netdev_ops = &nss_ipsecmgr_tunnel_ops; + +- dev->destructor = nss_ipsecmgr_tunnel_free; ++ dev->priv_destructor = nss_ipsecmgr_tunnel_free; + + /* + * get the MAC address from the ethernet device diff --git a/qca-nss-clients/patches/0004-kernel-5.4-support-dtls.patch b/qca-nss-clients/patches/0004-kernel-5.4-support-dtls.patch new file mode 100644 index 0000000..ae9c914 --- /dev/null +++ b/qca-nss-clients/patches/0004-kernel-5.4-support-dtls.patch @@ -0,0 +1,11 @@ +--- a/dtls/v1.0/nss_connmgr_dtls_netdev.c ++++ b/dtls/v1.0/nss_connmgr_dtls_netdev.c +@@ -160,7 +160,7 @@ static void nss_dtlsmgr_dev_setup(struct + dev->ethtool_ops = NULL; + dev->header_ops = NULL; + dev->netdev_ops = &nss_dtlsmgr_session_ops; +- dev->destructor = NULL; ++ dev->priv_destructor = NULL; + + memcpy(dev->dev_addr, "\xaa\xbb\xcc\xdd\xee\xff", dev->addr_len); + memset(dev->broadcast, 0xff, dev->addr_len); diff --git a/qca-nss-clients/patches/0005-vlanmgr-fix-compile-error.patch b/qca-nss-clients/patches/0005-vlanmgr-fix-compile-error.patch new file mode 100644 index 0000000..870845c --- /dev/null +++ b/qca-nss-clients/patches/0005-vlanmgr-fix-compile-error.patch @@ -0,0 +1,59 @@ +--- a/vlan/nss_vlan_mgr.c ++++ b/vlan/nss_vlan_mgr.c +@@ -688,8 +688,10 @@ detach_vsi: + */ + static void nss_vlan_mgr_instance_free(struct nss_vlan_pvt *v) + { ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT + int32_t i; + int ret = 0; ++#endif + + #ifdef NSS_VLAN_MGR_PPE_SUPPORT + if (v->ppe_vsi) { +@@ -999,8 +1001,11 @@ static int nss_vlan_mgr_register_event(s + int ret; + #endif + uint32_t vlan_tag; ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT + struct net_device *slave; +- int32_t port, port_if; ++ int32_t port; ++#endif ++ int32_t port_if; + struct vlan_dev_priv *vlan; + struct net_device *real_dev; + bool is_bond_master = false; +@@ -1393,8 +1398,10 @@ return_with_error: + int nss_vlan_mgr_join_bridge(struct net_device *dev, uint32_t bridge_vsi) + { + struct nss_vlan_pvt *v = nss_vlan_mgr_instance_find_and_ref(dev); ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT + struct net_device *real_dev; + int ret; ++#endif + + if (!v) + return 0; +@@ -1454,8 +1461,10 @@ EXPORT_SYMBOL(nss_vlan_mgr_join_bridge); + int nss_vlan_mgr_leave_bridge(struct net_device *dev, uint32_t bridge_vsi) + { + struct nss_vlan_pvt *v = nss_vlan_mgr_instance_find_and_ref(dev); ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT + struct net_device *real_dev; + int ret; ++#endif + + if (!v) + return 0; +--- a/vlan/Makefile ++++ b/vlan/Makefile +@@ -8,7 +8,7 @@ ifeq ($(SoC),$(filter $(SoC),ipq807x ipq + ccflags-y += -DNSS_VLAN_MGR_PPE_SUPPORT + endif + +-ccflags-y += -DNSS_VLAN_MGR_DEBUG_LEVEL=0 ++ccflags-y += -DNSS_VLAN_MGR_DEBUG_LEVEL=4 + ccflags-y += -Wall -Werror + + ifneq (,$(filter $(CONFIG_BONDING),y m)) diff --git a/qca-nss-clients/patches/0006-match-fix-compile-error.patch b/qca-nss-clients/patches/0006-match-fix-compile-error.patch new file mode 100644 index 0000000..ad3ad0b --- /dev/null +++ b/qca-nss-clients/patches/0006-match-fix-compile-error.patch @@ -0,0 +1,25 @@ +--- a/match/nss_match_priv.h ++++ b/match/nss_match_priv.h +@@ -29,19 +29,19 @@ + /* + * Statically compile messages at different levels + */ +-#if (NSS_match_DEBUG_LEVEL < 2) ++#if (NSS_MATCH_DEBUG_LEVEL < 2) + #define nss_match_warn(s, ...) + #else + #define nss_match_warn(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) + #endif + +-#if (NSS_match_DEBUG_LEVEL < 3) ++#if (NSS_MATCH_DEBUG_LEVEL < 3) + #define nss_match_info(s, ...) + #else + #define nss_match_info(s, ...) pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) + #endif + +-#if (NSS_match_DEBUG_LEVEL < 4) ++#if (NSS_MATCH_DEBUG_LEVEL < 4) + #define nss_match_trace(s, ...) + #else + #define nss_match_trace(s, ...) pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) diff --git a/qca-nss-clients/patches/0007-bridge-fix-compile-error.patch b/qca-nss-clients/patches/0007-bridge-fix-compile-error.patch new file mode 100644 index 0000000..539ff68 --- /dev/null +++ b/qca-nss-clients/patches/0007-bridge-fix-compile-error.patch @@ -0,0 +1,29 @@ +--- a/bridge/nss_bridge_mgr.c ++++ b/bridge/nss_bridge_mgr.c +@@ -1098,8 +1098,10 @@ int nss_bridge_mgr_register_br(struct ne + */ + b_pvt->ifnum = ifnum; + b_pvt->mtu = dev->mtu; ++#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT) + b_pvt->wan_if_num = -1; + b_pvt->wan_if_enabled = false; ++#endif + ether_addr_copy(b_pvt->dev_addr, dev->dev_addr); + spin_lock(&br_mgr_ctx.lock); + list_add(&b_pvt->list, &br_mgr_ctx.list); +@@ -1165,6 +1167,7 @@ static int nss_bridge_mgr_bond_slave_cha + return NOTIFY_DONE; + } + ++#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT) + /* + * Add or remove the slave based based on linking event + */ +@@ -1179,6 +1182,7 @@ static int nss_bridge_mgr_bond_slave_cha + cu_info->upper_dev->name, master->name); + } + } ++#endif + + return NOTIFY_DONE; + } diff --git a/qca-nss-clients/patches/0008-profiler-fix-compile-error.patch b/qca-nss-clients/patches/0008-profiler-fix-compile-error.patch new file mode 100644 index 0000000..8b6d92c --- /dev/null +++ b/qca-nss-clients/patches/0008-profiler-fix-compile-error.patch @@ -0,0 +1,61 @@ +--- a/profiler/profile.c ++++ b/profiler/profile.c +@@ -31,6 +31,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -937,12 +938,26 @@ static ssize_t debug_if(struct file *fil + return count; + } + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0) ++#define HAVE_PROC_OPS ++#endif ++ ++#ifdef HAVE_PROC_OPS ++static const struct proc_ops profile_fops = { ++ .proc_open = profile_open, ++ .proc_read = profile_read, ++ .proc_lseek = seq_lseek, ++ .proc_release = profile_release, ++ .proc_write = debug_if, ++}; ++#else + static const struct file_operations profile_fops = { + .open = profile_open, + .read = profile_read, + .release = profile_release, + .write = debug_if, + }; ++#endif + + /* + * showing sample status on Linux console +@@ -971,6 +986,15 @@ static ssize_t profile_rate_write(struct + return 0; + } + ++#ifdef HAVE_PROC_OPS ++static const struct proc_ops profile_rate_fops = { ++ .proc_open = profile_rate_open, ++ .proc_read = seq_read, ++ .proc_lseek = seq_lseek, ++ .proc_release = single_release, ++ .proc_write = profile_rate_write, ++}; ++#else + static const struct file_operations profile_rate_fops = { + .open = profile_rate_open, + .read = seq_read, +@@ -978,6 +1002,7 @@ static const struct file_operations prof + .release = single_release, + .write = profile_rate_write, + }; ++#endif + + /* + * hexdump diff --git a/qca-nss-clients/patches/0010-fix-portifmgr.patch b/qca-nss-clients/patches/0010-fix-portifmgr.patch new file mode 100644 index 0000000..343f17b --- /dev/null +++ b/qca-nss-clients/patches/0010-fix-portifmgr.patch @@ -0,0 +1,35 @@ +--- a/portifmgr/nss_portifmgr.c ++++ b/portifmgr/nss_portifmgr.c +@@ -187,16 +187,20 @@ drop: + } + + /* +- * nss_portifmgr_get_stats() ++ * nss_portifmgr_get_stats64() + * Netdev get stats function to get port stats + */ +-static struct rtnl_link_stats64 *nss_portifmgr_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) ++/* ++ * nss_nlgre_redir_cmn_dev_stats64 ++ * Report packet statistics to linux ++ */ ++static void nss_portifmgr_get_stats64(struct net_device *dev, ++ struct rtnl_link_stats64 *stats) + { + struct nss_portifmgr_priv *priv = (struct nss_portifmgr_priv *)netdev_priv(dev); + BUG_ON(priv == NULL); + + nss_portid_get_stats(priv->if_num, stats); +- return stats; + } + + /* +@@ -225,7 +229,7 @@ static const struct net_device_ops nss_p + .ndo_start_xmit = nss_portifmgr_start_xmit, + .ndo_set_mac_address = eth_mac_addr, + .ndo_change_mtu = nss_portifmgr_change_mtu, +- .ndo_get_stats64 = nss_portifmgr_get_stats, ++ .ndo_get_stats64 = nss_portifmgr_get_stats64, + }; + + /* diff --git a/qca-nss-clients/patches/0011-dtlsmgr-fix-SHA-header-include-in-5.15.patch b/qca-nss-clients/patches/0011-dtlsmgr-fix-SHA-header-include-in-5.15.patch new file mode 100644 index 0000000..a095a53 --- /dev/null +++ b/qca-nss-clients/patches/0011-dtlsmgr-fix-SHA-header-include-in-5.15.patch @@ -0,0 +1,48 @@ +--- a/dtls/v2.0/nss_dtlsmgr.c ++++ b/dtls/v2.0/nss_dtlsmgr.c +@@ -38,7 +38,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + #include + #include + +--- a/dtls/v2.0/nss_dtlsmgr_ctx.c ++++ b/dtls/v2.0/nss_dtlsmgr_ctx.c +@@ -40,7 +40,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + #include + #include + +--- a/dtls/v2.0/nss_dtlsmgr_ctx_dev.c ++++ b/dtls/v2.0/nss_dtlsmgr_ctx_dev.c +@@ -36,7 +36,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + + #include + #include diff --git a/qca-nss-clients/patches/0012-dtlsmgr-fix-debug-print-in-5.15.patch b/qca-nss-clients/patches/0012-dtlsmgr-fix-debug-print-in-5.15.patch new file mode 100644 index 0000000..89936db --- /dev/null +++ b/qca-nss-clients/patches/0012-dtlsmgr-fix-debug-print-in-5.15.patch @@ -0,0 +1,36 @@ +--- a/dtls/v2.0/nss_dtlsmgr_private.h ++++ b/dtls/v2.0/nss_dtlsmgr_private.h +@@ -36,9 +36,9 @@ + /* + * Compile messages for dynamic enable/disable + */ +-#define nss_dtlsmgr_warn(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) +-#define nss_dtlsmgr_info(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) +-#define nss_dtlsmgr_trace(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) ++#define nss_dtlsmgr_warn(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); ++#define nss_dtlsmgr_info(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); ++#define nss_dtlsmgr_trace(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); + #else + + /* +@@ -46,17 +46,17 @@ + */ + #define nss_dtlsmgr_warn(s, ...) { \ + if (NSS_DTLSMGR_DEBUG_LEVEL > NSS_DTLSMGR_DEBUG_LEVEL_ERROR) \ +- pr_warn("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) \ ++ pr_warn("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); \ + } + + #define nss_dtlsmgr_info(s, ...) { \ + if (NSS_DTLSMGR_DEBUG_LEVEL > NSS_DTLSMGR_DEBUG_LEVEL_WARN) \ +- pr_notice("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) \ ++ pr_notice("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); \ + } + + #define nss_dtlsmgr_trace(s, ...) { \ + if (NSS_DTLSMGR_DEBUG_LEVEL > NSS_DTLSMGR_DEBUG_LEVEL_INFO) \ +- pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) \ ++ pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); \ + } + + #endif /* CONFIG_DYNAMIC_DEBUG */ diff --git a/qca-nss-clients/patches/0013-tlsmgr-fix-SHA-header-include-in-5.15.patch b/qca-nss-clients/patches/0013-tlsmgr-fix-SHA-header-include-in-5.15.patch new file mode 100644 index 0000000..f3cee73 --- /dev/null +++ b/qca-nss-clients/patches/0013-tlsmgr-fix-SHA-header-include-in-5.15.patch @@ -0,0 +1,32 @@ +--- a/tls/nss_tlsmgr_crypto.c ++++ b/tls/nss_tlsmgr_crypto.c +@@ -41,7 +41,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + #include + #include + #include +--- a/tls/nss_tlsmgr_tun.c ++++ b/tls/nss_tlsmgr_tun.c +@@ -35,7 +35,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + + #include + #include diff --git a/qca-nss-clients/patches/0014-ovpnmgr-fix-SHA-header-include-in-5.15.patch b/qca-nss-clients/patches/0014-ovpnmgr-fix-SHA-header-include-in-5.15.patch new file mode 100644 index 0000000..0b8cd17 --- /dev/null +++ b/qca-nss-clients/patches/0014-ovpnmgr-fix-SHA-header-include-in-5.15.patch @@ -0,0 +1,32 @@ +--- a/openvpn/src/nss_ovpnmgr_crypto.c ++++ b/openvpn/src/nss_ovpnmgr_crypto.c +@@ -28,7 +28,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + #include + + #include +--- a/openvpn/src/nss_ovpnmgr_route.c ++++ b/openvpn/src/nss_ovpnmgr_route.c +@@ -34,7 +34,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + #include + + #include diff --git a/qca-nss-clients/patches/0015-tunipip6-fix-compile-error-in-5.15.patch b/qca-nss-clients/patches/0015-tunipip6-fix-compile-error-in-5.15.patch new file mode 100644 index 0000000..b9d6c2e --- /dev/null +++ b/qca-nss-clients/patches/0015-tunipip6-fix-compile-error-in-5.15.patch @@ -0,0 +1,11 @@ +--- a/tunipip6/nss_connmgr_tunipip6.c ++++ b/tunipip6/nss_connmgr_tunipip6.c +@@ -258,7 +258,7 @@ static void nss_tunipip6_decap_exception + struct iphdr *iph; + struct rtable *rt; + int cpu; +- int8_t ver = skb->data[0] >> 4; ++ __attribute__((unused)) int8_t ver = skb->data[0] >> 4; + + nss_tunipip6_trace("%px: received - %d bytes name %s ver %x\n", + dev, skb->len, dev->name, ver); diff --git a/qca-nss-clients/patches/0016-vxlanmgr-fix-compile-error-in-5.15.patch b/qca-nss-clients/patches/0016-vxlanmgr-fix-compile-error-in-5.15.patch new file mode 100644 index 0000000..80173f8 --- /dev/null +++ b/qca-nss-clients/patches/0016-vxlanmgr-fix-compile-error-in-5.15.patch @@ -0,0 +1,11 @@ +--- a/vxlanmgr/nss_vxlanmgr.c ++++ b/vxlanmgr/nss_vxlanmgr.c +@@ -84,7 +84,7 @@ int32_t nss_vxlanmgr_bind_ipsec_by_ip(un + { + int32_t ipsec_if_num; + nss_vxlanmgr_get_ipsec_if_num_by_ip_callback_t ipsec_cb; +- struct nss_ctx_instance *nss_ctx = nss_vxlan_get_ctx(); ++ __attribute__((unused)) struct nss_ctx_instance *nss_ctx = nss_vxlan_get_ctx(); + + /* + * Check if the VxLAN interface is applied over an IPsec interface by querying the IPsec. diff --git a/qca-nss-clients/patches/0017-tlsmgr-fix-debug-print-in-5.15.patch b/qca-nss-clients/patches/0017-tlsmgr-fix-debug-print-in-5.15.patch new file mode 100644 index 0000000..4fbdecb --- /dev/null +++ b/qca-nss-clients/patches/0017-tlsmgr-fix-debug-print-in-5.15.patch @@ -0,0 +1,34 @@ +--- a/tls/nss_tlsmgr_priv.h ++++ b/tls/nss_tlsmgr_priv.h +@@ -28,7 +28,7 @@ + #define NSS_TLSMGR_DEBUG_LEVEL_INFO 3 + #define NSS_TLSMGR_DEBUG_LEVEL_TRACE 4 + +-#define nss_tlsmgr_info_always(s, ...) pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) ++#define nss_tlsmgr_info_always(s, ...) pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); + + #define nss_tlsmgr_error(s, ...) do { \ + if (net_ratelimit()) { \ +@@ -43,18 +43,18 @@ + } while (0) + + #if defined(CONFIG_DYNAMIC_DEBUG) +-#define nss_tlsmgr_info(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) +-#define nss_tlsmgr_trace(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) ++#define nss_tlsmgr_info(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); ++#define nss_tlsmgr_trace(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); + #else + + #define nss_tlsmgr_info(s, ...) { \ + if (NSS_TLSMGR_DEBUG_LEVEL > NSS_TLSMGR_DEBUG_LEVEL_WARN) \ +- pr_notice("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) \ ++ pr_notice("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); \ + } + + #define nss_tlsmgr_trace(s, ...) { \ + if (NSS_TLSMGR_DEBUG_LEVEL > NSS_TLSMGR_DEBUG_LEVEL_INFO) \ +- pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__) \ ++ pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__); \ + } + + #endif /* CONFIG_DYNAMIC_DEBUG */ diff --git a/qca-nss-clients/patches/0018-kernel-6.1-support.patch b/qca-nss-clients/patches/0018-kernel-6.1-support.patch new file mode 100644 index 0000000..155ee4f --- /dev/null +++ b/qca-nss-clients/patches/0018-kernel-6.1-support.patch @@ -0,0 +1,277 @@ +--- a/gre/test/nss_connmgr_gre_test.c ++++ b/gre/test/nss_connmgr_gre_test.c +@@ -223,7 +223,7 @@ static int nss_connmgr_gre_test_show_pro + */ + static int nss_connmgr_gre_test_open_proc(struct inode *inode, struct file *filp) + { +- return single_open(filp, nss_connmgr_gre_test_show_proc, PDE_DATA(inode)); ++ return single_open(filp, nss_connmgr_gre_test_show_proc, pde_data(inode)); + } + + /* +--- a/gre/nss_connmgr_gre.c ++++ b/gre/nss_connmgr_gre.c +@@ -279,10 +279,10 @@ static struct rtnl_link_stats64 *nss_con + #else + start = u64_stats_fetch_begin_irq(&tstats->syncp); + #endif +- rx_packets = tstats->rx_packets; +- tx_packets = tstats->tx_packets; +- rx_bytes = tstats->rx_bytes; +- tx_bytes = tstats->tx_bytes; ++ rx_packets = u64_stats_read(&tstats->rx_packets); ++ tx_packets = u64_stats_read(&tstats->tx_packets); ++ rx_bytes = u64_stats_read(&tstats->rx_bytes); ++ tx_bytes = u64_stats_read(&tstats->tx_bytes); + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) + } while (u64_stats_fetch_retry_bh(&tstats->syncp, start)); + #else +@@ -697,11 +697,11 @@ static void nss_connmgr_gre_event_receiv + tstats = this_cpu_ptr(dev->tstats); + u64_stats_update_begin(&tstats->syncp); + if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER) { +- tstats->tx_packets += stats->tx_packets; +- tstats->tx_bytes += stats->tx_bytes; ++ u64_stats_add(&tstats->tx_packets, stats->tx_packets); ++ u64_stats_add(&tstats->tx_bytes, stats->tx_bytes); + } else if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER) { +- tstats->rx_packets += stats->rx_packets; +- tstats->rx_bytes += stats->rx_bytes; ++ u64_stats_add(&tstats->rx_packets, stats->rx_packets); ++ u64_stats_add(&tstats->rx_bytes, stats->rx_bytes); + } + u64_stats_update_end(&tstats->syncp); + dev->stats.rx_dropped += nss_cmn_rx_dropped_sum(stats); +--- a/tunipip6/nss_connmgr_tunipip6.c ++++ b/tunipip6/nss_connmgr_tunipip6.c +@@ -354,11 +354,11 @@ static void nss_tunipip6_update_dev_stat + + memset(&stats, 0, sizeof(stats)); + if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER) { +- stats.tx_packets = sync_stats->node_stats.tx_packets; +- stats.tx_bytes = sync_stats->node_stats.tx_bytes; ++ u64_stats_set(&stats.tx_packets, sync_stats->node_stats.tx_packets); ++ u64_stats_set(&stats.tx_bytes, sync_stats->node_stats.tx_bytes); + } else if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER) { +- stats.rx_packets = sync_stats->node_stats.rx_packets; +- stats.rx_bytes = sync_stats->node_stats.rx_bytes; ++ u64_stats_set(&stats.rx_packets, sync_stats->node_stats.rx_packets); ++ u64_stats_set(&stats.rx_bytes, sync_stats->node_stats.rx_bytes); + } else { + nss_tunipip6_warning("%px: Invalid interface type received from NSS\n", dev); + return; +--- a/nss_qdisc/igs/nss_mirred.c ++++ b/nss_qdisc/igs/nss_mirred.c +@@ -317,7 +317,7 @@ static int nss_mirred_act(struct sk_buff + * Update the last use of action. + */ + tcf_lastuse_update(&act->tcf_tm); +- bstats_cpu_update(this_cpu_ptr(act->common.cpu_bstats), skb); ++ bstats_update(this_cpu_ptr(act->common.cpu_bstats), skb); + + rcu_read_lock(); + retval = READ_ONCE(act->tcf_action); +--- a/nss_qdisc/nss_qdisc.h ++++ b/nss_qdisc/nss_qdisc.h +@@ -217,7 +217,7 @@ struct nss_qdisc { + /* Shaper configure callback for reading shaper specific + * responses (e.g. memory size). + */ +- struct gnet_stats_basic_packed bstats; /* Basic class statistics */ ++ struct gnet_stats_basic_sync bstats; /* Basic class statistics */ + struct gnet_stats_queue qstats; /* Qstats for use by classes */ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0)) + atomic_t refcnt; /* Reference count for class use */ +@@ -464,7 +464,7 @@ extern int nss_qdisc_init(struct Qdisc * + * Wrapper around gnet_stats_copy_basic() + */ + extern int nss_qdisc_gnet_stats_copy_basic(struct Qdisc *sch, +- struct gnet_dump *d, struct gnet_stats_basic_packed *b); ++ struct gnet_dump *d, struct gnet_stats_basic_sync *b); + + /* + * nss_qdisc_gnet_stats_copy_queue() +--- a/nss_qdisc/igs/nss_ifb.c ++++ b/nss_qdisc/igs/nss_ifb.c +@@ -544,8 +544,10 @@ static void nss_ifb_update_dev_stats(str + * post shaping. Therefore IFB interface's stats should be updated + * with NSS firmware's IFB TX stats only. + */ +- stats.rx_packets = stats.tx_packets = node_stats->tx_packets; +- stats.rx_bytes = stats.tx_bytes = node_stats->tx_bytes; ++ u64_stats_set(&stats.rx_packets, node_stats->tx_packets); ++ u64_stats_set(&stats.tx_packets, node_stats->tx_packets); ++ u64_stats_set(&stats.rx_bytes, node_stats->tx_bytes); ++ u64_stats_set(&stats.tx_bytes, node_stats->tx_bytes); + dev->stats.rx_dropped = dev->stats.tx_dropped += sync_stats->igs_stats.tx_dropped; + u64_stats_update_end(&stats.syncp); + +--- a/nss_qdisc/nss_qdisc.c ++++ b/nss_qdisc/nss_qdisc.c +@@ -2189,7 +2189,7 @@ int __nss_qdisc_init(struct Qdisc *sch, + * This is to prevent mixing NSS and PPE qdisc with linux qdisc. + */ + if ((parent != TC_H_ROOT) && (root->ops->owner != THIS_MODULE)) { +- nss_qdisc_warning("NSS qdisc %px (type %d) used along with non-nss qdiscs," ++ nss_qdisc_info("NSS qdisc %px (type %d) used along with non-nss qdiscs," + " or the interface is currently down", nq->qdisc, nq->type); + } + +@@ -2606,12 +2606,14 @@ int nss_qdisc_init(struct Qdisc *sch, st + * Wrapper around gnet_stats_copy_basic() + */ + int nss_qdisc_gnet_stats_copy_basic(struct Qdisc *sch, struct gnet_dump *d, +- struct gnet_stats_basic_packed *b) ++ struct gnet_stats_basic_sync *b) + { + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 18, 0)) + return gnet_stats_copy_basic(d, b); + #elif (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0)) + return gnet_stats_copy_basic(d, NULL, b); ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 16, 0)) ++ return gnet_stats_copy_basic(d, NULL, b, true); + #else + return gnet_stats_copy_basic(qdisc_root_sleeping_running(sch), d, NULL, b); + #endif +--- a/nss_qdisc/nss_qdisc_stats.c ++++ b/nss_qdisc/nss_qdisc_stats.c +@@ -161,7 +161,7 @@ static void nss_qdisc_stats_process_node + { + struct Qdisc *qdisc; + struct nss_qdisc *nq; +- struct gnet_stats_basic_packed *bstats; ++ struct gnet_stats_basic_sync *bstats; + struct gnet_stats_queue *qstats; + uint32_t qos_tag = response->qos_tag; + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0)) +@@ -215,8 +215,8 @@ static void nss_qdisc_stats_process_node + * Update qdisc->bstats + */ + spin_lock_bh(&nq->lock); +- bstats->bytes += (__u64)response->sn_stats.delta.dequeued_bytes; +- bstats->packets += response->sn_stats.delta.dequeued_packets; ++ u64_stats_add(&bstats->bytes, (__u64)response->sn_stats.delta.dequeued_bytes); ++ u64_stats_add(&bstats->packets, response->sn_stats.delta.dequeued_packets); + + /* + * Update qdisc->qstats +--- a/vxlanmgr/nss_vxlanmgr_tunnel.c ++++ b/vxlanmgr/nss_vxlanmgr_tunnel.c +@@ -489,8 +489,8 @@ static void nss_vxlanmgr_tunnel_inner_st + + tstats = this_cpu_ptr(dev->tstats); + u64_stats_update_begin(&tstats->syncp); +- tstats->tx_packets += stats->node_stats.tx_packets; +- tstats->tx_bytes += stats->node_stats.tx_bytes; ++ u64_stats_add(&tstats->tx_packets, stats->node_stats.tx_packets); ++ u64_stats_add(&tstats->tx_bytes, stats->node_stats.tx_bytes); + u64_stats_update_end(&tstats->syncp); + netdev_stats->tx_dropped += dropped; + } +@@ -526,8 +526,8 @@ static void nss_vxlanmgr_tunnel_outer_st + + tstats = this_cpu_ptr(dev->tstats); + u64_stats_update_begin(&tstats->syncp); +- tstats->rx_packets += stats->node_stats.tx_packets; +- tstats->rx_bytes += stats->node_stats.tx_bytes; ++ u64_stats_add(&tstats->rx_packets, stats->node_stats.tx_packets); ++ u64_stats_add(&tstats->rx_bytes, stats->node_stats.tx_bytes); + u64_stats_update_end(&tstats->syncp); + netdev_stats->rx_dropped += dropped; + dev_put(dev); +--- a/pvxlanmgr/nss_pvxlanmgr.c ++++ b/pvxlanmgr/nss_pvxlanmgr.c +@@ -177,7 +177,7 @@ static struct rtnl_link_stats64 *nss_pvx + * Netdev seems to be incrementing rx_dropped because we don't give IP header. + * So reset it as it's of no use for us. + */ +- atomic_long_set(&dev->rx_dropped, 0); ++ atomic_long_set(&(dev)->stats.__rx_dropped, 0); + priv = netdev_priv(dev); + memset(stats, 0, sizeof(struct rtnl_link_stats64)); + memcpy(stats, &priv->stats, sizeof(struct rtnl_link_stats64)); +@@ -305,9 +305,9 @@ static void nss_pvxlanmgr_dummy_netdev_s + dev->priv_destructor = NULL; + #endif + +- memcpy(dev->dev_addr, "\x00\x00\x00\x00\x00\x00", dev->addr_len); +- memset(dev->broadcast, 0xff, dev->addr_len); +- memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); ++ const uint8_t mac_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; ++ eth_hw_addr_set(dev, mac_addr); ++ eth_broadcast_addr(dev->broadcast); + } + + /* +--- a/clmapmgr/nss_clmapmgr.c ++++ b/clmapmgr/nss_clmapmgr.c +@@ -103,7 +103,7 @@ static struct rtnl_link_stats64 *nss_clm + * Netdev seems to be incrementing rx_dropped because we don't give IP header. + * So reset it as it's of no use for us. + */ +- atomic_long_set(&dev->rx_dropped, 0); ++ atomic_long_set(&(dev)->stats.__rx_dropped, 0); + priv = netdev_priv(dev); + memset(stats, 0, sizeof(struct rtnl_link_stats64)); + memcpy(stats, &priv->stats, sizeof(struct rtnl_link_stats64)); +--- a/tls/nss_tlsmgr_tun.c ++++ b/tls/nss_tlsmgr_tun.c +@@ -185,7 +185,7 @@ static void nss_tlsmgr_tun_setup(struct + /* + * Get the MAC address from the ethernet device + */ +- random_ether_addr(dev->dev_addr); ++ eth_random_addr((u8 *) dev->dev_addr); + + memset(dev->broadcast, 0xff, dev->addr_len); + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); +--- a/netlink/nss_nlgre_redir_cmn.c ++++ b/netlink/nss_nlgre_redir_cmn.c +@@ -384,7 +384,7 @@ static int nss_nlgre_redir_cmn_set_mac_a + return -EINVAL; + } + +- memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); ++ memcpy((void *) dev->dev_addr, addr->sa_data, ETH_ALEN); + return 0; + } + +--- a/nss_connmgr_tun6rd.c ++++ b/nss_connmgr_tun6rd.c +@@ -101,10 +101,10 @@ static void nss_tun6rd_update_dev_stats( + + u64_stats_init(&stats.syncp); + u64_stats_update_begin(&stats.syncp); +- stats.rx_packets = sync_stats->node_stats.rx_packets; +- stats.rx_bytes = sync_stats->node_stats.rx_bytes; +- stats.tx_packets = sync_stats->node_stats.tx_packets; +- stats.tx_bytes = sync_stats->node_stats.tx_bytes; ++ u64_stats_set(&stats.rx_packets, sync_stats->node_stats.rx_packets); ++ u64_stats_set(&stats.rx_bytes, sync_stats->node_stats.rx_bytes); ++ u64_stats_set(&stats.tx_packets, sync_stats->node_stats.tx_packets); ++ u64_stats_set(&stats.tx_bytes, sync_stats->node_stats.tx_bytes); + u64_stats_update_end(&stats.syncp); + #else + struct nss_tun6rd_stats stats; +--- a/ipsecmgr/v1.0/nss_ipsecmgr.c ++++ b/ipsecmgr/v1.0/nss_ipsecmgr.c +@@ -445,7 +445,7 @@ static void nss_ipsecmgr_tunnel_setup(st + /* + * get the MAC address from the ethernet device + */ +- random_ether_addr(dev->dev_addr); ++ eth_random_addr((u8 *) dev->dev_addr); + + memset(dev->broadcast, 0xff, dev->addr_len); + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); +--- a/ipsecmgr/v2.0/nss_ipsecmgr_tunnel.c ++++ b/ipsecmgr/v2.0/nss_ipsecmgr_tunnel.c +@@ -445,7 +445,7 @@ static void nss_ipsecmgr_tunnel_setup(st + /* + * Get the MAC address from the ethernet device + */ +- random_ether_addr(dev->dev_addr); ++ eth_random_addr((u8 *) dev->dev_addr); + + memset(dev->broadcast, 0xff, dev->addr_len); + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); diff --git a/qca-nss-clients/patches/0019-wifi-meshmgr-fix-uninitialized-and-implicit.patch b/qca-nss-clients/patches/0019-wifi-meshmgr-fix-uninitialized-and-implicit.patch new file mode 100644 index 0000000..b1efb81 --- /dev/null +++ b/qca-nss-clients/patches/0019-wifi-meshmgr-fix-uninitialized-and-implicit.patch @@ -0,0 +1,238 @@ +--- a/wifi_meshmgr/nss_wifi_meshmgr.c ++++ b/wifi_meshmgr/nss_wifi_meshmgr.c +@@ -49,7 +49,7 @@ static bool nss_wifi_meshmgr_verify_if_n + */ + static nss_wifi_meshmgr_status_t nss_wifi_meshmgr_tx_msg(struct nss_wifi_mesh_msg *msg) + { +- return nss_wifi_mesh_tx_msg(wmgr_ctx.nss_ctx, msg); ++ return (nss_wifi_meshmgr_status_t)nss_wifi_mesh_tx_msg(wmgr_ctx.nss_ctx, msg); + } + + /* +@@ -126,7 +126,7 @@ static void nss_wifi_meshmgr_cleanup(str + * Unregister and dealloc decap DI. + */ + nss_unregister_wifi_mesh_if(decap_ifnum); +- nss_status = nss_dynamic_interface_dealloc_node(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER); ++ nss_status = (nss_wifi_meshmgr_status_t)nss_dynamic_interface_dealloc_node(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER); + if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) { + nss_wifi_meshmgr_warn("%px: Failed to dealloc decap: %d\n", &wmgr_ctx, nss_status); + } +@@ -135,7 +135,7 @@ static void nss_wifi_meshmgr_cleanup(str + * Unregister and dealloc encap DI. + */ + nss_unregister_wifi_mesh_if(encap_ifnum); +- nss_status = nss_dynamic_interface_dealloc_node(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER); ++ nss_status = (nss_wifi_meshmgr_status_t)nss_dynamic_interface_dealloc_node(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER); + if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) { + nss_wifi_meshmgr_warn("%px: Failed to dealloc encap: %d\n", &wmgr_ctx, nss_status); + } +@@ -257,10 +257,10 @@ static void nss_wifi_meshmgr_tx_msg_cb(v + /* + * FIXME: The wmesh_ctx can be invalid if the memory goes away with the caller being timedout. + */ +- wmesh_ctx->response = NSS_WIFI_MESHMGR_SUCCESS; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_SUCCESS; + if (ncm->response != NSS_CMN_RESPONSE_ACK) { + nss_wifi_meshmgr_warn("%px: WiFi-Mesh error response %d error_code: %u\n", &wmgr_ctx, ncm->response, error_code); +- wmesh_ctx->response = nss_wifi_meshmgr_remap_error(error_code); ++ wmesh_ctx->response = (nss_tx_status_t)nss_wifi_meshmgr_remap_error(error_code); + } + + complete(&wmesh_ctx->complete); +@@ -289,10 +289,10 @@ static nss_wifi_meshmgr_status_t nss_wif + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- status = wmesh_ctx->response; ++ status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + return status; + } +@@ -324,7 +324,7 @@ nss_wifi_meshmgr_status_t nss_wifi_meshm + return NSS_WIFI_MESHMGR_FAILURE; + } + +- nss_status = nss_wifi_mesh_tx_buf(wmgr_ctx.nss_ctx, os_buf, encap_ifnum); ++ nss_status = (nss_wifi_meshmgr_status_t)nss_wifi_mesh_tx_buf(wmgr_ctx.nss_ctx, os_buf, encap_ifnum); + nss_wifi_meshmgr_ref_dec(wmesh_ctx); + return nss_status; + } +@@ -548,10 +548,10 @@ nss_wifi_meshmgr_dump_mesh_path_sync(nss + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -643,10 +643,10 @@ nss_wifi_meshmgr_dump_mesh_proxy_path_sy + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -715,7 +715,7 @@ nss_wifi_meshmgr_assoc_link_vap(nss_wifi + /* + * Send the link vap mesage to the NSS synchronously. + */ +- nss_status = nss_wifi_vdev_tx_msg(wmgr_ctx.nss_ctx, wifivdevmsg); ++ nss_status = (nss_wifi_meshmgr_status_t)nss_wifi_vdev_tx_msg(wmgr_ctx.nss_ctx, wifivdevmsg); + if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) { + nss_wifi_meshmgr_warn("%px: Mesh link vap association failed: %d.\n", &wmgr_ctx, nss_status); + } +@@ -761,10 +761,10 @@ nss_wifi_meshmgr_assoc_link_vap_sync(nss + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -886,10 +886,10 @@ nss_wifi_meshmgr_mesh_config_update_sync + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -985,10 +985,10 @@ nss_wifi_meshmgr_mesh_proxy_path_delete_ + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1084,10 +1084,10 @@ nss_wifi_meshmgr_mesh_proxy_path_update_ + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1183,10 +1183,10 @@ nss_wifi_meshmgr_mesh_proxy_path_add_syn + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1282,10 +1282,10 @@ nss_wifi_meshmgr_mesh_path_delete_sync(n + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1381,10 +1381,10 @@ nss_wifi_meshmgr_mesh_path_add_sync(nss_ + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + nss_wifi_meshmgr_ref_dec(wmesh_ctx); + return nss_status; +@@ -1479,10 +1479,10 @@ nss_wifi_meshmgr_mesh_path_update_sync(n + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1578,10 +1578,10 @@ nss_wifi_meshmgr_mesh_path_exception_syn + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1702,10 +1702,10 @@ nss_wifi_meshmgr_config_mesh_exception_s + ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT)); + if (!ret) { + nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx); +- wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; ++ wmesh_ctx->response = (nss_tx_status_t)NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT; + } + +- nss_status = wmesh_ctx->response; ++ nss_status = (nss_wifi_meshmgr_status_t)wmesh_ctx->response; + up(&wmesh_ctx->sem); + + nss_wifi_meshmgr_ref_dec(wmesh_ctx); +@@ -1795,7 +1795,7 @@ nss_wifi_mesh_handle_t nss_wifi_meshmgr_ + int32_t encap_ifnum, decap_ifnum; + uint32_t features = 0; + nss_wifi_mesh_handle_t mesh_handle; +- nss_wifi_meshmgr_status_t nss_status; ++ nss_wifi_meshmgr_status_t nss_status = NSS_WIFI_MESHMGR_SUCCESS; + struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx; + + spin_lock_bh(&wmgr_ctx.ref_lock); diff --git a/qca-nss-clients/patches/0020-capwapmgr-fix-compile-error.patch b/qca-nss-clients/patches/0020-capwapmgr-fix-compile-error.patch new file mode 100644 index 0000000..5a357c2 --- /dev/null +++ b/qca-nss-clients/patches/0020-capwapmgr-fix-compile-error.patch @@ -0,0 +1,169 @@ +--- a/capwapmgr/nss_capwapmgr.c ++++ b/capwapmgr/nss_capwapmgr.c +@@ -334,7 +334,7 @@ static struct rtnl_link_stats64 *nss_cap + * Netdev seems to be incrementing rx_dropped because we don't give IP header. + * So reset it as it's of no use for us. + */ +- atomic_long_set(&dev->rx_dropped, 0); ++ dev->stats.rx_dropped = 0; + + memset(stats, 0, sizeof (struct rtnl_link_stats64)); + nss_capwapmgr_fill_up_stats(stats, &global.tunneld); +@@ -379,7 +379,6 @@ static const struct net_device_ops nss_c + .ndo_stop = nss_capwapmgr_close, + .ndo_start_xmit = nss_capwapmgr_start_xmit, + .ndo_set_mac_address = eth_mac_addr, +- .ndo_change_mtu = eth_change_mtu, + .ndo_get_stats64 = nss_capwapmgr_dev_tunnel_stats, + }; + +@@ -403,7 +402,7 @@ static void nss_capwapmgr_dummpy_netdev_ + #else + dev->priv_destructor = NULL; + #endif +- memcpy(dev->dev_addr, "\x00\x00\x00\x00\x00\x00", dev->addr_len); ++ memcpy((u8 *)dev->dev_addr, "\x00\x00\x00\x00\x00\x00", dev->addr_len); + memset(dev->broadcast, 0xff, dev->addr_len); + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); + } +@@ -572,7 +571,7 @@ static struct nss_capwapmgr_tunnel *nss_ + * nss_capwapmgr_netdev_create() + * API to create a CAPWAP netdev + */ +-struct net_device *nss_capwapmgr_netdev_create() ++struct net_device *nss_capwapmgr_netdev_create(void) + { + struct nss_capwapmgr_priv *priv; + struct nss_capwapmgr_response *r; +@@ -1179,7 +1178,7 @@ static nss_capwapmgr_status_t nss_capwap + /* + * Call NSS driver + */ +- status = nss_capwap_tx_msg(ctx, msg); ++ status = (nss_capwapmgr_status_t)nss_capwap_tx_msg(ctx, msg); + if (status != NSS_CAPWAPMGR_SUCCESS) { + up(&r->sem); + dev_put(dev); +@@ -1220,7 +1219,7 @@ static nss_capwapmgr_status_t nss_capwap + struct nss_ctx_instance *ctx = nss_capwap_get_ctx(); + struct nss_capwap_msg capwapmsg; + struct nss_capwap_rule_msg *capwapcfg; +- nss_tx_status_t status; ++ nss_capwapmgr_status_t status; + + nss_capwapmgr_info("%px: ctx: CAPWAP Rule src_port: 0x%d dest_port:0x%d\n", ctx, + ntohl(msg->encap.src_port), ntohl(msg->encap.dest_port)); +@@ -1285,7 +1284,7 @@ static nss_capwapmgr_status_t nss_capwap + nss_capwapmgr_msg_event_receive, dev); + + status = nss_capwapmgr_tx_msg_sync(ctx, dev, &capwapmsg); +- if (status != NSS_TX_SUCCESS) { ++ if (status != NSS_CAPWAPMGR_SUCCESS) { + nss_capwapmgr_warn("%px: ctx: create encap data tunnel error %d \n", ctx, status); + return status; + } +@@ -1297,10 +1296,10 @@ static nss_capwapmgr_status_t nss_capwap + * nss_capwapmgr_tx_msg_enable_tunnel() + * Common function to send CAPWAP tunnel enable msg + */ +-static nss_tx_status_t nss_capwapmgr_tx_msg_enable_tunnel(struct nss_ctx_instance *ctx, struct net_device *dev, uint32_t if_num, uint32_t sibling_if_num) ++static nss_capwapmgr_status_t nss_capwapmgr_tx_msg_enable_tunnel(struct nss_ctx_instance *ctx, struct net_device *dev, uint32_t if_num, uint32_t sibling_if_num) + { + struct nss_capwap_msg capwapmsg; +- nss_tx_status_t status; ++ nss_capwapmgr_status_t status; + + /* + * Prepare the tunnel configuration parameter to send to NSS FW +@@ -1314,7 +1313,7 @@ static nss_tx_status_t nss_capwapmgr_tx_ + nss_capwap_msg_init(&capwapmsg, if_num, NSS_CAPWAP_MSG_TYPE_ENABLE_TUNNEL, sizeof(struct nss_capwap_enable_tunnel_msg), nss_capwapmgr_msg_event_receive, dev); + + status = nss_capwapmgr_tx_msg_sync(ctx, dev, &capwapmsg); +- if (status != NSS_TX_SUCCESS) { ++ if (status != NSS_CAPWAPMGR_SUCCESS) { + nss_capwapmgr_warn("%px: ctx: CMD: %d Tunnel error : %d \n", ctx, NSS_CAPWAP_MSG_TYPE_ENABLE_TUNNEL, status); + } + +@@ -1326,7 +1325,7 @@ static nss_tx_status_t nss_capwapmgr_tx_ + * Common function for CAPWAP tunnel operation messages without + * any message data structures. + */ +-static nss_tx_status_t nss_capwapmgr_tunnel_action(struct nss_ctx_instance *ctx, struct net_device *dev, uint32_t if_num, nss_capwap_msg_type_t cmd) ++static nss_capwapmgr_status_t nss_capwapmgr_tunnel_action(struct nss_ctx_instance *ctx, struct net_device *dev, uint32_t if_num, nss_capwap_msg_type_t cmd) + { + struct nss_capwap_msg capwapmsg; + nss_tx_status_t status; +@@ -1341,12 +1340,12 @@ static nss_tx_status_t nss_capwapmgr_tun + */ + nss_capwap_msg_init(&capwapmsg, if_num, cmd, 0, nss_capwapmgr_msg_event_receive, dev); + +- status = nss_capwapmgr_tx_msg_sync(ctx, dev, &capwapmsg); ++ status = (nss_tx_status_t)nss_capwapmgr_tx_msg_sync(ctx, dev, &capwapmsg); + if (status != NSS_TX_SUCCESS) { + nss_capwapmgr_warn("%px: ctx: CMD: %d Tunnel error : %d \n", ctx, cmd, status); + } + +- return status; ++ return (nss_capwapmgr_status_t)status; + } + + /* +@@ -1471,7 +1470,6 @@ EXPORT_SYMBOL(nss_capwapmgr_update_path_ + */ + nss_capwapmgr_status_t nss_capwapmgr_update_dest_mac_addr(struct net_device *dev, uint8_t tunnel_id, uint8_t *mac_addr) + { +- struct nss_capwapmgr_priv *priv; + struct nss_capwapmgr_tunnel *t; + nss_tx_status_t nss_status; + nss_capwapmgr_status_t status = NSS_CAPWAPMGR_SUCCESS; +@@ -1487,7 +1485,6 @@ nss_capwapmgr_status_t nss_capwapmgr_upd + } + + +- priv = netdev_priv(dev); + nss_capwapmgr_info("%px: %d: tunnel update mac Addr is being called\n", dev, tunnel_id); + + /* +@@ -1534,7 +1531,6 @@ EXPORT_SYMBOL(nss_capwapmgr_update_dest_ + */ + nss_capwapmgr_status_t nss_capwapmgr_update_src_interface(struct net_device *dev, uint8_t tunnel_id, uint32_t src_interface_num) + { +- struct nss_capwapmgr_priv *priv; + struct nss_capwapmgr_tunnel *t; + nss_tx_status_t nss_status; + uint32_t outer_trustsec_enabled, dtls_enabled, forward_if_num, src_interface_num_temp; +@@ -1548,7 +1544,6 @@ nss_capwapmgr_status_t nss_capwapmgr_upd + } + + +- priv = netdev_priv(dev); + nss_capwapmgr_info("%px: %d: tunnel update source interface is being called\n", dev, tunnel_id); + outer_trustsec_enabled = t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_OUTER_TRUSTSEC_ENABLED; + dtls_enabled = t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_DTLS_ENABLED; +@@ -1587,7 +1582,7 @@ nss_capwapmgr_status_t nss_capwapmgr_upd + /* + * Destroy the IP rule only if it already exist. + */ +- if (t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) { ++ if (NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) { + struct nss_ipv4_destroy v4_destroy; + v4_destroy.protocol = IPPROTO_UDP; + v4_destroy.src_ip = t->ip_rule.v4.src_ip; +@@ -1617,7 +1612,7 @@ nss_capwapmgr_status_t nss_capwapmgr_upd + /* + * Destroy the IP rule only if it already exist. + */ +- if (t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) { ++ if (NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) { + struct nss_ipv6_destroy v6_destroy; + + if (t->capwap_rule.which_udp == NSS_CAPWAP_TUNNEL_UDP) { +@@ -1761,7 +1756,7 @@ nss_capwapmgr_status_t nss_capwapmgr_dsc + uint8_t rule_nr = NSS_CAPWAPMGR_RULE_NR; + uint8_t list_id, v4_rule_id, v6_rule_id; + uint8_t lid, rid, i, j; +- int8_t err, fail_dscp; ++ uint8_t err, fail_dscp; + int8_t uid = -1; + + nss_capwapmgr_info("Setting priority %u for dscp %u mask %u\n", pri, dscp_value, dscp_mask); diff --git a/qca-nss-clients/patches/0022-netlink-modularize-makefile.patch b/qca-nss-clients/patches/0022-netlink-modularize-makefile.patch new file mode 100644 index 0000000..e436f58 --- /dev/null +++ b/qca-nss-clients/patches/0022-netlink-modularize-makefile.patch @@ -0,0 +1,539 @@ +--- a/netlink/Makefile ++++ b/netlink/Makefile +@@ -10,47 +10,83 @@ ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BU + + ccflags-y += -DCONFIG_NSS_NLIPV4=1 + ccflags-y += -DCONFIG_NSS_NLIPV6=1 +-ccflags-y += -DCONFIG_NSS_NLOAM=1 +-ccflags-y += -DCONFIG_NSS_NLGRE_REDIR_FAMILY=1 ++ccflags-y += -DCONFIG_NSS_NLOAM=$(strip $(if $(filter $(oam), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLGRE_REDIR_FAMILY=$(strip $(if $(filter $(CONFIG_NSS_NLGRE_REDIR_FAMILY), y), 1 , 0)) + ccflags-y += -DCONFIG_NSS_NLETHRX=1 + ccflags-y += -DCONFIG_NSS_NLDYNAMIC_INTERFACE=1 + ccflags-y += -DCONFIG_NSS_NLN2H=1 +-ccflags-y += -DCONFIG_NSS_NLIPV4_REASM=1 +-ccflags-y += -DCONFIG_NSS_NLIPV6_REASM=1 ++ccflags-y += -DCONFIG_NSS_NLIPV4_REASM=$(strip $(if $(filter $(CONFIG_NSS_NLIPV4_REASM), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLIPV6_REASM=$(strip $(if $(filter $(CONFIG_NSS_NLIPV6_REASM), y), 1 , 0)) + ccflags-y += -DCONFIG_NSS_NLWIFILI=1 +-ccflags-y += -DCONFIG_NSS_NLLSO_RX=1 +-ccflags-y += -DCONFIG_NSS_NLMAP_T=1 +-ccflags-y += -DCONFIG_NSS_NLPPPOE=1 +-ccflags-y += -DCONFIG_NSS_NLL2TPV2=1 +-ccflags-y += -DCONFIG_NSS_NLQRFS=1 +-ccflags-y += -DCONFIG_NSS_NLPPTP=1 ++ccflags-y += -DCONFIG_NSS_NLLSO_RX=$(strip $(if $(filter $(lso), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLMAP_T=$(strip $(if $(filter $(map-t), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLPPPOE=$(strip $(if $(filter $(pppoe), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLL2TPV2=$(strip $(if $(filter $(l2tp), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLQRFS=$(strip $(if $(filter $(CONFIG_NSS_NLQRFS), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLPPTP=$(strip $(if $(filter $(pptp), y), 1 , 0)) + ccflags-y += -DCONFIG_NSS_NLCAPWAP=${CAPWAP_ENABLED} + ccflags-y += -DCONFIG_NSS_NLIPSEC=${IPSEC_ENABLED} + ccflags-y += -DCONFIG_NSS_NLDTLS=${DTLS_ENABLED} +-ccflags-y += -DCONFIG_NSS_NLUDP_ST=1 ++ccflags-y += -DCONFIG_NSS_NLUDP_ST=$(strip $(if $(filter $(CONFIG_NSS_NLUDP_ST), y), 1 , 0)) + + qca-nss-netlink-objs := nss_nl.o ++ ++ifneq (,$(filter $(gre), y)) + qca-nss-netlink-objs += nss_nlgre_redir_family.o + qca-nss-netlink-objs += nss_nlgre_redir_cmd.o + qca-nss-netlink-objs += nss_nlgre_redir_cmn.o + qca-nss-netlink-objs += nss_nlgre_redir.o + qca-nss-netlink-objs += nss_nlgre_redir_lag.o ++endif ++ + qca-nss-netlink-objs += nss_nlipv4.o + qca-nss-netlink-objs += nss_nlipv6.o ++ ++ifneq (,$(filter $(oam), y)) + qca-nss-netlink-objs += nss_nloam.o ++endif ++ + qca-nss-netlink-objs += nss_nlethrx.o + qca-nss-netlink-objs += nss_nldynamic_interface.o + qca-nss-netlink-objs += nss_nln2h.o ++ ++ifneq (,$(filter $(CONFIG_NSS_NLIPV4_REASM), y)) + qca-nss-netlink-objs += nss_nlipv4_reasm.o ++endif ++ifneq (,$(filter $(CONFIG_NSS_NLIPV6_REASM), y)) + qca-nss-netlink-objs += nss_nlipv6_reasm.o ++endif ++ + qca-nss-netlink-objs += nss_nlwifili.o ++ ++ifneq (,$(filter $(lso), y)) + qca-nss-netlink-objs += nss_nllso_rx.o ++endif ++ ++ifneq (,$(filter $(map-t), y)) + qca-nss-netlink-objs += nss_nlmap_t.o ++endif ++ifneq (,$(filter $(pppoe), y)) + qca-nss-netlink-objs += nss_nlpppoe.o ++endif ++ ++ifneq (,$(filter $(l2tp), y)) + qca-nss-netlink-objs += nss_nll2tpv2.o ++endif ++ ++ifneq (,$(filter $(pptp), y)) + qca-nss-netlink-objs += nss_nlpptp.o ++endif ++ ++ifeq ($(SoC),$(filter $(SoC),ipq95xx ipq50xx ipq807x_64)) ++ifneq (,$(filter $(CONFIG_NSS_NLUDP_ST), y)) + qca-nss-netlink-objs += nss_nludp_st.o ++endif ++endif ++ ++ifneq (,$(filter $(CONFIG_NSS_NLQRFS), y)) + qca-nss-netlink-objs += nss_nlqrfs.o ++endif + + ifneq (,$(filter $(capwapmgr), y)) + qca-nss-netlink-objs += nss_nlcapwap.o +@@ -64,14 +100,11 @@ ifneq (,$(filter $(ipsecmgr), y)) + qca-nss-netlink-objs += nss_nlipsec.o + endif + ++ccflags-y += -DCONFIG_NSS_NLC2C_TX=$(strip $(if $(filter $(CONFIG_NSS_NLC2C), y), 1 , 0)) ++ccflags-y += -DCONFIG_NSS_NLC2C_RX=$(strip $(if $(filter $(CONFIG_NSS_NLC2C), y), 1 , 0)) + ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64)) +-ccflags-y += -DCONFIG_NSS_NLC2C_TX=1 +-ccflags-y += -DCONFIG_NSS_NLC2C_RX=1 +-qca-nss-netlink-objs += nss_nlc2c_tx.o +-qca-nss-netlink-objs += nss_nlc2c_rx.o +-else +-ccflags-y += -DCONFIG_NSS_NLC2C_TX=0 +-ccflags-y += -DCONFIG_NSS_NLC2C_RX=0 ++qca-nss-netlink-objs += $(strip $(if $(filter $(CONFIG_NSS_NLC2C), y), nss_nlc2c_tx.o,)) ++qca-nss-netlink-objs += $(strip $(if $(filter $(CONFIG_NSS_NLC2C), y), nss_nlc2c_rx.o,)) + endif + + ifeq ($(SoC),$(filter $(SoC),ipq60xx ipq60xx_64 ipq807x ipq807x_64)) +--- a/netlink/nss_nludp_st.h ++++ b/netlink/nss_nludp_st.h +@@ -23,10 +23,9 @@ + #ifndef __NSS_NLUDP_ST_H + #define __NSS_NLUDP_ST_H + ++#if defined(CONFIG_NSS_NLUDP_ST) && CONFIG_NSS_NLUDP_ST > 0 + bool nss_nludp_st_init(void); + bool nss_nludp_st_exit(void); +- +-#if defined(CONFIG_NSS_NLUDP_ST) + #define NSS_NLUDP_ST_INIT nss_nludp_st_init + #define NSS_NLUDP_ST_EXIT nss_nludp_st_exit + #else +--- a/netlink/nss_nldynamic_interface.h ++++ b/netlink/nss_nldynamic_interface.h +@@ -26,7 +26,7 @@ + bool nss_nldynamic_interface_init(void); + bool nss_nldynamic_interface_exit(void); + +-#if defined(CONFIG_NSS_NLDYNAMIC_INTERFACE) ++#if defined(CONFIG_NSS_NLDYNAMIC_INTERFACE) && CONFIG_NSS_NLDYNAMIC_INTERFACE > 0 + #define NSS_NLDYNAMIC_INTERFACE_INIT nss_nldynamic_interface_init + #define NSS_NLDYNAMIC_INTERFACE_EXIT nss_nldynamic_interface_exit + #else +--- a/netlink/nss_nlethrx.h ++++ b/netlink/nss_nlethrx.h +@@ -26,7 +26,7 @@ + bool nss_nlethrx_init(void); + bool nss_nlethrx_exit(void); + +-#if defined(CONFIG_NSS_NLETHRX) ++#if defined(CONFIG_NSS_NLETHRX) && CONFIG_NSS_NLETHRX > 0 + #define NSS_NLETHRX_INIT nss_nlethrx_init + #define NSS_NLETHRX_EXIT nss_nlethrx_exit + #else +--- a/netlink/nss_nlgre_redir_family.h ++++ b/netlink/nss_nlgre_redir_family.h +@@ -33,7 +33,7 @@ bool nss_nlgre_redir_family_init(void); + */ + bool nss_nlgre_redir_family_exit(void); + +-#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY) ++#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY) && CONFIG_NSS_NLGRE_REDIR_FAMILY > 0 + #define NSS_NLGRE_REDIR_FAMILY_INIT nss_nlgre_redir_family_init + #define NSS_NLGRE_REDIR_FAMILY_EXIT nss_nlgre_redir_family_exit + #else +--- a/netlink/nss_nlipv4.c ++++ b/netlink/nss_nlipv4.c +@@ -336,6 +336,7 @@ static int nss_nlipv4_verify_conn_rule(s + tuple->return_ident, tuple->flow_ident); + break; + ++#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY) && CONFIG_NSS_NLGRE_REDIR_FAMILY > 0 + case NSS_NL_IFTYPE_TUNNEL_GRE: + /* + * Currently this implementation is only for gre_redir +@@ -349,6 +350,7 @@ static int nss_nlipv4_verify_conn_rule(s + + conn->flow_mtu = nss_nlgre_redir_cmd_get_mtu(flow_dev, NSS_GRE_REDIR_IP_HDR_TYPE_IPV4, conn->flow_interface_num); + break; ++#endif /*!CONFIG_NSS_NLGRE_REDIR_FAMILY */ + + case NSS_NL_IFTYPE_VLAN: + conn->flow_interface_num = nss_cmn_get_interface_number_by_dev(vlan_dev_real_dev(flow_dev)); +@@ -396,6 +398,7 @@ static int nss_nlipv4_verify_conn_rule(s + tuple->return_ident, tuple->flow_ident); + break; + ++#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY) && CONFIG_NSS_NLGRE_REDIR_FAMILY > 0 + case NSS_NL_IFTYPE_TUNNEL_GRE: + conn->return_interface_num = nss_nlgre_redir_cmd_get_ifnum(return_dev, tuple->protocol); + if (conn->return_interface_num < 0 ) { +@@ -406,6 +409,7 @@ static int nss_nlipv4_verify_conn_rule(s + + conn->return_mtu = nss_nlgre_redir_cmd_get_mtu(return_dev, NSS_GRE_REDIR_IP_HDR_TYPE_IPV4, conn->return_interface_num); + break; ++#endif /*!CONFIG_NSS_NLGRE_REDIR_FAMILY */ + + case NSS_NL_IFTYPE_VLAN: + conn->return_interface_num = nss_cmn_get_interface_number_by_dev(vlan_dev_real_dev(return_dev)); +@@ -480,6 +484,7 @@ static int nss_nlipv4_verify_tcp_rule(st + return 0; + } + ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + /* + * nss_nlipv4_verify_pppoe_rule() + * verify and override pppoe rule entries +@@ -505,6 +510,7 @@ static int nss_nlipv4_verify_pppoe_rule( + */ + return 0; + } ++#endif + + /* + * nss_nlipv4_verify_qos_rule() +@@ -777,6 +783,7 @@ static int nss_nlipv4_ops_create_rule(st + goto done; + } + ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + /* + * check pppoe rule + */ +@@ -785,6 +792,7 @@ static int nss_nlipv4_ops_create_rule(st + nss_nl_error("%d:invalid pppoe rule information passed\n", pid); + goto done; + } ++#endif + + /* + * check qos rule +--- a/netlink/nss_nlipv4.h ++++ b/netlink/nss_nlipv4.h +@@ -24,7 +24,7 @@ + bool nss_nlipv4_init(void); + bool nss_nlipv4_exit(void); + +-#if defined(CONFIG_NSS_NLIPV4) ++#if defined(CONFIG_NSS_NLIPV4) && CONFIG_NSS_NLIPV4 > 0 + #define NSS_NLIPV4_INIT nss_nlipv4_init + #define NSS_NLIPV4_EXIT nss_nlipv4_exit + #else +--- a/netlink/nss_nlipv4_reasm.h ++++ b/netlink/nss_nlipv4_reasm.h +@@ -26,7 +26,7 @@ + bool nss_nlipv4_reasm_init(void); + bool nss_nlipv4_reasm_exit(void); + +-#if defined(CONFIG_NSS_NLIPV4_REASM) ++#if defined(CONFIG_NSS_NLIPV4_REASM) && CONFIG_NSS_NLIPV4_REASM > 0 + #define NSS_NLIPV4_REASM_INIT nss_nlipv4_reasm_init + #define NSS_NLIPV4_REASM_EXIT nss_nlipv4_reasm_exit + #else +--- a/netlink/nss_nlipv6.c ++++ b/netlink/nss_nlipv6.c +@@ -353,6 +353,7 @@ static int nss_nlipv6_verify_conn_rule(s + tuple->return_ident, tuple->flow_ident); + break; + ++#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY) && CONFIG_NSS_NLGRE_REDIR_FAMILY > 0 + case NSS_NL_IFTYPE_TUNNEL_GRE: + conn->flow_interface_num = nss_nlgre_redir_cmd_get_ifnum(flow_dev, tuple->protocol); + if (conn->flow_interface_num < 0 ) { +@@ -363,6 +364,7 @@ static int nss_nlipv6_verify_conn_rule(s + + conn->flow_mtu = nss_nlgre_redir_cmd_get_mtu(flow_dev, NSS_GRE_REDIR_IP_HDR_TYPE_IPV6, conn->flow_interface_num); + break; ++#endif /* !CONFIG_NSS_NLGRE_REDIR_FAMILY */ + + case NSS_NL_IFTYPE_VLAN: + conn->flow_interface_num = nss_cmn_get_interface_number_by_dev(vlan_dev_real_dev(flow_dev)); +@@ -411,6 +413,7 @@ static int nss_nlipv6_verify_conn_rule(s + tuple->return_ident, tuple->flow_ident); + break; + ++#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY) && CONFIG_NSS_NLGRE_REDIR_FAMILY > 0 + case NSS_NL_IFTYPE_TUNNEL_GRE: + conn->return_interface_num = nss_nlgre_redir_cmd_get_ifnum(return_dev, tuple->protocol); + if (conn->return_interface_num < 0 ) { +@@ -421,6 +424,7 @@ static int nss_nlipv6_verify_conn_rule(s + + conn->return_mtu = nss_nlgre_redir_cmd_get_mtu(return_dev, NSS_GRE_REDIR_IP_HDR_TYPE_IPV6, conn->return_interface_num); + break; ++#endif /* !CONFIG_NSS_NLGRE_REDIR_FAMILY */ + + case NSS_NL_IFTYPE_VLAN: + conn->return_interface_num = nss_cmn_get_interface_number_by_dev(vlan_dev_real_dev(return_dev)); +@@ -486,6 +490,7 @@ static int nss_nlipv6_verify_tcp_rule(st + return 0; + } + ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + /* + * nss_nlipv6_verify_pppoe_rule() + * verify and override pppoe rule entries +@@ -510,6 +515,7 @@ static int nss_nlipv6_verify_pppoe_rule( + */ + return 0; + } ++#endif + + /* + * nss_nlipv6_verify_igs_rule() +@@ -771,6 +777,7 @@ static int nss_nlipv6_ops_create_rule(st + goto done; + } + ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + /* + * check pppoe rule + */ +@@ -779,6 +786,7 @@ static int nss_nlipv6_ops_create_rule(st + nss_nl_error("%d:invalid pppoe rule information passed\n", pid); + goto done; + } ++#endif + + /* + * check qos rule +--- a/netlink/nss_nlipv6.h ++++ b/netlink/nss_nlipv6.h +@@ -26,7 +26,7 @@ + bool nss_nlipv6_init(void); + bool nss_nlipv6_exit(void); + +-#if defined(CONFIG_NSS_NLIPV6) ++#if defined(CONFIG_NSS_NLIPV6) && CONFIG_NSS_NLIPV6 > 0 + #define NSS_NLIPV6_INIT nss_nlipv6_init + #define NSS_NLIPV6_EXIT nss_nlipv6_exit + #else +--- a/netlink/nss_nlipv6_reasm.h ++++ b/netlink/nss_nlipv6_reasm.h +@@ -26,7 +26,7 @@ + bool nss_nlipv6_reasm_init(void); + bool nss_nlipv6_reasm_exit(void); + +-#if defined(CONFIG_NSS_NLIPV6_REASM) ++#if defined(CONFIG_NSS_NLIPV6_REASM) && CONFIG_NSS_NLIPV6_REASM > 0 + #define NSS_NLIPV6_REASM_INIT nss_nlipv6_reasm_init + #define NSS_NLIPV6_REASM_EXIT nss_nlipv6_reasm_exit + #else +--- a/netlink/nss_nll2tpv2.h ++++ b/netlink/nss_nll2tpv2.h +@@ -26,7 +26,7 @@ + bool nss_nll2tpv2_init(void); + bool nss_nll2tpv2_exit(void); + +-#if defined(CONFIG_NSS_NLL2TPV2) ++#if defined(CONFIG_NSS_NLL2TPV2) && CONFIG_NSS_NLL2TPV2 > 0 + #define NSS_NLL2TPV2_INIT nss_nll2tpv2_init + #define NSS_NLL2TPV2_EXIT nss_nll2tpv2_exit + #else +--- a/netlink/nss_nllso_rx.h ++++ b/netlink/nss_nllso_rx.h +@@ -26,7 +26,7 @@ + bool nss_nllso_rx_init(void); + bool nss_nllso_rx_exit(void); + +-#if defined(CONFIG_NSS_NLLSO_RX) ++#if defined(CONFIG_NSS_NLLSO_RX) && CONFIG_NSS_NLLSO_RX > 0 + #define NSS_NLLSO_RX_INIT nss_nllso_rx_init + #define NSS_NLLSO_RX_EXIT nss_nllso_rx_exit + #else +--- a/netlink/nss_nlmap_t.h ++++ b/netlink/nss_nlmap_t.h +@@ -26,7 +26,7 @@ + bool nss_nlmap_t_init(void); + bool nss_nlmap_t_exit(void); + +-#if defined(CONFIG_NSS_NLMAP_T) ++#if defined(CONFIG_NSS_NLMAP_T) && CONFIG_NSS_NLMAP_T > 0 + #define NSS_NLMAP_T_INIT nss_nlmap_t_init + #define NSS_NLMAP_T_EXIT nss_nlmap_t_exit + #else +--- a/netlink/nss_nln2h.h ++++ b/netlink/nss_nln2h.h +@@ -26,7 +26,7 @@ + bool nss_nln2h_init(void); + bool nss_nln2h_exit(void); + +-#if defined(CONFIG_NSS_NLN2H) ++#if defined(CONFIG_NSS_NLN2H) && CONFIG_NSS_NLN2H > 0 + #define NSS_NLN2H_INIT nss_nln2h_init + #define NSS_NLN2H_EXIT nss_nln2h_exit + #else +--- a/netlink/nss_nloam.h ++++ b/netlink/nss_nloam.h +@@ -25,7 +25,7 @@ + bool nss_nloam_init(void); + bool nss_nloam_exit(void); + +-#if defined(CONFIG_NSS_NLOAM) ++#if defined(CONFIG_NSS_NLOAM) && CONFIG_NSS_NLOAM > 0 + #define NSS_NLOAM_INIT nss_nloam_init + #define NSS_NLOAM_EXIT nss_nloam_exit + #else +--- a/netlink/nss_nlpppoe.h ++++ b/netlink/nss_nlpppoe.h +@@ -26,7 +26,7 @@ + bool nss_nlpppoe_init(void); + bool nss_nlpppoe_exit(void); + +-#if defined(CONFIG_NSS_NLPPPOE) ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + #define NSS_NLPPPOE_INIT nss_nlpppoe_init + #define NSS_NLPPPOE_EXIT nss_nlpppoe_exit + #else +--- a/netlink/nss_nlpptp.h ++++ b/netlink/nss_nlpptp.h +@@ -26,7 +26,7 @@ + bool nss_nlpptp_init(void); + bool nss_nlpptp_exit(void); + +-#if defined(CONFIG_NSS_NLPPTP) ++#if defined(CONFIG_NSS_NLPPTP) && CONFIG_NSS_NLPPTP > 0 + #define NSS_NLPPTP_INIT nss_nlpptp_init + #define NSS_NLPPTP_EXIT nss_nlpptp_exit + #else +--- a/netlink/nss_nlwifili.h ++++ b/netlink/nss_nlwifili.h +@@ -26,7 +26,7 @@ + bool nss_nlwifili_init(void); + bool nss_nlwifili_exit(void); + +-#if defined(CONFIG_NSS_NLWIFILI) ++#if defined(CONFIG_NSS_NLWIFILI) && CONFIG_NSS_NLWIFILI > 0 + #define NSS_NLWIFILI_INIT nss_nlwifili_init + #define NSS_NLWIFILI_EXIT nss_nlwifili_exit + #else +--- a/netlink/nss_nl.c ++++ b/netlink/nss_nl.c +@@ -289,23 +289,23 @@ static struct nss_nl_family family_handl + .valid = CONFIG_NSS_NLPPTP /* 1 or 0 */ + }, + { +- /* +- * NSS_NLUDP_ST +- */ +- .name = NSS_NLUDP_ST_FAMILY, /* udp_st */ +- .entry = NSS_NLUDP_ST_INIT, /* init */ +- .exit = NSS_NLUDP_ST_EXIT, /* exit */ +- .valid = CONFIG_NSS_NLUDP_ST /* 1 or 0 */ +- }, ++ /* ++ * NSS_NLUDP_ST ++ */ ++ .name = NSS_NLUDP_ST_FAMILY, /* udp_st */ ++ .entry = NSS_NLUDP_ST_INIT, /* init */ ++ .exit = NSS_NLUDP_ST_EXIT, /* exit */ ++ .valid = CONFIG_NSS_NLUDP_ST /* 1 or 0 */ ++ }, + { +- /* +- * NSS_NLQRFS +- */ +- .name = NSS_NLQRFS_FAMILY, /* qrfs */ +- .entry = NSS_NLQRFS_INIT, /* init */ +- .exit = NSS_NLQRFS_EXIT, /* exit */ +- .valid = CONFIG_NSS_NLQRFS /* 1 or 0 */ +- }, ++ /* ++ * NSS_NLQRFS ++ */ ++ .name = NSS_NLQRFS_FAMILY, /* qrfs */ ++ .entry = NSS_NLQRFS_INIT, /* init */ ++ .exit = NSS_NLQRFS_EXIT, /* exit */ ++ .valid = CONFIG_NSS_NLQRFS /* 1 or 0 */ ++ }, + + + }; +--- a/netlink/nss_nlqrfs.h ++++ b/netlink/nss_nlqrfs.h +@@ -26,7 +26,7 @@ + bool nss_nlqrfs_init(void); + bool nss_nlqrfs_exit(void); + +-#if defined(CONFIG_NSS_NLQRFS) ++#if defined(CONFIG_NSS_NLQRFS) && CONFIG_NSS_NLQRFS > 0 + #define NSS_NLQRFS_INIT nss_nlqrfs_init + #define NSS_NLQRFS_EXIT nss_nlqrfs_exit + #else +--- a/netlink/nss_nludp_st.c ++++ b/netlink/nss_nludp_st.c +@@ -1162,6 +1162,7 @@ fail: + return ret; + } + ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + /* + * nss_nludp_st_pppoe_get_chan_and_info() + * Gets the PPPoE channel information. +@@ -1296,6 +1297,8 @@ fail: + ppp_release_channels(ppp_chan, 1); + return ret; + } ++#endif ++ + + /* + * nss_nludp_st_create_ipv4_rule() +@@ -1391,9 +1394,11 @@ static int nss_nludp_st_create_ipv4_rule + ret = nss_nludp_st_ipv4_rawip_iface_config(net_dev, nircm); + break; + ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + case ARPHRD_PPP: + ret = nss_nludp_st_ipv4_pppoe_iface_config(net_dev, nircm); + break; ++#endif + + case ARPHRD_ETHER: + /* +@@ -1620,6 +1625,7 @@ fail: + return ret; + } + ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + /* + * nss_nludp_st_ipv6_pppoe_iface_config() + * Configure the WAN interface as PPPoE for IPv6 protocol. +@@ -1723,6 +1729,7 @@ fail: + ppp_release_channels(ppp_chan, 1); + return ret; + } ++#endif + + /* + * nss_nludp_st_create_ipv6_rule() +@@ -1814,9 +1821,11 @@ static int nss_nludp_st_create_ipv6_rule + ret = nss_nludp_st_ipv6_rawip_iface_config(net_dev, nircm); + break; + ++#if defined(CONFIG_NSS_NLPPPOE) && CONFIG_NSS_NLPPPOE > 0 + case ARPHRD_PPP: + ret = nss_nludp_st_ipv6_pppoe_iface_config(net_dev, nircm); + break; ++#endif + + case ARPHRD_ETHER: + /* diff --git a/qca-nss-clients/patches/0024-switch-to-wifili.patch b/qca-nss-clients/patches/0024-switch-to-wifili.patch new file mode 100644 index 0000000..53832f3 --- /dev/null +++ b/qca-nss-clients/patches/0024-switch-to-wifili.patch @@ -0,0 +1,93 @@ +--- a/match/nss_match_cmd.c ++++ b/match/nss_match_cmd.c +@@ -460,10 +460,10 @@ static int nss_match_cmd_procfs_reset_ne + char *cmd_buf = nss_match_data; + nss_tx_status_t nss_tx_status; + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); +- struct nss_ctx_instance *wifi_nss_ctx = nss_wifi_get_context(); ++ struct nss_ctx_instance *wifili_nss_ctx = nss_wifili_get_context(); + +- if (!nss_ctx || !wifi_nss_ctx) { +- pr_warn("%px: NSS Context not found. wifi_nss_ctx: %px. Reset nexthop failed", nss_ctx, wifi_nss_ctx); ++ if (!nss_ctx || !wifili_nss_ctx) { ++ pr_warn("%px: NSS Context not found. wifili_nss_ctx: %px. Reset nexthop failed", nss_ctx, wifili_nss_ctx); + return -ENOMEM; + } + +@@ -495,9 +495,9 @@ static int nss_match_cmd_procfs_reset_ne + * nss_phys_if_reset_nexthop: Used for physical interfaces. + * nss_if_reset_nexthop: used for VAP interfaces. + */ +- type = nss_dynamic_interface_get_type(wifi_nss_ctx, if_num); ++ type = nss_dynamic_interface_get_type(wifili_nss_ctx, if_num); + if (type == NSS_DYNAMIC_INTERFACE_TYPE_VAP) { +- nss_tx_status = nss_if_reset_nexthop(wifi_nss_ctx, if_num); ++ nss_tx_status = nss_if_reset_nexthop(wifili_nss_ctx, if_num); + } else if (if_num < NSS_MAX_PHYSICAL_INTERFACES) { + nss_tx_status = nss_phys_if_reset_nexthop(nss_ctx, if_num); + } else { +@@ -528,7 +528,7 @@ static int nss_match_cmd_procfs_set_if_n + uint32_t nh_if_num; + int table_id; + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); +- struct nss_ctx_instance *wifi_nss_ctx = nss_wifi_get_context(); ++ struct nss_ctx_instance *wifili_nss_ctx = nss_wifili_get_context(); + char *dev_name, *nexthop_msg; + char *cmd_buf = NULL; + size_t count = *lenp; +@@ -539,8 +539,8 @@ static int nss_match_cmd_procfs_set_if_n + return ret; + } + +- if (!nss_ctx || !wifi_nss_ctx) { +- pr_warn("%px: NSS Context not found. wifi_nss_ctx: %px. Set nexthop failed", nss_ctx, wifi_nss_ctx); ++ if (!nss_ctx || !wifili_nss_ctx) { ++ pr_warn("%px: NSS Context not found. wifili_nss_ctx: %px. Set nexthop failed", nss_ctx, wifili_nss_ctx); + return -ENOMEM; + } + +@@ -607,9 +607,9 @@ static int nss_match_cmd_procfs_set_if_n + * nss_phys_if_set_nexthop: Used for physical interfaces. + * nss_if_set_nexthop: used for VAP interfaces. + */ +- type = nss_dynamic_interface_get_type(wifi_nss_ctx, if_num); ++ type = nss_dynamic_interface_get_type(wifili_nss_ctx, if_num); + if (type == NSS_DYNAMIC_INTERFACE_TYPE_VAP) { +- nss_tx_status = nss_if_set_nexthop(wifi_nss_ctx, if_num, nh_if_num); ++ nss_tx_status = nss_if_set_nexthop(wifili_nss_ctx, if_num, nh_if_num); + } else if (if_num < NSS_MAX_PHYSICAL_INTERFACES) { + nss_tx_status = nss_phys_if_set_nexthop(nss_ctx, if_num, nh_if_num); + } else { +--- a/gre/nss_connmgr_gre.c ++++ b/gre/nss_connmgr_gre.c +@@ -1672,7 +1672,7 @@ int nss_connmgr_gre_set_wifi_next_hop(st + return GRE_ERR_NEXT_NODE_UNREG_IN_AE; + } + +- ctx = nss_wifi_get_context(); ++ ctx = nss_wifili_get_context(); + status = nss_wifi_vdev_set_next_hop(ctx, ifnumber, NSS_GRE_INTERFACE); + if (status != NSS_TX_SUCCESS) { + nss_connmgr_gre_info("%px: wifi drv api failed to set next hop\n", wifi_vdev); +--- a/mirror/nss_mirror_ctl.c ++++ b/mirror/nss_mirror_ctl.c +@@ -480,7 +480,7 @@ static int nss_mirror_ctl_parse_enable_i + type = nss_dynamic_interface_get_type(nss_ctx, if_num); + + if (type == NSS_DYNAMIC_INTERFACE_TYPE_VAP) { +- status = nss_wifi_vdev_set_next_hop(nss_wifi_get_context(), if_num, mirror_if_num); ++ status = nss_wifi_vdev_set_next_hop(nss_wifili_get_context(), if_num, mirror_if_num); + } else if (if_num < NSS_MAX_PHYSICAL_INTERFACES) { + status = nss_phys_if_set_nexthop(nss_ctx, if_num, mirror_if_num); + } else { +--- a/netlink/nss_nlgre_redir_cmn.c ++++ b/netlink/nss_nlgre_redir_cmn.c +@@ -905,7 +905,7 @@ int nss_nlgre_redir_cmn_set_next_hop(uin + } + + nss_nl_info("%px: next hop interface number is %d\n", nss_ctx, next_dev_ifnum); +- ctx = nss_wifi_get_context(); ++ ctx = nss_wifili_get_context(); + + ret = nss_wifi_vdev_set_next_hop(ctx, ifnumber, next_dev_ifnum); + if (ret != NSS_TX_SUCCESS) { diff --git a/qca-nss-clients/patches/0025-nss-clients-add-kernel-6.6-support.patch b/qca-nss-clients/patches/0025-nss-clients-add-kernel-6.6-support.patch new file mode 100644 index 0000000..2d4bd0a --- /dev/null +++ b/qca-nss-clients/patches/0025-nss-clients-add-kernel-6.6-support.patch @@ -0,0 +1,274 @@ +--- a/bridge/nss_bridge_mgr.c ++++ b/bridge/nss_bridge_mgr.c +@@ -1369,7 +1369,6 @@ static struct notifier_block nss_bridge_ + .notifier_call = nss_bridge_mgr_netdevice_event, + }; + +-#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT) + /* + * nss_bridge_mgr_is_physical_dev() + * Check if the device is on physical device. +@@ -1598,25 +1597,6 @@ static struct ctl_table nss_bridge_mgr_t + { } + }; + +-static struct ctl_table nss_bridge_mgr_dir[] = { +- { +- .procname = "bridge_mgr", +- .mode = 0555, +- .child = nss_bridge_mgr_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_bridge_mgr_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_bridge_mgr_dir, +- }, +- { } +-}; +-#endif +- + /* + * nss_bridge_mgr_init_module() + * bridge_mgr module init function +@@ -1636,7 +1616,7 @@ int __init nss_bridge_mgr_init_module(vo + #if defined(NSS_BRIDGE_MGR_PPE_SUPPORT) + br_mgr_ctx.wan_if_num = -1; + br_fdb_update_register_notify(&nss_bridge_mgr_fdb_update_notifier); +- br_mgr_ctx.nss_bridge_mgr_header = register_sysctl_table(nss_bridge_mgr_root_dir); ++ br_mgr_ctx.nss_bridge_mgr_header = register_sysctl("nss/bridge_mgr", nss_bridge_mgr_table); + + /* + * Enable ACL rule to enable L2 exception. This is needed if PPE Virtual ports is added to bridge. +--- a/gre/nss_connmgr_gre.c ++++ b/gre/nss_connmgr_gre.c +@@ -277,7 +277,7 @@ static struct rtnl_link_stats64 *nss_con + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) + start = u64_stats_fetch_begin_bh(&tstats->syncp); + #else +- start = u64_stats_fetch_begin_irq(&tstats->syncp); ++ start = u64_stats_fetch_begin(&tstats->syncp); + #endif + rx_packets = u64_stats_read(&tstats->rx_packets); + tx_packets = u64_stats_read(&tstats->tx_packets); +@@ -286,7 +286,7 @@ static struct rtnl_link_stats64 *nss_con + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) + } while (u64_stats_fetch_retry_bh(&tstats->syncp, start)); + #else +- } while (u64_stats_fetch_retry_irq(&tstats->syncp, start)); ++ } while (u64_stats_fetch_retry(&tstats->syncp, start)); + #endif + + tot->rx_packets += rx_packets; +--- a/vlan/nss_vlan_mgr.c ++++ b/vlan/nss_vlan_mgr.c +@@ -1582,30 +1582,6 @@ static struct ctl_table nss_vlan_table[] + }; + + /* +- * nss_vlan sysctl dir +- */ +-static struct ctl_table nss_vlan_dir[] = { +- { +- .procname = "vlan_client", +- .mode = 0555, +- .child = nss_vlan_table, +- }, +- { } +-}; +- +-/* +- * nss_vlan systel root dir +- */ +-static struct ctl_table nss_vlan_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_vlan_dir, +- }, +- { } +-}; +- +-/* + * nss_vlan_mgr_add_bond_slave() + * Add new slave port to bond_vlan + */ +@@ -1944,7 +1920,7 @@ int __init nss_vlan_mgr_init_module(void + vlan_mgr_ctx.stpid = ETH_P_8021Q; + + #ifdef NSS_VLAN_MGR_PPE_SUPPORT +- vlan_mgr_ctx.sys_hdr = register_sysctl_table(nss_vlan_root_dir); ++ vlan_mgr_ctx.sys_hdr = register_sysctl("nss/vlan_client", nss_vlan_table); + if (!vlan_mgr_ctx.sys_hdr) { + nss_vlan_mgr_warn("Unabled to register sysctl table for vlan manager\n"); + return -EFAULT; +--- a/match/nss_match_cmd.c ++++ b/match/nss_match_cmd.c +@@ -692,33 +692,6 @@ static struct ctl_table nss_match_table[ + { } + }; + +-static struct ctl_table nss_match_root_dir[] = { +- { +- .procname = "match", +- .mode = 0555, +- .child = nss_match_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_match_nss_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_match_root_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_match_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_match_nss_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_match_ctl_header; + + /* +@@ -726,7 +699,7 @@ static struct ctl_table_header *nss_matc + * Register command line interface for match. + */ + bool nss_match_ctl_register(void) { +- nss_match_ctl_header = register_sysctl_table(nss_match_root); ++ nss_match_ctl_header = register_sysctl("dev/nss/match", nss_match_table); + if (!nss_match_ctl_header) { + nss_match_warn("Unable to register command line interface.\n"); + return false; +--- a/tunipip6/nss_connmgr_tunipip6_sysctl.c ++++ b/tunipip6/nss_connmgr_tunipip6_sysctl.c +@@ -449,33 +449,6 @@ static struct ctl_table nss_tunipip6_tab + { } + }; + +-static struct ctl_table nss_tunipip6_root_dir[] = { +- { +- .procname = "ipip6", +- .mode = 0555, +- .child = nss_tunipip6_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_tunipip6_nss_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_tunipip6_root_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_tunipip6_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_tunipip6_nss_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_tunipip6_ctl_header; + + /* +@@ -483,7 +456,7 @@ static struct ctl_table_header *nss_tuni + * Register command line interface for tunipip6. + */ + bool nss_tunipip6_sysctl_register(void) { +- nss_tunipip6_ctl_header = register_sysctl_table(nss_tunipip6_root); ++ nss_tunipip6_ctl_header = register_sysctl("drv/nss/ipip6", nss_tunipip6_table); + if (!nss_tunipip6_ctl_header) { + return false; + } +--- a/mirror/nss_mirror_ctl.c ++++ b/mirror/nss_mirror_ctl.c +@@ -919,48 +919,12 @@ static struct ctl_table nss_mirror_table + }; + + /* +- * nss mirror dir +- */ +-static struct ctl_table nss_mirror_root_dir[] = { +- { +- .procname = "mirror", +- .mode = 0555, +- .child = nss_mirror_table, +- }, +- { } +-}; +- +-/* +- * nss mirror sysctl nss root dir +- */ +-static struct ctl_table nss_mirror_nss_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_mirror_root_dir, +- }, +- { } +-}; +- +-/* +- * nss mirror sysctl root dir +- */ +-static struct ctl_table nss_mirror_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_mirror_nss_root_dir, +- }, +- { } +-}; +- +-/* + * nss_mirror_ctl_register() + * Register command line interface for mirror. + */ + int nss_mirror_ctl_register(void) + { +- nss_mirror_ctl_header = register_sysctl_table(nss_mirror_root); ++ nss_mirror_ctl_header = register_sysctl("dev/nss/mirror", nss_mirror_table); + if (!nss_mirror_ctl_header) { + nss_mirror_warn("Creating sysctl directory table header for mirror failed\n"); + return -1; +--- a/l2tp/l2tpv2/nss_connmgr_l2tpv2.c ++++ b/l2tp/l2tpv2/nss_connmgr_l2tpv2.c +@@ -1030,7 +1030,7 @@ int __init nss_connmgr_l2tpv2_init_modul + } + #endif + #if defined(NSS_L2TP_IPSEC_BIND_BY_NETDEV) +- ctl_tbl_hdr = register_sysctl_table(nss_connmgr_l2tpv2_sysroot); ++ ctl_tbl_hdr = register_sysctl("dev/nss/l2tpv2", nss_connmgr_l2tpv2_table); + if (!ctl_tbl_hdr) { + nss_connmgr_l2tpv2_info("Unable to register sysctl table for L2TP conn mgr\n"); + return -EFAULT; +--- a/netlink/nss_nl.c ++++ b/netlink/nss_nl.c +@@ -475,7 +475,11 @@ struct nss_nlcmn *nss_nl_get_msg(struct + /* + * validate the common message header version & magic + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 6, 0)) + cm = info->userhdr; ++#else ++ cm = genl_info_userhdr(info); ++#endif + if (nss_nlcmn_chk_ver(cm, family->version) == false) { + nss_nl_error("%d, %s: version mismatch (%d)\n", pid, family->name, cm->version); + return NULL; diff --git a/qca-nss-clients/patches/0028-dtlsmgr-use-eth_hw_addr_set.patch b/qca-nss-clients/patches/0028-dtlsmgr-use-eth_hw_addr_set.patch new file mode 100644 index 0000000..20a1e8e --- /dev/null +++ b/qca-nss-clients/patches/0028-dtlsmgr-use-eth_hw_addr_set.patch @@ -0,0 +1,13 @@ +--- a/dtls/v2.0/nss_dtlsmgr_ctx_dev.c ++++ b/dtls/v2.0/nss_dtlsmgr_ctx_dev.c +@@ -532,7 +532,8 @@ void nss_dtlsmgr_ctx_dev_setup(struct ne + #else + dev->priv_destructor = nss_dtlsmgr_ctx_dev_free; + #endif +- memcpy(dev->dev_addr, "\xaa\xbb\xcc\xdd\xee\xff", dev->addr_len); +- memset(dev->broadcast, 0xff, dev->addr_len); ++ const uint8_t mac_addr[ETH_ALEN] = { 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff }; ++ eth_hw_addr_set(dev, mac_addr); ++ eth_broadcast_addr(dev->broadcast); + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); + } diff --git a/qca-nss-clients/patches/0029-dtlsmgr-properly-update-stats.patch b/qca-nss-clients/patches/0029-dtlsmgr-properly-update-stats.patch new file mode 100644 index 0000000..832d35e --- /dev/null +++ b/qca-nss-clients/patches/0029-dtlsmgr-properly-update-stats.patch @@ -0,0 +1,13 @@ +--- a/dtls/v2.0/nss_dtlsmgr_ctx_dev.c ++++ b/dtls/v2.0/nss_dtlsmgr_ctx_dev.c +@@ -236,6 +236,10 @@ void nss_dtlsmgr_ctx_dev_rx_inner(struct + skb->skb_iif = dev->ifindex; + skb->dev = dev; + ++ // Update the statistics ++ stats->rx_packets++; ++ stats->rx_bytes += skb->len; ++ + ctx->data_cb(ctx->app_data, skb); + dev_put(dev); + } diff --git a/qca-nss-clients/patches/0030-fixup-compiler-errors.patch b/qca-nss-clients/patches/0030-fixup-compiler-errors.patch new file mode 100644 index 0000000..ab9aedb --- /dev/null +++ b/qca-nss-clients/patches/0030-fixup-compiler-errors.patch @@ -0,0 +1,473 @@ +--- a/match/nss_match.c ++++ b/match/nss_match.c +@@ -76,9 +76,10 @@ static nss_match_status_t nss_match_veri + * nss_match_sync_callback() + * Sync callback for syncing stats. + */ +-static void nss_match_sync_callback(void *app_data, struct nss_match_msg *nmm) ++static void nss_match_sync_callback(void *app_data, struct nss_cmn_msg *cmm) + { + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); ++ struct nss_match_msg *nmm = (struct nss_match_msg *)cmm; + + switch (nmm->cm.type) { + case NSS_MATCH_STATS_SYNC: +--- a/nss_qdisc/nss_ppe.c ++++ b/nss_qdisc/nss_ppe.c +@@ -348,8 +348,8 @@ static void nss_ppe_queue_disable(struct + /* + * Disable queue enqueue, dequeue and flush the queue. + */ +- fal_qm_enqueue_ctrl_set(0, npq->q.ucast_qid, false); +- fal_scheduler_dequeue_ctrl_set(0, npq->q.ucast_qid, false); ++ fal_qm_enqueue_ctrl_set(0, npq->q.ucast_qid, 0); ++ fal_scheduler_dequeue_ctrl_set(0, npq->q.ucast_qid, 0); + fal_queue_flush(0, port_num, npq->q.ucast_qid); + + nss_qdisc_info("Disable SSDK level0 queue scheduler successful\n"); +@@ -370,8 +370,8 @@ static void nss_ppe_queue_enable(struct + /* + * Enable queue enqueue and dequeue. + */ +- fal_qm_enqueue_ctrl_set(0, npq->q.ucast_qid, true); +- fal_scheduler_dequeue_ctrl_set(0, npq->q.ucast_qid, true); ++ fal_qm_enqueue_ctrl_set(0, npq->q.ucast_qid, 1); ++ fal_scheduler_dequeue_ctrl_set(0, npq->q.ucast_qid, 1); + + nss_qdisc_info("Enable SSDK level0 queue scheduler successful\n"); + } +@@ -535,14 +535,14 @@ static void nss_ppe_all_queue_disable(ui + * Disable queue enqueue, dequeue and flush the queue. + */ + for (offset = 0; offset < nss_ppe_max_get(port_num, NSS_PPE_UCAST_QUEUE); offset++) { +- fal_qm_enqueue_ctrl_set(0, qid + offset, false); +- fal_scheduler_dequeue_ctrl_set(0, qid + offset, false); ++ fal_qm_enqueue_ctrl_set(0, qid + offset, 0); ++ fal_scheduler_dequeue_ctrl_set(0, qid + offset, 0); + fal_queue_flush(0, port_num, qid + offset); + } + + for (offset = 0; offset < nss_ppe_max_get(port_num, NSS_PPE_MCAST_QUEUE); offset++) { +- fal_qm_enqueue_ctrl_set(0, mcast_qid + offset, false); +- fal_scheduler_dequeue_ctrl_set(0, mcast_qid + offset, false); ++ fal_qm_enqueue_ctrl_set(0, mcast_qid + offset, 0); ++ fal_scheduler_dequeue_ctrl_set(0, mcast_qid + offset, 0); + fal_queue_flush(0, port_num, mcast_qid + offset); + } + +@@ -563,13 +563,13 @@ static void nss_ppe_all_queue_enable(uin + * Enable queue enqueue and dequeue. + */ + for (offset = 0; offset < nss_ppe_max_get(port_num, NSS_PPE_UCAST_QUEUE); offset++) { +- fal_qm_enqueue_ctrl_set(0, qid + offset, true); +- fal_scheduler_dequeue_ctrl_set(0, qid + offset, true); ++ fal_qm_enqueue_ctrl_set(0, qid + offset, 1); ++ fal_scheduler_dequeue_ctrl_set(0, qid + offset, 1); + } + + for (offset = 0; offset < nss_ppe_max_get(port_num, NSS_PPE_MCAST_QUEUE); offset++) { +- fal_qm_enqueue_ctrl_set(0, mcast_qid + offset, true); +- fal_scheduler_dequeue_ctrl_set(0, mcast_qid + offset, true); ++ fal_qm_enqueue_ctrl_set(0, mcast_qid + offset, 1); ++ fal_scheduler_dequeue_ctrl_set(0, mcast_qid + offset, 1); + } + + nss_qdisc_info("Enable SSDK level0 queue scheduler successful\n"); +@@ -589,15 +589,15 @@ static void nss_ppe_assigned_queue_enabl + spin_lock_bh(&ppe_port->lock); + res = ppe_port->res_used[NSS_PPE_UCAST_QUEUE]; + while (res) { +- fal_qm_enqueue_ctrl_set(0, qid + res->offset, true); +- fal_scheduler_dequeue_ctrl_set(0, qid + res->offset, true); ++ fal_qm_enqueue_ctrl_set(0, qid + res->offset, (a_bool_t)true); ++ fal_scheduler_dequeue_ctrl_set(0, qid + res->offset, (a_bool_t)true); + res = res->next; + } + + res = ppe_port->res_used[NSS_PPE_MCAST_QUEUE]; + while (res) { +- fal_qm_enqueue_ctrl_set(0, mcast_qid + res->offset, true); +- fal_scheduler_dequeue_ctrl_set(0, mcast_qid + res->offset, true); ++ fal_qm_enqueue_ctrl_set(0, mcast_qid + res->offset, (a_bool_t)true); ++ fal_scheduler_dequeue_ctrl_set(0, mcast_qid + res->offset, (a_bool_t)true); + res = res->next; + } + +@@ -642,7 +642,7 @@ static int nss_ppe_l1_queue_scheduler_co + l1cfg.e_pri = NSS_PPE_PRIORITY_MAX - npq->scheduler.priority; + l1cfg.c_drr_id = npq->l1c_drrid; + l1cfg.e_drr_id = npq->l1e_drrid; +- l1cfg.drr_frame_mode = NSS_PPE_FRAME_CRC; ++ l1cfg.drr_frame_mode = (fal_qos_drr_frame_mode_t)NSS_PPE_FRAME_CRC; + + nss_qdisc_trace("SSDK level1 configuration: Port:%d, l0spid:%d, c_drrid:%d, c_pri:%d, c_drr_wt:%d, e_drrid:%d, e_pri:%d, e_drr_wt:%d, l1spid:%d\n", + port_num, npq->l0spid, l1cfg.c_drr_id, l1cfg.c_pri, l1cfg.c_drr_wt, l1cfg.e_drr_id, l1cfg.e_pri, l1cfg.e_drr_wt, l1cfg.sp_id); +@@ -935,7 +935,7 @@ static int nss_ppe_l0_queue_scheduler_co + l0cfg.e_pri = NSS_PPE_PRIORITY_MAX - npq->scheduler.priority; + l0cfg.c_drr_id = npq->l0c_drrid; + l0cfg.e_drr_id = npq->l0e_drrid; +- l0cfg.drr_frame_mode = NSS_PPE_FRAME_CRC; ++ l0cfg.drr_frame_mode = (fal_qos_drr_frame_mode_t)NSS_PPE_FRAME_CRC; + + nss_qdisc_trace("SSDK level0 configuration: Port:%d, ucast_qid:%d, c_drrid:%d, c_pri:%d, c_drr_wt:%d, e_drrid:%d, e_pri:%d, e_drr_wt:%d, l0spid:%d\n", + port_num, npq->q.ucast_qid, l0cfg.c_drr_id, l0cfg.c_pri, l0cfg.c_drr_wt, l0cfg.e_drr_id, l0cfg.e_pri, l0cfg.e_drr_wt, l0cfg.sp_id); +@@ -1059,7 +1059,7 @@ static int nss_ppe_port_shaper_set(struc + cfg.c_shaper_en = 1; + cfg.cbs = npq->shaper.cburst; + cfg.cir = (npq->shaper.crate / 1000) * 8; +- cfg.shaper_frame_mode = NSS_PPE_FRAME_CRC; ++ cfg.shaper_frame_mode = (fal_shaper_frame_mode_t)NSS_PPE_FRAME_CRC; + + /* + * Take HW scaling into consideration +@@ -1141,7 +1141,7 @@ static int nss_ppe_flow_shaper_set(struc + cfg.e_shaper_en = 1; + cfg.ebs = npq->shaper.cburst; + cfg.eir = ((npq->shaper.crate / 1000) * 8) - cfg.cir; +- cfg.shaper_frame_mode = NSS_PPE_FRAME_CRC; ++ cfg.shaper_frame_mode = (fal_shaper_frame_mode_t)NSS_PPE_FRAME_CRC; + + /* + * Take HW scaling into consideration +@@ -1225,7 +1225,7 @@ static int nss_ppe_queue_shaper_set(stru + cfg.e_shaper_en = 1; + cfg.ebs = npq->shaper.cburst; + cfg.eir = ((npq->shaper.crate / 1000) * 8) - cfg.cir; +- cfg.shaper_frame_mode = NSS_PPE_FRAME_CRC; ++ cfg.shaper_frame_mode = (fal_shaper_frame_mode_t)NSS_PPE_FRAME_CRC; + + /* + * Take HW scaling into consideration +@@ -1293,7 +1293,6 @@ static void nss_ppe_attach_free(uint32_t + spin_unlock_bh(&ppe_port->lock); + + nss_qdisc_info("port:%d, type:%d, res:%px\n", port, res->type, res); +- return; + } + + /* +@@ -2379,7 +2378,7 @@ int nss_ppe_init(struct Qdisc *sch, stru + * nothing useful and thus we don't allocate any resource". + */ + nss_qdisc_trace("Qdisc parent = %px, handle=%x\n", nq->parent, nq->parent->qos_tag); +- if ((nq->parent->npq.sub_type == NSS_SHAPER_CONFIG_PPE_SN_TYPE_HTB)) { ++ if (nq->parent->npq.sub_type == NSS_SHAPER_CONFIG_PPE_SN_TYPE_HTB) { + nq->npq.level = nq->parent->npq.level; + } else { + nq->npq.level = nq->parent->npq.level - 1; +--- a/nss_qdisc/nss_ppe_mc.c ++++ b/nss_qdisc/nss_ppe_mc.c +@@ -32,8 +32,8 @@ int nss_ppe_mcast_queue_reset(struct nss + return 0; + } + +- fal_qm_enqueue_ctrl_set(0, npq->q.mcast_qid, false); +- fal_scheduler_dequeue_ctrl_set(0, npq->q.mcast_qid, false); ++ fal_qm_enqueue_ctrl_set(0, npq->q.mcast_qid, 0); ++ fal_scheduler_dequeue_ctrl_set(0, npq->q.mcast_qid, 0); + fal_queue_flush(0, port_num, npq->q.mcast_qid); + + /* +@@ -153,8 +153,8 @@ int nss_ppe_mcast_queue_set(struct nss_q + } + } + +- fal_qm_enqueue_ctrl_set(0, npq->q.mcast_qid, true); +- fal_scheduler_dequeue_ctrl_set(0, npq->q.mcast_qid, true); ++ fal_qm_enqueue_ctrl_set(0, npq->q.mcast_qid, 1); ++ fal_scheduler_dequeue_ctrl_set(0, npq->q.mcast_qid, 1); + + nss_qdisc_info("SSDK multicast queue configuration successful for port:%d\n", port_num); + return 0; +@@ -164,4 +164,4 @@ fail: + npq->q.mcast_qid = 0; + npq->q.mcast_valid = 0; + return -EINVAL; +-} +\ No newline at end of file ++} +--- a/nss_qdisc/nss_wred.c ++++ b/nss_qdisc/nss_wred.c +@@ -291,7 +291,7 @@ static int nss_wred_change(struct Qdisc + + nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag; + nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.limit = qopt->limit; +- nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.weight_mode = qopt->weight_mode; ++ nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.weight_mode = (nss_shaper_config_wred_weight_mode_t)qopt->weight_mode; + nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.weight_mode_value = qopt->weight_mode_value; + nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.rap.min = qopt->rap.min; + nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.rap.max = qopt->rap.max; +--- a/openvpn/plugins/nss_ovpn_sk.c ++++ b/openvpn/plugins/nss_ovpn_sk.c +@@ -156,7 +156,7 @@ static int nss_ovpn_sk_crypto_key_add(st + return -EFAULT; + } + +- crypto_cfg.algo = crypto_info.config.algo; ++ crypto_cfg.algo = (enum nss_ovpnmgr_algo)crypto_info.config.algo; + crypto_cfg.encrypt.cipher_keylen = crypto_info.config.cipher_key_size; + crypto_cfg.encrypt.hmac_keylen = crypto_info.config.hmac_key_size; + crypto_cfg.decrypt.cipher_keylen = crypto_info.config.cipher_key_size; +@@ -364,7 +364,7 @@ static int nss_ovpn_sk_tun_add(struct so + tun_hdr.dst_port = tun_data.tun_hdr.dst_port; + tun_hdr.hop_limit = tun_data.tun_hdr.hop_limit; + +- crypto_cfg.algo = tun_data.crypto.config.algo; ++ crypto_cfg.algo = (enum nss_ovpnmgr_algo)tun_data.crypto.config.algo; + crypto_cfg.encrypt.cipher_keylen = tun_data.crypto.config.cipher_key_size; + crypto_cfg.encrypt.hmac_keylen = tun_data.crypto.config.hmac_key_size; + crypto_cfg.decrypt.cipher_keylen = tun_data.crypto.config.cipher_key_size; +@@ -442,7 +442,7 @@ static int nss_ovpn_sk_tun_add(struct so + * nss_ovpn_sk_app_dereg() + * Deregister application. + */ +-static int nss_ovpn_sk_app_dereg(struct socket *sock, unsigned long argp) ++static int nss_ovpn_sk_app_dereg(struct socket *sock) + { + struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk; + int ret; +@@ -491,7 +491,7 @@ static int nss_ovpn_sk_app_reg(struct so + return -EFAULT; + } + +- ret = nss_ovpnmgr_app_add(pinfo->dev, app.app_mode, (void *)sock); ++ ret = nss_ovpnmgr_app_add(pinfo->dev, (enum nss_ovpnmgr_app_mode)app.app_mode, (void *)sock); + if (ret) { + nss_ovpn_sk_warn("%px: Failed to register application, pid=%u\n", sock, app.pid); + dev_put(pinfo->dev); +@@ -689,7 +689,7 @@ static int nss_ovpn_sk_recvmsg(struct so + return -EINVAL; + } + +- skb = skb_recv_datagram(sk, flags, MSG_DONTWAIT, &ret); ++ skb = skb_recv_datagram(sk, flags, &ret); + if (!skb) { + nss_ovpn_sk_warn("%px: There are no packets in the queue.\n", sock); + return -ENOBUFS; +@@ -740,7 +740,7 @@ static int nss_ovpn_sk_ioctl(struct sock + case NSS_OVPN_SK_SIOC_APP_REG: + return nss_ovpn_sk_app_reg(sock, argp); + case NSS_OVPN_SK_SIOC_APP_DEREG: +- return nss_ovpn_sk_app_dereg(sock, argp); ++ return nss_ovpn_sk_app_dereg(sock); + case NSS_OVPN_SK_SIOC_TUN_ADD: + return nss_ovpn_sk_tun_add(sock, argp); + case NSS_OVPN_SK_SIOC_TUN_DEL: +@@ -773,15 +773,12 @@ static const struct proto_ops nss_ovpn_s + .ioctl = nss_ovpn_sk_ioctl, + .listen = sock_no_listen, + .shutdown = sock_no_shutdown, +- .getsockopt = sock_no_getsockopt, + .mmap = sock_no_mmap, +- .sendpage = sock_no_sendpage, + .sendmsg = nss_ovpn_sk_sendmsg, + .recvmsg = nss_ovpn_sk_recvmsg, + .poll = datagram_poll, + .bind = sock_no_bind, + .release = nss_ovpn_sk_release, +- .setsockopt = sock_no_setsockopt, + .accept = sock_no_accept, + }; + +--- a/pvxlanmgr/nss_pvxlanmgr.c ++++ b/pvxlanmgr/nss_pvxlanmgr.c +@@ -408,7 +408,7 @@ nss_pvxlanmgr_status_t nss_pvxlanmgr_net + if (ret != NSS_TX_SUCCESS) { + nss_pvxlanmgr_warn("%px: Tunnel disable failed: %d\n", dev, ret); + dev_put(dev); +- return ret; ++ return (nss_pvxlanmgr_status_t)ret; + } + + ret = nss_pvxlanmgr_tunnel_tx_msg_disable(priv->pvxlan_ctx, priv->if_num_outer); +@@ -416,11 +416,11 @@ nss_pvxlanmgr_status_t nss_pvxlanmgr_net + nss_pvxlanmgr_warn("%px: Tunnel disable failed: %d\n", dev, ret); + nss_pvxlanmgr_tunnel_tx_msg_enable(priv->pvxlan_ctx, priv->if_num_host_inner, priv->if_num_outer); + dev_put(dev); +- return ret; ++ return (nss_pvxlanmgr_status_t)ret; + } + + dev_put(dev); +- return ret; ++ return (nss_pvxlanmgr_status_t)ret; + } + EXPORT_SYMBOL(nss_pvxlanmgr_netdev_disable); + +@@ -440,7 +440,7 @@ nss_pvxlanmgr_status_t nss_pvxlanmgr_net + if (ret != NSS_TX_SUCCESS) { + nss_pvxlanmgr_warn("%px: Tunnel enable failed: %d\n", dev, ret); + dev_put(dev); +- return ret; ++ return (nss_pvxlanmgr_status_t)ret; + } + + ret = nss_pvxlanmgr_tunnel_tx_msg_enable(priv->pvxlan_ctx, priv->if_num_outer, priv->if_num_host_inner); +@@ -448,11 +448,11 @@ nss_pvxlanmgr_status_t nss_pvxlanmgr_net + nss_pvxlanmgr_warn("%px: Tunnel enable failed: %d\n", dev, ret); + nss_pvxlanmgr_tunnel_tx_msg_disable(priv->pvxlan_ctx, priv->if_num_host_inner); + dev_put(dev); +- return ret; ++ return (nss_pvxlanmgr_status_t)ret; + } + + dev_put(dev); +- return ret; ++ return (nss_pvxlanmgr_status_t)ret; + } + EXPORT_SYMBOL(nss_pvxlanmgr_netdev_enable); + +@@ -524,7 +524,7 @@ EXPORT_SYMBOL(nss_pvxlanmgr_netdev_destr + * nss_pvxlanmgr_netdev_create() + * API to create a Pvxlan netdev + */ +-struct net_device *nss_pvxlanmgr_netdev_create() ++struct net_device *nss_pvxlanmgr_netdev_create(void) + { + struct nss_pvxlanmgr_priv *priv; + struct net_device *dev; +--- a/pvxlanmgr/nss_pvxlanmgr_tunnel.c ++++ b/pvxlanmgr/nss_pvxlanmgr_tunnel.c +@@ -67,7 +67,7 @@ static inline nss_pvxlanmgr_status_t nss + } + + dev_put(dev); +- return status; ++ return (nss_pvxlanmgr_status_t)status; + } + + /* +@@ -110,7 +110,7 @@ static inline nss_pvxlanmgr_status_t nss + } + + dev_put(dev); +- return status; ++ return (nss_pvxlanmgr_status_t)status; + } + + /* +@@ -138,7 +138,7 @@ static nss_pvxlanmgr_status_t nss_pvxlan + status = nss_pvxlanmgr_tunnel_tx_msg(ctx, &pvxlanmsg, if_num, NSS_PVXLAN_MSG_TYPE_TUNNEL_DESTROY_RULE, sizeof(struct nss_pvxlan_rule_msg)); + if (status != NSS_TX_SUCCESS) { + nss_pvxlanmgr_warn("%px: ctx: create encap data tunnel error %d\n", ctx, status); +- return status; ++ return (nss_pvxlanmgr_status_t)status; + } + + return NSS_PVXLANMGR_SUCCESS; +@@ -169,7 +169,7 @@ static nss_pvxlanmgr_status_t nss_pvxlan + status = nss_pvxlanmgr_tunnel_tx_msg(ctx, &pvxlanmsg, if_num, NSS_PVXLAN_MSG_TYPE_TUNNEL_CREATE_RULE, sizeof(struct nss_pvxlan_rule_msg)); + if (status != NSS_TX_SUCCESS) { + nss_pvxlanmgr_warn("%px: ctx: create encap data tunnel error %d\n", ctx, status); +- return status; ++ return (nss_pvxlanmgr_status_t)status; + } + + return NSS_PVXLANMGR_SUCCESS; +@@ -482,7 +482,7 @@ nss_pvxlanmgr_status_t nss_pvxlanmgr_tun + if_num_outer = priv->if_num_outer; + + status = nss_pvxlanmgr_tunnel_pvxlan_rule_create(priv->pvxlan_ctx, if_num_host_inner, &pvxlan_rule); +- nss_pvxlanmgr_info("%px: dynamic interface if_num is :%d and pvxlan tunnel status:%d\n", dev, if_num_host_inner, status); ++ nss_pvxlanmgr_info("%px: dynamic interface if_num is :%d, if_num_outer :%d, and pvxlan tunnel status:%d\n", dev, if_num_host_inner, if_num_outer, status); + if (status != NSS_PVXLANMGR_SUCCESS) { + nss_pvxlanmgr_warn("%px: %d: PVXLAN rule create failed with status: %d\n", dev, if_num_host_inner, status); + dev_put(dev); +@@ -586,7 +586,7 @@ nss_pvxlanmgr_status_t nss_pvxlanmgr_tun + if_num_outer = priv->if_num_outer; + + status = nss_pvxlanmgr_tunnel_pvxlan_rule_create(priv->pvxlan_ctx, if_num_host_inner, &pvxlan_rule); +- nss_pvxlanmgr_info("%px: dynamic interface if_num is :%d and pvxlan tunnel status:%d\n", dev, if_num_host_inner, status); ++ nss_pvxlanmgr_info("%px: dynamic interface if_num is :%d, if_num_outer :%d, and pvxlan tunnel status:%d\n", dev, if_num_host_inner, if_num_outer, status); + if (status != NSS_PVXLANMGR_SUCCESS) { + nss_pvxlanmgr_warn("%px: %d: PVXLAN rule create failed with status: %d\n", dev, if_num_host_inner, status); + dev_put(dev); +--- a/tls/nss_tlsmgr_crypto.c ++++ b/tls/nss_tlsmgr_crypto.c +@@ -250,7 +250,7 @@ nss_tlsmgr_status_t nss_tlsmgr_crypto_up + status = nss_tls_tx_msg_sync(ctx->nss_ctx, ctx->ifnum, msg_type, sizeof(*ntcu), &ntm); + if (status != NSS_TX_SUCCESS) { + nss_tlsmgr_warn("%px: Failed to configure decap, status:%d, error:%d", ctx, status, ntm.cm.error); +- return false; ++ return (nss_tlsmgr_status_t)false; + } + + /* +@@ -361,7 +361,7 @@ nss_tlsmgr_status_t nss_tlsmgr_crypto_up + if (status != NSS_TX_SUCCESS) { + nss_tlsmgr_crypto_free(crypto); + nss_tlsmgr_warn("%px: Failed to configure decap, status:%d, error:%d", ctx, status, ntm.cm.error); +- return false; ++ return (nss_tlsmgr_status_t)false; + } + + /* +--- a/vlan/nss_vlan_mgr.c ++++ b/vlan/nss_vlan_mgr.c +@@ -448,8 +448,8 @@ static int nss_vlan_mgr_bond_configure_p + /* + * Fields for match + */ +- v->eg_xlt_rule.vsi_valid = true; /* Use vsi as search key*/ +- v->eg_xlt_rule.vsi_enable = true; /* Use vsi as search key*/ ++ v->eg_xlt_rule.vsi_valid = 1; /* Use vsi as search key*/ ++ v->eg_xlt_rule.vsi_enable = 1; /* Use vsi as search key*/ + v->eg_xlt_rule.vsi = vsi; /* Use vsi as search key*/ + v->eg_xlt_rule.s_tagged = 0x7; /* Accept tagged/untagged/priority tagged svlan */ + v->eg_xlt_rule.c_tagged = 0x7; /* Accept tagged/untagged/priority tagged cvlan */ +@@ -612,8 +612,8 @@ static int nss_vlan_mgr_configure_ppe(st + /* + * Fields for match + */ +- v->eg_xlt_rule.vsi_valid = true; /* Use vsi as search key*/ +- v->eg_xlt_rule.vsi_enable = true; /* Use vsi as search key*/ ++ v->eg_xlt_rule.vsi_valid = 1; /* Use vsi as search key*/ ++ v->eg_xlt_rule.vsi_enable = 1; /* Use vsi as search key*/ + v->eg_xlt_rule.vsi = vsi; /* Use vsi as search key*/ + v->eg_xlt_rule.s_tagged = 0x7; /* Accept tagged/untagged/priority tagged svlan */ + v->eg_xlt_rule.c_tagged = 0x7; /* Accept tagged/untagged/priority tagged cvlan */ +@@ -1805,8 +1805,8 @@ void nss_vlan_mgr_add_vlan_rule(struct n + /* + * Fields for match + */ +- eg_xlt_rule.vsi_valid = true; /* Use vsi as search key */ +- eg_xlt_rule.vsi_enable = true; /* Use vsi as search key */ ++ eg_xlt_rule.vsi_valid = 1; /* Use vsi as search key */ ++ eg_xlt_rule.vsi_enable = 1; /* Use vsi as search key */ + eg_xlt_rule.vsi = bridge_vsi; /* Use vsi as search key */ + eg_xlt_rule.s_tagged = 0x7; /* Accept tagged/untagged/priority tagged svlan */ + eg_xlt_rule.c_tagged = 0x7; /* Accept tagged/untagged/priority tagged cvlan */ +@@ -1873,8 +1873,8 @@ void nss_vlan_mgr_del_vlan_rule(struct n + /* + * Fields for match + */ +- eg_xlt_rule.vsi_valid = true; /* Use vsi as search key */ +- eg_xlt_rule.vsi_enable = true; /* Use vsi as search key */ ++ eg_xlt_rule.vsi_valid = 1; /* Use vsi as search key */ ++ eg_xlt_rule.vsi_enable = 1; /* Use vsi as search key */ + eg_xlt_rule.vsi = bridge_vsi; /* Use vsi as search key */ + eg_xlt_rule.s_tagged = 0x7; /* Accept tagged/untagged/priority tagged svlan */ + eg_xlt_rule.c_tagged = 0x7; /* Accept tagged/untagged/priority tagged cvlan */ +--- a/wifi_meshmgr/nss_wifi_meshmgr.c ++++ b/wifi_meshmgr/nss_wifi_meshmgr.c +@@ -1637,9 +1637,6 @@ nss_wifi_meshmgr_config_mesh_exception(n + break; + + case NSS_WIFI_MESH_US_MESH_PROXY_NOT_FOUND: +- ifnum = decap_ifnum; +- break; +- + case NSS_WIFI_MESH_US_MESH_PATH_NOT_FOUND: + ifnum = decap_ifnum; + break; +--- a/netlink/nss_nlipsec.c ++++ b/netlink/nss_nlipsec.c +@@ -228,7 +228,7 @@ static void nss_nlipsec_process_event(vo + /* + * Initialize the NETLINK common header + */ +- nss_nlipsec_rule_init(nl_rule, ev->type); ++ nss_nlipsec_rule_init(nl_rule, (enum nss_nlipsec_cmd)ev->type); + + /* + * Copy the contents of the sync message into the NETLINK message diff --git a/qca-nss-clients/patches/0031-kernel-6.12-support.patch b/qca-nss-clients/patches/0031-kernel-6.12-support.patch new file mode 100644 index 0000000..e9b110d --- /dev/null +++ b/qca-nss-clients/patches/0031-kernel-6.12-support.patch @@ -0,0 +1,875 @@ +--- a/Makefile ++++ b/Makefile +@@ -10,6 +10,9 @@ qca-nss-tun6rd-objs := nss_connmgr_tun6r + ccflags-y += -DNSS_TUN6RD_DEBUG_LEVEL=0 + ccflags-y += -Wall -Werror + ++# Kernel 6.12 compatibility ++ccflags-y += -Wno-missing-prototypes -include $(src)/compat.h ++ + KERNELVERSION := $(word 1, $(subst ., ,$(KERNELVERSION))).$(word 2, $(subst ., ,$(KERNELVERSION))) + + obj-$(bridge-mgr)+= bridge/ +--- a/bridge/nss_bridge_mgr.c ++++ b/bridge/nss_bridge_mgr.c +@@ -1486,7 +1486,7 @@ static struct notifier_block nss_bridge_ + * nss_bridge_mgr_wan_inf_add_handler + * Marks an interface as a WAN interface for special handling by bridge. + */ +-static int nss_bridge_mgr_wan_intf_add_handler(struct ctl_table *table, ++static int nss_bridge_mgr_wan_intf_add_handler(compat_const struct ctl_table *table, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -1535,7 +1535,7 @@ static int nss_bridge_mgr_wan_intf_add_h + * nss_bridge_mgr_wan_inf_del_handler + * Un-marks an interface as a WAN interface. + */ +-static int nss_bridge_mgr_wan_intf_del_handler(struct ctl_table *table, ++static int nss_bridge_mgr_wan_intf_del_handler(compat_const struct ctl_table *table, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -1593,8 +1593,7 @@ static struct ctl_table nss_bridge_mgr_t + .maxlen = sizeof(char) * IFNAMSIZ, + .mode = 0644, + .proc_handler = &nss_bridge_mgr_wan_intf_del_handler, +- }, +- { } ++ } + }; + + /* +--- a/dtls/v2.0/nss_dtlsmgr_ctx_dev.c ++++ b/dtls/v2.0/nss_dtlsmgr_ctx_dev.c +@@ -284,7 +284,11 @@ void nss_dtlsmgr_ctx_dev_rx_outer(struct + skb_set_transport_header(skb, sizeof(struct iphdr)); + + iph = ip_hdr(skb); ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + nss_dtlsmgr_warn("%px: No IPv4 route or out dev", dev); + dev_kfree_skb_any(skb); +--- a/gre/nss_connmgr_gre.c ++++ b/gre/nss_connmgr_gre.c +@@ -40,6 +40,12 @@ + #define MAX_RETRY_COUNT 100 + #define MAX_WIFI_HEADROOM 66 + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 10, 0) ++#define TUNNEL_CSUM IP_TUNNEL_CSUM_BIT ++#define TUNNEL_SEQ IP_TUNNEL_SEQ_BIT ++#define TUNNEL_KEY IP_TUNNEL_KEY_BIT ++#endif ++ + /* + * GRE connection manager context structure + */ +@@ -186,7 +192,12 @@ static int nss_connmgr_gre_dev_init(stru + if ((dev->priv_flags_ext & IFF_EXT_GRE_V4_TAP) || (dev->type == ARPHRD_IPGRE)) { + dev->needed_headroom = sizeof(struct iphdr) + sizeof(struct ethhdr) + MAX_WIFI_HEADROOM + append; + dev->mtu = ETH_DATA_LEN - sizeof(struct iphdr) - append; ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA; ++#else ++ dev->features |= NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA; ++ dev->netns_local = true; ++#endif + dev->hw_features |= NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA; + return 0; + } +@@ -200,7 +211,11 @@ static int nss_connmgr_gre_dev_init(stru + dev->mtu = IPV6_MIN_MTU; + } + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + dev->features |= NETIF_F_NETNS_LOCAL; ++#else ++ dev->netns_local = true; ++#endif + return 0; + } + +@@ -211,7 +226,6 @@ static int nss_connmgr_gre_dev_init(stru + static void nss_connmgr_gre_dev_uninit(struct net_device *dev) + { + free_percpu(dev->tstats); +- return; + } + + /* +@@ -578,7 +592,6 @@ static void nss_connmgr_gre_tap_inner_ex + */ + skb->protocol = eth_type_trans(skb, dev); + netif_receive_skb(skb); +- return; + } + + /* +@@ -724,10 +737,10 @@ static void nss_connmgr_gre_make_name(st + { + switch (cfg->mode) { + case GRE_MODE_TUN: +- strlcpy(name, "tun-%d", IFNAMSIZ); ++ strscpy(name, "tun-%d", IFNAMSIZ); + break; + case GRE_MODE_TAP: +- strlcpy(name, "tap-%d", IFNAMSIZ); ++ strscpy(name, "tap-%d", IFNAMSIZ); + break; + default: + break; +@@ -757,7 +770,7 @@ static struct net_device *__nss_connmgr_ + int ret = -1, retry, next_if_num_inner = 0, next_if_num_outer = 0; + + if (cfg->name) { +- strlcpy(name, cfg->name, IFNAMSIZ); ++ strscpy(name, cfg->name, IFNAMSIZ); + } else { + nss_connmgr_gre_make_name(cfg, name); + } +--- a/gre/nss_connmgr_gre_v4.c ++++ b/gre/nss_connmgr_gre_v4.c +@@ -45,7 +45,11 @@ static struct net_device *nss_connmgr_gr + struct net_device *dev; + uint32_t ip_addr __attribute__ ((unused)) = ntohl(dest_ip); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, htonl(dest_ip), 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, htonl(dest_ip), 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + nss_connmgr_gre_warning("Unable to lookup route for %pI4\n", &ip_addr); + return NULL; +@@ -87,7 +91,11 @@ static int nss_connmgr_gre_v4_get_mac_ad + dev_put(local_dev); + nss_connmgr_gre_info("Src MAC address for %pI4 is %pM\n", &laddr, src_mac); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, raddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, raddr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + nss_connmgr_gre_warning("route look up failed for %pI4\n", &raddr); + return GRE_ERR_RADDR_ROUTE_LOOKUP; +@@ -216,9 +224,9 @@ int nss_connmgr_gre_v4_set_config(struct + t->parms.o_key = cfg->okey; + } + +- nss_connmgr_gre_set_gre_flags(cfg, &t->parms.o_flags, &t->parms.i_flags); ++ nss_connmgr_gre_set_gre_flags(cfg, (uint16_t *)&t->parms.o_flags, (uint16_t *)&t->parms.i_flags); + +- strlcpy(t->parms.name, dev->name, IFNAMSIZ); ++ strscpy(t->parms.name, dev->name, IFNAMSIZ); + t->dev = dev; + return GRE_SUCCESS; + } +@@ -330,8 +338,13 @@ int nss_connmgr_gre_v4_get_config(struct + memcpy(cmsg->src_ip, &src_ip, 4); + memcpy(cmsg->dest_ip, &dest_ip, 4); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + cmsg->flags |= nss_connmgr_gre_get_nss_config_flags(t->parms.o_flags, + t->parms.i_flags, ++#else ++ cmsg->flags |= nss_connmgr_gre_get_nss_config_flags(*t->parms.o_flags, ++ *t->parms.i_flags, ++#endif + iphdr->tos, iphdr->ttl, + iphdr->frag_off); + +--- a/ipsecmgr/v1.0/nss_ipsecmgr.c ++++ b/ipsecmgr/v1.0/nss_ipsecmgr.c +@@ -526,7 +526,11 @@ static struct net_device *nss_ipsecmgr_t + } + + if (!is_encap) { ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph->saddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph->saddr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + return NULL; + } +--- a/ipsecmgr/v1.0/nss_ipsecmgr_flow.c ++++ b/ipsecmgr/v1.0/nss_ipsecmgr_flow.c +@@ -915,7 +915,11 @@ bool nss_ipsecmgr_flow_process_pmtu(stru + if (unlikely(skb_dst(skb))) + goto send_icmp; + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, ip_hdr(skb)->daddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, ip_hdr(skb)->daddr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + return false; + } +--- a/ipsecmgr/v2.0/nss_ipsecmgr_ctx.c ++++ b/ipsecmgr/v2.0/nss_ipsecmgr_ctx.c +@@ -230,7 +230,11 @@ static void nss_ipsecmgr_ctx_notify_ipv4 + * flow that coming in for the first time. We should query + * the Linux to see the associated NETDEV + */ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph->saddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph->saddr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + dev_kfree_skb_any(skb); + ctx->hstats.v4_notify_drop++; +@@ -258,7 +262,11 @@ static void nss_ipsecmgr_ctx_route_ipv4( + struct iphdr *iph = ip_hdr(skb); + struct rtable *rt; + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_ipsecmgr_warn("%pK: No route, drop packet.\n", skb); + dev_kfree_skb_any(skb); +--- a/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.c ++++ b/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.c +@@ -149,7 +149,11 @@ static void nss_ipsec_xfrm_tunnel_rx_out + if (ip_hdr(skb)->version == IPVERSION) { + struct iphdr *iph = ip_hdr(skb); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + struct rtable *rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0); ++#else ++ struct rtable *rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_ipsec_xfrm_warn("%px: Failed to handle ipv4 exception after encap; No route\n", skb); + goto drop; +@@ -285,7 +289,11 @@ struct nss_ipsec_xfrm_tunnel *nss_ipsec_ + + switch (family) { + case AF_INET: ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, remote->a4, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, remote->a4, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + nss_ipsec_xfrm_err("%p:Failed to allocate tunnel; No IPv4 dst found\n", drv); + return NULL; +--- a/l2tp/l2tpv2/nss_connmgr_l2tpv2.c ++++ b/l2tp/l2tpv2/nss_connmgr_l2tpv2.c +@@ -319,7 +319,7 @@ static struct nss_connmgr_l2tpv2_session + */ + dev_hold(dev); + l2tpv2_session_data->dev = dev; +- strlcpy(session->ifname, dev->name, IFNAMSIZ); ++ strscpy(session->ifname, dev->name, IFNAMSIZ); + + /* + * There is no need for protecting simultaneous addition & +@@ -417,7 +417,11 @@ static void nss_connmgr_l2tpv2_exception + /* + * set skb_iif + */ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph_inner->saddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph_inner->saddr, 0, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_connmgr_l2tpv2_warning("Martian packets !!!"); + } else { +@@ -859,7 +863,7 @@ EXPORT_SYMBOL(l2tpmgr_unregister_ipsecmg + * nss_connmgr_l2tpv2_proc_handler() + * Read and write handler for sysctl. + */ +-static int nss_connmgr_l2tpv2_proc_handler(struct ctl_table *ctl, ++static int nss_connmgr_l2tpv2_proc_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -979,8 +983,7 @@ static struct ctl_table nss_connmgr_l2tp + .maxlen = L2TP_SYSCTL_STR_LEN_MAX, + .mode = 0644, + .proc_handler = &nss_connmgr_l2tpv2_proc_handler, +- }, +- { } ++ } + }; + + /* +@@ -991,8 +994,7 @@ static struct ctl_table nss_connmgr_l2tp + .procname = "l2tpv2", + .mode = 0555, + .child = nss_connmgr_l2tpv2_table, +- }, +- { } ++ } + }; + + /* +@@ -1003,8 +1005,7 @@ static struct ctl_table nss_connmgr_l2tp + .procname = "nss", + .mode = 0555, + .child = nss_connmgr_l2tpv2_dir, +- }, +- { } ++ } + }; + #endif + +--- a/l2tp/l2tpv2/nss_l2tpv2_stats.c ++++ b/l2tp/l2tpv2/nss_l2tpv2_stats.c +@@ -129,7 +129,11 @@ void nss_l2tpv2_update_dev_stats(struct + dev_put(dev); + return; + } ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) + session = l2tp_tunnel_get_session(tunnel, data.l2tpv2.session.session_id); ++#else ++ session = l2tp_v2_session_get(dev_net(dev), data.l2tpv2.tunnel.tunnel_id, data.l2tpv2.session.session_id); ++#endif + if (!session) { + tunnel_put(tunnel); + dev_put(dev); +--- a/match/nss_match_cmd.c ++++ b/match/nss_match_cmd.c +@@ -124,7 +124,7 @@ static enum nss_match_profile_type nss_m + * nss_match_cmd_procfs_config_handler() + * Handles command input by user to create and configure match instance. + */ +-static int nss_match_cmd_procfs_config_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_match_cmd_procfs_config_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + char *command_str, *token, *param, *value; + char *input_msg, *input_msg_orig; +@@ -451,7 +451,7 @@ fail: + * nss_match_cmd_procfs_reset_nexthop + * Reset to default nexthop of an interface + */ +-static int nss_match_cmd_procfs_reset_nexthop(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_match_cmd_procfs_reset_nexthop(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct net_device *dev; + uint32_t if_num, type = 0; +@@ -521,7 +521,7 @@ static int nss_match_cmd_procfs_reset_ne + * Set next hop of an interface to a match instance. + * Only VAP and physical interfaces are supported as of now. + */ +-static int nss_match_cmd_procfs_set_if_nexthop(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_match_cmd_procfs_set_if_nexthop(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct net_device *dev; + uint32_t if_num, type = 0; +@@ -632,7 +632,7 @@ static int nss_match_cmd_procfs_set_if_n + * nss_match_cmd_procfs_read_help() + * Display help for commands. + */ +-static int nss_match_cmd_procfs_read_help(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_match_cmd_procfs_read_help(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret = proc_dointvec(ctl, write, buffer, lenp, ppos); + +@@ -688,8 +688,7 @@ static struct ctl_table nss_match_table[ + .maxlen = sizeof(nss_match_data), + .mode = 0400, + .proc_handler = &nss_match_cmd_procfs_read_help, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_match_ctl_header; +--- a/mirror/nss_mirror_ctl.c ++++ b/mirror/nss_mirror_ctl.c +@@ -132,7 +132,7 @@ static int nss_mirror_ctl_get_netdev_by_ + { + char dev_name[IFNAMSIZ] = {0}; + +- strlcpy(dev_name, name, IFNAMSIZ); ++ strscpy(dev_name, name, IFNAMSIZ); + if (dev_name[strlen(dev_name) - 1] == '\n') { + dev_name[strlen(dev_name) - 1] = '\0'; + } +@@ -357,7 +357,7 @@ static int nss_mirror_ctl_parse_display_ + return -1; + } + +- strlcpy(dev_name, value, IFNAMSIZ); ++ strscpy(dev_name, value, IFNAMSIZ); + if (dev_name[strlen(dev_name) - 1] == '\n') { + dev_name[strlen(dev_name) - 1] = '\0'; + } +@@ -754,7 +754,7 @@ static int32_t nss_mirror_ctl_parse_cmd( + * nss_mirror_ctl_config_handler() + * Mirror sysctl config handler. + */ +-static int nss_mirror_ctl_config_handler(struct ctl_table *ctl, int write, ++static int nss_mirror_ctl_config_handler(compat_const struct ctl_table *ctl, int write, + void __user *buf, size_t *lenp, loff_t *ppos) + { + char *buffer, *pfree; +@@ -914,8 +914,7 @@ static struct ctl_table nss_mirror_table + .maxlen = sizeof(nss_mirror_config_data), + .mode = 0644, + .proc_handler = &nss_mirror_ctl_config_handler, +- }, +- { } ++ } + }; + + /* +--- a/netlink/nss_nlipv4.c ++++ b/netlink/nss_nlipv4.c +@@ -129,7 +129,11 @@ static struct neighbour *nss_nlipv4_get_ + /* + * search for route entry + */ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, ip_addr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, ip_addr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + return NULL; + } +--- a/netlink/nss_nludp_st.c ++++ b/netlink/nss_nludp_st.c +@@ -749,7 +749,11 @@ static struct neighbour *nss_nludp_st_ge + /* + * search for route entry + */ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, ip_addr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, ip_addr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + return NULL; + } +--- a/nss_qdisc/nss_bf.c ++++ b/nss_qdisc/nss_bf.c +@@ -381,7 +381,11 @@ static int nss_bf_graft_class(struct Qdi + */ + nss_qdisc_info("Grafting old: %px with new: %px\n", *old, new); + if (*old != &noop_qdisc) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 8, 0) + struct nss_qdisc *nq_old = (struct nss_qdisc *)qdisc_priv(*old); ++#else ++ struct nss_qdisc *nq_old = (struct nss_qdisc *)qdisc_priv(((struct Qdisc *)(*old))); ++#endif + nss_qdisc_info("Detaching old: %px\n", *old); + nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag; + if (nss_qdisc_node_detach(&cl->nq, nq_old, &nim_detach, +--- a/nss_qdisc/nss_qdisc.c ++++ b/nss_qdisc/nss_qdisc.c +@@ -374,7 +374,9 @@ static int nss_qdisc_refresh_bshaper_ass + br_update.port_list_count = 0; + br_update.unassign_count = 0; + +- read_lock(&dev_base_lock); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0)) ++ read_lock(&dev_base_lock); ++#endif + dev = first_net_device(&init_net); + + while(dev) { +@@ -421,7 +423,10 @@ static int nss_qdisc_refresh_bshaper_ass + nextdev: + dev = next_net_device(dev); + } +- read_unlock(&dev_base_lock); ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0)) ++ read_unlock(&dev_base_lock); ++#endif + + nss_qdisc_info("List count %d\n", br_update.port_list_count); + +--- a/nss_qdisc/nss_tbl.c ++++ b/nss_qdisc/nss_tbl.c +@@ -350,7 +350,11 @@ static int nss_tbl_graft(struct Qdisc *s + + nss_qdisc_info("Grafting old: %px with new: %px\n", *old, new); + if (*old != &noop_qdisc) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 8, 0) + struct nss_qdisc *nq_old = (struct nss_qdisc *)qdisc_priv(*old); ++#else ++ struct nss_qdisc *nq_old = (struct nss_qdisc *)qdisc_priv(((struct Qdisc *)(*old))); ++#endif + nss_qdisc_info("Detaching old: %px\n", *old); + nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag; + if (nss_qdisc_node_detach(&q->nq, nq_old, &nim_detach, +--- a/openvpn/plugins/nss_ovpn_sk.c ++++ b/openvpn/plugins/nss_ovpn_sk.c +@@ -225,7 +225,11 @@ static int nss_ovpn_sk_update_ipv4_tuple + { + struct rtable *rt; + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(dev_net(pinfo->dev), tun_data->tun_hdr.dst_ip[0], 0, 0, 0); ++#else ++ rt = ip_route_output(dev_net(pinfo->dev), tun_data->tun_hdr.dst_ip[0], 0, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_ovpn_sk_warn("%px: Failed to find IPv4 route.\n", pinfo); + return -EINVAL; +--- a/openvpn/src/nss_ovpnmgr_tun.c ++++ b/openvpn/src/nss_ovpnmgr_tun.c +@@ -69,7 +69,11 @@ static void nss_ovpnmgr_tun_ipv4_forward + skb_reset_network_header(skb); + iph = ip_hdr(skb); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(dev_net(app->dev), iph->daddr, iph->saddr, 0, 0); ++#else ++ rt = ip_route_output(dev_net(app->dev), iph->daddr, iph->saddr, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_ovpnmgr_warn("%px: Failed to find IPv4 route.\n", skb); + tun->outer.stats.host_pkt_drop++; +--- a/openvpn/src/nss_ovpnmgr_app.c ++++ b/openvpn/src/nss_ovpnmgr_app.c +@@ -51,7 +51,11 @@ static struct net_device *nss_ovpnmgr_ap + struct rtable *rt4; + + if (rt->ip_version == IPVERSION) { ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt4 = ip_route_output(&init_net, rt->ip_addr[0], 0, 0, 0); ++#else ++ rt4 = ip_route_output(&init_net, rt->ip_addr[0], 0, 0, 0, 0); ++#endif + if (IS_ERR(rt4)) { + return NULL; + } +--- a/tunipip6/nss_connmgr_tunipip6.c ++++ b/tunipip6/nss_connmgr_tunipip6.c +@@ -174,7 +174,11 @@ static void nss_tunipip6_encap_exception + nss_tunipip6_info("%px: received - %d bytes name %s ver %x\n", + skb, skb->len, dev->name, iph->version); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph->daddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph->daddr, 0, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_tunipip6_info("%px: Failed to find IPv4 route for dest %pI4 src %pI4\n", skb, &iph->daddr, &iph->saddr); + dev_kfree_skb_any(skb); +@@ -284,7 +288,11 @@ static void nss_tunipip6_decap_exception + iph = ip_hdr(skb); + nss_tunipip6_assert(iph->version == 4); + ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, iph->daddr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, iph->daddr, 0, 0, 0, 0); ++#endif + if (unlikely(IS_ERR(rt))) { + nss_tunipip6_info("%px: Failed to find IPv4 route for %pI4\n", skb, &iph->daddr); + dev_kfree_skb_any(skb); +--- a/tunipip6/nss_connmgr_tunipip6_sysctl.c ++++ b/tunipip6/nss_connmgr_tunipip6_sysctl.c +@@ -52,7 +52,7 @@ enum nss_tunipip6_sysctl_mode { + }; + + +-static int nss_tunipip6_data_parser(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos, enum nss_tunipip6_sysctl_mode mode) ++static int nss_tunipip6_data_parser(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos, enum nss_tunipip6_sysctl_mode mode) + { + char dev_name[NETDEV_STR_LEN] = {0}, ipv6_prefix_str[PREFIX_STR_LEN] = {0}, ipv6_suffix_str[PREFIX_STR_LEN] = {0}, ipv4_prefix_str[PREFIX_STR_LEN] = {0}; + uint32_t ipv6_prefix[4], ipv6_prefix_len, ipv6_suffix[4], ipv6_suffix_len, ipv4_prefix, ipv4_prefix_len, ea_len, psid_offset; +@@ -108,7 +108,7 @@ static int nss_tunipip6_data_parser(stru + */ + + if (!strcmp(param, "netdev")) { +- strlcpy(dev_name, value, 30); ++ strscpy(dev_name, value, 30); + dev = dev_get_by_name(&init_net, dev_name); + if (!dev) { + kfree(pfree); +@@ -147,7 +147,7 @@ static int nss_tunipip6_data_parser(stru + } + + if (!strcmp(param, "ipv4_prefix")) { +- strlcpy(ipv4_prefix_str, value, 30); ++ strscpy(ipv4_prefix_str, value, 30); + ret = in4_pton(ipv4_prefix_str, -1, (uint8_t *)&ipv4_prefix, -1, NULL); + if (ret != 1) { + kfree(pfree); +@@ -173,7 +173,7 @@ static int nss_tunipip6_data_parser(stru + } + + if (!strcmp(param, "ipv6_prefix")) { +- strlcpy(ipv6_prefix_str, value, 100); ++ strscpy(ipv6_prefix_str, value, 100); + ret = in6_pton(ipv6_prefix_str, -1, (uint8_t *)&ipv6_prefix, -1, NULL); + if (ret != 1) { + kfree(pfree); +@@ -199,7 +199,7 @@ static int nss_tunipip6_data_parser(stru + } + + if (!strcmp(param, "ipv6_suffix")) { +- strlcpy(ipv6_suffix_str, value, 100); ++ strscpy(ipv6_suffix_str, value, 100); + ret = in6_pton(ipv6_suffix_str, -1, (uint8_t *)&ipv6_suffix, -1, NULL); + if (ret != 1) { + kfree(pfree); +@@ -368,27 +368,27 @@ fail: + return 0; + } + +-static int nss_tunipip6_cmd_procfs_add_maprule(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_tunipip6_cmd_procfs_add_maprule(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + return nss_tunipip6_data_parser(ctl, write, buffer, lenp, ppos, NSS_TUNIPIP6_SYSCTL_ADD_MAPRULE); + } + +-static int nss_tunipip6_cmd_procfs_del_maprule(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_tunipip6_cmd_procfs_del_maprule(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + return nss_tunipip6_data_parser(ctl, write, buffer, lenp, ppos, NSS_TUNIPIP6_SYSCTL_DEL_MAPRULE); + } + +-static int nss_tunipip6_cmd_procfs_flush_fmr_rule(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_tunipip6_cmd_procfs_flush_fmr_rule(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + return nss_tunipip6_data_parser(ctl, write, buffer, lenp, ppos, NSS_TUNIPIP6_SYSCTL_FLUSH_FMR_RULE); + } + +-static int nss_tunipip6_cmd_procfs_enable_frag_id(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_tunipip6_cmd_procfs_enable_frag_id(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + return nss_tunipip6_data_parser(ctl, write, buffer, lenp, ppos, NSS_TUNIPIP6_SYSCTL_FRAG_ID); + } + +-static int nss_tunipip6_cmd_procfs_read_help(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_tunipip6_cmd_procfs_read_help(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret = proc_dointvec(ctl, write, buffer, lenp, ppos); + +@@ -445,8 +445,7 @@ static struct ctl_table nss_tunipip6_tab + .maxlen = sizeof(nss_tunipip6_data), + .mode = 0400, + .proc_handler = &nss_tunipip6_cmd_procfs_read_help, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_tunipip6_ctl_header; +--- a/vlan/nss_vlan_mgr.c ++++ b/vlan/nss_vlan_mgr.c +@@ -1549,7 +1549,7 @@ static int nss_vlan_mgr_update_ppe_tpid( + * nss_vlan_mgr_tpid_proc_handler() + * Sets customer TPID and service TPID + */ +-static int nss_vlan_mgr_tpid_proc_handler(struct ctl_table *ctl, ++static int nss_vlan_mgr_tpid_proc_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -1577,8 +1577,7 @@ static struct ctl_table nss_vlan_table[] + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_vlan_mgr_tpid_proc_handler, +- }, +- { } ++ } + }; + + /* +--- a/nss_qdisc/nss_htb.c ++++ b/nss_qdisc/nss_htb.c +@@ -642,7 +642,11 @@ static int nss_htb_graft_class(struct Qd + nss_qdisc_info("grafting old: %x with new: %x\n", (*old)->handle, new->handle); + if (*old != &noop_qdisc) { + nss_qdisc_trace("detaching old: %x\n", (*old)->handle); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) + nq_old = qdisc_priv(*old); ++#else ++ nq_old = qdisc_priv(((struct Qdisc *)(*old))); ++#endif + nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag; + nim_detach.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_detach.child_qos_tag = nq_old->qos_tag; + if (nss_qdisc_node_detach(&cl->nq, nq_old, &nim_detach, +--- a/nss_qdisc/nss_wrr.c ++++ b/nss_qdisc/nss_wrr.c +@@ -488,7 +488,11 @@ static int nss_wrr_graft_class(struct Qd + */ + nss_qdisc_info("Grafting old: %px with new: %px\n", *old, new); + if (*old != &noop_qdisc) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 8, 0) + struct nss_qdisc *nq_child = qdisc_priv(*old); ++#else ++ struct nss_qdisc *nq_child = qdisc_priv(((struct Qdisc *)(*old))); ++#endif + nss_qdisc_info("Detaching old: %px\n", *old); + nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag; + if (nss_qdisc_node_detach(&cl->nq, nq_child, &nim_detach, +--- a/gre/test/nss_connmgr_gre_test.c ++++ b/gre/test/nss_connmgr_gre_test.c +@@ -143,7 +143,7 @@ static ssize_t nss_connmgr_gre_test_writ + * parameter parsing for delete command + */ + if (!strcmp(param, "dev")) { +- strlcpy(dev_name, value, IFNAMSIZ); ++ strscpy(dev_name, value, IFNAMSIZ); + dev_name_valid = true; + break; + } +@@ -153,19 +153,19 @@ static ssize_t nss_connmgr_gre_test_writ + * tap create command + */ + if (!strcmp(param, "next_dev")) { +- strlcpy(dev_name, value, IFNAMSIZ); ++ strscpy(dev_name, value, IFNAMSIZ); + dev_name_valid = true; + continue; + } + + if (!strcmp(param, "saddr")) { +- strlcpy(saddr, value, 20); ++ strscpy(saddr, value, 20); + saddr_valid = true; + continue; + } + + if (!strcmp(param, "daddr")) { +- strlcpy(daddr, value, 20); ++ strscpy(daddr, value, 20); + daddr_valid = true; + continue; + } +--- a/clmapmgr/nss_clmapmgr.c ++++ b/clmapmgr/nss_clmapmgr.c +@@ -185,7 +185,7 @@ static void nss_clmapmgr_setup(struct ne + { + char name[IFNAMSIZ] = {0}; + +- strlcpy(name, "nssclmap%d", IFNAMSIZ); ++ strscpy(name, "nssclmap%d", IFNAMSIZ); + memcpy(dev->name, name, IFNAMSIZ); + dev->netdev_ops = &nss_clmapmgr_ops; + eth_hw_addr_random(dev); +--- a/portifmgr/nss_portifmgr.c ++++ b/portifmgr/nss_portifmgr.c +@@ -266,7 +266,7 @@ struct net_device *nss_portifmgr_create_ + ndev->vlan_features |= NSS_PORTIFMGR_SUPPORTED_FEATURES; + ndev->wanted_features |= NSS_PORTIFMGR_SUPPORTED_FEATURES; + ndev->mtu = real_dev->mtu - NSS_PORTIFMGR_EXTRA_HEADER_SIZE; +- strlcpy(ndev->name, name, IFNAMSIZ); ++ strscpy(ndev->name, name, IFNAMSIZ); + + /* + * Setup temp mac address, this can be changed with ifconfig later +--- a/profiler/profile.c ++++ b/profiler/profile.c +@@ -138,7 +138,7 @@ int profile_register_performance_counter + } + + profile_counter[i] = counter; +- strlcpy(profile_name[i], name, PROFILE_COUNTER_NAME_LENGTH); ++ strscpy(profile_name[i], name, PROFILE_COUNTER_NAME_LENGTH); + profile_name[i][PROFILE_COUNTER_NAME_LENGTH - 1] = 0; + + return 1; +@@ -317,7 +317,7 @@ static int profile_make_stats_packet(cha + counter_ptr = (struct profile_counter *)ptr; + for (n = 0; n < profile_num_counters; ++n) { + counter_ptr->value = htonl(*profile_counter[n]); +- strlcpy(counter_ptr->name, profile_name[n], ++ strscpy(counter_ptr->name, profile_name[n], + PROFILE_COUNTER_NAME_LENGTH); + counter_ptr++; + } +--- a/gre/nss_connmgr_gre_v6.c ++++ b/gre/nss_connmgr_gre_v6.c +@@ -322,9 +322,9 @@ int nss_connmgr_gre_v6_set_config(struct + t->parms.o_key = cfg->okey; + } + +- nss_connmgr_gre_set_gre_flags(cfg, &t->parms.o_flags, &t->parms.i_flags); ++ nss_connmgr_gre_set_gre_flags(cfg, (uint16_t *)&t->parms.o_flags, (uint16_t *)&t->parms.i_flags); + +- strlcpy(t->parms.name, dev->name, IFNAMSIZ); ++ strscpy(t->parms.name, dev->name, IFNAMSIZ); + t->dev = dev; + return GRE_SUCCESS; + } +@@ -359,8 +359,13 @@ int nss_connmgr_gre_v6_get_config(struct + /* + * IPv6 outer tos field is always inherited from inner IP header. + */ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 10, 0) + cmsg->flags |= nss_connmgr_gre_get_nss_config_flags(t->parms.o_flags, + t->parms.i_flags, ++#else ++ cmsg->flags |= nss_connmgr_gre_get_nss_config_flags(*t->parms.o_flags, ++ *t->parms.i_flags, ++#endif + t->parms.flowinfo, + t->parms.hop_limit, 0); + +--- /dev/null ++++ b/compat.h +@@ -0,0 +1,15 @@ ++// compat.h ++#ifndef _COMPAT_H ++#define _COMPAT_H ++ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 10, 0) ++#include ++#define compat_const const ++#define strlcpy strscpy ++#else ++#define compat_const ++#endif ++ ++#endif /* _COMPAT_H */ +--- a/nss_qdisc/nss_prio.c ++++ b/nss_qdisc/nss_prio.c +@@ -341,7 +341,11 @@ static int nss_prio_graft(struct Qdisc * + + nss_qdisc_info("Grafting old: %px with new: %px\n", *old, new); + if (*old != &noop_qdisc) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 8, 0) + struct nss_qdisc *nq_old = qdisc_priv(*old); ++#else ++ struct nss_qdisc *nq_old = qdisc_priv(((struct Qdisc *)(*old))); ++#endif + nss_qdisc_info("Detaching old: %px\n", *old); + nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag; + +--- a/netlink/nss_nldtls.c ++++ b/netlink/nss_nldtls.c +@@ -1108,7 +1108,7 @@ static ssize_t nss_nldtls_tunnel_stats_r + list_for_each_entry(entry, &gbl_ctx.dtls_list_head, list) { + spin_lock_bh(&gbl_ctx.lock); + memcpy(&stats, &entry->stats, sizeof(stats)); +- strlcpy(dev_name, entry->dev_name, IFNAMSIZ); ++ strscpy(dev_name, entry->dev_name, IFNAMSIZ); + spin_unlock_bh(&gbl_ctx.lock); + + size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n--------------------------------"); +--- a/netlink/nss_nlipsec.c ++++ b/netlink/nss_nlipsec.c +@@ -394,7 +394,7 @@ static int nss_nlipsec_op_create_tunnel( + * the tunnel I/F name into the same rule and send it + * as part of the response for the create operation + */ +- strlcpy(nl_rule->ifname, dev->name, IFNAMSIZ); ++ strscpy(nl_rule->ifname, dev->name, IFNAMSIZ); + + /* + * Send to userspace diff --git a/qca-nss-clients/patches/0032-match-fix-procfs-read-write.patch b/qca-nss-clients/patches/0032-match-fix-procfs-read-write.patch new file mode 100644 index 0000000..3361a95 --- /dev/null +++ b/qca-nss-clients/patches/0032-match-fix-procfs-read-write.patch @@ -0,0 +1,406 @@ +--- a/match/nss_match_cmd.c ++++ b/match/nss_match_cmd.c +@@ -127,29 +127,30 @@ static enum nss_match_profile_type nss_m + static int nss_match_cmd_procfs_config_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + char *command_str, *token, *param, *value; +- char *input_msg, *input_msg_orig; ++ char *input_msg, *pos; + nss_match_cmd_t command; + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); + size_t count = *lenp; + int ret = proc_dostring(ctl, write, buffer, lenp, ppos); ++ char cmd_buf[100] = {0}; /* Use a fixed buffer size matching nss_match_data */ + + if (!write) { + return ret; + } + +- input_msg = (char *)kzalloc(count + 1, GFP_KERNEL); +- if (!input_msg) { +- nss_match_warn("%px: Dynamic allocation falied while writing input message from file", ctl); +- return -ENOMEM; ++ if (count >= sizeof(cmd_buf)) { ++ nss_match_warn("%px: Input too large: %zu\n", ctl, count); ++ return -EINVAL; + } + +- input_msg_orig = input_msg; +- if (copy_from_user(input_msg, buffer, count)) { +- kfree(input_msg); +- nss_match_warn("%px: Cannot copy user's entry to kernel memory\n", ctl); +- return -EFAULT; ++ memcpy(cmd_buf, buffer, count); ++ cmd_buf[count] = '\0'; /* Ensure null termination */ ++ ++ if ((pos = strrchr(cmd_buf, '\n')) != NULL) { ++ *pos = '\0'; + } + ++ input_msg = cmd_buf; + command_str = strsep(&input_msg, " "); + command = nss_match_cmd_parse(command_str); + +@@ -161,20 +162,17 @@ static int nss_match_cmd_procfs_config_h + profile_type = nss_match_cmd_get_profile_type(input_msg); + if (profile_type == NSS_MATCH_PROFILE_TYPE_NONE) { + pr_warn("%px: Please provide a valid profile type\n", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + + table_id = nss_match_instance_create(); + if (table_id <= 0) { + pr_warn("%px: Cannot create a new match instance\n", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + + nss_match_db_profile_type_add(profile_type, table_id); + pr_warn("%px: New match instance created, table_id = %d\n", ctl, table_id); +- kfree(input_msg_orig); + return count; + } + +@@ -194,32 +192,27 @@ static int nss_match_cmd_procfs_config_h + ret = sscanf(value, "%u", &table_id); + if (!ret) { + pr_warn("%px: Cannot convert to integer. Wrong input!!", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + } + + if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) { + pr_warn("%px: Invalid table_id %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (nss_match_db_table_validate(table_id)) { + pr_warn("%px: Table is already configured, %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (nss_match_db_parse_cmd(table_id, input_msg, &input_mask_param, NSS_MATCH_ADD_MASK)) { +- kfree(input_msg_orig); + return -EINVAL; + } + + nss_match_db_mask_add(&input_mask_param.msg.configure_msg, table_id); + pr_warn("%px: Mask added to instance successfully. %d", ctl, table_id); + +- kfree(input_msg_orig); + return count; + } + +@@ -240,43 +233,36 @@ static int nss_match_cmd_procfs_config_h + ret = sscanf(value, "%u", &table_id); + if (!ret) { + pr_warn("%px: Cannot convert to integer. Wrong input!!", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + } + + if ((table_id == 0) || (table_id > NSS_MATCH_INSTANCE_MAX)) { + pr_warn("%px: Invalid table_id %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (nss_match_db_table_validate(table_id)) { + pr_warn("%px: Table is already configured, %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (!nss_match_db_instance_config_get(&config_msg, &if_num, table_id)) { + pr_warn("%px: Unable to fetch stored configuration %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (if_num < 0) { + nss_match_warn("%px: Incorrect interface number: %d\n", ctl, if_num); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (nss_match_cmd_enable_instance(&config_msg, if_num, table_id)) { + pr_warn("%px: Failed to enable table %d\n", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + pr_warn("%px: Table %d enabled successfully\n", ctl, table_id); +- kfree(input_msg_orig); + return count; + } + +@@ -298,14 +284,12 @@ static int nss_match_cmd_procfs_config_h + ret = sscanf(value, "%u", &table_id); + if (!ret) { + pr_warn("%px: Cannot convert to integer. Wrong input!!", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + } + + if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) { + pr_warn("%px: Invalid table_id: %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + +@@ -313,7 +297,6 @@ static int nss_match_cmd_procfs_config_h + + if (nss_match_db_parse_cmd(table_id, input_msg, &input_rule_param, NSS_MATCH_ADD_RULE)) { + pr_warn("%px: Wrong input", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + +@@ -325,12 +308,10 @@ static int nss_match_cmd_procfs_config_h + + if (rule_id < 0) { + pr_warn("%px: Failed to add rule into table %d.\n", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + pr_warn("%px: Rule added to table %d successfully with rule_id: %d\n", ctl, table_id, rule_id); +- kfree(input_msg_orig); + return count; + } + +@@ -352,7 +333,6 @@ static int nss_match_cmd_procfs_config_h + if (!(strncasecmp(param, "rule_id", strlen("rule_id")))) { + if (!sscanf(token, "%hu", &rule_id)) { + pr_warn("%px: Cannot convert to integer. Wrong input\n", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + continue; +@@ -361,36 +341,30 @@ static int nss_match_cmd_procfs_config_h + if (!strncasecmp(param, "table_id", strlen("table_id"))) { + if (!sscanf(token, "%u", &table_id)) { + pr_warn("%px: Cannot convert to integer. Wrong input!!", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + continue; + } + +- kfree(input_msg_orig); + return -EINVAL; + } + + if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) { + pr_warn("%px: Invalid table_id: %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (rule_id == 0 || rule_id > NSS_MATCH_INSTANCE_RULE_MAX) { + pr_warn("%px: Invalid rule_id: %d", ctl, rule_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (nss_match_rule_delete(nss_ctx, rule_id, table_id)) { + pr_warn("%px: Failed to delete rule from table %d.\n", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + pr_warn("%px: Rule deleted from table %d successfully\n", ctl, table_id); +- kfree(input_msg_orig); + return count; + } + +@@ -410,39 +384,33 @@ static int nss_match_cmd_procfs_config_h + ret = sscanf(token, "%u", &table_id); + if (!ret) { + pr_warn("%px: Cannot convert to integer. Wrong input!!", input_msg); +- kfree(input_msg_orig); + return -EINVAL; + } + } + + if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) { + pr_warn("%px: Invalid table_id: %d", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + if (nss_match_instance_destroy(table_id)) { + pr_warn("%px: Failed to destroy table %d\n", ctl, table_id); +- kfree(input_msg_orig); + return -EINVAL; + } + + pr_warn("%px: Table %d destroyed successfully.\n", ctl, table_id); +- kfree(input_msg_orig); + return count; + } + + default: + { + pr_warn("%px: Input command is not as per syntax, Please enter a valid command", ctl); +- kfree(input_msg_orig); + return -EINVAL; + } + } + + fail: + pr_warn("%px: Wrong input, check help. (cat /proc/sys/dev/nss/match/help)", ctl); +- kfree(input_msg_orig); + return ret; + + } +@@ -456,11 +424,12 @@ static int nss_match_cmd_procfs_reset_ne + struct net_device *dev; + uint32_t if_num, type = 0; + int ret; +- char *dev_name; +- char *cmd_buf = nss_match_data; ++ char *pos; ++ char cmd_buf[IFNAMSIZ] = {0}; + nss_tx_status_t nss_tx_status; + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); + struct nss_ctx_instance *wifili_nss_ctx = nss_wifili_get_context(); ++ size_t count = *lenp; + + if (!nss_ctx || !wifili_nss_ctx) { + pr_warn("%px: NSS Context not found. wifili_nss_ctx: %px. Reset nexthop failed", nss_ctx, wifili_nss_ctx); +@@ -473,19 +442,30 @@ static int nss_match_cmd_procfs_reset_ne + return ret; + } + ++ if (count >= sizeof(cmd_buf)) { ++ nss_match_warn("%px: Input too large: %zu\n", ctl, count); ++ return -EINVAL; ++ } ++ ++ memcpy(cmd_buf, buffer, count); ++ cmd_buf[count] = '\0'; /* Ensure null termination */ ++ ++ if ((pos = strrchr(cmd_buf, '\n')) != NULL) { ++ *pos = '\0'; ++ } ++ + /* + * Parse and read the devname from command. + */ +- dev_name = strsep(&cmd_buf, "\0"); +- dev = dev_get_by_name(&init_net, dev_name); ++ dev = dev_get_by_name(&init_net, cmd_buf); + if (!dev) { +- pr_warn("%px: Cannot find the net device: %s. Reset nexthop failed.\n", nss_ctx, dev_name); ++ pr_warn("%px: Cannot find the net device: %s. Reset nexthop failed.\n", nss_ctx, cmd_buf); + return -ENODEV; + } + + if_num = nss_cmn_get_interface_number_by_dev(dev); + if (if_num < 0) { +- pr_warn("%px: Invalid if_num for interface: %s. Reset nexthop failed.\n", nss_ctx, dev_name); ++ pr_warn("%px: Invalid if_num for interface: %s. Reset nexthop failed.\n", nss_ctx, cmd_buf); + dev_put(dev); + return -ENODEV; + } +@@ -529,7 +509,7 @@ static int nss_match_cmd_procfs_set_if_n + int table_id; + struct nss_ctx_instance *nss_ctx = nss_match_get_context(); + struct nss_ctx_instance *wifili_nss_ctx = nss_wifili_get_context(); +- char *dev_name, *nexthop_msg; ++ char *dev_name, *pos; + char *cmd_buf = NULL; + size_t count = *lenp; + nss_tx_status_t nss_tx_status; +@@ -544,31 +524,28 @@ static int nss_match_cmd_procfs_set_if_n + return -ENOMEM; + } + +- cmd_buf = (char *)kzalloc(count + 1, GFP_KERNEL); +- nexthop_msg = cmd_buf; +- if (!cmd_buf) { +- pr_warn("%px: Cannot allocate buffer to read input", nss_ctx); +- return -ENOMEM; ++ if (count >= sizeof(cmd_buf)) { ++ nss_match_warn("%px: Input too large: %zu\n", ctl, count); ++ return -EINVAL; + } + +- if (copy_from_user(cmd_buf, buffer, count)) { +- kfree(nexthop_msg); +- pr_warn("%px: Cannot copy user's entry to kernel memory\n", nss_ctx); +- return -EFAULT; ++ memcpy(cmd_buf, buffer, count); ++ cmd_buf[count] = '\0'; /* Ensure null termination */ ++ ++ if ((pos = strrchr(cmd_buf, '\n')) != NULL) { ++ *pos = '\0'; + } + + dev_name = strsep(&cmd_buf, " "); + dev = dev_get_by_name(&init_net, dev_name); + if (!dev) { + pr_warn("%px: Cannot find the net device\n", nss_ctx); +- kfree(nexthop_msg); + return -ENODEV; + } + + if_num = nss_cmn_get_interface_number_by_dev(dev); + if (if_num < 0) { + pr_warn("%px: Invalid interface number:%d\n", nss_ctx, if_num); +- kfree(nexthop_msg); + dev_put(dev); + return -ENODEV; + } +@@ -576,20 +553,17 @@ static int nss_match_cmd_procfs_set_if_n + if (isdigit(cmd_buf[0])) { + if (!sscanf(cmd_buf, "%u", &nh_if_num)) { + pr_warn("%px, Failed to write the nexthop if_num token to integer\n", nss_ctx); +- kfree(nexthop_msg); + dev_put(dev); + return -EFAULT; + } + } else { + pr_warn("%px: Invalid nexthop interface number.\n", nss_ctx); +- kfree(nexthop_msg); + dev_put(dev); + return -ENODEV; + } + + if (nh_if_num < 0) { + pr_warn("%px: Invalid nexthop interface number:%d\n", nss_ctx, if_num); +- kfree(nexthop_msg); + dev_put(dev); + return -ENODEV; + } +@@ -597,7 +571,6 @@ static int nss_match_cmd_procfs_set_if_n + table_id = nss_match_get_table_id_by_ifnum(nh_if_num); + if (table_id <= 0 || table_id > NSS_MATCH_INSTANCE_MAX) { + pr_warn("Invalid match interface. Failed to set %d as nexthop.\n", nh_if_num); +- kfree(nexthop_msg); + dev_put(dev); + return -EFAULT; + } +@@ -614,7 +587,6 @@ static int nss_match_cmd_procfs_set_if_n + nss_tx_status = nss_phys_if_set_nexthop(nss_ctx, if_num, nh_if_num); + } else { + pr_warn("Invalid interface to set nexthop. Failed to set nexthop on if_num %d.\n", if_num); +- kfree(nexthop_msg); + dev_put(dev); + return -EFAULT; + } +@@ -623,7 +595,6 @@ static int nss_match_cmd_procfs_set_if_n + pr_warn("%px: Sending message failed, cannot change nexthop\n", nss_ctx); + } + +- kfree(nexthop_msg); + dev_put(dev); + return ret; + } diff --git a/qca-nss-clients/patches/0033-ipsecmgr-fix-compile-error.patch b/qca-nss-clients/patches/0033-ipsecmgr-fix-compile-error.patch new file mode 100644 index 0000000..def9fd8 --- /dev/null +++ b/qca-nss-clients/patches/0033-ipsecmgr-fix-compile-error.patch @@ -0,0 +1,334 @@ +--- a/ipsecmgr/v2.0/plugins/klips/nss_ipsec_klips.c ++++ b/ipsecmgr/v2.0/plugins/klips/nss_ipsec_klips.c +@@ -146,7 +146,6 @@ static int nss_ipsec_klips_offload_esp(s + static struct net_protocol esp_protocol = { + .handler = nss_ipsec_klips_offload_esp, + .no_policy = 1, +- .netns_ok = 1, + }; + + /* +@@ -304,7 +303,7 @@ static struct nss_ipsec_klips_tun *nss_i + * Read/write lock needs to taken by the caller since sa + * table is looked up here + */ +- BUG_ON(write_can_lock(&tunnel_map.lock)); ++ lockdep_assert_held_write(&tunnel_map.lock); + + if (!klips_dev) { + return NULL; +@@ -387,7 +386,7 @@ static struct nss_ipsec_klips_tun *nss_i + * Read/write lock needs to be taken by the caller since tunnel + * table is looked up here + */ +- BUG_ON(write_can_lock(&tunnel_map.lock)); ++ lockdep_assert_held_write(&tunnel_map.lock); + + for (i = 0, tun = tunnel_map.tbl; i < tunnel_map.max; i++, tun++) { + if (!tun->klips_dev) { +@@ -507,7 +506,7 @@ static struct nss_ipsec_klips_sa *nss_ip + * Read/write lock needs to taken by the caller since sa + * table is looked up here + */ +- BUG_ON(write_can_lock(&tunnel_map.lock)); ++ lockdep_assert_held_write(&tunnel_map.lock); + + list_for_each_entry_safe(sa, tmp, head, list) { + if (sa->sid == crypto_idx) +@@ -531,7 +530,7 @@ static void nss_ipsec_klips_sa_flush(str + * Read/write lock needs to taken by the caller since sa + * table is modified here + */ +- BUG_ON(write_can_lock(&tunnel_map.lock)); ++ lockdep_assert_held_write(&tunnel_map.lock); + + list_for_each_entry_safe(sa, tmp, head, list) { + list_del_init(&sa->list); +@@ -1293,7 +1292,7 @@ static void nss_ipsec_klips_register_nat + /* + * write lock is needed as we are modifying tunnel entry. + */ +- BUG_ON(write_can_lock(&tunnel_map.lock)); ++ lockdep_assert_held_write(&tunnel_map.lock); + + sock_hold(sk); + tun->sk_encap_rcv = udp_sk(sk)->encap_rcv; +@@ -1310,7 +1309,7 @@ static void nss_ipsec_klips_unregister_n + /* + * write lock is needed as we are modifying tunnel entry. + */ +- BUG_ON(write_can_lock(&tunnel_map.lock)); ++ lockdep_assert_held_write(&tunnel_map.lock); + + xchg(&udp_sk(tun->sk)->encap_rcv, tun->sk_encap_rcv); + sock_put(tun->sk); +--- a/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm.c ++++ b/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm.c +@@ -1243,6 +1243,7 @@ drop: + return -EINVAL; + } + ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 4, 0)) + /* + * nss_ipsec_xfrm_v4_output_finish() + * This is called for non-offloaded transformations after the NF_POST routing hooks +@@ -1264,9 +1265,8 @@ static int nss_ipsec_xfrm_v4_output_fini + */ + static int nss_ipsec_xfrm_v4_extract_input(struct xfrm_state *x, struct sk_buff *skb) + { +- struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; +- + nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb); ++ struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + return drv->xsa.v4->extract_input(x, skb); + } + +@@ -1278,11 +1278,12 @@ static int nss_ipsec_xfrm_v4_extract_inp + */ + static int nss_ipsec_xfrm_v4_extract_output(struct xfrm_state *x, struct sk_buff *skb) + { +- struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + + nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb); ++ struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + return drv->xsa.v4->extract_output(x, skb); + } ++#endif + + /* + * nss_ipsec_xfrm_v4_transport_finish() +@@ -1381,14 +1382,14 @@ fallback: + * nss_ipsec_xfrm_esp_init_state() + * Initialize IPsec xfrm state of type ESP. + */ +-static int nss_ipsec_xfrm_esp_init_state(struct xfrm_state *x) ++static int nss_ipsec_xfrm_esp_init_state(struct xfrm_state *x, struct netlink_ext_ack *extac) + { + struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + struct nss_ipsec_xfrm_tunnel *tun = NULL; + struct nss_ipsec_xfrm_sa *sa = NULL; + xfrm_address_t remote = {0}; + xfrm_address_t local = {0}; +- struct net_device *local_dev; ++ struct net_device *local_dev = NULL; + bool new_tun = 0; + size_t ip_addr_len; + +@@ -1396,7 +1397,7 @@ static int nss_ipsec_xfrm_esp_init_state + local_dev = ip_dev_find(&init_net, x->id.daddr.a4); + ip_addr_len = sizeof(local.a4); + } else { +- local_dev = ipv6_dev_find(&init_net, &x->id.daddr.in6, 1); ++ local_dev = ipv6_dev_find(&init_net, &x->id.daddr.in6, local_dev); + ip_addr_len = sizeof(local.a6); + } + +@@ -1737,6 +1738,7 @@ drop: + return -EINVAL; + } + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + /* + * nss_ipsec_xfrm_v6_output_finish() + * This is called for non-offloaded transformations after the NF_POST routing hooks +@@ -1758,9 +1760,9 @@ static int nss_ipsec_xfrm_v6_output_fini + */ + static int nss_ipsec_xfrm_v6_extract_input(struct xfrm_state *x, struct sk_buff *skb) + { +- struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + + nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb); ++ struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + return drv->xsa.v6->extract_input(x, skb); + } + +@@ -1772,11 +1774,11 @@ static int nss_ipsec_xfrm_v6_extract_inp + */ + static int nss_ipsec_xfrm_v6_extract_output(struct xfrm_state *x, struct sk_buff *skb) + { +- struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; +- + nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb); ++ struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + return drv->xsa.v6->extract_output(x, skb); + } ++#endif + + /* + * nss_ipsec_xfrm_v6_transport_finish() +@@ -1804,22 +1806,25 @@ void nss_ipsec_xfrm_v6_local_error(struc + return drv->xsa.v6->local_error(skb, mtu); + } + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + /* + * nss_ipsec_xfrm_v6_esp_hdr_offset() + * Invoked by stack for IPv6 transport mode in encap. + * Redirect to the native version. + */ +-static int nss_ipsec_xfrm_v6_esp_hdr_offset(struct xfrm_state *x, struct sk_buff *skb, u8 **prevhdr) ++static int nss_ipsec_xfrm_v6_esp_hdr_offset(struct xfrm_state *x, struct sk_buff *skb, u8 **prevhdr) + { +- struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; + + nss_ipsec_xfrm_trace("%px: Redirect to native esp6 stack\n", skb); +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) +- return drv->xsa.v6->type_map[IPPROTO_ESP]->hdr_offset(x, skb, prevhdr); +-#else +- return drv->xsa.v6->type_esp->hdr_offset(x, skb, prevhdr); +-#endif ++ ++ struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm; ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) ++ return drv->xsa.v6->type_map[IPPROTO_ESP]->hdr_offset(x, skb, prevhdr); ++ #else ++ return drv->xsa.v6->type_esp->hdr_offset(x, skb, prevhdr); ++ #endif + } ++#endif + + /* + * nss_ipsec_xfrm_esp6_rcv() +@@ -1970,7 +1975,6 @@ static void nss_ipsec_xfrm_state_delete( + nss_ipsec_xfrm_del_tun(drv, tun); + } + +- return; + } + + /* +@@ -2045,9 +2049,11 @@ static struct xfrm_state_afinfo xfrm_v4_ + .init_temprop = nss_ipsec_xfrm_v4_init_param, + #endif + .output = nss_ipsec_xfrm_v4_output, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + .output_finish = nss_ipsec_xfrm_v4_output_finish, + .extract_input = nss_ipsec_xfrm_v4_extract_input, + .extract_output = nss_ipsec_xfrm_v4_extract_output, ++#endif + .transport_finish = nss_ipsec_xfrm_v4_transport_finish, + .local_error = nss_ipsec_xfrm_v4_local_error, + }; +@@ -2092,7 +2098,6 @@ struct xfrm_mode xfrm_v6_mode_map[XFRM_M + * IPv4 xfrm_type ESP object. + */ + static const struct xfrm_type xfrm_v4_type = { +- .description = "NSS ESP4", + .owner = THIS_MODULE, + .proto = IPPROTO_ESP, + .flags = XFRM_TYPE_REPLAY_PROT, +@@ -2128,9 +2133,11 @@ static struct xfrm_state_afinfo xfrm_v6_ + .state_sort = nss_ipsec_xfrm_v6_sort_state, + #endif + .output = nss_ipsec_xfrm_v6_output, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + .output_finish = nss_ipsec_xfrm_v6_output_finish, + .extract_input = nss_ipsec_xfrm_v6_extract_input, + .extract_output = nss_ipsec_xfrm_v6_extract_output, ++#endif + .transport_finish = nss_ipsec_xfrm_v6_transport_finish, + .local_error = nss_ipsec_xfrm_v6_local_error, + }; +@@ -2139,7 +2146,6 @@ static struct xfrm_state_afinfo xfrm_v6_ + * IPv6 xfrm_type ESP object. + */ + static const struct xfrm_type xfrm_v6_type = { +- .description = "NSS ESP6", + .owner = THIS_MODULE, + .proto = IPPROTO_ESP, + .flags = XFRM_TYPE_REPLAY_PROT, +@@ -2148,7 +2154,9 @@ static const struct xfrm_type xfrm_v6_ty + .get_mtu = nss_ipsec_xfrm_esp_get_mtu, + .input = nss_ipsec_xfrm_esp_input, + .output = nss_ipsec_xfrm_esp_output, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + .hdr_offset = nss_ipsec_xfrm_v6_esp_hdr_offset, ++#endif + }; + + /* +@@ -2234,7 +2242,6 @@ static void nss_ipsec_xfrm_restore_afinf + } + + xfrm_unregister_type(base, family); +- + xfrm_state_update_afinfo(family, afinfo); + } + +@@ -2319,14 +2326,10 @@ static void nss_ipsec_xfrm_override_afin + */ + int __init nss_ipsec_xfrm_init_module(void) + { +- + rwlock_init(&g_ipsec_xfrm.lock); +- + nss_ipsec_xfrm_init_tun_db(&g_ipsec_xfrm); + nss_ipsec_xfrm_init_flow_db(&g_ipsec_xfrm); +- + init_completion(&g_ipsec_xfrm.complete); +- + net_get_random_once(&g_ipsec_xfrm.hash_nonce, sizeof(g_ipsec_xfrm.hash_nonce)); + + /* +@@ -2354,7 +2357,6 @@ int __init nss_ipsec_xfrm_init_module(vo + nss_ipsec_xfrm_override_afinfo(&g_ipsec_xfrm, AF_INET6); + + ecm_interface_ipsec_register_callbacks(&xfrm_ecm_ipsec_cb); +- ecm_notifier_register_connection_notify(&xfrm_ecm_notifier); + + #if defined(NSS_L2TPV2_ENABLED) + l2tpmgr_register_ipsecmgr_callback_by_ipaddr(&xfrm_l2tp); +@@ -2367,6 +2369,7 @@ int __init nss_ipsec_xfrm_init_module(vo + /* + * Register for xfrm events + */ ++ ecm_notifier_register_connection_notify(&xfrm_ecm_notifier); + xfrm_register_km(&nss_ipsec_xfrm_mgr); + + /* +@@ -2377,6 +2380,7 @@ int __init nss_ipsec_xfrm_init_module(vo + return 0; + + unreg_v4_handler: ++ xfrm4_protocol_deregister(&xfrm4_proto, IPPROTO_ESP); + xfrm6_protocol_deregister(&xfrm6_proto, IPPROTO_ESP); + return -EAGAIN; + } +--- a/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_sa.c ++++ b/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_sa.c +@@ -183,7 +183,7 @@ static bool nss_ipsec_xfrm_sa_init_crypt + */ + static void nss_ipsec_xfrm_sa_init_tuple(struct nss_ipsec_xfrm_sa *sa, struct xfrm_state *x) + { +- struct net_device *local_dev; ++ struct net_device *local_dev = NULL; + + sa->type = NSS_IPSECMGR_SA_TYPE_ENCAP; + sa->tuple.spi_index = ntohl(x->id.spi); +@@ -217,7 +217,7 @@ static void nss_ipsec_xfrm_sa_init_tuple + sa->tuple.dest_ip[2] = ntohl(x->id.daddr.a6[2]); + sa->tuple.dest_ip[3] = ntohl(x->id.daddr.a6[3]); + +- local_dev = ipv6_dev_find(&init_net, (struct in6_addr *)x->id.daddr.a6, 1); ++ local_dev = ipv6_dev_find(&init_net, (struct in6_addr *)x->id.daddr.a6, local_dev); + } + + /* +--- a/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.c ++++ b/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.c +@@ -130,7 +130,6 @@ err: + drop: + atomic64_inc(&drv->stats.inner_drop); + dev_kfree_skb_any(skb); +- return; + } + + /* +@@ -194,7 +193,6 @@ static void nss_ipsec_xfrm_tunnel_rx_out + drop: + dev_kfree_skb_any(skb); + atomic64_inc(&drv->stats.outer_drop); +- return; + } + + /* diff --git a/qca-nss-crypto/Makefile b/qca-nss-crypto/Makefile new file mode 100644 index 0000000..f883934 --- /dev/null +++ b/qca-nss-crypto/Makefile @@ -0,0 +1,90 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-crypto +PKG_RELEASE:=1 + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-crypto.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2024-09-16 +PKG_SOURCE_VERSION:=60e27b9 +PKG_MIRROR_HASH:=f4d992ccfccdbd14463872afac44ab7d44cfae683a8e9768cee27948b62fd62d +QSDK_VERSION:=12.5 +PKG_VERSION:=$(QSDK_VERSION).$(subst -,.,$(PKG_SOURCE_DATE))~$(PKG_SOURCE_VERSION) + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-crypto + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Cryptographic API modules + DEPENDS:=@(TARGET_qualcommax||TARGET_ipq806x) \ + +kmod-qca-nss-drv \ + +@NSS_DRV_CRYPTO_ENABLE \ + +TARGET_qualcommax_ipq807x:nss-eip-firmware \ + +TARGET_qualcommax_ipq60xx:nss-eip-firmware + TITLE:=Kernel driver for NSS crypto driver +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-crypto),) + FILES:=$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src/qca-nss-crypto.ko \ + $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/tool/qca-nss-crypto-tool.ko + AUTOLOAD:=$(call AutoProbe,qca-nss-crypto) +endif +endef + +define KernelPackage/qca-nss-crypto/Description +This package contains a NSS crypto driver for QCA chipset +endef + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-crypto),) +# v1.0 is for Akronite +# v2.0 is for Hawkeye/Cypress/Maple +ifneq (, $(findstring $(CONFIG_TARGET_SUBTARGET), "ipq807x" "ipq60xx" "ipq50xx")) +NSS_CRYPTO_DIR:=v2.0 +else +NSS_CRYPTO_DIR:=v1.0 +endif + +EXTRA_CFLAGS+= \ + -DCONFIG_NSS_DEBUG_LEVEL=4 \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include \ + -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src + +ifeq ($(CONFIG_TARGET_BOARD), "qualcommax") + SOC:=$(CONFIG_TARGET_SUBTARGET) +endif + +MAKE_OPTS+= \ + NSS_CRYPTO_DIR=$(NSS_CRYPTO_DIR) \ + SoC=$(SOC) \ + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-nss-crypto + $(CP) $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include/* $(1)/usr/include/qca-nss-crypto +endef + +define Build/Compile + +$(KERNEL_MAKE) \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + $(strip $(MAKE_OPTS)) \ + $(PKG_JOBS) \ + modules +endef + +else + +define Build/Compile + : +endef + +define Build/Install + : +endef + +endif + +$(eval $(call KernelPackage,qca-nss-crypto)) diff --git a/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch b/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 0000000..19454c4 --- /dev/null +++ b/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,94 @@ +From 8baa8e747247403c6f814ea5dc3e463c70e0415f Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 8 Jun 2021 22:14:34 +0200 +Subject: [PATCH 2/3] nss-crypto: replace ioremap_nocache() with ioremap + +ioremap_nocache() was dropped in kernel 5.5 as regular +ioremap() was exactly the same. + +So, simply replace all of the ioremap_nocache() calls +with ioremap(). + +Signed-off-by: Robert Marko +--- + v1.0/src/nss_crypto_dtsi.c | 4 ++-- + v1.0/src/nss_crypto_platform.c | 4 ++-- + v2.0/src/hal/ipq50xx/nss_crypto_ce5.c | 4 ++-- + v2.0/src/hal/ipq60xx/nss_crypto_eip197.c | 2 +- + v2.0/src/hal/ipq807x/nss_crypto_eip197.c | 2 +- + 5 files changed, 8 insertions(+), 8 deletions(-) + +--- a/v1.0/src/nss_crypto_dtsi.c ++++ b/v1.0/src/nss_crypto_dtsi.c +@@ -311,11 +311,11 @@ static int nss_crypto_probe(struct platf + e_ctrl->dev = &pdev->dev; + + e_ctrl->cmd_base = crypto_res.start; +- e_ctrl->crypto_base = ioremap_nocache(e_ctrl->cmd_base, resource_size(&crypto_res)); ++ e_ctrl->crypto_base = ioremap(e_ctrl->cmd_base, resource_size(&crypto_res)); + nss_crypto_assert(e_ctrl->crypto_base); + + e_ctrl->bam_pbase = bam_res.start; +- e_ctrl->bam_base = ioremap_nocache(e_ctrl->bam_pbase, resource_size(&bam_res)); ++ e_ctrl->bam_base = ioremap(e_ctrl->bam_pbase, resource_size(&bam_res)); + nss_crypto_assert(e_ctrl->bam_base); + + e_ctrl->bam_ee = bam_ee; +--- a/v1.0/src/nss_crypto_platform.c ++++ b/v1.0/src/nss_crypto_platform.c +@@ -134,11 +134,11 @@ static int nss_crypto_probe(struct platf + e_ctrl->bam_ee = res->bam_ee; + + e_ctrl->cmd_base = res->crypto_pbase; +- e_ctrl->crypto_base = ioremap_nocache(res->crypto_pbase, res->crypto_pbase_sz); ++ e_ctrl->crypto_base = ioremap(res->crypto_pbase, res->crypto_pbase_sz); + nss_crypto_assert(e_ctrl->crypto_base); + + e_ctrl->bam_pbase = res->bam_pbase; +- e_ctrl->bam_base = ioremap_nocache(res->bam_pbase, res->bam_pbase_sz); ++ e_ctrl->bam_base = ioremap(res->bam_pbase, res->bam_pbase_sz); + nss_crypto_assert(e_ctrl->bam_base); + + /* +--- a/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c ++++ b/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c +@@ -288,7 +288,7 @@ int nss_crypto_ce5_engine_init(struct pl + * remap the I/O addresses for crypto + */ + eng->crypto_paddr = crypto_res->start; +- eng->crypto_vaddr = ioremap_nocache(crypto_res->start, resource_size(crypto_res)); ++ eng->crypto_vaddr = ioremap(crypto_res->start, resource_size(crypto_res)); + if (!eng->crypto_vaddr) { + nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)eng->crypto_paddr); + nss_crypto_engine_free(eng); +@@ -299,7 +299,7 @@ int nss_crypto_ce5_engine_init(struct pl + * remap the I/O addresses for bam + */ + eng->dma_paddr = bam_res->start; +- eng->dma_vaddr = ioremap_nocache(bam_res->start, resource_size(bam_res)); ++ eng->dma_vaddr = ioremap(bam_res->start, resource_size(bam_res)); + if (!eng->dma_vaddr) { + iounmap(eng->crypto_vaddr); + nss_crypto_warn("%px: unable to remap dma_addr(0x%px)\n", node, (void *)eng->dma_paddr); +--- a/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c ++++ b/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c +@@ -490,7 +490,7 @@ int nss_crypto_eip197_engine_init(struct + * remap the I/O addresses + */ + paddr = res->start + offset; +- vaddr = ioremap_nocache(paddr, resource_size(res)); ++ vaddr = ioremap(paddr, resource_size(res)); + if (!vaddr) { + nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)paddr); + return -EIO; +--- a/v2.0/src/hal/ipq807x/nss_crypto_eip197.c ++++ b/v2.0/src/hal/ipq807x/nss_crypto_eip197.c +@@ -490,7 +490,7 @@ int nss_crypto_eip197_engine_init(struct + * remap the I/O addresses + */ + paddr = res->start + offset; +- vaddr = ioremap_nocache(paddr, resource_size(res)); ++ vaddr = ioremap(paddr, resource_size(res)); + if (!vaddr) { + nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)paddr); + return -EIO; diff --git a/qca-nss-crypto/patches/0004-nss-crypto-support-kernel-6.12.patch b/qca-nss-crypto/patches/0004-nss-crypto-support-kernel-6.12.patch new file mode 100644 index 0000000..3107198 --- /dev/null +++ b/qca-nss-crypto/patches/0004-nss-crypto-support-kernel-6.12.patch @@ -0,0 +1,429 @@ +--- a/v2.0/src/nss_crypto_ctrl.c ++++ b/v2.0/src/nss_crypto_ctrl.c +@@ -833,7 +833,7 @@ void nss_crypto_process_event(void *app_ + * nss_crypto_free() + * Free crypto context + */ +-void nss_crypto_free(struct nss_crypto_ctx *ctx) ++static void nss_crypto_free(struct nss_crypto_ctx *ctx) + { + struct nss_crypto_ctrl *ctrl = &g_control; + int32_t status; +@@ -893,7 +893,7 @@ free: + * possible that the host to NSS queue is busy in which + * case we need to retry. + */ +-void nss_crypto_delayed_free(struct work_struct *work) ++static void nss_crypto_delayed_free(struct work_struct *work) + { + struct nss_crypto_ctrl *ctrl = &g_control; + struct nss_crypto_ctx *ctx; +@@ -1244,7 +1244,7 @@ void nss_crypto_engine_free(struct nss_c + * nss_crypto_ndev_setup() + * setup the dummy netdevice + */ +-void nss_crypto_ndev_setup(struct net_device *dev) ++static void nss_crypto_ndev_setup(struct net_device *dev) + { + nss_crypto_info("%px: dummy netdevice for crypto\n", dev); + } +@@ -1575,11 +1575,10 @@ static int nss_crypto_device_probe(struc + * nss_crypto_device_remove() + * remove crypto device and deregister everything + */ +-static int nss_crypto_device_remove(struct platform_device *pdev) ++static void nss_crypto_device_remove(struct platform_device *pdev) + { + nss_crypto_hw_deinit(pdev); + nss_crypto_node_free(platform_get_drvdata(pdev)); +- return 0; + }; + + /* +@@ -1588,7 +1587,11 @@ static int nss_crypto_device_remove(stru + */ + static struct platform_driver nss_crypto_device = { + .probe = nss_crypto_device_probe, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 11, 0) ++ .remove_new = nss_crypto_device_remove, ++#else + .remove = nss_crypto_device_remove, ++#endif + .driver = { + .owner = THIS_MODULE, + .name = "nss-crypto-device", +@@ -1656,7 +1659,7 @@ static int nss_crypto_probe(struct platf + * nss_crypto_remove() + * remove the crypto driver + */ +-static int nss_crypto_remove(struct platform_device *pdev) ++static void nss_crypto_remove(struct platform_device *pdev) + { + struct nss_crypto_ctrl *ctrl = platform_get_drvdata(pdev); + +@@ -1670,7 +1673,6 @@ static int nss_crypto_remove(struct plat + * Clear the active state of driver + */ + ctrl->active = false; +- return 0; + } + + /* +@@ -1679,7 +1681,11 @@ static int nss_crypto_remove(struct plat + */ + static struct platform_driver nss_crypto_drv = { + .probe = nss_crypto_probe, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 11, 0) ++ .remove_new = nss_crypto_remove, ++#else + .remove = nss_crypto_remove, ++#endif + .driver = { + .owner = THIS_MODULE, + .name = "nss-crypto", +@@ -1691,7 +1697,7 @@ static struct platform_driver nss_crypto + * nss_crypto_delayed_probe() + * delayed sequence to initialize crypto after NSS FW is initialized + */ +-void nss_crypto_delayed_probe(struct work_struct *work) ++static void nss_crypto_delayed_probe(struct work_struct *work) + { + struct nss_crypto_ctrl *ctrl; + struct nss_crypto_user *user; +--- a/v2.0/tool/nss_crypto_bench.c ++++ b/v2.0/tool/nss_crypto_bench.c +@@ -717,7 +717,7 @@ static int32_t crypto_bench_prep_buf(str + return CRYPTO_BENCH_OK; + } + +-void crypto_bench_mcmp(void) ++static void crypto_bench_mcmp(void) + { + struct crypto_op *op; + struct list_head *ptr; +@@ -844,7 +844,7 @@ static int crypto_bench_tx(void *arg) + /* + * Context should be ATOMIC + */ +-void crypto_bench_done(void *app_data, struct nss_crypto_hdr *ch, uint8_t error) ++static void crypto_bench_done(void *app_data, struct nss_crypto_hdr *ch, uint8_t error) + { + struct nss_crypto_buf *buf; + struct crypto_op *op; +@@ -914,7 +914,7 @@ static const struct file_operations cmd_ + .write = crypto_bench_cmd_write, + }; + +-void crypto_bench_attach(void *app_data, struct nss_crypto_user *user) ++static void crypto_bench_attach(void *app_data, struct nss_crypto_user *user) + { + spin_lock_init(&op_lock); + +@@ -960,13 +960,13 @@ void crypto_bench_attach(void *app_data + debugfs_create_u32("enqueue_errors", CRYPTO_BENCH_PERM_RO, droot, ¶m.tx_err); + } + +-void crypto_bench_detach(void *app_data, struct nss_crypto_user *user) ++static void crypto_bench_detach(void *app_data, struct nss_crypto_user *user) + { + crypto_bench_flush(); + kmem_cache_destroy(crypto_op_zone); + } + +-int __init crypto_bench_init(void) ++static int __init crypto_bench_init(void) + { + ctx = kmalloc(sizeof(struct nss_crypto_user_ctx), GFP_KERNEL); + if (!ctx) { +@@ -980,7 +980,7 @@ int __init crypto_bench_init(void) + + ctx->attach = crypto_bench_attach; + ctx->detach = crypto_bench_detach; +- strlcpy(ctx->name, "bench", sizeof(ctx->name)); ++ strscpy(ctx->name, "bench", sizeof(ctx->name)); + ctx->hdr_pool_sz = 1024; + ctx->default_hdr_sz = 512; + ctx->timeout_ticks = 1; +@@ -991,7 +991,7 @@ int __init crypto_bench_init(void) + return 0; + } + +-void __exit crypto_bench_exit(void) ++static void __exit crypto_bench_exit(void) + { + crypto_bench_info("Crypto bench unloaded\n"); + +--- a/v2.0/src/hal/ipq60xx/nss_crypto_eip197.h ++++ b/v2.0/src/hal/ipq60xx/nss_crypto_eip197.h +@@ -19,7 +19,9 @@ + #ifndef __NSS_CRYPTO_EIP197_H + #define __NSS_CRYPTO_EIP197_H + ++#include + #include ++#include + + /* + * Common configuration data for command and result +--- a/v2.0/src/hal/ipq60xx/nss_crypto_hw.c ++++ b/v2.0/src/hal/ipq60xx/nss_crypto_hw.c +@@ -15,8 +15,10 @@ + * PERFORMANCE OF THIS SOFTWARE. + */ + ++#include + #include + #include "nss_crypto_eip197.h" ++#include "nss_crypto_hw.h" + + /* + * nss_crypto_hw_deinit() +@@ -27,7 +29,6 @@ void nss_crypto_hw_deinit(struct platfor + /* + * TODO: Add support for putting HW into reset + */ +- return; + } + + /* +--- a/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c ++++ b/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c +@@ -455,7 +455,7 @@ free: + * nss_crypto_eip197_ctx_fill() + * Fill context record specific information + */ +-int nss_crypto_eip197_ctx_fill(struct nss_crypto_ctx *ctx, struct nss_crypto_session_data *data, ++static int nss_crypto_eip197_ctx_fill(struct nss_crypto_ctx *ctx, struct nss_crypto_session_data *data, + struct nss_crypto_cmn_ctx *msg) + { + if (data->algo > NSS_CRYPTO_CMN_ALGO_MAX) +@@ -477,7 +477,7 @@ int nss_crypto_eip197_ctx_fill(struct ns + * nss_crypto_eip197_engine_init() + * allocate & initialize engine + */ +-int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_node *np, ++static int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_node *np, + struct resource *res, uint32_t offset) + { + struct nss_crypto_node *node = platform_get_drvdata(pdev); +@@ -545,7 +545,7 @@ int nss_crypto_eip197_engine_init(struct + * nss_crypto_eip197_node_init() + * allocate & initialize eip197 node + */ +-int nss_crypto_eip197_node_init(struct platform_device *pdev, const char *name) ++static int nss_crypto_eip197_node_init(struct platform_device *pdev, const char *name) + { + struct device_node *np = of_node_get(pdev->dev.of_node); + struct nss_crypto_node *node; +--- a/v2.0/src/hal/ipq807x/nss_crypto_eip197.h ++++ b/v2.0/src/hal/ipq807x/nss_crypto_eip197.h +@@ -20,6 +20,8 @@ + #define __NSS_CRYPTO_EIP197_H + + #include ++#include ++#include + + /* + * Common configuration data for command and result +--- a/v2.0/src/hal/ipq807x/nss_crypto_hw.c ++++ b/v2.0/src/hal/ipq807x/nss_crypto_hw.c +@@ -15,8 +15,10 @@ + * PERFORMANCE OF THIS SOFTWARE. + */ + ++#include + #include + #include "nss_crypto_eip197.h" ++#include "nss_crypto_hw.h" + + /* + * nss_crypto_hw_deinit() +@@ -27,7 +29,6 @@ void nss_crypto_hw_deinit(struct platfor + /* + * TODO: Add support for putting HW into reset + */ +- return; + } + + /* +--- a/v2.0/src/hal/ipq95xx/nss_crypto_eip197.h ++++ b/v2.0/src/hal/ipq95xx/nss_crypto_eip197.h +@@ -20,6 +20,7 @@ + #define __NSS_CRYPTO_EIP197_H + + #include ++#include + + /* + * Common configuration data for command and result +--- a/v2.0/src/hal/ipq95xx/nss_crypto_hw.c ++++ b/v2.0/src/hal/ipq95xx/nss_crypto_hw.c +@@ -16,8 +16,10 @@ + * PERFORMANCE OF THIS SOFTWARE. + */ + ++#include + #include + #include "nss_crypto_eip197.h" ++#include "nss_crypto_hw.h" + + /* + * nss_crypto_hw_deinit() +@@ -28,7 +30,6 @@ void nss_crypto_hw_deinit(struct platfor + /* + * TODO: Add support for putting HW into reset + */ +- return; + } + + /* +--- a/v2.0/src/hal/ipq807x/nss_crypto_eip197.c ++++ b/v2.0/src/hal/ipq807x/nss_crypto_eip197.c +@@ -455,7 +455,7 @@ free: + * nss_crypto_eip197_ctx_fill() + * Fill context record specific information + */ +-int nss_crypto_eip197_ctx_fill(struct nss_crypto_ctx *ctx, struct nss_crypto_session_data *data, ++static int nss_crypto_eip197_ctx_fill(struct nss_crypto_ctx *ctx, struct nss_crypto_session_data *data, + struct nss_crypto_cmn_ctx *msg) + { + if (data->algo > NSS_CRYPTO_CMN_ALGO_MAX) +@@ -477,7 +477,7 @@ int nss_crypto_eip197_ctx_fill(struct ns + * nss_crypto_eip197_engine_init() + * allocate & initialize engine + */ +-int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_node *np, ++static int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_node *np, + struct resource *res, uint32_t offset) + { + struct nss_crypto_node *node = platform_get_drvdata(pdev); +@@ -545,7 +545,7 @@ int nss_crypto_eip197_engine_init(struct + * nss_crypto_eip197_node_init() + * allocate & initialize eip197 node + */ +-int nss_crypto_eip197_node_init(struct platform_device *pdev, const char *name) ++static int nss_crypto_eip197_node_init(struct platform_device *pdev, const char *name) + { + struct device_node *np = of_node_get(pdev->dev.of_node); + struct nss_crypto_node *node; +--- a/v2.0/src/hal/ipq95xx/nss_crypto_eip197.c ++++ b/v2.0/src/hal/ipq95xx/nss_crypto_eip197.c +@@ -456,7 +456,7 @@ free: + * nss_crypto_eip197_ctx_fill() + * Fill context record specific information + */ +-int nss_crypto_eip197_ctx_fill(struct nss_crypto_ctx *ctx, struct nss_crypto_session_data *data, ++static int nss_crypto_eip197_ctx_fill(struct nss_crypto_ctx *ctx, struct nss_crypto_session_data *data, + struct nss_crypto_cmn_ctx *msg) + { + if (data->algo > NSS_CRYPTO_CMN_ALGO_MAX) +@@ -478,7 +478,7 @@ int nss_crypto_eip197_ctx_fill(struct ns + * nss_crypto_eip197_engine_init() + * allocate & initialize engine + */ +-int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_node *np, ++static int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_node *np, + struct resource *res, uint32_t offset) + { + struct nss_crypto_node *node = platform_get_drvdata(pdev); +@@ -550,7 +550,7 @@ int nss_crypto_eip197_engine_init(struct + * nss_crypto_eip197_node_init() + * allocate & initialize eip197 node + */ +-int nss_crypto_eip197_node_init(struct platform_device *pdev, const char *name) ++static int nss_crypto_eip197_node_init(struct platform_device *pdev, const char *name) + { + struct device_node *np = of_node_get(pdev->dev.of_node); + struct nss_crypto_node *node; +--- a/v2.0/src/hal/ipq807x/nss_crypto_eip197_init.c ++++ b/v2.0/src/hal/ipq807x/nss_crypto_eip197_init.c +@@ -404,7 +404,7 @@ static void nss_crypto_eip197_hw_setup_c + * nss_crypto_eip197_hw_setup_cache() + * setup EIP197 flow and transform cache + */ +-void nss_crypto_eip197_hw_setup_cache(void __iomem *base_addr) ++static void nss_crypto_eip197_hw_setup_cache(void __iomem *base_addr) + { + void __iomem *addr; + uint32_t val; +@@ -785,7 +785,7 @@ static void nss_crypto_eip197_hw_disable + * nss_crypto_eip197_hw_setup() + * Pre initialization function for eip197 + */ +-void nss_crypto_eip197_hw_setup(void __iomem *base_addr) ++static void nss_crypto_eip197_hw_setup(void __iomem *base_addr) + { + /* + * Reset EIP blocks and check if reset is complete +--- a/v2.0/src/hal/ipq60xx/nss_crypto_eip197_init.c ++++ b/v2.0/src/hal/ipq60xx/nss_crypto_eip197_init.c +@@ -437,7 +437,7 @@ static void nss_crypto_eip197_hw_setup_c + * nss_crypto_eip197_hw_setup_cache() + * setup EIP197 flow and transform cache + */ +-void nss_crypto_eip197_hw_setup_cache(void __iomem *base_addr) ++static void nss_crypto_eip197_hw_setup_cache(void __iomem *base_addr) + { + void __iomem *addr; + uint32_t val; +@@ -823,7 +823,7 @@ static void nss_crypto_eip197_hw_disable + * nss_crypto_eip197_hw_setup() + * Pre initialization function for eip197 + */ +-void nss_crypto_eip197_hw_setup(void __iomem *base_addr) ++static void nss_crypto_eip197_hw_setup(void __iomem *base_addr) + { + /* + * Reset EIP blocks and check if reset is complete +--- a/v2.0/src/hal/ipq95xx/nss_crypto_eip197_init.c ++++ b/v2.0/src/hal/ipq95xx/nss_crypto_eip197_init.c +@@ -437,7 +437,7 @@ static void nss_crypto_eip197_hw_setup_c + * nss_crypto_eip197_hw_setup_cache() + * setup EIP197 flow and transform cache + */ +-void nss_crypto_eip197_hw_setup_cache(void __iomem *base_addr) ++static void nss_crypto_eip197_hw_setup_cache(void __iomem *base_addr) + { + void __iomem *addr; + uint32_t val; +@@ -827,7 +827,7 @@ static void nss_crypto_eip197_hw_disable + * nss_crypto_eip197_hw_setup() + * Pre initialization function for eip197 + */ +-void nss_crypto_eip197_hw_setup(void __iomem *base_addr) ++static void nss_crypto_eip197_hw_setup(void __iomem *base_addr) + { + /* + * Reset EIP blocks and check if reset is complete +--- a/v1.0/src/nss_crypto_dtsi.c ++++ b/v1.0/src/nss_crypto_dtsi.c +@@ -346,7 +346,7 @@ static int nss_crypto_probe(struct platf + * nss_crypto_remove() + * remove the crypto engine and deregister everything + */ +-static int nss_crypto_remove(struct platform_device *pdev) ++static void nss_crypto_remove(struct platform_device *pdev) + { + struct nss_crypto_ctrl_eng *e_ctrl; + struct nss_crypto_ctrl *ctrl; +@@ -361,7 +361,6 @@ static int nss_crypto_remove(struct plat + kfree(ctrl->clocks); + } + +- return 0; + }; + + static struct of_device_id nss_crypto_dt_ids[] = { +@@ -375,7 +374,11 @@ MODULE_DEVICE_TABLE(of, nss_crypto_dt_id + */ + static struct platform_driver nss_crypto_drv = { + .probe = nss_crypto_probe, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 11, 0) ++ .remove_new = nss_crypto_remove, ++#else + .remove = nss_crypto_remove, ++#endif + .driver = { + .owner = THIS_MODULE, + .name = "nss-crypto", diff --git a/qca-nss-drv/Config.in b/qca-nss-drv/Config.in new file mode 100644 index 0000000..6b9cf85 --- /dev/null +++ b/qca-nss-drv/Config.in @@ -0,0 +1,271 @@ +menu "Configuration" + depends on PACKAGE_kmod-qca-nss-drv + +comment "Build Options" + +choice + prompt "Memory Profile" + default NSS_MEM_PROFILE_HIGH if TARGET_qualcommax_ipq807x + default NSS_MEM_PROFILE_MEDIUM if (TARGET_qualcommax_ipq60xx || TARGET_qualcommax_ipq50xx) + help + This option allows you to select the memory profile. + It should correspond to the total RAM of your board. + + config NSS_MEM_PROFILE_HIGH + bool "Use 1G memory profile" + depends on TARGET_qualcommax_ipq807x + help + This allows configuring NSS boards with 1GB+ memory. + + config NSS_MEM_PROFILE_MEDIUM + bool "Use 512MB memory profile" + help + This allows configuring NSS for boards with 512M memory. + + config NSS_MEM_PROFILE_LOW + bool "Use 256MB memory profile" + help + This allows configuring NSS for boards with 256M memory. +endchoice + +config NSS_DRV_BRIDGE_ENABLE + bool + default n + prompt "Enable BRIDGE" + depends on TARGET_qualcommax_ipq807x || TARGET_qualcommax_ipq60xx + +config NSS_DRV_CAPWAP_ENABLE + bool + default n + prompt "Enable CAPWAP" + depends on TARGET_qualcommax_ipq807x || TARGET_qualcommax_ipq60xx + +config NSS_DRV_C2C_ENABLE + bool + default n + prompt "Enable C2C" + depends on TARGET_ipq806x || TARGET_qualcommax_ipq807x + +config NSS_DRV_CLMAP_ENABLE + bool + default n + prompt "Enable CLMAP" + +config NSS_DRV_CRYPTO_ENABLE + bool + default n + prompt "Enable CRYPTO" + +config NSS_DRV_DTLS_ENABLE + bool + default n + prompt "Enable DTLS" + depends on TARGET_qualcommax_ipq807x || TARGET_qualcommax_ipq60xx + +config NSS_DRV_GRE_ENABLE + bool + default n + prompt "Enable GRE" + +config NSS_DRV_GRE_REDIR_ENABLE + bool + default n + depends on NSS_DRV_GRE_ENABLE + prompt "Enable GRE_REDIR" + +config NSS_DRV_GRE_TUNNEL_ENABLE + bool + default n + depends on NSS_DRV_GRE_ENABLE + prompt "Enable GRE_TUNNEL" + +config NSS_DRV_IGS_ENABLE + bool + default n + prompt "Enable IGS" + +config NSS_DRV_IPSEC_ENABLE + bool + default n + prompt "Enable IPSEC" + +config NSS_DRV_IPV4_REASM_ENABLE + bool + default n + prompt "Enable IPV4_REASM" + +config NSS_DRV_IPV6_ENABLE + bool + default n + prompt "Enable IPV6" + +config NSS_DRV_IPV6_REASM_ENABLE + bool + default n + depends on NSS_DRV_IPV6_ENABLE + prompt "Enable IPV6_REASM" + +config NSS_DRV_L2TP_ENABLE + bool + default n + prompt "Enable L2TP" + +config NSS_DRV_LAG_ENABLE + bool + default n + prompt "Enable LAG" + depends on TARGET_qualcommax_ipq807x || TARGET_qualcommax_ipq60xx + +config NSS_DRV_MAPT_ENABLE + bool + default n + prompt "Enable MAPT" + +config NSS_DRV_MATCH_ENABLE + bool + default n + prompt "Enable MATCH" + +config NSS_DRV_MIRROR_ENABLE + bool + default n + prompt "Enable MIRROR" + +config NSS_DRV_OAM_ENABLE + bool + default n + prompt "Enable OAM" + depends on TARGET_ipq806x + +config NSS_DRV_PORTID_ENABLE + bool + default n + prompt "Enable PORTID" + depends on TARGET_ipq806x + +config NSS_DRV_LSO_RX_ENABLE + bool + default n + prompt "Enable LSO RX" + +config NSS_DRV_PPPOE_ENABLE + bool + default n + prompt "Enable PPPOE" + +config NSS_DRV_PPTP_ENABLE + bool + default n + prompt "Enable PPTP" + +config NSS_DRV_PVXLAN_ENABLE + bool + default n + prompt "Enable PVXLAN" + +config NSS_DRV_QRFS_ENABLE + bool + default n + prompt "Enable QRFS" + depends on TARGET_qualcommax_ipq807x + +config NSS_DRV_QVPN_ENABLE + bool + default n + prompt "Enable OpenVpn (QVPN)" + depends on TARGET_qualcommax_ipq807x || TARGET_qualcommax_ipq60xx + +config NSS_DRV_RMNET_ENABLE + bool + default n + prompt "Enable RMNET" + depends on TARGET_qualcommax_ipq807x || TARGET_qualcommax_ipq50xx + +config NSS_DRV_SHAPER_ENABLE + bool + default n + prompt "Enable SHAPER" + +config NSS_DRV_SJACK_ENABLE + bool + default n + prompt "Enable SJACK" + +config NSS_DRV_TLS_ENABLE + bool + default n + prompt "Enable TLS" + depends on TARGET_qualcommax_ipq807x || TARGET_qualcommax_ipq60xx + +config NSS_DRV_TRUSTSEC_ENABLE + bool + default n + prompt "Enable TRUSTSEC" + +config NSS_DRV_UDP_ST_ENABLE + bool + default n + prompt "Enable UDP Speedtest" + depends on TARGET_qualcommax_ipq807x || TARGET_qualcommax_ipq50xx + +config NSS_DRV_TRUSTSEC_RX_ENABLE + bool + default n + prompt "Enable TRUSTSEC_RX" + depends on NSS_DRV_TRUSTSEC_ENABLE + +config NSS_DRV_TSTAMP_ENABLE + bool + default n + prompt "Enable TSTAMP" + depends on TARGET_ipq806x + +config NSS_DRV_TUN6RD_ENABLE + bool + default n + prompt "Enable TUN6RD" + +config NSS_DRV_TUNIPIP6_ENABLE + bool + default n + prompt "Enable TUNIPIP6" + +config NSS_DRV_VIRT_IF_ENABLE + bool + default n + prompt "Enable VIRT_IF" + +config NSS_DRV_VLAN_ENABLE + bool + default n + prompt "Enable VLAN" + depends on TARGET_qualcommax_ipq807x || TARGET_qualcommax_ipq60xx + +config NSS_DRV_VXLAN_ENABLE + bool + default n + prompt "Enable VXLAN" + +config NSS_DRV_WIFIOFFLOAD_ENABLE + bool + default n + prompt "Enable WIFI" + +config NSS_DRV_WIFI_EXT_VDEV_ENABLE + bool + default n + depends on NSS_DRV_WIFIOFFLOAD_ENABLE + prompt "Enable WIFI EXT VDEV" + +config NSS_DRV_WIFI_MESH_ENABLE + bool + default n + depends on NSS_DRV_WIFIOFFLOAD_ENABLE + prompt "Enable WIFI MESH" + +config NSS_DRV_WIFI_LEGACY_ENABLE + bool + default n + depends on TARGET_ipq806x + prompt "Enable Legacy WIFI" +endmenu diff --git a/qca-nss-drv/Makefile b/qca-nss-drv/Makefile new file mode 100644 index 0000000..29a87fd --- /dev/null +++ b/qca-nss-drv/Makefile @@ -0,0 +1,364 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-drv +PKG_RELEASE:=17 + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-drv.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2024-11-13 +PKG_SOURCE_VERSION:=d5ee67b +PKG_MIRROR_HASH:=4969320b2315eb07aefec4e189973800dd909c487794cc8383417fd2f97e689f +QSDK_VERSION:=12.5 +PKG_VERSION:=$(QSDK_VERSION).$(subst -,.,$(PKG_SOURCE_DATE))~$(PKG_SOURCE_VERSION) + +PKG_BUILD_PARALLEL:=1 +PKG_FLAGS:=nonshared + +PKG_CONFIG_DEPENDS:= \ + CONFIG_NSS_DRV_BRIDGE_ENABLE \ + CONFIG_NSS_DRV_CAPWAP_ENABLE \ + CONFIG_NSS_DRV_C2C_ENABLE \ + CONFIG_NSS_DRV_CLMAP_ENABLE \ + CONFIG_NSS_DRV_CRYPTO_ENABLE \ + CONFIG_NSS_DRV_DTLS_ENABLE \ + CONFIG_NSS_DRV_GRE_ENABLE \ + CONFIG_NSS_DRV_GRE_REDIR_ENABLE \ + CONFIG_NSS_DRV_GRE_TUNNEL_ENABLE \ + CONFIG_NSS_DRV_IGS_ENABLE \ + CONFIG_NSS_DRV_IPSEC_ENABLE \ + CONFIG_NSS_DRV_IPV4_REASM_ENABLE \ + CONFIG_NSS_DRV_IPV6_ENABLE \ + CONFIG_NSS_DRV_IPV6_REASM_ENABLE \ + CONFIG_NSS_DRV_LSO_RX_ENABLE \ + CONFIG_NSS_DRV_L2TP_ENABLE \ + CONFIG_NSS_DRV_LAG_ENABLE \ + CONFIG_NSS_DRV_MAPT_ENABLE \ + CONFIG_NSS_DRV_MATCH_ENABLE \ + CONFIG_NSS_DRV_MIRROR_ENABLE \ + CONFIG_NSS_DRV_OAM_ENABLE \ + CONFIG_NSS_DRV_PORTID_ENABLE \ + CONFIG_NSS_DRV_PPPOE_ENABLE \ + CONFIG_NSS_DRV_PPTP_ENABLE \ + CONFIG_NSS_DRV_PVXLAN_ENABLE \ + CONFIG_NSS_DRV_QRFS_ENABLE \ + CONFIG_NSS_DRV_QVPN_ENABLE \ + CONFIG_NSS_DRV_RMNET_ENABLE \ + CONFIG_NSS_DRV_SHAPER_ENABLE \ + CONFIG_NSS_DRV_SJACK_ENABLE \ + CONFIG_NSS_DRV_UDP_ST_ENABLE \ + CONFIG_NSS_DRV_TLS_ENABLE \ + CONFIG_NSS_DRV_TRUSTSEC_ENABLE \ + CONFIG_NSS_DRV_TRUSTSEC_RX_ENABLE \ + CONFIG_NSS_DRV_TSTAMP_ENABLE \ + CONFIG_NSS_DRV_TUN6RD_ENABLE \ + CONFIG_NSS_DRV_TUNIPIP6_ENABLE \ + CONFIG_NSS_DRV_VIRT_IF_ENABLE \ + CONFIG_NSS_DRV_VLAN_ENABLE \ + CONFIG_NSS_DRV_VXLAN_ENABLE \ + CONFIG_NSS_DRV_WIFIOFFLOAD_ENABLE \ + CONFIG_NSS_DRV_WIFI_EXT_VDEV_ENABLE \ + CONFIG_NSS_DRV_WIFI_MESH_ENABLE \ + CONFIG_NSS_DRV_WIFI_LEGACY_ENABLE \ + CONFIG_NSS_FIRMWARE_VERSION_11_4 + +ifeq ($(CONFIG_NSS_FIRMWARE_VERSION_11_4),y) +PKG_SOURCE_DATE:=2021-09-13 +PKG_SOURCE_VERSION:=53e5863 +PKG_MIRROR_HASH:=f13681c4aadde3aa713e4ae1426d22f19a387a729521aa1e19ba9d690c17b8e3 +PATCH_DIR:=$(CURDIR)/patches-11.4 +QSDK_VERSION:=11.4.0.5 +PKG_VERSION:=$(QSDK_VERSION).$(subst -,.,$(PKG_SOURCE_DATE))~$(PKG_SOURCE_VERSION) +endif + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +NSS_CLIENTS_DIR:=$(TOPDIR)/qca/src/qca-nss-clients + +define KernelPackage/qca-nss-drv + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@(TARGET_ipq806x||TARGET_qualcommax) \ + +TARGET_qualcommax:kmod-qca-nss-dp \ + +TARGET_qualcommax:nss-firmware + TITLE:=Kernel driver for NSS (core driver) + FILES:=$(PKG_BUILD_DIR)/qca-nss-drv.ko + AUTOLOAD:=$(call AutoLoad,32,qca-nss-drv) +endef + +define KernelPackage/qca-nss-drv/config + source "$(SOURCE)/Config.in" +endef + +define KernelPackage/qca-nss-drv/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_DIR) $(1)/etc/config + $(INSTALL_DIR) $(1)/etc/hotplug.d/firmware + $(INSTALL_DIR) $(1)/usr/bin + + $(INSTALL_BIN) ./files/skb_recycler.init $(1)/etc/init.d/skb_recycler + $(INSTALL_BIN) ./files/qca-nss-drv.init $(1)/etc/init.d/qca-nss-drv + $(INSTALL_DATA) ./files/qca-nss-drv.uci $(1)/etc/config/nss + $(INSTALL_DATA) ./files/qca-nss-drv.hotplug $(1)/etc/hotplug.d/firmware/10-qca-nss-fw + $(INSTALL_BIN) ./files/qca-nss-drv.debug $(1)/usr/bin/nss_stats +endef + +define KernelPackage/qca-nss-drv/conffiles +/etc/config/nss +/etc/config/skb_recycler +endef + +define KernelPackage/qca-nss-drv/Description +This package contains a NSS driver for QCA chipset +endef + +ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq807x") + SOC="ipq807x_64" + subtarget:=$(CONFIG_TARGET_SUBTARGET) +else ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq60xx") + SOC="ipq60xx_64" + subtarget:=$(CONFIG_TARGET_SUBTARGET) +else ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq50xx") + SOC="ipq50xx_64" + subtarget:=$(CONFIG_TARGET_SUBTARGET) +endif + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-drv + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-drv/ +ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64" "ipq50xx" "ipq50xx_64")) + $(RM) $(1)/usr/include/qca-nss-drv/nss_ipsecmgr.h +endif +endef + +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-dp \ + -I$(STAGING_DIR)/usr/include/qca-ssdk \ + -Wno-missing-declarations -Wno-missing-prototypes \ + -Wno-empty-body -Wno-unused-variable + +ifdef CONFIG_NSS_MEM_PROFILE_MEDIUM + EXTRA_CFLAGS += -DNSS_MEM_PROFILE_MEDIUM +else ifdef CONFIG_NSS_MEM_PROFILE_LOW + EXTRA_CFLAGS += -DNSS_MEM_PROFILE_LOW +endif + +ifdef CONFIG_NSS_FIRMWARE_VERSION_12_5 + EXTRA_CFLAGS += -DNSS_FIRMWARE_VERSION_12_5 +endif + +DRV_MAKE_OPTS:= + +ifndef CONFIG_NSS_DRV_BRIDGE_ENABLE + DRV_MAKE_OPTS += NSS_DRV_BRIDGE_ENABLE=n +endif + +ifneq ($(CONFIG_TARGET_BOARD), "ipq806x") +ifndef CONFIG_NSS_DRV_C2C_ENABLE + DRV_MAKE_OPTS += NSS_DRV_C2C_ENABLE=n +endif +endif + +ifndef CONFIG_NSS_DRV_CLMAP_ENABLE + DRV_MAKE_OPTS += NSS_DRV_CLMAP_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_CRYPTO_ENABLE + DRV_MAKE_OPTS += NSS_DRV_CRYPTO_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_DTLS_ENABLE + DRV_MAKE_OPTS += NSS_DRV_DTLS_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_GRE_ENABLE +ifndef CONFIG_PACKAGE_kmod-gre + DRV_MAKE_OPTS += NSS_DRV_GRE_ENABLE=n +endif +endif + +ifndef CONFIG_NSS_DRV_GRE_REDIR_ENABLE + DRV_MAKE_OPTS += NSS_DRV_GRE_REDIR_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_GRE_TUNNEL_ENABLE + DRV_MAKE_OPTS += NSS_DRV_GRE_TUNNEL_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_IGS_ENABLE + DRV_MAKE_OPTS += NSS_DRV_IGS_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_IPSEC_ENABLE +ifndef CONFIG_PACKAGE_kmod-ipsec + DRV_MAKE_OPTS += NSS_DRV_IPSEC_ENABLE=n +endif +endif + +ifndef CONFIG_NSS_DRV_IPV4_REASM_ENABLE + DRV_MAKE_OPTS += NSS_DRV_IPV4_REASM_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_IPV6_ENABLE + DRV_MAKE_OPTS += NSS_DRV_IPV6_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_IPV6_REASM_ENABLE + DRV_MAKE_OPTS += NSS_DRV_IPV6_REASM_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_L2TP_ENABLE +ifndef CONFIG_PACKAGE_kmod-l2tp + DRV_MAKE_OPTS += NSS_DRV_L2TP_ENABLE=n +endif +endif + +ifndef CONFIG_NSS_DRV_LAG_ENABLE + DRV_MAKE_OPTS += NSS_DRV_LAG_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_MAPT_ENABLE +ifndef CONFIG_PACKAGE_kmod-nat46 + DRV_MAKE_OPTS += NSS_DRV_MAPT_ENABLE=n +endif +endif + +ifndef CONFIG_NSS_DRV_MATCH_ENABLE + DRV_MAKE_OPTS += NSS_DRV_MATCH_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_MIRROR_ENABLE + DRV_MAKE_OPTS += NSS_DRV_MIRROR_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_OAM_ENABLE + DRV_MAKE_OPTS += NSS_DRV_OAM_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_PORTID_ENABLE + DRV_MAKE_OPTS += NSS_DRV_PORTID_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_PPPOE_ENABLE +ifndef CONFIG_PACKAGE_kmod-pppoe + DRV_MAKE_OPTS += NSS_DRV_PPPOE_ENABLE=n +endif +endif + +ifndef CONFIG_NSS_DRV_PPTP_ENABLE +ifndef CONFIG_PACKAGE_kmod-pptp + DRV_MAKE_OPTS += NSS_DRV_PPTP_ENABLE=n +endif +endif + +ifndef CONFIG_NSS_DRV_PVXLAN_ENABLE + DRV_MAKE_OPTS += NSS_DRV_PVXLAN_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_QRFS_ENABLE + DRV_MAKE_OPTS += NSS_DRV_QRFS_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_QVPN_ENABLE + DRV_MAKE_OPTS += NSS_DRV_QVPN_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_OVPN_ENABLE + DRV_MAKE_OPTS += NSS_DRV_OVPN_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_RMNET_ENABLE + DRV_MAKE_OPTS += NSS_DRV_RMNET_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_SHAPER_ENABLE + DRV_MAKE_OPTS += NSS_DRV_SHAPER_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_SJACK_ENABLE + DRV_MAKE_OPTS += NSS_DRV_SJACK_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_TLS_ENABLE + DRV_MAKE_OPTS += NSS_DRV_TLS_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_TRUSTSEC_ENABLE + DRV_MAKE_OPTS += NSS_DRV_TRUSTSEC_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_TRUSTSEC_RX_ENABLE + DRV_MAKE_OPTS += NSS_DRV_TRUSTSEC_RX_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_TSTAMP_ENABLE + DRV_MAKE_OPTS += NSS_DRV_TSTAMP_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_TUN6RD_ENABLE +ifndef CONFIG_PACKAGE_kmod-sit + DRV_MAKE_OPTS += NSS_DRV_TUN6RD_ENABLE=n +endif +endif + +ifndef CONFIG_NSS_DRV_TUNIPIP6_ENABLE + DRV_MAKE_OPTS += NSS_DRV_TUNIPIP6_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_VIRT_IF_ENABLE + DRV_MAKE_OPTS += NSS_DRV_VIRT_IF_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_VLAN_ENABLE + DRV_MAKE_OPTS += NSS_DRV_VLAN_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_VXLAN_ENABLE + DRV_MAKE_OPTS += NSS_DRV_VXLAN_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_WIFIOFFLOAD_ENABLE + DRV_MAKE_OPTS += NSS_DRV_WIFIOFFLOAD_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_WIFI_EXT_VDEV_ENABLE + DRV_MAKE_OPTS += NSS_DRV_WIFI_EXT_VDEV_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_WIFI_MESH_ENABLE + DRV_MAKE_OPTS += NSS_DRV_WIFI_MESH_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_UDP_ST_ENABLE + DRV_MAKE_OPTS += NSS_DRV_UDP_ST_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_CAPWAP_ENABLE + DRV_MAKE_OPTS += NSS_DRV_CAPWAP_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_LSO_RX_ENABLE + DRV_MAKE_OPTS += NSS_DRV_LSO_RX_ENABLE=n +endif + +ifndef CONFIG_NSS_DRV_WIFI_LEGACY_ENABLE + DRV_MAKE_OPTS += NSS_DRV_WIFI_LEGACY_ENABLE=n +endif + +define Build/Configure + $(LN) arch/nss_$(SOC).h $(PKG_BUILD_DIR)/exports/nss_arch.h +endef + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" $(strip $(DRV_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv)) diff --git a/qca-nss-drv/files/qca-nss-drv.debug b/qca-nss-drv/files/qca-nss-drv.debug new file mode 100644 index 0000000..3e95310 --- /dev/null +++ b/qca-nss-drv/files/qca-nss-drv.debug @@ -0,0 +1,89 @@ +#!/bin/sh +# shellcheck disable=2046,3037,3010 +############################################################################### +# QCA NSS Driver Debug Script +# version 20250631 +# +# Requires: NSS Driver 11.4+ +# Usage: /lib/debug/qca-nss-drv (no arguments) +# Description: Display non-zero NSS statistics with color highlighting +# (requires a terminal that supports ANSI escape codes) +# +# Maintainer: Sean Khan (https://forum.openwrt.org/u/qosmio) +# NSS Packages Repository: https://github.com/qosmio/nss-packages (branch: NSS-12.5-K6.x) +# +color() { + awk ' +function color(c, s) { + if ($3 > 0) { + if ($3 ~ /^[0-9]+/ && $3 > 0 && $0 ~ /%/ ) c = 3 + if ($2 ~ /Avg/ ) c = 4 + if ($1 ~ /#/ ) c = 7 + if ($3 ~ /^[0-9]+$/ && $3 > 0 && $0 ~ /=/ ) c = 3 + if ($0 ~ /< /dev/console + echo 1 > /sys/class/firmware/"$DEVICENAME"/loading + cat "$1" > /sys/class/firmware/"$DEVICENAME"/data + echo 0 > /sys/class/firmware/"$DEVICENAME"/loading +} + +select_nss_fw() { + rm -f /lib/firmware/"$DEVICENAME" + ln -s "$1" /lib/firmware/"$DEVICENAME" + echo '<5>hotplug: symlinking' "$DEVICENAME"' to '"$1" > /dev/kmsg +} + +[ "$ACTION" != "add" ] && exit + +# dev name for UCI, since it doesn't let you use . or - +SDEVNAME=$(echo "${DEVICENAME}" | sed s/[.-]/_/g) + +SELECTED_FW=$(uci get nss."${SDEVNAME}".firmware 2> /dev/null) +[ -e "${SELECTED_FW}" ] && { + $select_or_load "${SELECTED_FW}" + exit +} + +case $DEVICENAME in + qca-nss0* | qca-nss.0*) + if [ -e /lib/firmware/qca-nss0-enterprise.bin ]; then + $select_or_load /lib/firmware/qca-nss0-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss0-retail.bin + fi + exit + ;; + qca-nss1* | qca-nss.1*) + if [ -e /lib/firmware/qca-nss1-enterprise.bin ]; then + $select_or_load /lib/firmware/qca-nss1-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss1-retail.bin + fi + exit + ;; +esac diff --git a/qca-nss-drv/files/qca-nss-drv.init b/qca-nss-drv/files/qca-nss-drv.init new file mode 100644 index 0000000..10f60ff --- /dev/null +++ b/qca-nss-drv/files/qca-nss-drv.init @@ -0,0 +1,143 @@ +#!/bin/sh /etc/rc.common +# vim: set syn=bash +# shellcheck disable=2155,3010,3019,3043,3057,3060 + +# shellcheck disable=2034 +START=94 +PROG="qca-nss-drv" + +log_msg() { + + local irq_name="$1" affinity="$2" occurrence="$3" irq="$4" + + msg="$(printf "Pinning IRQ($irq) %-24s to CPU ${affinity}\n" "$irq_name")" + + [[ $irq_name =~ "nss" ]] && msg="$msg (NSS Core $((occurrence - 1)))" + + logger -t "$PROG" "$msg" +} + +###################################################################### +### Takes a comma, space separated, or range list of CPU numbers and +## returns a bitmask of CPUs. +## cpus_to_bitmask "0,1,2,3" -> f +## cpus_to_bitmask "0 1 2 3" -> f +## cpus_to_bitmask "0-3" -> f +## cpus_to_bitmask "3" -> 8 +####################################################################### + +cpus_to_bitmask() { + + local bitmask=0 + # shellcheck disable=2048 + for range in ${*//,/ }; do + start="${range%-*}" + end="${range#*-}" + if [ -z "$end" ]; then + bitmask="$((bitmask | 1 << start))" + else + bitmask="$((bitmask | (2 ** (end - start + 1) - 1) << start))" + fi + done + printf '%x' $bitmask +} + +###################################################################### +### Takes a bitmask of CPUs and returns a space separated list of +## CPU numbers. +## bitmask_to_cpus f -> 0 1 2 3 +###################################################################### + +bitmask_to_cpus() { + + [ "${1:0:2}" != "0x" ] && set -- "0x$1" + local bitmask="$(printf '%d' "$1")" + + local cpus="" + for i in $(seq 0 63); do + if [ $((bitmask & 1)) -ne 0 ]; then + cpus="$cpus $i" + fi + bitmask=$((bitmask >> 1)) + done + echo "${cpus# }" +} + +###################################################################### +### Sets the affinity of the IRQs with the given name to the given CPU. +## first argument: IRQ name ("nss_queue0") +## second argument: CPU number +## third argument: occurrence of the IRQ name +## since NSS core 0/1 share the same IRQ names +## set_affinity "nss_queue0" 1 1 + +set_affinity() { + + local irq_name="$1" affinity="$2" occurrence="${3:-1}" bitmask + + awk -v irq_name="$irq_name" -v occurrence="$occurrence" ' + BEGIN{count=0} + $NF==irq_name { + if(++count==occurrence){ + sub(/:$/,"",$1) + print $1 + } + }' /proc/interrupts | while read -r irq; do + $enable_log && { + log_msg "$irq_name" "$affinity" "$occurrence" "$irq" + } + bitmask=$(cpus_to_bitmask "$affinity") && echo "$bitmask" > /proc/irq/"$irq"/smp_affinity + done +} + +enable_rps() { + + # NSS Core 0 : 4 nss queues to each core + set_affinity "nss_queue0" 0 1 + set_affinity "nss_queue1" 1 1 + set_affinity "nss_queue2" 2 1 + set_affinity "nss_queue3" 3 1 + + # NSS Core 1 : 1 nss queue to 3rd core + set_affinity "nss_queue0" 3 2 + set_affinity "nss_queue1" 2 2 + set_affinity "nss_queue2" 1 2 + set_affinity "nss_queue3" 0 2 + + # NSS Core 0 : 2 nss sos/queues to last core + set_affinity "nss_empty_buf_sos" 0 1 + set_affinity "nss_empty_buf_queue" 0 1 + + # NSS Core 1 : 1 nss sos to last core + set_affinity "nss_empty_buf_sos" 3 2 + set_affinity "nss_empty_buf_queue" 3 2 + + # USB 3.0 : pin to 3rd core + set_affinity "xhci-hcd:usb1" 2 1 + set_affinity "xhci-hcd:usb2" 2 1 + set_affinity "xhci-hcd:usb3" 2 1 + + # TCL Completion, REO Dest, ERR, Exception and h2rxdma + # are offloaded, so balance remaining IRQs accordingly. + # PPDU IRQ : pin to 2nd and 3rd core + set_affinity 'ppdu-end-interrupts-mac1' 2 1 + set_affinity 'ppdu-end-interrupts-mac2' 3 1 + set_affinity 'ppdu-end-interrupts-mac3' 1 1 + + set_affinity 'ath10k_pci' 2,3 1 + + # Enable NSS RPS + sysctl -w dev.nss.rps.enable=1 >/dev/null 2>&1 +} + +start() { + + local enable_rps + + config_load nss + config_get enable_rps "general" enable_rps 1 + config_get_bool enable_log "general" enable_log 1 + + [ "$enable_log" -eq 1 ] && enable_log=true || enable_log=false + [ "$enable_rps" -eq 1 ] && enable_rps +} diff --git a/qca-nss-drv/files/qca-nss-drv.uci b/qca-nss-drv/files/qca-nss-drv.uci new file mode 100644 index 0000000..4a8b766 --- /dev/null +++ b/qca-nss-drv/files/qca-nss-drv.uci @@ -0,0 +1,3 @@ +config nss 'general' + option enable_rps '1' + option enable_log '1' diff --git a/qca-nss-drv/files/skb_recycler.init b/qca-nss-drv/files/skb_recycler.init new file mode 100644 index 0000000..5cfaeef --- /dev/null +++ b/qca-nss-drv/files/skb_recycler.init @@ -0,0 +1,92 @@ +#!/bin/sh /etc/rc.common +# shellcheck disable=3043 + +START=40 +USE_PROCD=1 +NAME=skb_recycler + +ucidef_set_skb_recycler() { + uci import << EOF +package $NAME +config $NAME 'opt' +EOF + +} + +skb_recycler_config() { + + . /lib/config/uci.sh + + local CFG + local max_skbs + local max_spare_skbs + local enable + local memtotal + CFG="$1" + + config_get max_skbs "${CFG}" max_skbs + config_get max_spare_skbs "${CFG}" max_spare_skbs + config_get enable "${CFG}" enable + + memtotal=$(awk '/MemTotal/{print $2}' /proc/meminfo) + + [ -z "$max_skbs" ] && { + [ $memtotal -le 512000 ] && max_skbs=512 || max_skbs=1024 + uci_set $NAME "${CFG}" max_skbs "$max_skbs" + uci_commit "$NAME" + } + + [ -z "$max_spare_skbs" ] && { + [ $memtotal -le 512000 ] && max_spare_skbs=128 || max_spare_skbs=256 + uci_set $NAME "${CFG}" max_spare_skbs "$max_spare_skbs" + uci_commit "$NAME" + } + + [ -z "$enable" ] && { + [ $memtotal -le 256000 ] && enable=0 || enable=1 + uci_set $NAME "${CFG}" enable "$enable" + uci_commit "$NAME" + } + + [ "$enable" -eq 0 ] && enable_disable="Disabling" || enable_disable="Enabling" + + if [ -r "/proc/net/$NAME/skb_recycler_enable" ]; then + logger -t "$NAME" -p user.notice "$enable_disable $NAME" + echo "$enable" > /proc/net/$NAME/skb_recycler_enable + else + if [ "$enable" -eq 0 ]; then + logger -t "$NAME" -p user.warn "$NAME kernel feature 'skb_recycler_enable' not available" + logger -t "$NAME" -p user.notice "$enable_disable $NAME" + echo 1 > /proc/net/$NAME/max_skbs + echo 1 > /proc/net/$NAME/max_spare_skbs + echo 1 > /proc/net/$NAME/flush + fi + fi + + logger -t "$NAME" -p user.notice "Setting max_skbs to $max_skbs" + echo "$max_skbs" > /proc/net/$NAME/max_skbs + + logger -t "$NAME" -p user.notice "Setting max_spare_skbs to $max_spare_skbs" + echo "$max_spare_skbs" > /proc/net/$NAME/max_spare_skbs + + [ "$enable" -eq 0 ] && echo 1 > /proc/net/$NAME/flush +} + +check_config() { + config_load "$NAME" || { + touch /etc/config/$NAME + ucidef_set_skb_recycler + } +} + +reload_service() { + [ ! -r /proc/net/$NAME ] && logger -t "$NAME" -p user.warn "skb_recycler feature not available" && return + + check_config + config_load $NAME + config_foreach skb_recycler_config $NAME +} + +start_service() { + reload_service +} diff --git a/qca-nss-drv/files/skb_recycler.uci b/qca-nss-drv/files/skb_recycler.uci new file mode 100644 index 0000000..c9ee862 --- /dev/null +++ b/qca-nss-drv/files/skb_recycler.uci @@ -0,0 +1,6 @@ + +config skb_recycler 'opt' + option max_skbs '1024' + option max_spare_skbs '512' + option enable '0' + diff --git a/qca-nss-drv/patches-11.4/0001-nss-drv-replace-ioremap_nocache-with-ioremap.patch b/qca-nss-drv/patches-11.4/0001-nss-drv-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 0000000..c749a68 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0001-nss-drv-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,178 @@ +From dddfe22459a988a5b86d195bc3cc3bd3c2ac7037 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 14 Jan 2023 21:52:38 +0100 +Subject: [PATCH 1/4] nss-drv: replace ioremap_nocache() with ioremap() + +Since 5.5 ioremap_nocache is equal to ioremap on all archs and was removed +from the kernel, so just use ioremap instead. + +Signed-off-by: Robert Marko +--- + nss_hal/fsm9010/nss_hal_pvt.c | 2 +- + nss_hal/ipq50xx/nss_hal_pvt.c | 6 +++--- + nss_hal/ipq60xx/nss_hal_pvt.c | 8 ++++---- + nss_hal/ipq806x/nss_hal_pvt.c | 4 ++-- + nss_hal/ipq807x/nss_hal_pvt.c | 6 +++--- + nss_hal/ipq95xx/nss_hal_pvt.c | 6 +++--- + nss_hal/nss_hal.c | 4 ++-- + nss_meminfo.c | 2 +- + nss_ppe.c | 2 +- + 9 files changed, 20 insertions(+), 20 deletions(-) + +--- a/nss_hal/fsm9010/nss_hal_pvt.c ++++ b/nss_hal/fsm9010/nss_hal_pvt.c +@@ -145,7 +145,7 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->vphys = res_vphys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +--- a/nss_hal/ipq50xx/nss_hal_pvt.c ++++ b/nss_hal/ipq50xx/nss_hal_pvt.c +@@ -184,13 +184,13 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -348,7 +348,7 @@ static int __nss_hal_common_reset(struct + + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; +--- a/nss_hal/ipq60xx/nss_hal_pvt.c ++++ b/nss_hal/ipq60xx/nss_hal_pvt.c +@@ -207,13 +207,13 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -433,13 +433,13 @@ static int __nss_hal_common_reset(struct + + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; + } + +- nss_misc_reset_flag = ioremap_nocache(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); ++ nss_misc_reset_flag = ioremap(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); + if (!nss_misc_reset_flag) { + pr_err("%px: ioremap fail for nss_misc_reset_flag\n", nss_dev); + return -EFAULT; +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -458,7 +458,7 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->vphys = res_vphys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +@@ -711,7 +711,7 @@ static int __nss_hal_common_reset(struct + } + of_node_put(cmn); + +- fpb_base = ioremap_nocache(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); ++ fpb_base = ioremap(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); + if (!fpb_base) { + pr_err("%px: ioremap fail for nss_fpb_base\n", nss_dev); + return -EFAULT; +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -234,7 +234,7 @@ static struct nss_platform_data *__nss_h + npd->vphys = res_vphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +@@ -247,7 +247,7 @@ static struct nss_platform_data *__nss_h + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -467,7 +467,7 @@ static int __nss_hal_common_reset(struct + } + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -78,9 +78,9 @@ int nss_hal_firmware_load(struct nss_ctx + return rc; + } + +- load_mem = ioremap_nocache(npd->load_addr, nss_fw->size); ++ load_mem = ioremap(npd->load_addr, nss_fw->size); + if (!load_mem) { +- nss_info_always("%px: ioremap_nocache failed: %x", nss_ctx, npd->load_addr); ++ nss_info_always("%px: ioremap failed: %x", nss_ctx, npd->load_addr); + release_firmware(nss_fw); + return rc; + } +--- a/nss_meminfo.c ++++ b/nss_meminfo.c +@@ -728,7 +728,7 @@ bool nss_meminfo_init(struct nss_ctx_ins + /* + * meminfo_start is the label where the start address of meminfo map is stored. + */ +- meminfo_start = (uint32_t *)ioremap_nocache(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, ++ meminfo_start = (uint32_t *)ioremap(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, + NSS_MEMINFO_RESERVE_AREA_SIZE); + if (!meminfo_start) { + nss_info_always("%px: cannot remap meminfo start\n", nss_ctx); +--- a/nss_ppe.c ++++ b/nss_ppe.c +@@ -357,7 +357,7 @@ void nss_ppe_init(void) + /* + * Get the PPE base address + */ +- ppe_pvt.ppe_base = ioremap_nocache(PPE_BASE_ADDR, PPE_REG_SIZE); ++ ppe_pvt.ppe_base = ioremap(PPE_BASE_ADDR, PPE_REG_SIZE); + if (!ppe_pvt.ppe_base) { + nss_warning("DRV can't get PPE base address\n"); + return; diff --git a/qca-nss-drv/patches-11.4/0002-Control-fab-scaling-from-package-Makefile.patch b/qca-nss-drv/patches-11.4/0002-Control-fab-scaling-from-package-Makefile.patch new file mode 100644 index 0000000..5e3f58b --- /dev/null +++ b/qca-nss-drv/patches-11.4/0002-Control-fab-scaling-from-package-Makefile.patch @@ -0,0 +1,31 @@ +From 40d4b080f17883ac6b39c74a5feb1af384ab6a51 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 11 Jun 2020 16:57:39 +0200 +Subject: [PATCH] nss-drv: Control fab scaling from package Makefile + +Lets control the fab scaling from the package Makefile +instead of using kernel checks that dont work. +Fab scaling in OpenWrt is done in a external way. + +Signed-off-by: Robert Marko +--- + Makefile | 9 --------- + 1 file changed, 9 deletions(-) + +--- a/Makefile ++++ b/Makefile +@@ -510,14 +510,7 @@ NSS_CCFLAGS = -DNSS_DT_SUPPORT=1 -DNSS_F + ccflags-y += -I$(obj) + endif + +-# Fabric scaling is supported in 3.14 and 4.4 only +-ifneq ($(findstring 3.14, $(KERNELVERSION)),) +-NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=1 +-else ifneq ($(findstring 4.4, $(KERNELVERSION)),) +-NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=1 +-else + NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=0 +-endif + + # Disable Frequency scaling + ifeq "$(NSS_FREQ_SCALE_DISABLE)" "y" diff --git a/qca-nss-drv/patches-11.4/0005-fix-NULL-pointer-exception.patch b/qca-nss-drv/patches-11.4/0005-fix-NULL-pointer-exception.patch new file mode 100644 index 0000000..2100eac --- /dev/null +++ b/qca-nss-drv/patches-11.4/0005-fix-NULL-pointer-exception.patch @@ -0,0 +1,11 @@ +--- a/nss_core.c ++++ b/nss_core.c +@@ -1616,7 +1616,7 @@ static int32_t nss_core_handle_cause_que + * + */ + if (unlikely((buffer_type == N2H_BUFFER_CRYPTO_RESP))) { +- dma_unmap_single(NULL, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); ++ dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); + goto consume; + } + diff --git a/qca-nss-drv/patches-11.4/0006-Fix-Kernel-Panic-dma-with-NULL-dev.patch b/qca-nss-drv/patches-11.4/0006-Fix-Kernel-Panic-dma-with-NULL-dev.patch new file mode 100644 index 0000000..a11dc94 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0006-Fix-Kernel-Panic-dma-with-NULL-dev.patch @@ -0,0 +1,30 @@ +From 89949decfd9a0f86427b502aae4fbc3a3ef399f0 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 23 Jun 2020 19:50:28 +0200 +Subject: [PATCH] Fix Kernel Panic dma with NULL dev + +--- + nss_coredump.c | 4 ++-- + nss_log.c | 8 +++++--- + 2 files changed, 8 insertions(+), 6 deletions(-) + +--- a/nss_coredump.c ++++ b/nss_coredump.c +@@ -154,7 +154,7 @@ void nss_fw_coredump_notify(struct nss_c + dma_addr = nss_own->meminfo_ctx.logbuffer_dma; + } + +- dma_sync_single_for_cpu(NULL, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_own->dev, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); + + /* + * If the current entry is smaller than or equal to the number of NSS_LOG_COREDUMP_LINE_NUM, +@@ -181,7 +181,7 @@ void nss_fw_coredump_notify(struct nss_c + + offset = (index * sizeof(struct nss_log_entry)) + + offsetof(struct nss_log_descriptor, log_ring_buffer); +- dma_sync_single_for_cpu(NULL, dma_addr + offset, ++ dma_sync_single_for_cpu(nss_own->dev, dma_addr + offset, + sizeof(struct nss_log_entry), DMA_FROM_DEVICE); + nss_info_always("%px: %s\n", nss_own, nle_print->message); + nle_print++; diff --git a/qca-nss-drv/patches-11.4/0006-nss-drv-Fix-nss_clmap_stats-enum-int-compilation-error-GCC-13.patch b/qca-nss-drv/patches-11.4/0006-nss-drv-Fix-nss_clmap_stats-enum-int-compilation-error-GCC-13.patch new file mode 100644 index 0000000..7cdb012 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0006-nss-drv-Fix-nss_clmap_stats-enum-int-compilation-error-GCC-13.patch @@ -0,0 +1,11 @@ +--- a/nss_clmap_stats.c ++++ b/nss_clmap_stats.c +@@ -63,7 +63,7 @@ void nss_clmap_stats_session_unregister( + * nss_clmap_stats_session_register + * Register debug statistic for clmap session. + */ +-bool nss_clmap_stats_session_register(uint32_t if_num, uint32_t if_type, struct net_device *netdev) ++bool nss_clmap_stats_session_register(uint32_t if_num, enum nss_clmap_interface_type if_type, struct net_device *netdev) + { + uint32_t i; + bool stats_status = false; diff --git a/qca-nss-drv/patches-11.4/0007-Exported-set-nexthop-function.patch b/qca-nss-drv/patches-11.4/0007-Exported-set-nexthop-function.patch new file mode 100644 index 0000000..7c23a04 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0007-Exported-set-nexthop-function.patch @@ -0,0 +1,23 @@ +From f8cf061454a3707c0c84d0fca685e84455f91362 Mon Sep 17 00:00:00 2001 +From: Suruchi Suman +Date: Tue, 3 Dec 2019 12:57:38 +0530 +Subject: [qca-nss-drv] Exported set nexhop function from drv. + +Change-Id: I3df6658bef72fe574ac9acfb7aac61785769766f +Signed-off-by: Suruchi Suman +--- + nss_phys_if.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -52,7 +52,8 @@ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))))) ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) + #error "Check skb recycle code in this file to match Linux version" + #endif + diff --git a/qca-nss-drv/patches-11.4/0007-nss-drv-Fix-nss_wifili_if-compilation-error-GCC-13.patch b/qca-nss-drv/patches-11.4/0007-nss-drv-Fix-nss_wifili_if-compilation-error-GCC-13.patch new file mode 100644 index 0000000..1d7e8c9 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0007-nss-drv-Fix-nss_wifili_if-compilation-error-GCC-13.patch @@ -0,0 +1,11 @@ +--- a/exports/nss_wifili_if.h ++++ b/exports/nss_wifili_if.h +@@ -1995,7 +1995,7 @@ void nss_wifili_release_external_if(nss_ + */ + uint8_t nss_wifili_thread_scheme_alloc(struct nss_ctx_instance *nss_ctx, + int32_t radio_ifnum, +- uint32_t radio_priority); ++ enum nss_wifili_thread_scheme_priority radio_priority); + + /** + * nss_wifili_thread_scheme_dealloc diff --git a/qca-nss-drv/patches-11.4/0009-kernel-5.15-support.patch b/qca-nss-drv/patches-11.4/0009-kernel-5.15-support.patch new file mode 100644 index 0000000..6cec4e4 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0009-kernel-5.15-support.patch @@ -0,0 +1,85 @@ +From 2a3b9f4659542e529f4e1a535c33dfde7e272707 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 5 Apr 2022 18:10:57 +0200 +Subject: [PATCH 2/4] nss-drv: add support for kernel 5.15 + +- Fix coredump panic notifier include change. +- Fix skb ZEROCOPY flag. +- Add skb reuse support for 5.15 kernel version. + +Signed-off-by: Ansuel Smith +--- + nss_core.c | 5 +++-- + nss_coredump.c | 4 ++++ + nss_hal/nss_hal.c | 1 + + 3 files changed, 9 insertions(+), 2 deletions(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -53,7 +53,9 @@ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))) || \ ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)))) || \ ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0)))))) + #error "Check skb recycle code in this file to match Linux version" + #endif + +@@ -2580,7 +2582,7 @@ static inline bool nss_core_skb_can_reus + if (unlikely(irqs_disabled())) + return false; + +- if (unlikely(skb_shinfo(nbuf)->tx_flags & SKBTX_DEV_ZEROCOPY)) ++ if (unlikely(skb_shinfo(nbuf)->flags & SKBFL_ZEROCOPY_ENABLE)) + return false; + + if (unlikely(skb_is_nonlinear(nbuf))) +--- a/nss_coredump.c ++++ b/nss_coredump.c +@@ -23,7 +23,11 @@ + #include "nss_hal.h" + #include "nss_log.h" + #include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) + #include /* for panic_notifier_list */ ++#else ++#include ++#endif + #include /* for time */ + #include "nss_tx_rx_common.h" + +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + + #include "nss_hal.h" + #include "nss_arch.h" +@@ -57,9 +58,9 @@ int nss_hal_firmware_load(struct nss_ctx + int rc; + + if (nss_ctx->id == 0) { +- rc = request_firmware(&nss_fw, NSS_AP0_IMAGE, &(nss_dev->dev)); ++ rc = firmware_request_nowarn(&nss_fw, NSS_AP0_IMAGE, &(nss_dev->dev)); + } else if (nss_ctx->id == 1) { +- rc = request_firmware(&nss_fw, NSS_AP1_IMAGE, &(nss_dev->dev)); ++ rc = firmware_request_nowarn(&nss_fw, NSS_AP1_IMAGE, &(nss_dev->dev)); + } else { + nss_warning("%px: Invalid nss dev: %d\n", nss_ctx, nss_ctx->id); + return -EINVAL; +--- a/nss_data_plane/nss_data_plane_gmac.c ++++ b/nss_data_plane/nss_data_plane_gmac.c +@@ -20,7 +20,7 @@ + #include "nss_tx_rx_common.h" + #include + +-#define NSS_DP_GMAC_SUPPORTED_FEATURES (NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_FRAGLIST | (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_UFO)) ++#define NSS_DP_GMAC_SUPPORTED_FEATURES (NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_FRAGLIST | (NETIF_F_TSO | NETIF_F_TSO6)) + #define NSS_DATA_PLANE_GMAC_MAX_INTERFACES 4 + + static DEFINE_SPINLOCK(nss_data_plane_gmac_stats_lock); diff --git a/qca-nss-drv/patches-11.4/0010-nss-drv-dynamic-interface-desc.patch b/qca-nss-drv/patches-11.4/0010-nss-drv-dynamic-interface-desc.patch new file mode 100644 index 0000000..6d3434b --- /dev/null +++ b/qca-nss-drv/patches-11.4/0010-nss-drv-dynamic-interface-desc.patch @@ -0,0 +1,18 @@ +--- a/nss_dynamic_interface_stats.c ++++ b/nss_dynamic_interface_stats.c +@@ -87,8 +87,15 @@ const char *nss_dynamic_interface_type_n + "NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_H2N", + "NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_EXTERNAL0", + "NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_EXTERNAL1", ++ "NSS_DYNAMIC_INTERFACE_TYPE_TLS_INNER", ++ "NSS_DYNAMIC_INTERFACE_TYPE_TLS_OUTER", ++ "NSS_DYNAMIC_INTERFACE_TYPE_MIRROR", ++ "NSS_DYNAMIC_INTERFACE_TYPE_WIFI_EXT_VDEV_WDS", + "NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER", + "NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER", ++ "NSS_DYNAMIC_INTERFACE_TYPE_WIFI_EXT_VDEV_VLAN", ++ "NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER", ++ "NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER" + }; + + /* diff --git a/qca-nss-drv/patches-11.4/0011-rework-getting-the-reserved-memory-size.patch b/qca-nss-drv/patches-11.4/0011-rework-getting-the-reserved-memory-size.patch new file mode 100644 index 0000000..8feb18b --- /dev/null +++ b/qca-nss-drv/patches-11.4/0011-rework-getting-the-reserved-memory-size.patch @@ -0,0 +1,114 @@ +From 1c2b564d7b29644765925a784d468f40555ded8a Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 10 Feb 2023 12:50:51 +0100 +Subject: [PATCH] nss-drv: rework getting the reserved-memory size + +Currently, the way NSS DRV gets the reserved memory node strictly depends +on the nss@40000000 node being present so it can find it after globaly +looking for the reserved-memory node and then going through its children. + +After that its evaluation the address and size cells manually in order to +properly calculate the size of reserved-memory. + +We can make this way more reliable and generic, so lets pass the memory +region wia the NSS common DTS node, match it via its compatible and then +get the memory region phandle and simply convert it to a resource. + +Signed-off-by: Robert Marko +--- + nss_core.c | 70 +++++++++++++++++++++++------------------------------- + 1 file changed, 30 insertions(+), 40 deletions(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -23,6 +23,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #ifdef CONFIG_BRIDGE_NETFILTER +@@ -451,50 +453,38 @@ static void nss_core_handle_crypto_pkt(s + */ + static uint32_t nss_soc_mem_info(void) + { +- struct device_node *node; +- struct device_node *snode; +- int addr_cells; +- int size_cells; +- int n_items; +- uint32_t nss_msize = 8 << 20; /* default: 8MB */ +- const __be32 *ppp; +- +- node = of_find_node_by_name(NULL, "reserved-memory"); +- if (!node) { +- nss_info_always("reserved-memory not found\n"); +- return nss_msize; +- } +- +- ppp = (__be32 *)of_get_property(node, "#address-cells", NULL); +- addr_cells = ppp ? be32_to_cpup(ppp) : 2; +- nss_info("%px addr cells %d\n", ppp, addr_cells); +- ppp = (__be32 *)of_get_property(node, "#size-cells", NULL); +- size_cells = ppp ? be32_to_cpup(ppp) : 2; +- nss_info("%px size cells %d\n", ppp, size_cells); +- +- for_each_child_of_node(node, snode) { +- /* +- * compare (snode->full_name, "/reserved-memory/nss@40000000") may be safer +- */ +- nss_info("%px snode %s fn %s\n", snode, snode->name, snode->full_name); +- if (strcmp(snode->name, "nss") == 0) +- break; +- } +- of_node_put(node); +- if (!snode) { +- nss_info_always("nss@node not found: needed to determine NSS reserved DDR\n"); +- return nss_msize; +- } +- +- ppp = (__be32 *)of_get_property(snode, "reg", &n_items); +- if (ppp) { +- n_items /= sizeof(ppp[0]); +- nss_msize = be32_to_cpup(ppp + addr_cells + size_cells - 1); +- nss_info_always("addr/size storage words %d %d # words %d in DTS, ddr size %x\n", +- addr_cells, size_cells, n_items, nss_msize); ++ struct device_node *common_node, *memory_node; ++ struct resource r; ++ int ret; ++ ++ common_node = of_find_compatible_node(NULL, NULL, "qcom,nss-common"); ++ if (!common_node) { ++ nss_info_always("NSS common node not found!\n"); ++ goto err_use_default_memsize; ++ } ++ ++ memory_node = of_parse_phandle(common_node, "memory-region", 0); ++ if (!memory_node) { ++ nss_info_always("NSS reserved-memory node not found!\n"); ++ goto err_use_default_memsize; ++ } ++ ++ ret = of_address_to_resource(memory_node, 0, &r); ++ of_node_put(common_node); ++ of_node_put(memory_node); ++ if (ret) { ++ nss_info_always("NSS reserved-memory resource not found!\n"); ++ goto err_use_default_memsize; + } +- of_node_put(snode); +- return nss_msize; ++ ++ nss_info_always("NSS DDR size is 0x%x\n", (uint32_t) resource_size(&r)); ++ ++ return resource_size(&r); ++ ++err_use_default_memsize: ++ nss_info_always("Using default NSS reserved-memory size of 0x%x !\n", SZ_8M); ++ ++ return SZ_8M; + } + + /* diff --git a/qca-nss-drv/patches-11.4/0012-Makefile-modularize-driver.patch b/qca-nss-drv/patches-11.4/0012-Makefile-modularize-driver.patch new file mode 100644 index 0000000..8ad2124 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0012-Makefile-modularize-driver.patch @@ -0,0 +1,188 @@ +--- a/Makefile ++++ b/Makefile +@@ -5,6 +5,9 @@ + obj-m += qca-nss-drv.o + + # ++# Regular NSS path ++# ++# + # List the files that belong to the driver in alphabetical order. + # + qca-nss-drv-objs := \ +@@ -16,57 +19,38 @@ qca-nss-drv-objs := \ + nss_dynamic_interface.o \ + nss_dynamic_interface_log.o \ + nss_dynamic_interface_stats.o \ +- nss_eth_rx.o \ +- nss_eth_rx_stats.o \ +- nss_eth_rx_strings.o \ +- nss_gmac_stats.o \ +- nss_if.o \ +- nss_if_log.o \ + nss_init.o \ +- nss_ipv4.o \ +- nss_ipv4_stats.o \ +- nss_ipv4_strings.o \ +- nss_ipv4_log.o \ + nss_log.o \ +- nss_lso_rx.o \ +- nss_lso_rx_stats.o \ +- nss_lso_rx_strings.o \ + nss_meminfo.o \ + nss_n2h.o \ + nss_n2h_stats.o \ + nss_n2h_strings.o \ +- nss_phys_if.o \ + nss_pm.o \ + nss_profiler.o \ + nss_project.o \ +- nss_pppoe.o \ +- nss_pppoe_log.o \ +- nss_pppoe_stats.o \ +- nss_pppoe_strings.o \ + nss_rps.o \ + nss_stats.o \ + nss_strings.o \ +- nss_tx_msg_sync.o \ + nss_unaligned.o \ + nss_unaligned_log.o \ +- nss_unaligned_stats.o \ ++ nss_unaligned_stats.o ++ ++# Base NSS HAL support ++qca-nss-drv-objs += nss_hal/nss_hal.o ++ ++ifneq "$(NSS_DRV_POINT_OFFLOAD)" "y" ++qca-nss-drv-objs += \ ++ nss_gmac_stats.o \ ++ nss_if.o \ ++ nss_if_log.o \ ++ nss_phys_if.o \ ++ nss_tx_msg_sync.o \ + nss_virt_if.o \ +- nss_virt_if_stats.o \ +- nss_vlan.o \ +- nss_vlan_log.o \ +- nss_wifi.o \ +- nss_wifi_log.o \ +- nss_wifi_stats.o \ +- nss_wifi_vdev.o \ +- nss_wifili.o \ +- nss_wifili_log.o \ +- nss_wifili_stats.o \ +- nss_wifili_strings.o \ +- nss_wifi_mac_db.o ++ nss_virt_if_stats.o + +-# Base NSS data plane/HAL support ++# Base NSS data plane support + qca-nss-drv-objs += nss_data_plane/nss_data_plane_common.o +-qca-nss-drv-objs += nss_hal/nss_hal.o ++endif + + ifneq "$(NSS_DRV_BRIDGE_ENABLE)" "n" + ccflags-y += -DNSS_DRV_BRIDGE_ENABLE +@@ -332,7 +316,70 @@ qca-nss-drv-objs += \ + nss_udp_st_strings.o + endif + ++ifneq "$(NSS_DRV_IPV4_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_IPV4_ENABLE ++qca-nss-drv-objs += \ ++ nss_ipv4.o \ ++ nss_ipv4_stats.o \ ++ nss_ipv4_strings.o \ ++ nss_ipv4_log.o ++endif ++ ++ifneq "$(NSS_DRV_ETH_RX_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_ETH_RX_ENABLE ++qca-nss-drv-objs += \ ++ nss_eth_rx.o \ ++ nss_eth_rx_stats.o \ ++ nss_eth_rx_strings.o ++endif ++ ++ifneq "$(NSS_DRV_PPPOE_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_PPPOE_ENABLE ++qca-nss-drv-objs += \ ++ nss_pppoe.o \ ++ nss_pppoe_log.o \ ++ nss_pppoe_stats.o \ ++ nss_pppoe_strings.o ++endif ++ ++ifneq "$(NSS_DRV_WIFIOFFLOAD_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_WIFIOFFLOAD_ENABLE ++ifneq "$(NSS_DRV_WIFI_LEGACY_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_WIFI_LEGACY_ENABLE ++qca-nss-drv-objs += \ ++ nss_wifi.o \ ++ nss_wifi_log.o \ ++ nss_wifi_stats.o + ifeq ($(SoC),$(filter $(SoC),ipq806x)) ++ccflags-y += -DNSS_HAL_IPQ806x_SUPPORT ++endif ++endif ++qca-nss-drv-objs += \ ++ nss_wifi_vdev.o \ ++ nss_wifili.o \ ++ nss_wifili_log.o \ ++ nss_wifili_stats.o \ ++ nss_wifili_strings.o \ ++ nss_wifi_mac_db.o ++endif ++ ++ifneq "$(NSS_DRV_VLAN_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_VLAN_ENABLE ++qca-nss-drv-objs += \ ++ nss_vlan.o \ ++ nss_vlan_log.o ++endif ++ ++ifneq "$(NSS_DRV_LSO_RX_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_LSO_RX_ENABLE ++qca-nss-drv-objs += \ ++ nss_lso_rx.o \ ++ nss_lso_rx_stats.o \ ++ nss_lso_rx_strings.o ++endif ++ ++ifeq ($(SoC),$(filter $(SoC),ipq806x)) ++ccflags-y += -DNSS_DRV_IPV4_ENABLE -DNSS_DRV_IPV6_ENABLE + qca-nss-drv-objs += nss_data_plane/nss_data_plane_gmac.o \ + nss_hal/ipq806x/nss_hal_pvt.o + +@@ -438,6 +485,8 @@ qca-nss-drv-objs += \ + endif + endif + ++ccflags-y += -DNSS_DATA_PLANE_GENERIC_SUPPORT ++ + ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64)) + qca-nss-drv-objs += nss_hal/ipq807x/nss_hal_pvt.o \ + nss_data_plane/hal/nss_ipq807x.o +@@ -496,6 +545,7 @@ ccflags-y += -I$(obj)/nss_hal/ipq50xx -D + endif + + ccflags-y += -I$(obj)/nss_hal/include -I$(obj)/nss_data_plane/include -I$(obj)/exports -DNSS_DEBUG_LEVEL=0 -DNSS_PKT_STATS_ENABLED=1 ++ + ccflags-y += -I$(obj)/nss_data_plane/hal/include + ccflags-y += -DNSS_PM_DEBUG_LEVEL=0 -DNSS_SKB_REUSE_SUPPORT=1 + ccflags-y += -Wall -Werror +@@ -510,7 +560,14 @@ NSS_CCFLAGS = -DNSS_DT_SUPPORT=1 -DNSS_F + ccflags-y += -I$(obj) + endif + ++# Fabric scaling is supported in 3.14 and 4.4 only ++ifneq ($(findstring 3.14, $(KERNELVERSION)),) ++NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=1 ++else ifneq ($(findstring 4.4, $(KERNELVERSION)),) ++NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=1 ++else + NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=0 ++endif + + # Disable Frequency scaling + ifeq "$(NSS_FREQ_SCALE_DISABLE)" "y" diff --git a/qca-nss-drv/patches-11.4/0012-nss-drv-quiet-messages.patch b/qca-nss-drv/patches-11.4/0012-nss-drv-quiet-messages.patch new file mode 100644 index 0000000..46a34dc --- /dev/null +++ b/qca-nss-drv/patches-11.4/0012-nss-drv-quiet-messages.patch @@ -0,0 +1,103 @@ +--- a/nss_core.c ++++ b/nss_core.c +@@ -477,7 +477,7 @@ static uint32_t nss_soc_mem_info(void) + goto err_use_default_memsize; + } + +- nss_info_always("NSS DDR size is 0x%x\n", (uint32_t) resource_size(&r)); ++ nss_info("NSS DDR size is 0x%x\n", (uint32_t) resource_size(&r)); + + return resource_size(&r); + +--- a/nss_hal/ipq50xx/nss_hal_pvt.c ++++ b/nss_hal/ipq50xx/nss_hal_pvt.c +@@ -449,15 +449,15 @@ static int __nss_hal_clock_configure(str + } + } + +- nss_info_always("Supported Frequencies - "); ++ nss_info("Supported Frequencies - "); + for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) { + switch (nss_runtime_samples.freq_scale[i].frequency) { + case NSS_FREQ_850: +- nss_info_always("850 MHz "); ++ nss_info("850 MHz "); + break; + + case NSS_FREQ_1000: +- nss_info_always("1 GHz "); ++ nss_info("1 GHz "); + break; + + case NSS_FREQ_SCALE_NA: +@@ -468,7 +468,7 @@ static int __nss_hal_clock_configure(str + return -EFAULT; + } + } +- nss_info_always("\n"); ++ nss_info("\n"); + + /* + * Set values only once for core0. Grab the proper clock. +--- a/nss_hal/ipq60xx/nss_hal_pvt.c ++++ b/nss_hal/ipq60xx/nss_hal_pvt.c +@@ -532,22 +532,22 @@ static int __nss_hal_clock_configure(str + } + } + +- nss_info_always("Supported Frequencies - "); ++ nss_info("Supported Frequencies - "); + for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) { + if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_187) { +- nss_info_always("187.2 MHz "); ++ nss_info("187.2 MHz "); + } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_748) { +- nss_info_always("748.8 MHz "); ++ nss_info("748.8 MHz "); + } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1497) { +- nss_info_always("1.4976 GHz "); ++ nss_info("1.4976 GHz "); + } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1689) { +- nss_info_always("1.6896 GHz "); ++ nss_info("1.6896 GHz "); + } else { + nss_info_always("Error\nNo Table/Invalid Frequency Found\n"); + return -EFAULT; + } + } +- nss_info_always("\n"); ++ nss_info("\n"); + + /* + * Set values only once for core0. Grab the proper clock. +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -571,22 +571,22 @@ static int __nss_hal_clock_configure(str + } + } + +- nss_info_always("Supported Frequencies - "); ++ nss_info("Supported Frequencies - "); + for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) { + if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_187) { +- nss_info_always("187.2 MHz "); ++ nss_info("187.2 MHz "); + } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_748) { +- nss_info_always("748.8 MHz "); ++ nss_info("748.8 MHz "); + } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1497) { +- nss_info_always("1.4976 GHz "); ++ nss_info("1.4976 GHz "); + } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1689) { +- nss_info_always("1.6896 GHz "); ++ nss_info("1.6896 GHz "); + } else { + nss_info_always("Error\nNo Table/Invalid Frequency Found\n"); + return -EFAULT; + } + } +- nss_info_always("\n"); ++ nss_info("\n"); + + /* + * Set values only once for core0. Grab the proper clock. diff --git a/qca-nss-drv/patches-11.4/0013-backport-12.4-docs.patch b/qca-nss-drv/patches-11.4/0013-backport-12.4-docs.patch new file mode 100644 index 0000000..34f2b09 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0013-backport-12.4-docs.patch @@ -0,0 +1,983 @@ +--- a/exports/nss_wifi_mesh.h ++++ b/exports/nss_wifi_mesh.h +@@ -102,7 +102,7 @@ enum nss_wifi_mesh_pre_header_type { + + /* + * nss_wifi_mesh_extended_data_pkt_types +- * Wi-Fi mesh extended data pkt types. ++ * Wi-Fi mesh extended data packet types. + */ + enum nss_wifi_mesh_extended_data_pkt_types { + WIFI_MESH_EXT_DATA_PKT_TYPE_NONE, /**< No packet type. */ +@@ -114,13 +114,13 @@ enum nss_wifi_mesh_extended_data_pkt_typ + * Wi-Fi header + */ + struct nss_wifi_mesh_ieee80211_hdr { +- uint16_t frame_ctl; /* Frame control. */ +- uint16_t duration_id; /* Duration ID. */ +- uint8_t addr1[ETH_ALEN]; /* Address 1. */ +- uint8_t addr2[ETH_ALEN]; /* Address 2. */ +- uint8_t addr3[ETH_ALEN]; /* Address 3. */ +- uint16_t seq_ctrl; /* Sequence control. */ +- uint8_t addr4[ETH_ALEN]; /* Address 4. */ ++ uint16_t frame_ctl; /**< Frame control. */ ++ uint16_t duration_id; /**< Duration ID. */ ++ uint8_t addr1[ETH_ALEN]; /**< Address 1. */ ++ uint8_t addr2[ETH_ALEN]; /**< Address 2. */ ++ uint8_t addr3[ETH_ALEN]; /**< Address 3. */ ++ uint16_t seq_ctrl; /**< Sequence control. */ ++ uint8_t addr4[ETH_ALEN]; /**< Address 4. */ + }__packed; + + /* +@@ -128,16 +128,16 @@ struct nss_wifi_mesh_ieee80211_hdr { + * Wi-Fi mesh header + */ + struct nss_wifi_mesh_ieee80211s_hdr { +- uint8_t flags; /* Mesh flags. */ +- uint8_t ttl; /* TTL. */ +- uint32_t seq_num; /* Sequence number. */ +- uint8_t eaddr1[ETH_ALEN]; /* Mesh Address1. */ +- uint8_t eaddr2[ETH_ALEN]; /* Mesh Address2. */ ++ uint8_t flags; /**< Mesh flags. */ ++ uint8_t ttl; /**< TTL. */ ++ uint32_t seq_num; /**< Sequence number. */ ++ uint8_t eaddr1[ETH_ALEN]; /**< Mesh Address1. */ ++ uint8_t eaddr2[ETH_ALEN]; /**< Mesh Address2. */ + }__packed; + + /* + * nss_wifi_mesh_per_packet_metadata +- * Wi-Fi mesh per packet metadata structure. ++ * Wi-Fi mesh per packet metadata structure. + */ + struct nss_wifi_mesh_per_packet_metadata { + uint16_t pkt_type; /* Packet type of the metadata. */ +@@ -150,8 +150,8 @@ struct nss_wifi_mesh_per_packet_metadata + * NSS-to-host path will be seen by ECM for rules. + */ + enum nss_wifi_mesh_dp_type { +- NSS_WIFI_MESH_DP_INNER, /**< Inner/Encapsulation Interface. */ +- NSS_WIFI_MESH_DP_OUTER, /**< Outer/Decapsulation Interface. */ ++ NSS_WIFI_MESH_DP_INNER, /**< Inner/encapsulation interface. */ ++ NSS_WIFI_MESH_DP_OUTER, /**< Outer/decapsulation interface. */ + }; + + /** +@@ -353,7 +353,7 @@ struct nss_wifi_mesh_proxy_path_del_msg + + /** + * nss_wifi_mesh_mpath_not_found_msg +- * Wi-Fi mesh path not found meesage. ++ * Wi-Fi mesh path not found message. + */ + struct nss_wifi_mesh_mpath_not_found_msg { + uint8_t dest_mac_addr[ETH_ALEN]; /**< Destination MAC address. */ +@@ -389,28 +389,28 @@ struct nss_wifi_mesh_path_expiry_msg { + * Encapsulation statistics. + */ + struct nss_wifi_mesh_encap_stats { +- uint32_t expiry_notify_sent; /* Number of times expiry notification sent to host. */ +- uint32_t mc_count; /* Number of multicast packets. */ +- uint32_t mp_not_found; /* Number of times mesh path is not found. */ +- uint32_t mp_active; /* Number of times mesh path is active. */ +- uint32_t mpp_not_found; /* Number of times proxy path is not found. */ +- uint32_t mpp_found; /* Number of times proxy path is found. */ +- uint32_t encap_hdr_fail; /* Number of times encapsulating mesh header failed. */ +- uint32_t mp_del_notify_fail; /* Number of times notifying mesh path delete failed. */ +- uint32_t link_enqueue; /* Number of packets enqueued to the link VAP. */ +- uint32_t link_enq_fail; /* Number of times enqueue to link vap failed. */ +- uint32_t ra_lup_fail; /* Number of times receiver address look up is failed. */ +- uint32_t dummy_add_count; /* Number of times dummy path is added. */ +- uint32_t encap_mp_add_notify_fail; /* Number of times add notification failed. */ +- uint32_t dummy_add_fail; /* Number of times dummy addition failed. */ +- uint32_t dummy_lup_fail; /* Number of times dummy lookup failed. */ +- uint32_t send_to_host_failed; /* Number of packets failed to be sent to host. */ +- uint32_t sent_to_host; /* Number of packets sent to host. */ +- uint32_t expiry_notify_fail; /* Number of times expiry notification to host failed. */ +- uint32_t no_headroom; /* Number of packets dropped because there is no headroom. */ +- uint32_t path_refresh_sent; /* Number of times path refresh is sent to host. */ +- uint32_t linearise_failed; /* Number of packets dropped because pb_linearise. */ +- uint32_t mp_exception_event_rl_dropped; /* Number of packets dropped due to rate limit. */ ++ uint32_t expiry_notify_sent; /**< Number of times expiry notification sent to host. */ ++ uint32_t mc_count; /**< Number of multicast packets. */ ++ uint32_t mp_not_found; /**< Number of times mesh path is not found. */ ++ uint32_t mp_active; /**< Number of times mesh path is active. */ ++ uint32_t mpp_not_found; /**< Number of times proxy path is not found. */ ++ uint32_t mpp_found; /**< Number of times proxy path is found. */ ++ uint32_t encap_hdr_fail; /**< Number of times encapsulating mesh header failed. */ ++ uint32_t mp_del_notify_fail; /**< Number of times notifying mesh path delete failed. */ ++ uint32_t link_enqueue; /**< Number of packets enqueued to the link VAP. */ ++ uint32_t link_enq_fail; /**< Number of times enqueue to link vap failed. */ ++ uint32_t ra_lup_fail; /**< Number of times receiver address look up is failed. */ ++ uint32_t dummy_add_count; /**< Number of times dummy path is added. */ ++ uint32_t encap_mp_add_notify_fail; /**< Number of times add notification failed. */ ++ uint32_t dummy_add_fail; /**< Number of times dummy addition failed. */ ++ uint32_t dummy_lup_fail; /**< Number of times dummy lookup failed. */ ++ uint32_t send_to_host_failed; /**< Number of packets failed to be sent to host. */ ++ uint32_t sent_to_host; /**< Number of packets sent to host. */ ++ uint32_t expiry_notify_fail; /**< Number of times expiry notification to host failed. */ ++ uint32_t no_headroom; /**< Number of packets dropped because there is no headroom. */ ++ uint32_t path_refresh_sent; /**< Number of times path refresh is sent to host. */ ++ uint32_t linearise_failed; /**< Number of packets dropped because pb_linearise. */ ++ uint32_t mp_exception_event_rl_dropped; /**< Number of packets dropped due to rate limit. */ + }; + + /* +@@ -532,22 +532,22 @@ struct nss_wifi_mesh_path_stats { + * Wi-Fi mesh proxy path statistics. + */ + struct nss_wifi_mesh_proxy_path_stats { +- uint32_t alloc_failures; /**< Mesh proxy path alloc failure count. */ +- uint32_t entry_exist_failures; /**< Mesh proxy path entry already exists. */ +- uint32_t add_success; /**< Mesh proxy path add success count. */ +- uint32_t table_full_errors; /**< Mesh proxy path table full count. */ +- uint32_t insert_failures; /**< Mesh proxy path insert failure count. */ +- uint32_t not_found; /**< Mesh proxy path not found count. */ +- uint32_t unhashed_errors; /**< Mesh proxy path unhased erorr count. */ +- uint32_t delete_failures; /**< Mesh proxy path delete failure count. */ +- uint32_t delete_success; /**< Mesh proxy path delete success count. */ +- uint32_t update_success; /**< Mesh proxy path update success count. */ +- uint32_t lookup_success; /**< Mesh proxy path lookup success count. */ +- uint32_t add_requests; /**< Mesh proxy path addition requests. */ +- uint32_t del_requests; /**< Mesh proxy path deletion requests. */ +- uint32_t update_requests; /**< Mesh proxy path updation requests. */ +- uint32_t mda_updations; /**< Mesh proxy path mda updations. */ +- uint32_t flag_updations; /**< Mesh proxy path flags updations. */ ++ uint32_t alloc_failures; /**< Mesh proxy path allocation failure count. */ ++ uint32_t entry_exist_failures; /**< Mesh proxy path entry already exists. */ ++ uint32_t add_success; /**< Mesh proxy path add success count. */ ++ uint32_t table_full_errors; /**< Mesh proxy path table full count. */ ++ uint32_t insert_failures; /**< Mesh proxy path insert failure count. */ ++ uint32_t not_found; /**< Mesh proxy path not found count. */ ++ uint32_t unhashed_errors; /**< Mesh proxy path unhased erorr count. */ ++ uint32_t delete_failures; /**< Mesh proxy path delete failure count. */ ++ uint32_t delete_success; /**< Mesh proxy path delete success count. */ ++ uint32_t update_success; /**< Mesh proxy path update success count. */ ++ uint32_t lookup_success; /**< Mesh proxy path lookup success count. */ ++ uint32_t add_requests; /**< Mesh proxy path addition requests. */ ++ uint32_t del_requests; /**< Mesh proxy path deletion requests. */ ++ uint32_t update_requests; /**< Mesh proxy path updation requests. */ ++ uint32_t mda_updations; /**< Mesh proxy path mda updations. */ ++ uint32_t flag_updations; /**< Mesh proxy path flags updations. */ + uint32_t mesh_proxy_path_dummy_lookup_success; /**< Mesh proxy path dummy entry lookup successes. */ + uint32_t mesh_proxy_path_dummy_lookup_failures; /**< Mesh proxy path dummy entry lookup failures. */ + uint32_t mesh_proxy_path_dummy_add_failures; /**< Mesh proxy path dummy entry add failures. */ +@@ -975,7 +975,7 @@ nss_tx_status_t nss_wifi_mesh_tx_msg_ext + + /** + * nss_wifi_mesh_verify_if_num +- * Verify Wi-Fi mesh interface number. ++ * Verifies the Wi-Fi mesh interface number. + * + * @datatypes + * interface number \n +@@ -1014,4 +1014,9 @@ extern int nss_wifi_mesh_stats_register_ + * 0 on success or non-zero on failure. + */ + extern int nss_wifi_mesh_stats_unregister_notifier(struct notifier_block *nb); ++ ++/** ++ * @} ++ */ ++ + #endif /* __NSS_WIFI_MESH_H */ +--- a/exports/nss_c2c_rx.h ++++ b/exports/nss_c2c_rx.h +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -36,7 +36,7 @@ enum nss_c2c_rx_stats_types { + /**< Number of received simple pbufs. */ + NSS_C2C_RX_STATS_PBUF_SG, /**< Number of scatter-gather pbufs received. */ + NSS_C2C_RX_STATS_PBUF_RETURNING, /**< Number of returning scatter-gather pbufs. */ +- NSS_C2C_RX_STATS_INVAL_DEST, /**< Number of pbuf enqueue failures because of destination is invalid. */ ++ NSS_C2C_RX_STATS_INVAL_DEST, /**< Number of pbuf enqueue failures because destination is invalid. */ + NSS_C2C_RX_STATS_MAX, /**< Maximum message type. */ + }; + +--- a/exports/nss_c2c_tx.h ++++ b/exports/nss_c2c_tx.h +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -72,9 +72,9 @@ enum nss_c2c_tx_test_type { + */ + enum nss_c2c_tx_stats_types { + NSS_C2C_TX_STATS_PBUF_SIMPLE = NSS_STATS_NODE_MAX, +- /**< Number of received simple pbuf. */ +- NSS_C2C_TX_STATS_PBUF_SG, /**< Number of scatter-gather pbuf received. */ +- NSS_C2C_TX_STATS_PBUF_RETURNING, /**< Number of returning scatter-gather pbuf. */ ++ /**< Number of received simple pbufs. */ ++ NSS_C2C_TX_STATS_PBUF_SG, /**< Number of scatter-gather pbufs received. */ ++ NSS_C2C_TX_STATS_PBUF_RETURNING, /**< Number of returning scatter-gather pbufs. */ + NSS_C2C_TX_STATS_MAX, /**< Maximum message type. */ + }; + +--- a/exports/nss_cmn.h ++++ b/exports/nss_cmn.h +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2014, 2016-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2014, 2016-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -27,7 +27,7 @@ + * @{ + */ + +-/* ++/** + * Interface Number 1 Valid 7 Core 8 Type 16 Index + */ + typedef int32_t nss_if_num_t; +--- a/exports/nss_gre.h ++++ b/exports/nss_gre.h +@@ -1,6 +1,9 @@ + /* + **************************************************************************** + * Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved. ++ * ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -101,16 +104,16 @@ enum nss_gre_msg_types { + }; + + /** +- * GRE Mode Types ++ * GRE mode types. + */ + enum nss_gre_mode { +- NSS_GRE_MODE_TUN, /**< GRE Tunnel interface. */ +- NSS_GRE_MODE_TAP, /**< GRE Tap interface. */ ++ NSS_GRE_MODE_TUN, /**< GRE tunnel interface. */ ++ NSS_GRE_MODE_TAP, /**< GRE TAP interface. */ + NSS_GRE_MODE_MAX /**< Maxmum GRE mode. */ + }; + + /** +- * GRE IP Types ++ * GRE IP types. + */ + enum nss_gre_ip_types { + NSS_GRE_IP_IPV4, /**< Outer Tunnel is IPV4. */ +@@ -168,11 +171,11 @@ enum nss_gre_session_types { + * GRE create message structure. + */ + struct nss_gre_config_msg { +- uint32_t src_ip[4]; /**< Source IPv4 or IPv6 Adddress. */ +- uint32_t dest_ip[4]; /**< Destination IPv4 or IPv6 Adddress. */ ++ uint32_t src_ip[4]; /**< Source IPv4 or IPv6 address. */ ++ uint32_t dest_ip[4]; /**< Destination IPv4 or IPv6 address. */ + uint32_t flags; /**< GRE Flags. */ +- uint32_t ikey; /**< GRE rx KEY.*/ +- uint32_t okey; /**< GRE tx KEY. */ ++ uint32_t ikey; /**< GRE Rx key.*/ ++ uint32_t okey; /**< GRE Tx key. */ + uint32_t mode; /**< GRE TUN or TAP. */ + uint32_t ip_type; /**< IPv4 or IPv6 type. */ + uint32_t next_node_if_num; /**< To whom to forward packets. */ +@@ -185,7 +188,7 @@ struct nss_gre_config_msg { + }; + + /** +- * GRE link up message structure ++ * GRE link up message structure. + */ + struct nss_gre_linkup_msg { + int if_number; /**< Interface number. */ +@@ -202,11 +205,11 @@ struct nss_gre_linkdown_msg { + * GRE deconfig message structure + */ + struct nss_gre_deconfig_msg { +- int if_number; /**< Interface number */ ++ int if_number; /**< Interface number. */ + }; + + /** +- * GRE session statistics message ++ * GRE session statistics message. + */ + struct nss_gre_session_stats_msg { + struct nss_cmn_node_stats node_stats; /**< Common node statistics. */ +@@ -214,7 +217,7 @@ struct nss_gre_session_stats_msg { + }; + + /** +- * GRE base statistics message ++ * GRE base statistics message. + */ + struct nss_gre_base_stats_msg { + uint32_t stats[NSS_GRE_BASE_DEBUG_MAX]; /**< Base debug statistics. */ +@@ -241,10 +244,10 @@ struct nss_gre_session_stats_notificatio + + /** + * nss_gre_msg +- * Message structure to send/receive GRE messages ++ * Message structure to send/receive GRE messages. + */ + struct nss_gre_msg { +- struct nss_cmn_msg cm; /**< Common message header */ ++ struct nss_cmn_msg cm; /**< Common message header. */ + + /** + * Payload of a GRE message. +@@ -304,7 +307,7 @@ extern nss_tx_status_t nss_gre_tx_msg_sy + + /** + * nss_gre_tx_buf +- * Sends packet to the NSS ++ * Sends a packet to the NSS. + * + * @datatypes + * nss_ctx_instance \n +--- a/exports/nss_gre_redir.h ++++ b/exports/nss_gre_redir.h +@@ -302,7 +302,7 @@ struct nss_gre_redir_stats_sync_msg { + + /** + * nss_gre_redir_tun_stats +- * GRE redirect statistics to accumulate all the stats values. ++ * GRE redirect statistics to accumulate all stats values. + */ + struct nss_gre_redir_tun_stats { + uint64_t rx_packets; /**< Number of packets received. */ +--- a/exports/nss_if.h ++++ b/exports/nss_if.h +@@ -321,6 +321,23 @@ extern struct nss_ctx_instance *nss_if_r + extern nss_tx_status_t nss_if_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num); + + /** ++ * nss_if_tx_msg_with_size ++ * Sends a message to the NSS interface. ++ * ++ * @datatypes ++ * nss_ctx_instance \n ++ * nss_if_msg ++ * ++ * @param[in,out] nss_ctx Pointer to the NSS context. ++ * @param[in] nim Pointer to the NSS interface message. ++ * @param[in] size Total message buffer size. ++ * ++ * @return ++ * Status of the Tx operation. ++ */ ++nss_tx_status_t nss_if_tx_msg_with_size(struct nss_ctx_instance *nss_ctx, struct nss_if_msg *nim, uint32_t size); ++ ++/** + * nss_if_tx_msg + * Sends a message to the NSS interface. + * +@@ -338,7 +355,7 @@ nss_tx_status_t nss_if_tx_msg(struct nss + + /** + * nss_if_msg_sync +- * Sends a message to the NSS interface and wait for the response. ++ * Sends a message to the NSS interface and waits for the response. + * + * @datatypes + * nss_ctx_instance \n +@@ -385,7 +402,7 @@ nss_tx_status_t nss_if_reset_nexthop(str + + /** + * nss_if_change_mtu +- * Change the MTU of the interface. ++ * Changes the MTU of the interface. + * + * @datatypes + * nss_ctx_instance +@@ -401,7 +418,7 @@ nss_tx_status_t nss_if_change_mtu(struct + + /** + * nss_if_change_mac_addr +- * Change the MAC address of the interface. ++ * Changes the MAC address of the interface. + * + * @datatypes + * nss_ctx_instance +@@ -417,7 +434,7 @@ nss_tx_status_t nss_if_change_mac_addr(s + + /** + * nss_if_vsi_unassign +- * Detach the VSI ID from the given interface. ++ * Detaches the VSI ID from the given interface. + * + * @datatypes + * nss_ctx_instance +@@ -433,7 +450,7 @@ nss_tx_status_t nss_if_vsi_unassign(stru + + /** + * nss_if_vsi_assign +- * Attach the VSI ID to the given interface. ++ * Attaches the VSI ID to the given interface. + * + * @datatypes + * nss_ctx_instance +--- a/exports/nss_ipv4.h ++++ b/exports/nss_ipv4.h +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -55,16 +58,16 @@ struct nss_ipv4_create { + /**< Source interface number (virtual or physical). */ + int32_t dest_interface_num; + /**< Destination interface number (virtual or physical). */ +- int32_t protocol; /**< L4 protocol (e.g., TCP or UDP). */ +- uint32_t flags; /**< Flags (if any) associated with this rule. */ ++ int32_t protocol; /**< L4 protocol, e.g., TCP or UDP. */ ++ uint32_t flags; /**< Flags associated with this rule. */ + uint32_t from_mtu; /**< MTU of the incoming interface. */ + uint32_t to_mtu; /**< MTU of the outgoing interface. */ + uint32_t src_ip; /**< Source IP address. */ +- int32_t src_port; /**< Source L4 port (e.g., TCP or UDP port). */ ++ int32_t src_port; /**< Source L4 port, e.g., TCP or UDP port. */ + uint32_t src_ip_xlate; /**< Translated source IP address (used with SNAT). */ + int32_t src_port_xlate; /**< Translated source L4 port (used with SNAT). */ + uint32_t dest_ip; /**< Destination IP address. */ +- int32_t dest_port; /**< Destination L4 port (e.g., TCP or UDP port). */ ++ int32_t dest_port; /**< Destination L4 port, e.g., TCP or UDP port. */ + uint32_t dest_ip_xlate; + /**< Translated destination IP address (used with DNAT). */ + int32_t dest_port_xlate; +@@ -82,7 +85,7 @@ struct nss_ipv4_create { + uint32_t flow_end; /**< TCP window end. */ + uint32_t flow_max_end; /**< TCP window maximum end. */ + uint32_t flow_pppoe_if_exist; +- /**< Flow direction: PPPoE interface exist flag. */ ++ /**< Flow direction: PPPoE interface existence flag. */ + int32_t flow_pppoe_if_num; + /**< Flow direction: PPPoE interface number. */ + uint16_t ingress_vlan_tag; /**< Ingress VLAN tag expected for this flow. */ +@@ -131,9 +134,9 @@ struct nss_ipv4_create { + struct nss_ipv4_destroy { + int32_t protocol; /**< L4 protocol ID. */ + uint32_t src_ip; /**< Source IP address. */ +- int32_t src_port; /**< Source L4 port (e.g., TCP or UDP port). */ ++ int32_t src_port; /**< Source L4 port, e.g., TCP or UDP port. */ + uint32_t dest_ip; /**< Destination IP address. */ +- int32_t dest_port; /**< Destination L4 port (e.g., TCP or UDP port). */ ++ int32_t dest_port; /**< Destination L4 port, e.g., TCP or UDP port. */ + }; + + /** +@@ -956,10 +959,10 @@ struct nss_ipv4_node_sync { + /**< Number of multicast connection flushes. */ + + uint32_t ipv4_connection_create_invalid_mirror_ifnum; +- /**< Number of create request failed with an invalid mirror interface number. */ ++ /**< Number of failed create requests with an invalid mirror interface number. */ + + uint32_t ipv4_connection_create_invalid_mirror_iftype; +- /**< Number of create request failed with an invalid mirror interface type. */ ++ /**< Number of failed create requests with an invalid mirror interface type. */ + + uint32_t ipv4_mirror_failures; + /**< Mirror packet failed. */ +--- a/exports/nss_ipv6.h ++++ b/exports/nss_ipv6.h +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -82,14 +85,14 @@ struct nss_ipv6_create { + /**< Source interface number (virtual or physical). */ + int32_t dest_interface_num; + /**< Destination interface number (virtual or physical). */ +- int32_t protocol; /**< L4 protocol (e.g., TCP or UDP). */ +- uint32_t flags; /**< Flags (if any) associated with this rule. */ ++ int32_t protocol; /**< L4 protocol, e.g., TCP or UDP,. */ ++ uint32_t flags; /**< Flags associated with this rule. */ + uint32_t from_mtu; /**< MTU of the incoming interface. */ + uint32_t to_mtu; /**< MTU of the outgoing interface. */ + uint32_t src_ip[4]; /**< Source IP address. */ +- int32_t src_port; /**< Source L4 port (e.g., TCP or UDP port). */ ++ int32_t src_port; /**< Source L4 port, e.g., TCP or UDP port. */ + uint32_t dest_ip[4]; /**< Destination IP address. */ +- int32_t dest_port; /**< Destination L4 port (e.g., TCP or UDP port). */ ++ int32_t dest_port; /**< Destination L4 port, e.g., TCP or UDP port. */ + uint8_t src_mac[ETH_ALEN]; /**< Source MAC address. */ + uint8_t dest_mac[ETH_ALEN]; /**< Destination MAC address. */ + uint8_t flow_window_scale; /**< Window scaling factor (TCP). */ +@@ -111,7 +114,7 @@ struct nss_ipv6_create { + uint32_t return_max_end; + /**< Maximum end for the return direction. */ + uint32_t return_pppoe_if_exist; +- /**< Return direction: PPPoE interface exist flag. */ ++ /**< Return direction: PPPoE interface existence flag. */ + int32_t return_pppoe_if_num; + /**< Return direction: PPPoE interface number. */ + uint16_t egress_vlan_tag; /**< Egress VLAN tag expected for this flow. */ +@@ -139,11 +142,11 @@ struct nss_ipv6_create { + * Information for an IPv6 flow or connection destroy rule. + */ + struct nss_ipv6_destroy { +- int32_t protocol; /**< L4 protocol (e.g., TCP or UDP). */ ++ int32_t protocol; /**< L4 protocol, e.g., TCP or UDP. */ + uint32_t src_ip[4]; /**< Source IP address. */ +- int32_t src_port; /**< Source L4 port (e.g., TCP or UDP port). */ ++ int32_t src_port; /**< Source L4 port, e.g., TCP or UDP port. */ + uint32_t dest_ip[4]; /**< Destination IP address. */ +- int32_t dest_port; /**< Destination L4 port (e.g., TCP or UDP port). */ ++ int32_t dest_port; /**< Destination L4 port, e.g., TCP or UDP port. */ + }; + + /** +@@ -951,10 +954,10 @@ struct nss_ipv6_node_sync { + /**< Number of multicast connection flushes. */ + + uint32_t ipv6_connection_create_invalid_mirror_ifnum; +- /**< Number of create request failed with an invalid mirror interface number. */ ++ /**< Number of failed create requests with an invalid mirror interface number. */ + + uint32_t ipv6_connection_create_invalid_mirror_iftype; +- /**< Number of create request failed with an invalid mirror interface type. */ ++ /**< Number of failed create requests with an invalid mirror interface type. */ + + uint32_t ipv6_mirror_failures; + /**< Mirror packet failed. */ +--- a/exports/nss_lso_rx.h ++++ b/exports/nss_lso_rx.h +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the +@@ -17,7 +17,7 @@ + */ + + /* +- * nss_lso_rx.h ++ * @file nss_lso_rx.h + * NSS driver LSO (Large Send Offload) Rx header file. + */ + +--- a/exports/nss_map_t.h ++++ b/exports/nss_map_t.h +@@ -36,14 +36,18 @@ + */ + #define NSS_MAX_MAP_T_DYNAMIC_INTERFACES 4 + ++/** ++ * MAP-T metadata flag. ++ */ + #define NSS_MAPT_MDATA_FLAG_DF_BIT (1 << 0) + +-/* +- * mapt meta data ++/** ++ * nss_map_t_mdata ++ * MAP-T metadata + */ + struct nss_map_t_mdata { +- uint16_t flags; +- uint16_t res[6]; ++ uint16_t flags; /**< Metadata flags. */ ++ uint16_t res[6]; /**< Reserved for future use. */ + }; + + /** +--- a/exports/nss_virt_if.h ++++ b/exports/nss_virt_if.h +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2014-2017, 2019, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2014-2017, 2019, 2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -93,8 +93,8 @@ struct nss_virt_if_interface_stats { + * Virtual interface statistics received from the NSS. + */ + struct nss_virt_if_stats { +- struct nss_virt_if_base_node_stats base_stats; +- struct nss_virt_if_interface_stats if_stats; ++ struct nss_virt_if_base_node_stats base_stats; /**< Virtual interface statistics of NSS base node. */ ++ struct nss_virt_if_interface_stats if_stats; /**< Virtual interface statistics of each pair of interfaces. */ + }; + + /** +--- a/nss_c2c_rx.c ++++ b/nss_c2c_rx.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +--- a/nss_c2c_tx.c ++++ b/nss_c2c_tx.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +--- a/nss_coredump.c ++++ b/nss_coredump.c +@@ -1,6 +1,8 @@ + /* + ************************************************************************** + * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +--- a/nss_dynamic_interface.c ++++ b/nss_dynamic_interface.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2013, 2015-2021, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +--- a/nss_meminfo.c ++++ b/nss_meminfo.c +@@ -1,5 +1,6 @@ + /* + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above +--- a/nss_phys_if.h ++++ b/nss_phys_if.h +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +--- a/nss_profiler.c ++++ b/nss_profiler.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +--- a/nss_qrfs.c ++++ b/nss_qrfs.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +--- a/nss_rmnet_rx.c ++++ b/nss_rmnet_rx.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above +--- a/nss_stats.c ++++ b/nss_stats.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +--- a/nss_stats.h ++++ b/nss_stats.h +@@ -1,9 +1,12 @@ + /* + ************************************************************************** + * Copyright (c) 2016-2017, 2019-2020 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +--- a/nss_vxlan.c ++++ b/nss_vxlan.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +--- a/nss_data_plane/include/nss_data_plane.h ++++ b/nss_data_plane/include/nss_data_plane.h +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2014-2017,2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2014-2017,2020-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +--- a/nss_data_plane/nss_data_plane.c ++++ b/nss_data_plane/nss_data_plane.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +--- a/exports/nss_wifi_vdev.h ++++ b/exports/nss_wifi_vdev.h +@@ -1069,13 +1069,13 @@ struct nss_wifi_vdev_msg { + struct nss_wifi_vdev_me_snptbl_deny_grp_add_msg vdev_deny_member_add; + /**< Add a snooplist member to the deny list. */ + struct nss_wifi_vdev_me_hmmc_add_msg vdev_hmmc_member_add; +- /**< Adds a new member into the HMMC list. */ ++ /**< Adds a member to the HMMC list. */ + struct nss_wifi_vdev_me_hmmc_del_msg vdev_hmmc_member_del; +- /**< Delete a member from the HMMC list. */ ++ /**< Deletes a member from the HMMC list. */ + struct nss_wifi_vdev_me_deny_ip_add_msg vdev_deny_list_member_add; +- /**< Adds a new member into the deny list. */ ++ /**< Adds a member to the denylist. */ + struct nss_wifi_vdev_me_deny_ip_del_msg vdev_deny_list_member_del; +- /**< Delete a member from the deny list. */ ++ /**< Deletes a member from the denylist. */ + struct nss_wifi_vdev_txmsg vdev_txmsgext; + /**< Transmits special data. */ + struct nss_wifi_vdev_vow_dbg_cfg_msg vdev_vow_dbg_cfg; +--- a/exports/nss_wifi_ext_vdev_if.h ++++ b/exports/nss_wifi_ext_vdev_if.h +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2020, 2021, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above +@@ -26,6 +26,11 @@ + + #define NSS_WIFI_EXT_VDEV_MAX 16 + ++/** ++ * @addtogroup nss_wifi_ext_vdev_subsystem ++ * @{ ++ */ ++ + /* + * nss_wifi_ext_vdev_msg_types + * WiFi extension virtual device mesage types. +@@ -294,4 +299,8 @@ extern struct nss_ctx_instance *nss_wifi + nss_wifi_ext_vdev_data_callback_t cb_func_data, nss_wifi_ext_vdev_ext_data_callback_t cb_func_ext, + nss_wifi_ext_vdev_msg_callback_t cb_func_msg, struct net_device *netdev, uint32_t features, + void *app_ctx); ++/** ++ * @} ++ */ ++ + #endif +--- a/exports/nss_wifili_if.h ++++ b/exports/nss_wifili_if.h +@@ -1,16 +1,19 @@ + /* + ************************************************************************** + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. +- * Permission to use, copy, modify, and/or distribute this software for +- * any purpose with or without fee is hereby granted, provided that the +- * above copyright notice and this permission notice appear in all copies. ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +- * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +@@ -711,7 +714,7 @@ struct nss_wifili_hal_srng_soc_msg { + uint32_t shadow_wrptr_mem_addr; + /**< Shadow write pointer address. */ + uint32_t lmac_rings_start_id; +- /**< start id of LMAC rings. */ ++ /**< Start ID of LMAC rings. */ + }; + + /** +--- a/exports/nss_wifi_mac_db_if.h ++++ b/exports/nss_wifi_mac_db_if.h +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2020, 2021, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above +@@ -25,6 +25,11 @@ + + #define NSS_WIFI_MAC_DB_ENTRY_IF_LOCAL 0x1 + ++ /** ++ * @addtogroup nss_wifi_mac_db_if_subsystem ++ * @{ ++ */ ++ + /* + * MAX Wi-Fi MAC database entries sent in group + * is chosen considering the entry size and +@@ -72,6 +77,7 @@ enum nss_wifi_mac_db_if_opmode { + }; + + /** ++ * nss_wifi_mac_db_err_types + * Wi-Fi MAC database errors. + */ + enum nss_wifi_mac_db_err_types { +@@ -274,4 +280,9 @@ struct nss_ctx_instance *nss_register_wi + */ + void nss_unregister_wifi_mac_db_if(uint32_t if_num); + struct nss_ctx_instance *nss_wifi_mac_db_get_context(void); ++ ++/** ++ * @} ++ */ ++ + #endif /* __NSS_WIFI_MAC_DB_H */ +--- a/nss_wifili_stats.c ++++ b/nss_wifili_stats.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +--- a/nss_wifili_strings.c ++++ b/nss_wifili_strings.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the +@@ -71,10 +71,10 @@ struct nss_stats_info nss_wifili_strings + * wifili tx comp stats + */ + struct nss_stats_info nss_wifili_strings_stats_tx_comp[NSS_WIFILI_STATS_TX_DESC_FREE_MAX] = { +- {"tx_desc_free_inv_bufsrc" , NSS_STATS_TYPE_ERROR}, +- {"tx_desc_free_inv_cookie" , NSS_STATS_TYPE_SPECIAL}, +- {"tx_desc_free_hw_ring_empty" , NSS_STATS_TYPE_SPECIAL}, +- {"tx_desc_free_reaped" , NSS_STATS_TYPE_SPECIAL} ++ {"tx_desc_free_inv_bufsrc" , NSS_STATS_TYPE_ERROR}, ++ {"tx_desc_free_inv_cookie" , NSS_STATS_TYPE_SPECIAL}, ++ {"tx_desc_free_hw_ring_empty" , NSS_STATS_TYPE_SPECIAL}, ++ {"tx_desc_free_reaped" , NSS_STATS_TYPE_SPECIAL} + }; + + /* diff --git a/qca-nss-drv/patches-11.4/0013-backport-12.4.patch b/qca-nss-drv/patches-11.4/0013-backport-12.4.patch new file mode 100644 index 0000000..8eae12c --- /dev/null +++ b/qca-nss-drv/patches-11.4/0013-backport-12.4.patch @@ -0,0 +1,1209 @@ +--- a/exports/nss_gre.h ++++ b/exports/nss_gre.h +@@ -448,7 +448,17 @@ typedef void (*nss_gre_pkt_callback_t)(s + * @return + * None. + */ ++#ifdef NSS_DRV_GRE_ENABLE + extern void nss_gre_register_pkt_callback(nss_gre_pkt_callback_t cb); ++#else ++static inline void nss_gre_register_pkt_callback(nss_gre_pkt_callback_t cb) ++{ ++ /* ++ * Dummy registration function for external modules when GRE ++ * is disabled ++ */ ++} ++#endif + + /** + * nss_gre_unregister_pkt_callback +@@ -460,7 +470,17 @@ extern void nss_gre_register_pkt_callbac + * @return + * None. + */ ++#ifdef NSS_DRV_GRE_ENABLE + extern void nss_gre_unregister_pkt_callback(void); ++#else ++static inline void nss_gre_unregister_pkt_callback(void) ++{ ++ /* ++ * Dummy registration function for external modules when GRE ++ * is disabled ++ */ ++} ++#endif + + /** + * nss_gre_stats_unregister_notifier +--- a/exports/nss_ipv4.h ++++ b/exports/nss_ipv4.h +@@ -103,7 +103,7 @@ struct nss_ipv4_create { + /**< Return direction: PPPoE interface number. */ + uint16_t egress_vlan_tag; /**< Egress VLAN tag expected for this flow. */ + uint8_t spo_needed; /**< Indicates whether SPO is required. */ +- uint32_t param_a0; /**< Custom parameter 0. */ ++ struct net_device *top_ndev; /**< Netdevice associated with the top interface. */ + uint32_t param_a1; /**< Custom parameter 1. */ + uint32_t param_a2; /**< Custom parameter 2. */ + uint32_t param_a3; /**< Custom parameter 3. */ +--- a/exports/nss_ipv6.h ++++ b/exports/nss_ipv6.h +@@ -135,6 +135,7 @@ struct nss_ipv6_create { + /**< Egress VLAN tag expected for this flow. */ + uint8_t flow_dscp; /**< IP DSCP value for flow direction. */ + uint8_t return_dscp; /**< IP DSCP value for the return direction. */ ++ struct net_device *top_ndev; /**< Netdevice associated with the top interface. */ + }; + + /** +--- a/exports/nss_wifili_if.h ++++ b/exports/nss_wifili_if.h +@@ -104,6 +104,11 @@ + #define NSS_WIFILI_PEER_SIZE 1600 + + /* ++ * Maximum size of target SoC type string ++ */ ++#define NSS_WIFILI_SOC_STRING_SIZE_MAX 24 ++ ++/* + * Radio specific flags + */ + #define NSS_WIFILI_PDEV_FLAG_V3_STATS_ENABLED 0x00000008 +@@ -660,9 +665,12 @@ struct nss_wifili_stats { + * NSS wifili soc stats + */ + struct nss_wifili_soc_stats { +- uint32_t soc_maxpdev; /**< Maximum number of radios per SoC. */ ++ uint32_t soc_maxpdev; ++ /**< Maximum number of radios per SoC. */ + struct nss_wifili_stats stats_wifili; +- /**< Per-SoC statistics. */ ++ /**< Per-SoC statistics. */ ++ char soc_type[NSS_WIFILI_SOC_STRING_SIZE_MAX]; ++ /**< Target SoC type string. */ + }; + + /** +@@ -1267,6 +1275,8 @@ struct nss_wifili_device_stats { + struct nss_wifili_stats_sync_msg { + struct nss_wifili_device_stats stats; + /**< Device statistics. */ ++ uint32_t target_type; ++ /**< Target SoC type. */ + }; + + /** +--- a/nss_c2c_rx.c ++++ b/nss_c2c_rx.c +@@ -110,7 +110,7 @@ void nss_c2c_rx_register_handler(struct + + if (nss_ctx->id == NSS_CORE_0) { + nss_c2c_rx_stats_dentry_create(); ++ nss_c2c_rx_strings_dentry_create(); + } +- nss_c2c_rx_strings_dentry_create(); + } + EXPORT_SYMBOL(nss_c2c_rx_register_handler); +--- a/nss_c2c_tx.c ++++ b/nss_c2c_tx.c +@@ -145,8 +145,8 @@ void nss_c2c_tx_register_handler(struct + + if (nss_ctx->id == NSS_CORE_0) { + nss_c2c_tx_stats_dentry_create(); ++ nss_c2c_tx_strings_dentry_create(); + } +- nss_c2c_tx_strings_dentry_create(); + } + EXPORT_SYMBOL(nss_c2c_tx_register_handler); + +--- a/nss_core.c ++++ b/nss_core.c +@@ -522,7 +522,7 @@ static void nss_get_ddr_info(struct nss_ + const __be32 *ppp = (__be32 *)of_get_property(node, "reg", &n_items); + + n_items /= sizeof(ppp[0]); +- nss_info_always("node size %d # items %d\n", ++ nss_info("node size %d # items %d\n", + of_n_size_cells(node), n_items); + if (ppp) { + if (n_items & 1) { /* case 1 */ +@@ -549,7 +549,7 @@ case3: + n_items = 0; + if (n_items) { + of_node_put(node); +- nss_info_always("%s: %x %u (avl %u) items %d active_cores %d\n", ++ nss_info("%s: %x %u (avl %u) items %d active_cores %d\n", + name, mmu->start_address, mmu->ddr_size, + avail_ddr, n_items, mmu->num_active_cores); + /* +@@ -886,7 +886,7 @@ static inline void nss_core_handle_buffe + /* + * linearize or free if requested. + */ +- if (unlikely(skb_is_nonlinear(nbuf))) { ++ if (unlikely(skb_is_nonlinear(nbuf))) { + if (nss_core_skb_needs_linearize(nbuf, ndev->features) && __skb_linearize(nbuf)) { + dev_kfree_skb_any(nbuf); + return; +@@ -944,11 +944,11 @@ static inline void nss_core_handle_ext_b + ext_cb = subsys_dp_reg->ext_cb; + if (likely(ext_cb) && likely(ndev)) { + +- if (unlikely(skb_is_nonlinear(nbuf))) { ++ if (unlikely(skb_is_nonlinear(nbuf))) { + if (nss_core_skb_needs_linearize(nbuf, ndev->features) && __skb_linearize(nbuf)) { + /* +- * We needed to linearize, but __skb_linearize() failed. So free the nbuf. +- */ ++ * We needed to linearize, but __skb_linearize() failed. So free the nbuf. ++ */ + dev_kfree_skb_any(nbuf); + return; + } +@@ -1685,6 +1685,7 @@ static void nss_core_init_nss(struct nss + { + struct nss_top_instance *nss_top; + int ret; ++ int i; + + NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(*if_map), DMA_FROM_DEVICE); + NSS_CORE_DSB(); +@@ -1700,6 +1701,9 @@ static void nss_core_init_nss(struct nss + #ifdef NSS_DRV_C2C_ENABLE + nss_ctx->c2c_start = nss_ctx->meminfo_ctx.c2c_start_dma; + #endif ++ for (i = 0; i < NSS_H2N_DESC_RING_NUM; i++) { ++ nss_ctx->h2n_desc_rings[i].nss_index_local = 0; ++ } + + nss_top = nss_ctx->nss_top; + spin_lock_bh(&nss_top->lock); +@@ -1723,12 +1727,15 @@ static void nss_core_init_nss(struct nss + * Configure the maximum number of IPv4/IPv6 + * connections supported by the accelerator. + */ +- nss_ipv4_conn_cfg = max_ipv4_conn; ++#ifdef NSS_DRV_IPV4_ENABLE ++ nss_ipv4_conn_cfg = max_ipv4_conn; ++ nss_ipv4_update_conn_count(max_ipv4_conn); ++#endif ++ + #ifdef NSS_DRV_IPV6_ENABLE + nss_ipv6_conn_cfg = max_ipv6_conn; + nss_ipv6_update_conn_count(max_ipv6_conn); + #endif +- nss_ipv4_update_conn_count(max_ipv4_conn); + + #ifdef NSS_MEM_PROFILE_LOW + /* +@@ -3014,48 +3021,52 @@ int32_t nss_core_send_buffer(struct nss_ + * Take a lock for queue + */ + spin_lock_bh(&h2n_desc_ring->lock); +- +- /* +- * We need to work out if there's sufficent space in our transmit descriptor +- * ring to place all the segments of a nbuf. +- */ +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); +- NSS_CORE_DSB(); +- nss_index = if_map->h2n_nss_index[qid]; +- ++ nss_index = h2n_desc_ring->nss_index_local; + hlos_index = h2n_desc_ring->hlos_index; +- + count = ((nss_index - hlos_index - 1) + size) & (mask); + ++ /* ++ * If local index shows that there is not enough space in the ring, ++ * Read the actual index from the consumer's generation (NSS-FW). ++ */ + if (unlikely(count < (segments + 1))) { + /* +- * NOTE: tx_q_full_cnt and TX_STOPPED flags will be used +- * when we will add support for DESC Q congestion management +- * in future +- */ +- h2n_desc_ring->tx_q_full_cnt++; +- h2n_desc_ring->flags |= NSS_H2N_DESC_RING_FLAGS_TX_STOPPED; +- spin_unlock_bh(&h2n_desc_ring->lock); +- nss_warning("%px: Data/Command Queue full reached", nss_ctx); ++ * We need to work out if there's sufficent space in our transmit descriptor ++ * ring to place all the segments of a nbuf. ++ */ ++ NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); ++ NSS_CORE_DSB(); ++ nss_index = if_map->h2n_nss_index[qid]; ++ h2n_desc_ring->nss_index_local = nss_index; ++ count = ((nss_index - hlos_index - 1) + size) & (mask); ++ if (unlikely(count < (segments + 1))) { ++ /* ++ * NOTE: tx_q_full_cnt and TX_STOPPED flags will be used ++ * when we will add support for DESC Q congestion management ++ * in future ++ */ ++ h2n_desc_ring->tx_q_full_cnt++; ++ h2n_desc_ring->flags |= NSS_H2N_DESC_RING_FLAGS_TX_STOPPED; ++ spin_unlock_bh(&h2n_desc_ring->lock); ++ nss_warning("%px: Data/Command Queue full reached", nss_ctx); + + #if (NSS_PKT_STATS_ENABLED == 1) +- if (nss_ctx->id == NSS_CORE_0) { +- NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_QUEUE_FULL_0]); +- } else if (nss_ctx->id == NSS_CORE_1) { +- NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_QUEUE_FULL_1]); +- } else { +- nss_warning("%px: Invalid nss core: %d\n", nss_ctx, nss_ctx->id); +- } ++ if (nss_ctx->id == NSS_CORE_0) { ++ NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_QUEUE_FULL_0]); ++ } else if (nss_ctx->id == NSS_CORE_1) { ++ NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_QUEUE_FULL_1]); ++ } else { ++ nss_warning("%px: Invalid nss core: %d\n", nss_ctx, nss_ctx->id); ++ } + #endif ++ /* ++ * Enable de-congestion interrupt from NSS ++ */ ++ nss_hal_enable_interrupt(nss_ctx, nss_ctx->int_ctx[0].shift_factor, NSS_N2H_INTR_TX_UNBLOCKED); + +- /* +- * Enable de-congestion interrupt from NSS +- */ +- nss_hal_enable_interrupt(nss_ctx, nss_ctx->int_ctx[0].shift_factor, NSS_N2H_INTR_TX_UNBLOCKED); +- +- return NSS_CORE_STATUS_FAILURE_QUEUE; ++ return NSS_CORE_STATUS_FAILURE_QUEUE; ++ } + } +- + desc = &desc_ring[hlos_index]; + + /* +--- a/nss_core.h ++++ b/nss_core.h +@@ -389,6 +389,7 @@ struct hlos_n2h_desc_ring { + struct hlos_h2n_desc_rings { + struct h2n_desc_if_instance desc_ring; /* Descriptor ring */ + uint32_t hlos_index; ++ uint32_t nss_index_local; /* Index number for the next descriptor (NSS owned) */ + spinlock_t lock; /* Lock to save from simultaneous access */ + uint32_t flags; /* Flags */ + uint64_t tx_q_full_cnt; /* Descriptor queue full count */ +--- a/nss_coredump.c ++++ b/nss_coredump.c +@@ -49,7 +49,8 @@ static struct workqueue_struct *coredump + */ + static void nss_coredump_wait(struct work_struct *work) + { +- panic("did not get all coredump finished signals\n"); ++ if (!(nss_cmd_buf.coredump & 0xFFFFFFFE)) ++ panic("did not get all coredump finished signals\n"); + } + + /* +--- a/nss_crypto_cmn.c ++++ b/nss_crypto_cmn.c +@@ -226,6 +226,12 @@ nss_tx_status_t nss_crypto_cmn_tx_msg_sy + * further details read Linux/Documentation/memory-barrier.txt + */ + smp_rmb(); ++ ++ if (msg->cm.response != NSS_CMN_RESPONSE_ACK) { ++ up(&pvt->sem); ++ return NSS_TX_FAILURE; ++ } ++ + up(&pvt->sem); + + return NSS_TX_SUCCESS; +--- a/nss_dynamic_interface.c ++++ b/nss_dynamic_interface.c +@@ -323,7 +323,9 @@ nss_tx_status_t nss_dynamic_interface_de + void nss_dynamic_interface_register_handler(struct nss_ctx_instance *nss_ctx) + { + nss_core_register_handler(nss_ctx, NSS_DYNAMIC_INTERFACE, nss_dynamic_interface_handler, NULL); +- nss_dynamic_interface_stats_dentry_create(); ++ if (nss_ctx->id == NSS_CORE_0) { ++ nss_dynamic_interface_stats_dentry_create(); ++ } + } + + /* +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -981,12 +981,12 @@ static int __nss_hal_clock_configure(str + * Check if turbo is supported + */ + if (npd->turbo_frequency) { +- nss_info_always("nss_driver - Turbo Support %d\n", npd->turbo_frequency); ++ nss_info("nss_driver - Turbo Support %d\n", npd->turbo_frequency); + #if (NSS_PM_SUPPORT == 1) + nss_pm_set_turbo(); + #endif + } else { +- nss_info_always("nss_driver - Turbo No Support %d\n", npd->turbo_frequency); ++ nss_info("nss_driver - Turbo No Support %d\n", npd->turbo_frequency); + } + + /* +@@ -1085,26 +1085,26 @@ clk_complete: + } + } + +- nss_info_always("Supported Frequencies - "); ++ nss_info("Supported Frequencies - "); + for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) { + if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_110) { +- nss_info_always("110Mhz "); ++ nss_info("110Mhz "); + } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_275) { +- nss_info_always("275Mhz "); ++ nss_info("275Mhz "); + } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_550) { +- nss_info_always("550Mhz "); ++ nss_info("550Mhz "); + } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_600) { +- nss_info_always("600Mhz "); ++ nss_info("600Mhz "); + } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_733) { +- nss_info_always("733Mhz "); ++ nss_info("733Mhz "); + } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_800) { +- nss_info_always("800Mhz "); ++ nss_info("800Mhz "); + } else { + nss_info_always("Error\nNo Table/Invalid Frequency Found - Loading Old Tables -"); + return -EFAULT; + } + } +- nss_info_always("\n"); ++ nss_info("\n"); + + /* + * Set default frequency +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -41,7 +41,6 @@ + /* + * Macros + */ +-#define MIN_IMG_SIZE (64*1024) + #define NSS_AP0_IMAGE "qca-nss0.bin" + #define NSS_AP1_IMAGE "qca-nss1.bin" + +@@ -62,7 +61,7 @@ int nss_hal_firmware_load(struct nss_ctx + } else if (nss_ctx->id == 1) { + rc = firmware_request_nowarn(&nss_fw, NSS_AP1_IMAGE, &(nss_dev->dev)); + } else { +- nss_warning("%px: Invalid nss dev: %d\n", nss_ctx, nss_ctx->id); ++ nss_warning("%px: Invalid nss dev: %d", nss_ctx, nss_ctx->id); + return -EINVAL; + } + +@@ -74,10 +73,6 @@ int nss_hal_firmware_load(struct nss_ctx + return rc; + } + +- if (nss_fw->size < MIN_IMG_SIZE) { +- nss_info_always("%px: nss firmware is truncated, size:%d", nss_ctx, (int)nss_fw->size); +- return rc; +- } + + load_mem = ioremap(npd->load_addr, nss_fw->size); + if (!load_mem) { +@@ -86,7 +81,7 @@ int nss_hal_firmware_load(struct nss_ctx + return rc; + } + +- nss_info_always("nss_driver - fw of size %d bytes copied to load addr: %x, nss_id : %d\n", (int)nss_fw->size, npd->load_addr, nss_dev->id); ++ nss_info("nss_driver - fw of size %d bytes copied to load addr: %x, nss_id : %d\n", (int)nss_fw->size, npd->load_addr, nss_dev->id); + memcpy_toio(load_mem, nss_fw->data, nss_fw->size); + release_firmware(nss_fw); + iounmap(load_mem); +@@ -210,14 +205,14 @@ int nss_hal_probe(struct platform_device + if (nss_top_main.nss_hal_common_init_done == false) { + err = nss_top->hal_ops->common_reset(nss_dev); + if (err) { +- nss_info_always("NSS HAL common init failed\n"); ++ nss_info_always("NSS HAL common init failed"); + return -EFAULT; + } + } + + #if (NSS_DT_SUPPORT == 1) + if (!nss_dev->dev.of_node) { +- pr_err("nss-driver: Device tree not available\n"); ++ pr_err("nss-driver: Device tree not available"); + return -ENODEV; + } + +@@ -242,27 +237,27 @@ int nss_hal_probe(struct platform_device + */ + nss_ctx->dev = &nss_dev->dev; + +- nss_info("%px: NSS_DEV_ID %s\n", nss_ctx, dev_name(&nss_dev->dev)); ++ nss_info("%px: NSS_DEV_ID %s", nss_ctx, dev_name(&nss_dev->dev)); + + /* + * Do firmware load from nss-drv if required + */ + err = nss_top->hal_ops->firmware_load(nss_ctx, nss_dev, npd); + if (err) { +- nss_info_always("%px: firmware load from driver failed\n", nss_ctx); ++ nss_info_always("%px: firmware load from driver failed", nss_ctx); + goto err_init; + } + + err = nss_top->hal_ops->clock_configure(nss_ctx, nss_dev, npd); + if (err) { +- nss_info_always("%px: clock configure failed\n", nss_ctx); ++ nss_info_always("%px: clock configure failed", nss_ctx); + goto err_init; + } + + /* + * Get load address of NSS firmware + */ +- nss_info("%px: Setting NSS%d Firmware load address to %x\n", nss_ctx, nss_ctx->id, npd->load_addr); ++ nss_info("%px: Setting NSS%d Firmware load address to %x", nss_ctx, nss_ctx->id, npd->load_addr); + nss_top->nss[nss_ctx->id].load = npd->load_addr; + + /* +@@ -298,7 +293,7 @@ int nss_hal_probe(struct platform_device + nss_ctx, nss_ctx->vphys, nss_ctx->vmap, nss_ctx->nphys, nss_ctx->nmap); + + if (!nss_meminfo_init(nss_ctx)) { +- nss_info_always("%px: meminfo init failed\n", nss_ctx); ++ nss_info_always("%px: meminfo init failed", nss_ctx); + err = -EFAULT; + goto err_init; + } +@@ -360,18 +355,25 @@ int nss_hal_probe(struct platform_device + } + #endif + ++#ifdef NSS_DRV_IPV4_ENABLE + if (npd->ipv4_enabled == NSS_FEATURE_ENABLED) { + nss_top->ipv4_handler_id = nss_dev->id; + nss_ipv4_register_handler(); ++#endif + + #ifdef NSS_DRV_EDMA_ENABLE + nss_top->edma_handler_id = nss_dev->id; + nss_edma_register_handler(); + #endif ++ ++#ifdef NSS_DRV_ETH_RX_ENABLE + nss_eth_rx_register_handler(nss_ctx); ++#endif ++ + #ifdef NSS_DRV_LAG_ENABLE + nss_lag_register_handler(); + #endif ++ + #ifdef NSS_DRV_TRUSTSEC_ENABLE + nss_top->trustsec_tx_handler_id = nss_dev->id; + nss_trustsec_tx_register_handler(); +@@ -466,10 +468,12 @@ int nss_hal_probe(struct platform_device + } + #endif + ++#ifdef NSS_DRV_PPPOE_ENABLE + if (npd->pppoe_enabled == NSS_FEATURE_ENABLED) { + nss_top->pppoe_handler_id = nss_dev->id; + nss_pppoe_register_handler(); + } ++#endif + + #ifdef NSS_DRV_PPE_ENABLE + if (npd->ppe_enabled == NSS_FEATURE_ENABLED) { +@@ -564,6 +568,7 @@ int nss_hal_probe(struct platform_device + } + #endif + ++#ifdef NSS_DRV_WIFIOFFLOAD_ENABLE + if (npd->wifioffload_enabled == NSS_FEATURE_ENABLED) { + nss_top->wifi_handler_id = nss_dev->id; + nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VAP] = nss_dev->id; +@@ -591,6 +596,7 @@ int nss_hal_probe(struct platform_device + */ + nss_wifili_thread_scheme_db_init(nss_dev->id); + } ++#endif + + #ifdef NSS_DRV_OAM_ENABLE + if (npd->oam_enabled == NSS_FEATURE_ENABLED) { +@@ -607,11 +613,13 @@ int nss_hal_probe(struct platform_device + } + #endif + ++#ifdef NSS_DRV_VLAN_ENABLE + if (npd->vlan_enabled == NSS_FEATURE_ENABLED) { + nss_top->vlan_handler_id = nss_dev->id; + nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VLAN] = nss_dev->id; + nss_vlan_register_handler(); + } ++#endif + + #ifdef NSS_DRV_QVPN_ENABLE + #if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT) +@@ -712,7 +720,9 @@ int nss_hal_probe(struct platform_device + nss_freq_init_cpu_usage(); + #endif + ++#ifdef NSS_DRV_LSO_RX_ENABLE + nss_lso_rx_register_handler(nss_ctx); ++#endif + } + + nss_top->frequency_handler_id = nss_dev->id; +--- a/nss_if.c ++++ b/nss_if.c +@@ -160,10 +160,10 @@ nss_tx_status_t nss_if_tx_buf(struct nss + } + + /* +- * nss_if_tx_msg() +- * Transmit a message to the specific interface on this core. ++ * nss_if_tx_msg_with_size() ++ * Transmit a message to the specific interface on this core with a specified size. + */ +-nss_tx_status_t nss_if_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_if_msg *nim) ++nss_tx_status_t nss_if_tx_msg_with_size(struct nss_ctx_instance *nss_ctx, struct nss_if_msg *nim, uint32_t size) + { + struct nss_cmn_msg *ncm = &nim->cm; + struct net_device *dev; +@@ -198,7 +198,19 @@ nss_tx_status_t nss_if_tx_msg(struct nss + return NSS_TX_FAILURE_BAD_PARAM; + } + +- return nss_core_send_cmd(nss_ctx, nim, sizeof(*nim), NSS_NBUF_PAYLOAD_SIZE); ++ return nss_core_send_cmd(nss_ctx, nim, sizeof(*nim), size); ++} ++EXPORT_SYMBOL(nss_if_tx_msg_with_size); ++ ++/* ++ * nss_if_tx_msg() ++ * Transmit a message to the specific interface on this core. ++ */ ++nss_tx_status_t nss_if_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_if_msg *nim) ++{ ++ NSS_VERIFY_CTX_MAGIC(nss_ctx); ++ ++ return nss_if_tx_msg_with_size(nss_ctx, nim, NSS_NBUF_PAYLOAD_SIZE); + } + + /* +--- a/nss_init.c ++++ b/nss_init.c +@@ -633,10 +633,24 @@ static struct ctl_table_header *nss_dev_ + */ + static int __init nss_init(void) + { ++#if defined(NSS_DRV_POINT_OFFLOAD) ++ struct device_node *pof = NULL; ++#endif ++ ++ + #if (NSS_DT_SUPPORT == 1) + struct device_node *cmn = NULL; + #endif +- nss_info("Init NSS driver"); ++ ++#if defined(NSS_DRV_POINT_OFFLOAD) ++ pof = of_find_node_by_name(NULL, "reg_update"); ++ if ((!pof) || (!of_property_read_bool(pof, "ubi_core_enable"))) { ++ nss_info_always("UBI is not enabled. Disable qca-nss-drv\n"); ++ return 0; ++ } ++#endif ++ ++nss_info("Init NSS driver"); + + #if (NSS_DT_SUPPORT == 1) + /* +@@ -739,7 +753,9 @@ static int __init nss_init(void) + /* + * Registering sysctl for ipv4/6 specific config. + */ ++#ifdef NSS_DRV_IPV4_ENABLE + nss_ipv4_register_sysctl(); ++#endif + #ifdef NSS_DRV_IPV6_ENABLE + nss_ipv6_register_sysctl(); + #endif +@@ -778,7 +794,9 @@ static int __init nss_init(void) + /* + * Registering sysctl for pppoe specific config. + */ ++#ifdef NSS_DRV_PPPOE_ENABLE + nss_pppoe_register_sysctl(); ++#endif + + /* + * Setup Runtime Sample values +@@ -916,13 +934,17 @@ static void __exit nss_cleanup(void) + /* + * Unregister pppoe specific sysctl + */ ++#ifdef NSS_DRV_PPPOE_ENABLE + nss_pppoe_unregister_sysctl(); ++#endif + + /* + * Unregister ipv4/6 specific sysctl and free allocated to connection tables + */ ++#ifdef NSS_DRV_IPV4_ENABLE + nss_ipv4_unregister_sysctl(); + nss_ipv4_free_conn_tables(); ++#endif + + #ifdef NSS_DRV_IPV6_ENABLE + nss_ipv6_unregister_sysctl(); +--- a/nss_meminfo.c ++++ b/nss_meminfo.c +@@ -409,7 +409,7 @@ static bool nss_meminfo_init_block_lists + + if (strcmp(r->name, "profile_dma_ctrl") == 0) { + mem_ctx->sdma_ctrl = kern_addr; +- nss_info_always("%px: set sdma %px\n", nss_ctx, kern_addr); ++ nss_info("%px: set sdma %px\n", nss_ctx, kern_addr); + } + + /* +@@ -536,6 +536,13 @@ static bool nss_meminfo_configure_n2h_h2 + } + + /* ++ * Returning true allows to execute firmware bin ++ */ ++ if (!mem_ctx->if_map) { ++ return true; ++ } ++ ++ /* + * Bring a fresh copy of if_map from memory in order to read it correctly. + */ + if_map = mem_ctx->if_map; +@@ -794,6 +801,6 @@ bool nss_meminfo_init(struct nss_ctx_ins + + nss_meminfo_init_debugfs(nss_ctx); + +- nss_info_always("%px: meminfo init succeed\n", nss_ctx); ++ nss_info("%px: meminfo init succeed\n", nss_ctx); + return true; + } +--- a/nss_n2h.c ++++ b/nss_n2h.c +@@ -2061,10 +2061,9 @@ void nss_n2h_register_handler(struct nss + + if (nss_ctx->id == NSS_CORE_0) { + nss_n2h_stats_dentry_create(); ++ nss_n2h_strings_dentry_create(); ++ nss_drv_strings_dentry_create(); + } +- nss_n2h_strings_dentry_create(); +- +- nss_drv_strings_dentry_create(); + } + + /* +--- a/nss_phys_if.h ++++ b/nss_phys_if.h +@@ -70,6 +70,12 @@ struct nss_phys_if_estats { + uint32_t gmac_worst_case_ticks; /**< Worst case iteration of the GMAC in ticks */ + uint32_t gmac_iterations; /**< Number of iterations around the GMAC */ + uint32_t tx_pause_frames; /**< Number of pause frames sent by the GMAC */ ++ ++ /* ++ * On IPQ50xx, we rely on the SSDK to pull the mmc stats. ++ * The FAL layer does not do this on IPQ806x. ++ */ ++#if defined(NSS_HAL_IPQ806X_SUPPORT) + uint32_t mmc_rx_overflow_errors; + /**< Number of RX overflow errors */ + uint32_t mmc_rx_watchdog_timeout_errors; +@@ -94,6 +100,7 @@ struct nss_phys_if_estats { + uint32_t mmc_tx_single_col; /* Number of single collisions */ + uint32_t mmc_tx_multiple_col; /* Number of multiple collisions */ + uint32_t mmc_tx_octets_gb; /* Number of good/bad octets sent*/ ++#endif + }; + + /** +--- a/nss_profiler.c ++++ b/nss_profiler.c +@@ -100,7 +100,7 @@ nss_tx_status_t nss_profiler_if_tx_buf(v + return NSS_TX_FAILURE_TOO_LARGE; + } + +- npm = kzalloc(sizeof(*npm), GFP_KERNEL); ++ npm = kzalloc(sizeof(*npm), GFP_ATOMIC); + if (!npm) { + nss_warning("%px: Failed to allocate memory for message\n", nss_ctx); + return NSS_TX_FAILURE; +@@ -124,6 +124,7 @@ void *nss_profiler_alloc_dma(struct nss_ + { + int size; + void *kaddr; ++ dma_addr_t dma_addr; + struct nss_profile_sdma_producer *dma; + struct nss_profile_sdma_ctrl *ctrl = (struct nss_profile_sdma_ctrl *)nss_ctx->meminfo_ctx.sdma_ctrl; + if (!ctrl) +@@ -135,7 +136,13 @@ void *nss_profiler_alloc_dma(struct nss_ + kaddr = kmalloc(size, GFP_KERNEL | __GFP_ZERO); + + if (kaddr) { +- dma->desc_ring = dma_map_single(nss_ctx->dev, kaddr, size, DMA_FROM_DEVICE); ++ dma_addr = dma_map_single(nss_ctx->dev, kaddr, size, DMA_FROM_DEVICE); ++ if (unlikely(dma_mapping_error(nss_ctx->dev, dma_addr))) { ++ nss_info_always("%px: failed to map DDR block\n", nss_ctx); ++ kfree(kaddr); ++ return NULL; ++ } ++ dma->desc_ring = dma_addr; + NSS_CORE_DSB(); + } + ctrl->consumer[0].ring.kp = kaddr; +--- a/nss_qrfs.c ++++ b/nss_qrfs.c +@@ -415,6 +415,65 @@ nss_tx_status_t nss_qrfs_set_flow_rule(s + EXPORT_SYMBOL(nss_qrfs_set_flow_rule); + + /* ++ * nss_qrfs_configure_flow_rule() ++ * Configures a QRFS flow rule to NSS firmware ++ */ ++nss_tx_status_t nss_qrfs_configure_flow_rule(uint32_t *dst_addr, uint32_t *src_addr, uint16_t dst_port, uint16_t src_port, uint32_t version, uint16_t proto, uint16_t cpu, enum nss_qrfs_msg_types type) { ++ ++ struct nss_qrfs_msg nqm; ++ struct nss_qrfs_flow_rule_msg *nqfrm; ++ nss_tx_status_t status; ++ struct nss_ctx_instance *nss_ctx = NULL; ++ nss_qrfs_msg_callback_t cb = NULL; ++ int i; ++ ++ ++ memset(&nqm, 0, sizeof(struct nss_qrfs_msg)); ++ nss_qrfs_msg_init(&nqm, NSS_QRFS_INTERFACE, type, ++ sizeof(struct nss_qrfs_flow_rule_msg), cb, (void *)nss_ctx); ++ if (type == NSS_QRFS_MSG_FLOW_ADD) { ++ nqfrm = &nqm.msg.flow_add; ++ cb = nss_qrfs_flow_add_msg_callback; ++ } else if (type == NSS_QRFS_MSG_FLOW_DELETE) { ++ nqfrm = &nqm.msg.flow_delete; ++ cb = nss_qrfs_flow_delete_msg_callback; ++ } else { ++ nss_warning("QRFS configure rule failed, not supported message type.\n"); ++ return NSS_TX_FAILURE_BAD_PARAM; ++ } ++ ++ ++ nqfrm->protocol = proto; ++ nqfrm->ip_version = version; ++ ++ if (version == 4) { ++ nqfrm->src_addr[0] = src_addr[0]; ++ nqfrm->dst_addr[0] = dst_addr[0]; ++ } else { ++ memcpy(nqfrm->src_addr, src_addr, sizeof(uint32_t) * 4); ++ memcpy(nqfrm->dst_addr, dst_addr, sizeof(uint32_t) * 4); ++ } ++ ++ nqfrm->src_port = src_port; ++ nqfrm->dst_port = dst_port; ++ nqfrm->cpu = cpu; ++ nqfrm->if_num = 0; ++ ++ for(i = 0; i < NSS_CORE_MAX; i++) { ++ nss_ctx = nss_qrfs_get_ctx(i); ++ status = nss_qrfs_tx_msg(nss_ctx, &nqm); ++ ++ if (status) { ++ nss_warning("%px: QRFS configure rule failed, error code: %d\n", nss_ctx, status); ++ return NSS_TX_FAILURE; ++ } ++ } ++ ++ return NSS_TX_SUCCESS; ++} ++EXPORT_SYMBOL(nss_qrfs_configure_flow_rule); ++ ++/* + * nss_qrfs_register_handler() + */ + void nss_qrfs_register_handler(struct nss_ctx_instance *nss_ctx) +--- a/exports/nss_qrfs.h ++++ b/exports/nss_qrfs.h +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2017-2018, 2021 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -110,6 +110,7 @@ struct nss_qrfs_msg { + } msg; /**< Message payload. */ + }; + ++#ifdef __KERNEL__ + /** + * Callback function for receiving QRFS messages. + * +@@ -176,6 +177,23 @@ void nss_qrfs_notify_unregister(int core + * Status of the Tx operation. + */ + nss_tx_status_t nss_qrfs_set_flow_rule(struct sk_buff *skb, uint32_t cpu, uint32_t action); ++/** ++ * nss_qrfs_configure_flow_rule ++ * Configures and sends a QRFS message to the NSS core to configure(add/remove) the flow rule. ++ * ++ * @param[in] dst_addr Destination IP address. ++ * @param[in] src_addr Source IP address. ++ * @param[in] dst_port Destination port. ++ * @param[in] src_port Source port. ++ * @param[in] version IP version. ++ * @param[in] proto Protocol. ++ * @param[in] cpu CPU number to be offloaded to. ++ * @param[in] type Type of action to perform on the flow table, can be add or delete. ++ * ++ * @return ++ * Status of the Tx operation. ++ */ ++nss_tx_status_t nss_qrfs_configure_flow_rule(uint32_t *dst_addr, uint32_t *src_addr, uint16_t dst_port, uint16_t src_port, uint32_t version, uint16_t proto, uint16_t cpu, enum nss_qrfs_msg_types type); + + /** + * nss_qrfs_init +@@ -190,4 +208,5 @@ void nss_qrfs_init(void); + * @} + */ + ++#endif + #endif /* __NSS_QRFS_H */ +--- a/nss_rmnet_rx.c ++++ b/nss_rmnet_rx.c +@@ -243,6 +243,8 @@ static int nss_rmnet_rx_handle_destroy_s + rmnet_rx_handle[index_h2n] = NULL; + spin_unlock_bh(&nss_rmnet_rx_lock); + ++ kfree(handle->stats_h2n); ++ kfree(handle->stats_n2h); + kfree(handle->pvt); + kfree(handle); + +--- a/nss_rps.c ++++ b/nss_rps.c +@@ -278,6 +278,7 @@ static nss_tx_status_t nss_rps_cfg(struc + return NSS_SUCCESS; + } + ++#ifdef NSS_DRV_IPV4_ENABLE + /* + * nss_rps_ipv4_hash_bitmap_cfg() + * Send Message to NSS to configure hash_bitmap. +@@ -306,6 +307,7 @@ static nss_tx_status_t nss_rps_ipv4_hash + up(&nss_rps_cfg_pvt.sem); + return NSS_SUCCESS; + } ++#endif + + #ifdef NSS_DRV_IPV6_ENABLE + /* +@@ -456,8 +458,8 @@ static int nss_rps_hash_bitmap_cfg_handl + void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; +- struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +- int ret, ret_ipv4, current_state; ++ struct nss_ctx_instance *nss_ctx __attribute__((unused)) = &nss_top->nss[0]; ++ int ret, current_state; + + current_state = nss_rps_hash_bitmap; + ret = proc_dointvec(ctl, write, buffer, lenp, ppos); +@@ -471,16 +473,24 @@ static int nss_rps_hash_bitmap_cfg_handl + return ret; + } + ++#if !defined(NSS_DRV_IPV4_ENABLE) || !defined(NSS_DRV_IPV6_ENABLE) ++ nss_info_always("%px: Feature is not supported\n", nss_ctx); ++ return 0; ++#else + if (nss_rps_hash_bitmap <= (NSS_RPS_MAX_CORE_HASH_BITMAP)) { + nss_info("Configuring NSS RPS hash_bitmap\n"); +- ret_ipv4 = nss_rps_ipv4_hash_bitmap_cfg(nss_ctx, nss_rps_hash_bitmap); ++#ifdef NSS_DRV_IPV4_ENABLE ++ { ++ int ret_ipv4; ++ ret_ipv4 = nss_rps_ipv4_hash_bitmap_cfg(nss_ctx, nss_rps_hash_bitmap); + +- if (ret_ipv4 != NSS_SUCCESS) { +- nss_warning("%px: ipv4 hash_bitmap config message failed\n", nss_ctx); +- nss_rps_hash_bitmap = current_state; +- return ret_ipv4; ++ if (ret_ipv4 != NSS_SUCCESS) { ++ nss_warning("%px: ipv4 hash_bitmap config message failed\n", nss_ctx); ++ nss_rps_hash_bitmap = current_state; ++ return ret_ipv4; ++ } + } +- ++#endif + #ifdef NSS_DRV_IPV6_ENABLE + { + int ret_ipv6; +@@ -501,6 +511,7 @@ static int nss_rps_hash_bitmap_cfg_handl + + nss_info_always("Invalid input value. Valid values are less than %d\n", (NSS_RPS_MAX_CORE_HASH_BITMAP)); + return ret; ++#endif + } + + /* nss_rps_pri_map_cfg_handler() +--- a/nss_stats.c ++++ b/nss_stats.c +@@ -152,6 +152,14 @@ int nss_stats_open(struct inode *inode, + } + + /* ++ * nss_clear_stats_write() ++ * Clear content of stats. ++ */ ++ssize_t nss_clear_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) { ++ return -ESRCH; ++} ++ ++/* + * nss_stats_release() + * Releases stats file. + */ +--- a/nss_stats.h ++++ b/nss_stats.h +@@ -41,10 +41,11 @@ + #define NSS_STATS_EXTRA_OUTPUT_LINES 35 + + #define NSS_STATS_DECLARE_FILE_OPERATIONS(name) \ +-static const struct file_operations nss_##name##_stats_ops = { \ ++static struct file_operations nss_##name##_stats_ops = { \ + .open = nss_stats_open, \ + .read = nss_##name##_stats_read, \ +- .llseek = generic_file_llseek, \ ++ .write = nss_clear_stats_write, \ ++ .llseek = generic_file_llseek, \ + .release = nss_stats_release, \ + }; + +@@ -71,6 +72,7 @@ extern void nss_stats_register_sysctl(vo + void nss_stats_init(void); + extern int nss_stats_release(struct inode *inode, struct file *filp); + extern int nss_stats_open(struct inode *inode, struct file *filp); ++extern ssize_t nss_clear_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos); + void nss_stats_create_dentry(char *name, const struct file_operations *ops); + extern void nss_stats_reset_common_stats(uint32_t if_num); + extern size_t nss_stats_fill_common_stats(uint32_t if_num, int instance, char *lbuf, size_t size_wr, size_t size_al, char *node); +--- a/nss_vxlan.c ++++ b/nss_vxlan.c +@@ -226,6 +226,7 @@ bool nss_vxlan_unregister_if(uint32_t if + } + + nss_core_unregister_handler(nss_ctx, if_num); ++ nss_core_unregister_msg_handler(nss_ctx, if_num); + nss_core_unregister_subsys_dp(nss_ctx, if_num); + return true; + } +--- a/nss_wifi_vdev.c ++++ b/nss_wifi_vdev.c +@@ -199,8 +199,16 @@ EXPORT_SYMBOL(nss_wifi_vdev_tx_msg_ext); + */ + nss_tx_status_t nss_wifi_vdev_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num) + { ++ enum nss_dynamic_interface_type if_type; ++ + BUG_ON(((if_num < NSS_DYNAMIC_IF_START) || (if_num >= (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES)))); + ++ if_type = nss_dynamic_interface_get_type(nss_ctx, if_num); ++ if (if_type != NSS_DYNAMIC_INTERFACE_TYPE_VAP) { ++ nss_warning("%px: non vap %d packet tx not allowed", nss_ctx, if_num); ++ return NSS_TX_FAILURE_NOT_SUPPORTED; ++ } ++ + return nss_core_send_packet(nss_ctx, os_buf, if_num, H2N_BIT_FLAG_BUFFER_REUSABLE); + } + EXPORT_SYMBOL(nss_wifi_vdev_tx_buf); +--- a/nss_data_plane/include/nss_data_plane.h ++++ b/nss_data_plane/include/nss_data_plane.h +@@ -25,6 +25,8 @@ + #include + #include "nss_phys_if.h" + ++#define NSS_DATA_PLANE_MAX_PACKET_LEN 65535 ++ + /* + * nss_data_plane_schedule_registration() + * Called from nss_init to schedule a work to do data_plane register to data plane host driver +--- a/nss_data_plane/nss_data_plane.c ++++ b/nss_data_plane/nss_data_plane.c +@@ -101,12 +101,6 @@ static int __nss_data_plane_mac_addr(str + static int __nss_data_plane_change_mtu(struct nss_dp_data_plane_ctx *dpc, uint32_t mtu) + { + struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc; +- +- if (mtu > NSS_DP_MAX_MTU_SIZE) { +- nss_warning("%px: MTU exceeds MAX size %d\n", dp, mtu); +- return NSS_DP_FAILURE; +- } +- + return nss_phys_if_change_mtu(dp->nss_ctx, mtu, dp->if_num); + } + +@@ -166,8 +160,9 @@ static netdev_tx_t __nss_data_plane_buf( + goto drop; + } + +- if (skb->len > NSS_DP_MAX_PACKET_LEN) { +- nss_warning("skb->len ( %u ) > Maximum packet length ( %u ) \n", skb->len, NSS_DP_MAX_PACKET_LEN); ++ if (skb->len > NSS_DATA_PLANE_MAX_PACKET_LEN) { ++ nss_warning("skb->len ( %u ) > Maximum packet length ( %u ) \n", ++ skb->len, NSS_DATA_PLANE_MAX_PACKET_LEN); + goto drop; + } + +--- a/nss_wifili_stats.c ++++ b/nss_wifili_stats.c +@@ -37,6 +37,38 @@ ATOMIC_NOTIFIER_HEAD(nss_wifili_stats_no + struct nss_wifili_soc_stats soc_stats[NSS_WIFILI_MAX_SOC_NUM]; + + /* ++ * nss_wifili_target_type_string() ++ * Convert Target Type Integer to String ++ */ ++void nss_wifili_target_type_to_string(uint32_t target_type, char *target_type_str) ++{ ++ switch (target_type) { ++ ++ case NSS_WIFILI_TARGET_TYPE_QCA8074: ++ snprintf(target_type_str, NSS_WIFILI_SOC_STRING_SIZE_MAX, "IPQ8074 V1"); ++ break; ++ case NSS_WIFILI_TARGET_TYPE_QCA8074V2: ++ case 0: ++ snprintf(target_type_str, NSS_WIFILI_SOC_STRING_SIZE_MAX, "IPQ8074 V2"); ++ break; ++ case NSS_WIFILI_TARGET_TYPE_QCA6018: ++ snprintf(target_type_str, NSS_WIFILI_SOC_STRING_SIZE_MAX, "IPQ6018"); ++ break; ++ case NSS_WIFILI_TARGET_TYPE_QCN9000: ++ snprintf(target_type_str, NSS_WIFILI_SOC_STRING_SIZE_MAX, "QCN9000"); ++ break; ++ case NSS_WIFILI_TARGET_TYPE_QCA5018: ++ snprintf(target_type_str, NSS_WIFILI_SOC_STRING_SIZE_MAX, "IPQ5018"); ++ break; ++ case NSS_WIFILI_TARGET_TYPE_QCN6122: ++ snprintf(target_type_str, NSS_WIFILI_SOC_STRING_SIZE_MAX, "QCN6122"); ++ break; ++ default : ++ snprintf(target_type_str, NSS_WIFILI_SOC_STRING_SIZE_MAX, "Unknown"); ++ } ++} ++ ++/* + * nss_wifili_stats_read() + * Read wifili statistics + */ +@@ -56,6 +88,7 @@ static ssize_t nss_wifili_stats_read(str + char *lbuf = NULL; + uint32_t soc_idx; + struct nss_wifili_stats *stats_wifili = NULL; ++ char pdev_tag[NSS_WIFILI_SOC_STRING_SIZE_MAX]; + + /* + * Max number of pdev depends on type of soc (Internal/Attached). +@@ -83,12 +116,17 @@ static ssize_t nss_wifili_stats_read(str + return 0; + } + +- size_wr += nss_stats_banner(lbuf, size_wr, size_al, "wifili", NSS_STATS_SINGLE_CORE); + + for (soc_idx = 0; soc_idx < NSS_WIFILI_MAX_SOC_NUM; soc_idx++) { ++ if (soc_stats[soc_idx].soc_maxpdev == 0) { ++ continue; ++ } ++ ++ size_wr += nss_stats_banner(lbuf, size_wr, size_al, soc_stats[soc_idx].soc_type, NSS_STATS_SINGLE_CORE); + stats_wifili = &(soc_stats[soc_idx].stats_wifili); + for (i = 0; i < soc_stats[soc_idx].soc_maxpdev; i++) { +- ++ snprintf(pdev_tag, NSS_WIFILI_SOC_STRING_SIZE_MAX, "PDEV %d", i); ++ size_wr += nss_stats_banner(lbuf, size_wr, size_al, pdev_tag, NSS_STATS_SINGLE_CORE); + spin_lock_bh(&nss_top_main.stats_lock); + size_wr += nss_stats_print("wifili", "txrx", i + , nss_wifili_strings_stats_txrx +@@ -238,6 +276,9 @@ void nss_wifili_stats_sync(struct nss_ct + struct nss_wifili_stats *stats = NULL; + struct nss_wifili_device_stats *devstats = &wlsoc_stats->stats; + uint32_t index; ++ char target_type_str[NSS_WIFILI_SOC_STRING_SIZE_MAX]; ++ ++ nss_wifili_target_type_to_string(wlsoc_stats->target_type, target_type_str); + + /* + * Max number of pdev depends on type of soc (Internal/Attached). +@@ -246,16 +287,19 @@ void nss_wifili_stats_sync(struct nss_ct + case NSS_WIFILI_INTERNAL_INTERFACE: + nwss = &soc_stats[0]; + nwss->soc_maxpdev = NSS_WIFILI_MAX_PDEV_NUM_MSG; ++ snprintf(nwss->soc_type, NSS_WIFILI_SOC_STRING_SIZE_MAX, "INTERNAL: %s", target_type_str); + break; + + case NSS_WIFILI_EXTERNAL_INTERFACE0: + nwss = &soc_stats[1]; + nwss->soc_maxpdev = NSS_WIFILI_SOC_ATTACHED_MAX_PDEV_NUM; ++ snprintf(nwss->soc_type, NSS_WIFILI_SOC_STRING_SIZE_MAX, "ATTACH 0: %s", target_type_str); + break; + + case NSS_WIFILI_EXTERNAL_INTERFACE1: + nwss = &soc_stats[2]; + nwss->soc_maxpdev = NSS_WIFILI_SOC_ATTACHED_MAX_PDEV_NUM; ++ snprintf(nwss->soc_type, NSS_WIFILI_SOC_STRING_SIZE_MAX, "ATTACH 1: %s", target_type_str); + break; + + default: +@@ -458,7 +502,7 @@ void nss_wifili_stats_notify(struct nss_ + struct nss_wifili_stats_notification *wifili_stats; + uint32_t index = 0; + +- wifili_stats = kzalloc(sizeof(struct nss_wifili_stats_notification), GFP_ATOMIC); ++ wifili_stats = kzalloc(sizeof(struct nss_wifili_stats_notification), in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); + if (!wifili_stats) { + nss_warning("%px: Failed to allocate memory for wifili stats\n", nss_ctx); + return; +--- a/nss_wifili_stats.h ++++ b/nss_wifili_stats.h +@@ -22,6 +22,13 @@ + #ifndef __NSS_WIFILI_STATS_H + #define __NSS_WIFILI_STATS_H + ++#define NSS_WIFILI_TARGET_TYPE_QCA8074 20 ++#define NSS_WIFILI_TARGET_TYPE_QCA8074V2 24 ++#define NSS_WIFILI_TARGET_TYPE_QCA6018 25 ++#define NSS_WIFILI_TARGET_TYPE_QCN9000 26 ++#define NSS_WIFILI_TARGET_TYPE_QCA5018 29 ++#define NSS_WIFILI_TARGET_TYPE_QCN6122 30 ++ + #include "nss_core.h" + #include "nss_wifili_if.h" + +--- a/nss_wifi_mesh_stats.c ++++ b/nss_wifi_mesh_stats.c +@@ -223,7 +223,7 @@ static uint32_t nss_wifi_mesh_get_valid_ + static ssize_t nss_wifi_mesh_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos, uint16_t type) + { + uint32_t max_output_lines, max_stats; +- size_t size_al, size_wr; ++ size_t size_al, size_wr = 0; + ssize_t bytes_read = 0; + struct nss_stats_data *data = fp->private_data; + int ifindex; diff --git a/qca-nss-drv/patches-11.4/0013-nss-drv-remove-legacy-wifi.patch b/qca-nss-drv/patches-11.4/0013-nss-drv-remove-legacy-wifi.patch new file mode 100644 index 0000000..c159e98 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0013-nss-drv-remove-legacy-wifi.patch @@ -0,0 +1,12 @@ +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -572,7 +572,9 @@ int nss_hal_probe(struct platform_device + if (npd->wifioffload_enabled == NSS_FEATURE_ENABLED) { + nss_top->wifi_handler_id = nss_dev->id; + nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VAP] = nss_dev->id; ++#if defined(NSS_HAL_IPQ806x_SUPPORT) + nss_wifi_register_handler(); ++#endif + nss_wifili_register_handler(); + #ifdef NSS_DRV_WIFI_EXT_VDEV_ENABLE + nss_wifi_ext_vdev_register_handler(); diff --git a/qca-nss-drv/patches-11.4/0014-Add-kernel-6.1-support.patch b/qca-nss-drv/patches-11.4/0014-Add-kernel-6.1-support.patch new file mode 100644 index 0000000..1d405e4 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0014-Add-kernel-6.1-support.patch @@ -0,0 +1,183 @@ +--- a/nss_hal/fsm9010/nss_hal_pvt.c ++++ b/nss_hal/fsm9010/nss_hal_pvt.c +@@ -291,7 +291,7 @@ static int __nss_hal_request_irq(struct + } + + int_ctx->irq = npd->irq[irq_num]; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi, 64); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi, 64); + return 0; + } + +--- a/nss_hal/ipq50xx/nss_hal_pvt.c ++++ b/nss_hal/ipq50xx/nss_hal_pvt.c +@@ -598,7 +598,7 @@ static int __nss_hal_request_irq(struct + return err; + } + +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, napi_poll_cb, napi_wgt); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, napi_poll_cb, napi_wgt); + int_ctx->cause = cause; + err = request_irq(irq, nss_hal_handle_irq, 0, irq_name, int_ctx); + if (err) { +--- a/nss_hal/ipq60xx/nss_hal_pvt.c ++++ b/nss_hal/ipq60xx/nss_hal_pvt.c +@@ -614,62 +614,62 @@ static int __nss_hal_request_irq(struct + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_sos", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_queue", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_TX_UNBLOCKED; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss-tx-unblock", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_0; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue0", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1) { + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_1; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue1", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2) { + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_2; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue2", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3) { + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_3; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue3", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE) { + int_ctx->cause = NSS_N2H_INTR_COREDUMP_COMPLETE; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_coredump_complete", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_paged_empty_buf_sos", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA) { + int_ctx->cause = NSS_N2H_INTR_PROFILE_DMA; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_profile_dma", int_ctx); + } + +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -1186,7 +1186,7 @@ static int __nss_hal_request_irq(struct + } + + int_ctx->irq = npd->irq[irq_num]; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi, 64); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi, 64); + + return 0; + } +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -657,62 +657,62 @@ static int __nss_hal_request_irq(struct + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_sos", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_queue", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_TX_UNBLOCKED; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss-tx-unblock", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_0; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue0", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1) { + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_1; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue1", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2) { + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_2; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue2", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3) { + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_3; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue3", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE) { + int_ctx->cause = NSS_N2H_INTR_COREDUMP_COMPLETE; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_coredump_complete", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_paged_empty_buf_sos", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA) { + int_ctx->cause = NSS_N2H_INTR_PROFILE_DMA; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_profile_dma", int_ctx); + } + diff --git a/qca-nss-drv/patches-11.4/0014-nss-drv-avoid-recreating-virt_if.patch b/qca-nss-drv/patches-11.4/0014-nss-drv-avoid-recreating-virt_if.patch new file mode 100644 index 0000000..3de48d4 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0014-nss-drv-avoid-recreating-virt_if.patch @@ -0,0 +1,14 @@ +--- a/nss_stats.c ++++ b/nss_stats.c +@@ -388,8 +388,9 @@ size_t nss_stats_print(char *node, char + */ + void nss_stats_create_dentry(char *name, const struct file_operations *ops) + { +- if (!debugfs_create_file(name, 0400, nss_top_main.stats_dentry, &nss_top_main, ops)) { +- nss_warning("Failed to create debug entry for subsystem %s\n", name); ++ if (!debugfs_lookup(name, nss_top_main.stats_dentry)) ++ if (!debugfs_create_file(name, 0400, nss_top_main.stats_dentry, &nss_top_main, ops)) { ++ nss_warning("Failed to create debug entry for subsystem %s\n", name); + } + } + diff --git a/qca-nss-drv/patches-11.4/0015-nss-drv-fix-igs.patch b/qca-nss-drv/patches-11.4/0015-nss-drv-fix-igs.patch new file mode 100644 index 0000000..e027d8b --- /dev/null +++ b/qca-nss-drv/patches-11.4/0015-nss-drv-fix-igs.patch @@ -0,0 +1,40 @@ +--- a/nss_igs.c ++++ b/nss_igs.c +@@ -163,7 +163,7 @@ EXPORT_SYMBOL(nss_igs_register_if); + * nss_igs_get_context() + * Get the IGS context. + */ +-struct nss_ctx_instance *nss_igs_get_context() ++struct nss_ctx_instance *nss_igs_get_context(void) + { + return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.igs_handler_id]; + } +@@ -177,8 +177,9 @@ EXPORT_SYMBOL(nss_igs_get_context); + void nss_igs_module_save(struct tc_action_ops *act, struct module *module) + { + nss_assert(act); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) + nss_assert(act->type == TCA_ACT_MIRRED_NSS); +- ++#endif + nss_igs_module = module; + } + EXPORT_SYMBOL(nss_igs_module_save); +@@ -188,7 +189,7 @@ EXPORT_SYMBOL(nss_igs_module_save); + * nss_igs_module_get() + * Get the ingress shaping module reference. + */ +-bool nss_igs_module_get() ++bool nss_igs_module_get(void) + { + nss_assert(nss_igs_module); + return try_module_get(nss_igs_module); +@@ -199,7 +200,7 @@ EXPORT_SYMBOL(nss_igs_module_get); + * nss_igs_module_put() + * Release the ingress shaping module reference. + */ +-void nss_igs_module_put() ++void nss_igs_module_put(void) + { + nss_assert(nss_igs_module); + module_put(nss_igs_module); diff --git a/qca-nss-drv/patches-11.4/0016-nss-drv-add-support-for-kernel-6.6.patch b/qca-nss-drv/patches-11.4/0016-nss-drv-add-support-for-kernel-6.6.patch new file mode 100644 index 0000000..4138842 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0016-nss-drv-add-support-for-kernel-6.6.patch @@ -0,0 +1,824 @@ +--- a/nss_core.c ++++ b/nss_core.c +@@ -57,7 +57,7 @@ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0)))))) ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(6, 14, 0)))))) + #error "Check skb recycle code in this file to match Linux version" + #endif + +@@ -1063,13 +1063,18 @@ static inline void nss_core_rx_pbuf(stru + */ + static inline void nss_core_set_skb_classify(struct sk_buff *nbuf) + { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 6, 0)) + #ifdef CONFIG_NET_CLS_ACT + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) +- nbuf->tc_verd = SET_TC_NCLS_NSS(nbuf->tc_verd); ++ nbuf->tc_verd = SET_TC_NCLS_NSS(nbuf->tc_verd); + #else +- skb_set_tc_classify_offload(nbuf); ++ skb_set_tc_classify_offload(nbuf); + #endif + #endif ++#else ++ nss_warning("%px:API not supported on 6.6\n", nbuf); ++ nss_assert(0); ++#endif + } + + /* +@@ -2609,6 +2614,16 @@ static inline bool nss_core_skb_can_reus + return false; + #endif + ++ /* ++ * TODO: This check is only validated on kernel 6.6 ++ * This needs to be validated on prior linux ++ * kernel versions. ++ */ ++#ifdef CONFIG_SKB_EXTENSIONS ++ if (nbuf->active_extensions) ++ return false; ++#endif ++ + return true; + } + +--- a/nss_dynamic_interface.c ++++ b/nss_dynamic_interface.c +@@ -226,7 +226,7 @@ int nss_dynamic_interface_alloc_node(enu + core_id = nss_top_main.dynamic_interface_table[type]; + nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[core_id]; + di_data.if_num = -1; +- di_data.response = false; ++ di_data.response = NSS_CMN_RESPONSE_ACK; + init_completion(&di_data.complete); + + nss_dynamic_interface_msg_init(&ndim, NSS_DYNAMIC_INTERFACE, NSS_DYNAMIC_INTERFACE_ALLOC_NODE, +@@ -285,7 +285,7 @@ nss_tx_status_t nss_dynamic_interface_de + + core_id = nss_top_main.dynamic_interface_table[type]; + nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[core_id]; +- di_data.response = false; ++ di_data.response = NSS_CMN_RESPONSE_ACK; + init_completion(&di_data.complete); + + if (nss_is_dynamic_interface(if_num) == false) { +--- a/nss_init.c ++++ b/nss_init.c +@@ -584,48 +584,9 @@ static struct ctl_table nss_general_tabl + { } + }; + +-static struct ctl_table nss_init_dir[] = { +-#if (NSS_FREQ_SCALE_SUPPORT == 1) +- { +- .procname = "clock", +- .mode = 0555, +- .child = nss_freq_table, +- }, +-#endif +- { +- .procname = "general", +- .mode = 0555, +- .child = nss_general_table, +- }, +-#if (NSS_SKB_REUSE_SUPPORT == 1) +- { +- .procname = "skb_reuse", +- .mode = 0555, +- .child = nss_skb_reuse_table, +- }, +-#endif +- { } +-}; +- +-static struct ctl_table nss_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_init_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_root_dir, +- }, +- { } +-}; +- +-static struct ctl_table_header *nss_dev_header; ++static struct ctl_table_header *nss_clock_header; ++static struct ctl_table_header *nss_skb_header; ++static struct ctl_table_header *nss_general_header; + + /* + * nss_init() +@@ -748,7 +709,16 @@ nss_info("Init NSS driver"); + /* + * Register sysctl table. + */ +- nss_dev_header = register_sysctl_table(nss_root); ++ // to avoid multiple calls to `register_sysctl_table` ++ nss_general_header = register_sysctl("dev/nss/general", nss_general_table); ++ ++#if (NSS_SKB_REUSE_SUPPORT == 1) ++ nss_skb_header = register_sysctl("dev/nss/skb_reuse", nss_skb_reuse_table); ++#endif ++ ++#if (NSS_FREQ_SCALE_SUPPORT == 1) ++ nss_clock_header = register_sysctl("dev/nss/clock", nss_freq_table); ++#endif + + /* + * Registering sysctl for ipv4/6 specific config. +@@ -911,8 +881,18 @@ static void __exit nss_cleanup(void) + { + nss_info("Exit NSS driver"); + +- if (nss_dev_header) +- unregister_sysctl_table(nss_dev_header); ++ if (nss_general_header) ++ unregister_sysctl_table(nss_general_header); ++ ++#if (NSS_SKB_REUSE_SUPPORT == 1) ++ if (nss_skb_header) ++ unregister_sysctl_table(nss_skb_header); ++#endif ++ ++#if (NSS_FREQ_SCALE_SUPPORT == 1) ++ if (nss_clock_header) ++ unregister_sysctl_table(nss_clock_header); ++#endif + + /* + * Unregister n2h specific sysctl +--- a/nss_project.c ++++ b/nss_project.c +@@ -279,33 +279,6 @@ static struct ctl_table nss_project_tabl + { } + }; + +-static struct ctl_table nss_project_dir[] = { +- { +- .procname = "project", +- .mode = 0555, +- .child = nss_project_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_project_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_project_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_project_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_project_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_project_header; + + /* +@@ -314,7 +287,7 @@ static struct ctl_table_header *nss_proj + */ + void nss_project_register_sysctl(void) + { +- nss_project_header = register_sysctl_table(nss_project_root); ++ nss_project_header = register_sysctl("dev/nss/project", nss_project_table); + } + + /* +--- a/nss_n2h.c ++++ b/nss_n2h.c +@@ -1155,11 +1155,11 @@ static nss_tx_status_t nss_n2h_mitigatio + } + + up(&nss_n2h_mitigationcp[core_num].sem); +- return NSS_SUCCESS; ++ return NSS_TX_SUCCESS; + + failure: + up(&nss_n2h_mitigationcp[core_num].sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + static inline void nss_n2h_buf_pool_free(struct nss_n2h_buf_pool *buf_pool) +@@ -1240,10 +1240,10 @@ static nss_tx_status_t nss_n2h_buf_pool_ + up(&nss_n2h_bufcp[core_num].sem); + } while(num_pages); + +- return NSS_SUCCESS; ++ return NSS_TX_SUCCESS; + failure: + up(&nss_n2h_bufcp[core_num].sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + /* +@@ -1542,7 +1542,7 @@ static nss_tx_status_t nss_n2h_host_bp_c + if (nss_tx_status != NSS_TX_SUCCESS) { + nss_warning("%px: nss_tx error setting back pressure\n", nss_ctx); + up(&nss_n2h_host_bp_cfg_pvt.sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + /* +@@ -1552,7 +1552,7 @@ static nss_tx_status_t nss_n2h_host_bp_c + if (ret == 0) { + nss_warning("%px: Waiting for ack timed out\n", nss_ctx); + up(&nss_n2h_host_bp_cfg_pvt.sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + /* +@@ -1560,11 +1560,11 @@ static nss_tx_status_t nss_n2h_host_bp_c + */ + if (nss_n2h_host_bp_cfg_pvt.response == NSS_FAILURE) { + up(&nss_n2h_host_bp_cfg_pvt.sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + up(&nss_n2h_host_bp_cfg_pvt.sem); +- return NSS_SUCCESS; ++ return NSS_TX_SUCCESS; + } + + /* +@@ -1859,38 +1859,9 @@ static struct ctl_table nss_n2h_table_mu + { } + }; + +-/* +- * This table will be overwritten during single-core registration +- */ +-static struct ctl_table nss_n2h_dir[] = { +- { +- .procname = "n2hcfg", +- .mode = 0555, +- .child = nss_n2h_table_multi_core, +- }, +- { } +-}; +- +-static struct ctl_table nss_n2h_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_n2h_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_n2h_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_n2h_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_n2h_header; + ++ + /* + * nss_n2h_cfg_empty_pool_size() + * Config empty buffer pool +@@ -2130,8 +2101,7 @@ void nss_n2h_single_core_register_sysctl + /* + * Register sysctl table. + */ +- nss_n2h_dir[0].child = nss_n2h_table_single_core; +- nss_n2h_header = register_sysctl_table(nss_n2h_root); ++ nss_n2h_header = register_sysctl("dev/nss/n2hcfg", nss_n2h_table_single_core); + } + + /* +@@ -2229,7 +2199,7 @@ void nss_n2h_multi_core_register_sysctl( + /* + * Register sysctl table. + */ +- nss_n2h_header = register_sysctl_table(nss_n2h_root); ++ nss_n2h_header = register_sysctl("dev/nss/n2hcfg", nss_n2h_table_multi_core); + } + + /* +--- a/nss_ppe_vp.c ++++ b/nss_ppe_vp.c +@@ -783,24 +783,6 @@ static struct ctl_table nss_ppe_vp_table + { } + }; + +-static struct ctl_table nss_ppe_vp_dir[] = { +- { +- .procname = "ppe_vp", +- .mode = 0555, +- .child = nss_ppe_vp_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_ppe_vp_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_ppe_vp_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_ppe_vp_procfs_header; + + /* +@@ -812,7 +794,7 @@ void nss_ppe_vp_procfs_register(void) + /* + * Register sysctl table. + */ +- nss_ppe_vp_procfs_header = register_sysctl_table(nss_ppe_vp_root_dir); ++ nss_ppe_vp_procfs_header = register_sysctl("dev/nss/ppe_vp", nss_ppe_vp_table); + } + + /* +--- a/nss_pppoe.c ++++ b/nss_pppoe.c +@@ -353,33 +353,6 @@ static struct ctl_table nss_pppoe_table[ + { } + }; + +-static struct ctl_table nss_pppoe_dir[] = { +- { +- .procname = "pppoe", +- .mode = 0555, +- .child = nss_pppoe_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_pppoe_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_pppoe_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_pppoe_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_pppoe_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_pppoe_header; + + /* +@@ -391,7 +364,7 @@ void nss_pppoe_register_sysctl(void) + /* + * Register sysctl table. + */ +- nss_pppoe_header = register_sysctl_table(nss_pppoe_root); ++ nss_pppoe_header = register_sysctl("dev/nss/pppoe", nss_pppoe_table); + } + + /* +--- a/nss_rps.c ++++ b/nss_rps.c +@@ -251,7 +251,7 @@ static nss_tx_status_t nss_rps_cfg(struc + nss_warning("%px: nss_tx error setting rps\n", nss_ctx); + + up(&nss_rps_cfg_pvt.sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + /* +@@ -261,7 +261,7 @@ static nss_tx_status_t nss_rps_cfg(struc + if (ret == 0) { + nss_warning("%px: Waiting for ack timed out\n", nss_ctx); + up(&nss_rps_cfg_pvt.sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + /* +@@ -271,11 +271,11 @@ static nss_tx_status_t nss_rps_cfg(struc + */ + if (NSS_FAILURE == nss_rps_cfg_pvt.response) { + up(&nss_rps_cfg_pvt.sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + up(&nss_rps_cfg_pvt.sem); +- return NSS_SUCCESS; ++ return NSS_TX_SUCCESS; + } + + #ifdef NSS_DRV_IPV4_ENABLE +@@ -301,11 +301,11 @@ static nss_tx_status_t nss_rps_ipv4_hash + nss_warning("%px: nss_tx error setting rps\n", nss_ctx); + + up(&nss_rps_cfg_pvt.sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + up(&nss_rps_cfg_pvt.sem); +- return NSS_SUCCESS; ++ return NSS_TX_SUCCESS; + } + #endif + +@@ -332,11 +332,11 @@ static nss_tx_status_t nss_rps_ipv6_hash + nss_warning("%px: nss_tx error setting rps\n", nss_ctx); + + up(&nss_rps_cfg_pvt.sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + up(&nss_rps_cfg_pvt.sem); +- return NSS_SUCCESS; ++ return NSS_TX_SUCCESS; + } + #endif + +@@ -372,7 +372,7 @@ static nss_tx_status_t nss_rps_pri_map_c + nss_warning("%px: nss_tx error setting rps\n", nss_ctx); + + up(&nss_rps_cfg_pvt.sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + /* +@@ -382,7 +382,7 @@ static nss_tx_status_t nss_rps_pri_map_c + if (ret == 0) { + nss_warning("%px: Waiting for ack timed out\n", nss_ctx); + up(&nss_rps_cfg_pvt.sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + /* +@@ -392,11 +392,11 @@ static nss_tx_status_t nss_rps_pri_map_c + */ + if (NSS_FAILURE == nss_rps_cfg_pvt.response) { + up(&nss_rps_cfg_pvt.sem); +- return NSS_FAILURE; ++ return NSS_TX_FAILURE; + } + + up(&nss_rps_cfg_pvt.sem); +- return NSS_SUCCESS; ++ return NSS_TX_SUCCESS; + } + + /* +@@ -574,33 +574,6 @@ static struct ctl_table nss_rps_table[] + { } + }; + +-static struct ctl_table nss_rps_dir[] = { +- { +- .procname = "rps", +- .mode = 0555, +- .child = nss_rps_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_rps_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_rps_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_rps_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_rps_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_rps_header; + + /* +@@ -637,7 +610,7 @@ void nss_rps_register_sysctl(void) + /* + * Register sysctl table. + */ +- nss_rps_header = register_sysctl_table(nss_rps_root); ++ nss_rps_header = register_sysctl("dev/nss/rps", nss_rps_table); + } + + /* +--- a/nss_stats.c ++++ b/nss_stats.c +@@ -88,32 +88,6 @@ static struct ctl_table nss_stats_table[ + { } + }; + +-static struct ctl_table nss_stats_dir[] = { +- { +- .procname = "stats", +- .mode = 0555, +- .child = nss_stats_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_stats_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_stats_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_stats_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_stats_root_dir, +- }, +- { } +-}; + static struct ctl_table_header *nss_stats_header; + + /* +@@ -125,7 +99,7 @@ void nss_stats_register_sysctl(void) + /* + * Register sysctl table. + */ +- nss_stats_header = register_sysctl_table(nss_stats_root); ++ nss_stats_header = register_sysctl("dev/nss/stats", nss_stats_table); + } + + /* +--- a/nss_c2c_tx.c ++++ b/nss_c2c_tx.c +@@ -334,33 +334,6 @@ static struct ctl_table nss_c2c_tx_table + { } + }; + +-static struct ctl_table nss_c2c_tx_dir[] = { +- { +- .procname = "c2c_tx", +- .mode = 0555, +- .child = nss_c2c_tx_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_c2c_tx_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_c2c_tx_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_c2c_tx_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_c2c_tx_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_c2c_tx_header; + + /* +@@ -378,7 +351,7 @@ void nss_c2c_tx_register_sysctl(void) + /* + * Register sysctl table. + */ +- nss_c2c_tx_header = register_sysctl_table(nss_c2c_tx_root); ++ nss_c2c_tx_header = register_sysctl("dev/nss/c2c_tx", nss_c2c_tx_table); + } + + /* +--- a/nss_dma.c ++++ b/nss_dma.c +@@ -378,33 +378,6 @@ static struct ctl_table nss_dma_table[] + { } + }; + +-static struct ctl_table nss_dma_dir[] = { +- { +- .procname = "dma", +- .mode = 0555, +- .child = nss_dma_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_dma_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_dma_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_dma_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_dma_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_dma_header; + + /* +@@ -422,7 +395,7 @@ void nss_dma_register_sysctl(void) + /* + * Register sysctl table. + */ +- nss_dma_header = register_sysctl_table(nss_dma_root); ++ nss_dma_header = register_sysctl("dev/nss/dma", nss_dma_table); + } + + /* +--- a/nss_ipv4.c ++++ b/nss_ipv4.c +@@ -712,33 +712,6 @@ static struct ctl_table nss_ipv4_table[] + { } + }; + +-static struct ctl_table nss_ipv4_dir[] = { +- { +- .procname = "ipv4cfg", +- .mode = 0555, +- .child = nss_ipv4_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_ipv4_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_ipv4_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_ipv4_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_ipv4_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_ipv4_header; + + /* +@@ -753,7 +726,7 @@ void nss_ipv4_register_sysctl(void) + /* + * Register sysctl table. + */ +- nss_ipv4_header = register_sysctl_table(nss_ipv4_root); ++ nss_ipv4_header = register_sysctl("dev/nss/ipv4cfg", nss_ipv4_table); + } + + /* +--- a/nss_ipv6.c ++++ b/nss_ipv6.c +@@ -18,6 +18,7 @@ + * nss_ipv6.c + * NSS IPv6 APIs + */ ++#include "linux/ipv6.h" + #include + #include "nss_dscp_map.h" + #include "nss_ipv6_stats.h" +@@ -377,7 +378,7 @@ EXPORT_SYMBOL(nss_ipv6_get_mgr); + * nss_ipv6_register_handler() + * Register our handler to receive messages for this interface + */ +-void nss_ipv6_register_handler() ++void nss_ipv6_register_handler(void) + { + struct nss_ctx_instance *nss_ctx = nss_ipv6_get_mgr(); + +@@ -706,33 +707,6 @@ static struct ctl_table nss_ipv6_table[] + { } + }; + +-static struct ctl_table nss_ipv6_dir[] = { +- { +- .procname = "ipv6cfg", +- .mode = 0555, +- .child = nss_ipv6_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_ipv6_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_ipv6_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_ipv6_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_ipv6_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_ipv6_header; + + /* +@@ -747,7 +721,7 @@ void nss_ipv6_register_sysctl(void) + /* + * Register sysctl table. + */ +- nss_ipv6_header = register_sysctl_table(nss_ipv6_root); ++ nss_ipv6_header = register_sysctl("dev/nss/ipv6cfg", nss_ipv6_table); + } + + /* +--- a/nss_pm.c ++++ b/nss_pm.c +@@ -323,6 +323,7 @@ error: + nss_pm_interface_status_t nss_pm_set_perf_level(void *handle, nss_pm_perf_level_t lvl) + { + #if ((NSS_DT_SUPPORT == 1) && (NSS_FREQ_SCALE_SUPPORT == 1)) ++#if !defined(NSS_HAL_IPQ807x_SUPPORT) + nss_freq_scales_t index; + + switch (lvl) { +@@ -335,10 +336,9 @@ nss_pm_interface_status_t nss_pm_set_per + break; + + default: +- index = NSS_PM_PERF_LEVEL_IDLE; ++ index = NSS_FREQ_MID_SCALE; + } + +-#if !defined(NSS_HAL_IPQ807x_SUPPORT) + nss_freq_sched_change(index, false); + #endif + +--- a/nss_coredump.c ++++ b/nss_coredump.c +@@ -25,10 +25,11 @@ + #include "nss_hal.h" + #include "nss_log.h" + #include +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 6, 0)) + #include /* for panic_notifier_list */ + #else +-#include ++#include /* for panic_notifier_list */ + #endif + #include /* for time */ + #include "nss_tx_rx_common.h" diff --git a/qca-nss-drv/patches-11.4/0016-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch b/qca-nss-drv/patches-11.4/0016-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch new file mode 100644 index 0000000..9e6b912 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0016-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch @@ -0,0 +1,558 @@ +From e6814c47d22ee5133a71016375239f87ea265794 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Tue, 5 Apr 2022 15:38:18 +0200 +Subject: [PATCH 4/4] nss-drv: rework NSS_CORE_DMA_CACHE_MAINT ops + +Rework NSS_CORE_DMA_CACHE_MAINT ops to use standard dma sync ops instead +of using the direct arch function. This permit to skip any hack/patch +needed for nss-drv to correctly compile on upstream kernel. + +We drop any NSS_CORE_DMA_CACHE_MAINT use in nss_core and we correctly +use the dma_sync_single_for_device we correctly dma addr using the new +DMA helper. +We drop sync for IOREMAP addr and we just leave a memory block. +We hope the nss_profiler is correctly ported. +We finally drop the NSS_CORE_DMA_CACHE_MAINT jus in case someone wants +to use it. + +Signed-off-by: Christian Marangi +--- + nss_core.c | 136 +++++++++++++++++++++++++--------- + nss_core.h | 41 +++++----- + nss_hal/ipq806x/nss_hal_pvt.c | 5 +- + nss_hal/ipq807x/nss_hal_pvt.c | 5 +- + nss_meminfo.c | 5 +- + nss_profiler.c | 3 +- + 6 files changed, 127 insertions(+), 68 deletions(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -1426,6 +1426,8 @@ static inline void nss_core_handle_empty + uint32_t count, uint32_t hlos_index, + uint16_t mask) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ + while (count) { + /* + * Since we only return the primary skb, we have no way to unmap +@@ -1479,7 +1481,9 @@ next: + n2h_desc_ring->hlos_index = hlos_index; + if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, ++ n2h_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + } + +@@ -1501,6 +1505,7 @@ static int32_t nss_core_handle_cause_que + struct nss_ctx_instance *nss_ctx = int_ctx->nss_ctx; + struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct nss_if_mem_map *if_map = mem_ctx->if_map; ++ int dma_size; + + qid = nss_core_cause_to_queue(cause); + +@@ -1512,7 +1517,8 @@ static int32_t nss_core_handle_cause_que + n2h_desc_ring = &nss_ctx->n2h_desc_ring[qid]; + desc_if = &n2h_desc_ring->desc_ring; + desc_ring = desc_if->desc; +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_ctx->dev, n2h_nss_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + nss_index = if_map->n2h_nss_index[qid]; + +@@ -1541,13 +1547,23 @@ static int32_t nss_core_handle_cause_que + start = hlos_index; + end = (hlos_index + count) & mask; + if (end > start) { +- dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor)); ++ dma_size = sizeof(struct n2h_descriptor) * (end - start + 1); ++ ++ dma_sync_single_for_cpu(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, start), ++ dma_size, DMA_FROM_DEVICE); + } else { + /* + * We have wrapped around + */ +- dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct n2h_descriptor)); +- dmac_inv_range((void *)&desc_ring[0], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor)); ++ dma_size = sizeof(struct n2h_descriptor) * (mask - start + 1); ++ ++ dma_sync_single_for_cpu(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, start), ++ dma_size, DMA_FROM_DEVICE); ++ ++ dma_size = sizeof(struct n2h_descriptor) * (end + 1); ++ ++ dma_sync_single_for_cpu(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, 0), dma_size, ++ DMA_FROM_DEVICE); + } + + /* +@@ -1676,7 +1692,8 @@ next: + n2h_desc_ring->hlos_index = hlos_index; + if_map->n2h_hlos_index[qid] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, n2h_hlos_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + return count; +@@ -1688,11 +1705,12 @@ next: + */ + static void nss_core_init_nss(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct nss_top_instance *nss_top; + int ret; + int i; + +- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(*if_map), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(*if_map), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + + /* +@@ -1768,6 +1786,7 @@ static void nss_core_alloc_paged_buffers + uint16_t count, int16_t mask, int32_t hlos_index, uint32_t alloc_fail_count, + uint32_t buffer_type, uint32_t buffer_queue, uint32_t stats_index) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct sk_buff *nbuf; + struct page *npage; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[buffer_queue]; +@@ -1837,7 +1856,9 @@ static void nss_core_alloc_paged_buffers + /* + * Flush the descriptor + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, buffer_queue, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + hlos_index = (hlos_index + 1) & (mask); + count--; +@@ -1851,7 +1872,8 @@ static void nss_core_alloc_paged_buffers + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[buffer_queue] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[buffer_queue], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, buffer_queue), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + NSS_PKT_STATS_INC(&nss_top->stats_drv[stats_index]); +@@ -1864,7 +1886,7 @@ static void nss_core_alloc_paged_buffers + static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map, + int jumbo_mru, uint16_t count, int16_t mask, int32_t hlos_index) + { +- ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct sk_buff *nbuf; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; + struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring; +@@ -1911,7 +1933,9 @@ static void nss_core_alloc_jumbo_mru_buf + /* + * Flush the descriptor + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + hlos_index = (hlos_index + 1) & (mask); + count--; +@@ -1925,7 +1949,8 @@ static void nss_core_alloc_jumbo_mru_buf + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]); +@@ -1938,6 +1963,7 @@ static void nss_core_alloc_jumbo_mru_buf + static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map, + uint16_t max_buf_size, uint16_t count, int16_t mask, int32_t hlos_index) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; + struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring; + struct h2n_descriptor *desc_ring = desc_if->desc; +@@ -1945,6 +1971,7 @@ static void nss_core_alloc_max_avail_siz + uint16_t payload_len = max_buf_size + NET_SKB_PAD; + uint16_t start = hlos_index; + uint16_t prev_hlos_index; ++ int dma_size; + + while (count) { + dma_addr_t buffer; +@@ -1997,13 +2024,26 @@ static void nss_core_alloc_max_avail_siz + * Flush the descriptors, including the descriptor at prev_hlos_index. + */ + if (prev_hlos_index > start) { +- dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor)); ++ dma_size = sizeof(struct h2n_descriptor) * (prev_hlos_index - start + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, start), ++ dma_size, DMA_TO_DEVICE); + } else { + /* + * We have wrapped around + */ +- dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct h2n_descriptor)); +- dmac_clean_range((void *)&desc_ring[0], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor)); ++ dma_size = sizeof(struct h2n_descriptor) * (mask - start + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, start), ++ dma_size, DMA_TO_DEVICE); ++ ++ dma_size = sizeof(struct h2n_descriptor) * (prev_hlos_index + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, 0), ++ dma_size, DMA_TO_DEVICE); + } + + /* +@@ -2014,7 +2054,8 @@ static void nss_core_alloc_max_avail_siz + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]); +@@ -2027,6 +2068,7 @@ static void nss_core_alloc_max_avail_siz + static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss_ctx, + struct nss_if_mem_map *if_map, uint16_t max_buf_size) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + uint16_t count, size, mask; + int32_t nss_index, hlos_index; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; +@@ -2037,7 +2079,8 @@ static inline void nss_core_handle_empty + /* + * Check how many empty buffers could be filled in queue + */ +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; + +@@ -2082,6 +2125,7 @@ static inline void nss_core_handle_empty + static inline void nss_core_handle_paged_empty_buffer_sos(struct nss_ctx_instance *nss_ctx, + struct nss_if_mem_map *if_map, uint16_t max_buf_size) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + uint16_t count, size, mask; + int32_t nss_index, hlos_index; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE]; +@@ -2089,7 +2133,8 @@ static inline void nss_core_handle_paged + /* + * Check how many empty buffers could be filled in queue + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE]; + +@@ -2667,9 +2712,11 @@ void nss_skb_reuse(struct sk_buff *nbuf) + * Sends one skb to NSS FW + */ + static inline int32_t nss_core_send_buffer_simple_skb(struct nss_ctx_instance *nss_ctx, +- struct h2n_desc_if_instance *desc_if, uint32_t if_num, +- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) ++ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, ++ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ struct nss_if_mem_map *if_map = mem_ctx->if_map; + struct h2n_descriptor *desc_ring = desc_if->desc; + struct h2n_descriptor *desc; + uint16_t bit_flags; +@@ -2723,7 +2770,8 @@ static inline int32_t nss_core_send_buff + (nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len, + sz, (uint32_t)nbuf->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + /* + * We are done using the skb fields and can reuse it now +@@ -2747,7 +2795,8 @@ no_reuse: + (nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len, + (uint16_t)skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_SIMPLE]); + return 1; +@@ -2761,9 +2810,11 @@ no_reuse: + * Used to differentiate from FRAGLIST + */ + static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss_ctx, +- struct h2n_desc_if_instance *desc_if, uint32_t if_num, +- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) ++ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, ++ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ struct nss_if_mem_map *if_map = mem_ctx->if_map; + struct h2n_descriptor *desc_ring = desc_if->desc; + struct h2n_descriptor *desc; + const skb_frag_t *frag; +@@ -2803,7 +2854,8 @@ static inline int32_t nss_core_send_buff + (nss_ptr_t)NULL, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len, + skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + /* + * Now handle rest of the fragments. +@@ -2827,7 +2879,8 @@ static inline int32_t nss_core_send_buff + (nss_ptr_t)NULL, 0, skb_frag_size(frag), skb_frag_size(frag), + nbuf->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + } + + /* +@@ -2843,7 +2896,8 @@ static inline int32_t nss_core_send_buff + desc->bit_flags &= ~(H2N_BIT_FLAG_DISCARD); + desc->opaque = (nss_ptr_t)nbuf; + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_NR_FRAGS]); + return i+1; +@@ -2857,9 +2911,11 @@ static inline int32_t nss_core_send_buff + * Used to differentiate from FRAGS + */ + static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss_ctx, +- struct h2n_desc_if_instance *desc_if, uint32_t if_num, +- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) ++ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, ++ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ struct nss_if_mem_map *if_map = mem_ctx->if_map; + struct h2n_descriptor *desc_ring = desc_if->desc; + struct h2n_descriptor *desc; + dma_addr_t buffer; +@@ -2898,7 +2954,8 @@ static inline int32_t nss_core_send_buff + (nss_ptr_t)nbuf, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len, + skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + /* + * Walk the frag_list in nbuf +@@ -2951,7 +3008,8 @@ static inline int32_t nss_core_send_buff + (nss_ptr_t)iter, iter->data - iter->head, iter->len - iter->data_len, + skb_end_offset(iter), iter->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + i++; + } +@@ -2970,7 +3028,8 @@ static inline int32_t nss_core_send_buff + * Update bit flag for last descriptor. + */ + desc->bit_flags |= H2N_BIT_FLAG_LAST_SEGMENT; +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_FRAGLIST]); + return i+1; +@@ -3049,8 +3108,10 @@ int32_t nss_core_send_buffer(struct nss_ + * We need to work out if there's sufficent space in our transmit descriptor + * ring to place all the segments of a nbuf. + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); ++ + nss_index = if_map->h2n_nss_index[qid]; + h2n_desc_ring->nss_index_local = nss_index; + count = ((nss_index - hlos_index - 1) + size) & (mask); +@@ -3115,13 +3176,13 @@ int32_t nss_core_send_buffer(struct nss_ + count = 0; + if (likely((segments == 0) || is_bounce)) { + count = nss_core_send_buffer_simple_skb(nss_ctx, desc_if, if_num, +- nbuf, hlos_index, flags, buffer_type, mss); ++ nbuf, qid, hlos_index, flags, buffer_type, mss); + } else if (skb_has_frag_list(nbuf)) { + count = nss_core_send_buffer_fraglist(nss_ctx, desc_if, if_num, +- nbuf, hlos_index, flags, buffer_type, mss); ++ nbuf, qid, hlos_index, flags, buffer_type, mss); + } else { + count = nss_core_send_buffer_nr_frags(nss_ctx, desc_if, if_num, +- nbuf, hlos_index, flags, buffer_type, mss); ++ nbuf, qid, hlos_index, flags, buffer_type, mss); + } + + if (unlikely(count <= 0)) { +@@ -3145,7 +3206,8 @@ int32_t nss_core_send_buffer(struct nss_ + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[qid] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + #ifdef CONFIG_DEBUG_KMEMLEAK +--- a/nss_core.h ++++ b/nss_core.h +@@ -100,31 +100,30 @@ + #endif + + /* +- * Cache operation ++ * DMA Offset helper + */ +-#define NSS_CORE_DSB() dsb(sy) +-#define NSS_CORE_DMA_CACHE_MAINT(start, size, dir) nss_core_dma_cache_maint(start, size, dir) ++#define n2h_desc_index_offset(_index) sizeof(struct n2h_descriptor) * (_index) ++#define h2n_desc_index_offset(_index) sizeof(struct h2n_descriptor) * (_index) ++ ++#define n2h_desc_index_to_dma(_if_map_addr, _qid, _index) (_if_map_addr)->n2h_desc_if[(_qid)].desc_addr + n2h_desc_index_offset(_index) ++#define h2n_desc_index_to_dma(_if_map_addr, _qid, _index) (_if_map_addr)->h2n_desc_if[(_qid)].desc_addr + h2n_desc_index_offset(_index) ++ ++#define h2n_nss_index_offset offsetof(struct nss_if_mem_map, h2n_nss_index) ++#define n2h_nss_index_offset offsetof(struct nss_if_mem_map, n2h_nss_index) ++#define h2n_hlos_index_offset offsetof(struct nss_if_mem_map, h2n_hlos_index) ++#define n2h_hlos_index_offset offsetof(struct nss_if_mem_map, n2h_hlos_index) ++ ++#define h2n_nss_index_to_dma(_if_map_addr, _index) (_if_map_addr) + h2n_nss_index_offset + (sizeof(uint32_t) * (_index)) ++#define n2h_nss_index_to_dma(_if_map_addr, _index) (_if_map_addr) + n2h_nss_index_offset + (sizeof(uint32_t) * (_index)) ++#define h2n_hlos_index_to_dma(_if_map_addr, _index) (_if_map_addr) + h2n_hlos_index_offset + (sizeof(uint32_t) * (_index)) ++#define n2h_hlos_index_to_dma(_if_map_addr, _index) (_if_map_addr) + n2h_hlos_index_offset + (sizeof(uint32_t) * (_index)) + + /* +- * nss_core_dma_cache_maint() +- * Perform the appropriate cache op based on direction ++ * Cache operation + */ +-static inline void nss_core_dma_cache_maint(void *start, uint32_t size, int direction) +-{ +- switch (direction) { +- case DMA_FROM_DEVICE:/* invalidate only */ +- dmac_inv_range(start, start + size); +- break; +- case DMA_TO_DEVICE:/* writeback only */ +- dmac_clean_range(start, start + size); +- break; +- case DMA_BIDIRECTIONAL:/* writeback and invalidate */ +- dmac_flush_range(start, start + size); +- break; +- default: +- BUG(); +- } +-} ++#define NSS_CORE_DSB() dsb(sy) ++#define NSS_CORE_DMA_CACHE_MAINT(dev, start, size, dir) BUILD_BUG_ON_MSG(1, \ ++ "NSS_CORE_DMA_CACHE_MAINT is deprecated. Fix the code to use correct dma_sync_* API") + + #define NSS_DEVICE_IF_START NSS_PHYSICAL_IF_START + +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -477,10 +477,9 @@ static struct nss_platform_data *__nss_h + /* + * Clear TCM memory used by this core + */ +- for (i = 0; i < resource_size(&res_vphys) ; i += 4) { ++ for (i = 0; i < resource_size(&res_vphys) ; i += 4) + nss_write_32(npd->vmap, i, 0); +- NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE); +- } ++ + NSS_CORE_DSB(); + + /* +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -256,10 +256,9 @@ static struct nss_platform_data *__nss_h + /* + * Clear TCM memory used by this core + */ +- for (i = 0; i < resource_size(&res_vphys) ; i += 4) { ++ for (i = 0; i < resource_size(&res_vphys) ; i += 4) + nss_write_32(npd->vmap, i, 0); +- NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE); +- } ++ + NSS_CORE_DSB(); + + /* +--- a/nss_meminfo.c ++++ b/nss_meminfo.c +@@ -415,7 +415,6 @@ static bool nss_meminfo_init_block_lists + /* + * Flush the updated meminfo request. + */ +- NSS_CORE_DMA_CACHE_MAINT(r, sizeof(struct nss_meminfo_request), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + /* +@@ -546,7 +545,7 @@ static bool nss_meminfo_configure_n2h_h2 + * Bring a fresh copy of if_map from memory in order to read it correctly. + */ + if_map = mem_ctx->if_map; +- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + + if_map->n2h_rings = NSS_N2H_RING_COUNT; +@@ -584,7 +583,7 @@ static bool nss_meminfo_configure_n2h_h2 + /* + * Flush the updated nss_if_mem_map. + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + return true; +--- a/nss_profiler.c ++++ b/nss_profiler.c +@@ -209,11 +209,12 @@ EXPORT_SYMBOL(nss_profile_dma_deregister + struct nss_profile_sdma_ctrl *nss_profile_dma_get_ctrl(struct nss_ctx_instance *nss_ctx) + { + struct nss_profile_sdma_ctrl *ctrl = nss_ctx->meminfo_ctx.sdma_ctrl; ++ int size = offsetof(struct nss_profile_sdma_ctrl, cidx); + if (!ctrl) { + return ctrl; + } + +- dmac_inv_range(ctrl, &ctrl->cidx); ++ dma_sync_single_for_cpu(nss_ctx->dev, (dma_addr_t) ctrl, size, DMA_FROM_DEVICE); + dsb(sy); + return ctrl; + } diff --git a/qca-nss-drv/patches-11.4/0017-nss-drv-remove-gmac-stat.patch b/qca-nss-drv/patches-11.4/0017-nss-drv-remove-gmac-stat.patch new file mode 100644 index 0000000..30b7d9a --- /dev/null +++ b/qca-nss-drv/patches-11.4/0017-nss-drv-remove-gmac-stat.patch @@ -0,0 +1,39 @@ +--- a/nss_stats.c ++++ b/nss_stats.c +@@ -375,7 +375,7 @@ void nss_stats_create_dentry(char *name, + /* + * gmac_stats_ops + */ +-NSS_STATS_DECLARE_FILE_OPERATIONS(gmac); ++// NSS_STATS_DECLARE_FILE_OPERATIONS(gmac); + + /* + * wt_stats_ops +@@ -430,7 +430,7 @@ void nss_stats_init(void) + /* + * gmac_stats + */ +- nss_stats_create_dentry("gmac", &nss_gmac_stats_ops); ++ // nss_stats_create_dentry("gmac", &nss_gmac_stats_ops); + + /* + * Per-project stats +--- a/Makefile ++++ b/Makefile +@@ -40,7 +40,6 @@ qca-nss-drv-objs += nss_hal/nss_hal.o + + ifneq "$(NSS_DRV_POINT_OFFLOAD)" "y" + qca-nss-drv-objs += \ +- nss_gmac_stats.o \ + nss_if.o \ + nss_if_log.o \ + nss_phys_if.o \ +@@ -381,7 +380,7 @@ endif + ifeq ($(SoC),$(filter $(SoC),ipq806x)) + ccflags-y += -DNSS_DRV_IPV4_ENABLE -DNSS_DRV_IPV6_ENABLE + qca-nss-drv-objs += nss_data_plane/nss_data_plane_gmac.o \ +- nss_hal/ipq806x/nss_hal_pvt.o ++ nss_hal/ipq806x/nss_hal_pvt.o nss_gmac_stats.o + + ifneq "$(NSS_DRV_C2C_ENABLE)" "n" + ccflags-y += -DNSS_DRV_C2C_ENABLE diff --git a/qca-nss-drv/patches-11.4/0017-nss-drv-wifili-add-exported-symbols.patch b/qca-nss-drv/patches-11.4/0017-nss-drv-wifili-add-exported-symbols.patch new file mode 100644 index 0000000..b750fc3 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0017-nss-drv-wifili-add-exported-symbols.patch @@ -0,0 +1,18 @@ +--- a/exports/nss_wifili_if.h ++++ b/exports/nss_wifili_if.h +@@ -683,6 +683,15 @@ struct nss_wifili_stats_notification { + struct nss_wifili_stats stats; /**< Wifili statistics. */ + }; + ++/** ++ * nss_wifili_get_context ++ * Gets the Wi-Fi Li context used in NSS GRE transmit. ++ * ++ * @return ++ * Pointer to the NSS core context. ++ */ ++extern struct nss_ctx_instance *nss_wifili_get_context(void); ++ + #ifdef __KERNEL__ /* only kernel will use. */ + + /** diff --git a/qca-nss-drv/patches-11.4/0018-nss-drv-more-uniform-kernel-msg.patch b/qca-nss-drv/patches-11.4/0018-nss-drv-more-uniform-kernel-msg.patch new file mode 100644 index 0000000..c0d9066 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0018-nss-drv-more-uniform-kernel-msg.patch @@ -0,0 +1,88 @@ +--- a/nss_n2h.c ++++ b/nss_n2h.c +@@ -1269,11 +1269,11 @@ static int nss_n2h_mitigationcfg_core0_h + } + + if (!nss_n2h_core0_mitigation_cfg) { +- printk(KERN_INFO "Disabling NSS MITIGATION\n"); ++ dev_info(nss_ctx->dev, "Disabling NSS MITIGATION\n"); + nss_n2h_mitigation_cfg(nss_ctx, 0, NSS_CORE_0); + return 0; + } +- printk(KERN_INFO "Invalid input value.Valid value is 0, Runtime re-enabling not supported\n"); ++ dev_info(nss_ctx->dev, "Invalid input value.Valid value is 0, Runtime re-enabling not supported\n"); + return -EINVAL; + } + +@@ -1300,11 +1300,11 @@ static int nss_n2h_mitigationcfg_core1_h + } + + if (!nss_n2h_core1_mitigation_cfg) { +- printk(KERN_INFO "Disabling NSS MITIGATION\n"); ++ dev_info(nss_ctx->dev, "Disabling NSS MITIGATION\n"); + nss_n2h_mitigation_cfg(nss_ctx, 0, NSS_CORE_1); + return 0; + } +- printk(KERN_INFO "Invalid input value.Valid value is 0, Runtime re-enabling not supported\n"); ++ dev_info(nss_ctx->dev, "Invalid input value.Valid value is 0, Runtime re-enabling not supported\n"); + return -EINVAL; + } + +@@ -1336,14 +1336,14 @@ static int nss_n2h_buf_cfg_core0_handler + } + + if ((nss_n2h_core0_add_buf_pool_size >= 1) && (nss_n2h_core0_add_buf_pool_size <= NSS_N2H_MAX_BUF_POOL_SIZE)) { +- printk(KERN_INFO "configuring additional NSS pbufs\n"); ++ dev_info(nss_ctx->dev, "Configuring additional NSS pbufs\n"); + ret = nss_n2h_buf_pool_cfg(nss_ctx, nss_n2h_core0_add_buf_pool_size, NSS_CORE_0); + nss_n2h_core0_add_buf_pool_size = nss_ctx->buf_sz_allocated; +- printk(KERN_INFO "additional pbufs of size %d got added to NSS\n", nss_ctx->buf_sz_allocated); ++ dev_info(nss_ctx->dev, "Additional pbufs of size %d got added to NSS\n", nss_ctx->buf_sz_allocated); + return ret; + } + +- printk(KERN_INFO "Invalid input value. should be greater than 1 and less than %d\n", NSS_N2H_MAX_BUF_POOL_SIZE); ++ dev_info(nss_ctx->dev, "Invalid input value. should be greater than 1 and less than %d\n", NSS_N2H_MAX_BUF_POOL_SIZE); + return -EINVAL; + } + +@@ -1375,14 +1375,14 @@ static int nss_n2h_buf_cfg_core1_handler + } + + if ((nss_n2h_core1_add_buf_pool_size >= 1) && (nss_n2h_core1_add_buf_pool_size <= NSS_N2H_MAX_BUF_POOL_SIZE)) { +- printk(KERN_INFO "configuring additional NSS pbufs\n"); ++ dev_info(nss_ctx->dev, "Configuring additional NSS pbufs\n"); + ret = nss_n2h_buf_pool_cfg(nss_ctx, nss_n2h_core1_add_buf_pool_size, NSS_CORE_1); + nss_n2h_core1_add_buf_pool_size = nss_ctx->buf_sz_allocated; +- printk(KERN_INFO "additional pbufs of size %d got added to NSS\n", nss_ctx->buf_sz_allocated); ++ dev_info(nss_ctx->dev, "Additional pbufs of size %d got added to NSS\n", nss_ctx->buf_sz_allocated); + return ret; + } + +- printk(KERN_INFO "Invalid input value. should be greater than 1 and less than %d\n", NSS_N2H_MAX_BUF_POOL_SIZE); ++ dev_info(nss_ctx->dev, "Invalid input value. should be greater than 1 and less than %d\n", NSS_N2H_MAX_BUF_POOL_SIZE); + return -EINVAL; + } + +--- a/nss_core.c ++++ b/nss_core.c +@@ -2222,7 +2222,7 @@ static void nss_core_handle_cause_nonque + nss_core_init_nss(nss_ctx, if_map); + nss_send_ddr_info(nss_ctx); + +- nss_info_always("%px: nss core %d booted successfully\n", nss_ctx, nss_ctx->id); ++ dev_info(nss_ctx->dev, "NSS core %d booted successfully\n", nss_ctx->id); + nss_top = nss_ctx->nss_top; + + #ifdef NSS_DRV_C2C_ENABLE +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -81,7 +81,7 @@ int nss_hal_firmware_load(struct nss_ctx + return rc; + } + +- nss_info("nss_driver - fw of size %d bytes copied to load addr: %x, nss_id : %d\n", (int)nss_fw->size, npd->load_addr, nss_dev->id); ++ dev_info(&nss_dev->dev, "fw of size %d bytes copied to addr: %x, nss_id: %d", (int)nss_fw->size, npd->load_addr, nss_ctx->id); + memcpy_toio(load_mem, nss_fw->data, nss_fw->size); + release_firmware(nss_fw); + iounmap(load_mem); diff --git a/qca-nss-drv/patches-11.4/0019-nss-drv-mac80211-disable-signal-redirection.patch b/qca-nss-drv/patches-11.4/0019-nss-drv-mac80211-disable-signal-redirection.patch new file mode 100644 index 0000000..62e1fe4 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0019-nss-drv-mac80211-disable-signal-redirection.patch @@ -0,0 +1,11 @@ +--- a/nss_virt_if.c ++++ b/nss_virt_if.c +@@ -450,6 +450,8 @@ EXPORT_SYMBOL(nss_virt_if_create_sync_ne + */ + struct nss_virt_if_handle *nss_virt_if_create_sync(struct net_device *netdev) + { ++ if (!nss_ctl_redirect) ++ return NULL; + /* + * NSS_N2H_INTERFACE is the nexthop of the dynamic interface which is created for handling the + * n2h traffic. diff --git a/qca-nss-drv/patches-11.4/0019-nss-drv-reorg-irq-logic.patch b/qca-nss-drv/patches-11.4/0019-nss-drv-reorg-irq-logic.patch new file mode 100644 index 0000000..1c58e3b --- /dev/null +++ b/qca-nss-drv/patches-11.4/0019-nss-drv-reorg-irq-logic.patch @@ -0,0 +1,353 @@ +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -64,6 +64,20 @@ + #define NSS_NC_AXI_CLK "nss-nc-axi-clk" + + /* ++ * N2H interrupts ++ */ ++#define NSS_IRQ_NAME_EMPTY_BUF_SOS "nss_empty_buf_sos" ++#define NSS_IRQ_NAME_EMPTY_BUF_QUEUE "nss_empty_buf_queue" ++#define NSS_IRQ_NAME_TX_UNBLOCK "nss-tx-unblock" ++#define NSS_IRQ_NAME_QUEUE0 "nss_queue0" ++#define NSS_IRQ_NAME_QUEUE1 "nss_queue1" ++#define NSS_IRQ_NAME_QUEUE2 "nss_queue2" ++#define NSS_IRQ_NAME_QUEUE3 "nss_queue3" ++#define NSS_IRQ_NAME_COREDUMP_COMPLETE "nss_coredump_complete" ++#define NSS_IRQ_NAME_PAGED_EMPTY_BUF_SOS "nss_paged_empty_buf_sos" ++#define NSS_IRQ_NAME_PROFILE_DMA "nss_profile_dma" ++ ++/* + * Voltage values + */ + #define NOMINAL_VOLTAGE 1 +@@ -651,74 +665,96 @@ static void __nss_hal_send_interrupt(str + static int __nss_hal_request_irq(struct nss_ctx_instance *nss_ctx, struct nss_platform_data *npd, int irq_num) + { + struct int_ctx_instance *int_ctx = &nss_ctx->int_ctx[irq_num]; ++ uint32_t cause, napi_wgt; + int err = -1, irq = npd->irq[irq_num]; ++ int (*napi_poll_cb)(struct napi_struct *, int) = NULL; ++ const char *irq_name; + + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_sos", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_queue", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_TX_UNBLOCKED; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss-tx-unblock", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_0; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue0", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1) { +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_1; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue1", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2) { +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_2; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue2", int_ctx); +- } ++ switch (irq_num) { ++ case NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS: ++ napi_poll_cb = nss_core_handle_napi_non_queue; ++ napi_wgt = NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS; ++ irq_name = NSS_IRQ_NAME_EMPTY_BUF_SOS; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE; ++ irq_name = NSS_IRQ_NAME_EMPTY_BUF_QUEUE; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED: ++ napi_poll_cb = nss_core_handle_napi_non_queue; ++ napi_wgt = NSS_TX_UNBLOCKED_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_TX_UNBLOCKED; ++ irq_name = NSS_IRQ_NAME_TX_UNBLOCK; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_0; ++ irq_name = NSS_IRQ_NAME_QUEUE0; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_1; ++ irq_name = NSS_IRQ_NAME_QUEUE1; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_2; ++ irq_name = NSS_IRQ_NAME_QUEUE2; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_3; ++ irq_name = NSS_IRQ_NAME_QUEUE3; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE: ++ napi_poll_cb = nss_core_handle_napi_emergency; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_COREDUMP_COMPLETE; ++ irq_name = NSS_IRQ_NAME_COREDUMP_COMPLETE; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS: ++ napi_poll_cb = nss_core_handle_napi_non_queue; ++ napi_wgt = NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS; ++ irq_name = NSS_IRQ_NAME_PAGED_EMPTY_BUF_SOS; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA: ++ napi_poll_cb = nss_core_handle_napi_sdma; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_PROFILE_DMA; ++ irq_name = NSS_IRQ_NAME_PROFILE_DMA; ++ break; + +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3) { +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_3; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue3", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE) { +- int_ctx->cause = NSS_N2H_INTR_COREDUMP_COMPLETE; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_coredump_complete", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_paged_empty_buf_sos", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA) { +- int_ctx->cause = NSS_N2H_INTR_PROFILE_DMA; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_profile_dma", int_ctx); ++ default: ++ nss_warning("%px: nss%d: unsupported irq# %d\n", nss_ctx, nss_ctx->id, irq_num); ++ return err; + } + ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, napi_poll_cb, napi_wgt); ++ int_ctx->cause = cause; ++ err = request_irq(irq, nss_hal_handle_irq, 0, irq_name, int_ctx); + if (err) { ++ nss_warning("%px: nss%d: request_irq failed for irq# %d\n", nss_ctx, nss_ctx->id, irq_num); + return err; + } +- + int_ctx->irq = irq; + return 0; + } +--- a/nss_hal/ipq60xx/nss_hal_pvt.c ++++ b/nss_hal/ipq60xx/nss_hal_pvt.c +@@ -63,6 +63,20 @@ + #define NSS_UTCM_CLK "nss-utcm-clk" + + /* ++ * N2H interrupts ++ */ ++#define NSS_IRQ_NAME_EMPTY_BUF_SOS "nss_empty_buf_sos" ++#define NSS_IRQ_NAME_EMPTY_BUF_QUEUE "nss_empty_buf_queue" ++#define NSS_IRQ_NAME_TX_UNBLOCK "nss-tx-unblock" ++#define NSS_IRQ_NAME_QUEUE0 "nss_queue0" ++#define NSS_IRQ_NAME_QUEUE1 "nss_queue1" ++#define NSS_IRQ_NAME_QUEUE2 "nss_queue2" ++#define NSS_IRQ_NAME_QUEUE3 "nss_queue3" ++#define NSS_IRQ_NAME_COREDUMP_COMPLETE "nss_coredump_complete" ++#define NSS_IRQ_NAME_PAGED_EMPTY_BUF_SOS "nss_paged_empty_buf_sos" ++#define NSS_IRQ_NAME_PROFILE_DMA "nss_profile_dma" ++ ++/* + * Voltage values + */ + #define NOMINAL_VOLTAGE 1 +@@ -609,71 +623,94 @@ static void __nss_hal_send_interrupt(str + static int __nss_hal_request_irq(struct nss_ctx_instance *nss_ctx, struct nss_platform_data *npd, int irq_num) + { + struct int_ctx_instance *int_ctx = &nss_ctx->int_ctx[irq_num]; ++ uint32_t cause, napi_wgt; + int err = -1, irq = npd->irq[irq_num]; ++ int (*napi_poll_cb)(struct napi_struct *, int) = NULL; ++ const char *irq_name; + + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_sos", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_queue", int_ctx); +- } ++ switch (irq_num) { ++ case NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS: ++ napi_poll_cb = nss_core_handle_napi_non_queue; ++ napi_wgt = NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS; ++ irq_name = NSS_IRQ_NAME_EMPTY_BUF_SOS; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE; ++ irq_name = NSS_IRQ_NAME_EMPTY_BUF_QUEUE; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED: ++ napi_poll_cb = nss_core_handle_napi_non_queue; ++ napi_wgt = NSS_TX_UNBLOCKED_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_TX_UNBLOCKED; ++ irq_name = NSS_IRQ_NAME_TX_UNBLOCK; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_0; ++ irq_name = NSS_IRQ_NAME_QUEUE0; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_1; ++ irq_name = NSS_IRQ_NAME_QUEUE1; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_2; ++ irq_name = NSS_IRQ_NAME_QUEUE2; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_3; ++ irq_name = NSS_IRQ_NAME_QUEUE3; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE: ++ napi_poll_cb = nss_core_handle_napi_emergency; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_COREDUMP_COMPLETE; ++ irq_name = NSS_IRQ_NAME_COREDUMP_COMPLETE; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS: ++ napi_poll_cb = nss_core_handle_napi_non_queue; ++ napi_wgt = NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS; ++ irq_name = NSS_IRQ_NAME_PAGED_EMPTY_BUF_SOS; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA: ++ napi_poll_cb = nss_core_handle_napi_sdma; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_PROFILE_DMA; ++ irq_name = NSS_IRQ_NAME_PROFILE_DMA; ++ break; + +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_TX_UNBLOCKED; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss-tx-unblock", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_0; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue0", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1) { +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_1; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue1", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2) { +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_2; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue2", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3) { +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_3; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue3", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE) { +- int_ctx->cause = NSS_N2H_INTR_COREDUMP_COMPLETE; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_coredump_complete", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_paged_empty_buf_sos", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA) { +- int_ctx->cause = NSS_N2H_INTR_PROFILE_DMA; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_profile_dma", int_ctx); ++ default: ++ nss_warning("%px: nss%d: unsupported irq# %d\n", nss_ctx, nss_ctx->id, irq_num); ++ return err; + } + ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, napi_poll_cb, napi_wgt); ++ int_ctx->cause = cause; ++ err = request_irq(irq, nss_hal_handle_irq, 0, irq_name, int_ctx); + if (err) { ++ nss_warning("%px: nss%d: request_irq failed for irq# %d\n", nss_ctx, nss_ctx->id, irq_num); + return err; + } + diff --git a/qca-nss-drv/patches-11.4/0022-nss-drv-display-fw-version.patch b/qca-nss-drv/patches-11.4/0022-nss-drv-display-fw-version.patch new file mode 100644 index 0000000..8ad2326 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0022-nss-drv-display-fw-version.patch @@ -0,0 +1,78 @@ +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -43,6 +43,7 @@ + */ + #define NSS_AP0_IMAGE "qca-nss0.bin" + #define NSS_AP1_IMAGE "qca-nss1.bin" ++#define BUFFER_SIZE 8192 + + /* + * File local/Static variables/functions +@@ -50,6 +51,56 @@ + static const struct net_device_ops nss_netdev_ops; + static const struct ethtool_ops nss_ethtool_ops; + ++// Function to search for the byte sequence in the buffer ++static unsigned char *search_sequence(const unsigned char *buffer, ++ size_t buffer_size, ++ const unsigned char *sequence, ++ size_t sequence_size) ++{ ++ for (size_t i = 0; i <= buffer_size - sequence_size; i++) { ++ if (memcmp(buffer + i, sequence, sequence_size) == 0) { ++ return (unsigned char *)(buffer + i); ++ } ++ } ++ return NULL; ++} ++ ++static int nss_hal_firmware_info(struct platform_device *nss_dev, ++ const struct firmware *fw) ++{ ++ unsigned char *start_pos, *end_pos; ++ size_t i; ++ unsigned char start_sequence[] = { 0x56, 0x65, 0x72, 0x73, 0x69, 0x6f, 0x6e, 0x3a, 0x20 }; ++ unsigned char end_sequence[] = { 0x00 }; ++ char version[256]; ++ bool found = false; ++ ++ // Search for the start sequence ++ start_pos = search_sequence(fw->data, fw->size, start_sequence, sizeof(start_sequence)); ++ if (start_pos) { ++ start_pos += sizeof(start_sequence); ++ ++ end_pos = search_sequence(start_pos, fw->size - (start_pos - fw->data), end_sequence, sizeof(end_sequence)); ++ if (end_pos) { ++ // Convert the version information to a string ++ for (i = 0; start_pos + i < end_pos && i < sizeof(version) - 1; i++) { ++ version[i] = start_pos[i]; ++ } ++ version[i] = '\0'; ++ ++ dev_info(&nss_dev->dev, "NSS FW Version: %s", version); ++ found = true; ++ } ++ } ++ ++ if (!found) { ++ dev_err(&nss_dev->dev, "Unable to get NSS FW version"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ + int nss_hal_firmware_load(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd) + { + const struct firmware *nss_fw; +@@ -81,6 +132,10 @@ int nss_hal_firmware_load(struct nss_ctx + return rc; + } + ++ if (nss_ctx->id == 0) { ++ nss_hal_firmware_info(nss_dev, nss_fw); ++ } ++ + dev_info(&nss_dev->dev, "fw of size %d bytes copied to addr: %x, nss_id: %d", (int)nss_fw->size, npd->load_addr, nss_ctx->id); + memcpy_toio(load_mem, nss_fw->data, nss_fw->size); + release_firmware(nss_fw); diff --git a/qca-nss-drv/patches-11.4/0022-nss-drv-set-addr-to-const.patch b/qca-nss-drv/patches-11.4/0022-nss-drv-set-addr-to-const.patch new file mode 100644 index 0000000..3ed5db6 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0022-nss-drv-set-addr-to-const.patch @@ -0,0 +1,88 @@ +--- a/exports/nss_bridge.h ++++ b/exports/nss_bridge.h +@@ -273,7 +273,7 @@ nss_tx_status_t nss_bridge_tx_set_mtu_ms + * @return + * Status of the Tx operation. + */ +-nss_tx_status_t nss_bridge_tx_set_mac_addr_msg(uint32_t bridge_if_num, uint8_t *addr); ++nss_tx_status_t nss_bridge_tx_set_mac_addr_msg(uint32_t bridge_if_num, const uint8_t *addr); + + /** + * nss_bridge_tx_join_msg +--- a/exports/nss_vlan.h ++++ b/exports/nss_vlan.h +@@ -210,7 +210,7 @@ nss_tx_status_t nss_vlan_tx_set_mtu_msg( + * @return + * Status of the Tx operation. + */ +-nss_tx_status_t nss_vlan_tx_set_mac_addr_msg(uint32_t vlan_if_num, uint8_t *addr); ++nss_tx_status_t nss_vlan_tx_set_mac_addr_msg(uint32_t vlan_if_num, const uint8_t *addr); + + /** + * nss_vlan_tx_vsi_attach_msg +--- a/exports/nss_wifi_vdev.h ++++ b/exports/nss_wifi_vdev.h +@@ -1327,7 +1327,7 @@ nss_tx_status_t nss_wifi_vdev_base_set_n + * @return + * Status of the Tx operation. + */ +-nss_tx_status_t nss_wifi_vdev_set_peer_next_hop(struct nss_ctx_instance *nss_ctx, uint32_t nss_if, uint8_t *addr, uint32_t next_hop_if); ++nss_tx_status_t nss_wifi_vdev_set_peer_next_hop(struct nss_ctx_instance *nss_ctx, uint32_t nss_if, const uint8_t *addr, uint32_t next_hop_if); + + /* + * nss_wifi_vdev_set_dp_type +--- a/nss_bridge.c ++++ b/nss_bridge.c +@@ -304,7 +304,7 @@ EXPORT_SYMBOL(nss_bridge_tx_set_mtu_msg) + * nss_bridge_tx_set_mac_addr_msg + * API to send change mac addr message to NSS FW + */ +-nss_tx_status_t nss_bridge_tx_set_mac_addr_msg(uint32_t bridge_if_num, uint8_t *addr) ++nss_tx_status_t nss_bridge_tx_set_mac_addr_msg(uint32_t bridge_if_num, const uint8_t *addr) + { + struct nss_ctx_instance *nss_ctx = nss_bridge_get_context(); + struct nss_bridge_msg nbm; +--- a/nss_phys_if.c ++++ b/nss_phys_if.c +@@ -402,7 +402,7 @@ nss_tx_status_t nss_phys_if_link_state(s + * nss_phys_if_mac_addr() + * Send a MAC address to physical interface + */ +-nss_tx_status_t nss_phys_if_mac_addr(struct nss_ctx_instance *nss_ctx, uint8_t *addr, uint32_t if_num) ++nss_tx_status_t nss_phys_if_mac_addr(struct nss_ctx_instance *nss_ctx, const uint8_t *addr, uint32_t if_num) + { + struct nss_phys_if_msg nim; + struct nss_if_mac_address_set *nmas; +--- a/nss_phys_if.h ++++ b/nss_phys_if.h +@@ -284,7 +284,7 @@ nss_tx_status_t nss_phys_if_link_state(s + * + * @return nss_tx_status_t Tx status + */ +-nss_tx_status_t nss_phys_if_mac_addr(struct nss_ctx_instance *nss_ctx, uint8_t *addr, uint32_t if_num); ++nss_tx_status_t nss_phys_if_mac_addr(struct nss_ctx_instance *nss_ctx, const uint8_t *addr, uint32_t if_num); + + /** + * @brief Send MTU change notification to NSS +--- a/nss_vlan.c ++++ b/nss_vlan.c +@@ -246,7 +246,7 @@ EXPORT_SYMBOL(nss_vlan_tx_set_mtu_msg); + * nss_vlan_tx_set_mac_addr_msg + * API to send change mac addr message to NSS FW + */ +-nss_tx_status_t nss_vlan_tx_set_mac_addr_msg(uint32_t vlan_if_num, uint8_t *addr) ++nss_tx_status_t nss_vlan_tx_set_mac_addr_msg(uint32_t vlan_if_num, const uint8_t *addr) + { + struct nss_ctx_instance *nss_ctx = nss_vlan_get_context(); + struct nss_vlan_msg nvm; +--- a/nss_wifi_vdev.c ++++ b/nss_wifi_vdev.c +@@ -274,7 +274,7 @@ EXPORT_SYMBOL(nss_wifi_vdev_base_set_nex + /* + * nss_wifi_vdev_set_peer_next_hop() + */ +-nss_tx_status_t nss_wifi_vdev_set_peer_next_hop(struct nss_ctx_instance *ctx, uint32_t nss_if, uint8_t *addr, uint32_t next_hop_if) ++nss_tx_status_t nss_wifi_vdev_set_peer_next_hop(struct nss_ctx_instance *ctx, uint32_t nss_if, const uint8_t *addr, uint32_t next_hop_if) + { + nss_tx_status_t status; + struct nss_wifi_vdev_msg *wifivdevmsg = kzalloc(sizeof(struct nss_wifi_vdev_msg), GFP_KERNEL); diff --git a/qca-nss-drv/patches-11.4/0023-add-boot-delay.patch b/qca-nss-drv/patches-11.4/0023-add-boot-delay.patch new file mode 100644 index 0000000..a8ec052 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0023-add-boot-delay.patch @@ -0,0 +1,60 @@ +--- a/nss_core.c ++++ b/nss_core.c +@@ -87,6 +87,8 @@ MODULE_PARM_DESC(pn_qlimits, "Queue limi + static atomic_t jumbo_mru; + static atomic_t paged_mode; + ++static int nss_bootstate = 0; ++ + /* + * nss_core_update_max_ipv4_conn() + * Update the maximum number of configured IPv4 connections +@@ -2192,6 +2194,19 @@ static inline void nss_core_handle_tx_un + nss_hal_disable_interrupt(nss_ctx, nss_ctx->int_ctx[0].shift_factor, NSS_N2H_INTR_TX_UNBLOCKED); + } + ++void nss_bootwait(void) ++{ ++ int dead = 10 * 10; ++#if (NSS_MAX_CORES > 1) ++ while (nss_bootstate < 2 && dead-- > 0) ++#else ++ while (!nss_bootstate && dead-- > 0) ++#endif ++ { ++ msleep(100); ++ } ++} ++ + /* + * nss_core_handle_cause_nonqueue() + * Handle non-queue interrupt causes (e.g. empty buffer SOS, Tx unblocked) +@@ -2260,6 +2275,9 @@ static void nss_core_handle_cause_nonque + #endif + #endif + } ++ if (unlikely(nss_ctx->state == NSS_CORE_STATE_INITIALIZED)) { ++ nss_bootstate++; ++ } + + /* + * TODO: find better mechanism to handle empty buffers +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -827,6 +827,7 @@ int nss_hal_probe(struct platform_device + } + + nss_info("%px: All resources initialized and nss core%d has been brought out of reset", nss_ctx, nss_dev->id); ++ nss_bootwait(); + goto out; + + err_register_irq: +--- a/nss_core.h ++++ b/nss_core.h +@@ -1035,4 +1035,6 @@ extern void nss_ppe_free(void); + extern nss_tx_status_t nss_n2h_cfg_empty_pool_size(struct nss_ctx_instance *nss_ctx, uint32_t pool_sz); + extern nss_tx_status_t nss_n2h_paged_buf_pool_init(struct nss_ctx_instance *nss_ctx); + ++void nss_bootwait(void); ++ + #endif /* __NSS_CORE_H */ diff --git a/qca-nss-drv/patches-11.4/0023-nss-drv-add-missing-wifili-err-codes.patch b/qca-nss-drv/patches-11.4/0023-nss-drv-add-missing-wifili-err-codes.patch new file mode 100644 index 0000000..e94b696 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0023-nss-drv-add-missing-wifili-err-codes.patch @@ -0,0 +1,76 @@ +commit 1db9e5510558817d138de87f5a4942293a9fcb91 +Author: syed touqeer pasha +AuthorDate: Thu May 16 14:59:48 2024 +0530 +Commit: syed touqeer pasha +CommitDate: Thu May 16 14:59:48 2024 +0530 + +[qca-nss-drv] Add missing error code for wifili pkg. + +Add missing error code between nss fw and nss drv. + +Change-Id: I3f81da10b33fd15b1817a40eb906df9642a10d98 +Signed-off-by: syed touqeer pasha + +--- a/exports/nss_wifili_if.h ++++ b/exports/nss_wifili_if.h +@@ -392,6 +392,60 @@ enum nss_wifili_error_types { + /**< Invalid TLV length. */ + NSS_WIFILI_EMESG_RX_BUF_LEN_INVALID, + /**< Invalid Rx buffer length. */ ++ NSS_WIFILI_EMSG_INVALID_PDEV_ID, ++ /**< Invalid pdev id from host. */ ++ NSS_WIFILI_EMSG_NO_PDEV_PRESENT, ++ /**< Pdev corresponding to this pdev id is not present. */ ++ NSS_WIFILI_EMESG_WDS_UPDATE_FAIL, ++ /**< Wds peer ast update failed. */ ++ NSS_WIFILI_EMSG_VLAN_ID_SET_FAIL, ++ /**< Vlan id set failed. */ ++ NSS_WIFILI_EMSG_PDEV_UPDATE_INVALID_RADIOID_FAIL, ++ /**< Pdev update failed due to invalid radio id. */ ++ NSS_WIFILI_EMSG_PDEV_UPDATE_INVALID_LMACID_FAIL, ++ /**< Pdev update failed due to invalid lmac id. */ ++ NSS_WIFILI_EMSG_PDEV_UPDATE_INVALID_TARGETPDEVID_FAIL, ++ /**< Pdev update failed due to invalid target pdev id. */ ++ NSS_WIFILI_EMESG_PEER_AST_FLOWID_MAP_VAPID_INVALID_FAIL, ++ /**< Peer ast flow map failed due to invalid vdev_id. */ ++ NSS_WIFILI_EMESG_PEER_AST_FLOWID_MAP_VDEV_NULL_FAIL, ++ /**< Peer ast flow map failed due to vdev null. */ ++ NSS_WIFILI_EMESG_PEER_AST_FLOWID_MAP_PEERID_INVALID_FAIL, ++ /**< Peer ast flow map failed due to invalid peer_id. */ ++ NSS_WIFILI_EMSG_PEER_AST_FLOWID_MAP_STA_VAP_FAIL, ++ /**< Peer ast flowid map failed due to sta vap. */ ++ NSS_WIFILI_EMESG_PEER_AST_FLOWID_MAP_PEERID_MISMATCH_FAIL, ++ /**< Peer ast flow map failed due to mismatched peer_id. */ ++ NSS_WIFILI_EMESG_PEER_AST_FLOWID_MAP_PEER_NULL_FAIL, ++ /**< Peer ast flow map failed due to peer null. */ ++ NSS_WIFILI_EMSG_PEER_AST_FLOWID_MAP_AST_MISMATCH_FAIL, ++ /**< Peer ast flow map failed due to mismatched ast index. */ ++ NSS_WIFILI_EMSG_INVALID_V3_STATS_TYPE, ++ /**< Invalid v3 stats type. */ ++ NSS_WIFILI_EMSG_ISOLATION_SET_FAIL, ++ /**< Peer isolation set failed. */ ++ NSS_WIFILI_EMESG_WDS_ALREADY_PRESENT, ++ /**< Wds peer ast add failed. */ ++ NSS_WIFILI_EMSG_STATS_CLR_VDEV_NULL_FAIL, ++ /**< Statistics clear failed due to null vdev. */ ++ NSS_WIFILI_EMSG_INVALID_VDEV_ID, ++ /**< Invalid vdev id from host. */ ++ NSS_WIFILI_EMSG_PDEV_INIT_FAIL_INVALID_THREAD_SCHEME_ID, ++ /**< Incorrect scheme ID sent from host. */ ++ NSS_WIFILI_EMSG_PEER_WDS_4ADDR_EVENT_INV_PEER, ++ /**< Invalid peer ID sent from host. */ ++ NSS_WIFILI_EMSG_PEER_WDS_INVALID_IFNUM, ++ /**< Invalid peer ID sent from host. */ ++ NSS_WIFILI_EMSG_PEER_AUTH_FLAG_UPDATE_FAIL, ++ /**< Peer authentication flag update failed. */ ++ NSS_WIFILI_EMSG_PEER_TEARDOWN_ALLOC_FAIL, ++ /**< Alloc fail in peer tear down path. */ ++ NSS_WIFILI_EMSG_TX_CAPTURE_MODE_UPDATE_FAIL, ++ /**< Tx capture mode update failure. */ ++ NSS_WIFILI_EMSG_PEER_MEMORY_INSUFFICIENT_FROM_HOST, ++ /**< Peer memory from host is less than NSS peer struct. */ ++ NSS_WIFILI_EMSG_DUPLICATE_MPASS_ID_SET, ++ /**< Duplicate mpass vlan id set. */ + NSS_WIFILI_EMSG_UNKNOWN + /**< Unknown error message. */ + }; diff --git a/qca-nss-drv/patches-11.4/0024-fix-mesh-stats-naming.patch b/qca-nss-drv/patches-11.4/0024-fix-mesh-stats-naming.patch new file mode 100644 index 0000000..0b7bb91 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0024-fix-mesh-stats-naming.patch @@ -0,0 +1,39 @@ +--- a/nss_wifi_mesh_strings.c ++++ b/nss_wifi_mesh_strings.c +@@ -80,8 +80,8 @@ struct nss_stats_info nss_wifi_mesh_stri + {"not_found", NSS_STATS_TYPE_SPECIAL}, + {"delete_success", NSS_STATS_TYPE_SPECIAL}, + {"update_success", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_path_expired", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_path_refresh_needed", NSS_STATS_TYPE_SPECIAL}, ++ {"path_expired", NSS_STATS_TYPE_SPECIAL}, ++ {"path_refresh_needed", NSS_STATS_TYPE_SPECIAL}, + {"add_requests", NSS_STATS_TYPE_SPECIAL}, + {"del_requests", NSS_STATS_TYPE_SPECIAL}, + {"update_requests", NSS_STATS_TYPE_SPECIAL}, +@@ -91,8 +91,8 @@ struct nss_stats_info nss_wifi_mesh_stri + {"metric_updations", NSS_STATS_TYPE_SPECIAL}, + {"block_mesh_fwd_updations", NSS_STATS_TYPE_SPECIAL}, + {"delete_failures", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_path_dummy_add_failures",NSS_STATS_TYPE_SPECIAL}, +- {"mesh_path_dummy_add_success", NSS_STATS_TYPE_SPECIAL} ++ {"path_dummy_add_failures", NSS_STATS_TYPE_SPECIAL}, ++ {"path_dummy_add_success", NSS_STATS_TYPE_SPECIAL} + + }; + +@@ -126,10 +126,10 @@ struct nss_stats_info nss_wifi_mesh_stri + {"update_requests", NSS_STATS_TYPE_SPECIAL}, + {"mda_updations", NSS_STATS_TYPE_SPECIAL}, + {"flag_updations", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_proxy_path_dummy_lookup_success", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_proxy_path_dummy_lookup_failures", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_proxy_path_dummy_add_failures", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_proxy_path_dummy_add_success", NSS_STATS_TYPE_SPECIAL} ++ {"proxy_path_dummy_lookup_success", NSS_STATS_TYPE_SPECIAL}, ++ {"proxy_path_dummy_lookup_failures", NSS_STATS_TYPE_SPECIAL}, ++ {"proxy_path_dummy_add_failures", NSS_STATS_TYPE_SPECIAL}, ++ {"proxy_path_dummy_add_success", NSS_STATS_TYPE_SPECIAL} + }; + + /* diff --git a/qca-nss-drv/patches-11.4/0025-fix-missing-macro-gre_tunnel.patch b/qca-nss-drv/patches-11.4/0025-fix-missing-macro-gre_tunnel.patch new file mode 100644 index 0000000..17cdc22 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0025-fix-missing-macro-gre_tunnel.patch @@ -0,0 +1,14 @@ +--- a/exports/nss_gre_tunnel.h ++++ b/exports/nss_gre_tunnel.h +@@ -212,7 +212,11 @@ struct nss_gre_tunnel_stats { + * GRE tunnel transmission statistics structure. + */ + struct nss_gre_tunnel_stats_notification { ++#if defined(NSS_HAL_IPQ807x_SUPPORT) + uint64_t stats_ctx[NSS_GRE_TUNNEL_STATS_SESSION_MAX + NSS_CRYPTO_CMN_RESP_ERROR_MAX]; ++#else ++ uint64_t stats_ctx[NSS_GRE_TUNNEL_STATS_SESSION_MAX]; ++#endif + /**< Context transmission statistics. */ + uint32_t core_id; /**< Core ID. */ + uint32_t if_num; /**< Interface number. */ diff --git a/qca-nss-drv/patches-11.4/0025-nss_rps-fix-procfs-read-write.patch b/qca-nss-drv/patches-11.4/0025-nss_rps-fix-procfs-read-write.patch new file mode 100644 index 0000000..5cb4417 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0025-nss_rps-fix-procfs-read-write.patch @@ -0,0 +1,205 @@ +--- a/nss_rps.c ++++ b/nss_rps.c +@@ -67,7 +67,7 @@ static inline void nss_rps_pri_map_usage + * nss_rps_pri_map_print() + * Sysctl handler for printing rps/pri mapping. + */ +-static int nss_rps_pri_map_print(struct ctl_table *ctl, void __user *buffer, ++static int nss_rps_pri_map_print(void *buffer, + size_t *lenp, loff_t *ppos, int *pri_map) + { + char *r_buf; +@@ -106,7 +106,7 @@ static int nss_rps_pri_map_print(struct + len = scnprintf(r_buf + cp_bytes, 4, "\n"); + cp_bytes += len; + +- cp_bytes = simple_read_from_buffer(buffer, *lenp, ppos, r_buf, cp_bytes); ++ cp_bytes = memory_read_from_buffer(buffer, *lenp, ppos, r_buf, cp_bytes); + *lenp = cp_bytes; + kfree(r_buf); + return 0; +@@ -116,13 +116,10 @@ static int nss_rps_pri_map_print(struct + * nss_rps_pri_map_parse() + * Sysctl handler for rps/pri mappings. + */ +-static int nss_rps_pri_map_parse(struct ctl_table *ctl, void __user *buffer, +- size_t *lenp, loff_t *ppos, struct nss_rps_pri_map_parse_data *out) ++static int nss_rps_pri_map_parse(void *buffer, ++ size_t *lenp, struct nss_rps_pri_map_parse_data *out) + { +- size_t cp_bytes = 0; + char w_buf[5]; +- loff_t w_offset = 0; +- char *str; + unsigned int pri; + int core, res; + +@@ -137,14 +134,15 @@ static int nss_rps_pri_map_parse(struct + /* + * It's a write operation + */ +- cp_bytes = simple_write_to_buffer(w_buf, *lenp, &w_offset, buffer, 5); +- if (cp_bytes != *lenp) { +- nss_warning("failed to write to buffer\n"); +- return -EFAULT; ++ if (*lenp >= sizeof(w_buf)) { ++ nss_warning("Input too large: %zu\n", *lenp); ++ return -EINVAL; + } + +- str = w_buf; +- res = sscanf(str, "%u %d", &pri, &core); ++ memcpy(w_buf, buffer, *lenp); ++ w_buf[*lenp] = '\0'; /* Ensure null termination */ ++ ++ res = sscanf(w_buf, "%u %d", &pri, &core); + if (res != NSS_RPS_PRI_MAP_PARAM_FIELD_COUNT) { + nss_warning("failed to read the buffer\n"); + return -EFAULT; +@@ -404,7 +402,7 @@ static nss_tx_status_t nss_rps_pri_map_c + * Enable NSS RPS. + */ + static int nss_rps_cfg_handler(struct ctl_table *ctl, int write, +- void __user *buffer, size_t *lenp, loff_t *ppos) ++ void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx; +@@ -455,7 +453,7 @@ static int nss_rps_cfg_handler(struct ct + * Configure NSS rps_hash_bitmap + */ + static int nss_rps_hash_bitmap_cfg_handler(struct ctl_table *ctl, int write, +- void __user *buffer, size_t *lenp, loff_t *ppos) ++ void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx __attribute__((unused)) = &nss_top->nss[0]; +@@ -518,7 +516,7 @@ static int nss_rps_hash_bitmap_cfg_handl + * Configure NSS rps_pri_map + */ + static int nss_rps_pri_map_cfg_handler(struct ctl_table *ctl, int write, +- void __user *buffer, size_t *lenp, loff_t *ppos) ++ void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -526,10 +524,10 @@ static int nss_rps_pri_map_cfg_handler(s + int ret, ret_pri_map; + struct nss_rps_pri_map_parse_data out, current_state; + if (!write) { +- return nss_rps_pri_map_print(ctl, buffer, lenp, ppos, nss_rps_pri_map); ++ return nss_rps_pri_map_print(buffer, lenp, ppos, nss_rps_pri_map); + } + +- ret = nss_rps_pri_map_parse(ctl, buffer, lenp, ppos, &out); ++ ret = nss_rps_pri_map_parse(buffer, lenp, &out); + + if (ret != NSS_SUCCESS) { + nss_rps_pri_map_usage(); +--- a/nss_ipv6.c ++++ b/nss_ipv6.c +@@ -595,7 +595,7 @@ void nss_ipv6_free_conn_tables(void) + * nss_ipv6_accel_mode_cfg_handler() + * Configure acceleration mode for IPv6 + */ +-static int nss_ipv6_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv6_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -639,7 +639,7 @@ static int nss_ipv6_accel_mode_cfg_handl + * nss_ipv6_dscp_map_cfg_handler() + * Sysctl handler for dscp/pri mappings. + */ +-static int nss_ipv6_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv6_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +--- a/nss_ipv4.c ++++ b/nss_ipv4.c +@@ -599,7 +599,7 @@ void nss_ipv4_free_conn_tables(void) + * nss_ipv4_accel_mode_cfg_handler() + * Configure acceleration mode for IPv4 + */ +-static int nss_ipv4_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv4_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -643,7 +643,7 @@ static int nss_ipv4_accel_mode_cfg_handl + * nss_ipv4_dscp_map_cfg_handler() + * Sysctl handler for dscp/pri mappings. + */ +-static int nss_ipv4_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv4_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +--- a/nss_dscp_map.h ++++ b/nss_dscp_map.h +@@ -46,7 +46,7 @@ struct nss_dscp_map_parse { + * nss_dscp_map_print() + * Sysctl handler for printing dscp/pri mapping. + */ +-static int nss_dscp_map_print(struct ctl_table *ctl, void __user *buffer, size_t *lenp, ++static int nss_dscp_map_print(struct ctl_table *ctl, void *buffer, size_t *lenp, + loff_t *ppos, struct nss_dscp_map_entry *mapping) + { + char *r_buf; +@@ -105,7 +105,7 @@ static int nss_dscp_map_print(struct ctl + len = scnprintf(r_buf + cp_bytes, 4, "\n"); + cp_bytes += len; + +- cp_bytes = simple_read_from_buffer(buffer, *lenp, ppos, r_buf, cp_bytes); ++ cp_bytes = memory_read_from_buffer(buffer, *lenp, ppos, r_buf, cp_bytes); + *lenp = cp_bytes; + kfree(r_buf); + return 0; +@@ -115,35 +115,32 @@ static int nss_dscp_map_print(struct ctl + * nss_dscp_map_parse() + * Sysctl handler for dscp/pri mappings. + */ +-static int nss_dscp_map_parse(struct ctl_table *ctl, void __user *buffer, size_t *lenp, ++static int nss_dscp_map_parse(struct ctl_table *ctl, void *buffer, size_t *lenp, + loff_t *ppos, struct nss_dscp_map_parse *out) + { + int count; +- size_t cp_bytes = 0; +- char w_buf[7]; +- loff_t w_offset = 0; ++ char w_buf[8]; + char *str; + char *tokens[NSS_DSCP_MAP_PARAM_FIELD_COUNT]; + unsigned int dscp, priority, action; + int ret; + + /* +- * Buffer length cannot be more than 7 and less than 6. ++ * Buffer length cannot be more than 8 and less than 6. + */ +- if (*lenp < 6 || *lenp > 7) { +- nss_warning("Buffer is not correct. Invalid lenght: %d\n", (int)*lenp); ++ if (*lenp < 6 || *lenp > 8) { ++ nss_warning("Invalid length: %d\n", (int)*lenp); + return -EINVAL; + } + +- /* +- * It's a write operation +- */ +- cp_bytes = simple_write_to_buffer(w_buf, *lenp, &w_offset, buffer, 7); +- if (cp_bytes != *lenp) { +- nss_warning("failed to write to buffer\n"); +- return -EFAULT; ++ if (*lenp >= sizeof(w_buf)) { ++ nss_warning("Input too large: %zu\n", *lenp); ++ return -EINVAL; + } + ++ memcpy(w_buf, buffer, *lenp); ++ w_buf[*lenp] = '\0'; /* Ensure null termination */ ++ + count = 0; + str = w_buf; + tokens[count] = strsep(&str, " "); diff --git a/qca-nss-drv/patches-11.4/0026-nss-drv-add-support-for-kernel-6.12.patch b/qca-nss-drv/patches-11.4/0026-nss-drv-add-support-for-kernel-6.12.patch new file mode 100644 index 0000000..2225817 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0026-nss-drv-add-support-for-kernel-6.12.patch @@ -0,0 +1,800 @@ +--- a/nss_core.c ++++ b/nss_core.c +@@ -35,34 +35,16 @@ + #endif + #endif + #include ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 10, 0)) ++#include ++#endif + #include "nss_tx_rx_common.h" + #include "nss_data_plane.h" + + #define NSS_CORE_JUMBO_LINEAR_BUF_SIZE 128 + + #if (NSS_SKB_REUSE_SUPPORT == 1) +-/* +- * We have validated the skb recycling code within the NSS for the +- * following kernel versions. Before enabling the driver in new kernels, +- * the skb recycle code must be checked against Linux skb handling. +- * +- * Tested on: 3.4, 3.10, 3.14, 3.18, 4.4 and 5.4 +- */ +-#if (!( \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(6, 14, 0)))))) +-#error "Check skb recycle code in this file to match Linux version" +-#endif +- + static atomic_t max_reuse = ATOMIC_INIT(PAGE_SIZE); +- + #endif /* NSS_SKB_REUSE_SUPPORT */ + + static int max_ipv4_conn = NSS_DEFAULT_NUM_CONN; +--- a/Makefile ++++ b/Makefile +@@ -579,6 +579,8 @@ qca-nss-drv-objs += \ + ccflags-y += -DNSS_FREQ_SCALE_SUPPORT=1 + endif + ++ccflags-y += -include $(obj)/compat.h ++ + ccflags-y += $(NSS_CCFLAGS) + + export NSS_CCFLAGS +--- a/nss_init.c ++++ b/nss_init.c +@@ -115,10 +115,17 @@ static inline int nss_probe(struct platf + * nss_remove() + * HLOS device remove callback + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0)) + static inline int nss_remove(struct platform_device *nss_dev) + { + return nss_hal_remove(nss_dev); + } ++#else ++static inline void nss_remove(struct platform_device *nss_dev) ++{ ++ nss_hal_remove(nss_dev); ++} ++#endif + + #if (NSS_DT_SUPPORT == 1) + /* +@@ -128,7 +135,6 @@ struct of_device_id nss_dt_ids[] = { + { .compatible = "qcom,nss" }, + { .compatible = "qcom,nss0" }, + { .compatible = "qcom,nss1" }, +- {}, + }; + MODULE_DEVICE_TABLE(of, nss_dt_ids); + #endif +@@ -168,7 +174,7 @@ static void nss_reset_frequency_stats_sa + * nss_current_freq_handler() + * Handle Userspace Frequency Change Requests + */ +-static int nss_current_freq_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_current_freq_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret, i; + +@@ -228,7 +234,7 @@ static int nss_current_freq_handler(stru + * nss_auto_scale_handler() + * Enables or Disable Auto Scaling + */ +-static int nss_auto_scale_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_auto_scale_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -293,7 +299,7 @@ static int nss_auto_scale_handler(struct + * nss_get_freq_table_handler() + * Display Support Freq and Ex how to Change. + */ +-static int nss_get_freq_table_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_get_freq_table_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret, i; + +@@ -322,7 +328,7 @@ static int nss_get_freq_table_handler(st + * nss_get_average_inst_handler() + * Display AVG Inst Per Ms. + */ +-static int nss_get_average_inst_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_get_average_inst_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -344,7 +350,7 @@ static int nss_get_average_inst_handler( + * nss_debug_handler() + * Enable NSS debug output + */ +-static int nss_debug_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_debug_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -364,7 +370,7 @@ static int nss_debug_handler(struct ctl_ + * nss_coredump_handler() + * Send Signal To Coredump NSS Cores + */ +-static int nss_coredump_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_coredump_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[NSS_CORE_0]; + int ret; +@@ -389,7 +395,7 @@ static int nss_coredump_handler(struct c + * nss_jumbo_mru_handler() + * Sysctl to modify nss_jumbo_mru + */ +-static int nss_jumbo_mru_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_jumbo_mru_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -410,7 +416,7 @@ static int nss_jumbo_mru_handler(struct + * Sysctl to modify nss_paged_mode. + */ + +-static int nss_paged_mode_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_paged_mode_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -432,7 +438,7 @@ static int nss_paged_mode_handler(struct + * nss_get_min_reuse_handler() + * Sysctl to get min reuse sizes + */ +-static int nss_get_min_reuse_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_get_min_reuse_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + struct nss_ctx_instance *nss_ctx = NULL; +@@ -459,7 +465,7 @@ static int nss_get_min_reuse_handler(str + * nss_max_reuse_handler() + * Sysctl to modify nss_max_reuse + */ +-static int nss_max_reuse_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_max_reuse_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -494,8 +500,7 @@ static struct ctl_table nss_skb_reuse_ta + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_max_reuse_handler, +- }, +- { } ++ } + }; + #endif + +@@ -531,8 +536,7 @@ static struct ctl_table nss_freq_table[] + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_get_average_inst_handler, +- }, +- { } ++ } + }; + #endif + +@@ -580,8 +584,7 @@ static struct ctl_table nss_general_tabl + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_paged_mode_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_clock_header; +--- a/nss_stats.c ++++ b/nss_stats.c +@@ -70,7 +70,7 @@ static size_t nss_stats_spacing(uint64_t + * nss_stats_nonzero_handler() + * Handler to take nonzero stats print configuration. + */ +-static int nss_stats_nonzero_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_stats_nonzero_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + ret = proc_dointvec(ctl, write, buffer, lenp, ppos); +@@ -84,8 +84,7 @@ static struct ctl_table nss_stats_table[ + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_stats_nonzero_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_stats_header; +@@ -228,7 +227,7 @@ size_t nss_stats_banner(char *lbuf, size + size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "<"); + } + +- strlcpy(node_upr, node, NSS_STATS_NODE_NAME_MAX); ++ strscpy(node_upr, node, NSS_STATS_NODE_NAME_MAX + 1); + for (i = 0; node_upr[i] != '\0' && i < NSS_STATS_NODE_NAME_MAX; i++) { + node_upr[i] = toupper(node_upr[i]); + } +@@ -293,7 +292,7 @@ size_t nss_stats_print(char *node, char + continue; + } + +- strlcpy(stats_string, stats_info[i].stats_name, NSS_STATS_MAX_STR_LENGTH); ++ strscpy(stats_string, stats_info[i].stats_name, NSS_STATS_MAX_STR_LENGTH); + + /* + * Converting uppercase to lower case. +@@ -302,7 +301,7 @@ size_t nss_stats_print(char *node, char + stats_string[j] = tolower(stats_string[j]); + } + +- strlcpy(node_lwr, node, NSS_STATS_NODE_NAME_MAX); ++ strscpy(node_lwr, node, NSS_STATS_NODE_NAME_MAX + 1); + for (j = 0; node_lwr[j] != '\0' && j < NSS_STATS_NODE_NAME_MAX; j++) { + node_lwr[j] = tolower(node_lwr[j]); + } +--- a/nss_tunipip6_stats.c ++++ b/nss_tunipip6_stats.c +@@ -16,6 +16,10 @@ + ************************************************************************** + */ + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 10, 0) ++#include ++#endif ++ + #include "nss_core.h" + #include "nss_tunipip6.h" + #include "nss_stats.h" +--- /dev/null ++++ b/compat.h +@@ -0,0 +1,14 @@ ++// compat.h ++#ifndef _COMPAT_H ++#define _COMPAT_H ++ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 10, 0) ++#include ++#define compat_const const ++#else ++#define compat_const ++#endif ++ ++#endif /* _COMPAT_H */ +--- a/nss_c2c_tx.c ++++ b/nss_c2c_tx.c +@@ -284,7 +284,7 @@ EXPORT_SYMBOL(nss_c2c_tx_msg_init); + * nss_c2c_tx_performance_test_handler() + * Handles the performance test. + */ +-static int nss_c2c_tx_performance_test_handler(struct ctl_table *ctl, int write, ++static int nss_c2c_tx_performance_test_handler(compat_const struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; +@@ -330,8 +330,7 @@ static struct ctl_table nss_c2c_tx_table + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_c2c_tx_performance_test_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_c2c_tx_header; +--- a/nss_dma.c ++++ b/nss_dma.c +@@ -284,7 +284,7 @@ EXPORT_SYMBOL(nss_dma_get_context); + * nss_dma_test_handler() + * Handles the performance test. + */ +-static int nss_dma_test_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_dma_test_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_ctx_instance *nss_ctx = nss_dma_get_context(); + int cur_state = test_cfg.run.val; +@@ -374,8 +374,7 @@ static struct ctl_table nss_dma_table[] + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_dma_header; +--- a/nss_ipv4.c ++++ b/nss_ipv4.c +@@ -599,7 +599,7 @@ void nss_ipv4_free_conn_tables(void) + * nss_ipv4_accel_mode_cfg_handler() + * Configure acceleration mode for IPv4 + */ +-static int nss_ipv4_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv4_accel_mode_cfg_handler(compat_const struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -643,7 +643,7 @@ static int nss_ipv4_accel_mode_cfg_handl + * nss_ipv4_dscp_map_cfg_handler() + * Sysctl handler for dscp/pri mappings. + */ +-static int nss_ipv4_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv4_dscp_map_cfg_handler(compat_const struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -708,8 +708,7 @@ static struct ctl_table nss_ipv4_table[] + .maxlen = sizeof(struct nss_dscp_map_entry), + .mode = 0644, + .proc_handler = &nss_ipv4_dscp_map_cfg_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_ipv4_header; +--- a/nss_ipv6.c ++++ b/nss_ipv6.c +@@ -595,7 +595,7 @@ void nss_ipv6_free_conn_tables(void) + * nss_ipv6_accel_mode_cfg_handler() + * Configure acceleration mode for IPv6 + */ +-static int nss_ipv6_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv6_accel_mode_cfg_handler(compat_const struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -639,7 +639,7 @@ static int nss_ipv6_accel_mode_cfg_handl + * nss_ipv6_dscp_map_cfg_handler() + * Sysctl handler for dscp/pri mappings. + */ +-static int nss_ipv6_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv6_dscp_map_cfg_handler(compat_const struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -703,8 +703,7 @@ static struct ctl_table nss_ipv6_table[] + .maxlen = sizeof(struct nss_dscp_map_entry), + .mode = 0644, + .proc_handler = &nss_ipv6_dscp_map_cfg_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_ipv6_header; +--- a/nss_log.c ++++ b/nss_log.c +@@ -524,7 +524,7 @@ fail: + * nss_logbuffer_handler() + * Enable NSS debug output + */ +-int nss_logbuffer_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++int nss_logbuffer_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + int core_status; +--- a/nss_n2h.c ++++ b/nss_n2h.c +@@ -344,7 +344,7 @@ static int nss_n2h_get_paged_payload_inf + * nss_n2h_set_empty_buf_pool() + * Sets empty pool buffer + */ +-static int nss_n2h_set_empty_buf_pool(struct ctl_table *ctl, int write, ++static int nss_n2h_set_empty_buf_pool(compat_const struct ctl_table *ctl, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos, + nss_ptr_t core_num, int *new_val) +@@ -446,7 +446,7 @@ failure: + * nss_n2h_set_empty_paged_pool_buf() + * Sets empty paged pool buffer + */ +-static int nss_n2h_set_empty_paged_pool_buf(struct ctl_table *ctl, int write, ++static int nss_n2h_set_empty_paged_pool_buf(compat_const struct ctl_table *ctl, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos, + nss_ptr_t core_num, int *new_val) +@@ -548,7 +548,7 @@ failure: + * nss_n2h_set_water_mark() + * Sets water mark for N2H SOS + */ +-static int nss_n2h_set_water_mark(struct ctl_table *ctl, int write, ++static int nss_n2h_set_water_mark(compat_const struct ctl_table *ctl, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos, + uint32_t core_num, int *low, int *high) +@@ -662,7 +662,7 @@ failure: + * nss_n2h_set_paged_water_mark() + * Sets water mark for paged pool N2H SOS + */ +-static int nss_n2h_set_paged_water_mark(struct ctl_table *ctl, int write, ++static int nss_n2h_set_paged_water_mark(compat_const struct ctl_table *ctl, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos, + uint32_t core_num, int *low, int *high) +@@ -776,7 +776,7 @@ failure: + * nss_n2h_cfg_wifi_pool() + * Sets number of wifi payloads to adjust high water mark for N2H SoS + */ +-static int nss_n2h_cfg_wifi_pool(struct ctl_table *ctl, int write, ++static int nss_n2h_cfg_wifi_pool(compat_const struct ctl_table *ctl, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos, + int *payloads) +@@ -873,7 +873,7 @@ failure: + * nss_n2h_empty_pool_buf_core1_handler() + * Sets the number of empty buffer for core 1 + */ +-static int nss_n2h_empty_pool_buf_cfg_core1_handler(struct ctl_table *ctl, ++static int nss_n2h_empty_pool_buf_cfg_core1_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -885,7 +885,7 @@ static int nss_n2h_empty_pool_buf_cfg_co + * nss_n2h_empty_pool_buf_core0_handler() + * Sets the number of empty buffer for core 0 + */ +-static int nss_n2h_empty_pool_buf_cfg_core0_handler(struct ctl_table *ctl, ++static int nss_n2h_empty_pool_buf_cfg_core0_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -897,7 +897,7 @@ static int nss_n2h_empty_pool_buf_cfg_co + * nss_n2h_empty_paged_pool_buf_cfg_core1_handler() + * Sets the number of empty paged buffer for core 1 + */ +-static int nss_n2h_empty_paged_pool_buf_cfg_core1_handler(struct ctl_table *ctl, ++static int nss_n2h_empty_paged_pool_buf_cfg_core1_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -909,7 +909,7 @@ static int nss_n2h_empty_paged_pool_buf_ + * nss_n2h_empty_paged_pool_buf_cfg_core0_handler() + * Sets the number of empty paged buffer for core 0 + */ +-static int nss_n2h_empty_paged_pool_buf_cfg_core0_handler(struct ctl_table *ctl, ++static int nss_n2h_empty_paged_pool_buf_cfg_core0_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -921,7 +921,7 @@ static int nss_n2h_empty_paged_pool_buf_ + * nss_n2h_water_mark_core1_handler() + * Sets water mark for core 1 + */ +-static int nss_n2h_water_mark_core1_handler(struct ctl_table *ctl, ++static int nss_n2h_water_mark_core1_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -934,7 +934,7 @@ static int nss_n2h_water_mark_core1_hand + * nss_n2h_water_mark_core0_handler() + * Sets water mark for core 0 + */ +-static int nss_n2h_water_mark_core0_handler(struct ctl_table *ctl, ++static int nss_n2h_water_mark_core0_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -947,7 +947,7 @@ static int nss_n2h_water_mark_core0_hand + * nss_n2h_paged_water_mark_core1_handler() + * Sets paged water mark for core 1 + */ +-static int nss_n2h_paged_water_mark_core1_handler(struct ctl_table *ctl, ++static int nss_n2h_paged_water_mark_core1_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -960,7 +960,7 @@ static int nss_n2h_paged_water_mark_core + * nss_n2h_paged_water_mark_core0_handler() + * Sets paged water mark for core 0 + */ +-static int nss_n2h_paged_water_mark_core0_handler(struct ctl_table *ctl, ++static int nss_n2h_paged_water_mark_core0_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -973,7 +973,7 @@ static int nss_n2h_paged_water_mark_core + * nss_n2h_wifi_payloads_handler() + * Sets number of wifi payloads + */ +-static int nss_n2h_wifi_payloads_handler(struct ctl_table *ctl, ++static int nss_n2h_wifi_payloads_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -1250,7 +1250,7 @@ failure: + * nss_mitigation_handler() + * Enable NSS MITIGATION + */ +-static int nss_n2h_mitigationcfg_core0_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_n2h_mitigationcfg_core0_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[NSS_CORE_0]; +@@ -1281,7 +1281,7 @@ static int nss_n2h_mitigationcfg_core0_h + * nss_mitigation_handler() + * Enable NSS MITIGATION + */ +-static int nss_n2h_mitigationcfg_core1_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_n2h_mitigationcfg_core1_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[NSS_CORE_1]; +@@ -1312,7 +1312,7 @@ static int nss_n2h_mitigationcfg_core1_h + * nss_buf_handler() + * Add extra NSS bufs from host memory + */ +-static int nss_n2h_buf_cfg_core0_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_n2h_buf_cfg_core0_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[NSS_CORE_0]; +@@ -1351,7 +1351,7 @@ static int nss_n2h_buf_cfg_core0_handler + * nss_n2h_buf_handler() + * Add extra NSS bufs from host memory + */ +-static int nss_n2h_buf_cfg_core1_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_n2h_buf_cfg_core1_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[NSS_CORE_1]; +@@ -1404,7 +1404,7 @@ static void nss_n2h_queue_limit_callback + * nss_n2h_set_queue_limit_sync() + * Sets the n2h queue size limit synchronously. + */ +-static int nss_n2h_set_queue_limit_sync(struct ctl_table *ctl, int write, void __user *buffer, ++static int nss_n2h_set_queue_limit_sync(compat_const struct ctl_table *ctl, int write, void __user *buffer, + size_t *lenp, loff_t *ppos, uint32_t core_id) + { + struct nss_top_instance *nss_top = &nss_top_main; +@@ -1481,7 +1481,7 @@ static int nss_n2h_set_queue_limit_sync( + * nss_n2h_queue_limit_core0_handler() + * Sets the n2h queue size limit for core0 + */ +-static int nss_n2h_queue_limit_core0_handler(struct ctl_table *ctl, ++static int nss_n2h_queue_limit_core0_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -1493,7 +1493,7 @@ static int nss_n2h_queue_limit_core0_han + * nss_n2h_queue_limit_core1_handler() + * Sets the n2h queue size limit for core1 + */ +-static int nss_n2h_queue_limit_core1_handler(struct ctl_table *ctl, ++static int nss_n2h_queue_limit_core1_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -1571,7 +1571,7 @@ static nss_tx_status_t nss_n2h_host_bp_c + * nss_n2h_host_bp_cfg_handler() + * Enable n2h back pressure. + */ +-static int nss_n2h_host_bp_cfg_handler(struct ctl_table *ctl, int write, ++static int nss_n2h_host_bp_cfg_handler(compat_const struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos, uint32_t core_id) + { + struct nss_top_instance *nss_top = &nss_top_main; +@@ -1609,7 +1609,7 @@ static int nss_n2h_host_bp_cfg_handler(s + * nss_n2h_host_bp_cfg_core0_handler() + * Enable n2h back pressure in core 0. + */ +-static int nss_n2h_host_bp_cfg_core0_handler(struct ctl_table *ctl, int write, ++static int nss_n2h_host_bp_cfg_core0_handler(compat_const struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) + { + return nss_n2h_host_bp_cfg_handler(ctl, write, buffer, lenp, ppos, NSS_CORE_0); +@@ -1619,7 +1619,7 @@ static int nss_n2h_host_bp_cfg_core0_han + * nss_n2h_host_bp_cfg_core1_handler() + * Enable n2h back pressure in core 1. + */ +-static int nss_n2h_host_bp_cfg_core1_handler(struct ctl_table *ctl, int write, ++static int nss_n2h_host_bp_cfg_core1_handler(compat_const struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) + { + return nss_n2h_host_bp_cfg_handler(ctl, write, buffer, lenp, ppos, NSS_CORE_1); +@@ -1702,9 +1702,7 @@ static struct ctl_table nss_n2h_table_si + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_n2h_host_bp_cfg_core0_handler, +- }, +- +- { } ++ } + }; + + static struct ctl_table nss_n2h_table_multi_core[] = { +@@ -1855,8 +1853,7 @@ static struct ctl_table nss_n2h_table_mu + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_n2h_host_bp_cfg_core1_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_n2h_header; +--- a/nss_ppe_vp.c ++++ b/nss_ppe_vp.c +@@ -215,7 +215,7 @@ static void nss_ppe_vp_callback(void *ap + * Since ath0 has only one type i.e. ath0 is NSS_DYNAMIC_INTERFACE_TYPE_VAP, the above command can be rewritten as + * echo ath0 > /proc/sys/nss/ppe_vp/create => Here 6 can be ignored. + */ +-static nss_if_num_t nss_ppe_vp_parse_vp_cmd(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static nss_if_num_t nss_ppe_vp_parse_vp_cmd(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int32_t if_num; + struct net_device *dev; +@@ -693,7 +693,7 @@ static void nss_ppe_vp_handler(struct ns + * nss_ppe_vp_destroy_handler() + * PPE VP destroy handler. + */ +-static int nss_ppe_vp_destroy_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ppe_vp_destroy_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_ctx_instance *nss_ctx = nss_ppe_vp_get_context(); + int32_t if_num; +@@ -730,7 +730,7 @@ static int nss_ppe_vp_destroy_handler(st + * nss_ppe_vp_create_handler() + * PPE VP create handler. + */ +-static int nss_ppe_vp_create_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ppe_vp_create_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int32_t if_num; + struct nss_ctx_instance *nss_ctx = nss_ppe_vp_get_context(); +@@ -779,8 +779,7 @@ static struct ctl_table nss_ppe_vp_table + .maxlen = sizeof(nss_ppe_vp_cmd), + .mode = 0644, + .proc_handler = &nss_ppe_vp_destroy_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_ppe_vp_procfs_header; +--- a/nss_pppoe.c ++++ b/nss_pppoe.c +@@ -203,7 +203,7 @@ static void nss_pppoe_handler(struct nss + * nss_pppoe_br_accel_mode_handler() + * Enable/disable pppoe bridge acceleration in NSS + */ +-int nss_pppoe_br_accel_mode_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++int nss_pppoe_br_accel_mode_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_ctx_instance *nss_ctx = nss_pppoe_get_context(); + struct nss_pppoe_msg npm; +@@ -349,8 +349,7 @@ static struct ctl_table nss_pppoe_table[ + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_pppoe_br_accel_mode_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_pppoe_header; +--- a/nss_project.c ++++ b/nss_project.c +@@ -229,7 +229,7 @@ static void nss_project_msg_handler(stru + * Uses proc_dointvec to process data. For a write operation, also sends worker + * thread stats enable messages containing the new value to each NSS core. + */ +-static int nss_project_wt_stats_handler(struct ctl_table *ctl, int write, ++static int nss_project_wt_stats_handler(compat_const struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; +@@ -275,8 +275,7 @@ static struct ctl_table nss_project_tabl + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_project_wt_stats_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_project_header; +--- a/nss_rps.c ++++ b/nss_rps.c +@@ -401,7 +401,7 @@ static nss_tx_status_t nss_rps_pri_map_c + * nss_rps_cfg_handler() + * Enable NSS RPS. + */ +-static int nss_rps_cfg_handler(struct ctl_table *ctl, int write, ++static int nss_rps_cfg_handler(compat_const struct ctl_table *ctl, int write, + void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; +@@ -452,7 +452,7 @@ static int nss_rps_cfg_handler(struct ct + * nss_rps_hash_bitmap_cfg_handler() + * Configure NSS rps_hash_bitmap + */ +-static int nss_rps_hash_bitmap_cfg_handler(struct ctl_table *ctl, int write, ++static int nss_rps_hash_bitmap_cfg_handler(compat_const struct ctl_table *ctl, int write, + void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; +@@ -515,7 +515,7 @@ static int nss_rps_hash_bitmap_cfg_handl + /* nss_rps_pri_map_cfg_handler() + * Configure NSS rps_pri_map + */ +-static int nss_rps_pri_map_cfg_handler(struct ctl_table *ctl, int write, ++static int nss_rps_pri_map_cfg_handler(compat_const struct ctl_table *ctl, int write, + void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; +@@ -568,8 +568,7 @@ static struct ctl_table nss_rps_table[] + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_rps_pri_map_cfg_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_rps_header; +--- a/nss_core.h ++++ b/nss_core.h +@@ -990,7 +990,7 @@ extern void nss_stats_clean(void); + */ + extern void nss_log_init(void); + extern bool nss_debug_log_buffer_alloc(uint8_t nss_id, uint32_t nentry); +-extern int nss_logbuffer_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos); ++extern int nss_logbuffer_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos); + + /* + * APIs to set jumbo_mru & paged_mode +--- a/nss_dscp_map.h ++++ b/nss_dscp_map.h +@@ -46,7 +46,7 @@ struct nss_dscp_map_parse { + * nss_dscp_map_print() + * Sysctl handler for printing dscp/pri mapping. + */ +-static int nss_dscp_map_print(struct ctl_table *ctl, void *buffer, size_t *lenp, ++static int nss_dscp_map_print(compat_const struct ctl_table *ctl, void *buffer, size_t *lenp, + loff_t *ppos, struct nss_dscp_map_entry *mapping) + { + char *r_buf; +@@ -115,7 +115,7 @@ static int nss_dscp_map_print(struct ctl + * nss_dscp_map_parse() + * Sysctl handler for dscp/pri mappings. + */ +-static int nss_dscp_map_parse(struct ctl_table *ctl, void *buffer, size_t *lenp, ++static int nss_dscp_map_parse(compat_const struct ctl_table *ctl, void *buffer, size_t *lenp, + loff_t *ppos, struct nss_dscp_map_parse *out) + { + int count; +--- a/nss_n2h_stats.c ++++ b/nss_n2h_stats.c +@@ -43,6 +43,7 @@ static ssize_t nss_n2h_stats_read(struct + size_t size_wr = 0; + ssize_t bytes_read = 0; + uint64_t *stats_shadow; ++ char n2h_tag[7]; + + char *lbuf = kzalloc(size_al, GFP_KERNEL); + if (unlikely(lbuf == NULL)) { +@@ -66,7 +67,8 @@ static ssize_t nss_n2h_stats_read(struct + stats_shadow[i] = nss_n2h_stats[core][i]; + } + spin_unlock_bh(&nss_top_main.stats_lock); +- size_wr += nss_stats_banner(lbuf, size_wr, size_al, "n2h", core); ++ snprintf(n2h_tag, 7, "N2H %d", core); ++ size_wr += nss_stats_banner(lbuf, size_wr, size_al, n2h_tag, NSS_STATS_SINGLE_CORE); + size_wr += nss_stats_print("n2h", NULL, NSS_STATS_SINGLE_INSTANCE + , nss_n2h_strings_stats + , stats_shadow diff --git a/qca-nss-drv/patches-11.4/0026-treewide-fix-compiler-warnings.patch b/qca-nss-drv/patches-11.4/0026-treewide-fix-compiler-warnings.patch new file mode 100644 index 0000000..55906e9 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0026-treewide-fix-compiler-warnings.patch @@ -0,0 +1,102 @@ +--- a/nss_core.c ++++ b/nss_core.c +@@ -2215,12 +2215,16 @@ static void nss_core_handle_cause_nonque + * of processor will prevent any excessive penalties. + */ + if (unlikely(nss_ctx->state == NSS_CORE_STATE_UNINITIALIZED)) { ++#ifdef NSS_DRV_C2C_ENABLE + struct nss_top_instance *nss_top = NULL; ++#endif + nss_core_init_nss(nss_ctx, if_map); + nss_send_ddr_info(nss_ctx); + + dev_info(nss_ctx->dev, "NSS core %d booted successfully\n", nss_ctx->id); ++#ifdef NSS_DRV_C2C_ENABLE + nss_top = nss_ctx->nss_top; ++#endif + + #ifdef NSS_DRV_C2C_ENABLE + #if (NSS_MAX_CORES > 1) +--- a/nss_edma_stats.c ++++ b/nss_edma_stats.c +@@ -575,9 +575,8 @@ void nss_edma_stats_dentry_create(void) + /* + * edma error stats + */ +- edma_err_stats_d = NULL; + edma_err_stats_d = debugfs_create_file("err_stats", 0400, edma_d, &nss_top_main, &nss_edma_err_stats_ops); +- if (unlikely(edma_port_stats_d == NULL)) { ++ if (unlikely(edma_err_stats_d == NULL)) { + nss_warning("Failed to create qca-nss-drv/stats/edma/%d/err_stats file", 0); + return; + } +--- a/nss_match.c ++++ b/nss_match.c +@@ -244,7 +244,7 @@ EXPORT_SYMBOL(nss_match_unregister_insta + * nss_match_register_instance() + * Registers match instance. + */ +-struct nss_ctx_instance *nss_match_register_instance(int if_num, nss_match_msg_sync_callback_t notify_cb) ++struct nss_ctx_instance *nss_match_register_instance(int if_num, void (*notify_cb)(void *, struct nss_cmn_msg *)) + { + struct nss_ctx_instance *nss_ctx; + uint32_t status; +@@ -258,7 +258,7 @@ struct nss_ctx_instance *nss_match_regis + } + + nss_core_register_handler(nss_ctx, if_num, nss_match_handler, NULL); +- status = nss_core_register_msg_handler(nss_ctx, if_num, (nss_if_rx_msg_callback_t)notify_cb); ++ status = nss_core_register_msg_handler(nss_ctx, if_num, notify_cb); + if (status != NSS_CORE_STATUS_SUCCESS) { + nss_warning("%px: Not able to register handler for interface %d with NSS core\n", nss_ctx, if_num); + return NULL; +@@ -290,7 +290,7 @@ EXPORT_SYMBOL(nss_match_msg_init); + * nss_match_init() + * Initialize match. + */ +-void nss_match_init() ++void nss_match_init(void) + { + nss_match_stats_dentry_create(); + nss_match_strings_dentry_create(); +--- a/nss_map_t.c ++++ b/nss_map_t.c +@@ -378,7 +378,7 @@ EXPORT_SYMBOL(nss_map_t_unregister_if); + /* + * nss_get_map_t_context() + */ +-struct nss_ctx_instance *nss_map_t_get_context() ++struct nss_ctx_instance *nss_map_t_get_context(void) + { + return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.map_t_handler_id]; + } +--- a/exports/nss_match.h ++++ b/exports/nss_match.h +@@ -247,7 +247,7 @@ extern struct nss_ctx_instance *nss_matc + * @return + * Pointer to the NSS core context. + */ +-extern struct nss_ctx_instance *nss_match_register_instance(int if_num, nss_match_msg_sync_callback_t notify_cb); ++extern struct nss_ctx_instance *nss_match_register_instance(int if_num, void (*notify_cb)(void *, struct nss_cmn_msg *)); + + /** + * nss_match_unregister_instance +--- a/nss_lag.c ++++ b/nss_lag.c +@@ -237,7 +237,7 @@ nss_tx_status_t nss_lag_tx_slave_state(u + struct nss_lag_pvt lag_msg_state; + + init_completion(&lag_msg_state.complete); +- lag_msg_state.response = false; ++ lag_msg_state.response = NSS_CMN_RESPONSE_ACK; + + /* + * Construct a message to the NSS to update it +@@ -268,6 +268,6 @@ nss_tx_status_t nss_lag_tx_slave_state(u + return NSS_TX_FAILURE; + } + +- return lag_msg_state.response; ++ return (nss_tx_status_t)lag_msg_state.response; + } + EXPORT_SYMBOL(nss_lag_tx_slave_state); diff --git a/qca-nss-drv/patches-11.4/0027-Makefile-set-rearrange-arch-features.patch b/qca-nss-drv/patches-11.4/0027-Makefile-set-rearrange-arch-features.patch new file mode 100644 index 0000000..8a71b97 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0027-Makefile-set-rearrange-arch-features.patch @@ -0,0 +1,75 @@ +--- a/Makefile ++++ b/Makefile +@@ -123,12 +123,14 @@ qca-nss-drv-objs += \ + endif + endif + ++ifeq ($(SoC),$(filter $(SoC),ipq806x)) + ifneq "$(NSS_DRV_TSTAMP_ENABLE)" "n" + ccflags-y += -DNSS_DRV_TSTAMP_ENABLE + qca-nss-drv-objs += \ + nss_tstamp.o \ + nss_tstamp_stats.o + endif ++endif + + ifneq "$(NSS_DRV_GRE_ENABLE)" "n" + ccflags-y += -DNSS_DRV_GRE_ENABLE +@@ -248,6 +250,7 @@ qca-nss-drv-objs += \ + nss_rmnet_rx_stats.o + endif + ++ifeq ($(SoC),$(filter $(SoC),ipq806x)) + ifneq "$(NSS_DRV_PORTID_ENABLE)" "n" + ccflags-y += -DNSS_DRV_PORTID_ENABLE + qca-nss-drv-objs += \ +@@ -255,6 +258,7 @@ qca-nss-drv-objs += \ + nss_portid_log.o \ + nss_portid_stats.o + endif ++endif + + ifneq "$(NSS_DRV_IGS_ENABLE)" "n" + ccflags-y += -DNSS_DRV_IGS_ENABLE +@@ -263,12 +267,14 @@ qca-nss-drv-objs += \ + nss_igs_stats.o + endif + ++ifeq ($(SoC),$(filter $(SoC),ipq806x)) + ifneq "$(NSS_DRV_OAM_ENABLE)" "n" + ccflags-y += -DNSS_DRV_OAM_ENABLE + qca-nss-drv-objs += \ + nss_oam.o \ + nss_oam_log.o + endif ++endif + + ifneq "$(NSS_DRV_CLMAP_ENABLE)" "n" + ccflags-y += -DNSS_DRV_CLMAP_ENABLE +@@ -343,16 +349,13 @@ endif + + ifneq "$(NSS_DRV_WIFIOFFLOAD_ENABLE)" "n" + ccflags-y += -DNSS_DRV_WIFIOFFLOAD_ENABLE +-ifneq "$(NSS_DRV_WIFI_LEGACY_ENABLE)" "n" +-ccflags-y += -DNSS_DRV_WIFI_LEGACY_ENABLE ++ifeq ($(SoC),$(filter $(SoC),ipq806x)) + qca-nss-drv-objs += \ + nss_wifi.o \ + nss_wifi_log.o \ + nss_wifi_stats.o +-ifeq ($(SoC),$(filter $(SoC),ipq806x)) + ccflags-y += -DNSS_HAL_IPQ806x_SUPPORT +-endif +-endif ++else + qca-nss-drv-objs += \ + nss_wifi_vdev.o \ + nss_wifili.o \ +@@ -361,6 +364,7 @@ qca-nss-drv-objs += \ + nss_wifili_strings.o \ + nss_wifi_mac_db.o + endif ++endif + + ifneq "$(NSS_DRV_VLAN_ENABLE)" "n" + ccflags-y += -DNSS_DRV_VLAN_ENABLE diff --git a/qca-nss-drv/patches-11.4/0027-nss-drv-fix-null-ptr-log.patch b/qca-nss-drv/patches-11.4/0027-nss-drv-fix-null-ptr-log.patch new file mode 100644 index 0000000..7dc7a67 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0027-nss-drv-fix-null-ptr-log.patch @@ -0,0 +1,46 @@ +--- a/nss_bridge_log.c ++++ b/nss_bridge_log.c +@@ -99,7 +99,7 @@ static void nss_bridge_log_verbose(struc + */ + void nss_bridge_log_tx_msg(struct nss_bridge_msg *nbm) + { +- if (nbm->cm.type >= NSS_BRIDGE_MSG_TYPE_MAX) { ++ if (nbm->cm.type < (NSS_IF_MAX_MSG_TYPES + 1) || nbm->cm.type >= (NSS_IF_MAX_MSG_TYPES + NSS_BRIDGE_MSG_TYPE_MAX + 1)) { + nss_warning("%px: Invalid message type\n", nbm); + return; + } +@@ -119,6 +119,11 @@ void nss_bridge_log_rx_msg(struct nss_br + return; + } + ++ if (nbm->cm.type < (NSS_IF_MAX_MSG_TYPES + 1) || nbm->cm.type >= (NSS_IF_MAX_MSG_TYPES + NSS_BRIDGE_MSG_TYPE_MAX + 1)) { ++ nss_warning("%px: Invalid message type\n", nbm); ++ return; ++ } ++ + if (nbm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nbm->cm.response == NSS_CMN_RESPONSE_ACK)) { + nss_info("%px: type[%d]:%s, response[%d]:%s\n", nbm, nbm->cm.type, + nss_bridge_log_message_types_str[nbm->cm.type - NSS_IF_MAX_MSG_TYPES - 1], +--- a/nss_gre_log.c ++++ b/nss_gre_log.c +@@ -151,7 +151,7 @@ static void nss_gre_log_verbose(struct n + */ + void nss_gre_log_tx_msg(struct nss_gre_msg *ngm) + { +- if (ngm->cm.type >= NSS_GRE_MSG_MAX) { ++ if (ngm->cm.type < (NSS_IF_MAX_MSG_TYPES + 1) || ngm->cm.type >= (NSS_IF_MAX_MSG_TYPES + NSS_GRE_MSG_MAX + 1)) { + nss_warning("%px: Invalid message type\n", ngm); + return; + } +@@ -171,6 +171,11 @@ void nss_gre_log_rx_msg(struct nss_gre_m + return; + } + ++ if (ngm->cm.type < (NSS_IF_MAX_MSG_TYPES + 1) || ngm->cm.type >= (NSS_IF_MAX_MSG_TYPES + NSS_GRE_MSG_MAX + 1)) { ++ nss_warning("%px: Invalid message type\n", ngm); ++ return; ++ } ++ + if (ngm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ngm->cm.response == NSS_CMN_RESPONSE_ACK)) { + nss_info("%px: type[%d]:%s, response[%d]:%s\n", ngm, ngm->cm.type, + nss_gre_log_message_types_str[NSS_GRE_LOG_MESSAGE_TYPE_INDEX(ngm->cm.type)], diff --git a/qca-nss-drv/patches-11.4/0028-backport-12.5-fix-greredir-stats-partial-copy.patch b/qca-nss-drv/patches-11.4/0028-backport-12.5-fix-greredir-stats-partial-copy.patch new file mode 100644 index 0000000..1bfd963 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0028-backport-12.5-fix-greredir-stats-partial-copy.patch @@ -0,0 +1,170 @@ +From 472f636bb62f53312d170d28df8961cbfb7479d4 Mon Sep 17 00:00:00 2001 +From: Nitin Shetty +Date: Wed, 22 Nov 2023 19:24:58 +0530 +Subject: [PATCH 07/31] [qca-nss-drv] fix greredir stats partial copy issue. + +If the kernel passes smaller user buffer to copy stats +than required, copy the partial content from local buffer +and in next call copy the remaining content. + +Change-Id: Ice199d193ddb098407de5876a63fff8380894408 +Signed-off-by: Nitin Shetty +--- + nss_core.h | 10 +++++ + nss_gre_redir_stats.c | 90 ++++++++++++++++++++++++++++++++++++------- + 2 files changed, 86 insertions(+), 14 deletions(-) + +--- a/nss_core.h ++++ b/nss_core.h +@@ -504,6 +504,15 @@ struct nss_ctx_instance { + }; + + /* ++ * NSS stats read context ++ */ ++struct nss_stats_buff { ++ uint16_t msg_len; /* Length of message copied */ ++ char *msg_base_ptr; /* base buffer pointer */ ++ char *msg_cur_ptr; /* current buffer pointer */ ++}; ++ ++/* + * Main NSS context structure (singleton) + */ + struct nss_top_instance { +@@ -679,6 +688,7 @@ struct nss_top_instance { + struct nss_hal_ops *hal_ops; /* nss_hal ops for this target platform */ + struct nss_data_plane_ops *data_plane_ops; + /* nss_data_plane ops for this target platform */ ++ struct nss_stats_buff stats_buff; + }; + + #if (NSS_PKT_STATS_ENABLED == 1) +--- a/nss_gre_redir_stats.c ++++ b/nss_gre_redir_stats.c +@@ -53,6 +53,38 @@ bool nss_gre_redir_stats_get(int index, + EXPORT_SYMBOL(nss_gre_redir_stats_get); + + /* ++ * nss_gre_redir_stats_copy_rem_buf() ++ * Copy the local buffer to kernel user buffer ++ */ ++static int nss_gre_redir_stats_copy_rem_buf(struct nss_stats_buff *ws, char *buffer, ++ size_t length, int *total_read) ++{ ++ int bytes_read; ++ int return_value = 0; ++ ++ bytes_read = ws->msg_len; ++ ++ /* ++ * Calculate total bytes read to the current buffer ++ */ ++ if ((bytes_read + *total_read) >= length) { ++ bytes_read = length - *total_read; ++ return_value = -ENOMEM; ++ } ++ ++ if (copy_to_user(buffer + *total_read, ws->msg_cur_ptr, bytes_read)) { ++ return -EFAULT; ++ } ++ ++ ws->msg_len -= bytes_read; ++ ws->msg_cur_ptr += bytes_read; ++ ++ *total_read += bytes_read; ++ ++ return return_value; ++} ++ ++/* + * nss_gre_redir_stats_read() + * READ gre_redir tunnel stats. + */ +@@ -67,14 +99,27 @@ static ssize_t nss_gre_redir_stats_read( + size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines * NSS_GRE_REDIR_MAX_INTERFACES; + struct nss_stats_data *data = fp->private_data; + struct nss_gre_redir_tunnel_stats stats; +- ssize_t bytes_read = 0; +- size_t size_wr = 0; ++ struct nss_stats_buff *ws; ++ int bytes_read = 0; + int index = 0; ++ int status = 0; ++ ++ size_al = PAGE_SIZE; ++ ++ ws = (struct nss_stats_buff *)&nss_top_main.stats_buff; + +- char *lbuf = kzalloc(size_al, GFP_KERNEL); +- if (unlikely(!lbuf)) { +- nss_warning("Could not allocate memory for local statistics buffer"); +- return 0; ++ if (ws->msg_len) { ++ status = nss_gre_redir_stats_copy_rem_buf(ws, ubuf, sz, &bytes_read); ++ if (status < 0) { ++ goto done; ++ } ++ } else { ++ ws->msg_base_ptr = kmalloc(size_al, GFP_KERNEL); ++ if (!ws->msg_base_ptr) { ++ nss_warning("Could not allocate memory for local statistics buffer"); ++ return -ENOMEM; ++ } ++ ws->msg_cur_ptr = ws->msg_base_ptr; + } + + if (data) { +@@ -85,8 +130,7 @@ static ssize_t nss_gre_redir_stats_read( + * If we are done accomodating all the GRE_REDIR tunnels. + */ + if (index >= NSS_GRE_REDIR_MAX_INTERFACES) { +- kfree(lbuf); +- return 0; ++ goto done; + } + + for (; index < NSS_GRE_REDIR_MAX_INTERFACES; index++) { +@@ -100,18 +144,36 @@ static ssize_t nss_gre_redir_stats_read( + continue; + } + +- size_wr += nss_stats_banner(lbuf, size_wr, size_al, "gre_redir stats", NSS_STATS_SINGLE_CORE); +- size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nTunnel stats for %s\n", stats.dev->name); +- size_wr += nss_stats_print("gre_redir", NULL, NSS_STATS_SINGLE_INSTANCE, nss_gre_redir_strings_stats, +- &stats.tstats.rx_packets, NSS_GRE_REDIR_STATS_MAX, lbuf, size_wr, size_al); ++ ws->msg_cur_ptr = ws->msg_base_ptr; ++ ++ ws->msg_len = nss_stats_banner(ws->msg_base_ptr, ws->msg_len, size_al, "gre_redir stats", NSS_STATS_SINGLE_CORE); ++ ws->msg_len += scnprintf(ws->msg_base_ptr + ws->msg_len, size_al - ws->msg_len, "\nTunnel stats for %s\n", stats.dev->name); ++ ws->msg_len += nss_stats_print("gre_redir", NULL, NSS_STATS_SINGLE_INSTANCE, nss_gre_redir_strings_stats, ++ &stats.tstats.rx_packets, NSS_GRE_REDIR_STATS_MAX, ws->msg_base_ptr, ws->msg_len, size_al); ++ ++ status = nss_gre_redir_stats_copy_rem_buf(ws, ubuf, sz, &bytes_read); ++ ++ if (status < 0) { ++ index++; ++ break; ++ } ++ + } + +- bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf)); + if (data) { + data->index = index; + } + +- kfree(lbuf); ++done: ++ if (status == -EFAULT) { ++ bytes_read = -EFAULT; ++ } ++ ++ if (!ws->msg_len && ws->msg_base_ptr) { ++ kfree(ws->msg_base_ptr); ++ ws->msg_base_ptr = NULL; ++ } ++ + return bytes_read; + } + diff --git a/qca-nss-drv/patches-11.4/0028-nss_ppe_vp-fix-create-destroy.patch b/qca-nss-drv/patches-11.4/0028-nss_ppe_vp-fix-create-destroy.patch new file mode 100644 index 0000000..ebbbfec --- /dev/null +++ b/qca-nss-drv/patches-11.4/0028-nss_ppe_vp-fix-create-destroy.patch @@ -0,0 +1,57 @@ +--- a/nss_ppe_vp.c ++++ b/nss_ppe_vp.c +@@ -96,8 +96,8 @@ static void nss_ppe_vp_proc_help(void) + { + nss_info_always("== for dynamic interface types read following file =="); + nss_info_always("/sys/kernel/debug/qca-nss-drv/stats/dynamic_if/type_names"); +- nss_info_always("NSS PPE VP create: echo > /proc/sys/nss/ppe_vp/create"); +- nss_info_always("NSS PPE VP destroy: echo > /proc/sys/nss/ppe_vp/destroy"); ++ nss_info_always("NSS PPE VP create: echo > /proc/sys/dev/nss/ppe_vp/create"); ++ nss_info_always("NSS PPE VP destroy: echo > /proc/sys/dev/nss/ppe_vp/destroy"); + } + + /* +@@ -210,20 +210,19 @@ static void nss_ppe_vp_callback(void *ap + * nss_ppe_vp_parse_vp_cmd() + * Parse PPE VP create and destroy message and return the NSS interface number. + * Command usage: +- * echo /proc/sys/nss/ppe_vp/create> +- * echo ath0 6 > /proc/sys/nss/ppe_vp/create ++ * echo /proc/sys/dev/nss/ppe_vp/create> ++ * echo ath0 6 > /proc/sys/dev/nss/ppe_vp/create + * Since ath0 has only one type i.e. ath0 is NSS_DYNAMIC_INTERFACE_TYPE_VAP, the above command can be rewritten as +- * echo ath0 > /proc/sys/nss/ppe_vp/create => Here 6 can be ignored. ++ * echo ath0 > /proc/sys/dev/nss/ppe_vp/create => Here 6 can be ignored. + */ + static nss_if_num_t nss_ppe_vp_parse_vp_cmd(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int32_t if_num; + struct net_device *dev; +- uint32_t dynamic_if_type = (uint32_t)NSS_DYNAMIC_INTERFACE_TYPE_NONE; ++ uint32_t dynamic_if_type = (uint32_t)NSS_DYNAMIC_INTERFACE_TYPE_NONE; + struct nss_ctx_instance *nss_ctx = nss_ppe_vp_get_context(); + char *pos; + char cmd_buf[NSS_PPE_VP_MAX_CMD_STR] = {0}, dev_name[NSS_PPE_VP_MAX_CMD_STR] = {0}; +- size_t count = *lenp; + int ret = proc_dostring(ctl, write, buffer, lenp, ppos); + + if (!write) { +@@ -238,17 +237,7 @@ static nss_if_num_t nss_ppe_vp_parse_vp_ + + NSS_VERIFY_CTX_MAGIC(nss_ctx); + +- if (count >= NSS_PPE_VP_MAX_CMD_STR) { +- nss_ppe_vp_proc_help(); +- nss_warning("%px: Input string too big", nss_ctx); +- return -E2BIG; +- } +- +- if (copy_from_user(cmd_buf, buffer, count)) { +- nss_warning("%px: Cannot copy user's entry to kernel memory", nss_ctx); +- return -EFAULT; +- } +- ++ /* proc_dostring has already copied the data to nss_ppe_vp_cmd */ + if ((pos = strrchr(cmd_buf, '\n')) != NULL) { + *pos = '\0'; + } diff --git a/qca-nss-drv/patches-11.4/0029-backport-12.5-baseline-stats-write-functionality.patch b/qca-nss-drv/patches-11.4/0029-backport-12.5-baseline-stats-write-functionality.patch new file mode 100644 index 0000000..09ec68b --- /dev/null +++ b/qca-nss-drv/patches-11.4/0029-backport-12.5-baseline-stats-write-functionality.patch @@ -0,0 +1,1677 @@ +--- a/exports/nss_capwap.h ++++ b/exports/nss_capwap.h +@@ -595,6 +595,17 @@ extern uint32_t nss_capwap_get_max_buf_s + extern bool nss_capwap_get_stats(uint32_t if_num, struct nss_capwap_tunnel_stats *stats); + + /** ++ * nss_capwap_clear_stats ++ * Gets per-tunnel statistics. ++ * ++ * @param[in] if_num NSS interface number. ++ * ++ * @return ++ * TRUE or FALSE. ++ */ ++extern bool nss_capwap_clear_stats(uint32_t if_num); ++ ++/** + * nss_capwap_init + * Initializes the CAPWAP interface. + * +--- a/nss_c2c_rx_stats.c ++++ b/nss_c2c_rx_stats.c +@@ -90,6 +90,36 @@ static ssize_t nss_c2c_rx_stats_read(str + } + + /* ++ * nss_c2c_rx_stats_write() ++ * Write c2c_rx stats ++ */ ++static ssize_t nss_c2c_rx_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ int32_t i, core; ++ uint32_t reset; ++ ++ if (kstrtou32_from_user(ubuf, sz, 0, &reset)) { ++ return -EINVAL; ++ } ++ ++ if (reset != 0) { ++ return -EINVAL; ++ } ++ ++ /* ++ * c2c_rx node stats ++ */ ++ for (core = 0; core < NSS_MAX_CORES; core++) { ++ spin_lock_bh(&nss_c2c_rx_stats_lock); ++ for (i = 0; i < NSS_C2C_RX_STATS_MAX; i++) { ++ nss_c2c_rx_stats[core][i] = 0; ++ } ++ spin_unlock_bh(&nss_c2c_rx_stats_lock); ++ } ++ return sz; ++} ++ ++/* + * nss_c2c_rx_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(c2c_rx); +--- a/nss_c2c_tx_stats.c ++++ b/nss_c2c_tx_stats.c +@@ -84,6 +84,35 @@ static ssize_t nss_c2c_tx_stats_read(str + + return bytes_read; + } ++/* ++ * nss_c2c_tx_stats_write() ++ * Write c2c_tx stats ++ */ ++static ssize_t nss_c2c_tx_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ int32_t i, core; ++ uint32_t reset; ++ ++ if (kstrtou32_from_user(ubuf, sz, 0, &reset)) { ++ return -EINVAL; ++ } ++ ++ if (reset != 0) { ++ return -EINVAL; ++ } ++ ++ /* ++ * c2c_tx node stats ++ */ ++ for (core = 0; core < NSS_MAX_CORES; core++) { ++ spin_lock_bh(&nss_c2c_tx_stats_lock); ++ for (i = 0; i < NSS_C2C_TX_STATS_MAX; i++) { ++ nss_c2c_tx_stats[core][i] = 0; ++ } ++ spin_unlock_bh(&nss_c2c_tx_stats_lock); ++ } ++ return sz; ++} + + /* + * nss_c2c_tx_stats_ops +--- a/nss_capwap.c ++++ b/nss_capwap.c +@@ -162,6 +162,7 @@ static void nss_capwap_update_stats(stru + + switch(type) { + case NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER: ++ spin_lock_bh(&nss_capwap_spinlock); + stats->rx_segments += fstats->rx_segments; + stats->dtls_pkts += fstats->dtls_pkts; + stats->rx_dup_frag += fstats->rx_dup_frag; +@@ -180,9 +181,11 @@ static void nss_capwap_update_stats(stru + stats->pnode_stats.rx_packets += fstats->pnode_stats.rx_packets; + stats->pnode_stats.rx_bytes += fstats->pnode_stats.rx_bytes; + stats->pnode_stats.rx_dropped += nss_cmn_rx_dropped_sum(&fstats->pnode_stats); ++ spin_unlock_bh(&nss_capwap_spinlock); + break; + + case NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER: ++ spin_lock_bh(&nss_capwap_spinlock); + stats->tx_segments += fstats->tx_segments; + stats->tx_queue_full_drops += fstats->tx_queue_full_drops; + stats->tx_mem_failure_drops += fstats->tx_mem_failure_drops; +@@ -198,6 +201,7 @@ static void nss_capwap_update_stats(stru + stats->pnode_stats.tx_packets += fstats->pnode_stats.tx_packets; + stats->pnode_stats.tx_bytes += fstats->pnode_stats.tx_bytes; + stats->tx_dropped_inner += nss_cmn_rx_dropped_sum(&fstats->pnode_stats); ++ spin_unlock_bh(&nss_capwap_spinlock); + break; + + default: +@@ -384,6 +388,7 @@ bool nss_capwap_get_stats(uint32_t if_nu + spin_lock_bh(&nss_capwap_spinlock); + if (nss_capwap_hdl[if_num] == NULL) { + spin_unlock_bh(&nss_capwap_spinlock); ++ nss_warning("%px: unallocated if_num: %d", stats, if_num); + return false; + } + +@@ -394,6 +399,29 @@ bool nss_capwap_get_stats(uint32_t if_nu + EXPORT_SYMBOL(nss_capwap_get_stats); + + /* ++ * nss_capwap_clear_stats() ++ * API for clearing stats from a CAPWAP tunnel interface stats ++ */ ++bool nss_capwap_clear_stats(uint32_t if_num) ++{ ++ if (nss_capwap_verify_if_num(if_num) == false) { ++ return false; ++ } ++ ++ if_num = if_num - NSS_DYNAMIC_IF_START; ++ spin_lock_bh(&nss_capwap_spinlock); ++ if (nss_capwap_hdl[if_num] == NULL) { ++ spin_unlock_bh(&nss_capwap_spinlock); ++ nss_warning("unallocated if_num: %d", if_num); ++ return false; ++ } ++ ++ memset(&nss_capwap_hdl[if_num]->stats, 0, sizeof(struct nss_capwap_tunnel_stats)); ++ spin_unlock_bh(&nss_capwap_spinlock); ++ return true; ++} ++ ++/* + * nss_capwap_notify_register() + * Registers a message notifier with NSS FW. It should not be called from + * softirq or interrupts. +@@ -405,14 +433,14 @@ struct nss_ctx_instance *nss_capwap_noti + nss_ctx = &nss_top_main.nss[nss_top_main.capwap_handler_id]; + + if (nss_capwap_verify_if_num(if_num) == false) { +- nss_warning("%px: notfiy register received for invalid interface %d", nss_ctx, if_num); ++ nss_warning("%px: notify register received for invalid interface %d", nss_ctx, if_num); + return NULL; + } + + spin_lock_bh(&nss_capwap_spinlock); + if (nss_capwap_hdl[if_num - NSS_DYNAMIC_IF_START] != NULL) { + spin_unlock_bh(&nss_capwap_spinlock); +- nss_warning("%px: notfiy register tunnel already exists for interface %d", nss_ctx, if_num); ++ nss_warning("%px: notify register tunnel already exists for interface %d", nss_ctx, if_num); + return NULL; + } + spin_unlock_bh(&nss_capwap_spinlock); +--- a/nss_capwap_stats.c ++++ b/nss_capwap_stats.c +@@ -261,6 +261,91 @@ static ssize_t nss_capwap_encap_stats_re + } + + /* ++ * nss_capwap_stats_write() ++ * Write CAPWAP stats ++ */ ++static ssize_t nss_capwap_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos, uint16_t type) ++{ ++ struct nss_stats_data *data = fp->private_data; ++ uint32_t if_num = NSS_DYNAMIC_IF_START; ++ uint32_t max_if_num = NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES; ++ uint32_t reset; ++ ++ if (kstrtou32_from_user(ubuf, sz, 0, &reset)) ++ return -EINVAL; ++ ++ if (reset != 0) { ++ return -EINVAL; ++ } ++ ++ if (!data) { ++ nss_warning("%px:File private data is NULL", fp); ++ return -EINVAL; ++ } ++ ++ if (data) { ++ if_num = data->if_num; ++ } ++ ++ /* ++ * If we are done accomodating all the CAPWAP tunnels. ++ */ ++ if (if_num > max_if_num) { ++ return 0; ++ } ++ ++ for (; if_num <= max_if_num; if_num++) { ++ bool isthere; ++ enum nss_dynamic_interface_type dtype; ++ ++ if (nss_is_dynamic_interface(if_num) == false) { ++ continue; ++ } ++ ++ dtype = nss_dynamic_interface_get_type(nss_capwap_get_ctx(), if_num); ++ ++ /* ++ * Read encap stats from inner node and decap stats from outer node. ++ */ ++ if ((type == 1) && (dtype != NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER)) { ++ continue; ++ } ++ ++ if ((type == 0) && (dtype != NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER)) { ++ continue; ++ } ++ ++ /* ++ * If CAPWAP tunnel does not exists, then isthere will be false. ++ */ ++ isthere = nss_capwap_clear_stats(if_num); ++ if (!isthere) { ++ continue; ++ } ++ } ++ ++ return sz; ++} ++ ++/* ++ * nss_capwap_decap_stats_write() ++ * Write CAPWAP decap stats ++ */ ++static ssize_t nss_capwap_decap_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return nss_capwap_stats_write(fp, ubuf, sz, ppos, 0); ++} ++ ++/* ++ * nss_capwap_encap_stats_write() ++ * Write CAPWAP encap stats ++ */ ++static ssize_t nss_capwap_encap_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return nss_capwap_stats_write(fp, ubuf, sz, ppos, 1); ++} ++ ++/* + * nss_capwap_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(capwap_encap); +--- a/nss_clmap_stats.c ++++ b/nss_clmap_stats.c +@@ -233,6 +233,15 @@ void nss_clmap_stats_sync(struct nss_ctx + } + + /* ++ * nss_clmap_stats_write() ++ * Write CLMAP statistics ++ */ ++static ssize_t nss_clmap_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_clmap_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(clmap) +--- a/nss_core.h ++++ b/nss_core.h +@@ -91,12 +91,14 @@ + #define NSS_PKT_STATS_ADD(x, i) nss_pkt_stats_add((x), (i)) + #define NSS_PKT_STATS_SUB(x, i) nss_pkt_stats_sub((x), (i)) + #define NSS_PKT_STATS_READ(x) nss_pkt_stats_read(x) ++#define NSS_PKT_STATS_WRITE(x, i) nss_pkt_stats_write(x, (i)) + #else + #define NSS_PKT_STATS_INC(x) + #define NSS_PKT_STATS_DEC(x) + #define NSS_PKT_STATS_ADD(x, i) + #define NSS_PKT_STATS_SUB(x, i) + #define NSS_PKT_STATS_READ(x) ++#define NSS_PKT_STATS_WRITE(x, i) + #endif + + /* +@@ -732,6 +734,14 @@ static inline uint64_t nss_pkt_stats_rea + return atomic64_read(stat); + } + ++/* ++ * nss_pkt_stats_write() ++ */ ++static inline void nss_pkt_stats_write(atomic64_t *stat, uint32_t pkt) ++{ ++ atomic64_set(stat, pkt); ++} ++ + #endif + + /* +--- a/nss_crypto_cmn_stats.c ++++ b/nss_crypto_cmn_stats.c +@@ -86,6 +86,32 @@ static ssize_t nss_crypto_cmn_stats_read + } + + /* ++ * nss_crypto_cmn_stats_write() ++ * Write crypto common statistics ++ */ ++static ssize_t nss_crypto_cmn_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ int32_t i; ++ uint32_t reset; ++ ++ if (kstrtou32_from_user(ubuf, sz, 0, &reset)) { ++ return -EINVAL; ++ } ++ ++ if (reset != 0) { ++ return -EINVAL; ++ } ++ ++ spin_lock_bh(&nss_crypto_cmn_stats_lock); ++ for (i = 0; i < NSS_CRYPTO_CMN_STATS_MAX; i++) { ++ nss_crypto_cmn_stats[i] = 0; ++ } ++ ++ spin_unlock_bh(&nss_crypto_cmn_stats_lock); ++ return sz; ++} ++ ++/* + * nss_crypto_cmn_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(crypto_cmn); +--- a/nss_dma_stats.c ++++ b/nss_dma_stats.c +@@ -89,6 +89,15 @@ static ssize_t nss_dma_stats_read(struct + } + + /* ++ * nss_dma_stats_write() ++ * Write DMA statistics ++ */ ++static ssize_t nss_dma_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_dma_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(dma); +--- a/nss_drv_stats.c ++++ b/nss_drv_stats.c +@@ -64,6 +64,37 @@ static ssize_t nss_drv_stats_read(struct + } + + /* ++ * nss_drv_stats_write() ++ * Write DRV stats ++ */ ++static ssize_t nss_drv_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ int32_t i; ++ uint32_t reset; ++ ++ if (kstrtou32_from_user(ubuf, sz, 0, &reset)) { ++ return -EINVAL; ++ } ++ ++ if (reset != 0) { ++ return -EINVAL; ++ } ++ ++ /* ++ * DRV node stats ++ * SKB count is not a cumulative stats that accumulated over time. ++ * So, it shouldn't be reset. ++ */ ++ for (i = 0; (i < NSS_DRV_STATS_MAX); i++) { ++ if (i != NSS_DRV_STATS_NSS_SKB_COUNT) { ++ NSS_PKT_STATS_WRITE(&nss_top_main.stats_drv[i], 0); ++ } ++ } ++ ++ return sz; ++} ++ ++/* + * drv_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(drv); +@@ -164,3 +195,12 @@ ssize_t nss_wt_stats_read(struct file *f + + return bytes_read; + } ++ ++/* ++ * nss_wt_stats_write() ++ * Write WT statistics ++ */ ++ssize_t nss_wt_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} +--- a/nss_drv_stats.h ++++ b/nss_drv_stats.h +@@ -77,4 +77,5 @@ enum NSS_DRV_STATS { + + extern void nss_drv_stats_dentry_create(void); + extern ssize_t nss_wt_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos); ++extern ssize_t nss_wt_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos); + #endif /* __NSS_DRV_STATS_H */ +--- a/nss_dtls_cmn_stats.c ++++ b/nss_dtls_cmn_stats.c +@@ -131,6 +131,44 @@ static ssize_t nss_dtls_cmn_stats_read(s + } + + /* ++ * nss_dtls_cmn_stats_write() ++ * Write dtls common statistics ++ */ ++static ssize_t nss_dtls_cmn_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ int32_t i; ++ uint32_t reset; ++ enum nss_dynamic_interface_type type; ++ uint32_t if_num; ++ struct nss_ctx_instance *nss_ctx = nss_dtls_cmn_get_context(); ++ unsigned long *ifmap = nss_dtls_cmn_ifmap_get(); ++ ++ if (kstrtou32_from_user(ubuf, sz, 0, &reset)) { ++ return -EINVAL; ++ } ++ ++ if (reset != 0) { ++ return -EINVAL; ++ } ++ ++ for_each_set_bit(if_num, ifmap, NSS_MAX_NET_INTERFACES) { ++ ++ type = nss_dynamic_interface_get_type(nss_ctx, if_num); ++ if ((type != NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_INNER) && ++ (type != NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_OUTER)) { ++ continue; ++ } ++ ++ spin_lock_bh(&nss_dtls_cmn_stats_lock); ++ for (i = 0; i < NSS_DTLS_CMN_CTX_STATS_MAX; i++) { ++ nss_dtls_cmn_ctx_stats[if_num][i] = 0; ++ } ++ spin_unlock_bh(&nss_dtls_cmn_stats_lock); ++ } ++ return sz; ++} ++ ++/* + * nss_dtls_cmn_stats_ops. + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(dtls_cmn); +--- a/nss_dtls_stats.c ++++ b/nss_dtls_stats.c +@@ -129,6 +129,15 @@ static ssize_t nss_dtls_stats_read(struc + } + + /* ++ * nss_dtls_stats_write() ++ * Write DTLS statistics ++ */ ++static ssize_t nss_dtls_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_dtls_stats_ops. + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(dtls) +--- a/nss_dynamic_interface_stats.c ++++ b/nss_dynamic_interface_stats.c +@@ -139,6 +139,15 @@ static ssize_t nss_dynamic_interface_typ + } + + /* ++ * nss_dynamic_interface_type_names_stats_write() ++ * Write DYNAMIC_INTERFACE_TYPE_NAMES statistics ++ */ ++static ssize_t nss_dynamic_interface_type_names_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_dynamic_interface_type_names_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(dynamic_interface_type_names) +--- a/nss_edma_stats.c ++++ b/nss_edma_stats.c +@@ -464,6 +464,78 @@ static ssize_t nss_edma_err_stats_read(s + } + + /* ++ * nss_edma_port_stats_write() ++ * Write EDMA_PORT statistics ++ */ ++static ssize_t nss_edma_port_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_edma_port_type_stats_write() ++ * Write EDMA_PORT_TYPE statistics ++ */ ++static ssize_t nss_edma_port_type_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_edma_port_ring_map_stats_write() ++ * Write EDMA_PORT_RING_MAP statistics ++ */ ++static ssize_t nss_edma_port_ring_map_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_edma_txring_stats_write() ++ * Write EDMA_TXRING statistics ++ */ ++static ssize_t nss_edma_txring_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_edma_rxring_stats_write() ++ * Write EDMA_RXRING statistics ++ */ ++static ssize_t nss_edma_rxring_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_edma_txcmplring_stats_write() ++ * Write EDMA_TXCMPLRING statistics ++ */ ++static ssize_t nss_edma_txcmplring_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_edma_rxfillring_stats_write() ++ * Write EDMA_RXFILLRING statistics ++ */ ++static ssize_t nss_edma_rxfillring_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_edma_err_stats_write() ++ * Write EDMA_ERR statistics ++ */ ++static ssize_t nss_edma_err_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * edma_port_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(edma_port); +--- a/nss_eth_rx_stats.c ++++ b/nss_eth_rx_stats.c +@@ -105,6 +105,43 @@ static ssize_t nss_eth_rx_stats_read(str + } + + /* ++ * nss_eth_rx_stats_write() ++ * Write ETH_RX stats. ++ */ ++static ssize_t nss_eth_rx_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ int32_t i; ++ uint32_t reset; ++ struct nss_top_instance *nss_top = &nss_top_main; ++ ++ if (kstrtou32_from_user(ubuf, sz, 0, &reset)) { ++ return -EINVAL; ++ } ++ ++ if (reset != 0) { ++ return -EINVAL; ++ } ++ ++ /* ++ * eth_rx node stats. ++ */ ++ nss_stats_reset_common_stats(NSS_ETH_RX_INTERFACE); ++ ++ spin_lock_bh(&nss_top->stats_lock); ++ ++ for (i = 0; (i < NSS_ETH_RX_STATS_MAX); i++) { ++ nss_eth_rx_stats[i] = 0; ++ } ++ ++ for (i = 0; (i < NSS_ETH_RX_EXCEPTION_EVENT_MAX); i++) { ++ nss_eth_rx_exception_stats[i] = 0; ++ } ++ ++ spin_unlock_bh(&nss_top->stats_lock); ++ return sz; ++} ++ ++/* + * nss_eth_rx_stats_ops. + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(eth_rx); +--- a/nss_freq_stats.c ++++ b/nss_freq_stats.c +@@ -73,6 +73,15 @@ static ssize_t nss_freq_stats_read(struc + } + + /* ++ * nss_freq_stats_write() ++ * Write FREQ statistics ++ */ ++static ssize_t nss_freq_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_freq_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(freq) +--- a/nss_gmac_stats.c ++++ b/nss_gmac_stats.c +@@ -81,3 +81,12 @@ ssize_t nss_gmac_stats_read(struct file + + return bytes_read; + } ++ ++/* ++ * nss_gmac_stats_write() ++ * Write GMAC statistics ++ */ ++ssize_t nss_gmac_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} +--- a/nss_gmac_stats.h ++++ b/nss_gmac_stats.h +@@ -30,4 +30,5 @@ enum nss_stats_gmac { + }; + + extern ssize_t nss_gmac_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos); ++ssize_t nss_gmac_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos); + #endif /* __NSS_GMAC_STATS_H */ +--- a/nss_gre_redir_lag_ds_stats.c ++++ b/nss_gre_redir_lag_ds_stats.c +@@ -100,6 +100,15 @@ static ssize_t nss_gre_redir_lag_ds_cmn_ + } + + /* ++ * nss_gre_redir_lag_ds_cmn_stats_write() ++ * Write GRE_REDIR_LAG_DS_CMN statistics ++ */ ++static ssize_t nss_gre_redir_lag_ds_cmn_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_gre_redir_lag_ds_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(gre_redir_lag_ds_cmn) +--- a/nss_gre_redir_lag_us_stats.c ++++ b/nss_gre_redir_lag_us_stats.c +@@ -100,6 +100,15 @@ static ssize_t nss_gre_redir_lag_us_cmn_ + } + + /* ++ * nss_gre_redir_lag_us_cmn_stats_write() ++ * Write GRE_REDIR_LAG_US_CMN statistics ++ */ ++static ssize_t nss_gre_redir_lag_us_cmn_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_gre_redir_lag_us_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(gre_redir_lag_us_cmn) +@@ -223,4 +232,3 @@ int nss_gre_redir_lag_us_stats_register_ + return atomic_notifier_chain_register(&nss_gre_redir_lag_us_stats_notifier, nb); + } + EXPORT_SYMBOL(nss_gre_redir_lag_us_stats_register_notifier); +- +--- a/nss_gre_redir_mark_stats.c ++++ b/nss_gre_redir_mark_stats.c +@@ -104,6 +104,15 @@ static ssize_t nss_gre_redir_mark_stats_ + } + + /* ++ * nss_gre_redir_mark_stats_write() ++ * Write GRE_REDIR_MARK statistics ++ */ ++static ssize_t nss_gre_redir_mark_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_gre_redir_mark_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(gre_redir_mark) +--- a/nss_gre_redir_stats.c ++++ b/nss_gre_redir_stats.c +@@ -178,6 +178,15 @@ done: + } + + /* ++ * nss_gre_redir_stats_write() ++ * Write GRE_REDIR statistics ++ */ ++static ssize_t nss_gre_redir_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_gre_redir_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(gre_redir) +--- a/nss_gre_stats.c ++++ b/nss_gre_stats.c +@@ -259,6 +259,15 @@ static ssize_t nss_gre_stats_read(struct + } + + /* ++ * nss_gre_stats_write() ++ * Write GRE statistics ++ */ ++static ssize_t nss_gre_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_gre_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(gre) +--- a/nss_gre_tunnel_stats.c ++++ b/nss_gre_tunnel_stats.c +@@ -219,6 +219,15 @@ static ssize_t nss_gre_tunnel_stats_read + } + + /* ++ * nss_gre_tunnel_stats_write() ++ * Write GRE_TUNNEL statistics ++ */ ++static ssize_t nss_gre_tunnel_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_gre_tunnel_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(gre_tunnel) +--- a/nss_igs_stats.c ++++ b/nss_igs_stats.c +@@ -293,6 +293,15 @@ void nss_igs_stats_init(uint32_t if_num, + } + + /* ++ * nss_igs_stats_write() ++ * Write IGS statistics ++ */ ++static ssize_t nss_igs_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_igs_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(igs) +--- a/nss_ipsec_cmn_stats.c ++++ b/nss_ipsec_cmn_stats.c +@@ -115,6 +115,15 @@ static ssize_t nss_ipsec_cmn_stats_read( + } + + /* ++ * nss_ipsec_cmn_stats_write() ++ * Write IPSEC_CMN statistics ++ */ ++static ssize_t nss_ipsec_cmn_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_ipsec_cmn_stats_ops. + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(ipsec_cmn); +--- a/nss_ipv4_reasm_stats.c ++++ b/nss_ipv4_reasm_stats.c +@@ -84,6 +84,15 @@ static ssize_t nss_ipv4_reasm_stats_read + } + + /* ++ * nss_ipv4_reasm_stats_write() ++ * Write IPV4_REASM statistics ++ */ ++static ssize_t nss_ipv4_reasm_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_ipv4_reasm_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(ipv4_reasm); +--- a/nss_ipv4_stats.c ++++ b/nss_ipv4_stats.c +@@ -100,6 +100,44 @@ static ssize_t nss_ipv4_stats_read(struc + } + + /* ++ * nss_ipv4_stats_write() ++ * Write IPV4 stats ++ */ ++static ssize_t nss_ipv4_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ int32_t i; ++ uint32_t reset; ++ ++ if (kstrtou32_from_user(ubuf, sz, 0, &reset)) { ++ return -EINVAL; ++ } ++ ++ if (reset != 0) { ++ return -EINVAL; ++ } ++ ++ nss_stats_reset_common_stats(NSS_IPV4_RX_INTERFACE); ++ ++ /* ++ * IPv4 node stats ++ */ ++ spin_lock_bh(&nss_top_main.stats_lock); ++ for (i = 0; i < NSS_IPV4_STATS_MAX; i++) { ++ nss_ipv4_stats[i] = 0; ++ } ++ ++ /* ++ * Exception stats ++ */ ++ for (i = 0; (i < NSS_IPV4_EXCEPTION_EVENT_MAX); i++) { ++ nss_ipv4_exception_stats[i] = 0; ++ } ++ spin_unlock_bh(&nss_top_main.stats_lock); ++ ++ return sz; ++} ++ ++/* + * nss_ipv4_stats_conn_sync() + * Update driver specific information from the messsage. + */ +--- a/nss_ipv6_reasm_stats.c ++++ b/nss_ipv6_reasm_stats.c +@@ -84,6 +84,15 @@ static ssize_t nss_ipv6_reasm_stats_read + } + + /* ++ * nss_ipv6_reasm_stats_write() ++ * Write IPV6_REASM statistics ++ */ ++static ssize_t nss_ipv6_reasm_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_ipv6_reasm_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(ipv6_reasm); +--- a/nss_ipv6_stats.c ++++ b/nss_ipv6_stats.c +@@ -102,6 +102,44 @@ static ssize_t nss_ipv6_stats_read(struc + } + + /* ++ * nss_ipv6_stats_write() ++ * Write IPV6 stats. ++ */ ++static ssize_t nss_ipv6_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ int32_t i; ++ uint32_t reset; ++ ++ if (kstrtou32_from_user(ubuf, sz, 0, &reset)) { ++ return -EINVAL; ++ } ++ ++ if (reset != 0) { ++ return -EINVAL; ++ } ++ ++ nss_stats_reset_common_stats(NSS_IPV6_RX_INTERFACE); ++ ++ /* ++ * IPv6 node stats ++ */ ++ spin_lock_bh(&nss_top_main.stats_lock); ++ for (i = 0; (i < NSS_IPV6_STATS_MAX); i++) { ++ nss_ipv6_stats[i] = 0; ++ } ++ ++ /* ++ * Exception stats ++ */ ++ for (i = 0; (i < NSS_IPV6_EXCEPTION_EVENT_MAX); i++) { ++ nss_ipv6_exception_stats[i] = 0; ++ } ++ spin_unlock_bh(&nss_top_main.stats_lock); ++ ++ return sz; ++} ++ ++/* + * nss_ipv6_stats_conn_sync() + * Update driver specific information from the messsage. + */ +--- a/nss_l2tpv2_stats.c ++++ b/nss_l2tpv2_stats.c +@@ -93,6 +93,15 @@ static ssize_t nss_l2tpv2_stats_read(str + } + + /* ++ * nss_l2tpv2_stats_write() ++ * Write L2TPV2 statistics ++ */ ++static ssize_t nss_l2tpv2_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_l2tpv2_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(l2tpv2); +--- a/nss_lso_rx_stats.c ++++ b/nss_lso_rx_stats.c +@@ -84,6 +84,15 @@ static ssize_t nss_lso_rx_stats_read(str + } + + /* ++ * nss_lso_rx_stats_write() ++ * Write LSO_RX statistics ++ */ ++static ssize_t nss_lso_rx_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_lso_rx_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(lso_rx); +--- a/nss_map_t_stats.c ++++ b/nss_map_t_stats.c +@@ -90,6 +90,15 @@ static ssize_t nss_map_t_stats_read(stru + } + + /* ++ * nss_map_t_stats_write() ++ * Write MAP_T statistics ++ */ ++static ssize_t nss_map_t_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_map_t_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(map_t); +--- a/nss_match_stats.c ++++ b/nss_match_stats.c +@@ -127,6 +127,15 @@ void nss_match_stats_sync(struct nss_ctx + } + + /* ++ * nss_match_stats_write() ++ * Write MATCH statistics ++ */ ++static ssize_t nss_match_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_match_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(match) +--- a/nss_mirror_stats.c ++++ b/nss_mirror_stats.c +@@ -263,6 +263,15 @@ int nss_mirror_stats_init(uint32_t if_nu + } + + /* ++ * nss_mirror_stats_write() ++ * Write MIRROR statistics ++ */ ++static ssize_t nss_mirror_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_mirror_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(mirror) +--- a/nss_n2h_stats.c ++++ b/nss_n2h_stats.c +@@ -84,6 +84,37 @@ static ssize_t nss_n2h_stats_read(struct + } + + /* ++ * nss_n2h_stats_write() ++ * Write N2H stats ++ */ ++static ssize_t nss_n2h_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ int32_t i, core; ++ uint32_t reset; ++ ++ if (kstrtou32_from_user(ubuf, sz, 0, &reset)) { ++ return -EINVAL; ++ } ++ ++ if (reset != 0) { ++ return -EINVAL; ++ } ++ ++ /* ++ * N2H node stats ++ */ ++ spin_lock_bh(&nss_top_main.stats_lock); ++ for (core = 0; core < nss_top_main.num_nss; core++) { ++ for (i = 0; i < NSS_N2H_STATS_MAX; i++) { ++ nss_n2h_stats[core][i] = 0; ++ } ++ } ++ spin_unlock_bh(&nss_top_main.stats_lock); ++ ++ return sz; ++} ++ ++/* + * nss_n2h_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(n2h); +--- a/nss_portid_stats.c ++++ b/nss_portid_stats.c +@@ -87,6 +87,15 @@ static ssize_t nss_portid_stats_read(str + } + + /* ++ * nss_portid_stats_write() ++ * Write PORTID statistics ++ */ ++static ssize_t nss_portid_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_portid_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(portid) +--- a/nss_ppe_stats.c ++++ b/nss_ppe_stats.c +@@ -760,6 +760,70 @@ static ssize_t nss_ppe_nonexception_cc_s + } + + /* ++ * nss_ppe_conn_stats_write() ++ * Write PPE_CONN statistics ++ */ ++static ssize_t nss_ppe_conn_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_ppe_l3_stats_write() ++ * Write PPE_L3 statistics ++ */ ++static ssize_t nss_ppe_l3_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_ppe_code_stats_write() ++ * Write PPE_CODE statistics ++ */ ++static ssize_t nss_ppe_code_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_ppe_port_dc_stats_write() ++ * Write PPE_PORT_DC statistics ++ */ ++static ssize_t nss_ppe_port_dc_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_ppe_exception_stats_write() ++ * Write PPE_EXCEPTION statistics ++ */ ++static ssize_t nss_ppe_exception_cc_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_ppe_nonexception_stats_write() ++ * Write PPE_NONEXCEPTION statistics ++ */ ++static ssize_t nss_ppe_nonexception_cc_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_ppe_sc_stats_write() ++ * Write PPE_SC statistics ++ */ ++static ssize_t nss_ppe_sc_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++ ++/* + * nss_ppe_conn_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(ppe_conn) +--- a/nss_ppe_vp_stats.c ++++ b/nss_ppe_vp_stats.c +@@ -208,6 +208,15 @@ static ssize_t nss_ppe_vp_stats_read(str + } + + /* ++ * nss_ppe_vp_stats_write() ++ * Write PPE_VP statistics ++ */ ++static ssize_t nss_ppe_vp_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_ppe_vp_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(ppe_vp) +--- a/nss_pppoe_stats.c ++++ b/nss_pppoe_stats.c +@@ -209,6 +209,15 @@ void nss_pppoe_stats_sync(struct nss_ctx + } + + /* ++ * nss_pppoe_stats_write() ++ * Write PPPOE statistics ++ */ ++static ssize_t nss_pppoe_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_pppoe_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(pppoe); +--- a/nss_pptp_stats.c ++++ b/nss_pptp_stats.c +@@ -91,6 +91,15 @@ static ssize_t nss_pptp_stats_read(struc + } + + /* ++ * nss_pptp_stats_write() ++ * Write PPTP statistics ++ */ ++static ssize_t nss_pptp_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_pptp_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(pptp); +--- a/nss_pvxlan_stats.c ++++ b/nss_pvxlan_stats.c +@@ -69,6 +69,31 @@ static void nss_pvxlan_tunnel_stats_debu + } + + /* ++ * nss_pvxlan_tunnel_stats_debug_clear() ++ * Clear PVxLAN Tunnel statistics. ++ */ ++static void nss_pvxlan_tunnel_stats_debug_clear(void) ++{ ++ uint32_t i; ++ int32_t if_index; ++ uint32_t if_num; ++ ++ spin_lock_bh(&nss_pvxlan_tunnel_stats_debug_lock); ++ for (i = 0; i < NSS_PVXLAN_MAX_INTERFACES; i++) { ++ if (nss_pvxlan_tunnel_debug_stats[i].valid) { ++ if_index = nss_pvxlan_tunnel_debug_stats[i].if_index; ++ if_num = nss_pvxlan_tunnel_debug_stats[i].if_num; ++ memset(&nss_pvxlan_tunnel_debug_stats[i], 0, ++ sizeof(struct nss_pvxlan_tunnel_stats_debug)); ++ nss_pvxlan_tunnel_debug_stats[i].valid = true; ++ nss_pvxlan_tunnel_debug_stats[i].if_index = if_index; ++ nss_pvxlan_tunnel_debug_stats[i].if_num = if_num; ++ } ++ } ++ spin_unlock_bh(&nss_pvxlan_tunnel_stats_debug_lock); ++} ++ ++/* + * nss_pvxlan_stats_read() + * Read PVxLAN Tunnel statistics + */ +@@ -145,6 +170,31 @@ static ssize_t nss_pvxlan_stats_read(str + return bytes_read; + } + ++ ++/* ++ * nss_pvxlan_stats_write() ++ * Write PVxLAN stats ++ */ ++static ssize_t nss_pvxlan_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ uint32_t reset; ++ ++ if (kstrtou32_from_user(ubuf, sz, 0, &reset)) ++ return -EINVAL; ++ ++ if (reset != 0) { ++ return -EINVAL; ++ } ++ ++ /* ++ * Get all stats ++ */ ++ nss_pvxlan_tunnel_stats_debug_clear(); ++ ++ return sz; ++} ++ ++ + /* + * nss_pvxlan_stats_sync() + * Sync function for pvxlan statistics +--- a/nss_qrfs_stats.c ++++ b/nss_qrfs_stats.c +@@ -100,6 +100,15 @@ static ssize_t nss_qrfs_stats_read(struc + } + + /* ++ * nss_qrfs_stats_write() ++ * Write QRFS statistics ++ */ ++static ssize_t nss_qrfs_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_qrfs_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(qrfs) +--- a/nss_qvpn_stats.c ++++ b/nss_qvpn_stats.c +@@ -123,6 +123,15 @@ static ssize_t nss_qvpn_stats_read(struc + } + + /* ++ * nss_qvpn_stats_write() ++ * Write QVPN statistics ++ */ ++static ssize_t nss_qvpn_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_qvpn_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(qvpn) +--- a/nss_rmnet_rx_stats.c ++++ b/nss_rmnet_rx_stats.c +@@ -156,6 +156,15 @@ static ssize_t nss_rmnet_rx_stats_read(s + } + + /* ++ * nss_rmnet_rx_stats_write() ++ * Write RMNET_RX statistics ++ */ ++static ssize_t nss_rmnet_rx_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_rmnet_rx_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(rmnet_rx) +--- a/nss_sjack_stats.c ++++ b/nss_sjack_stats.c +@@ -55,6 +55,15 @@ static ssize_t nss_sjack_stats_read(stru + } + + /* ++ * nss_sjack_stats_write() ++ * Write SJACK statistics ++ */ ++static ssize_t nss_sjack_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_sjack_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(sjack) +--- a/nss_stats.h ++++ b/nss_stats.h +@@ -44,7 +44,7 @@ + static struct file_operations nss_##name##_stats_ops = { \ + .open = nss_stats_open, \ + .read = nss_##name##_stats_read, \ +- .write = nss_clear_stats_write, \ ++ .write = nss_##name##_stats_write, \ + .llseek = generic_file_llseek, \ + .release = nss_stats_release, \ + }; +@@ -72,7 +72,6 @@ extern void nss_stats_register_sysctl(vo + void nss_stats_init(void); + extern int nss_stats_release(struct inode *inode, struct file *filp); + extern int nss_stats_open(struct inode *inode, struct file *filp); +-extern ssize_t nss_clear_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos); + void nss_stats_create_dentry(char *name, const struct file_operations *ops); + extern void nss_stats_reset_common_stats(uint32_t if_num); + extern size_t nss_stats_fill_common_stats(uint32_t if_num, int instance, char *lbuf, size_t size_wr, size_t size_al, char *node); +--- a/nss_tls_stats.c ++++ b/nss_tls_stats.c +@@ -125,6 +125,15 @@ static ssize_t nss_tls_stats_read(struct + } + + /* ++ * nss_tls_stats_write() ++ * Write TLS statistics ++ */ ++static ssize_t nss_tls_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_tls_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(tls); +--- a/nss_trustsec_tx_stats.c ++++ b/nss_trustsec_tx_stats.c +@@ -131,6 +131,38 @@ static ssize_t nss_trustsec_tx_stats_rea + } + + /* ++ * nss_trustsec_tx_stats_write() ++ * Write Trustsec TX stats ++ */ ++static ssize_t nss_trustsec_tx_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ int32_t i; ++ uint32_t reset; ++ ++ if (kstrtou32_from_user(ubuf, sz, 0, &reset)) { ++ return -EINVAL; ++ } ++ ++ if (reset != 0) { ++ return -EINVAL; ++ } ++ ++ nss_stats_reset_common_stats(NSS_TRUSTSEC_TX_INTERFACE); ++ ++ /* ++ * Trustsec TX node stats ++ */ ++ spin_lock_bh(&nss_top_main.stats_lock); ++ for (i = 0; (i < NSS_TRUSTSEC_TX_STATS_MAX); i++) { ++ trustsec_tx_stats[i] = 0; ++ } ++ ++ spin_unlock_bh(&nss_top_main.stats_lock); ++ ++ return sz; ++} ++ ++/* + * nss_trustsec_tx_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(trustsec_tx) +--- a/nss_tstamp_stats.c ++++ b/nss_tstamp_stats.c +@@ -111,6 +111,15 @@ static ssize_t nss_tstamp_stats_read(str + } + + /* ++ * nss_tstamp_stats_write() ++ * Write TSTAMP statistics ++ */ ++static ssize_t nss_tstamp_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_tstamp_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(tstamp) +--- a/nss_tunipip6_stats.c ++++ b/nss_tunipip6_stats.c +@@ -114,6 +114,15 @@ void nss_tunipip6_stats_sync(struct nss_ + } + + /* ++ * nss_tunipip6_stats_write() ++ * Write TUNIPIP6 statistics ++ */ ++static ssize_t nss_tunipip6_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_tunipip6_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(tunipip6) +--- a/nss_udp_st_stats.c ++++ b/nss_udp_st_stats.c +@@ -113,6 +113,15 @@ static ssize_t nss_udp_st_stats_read(str + } + + /* ++ * nss_udp_st_stats_write() ++ * Write UDP_ST statistics ++ */ ++static ssize_t nss_udp_st_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_udp_st_stats_ops. + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(udp_st); +--- a/nss_unaligned_stats.c ++++ b/nss_unaligned_stats.c +@@ -74,6 +74,15 @@ static ssize_t nss_unaligned_stats_read( + } + + /* ++ * nss_unaligned_stats_write() ++ * Write UNALIGNED statistics ++ */ ++static ssize_t nss_unaligned_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_unaligned_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(unaligned) +--- a/nss_virt_if_stats.c ++++ b/nss_virt_if_stats.c +@@ -295,6 +295,15 @@ done: + } + + /* ++ * nss_virt_if_stats_write() ++ * Write VIRT_IF statistics ++ */ ++static ssize_t nss_virt_if_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_virt_if_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(virt_if) +--- a/nss_vxlan_stats.c ++++ b/nss_vxlan_stats.c +@@ -108,6 +108,15 @@ void nss_vxlan_stats_sync(struct nss_ctx + } + + /* ++ * nss_vxlan_stats_write() ++ * Write VXLAN statistics ++ */ ++static ssize_t nss_vxlan_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_vxlan_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(vxlan) +--- a/nss_wifi_ext_vdev_stats.c ++++ b/nss_wifi_ext_vdev_stats.c +@@ -220,6 +220,15 @@ static ssize_t nss_wifi_ext_vdev_stats_r + } + + /* ++ * nss_wifi_ext_vdev_stats_write() ++ * Write WIFI_EXT_VDEV statistics ++ */ ++static ssize_t nss_wifi_ext_vdev_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_wifi_ext_vdev_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(wifi_ext_vdev); +--- a/nss_wifi_mesh_stats.c ++++ b/nss_wifi_mesh_stats.c +@@ -436,6 +436,51 @@ static ssize_t nss_wifi_mesh_exception_s + } + + /* ++ * nss_wifi_mesh_encap_stats_write() ++ * Write WIFI_MESH_ENCAP statistics ++ */ ++static ssize_t nss_wifi_mesh_encap_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_wifi_mesh_decap_stats_write() ++ * Write WIFI_MESH_DECAP statistics ++ */ ++static ssize_t nss_wifi_mesh_decap_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_wifi_mesh_path_stats_write() ++ * Write WIFI_MESH_PATH statistics ++ */ ++static ssize_t nss_wifi_mesh_path_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_wifi_mesh_proxy_path_stats_write() ++ * Write WIFI_MESH_PROXY_PATH statistics ++ */ ++static ssize_t nss_wifi_mesh_proxy_path_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* ++ * nss_wifi_mesh_exception_stats_write() ++ * Write WIFI_MESH_EXCEPTION statistics ++ */ ++static ssize_t nss_wifi_mesh_exception_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_wifi_mesh_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(wifi_mesh_encap); +--- a/nss_wifi_stats.c ++++ b/nss_wifi_stats.c +@@ -143,6 +143,15 @@ static ssize_t nss_wifi_stats_read(struc + } + + /* ++ * nss_wifi_stats_write() ++ * Write WIFI statistics ++ */ ++static ssize_t nss_wifi_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * nss_wifi_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(wifi) +--- a/nss_wifili_stats.c ++++ b/nss_wifili_stats.c +@@ -251,6 +251,15 @@ static ssize_t nss_wifili_stats_read(str + } + + /* ++ * nss_wifili_stats_write() ++ * Write WIFILI statistics ++ */ ++static ssize_t nss_wifili_stats_write(struct file *fp, const char __user *ubuf, size_t sz, loff_t *ppos) ++{ ++ return -ESRCH; ++} ++ ++/* + * wifili_stats_ops + */ + NSS_STATS_DECLARE_FILE_OPERATIONS(wifili); diff --git a/qca-nss-drv/patches-11.4/0030-backport-11.5-pn_mq_en.patch b/qca-nss-drv/patches-11.4/0030-backport-11.5-pn_mq_en.patch new file mode 100644 index 0000000..f83d756 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0030-backport-11.5-pn_mq_en.patch @@ -0,0 +1,241 @@ +--- a/exports/nss_project.h ++++ b/exports/nss_project.h +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2017-2018, 2021 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -38,6 +38,12 @@ + #define NSS_PROJECT_IRQS_PER_MESSAGE 32 + + /** ++ * Maximum possible value of priority after classification ++ * at an ingress interface. ++ */ ++#define NSS_PROJECT_PRI_MQ_MAP_MAX_SIZE 16 ++ ++/** + * nss_project_message_types + * Project message types. + */ +@@ -46,6 +52,8 @@ enum nss_project_message_types { + /**< Message to enable or disable worker thread statistics. */ + NSS_PROJECT_MSG_WT_STATS_NOTIFY, + /**< NSS to HLOS message containing worker thread statistics. */ ++ NSS_PROJECT_MSG_SET_QUEUE_PRI_MAP_CFG, ++ /**< Message to configure priority to multi-queue mapping. */ + NSS_PROJECT_MSG_MAX, + }; + +@@ -60,6 +68,8 @@ enum nss_project_error_types { + /**< The firmware does not support worker thread statistics. */ + NSS_PROJECT_ERROR_WT_STATS_REDUNDANT_ENABLE, + /**< The firmware received a redundant request to enable worker thread statistics. */ ++ NSS_PROJECT_ERROR_MQ_NUMBER_INVALID, ++ /**< The firmware received an invalid multi-queue number. */ + NSS_PROJECT_ERROR_MAX, + }; + +@@ -111,6 +121,15 @@ struct nss_project_msg_wt_stats_notify { + }; + + /** ++ * nss_project_msg_pri_mq_map_cfg ++ * NSS priority to multi-queue mapping configuration. ++ */ ++struct nss_project_msg_pri_mq_map_cfg { ++ uint8_t pri_mq_map[NSS_PROJECT_PRI_MQ_MAP_MAX_SIZE]; ++ /**< Priority to multi-queue mapping array. */ ++}; ++ ++/** + * nss_project_msg + * General message structure for project messages. + */ +@@ -125,6 +144,8 @@ struct nss_project_msg { + /**< Enable or disable worker thread statistics. */ + struct nss_project_msg_wt_stats_notify wt_stats_notify; + /**< One-way worker thread statistics message. */ ++ struct nss_project_msg_pri_mq_map_cfg pri_mq_map_cfg; ++ /**< Configure priority to multi-queue message. */ + } msg; /**< Message payload. */ + }; + +@@ -170,6 +191,17 @@ void nss_project_unregister_sysctl(void) + void nss_project_register_handler(struct nss_ctx_instance *nss_ctx); + + /** ++ * nss_project_pri_mq_map_configure ++ * Configures priority to multi-queue mapping. ++ * ++ * @param[in] nss_ctx Pointer to the NSS context. ++ * ++ * @return ++ * Status of the configuration update operation. ++ */ ++extern nss_tx_status_t nss_project_pri_mq_map_configure(struct nss_ctx_instance *nss_ctx); ++ ++/** + * @} + */ + +--- a/nss_core.c ++++ b/nss_core.c +@@ -283,6 +283,17 @@ void nss_core_set_subsys_dp_type(struct + } + + /* ++ * nss_core_is_mq_enabled() ++ * Get multi-queue status. ++ * ++ * Returns 'true' if multi-queue is enabled otherwise returns 'false'. ++ */ ++bool nss_core_is_mq_enabled(void) ++{ ++ return pn_mq_en; ++} ++ ++/* + * nss_core_register_subsys_dp() + * Registers a netdevice and associated information at a given interface. + * +@@ -1720,7 +1731,13 @@ static void nss_core_init_nss(struct nss + if (nss_ctx->id) { + ret = nss_n2h_update_queue_config_async(nss_ctx, pn_mq_en, pn_qlimits); + if (ret != NSS_TX_SUCCESS) { +- nss_warning("Failed to send pnode queue config to core 1\n"); ++ nss_warning("%px: Failed to send pnode queue config to core 1\n", nss_ctx); ++ return; ++ } ++ ++ ret = nss_project_pri_mq_map_configure(nss_ctx); ++ if (ret != NSS_TX_SUCCESS) { ++ nss_warning("%px: Failed to send pnode priority to multi-queue config to core 1\n", nss_ctx); + } + return; + } +--- a/nss_core.h ++++ b/nss_core.h +@@ -983,6 +983,7 @@ extern void nss_core_register_subsys_dp( + uint32_t features); + extern void nss_core_unregister_subsys_dp(struct nss_ctx_instance *nss_ctx, uint32_t if_num); + void nss_core_set_subsys_dp_type(struct nss_ctx_instance *nss_ctx, struct net_device *ndev, uint32_t if_num, uint32_t type); ++extern bool nss_core_is_mq_enabled(void); + + static inline nss_if_rx_msg_callback_t nss_core_get_msg_handler(struct nss_ctx_instance *nss_ctx, uint32_t interface) + { +--- a/nss_data_plane/nss_data_plane_common.c ++++ b/nss_data_plane/nss_data_plane_common.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2014-2016,2020 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2014-2016,2020-2021 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -39,9 +39,16 @@ static void nss_data_plane_work_function + */ + ret = nss_n2h_update_queue_config_sync(nss_ctx, pn_mq_en, pn_qlimits); + if (ret != NSS_TX_SUCCESS) { +- nss_warning("Failed to send pnode queue config to core 0\n"); ++ nss_warning("%px: Failed to send pnode queue config to core 0\n", nss_ctx); ++ goto data_plane_reg; + } + ++ ret = nss_project_pri_mq_map_configure(nss_ctx); ++ if (ret != NSS_TX_SUCCESS) { ++ nss_warning("%px: Failed to send pnode priority to multi-queue config to core 0\n", nss_ctx); ++ } ++ ++data_plane_reg: + nss_top->data_plane_ops->data_plane_register(nss_ctx); + } + +--- a/nss_project.c ++++ b/nss_project.c +@@ -1,9 +1,12 @@ + /* + ************************************************************************** +- * Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2017-2018, 2020-2021, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. ++ * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +@@ -21,6 +24,9 @@ + #include "nss_tx_rx_common.h" + + static int nss_project_wt_stats_enable; ++static uint8_t nss_project_pri_mq_map[NSS_PROJECT_PRI_MQ_MAP_MAX_SIZE] = {0, 1, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}; ++module_param_array(nss_project_pri_mq_map, byte, NULL, 0); ++MODULE_PARM_DESC(nss_project_pri_mq_map, "Priority to multi-queue mapping"); + + /* + * nss_project_free_wt_stats() +@@ -264,6 +270,57 @@ static int nss_project_wt_stats_handler( + } + + /* ++ * nss_project_pri_mq_map_send_cfg() ++ * Sends message to firmware to configure priority to multi-queue mapping. ++ */ ++static nss_tx_status_t nss_project_pri_mq_map_send_cfg(struct nss_ctx_instance *nss_ctx) ++{ ++ struct nss_project_msg *npm; ++ struct nss_cmn_msg *ncm; ++ nss_tx_status_t ret; ++ ++ npm = kzalloc(sizeof(*npm), GFP_ATOMIC); ++ if (!npm) { ++ nss_warning("%px: Failed to allocate buffer for message\n", nss_ctx); ++ return NSS_TX_FAILURE; ++ } ++ ++ /* ++ * Populate the message ++ */ ++ ncm = &npm->cm; ++ nss_cmn_msg_init(ncm, NSS_PROJECT_INTERFACE, ++ NSS_PROJECT_MSG_SET_QUEUE_PRI_MAP_CFG, ++ sizeof(struct nss_project_msg_pri_mq_map_cfg), ++ NULL, NULL); ++ memcpy(npm->msg.pri_mq_map_cfg.pri_mq_map, nss_project_pri_mq_map, ++ sizeof(nss_project_pri_mq_map)); ++ ret = nss_core_send_cmd(nss_ctx, npm, sizeof(*npm), NSS_NBUF_PAYLOAD_SIZE); ++ kfree(npm); ++ return ret; ++} ++ ++/* ++ * nss_project_pri_mq_map_configure() ++ * API to configure priority to multi-queue mapping. ++ */ ++nss_tx_status_t nss_project_pri_mq_map_configure(struct nss_ctx_instance *nss_ctx) ++{ ++ /* ++ * Check if multi-queue configuration is enabled. ++ */ ++ if (!nss_core_is_mq_enabled()) { ++ nss_warning("%px: Multi-queue is disabled. Please enable multi-queue before configuring mapping\n", nss_ctx); ++ return NSS_TX_FAILURE_NOT_SUPPORTED; ++ } ++ ++ /* ++ * Send configuration message to NSS. ++ */ ++ return nss_project_pri_mq_map_send_cfg(nss_ctx); ++} ++ ++/* + * Tree of ctl_tables used to put the wt_stats proc node in the correct place in + * the file system. Allows the command $ echo 1 > proc/sys/dev/nss/project/wt_stats + * to enable worker thread statistics (echoing 0 into the same target will disable). diff --git a/qca-nss-drv/patches-11.4/0030-backport-12.5-ipq50xx-fixes.patch b/qca-nss-drv/patches-11.4/0030-backport-12.5-ipq50xx-fixes.patch new file mode 100644 index 0000000..62a4b07 --- /dev/null +++ b/qca-nss-drv/patches-11.4/0030-backport-12.5-ipq50xx-fixes.patch @@ -0,0 +1,161 @@ +--- a/nss_data_plane/hal/nss_ipq50xx.c ++++ b/nss_data_plane/hal/nss_ipq50xx.c +@@ -1,5 +1,7 @@ + /* +- * Copyright (c) 2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. ++ * ++ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above +@@ -65,11 +67,15 @@ void nss_data_plane_hal_set_features(str + dpc->dev->wanted_features |= NSS_DATA_PLANE_SUPPORTED_FEATURES; + + /* ++ * We advertise checksum offload for VLANs. + * Synopsys GMAC does not support checksum offload for QinQ VLANs. +- * Hence, we do not advertise checksum offload support for VLANs. ++ * However, we are dependent on netdev ops ndo_features_check to block ++ * QinQ VLAN TSO/checksum offload. + */ +- dpc->dev->vlan_features |= NSS_DATA_PLANE_SUPPORTED_FEATURES & +- (~(NETIF_F_RXCSUM | NETIF_F_HW_CSUM)); ++ dpc->dev->vlan_features |= NSS_DATA_PLANE_SUPPORTED_FEATURES; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)) ++ dpc->dev->vlan_features &= ~NETIF_F_UFO; ++#endif + } + + /* +@@ -82,34 +88,37 @@ void nss_data_plane_hal_stats_sync(struc + + spin_lock_bh(&nss_data_plane_hal_gmac_stats_lock); + +- gmac_stats->rx_bytes += stats->if_stats.rx_bytes; +- gmac_stats->rx_packets += stats->if_stats.rx_packets; +- gmac_stats->rx_errors += stats->estats.rx_errors; +- gmac_stats->rx_receive_errors += stats->estats.rx_receive_errors; +- gmac_stats->rx_descriptor_errors += stats->estats.rx_descriptor_errors; +- gmac_stats->rx_late_collision_errors += stats->estats.rx_late_collision_errors; +- gmac_stats->rx_dribble_bit_errors += stats->estats.rx_dribble_bit_errors; +- gmac_stats->rx_length_errors += stats->estats.rx_length_errors; +- gmac_stats->rx_ip_header_errors += stats->estats.rx_ip_header_errors; +- gmac_stats->rx_ip_payload_errors += stats->estats.rx_ip_payload_errors; +- gmac_stats->rx_no_buffer_errors += stats->estats.rx_no_buffer_errors; +- gmac_stats->rx_transport_csum_bypassed += stats->estats.rx_transport_csum_bypassed; +- +- gmac_stats->tx_bytes += stats->if_stats.tx_bytes; +- gmac_stats->tx_packets += stats->if_stats.tx_packets; +- gmac_stats->tx_collisions += stats->estats.tx_collisions; +- gmac_stats->tx_errors += stats->estats.tx_errors; +- gmac_stats->tx_jabber_timeout_errors += stats->estats.tx_jabber_timeout_errors; +- gmac_stats->tx_frame_flushed_errors += stats->estats.tx_frame_flushed_errors; +- gmac_stats->tx_loss_of_carrier_errors += stats->estats.tx_loss_of_carrier_errors; +- gmac_stats->tx_no_carrier_errors += stats->estats.tx_no_carrier_errors; +- gmac_stats->tx_late_collision_errors += stats->estats.tx_late_collision_errors; +- gmac_stats->tx_excessive_collision_errors += stats->estats.tx_excessive_collision_errors; +- gmac_stats->tx_excessive_deferral_errors += stats->estats.tx_excessive_deferral_errors; +- gmac_stats->tx_underflow_errors += stats->estats.tx_underflow_errors; +- gmac_stats->tx_ip_header_errors += stats->estats.tx_ip_header_errors; +- gmac_stats->tx_ip_payload_errors += stats->estats.tx_ip_payload_errors; +- gmac_stats->tx_dropped += stats->estats.tx_dropped; ++ gmac_stats->rx_stats.rx_bytes += stats->if_stats.rx_bytes; ++ gmac_stats->rx_stats.rx_packets += stats->if_stats.rx_packets; ++ gmac_stats->rx_stats.rx_errors += stats->estats.rx_errors; ++ gmac_stats->rx_stats.rx_descriptor_errors += stats->estats.rx_descriptor_errors; ++ gmac_stats->rx_stats.rx_late_collision_errors += stats->estats.rx_late_collision_errors; ++ gmac_stats->rx_stats.rx_dribble_bit_errors += stats->estats.rx_dribble_bit_errors; ++ gmac_stats->rx_stats.rx_length_errors += stats->estats.rx_length_errors; ++ gmac_stats->rx_stats.rx_ip_header_errors += stats->estats.rx_ip_header_errors; ++ gmac_stats->rx_stats.rx_ip_payload_errors += stats->estats.rx_ip_payload_errors; ++ gmac_stats->rx_stats.rx_no_buffer_errors += stats->estats.rx_no_buffer_errors; ++ gmac_stats->rx_stats.rx_transport_csum_bypassed += stats->estats.rx_transport_csum_bypassed; ++ gmac_stats->rx_stats.rx_missed += stats->estats.rx_missed; ++ gmac_stats->rx_stats.rx_fifo_overflows += stats->estats.fifo_overflows; ++ gmac_stats->rx_stats.rx_scatter_errors += stats->estats.rx_scatter_errors; ++ ++ gmac_stats->tx_stats.tx_bytes += stats->if_stats.tx_bytes; ++ gmac_stats->tx_stats.tx_packets += stats->if_stats.tx_packets; ++ gmac_stats->tx_stats.tx_collisions += stats->estats.tx_collisions; ++ gmac_stats->tx_stats.tx_errors += stats->estats.tx_errors; ++ gmac_stats->tx_stats.tx_jabber_timeout_errors += stats->estats.tx_jabber_timeout_errors; ++ gmac_stats->tx_stats.tx_frame_flushed_errors += stats->estats.tx_frame_flushed_errors; ++ gmac_stats->tx_stats.tx_loss_of_carrier_errors += stats->estats.tx_loss_of_carrier_errors; ++ gmac_stats->tx_stats.tx_no_carrier_errors += stats->estats.tx_no_carrier_errors; ++ gmac_stats->tx_stats.tx_late_collision_errors += stats->estats.tx_late_collision_errors; ++ gmac_stats->tx_stats.tx_excessive_collision_errors += stats->estats.tx_excessive_collision_errors; ++ gmac_stats->tx_stats.tx_excessive_deferral_errors += stats->estats.tx_excessive_deferral_errors; ++ gmac_stats->tx_stats.tx_underflow_errors += stats->estats.tx_underflow_errors; ++ gmac_stats->tx_stats.tx_ip_header_errors += stats->estats.tx_ip_header_errors; ++ gmac_stats->tx_stats.tx_ip_payload_errors += stats->estats.tx_ip_payload_errors; ++ gmac_stats->tx_stats.tx_dropped += stats->estats.tx_dropped; ++ gmac_stats->tx_stats.tx_ts_create_errors += stats->estats.tx_ts_create_errors; + + gmac_stats->hw_errs[0] += stats->estats.hw_errs[0]; + gmac_stats->hw_errs[1] += stats->estats.hw_errs[1]; +@@ -121,36 +130,6 @@ void nss_data_plane_hal_stats_sync(struc + gmac_stats->hw_errs[7] += stats->estats.hw_errs[7]; + gmac_stats->hw_errs[8] += stats->estats.hw_errs[8]; + gmac_stats->hw_errs[9] += stats->estats.hw_errs[9]; +- gmac_stats->rx_missed += stats->estats.rx_missed; +- +- gmac_stats->fifo_overflows += stats->estats.fifo_overflows; +- gmac_stats->rx_scatter_errors += stats->estats.rx_scatter_errors; +- gmac_stats->tx_ts_create_errors += stats->estats.tx_ts_create_errors; +- gmac_stats->gmac_total_ticks += stats->estats.gmac_total_ticks; +- gmac_stats->gmac_worst_case_ticks += stats->estats.gmac_worst_case_ticks; +- gmac_stats->gmac_iterations += stats->estats.gmac_iterations; +- gmac_stats->tx_pause_frames += stats->estats.tx_pause_frames; +- gmac_stats->mmc_rx_overflow_errors += stats->estats.mmc_rx_overflow_errors; +- gmac_stats->mmc_rx_watchdog_timeout_errors += stats->estats.mmc_rx_watchdog_timeout_errors; +- gmac_stats->mmc_rx_crc_errors += stats->estats.mmc_rx_crc_errors; +- gmac_stats->mmc_rx_ip_header_errors += stats->estats.mmc_rx_ip_header_errors; +- gmac_stats->mmc_rx_octets_g += stats->estats.mmc_rx_octets_g; +- gmac_stats->mmc_rx_ucast_frames += stats->estats.mmc_rx_ucast_frames; +- gmac_stats->mmc_rx_bcast_frames += stats->estats.mmc_rx_bcast_frames; +- gmac_stats->mmc_rx_mcast_frames += stats->estats.mmc_rx_mcast_frames; +- gmac_stats->mmc_rx_undersize += stats->estats.mmc_rx_undersize; +- gmac_stats->mmc_rx_oversize += stats->estats.mmc_rx_oversize; +- gmac_stats->mmc_rx_jabber += stats->estats.mmc_rx_jabber; +- gmac_stats->mmc_rx_octets_gb += stats->estats.mmc_rx_octets_gb; +- gmac_stats->mmc_rx_frag_frames_g += stats->estats.mmc_rx_frag_frames_g; +- gmac_stats->mmc_tx_octets_g += stats->estats.mmc_tx_octets_g; +- gmac_stats->mmc_tx_ucast_frames += stats->estats.mmc_tx_ucast_frames; +- gmac_stats->mmc_tx_bcast_frames += stats->estats.mmc_tx_bcast_frames; +- gmac_stats->mmc_tx_mcast_frames += stats->estats.mmc_tx_mcast_frames; +- gmac_stats->mmc_tx_deferred += stats->estats.mmc_tx_deferred; +- gmac_stats->mmc_tx_single_col += stats->estats.mmc_tx_single_col; +- gmac_stats->mmc_tx_multiple_col += stats->estats.mmc_tx_multiple_col; +- gmac_stats->mmc_tx_octets_gb += stats->estats.mmc_tx_octets_gb; + + spin_unlock_bh(&nss_data_plane_hal_gmac_stats_lock); + } +@@ -161,25 +140,7 @@ void nss_data_plane_hal_stats_sync(struc + uint16_t nss_data_plane_hal_get_mtu_sz(uint16_t mtu) + { + /* +- * GMACs support 3 Modes +- * Normal Mode Payloads upto 1522 Bytes ( 1500 + 14 + 4(Vlan) + 4(CRC)) +- * Mini Jumbo Mode Payloads upto 2000 Bytes (1978 + 14 + 4(Vlan) + 4 (CRC)) +- * Full Jumbo Mode payloads upto 9022 Bytes (9000 + 14 + 4(Vlan) + 4 (CRC)) +- */ +- +- /* +- * The configured MTU value on a GMAC interface should be one of these +- * cases. Finding the Needed MTU size that is required for GMAC to +- * successfully receive the frame. ++ * Return MTU value as is. + */ +- if (mtu <= NSS_DP_GMAC_NORMAL_FRAME_MTU) { +- return NSS_DP_GMAC_NORMAL_FRAME_MTU; +- } +- if (mtu <= NSS_DP_GMAC_MINI_JUMBO_FRAME_MTU) { +- return NSS_DP_GMAC_MINI_JUMBO_FRAME_MTU; +- } +- if (mtu <= NSS_DP_GMAC_FULL_JUMBO_FRAME_MTU) { +- return NSS_DP_GMAC_FULL_JUMBO_FRAME_MTU; +- } +- return 0; ++ return mtu; + } diff --git a/qca-nss-drv/patches/0001-nss-drv-replace-ioremap_nocache-with-ioremap.patch b/qca-nss-drv/patches/0001-nss-drv-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 0000000..d5f0bc7 --- /dev/null +++ b/qca-nss-drv/patches/0001-nss-drv-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,153 @@ +From dddfe22459a988a5b86d195bc3cc3bd3c2ac7037 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 14 Jan 2023 21:52:38 +0100 +Subject: [PATCH 1/4] nss-drv: replace ioremap_nocache() with ioremap() + +Since 5.5 ioremap_nocache is equal to ioremap on all archs and was removed +from the kernel, so just use ioremap instead. + +Signed-off-by: Robert Marko +--- + nss_hal/fsm9010/nss_hal_pvt.c | 2 +- + nss_hal/ipq50xx/nss_hal_pvt.c | 6 +++--- + nss_hal/ipq60xx/nss_hal_pvt.c | 8 ++++---- + nss_hal/ipq806x/nss_hal_pvt.c | 4 ++-- + nss_hal/ipq807x/nss_hal_pvt.c | 6 +++--- + nss_hal/ipq95xx/nss_hal_pvt.c | 6 +++--- + nss_hal/nss_hal.c | 4 ++-- + nss_meminfo.c | 2 +- + nss_ppe.c | 2 +- + 9 files changed, 20 insertions(+), 20 deletions(-) + +--- a/nss_hal/fsm9010/nss_hal_pvt.c ++++ b/nss_hal/fsm9010/nss_hal_pvt.c +@@ -145,7 +145,7 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->vphys = res_vphys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = nss_ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +--- a/nss_hal/ipq50xx/nss_hal_pvt.c ++++ b/nss_hal/ipq50xx/nss_hal_pvt.c +@@ -185,13 +185,13 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = nss_ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = nss_ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -349,7 +349,7 @@ static int __nss_hal_common_reset(struct + + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = nss_ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; +--- a/nss_hal/ipq60xx/nss_hal_pvt.c ++++ b/nss_hal/ipq60xx/nss_hal_pvt.c +@@ -208,13 +208,13 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = nss_ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = nss_ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -434,13 +434,13 @@ static int __nss_hal_common_reset(struct + + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = nss_ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; + } + +- nss_misc_reset_flag = ioremap_nocache(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); ++ nss_misc_reset_flag = nss_ioremap(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); + if (!nss_misc_reset_flag) { + pr_err("%px: ioremap fail for nss_misc_reset_flag\n", nss_dev); + return -EFAULT; +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -461,7 +461,7 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->vphys = res_vphys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = nss_ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +@@ -714,7 +714,7 @@ static int __nss_hal_common_reset(struct + } + of_node_put(cmn); + +- fpb_base = ioremap_nocache(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); ++ fpb_base = nss_ioremap(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); + if (!fpb_base) { + pr_err("%px: ioremap fail for nss_fpb_base\n", nss_dev); + return -EFAULT; +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -237,7 +237,7 @@ static struct nss_platform_data *__nss_h + npd->vphys = res_vphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = nss_ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +@@ -250,7 +250,7 @@ static struct nss_platform_data *__nss_h + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = nss_ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -470,7 +470,7 @@ static int __nss_hal_common_reset(struct + } + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = nss_ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; +--- a/nss_ppe.c ++++ b/nss_ppe.c +@@ -357,7 +357,7 @@ void nss_ppe_init(void) + /* + * Get the PPE base address + */ +- ppe_pvt.ppe_base = ioremap_nocache(PPE_BASE_ADDR, PPE_REG_SIZE); ++ ppe_pvt.ppe_base = nss_ioremap(PPE_BASE_ADDR, PPE_REG_SIZE); + if (!ppe_pvt.ppe_base) { + nss_warning("DRV can't get PPE base address\n"); + return; diff --git a/qca-nss-drv/patches/0002-nss-drv-add-support-for-kernel-5.15.patch b/qca-nss-drv/patches/0002-nss-drv-add-support-for-kernel-5.15.patch new file mode 100644 index 0000000..c462cd1 --- /dev/null +++ b/qca-nss-drv/patches/0002-nss-drv-add-support-for-kernel-5.15.patch @@ -0,0 +1,49 @@ +From 2a3b9f4659542e529f4e1a535c33dfde7e272707 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 5 Apr 2022 18:10:57 +0200 +Subject: [PATCH 2/4] nss-drv: add support for kernel 5.15 + +- Fix coredump panic notifier include change. +- Fix skb ZEROCOPY flag. +- Add skb reuse support for 5.15 kernel version. + +Signed-off-by: Ansuel Smith +--- + nss_core.c | 5 +++-- + nss_coredump.c | 4 ++++ + nss_hal/nss_hal.c | 1 + + 3 files changed, 9 insertions(+), 2 deletions(-) + +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + + #include "nss_hal.h" + #include "nss_arch.h" +@@ -58,9 +59,9 @@ int nss_hal_firmware_load(struct nss_ctx + int rc; + + if (nss_ctx->id == 0) { +- rc = request_firmware(&nss_fw, NSS_AP0_IMAGE, &(nss_dev->dev)); ++ rc = firmware_request_nowarn(&nss_fw, NSS_AP0_IMAGE, &(nss_dev->dev)); + } else if (nss_ctx->id == 1) { +- rc = request_firmware(&nss_fw, NSS_AP1_IMAGE, &(nss_dev->dev)); ++ rc = firmware_request_nowarn(&nss_fw, NSS_AP1_IMAGE, &(nss_dev->dev)); + } else { + nss_warning("%px: Invalid nss dev: %d\n", nss_ctx, nss_ctx->id); + return -EINVAL; +--- a/nss_data_plane/nss_data_plane_gmac.c ++++ b/nss_data_plane/nss_data_plane_gmac.c +@@ -20,7 +20,7 @@ + #include "nss_tx_rx_common.h" + #include + +-#define NSS_DP_GMAC_SUPPORTED_FEATURES (NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_FRAGLIST | (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_UFO)) ++#define NSS_DP_GMAC_SUPPORTED_FEATURES (NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_FRAGLIST | (NETIF_F_TSO | NETIF_F_TSO6)) + #define NSS_DATA_PLANE_GMAC_MAX_INTERFACES 4 + + static DEFINE_SPINLOCK(nss_data_plane_gmac_stats_lock); diff --git a/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch b/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch new file mode 100644 index 0000000..09d1039 --- /dev/null +++ b/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch @@ -0,0 +1,28 @@ +From a6e3e81daab4eb9acbdef0ad1fed056e1bfbe320 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 8 Jun 2021 23:24:43 +0200 +Subject: [PATCH 3/4] DMA: Fix NULL pointer exceptions + +There are multiple instances that pass NULL instead +of device to DMA functions. +That is incorrect and will cause kernel NULL pointer +exceptions. + +So, simply pass the device structure pointers. + +Signed-off-by: Robert Marko +--- + nss_core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -1664,7 +1664,7 @@ static int32_t nss_core_handle_cause_que + * + */ + if (unlikely((buffer_type == N2H_BUFFER_CRYPTO_RESP))) { +- dma_unmap_single(NULL, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); ++ dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); + goto consume; + } + diff --git a/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch b/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch new file mode 100644 index 0000000..a884384 --- /dev/null +++ b/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch @@ -0,0 +1,564 @@ +From e6814c47d22ee5133a71016375239f87ea265794 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Tue, 5 Apr 2022 15:38:18 +0200 +Subject: [PATCH 4/4] nss-drv: rework NSS_CORE_DMA_CACHE_MAINT ops + +Rework NSS_CORE_DMA_CACHE_MAINT ops to use standard dma sync ops instead +of using the direct arch function. This permit to skip any hack/patch +needed for nss-drv to correctly compile on upstream kernel. + +We drop any NSS_CORE_DMA_CACHE_MAINT use in nss_core and we correctly +use the dma_sync_single_for_device we correctly dma addr using the new +DMA helper. +We drop sync for IOREMAP addr and we just leave a memory block. +We hope the nss_profiler is correctly ported. +We finally drop the NSS_CORE_DMA_CACHE_MAINT jus in case someone wants +to use it. + +Signed-off-by: Christian Marangi +--- + nss_core.c | 136 +++++++++++++++++++++++++--------- + nss_core.h | 41 +++++----- + nss_hal/ipq806x/nss_hal_pvt.c | 5 +- + nss_hal/ipq807x/nss_hal_pvt.c | 5 +- + nss_meminfo.c | 5 +- + nss_profiler.c | 3 +- + 6 files changed, 127 insertions(+), 68 deletions(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -1476,6 +1476,8 @@ static inline void nss_core_handle_empty + uint32_t count, uint32_t hlos_index, + uint16_t mask) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ + while (count) { + /* + * Since we only return the primary skb, we have no way to unmap +@@ -1529,7 +1531,9 @@ next: + n2h_desc_ring->hlos_index = hlos_index; + if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, ++ n2h_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + } + +@@ -1551,6 +1555,7 @@ static int32_t nss_core_handle_cause_que + struct nss_ctx_instance *nss_ctx = int_ctx->nss_ctx; + struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct nss_if_mem_map *if_map = mem_ctx->if_map; ++ int dma_size; + + qid = nss_core_cause_to_queue(cause); + +@@ -1562,7 +1567,8 @@ static int32_t nss_core_handle_cause_que + n2h_desc_ring = &nss_ctx->n2h_desc_ring[qid]; + desc_if = &n2h_desc_ring->desc_ring; + desc_ring = desc_if->desc; +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_ctx->dev, n2h_nss_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + nss_index = if_map->n2h_nss_index[qid]; + +@@ -1591,13 +1597,23 @@ static int32_t nss_core_handle_cause_que + start = hlos_index; + end = (hlos_index + count) & mask; + if (end > start) { +- dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor)); ++ dma_size = sizeof(struct n2h_descriptor) * (end - start + 1); ++ ++ dma_sync_single_for_cpu(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, start), ++ dma_size, DMA_FROM_DEVICE); + } else { + /* + * We have wrapped around + */ +- dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct n2h_descriptor)); +- dmac_inv_range((void *)&desc_ring[0], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor)); ++ dma_size = sizeof(struct n2h_descriptor) * (mask - start + 1); ++ ++ dma_sync_single_for_cpu(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, start), ++ dma_size, DMA_FROM_DEVICE); ++ ++ dma_size = sizeof(struct n2h_descriptor) * (end + 1); ++ ++ dma_sync_single_for_cpu(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, 0), dma_size, ++ DMA_FROM_DEVICE); + } + + /* +@@ -1726,7 +1742,8 @@ next: + n2h_desc_ring->hlos_index = hlos_index; + if_map->n2h_hlos_index[qid] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, n2h_hlos_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + return count; +@@ -1738,11 +1755,12 @@ next: + */ + static void nss_core_init_nss(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct nss_top_instance *nss_top; + int ret; + int i; + +- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(*if_map), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(*if_map), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + + /* +@@ -1839,6 +1857,7 @@ static void nss_core_alloc_paged_buffers + uint16_t count, int16_t mask, int32_t hlos_index, uint32_t alloc_fail_count, + uint32_t buffer_type, uint32_t buffer_queue, uint32_t stats_index) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct sk_buff *nbuf; + struct page *npage; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[buffer_queue]; +@@ -1908,7 +1927,9 @@ static void nss_core_alloc_paged_buffers + /* + * Flush the descriptor + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, buffer_queue, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + hlos_index = (hlos_index + 1) & (mask); + count--; +@@ -1922,7 +1943,8 @@ static void nss_core_alloc_paged_buffers + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[buffer_queue] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[buffer_queue], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, buffer_queue), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + NSS_PKT_STATS_INC(&nss_top->stats_drv[stats_index]); +@@ -1935,7 +1957,7 @@ static void nss_core_alloc_paged_buffers + static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map, + int jumbo_mru, uint16_t count, int16_t mask, int32_t hlos_index) + { +- ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct sk_buff *nbuf; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; + struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring; +@@ -1982,7 +2004,9 @@ static void nss_core_alloc_jumbo_mru_buf + /* + * Flush the descriptor + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + hlos_index = (hlos_index + 1) & (mask); + count--; +@@ -1996,7 +2020,8 @@ static void nss_core_alloc_jumbo_mru_buf + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]); +@@ -2009,6 +2034,7 @@ static void nss_core_alloc_jumbo_mru_buf + static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map, + uint16_t max_buf_size, uint16_t count, int16_t mask, int32_t hlos_index) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; + struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring; + struct h2n_descriptor *desc_ring = desc_if->desc; +@@ -2016,6 +2042,7 @@ static void nss_core_alloc_max_avail_siz + uint16_t payload_len = max_buf_size + NET_SKB_PAD; + uint16_t start = hlos_index; + uint16_t prev_hlos_index; ++ int dma_size; + + while (count) { + dma_addr_t buffer; +@@ -2068,13 +2095,26 @@ static void nss_core_alloc_max_avail_siz + * Flush the descriptors, including the descriptor at prev_hlos_index. + */ + if (prev_hlos_index > start) { +- dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor)); ++ dma_size = sizeof(struct h2n_descriptor) * (prev_hlos_index - start + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, start), ++ dma_size, DMA_TO_DEVICE); + } else { + /* + * We have wrapped around + */ +- dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct h2n_descriptor)); +- dmac_clean_range((void *)&desc_ring[0], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor)); ++ dma_size = sizeof(struct h2n_descriptor) * (mask - start + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, start), ++ dma_size, DMA_TO_DEVICE); ++ ++ dma_size = sizeof(struct h2n_descriptor) * (prev_hlos_index + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, 0), ++ dma_size, DMA_TO_DEVICE); + } + + /* +@@ -2085,7 +2125,8 @@ static void nss_core_alloc_max_avail_siz + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]); +@@ -2098,6 +2139,7 @@ static void nss_core_alloc_max_avail_siz + static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss_ctx, + struct nss_if_mem_map *if_map, uint16_t max_buf_size) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + uint16_t count, size, mask; + int32_t nss_index, hlos_index; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; +@@ -2108,7 +2150,8 @@ static inline void nss_core_handle_empty + /* + * Check how many empty buffers could be filled in queue + */ +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; + +@@ -2153,6 +2196,7 @@ static inline void nss_core_handle_empty + static inline void nss_core_handle_paged_empty_buffer_sos(struct nss_ctx_instance *nss_ctx, + struct nss_if_mem_map *if_map, uint16_t max_buf_size) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + uint16_t count, size, mask; + int32_t nss_index, hlos_index; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE]; +@@ -2160,7 +2204,8 @@ static inline void nss_core_handle_paged + /* + * Check how many empty buffers could be filled in queue + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE]; + +@@ -2751,9 +2796,11 @@ void nss_skb_reuse(struct sk_buff *nbuf) + * Sends one skb to NSS FW + */ + static inline int32_t nss_core_send_buffer_simple_skb(struct nss_ctx_instance *nss_ctx, +- struct h2n_desc_if_instance *desc_if, uint32_t if_num, +- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) ++ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, ++ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ struct nss_if_mem_map *if_map = mem_ctx->if_map; + struct h2n_descriptor *desc_ring = desc_if->desc; + struct h2n_descriptor *desc; + uint16_t bit_flags; +@@ -2807,7 +2854,8 @@ static inline int32_t nss_core_send_buff + (nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len, + sz, (uint32_t)nbuf->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + /* + * We are done using the skb fields and can reuse it now +@@ -2831,7 +2879,8 @@ no_reuse: + (nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len, + (uint16_t)skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_SIMPLE]); + return 1; +@@ -2845,9 +2894,11 @@ no_reuse: + * Used to differentiate from FRAGLIST + */ + static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss_ctx, +- struct h2n_desc_if_instance *desc_if, uint32_t if_num, +- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) ++ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, ++ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ struct nss_if_mem_map *if_map = mem_ctx->if_map; + struct h2n_descriptor *desc_ring = desc_if->desc; + struct h2n_descriptor *desc; + const skb_frag_t *frag; +@@ -2887,7 +2938,8 @@ static inline int32_t nss_core_send_buff + (nss_ptr_t)NULL, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len, + skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + /* + * Now handle rest of the fragments. +@@ -2911,7 +2963,8 @@ static inline int32_t nss_core_send_buff + (nss_ptr_t)NULL, 0, skb_frag_size(frag), skb_frag_size(frag), + nbuf->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + } + + /* +@@ -2927,7 +2980,8 @@ static inline int32_t nss_core_send_buff + desc->bit_flags &= ~(H2N_BIT_FLAG_DISCARD); + desc->opaque = (nss_ptr_t)nbuf; + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_NR_FRAGS]); + return i+1; +@@ -2941,9 +2995,11 @@ static inline int32_t nss_core_send_buff + * Used to differentiate from FRAGS + */ + static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss_ctx, +- struct h2n_desc_if_instance *desc_if, uint32_t if_num, +- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) ++ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, ++ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ struct nss_if_mem_map *if_map = mem_ctx->if_map; + struct h2n_descriptor *desc_ring = desc_if->desc; + struct h2n_descriptor *desc; + dma_addr_t buffer; +@@ -2982,7 +3038,8 @@ static inline int32_t nss_core_send_buff + (nss_ptr_t)nbuf, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len, + skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + /* + * Walk the frag_list in nbuf +@@ -3035,7 +3092,8 @@ static inline int32_t nss_core_send_buff + (nss_ptr_t)iter, iter->data - iter->head, iter->len - iter->data_len, + skb_end_offset(iter), iter->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + i++; + } +@@ -3054,7 +3112,8 @@ static inline int32_t nss_core_send_buff + * Update bit flag for last descriptor. + */ + desc->bit_flags |= H2N_BIT_FLAG_LAST_SEGMENT; +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_FRAGLIST]); + return i+1; +@@ -3133,8 +3192,10 @@ int32_t nss_core_send_buffer(struct nss_ + * We need to work out if there's sufficent space in our transmit descriptor + * ring to place all the segments of a nbuf. + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); ++ + nss_index = if_map->h2n_nss_index[qid]; + h2n_desc_ring->nss_index_local = nss_index; + count = ((nss_index - hlos_index - 1) + size) & (mask); +@@ -3199,13 +3260,13 @@ int32_t nss_core_send_buffer(struct nss_ + count = 0; + if (likely((segments == 0) || is_bounce)) { + count = nss_core_send_buffer_simple_skb(nss_ctx, desc_if, if_num, +- nbuf, hlos_index, flags, buffer_type, mss); ++ nbuf, qid, hlos_index, flags, buffer_type, mss); + } else if (skb_has_frag_list(nbuf)) { + count = nss_core_send_buffer_fraglist(nss_ctx, desc_if, if_num, +- nbuf, hlos_index, flags, buffer_type, mss); ++ nbuf, qid, hlos_index, flags, buffer_type, mss); + } else { + count = nss_core_send_buffer_nr_frags(nss_ctx, desc_if, if_num, +- nbuf, hlos_index, flags, buffer_type, mss); ++ nbuf, qid, hlos_index, flags, buffer_type, mss); + } + + if (unlikely(count <= 0)) { +@@ -3229,7 +3290,8 @@ int32_t nss_core_send_buffer(struct nss_ + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[qid] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + #ifdef CONFIG_DEBUG_KMEMLEAK +--- a/nss_core.h ++++ b/nss_core.h +@@ -108,9 +108,22 @@ + + /* + * Cache operation +- */ +-#define NSS_CORE_DSB() dsb(sy) +-#define NSS_CORE_DMA_CACHE_MAINT(start, size, dir) nss_core_dma_cache_maint(start, size, dir) ++*/ ++#define n2h_desc_index_offset(_index) sizeof(struct n2h_descriptor) * (_index) ++#define h2n_desc_index_offset(_index) sizeof(struct h2n_descriptor) * (_index) ++ ++#define n2h_desc_index_to_dma(_if_map_addr, _qid, _index) (_if_map_addr)->n2h_desc_if[(_qid)].desc_addr + n2h_desc_index_offset(_index) ++#define h2n_desc_index_to_dma(_if_map_addr, _qid, _index) (_if_map_addr)->h2n_desc_if[(_qid)].desc_addr + h2n_desc_index_offset(_index) ++ ++#define h2n_nss_index_offset offsetof(struct nss_if_mem_map, h2n_nss_index) ++#define n2h_nss_index_offset offsetof(struct nss_if_mem_map, n2h_nss_index) ++#define h2n_hlos_index_offset offsetof(struct nss_if_mem_map, h2n_hlos_index) ++#define n2h_hlos_index_offset offsetof(struct nss_if_mem_map, n2h_hlos_index) ++ ++#define h2n_nss_index_to_dma(_if_map_addr, _index) (_if_map_addr) + h2n_nss_index_offset + (sizeof(uint32_t) * (_index)) ++#define n2h_nss_index_to_dma(_if_map_addr, _index) (_if_map_addr) + n2h_nss_index_offset + (sizeof(uint32_t) * (_index)) ++#define h2n_hlos_index_to_dma(_if_map_addr, _index) (_if_map_addr) + h2n_hlos_index_offset + (sizeof(uint32_t) * (_index)) ++#define n2h_hlos_index_to_dma(_if_map_addr, _index) (_if_map_addr) + n2h_hlos_index_offset + (sizeof(uint32_t) * (_index)) + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 6, 0)) + #define nss_ioremap ioremap_nocache +@@ -119,26 +132,11 @@ + #endif + + /* +- * nss_core_dma_cache_maint() +- * Perform the appropriate cache op based on direction +- */ +-static inline void nss_core_dma_cache_maint(void *start, uint32_t size, int direction) +-{ +- switch (direction) { +- case DMA_FROM_DEVICE:/* invalidate only */ +- dmac_inv_range(start, start + size); +- break; +- case DMA_TO_DEVICE:/* writeback only */ +- dmac_clean_range(start, start + size); +- break; +- case DMA_BIDIRECTIONAL:/* writeback and invalidate */ +- dmac_flush_range(start, start + size); +- break; +- default: +- BUG(); +- } +-} +- ++ * Cache operation ++*/ ++#define NSS_CORE_DSB() dsb(sy) ++#define NSS_CORE_DMA_CACHE_MAINT(dev, start, size, dir) BUILD_BUG_ON_MSG(1, \ ++ "NSS_CORE_DMA_CACHE_MAINT is deprecated. Fix the code to use correct dma_sync_* API") + #define NSS_DEVICE_IF_START NSS_PHYSICAL_IF_START + + #define NSS_IS_IF_TYPE(type, if_num) ((if_num >= NSS_##type##_IF_START) && (if_num < (NSS_##type##_IF_START + NSS_MAX_##type##_INTERFACES))) +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -477,10 +477,9 @@ static struct nss_platform_data *__nss_h + /* + * Clear TCM memory used by this core + */ +- for (i = 0; i < resource_size(&res_vphys) ; i += 4) { ++ for (i = 0; i < resource_size(&res_vphys) ; i += 4) + nss_write_32(npd->vmap, i, 0); +- NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE); +- } ++ + NSS_CORE_DSB(); + + /* +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -259,10 +259,9 @@ static struct nss_platform_data *__nss_h + /* + * Clear TCM memory used by this core + */ +- for (i = 0; i < resource_size(&res_vphys) ; i += 4) { ++ for (i = 0; i < resource_size(&res_vphys) ; i += 4) + nss_write_32(npd->vmap, i, 0); +- NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE); +- } ++ + NSS_CORE_DSB(); + + /* +--- a/nss_meminfo.c ++++ b/nss_meminfo.c +@@ -415,7 +415,6 @@ static bool nss_meminfo_init_block_lists + /* + * Flush the updated meminfo request. + */ +- NSS_CORE_DMA_CACHE_MAINT(r, sizeof(struct nss_meminfo_request), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + /* +@@ -546,7 +545,7 @@ static bool nss_meminfo_configure_n2h_h2 + * Bring a fresh copy of if_map from memory in order to read it correctly. + */ + if_map = mem_ctx->if_map; +- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + + if_map->n2h_rings = NSS_N2H_RING_COUNT; +@@ -584,7 +583,7 @@ static bool nss_meminfo_configure_n2h_h2 + /* + * Flush the updated nss_if_mem_map. + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + return true; +--- a/nss_profiler.c ++++ b/nss_profiler.c +@@ -209,11 +209,12 @@ EXPORT_SYMBOL(nss_profile_dma_deregister + struct nss_profile_sdma_ctrl *nss_profile_dma_get_ctrl(struct nss_ctx_instance *nss_ctx) + { + struct nss_profile_sdma_ctrl *ctrl = nss_ctx->meminfo_ctx.sdma_ctrl; ++ int size = offsetof(struct nss_profile_sdma_ctrl, cidx); + if (!ctrl) { + return ctrl; + } + +- dmac_inv_range(ctrl, &ctrl->cidx); ++ dma_sync_single_for_cpu(nss_ctx->dev, (dma_addr_t) ctrl, size, DMA_FROM_DEVICE); + dsb(sy); + return ctrl; + } diff --git a/qca-nss-drv/patches/0005-nss-drv-rework-getting-the-reserved-memory-size.patch b/qca-nss-drv/patches/0005-nss-drv-rework-getting-the-reserved-memory-size.patch new file mode 100644 index 0000000..b8e63a6 --- /dev/null +++ b/qca-nss-drv/patches/0005-nss-drv-rework-getting-the-reserved-memory-size.patch @@ -0,0 +1,114 @@ +From 1c2b564d7b29644765925a784d468f40555ded8a Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 10 Feb 2023 12:50:51 +0100 +Subject: [PATCH] nss-drv: rework getting the reserved-memory size + +Currently, the way NSS DRV gets the reserved memory node strictly depends +on the nss@40000000 node being present so it can find it after globaly +looking for the reserved-memory node and then going through its children. + +After that its evaluation the address and size cells manually in order to +properly calculate the size of reserved-memory. + +We can make this way more reliable and generic, so lets pass the memory +region wia the NSS common DTS node, match it via its compatible and then +get the memory region phandle and simply convert it to a resource. + +Signed-off-by: Robert Marko +--- + nss_core.c | 70 +++++++++++++++++++++++------------------------------- + 1 file changed, 30 insertions(+), 40 deletions(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -26,6 +26,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #ifdef CONFIG_BRIDGE_NETFILTER +@@ -491,50 +493,38 @@ static void nss_core_handle_crypto_pkt(s + */ + static uint32_t nss_soc_mem_info(void) + { +- struct device_node *node; +- struct device_node *snode; +- int addr_cells; +- int size_cells; +- int n_items; +- uint32_t nss_msize = 8 << 20; /* default: 8MB */ +- const __be32 *ppp; +- +- node = of_find_node_by_name(NULL, "reserved-memory"); +- if (!node) { +- nss_info_always("reserved-memory not found\n"); +- return nss_msize; +- } +- +- ppp = (__be32 *)of_get_property(node, "#address-cells", NULL); +- addr_cells = ppp ? be32_to_cpup(ppp) : 2; +- nss_info("%px addr cells %d\n", ppp, addr_cells); +- ppp = (__be32 *)of_get_property(node, "#size-cells", NULL); +- size_cells = ppp ? be32_to_cpup(ppp) : 2; +- nss_info("%px size cells %d\n", ppp, size_cells); +- +- for_each_child_of_node(node, snode) { +- /* +- * compare (snode->full_name, "/reserved-memory/nss@40000000") may be safer +- */ +- nss_info("%px snode %s fn %s\n", snode, snode->name, snode->full_name); +- if (strcmp(snode->name, "nss") == 0) +- break; +- } +- of_node_put(node); +- if (!snode) { +- nss_info_always("nss@node not found: needed to determine NSS reserved DDR\n"); +- return nss_msize; +- } +- +- ppp = (__be32 *)of_get_property(snode, "reg", &n_items); +- if (ppp) { +- n_items /= sizeof(ppp[0]); +- nss_msize = be32_to_cpup(ppp + addr_cells + size_cells - 1); +- nss_info("addr/size storage words %d %d # words %d in DTS, ddr size %x\n", +- addr_cells, size_cells, n_items, nss_msize); ++ struct device_node *common_node, *memory_node; ++ struct resource r; ++ int ret; ++ ++ common_node = of_find_compatible_node(NULL, NULL, "qcom,nss-common"); ++ if (!common_node) { ++ nss_info_always("NSS common node not found!\n"); ++ goto err_use_default_memsize; ++ } ++ ++ memory_node = of_parse_phandle(common_node, "memory-region", 0); ++ if (!memory_node) { ++ nss_info_always("NSS reserved-memory node not found!\n"); ++ goto err_use_default_memsize; ++ } ++ ++ ret = of_address_to_resource(memory_node, 0, &r); ++ of_node_put(common_node); ++ of_node_put(memory_node); ++ if (ret) { ++ nss_info_always("NSS reserved-memory resource not found!\n"); ++ goto err_use_default_memsize; + } +- of_node_put(snode); +- return nss_msize; ++ ++ nss_info_always("NSS DDR size is 0x%x\n", (uint32_t) resource_size(&r)); ++ ++ return resource_size(&r); ++ ++err_use_default_memsize: ++ nss_info_always("Using default NSS reserved-memory size of 0x%x !\n", SZ_8M); ++ ++ return SZ_8M; + } + + /* diff --git a/qca-nss-drv/patches/0006-nss-drv-Fix-nss_clmap_stats-enum-int-compilation-error-GCC-13.patch b/qca-nss-drv/patches/0006-nss-drv-Fix-nss_clmap_stats-enum-int-compilation-error-GCC-13.patch new file mode 100644 index 0000000..17d5cb6 --- /dev/null +++ b/qca-nss-drv/patches/0006-nss-drv-Fix-nss_clmap_stats-enum-int-compilation-error-GCC-13.patch @@ -0,0 +1,11 @@ +--- a/nss_clmap_stats.c ++++ b/nss_clmap_stats.c +@@ -66,7 +66,7 @@ void nss_clmap_stats_session_unregister( + * nss_clmap_stats_session_register + * Register debug statistic for clmap session. + */ +-bool nss_clmap_stats_session_register(uint32_t if_num, uint32_t if_type, struct net_device *netdev) ++bool nss_clmap_stats_session_register(uint32_t if_num, enum nss_clmap_interface_type if_type, struct net_device *netdev) + { + uint32_t i; + bool stats_status = false; diff --git a/qca-nss-drv/patches/0007-nss-drv-Fix-nss_wifili_if-compilation-error-GCC-13.patch b/qca-nss-drv/patches/0007-nss-drv-Fix-nss_wifili_if-compilation-error-GCC-13.patch new file mode 100644 index 0000000..cc4e38d --- /dev/null +++ b/qca-nss-drv/patches/0007-nss-drv-Fix-nss_wifili_if-compilation-error-GCC-13.patch @@ -0,0 +1,11 @@ +--- a/exports/nss_wifili_if.h ++++ b/exports/nss_wifili_if.h +@@ -2263,7 +2263,7 @@ void nss_wifili_release_external_if(nss_ + */ + uint8_t nss_wifili_thread_scheme_alloc(struct nss_ctx_instance *nss_ctx, + int32_t radio_ifnum, +- uint32_t radio_priority); ++ enum nss_wifili_thread_scheme_priority radio_priority); + + /** + * nss_wifili_thread_scheme_dealloc diff --git a/qca-nss-drv/patches/0008-Add-kernel-6.1-support.patch b/qca-nss-drv/patches/0008-Add-kernel-6.1-support.patch new file mode 100644 index 0000000..47fca01 --- /dev/null +++ b/qca-nss-drv/patches/0008-Add-kernel-6.1-support.patch @@ -0,0 +1,183 @@ +--- a/nss_hal/fsm9010/nss_hal_pvt.c ++++ b/nss_hal/fsm9010/nss_hal_pvt.c +@@ -291,7 +291,7 @@ static int __nss_hal_request_irq(struct + } + + int_ctx->irq = npd->irq[irq_num]; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi, 64); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi, 64); + return 0; + } + +--- a/nss_hal/ipq50xx/nss_hal_pvt.c ++++ b/nss_hal/ipq50xx/nss_hal_pvt.c +@@ -599,7 +599,7 @@ static int __nss_hal_request_irq(struct + return err; + } + +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, napi_poll_cb, napi_wgt); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, napi_poll_cb, napi_wgt); + int_ctx->cause = cause; + err = request_irq(irq, nss_hal_handle_irq, 0, irq_name, int_ctx); + if (err) { +--- a/nss_hal/ipq60xx/nss_hal_pvt.c ++++ b/nss_hal/ipq60xx/nss_hal_pvt.c +@@ -615,62 +615,62 @@ static int __nss_hal_request_irq(struct + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_sos", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_queue", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_TX_UNBLOCKED; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss-tx-unblock", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_0; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue0", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1) { + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_1; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue1", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2) { + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_2; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue2", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3) { + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_3; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue3", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE) { + int_ctx->cause = NSS_N2H_INTR_COREDUMP_COMPLETE; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_coredump_complete", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_paged_empty_buf_sos", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA) { + int_ctx->cause = NSS_N2H_INTR_PROFILE_DMA; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_profile_dma", int_ctx); + } + +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -1185,7 +1185,7 @@ static int __nss_hal_request_irq(struct + } + + int_ctx->irq = npd->irq[irq_num]; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi, 64); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi, 64); + + return 0; + } +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -659,62 +659,62 @@ static int __nss_hal_request_irq(struct + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_sos", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_queue", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_TX_UNBLOCKED; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss-tx-unblock", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_0; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue0", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1) { + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_1; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue1", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2) { + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_2; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue2", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3) { + int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_3; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue3", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE) { + int_ctx->cause = NSS_N2H_INTR_COREDUMP_COMPLETE; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_coredump_complete", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS) { +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); + int_ctx->cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS; + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_paged_empty_buf_sos", int_ctx); + } + + if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA) { + int_ctx->cause = NSS_N2H_INTR_PROFILE_DMA; +- netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); + err = request_irq(irq, nss_hal_handle_irq, 0, "nss_profile_dma", int_ctx); + } + diff --git a/qca-nss-drv/patches/0010-nss-drv-dynamic-interface-desc.patch b/qca-nss-drv/patches/0010-nss-drv-dynamic-interface-desc.patch new file mode 100644 index 0000000..bafd3f1 --- /dev/null +++ b/qca-nss-drv/patches/0010-nss-drv-dynamic-interface-desc.patch @@ -0,0 +1,18 @@ +--- a/nss_dynamic_interface_stats.c ++++ b/nss_dynamic_interface_stats.c +@@ -88,8 +88,15 @@ const char *nss_dynamic_interface_type_n + "NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_H2N", + "NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_EXTERNAL0", + "NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_EXTERNAL1", ++ "NSS_DYNAMIC_INTERFACE_TYPE_TLS_INNER", ++ "NSS_DYNAMIC_INTERFACE_TYPE_TLS_OUTER", ++ "NSS_DYNAMIC_INTERFACE_TYPE_MIRROR", ++ "NSS_DYNAMIC_INTERFACE_TYPE_WIFI_EXT_VDEV_WDS", + "NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER", + "NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER", ++ "NSS_DYNAMIC_INTERFACE_TYPE_WIFI_EXT_VDEV_VLAN", ++ "NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER", ++ "NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER" + }; + + /* diff --git a/qca-nss-drv/patches/0011-nss-drv-move-only-for-ipq806x.patch b/qca-nss-drv/patches/0011-nss-drv-move-only-for-ipq806x.patch new file mode 100644 index 0000000..4bae1f5 --- /dev/null +++ b/qca-nss-drv/patches/0011-nss-drv-move-only-for-ipq806x.patch @@ -0,0 +1,57 @@ +--- a/nss_stats.c ++++ b/nss_stats.c +@@ -407,9 +407,9 @@ void nss_stats_create_dentry(char *name, + /* + * gmac_stats_ops + */ +-#ifdef NSS_DATA_PLANE_GENERIC_SUPPORT +-NSS_STATS_DECLARE_FILE_OPERATIONS(gmac); +-#endif ++// #ifdef NSS_DATA_PLANE_GENERIC_SUPPORT ++// NSS_STATS_DECLARE_FILE_OPERATIONS(gmac); ++// #endif + + /* + * wt_stats_ops +@@ -464,9 +464,9 @@ void nss_stats_init(void) + /* + * gmac_stats + */ +-#ifdef NSS_DATA_PLANE_GENERIC_SUPPORT +- nss_stats_create_dentry("gmac", &nss_gmac_stats_ops); +-#endif ++// #ifdef NSS_DATA_PLANE_GENERIC_SUPPORT ++// nss_stats_create_dentry("gmac", &nss_gmac_stats_ops); ++// #endif + + /* + * Per-project stats +--- a/Makefile ++++ b/Makefile +@@ -26,7 +26,6 @@ qca-nss-drv-objs := \ + nss_n2h_stats.o \ + nss_n2h_strings.o \ + nss_pm.o \ +- nss_profiler.o \ + nss_project.o \ + nss_rps.o \ + nss_stats.o \ +@@ -40,7 +39,6 @@ qca-nss-drv-objs += nss_hal/nss_hal.o + + ifneq "$(NSS_DRV_POINT_OFFLOAD)" "y" + qca-nss-drv-objs += \ +- nss_gmac_stats.o \ + nss_if.o \ + nss_if_log.o \ + nss_phys_if.o \ +@@ -381,7 +379,9 @@ endif + + ifeq ($(SoC),$(filter $(SoC),ipq806x)) + qca-nss-drv-objs += nss_data_plane/nss_data_plane_gmac.o \ +- nss_hal/ipq806x/nss_hal_pvt.o ++ nss_hal/ipq806x/nss_hal_pvt.o \ ++ nss_gmac_stats.o \ ++ nss_profiler.o + + ifneq "$(NSS_DRV_C2C_ENABLE)" "n" + ccflags-y += -DNSS_DRV_C2C_ENABLE diff --git a/qca-nss-drv/patches/0012-nss-drv-quiet-messages.patch b/qca-nss-drv/patches/0012-nss-drv-quiet-messages.patch new file mode 100644 index 0000000..b897d22 --- /dev/null +++ b/qca-nss-drv/patches/0012-nss-drv-quiet-messages.patch @@ -0,0 +1,37 @@ +--- a/nss_core.c ++++ b/nss_core.c +@@ -517,7 +517,7 @@ static uint32_t nss_soc_mem_info(void) + goto err_use_default_memsize; + } + +- nss_info_always("NSS DDR size is 0x%x\n", (uint32_t) resource_size(&r)); ++ nss_info("NSS DDR size is 0x%x\n", (uint32_t) resource_size(&r)); + + return resource_size(&r); + +--- a/nss_hal/ipq95xx/nss_hal_pvt.c ++++ b/nss_hal/ipq95xx/nss_hal_pvt.c +@@ -724,19 +724,19 @@ static int __nss_hal_clock_configure(str + } + } + +- nss_info_always("Supported Frequencies - "); ++ nss_info("Supported Frequencies - "); + for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) { + switch (nss_runtime_samples.freq_scale[i].frequency) { + case NSS_FREQ_748: +- nss_info_always("748 MHz "); ++ nss_info("748 MHz "); + break; + + case NSS_FREQ_1497: +- nss_info_always("1.497 GHz "); ++ nss_info("1.497 GHz "); + break; + + case NSS_FREQ_1689: +- nss_info_always("1.689 GHz "); ++ nss_info("1.689 GHz "); + break; + + default: diff --git a/qca-nss-drv/patches/0013-nss-drv-remove-legacy-wifi.patch b/qca-nss-drv/patches/0013-nss-drv-remove-legacy-wifi.patch new file mode 100644 index 0000000..2f5d7f3 --- /dev/null +++ b/qca-nss-drv/patches/0013-nss-drv-remove-legacy-wifi.patch @@ -0,0 +1,33 @@ +--- a/Makefile ++++ b/Makefile +@@ -350,10 +350,17 @@ endif + + ifneq "$(NSS_DRV_WIFIOFFLOAD_ENABLE)" "n" + ccflags-y += -DNSS_DRV_WIFIOFFLOAD_ENABLE ++ifneq "$(NSS_DRV_WIFI_LEGACY_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_WIFI_LEGACY_ENABLE + qca-nss-drv-objs += \ + nss_wifi.o \ + nss_wifi_log.o \ +- nss_wifi_stats.o \ ++ nss_wifi_stats.o ++ifeq ($(SoC),$(filter $(SoC),ipq806x)) ++ccflags-y += -DNSS_HAL_IPQ806x_SUPPORT ++endif ++endif ++qca-nss-drv-objs += \ + nss_wifi_vdev.o \ + nss_wifili.o \ + nss_wifili_log.o \ +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -587,7 +587,9 @@ int nss_hal_probe(struct platform_device + if (npd->wifioffload_enabled == NSS_FEATURE_ENABLED) { + nss_top->wifi_handler_id = nss_dev->id; + nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VAP] = nss_dev->id; ++#if defined(NSS_HAL_IPQ806x_SUPPORT) + nss_wifi_register_handler(); ++#endif + nss_wifili_register_handler(); + #ifdef NSS_DRV_WIFI_EXT_VDEV_ENABLE + nss_wifi_ext_vdev_register_handler(); diff --git a/qca-nss-drv/patches/0014-nss-drv-avoid-recreating-virt_if.patch b/qca-nss-drv/patches/0014-nss-drv-avoid-recreating-virt_if.patch new file mode 100644 index 0000000..6ad5aa1 --- /dev/null +++ b/qca-nss-drv/patches/0014-nss-drv-avoid-recreating-virt_if.patch @@ -0,0 +1,14 @@ +--- a/nss_stats.c ++++ b/nss_stats.c +@@ -395,8 +395,9 @@ size_t nss_stats_print(char *node, char + */ + void nss_stats_create_dentry(char *name, const struct file_operations *ops) + { +- if (!debugfs_create_file(name, 0400, nss_top_main.stats_dentry, &nss_top_main, ops)) { +- nss_warning("Failed to create debug entry for subsystem %s\n", name); ++ if (!debugfs_lookup(name, nss_top_main.stats_dentry)) ++ if (!debugfs_create_file(name, 0400, nss_top_main.stats_dentry, &nss_top_main, ops)) { ++ nss_warning("Failed to create debug entry for subsystem %s\n", name); + } + } + diff --git a/qca-nss-drv/patches/0015-nss-drv-fix-igs.patch b/qca-nss-drv/patches/0015-nss-drv-fix-igs.patch new file mode 100644 index 0000000..e027d8b --- /dev/null +++ b/qca-nss-drv/patches/0015-nss-drv-fix-igs.patch @@ -0,0 +1,40 @@ +--- a/nss_igs.c ++++ b/nss_igs.c +@@ -163,7 +163,7 @@ EXPORT_SYMBOL(nss_igs_register_if); + * nss_igs_get_context() + * Get the IGS context. + */ +-struct nss_ctx_instance *nss_igs_get_context() ++struct nss_ctx_instance *nss_igs_get_context(void) + { + return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.igs_handler_id]; + } +@@ -177,8 +177,9 @@ EXPORT_SYMBOL(nss_igs_get_context); + void nss_igs_module_save(struct tc_action_ops *act, struct module *module) + { + nss_assert(act); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) + nss_assert(act->type == TCA_ACT_MIRRED_NSS); +- ++#endif + nss_igs_module = module; + } + EXPORT_SYMBOL(nss_igs_module_save); +@@ -188,7 +189,7 @@ EXPORT_SYMBOL(nss_igs_module_save); + * nss_igs_module_get() + * Get the ingress shaping module reference. + */ +-bool nss_igs_module_get() ++bool nss_igs_module_get(void) + { + nss_assert(nss_igs_module); + return try_module_get(nss_igs_module); +@@ -199,7 +200,7 @@ EXPORT_SYMBOL(nss_igs_module_get); + * nss_igs_module_put() + * Release the ingress shaping module reference. + */ +-void nss_igs_module_put() ++void nss_igs_module_put(void) + { + nss_assert(nss_igs_module); + module_put(nss_igs_module); diff --git a/qca-nss-drv/patches/0016-nss-drv-add-support-for-kernel-6.6.patch b/qca-nss-drv/patches/0016-nss-drv-add-support-for-kernel-6.6.patch new file mode 100644 index 0000000..68b9594 --- /dev/null +++ b/qca-nss-drv/patches/0016-nss-drv-add-support-for-kernel-6.6.patch @@ -0,0 +1,251 @@ +--- a/nss_ppe_vp.c ++++ b/nss_ppe_vp.c +@@ -783,24 +783,6 @@ static struct ctl_table nss_ppe_vp_table + { } + }; + +-static struct ctl_table nss_ppe_vp_dir[] = { +- { +- .procname = "ppe_vp", +- .mode = 0555, +- .child = nss_ppe_vp_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_ppe_vp_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_ppe_vp_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_ppe_vp_procfs_header; + + /* +@@ -812,7 +794,7 @@ void nss_ppe_vp_procfs_register(void) + /* + * Register sysctl table. + */ +- nss_ppe_vp_procfs_header = register_sysctl_table(nss_ppe_vp_root_dir); ++ nss_ppe_vp_procfs_header = register_sysctl("dev/nss/ppe_vp", nss_ppe_vp_table); + } + + /* +--- a/nss_pppoe.c ++++ b/nss_pppoe.c +@@ -353,33 +353,6 @@ static struct ctl_table nss_pppoe_table[ + { } + }; + +-static struct ctl_table nss_pppoe_dir[] = { +- { +- .procname = "pppoe", +- .mode = 0555, +- .child = nss_pppoe_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_pppoe_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_pppoe_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_pppoe_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_pppoe_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_pppoe_header; + + /* +@@ -391,7 +364,7 @@ void nss_pppoe_register_sysctl(void) + /* + * Register sysctl table. + */ +- nss_pppoe_header = register_sysctl_table(nss_pppoe_root); ++ nss_pppoe_header = register_sysctl("dev/nss/pppoe", nss_pppoe_table); + } + + /* +--- a/nss_c2c_tx.c ++++ b/nss_c2c_tx.c +@@ -334,33 +334,6 @@ static struct ctl_table nss_c2c_tx_table + { } + }; + +-static struct ctl_table nss_c2c_tx_dir[] = { +- { +- .procname = "c2c_tx", +- .mode = 0555, +- .child = nss_c2c_tx_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_c2c_tx_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_c2c_tx_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_c2c_tx_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_c2c_tx_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_c2c_tx_header; + + /* +@@ -378,7 +351,7 @@ void nss_c2c_tx_register_sysctl(void) + /* + * Register sysctl table. + */ +- nss_c2c_tx_header = register_sysctl_table(nss_c2c_tx_root); ++ nss_c2c_tx_header = register_sysctl("dev/nss/c2c_tx", nss_c2c_tx_table); + } + + /* +--- a/nss_ipv4.c ++++ b/nss_ipv4.c +@@ -712,33 +712,6 @@ static struct ctl_table nss_ipv4_table[] + { } + }; + +-static struct ctl_table nss_ipv4_dir[] = { +- { +- .procname = "ipv4cfg", +- .mode = 0555, +- .child = nss_ipv4_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_ipv4_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_ipv4_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_ipv4_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_ipv4_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_ipv4_header; + + /* +@@ -753,7 +726,7 @@ void nss_ipv4_register_sysctl(void) + /* + * Register sysctl table. + */ +- nss_ipv4_header = register_sysctl_table(nss_ipv4_root); ++ nss_ipv4_header = register_sysctl("dev/nss/ipv4cfg", nss_ipv4_table); + } + + /* +--- a/nss_ipv6.c ++++ b/nss_ipv6.c +@@ -18,6 +18,7 @@ + * nss_ipv6.c + * NSS IPv6 APIs + */ ++#include "linux/ipv6.h" + #include + #include "nss_dscp_map.h" + #include "nss_ipv6_stats.h" +@@ -377,7 +378,7 @@ EXPORT_SYMBOL(nss_ipv6_get_mgr); + * nss_ipv6_register_handler() + * Register our handler to receive messages for this interface + */ +-void nss_ipv6_register_handler() ++void nss_ipv6_register_handler(void) + { + struct nss_ctx_instance *nss_ctx = nss_ipv6_get_mgr(); + +@@ -706,33 +707,6 @@ static struct ctl_table nss_ipv6_table[] + { } + }; + +-static struct ctl_table nss_ipv6_dir[] = { +- { +- .procname = "ipv6cfg", +- .mode = 0555, +- .child = nss_ipv6_table, +- }, +- { } +-}; +- +-static struct ctl_table nss_ipv6_root_dir[] = { +- { +- .procname = "nss", +- .mode = 0555, +- .child = nss_ipv6_dir, +- }, +- { } +-}; +- +-static struct ctl_table nss_ipv6_root[] = { +- { +- .procname = "dev", +- .mode = 0555, +- .child = nss_ipv6_root_dir, +- }, +- { } +-}; +- + static struct ctl_table_header *nss_ipv6_header; + + /* +@@ -747,7 +721,7 @@ void nss_ipv6_register_sysctl(void) + /* + * Register sysctl table. + */ +- nss_ipv6_header = register_sysctl_table(nss_ipv6_root); ++ nss_ipv6_header = register_sysctl("dev/nss/ipv6cfg", nss_ipv6_table); + } + + /* +--- a/nss_pm.c ++++ b/nss_pm.c +@@ -326,6 +326,7 @@ error: + nss_pm_interface_status_t nss_pm_set_perf_level(void *handle, nss_pm_perf_level_t lvl) + { + #if ((NSS_DT_SUPPORT == 1) && (NSS_FREQ_SCALE_SUPPORT == 1)) ++#if !defined(NSS_HAL_IPQ807x_SUPPORT) + nss_freq_scales_t index; + + switch (lvl) { +@@ -341,7 +342,6 @@ nss_pm_interface_status_t nss_pm_set_per + index = NSS_FREQ_MID_SCALE; + } + +-#if !defined(NSS_HAL_IPQ807x_SUPPORT) + nss_freq_sched_change(index, false); + #endif + diff --git a/qca-nss-drv/patches/0017-nss-drv-wifili-add-exported-symbols.patch b/qca-nss-drv/patches/0017-nss-drv-wifili-add-exported-symbols.patch new file mode 100644 index 0000000..917c844 --- /dev/null +++ b/qca-nss-drv/patches/0017-nss-drv-wifili-add-exported-symbols.patch @@ -0,0 +1,18 @@ +--- a/exports/nss_wifili_if.h ++++ b/exports/nss_wifili_if.h +@@ -751,6 +751,15 @@ struct nss_wifili_stats_notification { + struct nss_wifili_stats stats; /**< Wifili statistics. */ + }; + ++/** ++ * nss_wifili_get_context ++ * Gets the Wi-Fi Li context used in NSS GRE transmit. ++ * ++ * @return ++ * Pointer to the NSS core context. ++ */ ++extern struct nss_ctx_instance *nss_wifili_get_context(void); ++ + #ifdef __KERNEL__ /* only kernel will use. */ + + /** diff --git a/qca-nss-drv/patches/0018-nss-drv-more-uniform-kernel-msg.patch b/qca-nss-drv/patches/0018-nss-drv-more-uniform-kernel-msg.patch new file mode 100644 index 0000000..4f530ee --- /dev/null +++ b/qca-nss-drv/patches/0018-nss-drv-more-uniform-kernel-msg.patch @@ -0,0 +1,88 @@ +--- a/nss_n2h.c ++++ b/nss_n2h.c +@@ -1300,11 +1300,11 @@ static int nss_n2h_mitigationcfg_core0_h + } + + if (!nss_n2h_core0_mitigation_cfg) { +- printk(KERN_INFO "Disabling NSS MITIGATION\n"); ++ dev_info(nss_ctx->dev, "Disabling NSS MITIGATION\n"); + nss_n2h_mitigation_cfg(nss_ctx, 0, NSS_CORE_0); + return 0; + } +- printk(KERN_INFO "Invalid input value.Valid value is 0, Runtime re-enabling not supported\n"); ++ dev_info(nss_ctx->dev, "Invalid input value.Valid value is 0, Runtime re-enabling not supported\n"); + return -EINVAL; + } + +@@ -1331,11 +1331,11 @@ static int nss_n2h_mitigationcfg_core1_h + } + + if (!nss_n2h_core1_mitigation_cfg) { +- printk(KERN_INFO "Disabling NSS MITIGATION\n"); ++ dev_info(nss_ctx->dev, "Disabling NSS MITIGATION\n"); + nss_n2h_mitigation_cfg(nss_ctx, 0, NSS_CORE_1); + return 0; + } +- printk(KERN_INFO "Invalid input value.Valid value is 0, Runtime re-enabling not supported\n"); ++ dev_info(nss_ctx->dev, "Invalid input value.Valid value is 0, Runtime re-enabling not supported\n"); + return -EINVAL; + } + +@@ -1367,14 +1367,14 @@ static int nss_n2h_buf_cfg_core0_handler + } + + if ((nss_n2h_core0_add_buf_pool_size >= 1) && (nss_n2h_core0_add_buf_pool_size <= NSS_N2H_MAX_BUF_POOL_SIZE)) { +- printk(KERN_INFO "configuring additional NSS pbufs\n"); ++ dev_info(nss_ctx->dev, "Configuring additional NSS pbufs\n"); + ret = nss_n2h_buf_pool_cfg(nss_ctx, nss_n2h_core0_add_buf_pool_size, NSS_CORE_0); + nss_n2h_core0_add_buf_pool_size = nss_ctx->buf_sz_allocated; +- printk(KERN_INFO "additional pbufs of size %d got added to NSS\n", nss_ctx->buf_sz_allocated); ++ dev_info(nss_ctx->dev, "Additional pbufs of size %d got added to NSS\n", nss_ctx->buf_sz_allocated); + return ret; + } + +- printk(KERN_INFO "Invalid input value. should be greater than 1 and less than %d\n", NSS_N2H_MAX_BUF_POOL_SIZE); ++ dev_info(nss_ctx->dev, "Invalid input value. should be greater than 1 and less than %d\n", NSS_N2H_MAX_BUF_POOL_SIZE); + return -EINVAL; + } + +@@ -1406,14 +1406,14 @@ static int nss_n2h_buf_cfg_core1_handler + } + + if ((nss_n2h_core1_add_buf_pool_size >= 1) && (nss_n2h_core1_add_buf_pool_size <= NSS_N2H_MAX_BUF_POOL_SIZE)) { +- printk(KERN_INFO "configuring additional NSS pbufs\n"); ++ dev_info(nss_ctx->dev, "Configuring additional NSS pbufs\n"); + ret = nss_n2h_buf_pool_cfg(nss_ctx, nss_n2h_core1_add_buf_pool_size, NSS_CORE_1); + nss_n2h_core1_add_buf_pool_size = nss_ctx->buf_sz_allocated; +- printk(KERN_INFO "additional pbufs of size %d got added to NSS\n", nss_ctx->buf_sz_allocated); ++ dev_info(nss_ctx->dev, "Additional pbufs of size %d got added to NSS\n", nss_ctx->buf_sz_allocated); + return ret; + } + +- printk(KERN_INFO "Invalid input value. should be greater than 1 and less than %d\n", NSS_N2H_MAX_BUF_POOL_SIZE); ++ dev_info(nss_ctx->dev, "Invalid input value. should be greater than 1 and less than %d\n", NSS_N2H_MAX_BUF_POOL_SIZE); + return -EINVAL; + } + +--- a/nss_core.c ++++ b/nss_core.c +@@ -2283,7 +2283,7 @@ static void nss_core_handle_cause_nonque + nss_core_init_nss(nss_ctx, if_map); + nss_send_ddr_info(nss_ctx); + +- nss_info_always("%px: nss core %d booted successfully\n", nss_ctx, nss_ctx->id); ++ dev_info(nss_ctx->dev, "NSS core %d booted successfully\n", nss_ctx->id); + nss_top = nss_ctx->nss_top; + + #ifdef NSS_DRV_C2C_ENABLE +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -83,7 +83,7 @@ int nss_hal_firmware_load(struct nss_ctx + return rc; + } + +- nss_info("nss_driver - fw of size %d bytes copied to load addr: %x, nss_id : %d\n", (int)nss_fw->size, npd->load_addr, nss_dev->id); ++ dev_info(&nss_dev->dev, "fw of size %d bytes copied to addr: %x, nss_id: %d\n", (int)nss_fw->size, npd->load_addr, nss_ctx->id); + memcpy_toio(load_mem, nss_fw->data, nss_fw->size); + release_firmware(nss_fw); + iounmap(load_mem); diff --git a/qca-nss-drv/patches/0019-nss-drv-mac80211-disable-signal-redirection.patch b/qca-nss-drv/patches/0019-nss-drv-mac80211-disable-signal-redirection.patch new file mode 100644 index 0000000..62e1fe4 --- /dev/null +++ b/qca-nss-drv/patches/0019-nss-drv-mac80211-disable-signal-redirection.patch @@ -0,0 +1,11 @@ +--- a/nss_virt_if.c ++++ b/nss_virt_if.c +@@ -450,6 +450,8 @@ EXPORT_SYMBOL(nss_virt_if_create_sync_ne + */ + struct nss_virt_if_handle *nss_virt_if_create_sync(struct net_device *netdev) + { ++ if (!nss_ctl_redirect) ++ return NULL; + /* + * NSS_N2H_INTERFACE is the nexthop of the dynamic interface which is created for handling the + * n2h traffic. diff --git a/qca-nss-drv/patches/0019-nss-drv-reorg-irq-logic.patch b/qca-nss-drv/patches/0019-nss-drv-reorg-irq-logic.patch new file mode 100644 index 0000000..70cbcae --- /dev/null +++ b/qca-nss-drv/patches/0019-nss-drv-reorg-irq-logic.patch @@ -0,0 +1,353 @@ +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -67,6 +67,20 @@ + #define NSS_NC_AXI_CLK "nss-nc-axi-clk" + + /* ++ * N2H interrupts ++ */ ++#define NSS_IRQ_NAME_EMPTY_BUF_SOS "nss_empty_buf_sos" ++#define NSS_IRQ_NAME_EMPTY_BUF_QUEUE "nss_empty_buf_queue" ++#define NSS_IRQ_NAME_TX_UNBLOCK "nss-tx-unblock" ++#define NSS_IRQ_NAME_QUEUE0 "nss_queue0" ++#define NSS_IRQ_NAME_QUEUE1 "nss_queue1" ++#define NSS_IRQ_NAME_QUEUE2 "nss_queue2" ++#define NSS_IRQ_NAME_QUEUE3 "nss_queue3" ++#define NSS_IRQ_NAME_COREDUMP_COMPLETE "nss_coredump_complete" ++#define NSS_IRQ_NAME_PAGED_EMPTY_BUF_SOS "nss_paged_empty_buf_sos" ++#define NSS_IRQ_NAME_PROFILE_DMA "nss_profile_dma" ++ ++/* + * Voltage values + */ + #define NOMINAL_VOLTAGE 1 +@@ -654,74 +668,96 @@ static void __nss_hal_send_interrupt(str + static int __nss_hal_request_irq(struct nss_ctx_instance *nss_ctx, struct nss_platform_data *npd, int irq_num) + { + struct int_ctx_instance *int_ctx = &nss_ctx->int_ctx[irq_num]; ++ uint32_t cause, napi_wgt; + int err = -1, irq = npd->irq[irq_num]; ++ int (*napi_poll_cb)(struct napi_struct *, int) = NULL; ++ const char *irq_name; + + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_sos", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_queue", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_TX_UNBLOCKED; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss-tx-unblock", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_0; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue0", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1) { +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_1; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue1", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2) { +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_2; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue2", int_ctx); +- } ++ switch (irq_num) { ++ case NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS: ++ napi_poll_cb = nss_core_handle_napi_non_queue; ++ napi_wgt = NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS; ++ irq_name = NSS_IRQ_NAME_EMPTY_BUF_SOS; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE; ++ irq_name = NSS_IRQ_NAME_EMPTY_BUF_QUEUE; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED: ++ napi_poll_cb = nss_core_handle_napi_non_queue; ++ napi_wgt = NSS_TX_UNBLOCKED_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_TX_UNBLOCKED; ++ irq_name = NSS_IRQ_NAME_TX_UNBLOCK; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_0; ++ irq_name = NSS_IRQ_NAME_QUEUE0; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_1; ++ irq_name = NSS_IRQ_NAME_QUEUE1; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_2; ++ irq_name = NSS_IRQ_NAME_QUEUE2; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_3; ++ irq_name = NSS_IRQ_NAME_QUEUE3; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE: ++ napi_poll_cb = nss_core_handle_napi_emergency; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_COREDUMP_COMPLETE; ++ irq_name = NSS_IRQ_NAME_COREDUMP_COMPLETE; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS: ++ napi_poll_cb = nss_core_handle_napi_non_queue; ++ napi_wgt = NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS; ++ irq_name = NSS_IRQ_NAME_PAGED_EMPTY_BUF_SOS; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA: ++ napi_poll_cb = nss_core_handle_napi_sdma; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_PROFILE_DMA; ++ irq_name = NSS_IRQ_NAME_PROFILE_DMA; ++ break; + +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3) { +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_3; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue3", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE) { +- int_ctx->cause = NSS_N2H_INTR_COREDUMP_COMPLETE; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_coredump_complete", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_paged_empty_buf_sos", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA) { +- int_ctx->cause = NSS_N2H_INTR_PROFILE_DMA; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_profile_dma", int_ctx); ++ default: ++ nss_warning("%px: nss%d: unsupported irq# %d\n", nss_ctx, nss_ctx->id, irq_num); ++ return err; + } + ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, napi_poll_cb, napi_wgt); ++ int_ctx->cause = cause; ++ err = request_irq(irq, nss_hal_handle_irq, 0, irq_name, int_ctx); + if (err) { ++ nss_warning("%px: nss%d: request_irq failed for irq# %d\n", nss_ctx, nss_ctx->id, irq_num); + return err; + } +- + int_ctx->irq = irq; + return 0; + } +--- a/nss_hal/ipq60xx/nss_hal_pvt.c ++++ b/nss_hal/ipq60xx/nss_hal_pvt.c +@@ -64,6 +64,20 @@ + #define NSS_UTCM_CLK "nss-utcm-clk" + + /* ++ * N2H interrupts ++ */ ++#define NSS_IRQ_NAME_EMPTY_BUF_SOS "nss_empty_buf_sos" ++#define NSS_IRQ_NAME_EMPTY_BUF_QUEUE "nss_empty_buf_queue" ++#define NSS_IRQ_NAME_TX_UNBLOCK "nss-tx-unblock" ++#define NSS_IRQ_NAME_QUEUE0 "nss_queue0" ++#define NSS_IRQ_NAME_QUEUE1 "nss_queue1" ++#define NSS_IRQ_NAME_QUEUE2 "nss_queue2" ++#define NSS_IRQ_NAME_QUEUE3 "nss_queue3" ++#define NSS_IRQ_NAME_COREDUMP_COMPLETE "nss_coredump_complete" ++#define NSS_IRQ_NAME_PAGED_EMPTY_BUF_SOS "nss_paged_empty_buf_sos" ++#define NSS_IRQ_NAME_PROFILE_DMA "nss_profile_dma" ++ ++/* + * Voltage values + */ + #define NOMINAL_VOLTAGE 1 +@@ -610,71 +624,94 @@ static void __nss_hal_send_interrupt(str + static int __nss_hal_request_irq(struct nss_ctx_instance *nss_ctx, struct nss_platform_data *npd, int irq_num) + { + struct int_ctx_instance *int_ctx = &nss_ctx->int_ctx[irq_num]; ++ uint32_t cause, napi_wgt; + int err = -1, irq = npd->irq[irq_num]; ++ int (*napi_poll_cb)(struct napi_struct *, int) = NULL; ++ const char *irq_name; + + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_sos", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_queue", int_ctx); +- } ++ switch (irq_num) { ++ case NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS: ++ napi_poll_cb = nss_core_handle_napi_non_queue; ++ napi_wgt = NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS; ++ irq_name = NSS_IRQ_NAME_EMPTY_BUF_SOS; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE; ++ irq_name = NSS_IRQ_NAME_EMPTY_BUF_QUEUE; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED: ++ napi_poll_cb = nss_core_handle_napi_non_queue; ++ napi_wgt = NSS_TX_UNBLOCKED_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_TX_UNBLOCKED; ++ irq_name = NSS_IRQ_NAME_TX_UNBLOCK; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_0; ++ irq_name = NSS_IRQ_NAME_QUEUE0; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_1; ++ irq_name = NSS_IRQ_NAME_QUEUE1; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_2; ++ irq_name = NSS_IRQ_NAME_QUEUE2; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3: ++ napi_poll_cb = nss_core_handle_napi_queue; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_DATA_QUEUE_3; ++ irq_name = NSS_IRQ_NAME_QUEUE3; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE: ++ napi_poll_cb = nss_core_handle_napi_emergency; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_COREDUMP_COMPLETE; ++ irq_name = NSS_IRQ_NAME_COREDUMP_COMPLETE; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS: ++ napi_poll_cb = nss_core_handle_napi_non_queue; ++ napi_wgt = NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS; ++ irq_name = NSS_IRQ_NAME_PAGED_EMPTY_BUF_SOS; ++ break; ++ ++ case NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA: ++ napi_poll_cb = nss_core_handle_napi_sdma; ++ napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT; ++ cause = NSS_N2H_INTR_PROFILE_DMA; ++ irq_name = NSS_IRQ_NAME_PROFILE_DMA; ++ break; + +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_TX_UNBLOCKED; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss-tx-unblock", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_0; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue0", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1) { +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_1; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue1", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2) { +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_2; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue2", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3) { +- int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_3; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue3", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE) { +- int_ctx->cause = NSS_N2H_INTR_COREDUMP_COMPLETE; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_coredump_complete", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS) { +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT); +- int_ctx->cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS; +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_paged_empty_buf_sos", int_ctx); +- } +- +- if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA) { +- int_ctx->cause = NSS_N2H_INTR_PROFILE_DMA; +- netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT); +- err = request_irq(irq, nss_hal_handle_irq, 0, "nss_profile_dma", int_ctx); ++ default: ++ nss_warning("%px: nss%d: unsupported irq# %d\n", nss_ctx, nss_ctx->id, irq_num); ++ return err; + } + ++ netif_napi_add_weight(&nss_ctx->napi_ndev, &int_ctx->napi, napi_poll_cb, napi_wgt); ++ int_ctx->cause = cause; ++ err = request_irq(irq, nss_hal_handle_irq, 0, irq_name, int_ctx); + if (err) { ++ nss_warning("%px: nss%d: request_irq failed for irq# %d\n", nss_ctx, nss_ctx->id, irq_num); + return err; + } + diff --git a/qca-nss-drv/patches/0020-nss-drv-display-fw-version.patch b/qca-nss-drv/patches/0020-nss-drv-display-fw-version.patch new file mode 100644 index 0000000..1ee7824 --- /dev/null +++ b/qca-nss-drv/patches/0020-nss-drv-display-fw-version.patch @@ -0,0 +1,79 @@ +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -30,7 +30,6 @@ + #include + + #include "nss_hal.h" +-#include "nss_arch.h" + #include "nss_core.h" + #include "nss_tx_rx_common.h" + #ifdef NSS_DATA_PLANE_GENERIC_SUPPORT +@@ -51,6 +50,57 @@ + */ + #define NSS_AP0_IMAGE "qca-nss0.bin" + #define NSS_AP1_IMAGE "qca-nss1.bin" ++#define BUFFER_SIZE 8192 ++ ++// Function to search for the byte sequence in the buffer ++static unsigned char *search_sequence(const unsigned char *buffer, ++ size_t buffer_size, ++ const unsigned char *sequence, ++ size_t sequence_size) ++{ ++ for (size_t i = 0; i <= buffer_size - sequence_size; i++) { ++ if (memcmp(buffer + i, sequence, sequence_size) == 0) { ++ return (unsigned char *)(buffer + i); ++ } ++ } ++ return NULL; ++} ++ ++static int nss_hal_firmware_info(struct platform_device *nss_dev, ++ const struct firmware *fw) ++{ ++ unsigned char *start_pos, *end_pos; ++ size_t i; ++ unsigned char start_sequence[] = { 0x56, 0x65, 0x72, 0x73, 0x69, 0x6f, 0x6e, 0x3a, 0x20 }; ++ unsigned char end_sequence[] = { 0x00 }; ++ char version[256]; ++ bool found = false; ++ ++ // Search for the start sequence ++ start_pos = search_sequence(fw->data, fw->size, start_sequence, sizeof(start_sequence)); ++ if (start_pos) { ++ start_pos += sizeof(start_sequence); ++ ++ end_pos = search_sequence(start_pos, fw->size - (start_pos - fw->data), end_sequence, sizeof(end_sequence)); ++ if (end_pos) { ++ // Convert the version information to a string ++ for (i = 0; start_pos + i < end_pos && i < sizeof(version) - 1; i++) { ++ version[i] = start_pos[i]; ++ } ++ version[i] = '\0'; ++ ++ dev_info(&nss_dev->dev, "NSS fw version: %s\n", version); ++ found = true; ++ } ++ } ++ ++ if (!found) { ++ dev_err(&nss_dev->dev, "Unable to get NSS fw version\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} + + int nss_hal_firmware_load(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd) + { +@@ -83,6 +133,10 @@ int nss_hal_firmware_load(struct nss_ctx + return rc; + } + ++ if (nss_ctx->id == 0) { ++ nss_hal_firmware_info(nss_dev, nss_fw); ++ } ++ + dev_info(&nss_dev->dev, "fw of size %d bytes copied to addr: %x, nss_id: %d\n", (int)nss_fw->size, npd->load_addr, nss_ctx->id); + memcpy_toio(load_mem, nss_fw->data, nss_fw->size); + release_firmware(nss_fw); diff --git a/qca-nss-drv/patches/0022-nss-drv-limit-fw-12.2.patch b/qca-nss-drv/patches/0022-nss-drv-limit-fw-12.2.patch new file mode 100644 index 0000000..8aff8b4 --- /dev/null +++ b/qca-nss-drv/patches/0022-nss-drv-limit-fw-12.2.patch @@ -0,0 +1,201 @@ +--- a/exports/nss_capwap.h ++++ b/exports/nss_capwap.h +@@ -284,6 +284,7 @@ struct nss_capwap_dtls_msg { + uint32_t reserved; /**< Reserved field for future use. */ + }; + ++#ifdef NSS_FIRMWARE_VERSION_12_5 + /** + * nss_capwap_flow_attr + * Inner Flow attributes. +@@ -293,6 +294,7 @@ struct nss_capwap_flow_attr { + uint32_t flow_id; /**< Flow Identification. */ + uint32_t scs_sdwf_id; /**< SCS or SDWF Identification. */ + }; ++#endif + + /** + * nss_capwap_flow_rule_msg +@@ -312,7 +314,11 @@ struct nss_capwap_flow_rule_msg { + /* + * Flow attributes. + */ ++#ifdef NSS_FIRMWARE_VERSION_12_5 + struct nss_capwap_flow_attr flow_attr; ++#else ++ uint32_t flow_id; /**< Flow identification. */ ++#endif + }; + + /** +--- a/exports/nss_ipv4.h ++++ b/exports/nss_ipv4.h +@@ -290,7 +290,9 @@ enum nss_ipv4_stats_types { + #define NSS_IPV4_RULE_CREATE_IDENTIFIER_VALID 0x1000 + /**< Identifier is valid. */ + #define NSS_IPV4_RULE_CREATE_MIRROR_VALID 0x2000 /**< Mirror fields are valid. */ ++#ifdef NSS_FIRMWARE_VERSION_12_5 + #define NSS_IPV4_RULE_CREATE_RAWIP_VALID 0x4000 /**< RAW IP fields are valid. */ ++#endif + + /* + * Multicast command rule flags +--- a/exports/nss_pvxlan.h ++++ b/exports/nss_pvxlan.h +@@ -63,8 +63,10 @@ typedef enum nss_pvxlan_msg_type { + NSS_PVXLAN_MSG_TYPE_TUNNEL_DISABLE, /**< Disable the tunnel. */ + NSS_PVXLAN_MSG_TYPE_MAC_ADD, /**< Add MAC rule to the database. */ + NSS_PVXLAN_MSG_TYPE_MAC_DEL, /**< Remove MAC rule from the database. */ ++#ifdef NSS_FIRMWARE_VERSION_12_5 + NSS_PVXLAN_MSG_TYPE_CONFIG_VP, /**< VP configuration. */ + NSS_PVXLAN_MSG_TYPE_UNCONFIG_VP, /**< VP unconfiguration. */ ++#endif + NSS_PVXLAN_MSG_TYPE_MAX, /**< Maximum message type. */ + } nss_pvxlan_msg_type_t; + +@@ -97,10 +99,12 @@ typedef enum nss_pvxlan_error_response_t + /**< MAC entry allocation failed. */ + PVXLAN_ERROR_MSG_MAC_ENTRY_DELETE_FAILED, + /**< MAC entry deletion failed. */ ++#ifdef NSS_FIRMWARE_VERSION_12_5 + PVXLAN_ERROR_MSG_CONFIG_VP_FAILED, + /**< VP configuration failed. */ + PVXLAN_ERROR_MSG_UNCONFIG_VP_FAILED, + /**< VP unconfiguration failed. */ ++#endif + NSS_PVXLAN_ERROR_MAX, /**< Maximum error type. */ + } nss_pvxlan_error_response_t; + +@@ -181,6 +185,7 @@ struct nss_pvxlan_mac_msg { + uint16_t policy_id; /**< Policy ID. */ + }; + ++#ifdef NSS_FIRMWARE_VERSION_12_5 + /** + * nss_pvxlan_vp_msg + * VP configuration message. +@@ -192,6 +197,7 @@ struct nss_pvxlan_vp_msg { + int16_t vp_num; /**< VP number. */ + bool ppe_to_host; /**< Enable/disable PPE to host mode. */ + }; ++#endif + + /** + * nss_pvxlan_msg +@@ -216,8 +222,10 @@ struct nss_pvxlan_msg { + /**< MAC rule add message. */ + struct nss_pvxlan_mac_msg mac_del; + /**< MAC rule delete message. */ ++#ifdef NSS_FIRMWARE_VERSION_12_5 + struct nss_pvxlan_vp_msg vp_config; + /**< VP configuration message. */ ++#endif + } msg; /**< Message payload. */ + }; + +--- a/exports/nss_wifili_if.h ++++ b/exports/nss_wifili_if.h +@@ -1496,8 +1496,10 @@ struct nss_wifili_rx_ctrl_stats { + uint32_t bcast_rcv_bytes; /**< Total number of broadcast bytes received. */ + uint32_t defrag_mcast_drop; /**< Total number of defrag multicast dropped packets. */ + uint32_t mcast_3addr_drop; /**< Total number of 3 address multicast dropped packets. */ ++#ifdef NSS_FIRMWARE_VERSION_12_5 + uint32_t ucast_rcv_cnt; /**< Total number of unicast packets received. */ + uint32_t ucast_rcv_bytes; /**< Total number of unicast bytes received. */ ++#endif + }; + + /** +@@ -1509,8 +1511,10 @@ struct nss_wifili_retry_ctrl_stats { + uint32_t tx_retry_count; /**< Transmit retry count. */ + uint32_t tx_multiple_retry_count; /**< Transmit multiple retry count. */ + uint32_t rx_retry_count; /**< Receive retry count. */ ++#ifdef NSS_FIRMWARE_VERSION_12_5 + uint32_t tx_mpdu_retry_count; /**< Per mpdu retry count. */ + uint32_t tx_mpdu_total_retry_count; /**< Total mpdu retry count. */ ++#endif + }; + + /** +--- a/nss_pvxlan_log.c ++++ b/nss_pvxlan_log.c +@@ -36,7 +36,9 @@ static int8_t *nss_pvxlan_log_message_ty + "PVxLAN Disable Tunnel", + "PVxLAN Add MAC rule", + "PVxLAN Delete MAC rule", ++#ifdef NSS_FIRMWARE_VERSION_12_5 + "PVxLAN Config VP" ++#endif + }; + + /* +@@ -54,7 +56,9 @@ static int8_t *nss_pvxlan_log_error_resp + "PVXLAN MAC Table Full", + "PVXLAN MAC Exists", + "PVXLAN MAC Does Not Exist", ++#ifdef NSS_FIRMWARE_VERSION_12_5 + "PVXLAN Config VP failed" ++#endif + }; + + /* +@@ -158,6 +162,7 @@ static void nss_pvxlan_log_mac_del_msg(s + nss_pvxlan_log_mac_msg(npvcm); + } + ++#ifdef NSS_FIRMWARE_VERSION_12_5 + /* + * nss_pvxlan_log_unconfig_vp_msg() + * Log NSS PVXLAN unconfig VP message. +@@ -181,6 +186,7 @@ static void nss_pvxlan_log_config_vp_msg + vpm->vp_num, + vpm->ppe_to_host ? "enabled" : "disabled"); + } ++#endif + + /* + * nss_pvxlan_log_verbose() +@@ -213,6 +219,7 @@ static void nss_pvxlan_log_verbose(struc + nss_pvxlan_log_mac_del_msg(npvm); + break; + ++#ifdef NSS_FIRMWARE_VERSION_12_5 + case NSS_PVXLAN_MSG_TYPE_CONFIG_VP: + nss_pvxlan_log_config_vp_msg(npvm); + break; +@@ -220,6 +227,7 @@ static void nss_pvxlan_log_verbose(struc + case NSS_PVXLAN_MSG_TYPE_UNCONFIG_VP: + nss_pvxlan_log_unconfig_vp_msg(npvm); + break; ++#endif + + case NSS_PVXLAN_MSG_TYPE_SYNC_STATS: + break; +--- a/nss_capwap_log.c ++++ b/nss_capwap_log.c +@@ -166,7 +166,11 @@ static void nss_capwap_flow_rule_msg(str + "CAPWAP Destination Port: %d\n" + "CAPWAP Source IP: %x %x %x %x\n" + "CAPWAP Destination IP: %x %x %x %x" ++#ifdef NSS_FIRMWARE_VERSION_12_5 + "CAPWAP Flow type:%d Flow ID: %d SCS_SDWF ID: %d", ++#else ++ "CAPWAP Flow ID: %d", ++#endif + ncfrm, + ncfrm->ip_version, ncfrm->protocol, + ncfrm->src_port, ncfrm->dst_port, +@@ -174,9 +178,13 @@ static void nss_capwap_flow_rule_msg(str + ncfrm->src_ip[2], ncfrm->src_ip[3], + ncfrm->dst_ip[0], ncfrm->dst_ip[1], + ncfrm->dst_ip[2], ncfrm->dst_ip[3], ++#ifdef NSS_FIRMWARE_VERSION_12_5 + ncfrm->flow_attr.type, + ncfrm->flow_attr.flow_id, + ncfrm->flow_attr.scs_sdwf_id); ++#else ++ ncfrm->flow_id); ++#endif + } + + /* diff --git a/qca-nss-drv/patches/0022-nss-drv-set-addr-to-const.patch b/qca-nss-drv/patches/0022-nss-drv-set-addr-to-const.patch new file mode 100644 index 0000000..fe78c3c --- /dev/null +++ b/qca-nss-drv/patches/0022-nss-drv-set-addr-to-const.patch @@ -0,0 +1,88 @@ +--- a/exports/nss_bridge.h ++++ b/exports/nss_bridge.h +@@ -273,7 +273,7 @@ nss_tx_status_t nss_bridge_tx_set_mtu_ms + * @return + * Status of the Tx operation. + */ +-nss_tx_status_t nss_bridge_tx_set_mac_addr_msg(uint32_t bridge_if_num, uint8_t *addr); ++nss_tx_status_t nss_bridge_tx_set_mac_addr_msg(uint32_t bridge_if_num, const uint8_t *addr); + + /** + * nss_bridge_tx_join_msg +--- a/exports/nss_vlan.h ++++ b/exports/nss_vlan.h +@@ -210,7 +210,7 @@ nss_tx_status_t nss_vlan_tx_set_mtu_msg( + * @return + * Status of the Tx operation. + */ +-nss_tx_status_t nss_vlan_tx_set_mac_addr_msg(uint32_t vlan_if_num, uint8_t *addr); ++nss_tx_status_t nss_vlan_tx_set_mac_addr_msg(uint32_t vlan_if_num, const uint8_t *addr); + + /** + * nss_vlan_tx_vsi_attach_msg +--- a/exports/nss_wifi_vdev.h ++++ b/exports/nss_wifi_vdev.h +@@ -1404,7 +1404,7 @@ nss_tx_status_t nss_wifi_vdev_base_set_n + * @return + * Status of the Tx operation. + */ +-nss_tx_status_t nss_wifi_vdev_set_peer_next_hop(struct nss_ctx_instance *nss_ctx, uint32_t nss_if, uint8_t *addr, uint32_t next_hop_if); ++nss_tx_status_t nss_wifi_vdev_set_peer_next_hop(struct nss_ctx_instance *nss_ctx, uint32_t nss_if, const uint8_t *addr, uint32_t next_hop_if); + + /* + * nss_wifi_vdev_set_dp_type +--- a/nss_bridge.c ++++ b/nss_bridge.c +@@ -304,7 +304,7 @@ EXPORT_SYMBOL(nss_bridge_tx_set_mtu_msg) + * nss_bridge_tx_set_mac_addr_msg + * API to send change mac addr message to NSS FW + */ +-nss_tx_status_t nss_bridge_tx_set_mac_addr_msg(uint32_t bridge_if_num, uint8_t *addr) ++nss_tx_status_t nss_bridge_tx_set_mac_addr_msg(uint32_t bridge_if_num, const uint8_t *addr) + { + struct nss_ctx_instance *nss_ctx = nss_bridge_get_context(); + struct nss_bridge_msg nbm; +--- a/nss_phys_if.c ++++ b/nss_phys_if.c +@@ -402,7 +402,7 @@ nss_tx_status_t nss_phys_if_link_state(s + * nss_phys_if_mac_addr() + * Send a MAC address to physical interface + */ +-nss_tx_status_t nss_phys_if_mac_addr(struct nss_ctx_instance *nss_ctx, uint8_t *addr, uint32_t if_num) ++nss_tx_status_t nss_phys_if_mac_addr(struct nss_ctx_instance *nss_ctx, const uint8_t *addr, uint32_t if_num) + { + struct nss_phys_if_msg nim; + struct nss_if_mac_address_set *nmas; +--- a/nss_phys_if.h ++++ b/nss_phys_if.h +@@ -284,7 +284,7 @@ nss_tx_status_t nss_phys_if_link_state(s + * + * @return nss_tx_status_t Tx status + */ +-nss_tx_status_t nss_phys_if_mac_addr(struct nss_ctx_instance *nss_ctx, uint8_t *addr, uint32_t if_num); ++nss_tx_status_t nss_phys_if_mac_addr(struct nss_ctx_instance *nss_ctx, const uint8_t *addr, uint32_t if_num); + + /** + * @brief Send MTU change notification to NSS +--- a/nss_vlan.c ++++ b/nss_vlan.c +@@ -246,7 +246,7 @@ EXPORT_SYMBOL(nss_vlan_tx_set_mtu_msg); + * nss_vlan_tx_set_mac_addr_msg + * API to send change mac addr message to NSS FW + */ +-nss_tx_status_t nss_vlan_tx_set_mac_addr_msg(uint32_t vlan_if_num, uint8_t *addr) ++nss_tx_status_t nss_vlan_tx_set_mac_addr_msg(uint32_t vlan_if_num, const uint8_t *addr) + { + struct nss_ctx_instance *nss_ctx = nss_vlan_get_context(); + struct nss_vlan_msg nvm; +--- a/nss_wifi_vdev.c ++++ b/nss_wifi_vdev.c +@@ -274,7 +274,7 @@ EXPORT_SYMBOL(nss_wifi_vdev_base_set_nex + /* + * nss_wifi_vdev_set_peer_next_hop() + */ +-nss_tx_status_t nss_wifi_vdev_set_peer_next_hop(struct nss_ctx_instance *ctx, uint32_t nss_if, uint8_t *addr, uint32_t next_hop_if) ++nss_tx_status_t nss_wifi_vdev_set_peer_next_hop(struct nss_ctx_instance *ctx, uint32_t nss_if, const uint8_t *addr, uint32_t next_hop_if) + { + nss_tx_status_t status; + struct nss_wifi_vdev_msg *wifivdevmsg = kzalloc(sizeof(struct nss_wifi_vdev_msg), GFP_KERNEL); diff --git a/qca-nss-drv/patches/0023-add-boot-delay.patch b/qca-nss-drv/patches/0023-add-boot-delay.patch new file mode 100644 index 0000000..95da2b7 --- /dev/null +++ b/qca-nss-drv/patches/0023-add-boot-delay.patch @@ -0,0 +1,60 @@ +--- a/nss_core.c ++++ b/nss_core.c +@@ -92,6 +92,8 @@ static int qos_mem_size = 0; + module_param(qos_mem_size, int, S_IRUGO); + MODULE_PARM_DESC(qos_mem_size, "QoS memory size"); + ++static int nss_bootstate = 0; ++ + /* + * Atomic variables to control jumbo_mru & paged_mode + */ +@@ -2253,6 +2255,19 @@ static inline void nss_core_handle_tx_un + nss_hal_disable_interrupt(nss_ctx, nss_ctx->int_ctx[0].shift_factor, NSS_N2H_INTR_TX_UNBLOCKED); + } + ++void nss_bootwait(void) ++{ ++ int dead = 10 * 10; ++#if (NSS_MAX_CORES > 1) ++ while (nss_bootstate < 2 && dead-- > 0) ++#else ++ while (!nss_bootstate && dead-- > 0) ++#endif ++ { ++ msleep(100); ++ } ++} ++ + /* + * nss_core_handle_cause_nonqueue() + * Handle non-queue interrupt causes (e.g. empty buffer SOS, Tx unblocked) +@@ -2321,6 +2336,9 @@ static void nss_core_handle_cause_nonque + #endif + #endif + } ++ if (unlikely(nss_ctx->state == NSS_CORE_STATE_INITIALIZED)) { ++ nss_bootstate++; ++ } + + #if defined(NSS_DRV_EDMA_LITE_ENABLE) + /* +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -850,6 +850,7 @@ int nss_hal_probe(struct platform_device + } + + nss_info("%px: All resources initialized and nss core%d has been brought out of reset", nss_ctx, nss_dev->id); ++ nss_bootwait(); + goto out; + + err_register_irq: +--- a/nss_core.h ++++ b/nss_core.h +@@ -1082,4 +1082,6 @@ extern nss_tx_status_t nss_n2h_cfg_empty + extern nss_tx_status_t nss_n2h_paged_buf_pool_init(struct nss_ctx_instance *nss_ctx); + extern nss_tx_status_t nss_n2h_cfg_qos_mem_size(struct nss_ctx_instance *nss_ctx, uint32_t pool_sz); + ++void nss_bootwait(void); ++ + #endif /* __NSS_CORE_H */ diff --git a/qca-nss-drv/patches/0024-fix-mesh-stats-naming.patch b/qca-nss-drv/patches/0024-fix-mesh-stats-naming.patch new file mode 100644 index 0000000..0b7bb91 --- /dev/null +++ b/qca-nss-drv/patches/0024-fix-mesh-stats-naming.patch @@ -0,0 +1,39 @@ +--- a/nss_wifi_mesh_strings.c ++++ b/nss_wifi_mesh_strings.c +@@ -80,8 +80,8 @@ struct nss_stats_info nss_wifi_mesh_stri + {"not_found", NSS_STATS_TYPE_SPECIAL}, + {"delete_success", NSS_STATS_TYPE_SPECIAL}, + {"update_success", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_path_expired", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_path_refresh_needed", NSS_STATS_TYPE_SPECIAL}, ++ {"path_expired", NSS_STATS_TYPE_SPECIAL}, ++ {"path_refresh_needed", NSS_STATS_TYPE_SPECIAL}, + {"add_requests", NSS_STATS_TYPE_SPECIAL}, + {"del_requests", NSS_STATS_TYPE_SPECIAL}, + {"update_requests", NSS_STATS_TYPE_SPECIAL}, +@@ -91,8 +91,8 @@ struct nss_stats_info nss_wifi_mesh_stri + {"metric_updations", NSS_STATS_TYPE_SPECIAL}, + {"block_mesh_fwd_updations", NSS_STATS_TYPE_SPECIAL}, + {"delete_failures", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_path_dummy_add_failures",NSS_STATS_TYPE_SPECIAL}, +- {"mesh_path_dummy_add_success", NSS_STATS_TYPE_SPECIAL} ++ {"path_dummy_add_failures", NSS_STATS_TYPE_SPECIAL}, ++ {"path_dummy_add_success", NSS_STATS_TYPE_SPECIAL} + + }; + +@@ -126,10 +126,10 @@ struct nss_stats_info nss_wifi_mesh_stri + {"update_requests", NSS_STATS_TYPE_SPECIAL}, + {"mda_updations", NSS_STATS_TYPE_SPECIAL}, + {"flag_updations", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_proxy_path_dummy_lookup_success", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_proxy_path_dummy_lookup_failures", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_proxy_path_dummy_add_failures", NSS_STATS_TYPE_SPECIAL}, +- {"mesh_proxy_path_dummy_add_success", NSS_STATS_TYPE_SPECIAL} ++ {"proxy_path_dummy_lookup_success", NSS_STATS_TYPE_SPECIAL}, ++ {"proxy_path_dummy_lookup_failures", NSS_STATS_TYPE_SPECIAL}, ++ {"proxy_path_dummy_add_failures", NSS_STATS_TYPE_SPECIAL}, ++ {"proxy_path_dummy_add_success", NSS_STATS_TYPE_SPECIAL} + }; + + /* diff --git a/qca-nss-drv/patches/0025-nss_rps-fix-procfs-read-write.patch b/qca-nss-drv/patches/0025-nss_rps-fix-procfs-read-write.patch new file mode 100644 index 0000000..cfdcdcd --- /dev/null +++ b/qca-nss-drv/patches/0025-nss_rps-fix-procfs-read-write.patch @@ -0,0 +1,195 @@ +--- a/nss_rps.c ++++ b/nss_rps.c +@@ -70,7 +70,7 @@ static inline void nss_rps_pri_map_usage + * nss_rps_pri_map_print() + * Sysctl handler for printing rps/pri mapping. + */ +-static int nss_rps_pri_map_print(struct ctl_table *ctl, void __user *buffer, ++static int nss_rps_pri_map_print(void *buffer, + size_t *lenp, loff_t *ppos, int *pri_map) + { + char *r_buf; +@@ -109,7 +109,7 @@ static int nss_rps_pri_map_print(struct + len = scnprintf(r_buf + cp_bytes, 4, "\n"); + cp_bytes += len; + +- cp_bytes = simple_read_from_buffer(buffer, *lenp, ppos, r_buf, cp_bytes); ++ cp_bytes = memory_read_from_buffer(buffer, *lenp, ppos, r_buf, cp_bytes); + *lenp = cp_bytes; + kfree(r_buf); + return 0; +@@ -119,13 +119,10 @@ static int nss_rps_pri_map_print(struct + * nss_rps_pri_map_parse() + * Sysctl handler for rps/pri mappings. + */ +-static int nss_rps_pri_map_parse(struct ctl_table *ctl, void __user *buffer, +- size_t *lenp, loff_t *ppos, struct nss_rps_pri_map_parse_data *out) ++static int nss_rps_pri_map_parse(void *buffer, ++ size_t *lenp, struct nss_rps_pri_map_parse_data *out) + { +- size_t cp_bytes = 0; + char w_buf[5]; +- loff_t w_offset = 0; +- char *str; + unsigned int pri; + int core, res; + +@@ -140,14 +137,15 @@ static int nss_rps_pri_map_parse(struct + /* + * It's a write operation + */ +- cp_bytes = simple_write_to_buffer(w_buf, *lenp, &w_offset, buffer, 5); +- if (cp_bytes != *lenp) { +- nss_warning("failed to write to buffer\n"); +- return -EFAULT; ++ if (*lenp >= sizeof(w_buf)) { ++ nss_warning("Input too large: %zu\n", *lenp); ++ return -EINVAL; + } + +- str = w_buf; +- res = sscanf(str, "%u %d", &pri, &core); ++ memcpy(w_buf, buffer, *lenp); ++ w_buf[*lenp] = '\0'; /* Ensure null termination */ ++ ++ res = sscanf(w_buf, "%u %d", &pri, &core); + if (res != NSS_RPS_PRI_MAP_PARAM_FIELD_COUNT) { + nss_warning("failed to read the buffer\n"); + return -EFAULT; +@@ -407,7 +405,7 @@ static nss_tx_status_t nss_rps_pri_map_c + * Enable NSS RPS. + */ + static int nss_rps_cfg_handler(struct ctl_table *ctl, int write, +- void __user *buffer, size_t *lenp, loff_t *ppos) ++ void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx; +@@ -458,7 +456,7 @@ static int nss_rps_cfg_handler(struct ct + * Configure NSS rps_hash_bitmap + */ + static int nss_rps_hash_bitmap_cfg_handler(struct ctl_table *ctl, int write, +- void __user *buffer, size_t *lenp, loff_t *ppos) ++ void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx __attribute__((unused)) = &nss_top->nss[0]; +@@ -521,7 +519,7 @@ static int nss_rps_hash_bitmap_cfg_handl + * Configure NSS rps_pri_map + */ + static int nss_rps_pri_map_cfg_handler(struct ctl_table *ctl, int write, +- void __user *buffer, size_t *lenp, loff_t *ppos) ++ void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -529,10 +527,10 @@ static int nss_rps_pri_map_cfg_handler(s + int ret, ret_pri_map; + struct nss_rps_pri_map_parse_data out, current_state; + if (!write) { +- return nss_rps_pri_map_print(ctl, buffer, lenp, ppos, nss_rps_pri_map); ++ return nss_rps_pri_map_print(buffer, lenp, ppos, nss_rps_pri_map); + } + +- ret = nss_rps_pri_map_parse(ctl, buffer, lenp, ppos, &out); ++ ret = nss_rps_pri_map_parse(buffer, lenp, &out); + + if (ret != NSS_SUCCESS) { + nss_rps_pri_map_usage(); +--- a/nss_ipv6.c ++++ b/nss_ipv6.c +@@ -595,7 +595,7 @@ void nss_ipv6_free_conn_tables(void) + * nss_ipv6_accel_mode_cfg_handler() + * Configure acceleration mode for IPv6 + */ +-static int nss_ipv6_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv6_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -639,7 +639,7 @@ static int nss_ipv6_accel_mode_cfg_handl + * nss_ipv6_dscp_map_cfg_handler() + * Sysctl handler for dscp/pri mappings. + */ +-static int nss_ipv6_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv6_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +--- a/nss_ipv4.c ++++ b/nss_ipv4.c +@@ -599,7 +599,7 @@ void nss_ipv4_free_conn_tables(void) + * nss_ipv4_accel_mode_cfg_handler() + * Configure acceleration mode for IPv4 + */ +-static int nss_ipv4_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv4_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -643,7 +643,7 @@ static int nss_ipv4_accel_mode_cfg_handl + * nss_ipv4_dscp_map_cfg_handler() + * Sysctl handler for dscp/pri mappings. + */ +-static int nss_ipv4_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv4_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +--- a/nss_dscp_map.h ++++ b/nss_dscp_map.h +@@ -46,7 +46,7 @@ struct nss_dscp_map_parse { + * nss_dscp_map_print() + * Sysctl handler for printing dscp/pri mapping. + */ +-static int nss_dscp_map_print(struct ctl_table *ctl, void __user *buffer, size_t *lenp, ++static int nss_dscp_map_print(struct ctl_table *ctl, void *buffer, size_t *lenp, + loff_t *ppos, struct nss_dscp_map_entry *mapping) + { + char *r_buf; +@@ -105,7 +105,7 @@ static int nss_dscp_map_print(struct ctl + len = scnprintf(r_buf + cp_bytes, 4, "\n"); + cp_bytes += len; + +- cp_bytes = simple_read_from_buffer(buffer, *lenp, ppos, r_buf, cp_bytes); ++ cp_bytes = memory_read_from_buffer(buffer, *lenp, ppos, r_buf, cp_bytes); + *lenp = cp_bytes; + kfree(r_buf); + return 0; +@@ -115,13 +115,11 @@ static int nss_dscp_map_print(struct ctl + * nss_dscp_map_parse() + * Sysctl handler for dscp/pri mappings. + */ +-static int nss_dscp_map_parse(struct ctl_table *ctl, void __user *buffer, size_t *lenp, ++static int nss_dscp_map_parse(struct ctl_table *ctl, void *buffer, size_t *lenp, + loff_t *ppos, struct nss_dscp_map_parse *out) + { + int count; +- size_t cp_bytes = 0; + char w_buf[7]; +- loff_t w_offset = 0; + char *str; + char *tokens[NSS_DSCP_MAP_PARAM_FIELD_COUNT]; + unsigned int dscp, priority, action; +@@ -135,15 +133,14 @@ static int nss_dscp_map_parse(struct ctl + return -EINVAL; + } + +- /* +- * It's a write operation +- */ +- cp_bytes = simple_write_to_buffer(w_buf, *lenp, &w_offset, buffer, 7); +- if (cp_bytes != *lenp) { +- nss_warning("failed to write to buffer\n"); +- return -EFAULT; ++ if (*lenp >= sizeof(w_buf)) { ++ nss_warning("Input too large: %zu\n", *lenp); ++ return -EINVAL; + } + ++ memcpy(w_buf, buffer, *lenp); ++ w_buf[*lenp] = '\0'; /* Ensure null termination */ ++ + count = 0; + str = w_buf; + tokens[count] = strsep(&str, " "); diff --git a/qca-nss-drv/patches/0026-nss-drv-add-support-for-kernel-6.12.patch b/qca-nss-drv/patches/0026-nss-drv-add-support-for-kernel-6.12.patch new file mode 100644 index 0000000..1098172 --- /dev/null +++ b/qca-nss-drv/patches/0026-nss-drv-add-support-for-kernel-6.12.patch @@ -0,0 +1,808 @@ +--- a/nss_core.c ++++ b/nss_core.c +@@ -38,6 +38,9 @@ + #endif + #endif + #include ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 10, 0)) ++#include ++#endif + #include "nss_tx_rx_common.h" + + #ifdef NSS_DATA_PLANE_GENERIC_SUPPORT +@@ -50,26 +53,7 @@ + #define NSS_CORE_JUMBO_LINEAR_BUF_SIZE 128 + + #if (NSS_SKB_REUSE_SUPPORT == 1) +-/* +- * We have validated the skb recycling code within the NSS for the +- * following kernel versions. Before enabling the driver in new kernels, +- * the skb recycle code must be checked against Linux skb handling. +- * +- * Tested on: 3.4, 3.10, 3.14, 3.18, 4.4, 5.4 and 6.6 +- */ +-#if (!( \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(6, 7, 0)))))) +-#error "Check skb recycle code in this file to match Linux version" +-#endif +- + static atomic_t max_reuse = ATOMIC_INIT(PAGE_SIZE); +- + #endif /* NSS_SKB_REUSE_SUPPORT */ + + static int max_ipv4_conn = NSS_DEFAULT_NUM_CONN; +--- a/Makefile ++++ b/Makefile +@@ -630,6 +630,8 @@ qca-nss-drv-objs += \ + ccflags-y += -DNSS_FREQ_SCALE_SUPPORT=1 + endif + ++ccflags-y += -include $(obj)/compat.h ++ + ccflags-y += $(NSS_CCFLAGS) + + export NSS_CCFLAGS +--- a/nss_init.c ++++ b/nss_init.c +@@ -123,10 +123,17 @@ static inline int nss_probe(struct platf + * nss_remove() + * HLOS device remove callback + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0)) + static inline int nss_remove(struct platform_device *nss_dev) + { + return nss_hal_remove(nss_dev); + } ++#else ++static inline void nss_remove(struct platform_device *nss_dev) ++{ ++ nss_hal_remove(nss_dev); ++} ++#endif + + #if (NSS_DT_SUPPORT == 1) + /* +@@ -136,7 +143,6 @@ struct of_device_id nss_dt_ids[] = { + { .compatible = "qcom,nss" }, + { .compatible = "qcom,nss0" }, + { .compatible = "qcom,nss1" }, +- {}, + }; + MODULE_DEVICE_TABLE(of, nss_dt_ids); + #endif +@@ -176,7 +182,7 @@ static void nss_reset_frequency_stats_sa + * nss_current_freq_handler() + * Handle Userspace Frequency Change Requests + */ +-static int nss_current_freq_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_current_freq_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret, i; + +@@ -236,7 +242,7 @@ static int nss_current_freq_handler(stru + * nss_auto_scale_handler() + * Enables or Disable Auto Scaling + */ +-static int nss_auto_scale_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_auto_scale_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -301,7 +307,7 @@ static int nss_auto_scale_handler(struct + * nss_get_freq_table_handler() + * Display Support Freq and Ex how to Change. + */ +-static int nss_get_freq_table_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_get_freq_table_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret, i; + +@@ -330,7 +336,7 @@ static int nss_get_freq_table_handler(st + * nss_get_average_inst_handler() + * Display AVG Inst Per Ms. + */ +-static int nss_get_average_inst_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_get_average_inst_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -352,7 +358,7 @@ static int nss_get_average_inst_handler( + * nss_debug_handler() + * Enable NSS debug output + */ +-static int nss_debug_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_debug_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -372,7 +378,7 @@ static int nss_debug_handler(struct ctl_ + * nss_coredump_handler() + * Send Signal To Coredump NSS Cores + */ +-static int nss_coredump_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_coredump_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[NSS_CORE_0]; + int ret; +@@ -397,7 +403,7 @@ static int nss_coredump_handler(struct c + * nss_jumbo_mru_handler() + * Sysctl to modify nss_jumbo_mru + */ +-static int nss_jumbo_mru_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_jumbo_mru_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -418,7 +424,7 @@ static int nss_jumbo_mru_handler(struct + * Sysctl to modify nss_paged_mode. + */ + +-static int nss_paged_mode_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_paged_mode_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -440,7 +446,7 @@ static int nss_paged_mode_handler(struct + * nss_get_min_reuse_handler() + * Sysctl to get min reuse sizes + */ +-static int nss_get_min_reuse_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_get_min_reuse_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + struct nss_ctx_instance *nss_ctx = NULL; +@@ -467,7 +473,7 @@ static int nss_get_min_reuse_handler(str + * nss_max_reuse_handler() + * Sysctl to modify nss_max_reuse + */ +-static int nss_max_reuse_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_max_reuse_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -502,8 +508,7 @@ static struct ctl_table nss_skb_reuse_ta + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_max_reuse_handler, +- }, +- { } ++ } + }; + #endif + +@@ -539,8 +544,7 @@ static struct ctl_table nss_freq_table[] + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_get_average_inst_handler, +- }, +- { } ++ } + }; + #endif + +@@ -588,8 +592,7 @@ static struct ctl_table nss_general_tabl + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_paged_mode_handler, +- }, +- { } ++ } + }; + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 6, 0)) +--- a/nss_stats.c ++++ b/nss_stats.c +@@ -70,7 +70,7 @@ static size_t nss_stats_spacing(uint64_t + * nss_stats_nonzero_handler() + * Handler to take nonzero stats print configuration. + */ +-static int nss_stats_nonzero_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_stats_nonzero_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + ret = proc_dointvec(ctl, write, buffer, lenp, ppos); +@@ -84,8 +84,7 @@ static struct ctl_table nss_stats_table[ + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_stats_nonzero_handler, +- }, +- { } ++ } + }; + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 6, 0)) +@@ -261,7 +260,7 @@ size_t nss_stats_banner(char *lbuf, size + size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "<"); + } + +- strlcpy(node_upr, node, NSS_STATS_NODE_NAME_MAX); ++ strscpy(node_upr, node, NSS_STATS_NODE_NAME_MAX + 1); + for (i = 0; node_upr[i] != '\0' && i < NSS_STATS_NODE_NAME_MAX; i++) { + node_upr[i] = toupper(node_upr[i]); + } +@@ -326,7 +325,7 @@ size_t nss_stats_print(char *node, char + continue; + } + +- strlcpy(stats_string, stats_info[i].stats_name, NSS_STATS_MAX_STR_LENGTH); ++ strscpy(stats_string, stats_info[i].stats_name, NSS_STATS_MAX_STR_LENGTH); + + /* + * Converting uppercase to lower case. +@@ -335,7 +334,7 @@ size_t nss_stats_print(char *node, char + stats_string[j] = tolower(stats_string[j]); + } + +- strlcpy(node_lwr, node, NSS_STATS_NODE_NAME_MAX); ++ strscpy(node_lwr, node, NSS_STATS_NODE_NAME_MAX + 1); + for (j = 0; node_lwr[j] != '\0' && j < NSS_STATS_NODE_NAME_MAX; j++) { + node_lwr[j] = tolower(node_lwr[j]); + } +--- a/nss_tunipip6_stats.c ++++ b/nss_tunipip6_stats.c +@@ -17,6 +17,10 @@ + ************************************************************************** + */ + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 10, 0) ++#include ++#endif ++ + #include "nss_core.h" + #include "nss_tunipip6.h" + #include "nss_stats.h" +--- /dev/null ++++ b/compat.h +@@ -0,0 +1,14 @@ ++// compat.h ++#ifndef _COMPAT_H ++#define _COMPAT_H ++ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 10, 0) ++#include ++#define compat_const const ++#else ++#define compat_const ++#endif ++ ++#endif /* _COMPAT_H */ +--- a/nss_c2c_tx.c ++++ b/nss_c2c_tx.c +@@ -284,7 +284,7 @@ EXPORT_SYMBOL(nss_c2c_tx_msg_init); + * nss_c2c_tx_performance_test_handler() + * Handles the performance test. + */ +-static int nss_c2c_tx_performance_test_handler(struct ctl_table *ctl, int write, ++static int nss_c2c_tx_performance_test_handler(compat_const struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; +@@ -330,8 +330,7 @@ static struct ctl_table nss_c2c_tx_table + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_c2c_tx_performance_test_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_c2c_tx_header; +--- a/nss_dma.c ++++ b/nss_dma.c +@@ -285,7 +285,7 @@ EXPORT_SYMBOL(nss_dma_get_context); + * nss_dma_test_handler() + * Handles the performance test. + */ +-static int nss_dma_test_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_dma_test_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_ctx_instance *nss_ctx = nss_dma_get_context(); + int cur_state = test_cfg.run.val; +@@ -375,8 +375,7 @@ static struct ctl_table nss_dma_table[] + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec, +- }, +- { } ++ } + }; + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 6, 0)) +--- a/nss_ipv4.c ++++ b/nss_ipv4.c +@@ -599,7 +599,7 @@ void nss_ipv4_free_conn_tables(void) + * nss_ipv4_accel_mode_cfg_handler() + * Configure acceleration mode for IPv4 + */ +-static int nss_ipv4_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv4_accel_mode_cfg_handler(compat_const struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -643,7 +643,7 @@ static int nss_ipv4_accel_mode_cfg_handl + * nss_ipv4_dscp_map_cfg_handler() + * Sysctl handler for dscp/pri mappings. + */ +-static int nss_ipv4_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv4_dscp_map_cfg_handler(compat_const struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -708,8 +708,7 @@ static struct ctl_table nss_ipv4_table[] + .maxlen = sizeof(struct nss_dscp_map_entry), + .mode = 0644, + .proc_handler = &nss_ipv4_dscp_map_cfg_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_ipv4_header; +--- a/nss_ipv6.c ++++ b/nss_ipv6.c +@@ -595,7 +595,7 @@ void nss_ipv6_free_conn_tables(void) + * nss_ipv6_accel_mode_cfg_handler() + * Configure acceleration mode for IPv6 + */ +-static int nss_ipv6_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv6_accel_mode_cfg_handler(compat_const struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -639,7 +639,7 @@ static int nss_ipv6_accel_mode_cfg_handl + * nss_ipv6_dscp_map_cfg_handler() + * Sysctl handler for dscp/pri mappings. + */ +-static int nss_ipv6_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ipv6_dscp_map_cfg_handler(compat_const struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[0]; +@@ -703,8 +703,7 @@ static struct ctl_table nss_ipv6_table[] + .maxlen = sizeof(struct nss_dscp_map_entry), + .mode = 0644, + .proc_handler = &nss_ipv6_dscp_map_cfg_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_ipv6_header; +--- a/nss_log.c ++++ b/nss_log.c +@@ -524,7 +524,7 @@ fail: + * nss_logbuffer_handler() + * Enable NSS debug output + */ +-int nss_logbuffer_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++int nss_logbuffer_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + int core_status; +--- a/nss_n2h.c ++++ b/nss_n2h.c +@@ -357,7 +357,7 @@ static int nss_n2h_get_paged_payload_inf + * nss_n2h_set_empty_buf_pool() + * Sets empty pool buffer + */ +-static int nss_n2h_set_empty_buf_pool(struct ctl_table *ctl, int write, ++static int nss_n2h_set_empty_buf_pool(compat_const struct ctl_table *ctl, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos, + nss_ptr_t core_num, int *new_val) +@@ -459,7 +459,7 @@ failure: + * nss_n2h_set_empty_paged_pool_buf() + * Sets empty paged pool buffer + */ +-static int nss_n2h_set_empty_paged_pool_buf(struct ctl_table *ctl, int write, ++static int nss_n2h_set_empty_paged_pool_buf(compat_const struct ctl_table *ctl, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos, + nss_ptr_t core_num, int *new_val) +@@ -561,7 +561,7 @@ failure: + * nss_n2h_set_water_mark() + * Sets water mark for N2H SOS + */ +-static int nss_n2h_set_water_mark(struct ctl_table *ctl, int write, ++static int nss_n2h_set_water_mark(compat_const struct ctl_table *ctl, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos, + uint32_t core_num, int *low, int *high) +@@ -675,7 +675,7 @@ failure: + * nss_n2h_set_paged_water_mark() + * Sets water mark for paged pool N2H SOS + */ +-static int nss_n2h_set_paged_water_mark(struct ctl_table *ctl, int write, ++static int nss_n2h_set_paged_water_mark(compat_const struct ctl_table *ctl, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos, + uint32_t core_num, int *low, int *high) +@@ -789,7 +789,7 @@ failure: + * nss_n2h_cfg_wifi_pool() + * Sets number of wifi payloads to adjust high water mark for N2H SoS + */ +-static int nss_n2h_cfg_wifi_pool(struct ctl_table *ctl, int write, ++static int nss_n2h_cfg_wifi_pool(compat_const struct ctl_table *ctl, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos, + int *payloads) +@@ -886,7 +886,7 @@ failure: + * nss_n2h_empty_pool_buf_core1_handler() + * Sets the number of empty buffer for core 1 + */ +-static int nss_n2h_empty_pool_buf_cfg_core1_handler(struct ctl_table *ctl, ++static int nss_n2h_empty_pool_buf_cfg_core1_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -898,7 +898,7 @@ static int nss_n2h_empty_pool_buf_cfg_co + * nss_n2h_empty_pool_buf_core0_handler() + * Sets the number of empty buffer for core 0 + */ +-static int nss_n2h_empty_pool_buf_cfg_core0_handler(struct ctl_table *ctl, ++static int nss_n2h_empty_pool_buf_cfg_core0_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -910,7 +910,7 @@ static int nss_n2h_empty_pool_buf_cfg_co + * nss_n2h_empty_paged_pool_buf_cfg_core1_handler() + * Sets the number of empty paged buffer for core 1 + */ +-static int nss_n2h_empty_paged_pool_buf_cfg_core1_handler(struct ctl_table *ctl, ++static int nss_n2h_empty_paged_pool_buf_cfg_core1_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -922,7 +922,7 @@ static int nss_n2h_empty_paged_pool_buf_ + * nss_n2h_empty_paged_pool_buf_cfg_core0_handler() + * Sets the number of empty paged buffer for core 0 + */ +-static int nss_n2h_empty_paged_pool_buf_cfg_core0_handler(struct ctl_table *ctl, ++static int nss_n2h_empty_paged_pool_buf_cfg_core0_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -934,7 +934,7 @@ static int nss_n2h_empty_paged_pool_buf_ + * nss_n2h_water_mark_core1_handler() + * Sets water mark for core 1 + */ +-static int nss_n2h_water_mark_core1_handler(struct ctl_table *ctl, ++static int nss_n2h_water_mark_core1_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -947,7 +947,7 @@ static int nss_n2h_water_mark_core1_hand + * nss_n2h_water_mark_core0_handler() + * Sets water mark for core 0 + */ +-static int nss_n2h_water_mark_core0_handler(struct ctl_table *ctl, ++static int nss_n2h_water_mark_core0_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -960,7 +960,7 @@ static int nss_n2h_water_mark_core0_hand + * nss_n2h_paged_water_mark_core1_handler() + * Sets paged water mark for core 1 + */ +-static int nss_n2h_paged_water_mark_core1_handler(struct ctl_table *ctl, ++static int nss_n2h_paged_water_mark_core1_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -973,7 +973,7 @@ static int nss_n2h_paged_water_mark_core + * nss_n2h_paged_water_mark_core0_handler() + * Sets paged water mark for core 0 + */ +-static int nss_n2h_paged_water_mark_core0_handler(struct ctl_table *ctl, ++static int nss_n2h_paged_water_mark_core0_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -986,7 +986,7 @@ static int nss_n2h_paged_water_mark_core + * nss_n2h_wifi_payloads_handler() + * Sets number of wifi payloads + */ +-static int nss_n2h_wifi_payloads_handler(struct ctl_table *ctl, ++static int nss_n2h_wifi_payloads_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -998,7 +998,7 @@ static int nss_n2h_wifi_payloads_handler + * nss_n2h_get_qos_mem_size_cfg_handler() + * Gets the QoS memory pool size + */ +-static int nss_n2h_get_qos_mem_size_cfg_handler(struct ctl_table *ctl, ++static int nss_n2h_get_qos_mem_size_cfg_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -1281,7 +1281,7 @@ failure: + * nss_mitigation_handler() + * Enable NSS MITIGATION + */ +-static int nss_n2h_mitigationcfg_core0_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_n2h_mitigationcfg_core0_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[NSS_CORE_0]; +@@ -1312,7 +1312,7 @@ static int nss_n2h_mitigationcfg_core0_h + * nss_mitigation_handler() + * Enable NSS MITIGATION + */ +-static int nss_n2h_mitigationcfg_core1_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_n2h_mitigationcfg_core1_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[NSS_CORE_1]; +@@ -1343,7 +1343,7 @@ static int nss_n2h_mitigationcfg_core1_h + * nss_buf_handler() + * Add extra NSS bufs from host memory + */ +-static int nss_n2h_buf_cfg_core0_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_n2h_buf_cfg_core0_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[NSS_CORE_0]; +@@ -1382,7 +1382,7 @@ static int nss_n2h_buf_cfg_core0_handler + * nss_n2h_buf_handler() + * Add extra NSS bufs from host memory + */ +-static int nss_n2h_buf_cfg_core1_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_n2h_buf_cfg_core1_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; + struct nss_ctx_instance *nss_ctx = &nss_top->nss[NSS_CORE_1]; +@@ -1435,7 +1435,7 @@ static void nss_n2h_queue_limit_callback + * nss_n2h_set_queue_limit_sync() + * Sets the n2h queue size limit synchronously. + */ +-static int nss_n2h_set_queue_limit_sync(struct ctl_table *ctl, int write, void __user *buffer, ++static int nss_n2h_set_queue_limit_sync(compat_const struct ctl_table *ctl, int write, void __user *buffer, + size_t *lenp, loff_t *ppos, uint32_t core_id) + { + struct nss_top_instance *nss_top = &nss_top_main; +@@ -1512,7 +1512,7 @@ static int nss_n2h_set_queue_limit_sync( + * nss_n2h_queue_limit_core0_handler() + * Sets the n2h queue size limit for core0 + */ +-static int nss_n2h_queue_limit_core0_handler(struct ctl_table *ctl, ++static int nss_n2h_queue_limit_core0_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -1524,7 +1524,7 @@ static int nss_n2h_queue_limit_core0_han + * nss_n2h_queue_limit_core1_handler() + * Sets the n2h queue size limit for core1 + */ +-static int nss_n2h_queue_limit_core1_handler(struct ctl_table *ctl, ++static int nss_n2h_queue_limit_core1_handler(compat_const struct ctl_table *ctl, + int write, void __user *buffer, + size_t *lenp, loff_t *ppos) + { +@@ -1602,7 +1602,7 @@ static nss_tx_status_t nss_n2h_host_bp_c + * nss_n2h_host_bp_cfg_handler() + * Enable n2h back pressure. + */ +-static int nss_n2h_host_bp_cfg_handler(struct ctl_table *ctl, int write, ++static int nss_n2h_host_bp_cfg_handler(compat_const struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos, uint32_t core_id) + { + struct nss_top_instance *nss_top = &nss_top_main; +@@ -1640,7 +1640,7 @@ static int nss_n2h_host_bp_cfg_handler(s + * nss_n2h_host_bp_cfg_core0_handler() + * Enable n2h back pressure in core 0. + */ +-static int nss_n2h_host_bp_cfg_core0_handler(struct ctl_table *ctl, int write, ++static int nss_n2h_host_bp_cfg_core0_handler(compat_const struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) + { + return nss_n2h_host_bp_cfg_handler(ctl, write, buffer, lenp, ppos, NSS_CORE_0); +@@ -1650,7 +1650,7 @@ static int nss_n2h_host_bp_cfg_core0_han + * nss_n2h_host_bp_cfg_core1_handler() + * Enable n2h back pressure in core 1. + */ +-static int nss_n2h_host_bp_cfg_core1_handler(struct ctl_table *ctl, int write, ++static int nss_n2h_host_bp_cfg_core1_handler(compat_const struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) + { + return nss_n2h_host_bp_cfg_handler(ctl, write, buffer, lenp, ppos, NSS_CORE_1); +@@ -1740,9 +1740,7 @@ static struct ctl_table nss_n2h_table_si + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_n2h_get_qos_mem_size_cfg_handler, +- }, +- +- { } ++ } + }; + + static struct ctl_table nss_n2h_table_multi_core[] = { +@@ -1900,8 +1898,7 @@ static struct ctl_table nss_n2h_table_mu + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_n2h_get_qos_mem_size_cfg_handler, +- }, +- { } ++ } + }; + + +--- a/nss_ppe_vp.c ++++ b/nss_ppe_vp.c +@@ -215,7 +215,7 @@ static void nss_ppe_vp_callback(void *ap + * Since ath0 has only one type i.e. ath0 is NSS_DYNAMIC_INTERFACE_TYPE_VAP, the above command can be rewritten as + * echo ath0 > /proc/sys/nss/ppe_vp/create => Here 6 can be ignored. + */ +-static nss_if_num_t nss_ppe_vp_parse_vp_cmd(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static nss_if_num_t nss_ppe_vp_parse_vp_cmd(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int32_t if_num; + struct net_device *dev; +@@ -693,7 +693,7 @@ static void nss_ppe_vp_handler(struct ns + * nss_ppe_vp_destroy_handler() + * PPE VP destroy handler. + */ +-static int nss_ppe_vp_destroy_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ppe_vp_destroy_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_ctx_instance *nss_ctx = nss_ppe_vp_get_context(); + int32_t if_num; +@@ -730,7 +730,7 @@ static int nss_ppe_vp_destroy_handler(st + * nss_ppe_vp_create_handler() + * PPE VP create handler. + */ +-static int nss_ppe_vp_create_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int nss_ppe_vp_create_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int32_t if_num; + struct nss_ctx_instance *nss_ctx = nss_ppe_vp_get_context(); +@@ -779,8 +779,7 @@ static struct ctl_table nss_ppe_vp_table + .maxlen = sizeof(nss_ppe_vp_cmd), + .mode = 0644, + .proc_handler = &nss_ppe_vp_destroy_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_ppe_vp_procfs_header; +--- a/nss_pppoe.c ++++ b/nss_pppoe.c +@@ -203,7 +203,7 @@ static void nss_pppoe_handler(struct nss + * nss_pppoe_br_accel_mode_handler() + * Enable/disable pppoe bridge acceleration in NSS + */ +-int nss_pppoe_br_accel_mode_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++int nss_pppoe_br_accel_mode_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_ctx_instance *nss_ctx = nss_pppoe_get_context(); + struct nss_pppoe_msg npm; +@@ -349,8 +349,7 @@ static struct ctl_table nss_pppoe_table[ + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_pppoe_br_accel_mode_handler, +- }, +- { } ++ } + }; + + static struct ctl_table_header *nss_pppoe_header; +--- a/nss_project.c ++++ b/nss_project.c +@@ -235,7 +235,7 @@ static void nss_project_msg_handler(stru + * Uses proc_dointvec to process data. For a write operation, also sends worker + * thread stats enable messages containing the new value to each NSS core. + */ +-static int nss_project_wt_stats_handler(struct ctl_table *ctl, int write, ++static int nss_project_wt_stats_handler(compat_const struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) + { + int ret; +@@ -332,8 +332,7 @@ static struct ctl_table nss_project_tabl + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_project_wt_stats_handler, +- }, +- { } ++ } + }; + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 6, 0)) +--- a/nss_rps.c ++++ b/nss_rps.c +@@ -404,7 +404,7 @@ static nss_tx_status_t nss_rps_pri_map_c + * nss_rps_cfg_handler() + * Enable NSS RPS. + */ +-static int nss_rps_cfg_handler(struct ctl_table *ctl, int write, ++static int nss_rps_cfg_handler(compat_const struct ctl_table *ctl, int write, + void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; +@@ -455,7 +455,7 @@ static int nss_rps_cfg_handler(struct ct + * nss_rps_hash_bitmap_cfg_handler() + * Configure NSS rps_hash_bitmap + */ +-static int nss_rps_hash_bitmap_cfg_handler(struct ctl_table *ctl, int write, ++static int nss_rps_hash_bitmap_cfg_handler(compat_const struct ctl_table *ctl, int write, + void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; +@@ -518,7 +518,7 @@ static int nss_rps_hash_bitmap_cfg_handl + /* nss_rps_pri_map_cfg_handler() + * Configure NSS rps_pri_map + */ +-static int nss_rps_pri_map_cfg_handler(struct ctl_table *ctl, int write, ++static int nss_rps_pri_map_cfg_handler(compat_const struct ctl_table *ctl, int write, + void *buffer, size_t *lenp, loff_t *ppos) + { + struct nss_top_instance *nss_top = &nss_top_main; +@@ -571,8 +571,7 @@ static struct ctl_table nss_rps_table[] + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &nss_rps_pri_map_cfg_handler, +- }, +- { } ++ } + }; + + +--- a/nss_core.h ++++ b/nss_core.h +@@ -1036,7 +1036,7 @@ extern void nss_stats_clean(void); + */ + extern void nss_log_init(void); + extern bool nss_debug_log_buffer_alloc(uint8_t nss_id, uint32_t nentry); +-extern int nss_logbuffer_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos); ++extern int nss_logbuffer_handler(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos); + + /* + * APIs to set jumbo_mru & paged_mode +--- a/nss_dscp_map.h ++++ b/nss_dscp_map.h +@@ -46,7 +46,7 @@ struct nss_dscp_map_parse { + * nss_dscp_map_print() + * Sysctl handler for printing dscp/pri mapping. + */ +-static int nss_dscp_map_print(struct ctl_table *ctl, void *buffer, size_t *lenp, ++static int nss_dscp_map_print(compat_const struct ctl_table *ctl, void *buffer, size_t *lenp, + loff_t *ppos, struct nss_dscp_map_entry *mapping) + { + char *r_buf; +@@ -115,7 +115,7 @@ static int nss_dscp_map_print(struct ctl + * nss_dscp_map_parse() + * Sysctl handler for dscp/pri mappings. + */ +-static int nss_dscp_map_parse(struct ctl_table *ctl, void *buffer, size_t *lenp, ++static int nss_dscp_map_parse(compat_const struct ctl_table *ctl, void *buffer, size_t *lenp, + loff_t *ppos, struct nss_dscp_map_parse *out) + { + int count; +--- a/nss_n2h_stats.c ++++ b/nss_n2h_stats.c +@@ -46,6 +46,7 @@ static ssize_t nss_n2h_stats_read(struct + size_t size_wr = 0; + ssize_t bytes_read = 0; + uint64_t *stats_shadow; ++ char n2h_tag[7]; + + char *lbuf = kzalloc(size_al, GFP_KERNEL); + if (unlikely(lbuf == NULL)) { +@@ -69,7 +70,8 @@ static ssize_t nss_n2h_stats_read(struct + stats_shadow[i] = nss_n2h_stats[core][i]; + } + spin_unlock_bh(&nss_top_main.stats_lock); +- size_wr += nss_stats_banner(lbuf, size_wr, size_al, "n2h", core); ++ snprintf(n2h_tag, 7, "N2H %d", core); ++ size_wr += nss_stats_banner(lbuf, size_wr, size_al, n2h_tag, NSS_STATS_SINGLE_CORE); + size_wr += nss_stats_print("n2h", NULL, NSS_STATS_SINGLE_INSTANCE + , nss_n2h_strings_stats + , stats_shadow diff --git a/qca-nss-drv/patches/0026-nss_gre-fix-missing-macro.patch b/qca-nss-drv/patches/0026-nss_gre-fix-missing-macro.patch new file mode 100644 index 0000000..17cdc22 --- /dev/null +++ b/qca-nss-drv/patches/0026-nss_gre-fix-missing-macro.patch @@ -0,0 +1,14 @@ +--- a/exports/nss_gre_tunnel.h ++++ b/exports/nss_gre_tunnel.h +@@ -212,7 +212,11 @@ struct nss_gre_tunnel_stats { + * GRE tunnel transmission statistics structure. + */ + struct nss_gre_tunnel_stats_notification { ++#if defined(NSS_HAL_IPQ807x_SUPPORT) + uint64_t stats_ctx[NSS_GRE_TUNNEL_STATS_SESSION_MAX + NSS_CRYPTO_CMN_RESP_ERROR_MAX]; ++#else ++ uint64_t stats_ctx[NSS_GRE_TUNNEL_STATS_SESSION_MAX]; ++#endif + /**< Context transmission statistics. */ + uint32_t core_id; /**< Core ID. */ + uint32_t if_num; /**< Interface number. */ diff --git a/qca-nss-drv/patches/0026-treewide-fix-compiler-warnings.patch b/qca-nss-drv/patches/0026-treewide-fix-compiler-warnings.patch new file mode 100644 index 0000000..567684a --- /dev/null +++ b/qca-nss-drv/patches/0026-treewide-fix-compiler-warnings.patch @@ -0,0 +1,102 @@ +--- a/nss_core.c ++++ b/nss_core.c +@@ -2278,12 +2278,16 @@ static void nss_core_handle_cause_nonque + * of processor will prevent any excessive penalties. + */ + if (unlikely(nss_ctx->state == NSS_CORE_STATE_UNINITIALIZED)) { ++#ifdef NSS_DRV_C2C_ENABLE + struct nss_top_instance *nss_top = NULL; ++#endif + nss_core_init_nss(nss_ctx, if_map); + nss_send_ddr_info(nss_ctx); + + dev_info(nss_ctx->dev, "NSS core %d booted successfully\n", nss_ctx->id); ++#ifdef NSS_DRV_C2C_ENABLE + nss_top = nss_ctx->nss_top; ++#endif + + #ifdef NSS_DRV_C2C_ENABLE + #if (NSS_MAX_CORES > 1) +--- a/nss_edma_stats.c ++++ b/nss_edma_stats.c +@@ -650,9 +650,8 @@ void nss_edma_stats_dentry_create(void) + /* + * edma error stats + */ +- edma_err_stats_d = NULL; + edma_err_stats_d = debugfs_create_file("err_stats", 0400, edma_d, &nss_top_main, &nss_edma_err_stats_ops); +- if (unlikely(edma_port_stats_d == NULL)) { ++ if (unlikely(edma_err_stats_d == NULL)) { + nss_warning("Failed to create qca-nss-drv/stats/edma/%d/err_stats file", 0); + return; + } +--- a/nss_match.c ++++ b/nss_match.c +@@ -244,7 +244,7 @@ EXPORT_SYMBOL(nss_match_unregister_insta + * nss_match_register_instance() + * Registers match instance. + */ +-struct nss_ctx_instance *nss_match_register_instance(int if_num, nss_match_msg_sync_callback_t notify_cb) ++struct nss_ctx_instance *nss_match_register_instance(int if_num, void (*notify_cb)(void *, struct nss_cmn_msg *)) + { + struct nss_ctx_instance *nss_ctx; + uint32_t status; +@@ -258,7 +258,7 @@ struct nss_ctx_instance *nss_match_regis + } + + nss_core_register_handler(nss_ctx, if_num, nss_match_handler, NULL); +- status = nss_core_register_msg_handler(nss_ctx, if_num, (nss_if_rx_msg_callback_t)notify_cb); ++ status = nss_core_register_msg_handler(nss_ctx, if_num, notify_cb); + if (status != NSS_CORE_STATUS_SUCCESS) { + nss_warning("%px: Not able to register handler for interface %d with NSS core\n", nss_ctx, if_num); + return NULL; +@@ -290,7 +290,7 @@ EXPORT_SYMBOL(nss_match_msg_init); + * nss_match_init() + * Initialize match. + */ +-void nss_match_init() ++void nss_match_init(void) + { + nss_match_stats_dentry_create(); + nss_match_strings_dentry_create(); +--- a/nss_map_t.c ++++ b/nss_map_t.c +@@ -378,7 +378,7 @@ EXPORT_SYMBOL(nss_map_t_unregister_if); + /* + * nss_get_map_t_context() + */ +-struct nss_ctx_instance *nss_map_t_get_context() ++struct nss_ctx_instance *nss_map_t_get_context(void) + { + return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.map_t_handler_id]; + } +--- a/exports/nss_match.h ++++ b/exports/nss_match.h +@@ -247,7 +247,7 @@ extern struct nss_ctx_instance *nss_matc + * @return + * Pointer to the NSS core context. + */ +-extern struct nss_ctx_instance *nss_match_register_instance(int if_num, nss_match_msg_sync_callback_t notify_cb); ++extern struct nss_ctx_instance *nss_match_register_instance(int if_num, void (*notify_cb)(void *, struct nss_cmn_msg *)); + + /** + * nss_match_unregister_instance +--- a/nss_lag.c ++++ b/nss_lag.c +@@ -237,7 +237,7 @@ nss_tx_status_t nss_lag_tx_slave_state(u + struct nss_lag_pvt lag_msg_state; + + init_completion(&lag_msg_state.complete); +- lag_msg_state.response = false; ++ lag_msg_state.response = NSS_CMN_RESPONSE_ACK; + + /* + * Construct a message to the NSS to update it +@@ -268,6 +268,6 @@ nss_tx_status_t nss_lag_tx_slave_state(u + return NSS_TX_FAILURE; + } + +- return lag_msg_state.response; ++ return (nss_tx_status_t)lag_msg_state.response; + } + EXPORT_SYMBOL(nss_lag_tx_slave_state); diff --git a/qca-nss-drv/patches/0027-Makefile-set-rearrange-arch-features.patch b/qca-nss-drv/patches/0027-Makefile-set-rearrange-arch-features.patch new file mode 100644 index 0000000..29976ca --- /dev/null +++ b/qca-nss-drv/patches/0027-Makefile-set-rearrange-arch-features.patch @@ -0,0 +1,75 @@ +--- a/Makefile ++++ b/Makefile +@@ -122,12 +122,14 @@ qca-nss-drv-objs += \ + endif + endif + ++ifeq ($(SoC),$(filter $(SoC),ipq806x)) + ifneq "$(NSS_DRV_TSTAMP_ENABLE)" "n" + ccflags-y += -DNSS_DRV_TSTAMP_ENABLE + qca-nss-drv-objs += \ + nss_tstamp.o \ + nss_tstamp_stats.o + endif ++endif + + ifneq "$(NSS_DRV_GRE_ENABLE)" "n" + ccflags-y += -DNSS_DRV_GRE_ENABLE +@@ -255,6 +257,7 @@ qca-nss-drv-objs += \ + nss_rmnet_rx_stats.o + endif + ++ifeq ($(SoC),$(filter $(SoC),ipq806x)) + ifneq "$(NSS_DRV_PORTID_ENABLE)" "n" + ccflags-y += -DNSS_DRV_PORTID_ENABLE + qca-nss-drv-objs += \ +@@ -262,6 +265,7 @@ qca-nss-drv-objs += \ + nss_portid_log.o \ + nss_portid_stats.o + endif ++endif + + ifneq "$(NSS_DRV_IGS_ENABLE)" "n" + ccflags-y += -DNSS_DRV_IGS_ENABLE +@@ -270,12 +274,14 @@ qca-nss-drv-objs += \ + nss_igs_stats.o + endif + ++ifeq ($(SoC),$(filter $(SoC),ipq806x)) + ifneq "$(NSS_DRV_OAM_ENABLE)" "n" + ccflags-y += -DNSS_DRV_OAM_ENABLE + qca-nss-drv-objs += \ + nss_oam.o \ + nss_oam_log.o + endif ++endif + + ifneq "$(NSS_DRV_CLMAP_ENABLE)" "n" + ccflags-y += -DNSS_DRV_CLMAP_ENABLE +@@ -350,16 +356,13 @@ endif + + ifneq "$(NSS_DRV_WIFIOFFLOAD_ENABLE)" "n" + ccflags-y += -DNSS_DRV_WIFIOFFLOAD_ENABLE +-ifneq "$(NSS_DRV_WIFI_LEGACY_ENABLE)" "n" +-ccflags-y += -DNSS_DRV_WIFI_LEGACY_ENABLE ++ifeq ($(SoC),$(filter $(SoC),ipq806x)) + qca-nss-drv-objs += \ + nss_wifi.o \ + nss_wifi_log.o \ + nss_wifi_stats.o +-ifeq ($(SoC),$(filter $(SoC),ipq806x)) + ccflags-y += -DNSS_HAL_IPQ806x_SUPPORT +-endif +-endif ++else + qca-nss-drv-objs += \ + nss_wifi_vdev.o \ + nss_wifili.o \ +@@ -368,6 +371,7 @@ qca-nss-drv-objs += \ + nss_wifili_strings.o \ + nss_wifi_mac_db.o + endif ++endif + + ifneq "$(NSS_DRV_VLAN_ENABLE)" "n" + ccflags-y += -DNSS_DRV_VLAN_ENABLE diff --git a/qca-nss-drv/patches/0027-nss-drv-fix-null-ptr-log.patch b/qca-nss-drv/patches/0027-nss-drv-fix-null-ptr-log.patch new file mode 100644 index 0000000..7dc7a67 --- /dev/null +++ b/qca-nss-drv/patches/0027-nss-drv-fix-null-ptr-log.patch @@ -0,0 +1,46 @@ +--- a/nss_bridge_log.c ++++ b/nss_bridge_log.c +@@ -99,7 +99,7 @@ static void nss_bridge_log_verbose(struc + */ + void nss_bridge_log_tx_msg(struct nss_bridge_msg *nbm) + { +- if (nbm->cm.type >= NSS_BRIDGE_MSG_TYPE_MAX) { ++ if (nbm->cm.type < (NSS_IF_MAX_MSG_TYPES + 1) || nbm->cm.type >= (NSS_IF_MAX_MSG_TYPES + NSS_BRIDGE_MSG_TYPE_MAX + 1)) { + nss_warning("%px: Invalid message type\n", nbm); + return; + } +@@ -119,6 +119,11 @@ void nss_bridge_log_rx_msg(struct nss_br + return; + } + ++ if (nbm->cm.type < (NSS_IF_MAX_MSG_TYPES + 1) || nbm->cm.type >= (NSS_IF_MAX_MSG_TYPES + NSS_BRIDGE_MSG_TYPE_MAX + 1)) { ++ nss_warning("%px: Invalid message type\n", nbm); ++ return; ++ } ++ + if (nbm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nbm->cm.response == NSS_CMN_RESPONSE_ACK)) { + nss_info("%px: type[%d]:%s, response[%d]:%s\n", nbm, nbm->cm.type, + nss_bridge_log_message_types_str[nbm->cm.type - NSS_IF_MAX_MSG_TYPES - 1], +--- a/nss_gre_log.c ++++ b/nss_gre_log.c +@@ -151,7 +151,7 @@ static void nss_gre_log_verbose(struct n + */ + void nss_gre_log_tx_msg(struct nss_gre_msg *ngm) + { +- if (ngm->cm.type >= NSS_GRE_MSG_MAX) { ++ if (ngm->cm.type < (NSS_IF_MAX_MSG_TYPES + 1) || ngm->cm.type >= (NSS_IF_MAX_MSG_TYPES + NSS_GRE_MSG_MAX + 1)) { + nss_warning("%px: Invalid message type\n", ngm); + return; + } +@@ -171,6 +171,11 @@ void nss_gre_log_rx_msg(struct nss_gre_m + return; + } + ++ if (ngm->cm.type < (NSS_IF_MAX_MSG_TYPES + 1) || ngm->cm.type >= (NSS_IF_MAX_MSG_TYPES + NSS_GRE_MSG_MAX + 1)) { ++ nss_warning("%px: Invalid message type\n", ngm); ++ return; ++ } ++ + if (ngm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ngm->cm.response == NSS_CMN_RESPONSE_ACK)) { + nss_info("%px: type[%d]:%s, response[%d]:%s\n", ngm, ngm->cm.type, + nss_gre_log_message_types_str[NSS_GRE_LOG_MESSAGE_TYPE_INDEX(ngm->cm.type)], diff --git a/qca-nss-drv/patches/0028-nss_ppe_vp-fix-create-destroy.patch b/qca-nss-drv/patches/0028-nss_ppe_vp-fix-create-destroy.patch new file mode 100644 index 0000000..ebbbfec --- /dev/null +++ b/qca-nss-drv/patches/0028-nss_ppe_vp-fix-create-destroy.patch @@ -0,0 +1,57 @@ +--- a/nss_ppe_vp.c ++++ b/nss_ppe_vp.c +@@ -96,8 +96,8 @@ static void nss_ppe_vp_proc_help(void) + { + nss_info_always("== for dynamic interface types read following file =="); + nss_info_always("/sys/kernel/debug/qca-nss-drv/stats/dynamic_if/type_names"); +- nss_info_always("NSS PPE VP create: echo > /proc/sys/nss/ppe_vp/create"); +- nss_info_always("NSS PPE VP destroy: echo > /proc/sys/nss/ppe_vp/destroy"); ++ nss_info_always("NSS PPE VP create: echo > /proc/sys/dev/nss/ppe_vp/create"); ++ nss_info_always("NSS PPE VP destroy: echo > /proc/sys/dev/nss/ppe_vp/destroy"); + } + + /* +@@ -210,20 +210,19 @@ static void nss_ppe_vp_callback(void *ap + * nss_ppe_vp_parse_vp_cmd() + * Parse PPE VP create and destroy message and return the NSS interface number. + * Command usage: +- * echo /proc/sys/nss/ppe_vp/create> +- * echo ath0 6 > /proc/sys/nss/ppe_vp/create ++ * echo /proc/sys/dev/nss/ppe_vp/create> ++ * echo ath0 6 > /proc/sys/dev/nss/ppe_vp/create + * Since ath0 has only one type i.e. ath0 is NSS_DYNAMIC_INTERFACE_TYPE_VAP, the above command can be rewritten as +- * echo ath0 > /proc/sys/nss/ppe_vp/create => Here 6 can be ignored. ++ * echo ath0 > /proc/sys/dev/nss/ppe_vp/create => Here 6 can be ignored. + */ + static nss_if_num_t nss_ppe_vp_parse_vp_cmd(compat_const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) + { + int32_t if_num; + struct net_device *dev; +- uint32_t dynamic_if_type = (uint32_t)NSS_DYNAMIC_INTERFACE_TYPE_NONE; ++ uint32_t dynamic_if_type = (uint32_t)NSS_DYNAMIC_INTERFACE_TYPE_NONE; + struct nss_ctx_instance *nss_ctx = nss_ppe_vp_get_context(); + char *pos; + char cmd_buf[NSS_PPE_VP_MAX_CMD_STR] = {0}, dev_name[NSS_PPE_VP_MAX_CMD_STR] = {0}; +- size_t count = *lenp; + int ret = proc_dostring(ctl, write, buffer, lenp, ppos); + + if (!write) { +@@ -238,17 +237,7 @@ static nss_if_num_t nss_ppe_vp_parse_vp_ + + NSS_VERIFY_CTX_MAGIC(nss_ctx); + +- if (count >= NSS_PPE_VP_MAX_CMD_STR) { +- nss_ppe_vp_proc_help(); +- nss_warning("%px: Input string too big", nss_ctx); +- return -E2BIG; +- } +- +- if (copy_from_user(cmd_buf, buffer, count)) { +- nss_warning("%px: Cannot copy user's entry to kernel memory", nss_ctx); +- return -EFAULT; +- } +- ++ /* proc_dostring has already copied the data to nss_ppe_vp_cmd */ + if ((pos = strrchr(cmd_buf, '\n')) != NULL) { + *pos = '\0'; + } diff --git a/qca-nss-ecm/Makefile b/qca-nss-ecm/Makefile new file mode 100644 index 0000000..d7cba36 --- /dev/null +++ b/qca-nss-ecm/Makefile @@ -0,0 +1,196 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-ecm +PKG_RELEASE:=7 + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-nss-ecm.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2024-11-06 +PKG_SOURCE_VERSION:=30fbfa4 +PKG_MIRROR_HASH:=a6b508a41ae79cb579e83ea1d1f5a158c7758ab45f1d26a698677a5ec61ca03d +QSDK_VERSION:=12.5 +PKG_VERSION:=$(QSDK_VERSION).$(subst -,.,$(PKG_SOURCE_DATE))~$(PKG_SOURCE_VERSION) + +PKG_BUILD_PARALLEL:=1 +PKG_FLAGS:=nonshared +PKG_BUILD_FLAGS:=gc-sections lto + +PKG_CONFIG_DEPENDS:= \ + CONFIG_NSS_DRV_PPPOE_ENABLE + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-ecm + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + DEPENDS:=@(TARGET_qualcommbe||TARGET_qualcommax||TARGET_ipq806x) \ + +ethtool \ + +kmod-nf-conntrack \ + +@(TARGET_qualcommax||TARGET_ipq806x):NSS_DRV_IPV6_ENABLE \ + +@(TARGET_qualcommax||TARGET_ipq806x):NSS_DRV_VIRT_IF_ENABLE \ + +@((TARGET_qualcommax||TARGET_ipq806x)&&PACKAGE_kmod-pppoe):NSS_DRV_PPPOE_ENABLE \ + +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \ + +PACKAGE_kmod-qca-mcs:kmod-qca-mcs \ + +PACKAGE_kmod-bonding:kmod-bonding \ + +PACKAGE_kmod-vxlan:kmod-vxlan \ + +PACKAGE_kmod-nat46:kmod-nat46 \ + +PACKAGE_kmod-ppp:kmod-ppp \ + +PACKAGE_kmod-pppoe:kmod-pppoe \ + +PACKAGE_kmod-pppoe:kmod-pptp \ + +PACKAGE_kmod-pppoe:kmod-pppol2tp + TITLE:=QCA NSS Enhanced Connection Manager (ECM) + FILES:=$(PKG_BUILD_DIR)/ecm.ko + KCONFIG:=CONFIG_NF_CONNTRACK_DSCPREMARK_EXT=y +endef + +define KernelPackage/qca-nss-ecm/Description +This package contains the QCA NSS Enhanced Connection Manager +endef + +define KernelPackage/qca-nss-ecm/conffiles +/etc/config/ecm +endef + +define KernelPackage/qca-nss-ecm/install + $(INSTALL_DIR) $(1)/etc/firewall.d $(1)/etc/init.d $(1)/usr/bin $(1)/lib/netifd/offload $(1)/etc/config $(1)/etc/uci-defaults $(1)/etc/sysctl.d $(1)/etc/hotplug.d/net + $(INSTALL_DATA) ./files/qca-nss-ecm.firewall $(1)/etc/firewall.d/qca-nss-ecm + $(INSTALL_BIN) ./files/qca-nss-ecm.init $(1)/etc/init.d/qca-nss-ecm + $(INSTALL_BIN) ./files/ecm_dump.sh $(1)/usr/bin/ + $(INSTALL_DATA) ./files/disable_offloads.sh $(1)/lib/netifd/offload + $(INSTALL_DATA) ./files/on-demand-down $(1)/lib/netifd/offload/on-demand-down + $(INSTALL_DATA) ./files/qca-nss-ecm.uci $(1)/etc/config/ecm + $(INSTALL_DATA) ./files/qca-nss-ecm.defaults $(1)/etc/uci-defaults/99-qca-nss-ecm + $(INSTALL_DATA) ./files/qca-nss-ecm.sysctl $(1)/etc/sysctl.d/qca-nss-ecm.conf + $(INSTALL_DATA) ./files/disable_offloads.hotplug $(1)/etc/hotplug.d/net/99-disable_offloads +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(STAGING_DIR)/usr/include/qca-mcs \ + -I$(STAGING_DIR)/usr/include/nat46 + +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "qualcommax" "ipq60xx")) +ECM_MAKE_OPTS+= ECM_NON_PORTED_SUPPORT_ENABLE=y \ + ECM_INTERFACE_VLAN_ENABLE=y \ + ECM_CLASSIFIER_MARK_ENABLE=y \ + ECM_CLASSIFIER_DSCP_ENABLE=y \ + ECM_CLASSIFIER_PCC_ENABLE=n +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv),) +ECM_MAKE_OPTS+=ECM_FRONT_END_NSS_ENABLE=y +endif + +# Disable ECM IPv6 support when global IPv6 support is disabled. +ifneq ($(CONFIG_IPV6),) +ECM_MAKE_OPTS+=ECM_IPV6_ENABLE=y +endif + +# Disable ECM Bridge VLAN Filtering support when global kernel config is disabled +ifneq ($(CONFIG_BRIDGE_VLAN_FILTERING),) +ECM_MAKE_OPTS+=ECM_BRIDGE_VLAN_FILTERING_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-igs),) +ECM_MAKE_OPTS+=ECM_CLASSIFIER_DSCP_IGS=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ovpn-link),) +ECM_MAKE_OPTS+=ECM_INTERFACE_OVPN_ENABLE=y +endif + +ifeq ($(CONFIG_PACKAGE_kmod-vxlan),y) +ECM_MAKE_OPTS+=ECM_INTERFACE_VXLAN_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-ovsmgr),) +ECM_MAKE_OPTS+=ECM_INTERFACE_OVS_BRIDGE_ENABLE=y \ + ECM_CLASSIFIER_OVS_ENABLE=y +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-ovsmgr +endif + +ifneq ($(CONFIG_PACKAGE_kmod-macvlan),) +ECM_MAKE_OPTS+=ECM_INTERFACE_MACVLAN_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-mcs),) +ECM_MAKE_OPTS+=ECM_MULTICAST_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-nat46),) +ECM_MAKE_OPTS+=ECM_INTERFACE_MAP_T_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-ipsec),) +ECM_MAKE_OPTS+=ECM_INTERFACE_IPSEC_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-pppoe),) +ECM_MAKE_OPTS+=ECM_INTERFACE_PPPOE_ENABLE=y \ + ECM_INTERFACE_PPTP_ENABLE=y \ + ECM_INTERFACE_PPP_ENABLE=y +else +ECM_MAKE_OPTS+=ECM_INTERFACE_PPPOE_ENABLE=n \ + ECM_INTERFACE_PPTP_ENABLE=n \ + ECM_INTERFACE_PPP_ENABLE=n +endif + +ifneq ($(CONFIG_PACKAGE_kmod-pppol2tp),) +ECM_MAKE_OPTS+=ECM_INTERFACE_L2TPV2_ENABLE=y +else +ECM_MAKE_OPTS+=ECM_INTERFACE_L2TPV2_ENABLE=n +endif + +ifneq ($(CONFIG_PACKAGE_kmod-gre)$(CONFIG_PACKAGE_kmod-gre6),) +ECM_MAKE_OPTS+=ECM_INTERFACE_GRE_TAP_ENABLE=y \ + ECM_INTERFACE_GRE_TUN_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-sit),) +ECM_MAKE_OPTS+=ECM_INTERFACE_SIT_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-ip6-tunnel),) +ECM_MAKE_OPTS+=ECM_INTERFACE_TUNIPIP6_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-mscs),) +ECM_MAKE_OPTS+=ECM_CLASSIFIER_MSCS_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-bonding),) +ECM_MAKE_OPTS+=ECM_INTERFACE_BOND_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qmi_wwan_q),) +ECM_MAKE_OPTS+=ECM_INTERFACE_RAWIP_ENABLE=y +endif + +ifneq ($(CONFIG_NSS_FIRMWARE_VERSION_12_5),) +EXTRA_CFLAGS+=-DNSS_FIRMWARE_VERSION_12_5 +endif + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-ecm + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm +endef + +ifeq ($(CONFIG_TARGET_BOARD), "qualcommax") + SOC:=$(CONFIG_TARGET_SUBTARGET) +endif + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" $(strip $(ECM_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-ecm)) diff --git a/qca-nss-ecm/files/disable_offloads.hotplug b/qca-nss-ecm/files/disable_offloads.hotplug new file mode 100644 index 0000000..0444882 --- /dev/null +++ b/qca-nss-ecm/files/disable_offloads.hotplug @@ -0,0 +1,17 @@ +#!/bin/sh +# shellcheck disable=1090 + +[ "$ACTION" != "add" ] && exit + +INC="/lib/netifd/offload/disable_offloads.sh" +. "$INC" 2> /dev/null || { + logger -t "$PROG" -p user.error "missing include script $INC. exiting..." + exit 1 +} + +# Only disable offloads for physical interfaces +if [ -r "/sys/class/net/$INTERFACE/device" ]; then + disable_offload "$INTERFACE" +fi + +exit 0 diff --git a/qca-nss-ecm/files/disable_offloads.sh b/qca-nss-ecm/files/disable_offloads.sh new file mode 100644 index 0000000..ecae95a --- /dev/null +++ b/qca-nss-ecm/files/disable_offloads.sh @@ -0,0 +1,227 @@ +#!/bin/sh +# shellcheck disable=3014,3043,2086,1091,2154 +# +# Helper script which uses ethtool to disable (most) +# interface offloads, if possible. +# +# Reference: +# https://forum.openwrt.org/t/how-to-make-ethtool-setting-persistent-on-br-lan/6433/14 +# +. /lib/functions.sh + +log() { + local status="$1" + local feature="$2" + local interface="$3" + + if [ $status -eq 0 ]; then + logger "[ethtool] $feature: disabled on $interface" + fi + + if [ $status -eq 1 ]; then + logger -s "[ethtool] $feature: failed to disable on $interface" + fi + + if [ $status -gt 1 ]; then + logger "[ethtool] $feature: no changes performed on $interface" + fi +} + +interface_is_virtual() { + local interface="$1" + [ -d /sys/devices/virtual/net/"$interface"/ ] || return 1 + return 0 +} + +get_base_interface() { + local interface="$1" + echo "$interface" | grep -Eo '^[a-z]*[0-9]*' 2> /dev/null || return 1 + return 0 +} + +disable_offloads() { + local interface="$1" + local features + local cmd + + # Check if we can change features + if ethtool -k $interface 1> /dev/null 2> /dev/null; then + + # Filter whitespaces + # Get only enabled/not fixed features + # Filter features that are only changeable by global keyword + # Filter empty lines + # Cut to First column + features=$(ethtool -k "$interface" | awk '{$1=$1;print}' \ + | grep -E '^.+: on$' \ + | grep -v -E '^tx-checksum-.+$' \ + | grep -v -E '^tx-scatter-gather.+$' \ + | grep -v -E '^tx-tcp.+segmentation.+$' \ + | grep -v -E '^tx-udp-fragmentation$' \ + | grep -v -E '^tx-generic-segmentation$' \ + | grep -v -E '^rx-gro$' \ + | grep -v -E '^$' \ + | cut -d: -f1) + + # Replace feature name by global keyword + echo $features + features=$(echo "$features" | sed -e s/rx-checksumming/rx/ \ + -e s/tx-checksumming/tx/ \ + -e s/scatter-gather/sg/ \ + -e s/tcp-segmentation-offload/tso/ \ + -e s/udp-fragmentation-offload/ufo/ \ + -e s/generic-segmentation-offload/gso/ \ + -e s/generic-receive-offload/gro/ \ + -e s/large-receive-offload/lro/ \ + -e s/rx-vlan-offload/rxvlan/ \ + -e s/tx-vlan-offload/txvlan/ \ + -e s/ntuple-filters/ntuple/ \ + -e s/receive-hashing/rxhash/) + + # Check if we can disable anything + if [ -z "$features" ]; then + logger "[ethtool] Offloads : no changes performed on $interface" + return 0 + fi + + # Construct ethtool command line + cmd="-K $interface" + + for feature in $features; do + cmd="$cmd $feature off" + done + + # Try to disable offloads + ethtool $cmd 1> /dev/null 2> /dev/null + log $? "Offloads" "$interface" + + else + log $? "Offloads" "$interface" + fi +} + +disable_feature() { + local feature="$1" + local interface="$2" + local cmd + local current_state + + current_state=$(ethtool -k $interface 2>/dev/null | awk -v feature="^$feature:" '$0 ~ feature {print $2}') + + # Only disable and log if the feature is currently enabled + if [ "$current_state" = "on" ]; then + # Construct ethtool command line + cmd="-K $interface $feature off" + + # Try to disable the feature + ethtool $cmd 1> /dev/null 2> /dev/null + log $? "Disabling feature: $feature" "($interface)" + fi +} + +disable_flow_control() { + local interface="$1" + local cmd + + # Check if we can change settings + if ethtool -a $interface 1> /dev/null 2> /dev/null; then + + # Construct ethtool command line + cmd="-A $interface autoneg off tx off rx off" + + # Try to disable flow control + ethtool $cmd 1> /dev/null 2> /dev/null + log $? "Flow Control" "$interface" + + else + log $? "Flow Control" "$interface" + fi +} + +disable_interrupt_moderation() { + local interface="$1" + local features + local cmd + + # Check if we can change settings + if ethtool -c $interface 1> /dev/null 2> /dev/null; then + # Construct ethtool command line + cmd="-C $interface adaptive-tx off adaptive-rx off" + + # Try to disable adaptive interrupt moderation + ethtool $cmd 1> /dev/null 2> /dev/null + log $? "Adaptive Interrupt Moderation" "$interface" + + features=$(ethtool -c $interface | awk '{$1=$1;print}' \ + | grep -v -E '^.+: 0$|Adaptive|Coalesce' \ + | grep -v -E '^$' \ + | cut -d: -f1) + + # Check if we can disable anything + if [ -z "$features" ]; then + logger "[ethtool] Interrupt Moderation: no changes performed on $interface" + return 0 + fi + + # Construct ethtool command line + cmd="-C $interface" + + for feature in $features; do + cmd="$cmd $feature 0" + done + + # Try to disable interrupt Moderation + ethtool $cmd 1> /dev/null 2> /dev/null + log $? "Interrupt Moderation" "$interface" + + else + log $? "Interrupt Moderation" "$interface" + fi +} + +disable_offload() { + config_load ecm + + config_get_bool enable_bridge_filtering general enable_bridge_filtering 0 + config_get_bool disable_offloads general disable_offloads 0 + config_get_bool disable_flow_control general disable_flow_control 0 + config_get_bool disable_interrupt_moderation general disable_interrupt_moderation 0 + config_get_bool disable_gro general disable_gro 0 + config_get_bool disable_gro_list general disable_gro_list 1 + + [ -z $1 ] && interface=$(echo /sys/class/net/*/device) || interface=$* + + for iface in $interface; do + i=${iface%/*} + i=${i##*/} + + # Skip Loopback and Bonding Masters + if [ $i == lo ] || [ -f $iface ]; then + continue + fi + + if [ "$disable_gro" -eq 1 ]; then + disable_feature gro "$i" + fi + + if [ "$disable_gro_list" -eq 1 ]; then + disable_feature "rx-gro-list" "$i" + else + logger -p user.warn -s "[ethtool] Enabling rx-gro-list (GRO Fraglist) will break UDP related traffic. (e.g. DNS, DHCP)" + logger -p user.warn -s "[ethtool] Leave this feature enabled unless you know what you are doing." + logger -p user.warn -s "[ethtool] Run \`uci set ecm.general.disable_gro_list=1 && uci commit ecm && service qca-nss-ecm restart\`" + fi + + if [ "$disable_offloads" -eq 1 ]; then + disable_offloads "$i" + fi + + if [ "$disable_flow_control" -eq 1 ]; then + disable_flow_control "$i" + fi + + if [ "$disable_interrupt_moderation" -eq 1 ]; then + disable_interrupt_moderation "$i" + fi + done +} diff --git a/qca-nss-ecm/files/ecm_dump.sh b/qca-nss-ecm/files/ecm_dump.sh new file mode 100644 index 0000000..dbf7de7 --- /dev/null +++ b/qca-nss-ecm/files/ecm_dump.sh @@ -0,0 +1,95 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +ECM_MODULE=${1:-ecm_state} +MOUNT_ROOT=/dev/ecm + +# +# usage: ecm_dump.sh [module=ecm_db] +# +# with no parameters, ecm_dump.sh will attempt to mount the +# ecm_db state file and cat its contents. +# +# example with a parameter: ecm_dump.sh ecm_classifier_default +# +# this will cause ecm_dump to attempt to find and mount the state +# file for the ecm_classifier_default module, and if successful +# cat the contents. +# + +# this is one of the state files, which happens to be the +# last module started in ecm +ECM_STATE=/sys/kernel/debug/ecm/ecm_state/state_dev_major + +# tests to see if ECM is up and ready to receive commands. +# returns 0 if ECM is fully up and ready, else 1 +ecm_is_ready() { + if [ ! -e "${ECM_STATE}" ] + then + return 1 + fi + return 0 +} + +# +# module_state_mount(module_name) +# Mounts the state file of the module, if supported +# +module_state_mount() { + local module_name=$1 + local mount_dir=$2 + local state_file="/sys/kernel/debug/ecm/${module_name}/state_dev_major" + + if [ -e "${mount_dir}/${module_name}" ] + then + # already mounted + return 0 + fi + + #echo "Mount state file for $module_name ..." + if [ ! -e "$state_file" ] + then + #echo "... $module_name does not support state" + return 1 + fi + + local major="`cat $state_file`" + #echo "... Mounting state $state_file with major: $major" + mknod "${mount_dir}/${module_name}" c $major 0 +} + +# +# main +# +ecm_is_ready || { + #echo "ECM is not running" + exit 1 +} + +# all state files are mounted under MOUNT_ROOT, so make sure it exists +mkdir -p ${MOUNT_ROOT} + +# +# attempt to mount state files for the requested module and cat it +# if the mount succeeded +# +module_state_mount ${ECM_MODULE} ${MOUNT_ROOT} && { + cat ${MOUNT_ROOT}/${ECM_MODULE} + exit 0 +} + +exit 2 diff --git a/qca-nss-ecm/files/on-demand-down b/qca-nss-ecm/files/on-demand-down new file mode 100644 index 0000000..02d708e --- /dev/null +++ b/qca-nss-ecm/files/on-demand-down @@ -0,0 +1,6 @@ +#!/bin/sh +# Copyright (c) 2016 The Linux Foundation. All rights reserved. + +[ -e "/sys/kernel/debug/ecm/ecm_db/defunct_all" ] && { + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all +} diff --git a/qca-nss-ecm/files/qca-nss-ecm.defaults b/qca-nss-ecm/files/qca-nss-ecm.defaults new file mode 100644 index 0000000..40a5c4f --- /dev/null +++ b/qca-nss-ecm/files/qca-nss-ecm.defaults @@ -0,0 +1,25 @@ +#!/bin/sh + +# convert old ecm config to new format +uci -q show ecm.general || { + echo "Converting 'ECM' config to new format." + sed -i "s/config.*general.*/config ecm 'general'/g" /etc/config/ecm +} + +uci -q batch << EOF + delete firewall.qcanssecm + set firewall.qcanssecm=include + set firewall.qcanssecm.type=script + set firewall.qcanssecm.path=/etc/firewall.d/qca-nss-ecm + commit firewall +EOF + +grep -q "fw3" /etc/init.d/firewall && { + uci -q batch << EOF + set firewall.qcanssecm.family=any + set firewall.qcanssecm.reload=1 + commit firewall +EOF +} + +exit 0 diff --git a/qca-nss-ecm/files/qca-nss-ecm.firewall b/qca-nss-ecm/files/qca-nss-ecm.firewall new file mode 100644 index 0000000..affbb94 --- /dev/null +++ b/qca-nss-ecm/files/qca-nss-ecm.firewall @@ -0,0 +1,34 @@ +#!/bin/sh + +FW_SCRIPT="/etc/init.d/firewall" + +if grep -q "fw3" "$FW_SCRIPT"; then + if ! iptables -nvL | grep -q "Chain ECM-RATE-LIMIT"; then + iptables -N ECM-RATE-LIMIT + fi + + iptables -F ECM-RATE-LIMIT + iptables -A ECM-RATE-LIMIT --match limit --limit 1000/sec --limit-burst 1000 -j RETURN + iptables -A ECM-RATE-LIMIT -j DROP + iptables -I zone_wan_forward 5 --match conntrack --ctstate NEW -j ECM-RATE-LIMIT + + [ -n "$(command -v ip6tables)" ] && { + if ! ip6tables -nvL | grep -q "Chain ECM-RATE-LIMIT"; then + ip6tables -N ECM-RATE-LIMIT + fi + + ip6tables -F ECM-RATE-LIMIT + ip6tables -A ECM-RATE-LIMIT --match limit --limit 1000/sec --limit-burst 1000 -j RETURN + ip6tables -A ECM-RATE-LIMIT -j DROP + ip6tables -I zone_wan_forward 5 --match conntrack --ctstate NEW -j ECM-RATE-LIMIT + } + +elif grep -q "fw4" "$FW_SCRIPT"; then + if ! nft list chain inet fw4 ecm_rate_limit > /dev/null 2>&1; then + nft add chain inet fw4 ecm_rate_limit + fi + + nft add rule inet fw4 ecm_rate_limit limit rate 1000/second burst 1000 packets counter return + nft add rule inet fw4 ecm_rate_limit counter drop + nft add rule inet fw4 forward_wan ct state new counter jump ecm_rate_limit comment '"!fw4: ECM Rate Limit 1000/pps"' +fi diff --git a/qca-nss-ecm/files/qca-nss-ecm.init b/qca-nss-ecm/files/qca-nss-ecm.init new file mode 100644 index 0000000..8fc3379 --- /dev/null +++ b/qca-nss-ecm/files/qca-nss-ecm.init @@ -0,0 +1,220 @@ +#!/bin/sh /etc/rc.common +# shellcheck disable=3043,3060,2086,2034 +# +# Copyright (c) 2014, 2019-2020 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +# The shebang above has an extra space intentionally to avoid having +# openwrt build scripts automatically enable this package starting +# at boot. + +START=26 +USE_PROCD=1 + +sysctl_update() { + local name value file + + name=${1//\//\\/} + value=${2//\//\\/} + file=${3:-/etc/sysctl.d/qca-nss-ecm.conf} + + if [ -r "/proc/sys/${name//./\/}" ]; then + sed -i -e '/^#\?\(\s*'"${name}"'\s*=\s*\).*/{s//\1'"${value}"'/;:a;n;ba;q}' \ + -e '$a'"${name}"'='"${value}" "${file}" + sysctl -w ${name}=${value} + else + # If the sysctl value is not available but it is found in the file, disable it to avoid + # sysctl throwing warnings + if grep -qE '^#?\s*'"${name}\s*?=" "${file}"; then + sed -i -e '/^#\?\(\s*'"${name}"'\s*=\s*\).*/{s//\#\1'"${value}"'/;:a;n;ba;q}' \ + -e '$a'"#${name}"'='"${value}" "${file}" + fi + fi +} + +get_front_end_mode() { + config_load "ecm" + + config_get front_end global acceleration_engine "auto" + + # shellcheck disable=2154 + case $front_end in + auto) + echo '0' + ;; + nss) + echo '1' + ;; + sfe) + echo '2' + ;; + both) + echo '4' + ;; + *) + echo '0' + ;; + esac +} + +disable_packet_steering() { + uci -q set network.globals.packet_steering=0 && uci commit network.globals.packet_steering + uci -q del network.globals.steering_flows && uci commit network.globals.steering_flows + + if [ -e "/usr/libexec/platform/packet-steering.sh" ]; then + /usr/libexec/platform/packet-steering.sh 0 + else + /usr/libexec/network/packet-steering.uc -l 0 0 + fi +} + +disable_bridge_filtering() { + sysctl_update net.bridge.bridge-nf-call-arptables 0 + sysctl_update net.bridge.bridge-nf-call-iptables 0 + sysctl_update net.bridge.bridge-nf-call-ip6tables 0 +} + +enable_bridge_filtering() { + + # If bridge filtering is enabled, apply and persist the sysctl flags + config_load ecm + config_get enable_bridge_filtering general enable_bridge_filtering 0 + + # shellcheck disable=2154 + if [ "$enable_bridge_filtering" -eq 1 ]; then + sysctl_update net.bridge.bridge-nf-call-arptables 1 + sysctl_update net.bridge.bridge-nf-call-iptables 1 + sysctl_update net.bridge.bridge-nf-call-ip6tables 1 + else + disable_bridge_filtering + fi +} + +set_front_end() { + local get_front_end_mode=${1:-0} + local module_conf=/etc/modules.conf + [ ! -r "$module_conf" ] && touch "$module_conf" + # If "options ecm" exists, modify or append front_end_selection + if grep -q "^options ecm" "$module_conf"; then + if grep -q "front_end_selection=" "$module_conf"; then + sed -i -E "s/(options ecm.*)front_end_selection=[0-9]+/\1front_end_selection=$get_front_end_mode/" "$module_conf" + else + # Append front_end_selection if missing + sed -i -E "s/^(options ecm.*)/\1 front_end_selection=$get_front_end_mode/" "$module_conf" + fi + else + # Add new "options ecm" line + echo "options ecm front_end_selection=$get_front_end_mode" >> "$module_conf" + fi +} + +load_ecm() { + [ -d /sys/module/ecm ] || { + local get_front_end_mode + get_front_end_mode="$(get_front_end_mode)" + modinfo ecm | awk '/depends/{gsub(",","\n",$NF);print $NF}' | xargs -r -n 1 modprobe + set_front_end $get_front_end_mode + modprobe ecm + echo 1 > /sys/kernel/debug/ecm/ecm_classifier_default/accel_delay_pkts + } + + # shellcheck disable=1091 + . /lib/netifd/offload/disable_offloads.sh + + disable_offload + + #Flushout stale accelerated connections if any + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo f > /proc/net/nf_conntrack + + # Set conntrack event mode to 1 for 6.1 kernel to get the conntrack events from ECM + local kernel_major + kernel_major=$(uname -r | cut -d. -f1) + if [ "$kernel_major" -eq 6 ]; then + echo 1 > /proc/sys/net/netfilter/nf_conntrack_events + fi +} + +unload_ecm() { + disable_bridge_filtering + + # Change it back to 6.1 linux's default setting + local kernel_major + kernel_major="$(uname -r | cut -d. -f1)" + if [ "$kernel_major" -eq 6 ]; then + echo 2 > /proc/sys/net/netfilter/nf_conntrack_events + fi + + if [ -d /sys/module/ecm ]; then + # + # Stop ECM frontends + # + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + + # + # Defunct the connections + # + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo f > /proc/net/nf_conntrack + + sleep 1 + rmmod ecm + fi +} + +service_triggers() { + procd_add_reload_trigger "network" + procd_add_reload_trigger "packet_steering" +} + +reload_service() { + disable_packet_steering +} + +start_service() { + load_ecm + + disable_packet_steering + + # Only enable bridge filtering if using deprecated fw3 + if [ ! -r /sbin/fw4 ]; then + enable_bridge_filtering + else + disable_bridge_filtering + fi + + # If the acceleration engine is NSS, enable wifi redirect + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=1 + + if [ -d /sys/module/qca_ovsmgr ]; then + insmod ecm_ovs + fi +} + +stop_service() { + # If ECM is already not loaded, just return + if [ ! -d /sys/module/ecm ]; then + return + fi + + # If the acceleration engine is NSS, disable wifi redirect + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=0 + + if [ -d /sys/module/ecm_ovs ]; then + rmmod ecm_ovs + fi + + unload_ecm +} diff --git a/qca-nss-ecm/files/qca-nss-ecm.sysctl b/qca-nss-ecm/files/qca-nss-ecm.sysctl new file mode 100644 index 0000000..aea077a --- /dev/null +++ b/qca-nss-ecm/files/qca-nss-ecm.sysctl @@ -0,0 +1,3 @@ +# nf_conntrack_tcp_no_window_check is 0 by default, set it to 1 +net.netfilter.nf_conntrack_tcp_no_window_check=1 +net.netfilter.nf_conntrack_max=32768 diff --git a/qca-nss-ecm/files/qca-nss-ecm.uci b/qca-nss-ecm/files/qca-nss-ecm.uci new file mode 100644 index 0000000..d51246d --- /dev/null +++ b/qca-nss-ecm/files/qca-nss-ecm.uci @@ -0,0 +1,9 @@ +config ecm 'global' + option acceleration_engine 'auto' + +config ecm 'general' + option disable_offloads '0' + option disable_flow_control '0' + option disable_interrupt_moderation '0' + option disable_gro '0' + option disable_gro_list '1' diff --git a/qca-nss-ecm/patches/0001-treewide-componentize-the-module-even-more.patch b/qca-nss-ecm/patches/0001-treewide-componentize-the-module-even-more.patch new file mode 100644 index 0000000..a30299b --- /dev/null +++ b/qca-nss-ecm/patches/0001-treewide-componentize-the-module-even-more.patch @@ -0,0 +1,330 @@ +From 09980e54011e2d95a9db2d6134f635bc90e5a7f2 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 19 May 2021 02:38:53 +0200 +Subject: [PATCH 01/12] treewide: componentize the module even more + +Signed-off-by: Ansuel Smith +--- + Makefile | 56 +++++++++++++++++++++++++------- + ecm_db/ecm_db_connection.c | 8 +++++ + ecm_db/ecm_db_node.c | 4 +++ + ecm_interface.c | 8 +++++ + frontends/ecm_front_end_common.c | 7 ++++ + 5 files changed, 72 insertions(+), 11 deletions(-) + +--- a/Makefile ++++ b/Makefile +@@ -4,7 +4,6 @@ + ifeq ($(ECM_FRONT_END_SFE_ENABLE), y) + obj-m += examples/ecm_sfe_l2.o + endif +-obj-m +=examples/ecm_ae_select.o + + obj-m += ecm.o + ifeq ($(BUILD_ECM_WIFI_PLUGIN),y) +@@ -24,6 +23,9 @@ endif + ifeq ($(EXAMPLES_BUILD_OVS),y) + obj-m += examples/ecm_ovs.o + endif ++ifeq ($(EXAMPLES_BUILD_AE),y) ++obj-m +=examples/ecm_ae_select.o ++endif + + ecm-y := \ + frontends/cmn/ecm_ae_classifier.o \ +@@ -115,10 +117,18 @@ ccflags-$(ECM_INTERFACE_BOND_ENABLE) += + # Define ECM_INTERFACE_PPPOE_ENABLE=y in order + # to enable support for PPPoE acceleration. + # ############################################################################# +-ECM_INTERFACE_PPPOE_ENABLE=y ++ifndef $(ECM_INTERFACE_PPPOE_ENABLE) ++ ECM_INTERFACE_PPPOE_ENABLE=y ++endif + ccflags-$(ECM_INTERFACE_PPPOE_ENABLE) += -DECM_INTERFACE_PPPOE_ENABLE + + # ############################################################################# ++# Define ECM_INTERFACE_L2TPV2_PPTP_ENABLE=y in order ++# to enable support for l2tpv2 or PPTP detection. ++# ############################################################################# ++ccflags-$(ECM_INTERFACE_L2TPV2_PPTP_ENABLE) += -DECM_INTERFACE_L2TPV2_PPTP_ENABLE ++ ++# ############################################################################# + # Define ECM_INTERFACE_L2TPV2_ENABLE=y in order + # to enable support for l2tpv2 acceleration. + # ############################################################################# +@@ -151,6 +161,12 @@ endif + ccflags-$(ECM_INTERFACE_PPP_ENABLE) += -DECM_INTERFACE_PPP_ENABLE + + # ############################################################################# ++# Define ECM_INTERFACE_GRE_ENABLE=y in order ++# to enable support for GRE detection. ++# ############################################################################# ++ccflags-$(ECM_INTERFACE_GRE_ENABLE) += -DECM_INTERFACE_GRE_ENABLE ++ ++# ############################################################################# + # Define ECM_INTERFACE_GRE_TAP_ENABLE=y in order + # to enable support for GRE TAP interface. + # ############################################################################# +@@ -233,7 +249,9 @@ ccflags-$(ECM_INTERFACE_OVS_BRIDGE_ENABL + # ############################################################################# + # Define ECM_INTERFACE_VLAN_ENABLE=y in order to enable support for VLAN + # ############################################################################# +-ECM_INTERFACE_VLAN_ENABLE=y ++ifndef $(ECM_INTERFACE_VLAN_ENABLE) ++ ECM_INTERFACE_VLAN_ENABLE=y ++endif + ccflags-$(ECM_INTERFACE_VLAN_ENABLE) += -DECM_INTERFACE_VLAN_ENABLE + + # ############################################################################# +@@ -275,7 +293,9 @@ ccflags-$(ECM_CLASSIFIER_OVS_ENABLE) += + # ############################################################################# + # Define ECM_CLASSIFIER_MARK_ENABLE=y in order to enable mark classifier. + # ############################################################################# +-ECM_CLASSIFIER_MARK_ENABLE=y ++ifndef $(ECM_CLASSIFIER_MARK_ENABLE) ++ ECM_CLASSIFIER_MARK_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_MARK_ENABLE) += ecm_classifier_mark.o + ccflags-$(ECM_CLASSIFIER_MARK_ENABLE) += -DECM_CLASSIFIER_MARK_ENABLE + +@@ -299,7 +319,9 @@ ccflags-$(ECM_CLASSIFIER_NL_ENABLE) += - + # ############################################################################# + # Define ECM_CLASSIFIER_DSCP_ENABLE=y in order to enable DSCP classifier. + # ############################################################################# +-ECM_CLASSIFIER_DSCP_ENABLE=y ++ifndef $(ECM_CLASSIFIER_DSCP_ENABLE) ++ ECM_CLASSIFIER_DSCP_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_DSCP_ENABLE) += ecm_classifier_dscp.o + ccflags-$(ECM_CLASSIFIER_DSCP_ENABLE) += -DECM_CLASSIFIER_DSCP_ENABLE + ccflags-$(ECM_CLASSIFIER_DSCP_IGS) += -DECM_CLASSIFIER_DSCP_IGS +@@ -318,7 +340,9 @@ ccflags-$(ECM_CLASSIFIER_HYFI_ENABLE) += + # the Parental Controls subsystem classifier in ECM. Currently disabled until + # customers require it / if they need to integrate their Parental Controls with it. + # ############################################################################# +-ECM_CLASSIFIER_PCC_ENABLE=y ++ifndef $(ECM_CLASSIFIER_PCC_ENABLE) ++ ECM_CLASSIFIER_PCC_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_PCC_ENABLE) += ecm_classifier_pcc.o + ccflags-$(ECM_CLASSIFIER_PCC_ENABLE) += -DECM_CLASSIFIER_PCC_ENABLE + +@@ -367,27 +391,36 @@ ccflags-$(ECM_NON_PORTED_SUPPORT_ENABLE) + # ############################################################################# + # Define ECM_STATE_OUTPUT_ENABLE=y to support XML state output + # ############################################################################# +-ECM_STATE_OUTPUT_ENABLE=y ++ifndef $(ECM_STATE_OUTPUT_ENABLE) ++ ECM_STATE_OUTPUT_ENABLE=y ++endif + ecm-$(ECM_STATE_OUTPUT_ENABLE) += ecm_state.o + ccflags-$(ECM_STATE_OUTPUT_ENABLE) += -DECM_STATE_OUTPUT_ENABLE + + # ############################################################################# + # Define ECM_DB_ADVANCED_STATS_ENABLE to support XML state output + # ############################################################################# +-ECM_DB_ADVANCED_STATS_ENABLE=y ++ifndef $(ECM_DB_ADVANCED_STATS_ENABLE) ++ ECM_DB_ADVANCED_STATS_ENABLE=y ++endif + ccflags-$(ECM_DB_ADVANCED_STATS_ENABLE) += -DECM_DB_ADVANCED_STATS_ENABLE + + # ############################################################################# + # Define ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y in order to enable + # the database to track relationships between objects. + # ############################################################################# +-ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y ++ifndef $(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) ++ ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y ++endif + ccflags-$(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) += -DECM_DB_XREF_ENABLE + + # ############################################################################# + # Define ECM_TRACKER_DPI_SUPPORT_ENABLE=y in order to enable support for + # deep packet inspection and tracking of data with the trackers. + # ############################################################################# ++ifndef $(ECM_TRACKER_DPI_SUPPORT_ENABLE) ++ ECM_TRACKER_DPI_SUPPORT_ENABLE=y ++endif + ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE) += -DECM_TRACKER_DPI_SUPPORT_ENABLE + + # ############################################################################# +@@ -395,14 +428,18 @@ ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE + # support for the database keeping lists of connections that are assigned + # on a per TYPE of classifier basis. + # ############################################################################# +-ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y ++ifndef $(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) ++ ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y ++endif + ccflags-$(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) += -DECM_DB_CTA_TRACK_ENABLE + + # ############################################################################# + # Define ECM_BAND_STEERING_ENABLE=y in order to enable + # band steering feature. + # ############################################################################# +-ECM_BAND_STEERING_ENABLE=y ++ifndef $(ECM_BAND_STEERING_ENABLE) ++ ECM_BAND_STEERING_ENABLE=y ++endif + ccflags-$(ECM_BAND_STEERING_ENABLE) += -DECM_BAND_STEERING_ENABLE + + # ############################################################################# +--- a/ecm_db/ecm_db_connection.c ++++ b/ecm_db/ecm_db_connection.c +@@ -446,7 +446,9 @@ EXPORT_SYMBOL(ecm_db_connection_make_def + */ + void ecm_db_connection_data_totals_update(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) + { ++#ifdef ECM_DB_ADVANCED_STATS_ENABLE + int32_t i; ++#endif + + DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); + +@@ -1539,6 +1541,7 @@ void ecm_db_connection_defunct_all(void) + } + EXPORT_SYMBOL(ecm_db_connection_defunct_all); + ++#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE + /* + * ecm_db_connection_defunct_by_classifier() + * Make defunct based on masked fields +@@ -1705,6 +1708,7 @@ next_ci: + ECM_IP_ADDR_TO_OCTAL(dest_addr_mask), dest_port_mask, proto_mask, cnt); + } + } ++#endif + + /* + * ecm_db_connection_defunct_by_port() +@@ -1994,6 +1998,7 @@ struct ecm_db_node_instance *ecm_db_conn + } + EXPORT_SYMBOL(ecm_db_connection_node_get_and_ref); + ++#ifdef ECM_DB_XREF_ENABLE + /* + * ecm_db_connection_mapping_get_and_ref_next() + * Return reference to next connection in the mapping chain in the specified direction. +@@ -2035,6 +2040,7 @@ struct ecm_db_connection_instance *ecm_d + return nci; + } + EXPORT_SYMBOL(ecm_db_connection_iface_get_and_ref_next); ++#endif + + /* + * ecm_db_connection_mapping_get_and_ref() +--- a/ecm_db/ecm_db_node.c ++++ b/ecm_db/ecm_db_node.c +@@ -489,9 +489,11 @@ EXPORT_SYMBOL(ecm_db_node_iface_get_and_ + void ecm_db_node_add(struct ecm_db_node_instance *ni, struct ecm_db_iface_instance *ii, uint8_t *address, + ecm_db_node_final_callback_t final, void *arg) + { ++#ifdef ECM_DB_XREF_ENABLE + #if (DEBUG_LEVEL >= 1) + int dir; + #endif ++#endif + ecm_db_node_hash_t hash_index; + struct ecm_db_listener_instance *li; + +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -1525,6 +1525,7 @@ struct neighbour *ecm_interface_ipv6_nei + */ + bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out) + { ++#ifdef ECM_INTERFACE_PPTP_ENABLE + struct net_device *in; + + /* +@@ -1549,6 +1550,7 @@ bool ecm_interface_is_pptp(struct sk_buf + } + + dev_put(in); ++#endif + return false; + } + +@@ -1561,6 +1563,7 @@ bool ecm_interface_is_pptp(struct sk_buf + */ + bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct net_device *out, int ver) + { ++#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE + uint32_t flag = 0; + struct net_device *in; + +@@ -1593,6 +1596,7 @@ bool ecm_interface_is_l2tp_packet_by_ver + } + + dev_put(in); ++#endif + return false; + } + +@@ -1605,6 +1609,7 @@ bool ecm_interface_is_l2tp_packet_by_ver + */ + bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *out) + { ++#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE + struct net_device *in; + + /* +@@ -1627,6 +1632,7 @@ bool ecm_interface_is_l2tp_pptp(struct s + } + + dev_put(in); ++#endif + return false; + } + +@@ -7187,6 +7193,7 @@ static void ecm_interface_regenerate_con + return; + } + ++#ifdef ECM_DB_XREF_ENABLE + for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) { + /* + * Re-generate all connections associated with this interface +@@ -7202,6 +7209,7 @@ static void ecm_interface_regenerate_con + ci[dir] = cin; + } + } ++#endif + + #ifdef ECM_MULTICAST_ENABLE + /* +--- a/frontends/ecm_front_end_common.c ++++ b/frontends/ecm_front_end_common.c +@@ -540,6 +540,7 @@ bool ecm_front_end_gre_proto_is_accel_al + struct nf_conntrack_tuple *reply_tuple, + int ip_version, uint16_t offset) + { ++#ifdef ECM_INTERFACE_GRE_ENABLE + struct net_device *dev; + struct gre_base_hdr *greh; + +@@ -551,10 +552,12 @@ bool ecm_front_end_gre_proto_is_accel_al + /* + * Case 1: PPTP locally terminated + */ ++#ifdef ECM_INTERFACE_PPTP_ENABLE + if (ecm_interface_is_pptp(skb, outdev)) { + DEBUG_TRACE("%px: PPTP GRE locally terminated - allow acceleration\n", skb); + return true; + } ++#endif + + /* + * Case 2: PPTP pass through +@@ -682,6 +685,10 @@ bool ecm_front_end_gre_proto_is_accel_al + */ + DEBUG_TRACE("%px: GRE IPv%d pass through non NAT - allow acceleration\n", skb, ip_version); + return true; ++#else ++ DEBUG_TRACE("%px: GRE%d feature is disabled - do not allow acceleration\n", skb, ip_version); ++ return false; ++#endif + } + + #ifdef ECM_CLASSIFIER_DSCP_ENABLE diff --git a/qca-nss-ecm/patches/0004-qca-nss-ecm-resolve-the-cpu-high-load-regarding-ecm.patch b/qca-nss-ecm/patches/0004-qca-nss-ecm-resolve-the-cpu-high-load-regarding-ecm.patch new file mode 100644 index 0000000..b5f3876 --- /dev/null +++ b/qca-nss-ecm/patches/0004-qca-nss-ecm-resolve-the-cpu-high-load-regarding-ecm.patch @@ -0,0 +1,55 @@ +From 65aa71f33891bcf0b75995219e31abaf674c6199 Mon Sep 17 00:00:00 2001 +From: Dirk Buchwalder +Date: Sun, 27 Jun 2021 16:52:39 +0200 +Subject: [PATCH 05/12] qca-nss-ecm: resolve the cpu high load regarding ecm + +If using ECM, cpu load goes up (around 1.0) and stucks there. +This is due to using uninterruptible sleep function, +the patch changes this to interruptible sleep function. + +Signed-off-by: Dirk Buchwalder buchwalder@posteo.de +--- + frontends/nss/ecm_nss_ipv4.c | 4 ++-- + frontends/nss/ecm_nss_ipv6.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -700,7 +700,7 @@ static void ecm_nss_ipv4_stats_sync_req_ + } + spin_unlock_bh(&ecm_nss_ipv4_lock); + +- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -714,7 +714,7 @@ static void ecm_nss_ipv4_stats_sync_req_ + } + + if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); + } + ecm_nss_ipv4_roll_check_jiffies = jiffies; + ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -676,7 +676,7 @@ static void ecm_nss_ipv6_stats_sync_req_ + } + spin_unlock_bh(&ecm_nss_ipv6_lock); + +- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -690,7 +690,7 @@ static void ecm_nss_ipv6_stats_sync_req_ + } + + if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); + } + ecm_nss_ipv6_roll_check_jiffies = jiffies; + ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; diff --git a/qca-nss-ecm/patches/0006-treewide-rework-notifier-changes-for-5.15.patch b/qca-nss-ecm/patches/0006-treewide-rework-notifier-changes-for-5.15.patch new file mode 100644 index 0000000..f125248 --- /dev/null +++ b/qca-nss-ecm/patches/0006-treewide-rework-notifier-changes-for-5.15.patch @@ -0,0 +1,87 @@ +From 0df0d3ffb4b6df09a28d233925b533de14be6f0e Mon Sep 17 00:00:00 2001 +From: Bit Thief +Date: Tue, 4 Apr 2023 05:22:33 +0300 +Subject: [PATCH] treewide: rework notifier changes for 5.15 + +--- + ecm_conntrack_notifier.c | 35 +++++++++++++++-------------------- + 1 file changed, 15 insertions(+), 20 deletions(-) + +--- a/ecm_conntrack_notifier.c ++++ b/ecm_conntrack_notifier.c +@@ -332,15 +332,8 @@ EXPORT_SYMBOL(ecm_conntrack_ipv4_event); + * ecm_conntrack_event() + * Callback event invoked when conntrack connection state changes, currently we handle destroy events to quickly release state + */ +-#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS +-static int ecm_conntrack_event(struct notifier_block *this, unsigned long events, void *ptr) +-#else +-static int ecm_conntrack_event(unsigned int events, struct nf_ct_event *item) +-#endif ++static int ecm_conntrack_event(unsigned int events, const struct nf_ct_event *item) + { +-#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS +- struct nf_ct_event *item = (struct nf_ct_event *)ptr; +-#endif + struct nf_conn *ct = item->ct; + + /* +@@ -387,23 +380,17 @@ static int ecm_conntrack_event(unsigned + return NOTIFY_DONE; + } + +-#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS +-/* +- * struct notifier_block ecm_conntrack_notifier +- * Netfilter conntrack event system to monitor connection tracking changes +- */ +-static struct notifier_block ecm_conntrack_notifier = { +- .notifier_call = ecm_conntrack_event, +-}; +-#else + /* + * struct nf_ct_event_notifier ecm_conntrack_notifier + * Netfilter conntrack event system to monitor connection tracking changes + */ + static struct nf_ct_event_notifier ecm_conntrack_notifier = { +- .fcn = ecm_conntrack_event, +-}; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) ++ .fcn = ecm_conntrack_event, ++#else ++ .ct_event = ecm_conntrack_event, + #endif ++}; + #endif + + /* +@@ -440,12 +427,16 @@ int ecm_conntrack_notifier_init(struct d + /* + * Eventing subsystem is available so we register a notifier hook to get fast notifications of expired connections + */ +- result = nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) ++ result = nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier); + if (result < 0) { + DEBUG_ERROR("Can't register nf notifier hook.\n"); + debugfs_remove_recursive(ecm_conntrack_notifier_dentry); + return result; + } ++#else ++ nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier); ++#endif + + /* + * Hold netns reference to keep the basic conntrack alive and +@@ -487,7 +478,11 @@ void ecm_conntrack_notifier_exit(void) + #ifdef ECM_IPV6_ENABLE + nf_ct_netns_put(&init_net, NFPROTO_IPV6); + #endif ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) + nf_conntrack_unregister_notifier(&init_net, &ecm_conntrack_notifier); ++#else ++ nf_conntrack_unregister_notifier(&init_net); ++#endif + #endif + /* + * Remove the debugfs files recursively. diff --git a/qca-nss-ecm/patches/0008-ecm_tracker_datagram-drop-static-for-EXPORT_SYMBOL.patch b/qca-nss-ecm/patches/0008-ecm_tracker_datagram-drop-static-for-EXPORT_SYMBOL.patch new file mode 100644 index 0000000..aa3e4d9 --- /dev/null +++ b/qca-nss-ecm/patches/0008-ecm_tracker_datagram-drop-static-for-EXPORT_SYMBOL.patch @@ -0,0 +1,50 @@ +From 9827d8597545ecfee17eba7b08d48dbcdf55c614 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sun, 8 May 2022 18:39:39 +0200 +Subject: [PATCH 09/12] ecm_tracker_datagram: drop static for EXPORT_SYMBOL + +EXPORT_SYMBOL should NOT be static + +Signed-off-by: Ansuel Smith +--- + ecm_tracker_datagram.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/ecm_tracker_datagram.c ++++ b/ecm_tracker_datagram.c +@@ -203,7 +203,7 @@ static void ecm_tracker_datagram_datagra + * ecm_tracker_datagram_discard_all() + * Discard all tracked data + */ +-static void ecm_tracker_datagram_discard_all(struct ecm_tracker_datagram_internal_instance *dtii) ++void ecm_tracker_datagram_discard_all(struct ecm_tracker_datagram_internal_instance *dtii) + { + int32_t src_count; + int32_t dest_count; +@@ -364,7 +364,7 @@ static void ecm_tracker_datagram_datagra + * ecm_tracker_datagram_datagram_size_get() + * Return size in bytes of datagram at index i that was sent to the target + */ +-static int32_t ecm_tracker_datagram_datagram_size_get(struct ecm_tracker_datagram_instance *uti, ecm_tracker_sender_type_t sender, int32_t i) ++int32_t ecm_tracker_datagram_datagram_size_get(struct ecm_tracker_datagram_instance *uti, ecm_tracker_sender_type_t sender, int32_t i) + { + struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)uti; + +@@ -412,7 +412,7 @@ static int32_t ecm_tracker_datagram_data + * ecm_tracker_datagram_datagram_read() + * Read size bytes from datagram at index i into the buffer + */ +-static int ecm_tracker_datagram_datagram_read(struct ecm_tracker_datagram_instance *uti, ecm_tracker_sender_type_t sender, int32_t i, int32_t offset, int32_t size, void *buffer) ++int ecm_tracker_datagram_datagram_read(struct ecm_tracker_datagram_instance *uti, ecm_tracker_sender_type_t sender, int32_t i, int32_t offset, int32_t size, void *buffer) + { + struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)uti; + int res; +@@ -466,7 +466,7 @@ static int ecm_tracker_datagram_datagram + * ecm_tracker_datagram_datagram_add() + * Append the datagram onto the tracker queue for the given target + */ +-static bool ecm_tracker_datagram_datagram_add(struct ecm_tracker_datagram_instance *uti, ecm_tracker_sender_type_t sender, struct sk_buff *skb) ++bool ecm_tracker_datagram_datagram_add(struct ecm_tracker_datagram_instance *uti, ecm_tracker_sender_type_t sender, struct sk_buff *skb) + { + struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)uti; + struct sk_buff *skbc; diff --git a/qca-nss-ecm/patches/0009-frontends-drop-udp_get_timeouts-and-use-standard-ups.patch b/qca-nss-ecm/patches/0009-frontends-drop-udp_get_timeouts-and-use-standard-ups.patch new file mode 100644 index 0000000..f86f6d2 --- /dev/null +++ b/qca-nss-ecm/patches/0009-frontends-drop-udp_get_timeouts-and-use-standard-ups.patch @@ -0,0 +1,63 @@ +From ef638a84405c9f6556a9d7c257ccbba74efd228e Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 14 May 2022 20:15:10 +0200 +Subject: [PATCH 10/12] frontends: drop udp_get_timeouts and use standard + upstream api + +Drop udp_get_timeouts and use nf_udp_pernet and ->timeouts +instead or relying on a downstream api not present upstream. +--- + frontends/nss/ecm_nss_ipv4.c | 3 ++- + frontends/nss/ecm_nss_ipv6.c | 3 ++- + frontends/sfe/ecm_sfe_ipv4.c | 3 ++- + frontends/sfe/ecm_sfe_ipv6.c | 3 ++- + 4 files changed, 8 insertions(+), 4 deletions(-) + +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -610,7 +610,8 @@ sync_conntrack: + #else + timeouts = nf_ct_timeout_lookup(ct); + if (!timeouts) { +- timeouts = udp_get_timeouts(nf_ct_net(ct)); ++ struct nf_udp_net *un = nf_udp_pernet(nf_ct_net(ct)); ++ timeouts = un->timeouts; + } + + spin_lock_bh(&ct->lock); +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -587,7 +587,8 @@ sync_conntrack: + #else + timeouts = nf_ct_timeout_lookup(ct); + if (!timeouts) { +- timeouts = udp_get_timeouts(nf_ct_net(ct)); ++ struct nf_udp_net *un = nf_udp_pernet(nf_ct_net(ct)); ++ timeouts = un->timeouts; + } + + spin_lock_bh(&ct->lock); +--- a/frontends/sfe/ecm_sfe_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ipv4.c +@@ -574,7 +574,8 @@ sync_conntrack: + #else + timeouts = nf_ct_timeout_lookup(ct); + if (!timeouts) { +- timeouts = udp_get_timeouts(nf_ct_net(ct)); ++ struct nf_udp_net *un = nf_udp_pernet(nf_ct_net(ct)); ++ timeouts = un->timeouts; + } + + spin_lock_bh(&ct->lock); +--- a/frontends/sfe/ecm_sfe_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ipv6.c +@@ -567,7 +567,8 @@ sync_conntrack: + #else + timeouts = nf_ct_timeout_lookup(ct); + if (!timeouts) { +- timeouts = udp_get_timeouts(nf_ct_net(ct)); ++ struct nf_udp_net *un = nf_udp_pernet(nf_ct_net(ct)); ++ timeouts = un->timeouts; + } + + spin_lock_bh(&ct->lock); diff --git a/qca-nss-ecm/patches/0010-ecm_interface-fix-ppp-generic-function-calls-for-5.15.patch b/qca-nss-ecm/patches/0010-ecm_interface-fix-ppp-generic-function-calls-for-5.15.patch new file mode 100644 index 0000000..27238cc --- /dev/null +++ b/qca-nss-ecm/patches/0010-ecm_interface-fix-ppp-generic-function-calls-for-5.15.patch @@ -0,0 +1,20 @@ +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -3640,7 +3640,7 @@ identifier_update: + if (skb && (skb->skb_iif == dev->ifindex)) { + struct pppol2tp_common_addr info; + +- if (__ppp_is_multilink(dev) > 0) { ++ if (ppp_is_multilink(dev) > 0) { + DEBUG_TRACE("%px: Net device: %px is MULTILINK PPP - Unknown to the ECM\n", feci, dev); + type_info.unknown.os_specific_ident = dev_interface_num; + +@@ -3650,7 +3650,7 @@ identifier_update: + ii = ecm_interface_unknown_interface_establish(&type_info.unknown, dev_name, dev_interface_num, ae_interface_num, dev_mtu); + return ii; + } +- channel_count = __ppp_hold_channels(dev, ppp_chan, 1); ++ channel_count = ppp_hold_channels(dev, ppp_chan, 1); + if (channel_count != 1) { + DEBUG_TRACE("%px: Net device: %px PPP has %d channels - ECM cannot handle this (interface becomes Unknown type)\n", + feci, dev, channel_count); diff --git a/qca-nss-ecm/patches/0011-ecm_classifier-move-defs.patch b/qca-nss-ecm/patches/0011-ecm_classifier-move-defs.patch new file mode 100644 index 0000000..9f01a8d --- /dev/null +++ b/qca-nss-ecm/patches/0011-ecm_classifier-move-defs.patch @@ -0,0 +1,22 @@ +--- a/ecm_classifier_mscs.c ++++ b/ecm_classifier_mscs.c +@@ -429,7 +429,6 @@ static void ecm_classifier_mscs_process( + struct ecm_db_connection_instance *ci = NULL; + struct ecm_front_end_connection_instance *feci; + ecm_front_end_acceleration_mode_t accel_mode; +- int protocol; + uint32_t became_relevant = 0; + ecm_classifier_mscs_process_callback_t cb = NULL; + bool scs_result = false; +@@ -441,10 +440,10 @@ static void ecm_classifier_mscs_process( + struct net_device *src_dev = NULL; + struct net_device *dest_dev = NULL; + uint64_t slow_pkts; ++ struct ecm_classifier_mscs_get_priority_info get_priority_info = {0}; + #ifdef ECM_CLASSIFIER_MSCS_SCS_ENABLE + struct sp_rule_input_params flow_input_params; + struct sp_rule_output_params flow_output_params; +- struct ecm_classifier_mscs_get_priority_info get_priority_info = {0}; + struct ecm_classifier_mscs_rule_match_info rule_match_info = {0}; + ecm_classifier_mscs_scs_priority_callback_t scs_cb = NULL; + #endif diff --git a/qca-nss-ecm/patches/0012-ecm_add-check-for-pppoe.patch b/qca-nss-ecm/patches/0012-ecm_add-check-for-pppoe.patch new file mode 100644 index 0000000..ac83029 --- /dev/null +++ b/qca-nss-ecm/patches/0012-ecm_add-check-for-pppoe.patch @@ -0,0 +1,42 @@ +--- a/frontends/include/ecm_front_end_common.h ++++ b/frontends/include/ecm_front_end_common.h +@@ -339,15 +339,19 @@ static inline bool ecm_front_end_ppppoe_ + fe_type = ecm_front_end_type_get(); + switch (fe_type) { + #ifdef ECM_FRONT_END_NSS_ENABLE ++#ifdef ECM_INTERFACE_PPPOE_ENABLE + case ECM_FRONT_END_TYPE_NSS: + ret = (nss_pppoe_get_br_accel_mode() == NSS_PPPOE_BR_ACCEL_MODE_DIS); + break; + #endif ++#endif + #ifdef ECM_FRONT_END_SFE_ENABLE ++#ifdef ECM_INTERFACE_PPPOE_ENABLE + case ECM_FRONT_END_TYPE_SFE: + ret = (sfe_pppoe_get_br_accel_mode() == SFE_PPPOE_BR_ACCEL_MODE_DISABLED); + break; + #endif ++#endif + default: + DEBUG_TRACE("front end type: %d\n", fe_type); + break; +@@ -369,15 +373,19 @@ static inline bool ecm_front_end_ppppoe_ + fe_type = ecm_front_end_type_get(); + switch (fe_type) { + #ifdef ECM_FRONT_END_NSS_ENABLE ++#ifdef ECM_INTERFACE_PPPOE_ENABLE + case ECM_FRONT_END_TYPE_NSS: + ret = (nss_pppoe_get_br_accel_mode() == NSS_PPPOE_BR_ACCEL_MODE_EN_3T); + break; + #endif ++#endif + #ifdef ECM_FRONT_END_SFE_ENABLE ++#ifdef ECM_INTERFACE_PPPOE_ENABLE + case ECM_FRONT_END_TYPE_SFE: + ret = (sfe_pppoe_get_br_accel_mode() == SFE_PPPOE_BR_ACCEL_MODE_EN_3T); + break; + #endif ++#endif + default: + DEBUG_WARN("front end type: %d is not supported\n", fe_type); + break; diff --git a/qca-nss-ecm/patches/0013-treewide-export-ipv4-and-ipv6-symbols.patch b/qca-nss-ecm/patches/0013-treewide-export-ipv4-and-ipv6-symbols.patch new file mode 100644 index 0000000..30ec513 --- /dev/null +++ b/qca-nss-ecm/patches/0013-treewide-export-ipv4-and-ipv6-symbols.patch @@ -0,0 +1,99 @@ +--- a/frontends/nss/ecm_nss_common.c ++++ b/frontends/nss/ecm_nss_common.c +@@ -67,6 +67,7 @@ bool ecm_nss_ipv6_is_conn_limit_reached( + + return false; + } ++EXPORT_SYMBOL(ecm_nss_ipv6_is_conn_limit_reached); + #endif + + /* +@@ -116,3 +117,4 @@ bool ecm_nss_ipv4_is_conn_limit_reached( + + return false; + } ++EXPORT_SYMBOL(ecm_nss_ipv4_is_conn_limit_reached); +--- a/frontends/nss/ecm_nss_non_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv4.c +@@ -1847,6 +1847,7 @@ struct ecm_front_end_connection_instance + + return feci; + } ++EXPORT_SYMBOL(ecm_nss_non_ported_ipv4_connection_instance_alloc); + + /* + * ecm_nss_non_ported_ipv4_debugfs_init() +--- a/frontends/nss/ecm_nss_non_ported_ipv4.h ++++ b/frontends/nss/ecm_nss_non_ported_ipv4.h +@@ -19,7 +19,7 @@ + + extern bool ecm_nss_non_ported_ipv4_debugfs_init(struct dentry *dentry); + +-extern struct ecm_front_end_connection_instance *ecm_nss_non_ported_ipv4_connection_instance_alloc( ++struct ecm_front_end_connection_instance *ecm_nss_non_ported_ipv4_connection_instance_alloc( + uint32_t accel_flags, + int protocol, + struct ecm_db_connection_instance **nci); +--- a/frontends/nss/ecm_nss_non_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv6.c +@@ -1657,6 +1657,7 @@ struct ecm_front_end_connection_instance + + return feci; + } ++EXPORT_SYMBOL(ecm_nss_non_ported_ipv6_connection_instance_alloc); + + /* + * ecm_nss_non_ported_ipv6_debugfs_init() +--- a/frontends/nss/ecm_nss_non_ported_ipv6.h ++++ b/frontends/nss/ecm_nss_non_ported_ipv6.h +@@ -19,7 +19,7 @@ + + extern bool ecm_nss_non_ported_ipv6_debugfs_init(struct dentry *dentry); + +-extern struct ecm_front_end_connection_instance *ecm_nss_non_ported_ipv6_connection_instance_alloc( ++struct ecm_front_end_connection_instance *ecm_nss_non_ported_ipv6_connection_instance_alloc( + uint32_t accel_flags, + int protocol, + struct ecm_db_connection_instance **nci); +--- a/frontends/nss/ecm_nss_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_ported_ipv4.c +@@ -1906,6 +1906,7 @@ struct ecm_front_end_connection_instance + + return feci; + } ++EXPORT_SYMBOL(ecm_nss_ported_ipv4_connection_instance_alloc); + + /* + * ecm_nss_ported_ipv4_debugfs_init() +--- a/frontends/nss/ecm_nss_ported_ipv4.h ++++ b/frontends/nss/ecm_nss_ported_ipv4.h +@@ -19,7 +19,7 @@ + + extern bool ecm_nss_ported_ipv4_debugfs_init(struct dentry *dentry); + +-extern struct ecm_front_end_connection_instance *ecm_nss_ported_ipv4_connection_instance_alloc( ++struct ecm_front_end_connection_instance *ecm_nss_ported_ipv4_connection_instance_alloc( + uint32_t accel_flags, + int protocol, + struct ecm_db_connection_instance **nci); +--- a/frontends/nss/ecm_nss_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_ported_ipv6.c +@@ -1812,6 +1812,7 @@ struct ecm_front_end_connection_instance + + return feci; + } ++EXPORT_SYMBOL(ecm_nss_ported_ipv6_connection_instance_alloc); + + /* + * ecm_nss_ported_ipv6_debugfs_init() +--- a/frontends/nss/ecm_nss_ported_ipv6.h ++++ b/frontends/nss/ecm_nss_ported_ipv6.h +@@ -19,7 +19,7 @@ + + extern bool ecm_nss_ported_ipv6_debugfs_init(struct dentry *dentry); + +-extern struct ecm_front_end_connection_instance *ecm_nss_ported_ipv6_connection_instance_alloc( ++struct ecm_front_end_connection_instance *ecm_nss_ported_ipv6_connection_instance_alloc( + uint32_t accel_flags, + int protocol, + struct ecm_db_connection_instance **nci); diff --git a/qca-nss-ecm/patches/0015-ecm-add-support-for-kernel-6.6.patch b/qca-nss-ecm/patches/0015-ecm-add-support-for-kernel-6.6.patch new file mode 100644 index 0000000..478210c --- /dev/null +++ b/qca-nss-ecm/patches/0015-ecm-add-support-for-kernel-6.6.patch @@ -0,0 +1,14 @@ +--- a/frontends/nss/ecm_nss_common.h ++++ b/frontends/nss/ecm_nss_common.h +@@ -277,8 +277,10 @@ static inline bool ecm_nss_common_igs_ac + */ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)) + if (likely(!(to_dev->ingress_cl_list))) { +-#else ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(6, 6, 0)) + if (likely(!(to_dev->miniq_ingress))) { ++#else ++ if (likely(!(to_dev->tcx_ingress))) { + #endif + dev_put(to_dev); + continue; diff --git a/qca-nss-ecm/patches/0016-ecm-conditionally-check-mlo-device.patch b/qca-nss-ecm/patches/0016-ecm-conditionally-check-mlo-device.patch new file mode 100644 index 0000000..d352982 --- /dev/null +++ b/qca-nss-ecm/patches/0016-ecm-conditionally-check-mlo-device.patch @@ -0,0 +1,14 @@ +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -4057,7 +4057,11 @@ static uint32_t ecm_interface_multicast_ + * For MLO bond netdevice, destination for multicast is bond netdevice itself + * Therefore, slave lookup is not needed. + */ ++#ifdef ECM_FRONT_END_SFE_ENABLE + if (ecm_front_end_is_lag_master(dest_dev) && !bond_is_mlo_device(dest_dev)) { ++#else ++ if (ecm_front_end_is_lag_master(dest_dev)) { ++#endif + /* + * Link aggregation + * Figure out which slave device of the link aggregation will be used to reach the destination. diff --git a/qca-nss-ecm/patches/0017-ecm-interface-fix-fortify_memcpy_chk.patch b/qca-nss-ecm/patches/0017-ecm-interface-fix-fortify_memcpy_chk.patch new file mode 100644 index 0000000..a6e8652 --- /dev/null +++ b/qca-nss-ecm/patches/0017-ecm-interface-fix-fortify_memcpy_chk.patch @@ -0,0 +1,53 @@ +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -8014,7 +8014,7 @@ static int ecm_interface_wifi_event_iwev + /* + * Copy the base data structure to get iwe->len + */ +- memcpy(&iwe_buf, pos, IW_EV_LCP_LEN); ++ memcpy(&iwe_buf, pos, min_t(size_t, IW_EV_LCP_LEN, (size_t)(end - pos))); + + /* + * Check that len is valid and that we have that much in the buffer. +@@ -8031,10 +8031,10 @@ static int ecm_interface_wifi_event_iwev + dpos = (char *)&iwe_buf.u.data.length; + dlen = dpos - (char *)&iwe_buf; + +- memcpy(dpos, pos + IW_EV_LCP_LEN, sizeof(struct iw_event) - dlen); ++ memcpy(dpos, pos + IW_EV_LCP_LEN, min_t(size_t, sizeof(struct iw_event) - dlen, (size_t)(end - pos - IW_EV_LCP_LEN))); + + if (custom + iwe->u.data.length > end) { +- DEBUG_WARN("Invalid buffer length received in the event iwe->u.data.length %d\n", iwe->u.data.length); ++ DEBUG_WARN("Invalid buffer length received in the event iwe->u.data.length %d\n", (int)iwe->u.data.length); + return -1; + } + +@@ -8042,7 +8042,7 @@ static int ecm_interface_wifi_event_iwev + * Check the flags of iw event if it indicates the IW authorized signal. + */ + if (iwe->u.data.flags == ECM_INTERFACE_WIFI_EVENT_NODE_AUTH) { +- dbuf = kzalloc((iwe->u.data.length + 1), GFP_KERNEL); ++ dbuf = kzalloc(iwe->u.data.length, GFP_KERNEL); + if (!dbuf) { + DEBUG_WARN("Failed to allocated a buffer to process the custom event"); + return -1; +@@ -8065,16 +8065,16 @@ static int ecm_interface_wifi_event_iwev + return 0; + } + +- if ((iwe->len > sizeof(struct iw_event)) || (iwe->len + pos) > end) { ++ if ((iwe->len > sizeof(struct iw_event)) || (iwe->len + pos > end)) { + return -1; + } + + /* + * Do the copy again with the full length. + */ +- memcpy(&iwe_buf, pos, iwe->len); ++ memcpy(&iwe_buf, pos, min_t(size_t, iwe->len, (size_t)(end - pos))); + +- if (iwe->cmd == IWEVEXPIRED) { ++ if (iwe->cmd == IWEVEXPIRED && iwe->len >= sizeof(struct iw_event)) { + DEBUG_INFO("STA %pM leaving\n", (uint8_t *)iwe->u.addr.sa_data); + ecm_interface_node_connections_defunct((uint8_t *)iwe->u.addr.sa_data, ECM_DB_IP_VERSION_IGNORE); + } else { diff --git a/qca-nss-ecm/patches/0018-ecm-compat-nss-12_5.patch b/qca-nss-ecm/patches/0018-ecm-compat-nss-12_5.patch new file mode 100644 index 0000000..4f281a3 --- /dev/null +++ b/qca-nss-ecm/patches/0018-ecm-compat-nss-12_5.patch @@ -0,0 +1,34 @@ +--- a/frontends/nss/ecm_nss_non_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv4.c +@@ -854,6 +854,7 @@ static void ecm_nss_non_ported_ipv4_conn + DEBUG_TRACE("%px: PPTP - unsupported\n", feci); + #endif + break; ++#ifdef NSS_FIRMWARE_VERSION_12_5 + case ECM_DB_IFACE_TYPE_RAWIP: + #ifdef ECM_INTERFACE_RAWIP_ENABLE + nircm->valid_flags |= NSS_IPV4_RULE_CREATE_RAWIP_VALID; +@@ -862,6 +863,7 @@ static void ecm_nss_non_ported_ipv4_conn + DEBUG_TRACE("%px: RAWIP - unsupported\n", feci); + #endif + break; ++#endif + default: + DEBUG_TRACE("%px: Ignoring: %d (%s)\n", feci, ii_type, ii_name); + } +@@ -1071,6 +1073,7 @@ static void ecm_nss_non_ported_ipv4_conn + DEBUG_TRACE("%px: IPSEC - unsupported\n", feci); + #endif + break; ++#ifdef NSS_FIRMWARE_VERSION_12_5 + case ECM_DB_IFACE_TYPE_RAWIP: + #ifdef ECM_INTERFACE_RAWIP_ENABLE + nircm->valid_flags |= NSS_IPV4_RULE_CREATE_RAWIP_VALID; +@@ -1079,6 +1082,7 @@ static void ecm_nss_non_ported_ipv4_conn + DEBUG_TRACE("%px: RAWIP - unsupported\n", feci); + #endif + break; ++#endif + default: + DEBUG_TRACE("%px: Ignoring: %d (%s)\n", feci, ii_type, ii_name); + } diff --git a/qca-nss-ecm/patches/0020-remove-check-mlo-device.patch b/qca-nss-ecm/patches/0020-remove-check-mlo-device.patch new file mode 100644 index 0000000..696e05c --- /dev/null +++ b/qca-nss-ecm/patches/0020-remove-check-mlo-device.patch @@ -0,0 +1,14 @@ +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -4057,11 +4057,7 @@ static uint32_t ecm_interface_multicast_ + * For MLO bond netdevice, destination for multicast is bond netdevice itself + * Therefore, slave lookup is not needed. + */ +-#ifdef ECM_FRONT_END_SFE_ENABLE +- if (ecm_front_end_is_lag_master(dest_dev) && !bond_is_mlo_device(dest_dev)) { +-#else + if (ecm_front_end_is_lag_master(dest_dev)) { +-#endif + /* + * Link aggregation + * Figure out which slave device of the link aggregation will be used to reach the destination. diff --git a/qca-nss-ecm/patches/0021-fix-read-write-tcp-udp-denied-ports.patch b/qca-nss-ecm/patches/0021-fix-read-write-tcp-udp-denied-ports.patch new file mode 100644 index 0000000..0997647 --- /dev/null +++ b/qca-nss-ecm/patches/0021-fix-read-write-tcp-udp-denied-ports.patch @@ -0,0 +1,79 @@ +--- a/frontends/ecm_front_end_common.c ++++ b/frontends/ecm_front_end_common.c +@@ -860,7 +860,7 @@ uint64_t ecm_front_end_get_slow_packet_c + * ecm_front_end_ppe_fse_enable_limit_handler() + * Sysctl to enable/disable FSE programming through PPE. + */ +-int ecm_front_end_ppe_fse_enable_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++int ecm_front_end_ppe_fse_enable_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + +@@ -895,7 +895,7 @@ int ecm_front_end_ppe_fse_enable_handler + * ecm_front_end_db_conn_limit_handler() + * Database connection limit sysctl node handler. + */ +-int ecm_front_end_db_conn_limit_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++int ecm_front_end_db_conn_limit_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + int ret; + int current_value; +@@ -930,7 +930,7 @@ int ecm_front_end_db_conn_limit_handler( + * ecm_front_end_denied_ports_read() + * Reads the denied ports from the denied ports array and prints. + */ +-static void ecm_front_end_denied_ports_read(void __user *buffer, size_t *lenp, loff_t *ppos, struct hlist_head *denied_ports) ++static void ecm_front_end_denied_ports_read(void *buffer, size_t *lenp, loff_t *ppos, struct hlist_head *denied_ports) + { + char *read_buf; + int i, len; +@@ -966,7 +966,7 @@ static void ecm_front_end_denied_ports_r + len = scnprintf(read_buf + bytes, 4, "\n"); + bytes += len; + +- bytes = simple_read_from_buffer(buffer, *lenp, ppos, read_buf, bytes); ++ bytes = memory_read_from_buffer(buffer, *lenp, ppos, read_buf, bytes); + *lenp = bytes; + kfree(read_buf); + } +@@ -993,7 +993,7 @@ static inline bool ecm_front_end_is_port + * ecm_front_end_denied_ports_handler() + * Proc handler function for denied ports read/write operation. + */ +-static int ecm_front_end_denied_ports_handler(int write, void __user *buffer, size_t *lenp, loff_t *ppos, struct hlist_head *denied_ports, bool is_udp) ++static int ecm_front_end_denied_ports_handler(int write, void *buffer, size_t *lenp, loff_t *ppos, struct hlist_head *denied_ports, bool is_udp) + { + + char *buf; +@@ -1018,10 +1018,9 @@ static int ecm_front_end_denied_ports_ha + count = ECM_FRONT_END_DENIED_PORTS_HTABLE_SIZE * 8 * sizeof(char); + } + +- if (copy_from_user(buf, buffer, count)) { +- kfree(pfree); +- return -EFAULT; +- } ++ memcpy(buf, buffer, count); ++ *lenp = count; ++ *ppos += count; + + token = strsep(&buf, " "); + if (strlen(token) != 3) { +@@ -1115,7 +1114,7 @@ static int ecm_front_end_denied_ports_ha + * ecm_front_end_udp_denied_ports_handler() + * Proc handler function for UDP denied ports read/write operation. + */ +-static int ecm_front_end_udp_denied_ports_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int ecm_front_end_udp_denied_ports_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + /* + * Usage: +@@ -1135,7 +1134,7 @@ static int ecm_front_end_udp_denied_port + * ecm_front_end_tcp_denied_ports_handler() + * Proc handler function for TCP denied ports read/write operation. + */ +-static int ecm_front_end_tcp_denied_ports_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++static int ecm_front_end_tcp_denied_ports_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) + { + /* + * Usage: diff --git a/qca-nss-ecm/patches/0022-fix-undefined-dev-for-tunipip6.patch b/qca-nss-ecm/patches/0022-fix-undefined-dev-for-tunipip6.patch new file mode 100644 index 0000000..fd9cb12 --- /dev/null +++ b/qca-nss-ecm/patches/0022-fix-undefined-dev-for-tunipip6.patch @@ -0,0 +1,11 @@ +--- a/frontends/nss/ecm_nss_non_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv6.c +@@ -342,7 +342,7 @@ static void ecm_nss_non_ported_ipv6_conn + ip_addr_t src_ip; + ip_addr_t dest_ip; + ecm_front_end_acceleration_mode_t result_mode; +-#if defined(ECM_INTERFACE_GRE_TAP_ENABLE) || defined(ECM_INTERFACE_GRE_TUN_ENABLE) ++#if defined(ECM_INTERFACE_GRE_TAP_ENABLE) || defined(ECM_INTERFACE_GRE_TUN_ENABLE) || defined(ECM_INTERFACE_TUNIPIP6_ENABLE) + struct net_device *dev; + #endif + diff --git a/qca-nss-ecm/patches/0023-nss-ecm-add-kernel-6.12-support.patch b/qca-nss-ecm/patches/0023-nss-ecm-add-kernel-6.12-support.patch new file mode 100644 index 0000000..c970408 --- /dev/null +++ b/qca-nss-ecm/patches/0023-nss-ecm-add-kernel-6.12-support.patch @@ -0,0 +1,482 @@ +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -1278,7 +1278,11 @@ static bool ecm_interface_find_route_by_ + * it is using to communicate with that IP address. + */ + ECM_IP_ADDR_TO_NIN4_ADDR(be_addr, addr); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) + ecm_rt->rt.rtv4 = ip_route_output(&init_net, be_addr, 0, 0, 0); ++#else ++ ecm_rt->rt.rtv4 = ip_route_output(&init_net, be_addr, 0, 0, 0, 0); ++#endif + if (IS_ERR(ecm_rt->rt.rtv4)) { + DEBUG_TRACE("No output route to: %pI4n\n", &be_addr); + return false; +@@ -1469,7 +1473,11 @@ struct neighbour *ecm_interface_ipv4_nei + __be32 ipv4_addr; + + ECM_IP_ADDR_TO_NIN4_ADDR(ipv4_addr, addr); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) + rt = ip_route_output(&init_net, ipv4_addr, 0, 0, 0); ++#else ++ rt = ip_route_output(&init_net, ipv4_addr, 0, 0, 0, 0); ++#endif + if (IS_ERR(rt)) { + return NULL; + } +@@ -8274,8 +8282,13 @@ int ecm_interface_wifi_event_stop(void) + * ecm_interface_igs_enabled_handler() + * IGS enabled check sysctl node handler. + */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) + static int ecm_interface_igs_enabled_handler(struct ctl_table *ctl, int write, void __user *buffer, + size_t *lenp, loff_t *ppos) ++#else ++static int ecm_interface_igs_enabled_handler(const struct ctl_table *ctl, int write, void __user *buffer, ++ size_t *lenp, loff_t *ppos) ++#endif + { + int ret; + int current_value; +@@ -8315,7 +8328,11 @@ static int ecm_interface_igs_enabled_han + * ecm_interface_src_check_handler() + * Source interface check sysctl node handler. + */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) + static int ecm_interface_src_check_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++#else ++static int ecm_interface_src_check_handler(const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++#endif + { + int ret; + int current_value; +@@ -8369,7 +8386,6 @@ static struct ctl_table ecm_interface_ta + .proc_handler = &ecm_interface_igs_enabled_handler, + }, + #endif +- { } + }; + + #ifdef ECM_INTERFACE_IPSEC_GLUE_LAYER_SUPPORT_ENABLE +--- a/ecm_db/ecm_db_connection.c ++++ b/ecm_db/ecm_db_connection.c +@@ -698,7 +698,7 @@ EXPORT_SYMBOL(ecm_db_connection_node_add + void ecm_db_connection_iface_name_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir, char *name_buffer) + { + DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci); +- strlcpy(name_buffer, ci->node[dir]->iface->name, IFNAMSIZ); ++ strscpy(name_buffer, ci->node[dir]->iface->name, IFNAMSIZ); + } + EXPORT_SYMBOL(ecm_db_connection_iface_name_get); + +--- a/ecm_db/ecm_db_iface.c ++++ b/ecm_db/ecm_db_iface.c +@@ -247,7 +247,7 @@ static int ecm_db_iface_state_get_base(s + interface_identifier = ii->interface_identifier; + ae_interface_identifier = ii->ae_interface_identifier; + spin_lock_bh(&ecm_db_lock); +- strlcpy(name, ii->name, IFNAMSIZ); ++ strscpy(name, ii->name, IFNAMSIZ); + mtu = ii->mtu; + spin_unlock_bh(&ecm_db_lock); + +@@ -1178,7 +1178,7 @@ void ecm_db_iface_interface_name_get(str + { + DEBUG_CHECK_MAGIC(ii, + ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii); +- strlcpy(name_buffer, ii->name, IFNAMSIZ); ++ strscpy(name_buffer, ii->name, IFNAMSIZ); + } + EXPORT_SYMBOL(ecm_db_iface_interface_name_get); + +@@ -2708,7 +2708,7 @@ void ecm_db_iface_add_ethernet(struct ec + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -2760,7 +2760,7 @@ void ecm_db_iface_add_lag(struct ecm_db_ + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -2811,7 +2811,7 @@ void ecm_db_iface_add_bridge(struct ecm_ + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -2862,7 +2862,7 @@ void ecm_db_iface_add_ovs_bridge(struct + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -2913,7 +2913,7 @@ void ecm_db_iface_add_macvlan(struct ecm + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -2964,7 +2964,7 @@ void ecm_db_iface_add_vlan(struct ecm_db + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -3018,7 +3018,7 @@ void ecm_db_iface_add_map_t(struct ecm_d + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -3070,7 +3070,7 @@ void ecm_db_iface_add_gre_tun(struct ecm + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -3122,7 +3122,7 @@ void ecm_db_iface_add_pppoe(struct ecm_d + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -3175,7 +3175,7 @@ void ecm_db_iface_add_pppol2tpv2(struct + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -3228,7 +3228,7 @@ void ecm_db_iface_add_pptp(struct ecm_db + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -3278,7 +3278,7 @@ void ecm_db_iface_add_unknown(struct ecm + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -3327,7 +3327,7 @@ void ecm_db_iface_add_loopback(struct ec + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -3386,7 +3386,7 @@ void ecm_db_iface_add_sit(struct ecm_db_ + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -3436,7 +3436,7 @@ void ecm_db_iface_add_tunipip6(struct ec + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -3489,7 +3489,7 @@ void ecm_db_iface_add_ipsec_tunnel(struc + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -3541,7 +3541,7 @@ void ecm_db_iface_add_rawip(struct ecm_d + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +@@ -3592,7 +3592,7 @@ void ecm_db_iface_add_ovpn(struct ecm_db + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = type_info->tun_ifnum; +@@ -3643,7 +3643,7 @@ void ecm_db_iface_add_vxlan(struct ecm_d + #endif + ii->arg = arg; + ii->final = final; +- strlcpy(ii->name, name, IFNAMSIZ); ++ strscpy(ii->name, name, IFNAMSIZ); + ii->mtu = mtu; + ii->interface_identifier = interface_identifier; + ii->ae_interface_identifier = ae_interface_identifier; +--- a/frontends/ecm_front_end_common.c ++++ b/frontends/ecm_front_end_common.c +@@ -18,6 +18,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -895,7 +896,11 @@ int ecm_front_end_ppe_fse_enable_handler + * ecm_front_end_db_conn_limit_handler() + * Database connection limit sysctl node handler. + */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) + int ecm_front_end_db_conn_limit_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++#else ++int ecm_front_end_db_conn_limit_handler(const struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++#endif + { + int ret; + int current_value; +@@ -1114,7 +1119,11 @@ static int ecm_front_end_denied_ports_ha + * ecm_front_end_udp_denied_ports_handler() + * Proc handler function for UDP denied ports read/write operation. + */ +-static int ecm_front_end_udp_denied_ports_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) ++int ecm_front_end_udp_denied_ports_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++#else ++int ecm_front_end_udp_denied_ports_handler(const struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++#endif + { + /* + * Usage: +@@ -1134,7 +1143,11 @@ static int ecm_front_end_udp_denied_port + * ecm_front_end_tcp_denied_ports_handler() + * Proc handler function for TCP denied ports read/write operation. + */ +-static int ecm_front_end_tcp_denied_ports_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) ++int ecm_front_end_tcp_denied_ports_handler(struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++#else ++int ecm_front_end_tcp_denied_ports_handler(const struct ctl_table *ctl, int write, void *buffer, size_t *lenp, loff_t *ppos) ++#endif + { + /* + * Usage: +@@ -1181,7 +1194,6 @@ static struct ctl_table ecm_front_end_sy + .mode = 0644, + .proc_handler = &ecm_front_end_tcp_denied_ports_handler, + }, +- {} + }; + + /* +--- a/frontends/sfe/ecm_sfe_common.c ++++ b/frontends/sfe/ecm_sfe_common.c +@@ -308,7 +308,11 @@ void ecm_sfe_common_fast_xmit_set(uint32 + * ecm_sfe_fast_xmit_enable_handler() + * Fast transmit sysctl node handler. + */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) + int ecm_sfe_fast_xmit_enable_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++#else ++int ecm_sfe_fast_xmit_enable_handler(const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++#endif + { + int ret; + +@@ -332,7 +336,11 @@ int ecm_sfe_fast_xmit_enable_handler(str + * ecm_sfe_fse_enable_handler() + * Sysctl to enable/disable FSE programming through ECM SFE frontend. + */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 10, 0) + int ecm_sfe_fse_enable_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++#else ++int ecm_sfe_fse_enable_handler(const struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) ++#endif + { + int ret; + int current_val; +@@ -467,14 +475,13 @@ static struct ctl_table ecm_sfe_sysctl_t + .proc_handler = &ecm_sfe_mht_enable_handler, + }, + #endif +- {} + }; + + /* + * ecm_sfe_sysctl_tbl_init() + * Register sysctl for SFE + */ +-int ecm_sfe_sysctl_tbl_init() ++int ecm_sfe_sysctl_tbl_init(void) + { + ecm_sfe_ctl_tbl_hdr = register_sysctl(ECM_FRONT_END_SYSCTL_PATH, ecm_sfe_sysctl_tbl); + if (!ecm_sfe_ctl_tbl_hdr) { +@@ -489,7 +496,7 @@ int ecm_sfe_sysctl_tbl_init() + * ecm_sfe_sysctl_tbl_exit() + * Unregister sysctl for SFE + */ +-void ecm_sfe_sysctl_tbl_exit() ++void ecm_sfe_sysctl_tbl_exit(void) + { + if (ecm_sfe_ctl_tbl_hdr) { + unregister_sysctl_table(ecm_sfe_ctl_tbl_hdr); +--- a/ecm_classifier_hyfi.c ++++ b/ecm_classifier_hyfi.c +@@ -437,7 +437,7 @@ static void ecm_classifier_hyfi_get_brid + struct net_device *master; + master = ecm_interface_get_and_hold_dev_master(dev); + if (master) { +- strlcpy(name_buffer, master->name, IFNAMSIZ); ++ strscpy(name_buffer, master->name, IFNAMSIZ); + dev_put(master); + dev_put(dev); + break; +@@ -841,13 +841,13 @@ struct ecm_classifier_hyfi_instance *ecm + /* one of the bridge name is null, typical + * routed connection. Consider valid bridge*/ + if (strlen(to_bridge)) { +- strlcpy(chfi->bridge_name, to_bridge, IFNAMSIZ); ++ strscpy(chfi->bridge_name, to_bridge, IFNAMSIZ); + } else if (strlen(from_bridge)) { +- strlcpy(chfi->bridge_name, from_bridge, IFNAMSIZ); ++ strscpy(chfi->bridge_name, from_bridge, IFNAMSIZ); + } + } else if (!strncmp(to_bridge, from_bridge, IFNAMSIZ)) { + /* Pure bridge connection. Consider any one bridge */ +- strlcpy(chfi->bridge_name, to_bridge, IFNAMSIZ); ++ strscpy(chfi->bridge_name, to_bridge, IFNAMSIZ); + } else { + /* multi-bridge connection */ + chfi->multi_bridge_flow = true; +--- a/examples/ecm_pcc_test.c ++++ b/examples/ecm_pcc_test.c +@@ -716,9 +716,9 @@ static unsigned int ecm_pcc_test_update_ + o_feature_flags = rule->feature_flags; + rule->accel = accel; + rule->feature_flags = feature_flags; +- strlcpy(rule->name, name, sizeof(rule->name)); +- strlcpy(rule->mirror_info.tuple_mirror_dev, tuple_mirror_dev, IFNAMSIZ); +- strlcpy(rule->mirror_info.tuple_ret_mirror_dev, tuple_ret_mirror_dev, IFNAMSIZ); ++ strscpy(rule->name, name, sizeof(rule->name)); ++ strscpy(rule->mirror_info.tuple_mirror_dev, tuple_mirror_dev, IFNAMSIZ); ++ strscpy(rule->mirror_info.tuple_ret_mirror_dev, tuple_ret_mirror_dev, IFNAMSIZ); + rule->ap_info.flow_ap_index = flow_ap_index; + rule->ap_info.return_ap_index = return_ap_index; + spin_unlock_bh(&ecm_pcc_test_rules_lock); +@@ -881,7 +881,7 @@ static unsigned int ecm_pcc_test_add_rul + if (!new_rule) + return 0; + +- strlcpy(new_rule->name, name, sizeof(new_rule->name)); ++ strscpy(new_rule->name, name, sizeof(new_rule->name)); + new_rule->accel = accel; + new_rule->proto = proto; + new_rule->src_port = src_port; +@@ -892,8 +892,8 @@ static unsigned int ecm_pcc_test_add_rul + new_rule->dest_addr = *dest_addr; + new_rule->ipv = ipv; + new_rule->feature_flags = feature_flags; +- strlcpy(new_rule->mirror_info.tuple_mirror_dev, tuple_mirror_dev, IFNAMSIZ); +- strlcpy(new_rule->mirror_info.tuple_ret_mirror_dev, tuple_ret_mirror_dev, IFNAMSIZ); ++ strscpy(new_rule->mirror_info.tuple_mirror_dev, tuple_mirror_dev, IFNAMSIZ); ++ strscpy(new_rule->mirror_info.tuple_ret_mirror_dev, tuple_ret_mirror_dev, IFNAMSIZ); + new_rule->ap_info.flow_ap_index = flow_ap_index; + new_rule->ap_info.return_ap_index = return_ap_index; + INIT_LIST_HEAD(&new_rule->list); +@@ -1024,7 +1024,7 @@ static ssize_t ecm_pcc_test_rule_write(s + /* + * Convert fields + */ +- strlcpy(name, fields[0], sizeof(name)); ++ strscpy(name, fields[0], sizeof(name)); + + name[sizeof(name) - 1] = 0; + if (sscanf(fields[1], "%u", &oper) != 1) +@@ -1072,9 +1072,9 @@ static ssize_t ecm_pcc_test_rule_write(s + return -EINVAL; + } + +- strlcpy(tuple_mirror_dev, fields[11], IFNAMSIZ); ++ strscpy(tuple_mirror_dev, fields[11], IFNAMSIZ); + +- strlcpy(tuple_ret_mirror_dev, fields[12], IFNAMSIZ); ++ strscpy(tuple_ret_mirror_dev, fields[12], IFNAMSIZ); + + if (sscanf(fields[13], "%d", &flow_ap_index) != 1) + goto sscanf_read_error; +--- a/Makefile ++++ b/Makefile +@@ -541,4 +541,10 @@ endif + + ccflags-y += -Wall -Werror + ++# Kernel 6.12 compat headers ++ccflags-y += -I$(obj)/compat ++ ++# GCC 15+ has stricter checks for prototypes and declarations. Silence them ++ccflags-y += -Wno-missing-prototypes -Wno-missing-declarations ++ + obj ?= . +--- /dev/null ++++ b/compat/asm/unaligned.h +@@ -0,0 +1,13 @@ ++/* Compatibility header for moved to in kernel 6.10+ */ ++#ifndef _ASM_UNALIGNED_H ++#define _ASM_UNALIGNED_H ++ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,10,0) ++#include ++#else ++#include_next ++#endif ++ ++#endif /* _ASM_UNALIGNED_H */ diff --git a/qca-nss-ecm/patches/0024-ecm-add-wildcard-opt-to-del-denied.patch b/qca-nss-ecm/patches/0024-ecm-add-wildcard-opt-to-del-denied.patch new file mode 100644 index 0000000..7ca5c97 --- /dev/null +++ b/qca-nss-ecm/patches/0024-ecm-add-wildcard-opt-to-del-denied.patch @@ -0,0 +1,145 @@ +--- a/frontends/ecm_front_end_common.c ++++ b/frontends/ecm_front_end_common.c +@@ -966,10 +966,12 @@ static void ecm_front_end_denied_ports_r + } + + /* +- * Add new line character at the end. ++ * Add new line character at the end only if we have content + */ +- len = scnprintf(read_buf + bytes, 4, "\n"); +- bytes += len; ++ if (bytes > 0) { ++ len = scnprintf(read_buf + bytes, 4, "\n"); ++ bytes += len; ++ } + + bytes = memory_read_from_buffer(buffer, *lenp, ppos, read_buf, bytes); + *lenp = bytes; +@@ -1000,7 +1002,6 @@ static inline bool ecm_front_end_is_port + */ + static int ecm_front_end_denied_ports_handler(int write, void *buffer, size_t *lenp, loff_t *ppos, struct hlist_head *denied_ports, bool is_udp) + { +- + char *buf; + char *pfree; + char *token; +@@ -1075,36 +1076,58 @@ static int ecm_front_end_denied_ports_ha + } + } + } else if (!strncmp(token, "del", 3)) { +- while (buf) { +- token = strsep(&buf, " "); +- if (kstrtol(token, 10, &val)) { +- DEBUG_ERROR("%s is not a number\n", token); +- kfree(pfree); +- return -EINVAL; +- } +- if (sscanf(token, "%d", &port)) { +- struct hlist_node *pnode, *temp; +- uint32_t hash; ++ token = strsep(&buf, " "); + +- if (port < 0 || port > 65535) { +- DEBUG_ERROR("port %d is not between (0-65535)\n", port); ++ /* Simple check for wildcard - handles both with and without newline */ ++ if (token && token[0] == '*') { ++ int i; ++ struct hlist_node *pnode, *temp; ++ ++ /* Loop through all hash buckets and delete all entries */ ++ for (i = 0; i < ECM_FRONT_END_DENIED_PORTS_HTABLE_SIZE; i++) { ++ hlist_for_each_safe(pnode, temp, &denied_ports[i]) { ++ struct ecm_denied_port_node *p = hlist_entry(pnode, struct ecm_denied_port_node, hnode); ++ hlist_del(&p->hnode); ++ vfree(p); ++ if (is_udp) { ++ atomic_dec(&ecm_udp_denied_port_count); ++ } else { ++ atomic_dec(&ecm_tcp_denied_port_count); ++ } ++ } ++ } ++ } else { ++ while (token) { ++ if (kstrtol(token, 10, &val)) { ++ DEBUG_ERROR("%s is not a number\n", token); + kfree(pfree); + return -EINVAL; + } ++ if (sscanf(token, "%d", &port)) { ++ struct hlist_node *pnode, *temp; ++ uint32_t hash; ++ ++ if (port < 0 || port > 65535) { ++ DEBUG_ERROR("port %d is not between (0-65535)\n", port); ++ kfree(pfree); ++ return -EINVAL; ++ } + +- hash = hash_32(port, ECM_FRONT_END_DENIED_PORTS_HTABLE_SIZE); +- hlist_for_each_safe(pnode, temp, &denied_ports[hash]) { +- struct ecm_denied_port_node *p = hlist_entry(pnode, struct ecm_denied_port_node, hnode); +- if (p->port == port) { +- hlist_del(&p->hnode); +- vfree(p); +- if (is_udp) { +- atomic_dec(&ecm_udp_denied_port_count); +- } else { +- atomic_dec(&ecm_tcp_denied_port_count); ++ hash = hash_32(port, ECM_FRONT_END_DENIED_PORTS_HTABLE_SIZE); ++ hlist_for_each_safe(pnode, temp, &denied_ports[hash]) { ++ struct ecm_denied_port_node *p = hlist_entry(pnode, struct ecm_denied_port_node, hnode); ++ if (p->port == port) { ++ hlist_del(&p->hnode); ++ vfree(p); ++ if (is_udp) { ++ atomic_dec(&ecm_udp_denied_port_count); ++ } else { ++ atomic_dec(&ecm_tcp_denied_port_count); ++ } + } + } + } ++ token = strsep(&buf, " "); + } + } + } else { +@@ -1133,6 +1156,9 @@ int ecm_front_end_udp_denied_ports_handl + * Delete ports from the list: + * echo del 67 > /proc/sys/net/ecm/udp_denied_ports + * ++ * Delete all ports from the list: ++ * echo del * > /proc/sys/net/ecm/udp_denied_ports ++ * + * Dump the list to the console: + * cat /proc/sys/net/ecm/udp_denied_ports + */ +@@ -1157,6 +1183,9 @@ int ecm_front_end_tcp_denied_ports_handl + * Delete ports from the list: + * echo del 67 > /proc/sys/net/ecm/tcp_denied_ports + * ++ * Delete all ports from the list: ++ * echo del * > /proc/sys/net/ecm/tcp_denied_ports ++ * + * Dump the list to the console: + * cat /proc/sys/net/ecm/tcp_denied_ports + */ +@@ -1200,7 +1229,7 @@ static struct ctl_table ecm_front_end_sy + * ecm_front_end_common_sysctl_register() + * Function to register sysctl node during front end init + */ +-void ecm_front_end_common_sysctl_register() ++void ecm_front_end_common_sysctl_register(void) + { + /* + * Register sysctl table. +@@ -1217,7 +1246,7 @@ void ecm_front_end_common_sysctl_registe + * ecm_front_end_common_sysctl_unregister() + * Function to unregister sysctl node during front end exit + */ +-void ecm_front_end_common_sysctl_unregister() ++void ecm_front_end_common_sysctl_unregister(void) + { + /* + * Unregister sysctl table. diff --git a/qca-nss-macsec/Makefile b/qca-nss-macsec/Makefile new file mode 100644 index 0000000..9a317e0 --- /dev/null +++ b/qca-nss-macsec/Makefile @@ -0,0 +1,85 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-macsec +PKG_RELEASE:=2 +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-macsec +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2023-10-16 +PKG_SOURCE_VERSION:=b94e22d +PKG_MIRROR_HASH:=083dba530091b0a6000c7889f123e477c84789bca647bf6eb03b688bff0882b8 +QSDK_VERSION:=12.4.5 +PKG_VERSION:=$(QSDK_VERSION).$(subst -,.,$(PKG_SOURCE_DATE))~$(PKG_SOURCE_VERSION) + +PKG_BUILD_PARALLEL:=1 +PKG_FLAGS:=nonshared + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-macsec + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@(TARGET_qualcommax_ipq807x||TARGET_ipq60xx) \ + +libc \ + @BROKEN + TITLE:=Kernel driver for NSS macsec + FILES:=$(PKG_BUILD_DIR)/qca-nss-macsec.ko + AUTOLOAD:=$(call AutoLoad,52,qca-nss-macsec) +endef + +define KernelPackage/qca-nss-macsec/Description +This package contains a MACSEC driver for QCA chipset +endef + +EXTRA_CFLAGS+= \ + -Wno-missing-prototypes \ + -Wno-missing-declarations + +QCA_NSS_MACSEC_CONFIG_OPTS+= TOOL_PATH=$(TOOLCHAIN_DIR)/bin/ \ + SYS_PATH=$(LINUX_DIR) \ + TOOLPREFIX=$(TARGET_CROSS) \ + KVER=$(LINUX_VERSION) \ + CFLAGS="$(TARGET_CFLAGS) $(EXTRA_CFLAGS)" \ + LDFLAGS="$(TARGET_LDFLAGS)" \ + ARCH=$(LINUX_KARCH) + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-nss-macsec + $(INSTALL_DIR) $(1)/usr/lib + $(CP) $(PKG_BUILD_DIR)/include/nss_macsec_types.h $(1)/usr/include/qca-nss-macsec + $(CP) $(PKG_BUILD_DIR)/include/nss_macsec_secy.h $(1)/usr/include/qca-nss-macsec + $(CP) $(PKG_BUILD_DIR)/include/nss_macsec_secy_rx.h $(1)/usr/include/qca-nss-macsec + $(CP) $(PKG_BUILD_DIR)/include/nss_macsec_secy_tx.h $(1)/usr/include/qca-nss-macsec + $(CP) $(PKG_BUILD_DIR)/libfal.so $(1)/usr/lib +endef + +ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq807x") + SOC=ipq807x_64 + subtarget:=$(CONFIG_TARGET_SUBTARGET) +else ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq60xx") + SOC=ipq60xx_64 + subtarget:=$(CONFIG_TARGET_SUBTARGET) +else ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq50xx") + SOC=ipq50xx_64 + subtarget:=$(CONFIG_TARGET_SUBTARGET) +endif + +define Build/Compile + +$(KERNEL_MAKE) \ + M="$(PKG_BUILD_DIR)" \ + SoC="$(subtarget)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + $(PKG_JOBS) \ + modules + +$(MAKE) -C $(PKG_BUILD_DIR) $(strip $(QCA_NSS_MACSEC_CONFIG_OPTS)) $(PKG_JOBS) -f Makefile.shell +endef + +define KernelPackage/qca-nss-macsec/install + $(INSTALL_DIR) $(1)/usr/sbin + $(INSTALL_DIR) $(1)/usr/lib + $(INSTALL_BIN) $(PKG_BUILD_DIR)/*.so $(1)/usr/lib/ + $(INSTALL_BIN) $(PKG_BUILD_DIR)/macsec_shell $(1)/usr/sbin/ +endef + +$(eval $(call KernelPackage,qca-nss-macsec)) diff --git a/qca-nss-macsec/patches/0001-change-warning-to-debug.patch b/qca-nss-macsec/patches/0001-change-warning-to-debug.patch new file mode 100644 index 0000000..25f8f9c --- /dev/null +++ b/qca-nss-macsec/patches/0001-change-warning-to-debug.patch @@ -0,0 +1,19 @@ +--- a/nss_macsec_init.c ++++ b/nss_macsec_init.c +@@ -15,6 +15,7 @@ + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + ++#include "linux/kern_levels.h" + #include + #include + #include +@@ -296,7 +297,7 @@ static int nss_macsec_dt_init(uint32_t d + + nss_macsec_node = of_find_node_by_name(NULL, dev_name); + if (!nss_macsec_node) { +- printk(KERN_ERR "cannot find nss-macsec%d node\n", dev_id); ++ printk(KERN_DEBUG "cannot find nss-macsec%d node\n", dev_id); + return -ENODEV; + } + printk(KERN_INFO "%s DT exist!\n", dev_name); diff --git a/qca-ssdk-shell/Makefile b/qca-ssdk-shell/Makefile new file mode 100644 index 0000000..38a54b5 --- /dev/null +++ b/qca-ssdk-shell/Makefile @@ -0,0 +1,51 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-ssdk-shell +PKG_RELEASE:=4 + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/ssdk-shell.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2024-12-17 +PKG_SOURCE_VERSION:=a2b7be2 +PKG_MIRROR_HASH:=7f546cc9db6627ee8c06db47c957c6a4452e72194b7af355e7f4e164d0848295 +QSDK_VERSION:=12.5 +PKG_VERSION:=$(QSDK_VERSION).$(subst -,.,$(PKG_SOURCE_DATE))~$(PKG_SOURCE_VERSION) + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define Package/qca-ssdk-shell + SECTION:=QCA + CATEGORY:=Utilities + TITLE:=Shell application for QCA SSDK + DEPENDS:=+kmod-qca-ssdk +endef + + +define Package/qca-ssdk-shell/Description + This package contains a qca-ssdk shell application for QCA chipset +endef + +ifndef CONFIG_TOOLCHAIN_BIN_PATH +CONFIG_TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin +endif + +QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) \ + SYS_PATH=$(LINUX_DIR) \ + TOOLPREFIX=$(TARGET_CROSS) \ + KVER=$(LINUX_VERSION) \ + CFLAGS="$(TARGET_CFLAGS)" \ + LDFLAGS="$(TARGET_LDFLAGS)" \ + ARCH=$(LINUX_KARCH) + +define Build/Compile + $(MAKE) -C $(PKG_BUILD_DIR) $(PKG_JOBS) $(strip $(QCASSDK_CONFIG_OPTS)) +endef + +define Package/qca-ssdk-shell/install + $(INSTALL_DIR) $(1)/usr/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/build/bin/ssdk_sh $(1)/usr/sbin/ +endef + + +$(eval $(call BuildPackage,qca-ssdk-shell)) diff --git a/qca-ssdk-shell/patches/0002-qca-ssdk-shell-fix-ioctl-segfault.patch b/qca-ssdk-shell/patches/0002-qca-ssdk-shell-fix-ioctl-segfault.patch new file mode 100644 index 0000000..3691bed --- /dev/null +++ b/qca-ssdk-shell/patches/0002-qca-ssdk-shell-fix-ioctl-segfault.patch @@ -0,0 +1,93 @@ +--- a/include/init/ssdk_init.h ++++ b/include/init/ssdk_init.h +@@ -33,8 +33,6 @@ extern "C" { + + #define SSDK_MAX_VIRTUAL_PORT_NUM \ + (SSDK_MAX_VIRTUAL_PORT_ID-SSDK_MIN_VIRTUAL_PORT_ID+1) +-#define IOCTL_COMPAT +- + /*qca808x_start*/ + typedef enum { + HSL_MDIO = 1, +@@ -267,17 +265,6 @@ typedef struct + a_bool_t in_interfacectrl; + } ssdk_features; + /*qca808x_start*/ +-#ifdef IOCTL_COMPAT +- typedef struct +- { +- hsl_init_mode cpu_mode; +- hsl_access_mode reg_mode; +- ssdk_chip_type chip_type; +- a_uint32_t chip_revision; +- a_uint32_t nl_prot; +- } ssdk_init_cfg_us; +-#endif +- + #define CFG_STR_SIZE 20 + typedef struct + { +@@ -294,11 +281,7 @@ typedef struct + /*qca808x_end*/ + ssdk_features features; + /*qca808x_start*/ +-#ifdef IOCTL_COMPAT +- ssdk_init_cfg_us init_cfg; +-#else + ssdk_init_cfg init_cfg; +-#endif + } ssdk_cfg_t; + sw_error_t + ssdk_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); +--- a/src/shell/shell.c ++++ b/src/shell/shell.c +@@ -616,10 +616,8 @@ cmd_socket_init(int dev_id) + #endif + init_cfg.chip_type=CHIP_UNSPECIFIED; + /*qca808x_end*/ +-#ifndef IOCTL_COMPAT + init_cfg.reg_func.mdio_set = NULL; + init_cfg.reg_func.mdio_get = NULL; +-#endif + /*qca808x_start*/ + rv = ssdk_init(dev_id, &init_cfg); + if (SW_OK == rv) +--- a/src/shell/shell_io.c ++++ b/src/shell/shell_io.c +@@ -11863,15 +11863,7 @@ static void + _cmd_collect_shell_cfg(ssdk_cfg_t *shell_cfg) + { + memset(shell_cfg, 0, sizeof(ssdk_cfg_t)); +-#ifdef IOCTL_COMPAT +- shell_cfg->init_cfg.cpu_mode = init_cfg.cpu_mode; +- shell_cfg->init_cfg.reg_mode = init_cfg.reg_mode; +- shell_cfg->init_cfg.chip_type = init_cfg.chip_type; +- shell_cfg->init_cfg.chip_revision = init_cfg.chip_revision; +- shell_cfg->init_cfg.nl_prot = init_cfg.nl_prot; +-#else + shell_cfg->init_cfg = init_cfg; +-#endif + + #ifdef VERSION + aos_mem_copy(shell_cfg->build_ver, VERSION, sizeof(VERSION)); +@@ -11938,7 +11930,7 @@ _cmd_collect_shell_cfg(ssdk_cfg_t *shell + static void + _cmd_data_print_cfg(ssdk_cfg_t *entry) + { +- ssdk_init_cfg_us *init = &(entry->init_cfg); ++ ssdk_init_cfg *init = &(entry->init_cfg); + + dprintf("[build verison]:%-10s [build date]:%s\n", entry->build_ver, entry->build_date); + dprintf("[chip type]:%-14s [arch]:%-12s [os]:%s\n", entry->chip_type, entry->cpu_type, entry->os_info); +@@ -11949,10 +11941,8 @@ _cmd_data_print_cfg(ssdk_cfg_t *entry) + cmd_cpu_mode(init->cpu_mode), cmd_access_mode(init->reg_mode), + init->nl_prot); + /*qca808x_end*/ +-#if 0 +-dprintf("[inf defined]:mdio_set(%s) mdio_get(%s) header_reg_set(%s) header_reg_get(%s)\n", ++ dprintf("[inf defined]:mdio_set(%s) mdio_get(%s) header_reg_set(%s) header_reg_get(%s)\n", + DEFINED2STR(mdio_set), DEFINED2STR(mdio_get), DEFINED2STR(header_reg_set), DEFINED2STR(header_reg_get)); +-#endif + /*qca808x_start*/ + } + diff --git a/qca-ssdk-shell/patches/0003-qca-ssdk-shell-fix-tmpbool.patch b/qca-ssdk-shell/patches/0003-qca-ssdk-shell-fix-tmpbool.patch new file mode 100644 index 0000000..5ac56af --- /dev/null +++ b/qca-ssdk-shell/patches/0003-qca-ssdk-shell-fix-tmpbool.patch @@ -0,0 +1,11 @@ +--- a/src/shell/shell_io.c ++++ b/src/shell/shell_io.c +@@ -40933,7 +40933,7 @@ sw_error_t + cmd_data_check_tunnel_flags_parser(char *cmd_str, void * val, a_uint32_t size) + { + char *cmd; +- a_bool_t tmpbool; ++ a_bool_t tmpbool = A_FALSE;; + a_uint32_t tmpdata = 0; + sw_error_t rv; + fal_tunnel_flags_excep_parser_ctrl_t entry; diff --git a/qca-ssdk-shell/patches/0004-qca-ssdk-shell-fix-build-gcc-15.patch b/qca-ssdk-shell/patches/0004-qca-ssdk-shell-fix-build-gcc-15.patch new file mode 100644 index 0000000..847fab5 --- /dev/null +++ b/qca-ssdk-shell/patches/0004-qca-ssdk-shell-fix-build-gcc-15.patch @@ -0,0 +1,215 @@ +--- a/include/shell/shell_config.h ++++ b/include/shell/shell_config.h +@@ -71,7 +71,7 @@ extern "C" { + char *sub_memo; + char *sub_usage; + int sub_api; +- sw_error_t (*sub_func) (); ++ sw_error_t (*sub_func) (a_ulong_t *); + }; + struct cmd_des_t + { +--- a/include/shell/shell_io.h ++++ b/include/shell/shell_io.h +@@ -29,8 +29,8 @@ + typedef struct + { + sw_data_type_e data_type; +- sw_error_t(*param_check) (); +- void (*show_func) (); ++ void *param_check; ++ void *show_func; + } sw_data_type_t; + + void set_talk_mode(int mode); +@@ -42,7 +42,7 @@ sw_data_type_t * cmd_data_type_find(sw_d + void cmd_strtol(char *str, a_uint32_t * arg_val); + + sw_error_t __cmd_data_check_complex(char *info, char *defval, char *usage, +- sw_error_t(*chk_func)(), void *arg_val, ++ void *chk_func, void *arg_val, + a_uint32_t size); + + sw_error_t cmd_data_check_portid(char *cmdstr, fal_port_t * val, a_uint32_t size); +--- a/src/shell/shell.c ++++ b/src/shell/shell.c +@@ -125,44 +125,41 @@ cmd_api_func(sw_api_func_t *fp, a_uint32 + { + a_ulong_t *p = &args[2]; + sw_error_t rv; +- sw_error_t(*func) (); +- +- func = fp->func; + + switch (nr_param) + { + case 0: +- rv = (func) (); ++ rv = ((sw_error_t (*)(void))fp->func)(); + break; + case 1: +- rv = (func) (p[0]); ++ rv = ((sw_error_t (*)(a_ulong_t))fp->func)(p[0]); + break; + case 2: +- rv = (func) (p[0], p[1]); ++ rv = ((sw_error_t (*)(a_ulong_t, a_ulong_t))fp->func)(p[0], p[1]); + break; + case 3: +- rv = (func) (p[0], p[1], p[2]); ++ rv = ((sw_error_t (*)(a_ulong_t, a_ulong_t, a_ulong_t))fp->func)(p[0], p[1], p[2]); + break; + case 4: +- rv = (func) (p[0], p[1], p[2], p[3]); ++ rv = ((sw_error_t (*)(a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t))fp->func)(p[0], p[1], p[2], p[3]); + break; + case 5: +- rv = (func) (p[0], p[1], p[2], p[3], p[4]); ++ rv = ((sw_error_t (*)(a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t))fp->func)(p[0], p[1], p[2], p[3], p[4]); + break; + case 6: +- rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5]); ++ rv = ((sw_error_t (*)(a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t))fp->func)(p[0], p[1], p[2], p[3], p[4], p[5]); + break; + case 7: +- rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6]); ++ rv = ((sw_error_t (*)(a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t))fp->func)(p[0], p[1], p[2], p[3], p[4], p[5], p[6]); + break; + case 8: +- rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); ++ rv = ((sw_error_t (*)(a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t))fp->func)(p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); + break; + case 9: +- rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]); ++ rv = ((sw_error_t (*)(a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t))fp->func)(p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]); + break; + case 10: +- rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], ++ rv = ((sw_error_t (*)(a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t, a_ulong_t))fp->func)(p[0], p[1], p[2], p[3], p[4], p[5], + p[6], p[7], p[8], p[9]); + break; + default: +@@ -206,7 +203,7 @@ cmd_api_output(sw_api_param_t *pp, a_uin + + if (data_type->show_func) + { +- data_type->show_func(pptmp->param_name, pbuf, pptmp->data_size); ++ ((void (*)(a_uint8_t *, void *, a_uint32_t))data_type->show_func)(pptmp->param_name, pbuf, pptmp->data_size); + } + else + { +@@ -297,11 +294,11 @@ cmd_parse_api(char **cmd_str, a_ulong_t + { + if(!(pptmp->param_type & SW_PARAM_PTR) && sizeof(a_ulong_t) != sizeof(a_uint32_t)) { + a_uint32_t tmp = 0; +- if (data_type->param_check(tmp_str, &tmp, pptmp->data_size) != SW_OK) ++ if (((sw_error_t (*)(char *, void *, a_uint32_t))data_type->param_check)(tmp_str, &tmp, pptmp->data_size) != SW_OK) + return SW_BAD_PARAM; + *(a_ulong_t *)pentry = tmp; + } else { +- if (data_type->param_check(tmp_str, pentry, pptmp->data_size) != SW_OK) ++ if (((sw_error_t (*)(char *, void *, a_uint32_t))data_type->param_check)(tmp_str, pentry, pptmp->data_size) != SW_OK) + return SW_BAD_PARAM; + } + +--- a/src/shell/shell_io.c ++++ b/src/shell/shell_io.c +@@ -989,7 +989,7 @@ sw_error_t __cmd_data_check_quit_help(ch + } + + sw_error_t __cmd_data_check_complex(char *info, char *defval, char *usage, +- sw_error_t(*chk_func)(), void *arg_val, ++ void *chk_func, void *arg_val, + a_uint32_t size) + { + sw_error_t ret; +@@ -1003,7 +1003,7 @@ sw_error_t __cmd_data_check_complex(char + if (ret == SW_ABORTED) + return ret; + else if (ret == SW_OK) { +- ret = chk_func(cmd, arg_val, size); ++ ret = ((sw_error_t (*)(char *, void *, a_uint32_t))chk_func)(cmd, arg_val, size); + if (ret) + dprintf("%s", usage); + } +@@ -14655,7 +14655,7 @@ cmd_data_check_egress_shaper(char *cmd_s + { + char *cmd; + sw_error_t rv; +- a_bool_t bool = A_FALSE; ++ a_bool_t bool_val = A_FALSE; + fal_egress_shaper_t entry; + + aos_mem_zero(&entry, sizeof (fal_egress_shaper_t)); +@@ -14677,7 +14677,7 @@ cmd_data_check_egress_shaper(char *cmd_s + } + else + { +- rv = cmd_data_check_confirm(cmd, A_TRUE, &bool, ++ rv = cmd_data_check_confirm(cmd, A_TRUE, &bool_val, + sizeof (a_bool_t)); + if (SW_OK != rv) + dprintf("usage: \n"); +@@ -14685,7 +14685,7 @@ cmd_data_check_egress_shaper(char *cmd_s + } + while (talk_mode && (SW_OK != rv)); + +- if (A_TRUE == bool) ++ if (A_TRUE == bool_val) + { + entry.meter_unit = FAL_BYTE_BASED; + } +@@ -14865,7 +14865,7 @@ cmd_data_check_acl_policer(char *cmd_str + { + char *cmd; + sw_error_t rv; +- a_bool_t bool = A_FALSE; ++ a_bool_t bool_val = A_FALSE; + fal_acl_policer_t entry; + + aos_mem_zero(&entry, sizeof (fal_acl_policer_t)); +@@ -14912,7 +14912,7 @@ cmd_data_check_acl_policer(char *cmd_str + } + else + { +- rv = cmd_data_check_confirm(cmd, A_TRUE, &bool, ++ rv = cmd_data_check_confirm(cmd, A_TRUE, &bool_val, + sizeof (a_bool_t)); + if (SW_OK != rv) + dprintf("usage: \n"); +@@ -14920,7 +14920,7 @@ cmd_data_check_acl_policer(char *cmd_str + } + while (talk_mode && (SW_OK != rv)); + +- if (A_TRUE == bool) ++ if (A_TRUE == bool_val) + { + entry.meter_unit = FAL_BYTE_BASED; + } +@@ -15205,7 +15205,7 @@ cmd_data_check_port_policer(char *cmd_st + { + char *cmd; + sw_error_t rv; +- a_bool_t bool = A_FALSE; ++ a_bool_t bool_val = A_FALSE; + fal_port_policer_t entry; + + aos_mem_zero(&entry, sizeof (fal_port_policer_t)); +@@ -15252,7 +15252,7 @@ cmd_data_check_port_policer(char *cmd_st + } + else + { +- rv = cmd_data_check_confirm(cmd, A_TRUE, &bool, ++ rv = cmd_data_check_confirm(cmd, A_TRUE, &bool_val, + sizeof (a_bool_t)); + if (SW_OK != rv) + dprintf("usage: \n"); +@@ -15260,7 +15260,7 @@ cmd_data_check_port_policer(char *cmd_st + } + while (talk_mode && (SW_OK != rv)); + +- if (A_TRUE == bool) ++ if (A_TRUE == bool_val) + { + entry.meter_unit = FAL_BYTE_BASED; + } diff --git a/qca-ssdk-shell/patches/0005-qca-ssdk-shell-fix-make.patch b/qca-ssdk-shell/patches/0005-qca-ssdk-shell-fix-make.patch new file mode 100644 index 0000000..cd2da2c --- /dev/null +++ b/qca-ssdk-shell/patches/0005-qca-ssdk-shell-fix-make.patch @@ -0,0 +1,46 @@ +--- a/config ++++ b/config +@@ -84,7 +84,7 @@ endif + #CPU_CFLAG=-Wstrict-prototypes -Wundef -fomit-frame-pointer -G 0 -mno-abicalls -Wno-trigraphs -fno-strict-aliasing -fno-common -ffreestanding -O2 -fno-pic -pipe -mabi=32 -march=r4600 -Wa,-32 -Wa,-march=r4600 -Wa,--trap -DMODULE -mlong-calls -DEXPORT_SYMTAB + + +-KERNEL_MODE=FLASE ++KERNEL_MODE=TRUE + #compatiable with OpenWRT + ifeq ($(SWITCH_SSDK_MODE),user) + KERNEL_MODE=FLASE +--- a/make/config.mk ++++ b/make/config.mk +@@ -73,7 +73,7 @@ OPT_FLAG= + LD_FLAG= + + SHELLOBJ=ssdk_sh +-US_MOD=libssdk_us ++US_MOD=ssdk_us + KS_MOD=ssdk_ks + + ifeq (TRUE, $(KERNEL_MODE)) +--- a/Makefile ++++ b/Makefile +@@ -22,9 +22,9 @@ kslib_o: + $(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=KSLIB -C src/$i all || exit 1;) + + uslib:uslib_o +- $(AR) -r $(BIN_DIR)/$(US_MOD)_$(RUNMODE).a $(wildcard $(BLD_DIR)/USLIB/*.o) +- $(CC) -fPIC -shared -o $(BIN_DIR)/$(US_MOD).so $(wildcard $(BLD_DIR)/USLIB/*.o) +- $(STRIP) $(BIN_DIR)/$(US_MOD).so ++ $(AR) -r $(BIN_DIR)/lib$(US_MOD)_$(RUNMODE).a $(wildcard $(BLD_DIR)/USLIB/*.o) ++ $(CC) -fPIC -shared -o $(BIN_DIR)/lib$(US_MOD)_$(RUNMODE).so $(wildcard $(BLD_DIR)/USLIB/*.o) ++ $(STRIP) $(BIN_DIR)/lib$(US_MOD)_$(RUNMODE).so + + uslib_o: + $(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=USLIB -C src/$i all || exit 1;) +--- a/src/shell/Makefile ++++ b/src/shell/Makefile +@@ -21,4 +21,5 @@ else + endif + + lib: +- $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $(LDFLAGS) $(EXTRA_LDFLAGS) $(OBJ_FILE) $(BIN_DIR)/$(US_MOD)_$(RUNMODE).a -o $(DST_DIR)/$(SHELLOBJ) $(PT_LIB) ++ # $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $(LDFLAGS) $(EXTRA_LDFLAGS) $(OBJ_FILE) -L$(BIN_DIR) -l$(US_MOD)_$(RUNMODE) -Wl,-rpath,/usr/lib -o $(DST_DIR)/$(SHELLOBJ) $(PT_LIB) ++ $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $(LDFLAGS) $(EXTRA_LDFLAGS) $(OBJ_FILE) -L$(BIN_DIR) -l:lib$(US_MOD)_$(RUNMODE).a -o $(DST_DIR)/$(SHELLOBJ) $(PT_LIB) diff --git a/qca-ssdk-shell/patches/0006-qca-ssdk-shell-remove-unused-chip-code.patch b/qca-ssdk-shell/patches/0006-qca-ssdk-shell-remove-unused-chip-code.patch new file mode 100644 index 0000000..41d8ba3 --- /dev/null +++ b/qca-ssdk-shell/patches/0006-qca-ssdk-shell-remove-unused-chip-code.patch @@ -0,0 +1,612 @@ +From 6f305d4fa1999e238795ecbdaea5f57c4556f8ed Mon Sep 17 00:00:00 2001 +From: esong +Date: Wed, 31 Jul 2024 18:14:39 +0800 +Subject: [PATCH] [qca-ssdk-shell] remove unused chip code + +Change-Id: I2d3a0a20479275c6f39d84df7514c65611bde29c +Signed-off-by: esong +--- + config | 2 +- + include/init/ssdk_init.h | 60 ++------------------------- + make/config.mk | 56 ++++++++----------------- + make/linux_opt.mk | 20 --------- + src/api/api_access.c | 89 +++------------------------------------- + src/shell/shell_config.c | 1 - + src/shell/shell_io.c | 10 +---- + src/shell/shell_sw.c | 34 --------------- + 8 files changed, 29 insertions(+), 243 deletions(-) + +From e1cb624952b8a83dbf2b1933fd13327bdf865cab Mon Sep 17 00:00:00 2001 +From: zhongjia +Date: Wed, 16 Oct 2024 19:52:38 +0800 +Subject: [PATCH] [qca-ssdk-shell] remove some unsupported mode + +Change-Id: I084653d61f1cb83b334f4941bd700a2e6ff219d1 +Signed-off-by: zhongjia +--- + include/fal/fal_port_ctrl.h | 79 +++++++++++++++++++++++-------------- + src/shell/shell_config.c | 4 +- + src/shell/shell_io.c | 48 ---------------------- + 3 files changed, 52 insertions(+), 79 deletions(-) + +--- a/config ++++ b/config +@@ -93,7 +93,7 @@ endif + #FAL=FALSE or not define FAL, FAL will not be included in SSDK + FAL=TRUE + +-#CHIP_TYPE can be defined as ATHENA, GARUDA, SHIVA, HORUS, ISIS, ISISC and ALL_CHIP(ALL_CHIP means GARUDA, SHIVA, HORUS and ISIS) ++#CHIP_TYPE can be defined as ISIS, ISISC and ALL_CHIP(ALL_CHIP means ISIS) + CHIP_TYPE=ISISC + + #UK_IF=FALSE or not define UK_IF, UK_IF will not be included in SSDK +--- a/include/init/ssdk_init.h ++++ b/include/init/ssdk_init.h +@@ -1,7 +1,7 @@ + /* + * Copyright (c) 2014, 2017-2019, 2021, The Linux Foundation. All rights reserved. + * +- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the +@@ -120,11 +120,7 @@ extern "C" { + typedef enum + { + CHIP_UNSPECIFIED = 0, +- CHIP_ATHENA, +- CHIP_GARUDA, +- CHIP_SHIVA, +- CHIP_HORUS, +- CHIP_ISIS, ++ CHIP_ISIS = 5, + CHIP_ISISC, + CHIP_DESS, + CHIP_HPPE, +@@ -181,58 +177,8 @@ typedef struct + a_uint32_t mac_mode2; + } ssdk_init_cfg; + /*qca808x_end*/ +-#if defined ATHENA +-#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2}; +-#elif defined GARUDA +- +-#define def_init_cfg_cpu2 {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2,}; +- +-#define def_init_spec_cfg_cpu2 {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_TRUE, \ +- .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \ +- .tx_delay_s0 = A_TRUE, .tx_delay_s1 = A_FALSE,\ +- .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE,\ +- .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,} +- +-#define def_init_cfg_cpu1 {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1,}; +- +-#define def_init_spec_cfg_cpu1 {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_FALSE, \ +- .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \ +- .tx_delay_s0 = A_TRUE, .tx_delay_s1 = A_FALSE,\ +- .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \ +- .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,} +- +-#define def_init_cfg_cpu1plus {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1_PLUS,}; +- +-#define def_init_spec_cfg_cpu1plus {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_FALSE, \ +- .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \ +- .tx_delay_s0 = A_FALSE, .tx_delay_s1 = A_FALSE,\ +- .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \ +- .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,} + +-#define def_init_cfg_nocpu {.reg_mode = HSL_MDIO, .cpu_mode = HSL_NO_CPU,}; +- +-#define def_init_spec_cfg_nocpu { .mac0_rgmii = A_FALSE, .mac5_rgmii = A_FALSE, \ +- .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \ +- .tx_delay_s0 = A_FALSE, .tx_delay_s1 = A_FALSE,\ +- .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \ +- .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,} +- +-#define def_init_cfg_cpu1_gmii {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1,}; +- +-#define def_init_spec_cfg_cpu1_gmii {.mac0_rgmii = A_FALSE, .mac5_rgmii = A_FALSE, \ +- .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \ +- .tx_delay_s0 = A_TRUE, .tx_delay_s1 = A_FALSE,\ +- .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \ +- .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,} +- +-#define def_init_cfg def_init_cfg_cpu2 +-#define def_init_spec_cfg def_init_spec_cfg_cpu2 +- +-#elif defined SHIVA +-#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2}; +-#elif defined HORUS +-#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2}; +-#elif defined ISIS ++#if defined ISIS + #define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2}; + #elif defined ISISC + /*qca808x_start*/ +--- a/make/config.mk ++++ b/make/config.mk +@@ -23,44 +23,24 @@ ifndef OS_VER + OS_VER=2_6 + endif + +-#support chip type such as ATHENA GARUDA +-ifndef CHIP_TYPE +- SUPPORT_CHIP = GARUDA +-else +- ifeq (GARUDA, $(CHIP_TYPE)) +- SUPPORT_CHIP = GARUDA +- endif +- +- ifeq (ATHENA, $(CHIP_TYPE)) +- SUPPORT_CHIP = ATHENA +- endif +- +- ifeq (SHIVA, $(CHIP_TYPE)) +- SUPPORT_CHIP = SHIVA +- endif +- +- ifeq (HORUS, $(CHIP_TYPE)) +- SUPPORT_CHIP = HORUS +- endif +- +- ifeq (ISIS, $(CHIP_TYPE)) +- SUPPORT_CHIP = ISIS +- endif ++#support chip type ++ifeq (ISIS, $(CHIP_TYPE)) ++ SUPPORT_CHIP = ISIS ++endif + +- ifeq (ISISC, $(CHIP_TYPE)) +- SUPPORT_CHIP = ISISC +- endif ++ifeq (ISISC, $(CHIP_TYPE)) ++ SUPPORT_CHIP = ISISC ++endif + +- ifeq (ALL_CHIP, $(CHIP_TYPE)) +- ifneq (TRUE, $(FAL)) +- $(error FAL must be TRUE when CHIP_TYPE is defined as ALL_CHIP!) +- endif +- SUPPORT_CHIP = GARUDA SHIVA HORUS ISIS ISISC +- endif ++ifeq (ALL_CHIP, $(CHIP_TYPE)) ++ ifneq (TRUE, $(FAL)) ++ $(error FAL must be TRUE when CHIP_TYPE is defined as ALL_CHIP!) ++ endif ++ SUPPORT_CHIP = ISIS ISISC ++endif + +- ifndef SUPPORT_CHIP +- $(error defined CHIP_TYPE isn't supported!) +- endif ++ifndef SUPPORT_CHIP ++ $(error defined CHIP_TYPE isn't supported!) + endif + + #define compile tool prefix +--- a/make/linux_opt.mk ++++ b/make/linux_opt.mk +@@ -216,26 +216,6 @@ MODULE_INC += -I$(PRJ_PATH)/include \ + -I$(PRJ_PATH)/include/sal/sd/linux/uk_interface \ + -I$(PRJ_PATH)/include/init + +-ifneq (,$(findstring ATHENA, $(SUPPORT_CHIP))) +- MODULE_INC += -I$(PRJ_PATH)/include/hsl/athena +- MODULE_CFLAG += -DATHENA +-endif +- +-ifneq (,$(findstring GARUDA, $(SUPPORT_CHIP))) +- MODULE_INC += -I$(PRJ_PATH)/include/hsl/garuda +- MODULE_CFLAG += -DGARUDA +-endif +- +-ifneq (,$(findstring SHIVA, $(SUPPORT_CHIP))) +- MODULE_INC += -I$(PRJ_PATH)/include/hsl/shiva +- MODULE_CFLAG += -DSHIVA +-endif +- +-ifneq (,$(findstring HORUS, $(SUPPORT_CHIP))) +- MODULE_INC += -I$(PRJ_PATH)/include/hsl/horus +- MODULE_CFLAG += -DHORUS +-endif +- + ifneq (,$(findstring ISIS, $(SUPPORT_CHIP))) + ifneq (ISISC, $(SUPPORT_CHIP)) + MODULE_INC += -I$(PRJ_PATH)/include/hsl/isis +--- a/src/api/api_access.c ++++ b/src/api/api_access.c +@@ -1,5 +1,8 @@ + /* + * Copyright (c) 2014,2018, The Linux Foundation. All rights reserved. ++ * ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -19,71 +22,7 @@ + #if (defined(KERNEL_MODULE)) + #include "hsl.h" + #include "hsl_dev.h" +-#if defined ATHENA +-#include "fal_igmp.h" +-#include "fal_leaky.h" +-#include "athena_mib.h" +-#include "athena_port_ctrl.h" +-#include "athena_portvlan.h" +-#include "athena_fdb.h" +-#include "athena_vlan.h" +-#include "athena_init.h" +-#include "athena_reg_access.h" +-#include "athena_reg.h" +-#elif defined GARUDA +-#include "garuda_mib.h" +-#include "garuda_qos.h" +-#include "garuda_rate.h" +-#include "garuda_port_ctrl.h" +-#include "garuda_portvlan.h" +-#include "garuda_fdb.h" +-#include "garuda_vlan.h" +-#include "garuda_mirror.h" +-#include "garuda_stp.h" +-#include "garuda_misc.h" +-#include "garuda_leaky.h" +-#include "garuda_igmp.h" +-#include "garuda_acl.h" +-#include "garuda_led.h" +-#include "garuda_init.h" +-#include "garuda_reg_access.h" +-#include "garuda_reg.h" +-#elif defined SHIVA +-#include "shiva_mib.h" +-#include "shiva_qos.h" +-#include "shiva_rate.h" +-#include "shiva_port_ctrl.h" +-#include "shiva_portvlan.h" +-#include "shiva_fdb.h" +-#include "shiva_vlan.h" +-#include "shiva_mirror.h" +-#include "shiva_stp.h" +-#include "shiva_misc.h" +-#include "shiva_leaky.h" +-#include "shiva_igmp.h" +-#include "shiva_acl.h" +-#include "shiva_led.h" +-#include "shiva_init.h" +-#include "shiva_reg_access.h" +-#include "shiva_reg.h" +-#elif defined HORUS +-#include "horus_mib.h" +-#include "horus_qos.h" +-#include "horus_rate.h" +-#include "horus_port_ctrl.h" +-#include "horus_portvlan.h" +-#include "horus_fdb.h" +-#include "horus_vlan.h" +-#include "horus_mirror.h" +-#include "horus_stp.h" +-#include "horus_misc.h" +-#include "horus_leaky.h" +-#include "horus_igmp.h" +-#include "horus_led.h" +-#include "horus_init.h" +-#include "horus_reg_access.h" +-#include "horus_reg.h" +-#elif defined ISIS ++#if defined ISIS + #include "isis_mib.h" + #include "isis_qos.h" + #include "isis_cosmap.h" +@@ -141,15 +80,7 @@ + /*qca808x_end*/ + #if (((!defined(USER_MODE)) && defined(KERNEL_MODULE)) || (defined(USER_MODE) && (!defined(KERNEL_MODULE)))) + #ifdef HSL_STANDALONG +-#if defined ATHENA +-#include "athena_api.h" +-#elif defined GARUDA +-#include "garuda_api.h" +-#elif defined SHIVA +-#include "shiva_api.h" +-#elif defined HORUS +-#include "horus_api.h" +-#elif defined ISIS ++#if defined ISIS + #include "isis_api.h" + #elif defined ISISC + #include "isisc_api.h" +@@ -159,15 +90,7 @@ + #include "fal_api.h" + #endif + #elif (defined(USER_MODE)) +-#if defined ATHENA +-#include "athena_api.h" +-#elif defined GARUDA +-#include "garuda_api.h" +-#elif defined SHIVA +-#include "shiva_api.h" +-#elif defined HORUS +-#include "horus_api.h" +-#elif defined ISIS ++#if defined ISIS + #include "isis_api.h" + #elif defined ISISC + #include "isisc_api.h" +--- a/src/shell/shell_config.c ++++ b/src/shell/shell_config.c +@@ -334,7 +334,6 @@ struct cmd_des_t gcmd_des[] = + "", SW_API_NESTVLAN_TPID_SET, NULL}, + {"sVlanTPID", "get", "get service VLAN tpid", + "", SW_API_NESTVLAN_TPID_GET, NULL}, +- /*shiva*/ + {"invlan", "set", "set port invlan mode", + " ", + SW_API_PT_IN_VLAN_MODE_SET, NULL}, +--- a/src/shell/shell_io.c ++++ b/src/shell/shell_io.c +@@ -11873,15 +11873,7 @@ _cmd_collect_shell_cfg(ssdk_cfg_t *shell + aos_mem_copy(shell_cfg->build_date, BUILD_DATE, sizeof(BUILD_DATE)); + #endif + +- if (ssdk_cfg.init_cfg.chip_type == CHIP_ATHENA) +- aos_mem_copy(shell_cfg->chip_type, "athena", sizeof("athena")); +- else if (ssdk_cfg.init_cfg.chip_type == CHIP_GARUDA) +- aos_mem_copy(shell_cfg->chip_type, "garuda", sizeof("garuda")); +- else if (ssdk_cfg.init_cfg.chip_type == CHIP_SHIVA) +- aos_mem_copy(shell_cfg->chip_type, "shiva", sizeof("shiva")); +- else if (ssdk_cfg.init_cfg.chip_type == CHIP_HORUS) +- aos_mem_copy(shell_cfg->chip_type, "horus", sizeof("horus")); +- else if (ssdk_cfg.init_cfg.chip_type == CHIP_ISIS) ++ if (ssdk_cfg.init_cfg.chip_type == CHIP_ISIS) + aos_mem_copy(shell_cfg->chip_type, "isis", sizeof("isis")); + else if (ssdk_cfg.init_cfg.chip_type == CHIP_ISISC) + aos_mem_copy(shell_cfg->chip_type, "isisc", sizeof("isisc")); +--- a/src/shell/shell_sw.c ++++ b/src/shell/shell_sw.c +@@ -113,34 +113,6 @@ cmd_show_fdb(a_ulong_t *arg_val) + cmd_print_error(rtn); + else + dprintf("\ntotal %d entries\n", cnt); +- }else if (ssdk_cfg.init_cfg.chip_type == CHIP_SHIVA) { +- sw_error_t rtn; +- a_uint32_t cnt = 0; +- fal_fdb_entry_t *fdb_entry = (fal_fdb_entry_t *) (ioctl_buf + 2); +- +- memset(fdb_entry, 0, sizeof (fal_fdb_entry_t)); +- arg_val[0] = SW_API_FDB_ITERATE; +- *(ioctl_buf + 1) = 0; +- +- while (1) +- { +- arg_val[1] = (a_ulong_t) ioctl_buf; +- arg_val[2] = get_devid(); +- arg_val[3] = (a_ulong_t) (ioctl_buf + 1); +- arg_val[4] = (a_ulong_t) fdb_entry; +- +- rtn = cmd_exec_api(arg_val); +- if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf))) +- { +- break; +- } +- cnt++; +- } +- +- if((rtn != SW_OK) && (rtn != SW_NO_MORE)) +- cmd_print_error(rtn); +- else +- dprintf("\ntotal %d entries\n", cnt); + }else { + sw_error_t rtn; + a_uint32_t cnt = 0; +@@ -228,12 +200,6 @@ cmd_show_vlan(a_ulong_t *arg_val) + case CHIP_DESS: + tmp_vid = FAL_NEXT_ENTRY_FIRST_ID; + break; +- case CHIP_ATHENA: +- case CHIP_GARUDA: +- case CHIP_SHIVA: +- case CHIP_HORUS: +- tmp_vid = 0; +- break; + default: + return SW_NOT_SUPPORTED; + } +--- a/include/fal/fal_port_ctrl.h ++++ b/include/fal/fal_port_ctrl.h +@@ -218,42 +218,63 @@ typedef enum { + } fal_port_auto_neg_status_t; + /*qca808x_start*/ + ++typedef enum { ++ PHY_INTERFACE_MODE_NA, ++ PHY_INTERFACE_MODE_INTERNAL, ++ PHY_INTERFACE_MODE_MII, ++ PHY_INTERFACE_MODE_GMII, ++ PHY_INTERFACE_MODE_SGMII, ++ PHY_INTERFACE_MODE_TBI, ++ PHY_INTERFACE_MODE_REVMII, ++ PHY_INTERFACE_MODE_RMII, ++ PHY_INTERFACE_MODE_REVRMII, ++ PHY_INTERFACE_MODE_RGMII, ++ PHY_INTERFACE_MODE_RGMII_ID, ++ PHY_INTERFACE_MODE_RGMII_RXID, ++ PHY_INTERFACE_MODE_RGMII_TXID, ++ PHY_INTERFACE_MODE_RTBI, ++ PHY_INTERFACE_MODE_SMII, ++ PHY_INTERFACE_MODE_XGMII, ++ PHY_INTERFACE_MODE_XLGMII, ++ PHY_INTERFACE_MODE_MOCA, ++ PHY_INTERFACE_MODE_PSGMII, ++ PHY_INTERFACE_MODE_QSGMII, ++ PHY_INTERFACE_MODE_TRGMII, ++ PHY_INTERFACE_MODE_100BASEX, ++ PHY_INTERFACE_MODE_1000BASEX, ++ PHY_INTERFACE_MODE_2500BASEX, ++ PHY_INTERFACE_MODE_5GBASER, ++ PHY_INTERFACE_MODE_RXAUI, ++ PHY_INTERFACE_MODE_XAUI, ++ PHY_INTERFACE_MODE_10GBASER, ++ PHY_INTERFACE_MODE_25GBASER, ++ PHY_INTERFACE_MODE_USXGMII, ++ PHY_INTERFACE_MODE_10GKR, ++ PHY_INTERFACE_MODE_QUSGMII, ++ PHY_INTERFACE_MODE_1000BASEKX, ++ PHY_INTERFACE_MODE_MAX, ++} phy_interface_t; ++ + /** Phy interface mode */ + typedef enum { +- PHY_PSGMII_BASET = 0, +- /**< PSGMII mode */ +- PHY_PSGMII_BX1000 = 1, +- /**< PSGMII BX1000 mode */ +- PHY_PSGMII_FX100 = 2, +- /**< PSGMII FX100 mode */ +- PHY_PSGMII_AMDET = 3, +- /**< PSGMII Auto mode */ +- PHY_SGMII_BASET = 4, ++ PHY_SGMII_BASET = PHY_INTERFACE_MODE_SGMII, + /**< SGMII mode */ +- PORT_QSGMII, ++ PORT_RGMII_BASET = PHY_INTERFACE_MODE_RGMII, ++ /**< RGMII mode */ ++ PHY_PSGMII_BASET = PHY_INTERFACE_MODE_PSGMII, ++ /**< PSGMII mode */ ++ PORT_QSGMII = PHY_INTERFACE_MODE_QSGMII, + /** ", ++ " ", + SW_API_PT_INTERFACE_MODE_SET, NULL}, + {"interfaceMode", "get", "get interface mode of phy", "", + SW_API_PT_INTERFACE_MODE_GET, NULL}, +--- a/src/shell/shell_io.c ++++ b/src/shell/shell_io.c +@@ -1840,20 +1840,8 @@ cmd_data_check_interface_mode(char *cmd_ + + if (!strncasecmp(cmd_str, "psgmii_baset", 13)) + *arg_val = PHY_PSGMII_BASET; +- else if (!strncasecmp(cmd_str, "psgmii_bx1000", 14)) +- *arg_val = PHY_PSGMII_BX1000; +- else if (!strncasecmp(cmd_str, "psgmii_fx100", 13)) +- *arg_val = PHY_PSGMII_FX100; +- else if (!strncasecmp(cmd_str, "psgmii_amdet", 13)) +- *arg_val = PHY_PSGMII_AMDET; +- else if (!strncasecmp(cmd_str, "rgmii_amdet", 13)) +- *arg_val = PORT_RGMII_AMDET; + else if (!strncasecmp(cmd_str, "rgmii_baset", 13)) + *arg_val = PORT_RGMII_BASET; +- else if (!strncasecmp(cmd_str, "rgmii_bx1000", 13)) +- *arg_val = PORT_RGMII_BX1000; +- else if (!strncasecmp(cmd_str, "rgmii_fx100", 13)) +- *arg_val = PORT_RGMII_FX100; + else if (!strncasecmp(cmd_str, "sgmii_baset", 13)) + *arg_val = PHY_SGMII_BASET; + else if (!strncasecmp(cmd_str, "qsgmii", 13)) +@@ -1866,12 +1854,8 @@ cmd_data_check_interface_mode(char *cmd_ + *arg_val = PORT_10GBASE_R; + else if (!strncasecmp(cmd_str, "sgmii_fiber", 20)) + *arg_val = PORT_SGMII_FIBER; +- else if (!strncasecmp(cmd_str, "psgmii_fiber", 20)) +- *arg_val = PHY_PSGMII_FIBER; + else if (!strncasecmp(cmd_str, "uqxgmii", 20)) + *arg_val = PORT_UQXGMII; +- else if (!strncasecmp(cmd_str, "uqxgmii_3channels", 20)) +- *arg_val = PORT_UQXGMII_3CHANNELS; + else if (!strncasecmp(cmd_str, "auto", 5)) + *arg_val = PORT_INTERFACE_MODE_AUTO; + else if (!strncasecmp(cmd_str, "interfacemode_max", 20)) +@@ -1893,34 +1877,10 @@ cmd_data_print_interface_mode(a_uint8_t + { + dprintf("PSGMII_BASET"); + } +- else if (*(a_uint32_t *) buf == PHY_PSGMII_BX1000) +- { +- dprintf("PSGMII_BX1000"); +- } +- else if (*(a_uint32_t *) buf == PHY_PSGMII_FX100) +- { +- dprintf("PSGMII_FX100"); +- } +- else if (*(a_uint32_t *) buf == PHY_PSGMII_AMDET) +- { +- dprintf("PSGMII_AMDET"); +- } +- else if (*(a_uint32_t *) buf == PORT_RGMII_AMDET) +- { +- dprintf("RGMII_AMDET"); +- } + else if (*(a_uint32_t *) buf == PORT_RGMII_BASET) + { + dprintf("RGMII_BASET"); + } +- else if (*(a_uint32_t *) buf == PORT_RGMII_BX1000) +- { +- dprintf("RGMII_BX1000"); +- } +- else if (*(a_uint32_t *) buf == PORT_RGMII_FX100) +- { +- dprintf("RGMII_FX100"); +- } + else if (*(a_uint32_t *) buf == PHY_SGMII_BASET) + { + dprintf("SGMII_BASET"); +@@ -1945,18 +1905,10 @@ cmd_data_print_interface_mode(a_uint8_t + { + dprintf("sgmii_fiber"); + } +- else if (*(a_uint32_t *) buf == PHY_PSGMII_FIBER) +- { +- dprintf("psgmii_fiber"); +- } + else if(*(a_uint32_t *) buf == PORT_UQXGMII) + { + dprintf("uqxgmii"); + } +- else if(*(a_uint32_t *) buf == PORT_UQXGMII_3CHANNELS) +- { +- dprintf("uqxgmii_3channels"); +- } + else if(*(a_uint32_t *) buf == PORT_INTERFACE_MODE_AUTO) + { + dprintf("auto");