From 92aa9ba8652e9d8d5524a631092611e20862f328 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 24 Jun 2022 20:08:48 +0200 Subject: [PATCH] nss-dp: edma-v1: add support for threaded napi Add support for threaded napi. Signed-off-by: Christian Marangi --- ...e-rx-napi-to-per-ring-implementation.patch | 267 ++++++++++++++++++ ...e-tx-napi-to-per-ring-implementation.patch | 206 ++++++++++++++ ...dma_v1-add-support-for-threaded-napi.patch | 112 ++++++++ 3 files changed, 585 insertions(+) create mode 100644 qca/qca-nss-dp/patches/0018-edma_v1-move-rx-napi-to-per-ring-implementation.patch create mode 100644 qca/qca-nss-dp/patches/0019-edma_v1-move-tx-napi-to-per-ring-implementation.patch create mode 100644 qca/qca-nss-dp/patches/0020-edma_v1-add-support-for-threaded-napi.patch diff --git a/qca/qca-nss-dp/patches/0018-edma_v1-move-rx-napi-to-per-ring-implementation.patch b/qca/qca-nss-dp/patches/0018-edma_v1-move-rx-napi-to-per-ring-implementation.patch new file mode 100644 index 0000000..0071312 --- /dev/null +++ b/qca/qca-nss-dp/patches/0018-edma_v1-move-rx-napi-to-per-ring-implementation.patch @@ -0,0 +1,267 @@ +From 21ffe52de4834569486619b93a059a7a92000827 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 24 Jun 2022 18:07:32 +0200 +Subject: [PATCH 18/21] edma_v1: move rx napi to per ring implementation + +Move rx napi to per ring implementation. + +Signed-off-by: Christian Marangi +--- + hal/dp_ops/edma_dp/edma_v1/edma_cfg.c | 1 + + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 25 +++++-- + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h | 4 +- + hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 76 +++++++------------- + 4 files changed, 47 insertions(+), 59 deletions(-) + +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c b/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c +index 2e98aaf..20d055e 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c +@@ -410,6 +410,7 @@ static int edma_setup_ring_resources(struct edma_hw *ehw) + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; ++ rxdesc_ring->ehw = ehw; + rxdesc_ring->count = EDMA_RING_SIZE; + rxdesc_ring->id = ehw->rxdesc_ring_start + i; + +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +index 8932f40..565564a 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +@@ -407,7 +407,9 @@ void edma_cleanup(bool is_dp_override) + synchronize_irq(edma_hw.misc_intr); + free_irq(edma_hw.misc_intr, (void *)(edma_hw.pdev)); + +- netif_napi_del(&edma_hw.rx_napi); ++ for (i = 0; i < edma_hw.rxdesc_rings; i++) ++ netif_napi_del(&edma_hw.rxdesc_ring[i].napi); ++ + netif_napi_del(&edma_hw.tx_napi); + edma_hw.napi_added = 0; + } +@@ -443,6 +445,8 @@ static int edma_if_open(struct nss_dp_data_plane_ctx *dpc, + uint32_t tx_desc_ring, uint32_t rx_desc_ring, + uint32_t mode) + { ++ int i; ++ + if (!dpc->dev) + return NSS_DP_FAILURE; + +@@ -452,7 +456,9 @@ static int edma_if_open(struct nss_dp_data_plane_ctx *dpc, + if (edma_hw.active++ != 0) + return NSS_DP_SUCCESS; + +- napi_enable(&edma_hw.rx_napi); ++ for (i = 0; i < edma_hw.rxdesc_rings; i++) ++ napi_enable(&edma_hw.rxdesc_ring[i].napi); ++ + napi_enable(&edma_hw.tx_napi); + + /* +@@ -469,6 +475,8 @@ static int edma_if_open(struct nss_dp_data_plane_ctx *dpc, + */ + static int edma_if_close(struct nss_dp_data_plane_ctx *dpc) + { ++ int i; ++ + if (--edma_hw.active != 0) + return NSS_DP_SUCCESS; + +@@ -480,7 +488,9 @@ static int edma_if_close(struct nss_dp_data_plane_ctx *dpc) + /* + * Disable NAPI + */ +- napi_disable(&edma_hw.rx_napi); ++ for (i = 0; i < edma_hw.rxdesc_rings; i++) ++ napi_disable(&edma_hw.rxdesc_ring[i].napi); ++ + napi_disable(&edma_hw.tx_napi); + return NSS_DP_SUCCESS; + } +@@ -749,7 +759,7 @@ static int edma_irq_init(void) + for (i = 0; i < edma_hw.rxdesc_rings; i++) { + err = request_irq(edma_hw.rxdesc_intr[i], + edma_rx_handle_irq, IRQF_SHARED, +- "edma_rxdesc", (void *)edma_hw.pdev); ++ "edma_rxdesc", (void *)&edma_hw.rxdesc_ring[i]); + if (err) { + pr_debug("RXDESC ring IRQ:%d request failed\n", + edma_hw.rxdesc_intr[i]); +@@ -814,6 +824,8 @@ rx_fill_ring_intr_req_fail: + */ + static int edma_register_netdevice(struct net_device *netdev, uint32_t macid) + { ++ int i; ++ + if (!netdev) { + pr_info("nss_dp_edma: Invalid netdev pointer %px\n", netdev); + return -EINVAL; +@@ -839,8 +851,9 @@ static int edma_register_netdevice(struct net_device *netdev, uint32_t macid) + * NAPI add + */ + if (!edma_hw.napi_added) { +- netif_napi_add(netdev, &edma_hw.rx_napi, edma_rx_napi, +- NAPI_POLL_WEIGHT); ++ for (i = 0; i < edma_hw.rxdesc_rings; i++) ++ netif_napi_add(netdev, &edma_hw.rxdesc_ring[i].napi, edma_rx_napi, ++ NAPI_POLL_WEIGHT); + + netif_tx_napi_add(netdev, &edma_hw.tx_napi, edma_tx_napi, + NAPI_POLL_WEIGHT); +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h +index a45fb99..01a6453 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h +@@ -116,6 +116,8 @@ struct edma_rxfill_ring { + * RxDesc ring + */ + struct edma_rxdesc_ring { ++ struct napi_struct napi; /* napi structure */ ++ struct edma_hw *ehw; + uint32_t id; /* RXDESC ring number */ + struct edma_rxfill_ring *rxfill; /* RXFILL ring used */ + void *desc; /* descriptor ring virtual address */ +@@ -172,8 +174,6 @@ enum edma_tx { + * EDMA private data structure + */ + struct edma_hw { +- struct napi_struct rx_napi; +- /* napi structure */ + struct napi_struct tx_napi; + /* napi structure */ + struct net_device *netdev_arr[EDMA_MAX_GMACS]; +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +index 1fb8cbf..1d2fa8a 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +@@ -427,7 +427,7 @@ static uint32_t edma_clean_rx(struct edma_hw *ehw, + nss_phy_tstamp_rx_buf(ndev, skb); + else + #if defined(NSS_DP_ENABLE_NAPI_GRO) +- napi_gro_receive(&ehw->napi, skb); ++ napi_gro_receive(&rxdesc_ring->napi, skb); + #else + netif_receive_skb(skb); + #endif +@@ -462,17 +462,13 @@ next_rx_desc: + */ + int edma_rx_napi(struct napi_struct *napi, int budget) + { +- struct edma_hw *ehw = container_of(napi, struct edma_hw, rx_napi); +- struct edma_rxdesc_ring *rxdesc_ring = NULL; +- struct edma_rxfill_ring *rxfill_ring = NULL; ++ struct edma_rxdesc_ring *rxdesc_ring = container_of(napi, struct edma_rxdesc_ring, napi); ++ struct edma_rxfill_ring *rxfill_ring = rxdesc_ring->rxfill; ++ struct edma_hw *ehw = rxdesc_ring->ehw; + + int work_done = 0; +- int i; + +- for (i = 0; i < ehw->rxdesc_rings; i++) { +- rxdesc_ring = &ehw->rxdesc_ring[i]; +- work_done += edma_clean_rx(ehw, budget, rxdesc_ring); +- } ++ work_done += edma_clean_rx(ehw, budget, rxdesc_ring); + + /* + * TODO - rework and fix the budget control +@@ -486,22 +482,15 @@ int edma_rx_napi(struct napi_struct *napi, int budget) + /* + * Set RXDESC ring interrupt mask + */ +- for (i = 0; i < ehw->rxdesc_rings; i++) { +- rxdesc_ring = &ehw->rxdesc_ring[i]; +- edma_reg_write( +- EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id), +- ehw->rxdesc_intr_mask); +- } ++ edma_reg_write( ++ EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id), ++ ehw->rxdesc_intr_mask); + + /* + * Set RXFILL ring interrupt mask + */ +- for (i = 0; i < ehw->rxfill_rings; i++) { +- rxfill_ring = &ehw->rxfill_ring[i]; +- edma_reg_write(EDMA_REG_RXFILL_INT_MASK( +- rxfill_ring->id), +- edma_hw.rxfill_intr_mask); +- } ++ edma_reg_write(EDMA_REG_RXFILL_INT_MASK(rxfill_ring->id), ++ edma_hw.rxfill_intr_mask); + } + return work_done; + } +@@ -761,51 +750,36 @@ irqreturn_t edma_handle_misc_irq(int irq, void *ctx) + */ + irqreturn_t edma_rx_handle_irq(int irq, void *ctx) + { +- uint32_t reg_data = 0; ++ struct edma_rxdesc_ring *rxdesc_ring = (struct edma_rxdesc_ring *)ctx; + uint32_t rxdesc_intr_status = 0; +- int i; +- struct edma_rxdesc_ring *rxdesc_ring = NULL; +- struct edma_hw *ehw = NULL; +- struct platform_device *pdev = (struct platform_device *)ctx; +- +- ehw = platform_get_drvdata(pdev); +- if (!ehw) { +- pr_info("Unable to retrieve platrofm data"); +- return IRQ_HANDLED; +- } ++ uint32_t reg_data = 0; + + /* + * Read RxDesc intr status + */ +- for (i = 0; i < ehw->rxdesc_rings; i++) { +- rxdesc_ring = &ehw->rxdesc_ring[i]; +- reg_data = edma_reg_read( +- EDMA_REG_RXDESC_INT_STAT(rxdesc_ring->id)); +- rxdesc_intr_status |= reg_data & +- EDMA_RXDESC_RING_INT_STATUS_MASK; ++ reg_data = edma_reg_read( ++ EDMA_REG_RXDESC_INT_STAT(rxdesc_ring->id)); ++ rxdesc_intr_status |= reg_data & ++ EDMA_RXDESC_RING_INT_STATUS_MASK; + +- /* +- * Disable RxDesc intr +- */ +- edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id), +- EDMA_MASK_INT_DISABLE); +- } ++ /* ++ * Disable RxDesc intr ++ */ ++ edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id), ++ EDMA_MASK_INT_DISABLE); + + if (rxdesc_intr_status == 0) + return IRQ_NONE; + +- for (i = 0; i < ehw->rxdesc_rings; i++) { +- rxdesc_ring = &ehw->rxdesc_ring[i]; +- edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id), +- EDMA_MASK_INT_DISABLE); +- } ++ edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id), ++ EDMA_MASK_INT_DISABLE); + + /* + *TODO - per core NAPI + */ + if (rxdesc_intr_status) +- if (likely(napi_schedule_prep(&ehw->rx_napi))) +- __napi_schedule(&ehw->rx_napi); ++ if (likely(napi_schedule_prep(&rxdesc_ring->napi))) ++ __napi_schedule(&rxdesc_ring->napi); + + return IRQ_HANDLED; + } +-- +2.36.1 + diff --git a/qca/qca-nss-dp/patches/0019-edma_v1-move-tx-napi-to-per-ring-implementation.patch b/qca/qca-nss-dp/patches/0019-edma_v1-move-tx-napi-to-per-ring-implementation.patch new file mode 100644 index 0000000..da9e520 --- /dev/null +++ b/qca/qca-nss-dp/patches/0019-edma_v1-move-tx-napi-to-per-ring-implementation.patch @@ -0,0 +1,206 @@ +From de169603dcfa7a33026587c4cef9938cc6c28b1e Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 24 Jun 2022 18:25:16 +0200 +Subject: [PATCH 19/21] edma_v1: move tx napi to per ring implementation + +Move tx napi to per ring implementation. + +Signed-off-by: Christian Marangi +--- + hal/dp_ops/edma_dp/edma_v1/edma_cfg.c | 1 + + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 17 +++--- + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h | 4 +- + hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 55 +++++++------------- + 4 files changed, 32 insertions(+), 45 deletions(-) + +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c b/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c +index 20d055e..6f2c082 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c +@@ -373,6 +373,7 @@ static int edma_setup_ring_resources(struct edma_hw *ehw) + */ + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; ++ txcmpl_ring->ehw = ehw; + txcmpl_ring->count = EDMA_RING_SIZE; + txcmpl_ring->id = ehw->txcmpl_ring_start + i; + +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +index 565564a..49c7f8c 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +@@ -410,7 +410,8 @@ void edma_cleanup(bool is_dp_override) + for (i = 0; i < edma_hw.rxdesc_rings; i++) + netif_napi_del(&edma_hw.rxdesc_ring[i].napi); + +- netif_napi_del(&edma_hw.tx_napi); ++ for (i = 0; i < edma_hw.txcmpl_rings; i++) ++ netif_napi_del(&edma_hw.txcmpl_ring[i].napi); + edma_hw.napi_added = 0; + } + +@@ -459,7 +460,8 @@ static int edma_if_open(struct nss_dp_data_plane_ctx *dpc, + for (i = 0; i < edma_hw.rxdesc_rings; i++) + napi_enable(&edma_hw.rxdesc_ring[i].napi); + +- napi_enable(&edma_hw.tx_napi); ++ for (i = 0; i < edma_hw.txcmpl_rings; i++) ++ napi_enable(&edma_hw.txcmpl_ring[i].napi); + + /* + * Enable the interrupt masks. +@@ -491,7 +493,9 @@ static int edma_if_close(struct nss_dp_data_plane_ctx *dpc) + for (i = 0; i < edma_hw.rxdesc_rings; i++) + napi_disable(&edma_hw.rxdesc_ring[i].napi); + +- napi_disable(&edma_hw.tx_napi); ++ for (i = 0; i < edma_hw.txcmpl_rings; i++) ++ napi_disable(&edma_hw.txcmpl_ring[i].napi); ++ + return NSS_DP_SUCCESS; + } + +@@ -730,7 +734,7 @@ static int edma_irq_init(void) + for (i = 0; i < edma_hw.txcmpl_rings; i++) { + err = request_irq(edma_hw.txcmpl_intr[i], + edma_tx_handle_irq, IRQF_SHARED, +- "edma_txcmpl", (void *)edma_hw.pdev); ++ "edma_txcmpl", (void *)&edma_hw.txcmpl_ring[i]); + if (err) { + pr_debug("TXCMPL ring IRQ:%d request failed\n", + edma_hw.txcmpl_intr[i]); +@@ -855,8 +859,9 @@ static int edma_register_netdevice(struct net_device *netdev, uint32_t macid) + netif_napi_add(netdev, &edma_hw.rxdesc_ring[i].napi, edma_rx_napi, + NAPI_POLL_WEIGHT); + +- netif_tx_napi_add(netdev, &edma_hw.tx_napi, edma_tx_napi, +- NAPI_POLL_WEIGHT); ++ for (i = 0; i < edma_hw.txcmpl_rings; i++) ++ netif_tx_napi_add(netdev, &edma_hw.txcmpl_ring[i].napi, edma_tx_napi, ++ NAPI_POLL_WEIGHT); + /* + * Register the interrupt handlers and enable interrupts + */ +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h +index 01a6453..8ec7e35 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h +@@ -95,6 +95,8 @@ struct edma_txdesc_ring { + * TxCmpl ring + */ + struct edma_txcmpl_ring { ++ struct napi_struct napi; /* napi structure */ ++ struct edma_hw *ehw; + uint32_t id; /* TXCMPL ring number */ + void *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ +@@ -174,8 +176,6 @@ enum edma_tx { + * EDMA private data structure + */ + struct edma_hw { +- struct napi_struct tx_napi; +- /* napi structure */ + struct net_device *netdev_arr[EDMA_MAX_GMACS]; + /* netdev for each gmac port */ + struct device_node *device_node; +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +index 1d2fa8a..8221a9c 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +@@ -501,17 +501,14 @@ int edma_rx_napi(struct napi_struct *napi, int budget) + */ + int edma_tx_napi(struct napi_struct *napi, int budget) + { +- struct edma_hw *ehw = container_of(napi, struct edma_hw, tx_napi); +- struct edma_txcmpl_ring *txcmpl_ring = NULL; ++ struct edma_txcmpl_ring *txcmpl_ring = container_of(napi, struct edma_txcmpl_ring, napi); ++ struct edma_hw *ehw = txcmpl_ring->ehw; + + struct net_device *ndev; + int work_done = 0; + int i; + +- for (i = 0; i < ehw->txcmpl_rings; i++) { +- txcmpl_ring = &ehw->txcmpl_ring[i]; +- edma_clean_tx(ehw, txcmpl_ring); +- } ++ edma_clean_tx(ehw, txcmpl_ring); + + /* + * Resume netdev Tx queue +@@ -542,12 +539,8 @@ int edma_tx_napi(struct napi_struct *napi, int budget) + /* + * Set TXCMPL ring interrupt mask + */ +- for (i = 0; i < ehw->txcmpl_rings; i++) { +- txcmpl_ring = &ehw->txcmpl_ring[i]; +- edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id), +- ehw->txcmpl_intr_mask); +- } +- ++ edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id), ++ ehw->txcmpl_intr_mask); + } + return work_done; + } +@@ -790,35 +783,23 @@ irqreturn_t edma_rx_handle_irq(int irq, void *ctx) + */ + irqreturn_t edma_tx_handle_irq(int irq, void *ctx) + { +- uint32_t reg_data = 0; ++ struct edma_txcmpl_ring *txcmpl_ring = (struct edma_txcmpl_ring *)ctx; + uint32_t txcmpl_intr_status = 0; +- int i; +- struct edma_txcmpl_ring *txcmpl_ring = NULL; +- struct edma_hw *ehw = NULL; +- struct platform_device *pdev = (struct platform_device *)ctx; +- +- ehw = platform_get_drvdata(pdev); +- if (!ehw) { +- pr_info("Unable to retrieve platrofm data"); +- return IRQ_HANDLED; +- } ++ uint32_t reg_data = 0; + + /* + * Read TxCmpl intr status + */ +- for (i = 0; i < ehw->txcmpl_rings; i++) { +- txcmpl_ring = &ehw->txcmpl_ring[i]; +- reg_data = edma_reg_read( +- EDMA_REG_TX_INT_STAT(txcmpl_ring->id)); +- txcmpl_intr_status |= reg_data & +- EDMA_TXCMPL_RING_INT_STATUS_MASK; ++ reg_data = edma_reg_read( ++ EDMA_REG_TX_INT_STAT(txcmpl_ring->id)); ++ txcmpl_intr_status |= reg_data & ++ EDMA_TXCMPL_RING_INT_STATUS_MASK; + +- /* +- * Disable TxCmpl intr +- */ +- edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id), +- EDMA_MASK_INT_DISABLE); +- } ++ /* ++ * Disable TxCmpl intr ++ */ ++ edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id), ++ EDMA_MASK_INT_DISABLE); + + if (txcmpl_intr_status == 0) + return IRQ_NONE; +@@ -827,8 +808,8 @@ irqreturn_t edma_tx_handle_irq(int irq, void *ctx) + *TODO - per core NAPI + */ + if (txcmpl_intr_status) +- if (likely(napi_schedule_prep(&ehw->tx_napi))) +- __napi_schedule(&ehw->tx_napi); ++ if (likely(napi_schedule_prep(&txcmpl_ring->napi))) ++ __napi_schedule(&txcmpl_ring->napi); + + return IRQ_HANDLED; + } +-- +2.36.1 + diff --git a/qca/qca-nss-dp/patches/0020-edma_v1-add-support-for-threaded-napi.patch b/qca/qca-nss-dp/patches/0020-edma_v1-add-support-for-threaded-napi.patch new file mode 100644 index 0000000..64682fe --- /dev/null +++ b/qca/qca-nss-dp/patches/0020-edma_v1-add-support-for-threaded-napi.patch @@ -0,0 +1,112 @@ +From 0f7bf6cf6fd536cd5965d596067e469e84559761 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 24 Jun 2022 20:04:17 +0200 +Subject: [PATCH 20/21] edma_v1: add support for threaded napi + +Add required changed to enable threaded napi. Also change rxfill to use +napi_alloc_skb. + +Signed-off-by: Christian Marangi +--- + hal/dp_ops/edma_dp/edma_v1/edma_cfg.c | 5 ----- + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 12 ++++++++++-- + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h | 4 ++-- + hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 7 ++++--- + 4 files changed, 16 insertions(+), 12 deletions(-) + +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c b/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c +index 6f2c082..33f4297 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c +@@ -670,11 +670,6 @@ static void edma_configure_rxfill_ring(struct edma_hw *ehw, + + data = rxfill_ring->count & EDMA_RXFILL_RING_SIZE_MASK; + edma_reg_write(EDMA_REG_RXFILL_RING_SIZE(rxfill_ring->id), data); +- +- /* +- * Alloc Rx buffers +- */ +- edma_alloc_rx_buffer(ehw, rxfill_ring); + } + + /* +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +index 49c7f8c..3736254 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +@@ -457,8 +457,15 @@ static int edma_if_open(struct nss_dp_data_plane_ctx *dpc, + if (edma_hw.active++ != 0) + return NSS_DP_SUCCESS; + +- for (i = 0; i < edma_hw.rxdesc_rings; i++) +- napi_enable(&edma_hw.rxdesc_ring[i].napi); ++ for (i = 0; i < edma_hw.rxdesc_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring = &edma_hw.rxdesc_ring[i]; ++ /* ++ * Alloc Rx buffers ++ */ ++ edma_alloc_rx_buffer(&edma_hw, &rxdesc_ring->napi, rxdesc_ring->rxfill); ++ ++ napi_enable(&rxdesc_ring->napi); ++ } + + for (i = 0; i < edma_hw.txcmpl_rings; i++) + napi_enable(&edma_hw.txcmpl_ring[i].napi); +@@ -899,6 +906,7 @@ static int edma_if_init(struct nss_dp_data_plane_ctx *dpc) + * Headroom needed for Tx preheader + */ + netdev->needed_headroom += EDMA_TX_PREHDR_SIZE; ++ dev_set_threaded(netdev, true); + + return NSS_DP_SUCCESS; + } +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h +index 8ec7e35..7f8a8d4 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h +@@ -276,8 +276,8 @@ extern struct edma_hw edma_hw; + uint32_t edma_reg_read(uint32_t reg_off); + void edma_reg_write(uint32_t reg_off, uint32_t val); + +-int edma_alloc_rx_buffer(struct edma_hw *ehw, +- struct edma_rxfill_ring *rxfill_ring); ++int edma_alloc_rx_buffer(struct edma_hw *ehw, struct napi_struct *napi, ++ struct edma_rxfill_ring *rxfill_ring); + enum edma_tx edma_ring_xmit(struct edma_hw *ehw, + struct net_device *netdev, + struct sk_buff *skb, +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +index 8221a9c..001f883 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +@@ -29,7 +29,8 @@ + * Alloc Rx buffers for one RxFill ring + */ + int edma_alloc_rx_buffer(struct edma_hw *ehw, +- struct edma_rxfill_ring *rxfill_ring) ++ struct napi_struct *napi, ++ struct edma_rxfill_ring *rxfill_ring) + { + struct platform_device *pdev = ehw->pdev; + struct sk_buff *skb; +@@ -64,7 +65,7 @@ int edma_alloc_rx_buffer(struct edma_hw *ehw, + /* + * Allocate buffer + */ +- skb = dev_alloc_skb(alloc_size); ++ skb = napi_alloc_skb(napi, alloc_size); + if (unlikely(!skb)) + break; + +@@ -445,7 +446,7 @@ next_rx_desc: + work_done++; + } + +- edma_alloc_rx_buffer(ehw, rxdesc_ring->rxfill); ++ edma_alloc_rx_buffer(ehw, &rxdesc_ring->napi, rxdesc_ring->rxfill); + + /* + * make sure the consumer index is updated +-- +2.36.1 +