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Merge branch openwrt:main into main

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This commit is contained in:
King-Of-Knights 2025-02-19 22:33:27 +08:00
commit 760971a492
629 changed files with 48773 additions and 4753 deletions
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6
.github/labeler.yml vendored
View File

@ -80,6 +80,12 @@
- changed-files:
- any-glob-to-any-file:
- "target/linux/qualcommax/**"
- "package/kernel/qca-ssdk/**"
- "package/kernel/qca-nss-dp/**"
"target/qualcommbe":
- changed-files:
- any-glob-to-any-file:
- "target/linux/qualcommbe/**"
"target/ixp4xx":
- changed-files:
- any-glob-to-any-file:

2
include/bpf.mk
View File

@ -1,4 +1,4 @@
BPF_DEPENDS := @HAS_BPF_TOOLCHAIN
BPF_DEPENDS := @HAS_BPF_TOOLCHAIN +@NEED_BPF_TOOLCHAIN
LLVM_VER:=
CLANG_MIN_VER:=12

4
include/kernel-6.6
View File

@ -1,2 +1,2 @@
LINUX_VERSION-6.6 = .74
LINUX_KERNEL_HASH-6.6.74 = f15e2b1a8bab0eba494b07858a5abc88d8f788e25f6fe4a572a77840bbd5494d
LINUX_VERSION-6.6 = .77
LINUX_KERNEL_HASH-6.6.77 = 081089dfcf125aef67aa940ebb995ff789b646129f5d4b2365e1d5685b29a84e

3
include/version.mk
View File

@ -6,6 +6,9 @@
# Substituted by SDK, do not remove
# REVISION:=x
# SOURCE_DATE_EPOCH:=x
# BASE_FILES_VERSION:=x
# KERNEL_VERSION:=x
# LIBC_VERSION:=x
PKG_CONFIG_DEPENDS += \
CONFIG_VERSION_HOME_URL \

8
package/Makefile
View File

@ -100,7 +100,11 @@ ifneq ($(CONFIG_USE_APK),)
$(foreach pkg,$(shell cat $(PACKAGE_INSTALL_FILES) 2>/dev/null),$(pkg)$(call GetABISuffix,$(pkg))))
$(call apk,$(TARGET_DIR)) add --no-cache --initdb --no-scripts --arch $(ARCH_PACKAGES) \
--repositories-file /dev/null --repository file://$(PACKAGE_DIR_ALL)/packages.adb \
$$(cat $(TMP_DIR)/apk_install_list)
$$(cat $(TMP_DIR)/apk_install_list) \
"base-files=$(shell cat $(TMP_DIR)/base-files.version)" \
"libc=$(shell cat $(TMP_DIR)/libc.version)" \
"kernel=$(shell cat $(TMP_DIR)/kernel.version)"
rm -rf $(TARGET_DIR)/run
else
$(file >$(TMP_DIR)/opkg_install_list,\
@ -131,7 +135,7 @@ ifneq ($(CONFIG_USE_APK),)
--keys-dir $(TOPDIR) \
--sign $(BUILD_KEY_APK_SEC) \
--output packages.adb \
$$(ls *.apk | grep -vE '^(base-files-|kernel-|libc-)'); \
*.apk; \
echo -n '{"architecture": "$(ARCH_PACKAGES)", "packages":{' > index.json; \
$(STAGING_DIR_HOST)/bin/apk adbdump packages.adb | \
awk '/- name: / {pkg = $$NF} ; / version: / {printf "\"%s\": \"%s\", ", pkg, $$NF}' | \

1
package/base-files/Makefile
View File

@ -256,6 +256,7 @@ ifneq ($(CONFIG_USE_APK),)
rm -f $(1)/etc/uci-defaults/13_fix-group-user
rm -f $(1)/sbin/pkg_check
echo $(PKG_RELEASE)~$(lastword $(subst -, ,$(REVISION))) >$(TMP_DIR)/base-files.version
else
$(if $(CONFIG_CLEAN_IPKG),, \
mkdir -p $(1)/etc/opkg; \

4
package/base-files/files/lib/functions/caldata.sh
View File

@ -125,8 +125,8 @@ caldata_valid() {
caldata_patch_data() {
local data=$1
local data_count=$((${#1} / 2))
local data_offset=$(($2))
local chksum_offset=$(($3))
[ -n "$2" ] && local data_offset=$(($2))
[ -n "$3" ] && local chksum_offset=$(($3))
local target=$4
local fw_data
local fw_chksum

7
package/boot/arm-trusted-firmware-tools/Makefile
View File

@ -8,9 +8,9 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=arm-trusted-firmware-tools
PKG_VERSION:=2.9
PKG_VERSION:=2.12
PKG_RELEASE:=1
PKG_HASH:=76a66a1de0c01aeb83dfc7b72b51173fe62c6e51d6fca17cc562393117bed08b
PKG_HASH:=b4c047493cac1152203e1ba121ae57267e4899b7bf56eb365e22a933342d31c9
PKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>
PKG_HOST_ONLY:=1
@ -33,7 +33,8 @@ define Host/Compile
$(MAKE) -C \
$(HOST_BUILD_DIR)/tools/fiptool \
CPPFLAGS="$(HOST_CFLAGS)" \
LDFLAGS="$(HOST_LDFLAGS)"
LDFLAGS="$(HOST_LDFLAGS)" \
OPENSSL_DIR="$(STAGING_DIR_HOST)"
endef
define Host/Install

14
package/boot/arm-trusted-firmware-tools/patches/001-respect-LDFLAGS.patch
View File

@ -1,11 +1,11 @@
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -38,7 +38,7 @@
@@ -74,7 +74,7 @@ all: --openssl ${PROJECT}
${PROJECT}: ${OBJECTS} Makefile
@echo " HOSTLD $@"
- ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS}
+ ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} $(LDFLAGS)
@${ECHO_BLANK_LINE}
@echo "Built $@ successfully"
@${ECHO_BLANK_LINE}
$(s)echo " HOSTLD $@"
- $(q)$(host-cc) ${OBJECTS} -o $@ $(LDOPTS)
+ $(q)$(host-cc) ${OBJECTS} -o $@ $(LDOPTS) $(LDFLAGS)
$(s)echo
$(s)echo "Built $@ successfully"
$(s)echo

21
package/boot/arm-trusted-firmware-tools/patches/002-darwin_compile.patch
View File

@ -1,15 +1,6 @@
--- a/tools/fiptool/fiptool.c
+++ b/tools/fiptool/fiptool.c
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-
+#define _DARWIN_C_SOURCE
#ifndef _MSC_VER
#include <sys/mount.h>
#endif
@@ -18,6 +18,9 @@
@@ -19,6 +19,9 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
@ -19,3 +10,13 @@
#include "fiptool.h"
#include "tbbr_config.h"
--- a/tools/fiptool/fiptool_platform.h
+++ b/tools/fiptool/fiptool_platform.h
@@ -12,6 +12,7 @@
#ifndef FIPTOOL_PLATFORM_H
#define FIPTOOL_PLATFORM_H
+#define _DARWIN_C_SOURCE
#ifndef _MSC_VER
/* Not Visual Studio, so include Posix Headers. */

6
package/boot/imx-bootlets/Makefile
View File

@ -7,11 +7,11 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=imx-bootlets
PKG_VERSION:=10.05.02
PKG_VERSION:=10.12.01
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=http://trabant.uid0.hu/openwrt/
PKG_HASH:=09ecd81a64db5166a235932146faf08d0689bfc7ac04ac9fcc3a5bd809fba74a
PKG_HASH:=f7c98cbc41e15184cad61c56115e840e34ac3ebb4a162fadeea905e5038fd65b
PKG_FLAGS:=nonshared
@ -37,7 +37,7 @@ define Package/imx-bootlets/install
$(INSTALL_BIN) $(PKG_BUILD_DIR)/boot_prep/boot_prep $(STAGING_DIR)/boot_prep
$(INSTALL_BIN) $(PKG_BUILD_DIR)/linux_prep/output-target/linux_prep $(STAGING_DIR)/linux_prep
$(INSTALL_BIN) $(PKG_BUILD_DIR)/power_prep/power_prep $(STAGING_DIR)/power_prep
$(INSTALL_BIN) $(PKG_BUILD_DIR)/linux_prebuilt.db $(STAGING_DIR)/linux_prebuilt.db
$(INSTALL_BIN) $(PKG_BUILD_DIR)/linux_ivt.bd $(STAGING_DIR)/linux_ivt.bd
endef
$(eval $(call BuildPackage,imx-bootlets))

22
package/boot/imx-bootlets/patches/001-skip_sb_generation.patch
View File

@ -1,18 +1,22 @@
--- a/Makefile
+++ b/Makefile
@@ -32,10 +32,11 @@ ifeq "$(DFT_IMAGE)" "$(wildcard $(DFT_IM
sed -i 's,[^ *]image.*;,\timage="$(DFT_UBOOT)";,' uboot.db
elftosb2 -z -c ./uboot.db -o i$(ARCH)_uboot.sb
@@ -37,13 +37,13 @@ ifeq "$(DFT_IMAGE)" "$(wildcard $(DFT_IM
elftosb -z -c ./uboot.bd -o i$(ARCH)_uboot.sb
elftosb -z -f imx28 -c ./uboot_ivt.bd -o i$(ARCH)_ivt_uboot.sb
else
- @echo "by using the pre-built kernel"
- elftosb2 -z -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb
- @echo "generating U-Boot boot stream image"
- elftosb2 -z -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb
- elftosb -z -c ./linux.bd -o i$(ARCH)_linux.sb
- elftosb -z -f imx28 -c ./linux_ivt.bd -o i$(ARCH)_ivt_linux.sb
+ @echo "... not generating any image for now."
+ #@echo "by using the pre-built kernel"
+ #elftosb2 -z -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb
+ #elftosb -z -c ./linux.bd -o i$(ARCH)_linux.sb
+ #elftosb -z -f imx28 -c ./linux_ivt.bd -o i$(ARCH)_ivt_linux.sb
- @echo "generating U-Boot boot stream image"
- elftosb -z -c ./uboot.bd -o i$(ARCH)_uboot.sb
- elftosb -z -f imx28 -c ./uboot_ivt.bd -o i$(ARCH)_ivt_uboot.sb
+ #@echo "generating U-Boot boot stream image"
+ #elftosb2 -z -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb
+ #elftosb -z -c ./uboot.bd -o i$(ARCH)_uboot.sb
+ #elftosb -z -f imx28 -c ./uboot_ivt.bd -o i$(ARCH)_ivt_uboot.sb
endif
#@echo "generating kernel bootstream file sd_mmc_bootstream.raw"
#Please use cfimager to burn xxx_linux.sb. The below way will no

8
package/boot/imx-bootlets/patches/002-set_elftosb_config.patch
View File

@ -1,5 +1,5 @@
--- a/linux_prebuilt.db
+++ b/linux_prebuilt.db
--- a/linux_ivt.bd
+++ b/linux_ivt.bd
@@ -4,10 +4,10 @@ options {
flags = 0x01;
}
@ -7,11 +7,11 @@
- power_prep="./power_prep/power_prep";
- sdram_prep="./boot_prep/boot_prep";
- linux_prep="./linux_prep/output-target/linux_prep";
- zImage = "./zImage";
- zImage="./zImage";
+ power_prep="./power_prep";
+ sdram_prep="./boot_prep";
+ linux_prep="./linux_prep";
+ zImage = "./zImage_dtb";
+ zImage="./zImage_dtb";
}
section (0) {

13
package/boot/imx-bootlets/patches/003-add-olinuxino.patch
View File

@ -121,7 +121,7 @@
all: build_prep gen_bootstream
@@ -94,6 +97,8 @@ distclean: clean
@@ -101,6 +104,8 @@ distclean: clean
clean:
-rm -rf *.sb
rm -f sd_mmc_bootstream.raw
@ -130,14 +130,3 @@
$(MAKE) -C linux_prep clean ARCH=$(ARCH)
$(MAKE) -C boot_prep clean ARCH=$(ARCH)
$(MAKE) -C power_prep clean ARCH=$(ARCH)
--- a/uboot.db
+++ b/uboot.db
@@ -3,7 +3,7 @@
sources {
power_prep="./power_prep/power_prep";
sdram_prep="./boot_prep/boot_prep";
- image="/home/b18647/repos/ltib_latest/rootfs/boot/u-boot";
+ image="../boot/u-boot";
}
section (0) {

11
package/boot/imx-bootlets/patches/004-fix-ARM-8933_1.patch Normal file
View File

@ -0,0 +1,11 @@
--- a/linux_prep/core/cmdlines.S
+++ b/linux_prep/core/cmdlines.S
@@ -14,7 +14,7 @@
#define CMDLINES_FILE "output-target/command_lines_stripped.txt"
#endif
- .section .cmdlines, #alloc
+ .section .cmdlines, "a"
.globl cmdlines_start
cmdlines_start:
.incbin CMDLINES_FILE

8
package/boot/opensbi/Makefile
View File

@ -6,13 +6,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=opensbi
PKG_RELEASE:=1.4
PKG_RELEASE:=1.6
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/riscv/opensbi
PKG_SOURCE_DATE:=2023-12-24
PKG_SOURCE_VERSION:=a2b255b88918715173942f2c5e1f97ac9e90c877
PKG_MIRROR_HASH:=a81d7b3622feba80b2a45fe0d38600be73cfbee64a0426be82a71545c10c54d3
PKG_SOURCE_DATE:=2024-12-24
PKG_SOURCE_VERSION:=bd613dd92113f683052acfb23d9dc8ba60029e0a
PKG_MIRROR_HASH:=247bbb751635d9414cf47cce417185fd3323e98c524eafa825dc91b76cc5c054
PKG_BUILD_DIR=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)

23
package/boot/uboot-envtools/files/qualcommax_ipq50xx Normal file
View File

@ -0,0 +1,23 @@
[ -e /etc/config/ubootenv ] && exit 0
touch /etc/config/ubootenv
. /lib/uboot-envtools.sh
. /lib/functions.sh
board=$(board_name)
case "$board" in
linksys,mx2000|\
linksys,mx5500|\
linksys,spnmx56)
idx="$(find_mtd_index u_env)"
[ -n "$idx" ] && \
ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000"
;;
esac
config_load ubootenv
config_foreach ubootenv_add_app_config
exit 0

11
package/boot/uboot-envtools/files/qualcommax_ipq807x
View File

@ -26,6 +26,12 @@ ubootenv_add_mmc() {
}
case "$board" in
aliyun,ap8220|\
compex,wpq873|\
edgecore,eap102|\
zyxel,nbg7815)
ubootenv_add_mtd "0:appsblenv" "0x0" "0x10000" "0x10000"
;;
dynalink,dl-wrx36|\
netgear,rax120v2|\
netgear,sxr80|\
@ -37,11 +43,6 @@ tplink,eap620hd-v1|\
tplink,eap660hd-v1)
ubootenv_add_mtd "0:appsblenv" "0x0" "0x40000" "0x20000"
;;
compex,wpq873|\
edgecore,eap102|\
zyxel,nbg7815)
ubootenv_add_mtd "0:appsblenv" "0x0" "0x10000" "0x10000"
;;
edimax,cax1800)
ubootenv_add_mtd "0:appsblenv" "0x0" "0x10000" "0x20000"
;;

1
package/boot/uboot-envtools/files/realtek
View File

@ -28,6 +28,7 @@ zyxel,gs1900-10hp|\
zyxel,gs1900-16|\
zyxel,gs1900-24-v1|\
zyxel,gs1900-24e|\
zyxel,gs1900-24ep|\
zyxel,gs1900-24hp-v1|\
zyxel,gs1900-24hp-v2)
idx="$(find_mtd_index u-boot-env)"

4
package/boot/uboot-mediatek/Makefile
View File

@ -1,8 +1,8 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2024.10
PKG_HASH:=b28daf4ac17e43156363078bf510297584137f6df50fced9b12df34f61a92fb0
PKG_VERSION:=2025.01
PKG_HASH:=cdef7d507c93f1bbd9f015ea9bc21fa074268481405501945abc6f854d5b686f
PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host
UBOOT_USE_INTREE_DTC:=1

63
package/boot/uboot-mediatek/patches/010-menu-fix-the-logic-checking-whether-ESC-key-is-press.patch
View File

@ -1,63 +0,0 @@
From 72b4ba8417d33516b8489bac3c90dbbbf781a3d2 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 29 Oct 2024 17:47:10 +0800
Subject: [PATCH 1/3] menu: fix the logic checking whether ESC key is pressed
It's observed that the bootmenu on a serial console sometimes
incorrectly quitted with superfluous characters filled to command
line input:
> *** U-Boot Boot Menu ***
>
> 1. Startup system (Default)
> 2. Upgrade firmware
> 3. Upgrade ATF BL2
> 4. Upgrade ATF FIP
> 5. Load image
> 0. U-Boot console
>
>
> Press UP/DOWN to move, ENTER to select, ESC to quit
>MT7988> [B
Analysis shows it was caused by the wrong logic of bootmenu_loop:
At first the bootmenu_loop received the first ESC char correctly.
However, during the second call to bootmenu_loop, there's no data
in the UART Rx FIFO. Due to the low baudrate, the second char of
the down array key sequence hasn't be fully received.
But bootmenu_loop just did a mdelay(10), and then treated it as a
single ESC key press event. It didn't even try tstc() again after
the 10ms timeout.
This patch fixes this issue by letting bootmenu_loop check tstc()
twice.
Tested-By: E Shattow <lucent@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
common/menu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- a/common/menu.c
+++ b/common/menu.c
@@ -525,14 +525,15 @@ enum bootmenu_key bootmenu_loop(struct b
struct cli_ch_state *cch)
{
enum bootmenu_key key;
- int c;
+ int c, errchar = 0;
c = cli_ch_process(cch, 0);
if (!c) {
while (!c && !tstc()) {
schedule();
mdelay(10);
- c = cli_ch_process(cch, -ETIMEDOUT);
+ c = cli_ch_process(cch, errchar);
+ errchar = -ETIMEDOUT;
}
if (!c) {
c = getchar();

112
package/boot/uboot-mediatek/patches/011-menu-add-support-to-check-if-menu-needs-to-be-reprin.patch
View File

@ -1,112 +0,0 @@
From f1cbdd3330f0055dfbff0ef7d86276c4cc3cff2a Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 29 Oct 2024 17:47:16 +0800
Subject: [PATCH 2/3] menu: add support to check if menu needs to be reprinted
This patch adds a new callback named need_reprint for menu.
The need_reprint will be called before printing the menu. If the
callback exists and returns FALSE, menu printing will be canceled.
This is very useful if the menu was not changed. It can save time
for serial-based menu to handle more input data.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
boot/pxe_utils.c | 2 +-
cmd/bootmenu.c | 2 +-
cmd/eficonfig.c | 2 +-
common/menu.c | 11 +++++++++++
include/menu.h | 1 +
5 files changed, 15 insertions(+), 3 deletions(-)
--- a/boot/pxe_utils.c
+++ b/boot/pxe_utils.c
@@ -1449,7 +1449,7 @@ static struct menu *pxe_menu_to_menu(str
* Create a menu and add items for all the labels.
*/
m = menu_create(cfg->title, DIV_ROUND_UP(cfg->timeout, 10),
- cfg->prompt, NULL, label_print, NULL, NULL);
+ cfg->prompt, NULL, label_print, NULL, NULL, NULL);
if (!m)
return NULL;
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -506,7 +506,7 @@ static enum bootmenu_ret bootmenu_show(i
menu = menu_create(NULL, bootmenu->delay, 1, menu_display_statusline,
bootmenu_print_entry, bootmenu_choice_entry,
- bootmenu);
+ NULL, bootmenu);
if (!menu) {
bootmenu_destroy(bootmenu);
return BOOTMENU_RET_FAIL;
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -443,7 +443,7 @@ efi_status_t eficonfig_process_common(st
efi_menu->menu_desc = menu_desc;
menu = menu_create(NULL, 0, 1, display_statusline, item_data_print,
- item_choice, efi_menu);
+ item_choice, NULL, efi_menu);
if (!menu)
return EFI_INVALID_PARAMETER;
--- a/common/menu.c
+++ b/common/menu.c
@@ -43,6 +43,7 @@ struct menu {
void (*display_statusline)(struct menu *);
void (*item_data_print)(void *);
char *(*item_choice)(void *);
+ bool (*need_reprint)(void *);
void *item_choice_data;
struct list_head items;
int item_cnt;
@@ -117,6 +118,11 @@ static inline void *menu_item_destroy(st
*/
static inline void menu_display(struct menu *m)
{
+ if (m->need_reprint) {
+ if (!m->need_reprint(m->item_choice_data))
+ return;
+ }
+
if (m->title) {
puts(m->title);
putc('\n');
@@ -362,6 +368,9 @@ int menu_item_add(struct menu *m, char *
* item. Returns a key string corresponding to the chosen item or NULL if
* no item has been selected.
*
+ * need_reprint - If not NULL, will be called before printing the menu.
+ * Returning FALSE means the menu does not need reprint.
+ *
* item_choice_data - Will be passed as the argument to the item_choice function
*
* Returns a pointer to the menu if successful, or NULL if there is
@@ -371,6 +380,7 @@ struct menu *menu_create(char *title, in
void (*display_statusline)(struct menu *),
void (*item_data_print)(void *),
char *(*item_choice)(void *),
+ bool (*need_reprint)(void *),
void *item_choice_data)
{
struct menu *m;
@@ -386,6 +396,7 @@ struct menu *menu_create(char *title, in
m->display_statusline = display_statusline;
m->item_data_print = item_data_print;
m->item_choice = item_choice;
+ m->need_reprint = need_reprint;
m->item_choice_data = item_choice_data;
m->item_cnt = 0;
--- a/include/menu.h
+++ b/include/menu.h
@@ -13,6 +13,7 @@ struct menu *menu_create(char *title, in
void (*display_statusline)(struct menu *),
void (*item_data_print)(void *),
char *(*item_choice)(void *),
+ bool (*need_reprint)(void *),
void *item_choice_data);
int menu_default_set(struct menu *m, char *item_key);
int menu_get_choice(struct menu *m, void **choice);

75
package/boot/uboot-mediatek/patches/012-bootmenu-add-reprint-check.patch
View File

@ -1,75 +0,0 @@
From 702752cfae954648d6133bdff19283343b3339ef Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 29 Oct 2024 17:47:22 +0800
Subject: [PATCH 3/3] bootmenu: add reprint check
Record the last active menu item and check if it equals to the
current selected item before reprint.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
cmd/bootmenu.c | 16 +++++++++++++++-
include/menu.h | 1 +
2 files changed, 16 insertions(+), 1 deletion(-)
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -103,11 +103,13 @@ static char *bootmenu_choice_entry(void
switch (key) {
case BKEY_UP:
+ menu->last_active = menu->active;
if (menu->active > 0)
--menu->active;
/* no menu key selected, regenerate menu */
return NULL;
case BKEY_DOWN:
+ menu->last_active = menu->active;
if (menu->active < menu->count - 1)
++menu->active;
/* no menu key selected, regenerate menu */
@@ -133,6 +135,17 @@ static char *bootmenu_choice_entry(void
return NULL;
}
+static bool bootmenu_need_reprint(void *data)
+{
+ struct bootmenu_data *menu = data;
+ bool need_reprint;
+
+ need_reprint = menu->last_active != menu->active;
+ menu->last_active = menu->active;
+
+ return need_reprint;
+}
+
static void bootmenu_destroy(struct bootmenu_data *menu)
{
struct bootmenu_entry *iter = menu->first;
@@ -332,6 +345,7 @@ static struct bootmenu_data *bootmenu_cr
menu->delay = delay;
menu->active = 0;
+ menu->last_active = -1;
menu->first = NULL;
default_str = env_get("bootmenu_default");
@@ -506,7 +520,7 @@ static enum bootmenu_ret bootmenu_show(i
menu = menu_create(NULL, bootmenu->delay, 1, menu_display_statusline,
bootmenu_print_entry, bootmenu_choice_entry,
- NULL, bootmenu);
+ bootmenu_need_reprint, bootmenu);
if (!menu) {
bootmenu_destroy(bootmenu);
return BOOTMENU_RET_FAIL;
--- a/include/menu.h
+++ b/include/menu.h
@@ -40,6 +40,7 @@ int menu_show(int bootdelay);
struct bootmenu_data {
int delay; /* delay for autoboot */
int active; /* active menu entry */
+ int last_active; /* last active menu entry */
int count; /* total count of menu entries */
struct bootmenu_entry *first; /* first menu entry */
};

45
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@ -0,0 +1,45 @@
From 6e45549f4dac42748d66462e04f940ef6737289d Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:16 +0800
Subject: [PATCH 01/10] clk: mediatek: mt7629: fix parent clock of some top
clock muxes
According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL
shares the same parent selection with CLK_TOP_IRRX_SEL, while the
present parent selection for CLK_TOP_F10M_REF_SEL is actually used
for CLK_TOP_SGMII_REF_1_SEL.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/clk/mediatek/clk-mt7629.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -186,7 +186,7 @@ static const int pwm_parents[] = {
CLK_TOP_UNIVPLL2_D4
};
-static const int f10m_ref_parents[] = {
+static const int sgmii_ref_1_parents[] = {
CLK_XTAL,
CLK_TOP_SGMIIPLL_D2
};
@@ -369,7 +369,7 @@ static const struct mtk_composite top_mu
/* CLK_CFG_1 */
MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
- MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
+ MUX_GATE(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15),
MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
@@ -412,7 +412,7 @@ static const struct mtk_composite top_mu
/* CLK_CFG_8 */
MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7),
- MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15),
+ MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15),
MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23),
};

28
package/boot/uboot-mediatek/patches/060-02-arm-dts-mt7629-fix-sgmii-clock-selection-for-etherne.patch Normal file
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@ -0,0 +1,28 @@
From ba365c3d23411620d86b5baf621c8f5a4000ab33 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:20 +0800
Subject: [PATCH 02/10] arm: dts: mt7629: fix sgmii clock selection for
ethernet
Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow
sgmiisys1 work correctly.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7629.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -314,8 +314,10 @@
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
"sgmii_ck", "eth2pll";
assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
- <&topckgen CLK_TOP_F10M_REF_SEL>;
+ <&topckgen CLK_TOP_F10M_REF_SEL>,
+ <&topckgen CLK_TOP_SGMII_REF_1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
+ <&topckgen CLK_TOP_SYSPLL4_D16>,
<&topckgen CLK_TOP_SGMIIPLL_D2>;
power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
resets = <&ethsys ETHSYS_FE_RST>;

64
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@ -0,0 +1,64 @@
From 0d4d8e6f47ef22ea6b3041b4c0cb27b4ed4bf188 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:23 +0800
Subject: [PATCH 03/10] net: mediatek: use correct register field for SGMII
speed selection
The register field for SGMII speed selection is a 2-bit field with
value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved).
So it's necessary to set both bits instead of just setting/clearing
only the lower bit.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 12 ++++++------
drivers/net/mtk_eth.h | 3 ++-
2 files changed, 8 insertions(+), 7 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -835,8 +835,8 @@ static int mt7531_port_sgmii_init(struct
}
/* Set SGMII GEN2 speed(2.5G) */
- mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
- SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
+ mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK,
+ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500));
/* Disable SGMII AN */
mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port),
@@ -1281,8 +1281,7 @@ static int mtk_phy_probe(struct udevice
static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
{
/* Set SGMII GEN1 speed(1G) */
- clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
- SGMSYS_SPEED_2500, 0);
+ clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK);
/* Enable SGMII AN */
setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
@@ -1305,8 +1304,9 @@ static void mtk_sgmii_an_init(struct mtk
static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
{
/* Set SGMII GEN2 speed(2.5G) */
- setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
- SGMSYS_SPEED_2500);
+ clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
+ SGMSYS_SPEED_MASK,
+ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500));
/* Disable SGMII AN */
clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -108,7 +108,8 @@ enum mkt_eth_capabilities {
#define SGMSYS_GEN2_SPEED 0x2028
#define SGMSYS_GEN2_SPEED_V2 0x128
-#define SGMSYS_SPEED_2500 BIT(2)
+#define SGMSYS_SPEED_MASK GENMASK(3, 2)
+#define SGMSYS_SPEED_2500 1
/* USXGMII subsystem config registers */
/* Register to control USXGMII XFI PLL digital */

78
package/boot/uboot-mediatek/patches/060-04-net-mediatek-correct-register-name-of-ethsys-syscfg1.patch Normal file
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@ -0,0 +1,78 @@
From 7562da9454c1a6eff3db3b41c183e03039e855e6 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:27 +0800
Subject: [PATCH 04/10] net: mediatek: correct register name of ethsys syscfg1
The SYSCFG0 should be SYSCFG1 according to the programming guide.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 14 +++++++-------
drivers/net/mtk_eth.h | 12 ++++++------
2 files changed, 13 insertions(+), 13 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1450,8 +1450,8 @@ static void mtk_mac_init(struct mtk_eth_
}
ge_mode = GE_MODE_RGMII;
- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
- SYSCFG0_SGMII_SEL(priv->gmac_id));
+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M,
+ SYSCFG1_SGMII_SEL(priv->gmac_id));
if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
mtk_sgmii_an_init(priv);
else
@@ -1469,9 +1469,9 @@ static void mtk_mac_init(struct mtk_eth_
}
/* set the gmac to the right mode */
- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
- SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
- ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id));
+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG,
+ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
+ ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id));
if (priv->force_mode) {
mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
@@ -1527,8 +1527,8 @@ static void mtk_xmac_init(struct mtk_eth
}
/* Set GMAC to the correct mode */
- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
- SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG,
+ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
0);
if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII &&
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -65,11 +65,11 @@ enum mkt_eth_capabilities {
/* Ethernet subsystem registers */
-#define ETHSYS_SYSCFG0_REG 0x14
-#define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2))
-#define SYSCFG0_GE_MODE_M 0x3
-#define SYSCFG0_SGMII_SEL_M (0x3 << 8)
-#define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
+#define ETHSYS_SYSCFG1_REG 0x14
+#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2))
+#define SYSCFG1_GE_MODE_M 0x3
+#define SYSCFG1_SGMII_SEL_M (0x3 << 8)
+#define SYSCFG1_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
#define ETHSYS_CLKCFG0_REG 0x2c
#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
@@ -84,7 +84,7 @@ enum mkt_eth_capabilities {
#define QPHY_SEL_MASK 0x3
#define SGMII_QPHY_SEL 0x2
-/* SYSCFG0_GE_MODE: GE Modes */
+/* SYSCFG1_GE_MODE: GE Modes */
#define GE_MODE_RGMII 0
#define GE_MODE_MII 1
#define GE_MODE_MII_PHY 2

90
package/boot/uboot-mediatek/patches/060-05-net-mediatek-fix-sgmii-selection-for-mt7622.patch Normal file
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@ -0,0 +1,90 @@
From 82f05bc48821f3709f22f3d1f6e45290547f74be Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:41 +0800
Subject: [PATCH 05/10] net: mediatek: fix sgmii selection for mt7622
Unlike other platforms, mt7622 has only one SGMII and it can be
attached to either gmac1 or gmac2. So the register field of the
sgmii selection differs from other platforms as newer platforms can
control each sgmii individually.
This patch adds a new capability for mt7622 to handle this case.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 10 ++++++++--
drivers/net/mtk_eth.h | 8 ++++++--
2 files changed, 14 insertions(+), 4 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1434,7 +1434,7 @@ static void mtk_usxgmii_an_init(struct m
static void mtk_mac_init(struct mtk_eth_priv *priv)
{
- int i, ge_mode = 0;
+ int i, sgmii_sel_mask = 0, ge_mode = 0;
u32 mcr;
switch (priv->phy_interface) {
@@ -1450,8 +1450,13 @@ static void mtk_mac_init(struct mtk_eth_
}
ge_mode = GE_MODE_RGMII;
- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M,
+
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII))
+ sgmii_sel_mask = SYSCFG1_SGMII_SEL_M;
+
+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask,
SYSCFG1_SGMII_SEL(priv->gmac_id));
+
if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
mtk_sgmii_an_init(priv);
else
@@ -2112,6 +2117,7 @@ static const struct mtk_soc_data mt7623_
};
static const struct mtk_soc_data mt7622_data = {
+ .caps = MT7622_CAPS,
.ana_rgc3 = 0x2028,
.gdma_count = 2,
.pdma_base = PDMA_V1_BASE,
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -23,6 +23,7 @@ enum mkt_eth_capabilities {
/* PATH BITS */
MTK_ETH_PATH_GMAC1_TRGMII_BIT,
MTK_ETH_PATH_GMAC2_SGMII_BIT,
+ MTK_ETH_PATH_MT7622_SGMII_BIT,
};
#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
@@ -36,6 +37,7 @@ enum mkt_eth_capabilities {
#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
+#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT)
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
@@ -45,6 +47,8 @@ enum mkt_eth_capabilities {
#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
+#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII)
+
#define MT7623_CAPS (MTK_GMAC1_TRGMII)
#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
@@ -68,8 +72,8 @@ enum mkt_eth_capabilities {
#define ETHSYS_SYSCFG1_REG 0x14
#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2))
#define SYSCFG1_GE_MODE_M 0x3
-#define SYSCFG1_SGMII_SEL_M (0x3 << 8)
-#define SYSCFG1_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
+#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8)
+#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac))
#define ETHSYS_CLKCFG0_REG 0x2c
#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)

73
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@ -0,0 +1,73 @@
From d8d7e566545f836dd49611cafbf44eef56434e08 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:46 +0800
Subject: [PATCH 06/10] net: mediatek: fix gmac2 usability for mt7629
MT7629 need extra setting for gmac2 to work. So additional
capability is added for mt7629 to handle this case.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 6 ++++++
drivers/net/mtk_eth.h | 7 +++++++
2 files changed, 13 insertions(+)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1437,6 +1437,11 @@ static void mtk_mac_init(struct mtk_eth_
int i, sgmii_sel_mask = 0, ge_mode = 0;
u32 mcr;
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) {
+ mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG,
+ INFRA_MISC2_BONDING_OPTION, priv->gmac_id);
+ }
+
switch (priv->phy_interface) {
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII:
@@ -2101,6 +2106,7 @@ static const struct mtk_soc_data mt7981_
};
static const struct mtk_soc_data mt7629_data = {
+ .caps = MT7629_CAPS,
.ana_rgc3 = 0x128,
.gdma_count = 2,
.pdma_base = PDMA_V1_BASE,
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -24,6 +24,7 @@ enum mkt_eth_capabilities {
MTK_ETH_PATH_GMAC1_TRGMII_BIT,
MTK_ETH_PATH_GMAC2_SGMII_BIT,
MTK_ETH_PATH_MT7622_SGMII_BIT,
+ MTK_ETH_PATH_MT7629_GMAC2_BIT,
};
#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
@@ -38,6 +39,7 @@ enum mkt_eth_capabilities {
#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT)
+#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT)
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
@@ -51,6 +53,8 @@ enum mkt_eth_capabilities {
#define MT7623_CAPS (MTK_GMAC1_TRGMII)
+#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA)
+
#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
#define MT7986_CAPS (MTK_NETSYS_V2)
@@ -88,6 +92,9 @@ enum mkt_eth_capabilities {
#define QPHY_SEL_MASK 0x3
#define SGMII_QPHY_SEL 0x2
+#define MT7629_INFRA_MISC2_REG 0x70c
+#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0)
+
/* SYSCFG1_GE_MODE: GE Modes */
#define GE_MODE_RGMII 0
#define GE_MODE_MII 1

147
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@ -0,0 +1,147 @@
From ad0c47109e4c9f6297aa247d8bbf7131438bc435 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:50 +0800
Subject: [PATCH 07/10] net: mediatek: add support for 10GBASE-R
This patch adds support for 10GBASE-R interface mode
Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 83 +++++++++++++++++++++++++++++++++++++++++--
1 file changed, 81 insertions(+), 2 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1246,6 +1246,7 @@ static int mtk_phy_start(struct mtk_eth_
if (!priv->force_mode) {
if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
mtk_xphy_link_adjust(priv);
else
@@ -1425,6 +1426,71 @@ static void mtk_usxgmii_setup_phya_an_10
udelay(400);
}
+static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv)
+{
+ regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C);
+ regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
+ regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000);
+ ndelay(1020);
+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000);
+ ndelay(1020);
+
+ regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
+ regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
+ regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
+ regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
+ regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
+ regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
+ regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
+ regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
+ regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
+ regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
+ regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
+ regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
+ regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
+ regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
+ regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
+ regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
+ regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
+ regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
+ regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
+ regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
+ regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
+ regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
+ ndelay(1020);
+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
+ regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
+ regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
+ regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
+ regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
+ regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
+ regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
+ regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100);
+ regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000);
+ regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000);
+ regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
+ if (priv->gmac_id == 2)
+ regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400);
+ regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
+ regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
+ udelay(150);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
+ ndelay(1020);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
+ udelay(15);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
+ ndelay(1020);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
+ udelay(100);
+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
+ regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
+ udelay(400);
+}
+
static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
{
mtk_xfi_pll_enable(priv);
@@ -1432,6 +1498,13 @@ static void mtk_usxgmii_an_init(struct m
mtk_usxgmii_setup_phya_an_10000(priv);
}
+static void mtk_10gbaser_init(struct mtk_eth_priv *priv)
+{
+ mtk_xfi_pll_enable(priv);
+ mtk_usxgmii_reset(priv);
+ mtk_usxgmii_setup_phya_force_10000(priv);
+}
+
static void mtk_mac_init(struct mtk_eth_priv *priv)
{
int i, sgmii_sel_mask = 0, ge_mode = 0;
@@ -1532,6 +1605,9 @@ static void mtk_xmac_init(struct mtk_eth
case PHY_INTERFACE_MODE_USXGMII:
mtk_usxgmii_an_init(priv);
break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ mtk_10gbaser_init(priv);
+ break;
default:
break;
}
@@ -1541,7 +1617,8 @@ static void mtk_xmac_init(struct mtk_eth
SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
0);
- if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII &&
+ if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) &&
priv->gmac_id == 1) {
mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
@@ -1843,6 +1920,7 @@ static int mtk_eth_probe(struct udevice
/* Set MAC mode */
if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
mtk_xmac_init(priv);
else
@@ -1977,7 +2055,8 @@ static int mtk_eth_of_to_plat(struct ude
/* Upstream linux use mediatek,pnswap instead of pn_swap */
priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") ||
ofnode_read_bool(args.node, "mediatek,pnswap");
- } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
+ } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) {
/* get corresponding usxgmii phandle */
ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
NULL, 0, 0, &args);

144
package/boot/uboot-mediatek/patches/060-08-net-mediatek-make-sgmii-usxgmii-optional.patch Normal file
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@ -0,0 +1,144 @@
From 5ac929fd1ab1d0dc77b9167952aea7cafdb8619f Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:55 +0800
Subject: [PATCH 08/10] net: mediatek: make sgmii/usxgmii optional
Not all platforms supports sgmii and/or usxgmii. So we add Kconfig
options for these features and enable them only for supported
platforms.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/Kconfig | 12 ++++++++++++
drivers/net/mtk_eth.c | 39 +++++++++++++++++++++++++++++----------
2 files changed, 41 insertions(+), 10 deletions(-)
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -975,6 +975,18 @@ config MEDIATEK_ETH
This Driver support MediaTek Ethernet GMAC
Say Y to enable support for the MediaTek Ethernet GMAC.
+if MEDIATEK_ETH
+
+config MTK_ETH_SGMII
+ bool
+ default y if ARCH_MEDIATEK && !TARGET_MT7623
+
+config MTK_ETH_XGMII
+ bool
+ default y if TARGET_MT7987 || TARGET_MT7988
+
+endif # MEDIATEK_ETH
+
config HIFEMAC_ETH
bool "HiSilicon Fast Ethernet Controller"
select DM_CLK
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1505,7 +1505,7 @@ static void mtk_10gbaser_init(struct mtk
mtk_usxgmii_setup_phya_force_10000(priv);
}
-static void mtk_mac_init(struct mtk_eth_priv *priv)
+static int mtk_mac_init(struct mtk_eth_priv *priv)
{
int i, sgmii_sel_mask = 0, ge_mode = 0;
u32 mcr;
@@ -1522,13 +1522,16 @@ static void mtk_mac_init(struct mtk_eth_
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_2500BASEX:
+ if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) {
+ printf("Error: SGMII is not supported on this platform\n");
+ return -ENOTSUPP;
+ }
+
if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) {
mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK,
SGMII_QPHY_SEL);
}
- ge_mode = GE_MODE_RGMII;
-
if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII))
sgmii_sel_mask = SYSCFG1_SGMII_SEL_M;
@@ -1539,6 +1542,8 @@ static void mtk_mac_init(struct mtk_eth_
mtk_sgmii_an_init(priv);
else
mtk_sgmii_force_init(priv);
+
+ ge_mode = GE_MODE_RGMII;
break;
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
@@ -1595,12 +1600,19 @@ static void mtk_mac_init(struct mtk_eth_
RX_RST | RXC_DQSISEL);
mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0);
}
+
+ return 0;
}
-static void mtk_xmac_init(struct mtk_eth_priv *priv)
+static int mtk_xmac_init(struct mtk_eth_priv *priv)
{
u32 force_link = 0;
+ if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) {
+ printf("Error: 10Gb interface is not supported on this platform\n");
+ return -ENOTSUPP;
+ }
+
switch (priv->phy_interface) {
case PHY_INTERFACE_MODE_USXGMII:
mtk_usxgmii_an_init(priv);
@@ -1633,6 +1645,8 @@ static void mtk_xmac_init(struct mtk_eth
/* Force GMAC link down */
mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
+
+ return 0;
}
static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
@@ -1922,9 +1936,12 @@ static int mtk_eth_probe(struct udevice
if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
- mtk_xmac_init(priv);
+ ret = mtk_xmac_init(priv);
else
- mtk_mac_init(priv);
+ ret = mtk_mac_init(priv);
+
+ if (ret)
+ return ret;
/* Probe phy if switch is not specified */
if (priv->sw == SW_NONE)
@@ -2032,8 +2049,9 @@ static int mtk_eth_of_to_plat(struct ude
}
}
- if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
+ if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) &&
+ IS_ENABLED(CONFIG_MTK_ETH_SGMII)) {
/* get corresponding sgmii phandle */
ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
NULL, 0, 0, &args);
@@ -2055,8 +2073,9 @@ static int mtk_eth_of_to_plat(struct ude
/* Upstream linux use mediatek,pnswap instead of pn_swap */
priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") ||
ofnode_read_bool(args.node, "mediatek,pnswap");
- } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) {
+ } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) &&
+ IS_ENABLED(CONFIG_MTK_ETH_XGMII)) {
/* get corresponding usxgmii phandle */
ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
NULL, 0, 0, &args);

36
package/boot/uboot-mediatek/patches/060-09-net-mediatek-don-t-enable-GDMA-cpu-bridge-unconditio.patch Normal file
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@ -0,0 +1,36 @@
From b9dfb5636bc5eb9b783b88b8388dc7d1f41d6498 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:59 +0800
Subject: [PATCH 09/10] net: mediatek: don't enable GDMA cpu bridge
unconditionally for NETSYSv3
Enable GDMA cpu bridge only when 10Gb interface is enabled for GMAC other
than GMAC0, or when MT7988 internal switch is used.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1762,10 +1762,16 @@ static int mtk_eth_start(struct udevice
if (priv->sw == SW_MT7988 && priv->gmac_id == 0) {
mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG,
GDMA_BRIDGE_TO_CPU);
- }
- mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
- GDMA_CPU_BRIDGE_EN);
+ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
+ GDMA_CPU_BRIDGE_EN);
+ } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
+ priv->phy_interface == PHY_INTERFACE_MODE_XGMII) &&
+ priv->gmac_id != 0) {
+ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
+ GDMA_CPU_BRIDGE_EN);
+ }
}
udelay(500);

37
package/boot/uboot-mediatek/patches/060-10-net-mediatek-fix-usability-with-wget-command.patch Normal file
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@ -0,0 +1,37 @@
From c949686e558e00cbb8c38f7c060701006d70cea8 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:40:03 +0800
Subject: [PATCH 10/10] net: mediatek: fix usability with wget command
The wget command currently cannot work correctly with mtk_eth driver.
This patch fixed this by increase DMA ring size and invalidate ring data
after use.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -29,8 +29,8 @@
#include "mtk_eth.h"
-#define NUM_TX_DESC 24
-#define NUM_RX_DESC 24
+#define NUM_TX_DESC 32
+#define NUM_RX_DESC 32
#define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN)
#define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN)
#define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE)
@@ -1897,6 +1897,9 @@ static int mtk_eth_free_pkt(struct udevi
rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
+ invalidate_dcache_range((ulong)rxd->rxd1,
+ (ulong)rxd->rxd1 + PKTSIZE_ALIGN);
+
if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);

6311
package/boot/uboot-mediatek/patches/061-01-net-mediatek-split-ethernet-switch-code-from-mtk_eth.patch Normal file
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63
package/boot/uboot-mediatek/patches/061-02-net-mediatek-add-support-for-MediaTek-MT7987-SoC.patch Normal file
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@ -0,0 +1,63 @@
From fe106f2093733b8bd61946372945dfea552b4755 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 10 Jan 2025 16:41:20 +0800
Subject: [PATCH 2/3] net: mediatek: add support for MediaTek MT7987 SoC
This patch adds support for MediaTek MT7987.
MT7987 features MediaTek NETSYS v3, similar to MT7988, features three GMACs
which support 2.5Gb HSGMII. One 2.5Gb PHY is also embedded an can be
connected to a dedicated GMAC.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth/Kconfig | 4 ++--
drivers/net/mtk_eth/mtk_eth.c | 10 ++++++++++
2 files changed, 12 insertions(+), 2 deletions(-)
--- a/drivers/net/mtk_eth/Kconfig
+++ b/drivers/net/mtk_eth/Kconfig
@@ -16,7 +16,7 @@ config MTK_ETH_SGMII
config MTK_ETH_XGMII
bool
- default y if TARGET_MT7988
+ default y if TARGET_MT7987 || TARGET_MT7988
config MTK_ETH_SWITCH_MT7530
bool "Support for MediaTek MT7530 ethernet switch"
@@ -25,7 +25,7 @@ config MTK_ETH_SWITCH_MT7530
config MTK_ETH_SWITCH_MT7531
bool "Support for MediaTek MT7531 ethernet switch"
default y if TARGET_MT7622 || TARGET_MT7629 || TARGET_MT7981 || \
- TARGET_MT7986
+ TARGET_MT7986 || TARGET_MT7987
config MTK_ETH_SWITCH_MT7988
bool "Support for MediaTek MT7988 built-in ethernet switch"
--- a/drivers/net/mtk_eth/mtk_eth.c
+++ b/drivers/net/mtk_eth/mtk_eth.c
@@ -1477,6 +1477,15 @@ static const struct mtk_soc_data mt7988_
.rxd_size = sizeof(struct mtk_rx_dma_v2),
};
+static const struct mtk_soc_data mt7987_data = {
+ .caps = MT7987_CAPS,
+ .ana_rgc3 = 0x128,
+ .gdma_count = 3,
+ .pdma_base = PDMA_V3_BASE,
+ .txd_size = sizeof(struct mtk_tx_dma_v2),
+ .rxd_size = sizeof(struct mtk_rx_dma_v2),
+};
+
static const struct mtk_soc_data mt7986_data = {
.caps = MT7986_CAPS,
.ana_rgc3 = 0x128,
@@ -1531,6 +1540,7 @@ static const struct mtk_soc_data mt7621_
static const struct udevice_id mtk_eth_ids[] = {
{ .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data },
+ { .compatible = "mediatek,mt7987-eth", .data = (ulong)&mt7987_data },
{ .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
{ .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
{ .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },

1133
package/boot/uboot-mediatek/patches/061-03-net-mediatek-add-support-for-Airoha-AN8855-ethernet-.patch Normal file
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26
package/boot/uboot-mediatek/patches/070-01-board-mediatek-mt7622-remove-board_late_init.patch Normal file
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@ -0,0 +1,26 @@
From 92090b92fab207250d5b8d5a4a36aa34f5a91f19 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:16:33 +0800
Subject: [PATCH 01/15] board: mediatek: mt7622: remove board_late_init
The function board_late_init defined for mt7622 is useless now. Just
remove it.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
board/mediatek/mt7622/mt7622_rfb.c | 7 -------
1 file changed, 7 deletions(-)
--- a/board/mediatek/mt7622/mt7622_rfb.c
+++ b/board/mediatek/mt7622/mt7622_rfb.c
@@ -15,10 +15,3 @@ int board_init(void)
{
return 0;
}
-
-int board_late_init(void)
-{
- gd->env_valid = 1; //to load environment variable from persistent store
- env_relocate();
- return 0;
-}

48
package/boot/uboot-mediatek/patches/070-02-clk-mediatek-fix-uninitialized-fields-issue-in-INFRA.patch Normal file
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@ -0,0 +1,48 @@
From b033dfb21df8ae876ec69d84bc8c5fafd7aa8ced Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:16:38 +0800
Subject: [PATCH 02/15] clk: mediatek: fix uninitialized fields issue in
INFRA_MUX struct
This patch adds missing initialization of fields in INFRA_MUX struct
which caused uart broken after any other infra mux being enabled by
'clk_prepare_enable'
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/clk/mediatek/clk-mt7981.c | 1 +
drivers/clk/mediatek/clk-mt7986.c | 1 +
drivers/clk/mediatek/clk-mt7988.c | 1 +
3 files changed, 3 insertions(+)
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -359,6 +359,7 @@ static const struct mtk_parent infra_pci
.id = _id, .mux_reg = (_reg) + 0x8, \
.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
+ .gate_shift = -1, .upd_shift = -1, \
.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -366,6 +366,7 @@ static const struct mtk_parent infra_pci
.id = _id, .mux_reg = (_reg) + 0x8, \
.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
+ .gate_shift = -1, .upd_shift = -1, \
.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -485,6 +485,7 @@ static const int infra_pcie_gfmux_tl_ck_
.id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \
.mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, .parent = _parents, \
+ .gate_shift = -1, .upd_shift = -1, \
.num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \
}

25
package/boot/uboot-mediatek/patches/070-03-configs-mt7629-move-image-load-address-to-0x42000000.patch Normal file
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@ -0,0 +1,25 @@
From 7958b41b8c6a15c3c993affd2091f8c921b6a8a1 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:17:38 +0800
Subject: [PATCH 03/15] configs: mt7629: move image load address to 0x42000000
Update the image load address to ensure it matches the mt7629 NOR
controller's DMA alignment requirements.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
configs/mt7629_rfb_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -18,7 +18,7 @@ CONFIG_SPL_STACK=0x106000
CONFIG_SPL_TEXT_BASE=0x201000
CONFIG_SPL_STACK_R=y
CONFIG_SYS_BOOTM_LEN=0x4000000
-CONFIG_SYS_LOAD_ADDR=0x42007f1c
+CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SPL_PAYLOAD="u-boot-lzma.img"
CONFIG_BUILD_TARGET="u-boot-mtk.bin"
CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin"

24
package/boot/uboot-mediatek/patches/070-04-configs-mt7988-move-image-load-address-to-0x44000000.patch Normal file
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@ -0,0 +1,24 @@
From c7a3761ddfce2bd56ad319a254d5269cb26fa18f Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:17:44 +0800
Subject: [PATCH 04/15] configs: mt7988: move image load address to 0x44000000
This patch sets mt7988 image load address to 0x44000000 to support loading
larger images.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
configs/mt7988_rfb_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
@@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
CONFIG_TARGET_MT7988=y
-CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_SYS_LOAD_ADDR=0x44000000
CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_DEBUG_UART=y

23
package/boot/uboot-mediatek/patches/070-05-spi-mtk_spim-add-support-to-use-DT-live-tree.patch Normal file
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@ -0,0 +1,23 @@
From a2c2ac46ca4c4ef5fe043e584cf867a20e93226d Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:17:51 +0800
Subject: [PATCH 05/15] spi: mtk_spim: add support to use DT live tree
Change devfdt_get_addr_ptr to dev_read_addr_ptr to support DT live tree.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/spi/mtk_spim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
@@ -648,7 +648,7 @@ static int mtk_spim_probe(struct udevice
struct mtk_spim_priv *priv = dev_get_priv(dev);
int ret;
- priv->base = devfdt_get_addr_ptr(dev);
+ priv->base = dev_read_addr_ptr(dev);
if (!priv->base)
return -EINVAL;

27
package/boot/uboot-mediatek/patches/070-06-spi-mtk_spim-check-slave-device-mode-in-spi-mem-s-su.patch Normal file
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@ -0,0 +1,27 @@
From 7725d4ba16577b74567f7cffb2faffa8bdc5ad61 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:17:55 +0800
Subject: [PATCH 06/15] spi: mtk_spim: check slave device mode in spi-mem's
supports_op
Call spi_mem_default_supports_op() in supports_op to honor the
slave's supported single/dual/quad mode settings.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/spi/mtk_spim.c | 3 +++
1 file changed, 3 insertions(+)
--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
@@ -359,6 +359,9 @@ static bool mtk_spim_supports_op(struct
struct udevice *bus = dev_get_parent(slave->dev);
struct mtk_spim_priv *priv = dev_get_priv(bus);
+ if (!spi_mem_default_supports_op(slave, op))
+ return false;
+
if (op->cmd.buswidth == 0 || op->cmd.buswidth > 4 ||
op->addr.buswidth > 4 || op->dummy.buswidth > 4 ||
op->data.buswidth > 4)

96
package/boot/uboot-mediatek/patches/070-07-arm-dts-mediatek-add-quad-mode-capabilities-for-SPI-.patch Normal file
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@ -0,0 +1,96 @@
From c7a602028669f4409538c3ce0a63c4054d0f2b7a Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:01 +0800
Subject: [PATCH 07/15] arm: dts: mediatek: add quad mode capabilities for SPI
flashes
Explicitly add quad mode capabilities or the SPI controller may
start transfer in single mode.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7981-rfb.dts | 4 ++++
arch/arm/dts/mt7986a-rfb.dts | 4 ++++
arch/arm/dts/mt7986b-rfb.dts | 4 ++++
arch/arm/dts/mt7988-rfb.dts | 4 ++++
4 files changed, 16 insertions(+)
--- a/arch/arm/dts/mt7981-rfb.dts
+++ b/arch/arm/dts/mt7981-rfb.dts
@@ -143,6 +143,8 @@
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};
@@ -164,6 +166,8 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};
--- a/arch/arm/dts/mt7986a-rfb.dts
+++ b/arch/arm/dts/mt7986a-rfb.dts
@@ -190,12 +190,16 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
spi_nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};
--- a/arch/arm/dts/mt7986b-rfb.dts
+++ b/arch/arm/dts/mt7986b-rfb.dts
@@ -177,12 +177,16 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
spi_nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -144,6 +144,8 @@
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};
@@ -165,6 +167,8 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
};
};

98
package/boot/uboot-mediatek/patches/070-08-pwm-mediatek-add-pwm3-support-for-mt7981.patch Normal file
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@ -0,0 +1,98 @@
From 7071ba2658ef6175183cc5dc85819293811490b3 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:06 +0800
Subject: [PATCH 08/15] pwm: mediatek: add pwm3 support for mt7981
This patch adds pwm channel 2 (pwm3) support for mt7981
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7981-emmc-rfb.dts | 8 ++++++++
arch/arm/dts/mt7981-rfb.dts | 8 ++++++++
arch/arm/dts/mt7981-sd-rfb.dts | 8 ++++++++
arch/arm/dts/mt7981.dtsi | 10 ++++++++--
drivers/pwm/pwm-mtk.c | 2 +-
5 files changed, 33 insertions(+), 3 deletions(-)
--- a/arch/arm/dts/mt7981-emmc-rfb.dts
+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
@@ -95,6 +95,14 @@
};
};
+ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
+ three_pwm_pins_1: three-pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0_0", "pwm1_1", "pwm2";
+ };
+ };
+
mmc0_pins_default: mmc0default {
mux {
function = "flash";
--- a/arch/arm/dts/mt7981-rfb.dts
+++ b/arch/arm/dts/mt7981-rfb.dts
@@ -123,6 +123,14 @@
groups = "pwm0_1", "pwm1_0", "pwm2";
};
};
+
+ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
+ three_pwm_pins_1: three-pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0_0", "pwm1_1", "pwm2";
+ };
+ };
};
&spi0 {
--- a/arch/arm/dts/mt7981-sd-rfb.dts
+++ b/arch/arm/dts/mt7981-sd-rfb.dts
@@ -95,6 +95,14 @@
};
};
+ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
+ three_pwm_pins_1: three-pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0_0", "pwm1_1", "pwm2";
+ };
+ };
+
mmc0_pins_default: mmc0default {
mux {
function = "flash";
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -137,8 +137,14 @@
<&infracfg CLK_INFRA_PWM1_CK>,
<&infracfg CLK_INFRA_PWM2_CK>,
<&infracfg CLK_INFRA_PWM3_CK>;
- assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>;
+ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM1_SEL>,
+ <&infracfg CLK_INFRA_PWM2_SEL>,
+ <&infracfg CLK_INFRA_PWM3_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_PWM_SEL>,
+ <&topckgen CLK_TOP_PWM_SEL>,
+ <&topckgen CLK_TOP_PWM_SEL>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
status = "disabled";
};
--- a/drivers/pwm/pwm-mtk.c
+++ b/drivers/pwm/pwm-mtk.c
@@ -192,7 +192,7 @@ static const struct mtk_pwm_soc mt7629_d
};
static const struct mtk_pwm_soc mt7981_data = {
- .num_pwms = 2,
+ .num_pwms = 3,
.pwm45_fixup = false,
.reg_ver = PWM_REG_V2,
};

61
package/boot/uboot-mediatek/patches/070-09-pci-mediatek-add-support-for-multiple-ports-in-media.patch Normal file
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@ -0,0 +1,61 @@
From dfbadb86b3bc43c004671ab6eb46ee160a192e98 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:11 +0800
Subject: [PATCH 09/15] pci: mediatek: add support for multiple ports in
mediatek pcie gen3 driver
One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0
on this port represents the controller itself and bus 1 represents
the external PCIe device.
If multiple PCIe controllers are probed in U-Boot, U-Boot will use
bus numbers greater than 2 as input parameters. Therefore, we should
convert the BDF bus number to either 0 or 1 by subtracting the
offset by controller->seq_.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/pci/pcie_mediatek_gen3.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
--- a/drivers/pci/pcie_mediatek_gen3.c
+++ b/drivers/pci/pcie_mediatek_gen3.c
@@ -83,6 +83,28 @@ struct mtk_pcie {
struct phy phy;
};
+static pci_dev_t convert_bdf(const struct udevice *controller, pci_dev_t bdf)
+{
+ int bdfs[3];
+
+ bdfs[0] = PCI_BUS(bdf);
+ bdfs[1] = PCI_DEV(bdf);
+ bdfs[2] = PCI_FUNC(bdf);
+
+ /*
+ * One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0 on
+ * this port represents the controller itself and bus 1 represents the
+ * external PCIe device. If multiple PCIe controllers are probed in U-Boot,
+ * U-Boot will use bus numbers greater than 2 as input parameters. Therefore,
+ * we should convert the BDF bus number to either 0 or 1 by subtracting the
+ * offset by controller->seq_
+ */
+
+ bdfs[0] = bdfs[0] - controller->seq_;
+
+ return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
+}
+
static void mtk_pcie_config_tlp_header(const struct udevice *bus,
pci_dev_t devfn,
int where, int size)
@@ -91,6 +113,8 @@ static void mtk_pcie_config_tlp_header(c
int bytes;
u32 val;
+ devfn = convert_bdf(bus, devfn);
+
size = 1 << size;
bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3);

219
package/boot/uboot-mediatek/patches/070-10-arm-dts-mediatek-add-pcie-support-for-mt7988.patch Normal file
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@ -0,0 +1,219 @@
From 4064eb22e221ce93fef7f1ec3b13ac670c6b20e2 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:17 +0800
Subject: [PATCH 10/15] arm: dts: mediatek: add pcie support for mt7988
This patch adds PCIe support for mt7988
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7988-rfb.dts | 18 ++++
arch/arm/dts/mt7988.dtsi | 162 ++++++++++++++++++++++++++++++++++++
2 files changed, 180 insertions(+)
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -63,6 +63,24 @@
};
};
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+/* PCIE2 not working in u-boot */
+&pcie2 {
+ status = "disabled";
+};
+
+/* PCIE3 not working in u-boot */
+&pcie3 {
+ status = "disabled";
+};
+
&pinctrl {
i2c1_pins: i2c1-pins {
mux {
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -188,6 +188,152 @@
status = "okay";
};
+ pcie2: pcie@11280000 {
+ compatible = "mediatek,mt7988-pcie",
+ "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11280000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <3>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20200000 0 0x20200000 0 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ phys = <&xphyu3port0 PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+ <0 0 0 2 &pcie_intc2 1>,
+ <0 0 0 3 &pcie_intc2 2>,
+ <0 0 0 4 &pcie_intc2 3>;
+
+ pcie_intc2: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie3: pcie@11290000 {
+ compatible = "mediatek,mt7988-pcie",
+ "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11290000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <2>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x28200000 0 0x28200000 0 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ use-dedicated-phy;
+
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc3 0>,
+ <0 0 0 2 &pcie_intc3 1>,
+ <0 0 0 3 &pcie_intc3 2>,
+ <0 0 0 4 &pcie_intc3 3>;
+ pcie_intc3: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie0: pcie@11300000 {
+ compatible = "mediatek,mt7988-pcie",
+ "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11300000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <0>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x30200000 0 0x30200000 0 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ use-dedicated-phy;
+
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie1: pcie@11310000 {
+ compatible = "mediatek,mt7988-pcie",
+ "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11310000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <1>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x38200000 0 0x38200000 0 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ use-dedicated-phy;
+
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
usbtphy: usb-phy@11c50000 {
compatible = "mediatek,mt7988",
"mediatek,generic-tphy-v2";
@@ -214,6 +360,22 @@
status = "okay";
};
};
+
+ xphy: xphy@11e10000 {
+ compatible = "mediatek,mt7988", "mediatek,xsphy";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ xphyu3port0: usb-phy@11e13000 {
+ reg = <0 0x11e13400 0 0x500>;
+ clocks = <&dummy_clk>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
xfi_pextp0: syscon@11f20000 {
compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";

36
package/boot/uboot-mediatek/patches/070-11-arm-dts-medaitek-fix-internal-switch-link-speed-of-m.patch Normal file
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@ -0,0 +1,36 @@
From 4a85182570200bf5e87e2a9920e9d28e968bc6e0 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:22 +0800
Subject: [PATCH 11/15] arm: dts: medaitek: fix internal switch link speed of
mt7988
The CPU port of mt7988 internal switch uses 10Gb link speed.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7988-rfb.dts | 2 +-
arch/arm/dts/mt7988-sd-rfb.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -57,7 +57,7 @@
mediatek,switch = "mt7988";
fixed-link {
- speed = <1000>;
+ speed = <10000>;
full-duplex;
pause;
};
--- a/arch/arm/dts/mt7988-sd-rfb.dts
+++ b/arch/arm/dts/mt7988-sd-rfb.dts
@@ -48,7 +48,7 @@
mediatek,switch = "mt7988";
fixed-link {
- speed = <1000>;
+ speed = <10000>;
full-duplex;
pause;
};

103
package/boot/uboot-mediatek/patches/070-12-arm-dts-mediatek-add-support-for-all-three-GMACs-for.patch Normal file
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@ -0,0 +1,103 @@
From 64cf3dd0ef520a81a27359d83d58b64939e2aa06 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:27 +0800
Subject: [PATCH 12/15] arm: dts: mediatek: add support for all three GMACs for
mt7988
This patch add all three GMACs nodes for mt7988. Each GMAC can be
configured to connect to different ethernet switches/PHYs.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7988-rfb.dts | 3 +--
arch/arm/dts/mt7988-sd-rfb.dts | 3 +--
arch/arm/dts/mt7988.dtsi | 42 ++++++++++++++++++++++++++++++++--
3 files changed, 42 insertions(+), 6 deletions(-)
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -50,9 +50,8 @@
status = "okay";
};
-&eth {
+&eth0 {
status = "okay";
- mediatek,gmac-id = <0>;
phy-mode = "usxgmii";
mediatek,switch = "mt7988";
--- a/arch/arm/dts/mt7988-sd-rfb.dts
+++ b/arch/arm/dts/mt7988-sd-rfb.dts
@@ -41,9 +41,8 @@
status = "okay";
};
-&eth {
+&eth0 {
status = "okay";
- mediatek,gmac-id = <0>;
phy-mode = "usxgmii";
mediatek,switch = "mt7988";
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -587,11 +587,11 @@
#reset-cells = <1>;
};
- eth: ethernet@15100000 {
+ eth0: ethernet@15110100 {
compatible = "mediatek,mt7988-eth", "syscon";
reg = <0 0x15100000 0 0x20000>;
+ mediatek,gmac-id = <0>;
mediatek,ethsys = <&ethdma>;
- mediatek,sgmiisys = <&sgmiisys0>;
mediatek,usxgmiisys = <&usxgmiisys0>;
mediatek,xfi_pextp = <&xfi_pextp0>;
mediatek,xfi_pll = <&xfi_pll>;
@@ -602,6 +602,44 @@
#address-cells = <1>;
#size-cells = <0>;
mediatek,mcm;
+ status = "disabled";
+ };
+
+ eth1: ethernet@15110200 {
+ compatible = "mediatek,mt7988-eth", "syscon";
+ reg = <0 0x15100000 0 0x20000>;
+ mediatek,gmac-id = <1>;
+ mediatek,ethsys = <&ethdma>;
+ mediatek,sgmiisys = <&sgmiisys1>;
+ mediatek,usxgmiisys = <&usxgmiisys1>;
+ mediatek,xfi_pextp = <&xfi_pextp1>;
+ mediatek,xfi_pll = <&xfi_pll>;
+ mediatek,infracfg = <&topmisc>;
+ mediatek,toprgu = <&watchdog>;
+ resets = <&ethdma ETHDMA_FE_RST>;
+ reset-names = "fe";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mediatek,mcm;
+ status = "disabled";
+ };
+
+ eth2: ethernet@15110300 {
+ compatible = "mediatek,mt7988-eth", "syscon";
+ reg = <0 0x15100000 0 0x20000>;
+ mediatek,gmac-id = <2>;
+ mediatek,ethsys = <&ethdma>;
+ mediatek,sgmiisys = <&sgmiisys0>;
+ mediatek,usxgmiisys = <&usxgmiisys0>;
+ mediatek,xfi_pextp = <&xfi_pextp0>;
+ mediatek,xfi_pll = <&xfi_pll>;
+ mediatek,infracfg = <&topmisc>;
+ mediatek,toprgu = <&watchdog>;
+ resets = <&ethdma ETHDMA_FE_RST>;
+ reset-names = "fe";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mediatek,mcm;
status = "disabled";
};
};

81
package/boot/uboot-mediatek/patches/070-13-arm-dts-medaitek-add-flash-interface-driving-setting.patch Normal file
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@ -0,0 +1,81 @@
From 1090c6df3767da2c56d5827ba65ce91af8745420 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:41 +0800
Subject: [PATCH 13/15] arm: dts: medaitek: add flash interface driving
settings for mt7988
Add driving settings for both SPI and SD/eMMC interfaces to support ensure
flash devices is accessible for ram-booting.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7988-rfb.dts | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -101,6 +101,19 @@
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
+
+ conf-pu {
+ pins = "SPI0_CSB", "SPI0_HOLD", "SPI0_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+
+ conf-pd {
+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
+
};
spi2_pins: spi2-pins {
@@ -108,6 +121,18 @@
function = "spi";
groups = "spi2", "spi2_wp_hold";
};
+
+ conf-pu {
+ pins = "SPI2_CSB", "SPI2_HOLD", "SPI2_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+
+ conf-pd {
+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
};
mmc0_pins_default: mmc0default {
@@ -121,18 +146,25 @@
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
+ drive-strength = <MTK_DRIVE_4mA>;
+ mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
+ drive-strength = <MTK_DRIVE_6mA>;
+ mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-dsl {
pins = "EMMC_DSL";
+ mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
+ drive-strength = <MTK_DRIVE_4mA>;
+ mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
};

62
package/boot/uboot-mediatek/patches/070-14-arm-dts-mediatek-update-mt7981-mmc-node.patch Normal file
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@ -0,0 +1,62 @@
From 140303d0308738dfb04059333c9fc25b5159a776 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:55 +0800
Subject: [PATCH 14/15] arm: dts: mediatek: update mt7981 mmc node
1. Fix mmc clock order of mt7981 to match the clock name
2. Limit the max clock of SD to 50MHz to meet SD Card Spec 2.0
3. Increase the CLK pin driving strength to 8mA
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/arm/dts/mt7981-sd-rfb.dts | 6 ++++--
arch/arm/dts/mt7981.dtsi | 12 ++++++------
2 files changed, 10 insertions(+), 8 deletions(-)
--- a/arch/arm/dts/mt7981-sd-rfb.dts
+++ b/arch/arm/dts/mt7981-sd-rfb.dts
@@ -118,7 +118,7 @@
};
conf-clk {
pins = "SPI1_CS";
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-rst {
@@ -140,10 +140,12 @@
};
&mmc0 {
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>,
+ <&topckgen CLK_TOP_CB_NET2_D2>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
bus-width = <4>;
- max-frequency = <52000000>;
+ max-frequency = <50000000>;
cap-sd-highspeed;
r_smpl = <0>;
vmmc-supply = <&reg_3p3v>;
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -306,13 +306,13 @@
reg = <0x11230000 0x1000>,
<0x11C20000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_EMMC_400M>,
- <&topckgen CLK_TOP_EMMC_208M>,
+ clocks = <&topckgen CLK_TOP_EMMC_208M>,
+ <&topckgen CLK_TOP_EMMC_400M>,
<&infracfg CLK_INFRA_MSDC_CK>;
- assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>,
- <&topckgen CLK_TOP_EMMC_208M_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>,
- <&topckgen CLK_TOP_CB_M_D2>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
+ <&topckgen CLK_TOP_EMMC_400M_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_CB_NET2_D2>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};

36
package/boot/uboot-mediatek/patches/070-15-MAINTAINERS-update-file-list-for-MediaTek-ARM-platfo.patch Normal file
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@ -0,0 +1,36 @@
From 8707ea0360046522d0784135b6c9a7c564f9515c Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 17 Jan 2025 17:18:59 +0800
Subject: [PATCH 15/15] MAINTAINERS: update file list for MediaTek ARM platform
Add driver files for MediaTek ARM platform
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
MAINTAINERS | 5 +++++
1 file changed, 5 insertions(+)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -412,9 +412,13 @@ F: drivers/mmc/mtk-sd.c
F: drivers/phy/phy-mtk-*
F: drivers/pinctrl/mediatek/
F: drivers/power/domain/mtk-power-domain.c
+F: drivers/pci/pcie_mediatek_gen3.c
+F: drivers/pci/pcie_mediatek.c
+F: drivers/pwm/pwm-mtk.c
F: drivers/ram/mediatek/
F: drivers/spi/mtk_snfi_spi.c
F: drivers/spi/mtk_spim.c
+F: drivers/spi/mtk_snor.c
F: drivers/timer/mtk_timer.c
F: drivers/usb/host/xhci-mtk.c
F: drivers/usb/mtu3/
@@ -422,6 +426,7 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
+F: drivers/serial/serial_mtk.c
F: include/dt-bindings/clock/mediatek,*
F: include/dt-bindings/power/mediatek,*
F: tools/mtk_image.c

138
package/boot/uboot-mediatek/patches/071-01-pinctrl-mediatek-update-mt7981-pinctrl-driver-based-.patch Normal file
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@ -0,0 +1,138 @@
From 24e660265f11dad63687c5529cf732538946a197 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 24 Jan 2025 11:39:02 +0800
Subject: [PATCH] pinctrl: mediatek: update mt7981 pinctrl driver based on
upstream kernel
Update mt7981 pinctrl driver based on upstream kernel
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/pinctrl/mediatek/pinctrl-mt7981.c | 51 ++++++++++++++++++++---
1 file changed, 45 insertions(+), 6 deletions(-)
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
@@ -569,6 +569,11 @@ static const struct mtk_pin_desc mt7981_
MT7981_TYPE1_PIN(56, "WF_HB10"),
};
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins.
+ * The hardware probably has multiple combinations of these pinouts.
+ */
+
/* WA_AICE */
static const int mt7981_wa_aice1_pins[] = { 0, 1, };
static const int mt7981_wa_aice1_funcs[] = { 2, 2, };
@@ -632,6 +637,9 @@ static const int mt7981_wo0_jtag_1_funcs
static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
+static const int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
+static const int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
+
/* GBE_LED0 */
static const int mt7981_gbe_led0_pins[] = { 8, };
static const int mt7981_gbe_led0_funcs[] = { 3, };
@@ -718,6 +726,17 @@ static const int mt7981_drv_vbus_pins[]
static const int mt7981_drv_vbus_funcs[] = { 1, };
/* EMMC */
+static const int mt7981_emmc_reset_pins[] = { 15, };
+static const int mt7981_emmc_reset_funcs[] = { 2, };
+
+static const int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, };
+static const int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, };
+
+static const int mt7981_emmc_8_pins[] = {
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
+static const int mt7981_emmc_8_funcs[] = {
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+
static const int mt7981_emmc_45_pins[] = {
15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
static const int mt7981_emmc_45_funcs[] = {
@@ -754,6 +773,12 @@ static const int mt7981_uart1_0_funcs[]
static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
+static const int mt7981_uart1_2_pins[] = { 9, 10, };
+static const int mt7981_uart1_2_funcs[] = { 2, 2, };
+
+static const int mt7981_uart1_3_pins[] = { 26, 27, };
+static const int mt7981_uart1_3_funcs[] = { 2, 2, };
+
/* UART2 */
static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
@@ -832,6 +857,8 @@ static const struct mtk_group_desc mt798
PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
/* @GPIO(4,7) WM_JTAG(3) */
PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
+ /* @GPIO(4,5) WM_JTAG(4) */
+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
/* @GPIO(8) GBE_LED0(3) */
PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
/* @GPIO(4,6) PTA_EXT(4) */
@@ -844,7 +871,7 @@ static const struct mtk_group_desc mt798
PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
/* @GPIO(6,7) I2C(5) */
PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
- /* @GPIO(8): DFD_NTRST(6) */
+ /* @GPIO(0,1,4,5): DFD_NTRST(6) */
PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
/* @GPIO(9,10): WM_AICE(2) */
PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
@@ -870,6 +897,12 @@ static const struct mtk_group_desc mt798
PINCTRL_PIN_GROUP("udi", mt7981_udi),
/* @GPIO(14) DRV_VBUS(1) */
PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
+ /* @GPIO(15): EMMC_RSTB(2) */
+ PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset),
+ /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
+ PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4),
+ /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
+ PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8),
/* @GPIO(15,25): EMMC(2) */
PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
/* @GPIO(16,21): SNFI(3) */
@@ -888,8 +921,12 @@ static const struct mtk_group_desc mt798
PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
/* @GPIO(26,29): UART1(2) */
PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
+ /* @GPIO(9,10): UART1(2) */
+ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
+ /* @GPIO(26,27): UART1(2) */
+ PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3),
/* @GPIO(22,25): UART2(3) */
- PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_1),
+ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
/* @GPIO(22,24) PTA_EXT(4) */
PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
/* @GPIO(20,21): WM_UART(4) */
@@ -964,9 +1001,10 @@ static const struct mtk_io_type_desc mt7
*/
static const char *const mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2",
"wm_aice1_1", "wa_aice3", "wm_aice1_2", };
-static const char *const mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
- "uart1_0", "uart1_1", "uart2_0", "wm_aurt_1", "wm_aurt_2", "uart0", };
+static const char *const mt7981_uart_groups[] = { "net_wo0_uart_txd_0",
+ "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", "uart0", "uart1_0",
+ "uart1_1", "uart1_2", "uart1_3", "uart2_0", "uart2_0_tx_rx", "uart2_1",
+ "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
static const char *const mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
static const char *const mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
static const char *const mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk",
@@ -986,7 +1024,8 @@ static const char *const mt7981_i2c_grou
static const char *const mt7981_pcm_groups[] = { "pcm", };
static const char *const mt7981_udi_groups[] = { "udi", };
static const char *const mt7981_usb_groups[] = { "drv_vbus", };
-static const char *const mt7981_flash_groups[] = { "emmc_45", "snfi", };
+static const char *const mt7981_flash_groups[] = { "emmc_reset", "emmc_4",
+ "emmc_8", "emmc_45", "snfi", };
static const char *const mt7981_ethernet_groups[] = { "smi_mdc_mdio",
"gbe_ext_mdc_mdio", "wf0_mode1", "wf0_mode3", "mt7531_int", };
static const char *const mt7981_ant_groups[] = { "ant_sel", };

2
package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch
View File

@ -49,7 +49,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
config SYS_NAND_MAX_OOBFREE
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -40,3 +40,5 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPOR
@@ -40,3 +40,5 @@ obj-$(CONFIG_$(PHASE_)SPI_FLASH_SUPPORT)
obj-$(CONFIG_SPL_UBI) += ubispl/
endif

18
package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch
View File

@ -89,14 +89,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
depends on ENV_IS_IN_UBI
--- a/env/Makefile
+++ b/env/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_$(SPL_TPL_)ENV_IS_NOWHERE)
obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_MMC) += mmc.o
obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FAT) += fat.o
obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_EXT4) += ext4.o
+obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_MTD) += mtd.o
obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_NAND) += nand.o
obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_SPI_FLASH) += sf.o
obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FLASH) += flash.o
@@ -24,6 +24,7 @@ obj-$(CONFIG_$(PHASE_)ENV_IS_NOWHERE) +=
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MMC) += mmc.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FAT) += fat.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_EXT4) += ext4.o
+obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MTD) += mtd.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NAND) += nand.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_SPI_FLASH) += sf.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FLASH) += flash.o
--- a/env/env.c
+++ b/env/env.c
@@ -46,6 +46,9 @@ static enum env_location env_locations[]
@ -370,7 +370,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+};
--- a/include/env_internal.h
+++ b/include/env_internal.h
@@ -107,6 +107,7 @@ enum env_location {
@@ -108,6 +108,7 @@ enum env_location {
ENVL_FAT,
ENVL_FLASH,
ENVL_MMC,

173
package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch
View File

@ -13,13 +13,13 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
drivers/mtd/Makefile | 1 +
drivers/mtd/nmbm/Kconfig | 29 +
drivers/mtd/nmbm/Makefile | 5 +
drivers/mtd/nmbm/nmbm-core.c | 2936 +++++++++++++++++++++++++++++++
drivers/mtd/nmbm/nmbm-core.c | 3040 +++++++++++++++++++++++++++++++
drivers/mtd/nmbm/nmbm-debug.h | 37 +
drivers/mtd/nmbm/nmbm-debug.inl | 39 +
drivers/mtd/nmbm/nmbm-private.h | 137 ++
include/nmbm/nmbm-os.h | 66 +
include/nmbm/nmbm.h | 102 ++
10 files changed, 3354 insertions(+)
include/nmbm/nmbm-os.h | 68 +
include/nmbm/nmbm.h | 105 ++
10 files changed, 3463 insertions(+)
create mode 100644 drivers/mtd/nmbm/Kconfig
create mode 100644 drivers/mtd/nmbm/Makefile
create mode 100644 drivers/mtd/nmbm/nmbm-core.c
@ -31,15 +31,15 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -282,6 +282,8 @@ source "drivers/mtd/ubi/Kconfig"
source "drivers/mtd/nvmxip/Kconfig"
@@ -276,6 +276,8 @@ config SYS_NAND_MAX_CHIPS
help
The maximum number of NAND chips per device to be supported.
+source "drivers/mtd/nmbm/Kconfig"
+
endif
source "drivers/mtd/spi/Kconfig"
endmenu
source "drivers/mtd/ubi/Kconfig"
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_SPL_UBI) += ubispl/
@ -89,10 +89,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+obj-$(CONFIG_NMBM) += nmbm-core.o
--- /dev/null
+++ b/drivers/mtd/nmbm/nmbm-core.c
@@ -0,0 +1,2936 @@
@@ -0,0 +1,3040 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ * Copyright (C) 2021 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
@ -349,6 +349,37 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+}
+
+/*
+ * nmbm_panic_write_phys_page - Panic write page with retry
+ * @ni: NMBM instance structure
+ * @addr: linear address where the data will be written to
+ * @data: the main data to be written
+ *
+ * Write a page for at most NMBM_TRY_COUNT times.
+ */
+static bool nmbm_panic_write_phys_page(struct nmbm_instance *ni, uint64_t addr,
+ const void *data)
+{
+ int tries, ret;
+
+ if (ni->lower.flags & NMBM_F_READ_ONLY) {
+ nlog_err(ni, "%s called with NMBM_F_READ_ONLY set\n", addr);
+ return false;
+ }
+
+ for (tries = 0; tries < NMBM_TRY_COUNT; tries++) {
+ ret = ni->lower.panic_write_page(ni->lower.arg, addr, data);
+ if (!ret)
+ return true;
+
+ nmbm_reset_chip(ni);
+ }
+
+ nlog_err(ni, "Panic page write failed at address 0x%08llx\n", addr);
+
+ return false;
+}
+
+/*
+ * nmbm_erase_phys_block - Erase a block with retry
+ * @ni: NMBM instance structure
+ * @addr: Linear address
@ -752,7 +783,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ addr = ba2addr(ni, ba);
+
+ for (off = 0; off < ni->lower.erasesize; off += ni->lower.writesize) {
+ schedule();
+ WATCHDOG_RESET();
+
+ ret = nmbm_read_phys_page(ni, addr + off, ni->page_cache, NULL,
+ NMBM_MODE_PLACE_OOB);
@ -791,7 +822,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ bool success;
+
+ while (ba < limit) {
+ schedule();
+ WATCHDOG_RESET();
+
+ if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD)
+ goto next_block;
@ -842,7 +873,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ addr = ba2addr(ni, ba);
+
+ for (off = 0; off < ni->lower.erasesize; off += ni->lower.writesize) {
+ schedule();
+ WATCHDOG_RESET();
+
+ /* Prepare page data. fill 0xff to unused region */
+ memcpy(ni->page_cache, data, size);
@ -886,7 +917,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ bool success;
+
+ while (ba > limit) {
+ schedule();
+ WATCHDOG_RESET();
+
+ if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD)
+ goto next_block;
@ -941,7 +972,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ int ret;
+
+ while (sizeremain) {
+ schedule();
+ WATCHDOG_RESET();
+
+ leading = off & ni->writesize_mask;
+ chunksize = ni->lower.writesize - leading;
@ -991,7 +1022,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ int ret;
+
+ while (sizeremain) {
+ schedule();
+ WATCHDOG_RESET();
+
+ leading = off & ni->writesize_mask;
+ chunksize = ni->lower.writesize - leading;
@ -1047,7 +1078,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ bool success;
+
+ while (sizeremain && ba < limit) {
+ schedule();
+ WATCHDOG_RESET();
+
+ chunksize = sizeremain;
+ if (chunksize > ni->lower.erasesize)
@ -1309,7 +1340,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+
+ /* Try to write new info table next to the existing table */
+ while (write_ba >= ni->mapping_blocks_ba) {
+ schedule();
+ WATCHDOG_RESET();
+
+ success = nmbm_write_info_table(ni, write_ba,
+ ni->mapping_blocks_top_ba,
@ -1428,7 +1459,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+
+ /* Try to write temporary info table into spare unmapped blocks */
+ while (write_ba >= ni->mapping_blocks_ba) {
+ schedule();
+ WATCHDOG_RESET();
+
+ success = nmbm_write_info_table(ni, write_ba,
+ ni->mapping_blocks_top_ba,
@ -1514,7 +1545,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+
+ /* Write new backup info table. */
+ while (write_ba >= main_table_end_ba) {
+ schedule();
+ WATCHDOG_RESET();
+
+ success = nmbm_write_info_table(ni, write_ba,
+ ni->mapping_blocks_top_ba,
@ -1903,7 +1934,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ int ret;
+
+ while (sizeremain && ba < limit) {
+ schedule();
+ WATCHDOG_RESET();
+
+ if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD)
+ goto next_block;
@ -1996,7 +2027,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ bool success;
+
+ while (ba < limit - size2blk(ni, ni->info_table_size)) {
+ schedule();
+ WATCHDOG_RESET();
+
+ success = nmbm_try_load_info_table(ni, ba, table_end_ba,
+ write_count,
@ -2208,7 +2239,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ limit = block_count - ni->lower.max_reserved_blocks;
+
+ while (ba >= limit) {
+ schedule();
+ WATCHDOG_RESET();
+
+ ba--;
+ addr = ba2addr(ni, ba);
@ -2222,7 +2253,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ */
+ for (off = 0; off < ni->lower.erasesize;
+ off += ni->lower.writesize) {
+ schedule();
+ WATCHDOG_RESET();
+
+ ret = nmbn_read_data(ni, addr + off, &sig,
+ sizeof(sig));
@ -2281,7 +2312,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ return false;
+ }
+
+ if (!nld->oobsize || !is_power_of_2(nld->oobsize)) {
+ if (!nld->oobsize) {
+ nmbm_log_lower(nld, NMBM_LOG_ERR,
+ "Page spare size %u is not valid\n", nld->oobsize);
+ return false;
@ -2594,7 +2625,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ end_ba = addr2ba(ni, addr + size - 1);
+
+ while (start_ba <= end_ba) {
+ schedule();
+ WATCHDOG_RESET();
+
+ ret = nmbm_erase_logic_block(ni, start_ba);
+ if (ret) {
@ -2726,7 +2757,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ }
+
+ while (sizeremain) {
+ schedule();
+ WATCHDOG_RESET();
+
+ leading = off & ni->writesize_mask;
+ chunksize = ni->lower.writesize - leading;
@ -2822,6 +2853,53 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+}
+
+/*
+ * nmbm_panic_write_logic_page - Panic write page based on logic address
+ * @ni: NMBM instance structure
+ * @addr: logic linear address
+ * @data: buffer contains main data. optional.
+ */
+static int nmbm_panic_write_logic_page(struct nmbm_instance *ni, uint64_t addr,
+ const void *data)
+{
+ uint32_t lb, pb, offset;
+ uint64_t paddr;
+ bool success;
+
+ /* Extract block address and in-block offset */
+ lb = addr2ba(ni, addr);
+ offset = addr & ni->erasesize_mask;
+
+ /* Map logic block to physical block */
+ pb = ni->block_mapping[lb];
+
+ /* Whether the logic block is good (has valid mapping) */
+ if ((int32_t)pb < 0) {
+ nlog_debug(ni, "Logic block %u is a bad block\n", lb);
+ return -EIO;
+ }
+
+ /* Fail if physical block is marked bad */
+ if (nmbm_get_block_state(ni, pb) == BLOCK_ST_BAD)
+ return -EIO;
+
+ /* Assemble new address */
+ paddr = ba2addr(ni, pb) + offset;
+
+ success = nmbm_panic_write_phys_page(ni, paddr, data);
+ if (success)
+ return 0;
+
+ /*
+ * Do not remap bad block here. Just mark this block in state table.
+ * Remap this block on erasing.
+ */
+ nmbm_set_block_state(ni, pb, BLOCK_ST_NEED_REMAP);
+ nmbm_update_info_table(ni);
+
+ return -EIO;
+}
+
+/*
+ * nmbm_write_single_page - Write one page based on logic address
+ * @ni: NMBM instance structure
+ * @addr: logic linear address
@ -2851,6 +2929,32 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+}
+
+/*
+ * nmbm_panic_write_single_page - Panic write one page based on logic address
+ * @ni: NMBM instance structure
+ * @addr: logic linear address
+ * @data: buffer contains main data. optional.
+ */
+int nmbm_panic_write_single_page(struct nmbm_instance *ni, uint64_t addr,
+ const void *data)
+{
+ if (!ni)
+ return -EINVAL;
+
+ /* Sanity check */
+ if (ni->protected || (ni->lower.flags & NMBM_F_READ_ONLY)) {
+ nlog_debug(ni, "Device is forced read-only\n");
+ return -EROFS;
+ }
+
+ if (addr >= ba2addr(ni, ni->data_block_count)) {
+ nlog_err(ni, "Address 0x%llx is invalid\n", addr);
+ return -EINVAL;
+ }
+
+ return nmbm_panic_write_logic_page(ni, addr, data);
+}
+
+/*
+ * nmbm_write_range - Write data without oob
+ * @ni: NMBM instance structure
+ * @addr: logic linear address
@ -2893,7 +2997,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ }
+
+ while (sizeremain) {
+ schedule();
+ WATCHDOG_RESET();
+
+ leading = off & ni->writesize_mask;
+ chunksize = ni->lower.writesize - leading;
@ -3250,7 +3354,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+#endif /* _NMBM_PRIVATE_H_ */
--- /dev/null
+++ b/include/nmbm/nmbm-os.h
@@ -0,0 +1,66 @@
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
@ -3265,7 +3369,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+
+#include <div64.h>
+#include <stdbool.h>
+#include <watchdog.h>
+#include <cyclic.h>
+#include <u-boot/crc.h>
+#include <linux/errno.h>
+#include <linux/log2.h>
@ -3316,10 +3420,12 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+#define NMBM_DEFAULT_LOG_LEVEL 1
+#endif
+
+#define WATCHDOG_RESET schedule
+
+#endif /* _NMBM_OS_H_ */
--- /dev/null
+++ b/include/nmbm/nmbm.h
@@ -0,0 +1,102 @@
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
@ -3374,6 +3480,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ */
+ int (*read_page)(void *arg, uint64_t addr, void *buf, void *oob, enum nmbm_oob_mode mode);
+ int (*write_page)(void *arg, uint64_t addr, const void *buf, const void *oob, enum nmbm_oob_mode mode);
+ int (*panic_write_page)(void *arg, uint64_t addr, const void *buf);
+ int (*erase_block)(void *arg, uint64_t addr);
+
+ int (*is_bad_block)(void *arg, uint64_t addr);
@ -3410,6 +3517,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+int nmbm_write_single_page(struct nmbm_instance *ni, uint64_t addr,
+ const void *data, const void *oob,
+ enum nmbm_oob_mode mode);
+int nmbm_panic_write_single_page(struct nmbm_instance *ni, uint64_t addr,
+ const void *data);
+int nmbm_write_range(struct nmbm_instance *ni, uint64_t addr, size_t size,
+ const void *data, enum nmbm_oob_mode mode,
+ size_t *retlen);

4
package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -372,6 +372,20 @@ static int initr_nand(void)
@@ -381,6 +381,20 @@ static int initr_nand(void)
}
#endif
@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
#if defined(CONFIG_CMD_ONENAND)
/* go init the NAND */
static int initr_onenand(void)
@@ -663,6 +677,9 @@ static init_fnc_t init_sequence_r[] = {
@@ -694,6 +708,9 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_CMD_ONENAND
initr_onenand,
#endif

8
package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1465,6 +1465,12 @@ config CMD_NAND_TORTURE
@@ -1492,6 +1492,12 @@ config CMD_NAND_TORTURE
endif # CMD_NAND
@ -35,9 +35,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
obj-$(CONFIG_CMD_MUX) += mux.o
obj-$(CONFIG_CMD_NAND) += nand.o
+obj-$(CONFIG_CMD_NMBM) += nmbm.o
obj-$(CONFIG_CMD_NET) += net.o
obj-$(CONFIG_ENV_SUPPORT) += nvedit.o
obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o
ifdef CONFIG_NET
obj-$(CONFIG_CMD_NET) += net.o net-common.o
else ifdef CONFIG_NET_LWIP
--- /dev/null
+++ b/cmd/nmbm.c
@@ -0,0 +1,327 @@

6
package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -721,6 +721,42 @@ out_put_mtd:
@@ -730,6 +730,42 @@ out_put_mtd:
return CMD_RET_SUCCESS;
}
@ -63,7 +63,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
#ifdef CONFIG_AUTO_COMPLETE
static int mtd_name_complete(int argc, char *const argv[], char last_char,
int maxv, char *cmdv[])
@@ -768,6 +804,7 @@ U_BOOT_LONGHELP(mtd,
@@ -777,6 +813,7 @@ U_BOOT_LONGHELP(mtd,
"\n"
"Specific functions:\n"
"mtd bad <name>\n"
@ -71,7 +71,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
#if CONFIG_IS_ENABLED(CMD_MTD_OTP)
"mtd otpread <name> [u|f] <off> <size>\n"
"mtd otpwrite <name> <off> <hex string>\n"
@@ -808,4 +845,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
@@ -817,4 +854,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
U_BOOT_SUBCMD_MKENT_COMPLETE(erase, 4, 0, do_mtd_erase,
mtd_name_complete),
U_BOOT_SUBCMD_MKENT_COMPLETE(bad, 2, 1, do_mtd_bad,

44
package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
View File

@ -7,29 +7,29 @@ Add an env driver for NMBM upper MTD layer
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
cmd/nvedit.c | 3 +-
env/Kconfig | 19 ++++-
env/Makefile | 1 +
env/env.c | 3 +
env/nmbm.c | 155 +++++++++++++++++++++++++++++++++++++++++
include/env_internal.h | 1 +
tools/Makefile | 1 +
7 files changed, 180 insertions(+), 3 deletions(-)
6 files changed, 178 insertions(+), 2 deletions(-)
create mode 100644 env/nmbm.c
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -59,6 +59,7 @@ config ENV_IS_DEFAULT
def_bool y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \
!ENV_IS_IN_FAT && !ENV_IS_IN_FLASH && \
@@ -61,7 +61,7 @@ config ENV_IS_DEFAULT
!ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
+ !ENV_IS_IN_NMBM && \
!ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
!ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
!ENV_IS_IN_UBI && !ENV_IS_IN_MTD
@@ -315,6 +316,21 @@ config ENV_RANGE
Specifying a range with more erase blocks than are needed to hold
CONFIG_ENV_SIZE allows bad blocks within the range to be avoided.
- !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
+ !ENV_IS_IN_UBI && !ENV_IS_IN_NMBM && !ENV_IS_IN_MTD
select ENV_IS_NOWHERE
config ENV_IS_NOWHERE
@@ -305,6 +305,21 @@ config ENV_IS_IN_NAND
Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
using CONFIG_ENV_OFFSET_OOB.
+config ENV_IS_IN_NMBM
+ bool "Environment in a NMBM upper MTD layer"
@ -46,10 +46,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+ area within the first NAND device. CONFIG_ENV_OFFSET must be
+ aligned to an erase block boundary.
+
config ENV_IS_IN_NVRAM
bool "Environment in a non-volatile RAM"
depends on !CHAIN_OF_TRUST
@@ -591,7 +607,7 @@ config ENV_MTD_NAME
config ENV_RANGE
hex "Length of the region in which the environment can be written"
depends on ENV_IS_IN_NAND
@@ -591,7 +606,7 @@ config ENV_MTD_NAME
config ENV_OFFSET
hex "Environment offset"
depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
@ -60,13 +60,13 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
default 0xF0000 if ARCH_SUNXI
--- a/env/Makefile
+++ b/env/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FAT) +
obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_EXT4) += ext4.o
obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_MTD) += mtd.o
obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_NAND) += nand.o
+obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_NMBM) += nmbm.o
obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_SPI_FLASH) += sf.o
obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FLASH) += flash.o
@@ -26,6 +26,7 @@ obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FAT) +=
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_EXT4) += ext4.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MTD) += mtd.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NAND) += nand.o
+obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NMBM) += nmbm.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_SPI_FLASH) += sf.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FLASH) += flash.o
--- a/env/env.c
+++ b/env/env.c
@ -240,7 +240,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+};
--- a/include/env_internal.h
+++ b/include/env_internal.h
@@ -109,6 +109,7 @@ enum env_location {
@@ -110,6 +110,7 @@ enum env_location {
ENVL_MMC,
ENVL_MTD,
ENVL_NAND,

6
package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch
View File

@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1465,6 +1465,14 @@ config CMD_NAND_TORTURE
@@ -1492,6 +1492,14 @@ config CMD_NAND_TORTURE
endif # CMD_NAND
@ -49,8 +49,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
obj-$(CONFIG_CMD_NAND) += nand.o
+obj-$(CONFIG_CMD_NAND_EXT) += nand-ext.o
obj-$(CONFIG_CMD_NMBM) += nmbm.o
obj-$(CONFIG_CMD_NET) += net.o
obj-$(CONFIG_ENV_SUPPORT) += nvedit.o
ifdef CONFIG_NET
obj-$(CONFIG_CMD_NET) += net.o net-common.o
--- /dev/null
+++ b/cmd/nand-ext.c
@@ -0,0 +1,1062 @@

8
package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -2958,6 +2958,100 @@ static int spi_nor_init_params(struct sp
@@ -3248,6 +3248,100 @@ static int spi_nor_init_params(struct sp
return 0;
}
@ -114,7 +114,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
{
size_t i;
@@ -4077,6 +4171,7 @@ int spi_nor_scan(struct spi_nor *nor)
@@ -4450,6 +4544,7 @@ int spi_nor_scan(struct spi_nor *nor)
nor->write = spi_nor_write_data;
nor->read_reg = spi_nor_read_reg;
nor->write_reg = spi_nor_write_reg;
@ -124,7 +124,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -29,6 +29,7 @@
@@ -32,6 +32,7 @@
#define SNOR_MFR_SPANSION CFI_MFR_AMD
#define SNOR_MFR_SST CFI_MFR_SST
#define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
@ -132,7 +132,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
#define SNOR_MFR_CYPRESS 0x34
/*
@@ -567,6 +568,7 @@ struct spi_nor {
@@ -590,6 +591,7 @@ struct spi_nor {
void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);

15
package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -413,6 +413,14 @@ static int do_spi_protect(int argc, char
@@ -421,6 +421,14 @@ static int do_spi_protect(int argc, char
return ret == 0 ? 0 : 1;
}
@ -27,7 +27,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
enum {
STAGE_ERASE,
STAGE_CHECK,
@@ -607,6 +615,8 @@ static int do_spi_flash(struct cmd_tbl *
@@ -615,6 +623,8 @@ static int do_spi_flash(struct cmd_tbl *
ret = do_spi_flash_erase(argc, argv);
else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0)
ret = do_spi_protect(argc, argv);
@ -36,11 +36,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test"))
ret = do_spi_flash_test(argc, argv);
else
@@ -637,6 +647,7 @@ U_BOOT_LONGHELP(sf,
#ifdef CONFIG_CMD_SF_TEST
"\nsf test offset len - run a very basic destructive test"
@@ -643,8 +653,9 @@ U_BOOT_LONGHELP(sf,
" at address 'sector'"
#endif
+ "sf uuid - read uuid from flash"
#ifdef CONFIG_CMD_SF_TEST
- "\nsf test offset len - run a very basic destructive test"
+ "\nsf test offset len - run a very basic destructive test"
#endif
+ "\nsf uuid - read uuid from flash"
);
U_BOOT_CMD(

284
package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch
View File

@ -7,48 +7,24 @@ Add ability to use shortkey to select item for bootmenu command
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
cmd/bootmenu.c | 34 ++++++++++++++++++++++++-----
common/menu.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++--
include/menu.h | 12 +++++++----
3 files changed, 93 insertions(+), 11 deletions(-)
cmd/bootmenu.c | 28 +++++++++++++++++++++++---
common/menu.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++
include/cli.h | 2 ++
include/menu.h | 3 +++
4 files changed, 84 insertions(+), 3 deletions(-)
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -88,6 +88,7 @@ static char *bootmenu_choice_entry(void
struct bootmenu_data *menu = data;
struct bootmenu_entry *iter;
enum bootmenu_key key = BKEY_NONE;
+ int choice = -1;
int i;
cli_ch_init(cch);
@@ -95,10 +96,10 @@ static char *bootmenu_choice_entry(void
while (1) {
if (menu->delay >= 0) {
/* Autoboot was not stopped */
- key = bootmenu_autoboot_loop(menu, cch);
+ key = bootmenu_autoboot_loop(menu, cch, &choice);
} else {
/* Some key was pressed, so autoboot was stopped */
- key = bootmenu_loop(menu, cch);
+ key = bootmenu_loop(menu, cch, &choice);
}
switch (key) {
@@ -114,6 +115,12 @@ static char *bootmenu_choice_entry(void
@@ -114,6 +114,8 @@ static char *bootmenu_choice_entry(void
++menu->active;
/* no menu key selected, regenerate menu */
return NULL;
+ case BKEY_CHOICE:
+ menu->active = choice;
+ if (!menu->last_choiced) {
+ menu->last_choiced = true;
+ return NULL;
+ }
+ menu->active = cch->choice;
case BKEY_SELECT:
iter = menu->first;
for (i = 0; i < menu->active; ++i)
@@ -182,6 +189,9 @@ static int prepare_bootmenu_entry(struct
@@ -182,6 +184,9 @@ static int prepare_bootmenu_entry(struct
unsigned short int i = *index;
struct bootmenu_entry *entry = NULL;
struct bootmenu_entry *iter = *current;
@ -58,24 +34,28 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
while ((option = bootmenu_getoption(i))) {
@@ -196,11 +206,24 @@ static int prepare_bootmenu_entry(struct
@@ -196,11 +201,28 @@ static int prepare_bootmenu_entry(struct
if (!entry)
return -ENOMEM;
- entry->title = strndup(option, sep - option);
+ /* Add KEY_CHOICE support: '%d. %s\0' : len --> len + 4 */
+ /* Add BKEY_CHOICE support: '%c. %s\0' : len --> len + 4 */
+ len = sep - option + 4;
+
+ choice_option = malloc(len);
+ if (!choice_option) {
+ free(entry->title);
+ free(entry);
+ return -ENOMEM;
+ }
+
+ if (!get_choice_char(i, &choice_char))
+ len = snprintf(choice_option, len, "%c. %s", choice_char, option);
+ else
+ len = snprintf(choice_option, len, " %s", option);
+
+ entry->title = strndup(choice_option, len);
+
if (!entry->title) {
free(entry);
return -ENOMEM;
@ -84,15 +64,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
entry->command = strdup(sep + 1);
if (!entry->command) {
@@ -347,6 +370,7 @@ static struct bootmenu_data *bootmenu_cr
menu->active = 0;
menu->last_active = -1;
menu->first = NULL;
+ menu->last_choiced = false;
default_str = env_get("bootmenu_default");
if (default_str)
@@ -382,9 +406,9 @@ static struct bootmenu_data *bootmenu_cr
@@ -382,9 +404,9 @@ static struct bootmenu_data *bootmenu_cr
/* Add Quit entry if exiting bootmenu is disabled */
if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE))
@ -106,7 +78,15 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
free(entry);
--- a/common/menu.c
+++ b/common/menu.c
@@ -49,6 +49,33 @@ struct menu {
@@ -8,6 +8,7 @@
#include <cli.h>
#include <malloc.h>
#include <errno.h>
+#include <linux/ctype.h>
#include <linux/delay.h>
#include <linux/list.h>
#include <watchdog.h>
@@ -49,6 +50,33 @@ struct menu {
int item_cnt;
};
@ -140,185 +120,87 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
/*
* An iterator function for menu items. callback will be called for each item
* in m, with m, a pointer to the item, and extra being passed to callback. If
@@ -437,7 +464,7 @@ int menu_destroy(struct menu *m)
}
enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu,
- struct cli_ch_state *cch)
+ struct cli_ch_state *cch, int *choice)
@@ -441,6 +469,7 @@ enum bootmenu_key bootmenu_autoboot_loop
{
enum bootmenu_key key = BKEY_NONE;
int i, c;
@@ -472,6 +499,19 @@ enum bootmenu_key bootmenu_autoboot_loop
break;
default:
key = BKEY_NONE;
+ if (cch->esc_len || !choice)
+ break;
+
+ *choice = find_choice(c);
+ if ((*choice >= 0 &&
+ *choice < menu->count - 1)) {
+ key = BKEY_CHOICE;
+ } else if (c == '0') {
+ *choice = menu->count - 1;
+ key = BKEY_CHOICE;
+ } else {
+ key = BKEY_NONE;
+ }
break;
}
break;
@@ -492,7 +532,8 @@ enum bootmenu_key bootmenu_autoboot_loop
return key;
}
+ int choice;
-enum bootmenu_key bootmenu_conv_key(int ichar)
+enum bootmenu_key bootmenu_conv_key(struct bootmenu_data *menu, int ichar,
+ int *choice)
{
enum bootmenu_key key;
while (menu->delay > 0) {
if (ansi)
@@ -458,6 +487,18 @@ enum bootmenu_key bootmenu_autoboot_loop
menu->delay = -1;
c = getchar();
@@ -524,6 +565,20 @@ enum bootmenu_key bootmenu_conv_key(int
case ' ':
key = BKEY_SPACE;
break;
+ case '0' ... '9':
+ case 'a' ... 'z':
+ if (choice && menu) {
+ *choice = find_choice(ichar);
+ if ((*choice >= 0 && *choice < menu->count - 1)) {
+ choice = find_choice(c);
+ if ((choice >= 0 &&
+ choice < menu->count - 1)) {
+ cch->choice = choice;
+ key = BKEY_CHOICE;
+ break;
+ } else if (ichar == '0') {
+ *choice = menu->count - 1;
+ } else if (c == '0') {
+ cch->choice = menu->count - 1;
+ key = BKEY_CHOICE;
+ break;
+ }
+ }
+ fallthrough;
default:
key = BKEY_NONE;
break;
@@ -533,11 +588,17 @@ enum bootmenu_key bootmenu_conv_key(int
}
+
ichar = cli_ch_process(cch, c);
enum bootmenu_key bootmenu_loop(struct bootmenu_data *menu,
- struct cli_ch_state *cch)
+ struct cli_ch_state *cch,
+ int *choice)
switch (ichar) {
@@ -537,6 +578,7 @@ enum bootmenu_key bootmenu_loop(struct b
{
enum bootmenu_key key;
int c, errchar = 0;
+ int choice;
+ if (menu->last_choiced) {
+ menu->last_choiced = false;
+ return BKEY_SELECT;
+ }
+
c = cli_ch_process(cch, 0);
if (!c) {
while (!c && !tstc()) {
@@ -552,7 +613,7 @@ enum bootmenu_key bootmenu_loop(struct b
@@ -548,6 +590,18 @@ enum bootmenu_key bootmenu_loop(struct b
}
if (!c) {
c = getchar();
+
+ choice = find_choice(c);
+ if ((choice >= 0 &&
+ choice < menu->count - 1)) {
+ cch->choice = choice;
+ return BKEY_CHOICE;
+
+ } else if (c == '0') {
+ cch->choice = menu->count - 1;
+ return BKEY_CHOICE;
+ }
+
c = cli_ch_process(cch, c);
}
}
- key = bootmenu_conv_key(c);
+ key = bootmenu_conv_key(menu, c, choice);
return key;
}
--- a/include/menu.h
+++ b/include/menu.h
@@ -6,6 +6,8 @@
#ifndef __MENU_H__
#define __MENU_H__
+#include <linux/ctype.h>
+
struct cli_ch_state;
struct menu;
@@ -20,6 +22,8 @@ int menu_get_choice(struct menu *m, void
int menu_item_add(struct menu *m, char *item_key, void *item_data);
int menu_destroy(struct menu *m);
int menu_default_choice(struct menu *m, void **choice);
+/* Add KEY_CHOICE support */
+int get_choice_char(int index, char *result);
/**
* menu_show() Show a boot menu
@@ -43,6 +47,7 @@ struct bootmenu_data {
int last_active; /* last active menu entry */
int count; /* total count of menu entries */
struct bootmenu_entry *first; /* first menu entry */
+ bool last_choiced;
--- a/include/cli.h
+++ b/include/cli.h
@@ -23,6 +23,8 @@ struct cli_ch_state {
char esc_save[8];
int emit_upto;
bool emitting;
+ /* mediatek bootmenu choice feature */
+ char choice;
};
/** enum bootmenu_key - keys that can be returned by the bootmenu */
@@ -53,6 +58,7 @@ enum bootmenu_key {
/**
--- a/include/menu.h
+++ b/include/menu.h
@@ -37,6 +37,8 @@ int menu_default_choice(struct menu *m,
*/
int menu_show(int bootdelay);
+int get_choice_char(int index, char *result);
+
struct bootmenu_data {
int delay; /* delay for autoboot */
int active; /* active menu entry */
@@ -51,6 +53,7 @@ enum bootmenu_key {
BKEY_UP,
BKEY_DOWN,
BKEY_SELECT,
+ BKEY_CHOICE,
BKEY_QUIT,
BKEY_SAVE,
+ BKEY_CHOICE,
/* 'extra' keys, which are used by menus but not cedit */
BKEY_PLUS,
@@ -83,7 +89,7 @@ enum bootmenu_key {
* anything else: KEY_NONE
*/
enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu,
- struct cli_ch_state *cch);
+ struct cli_ch_state *cch, int *choice);
/**
* bootmenu_loop() - handle waiting for a keypress when autoboot is disabled
@@ -109,7 +115,7 @@ enum bootmenu_key bootmenu_autoboot_loop
* Space: BKEY_SPACE
*/
enum bootmenu_key bootmenu_loop(struct bootmenu_data *menu,
- struct cli_ch_state *cch);
+ struct cli_ch_state *cch, int *choice);
/**
* bootmenu_conv_key() - Convert a U-Boot keypress into a menu key
@@ -117,6 +123,7 @@ enum bootmenu_key bootmenu_loop(struct b
* @ichar: Keypress to convert (ASCII, including control characters)
* Returns: Menu key that corresponds to @ichar, or BKEY_NONE if none
*/
-enum bootmenu_key bootmenu_conv_key(int ichar);
+enum bootmenu_key bootmenu_conv_key(struct bootmenu_data *menu, int ichar,
+ int *choice);
#endif /* __MENU_H__ */
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -239,7 +239,7 @@ char *eficonfig_choice_entry(void *data)
cli_ch_init(cch);
while (1) {
- key = bootmenu_loop((struct bootmenu_data *)efi_menu, cch);
+ key = bootmenu_loop((struct bootmenu_data *)efi_menu, cch, NULL);
switch (key) {
case BKEY_UP:
@@ -1881,7 +1881,7 @@ char *eficonfig_choice_change_boot_order
cli_ch_init(cch);
while (1) {
- key = bootmenu_loop(NULL, cch);
+ key = bootmenu_loop(NULL, cch, NULL);
switch (key) {
case BKEY_PLUS:
--- a/boot/bootflow_menu.c
+++ b/boot/bootflow_menu.c
@@ -240,7 +240,7 @@ int bootflow_menu_run(struct bootstd_pri
key = 0;
if (ichar) {
- key = bootmenu_conv_key(ichar);
+ key = bootmenu_conv_key(NULL, ichar, NULL);
if (key == BKEY_NONE)
key = ichar;
}

6
package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch
View File

@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
};
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -77,6 +77,22 @@
@@ -53,6 +53,22 @@
#size-cells = <0>;
};
@ -55,7 +55,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
reg = <0x11014000 0x1000>;
--- a/configs/mt7622_rfb_defconfig
+++ b/configs/mt7622_rfb_defconfig
@@ -22,6 +22,7 @@ CONFIG_SYS_PROMPT="MT7622> "
@@ -20,6 +20,7 @@ CONFIG_SYS_PROMPT="MT7622> "
CONFIG_SYS_MAXARGS=8
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_MMC=y
@ -63,7 +63,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
CONFIG_CMD_PCI=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_PING=y
@@ -42,6 +43,9 @@ CONFIG_CLK=y
@@ -37,6 +38,9 @@ CONFIG_CLK=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y

2
package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch
View File

@ -18,7 +18,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1190,6 +1190,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -1195,6 +1195,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
mt7981-rfb.dtb \

11
package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -697,6 +697,7 @@ static int set_4byte(struct spi_nor *nor
@@ -758,6 +758,7 @@ static int set_4byte(struct spi_nor *nor
case SNOR_MFR_ISSI:
case SNOR_MFR_MACRONIX:
case SNOR_MFR_WINBOND:
@ -23,17 +23,18 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -83,7 +83,8 @@ const struct flash_info spi_nor_ids[] =
@@ -83,7 +83,9 @@ const struct flash_info spi_nor_ids[] =
{ INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
{ INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
- { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
+ { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("en25qx128", 0x1c7118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("en25qh256", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
@@ -149,6 +150,11 @@ const struct flash_info spi_nor_ids[] =
@@ -149,6 +151,11 @@ const struct flash_info spi_nor_ids[] =
{INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
{
@ -45,7 +46,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
@@ -490,6 +496,16 @@ const struct flash_info spi_nor_ids[] =
@@ -520,6 +527,16 @@ const struct flash_info spi_nor_ids[] =
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
@ -62,7 +63,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
@@ -549,6 +565,11 @@ const struct flash_info spi_nor_ids[] =
@@ -583,6 +600,11 @@ const struct flash_info spi_nor_ids[] =
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

4
package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -864,6 +864,14 @@ config MMC_MTK
@@ -876,6 +876,14 @@ config MMC_MTK
This is needed if support for any SD/SDIO/MMC devices is required.
If unsure, say N.
@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
config FSL_SDHC_V2_3
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -83,3 +83,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm
@@ -84,3 +84,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
obj-$(CONFIG_MMC_MTK) += mtk-sd.o
obj-$(CONFIG_MMC_SDHCI_F_SDH30) += f_sdh30.o

6
package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch
View File

@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -212,8 +212,8 @@ bad:
@@ -213,8 +213,8 @@ bad:
return err;
}
@ -25,7 +25,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
{
struct ubi_mkvol_req req;
int err;
@@ -246,7 +246,7 @@ static int ubi_create_vol(char *volume,
@@ -247,7 +247,7 @@ static int ubi_create_vol(char *volume,
return ubi_create_volume(ubi, &req);
}
@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
{
struct ubi_volume *vol;
int i;
@@ -261,7 +261,7 @@ static struct ubi_volume *ubi_find_volum
@@ -262,7 +262,7 @@ static struct ubi_volume *ubi_find_volum
return NULL;
}

2
package/boot/uboot-mediatek/patches/100-25-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -225,7 +225,11 @@ int ubi_create_vol(char *volume, int64_t
@@ -226,7 +226,11 @@ int ubi_create_vol(char *volume, int64_t
req.vol_id = vol_id;
req.alignment = 1;

2
package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch
View File

@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -689,6 +689,12 @@ config ENV_UBI_VOLUME_REDUND
@@ -688,6 +688,12 @@ config ENV_UBI_VOLUME_REDUND
help
Name of the redundant volume that you want to store the environment in.

5
package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch
View File

@ -12,7 +12,7 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support
--- a/board/mediatek/mt7622/mt7622_rfb.c
+++ b/board/mediatek/mt7622/mt7622_rfb.c
@@ -9,6 +9,11 @@
@@ -9,9 +9,47 @@
#include <init.h>
#include <asm/global_data.h>
@ -24,8 +24,7 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -22,3 +27,36 @@ int board_late_init(void)
env_relocate();
{
return 0;
}
+

149
package/boot/uboot-mediatek/patches/101-01-mtd-spinand-add-support-for-FORESEE-F35SQA002G.patch Normal file
View File

@ -0,0 +1,149 @@
From 49c8e854869d673df8452f24dfa8989cd0f615a8 Mon Sep 17 00:00:00 2001
From: Martin Kurbanov <mmkurbanov@salutedevices.com>
Date: Mon, 2 Oct 2023 17:04:58 +0300
Subject: [PATCH] mtd: spinand: add support for FORESEE F35SQA002G
Add support for FORESEE F35SQA002G SPI NAND.
Datasheet:
https://www.longsys.com/uploads/LM-00006FORESEEF35SQA002GDatasheet_1650183701.pdf
Signed-off-by: Martin Kurbanov <mmkurbanov@salutedevices.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20231002140458.147605-1-mmkurbanov@salutedevices.com
---
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c | 1 +
drivers/mtd/nand/spi/foresee.c | 95 ++++++++++++++++++++++++++++++++++
include/linux/mtd/spinand.h | 1 +
4 files changed, 98 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/nand/spi/foresee.c
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o
+spinand-objs := core.o esmt.o foresee.o etron.o gigadevice.o macronix.o micron.o paragon.o
spinand-objs += toshiba.o winbond.o xtx.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -834,6 +834,7 @@ static const struct spinand_manufacturer
&toshiba_spinand_manufacturer,
&winbond_spinand_manufacturer,
&esmt_c8_spinand_manufacturer,
+ &foresee_spinand_manufacturer,
&xtx_spinand_manufacturer,
};
--- /dev/null
+++ b/drivers/mtd/nand/spi/foresee.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023, SberDevices. All Rights Reserved.
+ *
+ * Author: Martin Kurbanov <mmkurbanov@salutedevices.com>
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_FORESEE 0xCD
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int f35sqa002g_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ return -ERANGE;
+}
+
+static int f35sqa002g_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ /* Reserve 2 bytes for the BBM. */
+ region->offset = 2;
+ region->length = 62;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops f35sqa002g_ooblayout = {
+ .ecc = f35sqa002g_ooblayout_ecc,
+ .rfree = f35sqa002g_ooblayout_free,
+};
+
+static int f35sqa002g_ecc_get_status(struct spinand_device *spinand, u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ return 1;
+
+ default:
+ break;
+ }
+
+ /* More than 1-bit error was detected in one or more sectors and
+ * cannot be corrected.
+ */
+ return -EBADMSG;
+}
+
+static const struct spinand_info foresee_spinand_table[] = {
+ SPINAND_INFO("F35SQA002G",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x72, 0x72),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&f35sqa002g_ooblayout,
+ f35sqa002g_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer foresee_spinand_manufacturer = {
+ .id = SPINAND_MFR_FORESEE,
+ .name = "FORESEE",
+ .chips = foresee_spinand_table,
+ .nchips = ARRAY_SIZE(foresee_spinand_table),
+ .ops = &foresee_spinand_manuf_ops,
+};
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -252,6 +252,7 @@ extern const struct spinand_manufacturer
extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
extern const struct spinand_manufacturer winbond_spinand_manufacturer;
extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
+extern const struct spinand_manufacturer foresee_spinand_manufacturer;
extern const struct spinand_manufacturer xtx_spinand_manufacturer;
/**

38
package/boot/uboot-mediatek/patches/101-02-mtd-spinand-add-support-for-FORESEE-F35SQA001G.patch Normal file
View File

@ -0,0 +1,38 @@
From ae461cde5c559675fc4c0ba351c7c31ace705f56 Mon Sep 17 00:00:00 2001
From: Bohdan Chubuk <chbgdn@gmail.com>
Date: Sun, 10 Nov 2024 22:50:47 +0200
Subject: [PATCH] mtd: spinand: add support for FORESEE F35SQA001G
Add support for FORESEE F35SQA001G SPI NAND.
Similar to F35SQA002G, but differs in capacity.
Datasheet:
- https://cdn.ozdisan.com/ETicaret_Dosya/704795_871495.pdf
Tested on Xiaomi AX3000T flashed with OpenWRT.
Signed-off-by: Bohdan Chubuk <chbgdn@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/foresee.c | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/drivers/mtd/nand/spi/foresee.c
+++ b/drivers/mtd/nand/spi/foresee.c
@@ -83,6 +83,16 @@ static const struct spinand_info foresee
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&f35sqa002g_ooblayout,
f35sqa002g_ecc_get_status)),
+ SPINAND_INFO("F35SQA001G",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71, 0x71),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&f35sqa002g_ooblayout,
+ f35sqa002g_ecc_get_status)),
};
static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = {

8
package/boot/uboot-mediatek/patches/050-mt7622-enable-pstore.patch → package/boot/uboot-mediatek/patches/103-01-mt7622-enable-pstore.patch
View File

@ -10,20 +10,20 @@
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* 64 KiB reserved for ramoops/pstore */
+ ramoops@42ff0000 {
+ compatible = "ramoops";
+ reg = <0 0x42ff0000 0 0x10000>;
+ reg = <0x42ff0000 0x10000>;
+ record-size = <0x1000>;
+ };
+
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@43000000 {
+ reg = <0 0x43000000 0 0x30000>;
+ reg = <0x43000000 0x30000>;
+ no-map;
+ };
+ };

10
package/boot/uboot-mediatek/patches/052-mt7981-enable-pstore.patch → package/boot/uboot-mediatek/patches/103-02-mt7981-enable-pstore.patch
View File

@ -10,26 +10,26 @@
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* 64 KiB reserved for ramoops/pstore */
+ ramoops@42ff0000 {
+ compatible = "ramoops";
+ reg = <0 0x42ff0000 0 0x10000>;
+ reg = <0x42ff0000 0x10000>;
+ record-size = <0x1000>;
+ };
+
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@43000000 {
+ reg = <0 0x43000000 0 0x30000>;
+ reg = <0x43000000 0x30000>;
+ no-map;
+ };
+
+ wmcpu_emi: wmcpu-reserved@4fc00000 {
+ no-map;
+ reg = <0 0x4fc00000 0 0x00100000>;
+ reg = <0x4fc00000 0x00100000>;
+ };
+ };
+

10
package/boot/uboot-mediatek/patches/051-mt7986-enable-pstore.patch → package/boot/uboot-mediatek/patches/103-03-mt7986-enable-pstore.patch
View File

@ -10,26 +10,26 @@
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* 64 KiB reserved for ramoops/pstore */
+ ramoops@42ff0000 {
+ compatible = "ramoops";
+ reg = <0 0x42ff0000 0 0x10000>;
+ reg = <0x42ff0000 0x10000>;
+ record-size = <0x1000>;
+ };
+
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@43000000 {
+ reg = <0 0x43000000 0 0x30000>;
+ reg = <0x43000000 0x30000>;
+ no-map;
+ };
+
+ wmcpu_emi: wmcpu-reserved@4fc00000 {
+ no-map;
+ reg = <0 0x4fc00000 0 0x00100000>;
+ reg = <0x4fc00000 0x00100000>;
+ };
+ };
+

0
package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch → package/boot/uboot-mediatek/patches/103-04-mt7988-enable-pstore.patch
View File

458
package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch
View File

@ -1,324 +1,268 @@
--- a/configs/mt7988_sd_rfb_defconfig
+++ b/configs/mt7988_sd_rfb_defconfig
@@ -11,6 +11,23 @@ CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x46000000
CONFIG_DEBUG_UART=y
@@ -5,37 +5,76 @@ CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x400000
CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_GPIO_HOG=y
+CONFIG_CMD_ENV_FLAGS=y
CONFIG_TARGET_MT7988=y
CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_ENV_OFFSET_REDUND=0x440000
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_SPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_SD_BOOT=y
+CONFIG_SPI_BOOT=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
CONFIG_SYS_CBSIZE=512
@@ -22,15 +39,118 @@ CONFIG_SYS_PROMPT="MT7988> "
CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
+CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_LOG=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-# CONFIG_CMD_ELF is not set
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_BOOTP=y
+CONFIG_CMD_BUTTON=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_ELF=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ENV_READMEM=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FDT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_STRINGS=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_PWM=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PING=y
+CONFIG_CMD_SF=y
CONFIG_CMD_SMC=y
+CONFIG_CMD_TFTPBOOT=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_UUID=y
+CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
-CONFIG_DOS_PARTITION=y
-CONFIG_EFI_PARTITION=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
+CONFIG_CMD_UBIFS=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_UUID=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DM_MMC=y
+CONFIG_DM_MTD=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_USB=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_PARTITION_UUIDS=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SCSI=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PCI=y
+CONFIG_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
+# CONFIG_MTD_RAW_NAND is not set
+CONFIG_DM_PCI=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPI_NAND=y
+CONFIG_MTK_SPI_NAND_MTD=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_MTK=y
+CONFIG_LZO=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_RANDOM_UUID=y
+CONFIG_REGEX=y
+CONFIG_USB=y
+CONFIG_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_STORAGE=y
CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_OFFSET_REDUND=0x440000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE_REDUND=0x40000
CONFIG_DOS_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
@@ -46,6 +166,9 @@ CONFIG_PROT_TCP=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
+CONFIG_MMC=y
+CONFIG_MMC_DEFAULT_DEV=1
+CONFIG_MMC_SUPPORTS_TUNING=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
@@ -11,7 +11,23 @@ CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x46000000
CONFIG_DEBUG_UART=y
-# CONFIG_AUTOBOOT is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NETCONSOLE=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.1"
CONFIG_USE_NETMASK=y
@@ -44,21 +83,32 @@ CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.2"
CONFIG_PROT_TCP=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
+CONFIG_GPIO_HOG=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_FIT=y
+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_SPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHY_FIXED=y
CONFIG_MEDIATEK_ETH=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_MT7988=y
CONFIG_POWER_DOMAIN=y
CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_PWM=y
CONFIG_PWM_MTK=y
CONFIG_RAM=y
@@ -67,5 +117,8 @@ CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTK_SPIM=y
-CONFIG_LZO=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_ZSTD=y
CONFIG_HEXDUMP=y
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
@@ -6,36 +6,76 @@ CONFIG_TEXT_BASE=0x41e00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_TARGET_MT7988=y
CONFIG_SYS_LOAD_ADDR=0x44000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
# CONFIG_EFI_LOADER is not set
-# CONFIG_AUTOBOOT is not set
+CONFIG_FIT=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_SD_BOOT=y
+CONFIG_SPI_BOOT=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=1049
@@ -22,15 +38,120 @@ CONFIG_SYS_PROMPT="MT7988> "
CONFIG_LOGLEVEL=7
+CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_LOG=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-# CONFIG_CMD_ELF is not set
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_BOOTP=y
+CONFIG_CMD_BUTTON=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_ELF=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ENV_READMEM=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FDT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_STRINGS=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_PWM=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PING=y
+CONFIG_CMD_SF=y
CONFIG_CMD_SMC=y
+CONFIG_CMD_TFTPBOOT=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_UUID=y
+CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
-CONFIG_DOS_PARTITION=y
-CONFIG_EFI_PARTITION=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
+CONFIG_CMD_UBIFS=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_UUID=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DM_MMC=y
+CONFIG_DM_MTD=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_USB=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_PARTITION_UUIDS=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SCSI=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PCI=y
+CONFIG_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
+# CONFIG_MTD_RAW_NAND is not set
+CONFIG_DM_PCI=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPI_NAND=y
+CONFIG_MTK_SPI_NAND_MTD=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_MTK=y
+CONFIG_LZO=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_RANDOM_UUID=y
+CONFIG_REGEX=y
+CONFIG_USB=y
+CONFIG_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_STORAGE=y
CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_UBI_PART="ubi"
+CONFIG_ENV_SIZE=0x1f000
+CONFIG_ENV_SIZE_REDUND=0x1f000
+CONFIG_ENV_UBI_VOLUME="ubootenv"
+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
CONFIG_DOS_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
@@ -46,6 +167,9 @@ CONFIG_PROT_TCP=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NETCONSOLE=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.1"
CONFIG_USE_NETMASK=y
@@ -44,9 +84,13 @@ CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.2"
CONFIG_PROT_TCP=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
+CONFIG_MMC=y
+CONFIG_MMC_DEFAULT_DEV=1
+CONFIG_MMC_SUPPORTS_TUNING=y
+CONFIG_GPIO_HOG=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y
@@ -64,13 +108,20 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHY_FIXED=y
CONFIG_MEDIATEK_ETH=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_MT7988=y
CONFIG_POWER_DOMAIN=y
CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_PWM=y
CONFIG_PWM_MTK=y
CONFIG_RAM=y
@@ -79,5 +130,8 @@ CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTK_SPIM=y
-CONFIG_LZO=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_ZSTD=y
CONFIG_HEXDUMP=y
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -144,6 +144,23 @@
compatible = "spi-nand";
reg = <0>;
@@ -195,6 +195,23 @@
spi-max-frequency = <52000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";

2
package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch
View File

@ -1,6 +1,6 @@
--- a/configs/mt7981_rfb_defconfig
+++ b/configs/mt7981_rfb_defconfig
@@ -30,6 +30,9 @@ CONFIG_CMD_MTD=y
@@ -31,6 +31,9 @@ CONFIG_CMD_MTD=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_PING=y
CONFIG_CMD_SMC=y

22
package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch
View File

@ -1,9 +1,9 @@
--- a/configs/mt7981_emmc_rfb_defconfig
+++ b/configs/mt7981_emmc_rfb_defconfig
@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
@@ -14,7 +14,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x46000000
CONFIG_DEBUG_UART=y
# CONFIG_EFI_LOADER is not set
-# CONFIG_AUTOBOOT is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_PRODUCT_NAME=""
@ -24,7 +24,7 @@
CONFIG_DEFAULT_FDT_FILE="mt7981-emmc-rfb"
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=1049
@@ -24,9 +39,23 @@ CONFIG_SYS_PROMPT="MT7981> "
@@ -25,9 +40,23 @@ CONFIG_SYS_PROMPT="MT7981> "
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
@ -49,7 +49,7 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
@@ -36,13 +65,35 @@ CONFIG_CMD_PART=y
@@ -37,13 +66,35 @@ CONFIG_CMD_PART=y
CONFIG_CMD_READ=y
CONFIG_CMD_PING=y
CONFIG_CMD_SMC=y
@ -87,10 +87,10 @@
CONFIG_CLK=y
--- a/configs/mt7981_rfb_defconfig
+++ b/configs/mt7981_rfb_defconfig
@@ -11,7 +11,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
@@ -12,7 +12,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x46000000
CONFIG_DEBUG_UART=y
# CONFIG_EFI_LOADER is not set
-# CONFIG_AUTOBOOT is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_PRODUCT_NAME=""
@ -111,7 +111,7 @@
CONFIG_DEFAULT_FDT_FILE="mt7981-rfb"
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=1049
@@ -22,23 +37,74 @@ CONFIG_SYS_PROMPT="MT7981> "
@@ -23,23 +38,74 @@ CONFIG_SYS_PROMPT="MT7981> "
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
@ -190,10 +190,10 @@
CONFIG_MTD_SPI_NAND=y
--- a/configs/mt7981_sd_rfb_defconfig
+++ b/configs/mt7981_sd_rfb_defconfig
@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
@@ -14,7 +14,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x46000000
CONFIG_DEBUG_UART=y
# CONFIG_EFI_LOADER is not set
-# CONFIG_AUTOBOOT is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_PRODUCT_NAME=""
@ -214,7 +214,7 @@
CONFIG_DEFAULT_FDT_FILE="mt7981-sd-rfb"
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=1049
@@ -24,9 +39,23 @@ CONFIG_SYS_PROMPT="MT7981> "
@@ -25,9 +40,23 @@ CONFIG_SYS_PROMPT="MT7981> "
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
@ -239,7 +239,7 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
@@ -36,13 +65,35 @@ CONFIG_CMD_PART=y
@@ -37,13 +66,35 @@ CONFIG_CMD_PART=y
CONFIG_CMD_READ=y
CONFIG_CMD_PING=y
CONFIG_CMD_SMC=y

12
package/boot/uboot-mediatek/patches/108-dts-arm64-mt7981-rfb-add-mtd-partitions.patch
View File

@ -1,9 +1,9 @@
--- a/arch/arm/dts/mt7981-rfb.dts
+++ b/arch/arm/dts/mt7981-rfb.dts
@@ -143,6 +143,37 @@
compatible = "spi-nand";
reg = <0>;
@@ -153,6 +153,37 @@
spi-max-frequency = <52000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
@ -38,10 +38,10 @@
};
};
@@ -164,6 +195,37 @@
compatible = "jedec,spi-nor";
reg = <0>;
@@ -176,6 +207,37 @@
spi-max-frequency = <52000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";

2
package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch
View File

@ -1,6 +1,6 @@
--- a/Makefile
+++ b/Makefile
@@ -1085,7 +1085,7 @@ quiet_cmd_pad_cat = CAT $@
@@ -1094,7 +1094,7 @@ quiet_cmd_pad_cat = CAT $@
cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; }
quiet_cmd_lzma = LZMA $@

4
package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
View File

@ -70,7 +70,7 @@
{
--- a/boot/image-fit.c
+++ b/boot/image-fit.c
@@ -2046,6 +2046,47 @@ static const char *fit_get_image_type_pr
@@ -2047,6 +2047,47 @@ static const char *fit_get_image_type_pr
return "unknown";
}
@ -120,7 +120,7 @@
int arch, int ph_type, int bootstage_id,
--- a/include/image.h
+++ b/include/image.h
@@ -1124,6 +1124,7 @@ int fit_parse_subimage(const char *spec,
@@ -1112,6 +1112,7 @@ int fit_parse_subimage(const char *spec,
ulong *addr, const char **image_name);
int fit_get_subimage_count(const void *fit, int images_noffset);

8
package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch
View File

@ -1,6 +1,6 @@
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -465,7 +465,11 @@ static void menu_display_statusline(stru
@@ -463,7 +463,11 @@ static void menu_display_statusline(stru
printf(ANSI_CURSOR_POSITION, 1, 1);
puts(ANSI_CLEAR_LINE);
printf(ANSI_CURSOR_POSITION, 2, 3);
@ -13,7 +13,7 @@
puts(ANSI_CLEAR_LINE_TO_END);
printf(ANSI_CURSOR_POSITION, 3, 1);
puts(ANSI_CLEAR_LINE);
@@ -550,6 +554,7 @@ static enum bootmenu_ret bootmenu_show(i
@@ -548,6 +552,7 @@ static enum bootmenu_ret bootmenu_show(i
return BOOTMENU_RET_FAIL;
}
@ -23,11 +23,11 @@
goto cleanup;
--- a/include/menu.h
+++ b/include/menu.h
@@ -47,6 +47,7 @@ struct bootmenu_data {
@@ -45,6 +45,7 @@ struct bootmenu_data {
int last_active; /* last active menu entry */
int count; /* total count of menu entries */
struct bootmenu_entry *first; /* first menu entry */
+ char *mtitle; /* custom menu title */
bool last_choiced;
};
/** enum bootmenu_key - keys that can be returned by the bootmenu */

4
package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
View File

@ -1,6 +1,6 @@
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -683,6 +683,12 @@ config CMD_ENV_EXISTS
@@ -692,6 +692,12 @@ config CMD_ENV_EXISTS
Check if a variable is defined in the environment for use in
shell scripting.
@ -15,7 +15,7 @@
help
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -273,6 +273,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in
@@ -273,6 +273,60 @@ static int do_env_ask(struct cmd_tbl *cm
}
#endif

2
package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch
View File

@ -16,7 +16,7 @@ Reviewed-by: Tom Rini <trini@konsulko.com>
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -617,6 +617,12 @@ int image_setup_libfdt(struct bootm_head
@@ -612,6 +612,12 @@ int image_setup_libfdt(struct bootm_head
images->fit_uname_cfg,
strlen(images->fit_uname_cfg) + 1, 1);

16
package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch
View File

@ -18,7 +18,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
#include <dt-bindings/clock/mt7981-clk.h>
#include <dt-bindings/reset/mt7629-reset.h>
#include <dt-bindings/pinctrl/mt65xx.h>
@@ -342,4 +343,50 @@
@@ -346,4 +347,50 @@
status = "disabled";
};
@ -31,11 +31,11 @@ Signed-off-by: John Crispin <john@phrozen.org>
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ clocks = <&infracfg_ao CK_INFRA_IUSB_SYS_CK>,
+ <&infracfg_ao CK_INFRA_IUSB_CK>,
+ <&infracfg_ao CK_INFRA_IUSB_133_CK>,
+ <&infracfg_ao CK_INFRA_IUSB_66M_CK>,
+ <&topckgen CK_TOP_U2U3_XHCI_SEL>;
+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
+ <&infracfg CLK_INFRA_IUSB_CK>,
+ <&infracfg CLK_INFRA_IUSB_133_CK>,
+ <&infracfg CLK_INFRA_IUSB_66M_CK>,
+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
+ clock-names = "sys_ck",
+ "ref_ck",
+ "mcu_ck",
@ -54,7 +54,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
+
+ u2port0: usb-phy@11e10000 {
+ reg = <0x11e10000 0x700>;
+ clocks = <&topckgen CK_TOP_USB_FRMCNT_SEL>;
+ clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
@ -62,7 +62,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
+
+ u3port0: usb-phy@11e10700 {
+ reg = <0x11e10700 0x900>;
+ clocks = <&topckgen CK_TOP_USB3_PHY_SEL>;
+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";

19
package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch
View File

@ -17,11 +17,12 @@
#include <mtd.h>
#include <linux/mtd/mtd.h>
@@ -23,7 +30,22 @@ int board_init(void)
@@ -21,6 +28,28 @@ int board_init(void)
return 0;
}
int board_late_init(void)
{
- gd->env_valid = 1; //to load environment variable from persistent store
+int board_late_init(void)
+{
+ struct udevice *dev;
+
+ if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) {
@ -38,9 +39,13 @@
+ }
+ }
+
env_relocate();
return 0;
}
+ env_relocate();
+ return 0;
+ }
+
int board_nmbm_init(void)
{
#ifdef CONFIG_ENABLE_NAND_NMBM
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -155,4 +155,11 @@ config MTK_BROM_HEADER_INFO

18
package/boot/uboot-mediatek/patches/314-mt7981-select-rootdisk.patch
View File

@ -67,10 +67,10 @@
+}
--- a/configs/mt7981_emmc_rfb_defconfig
+++ b/configs/mt7981_emmc_rfb_defconfig
@@ -114,3 +114,4 @@ CONFIG_FAT_WRITE=y
@@ -113,3 +113,4 @@ CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_FAT_WRITE=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
CONFIG_LMB_MAX_REGIONS=64
+CONFIG_OF_SYSTEM_SETUP=y
--- a/configs/mt7981_nor_rfb_defconfig
+++ b/configs/mt7981_nor_rfb_defconfig
@ -81,17 +81,17 @@
+CONFIG_OF_SYSTEM_SETUP=y
--- a/configs/mt7981_rfb_defconfig
+++ b/configs/mt7981_rfb_defconfig
@@ -135,3 +135,4 @@ CONFIG_MTK_SPIM=y
@@ -134,3 +134,4 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTK_SPIM=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
CONFIG_LMB_MAX_REGIONS=64
+CONFIG_OF_SYSTEM_SETUP=y
--- a/configs/mt7981_sd_rfb_defconfig
+++ b/configs/mt7981_sd_rfb_defconfig
@@ -114,3 +114,4 @@ CONFIG_FAT_WRITE=y
@@ -113,3 +113,4 @@ CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_FAT_WRITE=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
CONFIG_LMB_MAX_REGIONS=64
+CONFIG_OF_SYSTEM_SETUP=y
--- a/configs/mt7981_snfi_nand_rfb_defconfig
+++ b/configs/mt7981_snfi_nand_rfb_defconfig

18
package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch
View File

@ -1,6 +1,6 @@
--- a/configs/mt7623n_bpir2_defconfig
+++ b/configs/mt7623n_bpir2_defconfig
@@ -7,52 +7,98 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
@@ -7,34 +7,67 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10
@ -11,13 +11,14 @@
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_TARGET_MT7623=y
+CONFIG_RESET_BUTTON_LABEL="factory"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x84000000
+CONFIG_PCI=y
+CONFIG_AHCI=y
# CONFIG_EFI_GRUB_ARM32_WORKAROUND is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+# CONFIG_BOOTSTD is not set
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_AUTOBOOT_KEYED=y
@ -54,8 +55,8 @@
+CONFIG_CMD_RARP=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_HASH=y
@ -64,15 +65,15 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r2_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r2_env"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.1"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.2"
@@ -42,18 +75,31 @@ CONFIG_SERVERIP="192.168.1.2"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_SCSI_AHCI=y
@ -103,15 +104,14 @@
CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_SYSRESET=y
@@ -60,5 +106,6 @@ CONFIG_SYSRESET_WATCHDOG=y
@@ -61,4 +107,5 @@ CONFIG_SYSRESET_WATCHDOG=y
CONFIG_TIMER=y
CONFIG_MTK_TIMER=y
CONFIG_WDT_MTK=y
+CONFIG_RANDOM_UUID=y
CONFIG_LZMA=y
# CONFIG_EFI_GRUB_ARM32_WORKAROUND is not set
--- /dev/null
+++ b/bananapi_bpi-r2_env
+++ b/defenvs/bananapi_bpi-r2_env
@@ -0,0 +1,69 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254

14
package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch
View File

@ -1,6 +1,6 @@
--- a/configs/mt7623a_unielec_u7623_02_defconfig
+++ b/configs/mt7623a_unielec_u7623_02_defconfig
@@ -7,51 +7,97 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
@@ -7,32 +7,65 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10
@ -11,13 +11,13 @@
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_TARGET_MT7623=y
+CONFIG_RESET_BUTTON_LABEL="factory"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x84000000
+CONFIG_PCI=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+# CONFIG_BOOTSTD is not set
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_AUTOBOOT_KEYED=y
@ -53,8 +53,8 @@
+CONFIG_CMD_RARP=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_HASH=y
@ -63,15 +63,15 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="unielec_u7623-02_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/unielec_u7623-02_env"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.1"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.2"
@@ -40,18 +73,31 @@ CONFIG_SERVERIP="192.168.1.2"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_SCSI_AHCI=y
@ -109,7 +109,7 @@
+CONFIG_RANDOM_UUID=y
CONFIG_LZMA=y
--- /dev/null
+++ b/unielec_u7623-02_env
+++ b/defenvs/unielec_u7623-02_env
@@ -0,0 +1,47 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254

46
package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch
View File

@ -1,6 +1,6 @@
--- /dev/null
+++ b/configs/mt7622_bananapi_bpi-r64-sdmmc_defconfig
@@ -0,0 +1,130 @@
@@ -0,0 +1,128 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
@ -12,11 +12,11 @@
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_ENV_OFFSET_REDUND=0x480000
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
@ -48,14 +48,14 @@
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
@ -74,18 +74,16 @@
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-sdmmc_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r64-sdmmc_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_MTK_AHCI=y
@ -132,7 +130,7 @@
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
--- /dev/null
+++ b/bananapi_bpi-r64-sdmmc_env
+++ b/defenvs/bananapi_bpi-r64-sdmmc_env
@@ -0,0 +1,81 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254
@ -217,7 +215,7 @@
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"
--- /dev/null
+++ b/configs/mt7622_bananapi_bpi-r64-emmc_defconfig
@@ -0,0 +1,119 @@
@@ -0,0 +1,117 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
@ -229,11 +227,11 @@
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_ENV_OFFSET_REDUND=0x480000
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
@ -263,14 +261,14 @@
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
@ -286,18 +284,16 @@
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-emmc_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r64-emmc_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_MTK_AHCI=y
@ -338,7 +334,7 @@
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
--- /dev/null
+++ b/bananapi_bpi-r64-emmc_env
+++ b/defenvs/bananapi_bpi-r64-emmc_env
@@ -0,0 +1,56 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254
@ -408,10 +404,10 @@
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
@ -443,8 +439,8 @@
+CONFIG_CMD_RARP=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
@ -461,16 +457,16 @@
+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-snand_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r64-snand_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.3"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BUTTON=y
@ -508,7 +504,7 @@
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
--- /dev/null
+++ b/bananapi_bpi-r64-snand_env
+++ b/defenvs/bananapi_bpi-r64-snand_env
@@ -0,0 +1,56 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254

6
package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch → package/boot/uboot-mediatek/patches/407-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch
View File

@ -18,10 +18,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb"
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x280000
CONFIG_SYS_LOAD_ADDR=0x4007ff28
CONFIG_DEBUG_UART_BASE=0x11002000
CONFIG_DEBUG_UART_CLOCK=25000000
CONFIG_SYS_LOAD_ADDR=0x4007ff28
@@ -25,6 +27,9 @@ CONFIG_CMD_SF_TEST=y
@@ -26,6 +28,9 @@ CONFIG_CMD_SF_TEST=y
CONFIG_CMD_PING=y
CONFIG_CMD_SMC=y
CONFIG_ENV_OVERWRITE=y
@ -29,5 +29,5 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+CONFIG_ENV_MTD_NAME="spi-nand0"
+CONFIG_ENV_SIZE_REDUND=0x40000
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.1"

18
package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch
View File

@ -1,6 +1,6 @@
--- /dev/null
+++ b/configs/mt7622_linksys_e8450_defconfig
@@ -0,0 +1,112 @@
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
@ -9,10 +9,10 @@
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="mt7622-linksys-e8450-ubi"
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
@ -38,14 +38,14 @@
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
@ -66,7 +66,7 @@
+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="linksys_e8450_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/linksys_e8450_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
@ -75,8 +75,6 @@
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CLK=y
@ -332,7 +330,7 @@
+};
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1187,6 +1187,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -1192,6 +1192,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
mt7622-bananapi-bpi-r64.dtb \
@ -341,7 +339,7 @@
mt7629-rfb.dtb \
mt7981-rfb.dtb \
--- /dev/null
+++ b/linksys_e8450_env
+++ b/defenvs/linksys_e8450_env
@@ -0,0 +1,55 @@
+ethaddr_factory=ubi read 0x40080000 factory && env readmem -b ethaddr 0x400ffff4 0x6 ; setenv ethaddr_factory
+ipaddr=192.168.1.1

46
package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
View File

@ -11,10 +11,10 @@
+CONFIG_ENV_OFFSET=0xc0000
+CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr"
+CONFIG_RESET_BUTTON_SETTLE_DELAY=400
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
@ -40,13 +40,13 @@
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
@ -60,7 +60,7 @@
+CONFIG_ENV_SIZE_REDUND=0x4000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="ubnt_unifi-6-lr_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/ubnt_unifi-6-lr_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
@ -127,10 +127,10 @@
+CONFIG_ENV_OFFSET=0xc0000
+CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr"
+CONFIG_RESET_BUTTON_SETTLE_DELAY=400
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
@ -156,13 +156,13 @@
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
@ -176,7 +176,7 @@
+CONFIG_ENV_SIZE_REDUND=0x4000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="ubnt_unifi-6-lr-v2_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/ubnt_unifi-6-lr-v2_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
@ -243,10 +243,10 @@
+CONFIG_ENV_OFFSET=0xc0000
+CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr-v3"
+CONFIG_RESET_BUTTON_SETTLE_DELAY=400
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_SYS_LOAD_ADDR=0x40080000
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
@ -272,13 +272,13 @@
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
@ -292,7 +292,7 @@
+CONFIG_ENV_SIZE_REDUND=0x4000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="ubnt_unifi-6-lr_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/ubnt_unifi-6-lr_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
@ -739,7 +739,7 @@
+};
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1188,6 +1188,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -1193,6 +1193,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623a-unielec-u7623-02-emmc.dtb \
mt7622-bananapi-bpi-r64.dtb \
mt7622-linksys-e8450-ubi.dtb \
@ -749,7 +749,7 @@
mt7629-rfb.dtb \
mt7981-rfb.dtb \
--- /dev/null
+++ b/ubnt_unifi-6-lr_env
+++ b/defenvs/ubnt_unifi-6-lr_env
@@ -0,0 +1,50 @@
+ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory
+ipaddr=192.168.1.1
@ -802,7 +802,7 @@
+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"
--- /dev/null
+++ b/ubnt_unifi-6-lr-v2_env
+++ b/defenvs/ubnt_unifi-6-lr-v2_env
@@ -0,0 +1,50 @@
+ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory
+ipaddr=192.168.1.1
@ -855,7 +855,7 @@
+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"--- /dev/null
--- /dev/null
+++ b/ubnt_unifi-6-lr-v3_env
+++ b/defenvs/ubnt_unifi-6-lr-v3_env
@@ -0,0 +1,50 @@
+ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory
+ipaddr=192.168.1.1
@ -909,15 +909,15 @@
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -66,6 +66,7 @@
@@ -67,6 +67,7 @@
#include <wdt.h>
#include <asm-generic/gpio.h>
#include <efi_loader.h>
#include <relocate.h>
+#include <spi_flash.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -396,6 +397,20 @@ static int initr_onenand(void)
@@ -405,6 +406,20 @@ static int initr_onenand(void)
}
#endif
@ -938,7 +938,7 @@
#ifdef CONFIG_MMC
static int initr_mmc(void)
{
@@ -680,6 +695,9 @@ static init_fnc_t init_sequence_r[] = {
@@ -711,6 +726,9 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_NMBM_MTD
initr_nmbm,
#endif

2
package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch
View File

@ -161,11 +161,11 @@ Subject: [PATCH] add support for RAVPower RP-WD009
+CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
+CONFIG_MTDPARTS_DEFAULT="spi0.0:192k(factory-uboot),64k(config),64k(factory),1536k(loader),64k(params),64k(user_backup),64k(user),14272k(firmware),64k(mode)"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_LED=y
+CONFIG_LED_BLINK=y

10
package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch
View File

@ -16,10 +16,10 @@
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
+CONFIG_SPL_BSS_START_ADDR=0x80140000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SYS_LOAD_ADDR=0x83000000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xbe000c00
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_SYS_LOAD_ADDR=0x83000000
+CONFIG_ARCH_MTMIPS=y
+CONFIG_SOC_MT7621=y
+CONFIG_SYS_MIPS_TIMER_FREQ=440000000
@ -68,7 +68,7 @@
+CONFIG_ENV_SIZE_REDUND=0x10000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="zbtlink_zbt-wg3526-16m_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/zbtlink_zbt-wg3526-16m_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
@ -99,7 +99,7 @@
+# CONFIG_GZIP is not set
+CONFIG_SPL_LZMA=y
--- /dev/null
+++ b/zbtlink_zbt-wg3526-16m_env
+++ b/defenvs/zbtlink_zbt-wg3526-16m_env
@@ -0,0 +1,36 @@
+ethaddr_factory=mtd read factory $loadaddr 0x0 0x10000 ; setexpr macoffs $loadaddr + 0xe000 ; env readmem -b ethaddr $macoffs 0x6 ; setenv ethaddr_factory
+ipaddr=192.168.1.1
@ -171,7 +171,7 @@
+
+ reset {
+ label = "reset";
+ gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+ };
+ };
+
@ -180,7 +180,7 @@
+
+ led_status: status {
+ label = "green:status";
+ gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
+ };
+ };
+};

19
package/boot/uboot-mediatek/patches/429-add-netcore-n60.patch
View File

@ -1,6 +1,6 @@
--- /dev/null
+++ b/configs/mt7986_netcore_n60_defconfig
@@ -0,0 +1,130 @@
@@ -0,0 +1,127 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
@ -11,10 +11,10 @@
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-netcore-n60"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TARGET_MT7986=y
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
@ -45,14 +45,14 @@
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
@ -75,17 +75,15 @@
+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="netcore_n60_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/netcore_n60_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_MTK_AHCI=y
@ -130,7 +128,6 @@
+CONFIG_USB_STORAGE=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_LMB_MAX_REGIONS=64
--- /dev/null
+++ b/arch/arm/dts/mt7986a-netcore-n60.dts
@@ -0,0 +1,185 @@
@ -320,7 +317,7 @@
+ status = "disabled";
+};
--- /dev/null
+++ b/netcore_n60_env
+++ b/defenvs/netcore_n60_env
@@ -0,0 +1,57 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254

76
package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch
View File

@ -1,6 +1,6 @@
--- /dev/null
+++ b/configs/mt7986a_bpi-r3-emmc_defconfig
@@ -0,0 +1,139 @@
@@ -0,0 +1,136 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
@ -13,11 +13,11 @@
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TARGET_MT7986=y
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_ENV_OFFSET_REDUND=0x440000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
@ -51,14 +51,14 @@
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
@ -78,17 +78,15 @@
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_emmc_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r3_emmc_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_MTK_AHCI=y
@ -139,10 +137,9 @@
+CONFIG_USB_STORAGE=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_LMB_MAX_REGIONS=64
--- /dev/null
+++ b/configs/mt7986a_bpi-r3-nor_defconfig
@@ -0,0 +1,139 @@
@@ -0,0 +1,136 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
@ -155,10 +152,10 @@
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TARGET_MT7986=y
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
@ -192,14 +189,14 @@
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
@ -219,17 +216,15 @@
+CONFIG_ENV_SIZE_REDUND=0x20000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_nor_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r3_nor_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_MTK_AHCI=y
@ -281,10 +276,9 @@
+CONFIG_LZO=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_LMB_MAX_REGIONS=64
--- /dev/null
+++ b/configs/mt7986a_bpi-r3-sd_defconfig
@@ -0,0 +1,139 @@
@@ -0,0 +1,136 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
@ -297,11 +291,11 @@
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-sd"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TARGET_MT7986=y
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_ENV_OFFSET_REDUND=0x440000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
@ -335,14 +329,14 @@
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
@ -362,17 +356,15 @@
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_sdmmc_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r3_sdmmc_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_MTK_AHCI=y
@ -423,10 +415,9 @@
+CONFIG_USB_STORAGE=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_LMB_MAX_REGIONS=64
--- /dev/null
+++ b/configs/mt7986a_bpi-r3-snand_defconfig
@@ -0,0 +1,134 @@
@@ -0,0 +1,131 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
@ -437,10 +428,10 @@
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TARGET_MT7986=y
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
@ -473,14 +464,14 @@
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
@ -503,17 +494,15 @@
+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_snand_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r3_snand_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_MTK_AHCI=y
@ -560,9 +549,8 @@
+CONFIG_USB_STORAGE=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_LMB_MAX_REGIONS=64
--- /dev/null
+++ b/bananapi_bpi-r3_sdmmc_env
+++ b/defenvs/bananapi_bpi-r3_sdmmc_env
@@ -0,0 +1,81 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254
@ -646,7 +634,7 @@
+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"
--- /dev/null
+++ b/bananapi_bpi-r3_nor_env
+++ b/defenvs/bananapi_bpi-r3_nor_env
@@ -0,0 +1,60 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254
@ -709,7 +697,7 @@
+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"
--- /dev/null
+++ b/bananapi_bpi-r3_snand_env
+++ b/defenvs/bananapi_bpi-r3_snand_env
@@ -0,0 +1,73 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254
@ -785,7 +773,7 @@
+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"
--- /dev/null
+++ b/bananapi_bpi-r3_emmc_env
+++ b/defenvs/bananapi_bpi-r3_emmc_env
@@ -0,0 +1,61 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254

17
package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch
View File

@ -1,6 +1,6 @@
--- /dev/null
+++ b/configs/mt7986_xiaomi_redmi-ax6000_defconfig
@@ -0,0 +1,104 @@
@@ -0,0 +1,103 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
@ -11,10 +11,10 @@
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-xiaomi_redmi-ax6000"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TARGET_MT7986=y
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=30
@ -37,14 +37,14 @@
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
@ -63,15 +63,15 @@
+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="xiaomi_redmi-ax6000_env"
+CONFIG_DEFAULT_ENV_FILE="defenvs/xiaomi_redmi-ax6000_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BUTTON=y
@ -104,7 +104,6 @@
+CONFIG_RANDOM_UUID=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_LMB_MAX_REGIONS=64
--- /dev/null
+++ b/arch/arm/dts/mt7986a-xiaomi_redmi-ax6000.dts
@@ -0,0 +1,161 @@
@ -270,7 +269,7 @@
+ status = "disabled";
+};
--- /dev/null
+++ b/xiaomi_redmi-ax6000_env
+++ b/defenvs/xiaomi_redmi-ax6000_env
@@ -0,0 +1,55 @@
+ethaddr_factory=mtd read factory 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x40080004 0x6 ; setenv ethaddr_factory
+ipaddr=192.168.1.1

Some files were not shown because too many files have changed in this diff Show More