Restore the ipq807x series to official DTS

This commit is contained in:
Roc Lai 2025-12-03 07:08:07 +08:00
parent d663c3a6a2
commit 4d6d6b9d43
40 changed files with 3951 additions and 1116 deletions

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@ -1,16 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Dirk Buchwalder <buchwalder@posteo.de> */
/dts-v1/;
#include "ipq8074-512m.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Edimax CAX1800";
@ -18,14 +16,12 @@
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_red;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_red;
/* Aliases as required by u-boot to patch MAC addresses */
ethernet0 = &dp5;
label-mac-device = &dp5;
};
@ -64,150 +60,49 @@
};
};
&blsp1_spi1 {
status = "okay";
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
use-default-sizes;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00050000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x00050000 0x00010000>;
read-only;
};
partition@60000 {
label = "0:bootconfig";
reg = <0x00060000 0x00020000>;
read-only;
};
partition@80000 {
label = "0:bootconfig1";
reg = <0x00080000 0x00020000>;
read-only;
};
partition@a0000 {
label = "0:qsee";
reg = <0x000a0000 0x00180000>;
read-only;
};
partition@220000 {
label = "0:qsee_1";
reg = <0x00220000 0x00180000>;
read-only;
};
partition@3a0000 {
label = "0:devcfg";
reg = <0x003a0000 0x00010000>;
read-only;
};
partition@3b0000 {
label = "0:devcfg_1";
reg = <0x003b0000 0x00010000>;
read-only;
};
partition@3c0000 {
label = "0:apdp";
reg = <0x003c0000 0x00010000>;
read-only;
};
partition@3d0000 {
label = "0:apdp_1";
reg = <0x003d0000 0x00010000>;
read-only;
};
partition@3e0000 {
label = "0:rpm";
reg = <0x003e0000 0x00040000>;
read-only;
};
partition@420000 {
label = "0:rpm_1";
reg = <0x00420000 0x00040000>;
read-only;
};
partition@460000 {
label = "0:cdt";
reg = <0x00460000 0x00010000>;
read-only;
};
partition@470000 {
label = "0:cdt_1";
reg = <0x00470000 0x00010000>;
read-only;
};
partition@480000 {
label = "0:appsblenv";
reg = <0x00480000 0x00010000>;
};
partition@490000 {
label = "0:appsbl";
reg = <0x00490000 0x000a0000>;
read-only;
};
partition@530000 {
label = "0:appsbl_1";
reg = <0x00530000 0x000a0000>;
read-only;
};
partition@5d0000 {
label = "0:art";
reg = <0x005d0000 0x00040000>;
read-only;
};
partition@610000 {
label = "0:ethphyfw";
reg = <0x00610000 0x00080000>;
read-only;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
partitions {
status = "disabled";
};
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -219,7 +114,142 @@
partition@0 {
label = "rootfs";
reg = <0x0 0x0>;
reg = <0x0000000 0x3400000>;
};
};
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-select = <0>;
status = "okay";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
use-default-sizes;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:sbl1";
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:bootconfig";
reg = <0x60000 0x20000>;
read-only;
};
partition@80000 {
label = "0:bootconfig1";
reg = <0x80000 0x20000>;
read-only;
};
partition@a0000 {
label = "0:qsee";
reg = <0xa0000 0x180000>;
read-only;
};
partition@220000 {
label = "0:qsee_1";
reg = <0x220000 0x180000>;
read-only;
};
partition@3a0000 {
label = "0:devcfg";
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "0:devcfg_1";
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3c0000 {
label = "0:apdp";
reg = <0x3c0000 0x10000>;
read-only;
};
partition@3d0000 {
label = "0:apdp_1";
reg = <0x3d0000 0x10000>;
read-only;
};
partition@3e0000 {
label = "0:rpm";
reg = <0x3e0000 0x40000>;
read-only;
};
partition@420000 {
label = "0:rpm_1";
reg = <0x420000 0x40000>;
read-only;
};
partition@460000 {
label = "0:cdt";
reg = <0x460000 0x10000>;
read-only;
};
partition@470000 {
label = "0:cdt_1";
reg = <0x470000 0x10000>;
read-only;
};
partition@480000 {
label = "0:appsblenv";
reg = <0x480000 0x10000>;
};
partition@490000 {
label = "0:appsbl";
reg = <0x490000 0xa0000>;
read-only;
};
partition@530000 {
label = "0:appsbl_1";
reg = <0x530000 0xa0000>;
read-only;
};
partition@5d0000 {
label = "0:art";
reg = <0x5d0000 0x40000>;
read-only;
};
partition@610000 {
label = "0:ethphyfw";
reg = <0x610000 0x80000>;
read-only;
};
};
};
@ -230,12 +260,13 @@
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <0>;
qca8075_4: ethernet-phy@4 {
@ -248,8 +279,8 @@
&switch {
status = "okay";
switch_lan_bmp = <ESS_PORT5>;
switch_mac_mode = <MAC_MODE_PSGMII>;
switch_lan_bmp = <ESS_PORT5>; /* lan port bitmap */
switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
qcom,port_phyinfo {
port@5 {
@ -271,6 +302,7 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Edimax-CAX1800";
qcom,ath11k-fw-memory-mode = <1>;
};

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@ -3,11 +3,9 @@
/dts-v1/;
#include "ipq8074-512m.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -19,16 +17,17 @@
aliases {
serial0 = &blsp1_uart5;
serial1 = &blsp1_uart3;
led-boot = &led_status_red;
led-failsafe = &led_status_red;
led-running = &led_status_blue;
led-upgrade = &led_status_amber;
/*
* Aliases as required by u-boot
* to patch MAC addresses
*/
ethernet0 = &dp4;
ethernet1 = &dp2;
ethernet2 = &dp5;
label-mac-device = &dp4;
};
@ -83,14 +82,53 @@
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart3 {
status = "okay";
};
&blsp1_uart5 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&prng {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -228,12 +266,10 @@
port_id = <2>;
phy_address = <1>;
};
port@4 {
port_id = <4>;
phy_address = <3>;
};
port@5 {
port_id = <5>;
phy_address = <4>;
@ -269,6 +305,7 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "CMCC-RM2-6";
qcom,ath11k-fw-memory-mode = <1>;
};

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@ -2,22 +2,69 @@
/dts-v1/;
#include "ipq8071-edgecore.dtsi"
#include "ipq8074.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Aliyun AP8220";
compatible = "aliyun,ap8220", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led_pw: pw {
label = "pw:status";
led_power: power {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
led_bt: bt {
label = "bt:status";
wlan2g {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN_2GHZ;
gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1radio";
};
wlan5g {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN_5GHZ;
gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0radio";
};
bluetooth {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_BLUETOOTH;
gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
};
};
@ -33,15 +80,42 @@
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
button_pins: button-pins {
mux {
pins = "gpio66";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_spi1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
@ -50,89 +124,126 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00050000>;
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x00050000 0x00010000>;
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:qsee";
reg = <0x00060000 0x00180000>;
reg = <0x60000 0x180000>;
read-only;
};
partition@1e0000 {
label = "0:devcfg";
reg = <0x001e0000 0x00010000>;
reg = <0x1e0000 0x10000>;
read-only;
};
partition@1f0000 {
label = "0:apdp";
reg = <0x001f0000 0x00010000>;
reg = <0x1f0000 0x10000>;
read-only;
};
partition@200000 {
label = "0:rpm";
reg = <0x00200000 0x00040000>;
reg = <0x200000 0x40000>;
read-only;
};
partition@240000 {
label = "0:cdt";
reg = <0x00240000 0x00010000>;
reg = <0x240000 0x10000>;
read-only;
};
partition@250000 {
label = "0:appsblenv";
reg = <0x00250000 0x00010000>;
reg = <0x250000 0x10000>;
};
partition@260000 {
label = "0:appsbl";
reg = <0x00260000 0x000a0000>;
reg = <0x260000 0xa0000>;
read-only;
};
partition@300000 {
label = "0:art";
reg = <0x00300000 0x00040000>;
reg = <0x300000 0x40000>;
read-only;
};
partition@340000 {
label = "0:ethphyfw";
reg = <0x00340000 0x00080000>;
reg = <0x340000 0x80000>;
read-only;
};
partition@3c0000 {
label = "product_info";
reg = <0x003c0000 0x00010000>;
reg = <0x3c0000 0x10000>;
read-only;
};
partition@3d0000 {
label = "mtdoops";
reg = <0x003d0000 0x00020000>;
reg = <0x3d0000 0x20000>;
};
partition@3f0000 {
label = "priv_data1";
reg = <0x003f0000 0x00010000>;
reg = <0x3f0000 0x10000>;
read-only;
};
};
};
};
&blsp1_uart5 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&prng {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&qpic_nand {
status = "okay";
partitions {
status = "disabled";
};
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -143,15 +254,73 @@
#size-cells = <1>;
partition@0 {
label = "rootfs";
reg = <0x0 0x0>;
label = "rootfs1";
reg = <0x0000000 0x3000000>;
};
partition@3000000 {
label = "rootfs2";
reg = <0x3000000 0x3000000>;
};
partition@6000000 {
label = "usrdata";
reg = <0x6000000 0x2000000>;
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
qca8081_24: ethernet-phy@24 {
compatible = "ethernet-phy-id004d.d101";
reg = <24>;
reset-deassert-us = <10000>;
reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
};
qca8081_28: ethernet-phy@28 {
compatible = "ethernet-phy-id004d.d101";
reg = <28>;
reset-deassert-us = <10000>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
};
&switch {
status = "okay";
switch_lan_bmp = <ESS_PORT5>;
switch_wan_bmp = <ESS_PORT6>;
switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>;
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>;
qcom,port_phyinfo {
port@5 {
port_id = <5>;
phy_address = <24>;
port_mac_sel = "QGMAC_PORT";
};
port@6 {
port_id = <6>;
phy_address = <28>;
port_mac_sel = "QGMAC_PORT";
};
};
};
&edma {
status = "okay";
};
&dp5 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&qca8081_24>;
label = "wan";
};
@ -164,6 +333,6 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Aliyun-AP8220";
};

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@ -1,7 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ipq8071-ax3600.dts"
/ {
@ -9,6 +7,7 @@
compatible = "xiaomi,ax3600-stock", "qcom,ipq8074";
aliases {
/* Aliases as required by u-boot to patch MAC addresses */
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;

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@ -1,8 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
/dts-v1/;
#include "ipq8071-xiaomi.dtsi"
#include "ipq8071-ax3600.dtsi"
#include <dt-bindings/leds/common.h>
/ {
model = "Xiaomi AX3600";
@ -39,18 +41,23 @@
};
};
&pcie_qmp0 {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
pcie@0 {
wifi0: wifi@0,0 {
status = "okay";
compatible = "qcom,ath10k";
qcom,ath10k-fw-memory-mode = <1>;
qcom,ath10k-calibration-variant = "Xiaomi-AX3600";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "Xiaomi-AX3600";
nvmem-cell-names = "calibration";
nvmem-cells = <&caldata_qca9889>;
};
@ -58,7 +65,61 @@
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Xiaomi-AX3600";
};
&qca8075_1 {
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
default-state = "keep";
};
};
};
&qca8075_2 {
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};
&qca8075_3 {
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};
&qca8075_4 {
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};

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@ -0,0 +1,312 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
#include "ipq8074-512m.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_yellow;
led-failsafe = &led_system_yellow;
led-running = &led_system_blue;
led-upgrade = &led_system_yellow;
label-mac-device = &dp2;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_0";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
/*
* Bootloader will find the NAND DT node by the compatible and
* then "fixup" it by adding the partitions from the SMEM table
* using the legacy bindings thus making it impossible for us
* to change the partition table or utilize NVMEM for calibration.
* So add a dummy partitions node that bootloader will populate
* and set it as disabled so the kernel ignores it instead of
* printing warnings due to the broken way bootloader adds the
* partitions.
*/
partitions {
status = "disabled";
};
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:sbl1";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "0:mibib";
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "0:qsee";
reg = <0x200000 0x300000>;
read-only;
};
partition@500000 {
label = "0:devcfg";
reg = <0x500000 0x80000>;
read-only;
};
partition@580000 {
label = "0:rpm";
reg = <0x580000 0x80000>;
read-only;
};
partition@600000 {
label = "0:cdt";
reg = <0x600000 0x80000>;
read-only;
};
partition@680000 {
label = "0:appsblenv";
reg = <0x680000 0x80000>;
};
partition@700000 {
label = "0:appsbl";
reg = <0x700000 0x100000>;
read-only;
};
partition@800000 {
label = "0:art";
reg = <0x800000 0x80000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_dp2: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_dp3: macaddr@c {
reg = <0xc 0x6>;
};
macaddr_dp4: macaddr@12 {
reg = <0x12 0x6>;
};
macaddr_dp5: macaddr@18 {
reg = <0x18 0x6>;
};
caldata_qca9889: caldata@4d000 {
reg = <0x33000 0x844>;
};
};
};
partition@880000 {
label = "bdata";
reg = <0x880000 0x80000>;
};
partition@900000 {
/* This is crash + crash_syslog parts combined */
label = "pstore";
reg = <0x900000 0x100000>;
};
/* Make the first rootfs a dedicated ubi partition for kernel */
partition@a00000 {
label = "ubi_kernel";
reg = <0xa00000 0x23c0000>;
};
/* Place the real rootfs in the original second rootfs and
* expand it to the end of the nand
*/
rootfs: partition@2dc0000 {
label = "rootfs";
reg = <0x2dc0000 0xd240000>;
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <0>;
qca8075_1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
qca8075_2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
qca8075_3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
};
qca8075_4: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
};
};
};
&switch {
status = "okay";
switch_lan_bmp = <(ESS_PORT3 | ESS_PORT4 | ESS_PORT5)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT2>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
qcom,port_phyinfo {
port@2 {
port_id = <2>;
phy_address = <1>;
};
port@3 {
port_id = <3>;
phy_address = <2>;
};
port@4 {
port_id = <4>;
phy_address = <3>;
};
port@5 {
port_id = <5>;
phy_address = <4>;
};
};
};
&edma {
status = "okay";
};
&dp2 {
status = "okay";
phy-handle = <&qca8075_1>;
label = "wan";
nvmem-cells = <&macaddr_dp2>;
nvmem-cell-names = "mac-address";
};
&dp3 {
status = "okay";
phy-handle = <&qca8075_2>;
label = "lan1";
nvmem-cells = <&macaddr_dp3>;
nvmem-cell-names = "mac-address";
};
&dp4 {
status = "okay";
phy-handle = <&qca8075_3>;
label = "lan2";
nvmem-cells = <&macaddr_dp4>;
nvmem-cell-names = "mac-address";
};
&dp5 {
status = "okay";
phy-handle = <&qca8075_4>;
label = "lan3";
nvmem-cells = <&macaddr_dp5>;
nvmem-cell-names = "mac-address";
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
};

View File

@ -1,7 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ipq8071-ax6.dts"
/ {
@ -9,6 +7,7 @@
compatible = "redmi,ax6-stock", "qcom,ipq8074";
aliases {
/* Aliases as required by u-boot to patch MAC addresses */
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;

View File

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Zhijun You <hujy652@gmail.com> */
/dts-v1/;
#include "ipq8071-xiaomi.dtsi"
#include "ipq8071-ax3600.dtsi"
/ {
model = "Redmi AX6";
@ -37,11 +38,9 @@
* To be on the safe side, assume 128MiB of NAND.
*/
&rootfs {
reg = <0x02dc0000 0x05220000>;
reg = <0x2dc0000 0x5220000>;
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Redmi-AX6";
};

View File

@ -1,37 +1,114 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2022, Matthew Hagan <mnhagan88@gmail.com> */
/dts-v1/;
#include "ipq8071-edgecore.dtsi"
#include "ipq8074.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Edgecore EAP102";
compatible = "edgecore,eap102", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
serial1 = &blsp1_uart3;
led-boot = &led_system_green;
led-failsafe = &led_system_green;
led-running = &led_system_green;
led-upgrade = &led_system_green;
/* Aliases as required by u-boot to patch MAC addresses */
ethernet0 = &dp6;
ethernet1 = &dp5;
label-mac-device = &dp5;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_poe: poe {
label = "poe:status";
led_wanpoe {
label = "green:wanpoe";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
led_pw: pw {
label = "pw:status";
led_wlan2g {
label = "green:wlan2g";
gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1radio";
};
led_wlan5g {
label = "green:wlan5g";
gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0radio";
};
led_system_green: led_system {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
button_pins: button_pins {
reset_button {
pins = "gpio66";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_spi1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
@ -40,150 +117,179 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00050000>;
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x00050000 0x00010000>;
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:bootconfig";
reg = <0x00060000 0x00020000>;
reg = <0x60000 0x20000>;
read-only;
};
partition@80000 {
label = "0:bootconfig1";
reg = <0x00080000 0x00020000>;
reg = <0x80000 0x20000>;
read-only;
};
partition@a0000 {
label = "0:qsee";
reg = <0x000a0000 0x00180000>;
reg = <0xa0000 0x180000>;
read-only;
};
partition@220000 {
label = "0:qsee_1";
reg = <0x00220000 0x00180000>;
reg = <0x220000 0x180000>;
read-only;
};
partition@3a0000 {
label = "0:devcfg";
reg = <0x003a0000 0x00010000>;
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "0:devcfg_1";
reg = <0x003b0000 0x00010000>;
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3c0000 {
label = "0:apdp";
reg = <0x003c0000 0x00010000>;
reg = <0x3c0000 0x10000>;
read-only;
};
partition@3d0000 {
label = "0:apdp_1";
reg = <0x003d0000 0x00010000>;
reg = <0x3d0000 0x10000>;
read-only;
};
partition@3e0000 {
label = "0:rpm";
reg = <0x003e0000 0x00040000>;
reg = <0x3e0000 0x40000>;
read-only;
};
partition@420000 {
label = "0:rpm_1";
reg = <0x00420000 0x00040000>;
reg = <0x420000 0x40000>;
read-only;
};
partition@460000 {
label = "0:cdt";
reg = <0x00460000 0x00010000>;
reg = <0x460000 0x10000>;
read-only;
};
partition@470000 {
label = "0:cdt_1";
reg = <0x00470000 0x00010000>;
reg = <0x470000 0x10000>;
read-only;
};
partition@480000 {
label = "0:appsblenv";
reg = <0x00480000 0x00010000>;
reg = <0x480000 0x10000>;
};
partition@490000 {
label = "0:appsbl";
reg = <0x00490000 0x000c0000>;
reg = <0x490000 0xc0000>;
read-only;
};
partition@550000 {
label = "0:appsbl_1";
reg = <0x00530000 0x000c0000>;
reg = <0x530000 0xc0000>;
read-only;
};
partition@610000 {
label = "0:art";
reg = <0x00610000 0x00040000>;
reg = <0x610000 0x40000>;
read-only;
};
partition@650000 {
label = "0:ethphyfw";
reg = <0x00650000 0x00080000>;
reg = <0x650000 0x80000>;
read-only;
};
partition@6d0000 {
label = "0:product_info";
reg = <0x006d0000 0x00080000>;
reg = <0x6d0000 0x80000>;
read-only;
};
partition@750000 {
label = "priv_data1";
reg = <0x00750000 0x00010000>;
reg = <0x750000 0x10000>;
read-only;
};
partition@760000 {
label = "priv_data2";
reg = <0x00760000 0x00010000>;
reg = <0x760000 0x10000>;
read-only;
};
};
};
};
&blsp1_uart3 {
status = "okay";
};
&blsp1_uart5 {
status = "okay";
};
&crypto {
status = "okay";
};
&cryptobam {
status = "okay";
};
&prng {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&qpic_nand {
status = "okay";
partitions {
status = "disabled";
};
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -195,31 +301,79 @@
partition@0 {
label = "rootfs1";
reg = <0x00000000 0x03400000>;
reg = <0x0000000 0x3400000>;
};
partition@3400000 {
label = "0:wififw";
reg = <0x03400000 0x00800000>;
reg = <0x3400000 0x800000>;
read-only;
};
partition@3c00000 {
label = "rootfs2";
reg = <0x03c00000 0x03400000>;
reg = <0x3c00000 0x3400000>;
};
partition@7000000 {
label = "0:wififw_1";
reg = <0x07000000 0x00800000>;
reg = <0x7000000 0x800000>;
read-only;
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
qca8081_24: ethernet-phy@24 {
compatible = "ethernet-phy-id004d.d101";
reg = <24>;
reset-deassert-us = <10000>;
reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
};
qca8081_28: ethernet-phy@28 {
compatible = "ethernet-phy-id004d.d101";
reg = <28>;
reset-deassert-us = <10000>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
};
&switch {
status = "okay";
switch_lan_bmp = <ESS_PORT5>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
switch_mac_mode1 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@5 {
port_id = <5>;
phy_address = <24>;
port_mac_sel = "QGMAC_PORT";
};
port@6 {
port_id = <6>;
phy_address = <28>;
port_mac_sel = "QGMAC_PORT";
};
};
};
&edma {
status = "okay";
};
&dp5 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&qca8081_24>;
label = "lan";
};
@ -232,6 +386,6 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Edgecore-EAP102";
};

View File

@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ipq8071-mf269.dts"
/ {

View File

@ -3,11 +3,9 @@
/dts-v1/;
#include "ipq8074-512m.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -18,12 +16,10 @@
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
label-mac-device = &dp6_syn;
};
@ -34,6 +30,8 @@
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wps {
label = "wps";
@ -60,6 +58,15 @@
};
&tlmm {
button_pins: button_pins {
mux {
pins = "gpio37", "gpio46";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
i2c_pins: i2c-pins {
pins = "gpio21", "gpio22";
function = "blsp4_i2c1";
@ -67,24 +74,45 @@
bias-disable;
};
usb_pwr_pins: usb-pwr-pins {
pins = "gpio29";
function = "gpio";
drive-strength = <8>;
bias-disable;
output-high;
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
usb_pwr_pins: usb_pwr_pins {
mux {
pins = "gpio29";
function = "gpio";
drive-strength = <8>;
bias-disable;
output-high;
};
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-select = <0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
@ -93,114 +121,114 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00050000>;
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x00050000 0x00010000>;
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:bootconfig";
reg = <0x00060000 0x00020000>;
reg = <0x60000 0x20000>;
read-only;
};
partition@80000 {
label = "0:bootconfig1";
reg = <0x00080000 0x00020000>;
reg = <0x80000 0x20000>;
read-only;
};
partition@a0000 {
label = "0:qsee";
reg = <0x000a0000 0x00180000>;
reg = <0xa0000 0x180000>;
read-only;
};
partition@220000 {
label = "0:qsee_1";
reg = <0x00220000 0x00180000>;
reg = <0x220000 0x180000>;
read-only;
};
partition@3a0000 {
label = "0:devcfg";
reg = <0x003a0000 0x00010000>;
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "0:devcfg_1";
reg = <0x003b0000 0x00010000>;
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3c0000 {
label = "0:apdp";
reg = <0x003c0000 0x00010000>;
reg = <0x3c0000 0x10000>;
read-only;
};
partition@3d0000 {
label = "0:apdp_1";
reg = <0x003d0000 0x00010000>;
reg = <0x3d0000 0x10000>;
read-only;
};
partition@3e0000 {
label = "0:rpm";
reg = <0x003e0000 0x00040000>;
reg = <0x3e0000 0x40000>;
read-only;
};
partition@420000 {
label = "0:rpm_1";
reg = <0x00420000 0x00040000>;
reg = <0x420000 0x40000>;
read-only;
};
partition@460000 {
label = "0:cdt";
reg = <0x00460000 0x00010000>;
reg = <0x460000 0x10000>;
read-only;
};
partition@470000 {
label = "0:cdt_1";
reg = <0x00470000 0x00010000>;
reg = <0x470000 0x10000>;
read-only;
};
partition@480000 {
label = "0:appsblenv";
reg = <0x00480000 0x00010000>;
reg = <0x480000 0x10000>;
};
partition@490000 {
label = "0:appsbl";
reg = <0x00490000 0x000c0000>;
reg = <0x490000 0xc0000>;
read-only;
};
partition@550000 {
label = "0:appsbl_1";
reg = <0x00550000 0x000c0000>;
reg = <0x550000 0xc0000>;
read-only;
};
partition@610000 {
label = "0:art";
reg = <0x00610000 0x00040000>;
reg = <0x610000 0x40000>;
read-only;
};
partition@650000 {
label = "0:ethphyfw";
reg = <0x00650000 0x00080000>;
reg = <0x650000 0x80000>;
read-only;
};
};
@ -219,18 +247,45 @@
};
};
&blsp1_uart5 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&prng {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
/*
* Bootloader will find the NAND DT node by the compatible and
* then "fixup" it by adding the partitions from the SMEM table
* using the legacy bindings thus making it impossible for us
* to change the partition table or utilize NVMEM for calibration.
* So add a dummy partitions node that bootloader will populate
* and set it as disabled so the kernel ignores it instead of
* printing warnings due to the broken way bootloader adds the
* partitions.
*/
partitions {
status = "disabled";
};
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -242,13 +297,13 @@
partition@0 {
label = "fota-flag";
reg = <0x00000000 0x000a0000>;
reg = <0x0000000 0x00a0000>;
read-only;
};
partition@a0000 {
label = "mac";
reg = <0x000a0000 0x00080000>;
reg = <0x00a0000 0x0080000>;
read-only;
nvmem-layout {
@ -258,55 +313,69 @@
macaddr_mac_0: macaddr@0 {
compatible = "mac-base";
reg = <0x0 0x6>;
#nvmem-cell-cells = <1>;
reg = <0x00 0x06>;
};
};
};
partition@120000 {
label = "cfg-param";
reg = <0x00120000 0x01400000>;
reg = <0x0120000 0x1400000>;
read-only;
};
partition@1520000 {
label = "log";
reg = <0x01520000 0x00600000>;
reg = <0x1520000 0x0600000>;
read-only;
};
partition@1b20000 {
label = "oops";
reg = <0x01b20000 0x000a0000>;
reg = <0x1b20000 0x00a0000>;
read-only;
};
partition@1bc0000 {
label = "web";
reg = <0x01bc0000 0x00800000>;
reg = <0x1bc0000 0x0800000>;
read-only;
};
partition@23c0000 {
label = "ubi_kernel";
reg = <0x023c0000 0x03400000>;
reg = <0x23c0000 0x3400000>;
};
partition@57c0000 {
label = "0:wififw";
reg = <0x057c0000 0x00800000>;
reg = <0x57c0000 0x0800000>;
read-only;
};
/* rootfs partition is the result of squashing
* consecutive stock partitions:
* - openwrt_data (25 MiB)
* - data (30 MiB)
* - fota (99 MiB)
*/
partition@5fc0000 {
label = "rootfs";
reg = <0x05fc0000 0x09a00000>;
reg = <0x5fc0000 0x9a00000>;
};
};
};
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
pinctrl-0 = <&usb_pwr_pins>;
pinctrl-names = "default";
@ -337,10 +406,10 @@
&switch {
status = "okay";
switch_lan_bmp = <ESS_PORT5>;
switch_wan_bmp = <ESS_PORT6>;
switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>;
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>;
switch_lan_bmp = <ESS_PORT5>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@5 {
@ -348,7 +417,6 @@
phy_address = <24>;
port_mac_sel = "QGMAC_PORT";
};
port@6 {
port_id = <6>;
phy_address = <28>;
@ -379,6 +447,7 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "ZTE-MF269";
qcom,ath11k-fw-memory-mode = <1>;
};

View File

@ -1,13 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Dirk Buchwalder <buchwalder@posteo.de> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -18,19 +17,20 @@
aliases {
serial0 = &blsp1_uart5;
/*
* Aliases as required by u-boot
* to patch MAC addresses
*/
led-boot = &led_system_red;
led-failsafe = &led_system_red;
led-running = &led_pwr_green;
led-upgrade = &led_system_red;
ethernet0 = &dp1;
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp5;
ethernet5 = &dp6_syn;
label-mac-device = &dp1;
};
@ -40,6 +40,8 @@
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wps-button {
label = "wps";
@ -56,20 +58,22 @@
leds {
compatible = "gpio-leds";
pinctrl-0 = <&leds_pins>;
pinctrl-names = "default";
led_system_green: system-green {
led_system_green: led-system-green {
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
};
led_system_red: system-red {
led_system_red: led-system-red {
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_STATUS;
};
led_pwr_green: pwr-green {
led_pwr_green: led-pwr-green {
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
@ -167,15 +171,105 @@
};
};
&blsp1_spi1 {
&tlmm {
mdio_pins: mdio-state {
mdc-pins {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio-pins {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
button_pins: button-state {
wps-pins {
pins = "gpio57";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
rst-pins {
pins = "gpio67";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
leds_pins: leds-state {
pins = "gpio1", "gpio3", "gpio4", "gpio6", "gpio7", "gpio8",
"gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio42",
"gpio51", "gpio52", "gpio54", "gpio56";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
@ -184,66 +278,66 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00050000>;
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x00050000 0x00010000>;
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:qsee";
reg = <0x00060000 0x00180000>;
reg = <0x60000 0x180000>;
read-only;
};
partition@1e0000 {
label = "0:devcfg";
reg = <0x001e0000 0x00010000>;
reg = <0x1e0000 0x10000>;
read-only;
};
partition@1f0000 {
label = "0:apdp";
reg = <0x001f0000 0x00010000>;
reg = <0x1f0000 0x10000>;
read-only;
};
partition@200000 {
label = "0:rpm";
reg = <0x00200000 0x00040000>;
reg = <0x200000 0x40000>;
read-only;
};
partition@240000 {
label = "0:cdt";
reg = <0x00240000 0x00010000>;
reg = <0x240000 0x10000>;
read-only;
};
partition@250000 {
label = "0:appsblenv";
reg = <0x00250000 0x00020000>;
reg = <0x250000 0x20000>;
};
partition@270000 {
label = "0:appsbl";
reg = <0x00250000 0x00100000>;
reg = <0x250000 0x100000>;
read-only;
};
partition@370000 {
label = "0:art";
reg = <0x00370000 0x00040000>;
reg = <0x370000 0x40000>;
read-only;
};
partition@3b0000 {
label = "0:ethphyfw1";
reg = <0x003b0000 0x00080000>;
reg = <0x3b0000 0x80000>;
nvmem-layout {
compatible = "fixed-layout";
@ -251,14 +345,14 @@
#size-cells = <1>;
aqr0_fw: firmware@0 {
reg = <0x00000 0x5fc02>;
reg = <0x0 0x5fc02>;
};
};
};
partition@430000 {
label = "0:ethphyfw2";
reg = <0x00430000 0x00080000>;
reg = <0x430000 0x80000>;
nvmem-layout {
compatible = "fixed-layout";
@ -266,14 +360,14 @@
#size-cells = <1>;
aqr1_fw: firmware@0 {
reg = <0x00000 0x5fc02>;
reg = <0x0 0x5fc02>;
};
};
};
partition@4b0000 {
label = "reserved";
reg = <0x004b0000 0x00350000>;
reg = <0x4b0000 0x350000>;
};
};
};
@ -290,7 +384,7 @@
compatible ="ethernet-phy-ieee802.3-c45";
reg = <0>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
firmware-name = "marvell/AQR-G4_v5.4.C-AQR_CIG_WF-1945_0x00000000_ID44778_VER1630.cld";
firmware-name = "marvell/AQR-G4_v5.4.C-AQR_CIG_WF-1945_0x0_ID44778_VER1630.cld";
nvmem-cell-names = "firmware";
nvmem-cells = <&aqr0_fw>;
};
@ -299,15 +393,15 @@
compatible ="ethernet-phy-ieee802.3-c45";
reg = <8>;
reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
firmware-name = "marvell/AQR-G4_v5.4.C-AQR_CIG_WF-1945_0x00000008_ID44776_VER1630.cld";
firmware-name = "marvell/AQR-G4_v5.4.C-AQR_CIG_WF-1945_0x8_ID44776_VER1630.cld";
nvmem-cell-names = "firmware";
nvmem-cells = <&aqr1_fw>;
};
ethernet-phy-package@16 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <16>;
qcom,package-mode = "qsgmii";
@ -337,6 +431,10 @@
&sdhc_1 {
status = "okay";
/* According to the stock dts from the QNAP gpl drop
* the emmc has a problem with the hs400 > hs200 speed switch.
* Therefore remove the mmc-hs400-1_8v property
*/
/delete-property/ mmc-hs400-1_8v;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
@ -346,40 +444,35 @@
&switch {
status = "okay";
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT6)>;
switch_wan_bmp = <ESS_PORT5>;
switch_mac_mode = <MAC_MODE_QSGMII>;
switch_mac_mode1 = <MAC_MODE_USXGMII>;
switch_mac_mode2 = <MAC_MODE_USXGMII>;
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT6)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT5>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <16>;
};
port@1 {
port_id = <2>;
phy_address = <17>;
};
port@2 {
port_id = <3>;
phy_address = <18>;
};
port@3 {
port_id = <4>;
phy_address = <19>;
};
port@4 {
port_id = <5>;
phy_address = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
ethernet-phy-ieee802.3-c45;
};
port@5 {
port_id = <6>;
phy_address = <0>;
@ -438,6 +531,6 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "QNAP-301w";
};

View File

@ -1,13 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2023, Chukun Pan <amadeus@jmu.edu.cn> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -17,19 +16,20 @@
compatible = "arcadyan,aw1000", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
serial0 = &blsp1_uart5;
/*
* Aliases as required by u-boot
* to patch MAC addresses
*/
ethernet0 = &dp1;
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp6_syn;
label-mac-device = &dp1;
};
@ -90,7 +90,7 @@
sck-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
led_gpio: gpio {
led_gpio: led-gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
@ -105,7 +105,8 @@
compatible = "gpio-leds";
led_power: power {
label = "green:power";
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&led_gpio 0 GPIO_ACTIVE_HIGH>;
};
@ -165,14 +166,49 @@
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&prng {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -183,11 +219,32 @@
};
};
&qusb_phy_0 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
vdd-supply = <&usb_vbus>;
};
&ssphy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&mdio {
status = "okay";
@ -229,38 +286,47 @@
reg = <28>;
reset-deassert-us = <10000>;
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@2 {
reg = <2>;
active-low;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
default-state = "keep";
};
};
};
};
&switch {
status = "okay";
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>;
switch_wan_bmp = <ESS_PORT6>;
switch_mac_mode = <MAC_MODE_QSGMII>;
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>;
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@1 {
port_id = <1>;
phy_address = <0>;
};
port@2 {
port_id = <2>;
phy_address = <1>;
};
port@3 {
port_id = <3>;
phy_address = <2>;
};
port@4 {
port_id = <4>;
phy_address = <3>;
};
port@6 {
port_id = <6>;
phy_address = <28>;
@ -309,6 +375,6 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Arcadyan-AW1000";
};

View File

@ -1,33 +1,30 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// SPDX-License-Identifier: MIT, GPL-2.0 or later
/* Copyright (c) 2023, Ruslan Isaev <legale.legale@gmail.com> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Yuncore AX880";
compatible = "yuncore,ax880", "qcom,ipq8074";
compatible = "yuncore,ax880", "qcom,ipq8074", "qcom,ipq8074-hk09";
aliases {
serial0 = &blsp1_uart5;
serial1 = &blsp1_uart3;
led-boot = &led_system;
led-failsafe = &led_system;
led-running = &led_system;
led-upgrade = &led_system;
/* Aliases as required by u-boot to patch MAC addresses */
ethernet0 = &dp5_syn;
ethernet1 = &dp6_syn;
label-mac-device = &dp5_syn;
};
@ -38,6 +35,8 @@
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
@ -68,15 +67,42 @@
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
button_pins: button_pins {
reset_button {
pins = "gpio57";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_spi1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
@ -85,91 +111,91 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00050000>;
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x00050000 0x00010000>;
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:bootconfig";
reg = <0x00060000 0x00020000>;
reg = <0x60000 0x20000>;
read-only;
};
partition@80000 {
label = "0:bootconfig1";
reg = <0x00080000 0x00020000>;
reg = <0x80000 0x20000>;
read-only;
};
partition@a0000 {
label = "0:qsee_1";
reg = <0x000a0000 0x00180000>;
reg = <0xa0000 0x180000>;
read-only;
};
partition@220000 {
label = "0:qsee";
reg = <0x00220000 0x00180000>;
reg = <0x220000 0x180000>;
read-only;
};
partition@3a0000 {
label = "0:devcfg";
reg = <0x003a0000 0x00010000>;
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "0:devcfg_1";
reg = <0x003b0000 0x00010000>;
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3c0000 {
label = "0:apdp";
reg = <0x003c0000 0x00010000>;
reg = <0x3c0000 0x10000>;
read-only;
};
partition@3d0000 {
label = "0:apdp_1";
reg = <0x003d0000 0x00010000>;
reg = <0x3d0000 0x10000>;
read-only;
};
partition@3e0000 {
label = "0:rpm_1";
reg = <0x003e0000 0x00040000>;
reg = <0x3e0000 0x40000>;
read-only;
};
partition@420000 {
label = "0:rpm";
reg = <0x00420000 0x00040000>;
reg = <0x420000 0x40000>;
read-only;
};
partition@460000 {
label = "0:cdt_1";
reg = <0x00460000 0x00010000>;
reg = <0x460000 0x10000>;
read-only;
};
partition@470000 {
label = "0:cdt";
reg = <0x00470000 0x00010000>;
reg = <0x470000 0x10000>;
read-only;
};
partition@480000 {
label = "0:appsblenv";
reg = <0x00480000 0x00010000>;
reg = <0x480000 0x10000>;
nvmem-layout {
compatible = "u-boot,env";
@ -178,25 +204,25 @@
partition@490000 {
label = "0:appsbl_1";
reg = <0x00490000 0x000a0000>;
reg = <0x490000 0xa0000>;
read-only;
};
partition@550000 {
label = "0:appsbl";
reg = <0x00530000 0x000a0000>;
reg = <0x530000 0xa0000>;
read-only;
};
partition@610000 {
label = "0:art";
reg = <0x005d0000 0x00040000>;
reg = <0x5d0000 0x40000>;
read-only;
};
partition@650000 {
label = "0:ethphyfw";
reg = <0x00610000 0x00080000>;
reg = <0x610000 0x80000>;
read-only;
};
@ -204,18 +230,48 @@
};
};
//serial interface
&blsp1_uart3 {
status = "okay";
};
&blsp1_uart5 {
status = "okay";
};
&crypto {
status = "okay";
};
&cryptobam {
status = "okay";
};
&prng {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&qpic_nand {
status = "okay";
partitions {
status = "disabled";
};
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -227,23 +283,23 @@
partition@0 {
label = "rootfs_1";
reg = <0x00000000 0x03400000>;
reg = <0x0000000 0x3400000>;
};
partition@3400000 {
label = "0:wififw";
reg = <0x03400000 0x00800000>;
reg = <0x3400000 0x800000>;
read-only;
};
rootfs: partition@3c00000 {
label = "rootfs";
reg = <0x03c00000 0x03400000>;
reg = <0x3c00000 0x3400000>;
};
partition@7000000 {
label = "0:wififw_1";
reg = <0x07000000 0x00800000>;
reg = <0x7000000 0x800000>;
read-only;
};
};
@ -261,6 +317,18 @@
reg = <24>;
reset-deassert-us = <10000>;
reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
default-state = "keep";
};
};
};
qca8081_28: ethernet-phy@28 {
@ -268,16 +336,28 @@
reg = <28>;
reset-deassert-us = <10000>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};
};
&switch {
status = "okay";
switch_lan_bmp = <ESS_PORT6>;
switch_wan_bmp = <ESS_PORT5>;
switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>;
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>;
switch_lan_bmp = <ESS_PORT6>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT5>; /* wan port bitmap */
switch_mac_mode1 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@5 {
@ -285,7 +365,6 @@
phy_address = <24>;
port_mac_sel = "QGMAC_PORT";
};
port@6 {
port_id = <6>;
phy_address = <28>;
@ -312,6 +391,5 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Yuncore-AX880";
};

View File

@ -1,13 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -18,12 +17,10 @@
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_yellow;
led-failsafe = &led_system_yellow;
led-running = &led_system_blue;
led-upgrade = &led_system_yellow;
label-mac-device = &dp5;
};
@ -42,7 +39,7 @@
};
wps {
label = "wps";
label = "wps"; /* Labeled Mesh on the device */
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
@ -92,6 +89,22 @@
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
i2c_pins: i2c-pins {
pins = "gpio0", "gpio2";
function = "blsp5_i2c";
@ -100,6 +113,10 @@
};
};
&blsp1_uart5 {
status = "okay";
};
&blsp1_i2c6 {
status = "okay";
@ -107,18 +124,41 @@
pinctrl-names = "default";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
/*
* Bootloader will find the NAND DT node by the compatible and
* then "fixup" it by adding the partitions from the SMEM table
* using the legacy bindings thus making it impossible for us
* to change the partition table or utilize NVMEM for calibration.
* So add a dummy partitions node that bootloader will populate
* and set it as disabled so the kernel ignores it instead of
* printing warnings due to the broken way bootloader adds the
* partitions.
*/
partitions {
status = "disabled";
};
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -130,108 +170,108 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00100000>;
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "0:mibib";
reg = <0x00100000 0x00100000>;
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "0:bootconfig";
reg = <0x00200000 0x00080000>;
reg = <0x200000 0x80000>;
read-only;
};
partition@280000 {
label = "0:bootconfig1";
reg = <0x00280000 0x00080000>;
reg = <0x280000 0x80000>;
read-only;
};
partition@300000 {
label = "0:qsee";
reg = <0x00300000 0x00300000>;
reg = <0x300000 0x300000>;
read-only;
};
partition@600000 {
label = "0:qsee_1";
reg = <0x00600000 0x00300000>;
reg = <0x600000 0x300000>;
read-only;
};
partition@900000 {
label = "0:devcfg";
reg = <0x00900000 0x00080000>;
reg = <0x900000 0x80000>;
read-only;
};
partition@980000 {
label = "0:devcfg_1";
reg = <0x00980000 0x00080000>;
reg = <0x980000 0x80000>;
read-only;
};
partition@a00000 {
label = "0:apdp";
reg = <0x00a00000 0x00080000>;
reg = <0xa00000 0x80000>;
read-only;
};
partition@a80000 {
label = "0:apdp_1";
reg = <0x00a80000 0x00080000>;
reg = <0xa80000 0x80000>;
read-only;
};
partition@b00000 {
label = "0:rpm";
reg = <0x00b00000 0x00080000>;
reg = <0xb00000 0x80000>;
read-only;
};
partition@b80000 {
label = "0:rpm_1";
reg = <0x00b80000 0x00080000>;
reg = <0xb80000 0x80000>;
read-only;
};
partition@c00000 {
label = "0:cdt";
reg = <0x00c00000 0x00080000>;
reg = <0xc00000 0x80000>;
read-only;
};
partition@c80000 {
label = "0:cdt_1";
reg = <0x00c80000 0x00080000>;
reg = <0xc80000 0x80000>;
read-only;
};
partition@d00000 {
label = "0:appsblenv";
reg = <0x00d00000 0x00080000>;
reg = <0xd00000 0x80000>;
};
partition@d80000 {
label = "0:appsbl";
reg = <0x00d80000 0x00100000>;
reg = <0xd80000 0x100000>;
read-only;
};
partition@e80000 {
label = "0:appsbl_1";
reg = <0x00e80000 0x00100000>;
reg = <0xe80000 0x100000>;
read-only;
};
partition@f80000 {
label = "0:art";
reg = <0x00f80000 0x00080000>;
reg = <0xf80000 0x80000>;
read-only;
nvmem-layout {
@ -240,54 +280,67 @@
#size-cells = <1>;
macaddr_dp1: macaddr@0 {
reg = <0x00 0x06>;
reg = <0x0 0x6>;
};
macaddr_dp2: macaddr@6 {
reg = <0x06 0x06>;
reg = <0x6 0x6>;
};
macaddr_dp3: macaddr@c {
reg = <0x0c 0x06>;
reg = <0xc 0x6>;
};
macaddr_dp4: macaddr@12 {
reg = <0x12 0x06>;
reg = <0x12 0x6>;
};
macaddr_dp5: macaddr@18 {
reg = <0x18 0x06>;
reg = <0x18 0x6>;
};
caldata_qca9889: caldata@4d000 {
reg = <0x0004d000 0x00000844>;
reg = <0x4d000 0x844>;
};
};
};
partition@1000000 {
label = "bdata";
reg = <0x01000000 0x00080000>;
reg = <0x1000000 0x80000>;
};
partition@1080000 {
/* This is crash + crash_syslog parts combined */
label = "pstore";
reg = <0x01080000 0x00100000>;
reg = <0x1080000 0x100000>;
};
partition@1180000 {
label = "ubi_kernel";
reg = <0x01180000 0x03800000>;
reg = <0x1180000 0x3800000>;
};
partition@4980000 {
label = "rootfs";
reg = <0x04980000 0x0b680000>;
reg = <0x4980000 0xb680000>;
};
};
};
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&mdio {
status = "okay";
@ -296,9 +349,9 @@
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <0>;
qcom,package-mode = "qsgmii";
@ -306,21 +359,69 @@
qca8075_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};
qca8075_1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};
qca8075_2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};
qca8075_3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};
};
@ -329,38 +430,46 @@
reg = <24>;
reset-deassert-us = <10000>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
default-state = "keep";
};
};
};
};
&switch {
status = "okay";
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>;
switch_wan_bmp = <ESS_PORT5>;
switch_mac_mode = <MAC_MODE_QSGMII>;
switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>;
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT5>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance1*/
qcom,port_phyinfo {
port@1 {
port_id = <1>;
phy_address = <0>;
};
port@2 {
port_id = <2>;
phy_address = <1>;
};
port@3 {
port_id = <3>;
phy_address = <2>;
};
port@4 {
port_id = <4>;
phy_address = <3>;
};
port@5 {
port_id = <5>;
phy_address = <24>;
@ -418,33 +527,45 @@
nvmem-cell-names = "mac-address";
};
&pcie_qmp0 {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
pcie@0 {
wifi@0,0 {
status = "okay";
/* ath11k has no DT compatible for PCI cards */
compatible = "pci17cb,1104";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
reg = <0x00010000 0 0 0 0>;
qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
};
};
};
&pcie_qmp1 {
status = "okay";
};
&pcie1 {
status = "okay";
perst-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>;
pcie@0 {
wifi0: wifi@0,0 {
wifi@0,0 {
status = "okay";
compatible = "qcom,ath10k";
qcom,ath10k-fw-memory-mode = <1>;
qcom,ath10k-calibration-variant = "Xiaomi-AX9000";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "Xiaomi-AX9000";
nvmem-cell-names = "calibration";
nvmem-cells = <&caldata_qca9889>;
};
@ -453,6 +574,6 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
};

View File

@ -1,13 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2022, Robert Marko <robimarko@gmail.com> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -17,19 +16,17 @@
compatible = "dynalink,dl-wrx36", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_red;
led-failsafe = &led_system_red;
led-running = &led_system_blue;
led-upgrade = &led_system_red;
serial0 = &blsp1_uart5;
/* Aliases as required by u-boot to patch MAC addresses */
ethernet0 = &dp6_syn;
ethernet1 = &dp4;
ethernet2 = &dp3;
ethernet3 = &dp2;
ethernet4 = &dp1;
label-mac-device = &dp6_syn;
};
@ -69,14 +66,49 @@
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -87,6 +119,18 @@
};
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&mdio {
status = "okay";
@ -95,9 +139,9 @@
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <0>;
qcom,package-mode = "qsgmii";
@ -128,38 +172,54 @@
reg = <28>;
reset-deassert-us = <10000>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_WAN;
default-state = "keep";
active-low;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
default-state = "keep";
};
};
};
};
&switch {
status = "okay";
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>;
switch_wan_bmp = <ESS_PORT6>;
switch_mac_mode = <MAC_MODE_QSGMII>;
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>;
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@1 {
port_id = <1>;
phy_address = <0>;
};
port@2 {
port_id = <2>;
phy_address = <1>;
};
port@3 {
port_id = <3>;
phy_address = <2>;
};
port@4 {
port_id = <4>;
phy_address = <3>;
};
port@6 {
port_id = <6>;
phy_address = <28>;
@ -208,6 +268,5 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Dynalink-DL-WRX36";
};

View File

@ -1,12 +1,73 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
/dts-v1/;
#include "ipq8072-tplink.dtsi"
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "TP-Link EAP620 HD v1";
compatible = "tplink,eap620hd-v1", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_status_blue;
led-failsafe = &led_status_blue;
led-running = &led_status_blue;
led-upgrade = &led_status_blue;
};
chosen {
stdout-path = "serial0,115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_status_blue: status-blue {
function = LED_FUNCTION_STATUS;
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&mdio {
@ -31,7 +92,7 @@
&switch {
status = "okay";
switch_lan_bmp = <ESS_PORT6>;
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>;
switch_mac_mode2 = <MAC_MODE_SGMII_CHANNEL0>;
qcom,port_phyinfo {
port@6 {
@ -41,12 +102,42 @@
};
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "TP-Link-EAP620-HD-v1";
};
&edma {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&wifi {
status = "okay";
qcom,ath11k-calibration-variant = "TP-Link-EAP620-HD-v1";
};

View File

@ -1,17 +1,77 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
/dts-v1/;
#include "ipq8072-tplink.dtsi"
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "TP-Link EAP660 HD v1";
compatible = "tplink,eap660hd-v1", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_status_blue;
led-failsafe = &led_status_blue;
led-running = &led_status_blue;
led-upgrade = &led_status_blue;
};
chosen {
stdout-path = "serial0,115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_status_blue: status-blue {
function = LED_FUNCTION_STATUS;
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
@ -24,6 +84,7 @@
&dp5 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&qca8081_28>;
label = "lan";
};
@ -42,12 +103,30 @@
};
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "TP-Link-EAP660-HD-v1";
};
&edma {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&wifi {
status = "okay";
qcom,ath11k-calibration-variant = "TP-Link-EAP660-HD-v1";
};

View File

@ -3,11 +3,9 @@
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -18,18 +16,16 @@
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_blue;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_blue;
/* Aliases are required by U-Boot to patch MAC addresses */
ethernet0 = &dp6_syn;
ethernet1 = &dp4;
ethernet2 = &dp3;
ethernet3 = &dp2;
label-mac-device = &dp6_syn;
led-boot = &led_system_blue;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_blue;
};
chosen {
@ -38,6 +34,8 @@
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wps-button {
label = "wps";
@ -54,7 +52,39 @@
};
&tlmm {
i2c_3_pins: i2c-3-pins {
mdio_pins: mdio-state {
mdc-pins {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio-pins {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
button_pins: button-state {
wps-pins {
pins = "gpio42";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
rst-pins {
pins = "gpio44";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
i2c_3_pins: i2c-3-state {
pins = "gpio46", "gpio47";
function = "blsp2_i2c";
drive-strength = <8>;
@ -62,15 +92,61 @@
};
};
&blsp1_spi1 {
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
partitions {
compatible = "qcom,smem-part";
@ -86,13 +162,11 @@
reset-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <0>;
qcom,package-mode = "qsgmii";
qca8075_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
@ -130,33 +204,29 @@
&switch {
status = "okay";
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>;
switch_wan_bmp = <ESS_PORT6>;
switch_mac_mode = <MAC_MODE_QSGMII>;
switch_mac_mode1 = <MAC_MODE_10GBASE_R>;
switch_mac_mode2 = <MAC_MODE_USXGMII>;
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <MAC_MODE_10GBASE_R>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@1 {
port_id = <1>;
phy_address = <0>;
};
port@2 {
port_id = <2>;
phy_address = <1>;
};
port@3 {
port_id = <3>;
phy_address = <2>;
};
port@4 {
port_id = <4>;
phy_address = <3>;
};
port@6 {
port_id = <6>;
phy_address = <8>;
@ -203,33 +273,45 @@
label = "wan";
};
&pcie_qmp0 {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
&pcie_qmp1 {
status = "okay";
};
&pcie1 {
status = "okay";
perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
pcie@0 {
wifi@0,0 {
status = "okay";
/* ath11k has no DT compatible for PCI cards */
compatible = "pci17cb,1104";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "prpl-Haze";
reg = <0x00010000 0 0 0 0>;
qcom,ath11k-calibration-variant = "prpl-Haze";
};
};
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "prpl-Haze";
};
&blsp1_i2c3 {
&blsp1_i2c3{
pinctrl-0 = <&i2c_3_pins>;
pinctrl-names = "default";
status = "okay";
@ -241,7 +323,7 @@
#address-cells = <1>;
#size-cells = <0>;
led_system_red: system-red {
led_system_red: chan@0 {
chan-name = "red";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
@ -249,7 +331,7 @@
reg = <0>;
};
led_system_green: system-green {
led_system_green: chan@1 {
chan-name = "green";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
@ -257,7 +339,7 @@
reg = <1>;
};
led_system_blue: system-blue {
led_system_blue: chan@2 {
chan-name = "blue";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;

View File

@ -3,11 +3,9 @@
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -18,26 +16,30 @@
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_blue;
led-running = &led_system_blue;
led-failsafe = &led_system_red;
led-upgrade = &led_system_green;
/*
* Aliases as required by u-boot
* to patch MAC addresses
*/
ethernet0 = &dp1;
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp5;
led-boot = &led_system_blue;
led-running = &led_system_blue;
led-failsafe = &led_system_red;
led-upgrade = &led_system_green;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_0";
bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset-button {
label = "reset";
@ -53,22 +55,112 @@
};
};
&tlmm {
button_pins: button-state {
pins = "gpio54", "gpio67";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
mdio_pins: mdio-state {
mdc-pins {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio-pins {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
/*
* QCA4024 is not currently supported, keep for documentation purposes
*spi_3_pins: spi-3-state {
* spi-pins {
* pins = "gpio50", "gpio52", "gpio53";
* function = "blsp3_spi";
* drive-strength = <8>;
* bias-disable;
* };
*
* cs-pins {
* pins = "gpio22";
* function = "blsp3_spi2";
* drive-strength = <8>;
* bias-disable;
* };
*};
*
*quartz_pins: quartz-state {
* interrupt-pins {
* pins = "gpio48";
* function = "gpio";
* bias-disable;
* input;
* };
*
* reset-pins {
* pins = "gpio21";
* function = "gpio";
* bias-disable;
* output-high;
* };
*};
*/
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
/*
* Bootloader will find the NAND DT node by the compatible and
* then "fixup" it by adding the partitions from the SMEM table
* using the legacy bindings thus making it impossible for us
* to change the partition table or utilize NVMEM for calibration.
* So add a dummy partitions node that bootloader will populate
* and set it as disabled so the kernel ignores it instead of
* printing warnings due to the broken way bootloader adds the
* partitions.
*/
partitions {
status = "disabled";
};
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
#address-cells = <1>;
#size-cells = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
@ -76,108 +168,108 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00100000>;
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "0:mibib";
reg = <0x00100000 0x00100000>;
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "0:bootconfig";
reg = <0x00200000 0x00080000>;
reg = <0x200000 0x80000>;
read-only;
};
partition@280000 {
label = "0:bootconfig1";
reg = <0x00280000 0x00080000>;
reg = <0x280000 0x80000>;
read-only;
};
partition@300000 {
label = "0:qsee";
reg = <0x00300000 0x00300000>;
reg = <0x300000 0x300000>;
read-only;
};
partition@600000 {
label = "0:qsee_1";
reg = <0x00600000 0x00300000>;
reg = <0x600000 0x300000>;
read-only;
};
partition@900000 {
label = "0:devcfg";
reg = <0x00900000 0x00080000>;
reg = <0x900000 0x80000>;
read-only;
};
partition@980000 {
label = "0:devcfg_1";
reg = <0x00980000 0x00080000>;
reg = <0x980000 0x80000>;
read-only;
};
partition@a00000 {
label = "0:apdp";
reg = <0x00a00000 0x00080000>;
reg = <0xa00000 0x80000>;
read-only;
};
partition@a80000 {
label = "0:apdp_1";
reg = <0x00a80000 0x00080000>;
reg = <0xa80000 0x80000>;
read-only;
};
partition@b00000 {
label = "0:rpm";
reg = <0x00b00000 0x00080000>;
reg = <0xb00000 0x80000>;
read-only;
};
partition@b80000 {
label = "0:rpm_1";
reg = <0x00b80000 0x00080000>;
reg = <0xb80000 0x80000>;
read-only;
};
partition@c00000 {
label = "0:cdt";
reg = <0x00c00000 0x00080000>;
reg = <0xc00000 0x80000>;
read-only;
};
partition@c80000 {
label = "0:cdt_1";
reg = <0x00c80000 0x00080000>;
reg = <0xc80000 0x80000>;
read-only;
};
partition@d00000 {
label = "0:appsblenv";
reg = <0x00d00000 0x00080000>;
reg = <0xd00000 0x80000>;
};
partition@d80000 {
label = "0:appsbl";
reg = <0x00d80000 0x00100000>;
reg = <0xd80000 0x100000>;
read-only;
};
partition@e80000 {
label = "0:appsbl_1";
reg = <0x00e80000 0x00100000>;
reg = <0xe80000 0x100000>;
read-only;
};
partition@f80000 {
label = "0:art";
reg = <0x00f80000 0x00080000>;
reg = <0xf80000 0x80000>;
read-only;
nvmem-layout {
@ -186,68 +278,68 @@
#size-cells = <1>;
caldata_qca9984: caldata@33000 {
reg = <0x33000 0x02f20>;
reg = <0x33000 0x2f20>;
};
};
};
partition@1000000 {
label = "u_env";
reg = <0x01000000 0x00040000>;
reg = <0x1000000 0x40000>;
};
partition@1040000 {
label = "s_env";
reg = <0x01040000 0x00020000>;
reg = <0x1040000 0x20000>;
};
partition@1060000 {
label = "devinfo";
reg = <0x01060000 0x00020000>;
reg = <0x1060000 0x20000>;
read-only;
};
partition@1080000 {
label = "kernel";
reg = <0x01080000 0x09600000>;
reg = <0x1080000 0x9600000>;
};
partition@1680000 {
label = "rootfs";
reg = <0x01680000 0x09000000>;
reg = <0x1680000 0x9000000>;
};
partition@a680000 {
label = "alt_kernel";
reg = <0x0a680000 0x09600000>;
reg = <0xa680000 0x9600000>;
};
partition@ac80000 {
label = "alt_rootfs";
reg = <0x0ac80000 0x09000000>;
reg = <0xac80000 0x9000000>;
};
partition@13c80000 {
label = "sysdiag";
reg = <0x13c80000 0x00200000>;
reg = <0x13c80000 0x200000>;
read-only;
};
partition@13e80000 {
label = "0:ethphyfw";
reg = <0x13e80000 0x00080000>;
reg = <0x13e80000 0x80000>;
read-only;
};
partition@13f00000 {
label = "syscfg";
reg = <0x13f00000 0x0b800000>;
reg = <0x13f00000 0xb800000>;
read-only;
};
partition@1f700000 {
label = "0:wififw";
reg = <0x1f700000 0x00900000>;
reg = <0x1f700000 0x900000>;
read-only;
};
};
@ -264,19 +356,19 @@
reg = <0x62>;
nxp,hw-blink;
led_system_red: system-red {
led_system_red: led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_STATUS;
};
led_system_green: system-green {
led_system_green: led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
};
led_system_blue: system-blue {
led_system_blue: led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
@ -289,6 +381,22 @@
};
};
/*
* QCA4024 is not currently supported, keep for documentation purposes
*&blsp1_spi4 {
* status = "okay";
*
* pinctrl-0 = <&spi_3_pins &quartz_pins>;
* pinctrl-names = "default";
*
* iot@3 {
* compatible = "qca,qca4024";
* reg = <0>;
* spi-max-frequency = <24000000>;
* };
*};
*/
&mdio {
status = "okay";
@ -297,9 +405,9 @@
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <0>;
qca8075_0: ethernet-phy@0 {
@ -332,31 +440,27 @@
&switch {
status = "okay";
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>;
switch_wan_bmp = <ESS_PORT5>;
switch_mac_mode = <MAC_MODE_PSGMII>;
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT5>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
qcom,port_phyinfo {
port@1 {
port_id = <1>;
phy_address = <0>;
};
port@2 {
port_id = <2>;
phy_address = <1>;
};
port@3 {
port_id = <3>;
phy_address = <2>;
};
port@4 {
port_id = <4>;
phy_address = <3>;
};
port@5 {
port_id = <5>;
phy_address = <4>;
@ -398,18 +502,35 @@
label = "wan";
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&pcie_qmp1 {
status = "okay";
};
&pcie1 {
status = "okay";
perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
pcie@0 {
wifi@0,0 {
wifi0: wifi@0,0 {
status = "okay";
compatible = "qcom,ath10k";
qcom,ath10k-fw-memory-mode = <1>;
qcom,ath10k-calibration-variant = "Linksys-MX5300";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "Linksys-MX5300";
nvmem-cell-names = "pre-calibration";
nvmem-cells = <&caldata_qca9984>;
};
@ -418,6 +539,6 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Linksys-MX5300";
};

View File

@ -3,11 +3,9 @@
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -19,7 +17,6 @@
aliases {
serial0 = &blsp1_uart5;
serial1 = &blsp1_uart3;
led-boot = &led_system_blue;
led-running = &led_system_blue;
led-failsafe = &led_system_red;
@ -28,10 +25,10 @@
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_0";
bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
};
gpio-export {
gpio_export {
compatible = "gpio-export";
bt_pwr {
@ -43,6 +40,8 @@
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset-button {
label = "reset";
@ -58,22 +57,81 @@
};
};
&tlmm {
button_pins: button-state {
pins = "gpio64", "gpio67";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
mdio_pins: mdio-state {
mdc-pins {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio-pins {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart3 {
status = "okay";
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
/*
* Bootloader will find the NAND DT node by the compatible and
* then "fixup" it by adding the partitions from the SMEM table
* using the legacy bindings thus making it impossible for us
* to change the partition table or utilize NVMEM for calibration.
* So add a dummy partitions node that bootloader will populate
* and set it as disabled so the kernel ignores it instead of
* printing warnings due to the broken way bootloader adds the
* partitions.
*/
partitions {
status = "disabled";
};
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
#address-cells = <1>;
#size-cells = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
@ -81,124 +139,124 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00100000>;
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "0:mibib";
reg = <0x00100000 0x00100000>;
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "0:bootconfig";
reg = <0x00200000 0x00080000>;
reg = <0x200000 0x80000>;
read-only;
};
partition@280000 {
label = "0:bootconfig1";
reg = <0x00280000 0x00080000>;
reg = <0x280000 0x80000>;
read-only;
};
partition@300000 {
label = "0:qsee";
reg = <0x00300000 0x00300000>;
reg = <0x300000 0x300000>;
read-only;
};
partition@600000 {
label = "0:qsee_1";
reg = <0x00600000 0x00300000>;
reg = <0x600000 0x300000>;
read-only;
};
partition@900000 {
label = "0:devcfg";
reg = <0x00900000 0x00080000>;
reg = <0x900000 0x80000>;
read-only;
};
partition@980000 {
label = "0:devcfg_1";
reg = <0x00980000 0x00080000>;
reg = <0x980000 0x80000>;
read-only;
};
partition@a00000 {
label = "0:apdp";
reg = <0x00a00000 0x00080000>;
reg = <0xa00000 0x80000>;
read-only;
};
partition@a80000 {
label = "0:apdp_1";
reg = <0x00a80000 0x00080000>;
reg = <0xa80000 0x80000>;
read-only;
};
partition@b00000 {
label = "0:rpm";
reg = <0x00b00000 0x00080000>;
reg = <0xb00000 0x80000>;
read-only;
};
partition@b80000 {
label = "0:rpm_1";
reg = <0x00b80000 0x00080000>;
reg = <0xb80000 0x80000>;
read-only;
};
partition@c00000 {
label = "0:cdt";
reg = <0x00c00000 0x00080000>;
reg = <0xc00000 0x80000>;
read-only;
};
partition@c80000 {
label = "0:cdt_1";
reg = <0x00c80000 0x00080000>;
reg = <0xc80000 0x80000>;
read-only;
};
partition@d00000 {
label = "0:appsblenv";
reg = <0x00d00000 0x00080000>;
reg = <0xd00000 0x80000>;
};
partition@d80000 {
label = "0:appsbl";
reg = <0x00d80000 0x00100000>;
reg = <0xd80000 0x100000>;
read-only;
};
partition@e80000 {
label = "0:appsbl_1";
reg = <0x00e80000 0x00100000>;
reg = <0xe80000 0x100000>;
read-only;
};
partition@f80000 {
label = "0:art";
reg = <0x00f80000 0x00080000>;
reg = <0xf80000 0x80000>;
read-only;
};
partition@1000000 {
label = "u_env";
reg = <0x01000000 0x00040000>;
reg = <0x1000000 0x40000>;
};
partition@1040000 {
label = "s_env";
reg = <0x01040000 0x00020000>;
reg = <0x1040000 0x20000>;
};
partition@1060000 {
label = "devinfo";
reg = <0x01060000 0x00020000>;
reg = <0x1060000 0x20000>;
read-only;
nvmem-layout {
@ -213,33 +271,33 @@
partition@1080000 {
label = "kernel";
reg = <0x01080000 0x09600000>;
reg = <0x1080000 0x9600000>;
};
partition@1680000 {
label = "rootfs";
reg = <0x01680000 0x09000000>;
reg = <0x1680000 0x9000000>;
};
partition@a680000 {
label = "alt_kernel";
reg = <0x0a680000 0x09600000>;
reg = <0xa680000 0x9600000>;
};
partition@ac80000 {
label = "alt_rootfs";
reg = <0x0ac80000 0x09000000>;
reg = <0xac80000 0x9000000>;
};
partition@13c80000 {
label = "sysdiag";
reg = <0x13c80000 0x00200000>;
reg = <0x13c80000 0x200000>;
read-only;
};
partition@13e80000 {
label = "0:ethphyfw";
reg = <0x13e80000 0x00100000>;
reg = <0x13e80000 0x100000>;
read-only;
nvmem-layout {
@ -249,26 +307,26 @@
aqr_fw: firmware@0 {
/* Skip the QCOM MBN Header of 40 bytes */
reg = <0x00028 0x60002>;
reg = <0x28 0x60002>;
};
};
};
partition@13f80000 {
label = "syscfg";
reg = <0x13f80000 0x0b180000>;
reg = <0x13f80000 0xb180000>;
read-only;
};
partition@1f100000 {
label = "app_data";
reg = <0x1f100000 0x00500000>;
reg = <0x1f100000 0x500000>;
read-only;
};
partition@1f600000 {
label = "0:wififw";
reg = <0x1f600000 0x00a00000>;
reg = <0x1f600000 0xa00000>;
read-only;
};
};
@ -285,19 +343,19 @@
reg = <0x62>;
nxp,hw-blink;
led_system_red: system-red {
led_system_red: led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_STATUS;
};
led_system_green: system-green {
led_system_green: led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
};
led_system_blue: system-blue {
led_system_blue: led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
@ -313,9 +371,9 @@
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <0>;
qcom,package-mode = "qsgmii";
@ -354,10 +412,10 @@
&switch {
status = "okay";
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>;
switch_wan_bmp = <ESS_PORT6>;
switch_mac_mode = <MAC_MODE_QSGMII>;
switch_mac_mode2 = <MAC_MODE_USXGMII>;
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@1 {
@ -438,23 +496,42 @@
nvmem-cell-names = "mac-address";
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&pcie_qmp0 {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
pcie@0 {
wifi@0,0 {
status = "okay";
/* ath11k has no DT compatible for PCI cards */
compatible = "pci17cb,1104";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Linksys-MX8500";
reg = <0x00010000 0 0 0 0>;
qcom,ath11k-calibration-variant = "Linksys-MX8500";
};
};
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Linksys-MX8500";
};

View File

@ -3,11 +3,9 @@
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -17,18 +15,16 @@
compatible = "spectrum,sax1v1k", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_red;
led-failsafe = &led_system_red;
led-running = &led_system_blue;
led-upgrade = &led_system_red;
serial0 = &blsp1_uart5;
/* Aliases as required by u-boot to patch MAC addresses */
ethernet0 = &dp6_syn;
ethernet1 = &dp4;
ethernet2 = &dp3;
ethernet3 = &dp2;
label-mac-device = &dp6_syn;
};
@ -69,17 +65,54 @@
};
};
&mdio {
status = "okay";
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
status = "okay";
ethernet-phy-package@0 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <0>;
qcom,package-mode = "qsgmii";
@ -103,28 +136,51 @@
qca8081: ethernet-phy@28 {
compatible = "ethernet-phy-id004d.d101";
reg = <28>;
reset-deassert-us = <10000>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
reset-deassert-us = <10000>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_WAN;
default-state = "keep";
active-low;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
default-state = "keep";
active-low;
};
};
};
};
&sdhc_1 {
status = "okay";
/* Following same rule as QNAP 301W
* the emmc has a problem with the hs400 > hs200 speed switch.
* Therefore remove the mmc-hs400-1_8v property
*/
/delete-property/ mmc-hs400-1_8v;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
vqmmc-supply = <&l11>;
status = "okay";
};
&switch {
switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance2*/
status = "okay";
switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>;
switch_wan_bmp = <ESS_PORT6>;
switch_mac_mode = <MAC_MODE_QSGMII>;
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>;
qcom,port_phyinfo {
port@2 {
port_id = <2>;
@ -154,34 +210,33 @@
};
&dp2 {
status = "okay";
phy-mode = "qsgmii";
phy-handle = <&qca8075_1>;
label = "lan3";
status = "okay";
};
&dp3 {
status = "okay";
phy-mode = "qsgmii";
phy-handle = <&qca8075_2>;
label = "lan2";
status = "okay";
};
&dp4 {
status = "okay";
phy-mode = "qsgmii";
phy-handle = <&qca8075_3>;
label = "lan1";
status = "okay";
};
&dp6_syn {
status = "okay";
phy-handle = <&qca8081>;
label = "wan";
status = "okay";
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Spectrum-SAX1V1K";
status = "okay";
};

View File

@ -1,16 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Netgear WAX218";
@ -18,7 +15,6 @@
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_power_amber;
led-failsafe = &led_power_amber;
led-running = &led_power_amber;
@ -27,6 +23,10 @@
chosen {
stdout-path = "serial0:115200n8";
/*
* Netgear's U-Boot adds "ubi.mtd=rootfs root=mtd:ubi_rootfs"
* That fails to create a UBI block device, so add it here.
*/
bootargs-append = " ubi.block=0,rootfs root=/dev/ubiblock0_1";
};
@ -48,21 +48,21 @@
sck-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
led_gpio: gpio {
led_gpio: led_gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <2>;
spi-max-frequency = <1000000>;
registers-number = <1>;
enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
spi-max-frequency = <1000000>;
};
};
leds {
compatible = "gpio-leds";
led_power_amber: power-amber {
led_power_amber: led_power {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_AMBER>;
gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
@ -95,7 +95,7 @@
switch_lan_bmp = <ESS_PORT6>;
switch_mac_mode = <MAC_MODE_PSGMII>;
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>;
switch_mac_mode2 = <MAC_MODE_SGMII_CHANNEL0>;
qcom,port_phyinfo {
port@6 {
@ -106,6 +106,24 @@
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&mdio {
status = "okay";
@ -126,14 +144,15 @@
nvmem-cell-names = "mac-address";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -143,22 +162,20 @@
partition-0-appsblenv {
compatible = "fixed-partitions";
label = "0:appsblenv";
read-only;
#address-cells = <1>;
#size-cells = <1>;
label = "0:appsblenv";
read-only;
partition@0 {
label = "env-data";
reg = <0x00000000 0x00040000>;
reg = <0x0 0x40000>;
nvmem-layout {
compatible = "u-boot,env";
#address-cells = <1>;
#size-cells = <1>;
macaddr_ubootenv_ethaddr: ethaddr {};
macaddr_ubootenv_ethaddr: ethaddr {
};
};
};
};
@ -166,8 +183,12 @@
};
};
&blsp1_uart5 {
status = "okay";
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Netgear-WAX218";
};

View File

@ -3,14 +3,11 @@
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Netgear WAX620";
@ -18,19 +15,21 @@
aliases {
serial0 = &blsp1_uart5;
ethernet0 = &dp6;
label-mac-device = &dp6;
led-boot = &led_system_blue;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_blue;
ethernet0 = &dp6;
label-mac-device = &dp6;
};
chosen {
stdout-path = "serial0:115200n8";
/*
* Netgear's U-Boot adds "ubi.mtd=rootfs root=mtd:ubi_rootfs"
* That fails to create a UBI block device, so add it here.
*/
bootargs-append = " root=/dev/ubiblock0_1";
};
@ -52,14 +51,14 @@
sck-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
led_gpio: gpio {
led_gpio: led_gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <2>;
spi-max-frequency = <1000000>;
registers-number = <1>;
enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
spi-max-frequency = <1000000>;
};
};
@ -122,7 +121,7 @@
switch_lan_bmp = <ESS_PORT6>;
switch_mac_mode = <MAC_MODE_PSGMII>;
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>;
switch_mac_mode2 = <MAC_MODE_SGMII_CHANNEL0>;
qcom,port_phyinfo {
port@6 {
@ -133,6 +132,24 @@
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&mdio {
status = "okay";
@ -151,14 +168,15 @@
label = "lan";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -169,8 +187,12 @@
};
};
&blsp1_uart5 {
status = "okay";
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Netgear-WAX620";
};

View File

@ -1,13 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright 2023 Nokia */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -18,17 +17,15 @@
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_power_blue;
led-failsafe = &led_power_red;
led-running = &led_system_green;
led-upgrade = &led_system_blue;
/* Aliases as required by u-boot to patch MAC addresses */
ethernet0 = &dp6;
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
label-mac-device = &dp6;
};
@ -78,6 +75,22 @@
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
i2c_pins: i2c-pins {
pins = "gpio0", "gpio2";
function = "blsp5_i2c";
@ -86,6 +99,10 @@
};
};
&blsp1_uart5 {
status = "okay";
};
&blsp1_i2c6 {
status = "okay";
@ -93,15 +110,62 @@
pinctrl-names = "default";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
button_pins: button_pins {
reset_button {
pins = "gpio66";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_spi1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
@ -110,114 +174,114 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00050000>;
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x00050000 0x00010000>;
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:bootconfig";
reg = <0x00060000 0x00020000>;
reg = <0x60000 0x20000>;
read-only;
};
partition@80000 {
label = "0:bootconfig1";
reg = <0x00080000 0x00020000>;
reg = <0x80000 0x20000>;
read-only;
};
partition@a0000 {
label = "0:qsee";
reg = <0x000a0000 0x00180000>;
reg = <0xa0000 0x180000>;
read-only;
};
partition@220000 {
label = "0:qsee_1";
reg = <0x00220000 0x00180000>;
reg = <0x220000 0x180000>;
read-only;
};
partition@3a0000 {
label = "0:devcfg";
reg = <0x003a0000 0x00010000>;
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "0:devcfg_1";
reg = <0x003b0000 0x00010000>;
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3c0000 {
label = "0:apdp";
reg = <0x003c0000 0x00010000>;
reg = <0x3c0000 0x10000>;
read-only;
};
partition@3d0000 {
label = "0:apdp_1";
reg = <0x003d0000 0x00010000>;
reg = <0x3d0000 0x10000>;
read-only;
};
partition@3e0000 {
label = "0:rpm";
reg = <0x003e0000 0x00040000>;
reg = <0x3e0000 0x40000>;
read-only;
};
partition@420000 {
label = "0:rpm_1";
reg = <0x00420000 0x00040000>;
reg = <0x420000 0x40000>;
read-only;
};
partition@460000 {
label = "0:cdt";
reg = <0x00460000 0x00010000>;
reg = <0x460000 0x10000>;
read-only;
};
partition@470000 {
label = "0:cdt_1";
reg = <0x00470000 0x00010000>;
reg = <0x470000 0x10000>;
read-only;
};
partition@480000 {
label = "0:appsblenv";
reg = <0x00480000 0x00010000>;
reg = <0x480000 0x10000>;
};
partition@490000 {
label = "0:appsbl";
reg = <0x00490000 0x000a0000>;
reg = <0x490000 0xa0000>;
read-only;
};
partition@550000 {
label = "0:appsbl_1";
reg = <0x00530000 0x000a0000>;
reg = <0x530000 0xa0000>;
read-only;
};
partition@610000 {
label = "0:art";
reg = <0x005d0000 0x00040000>;
reg = <0x5d0000 0x40000>;
read-only;
};
partition@650000 {
label = "0:ethphyfw";
reg = <0x00610000 0x00080000>;
reg = <0x610000 0x80000>;
read-only;
};
};
@ -227,15 +291,8 @@
&qpic_nand {
status = "okay";
partitions {
status = "disabled";
};
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -247,40 +304,63 @@
partition@0 {
label = "rootfs";
reg = <0x00000000 0x03400000>;
reg = <0x0000000 0x3400000>;
};
partition@3400000 {
label = "0:wififw";
reg = <0x03400000 0x00800000>;
reg = <0x3400000 0x800000>;
read-only;
};
partition@3c00000 {
label = "rootfs_1";
reg = <0x03c00000 0x03400000>;
reg = <0x3c00000 0x3400000>;
};
partition@7000000 {
label = "0:wififw_1";
reg = <0x07000000 0x00800000>;
reg = <0x7000000 0x800000>;
read-only;
};
};
};
};
&qusb_phy_0 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <0>;
qca8075_1: ethernet-phy@1 {
@ -302,7 +382,6 @@
qca8081: ethernet-phy@28 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <28>;
reset-deassert-us = <10000>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
};
@ -310,28 +389,25 @@
&switch {
status = "okay";
switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>;
switch_wan_bmp = <ESS_PORT6>;
switch_mac_mode = <MAC_MODE_PSGMII>;
switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>;
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>;
switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@2 {
port_id = <2>;
phy_address = <1>;
};
port@3 {
port_id = <3>;
phy_address = <2>;
};
port@4 {
port_id = <4>;
phy_address = <3>;
};
port@6 {
port_id = <6>;
phy_address = <28>;
@ -368,18 +444,28 @@
label = "wan";
};
&pcie_qmp0 {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
&pcie_qmp1 {
status = "okay";
};
&pcie1 {
status = "okay";
perst-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>;
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Compex-WPQ873";
};

View File

@ -3,11 +3,9 @@
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -17,19 +15,19 @@
compatible = "zbtlink,zbt-z800ax", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_net;
led-failsafe = &led_net;
led-running = &led_net;
led-upgrade = &led_net;
serial0 = &blsp1_uart5;
/*
* Aliases as required by u-boot
* to patch MAC addresses
*/
ethernet0 = &dp1;
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp5;
label-mac-device = &dp1;
};
@ -50,6 +48,8 @@
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
@ -88,22 +88,52 @@
wlan5g {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN_5GHZ;
function = LED_FUNCTION_WLAN_5GHZ;
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0radio";
};
};
};
&tlmm {
button_pins: button-pins {
mux {
pins = "gpio34", "gpio46";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-select = <0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
@ -112,118 +142,138 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00050000>;
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x00050000 0x00010000>;
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:bootconfig";
reg = <0x00060000 0x00020000>;
reg = <0x60000 0x20000>;
};
partition@80000 {
label = "0:bootconfig1";
reg = <0x00080000 0x00020000>;
reg = <0x80000 0x20000>;
};
partition@a0000 {
label = "0:qsee";
reg = <0x000a0000 0x00180000>;
reg = <0xa0000 0x180000>;
read-only;
};
partition@220000 {
label = "0:qsee_1";
reg = <0x00220000 0x00180000>;
reg = <0x220000 0x180000>;
read-only;
};
partition@3a0000 {
label = "0:devcfg";
reg = <0x003a0000 0x00010000>;
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "0:devcfg_1";
reg = <0x003b0000 0x00010000>;
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3c0000 {
label = "0:apdp";
reg = <0x003c0000 0x00010000>;
reg = <0x3c0000 0x10000>;
read-only;
};
partition@3d0000 {
label = "0:apdp_1";
reg = <0x003d0000 0x00010000>;
reg = <0x3d0000 0x10000>;
read-only;
};
partition@3e0000 {
label = "0:rpm";
reg = <0x003e0000 0x00040000>;
reg = <0x3e0000 0x40000>;
read-only;
};
partition@420000 {
label = "0:rpm_1";
reg = <0x00420000 0x00040000>;
reg = <0x420000 0x40000>;
read-only;
};
partition@460000 {
label = "0:cdt";
reg = <0x00460000 0x00010000>;
reg = <0x460000 0x10000>;
read-only;
};
partition@470000 {
label = "0:cdt_1";
reg = <0x00470000 0x00010000>;
reg = <0x470000 0x10000>;
read-only;
};
partition@480000 {
label = "0:appsblenv";
reg = <0x00480000 0x00010000>;
reg = <0x480000 0x10000>;
};
partition@490000 {
label = "0:appsbl";
reg = <0x00490000 0x000a0000>;
reg = <0x490000 0xa0000>;
read-only;
};
partition@530000 {
label = "0:appsbl_1";
reg = <0x00530000 0x000a0000>;
reg = <0x530000 0xa0000>;
read-only;
};
partition@5d0000 {
label = "0:art";
reg = <0x005d0000 0x00040000>;
reg = <0x5d0000 0x40000>;
read-only;
};
partition@610000 {
label = "0:ethphyfw";
reg = <0x00610000 0x00080000>;
reg = <0x610000 0x80000>;
read-only;
};
};
};
};
&blsp1_uart5 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&prng {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
@ -232,10 +282,7 @@
};
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -247,29 +294,53 @@
partition@0 {
label = "rootfs";
reg = <0x00000000 0x03400000>;
reg = <0x0000000 0x3400000>;
};
partition@3400000 {
label = "0:wififw";
reg = <0x03400000 0x00800000>;
reg = <0x3400000 0x0800000>;
read-only;
};
partition@3c00000 {
label = "rootfs_1";
reg = <0x03c00000 0x03400000>;
reg = <0x3c00000 0x3400000>;
};
partition@7000000 {
label = "0:wififw_1";
reg = <0x07000000 0x00800000>;
reg = <0x7000000 0x0800000>;
read-only;
};
};
};
};
&qusb_phy_0 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&mdio {
status = "okay";
@ -322,22 +393,18 @@
port_id = <1>;
phy_address = <0>;
};
port@2 {
port_id = <2>;
phy_address = <1>;
};
port@3 {
port_id = <3>;
phy_address = <2>;
};
port@4 {
port_id = <4>;
phy_address = <3>;
};
port@5 {
port_id = <5>;
phy_address = <4>;
@ -381,6 +448,6 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "ZBT-Z800AX";
};

View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// SPDX-License-Identifier: GPL-2.0-only
#include <dt-bindings/thermal/thermal.h>
#include "ipq8074-cpr-regulator.dtsi"

View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// SPDX-License-Identifier: GPL-2.0-only
#include "pmp8074.dtsi"
@ -25,7 +25,7 @@
qcom,cpr-idle-cycles = <15>;
qcom,cpr-step-quot-init-min = <12>;
qcom,cpr-step-quot-init-max = <14>;
qcom,cpr-count-mode = <0>;
qcom,cpr-count-mode = <0>; /* All-at-once */
qcom,cpr-count-repeat = <14>;
qcom,cpr-down-error-step-limit = <1>;
qcom,cpr-up-error-step-limit = <1>;
@ -57,9 +57,15 @@
qcom,allow-voltage-interpolation;
qcom,allow-quotient-interpolation;
qcom,cpr-scaled-open-loop-voltage-as-ceiling;
qcom,cpr-voltage-ceiling = <840000 904000 944000 984000 992000 1064000>;
qcom,cpr-voltage-floor = <592000 648000 712000 744000 784000 848000>;
qcom,corner-frequencies = <1017600000 1382400000 1651200000 1843200000 1920000000 2208000000>;
qcom,cpr-voltage-ceiling =
<840000 904000 944000
984000 992000 1064000>;
qcom,cpr-voltage-floor =
<592000 648000 712000
744000 784000 848000>;
qcom,corner-frequencies =
<1017600000 1382400000 1651200000
1843200000 1920000000 2208000000>;
/* TT/FF parts i.e. turbo L1 OL voltage < 1048 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-0 =
@ -87,7 +93,7 @@
/* v2 - FF parts i.e. turbo L1 OL voltage < 992 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0 =
/* Speed bin 0; CPR rev 0..7 */
/* Speed bin 0; CPR rev 0..7 */
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
@ -186,27 +192,36 @@
qcom,cpr-speed-bin-corners = <2>;
qcom,allow-voltage-interpolation;
qcom,cpr-corner-fmax-map = <1 2>;
qcom,cpr-voltage-ceiling = <912000 992000>;
qcom,cpr-voltage-floor = <752000 792000>;
qcom,corner-frequencies = <1497600000 1689600000>;
qcom,cpr-voltage-ceiling =
<912000 992000>;
qcom,cpr-voltage-floor =
<752000 792000>;
qcom,corner-frequencies =
<1497600000 1689600000>;
/* TT/FF parts i.e. turbo OL voltage < 968 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-0 = <40000 40000>;
qcom,cpr-open-loop-voltage-fuse-adjustment-0 =
< 40000 40000>;
/* SS parts i.e turbo OL voltage >= 968 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-1 = <24000 24000>;
qcom,cpr-open-loop-voltage-fuse-adjustment-1 =
< 24000 24000>;
/* FF parts i.e. turbo OL voltage <= 832 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0= <40000 40000>;
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0=
<40000 40000>;
/* TT/SS parts i.e turbo OL voltage > 832 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-1= <40000 40000>;
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-1=
<40000 40000>;
/* FF parts i.e. turbo OL voltage <= 832 mV */
qcom,cpr-cold-temp-voltage-adjustment-v2-0 = <0 0>;
qcom,cpr-cold-temp-voltage-adjustment-v2-0 =
<0 0>;
/* TT/SS parts i.e turbo OL voltage > 832 mV */
qcom,cpr-cold-temp-voltage-adjustment-v2-1 = <35000 27000>;
qcom,cpr-cold-temp-voltage-adjustment-v2-1 =
<35000 27000>;
};
};
};

View File

@ -1,13 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2022, Robert Marko <robimarko@gmail.com>
altered by Jonathan Brophy <professor_jonny@hotmail.com>
to suit the TP-Link Deco X80-5G target */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -17,8 +18,8 @@
compatible = "tplink,deco-x80-5g", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
};
serial0 = &blsp1_uart5;
};
chosen {
stdout-path = "serial0:115200n8";
@ -50,8 +51,10 @@
};
};
keys {
gpio_keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset_button {
label = "reset";
@ -62,24 +65,26 @@
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
/*note the LED's defined here are not individual they are a single combined RGB element used for status functions.
To mimic the OEM default behaviour green and red are switched on from boot to indicate yellow (power on).*/
led_system_green: system-green {
led_system_green: green {
gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
default-state = "on";
};
led_system_red: system-red {
led_system_red: red {
gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_STATUS;
default-state = "on";
};
led_system_blue: system-blue {
led_system_blue: blue {
gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
@ -290,46 +295,106 @@
&tlmm {
antenna_pins: antenna-pins {
pins = "gpio56";
button_pins: button-state {
pins = "gpio27";
function = "gpio";
drive-strength = <2>;
bias-disable;
bias-pull-up;
};
fan_pins: fan-pins {
fan_pins: fan-state {
pins = "gpio40", "gpio41", "gpio42";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
modem_pins: modem-pins {
antenna_pins: antenna-state {
pins = "gpio56";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
modem_pins: modem-state {
pins = "gpio29", "gpio55";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
led_pins: led-state {
pins = "gpio50", "gpio51", "gpio52";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&prng {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
compatible = "qcom,smem-part"; /* define SMEM partition table */
};
};
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&mdio {
status = "okay";
@ -357,7 +422,7 @@
switch_wan_bmp = <ESS_PORT5>; /* wan port bitmap */
switch_lan_bmp = <ESS_PORT6>; /* lan port bitmap */
switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance2*/
switch_mac_mode2 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@5 {
@ -390,6 +455,5 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "tplink_deco-x80-5g";
};

View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// SPDX-License-Identifier: GPL-2.0-only
#include <dt-bindings/net/qcom-ipq-ess.h>
@ -26,8 +26,8 @@
compatible = "qcom,ess-switch-ipq807x";
reg = <0x3a000000 0x1000000>;
switch_access_mode = "local bus";
switch_cpu_bmp = <ESS_PORT0>;
switch_inner_bmp = <ESS_PORT7>;
switch_cpu_bmp = <ESS_PORT0>; /* cpu port bitmap */
switch_inner_bmp = <ESS_PORT7>; /*inner port bitmap*/
clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
<&gcc GCC_CMN_12GPLL_SYS_CLK>,
<&gcc GCC_UNIPHY0_AHB_CLK>,
@ -146,12 +146,12 @@
"nss_port6_rst";
mdio-bus = <&mdio>;
switch_mac_mode = <MAC_MODE_DISABLED>;
switch_mac_mode1 = <MAC_MODE_DISABLED>;
switch_mac_mode2 = <MAC_MODE_DISABLED>;
switch_mac_mode = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 0 */
switch_mac_mode1 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 1 */
switch_mac_mode2 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 2 */
bm_tick_mode = <0>;
tm_tick_mode = <0>;
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
status = "disabled";
@ -242,7 +242,7 @@
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>;
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};

View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// SPDX-License-Identifier: GPL-2.0-only
#include <dt-bindings/thermal/thermal.h>
#include "ipq8074-cpr-regulator.dtsi"

View File

@ -1,13 +1,15 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2022, Karol Przybylski <itor@o2.pl>
* Copyright (c) 2023, Andre Valentin <avalentin@marcant.net>
*/
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/input.h>
@ -19,9 +21,8 @@
aliases {
serial0 = &blsp1_uart5;
serial1 = &blsp1_uart3;
/* Alias as required by u-boot to patch MAC addresses */
ethernet0 = &dp1;
label-mac-device = &dp1;
};
@ -40,15 +41,60 @@
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart3 {
status = "okay";
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
@ -57,111 +103,108 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00050000>;
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x00050000 0x00010000>;
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:bootconfig";
reg = <0x00060000 0x00020000>;
reg = <0x60000 0x20000>;
read-only;
};
partition@80000 {
label = "0:bootconfig1";
reg = <0x00080000 0x00020000>;
reg = <0x80000 0x20000>;
read-only;
};
partition@a0000 {
label = "0:qsee";
reg = <0x000a0000 0x00180000>;
reg = <0xa0000 0x180000>;
read-only;
};
partition@220000 {
label = "0:qsee_1";
reg = <0x00220000 0x00180000>;
reg = <0x220000 0x180000>;
read-only;
};
partition@3a0000 {
label = "0:devcfg";
reg = <0x003a0000 0x00010000>;
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "0:devcfg_1";
reg = <0x003b0000 0x00010000>;
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3c0000 {
label = "0:apdp";
reg = <0x003c0000 0x00010000>;
reg = <0x3c0000 0x10000>;
read-only;
};
partition@3d0000 {
label = "0:apdp_1";
reg = <0x003d0000 0x00010000>;
reg = <0x3d0000 0x10000>;
read-only;
};
partition@3e0000 {
label = "0:rpm";
reg = <0x003e0000 0x00040000>;
reg = <0x3e0000 0x40000>;
read-only;
};
partition@420000 {
label = "0:rpm_1";
reg = <0x00420000 0x00040000>;
reg = <0x420000 0x40000>;
read-only;
};
partition@460000 {
label = "0:cdt";
reg = <0x00460000 0x00010000>;
reg = <0x460000 0x10000>;
read-only;
};
partition@470000 {
label = "0:cdt_1";
reg = <0x00470000 0x00010000>;
reg = <0x470000 0x10000>;
read-only;
};
partition@480000 {
label = "0:appsbl";
reg = <0x00480000 0x000c0000>;
reg = <0x480000 0xc0000>;
read-only;
};
partition@540000 {
label = "0:appsbl_1";
reg = <0x00540000 0x000c0000>;
reg = <0x540000 0xc0000>;
read-only;
};
partition@600000 {
label = "0:appsblenv";
reg = <0x00600000 0x00010000>;
reg = <0x600000 0x10000>;
nvmem-layout {
compatible = "u-boot,env";
#address-cells = <1>;
#size-cells = <1>;
macaddr_lan: ethaddr {
compatible = "mac-base";
#nvmem-cell-cells = <1>;
};
};
@ -169,13 +212,13 @@
partition@610000 {
label = "0:art";
reg = <0x00610000 0x00040000>;
reg = <0x610000 0x40000>;
read-only;
};
partition@650000 {
label = "0:ethphyfw";
reg = <0x00650000 0x00080000>;
reg = <0x650000 0x80000>;
read-only;
nvmem-layout {
@ -185,25 +228,25 @@
aqr_fw: aqr-fw@0 {
/* Skip the QCOM MBN Header of 40 bytes */
reg = <0x00028 0x5f402>;
reg = <0x28 0x5f402>;
};
};
};
partition@6d0000 {
label = "0:crt";
reg = <0x006d0000 0x00010000>;
reg = <0x6d0000 0x10000>;
read-only;
};
partition@6e0000 {
label = "dual_flag";
reg = <0x006e0000 0x00010000>;
reg = <0x6e0000 0x10000>;
};
partition@6f0000 {
label = "reserved";
reg = <0x006f0000 0x00110000>;
reg = <0x6f0000 0x110000>;
read-only;
};
};
@ -212,19 +255,16 @@
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <0>;
qcom,package-mode = "qsgmii";
qca8075_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
@ -257,6 +297,7 @@
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
reset-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
nvmem-cells = <&aqr_fw>;
nvmem-cell-names = "firmware";
};
@ -267,8 +308,8 @@
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT6)>;
switch_wan_bmp = <ESS_PORT5>;
switch_mac_mode = <MAC_MODE_QSGMII>;
switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>;
switch_mac_mode = <MAC_MODE_PSGMII>;
switch_mac_mode1 = <MAC_MODE_SGMII_CHANNEL0>;
switch_mac_mode2 = <MAC_MODE_USXGMII>;
qcom,port_phyinfo {
@ -361,6 +402,8 @@
};
&blsp1_i2c2 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
tmp103@70 {
@ -371,15 +414,39 @@
&sdhc_1 {
status = "okay";
/* unstable, problem with the hs400 > h200 speed switch */
/delete-property/ mmc-hs400-1_8v;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
vqmmc-supply = <&l11>;
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Zyxel-NBG7815";
};

View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// SPDX-License-Identifier: GPL-2.0-only
/ {
nss_dummy_reg: nss-regulator {
@ -22,55 +22,57 @@
nss0: nss@40000000 {
compatible = "qcom,nss";
interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 384 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 385 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 386 IRQ_TYPE_EDGE_RISING>;
reg = <0x39000000 0x1000>, <0x38000000 0x30000>, <0x0b111000 0x1000>;
<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 384 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 385 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 386 IRQ_TYPE_EDGE_RISING>;
reg = <0x39000000 0x1000>,
<0x38000000 0x30000>,
<0x0b111000 0x1000>;
reg-names = "nphys", "vphys", "qgic-phys";
clocks = <&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_CSR_CLK>,
<&gcc GCC_NSS_CFG_CLK>,
<&gcc GCC_NSS_IMEM_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_NSS_CE_AXI_CLK>,
<&gcc GCC_NSS_CE_APB_CLK>,
<&gcc GCC_NSSNOC_CE_AXI_CLK>,
<&gcc GCC_NSSNOC_CE_APB_CLK>,
<&gcc GCC_NSSNOC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_CORE_CLK>,
<&gcc GCC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_AXI_CLK>,
<&gcc GCC_UBI0_MPT_CLK>,
<&gcc GCC_UBI0_NC_AXI_CLK>;
<&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_CSR_CLK>,
<&gcc GCC_NSS_CFG_CLK>,
<&gcc GCC_NSS_IMEM_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_NSS_CE_AXI_CLK>,
<&gcc GCC_NSS_CE_APB_CLK>,
<&gcc GCC_NSSNOC_CE_AXI_CLK>,
<&gcc GCC_NSSNOC_CE_APB_CLK>,
<&gcc GCC_NSSNOC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_CORE_CLK>,
<&gcc GCC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_AXI_CLK>,
<&gcc GCC_UBI0_MPT_CLK>,
<&gcc GCC_UBI0_NC_AXI_CLK>;
clock-names = "nss-noc-clk",
"nss-ptp-ref-clk",
"nss-csr-clk",
"nss-cfg-clk",
"nss-imem-clk",
"nss-nssnoc-qosgen-ref-clk",
"nss-mem-noc-nss-axi-clk",
"nss-nssnoc-snoc-clk",
"nss-nssnoc-timeout-ref-clk",
"nss-ce-axi-clk",
"nss-ce-apb-clk",
"nss-nssnoc-ce-axi-clk",
"nss-nssnoc-ce-apb-clk",
"nss-nssnoc-ahb-clk",
"nss-core-clk",
"nss-ahb-clk",
"nss-axi-clk",
"nss-mpt-clk",
"nss-nc-axi-clk";
"nss-ptp-ref-clk",
"nss-csr-clk",
"nss-cfg-clk",
"nss-imem-clk",
"nss-nssnoc-qosgen-ref-clk",
"nss-mem-noc-nss-axi-clk",
"nss-nssnoc-snoc-clk",
"nss-nssnoc-timeout-ref-clk",
"nss-ce-axi-clk",
"nss-ce-apb-clk",
"nss-nssnoc-ce-axi-clk",
"nss-nssnoc-ce-apb-clk",
"nss-nssnoc-ahb-clk",
"nss-core-clk",
"nss-ahb-clk",
"nss-axi-clk",
"nss-mpt-clk",
"nss-nc-axi-clk";
qcom,id = <0>;
qcom,num-queue = <4>;
qcom,num-irq = <10>;
@ -111,54 +113,56 @@
nss1: nss@40800000 {
compatible = "qcom,nss";
interrupts = <GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 391 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 392 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 393 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 394 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 395 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 396 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 397 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 398 IRQ_TYPE_EDGE_RISING>;
reg = <0x39400000 0x1000>, <0x38030000 0x30000>, <0x0b111000 0x1000>;
<GIC_SPI 391 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 392 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 393 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 394 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 395 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 396 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 397 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 398 IRQ_TYPE_EDGE_RISING>;
reg = <0x39400000 0x1000>,
<0x38030000 0x30000>,
<0x0b111000 0x1000>;
reg-names = "nphys", "vphys", "qgic-phys";
clocks = <&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_CSR_CLK>,
<&gcc GCC_NSS_CFG_CLK>,
<&gcc GCC_NSS_IMEM_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_NSS_CE_AXI_CLK>,
<&gcc GCC_NSS_CE_APB_CLK>,
<&gcc GCC_NSSNOC_CE_AXI_CLK>,
<&gcc GCC_NSSNOC_CE_APB_CLK>,
<&gcc GCC_NSSNOC_UBI1_AHB_CLK>,
<&gcc GCC_UBI1_CORE_CLK>,
<&gcc GCC_UBI1_AHB_CLK>,
<&gcc GCC_UBI1_AXI_CLK>,
<&gcc GCC_UBI1_MPT_CLK>,
<&gcc GCC_UBI1_NC_AXI_CLK>;
<&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_CSR_CLK>,
<&gcc GCC_NSS_CFG_CLK>,
<&gcc GCC_NSS_IMEM_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_NSS_CE_AXI_CLK>,
<&gcc GCC_NSS_CE_APB_CLK>,
<&gcc GCC_NSSNOC_CE_AXI_CLK>,
<&gcc GCC_NSSNOC_CE_APB_CLK>,
<&gcc GCC_NSSNOC_UBI1_AHB_CLK>,
<&gcc GCC_UBI1_CORE_CLK>,
<&gcc GCC_UBI1_AHB_CLK>,
<&gcc GCC_UBI1_AXI_CLK>,
<&gcc GCC_UBI1_MPT_CLK>,
<&gcc GCC_UBI1_NC_AXI_CLK>;
clock-names = "nss-noc-clk",
"nss-ptp-ref-clk",
"nss-csr-clk",
"nss-cfg-clk",
"nss-imem-clk",
"nss-nssnoc-qosgen-ref-clk",
"nss-mem-noc-nss-axi-clk",
"nss-nssnoc-snoc-clk",
"nss-nssnoc-timeout-ref-clk",
"nss-ce-axi-clk",
"nss-ce-apb-clk",
"nss-nssnoc-ce-axi-clk",
"nss-nssnoc-ce-apb-clk",
"nss-nssnoc-ahb-clk",
"nss-core-clk",
"nss-ahb-clk",
"nss-axi-clk",
"nss-mpt-clk",
"nss-nc-axi-clk";
"nss-ptp-ref-clk",
"nss-csr-clk",
"nss-cfg-clk",
"nss-imem-clk",
"nss-nssnoc-qosgen-ref-clk",
"nss-mem-noc-nss-axi-clk",
"nss-nssnoc-snoc-clk",
"nss-nssnoc-timeout-ref-clk",
"nss-ce-axi-clk",
"nss-ce-apb-clk",
"nss-nssnoc-ce-axi-clk",
"nss-nssnoc-ce-apb-clk",
"nss-nssnoc-ahb-clk",
"nss-core-clk",
"nss-ahb-clk",
"nss-axi-clk",
"nss-mpt-clk",
"nss-nc-axi-clk";
qcom,id = <1>;
qcom,num-queue = <4>;
qcom,num-irq = <9>;
@ -181,15 +185,18 @@
#size-cells = <1>;
qcom,max-contexts = <64>;
qcom,max-context-size = <32>;
status = "okay";
ranges;
eip197_node {
compatible = "qcom,eip197";
reg-names = "crypto_pbase";
reg = <0x39800000 0x7ffff>;
clocks = <&gcc GCC_NSS_CRYPTO_CLK>, <&gcc GCC_NSSNOC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_PPE_CLK>;
clock-names = "crypto_clk", "crypto_nocclk", "crypto_ppeclk";
clocks = <&gcc GCC_NSS_CRYPTO_CLK>,
<&gcc GCC_NSSNOC_CRYPTO_CLK>,
<&gcc GCC_CRYPTO_PPE_CLK>;
clock-names = "crypto_clk",
"crypto_nocclk",
"crypto_ppeclk";
clock-frequency = /bits/ 64 <600000000 600000000 300000000>;
qcom,dma-mask = <0xff>;
qcom,transform-enabled;
@ -206,9 +213,9 @@
qcom,md5-hash;
qcom,sha160-hash;
qcom,sha224-hash;
qcom,sha256-hash;
qcom,sha384-hash;
qcom,sha512-hash;
qcom,sha256-hash;
qcom,md5-hmac;
qcom,sha160-hmac;
qcom,sha224-hmac;

View File

@ -5,11 +5,9 @@
#include "ipq8074.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
@ -19,11 +17,9 @@
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_white;
led-failsafe = &led_system_white;
led-running = &led_system_white;
led-upgrade = &led_system_white;
led-internet = &led_wan_white;
label-mac-device = &dp5;
};
@ -62,14 +58,14 @@
sck-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
led_gpio: gpio {
led_gpio: led_gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <2>;
spi-max-frequency = <1000000>;
enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
spi-max-frequency = <1000000>;
};
};
@ -130,6 +126,24 @@
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&mdio {
status = "okay";
@ -138,12 +152,11 @@
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
qcom,package-mode = "qsgmii";
compatible = "qcom,qca8075-package";
qca8075_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
@ -181,37 +194,32 @@
&switch {
status = "okay";
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT6)>;
switch_wan_bmp = <ESS_PORT5>;
switch_mac_mode = <MAC_MODE_QSGMII>;
switch_mac_mode2 = <MAC_MODE_USXGMII>;
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT6)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT5>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@1 {
port_id = <1>;
phy_address = <0>;
};
port@2 {
port_id = <2>;
phy_address = <1>;
};
port@3 {
port_id = <3>;
phy_address = <2>;
};
port@4 {
port_id = <4>;
phy_address = <3>;
};
port@5 {
port_id = <5>;
phy_address = <4>;
};
port@6 {
port_id = <6>;
phy_address = <7>;
@ -274,6 +282,10 @@
nvmem-cell-names = "mac-address";
};
&blsp1_uart5 {
status = "okay";
};
&blsp1_i2c2 {
status = "okay";
@ -286,18 +298,15 @@
};
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
partitions {
status = "disabled";
};
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -309,126 +318,126 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00100000>;
reg = <0x00 0x100000>;
read-only;
};
partition@100000 {
label = "0:mibib";
reg = <0x00100000 0x00100000>;
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "0:bootconfig";
reg = <0x00200000 0x00080000>;
reg = <0x200000 0x80000>;
read-only;
};
partition@280000 {
label = "0:bootconfig_1";
reg = <0x00280000 0x00080000>;
reg = <0x280000 0x80000>;
read-only;
};
partition@300000 {
label = "0:qsee";
reg = <0x00300000 0x00300000>;
reg = <0x300000 0x300000>;
read-only;
};
partition@600000 {
label = "0:qsee_1";
reg = <0x00600000 0x00300000>;
reg = <0x600000 0x300000>;
read-only;
};
partition@900000 {
label = "0:devcfg";
reg = <0x00900000 0x00080000>;
reg = <0x900000 0x80000>;
read-only;
};
partition@980000 {
label = "0:devcfg_1";
reg = <0x00980000 0x00080000>;
reg = <0x980000 0x80000>;
read-only;
};
partition@a00000 {
label = "0:apdp";
reg = <0x00a00000 0x00080000>;
reg = <0xa00000 0x80000>;
read-only;
};
partition@a80000 {
label = "0:apdp_1";
reg = <0x00a80000 0x00080000>;
reg = <0xa80000 0x80000>;
read-only;
};
partition@b00000 {
label = "0:rpm";
reg = <0x00b00000 0x00080000>;
reg = <0xb00000 0x80000>;
read-only;
};
partition@b80000 {
label = "0:rpm_1";
reg = <0x00b80000 0x00080000>;
reg = <0xb80000 0x80000>;
read-only;
};
partition@c00000 {
label = "0:cdt";
reg = <0x00c00000 0x00080000>;
reg = <0xc00000 0x80000>;
read-only;
};
partition@c80000 {
label = "0:cdt_1";
reg = <0x00c80000 0x00080000>;
reg = <0xc80000 0x80000>;
read-only;
};
partition@d00000 {
label = "0:appsblenv";
reg = <0x00d00000 0x00080000>;
reg = <0xd00000 0x80000>;
};
partition@d80000 {
label = "0:appsbl";
reg = <0x00d80000 0x00100000>;
reg = <0xd80000 0x100000>;
read-only;
};
partition@e80000 {
label = "0:appsbl_1";
reg = <0x00e80000 0x00100000>;
reg = <0xe80000 0x100000>;
read-only;
};
partition@f80000 {
label = "0:art";
reg = <0x00f80000 0x00080000>;
reg = <0xf80000 0x80000>;
read-only;
};
partition@1000000 {
label = "0:art.bak";
reg = <0x01000000 0x00080000>;
reg = <0x1000000 0x0080000>;
read-only;
};
partition@1080000 {
label = "config";
reg = <0x01080000 0x00100000>;
reg = <0x1080000 0x0100000>;
read-only;
};
partition@1180000 {
label = "boarddata1";
reg = <0x01180000 0x00100000>;
reg = <0x1180000 0x0100000>;
read-only;
nvmem-layout {
@ -437,57 +446,93 @@
#size-cells = <1>;
macaddr_lan: macaddr@0 {
reg = <0x00 0x06>;
reg = <0x0 0x6>;
};
macaddr_wan: macaddr@1 {
reg = <0x06 0x06>;
reg = <0x6 0x6>;
};
macaddr_wlan5g: macaddr@2 {
reg = <0x0c 0x06>;
reg = <0xc 0x6>;
};
};
};
partition@1280000 {
label = "boarddata2";
reg = <0x01280000 0x00100000>;
reg = <0x1280000 0x0100000>;
read-only;
};
partition@1380000 {
label = "pot";
reg = <0x01380000 0x00100000>;
reg = <0x1380000 0x0100000>;
read-only;
};
partition@1480000 {
label = "dnidata";
reg = <0x01480000 0x00500000>;
reg = <0x1480000 0x0500000>;
read-only;
};
partition@1980000 {
label = "kernel";
reg = <0x01980000 0x01d00000>;
reg = <0x1980000 0x1d00000>;
};
partition@7e00000 {
label = "ethphyfw";
reg = <0x07e00000 0x00080000>;
reg = <0x7e00000 0x80000>;
};
partition@e8800000 {
label = "rootfs";
reg = <0x0e880000 0x11780000>;
reg = <0xe880000 0x11780000>;
};
};
};
};
&wifi {
&qusb_phy_0 {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
};
&qusb_phy_1 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&wifi{
status = "okay";
qcom,ath11k-calibration-variant = "Netgear-RAX120v2";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&prng {
status = "okay";
};

View File

@ -1,13 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2024, Robert Marko <robimarko@gmail.com> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -17,22 +16,18 @@
compatible = "asus,rt-ax89x", "qcom,ipq8074";
aliases {
mdio-gpio0 = &mdio1;
serial0 = &blsp1_uart5;
led-boot = &led_pwr;
led-failsafe = &led_pwr;
led-running = &led_pwr;
led-upgrade = &led_pwr;
mdio-gpio0 = &mdio1;
ethernet0 = &dp1;
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp5_syn;
ethernet5 = &dp6_syn;
led-boot = &led_pwr;
led-failsafe = &led_pwr;
led-running = &led_pwr;
led-upgrade = &led_pwr;
};
chosen {
@ -43,6 +38,8 @@
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wifi-button {
label = "wifi";
@ -71,8 +68,10 @@
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_pwr: pwr {
led_pwr: led-pwr {
function = LED_FUNCTION_POWER;
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_WHITE>;
@ -127,7 +126,8 @@
compatible = "gpio-fan";
pinctrl-0 = <&fan_pins>;
pinctrl-names = "default";
gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>, <&tlmm 66 GPIO_ACTIVE_HIGH>;
gpios = <&tlmm 64 GPIO_ACTIVE_HIGH
&tlmm 66 GPIO_ACTIVE_HIGH>;
/*
* Not supported upstream, but good to document for
* future uses.
@ -249,12 +249,34 @@
};
&tlmm {
fan_pins: fan-pins {
pins = "gpio64", "gpio66";
button_pins: button-state {
pins = "gpio25", "gpio26", "gpio34", "gpio61";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
i2c_pins: i2c-pins {
pins = "gpio42", "gpio43";
function = "blsp1_i2c";
drive-strength = <8>;
bias-disable;
output-high;
};
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <16>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <16>;
bias-pull-up;
};
};
mdio_gpio_pins: mdio-gpio-pins {
@ -264,11 +286,10 @@
bias-pull-up;
};
uniphy_pins: uniphy-pins {
uniphy_pins: uniphy_pinmux {
mux {
pins = "gpio60";
function = "rx2";
drive-strength = <8>;
bias-disable;
};
@ -295,30 +316,86 @@
bias-pull-up;
};
};
led_pins: led-state {
power {
pins = "gpio21";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
default_off {
pins = "gpio18", "gpio19", "gpio20", "gpio47",
"gpio44", "gpio35", "gpio36";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
fan_pins: fan-state {
pins = "gpio64", "gpio66";
function = "gpio";
drive-strength = <8>;
bias-disable;
output-high;
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
vdd-supply = <&usb0_vbus>;
};
&ssphy_1 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
vdd-supply = <&usb1_vbus>;
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
partitions {
status = "disabled";
};
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -330,66 +407,70 @@
partition@0 {
label = "0:sbl1";
reg = <0x00000000 0x00060000>;
reg = <0x0 0x60000>;
read-only;
};
partition@60000 {
label = "0:mibib";
reg = <0x00060000 0x00040000>;
reg = <0x00060000 0x40000>;
read-only;
};
partition@a0000 {
label = "0:qsee";
reg = <0x000a0000 0x001e0000>;
reg = <0x000a0000 0x1e0000>;
read-only;
};
partition@280000 {
label = "0:devcfg";
reg = <0x00280000 0x00020000>;
reg = <0x00280000 0x20000>;
read-only;
};
partition@2a0000 {
label = "0:apdp";
reg = <0x002a0000 0x00020000>;
reg = <0x002a0000 0x20000>;
read-only;
};
partition@2c0000 {
label = "0:rpm";
reg = <0x002c0000 0x00040000>;
reg = <0x002c0000 0x40000>;
read-only;
};
partition@300000 {
label = "0:cdt";
reg = <0x00300000 0x00020000>;
reg = <0x00300000 0x20000>;
read-only;
};
partition@320000 {
label = "0:appsbl";
reg = <0x00320000 0x000c0000>;
reg = <0x00320000 0xc0000>;
read-only;
};
partition@3e0000 {
label = "0:appsblenv";
reg = <0x003e0000 0x00020000>;
reg = <0x003e0000 0x20000>;
};
partition@400000 {
compatible = "linux,ubi";
label = "UBI_DEV";
reg = <0x00400000 0x0fc00000>;
reg = <0x00400000 0xfc00000>;
};
};
};
};
&blsp1_i2c2 {
status = "okay";
};
&mdio {
status = "okay";
@ -439,9 +520,9 @@
};
ethernet-phy-package@8 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <8>;
qcom,package-mode = "qsgmii";
@ -471,7 +552,7 @@
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <10>;
reg = <0x10>;
ports {
#address-cells = <1>;
@ -538,7 +619,8 @@
compatible = "virtual,mdio-gpio";
pinctrl-0 = <&mdio_gpio_pins>;
pinctrl-names = "default";
gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>, <&tlmm 54 GPIO_ACTIVE_HIGH>;
gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>,
<&tlmm 54 GPIO_ACTIVE_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -562,28 +644,25 @@
pinctrl-0 = <&uniphy_pins>;
pinctrl-names = "default";
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT5 | ESS_PORT6)>;
switch_wan_bmp = <ESS_PORT4>;
switch_mac_mode = <MAC_MODE_QSGMII>;
switch_mac_mode1 = <MAC_MODE_10GBASE_R>;
switch_mac_mode2 = <MAC_MODE_USXGMII>;
switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT5 | ESS_PORT6)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT4>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <MAC_MODE_10GBASE_R>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0x8>;
};
port@1 {
port_id = <2>;
phy_address = <0x9>;
};
port@2 {
port_id = <3>;
phy_address = <0xa>;
};
port@3 {
port_id = <4>;
phy_address = <0xb>;
@ -593,8 +672,8 @@
port_id = <5>;
phy_address = <30>;
phy_i2c_address = <30>;
phy-i2c-mode;
media-type = "sfp";
phy-i2c-mode; /*i2c access phy */
media-type = "sfp"; /* fiber mode */
sfp_tx_dis_pin = <&tlmm 48 GPIO_ACTIVE_HIGH>;
sfp_mod_present_pin = <&tlmm 46 GPIO_ACTIVE_LOW>;
};
@ -656,6 +735,5 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Asus-RT-AX89X";
};

View File

@ -0,0 +1,542 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021, Flole <flole@flole.de>
* Copyright (c) 2023, Andrew Smith <gul.code@outlook.com>
*/
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_front_blue;
led-failsafe = &led_front_red;
led-running = &led_front_green;
led-upgrade = &led_front_white;
label-mac-device = &dp2;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " ubi.mtd=rootfs root=/dev/ubiblock0_0";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
led_front_blue: front-blue {
function = LED_FUNCTION_STATUS;
gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_BLUE>;
};
led_front_green: front-green {
function = LED_FUNCTION_STATUS;
gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
};
led_front_red: front-red {
function = LED_FUNCTION_STATUS;
gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_RED>;
};
led_front_white: front-white {
function = LED_FUNCTION_STATUS;
gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_WHITE>;
};
led_power_green: power-green {
function = LED_FUNCTION_POWER;
gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
};
led_power_red: power-red {
function = LED_FUNCTION_POWER;
gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_RED>;
panic-indicator;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
leds_pins: leds_pinmux {
led_power_green {
pins = "gpio21";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_power_red {
pins = "gpio22";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_white {
pins = "gpio26";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_green {
pins = "gpio29";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_red {
pins = "gpio31";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_blue {
pins = "gpio33";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&blsp1_i2c2 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
tlc59208f@27 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,tlc59108";
reg = <0x27>;
led@0 {
label = "rgb:led0";
reg = <0>;
linux,default-trigger = "default-off";
};
led@1 {
label = "rgb:led1";
reg = <1>;
linux,default-trigger = "default-off";
};
led@2 {
label = "rgb:led2";
reg = <2>;
linux,default-trigger = "default-off";
};
led@3 {
label = "rgb:led3";
reg = <3>;
linux,default-trigger = "default-off";
};
};
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
/*
* Bootloader will find the NAND DT node by the compatible and
* then "fixup" it by adding the partitions from the SMEM table
* using the legacy bindings thus making it impossible for us
* to change the partition table or utilize NVMEM for calibration.
* So add a dummy partitions node that bootloader will populate
* and set it as disabled so the kernel ignores it instead of
* printing warnings due to the broken way bootloader adds the
* partitions.
*/
partitions {
status = "disabled";
};
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:sbl1";
reg = <0x00 0x100000>;
read-only;
};
partition@100000 {
label = "0:mibib";
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "0:bootconfig";
reg = <0x200000 0x80000>;
read-only;
};
partition@280000 {
label = "0:bootconfig_1";
reg = <0x280000 0x80000>;
read-only;
};
partition@300000 {
label = "0:qsee";
reg = <0x300000 0x300000>;
read-only;
};
partition@600000 {
label = "0:qsee_1";
reg = <0x600000 0x300000>;
read-only;
};
partition@900000 {
label = "0:devcfg";
reg = <0x900000 0x80000>;
read-only;
};
partition@980000 {
label = "0:devcfg_1";
reg = <0x980000 0x80000>;
read-only;
};
partition@a00000 {
label = "0:apdp";
reg = <0xa00000 0x80000>;
read-only;
};
partition@a80000 {
label = "0:apdp_1";
reg = <0xa80000 0x80000>;
read-only;
};
partition@b00000 {
label = "0:rpm";
reg = <0xb00000 0x80000>;
read-only;
};
partition@b80000 {
label = "0:rpm_1";
reg = <0xb80000 0x80000>;
read-only;
};
partition@c00000 {
label = "0:cdt";
reg = <0xc00000 0x80000>;
read-only;
};
partition@c80000 {
label = "0:cdt_1";
reg = <0xc80000 0x80000>;
read-only;
};
partition@d00000 {
label = "0:appsblenv";
reg = <0xd00000 0x80000>;
};
partition@d80000 {
label = "0:appsbl";
reg = <0xd80000 0x100000>;
read-only;
};
partition@e80000 {
label = "0:appsbl_1";
reg = <0xe80000 0x100000>;
read-only;
};
partition@f80000 {
label = "0:art";
reg = <0xf80000 0x80000>;
read-only;
};
partition@1000000 {
label = "0:art.bak";
reg = <0x1000000 0x80000>;
read-only;
};
partition@1080000 {
label = "config";
reg = <0x1080000 0x100000>;
};
partition@1180000 {
label = "boarddata1";
reg = <0x1180000 0x100000>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_boarddata1_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_boarddata1_6: macaddr@6 {
reg = <0x6 0x6>;
};
};
};
partition@1280000 {
label = "boarddata2";
reg = <0x1280000 0x100000>;
};
partition@1380000 {
label = "pot";
reg = <0x1380000 0x100000>;
read-only;
};
partition@1480000 {
label = "dnidata";
reg = <0x1480000 0x500000>;
read-only;
};
partition@1980000 {
label = "kernel";
reg = <0x1980000 0x620000>;
};
partition@1fa0000 {
label = "rootfs";
reg = <0x1fa0000 0x66e0000>;
};
partition@8680000 {
label = "kernel2";
reg = <0x8680000 0x620000>;
read-only;
};
partition@8ca0000 {
label = "rootfs2";
reg = <0x8ca0000 0x66e0000>;
read-only;
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
compatible = "qcom,qca8075-package";
qca8075_1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
qca8075_2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
qca8075_3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
};
qca8075_4: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
};
};
qca8081_28: ethernet-phy@28 {
compatible = "ethernet-phy-id004d.d101";
reg = <28>;
reset-deassert-us = <10000>;
reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
};
};
&switch {
status = "okay";
switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT5)>; /* lan port bitmap */
switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance2*/
qcom,port_phyinfo {
port@2 {
port_id = <2>;
phy_address = <1>;
};
port@3 {
port_id = <3>;
phy_address = <2>;
};
port@4 {
port_id = <4>;
phy_address = <3>;
};
port@5 {
port_id = <5>;
phy_address = <4>;
};
port@6 {
port_id = <6>;
phy_address = <28>;
port_mac_sel = "QGMAC_PORT";
};
};
};
&edma {
status = "okay";
};
&dp2 {
status = "okay";
phy-handle = <&qca8075_1>;
label = "lan2";
nvmem-cells = <&macaddr_boarddata1_0>;
nvmem-cell-names = "mac-address";
};
&dp3 {
status = "okay";
phy-handle = <&qca8075_2>;
label = "lan3";
nvmem-cells = <&macaddr_boarddata1_0>;
nvmem-cell-names = "mac-address";
};
&dp4 {
status = "okay";
phy-handle = <&qca8075_3>;
label = "lan4";
nvmem-cells = <&macaddr_boarddata1_0>;
nvmem-cell-names = "mac-address";
};
&dp5 {
status = "okay";
phy-handle = <&qca8075_4>;
label = "lan5";
nvmem-cells = <&macaddr_boarddata1_0>;
nvmem-cell-names = "mac-address";
};
&dp6 {
status = "okay";
phy-handle = <&qca8081_28>;
label = "wan";
nvmem-cells = <&macaddr_boarddata1_6>;
nvmem-cell-names = "mac-address";
};
&wifi {
status = "okay";
qcom,ath11k-calibration-variant = "Netgear-SXK80";
};

View File

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Flole <flole@flole.de> */
/dts-v1/;
#include "ipq8074-netgear.dtsi"
#include "ipq8074-sxk80.dtsi"
/ {
model = "Netgear SXR80";

View File

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Flole <flole@flole.de> */
/dts-v1/;
#include "ipq8074-netgear.dtsi"
#include "ipq8074-sxk80.dtsi"
/ {
model = "Netgear SXS80";

View File

@ -3,13 +3,11 @@
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
@ -19,15 +17,14 @@
aliases {
serial0 = &blsp1_uart5;
ethernet0 = &dp6_syn;
ethernet1 = &dp4;
label-mac-device = &dp6_syn;
led-boot = &led_system_blue;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_blue;
ethernet0 = &dp6_syn;
ethernet1 = &dp4;
label-mac-device = &dp6_syn;
};
chosen {
@ -53,7 +50,7 @@
sck-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
led_gpio: gpio {
led_gpio: led-gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
@ -173,6 +170,24 @@
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&mdio {
status = "okay";
@ -181,9 +196,9 @@
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <0>;
qca8075_3: ethernet-phy@3 {
@ -212,14 +227,15 @@
label = "lan1";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -230,8 +246,12 @@
};
};
&blsp1_uart5 {
status = "okay";
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Netgear-WAX630";
};

View File

@ -3,11 +3,9 @@
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include "ipq8074-common.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/input.h>
@ -18,12 +16,10 @@
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_power_white;
led-failsafe = &led_power_red;
led-running = &led_power_white;
led-upgrade = &led_power_white;
label-mac-device = &dp5_syn;
};
@ -47,13 +43,13 @@
function = "router";
};
led_power_red: power-red {
led_power_red: led-2 {
gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
};
led_power_white: power-white {
led_power_white: led-3 {
gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_POWER;
@ -142,14 +138,49 @@
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
@ -159,22 +190,20 @@
partition-0-appsblenv {
compatible = "fixed-partitions";
label = "0:appsblenv";
read-only;
#address-cells = <1>;
#size-cells = <1>;
label = "0:appsblenv";
read-only;
partition@0 {
label = "env-data";
reg = <0x00000000 0x00040000>;
reg = <0x0 0x40000>;
nvmem-layout {
compatible = "u-boot,env";
#address-cells = <1>;
#size-cells = <1>;
macaddr_appsblenv_ethaddr: ethaddr {};
macaddr_appsblenv_ethaddr: ethaddr {
};
};
};
};
@ -184,10 +213,20 @@
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>, <&tlmm 63 GPIO_ACTIVE_LOW>;
/*
* RESET pins of phy chips
*
* WXR-5950AX12 has 2x RESET pins for QCA8075 and AQR113C.
* The pin of QCA8075 is for the chip and not phys in the chip, the
* pin of AQR113C is for 2x chips. So both pins are not appropriate
* to declare them as reset-gpios in phy nodes.
* Multiple entries in reset-gpios of mdio may not be supported, but
* leave the following as-is to show that the those reset pin exists.
*/
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>, /* QCA8075 RESET */
<&tlmm 63 GPIO_ACTIVE_LOW>; /* AQR113C RESET (2x) */
aqr113c_1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
@ -200,9 +239,9 @@
};
ethernet-phy-package@17 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qca8075-package";
reg = <0x18>;
qcom,package-mode = "qsgmii";
@ -312,6 +351,14 @@
nvmem-cell-names = "mac-address";
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
@ -320,6 +367,6 @@
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
qcom,ath11k-calibration-variant = "Buffalo-WXR-5950AX12";
};