diff --git a/config/Config-kernel.in b/config/Config-kernel.in index 39681be95d..c95e496af9 100644 --- a/config/Config-kernel.in +++ b/config/Config-kernel.in @@ -502,12 +502,10 @@ config KERNEL_FRAME_WARN # kernel configurations and lead to devices that dont have working console config KERNEL_DEBUG_LL_UART_NONE bool - default n depends on arm config KERNEL_DEBUG_LL bool - default n depends on arm select KERNEL_DEBUG_LL_UART_NONE help @@ -575,7 +573,6 @@ config KERNEL_PROBE_EVENTS_BTF_ARGS config KERNEL_BPF_KPROBE_OVERRIDE bool depends on KERNEL_KPROBES - default n config KERNEL_BPF_STREAM_PARSER bool "Allow a TCP stream parser to be used with BPF_MAP_TYPE_SOCKMAP" @@ -898,7 +895,6 @@ if KERNEL_CGROUPS bool "Legacy cgroup v1 cpusets controller" depends on KERNEL_CPUSETS depends on !LINUX_6_6 - default n help Legacy cgroup v1 cpusets controller which has been deprecated by cgroup v2 implementation. The v1 is there for legacy applications @@ -1000,7 +996,6 @@ if KERNEL_CGROUPS config KERNEL_MEMCG_V1 bool "Legacy cgroup v1 memory controller" - default n depends on KERNEL_MEMCG depends on !LINUX_6_6 help diff --git a/feeds.conf.default b/feeds.conf.default index 6a9d9d4a86..ea42a5da8e 100644 --- a/feeds.conf.default +++ b/feeds.conf.default @@ -1,4 +1,4 @@ -src-git nss_packages https://github.com/LiBwrt/nss-packages.git +src-git nss_packages https://github.com/qosmio/nss-packages.git src-git sqm_scripts_nss https://github.com/qosmio/sqm-scripts-nss.git src-git packages https://github.com/immortalwrt/packages.git src-git luci https://github.com/immortalwrt/luci.git diff --git a/include/kernel-build.mk b/include/kernel-build.mk index 404c318d41..c7396fda35 100644 --- a/include/kernel-build.mk +++ b/include/kernel-build.mk @@ -144,7 +144,7 @@ define BuildKernel $(Kernel/CompileImage) $(Kernel/CollectDebug) touch $$@ - + mostlyclean: FORCE $(Kernel/Clean) diff --git a/include/quilt.mk b/include/quilt.mk index a58390f6c5..e1ab931f8b 100644 --- a/include/quilt.mk +++ b/include/quilt.mk @@ -173,7 +173,7 @@ define Quilt/Template done; ! $(QUILT_CMD) next 2>/dev/null >/dev/null; \ } $(Quilt/Refresh/$(4)) - + $(3)update: $(3)quilt-check $(Quilt/Refresh/$(4)) endef diff --git a/include/subdir.mk b/include/subdir.mk index b4edbf8b96..ef1a64cfac 100644 --- a/include/subdir.mk +++ b/include/subdir.mk @@ -76,7 +76,7 @@ define subdir $(if $(BUILD_LOG),@mkdir -p $(BUILD_LOG_DIR)/$(1)/$(bd)/$(filter-out __default,$(variant))) $(if $($(1)/autoremove),$(call rebuild_check,$(1)/$(bd),$(target),,$(filter-out __default,$(variant)),$($(1)/$(bd)/variants))) $(call log_make,$(1)/$(bd),$(target),,$(filter-out __default,$(variant)),$($(1)/$(bd)/variants)) \ - || $(call ERROR,$(1), ERROR: $(1)/$(bd) failed to build$(if $(filter-out __default,$(variant)), (build variant: $(variant))).,$(findstring $(bd),$($(1)/builddirs-ignore-$(target)))) + || $(call ERROR,$(1), ERROR: $(1)/$(bd) failed to build$(if $(filter-out __default,$(variant)), (build variant: $(variant))).,$(findstring $(bd),$($(1)/builddirs-ignore-$(target)))) ) $(if $(PREREQ_ONLY)$(DUMP_TARGET_DB),, # aliases diff --git a/package/base-files/files/bin/config_generate b/package/base-files/files/bin/config_generate index 9c693cba9e..0d285b79db 100755 --- a/package/base-files/files/bin/config_generate +++ b/package/base-files/files/bin/config_generate @@ -3,6 +3,7 @@ CFG=/etc/board.json . /usr/share/libubox/jshn.sh +. /lib/functions/ipv4.sh [ -s $CFG ] || /bin/board_detect || exit 1 [ -s /etc/config/network -a -s /etc/config/system ] && exit 0 @@ -42,8 +43,7 @@ generate_static_network() { set network.loopback='interface' set network.loopback.device='lo' set network.loopback.proto='static' - set network.loopback.ipaddr='127.0.0.1' - set network.loopback.netmask='255.0.0.0' + add_list network.loopback.ipaddr='127.0.0.1/8' EOF [ -e /proc/sys/net/ipv6 ] && { uci -q batch <<-EOF @@ -160,18 +160,19 @@ generate_network() { case "$protocol" in static) - local ipad + local ipad netm prefix case "$1" in lan) ipad=${ipaddr:-"192.168.1.1"} ;; *) ipad=${ipaddr:-"192.168.$((addr_offset++)).1"} ;; esac netm=${netmask:-"255.255.255.0"} + str2ip netm "$netm" + netmask2prefix prefix "$netm" uci -q batch <<-EOF set network.$1.proto='static' - set network.$1.ipaddr='$ipad' - set network.$1.netmask='$netm' + add_list network.$1.ipaddr='$ipad/$prefix' EOF [ -e /proc/sys/net/ipv6 ] && uci set network.$1.ip6assign='60' ;; diff --git a/package/base-files/files/bin/ipcalc.sh b/package/base-files/files/bin/ipcalc.sh index 871a49ed6e..e8c7a07df6 100755 --- a/package/base-files/files/bin/ipcalc.sh +++ b/package/base-files/files/bin/ipcalc.sh @@ -133,8 +133,7 @@ _ip2str START "$start" _ip2str END "$end" if [ "$start" -le "$ipaddr" ] && [ "$ipaddr" -le "$end" ]; then - echo "error: address $IP inside range $START..$END" >&2 - exit 1 + echo "warning: address $IP inside range $START..$END" >&2 fi echo "START=$START" diff --git a/package/base-files/files/lib/functions/caldata.sh b/package/base-files/files/lib/functions/caldata.sh index f0fc907aef..b260cffbdb 100644 --- a/package/base-files/files/lib/functions/caldata.sh +++ b/package/base-files/files/lib/functions/caldata.sh @@ -201,7 +201,7 @@ ath11k_remove_regdomain() { regdomain=$(hexdump -v -n 2 -s 0x34 -e '1/1 "%02x"' $target) caldata_patch_data "0000" 0x34 0xa "$target" - + for offset in 0x450 0x458 0x500 0x5a8; do regdomain_data=$(hexdump -v -n 2 -s $offset -e '1/1 "%02x"' $target) diff --git a/package/base-files/files/lib/functions/system.sh b/package/base-files/files/lib/functions/system.sh index f43281b5dc..0b44314913 100644 --- a/package/base-files/files/lib/functions/system.sh +++ b/package/base-files/files/lib/functions/system.sh @@ -275,7 +275,7 @@ macaddr_unsetbit_mc() { macaddr_random() { local randsrc=$(get_mac_binary /dev/urandom 0) - + echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${randsrc}")")" } diff --git a/package/base-files/files/lib/upgrade/fwtool.sh b/package/base-files/files/lib/upgrade/fwtool.sh index 0bc6e6924e..75a3422d3a 100644 --- a/package/base-files/files/lib/upgrade/fwtool.sh +++ b/package/base-files/files/lib/upgrade/fwtool.sh @@ -67,7 +67,7 @@ fwtool_check_image() { # lets start with the original case [ "$dev" = "$device" ] # if the evaluated firmware is vanila openwrt, this evals as true -ie # [ ("$dev" == "glinet.gl-b3000") == ("$device" == "glinet,gl-b3000") ] - # however if the firmware is oem then $dev = b3000 and the above check fails resulting + # however if the firmware is oem then $dev = b3000 and the above check fails resulting # in the erroneous warnings. # so we add the secondary check [ "$dev" = "$oem" ]; # If in Step 1 the oem_file was found and valid, the $oem == "b3000" so @@ -86,7 +86,7 @@ fwtool_check_image() { # so we add the check for [ "$dev" = "$oem" ] if (([ "${devicecompat#.*}" != "${imagecompat#.*}" ] || [ "$dev" = "$oem" ])) && [ "$SAVE_CONFIG" = "1" ]; then # Step 4. - # here we have to gaurd against the default case, oem may exsist and default will pass + # here we have to gaurd against the default case, oem may exsist and default will pass # the original check [ "${devicecompat#.*}" != "${imagecompat#.*}" ] so we must # explicitly check $dev == $oem, if it is we update(reuse) the $devicecompat and imagecompat # variable to reflect the case - ( Openwrt -> OEM ) diff --git a/package/base-files/files/sbin/sysupgrade b/package/base-files/files/sbin/sysupgrade index 75817d178a..7d4823246e 100755 --- a/package/base-files/files/sbin/sysupgrade +++ b/package/base-files/files/sbin/sysupgrade @@ -278,7 +278,7 @@ create_backup_archive() { fi done disabled="$disabled\nexit 0" - tar_print_member "/etc/uci-defaults/10_disable_services" "$(echo -e $disabled)" || ret=1 + tar_print_member "/etc/uci-defaults/10_disable_services" "$(echo -e $disabled)" "$(date -r /etc/rc.d "+%s")" || ret=1 fi # Part of archive with installed packages info diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index f89bf8fedf..25e9cdde10 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -1,8 +1,8 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2025.01 -PKG_HASH:=cdef7d507c93f1bbd9f015ea9bc21fa074268481405501945abc6f854d5b686f +PKG_VERSION:=2025.04 +PKG_HASH:=439d3bef296effd54130be6a731c5b118be7fddd7fcc663ccbc5fb18294d8718 PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host UBOOT_USE_INTREE_DTC:=1 @@ -581,6 +581,18 @@ define U-Boot/mt7981_qihoo_360t7 DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 endef +define U-Boot/mt7981_snr_snr-cpe-ax2 + NAME:=SNR SNR-CPE-AX2 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=snr_snr-cpe-ax2 + UBOOT_CONFIG:=mt7981_snr_snr-cpe-ax2 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 +endef + define U-Boot/mt7981_xiaomi_mi-router-ax3000t NAME:=Xiaomi Router AX3000T BUILD_SUBTARGET:=filogic @@ -1029,6 +1041,7 @@ UBOOT_TARGETS := \ mt7981_rfb-snfi \ mt7981_routerich_ax3000 \ mt7981_qihoo_360t7 \ + mt7981_snr_snr-cpe-ax2 \ mt7981_xiaomi_mi-router-ax3000t \ mt7981_xiaomi_mi-router-wr30u \ mt7986_bananapi_bpi-r3-emmc \ diff --git a/package/boot/uboot-mediatek/patches/060-01-clk-mediatek-mt7629-fix-parent-clock-of-some-top-clo.patch b/package/boot/uboot-mediatek/patches/060-01-clk-mediatek-mt7629-fix-parent-clock-of-some-top-clo.patch deleted file mode 100644 index 387cf90477..0000000000 --- a/package/boot/uboot-mediatek/patches/060-01-clk-mediatek-mt7629-fix-parent-clock-of-some-top-clo.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 6e45549f4dac42748d66462e04f940ef6737289d Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 17 Dec 2024 16:39:16 +0800 -Subject: [PATCH 01/10] clk: mediatek: mt7629: fix parent clock of some top - clock muxes - -According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL -shares the same parent selection with CLK_TOP_IRRX_SEL, while the -present parent selection for CLK_TOP_F10M_REF_SEL is actually used -for CLK_TOP_SGMII_REF_1_SEL. - -Signed-off-by: Weijie Gao ---- - drivers/clk/mediatek/clk-mt7629.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7629.c -+++ b/drivers/clk/mediatek/clk-mt7629.c -@@ -186,7 +186,7 @@ static const int pwm_parents[] = { - CLK_TOP_UNIVPLL2_D4 - }; - --static const int f10m_ref_parents[] = { -+static const int sgmii_ref_1_parents[] = { - CLK_XTAL, - CLK_TOP_SGMIIPLL_D2 - }; -@@ -369,7 +369,7 @@ static const struct mtk_composite top_mu - - /* CLK_CFG_1 */ - MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), -- MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), -+ MUX_GATE(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15), - MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), - MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), - -@@ -412,7 +412,7 @@ static const struct mtk_composite top_mu - - /* CLK_CFG_8 */ - MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), -- MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15), -+ MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15), - MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), - }; - diff --git a/package/boot/uboot-mediatek/patches/060-02-arm-dts-mt7629-fix-sgmii-clock-selection-for-etherne.patch b/package/boot/uboot-mediatek/patches/060-02-arm-dts-mt7629-fix-sgmii-clock-selection-for-etherne.patch deleted file mode 100644 index c96490e408..0000000000 --- a/package/boot/uboot-mediatek/patches/060-02-arm-dts-mt7629-fix-sgmii-clock-selection-for-etherne.patch +++ /dev/null @@ -1,28 +0,0 @@ -From ba365c3d23411620d86b5baf621c8f5a4000ab33 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 17 Dec 2024 16:39:20 +0800 -Subject: [PATCH 02/10] arm: dts: mt7629: fix sgmii clock selection for - ethernet - -Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow -sgmiisys1 work correctly. - -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7629.dtsi | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/arch/arm/dts/mt7629.dtsi -+++ b/arch/arm/dts/mt7629.dtsi -@@ -314,8 +314,10 @@ - "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "sgmii_ck", "eth2pll"; - assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>, -- <&topckgen CLK_TOP_F10M_REF_SEL>; -+ <&topckgen CLK_TOP_F10M_REF_SEL>, -+ <&topckgen CLK_TOP_SGMII_REF_1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>, -+ <&topckgen CLK_TOP_SYSPLL4_D16>, - <&topckgen CLK_TOP_SGMIIPLL_D2>; - power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>; - resets = <ðsys ETHSYS_FE_RST>; diff --git a/package/boot/uboot-mediatek/patches/060-03-net-mediatek-use-correct-register-field-for-SGMII-sp.patch b/package/boot/uboot-mediatek/patches/060-03-net-mediatek-use-correct-register-field-for-SGMII-sp.patch deleted file mode 100644 index ba3fbf6d7f..0000000000 --- a/package/boot/uboot-mediatek/patches/060-03-net-mediatek-use-correct-register-field-for-SGMII-sp.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 0d4d8e6f47ef22ea6b3041b4c0cb27b4ed4bf188 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 17 Dec 2024 16:39:23 +0800 -Subject: [PATCH 03/10] net: mediatek: use correct register field for SGMII - speed selection - -The register field for SGMII speed selection is a 2-bit field with -value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved). -So it's necessary to set both bits instead of just setting/clearing -only the lower bit. - -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth.c | 12 ++++++------ - drivers/net/mtk_eth.h | 3 ++- - 2 files changed, 8 insertions(+), 7 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -835,8 +835,8 @@ static int mt7531_port_sgmii_init(struct - } - - /* Set SGMII GEN2 speed(2.5G) */ -- mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), -- SGMSYS_SPEED_2500, SGMSYS_SPEED_2500); -+ mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, -+ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); - - /* Disable SGMII AN */ - mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), -@@ -1281,8 +1281,7 @@ static int mtk_phy_probe(struct udevice - static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) - { - /* Set SGMII GEN1 speed(1G) */ -- clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, -- SGMSYS_SPEED_2500, 0); -+ clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK); - - /* Enable SGMII AN */ - setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, -@@ -1305,8 +1304,9 @@ static void mtk_sgmii_an_init(struct mtk - static void mtk_sgmii_force_init(struct mtk_eth_priv *priv) - { - /* Set SGMII GEN2 speed(2.5G) */ -- setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, -- SGMSYS_SPEED_2500); -+ clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, -+ SGMSYS_SPEED_MASK, -+ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); - - /* Disable SGMII AN */ - clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -108,7 +108,8 @@ enum mkt_eth_capabilities { - - #define SGMSYS_GEN2_SPEED 0x2028 - #define SGMSYS_GEN2_SPEED_V2 0x128 --#define SGMSYS_SPEED_2500 BIT(2) -+#define SGMSYS_SPEED_MASK GENMASK(3, 2) -+#define SGMSYS_SPEED_2500 1 - - /* USXGMII subsystem config registers */ - /* Register to control USXGMII XFI PLL digital */ diff --git a/package/boot/uboot-mediatek/patches/060-04-net-mediatek-correct-register-name-of-ethsys-syscfg1.patch b/package/boot/uboot-mediatek/patches/060-04-net-mediatek-correct-register-name-of-ethsys-syscfg1.patch deleted file mode 100644 index 8c549e76b1..0000000000 --- a/package/boot/uboot-mediatek/patches/060-04-net-mediatek-correct-register-name-of-ethsys-syscfg1.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 7562da9454c1a6eff3db3b41c183e03039e855e6 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 17 Dec 2024 16:39:27 +0800 -Subject: [PATCH 04/10] net: mediatek: correct register name of ethsys syscfg1 - -The SYSCFG0 should be SYSCFG1 according to the programming guide. - -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth.c | 14 +++++++------- - drivers/net/mtk_eth.h | 12 ++++++------ - 2 files changed, 13 insertions(+), 13 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -1450,8 +1450,8 @@ static void mtk_mac_init(struct mtk_eth_ - } - - ge_mode = GE_MODE_RGMII; -- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M, -- SYSCFG0_SGMII_SEL(priv->gmac_id)); -+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M, -+ SYSCFG1_SGMII_SEL(priv->gmac_id)); - if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) - mtk_sgmii_an_init(priv); - else -@@ -1469,9 +1469,9 @@ static void mtk_mac_init(struct mtk_eth_ - } - - /* set the gmac to the right mode */ -- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, -- SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), -- ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id)); -+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, -+ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), -+ ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id)); - - if (priv->force_mode) { - mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | -@@ -1527,8 +1527,8 @@ static void mtk_xmac_init(struct mtk_eth - } - - /* Set GMAC to the correct mode */ -- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, -- SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), -+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, -+ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), - 0); - - if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII && ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -65,11 +65,11 @@ enum mkt_eth_capabilities { - - /* Ethernet subsystem registers */ - --#define ETHSYS_SYSCFG0_REG 0x14 --#define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2)) --#define SYSCFG0_GE_MODE_M 0x3 --#define SYSCFG0_SGMII_SEL_M (0x3 << 8) --#define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) -+#define ETHSYS_SYSCFG1_REG 0x14 -+#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) -+#define SYSCFG1_GE_MODE_M 0x3 -+#define SYSCFG1_SGMII_SEL_M (0x3 << 8) -+#define SYSCFG1_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) - - #define ETHSYS_CLKCFG0_REG 0x2c - #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) -@@ -84,7 +84,7 @@ enum mkt_eth_capabilities { - #define QPHY_SEL_MASK 0x3 - #define SGMII_QPHY_SEL 0x2 - --/* SYSCFG0_GE_MODE: GE Modes */ -+/* SYSCFG1_GE_MODE: GE Modes */ - #define GE_MODE_RGMII 0 - #define GE_MODE_MII 1 - #define GE_MODE_MII_PHY 2 diff --git a/package/boot/uboot-mediatek/patches/060-05-net-mediatek-fix-sgmii-selection-for-mt7622.patch b/package/boot/uboot-mediatek/patches/060-05-net-mediatek-fix-sgmii-selection-for-mt7622.patch deleted file mode 100644 index a45e8789d2..0000000000 --- a/package/boot/uboot-mediatek/patches/060-05-net-mediatek-fix-sgmii-selection-for-mt7622.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 82f05bc48821f3709f22f3d1f6e45290547f74be Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 17 Dec 2024 16:39:41 +0800 -Subject: [PATCH 05/10] net: mediatek: fix sgmii selection for mt7622 - -Unlike other platforms, mt7622 has only one SGMII and it can be -attached to either gmac1 or gmac2. So the register field of the -sgmii selection differs from other platforms as newer platforms can -control each sgmii individually. - -This patch adds a new capability for mt7622 to handle this case. - -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth.c | 10 ++++++++-- - drivers/net/mtk_eth.h | 8 ++++++-- - 2 files changed, 14 insertions(+), 4 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -1434,7 +1434,7 @@ static void mtk_usxgmii_an_init(struct m - - static void mtk_mac_init(struct mtk_eth_priv *priv) - { -- int i, ge_mode = 0; -+ int i, sgmii_sel_mask = 0, ge_mode = 0; - u32 mcr; - - switch (priv->phy_interface) { -@@ -1450,8 +1450,13 @@ static void mtk_mac_init(struct mtk_eth_ - } - - ge_mode = GE_MODE_RGMII; -- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M, -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) -+ sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; -+ -+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask, - SYSCFG1_SGMII_SEL(priv->gmac_id)); -+ - if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) - mtk_sgmii_an_init(priv); - else -@@ -2112,6 +2117,7 @@ static const struct mtk_soc_data mt7623_ - }; - - static const struct mtk_soc_data mt7622_data = { -+ .caps = MT7622_CAPS, - .ana_rgc3 = 0x2028, - .gdma_count = 2, - .pdma_base = PDMA_V1_BASE, ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -23,6 +23,7 @@ enum mkt_eth_capabilities { - /* PATH BITS */ - MTK_ETH_PATH_GMAC1_TRGMII_BIT, - MTK_ETH_PATH_GMAC2_SGMII_BIT, -+ MTK_ETH_PATH_MT7622_SGMII_BIT, - }; - - #define MTK_TRGMII BIT(MTK_TRGMII_BIT) -@@ -36,6 +37,7 @@ enum mkt_eth_capabilities { - #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) - - #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) -+#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) - - #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) - -@@ -45,6 +47,8 @@ enum mkt_eth_capabilities { - - #define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) - -+#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII) -+ - #define MT7623_CAPS (MTK_GMAC1_TRGMII) - - #define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) -@@ -68,8 +72,8 @@ enum mkt_eth_capabilities { - #define ETHSYS_SYSCFG1_REG 0x14 - #define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) - #define SYSCFG1_GE_MODE_M 0x3 --#define SYSCFG1_SGMII_SEL_M (0x3 << 8) --#define SYSCFG1_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) -+#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8) -+#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac)) - - #define ETHSYS_CLKCFG0_REG 0x2c - #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) diff --git a/package/boot/uboot-mediatek/patches/060-06-net-mediatek-fix-gmac2-usability-for-mt7629.patch b/package/boot/uboot-mediatek/patches/060-06-net-mediatek-fix-gmac2-usability-for-mt7629.patch deleted file mode 100644 index 5bc6e705d0..0000000000 --- a/package/boot/uboot-mediatek/patches/060-06-net-mediatek-fix-gmac2-usability-for-mt7629.patch +++ /dev/null @@ -1,73 +0,0 @@ -From d8d7e566545f836dd49611cafbf44eef56434e08 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 17 Dec 2024 16:39:46 +0800 -Subject: [PATCH 06/10] net: mediatek: fix gmac2 usability for mt7629 - -MT7629 need extra setting for gmac2 to work. So additional -capability is added for mt7629 to handle this case. - -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth.c | 6 ++++++ - drivers/net/mtk_eth.h | 7 +++++++ - 2 files changed, 13 insertions(+) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -1437,6 +1437,11 @@ static void mtk_mac_init(struct mtk_eth_ - int i, sgmii_sel_mask = 0, ge_mode = 0; - u32 mcr; - -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) { -+ mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG, -+ INFRA_MISC2_BONDING_OPTION, priv->gmac_id); -+ } -+ - switch (priv->phy_interface) { - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII: -@@ -2101,6 +2106,7 @@ static const struct mtk_soc_data mt7981_ - }; - - static const struct mtk_soc_data mt7629_data = { -+ .caps = MT7629_CAPS, - .ana_rgc3 = 0x128, - .gdma_count = 2, - .pdma_base = PDMA_V1_BASE, ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -24,6 +24,7 @@ enum mkt_eth_capabilities { - MTK_ETH_PATH_GMAC1_TRGMII_BIT, - MTK_ETH_PATH_GMAC2_SGMII_BIT, - MTK_ETH_PATH_MT7622_SGMII_BIT, -+ MTK_ETH_PATH_MT7629_GMAC2_BIT, - }; - - #define MTK_TRGMII BIT(MTK_TRGMII_BIT) -@@ -38,6 +39,7 @@ enum mkt_eth_capabilities { - - #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) - #define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) -+#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) - - #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) - -@@ -51,6 +53,8 @@ enum mkt_eth_capabilities { - - #define MT7623_CAPS (MTK_GMAC1_TRGMII) - -+#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA) -+ - #define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) - - #define MT7986_CAPS (MTK_NETSYS_V2) -@@ -88,6 +92,9 @@ enum mkt_eth_capabilities { - #define QPHY_SEL_MASK 0x3 - #define SGMII_QPHY_SEL 0x2 - -+#define MT7629_INFRA_MISC2_REG 0x70c -+#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0) -+ - /* SYSCFG1_GE_MODE: GE Modes */ - #define GE_MODE_RGMII 0 - #define GE_MODE_MII 1 diff --git a/package/boot/uboot-mediatek/patches/060-07-net-mediatek-add-support-for-10GBASE-R.patch b/package/boot/uboot-mediatek/patches/060-07-net-mediatek-add-support-for-10GBASE-R.patch deleted file mode 100644 index f7a63a5b8a..0000000000 --- a/package/boot/uboot-mediatek/patches/060-07-net-mediatek-add-support-for-10GBASE-R.patch +++ /dev/null @@ -1,147 +0,0 @@ -From ad0c47109e4c9f6297aa247d8bbf7131438bc435 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 17 Dec 2024 16:39:50 +0800 -Subject: [PATCH 07/10] net: mediatek: add support for 10GBASE-R - -This patch adds support for 10GBASE-R interface mode - -Signed-off-by: Bo-Cun Chen -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth.c | 83 +++++++++++++++++++++++++++++++++++++++++-- - 1 file changed, 81 insertions(+), 2 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -1246,6 +1246,7 @@ static int mtk_phy_start(struct mtk_eth_ - - if (!priv->force_mode) { - if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || - priv->phy_interface == PHY_INTERFACE_MODE_XGMII) - mtk_xphy_link_adjust(priv); - else -@@ -1425,6 +1426,71 @@ static void mtk_usxgmii_setup_phya_an_10 - udelay(400); - } - -+static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv) -+{ -+ regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C); -+ regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); -+ regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000); -+ ndelay(1020); -+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000); -+ ndelay(1020); -+ -+ regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); -+ regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); -+ regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); -+ regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); -+ regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); -+ regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); -+ regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); -+ regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); -+ regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); -+ regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); -+ regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); -+ regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); -+ regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); -+ regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); -+ regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); -+ regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); -+ regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); -+ regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); -+ regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); -+ regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); -+ regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); -+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); -+ regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); -+ ndelay(1020); -+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); -+ regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); -+ regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); -+ regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); -+ regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); -+ regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); -+ regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); -+ regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100); -+ regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000); -+ regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000); -+ regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); -+ if (priv->gmac_id == 2) -+ regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400); -+ regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); -+ regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); -+ udelay(150); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); -+ udelay(15); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); -+ ndelay(1020); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); -+ udelay(100); -+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); -+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); -+ regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); -+ udelay(400); -+} -+ - static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) - { - mtk_xfi_pll_enable(priv); -@@ -1432,6 +1498,13 @@ static void mtk_usxgmii_an_init(struct m - mtk_usxgmii_setup_phya_an_10000(priv); - } - -+static void mtk_10gbaser_init(struct mtk_eth_priv *priv) -+{ -+ mtk_xfi_pll_enable(priv); -+ mtk_usxgmii_reset(priv); -+ mtk_usxgmii_setup_phya_force_10000(priv); -+} -+ - static void mtk_mac_init(struct mtk_eth_priv *priv) - { - int i, sgmii_sel_mask = 0, ge_mode = 0; -@@ -1532,6 +1605,9 @@ static void mtk_xmac_init(struct mtk_eth - case PHY_INTERFACE_MODE_USXGMII: - mtk_usxgmii_an_init(priv); - break; -+ case PHY_INTERFACE_MODE_10GBASER: -+ mtk_10gbaser_init(priv); -+ break; - default: - break; - } -@@ -1541,7 +1617,8 @@ static void mtk_xmac_init(struct mtk_eth - SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), - 0); - -- if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII && -+ if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && - priv->gmac_id == 1) { - mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX, - NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL); -@@ -1843,6 +1920,7 @@ static int mtk_eth_probe(struct udevice - - /* Set MAC mode */ - if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || - priv->phy_interface == PHY_INTERFACE_MODE_XGMII) - mtk_xmac_init(priv); - else -@@ -1977,7 +2055,8 @@ static int mtk_eth_of_to_plat(struct ude - /* Upstream linux use mediatek,pnswap instead of pn_swap */ - priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || - ofnode_read_bool(args.node, "mediatek,pnswap"); -- } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) { -+ } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) { - /* get corresponding usxgmii phandle */ - ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", - NULL, 0, 0, &args); diff --git a/package/boot/uboot-mediatek/patches/060-08-net-mediatek-make-sgmii-usxgmii-optional.patch b/package/boot/uboot-mediatek/patches/060-08-net-mediatek-make-sgmii-usxgmii-optional.patch deleted file mode 100644 index d6a885f889..0000000000 --- a/package/boot/uboot-mediatek/patches/060-08-net-mediatek-make-sgmii-usxgmii-optional.patch +++ /dev/null @@ -1,144 +0,0 @@ -From 5ac929fd1ab1d0dc77b9167952aea7cafdb8619f Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 17 Dec 2024 16:39:55 +0800 -Subject: [PATCH 08/10] net: mediatek: make sgmii/usxgmii optional - -Not all platforms supports sgmii and/or usxgmii. So we add Kconfig -options for these features and enable them only for supported -platforms. - -Signed-off-by: Weijie Gao ---- - drivers/net/Kconfig | 12 ++++++++++++ - drivers/net/mtk_eth.c | 39 +++++++++++++++++++++++++++++---------- - 2 files changed, 41 insertions(+), 10 deletions(-) - ---- a/drivers/net/Kconfig -+++ b/drivers/net/Kconfig -@@ -975,6 +975,18 @@ config MEDIATEK_ETH - This Driver support MediaTek Ethernet GMAC - Say Y to enable support for the MediaTek Ethernet GMAC. - -+if MEDIATEK_ETH -+ -+config MTK_ETH_SGMII -+ bool -+ default y if ARCH_MEDIATEK && !TARGET_MT7623 -+ -+config MTK_ETH_XGMII -+ bool -+ default y if TARGET_MT7987 || TARGET_MT7988 -+ -+endif # MEDIATEK_ETH -+ - config HIFEMAC_ETH - bool "HiSilicon Fast Ethernet Controller" - select DM_CLK ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -1505,7 +1505,7 @@ static void mtk_10gbaser_init(struct mtk - mtk_usxgmii_setup_phya_force_10000(priv); - } - --static void mtk_mac_init(struct mtk_eth_priv *priv) -+static int mtk_mac_init(struct mtk_eth_priv *priv) - { - int i, sgmii_sel_mask = 0, ge_mode = 0; - u32 mcr; -@@ -1522,13 +1522,16 @@ static void mtk_mac_init(struct mtk_eth_ - break; - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_2500BASEX: -+ if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { -+ printf("Error: SGMII is not supported on this platform\n"); -+ return -ENOTSUPP; -+ } -+ - if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) { - mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK, - SGMII_QPHY_SEL); - } - -- ge_mode = GE_MODE_RGMII; -- - if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) - sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; - -@@ -1539,6 +1542,8 @@ static void mtk_mac_init(struct mtk_eth_ - mtk_sgmii_an_init(priv); - else - mtk_sgmii_force_init(priv); -+ -+ ge_mode = GE_MODE_RGMII; - break; - case PHY_INTERFACE_MODE_MII: - case PHY_INTERFACE_MODE_GMII: -@@ -1595,12 +1600,19 @@ static void mtk_mac_init(struct mtk_eth_ - RX_RST | RXC_DQSISEL); - mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0); - } -+ -+ return 0; - } - --static void mtk_xmac_init(struct mtk_eth_priv *priv) -+static int mtk_xmac_init(struct mtk_eth_priv *priv) - { - u32 force_link = 0; - -+ if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { -+ printf("Error: 10Gb interface is not supported on this platform\n"); -+ return -ENOTSUPP; -+ } -+ - switch (priv->phy_interface) { - case PHY_INTERFACE_MODE_USXGMII: - mtk_usxgmii_an_init(priv); -@@ -1633,6 +1645,8 @@ static void mtk_xmac_init(struct mtk_eth - - /* Force GMAC link down */ - mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE); -+ -+ return 0; - } - - static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) -@@ -1922,9 +1936,12 @@ static int mtk_eth_probe(struct udevice - if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || - priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || - priv->phy_interface == PHY_INTERFACE_MODE_XGMII) -- mtk_xmac_init(priv); -+ ret = mtk_xmac_init(priv); - else -- mtk_mac_init(priv); -+ ret = mtk_mac_init(priv); -+ -+ if (ret) -+ return ret; - - /* Probe phy if switch is not specified */ - if (priv->sw == SW_NONE) -@@ -2032,8 +2049,9 @@ static int mtk_eth_of_to_plat(struct ude - } - } - -- if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII || -- priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { -+ if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) && -+ IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { - /* get corresponding sgmii phandle */ - ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", - NULL, 0, 0, &args); -@@ -2055,8 +2073,9 @@ static int mtk_eth_of_to_plat(struct ude - /* Upstream linux use mediatek,pnswap instead of pn_swap */ - priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || - ofnode_read_bool(args.node, "mediatek,pnswap"); -- } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) { -+ } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && -+ IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { - /* get corresponding usxgmii phandle */ - ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", - NULL, 0, 0, &args); diff --git a/package/boot/uboot-mediatek/patches/060-09-net-mediatek-don-t-enable-GDMA-cpu-bridge-unconditio.patch b/package/boot/uboot-mediatek/patches/060-09-net-mediatek-don-t-enable-GDMA-cpu-bridge-unconditio.patch deleted file mode 100644 index c9ea8f4401..0000000000 --- a/package/boot/uboot-mediatek/patches/060-09-net-mediatek-don-t-enable-GDMA-cpu-bridge-unconditio.patch +++ /dev/null @@ -1,36 +0,0 @@ -From b9dfb5636bc5eb9b783b88b8388dc7d1f41d6498 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 17 Dec 2024 16:39:59 +0800 -Subject: [PATCH 09/10] net: mediatek: don't enable GDMA cpu bridge - unconditionally for NETSYSv3 - -Enable GDMA cpu bridge only when 10Gb interface is enabled for GMAC other -than GMAC0, or when MT7988 internal switch is used. - -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth.c | 12 +++++++++--- - 1 file changed, 9 insertions(+), 3 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -1762,10 +1762,16 @@ static int mtk_eth_start(struct udevice - if (priv->sw == SW_MT7988 && priv->gmac_id == 0) { - mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, - GDMA_BRIDGE_TO_CPU); -- } - -- mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, -- GDMA_CPU_BRIDGE_EN); -+ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, -+ GDMA_CPU_BRIDGE_EN); -+ } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || -+ priv->phy_interface == PHY_INTERFACE_MODE_XGMII) && -+ priv->gmac_id != 0) { -+ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, -+ GDMA_CPU_BRIDGE_EN); -+ } - } - - udelay(500); diff --git a/package/boot/uboot-mediatek/patches/060-10-net-mediatek-fix-usability-with-wget-command.patch b/package/boot/uboot-mediatek/patches/060-10-net-mediatek-fix-usability-with-wget-command.patch deleted file mode 100644 index a20d79030f..0000000000 --- a/package/boot/uboot-mediatek/patches/060-10-net-mediatek-fix-usability-with-wget-command.patch +++ /dev/null @@ -1,37 +0,0 @@ -From c949686e558e00cbb8c38f7c060701006d70cea8 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 17 Dec 2024 16:40:03 +0800 -Subject: [PATCH 10/10] net: mediatek: fix usability with wget command - -The wget command currently cannot work correctly with mtk_eth driver. -This patch fixed this by increase DMA ring size and invalidate ring data -after use. - -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth.c | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -29,8 +29,8 @@ - - #include "mtk_eth.h" - --#define NUM_TX_DESC 24 --#define NUM_RX_DESC 24 -+#define NUM_TX_DESC 32 -+#define NUM_RX_DESC 32 - #define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN) - #define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) - #define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) -@@ -1897,6 +1897,9 @@ static int mtk_eth_free_pkt(struct udevi - - rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; - -+ invalidate_dcache_range((ulong)rxd->rxd1, -+ (ulong)rxd->rxd1 + PKTSIZE_ALIGN); -+ - if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || - MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) - rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); diff --git a/package/boot/uboot-mediatek/patches/061-01-net-mediatek-split-ethernet-switch-code-from-mtk_eth.patch b/package/boot/uboot-mediatek/patches/061-01-net-mediatek-split-ethernet-switch-code-from-mtk_eth.patch deleted file mode 100644 index b212c6c219..0000000000 --- a/package/boot/uboot-mediatek/patches/061-01-net-mediatek-split-ethernet-switch-code-from-mtk_eth.patch +++ /dev/null @@ -1,6311 +0,0 @@ -From 626cdca5b68acdc72d2533e2ed2306c06f296725 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 10 Jan 2025 16:41:13 +0800 -Subject: [PATCH 1/3] net: mediatek: split ethernet switch code from mtk_eth.c - -mtk_eth.c contains not only the ethernet GMAC/DMA driver, but also -some ethernet switch initialization code. As we may add more switch -support in the future, it's better to move them out of mtk_eth.c to -avoid increasing the code complexity. - -Since not all switches are supported for a particular board, Kconfig -options are added to allow user to select which switch should be -built into u-boot. If multiple switches are selected, auto-detecting -can also be enabled. - -Signed-off-by: Weijie Gao ---- - drivers/net/Kconfig | 21 +- - drivers/net/Makefile | 2 +- - drivers/net/mtk_eth/Kconfig | 35 + - drivers/net/mtk_eth/Makefile | 9 + - drivers/net/mtk_eth/mt7530.c | 281 ++++++++ - drivers/net/mtk_eth/mt7531.c | 293 +++++++++ - drivers/net/mtk_eth/mt753x.c | 262 ++++++++ - drivers/net/mtk_eth/mt753x.h | 286 ++++++++ - drivers/net/mtk_eth/mt7988.c | 160 +++++ - drivers/net/{ => mtk_eth}/mtk_eth.c | 971 ++++------------------------ - drivers/net/{ => mtk_eth}/mtk_eth.h | 301 ++------- - 11 files changed, 1520 insertions(+), 1101 deletions(-) - create mode 100644 drivers/net/mtk_eth/Kconfig - create mode 100644 drivers/net/mtk_eth/Makefile - create mode 100644 drivers/net/mtk_eth/mt7530.c - create mode 100644 drivers/net/mtk_eth/mt7531.c - create mode 100644 drivers/net/mtk_eth/mt753x.c - create mode 100644 drivers/net/mtk_eth/mt753x.h - create mode 100644 drivers/net/mtk_eth/mt7988.c - rename drivers/net/{ => mtk_eth}/mtk_eth.c (62%) - rename drivers/net/{ => mtk_eth}/mtk_eth.h (59%) - ---- a/drivers/net/Kconfig -+++ b/drivers/net/Kconfig -@@ -966,26 +966,7 @@ config TSEC_ENET - This driver implements support for the (Enhanced) Three-Speed - Ethernet Controller found on Freescale SoCs. - --config MEDIATEK_ETH -- bool "MediaTek Ethernet GMAC Driver" -- select PHYLIB -- select DM_GPIO -- select DM_RESET -- help -- This Driver support MediaTek Ethernet GMAC -- Say Y to enable support for the MediaTek Ethernet GMAC. -- --if MEDIATEK_ETH -- --config MTK_ETH_SGMII -- bool -- default y if ARCH_MEDIATEK && !TARGET_MT7623 -- --config MTK_ETH_XGMII -- bool -- default y if TARGET_MT7987 || TARGET_MT7988 -- --endif # MEDIATEK_ETH -+source "drivers/net/mtk_eth/Kconfig" - - config HIFEMAC_ETH - bool "HiSilicon Fast Ethernet Controller" ---- a/drivers/net/Makefile -+++ b/drivers/net/Makefile -@@ -67,7 +67,7 @@ obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio - obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o - obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o - obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o --obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o -+obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth/ - obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o - obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o - obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o ---- /dev/null -+++ b/drivers/net/mtk_eth/Kconfig -@@ -0,0 +1,35 @@ -+ -+config MEDIATEK_ETH -+ bool "MediaTek Ethernet GMAC Driver" -+ select PHYLIB -+ select DM_GPIO -+ select DM_RESET -+ help -+ This Driver support MediaTek Ethernet GMAC -+ Say Y to enable support for the MediaTek Ethernet GMAC. -+ -+if MEDIATEK_ETH -+ -+config MTK_ETH_SGMII -+ bool -+ default y if ARCH_MEDIATEK && !TARGET_MT7623 -+ -+config MTK_ETH_XGMII -+ bool -+ default y if TARGET_MT7988 -+ -+config MTK_ETH_SWITCH_MT7530 -+ bool "Support for MediaTek MT7530 ethernet switch" -+ default y if TARGET_MT7623 || SOC_MT7621 -+ -+config MTK_ETH_SWITCH_MT7531 -+ bool "Support for MediaTek MT7531 ethernet switch" -+ default y if TARGET_MT7622 || TARGET_MT7629 || TARGET_MT7981 || \ -+ TARGET_MT7986 -+ -+config MTK_ETH_SWITCH_MT7988 -+ bool "Support for MediaTek MT7988 built-in ethernet switch" -+ depends on TARGET_MT7988 -+ default y -+ -+endif # MEDIATEK_ETH ---- /dev/null -+++ b/drivers/net/mtk_eth/Makefile -@@ -0,0 +1,9 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+# Copyright (C) 2025 MediaTek Inc. -+# Author: Weijie Gao -+ -+obj-y += mtk_eth.o -+obj-$(CONFIG_MTK_ETH_SWITCH_MT7530) += mt753x.o mt7530.o -+obj-$(CONFIG_MTK_ETH_SWITCH_MT7531) += mt753x.o mt7531.o -+obj-$(CONFIG_MTK_ETH_SWITCH_MT7988) += mt753x.o mt7988.o ---- /dev/null -+++ b/drivers/net/mtk_eth/mt7530.c -@@ -0,0 +1,281 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2025 MediaTek Inc. -+ * -+ * Author: Weijie Gao -+ * Author: Mark Lee -+ */ -+ -+#include -+#include -+#include -+#include -+#include "mtk_eth.h" -+#include "mt753x.h" -+ -+#define CHIP_REV 0x7ffc -+#define CHIP_NAME_S 16 -+#define CHIP_NAME_M 0xffff0000 -+#define CHIP_REV_S 0 -+#define CHIP_REV_M 0x0f -+ -+static void mt7530_core_reg_write(struct mt753x_switch_priv *priv, u32 reg, -+ u32 val) -+{ -+ u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); -+ -+ mtk_mmd_ind_write(priv->epriv.eth, phy_addr, 0x1f, reg, val); -+} -+ -+static int mt7530_pad_clk_setup(struct mt753x_switch_priv *priv, int mode) -+{ -+ u32 ncpo1, ssc_delta; -+ -+ switch (mode) { -+ case PHY_INTERFACE_MODE_RGMII: -+ ncpo1 = 0x0c80; -+ ssc_delta = 0x87; -+ break; -+ -+ default: -+ printf("error: xMII mode %d is not supported\n", mode); -+ return -EINVAL; -+ } -+ -+ /* Disable MT7530 core clock */ -+ mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0); -+ -+ /* Disable MT7530 PLL */ -+ mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1, -+ (2 << RG_GSWPLL_POSDIV_200M_S) | -+ (32 << RG_GSWPLL_FBKDIV_200M_S)); -+ -+ /* For MT7530 core clock = 500Mhz */ -+ mt7530_core_reg_write(priv, CORE_GSWPLL_GRP2, -+ (1 << RG_GSWPLL_POSDIV_500M_S) | -+ (25 << RG_GSWPLL_FBKDIV_500M_S)); -+ -+ /* Enable MT7530 PLL */ -+ mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1, -+ (2 << RG_GSWPLL_POSDIV_200M_S) | -+ (32 << RG_GSWPLL_FBKDIV_200M_S) | -+ RG_GSWPLL_EN_PRE); -+ -+ udelay(20); -+ -+ mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); -+ -+ /* Setup the MT7530 TRGMII Tx Clock */ -+ mt7530_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1); -+ mt7530_core_reg_write(priv, CORE_PLL_GROUP6, 0); -+ mt7530_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta); -+ mt7530_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta); -+ mt7530_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | -+ RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); -+ -+ mt7530_core_reg_write(priv, CORE_PLL_GROUP2, -+ RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | -+ (1 << RG_SYSPLL_POSDIV_S)); -+ -+ mt7530_core_reg_write(priv, CORE_PLL_GROUP7, -+ RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) | -+ RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); -+ -+ /* Enable MT7530 core clock */ -+ mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, -+ REG_GSWCK_EN | REG_TRGMIICK_EN); -+ -+ return 0; -+} -+ -+static void mt7530_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) -+{ -+ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; -+ u32 pmcr = FORCE_MODE; -+ -+ if (enable) -+ pmcr = priv->pmcr; -+ -+ mt753x_reg_write(priv, PMCR_REG(6), pmcr); -+} -+ -+static int mt7530_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) -+{ -+ struct mt753x_switch_priv *priv = bus->priv; -+ -+ if (devad < 0) -+ return mtk_mii_read(priv->epriv.eth, addr, reg); -+ -+ return mtk_mmd_ind_read(priv->epriv.eth, addr, devad, reg); -+} -+ -+static int mt7530_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, -+ u16 val) -+{ -+ struct mt753x_switch_priv *priv = bus->priv; -+ -+ if (devad < 0) -+ return mtk_mii_write(priv->epriv.eth, addr, reg, val); -+ -+ return mtk_mmd_ind_write(priv->epriv.eth, addr, devad, reg, val); -+} -+ -+static int mt7530_mdio_register(struct mt753x_switch_priv *priv) -+{ -+ struct mii_dev *mdio_bus = mdio_alloc(); -+ int ret; -+ -+ if (!mdio_bus) -+ return -ENOMEM; -+ -+ mdio_bus->read = mt7530_mdio_read; -+ mdio_bus->write = mt7530_mdio_write; -+ snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name); -+ -+ mdio_bus->priv = priv; -+ -+ ret = mdio_register(mdio_bus); -+ if (ret) { -+ mdio_free(mdio_bus); -+ return ret; -+ } -+ -+ priv->mdio_bus = mdio_bus; -+ -+ return 0; -+} -+ -+static int mt7530_setup(struct mtk_eth_switch_priv *swpriv) -+{ -+ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; -+ u16 phy_addr, phy_val; -+ u32 i, val, txdrv; -+ -+ priv->smi_addr = MT753X_DFL_SMI_ADDR; -+ priv->reg_read = mt753x_mdio_reg_read; -+ priv->reg_write = mt753x_mdio_reg_write; -+ -+ if (!MTK_HAS_CAPS(priv->epriv.soc->caps, MTK_TRGMII_MT7621_CLK)) { -+ /* Select 250MHz clk for RGMII mode */ -+ mtk_ethsys_rmw(priv->epriv.eth, ETHSYS_CLKCFG0_REG, -+ ETHSYS_TRGMII_CLK_SEL362_5, 0); -+ -+ txdrv = 8; -+ } else { -+ txdrv = 4; -+ } -+ -+ /* Modify HWTRAP first to allow direct access to internal PHYs */ -+ mt753x_reg_read(priv, HWTRAP_REG, &val); -+ val |= CHG_TRAP; -+ val &= ~C_MDIO_BPS; -+ mt753x_reg_write(priv, MHWTRAP_REG, val); -+ -+ /* Calculate the phy base address */ -+ val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3; -+ priv->phy_base = (val | 0x7) + 1; -+ -+ /* Turn off PHYs */ -+ for (i = 0; i < MT753X_NUM_PHYS; i++) { -+ phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); -+ phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); -+ phy_val |= BMCR_PDOWN; -+ mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); -+ } -+ -+ /* Force MAC link down before reset */ -+ mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); -+ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); -+ -+ /* MT7530 reset */ -+ mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); -+ udelay(100); -+ -+ val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | -+ MAC_MODE | FORCE_MODE | -+ MAC_TX_EN | MAC_RX_EN | -+ BKOFF_EN | BACKPR_EN | -+ (SPEED_1000M << FORCE_SPD_S) | -+ FORCE_DPX | FORCE_LINK; -+ -+ /* MT7530 Port6: Forced 1000M/FD, FC disabled */ -+ priv->pmcr = val; -+ -+ /* MT7530 Port5: Forced link down */ -+ mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); -+ -+ /* Keep MAC link down before starting eth */ -+ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); -+ -+ /* MT7530 Port6: Set to RGMII */ -+ mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII); -+ -+ /* Hardware Trap: Enable Port6, Disable Port5 */ -+ mt753x_reg_read(priv, HWTRAP_REG, &val); -+ val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS | -+ (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) | -+ (P5_INTF_MODE_RGMII << P5_INTF_MODE_S); -+ val &= ~(C_MDIO_BPS | P6_INTF_DIS); -+ mt753x_reg_write(priv, MHWTRAP_REG, val); -+ -+ /* Setup switch core pll */ -+ mt7530_pad_clk_setup(priv, priv->epriv.phy_interface); -+ -+ /* Lower Tx Driving for TRGMII path */ -+ for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) -+ mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i), -+ (txdrv << TD_DM_DRVP_S) | -+ (txdrv << TD_DM_DRVN_S)); -+ -+ for (i = 0 ; i < NUM_TRGMII_CTRL; i++) -+ mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16); -+ -+ /* Enable port isolation to block inter-port communication */ -+ mt753x_port_isolation(priv); -+ -+ /* Turn on PHYs */ -+ for (i = 0; i < MT753X_NUM_PHYS; i++) { -+ phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); -+ phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); -+ phy_val &= ~BMCR_PDOWN; -+ mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); -+ } -+ -+ return mt7530_mdio_register(priv); -+} -+ -+static int mt7530_cleanup(struct mtk_eth_switch_priv *swpriv) -+{ -+ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; -+ -+ mdio_unregister(priv->mdio_bus); -+ -+ return 0; -+} -+ -+static int mt7530_detect(struct mtk_eth_priv *priv) -+{ -+ int ret; -+ u32 rev; -+ -+ ret = __mt753x_mdio_reg_read(priv, MT753X_DFL_SMI_ADDR, CHIP_REV, &rev); -+ if (ret) -+ return ret; -+ -+ if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == 0x7530) -+ return 0; -+ -+ return -ENODEV; -+} -+ -+MTK_ETH_SWITCH(mt7530) = { -+ .name = "mt7530", -+ .desc = "MediaTek MT7530", -+ .priv_size = sizeof(struct mt753x_switch_priv), -+ .reset_wait_time = 1000, -+ -+ .detect = mt7530_detect, -+ .setup = mt7530_setup, -+ .cleanup = mt7530_cleanup, -+ .mac_control = mt7530_mac_control, -+}; ---- /dev/null -+++ b/drivers/net/mtk_eth/mt7531.c -@@ -0,0 +1,293 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2025 MediaTek Inc. -+ * -+ * Author: Weijie Gao -+ * Author: Mark Lee -+ */ -+ -+#include -+#include -+#include -+#include -+#include "mtk_eth.h" -+#include "mt753x.h" -+ -+#define CHIP_REV 0x781C -+#define CHIP_NAME_S 16 -+#define CHIP_NAME_M 0xffff0000 -+#define CHIP_REV_S 0 -+#define CHIP_REV_M 0x0f -+#define CHIP_REV_E1 0x0 -+ -+static int mt7531_core_reg_read(struct mt753x_switch_priv *priv, u32 reg) -+{ -+ u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); -+ -+ return mt7531_mmd_read(priv, phy_addr, 0x1f, reg); -+} -+ -+static void mt7531_core_reg_write(struct mt753x_switch_priv *priv, u32 reg, -+ u32 val) -+{ -+ u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); -+ -+ mt7531_mmd_write(priv, phy_addr, 0x1f, reg, val); -+} -+ -+static void mt7531_core_pll_setup(struct mt753x_switch_priv *priv) -+{ -+ /* Step 1 : Disable MT7531 COREPLL */ -+ mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0); -+ -+ /* Step 2: switch to XTAL output */ -+ mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW); -+ -+ mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0); -+ -+ /* Step 3: disable PLLGP and enable program PLLGP */ -+ mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP); -+ -+ /* Step 4: program COREPLL output frequency to 500MHz */ -+ mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M, -+ 2 << RG_COREPLL_POSDIV_S); -+ udelay(25); -+ -+ /* Currently, support XTAL 25Mhz only */ -+ mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M, -+ 0x140000 << RG_COREPLL_SDM_PCW_S); -+ -+ /* Set feedback divide ratio update signal to high */ -+ mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, -+ RG_COREPLL_SDM_PCW_CHG); -+ -+ /* Wait for at least 16 XTAL clocks */ -+ udelay(10); -+ -+ /* Step 5: set feedback divide ratio update signal to low */ -+ mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0); -+ -+ /* add enable 325M clock for SGMII */ -+ mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); -+ -+ /* add enable 250SSC clock for RGMII */ -+ mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); -+ -+ /*Step 6: Enable MT7531 PLL */ -+ mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN); -+ -+ mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL); -+ -+ udelay(25); -+} -+ -+static int mt7531_port_sgmii_init(struct mt753x_switch_priv *priv, u32 port) -+{ -+ if (port != 5 && port != 6) { -+ printf("mt7531: port %d is not a SGMII port\n", port); -+ return -EINVAL; -+ } -+ -+ /* Set SGMII GEN2 speed(2.5G) */ -+ mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, -+ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); -+ -+ /* Disable SGMII AN */ -+ mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), -+ SGMII_AN_ENABLE, 0); -+ -+ /* SGMII force mode setting */ -+ mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE); -+ -+ /* Release PHYA power down state */ -+ mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port), -+ SGMII_PHYA_PWD, 0); -+ -+ return 0; -+} -+ -+static int mt7531_port_rgmii_init(struct mt753x_switch_priv *priv, u32 port) -+{ -+ u32 val; -+ -+ if (port != 5) { -+ printf("error: RGMII mode is not available for port %d\n", -+ port); -+ return -EINVAL; -+ } -+ -+ mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val); -+ val |= GP_CLK_EN; -+ val &= ~GP_MODE_M; -+ val |= GP_MODE_RGMII << GP_MODE_S; -+ val |= TXCLK_NO_REVERSE; -+ val |= RXCLK_NO_DELAY; -+ val &= ~CLK_SKEW_IN_M; -+ val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S; -+ val &= ~CLK_SKEW_OUT_M; -+ val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S; -+ mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val); -+ -+ return 0; -+} -+ -+static void mt7531_phy_setting(struct mt753x_switch_priv *priv) -+{ -+ int i; -+ u32 val; -+ -+ for (i = 0; i < MT753X_NUM_PHYS; i++) { -+ /* Enable HW auto downshift */ -+ mt7531_mii_write(priv, i, 0x1f, 0x1); -+ val = mt7531_mii_read(priv, i, PHY_EXT_REG_14); -+ val |= PHY_EN_DOWN_SHFIT; -+ mt7531_mii_write(priv, i, PHY_EXT_REG_14, val); -+ -+ /* PHY link down power saving enable */ -+ val = mt7531_mii_read(priv, i, PHY_EXT_REG_17); -+ val |= PHY_LINKDOWN_POWER_SAVING_EN; -+ mt7531_mii_write(priv, i, PHY_EXT_REG_17, val); -+ -+ val = mt7531_mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6); -+ val &= ~PHY_POWER_SAVING_M; -+ val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S; -+ mt7531_mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val); -+ } -+} -+ -+static void mt7531_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) -+{ -+ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; -+ u32 pmcr = FORCE_MODE_LNK; -+ -+ if (enable) -+ pmcr = priv->pmcr; -+ -+ mt753x_reg_write(priv, PMCR_REG(5), pmcr); -+ mt753x_reg_write(priv, PMCR_REG(6), pmcr); -+} -+ -+static int mt7531_setup(struct mtk_eth_switch_priv *swpriv) -+{ -+ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; -+ u32 i, val, pmcr, port5_sgmii; -+ u16 phy_addr, phy_val; -+ -+ priv->smi_addr = MT753X_DFL_SMI_ADDR; -+ priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK; -+ priv->reg_read = mt753x_mdio_reg_read; -+ priv->reg_write = mt753x_mdio_reg_write; -+ -+ /* Turn off PHYs */ -+ for (i = 0; i < MT753X_NUM_PHYS; i++) { -+ phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); -+ phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); -+ phy_val |= BMCR_PDOWN; -+ mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); -+ } -+ -+ /* Force MAC link down before reset */ -+ mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); -+ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); -+ -+ /* Switch soft reset */ -+ mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); -+ udelay(100); -+ -+ /* Enable MDC input Schmitt Trigger */ -+ mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN, -+ SMT_IOLB_5_SMI_MDC_EN); -+ -+ mt7531_core_pll_setup(priv); -+ -+ mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val); -+ port5_sgmii = !!(val & PAD_DUAL_SGMII_EN); -+ -+ /* port5 support either RGMII or SGMII, port6 only support SGMII. */ -+ switch (priv->epriv.phy_interface) { -+ case PHY_INTERFACE_MODE_RGMII: -+ if (!port5_sgmii) -+ mt7531_port_rgmii_init(priv, 5); -+ break; -+ -+ case PHY_INTERFACE_MODE_2500BASEX: -+ mt7531_port_sgmii_init(priv, 6); -+ if (port5_sgmii) -+ mt7531_port_sgmii_init(priv, 5); -+ break; -+ -+ default: -+ break; -+ } -+ -+ pmcr = MT7531_FORCE_MODE | -+ (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | -+ MAC_MODE | MAC_TX_EN | MAC_RX_EN | -+ BKOFF_EN | BACKPR_EN | -+ FORCE_RX_FC | FORCE_TX_FC | -+ (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | -+ FORCE_LINK; -+ -+ priv->pmcr = pmcr; -+ -+ /* Keep MAC link down before starting eth */ -+ mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); -+ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); -+ -+ /* Enable port isolation to block inter-port communication */ -+ mt753x_port_isolation(priv); -+ -+ /* Turn on PHYs */ -+ for (i = 0; i < MT753X_NUM_PHYS; i++) { -+ phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); -+ phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); -+ phy_val &= ~BMCR_PDOWN; -+ mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); -+ } -+ -+ mt7531_phy_setting(priv); -+ -+ /* Enable Internal PHYs */ -+ val = mt7531_core_reg_read(priv, CORE_PLL_GROUP4); -+ val |= MT7531_BYPASS_MODE; -+ val &= ~MT7531_POWER_ON_OFF; -+ mt7531_core_reg_write(priv, CORE_PLL_GROUP4, val); -+ -+ return mt7531_mdio_register(priv); -+} -+ -+static int mt7531_cleanup(struct mtk_eth_switch_priv *swpriv) -+{ -+ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; -+ -+ mdio_unregister(priv->mdio_bus); -+ -+ return 0; -+} -+ -+static int mt7531_detect(struct mtk_eth_priv *priv) -+{ -+ int ret; -+ u32 rev; -+ -+ ret = __mt753x_mdio_reg_read(priv, MT753X_DFL_SMI_ADDR, CHIP_REV, &rev); -+ if (ret) -+ return ret; -+ -+ if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == 0x7531) -+ return 0; -+ -+ return -ENODEV; -+} -+ -+MTK_ETH_SWITCH(mt7531) = { -+ .name = "mt7531", -+ .desc = "MediaTek MT7531", -+ .priv_size = sizeof(struct mt753x_switch_priv), -+ .reset_wait_time = 200, -+ -+ .detect = mt7531_detect, -+ .setup = mt7531_setup, -+ .cleanup = mt7531_cleanup, -+ .mac_control = mt7531_mac_control, -+}; ---- /dev/null -+++ b/drivers/net/mtk_eth/mt753x.c -@@ -0,0 +1,262 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2025 MediaTek Inc. -+ * -+ * Author: Weijie Gao -+ * Author: Mark Lee -+ */ -+ -+#include -+#include -+#include "mtk_eth.h" -+#include "mt753x.h" -+ -+/* -+ * MT753x Internal Register Address Bits -+ * ------------------------------------------------------------------- -+ * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 | -+ * |----------------------------------------|---------------|--------| -+ * | Page Address | Reg Address | Unused | -+ * ------------------------------------------------------------------- -+ */ -+ -+int __mt753x_mdio_reg_read(struct mtk_eth_priv *priv, u32 smi_addr, u32 reg, -+ u32 *data) -+{ -+ int ret, low_word, high_word; -+ -+ /* Write page address */ -+ ret = mtk_mii_write(priv, smi_addr, 0x1f, reg >> 6); -+ if (ret) -+ return ret; -+ -+ /* Read low word */ -+ low_word = mtk_mii_read(priv, smi_addr, (reg >> 2) & 0xf); -+ if (low_word < 0) -+ return low_word; -+ -+ /* Read high word */ -+ high_word = mtk_mii_read(priv, smi_addr, 0x10); -+ if (high_word < 0) -+ return high_word; -+ -+ if (data) -+ *data = ((u32)high_word << 16) | (low_word & 0xffff); -+ -+ return 0; -+} -+ -+int mt753x_mdio_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data) -+{ -+ return __mt753x_mdio_reg_read(priv->epriv.eth, priv->smi_addr, reg, -+ data); -+} -+ -+int mt753x_mdio_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data) -+{ -+ int ret; -+ -+ /* Write page address */ -+ ret = mtk_mii_write(priv->epriv.eth, priv->smi_addr, 0x1f, reg >> 6); -+ if (ret) -+ return ret; -+ -+ /* Write low word */ -+ ret = mtk_mii_write(priv->epriv.eth, priv->smi_addr, (reg >> 2) & 0xf, -+ data & 0xffff); -+ if (ret) -+ return ret; -+ -+ /* Write high word */ -+ return mtk_mii_write(priv->epriv.eth, priv->smi_addr, 0x10, data >> 16); -+} -+ -+int mt753x_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data) -+{ -+ return priv->reg_read(priv, reg, data); -+} -+ -+int mt753x_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data) -+{ -+ return priv->reg_write(priv, reg, data); -+} -+ -+void mt753x_reg_rmw(struct mt753x_switch_priv *priv, u32 reg, u32 clr, u32 set) -+{ -+ u32 val; -+ -+ priv->reg_read(priv, reg, &val); -+ val &= ~clr; -+ val |= set; -+ priv->reg_write(priv, reg, val); -+} -+ -+/* Indirect MDIO clause 22/45 access */ -+static int mt7531_mii_rw(struct mt753x_switch_priv *priv, int phy, int reg, -+ u16 data, u32 cmd, u32 st) -+{ -+ u32 val, timeout_ms; -+ ulong timeout; -+ int ret = 0; -+ -+ val = (st << MDIO_ST_S) | -+ ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | -+ ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | -+ ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); -+ -+ if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) -+ val |= data & MDIO_RW_DATA_M; -+ -+ mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST); -+ -+ timeout_ms = 100; -+ timeout = get_timer(0); -+ while (1) { -+ mt753x_reg_read(priv, MT7531_PHY_IAC, &val); -+ -+ if ((val & PHY_ACS_ST) == 0) -+ break; -+ -+ if (get_timer(timeout) > timeout_ms) -+ return -ETIMEDOUT; -+ } -+ -+ if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { -+ mt753x_reg_read(priv, MT7531_PHY_IAC, &val); -+ ret = val & MDIO_RW_DATA_M; -+ } -+ -+ return ret; -+} -+ -+int mt7531_mii_read(struct mt753x_switch_priv *priv, u8 phy, u8 reg) -+{ -+ u8 phy_addr; -+ -+ if (phy >= MT753X_NUM_PHYS) -+ return -EINVAL; -+ -+ phy_addr = MT753X_PHY_ADDR(priv->phy_base, phy); -+ -+ return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ, -+ MDIO_ST_C22); -+} -+ -+int mt7531_mii_write(struct mt753x_switch_priv *priv, u8 phy, u8 reg, u16 val) -+{ -+ u8 phy_addr; -+ -+ if (phy >= MT753X_NUM_PHYS) -+ return -EINVAL; -+ -+ phy_addr = MT753X_PHY_ADDR(priv->phy_base, phy); -+ -+ return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE, -+ MDIO_ST_C22); -+} -+ -+int mt7531_mmd_read(struct mt753x_switch_priv *priv, u8 addr, u8 devad, -+ u16 reg) -+{ -+ u8 phy_addr; -+ int ret; -+ -+ if (addr >= MT753X_NUM_PHYS) -+ return -EINVAL; -+ -+ phy_addr = MT753X_PHY_ADDR(priv->phy_base, addr); -+ -+ ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, -+ MDIO_ST_C45); -+ if (ret) -+ return ret; -+ -+ return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45, -+ MDIO_ST_C45); -+} -+ -+int mt7531_mmd_write(struct mt753x_switch_priv *priv, u8 addr, u8 devad, -+ u16 reg, u16 val) -+{ -+ u8 phy_addr; -+ int ret; -+ -+ if (addr >= MT753X_NUM_PHYS) -+ return 0; -+ -+ phy_addr = MT753X_PHY_ADDR(priv->phy_base, addr); -+ -+ ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, -+ MDIO_ST_C45); -+ if (ret) -+ return ret; -+ -+ return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE, -+ MDIO_ST_C45); -+} -+ -+static int mt7531_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) -+{ -+ struct mt753x_switch_priv *priv = bus->priv; -+ -+ if (devad < 0) -+ return mt7531_mii_read(priv, addr, reg); -+ -+ return mt7531_mmd_read(priv, addr, devad, reg); -+} -+ -+static int mt7531_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, -+ u16 val) -+{ -+ struct mt753x_switch_priv *priv = bus->priv; -+ -+ if (devad < 0) -+ return mt7531_mii_write(priv, addr, reg, val); -+ -+ return mt7531_mmd_write(priv, addr, devad, reg, val); -+} -+ -+int mt7531_mdio_register(struct mt753x_switch_priv *priv) -+{ -+ struct mii_dev *mdio_bus = mdio_alloc(); -+ int ret; -+ -+ if (!mdio_bus) -+ return -ENOMEM; -+ -+ mdio_bus->read = mt7531_mdio_read; -+ mdio_bus->write = mt7531_mdio_write; -+ snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name); -+ -+ mdio_bus->priv = priv; -+ -+ ret = mdio_register(mdio_bus); -+ if (ret) { -+ mdio_free(mdio_bus); -+ return ret; -+ } -+ -+ priv->mdio_bus = mdio_bus; -+ -+ return 0; -+} -+ -+void mt753x_port_isolation(struct mt753x_switch_priv *priv) -+{ -+ u32 i; -+ -+ for (i = 0; i < MT753X_NUM_PORTS; i++) { -+ /* Set port matrix mode */ -+ if (i != 6) -+ mt753x_reg_write(priv, PCR_REG(i), -+ (0x40 << PORT_MATRIX_S)); -+ else -+ mt753x_reg_write(priv, PCR_REG(i), -+ (0x3f << PORT_MATRIX_S)); -+ -+ /* Set port mode to user port */ -+ mt753x_reg_write(priv, PVC_REG(i), -+ (0x8100 << STAG_VPID_S) | -+ (VLAN_ATTR_USER << VLAN_ATTR_S)); -+ } -+} ---- /dev/null -+++ b/drivers/net/mtk_eth/mt753x.h -@@ -0,0 +1,286 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2025 MediaTek Inc. -+ * -+ * Author: Weijie Gao -+ * Author: Mark Lee -+ */ -+ -+#ifndef _MTK_ETH_MT753X_H_ -+#define _MTK_ETH_MT753X_H_ -+ -+#include -+#include -+#include -+#include -+ -+struct mtk_eth_priv; -+ -+#define MT753X_NUM_PHYS 5 -+#define MT753X_NUM_PORTS 7 -+#define MT753X_DFL_SMI_ADDR 31 -+#define MT753X_SMI_ADDR_MASK 0x1f -+ -+#define MT753X_PHY_ADDR(base, addr) \ -+ (((base) + (addr)) & 0x1f) -+ -+/* MT7530 Registers */ -+#define PCR_REG(p) (0x2004 + (p) * 0x100) -+#define PORT_MATRIX_S 16 -+#define PORT_MATRIX_M 0xff0000 -+ -+#define PVC_REG(p) (0x2010 + (p) * 0x100) -+#define STAG_VPID_S 16 -+#define STAG_VPID_M 0xffff0000 -+#define VLAN_ATTR_S 6 -+#define VLAN_ATTR_M 0xc0 -+ -+/* VLAN_ATTR: VLAN attributes */ -+#define VLAN_ATTR_USER 0 -+#define VLAN_ATTR_STACK 1 -+#define VLAN_ATTR_TRANSLATION 2 -+#define VLAN_ATTR_TRANSPARENT 3 -+ -+#define PMCR_REG(p) (0x3000 + (p) * 0x100) -+/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR -+ * MT7531 specific fields are defined below -+ */ -+#define FORCE_MODE_EEE1G BIT(25) -+#define FORCE_MODE_EEE100 BIT(26) -+#define FORCE_MODE_TX_FC BIT(27) -+#define FORCE_MODE_RX_FC BIT(28) -+#define FORCE_MODE_DPX BIT(29) -+#define FORCE_MODE_SPD BIT(30) -+#define FORCE_MODE_LNK BIT(31) -+#define MT7531_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ -+ FORCE_MODE_DPX | FORCE_MODE_SPD | \ -+ FORCE_MODE_LNK -+#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ -+ FORCE_MODE_DPX | FORCE_MODE_SPD | \ -+ FORCE_MODE_LNK -+ -+/* MT7531 SGMII Registers */ -+#define MT7531_SGMII_REG_BASE 0x5000 -+#define MT7531_SGMII_REG_PORT_BASE 0x1000 -+#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ -+ (p) * MT7531_SGMII_REG_PORT_BASE + (r)) -+#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00) -+#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20) -+#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8) -+#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128) -+#define MT7531_PHYA_ANA_SYSPLL(p) MT7531_SGMII_REG(((p) - 5), 0x158) -+/* XXX: all fields of MT7531 SGMII are defined under SGMSYS */ -+ -+/* MT753x System Control Register */ -+#define SYS_CTRL_REG 0x7000 -+#define SW_PHY_RST BIT(2) -+#define SW_SYS_RST BIT(1) -+#define SW_REG_RST BIT(0) -+ -+/* MT7531 */ -+#define MT7531_PHY_IAC 0x701c -+/* XXX: all fields are defined under GMAC_PIAC_REG */ -+ -+#define MT7531_CLKGEN_CTRL 0x7500 -+#define CLK_SKEW_OUT_S 8 -+#define CLK_SKEW_OUT_M 0x300 -+#define CLK_SKEW_IN_S 6 -+#define CLK_SKEW_IN_M 0xc0 -+#define RXCLK_NO_DELAY BIT(5) -+#define TXCLK_NO_REVERSE BIT(4) -+#define GP_MODE_S 1 -+#define GP_MODE_M 0x06 -+#define GP_CLK_EN BIT(0) -+ -+/* Values of GP_MODE */ -+#define GP_MODE_RGMII 0 -+#define GP_MODE_MII 1 -+#define GP_MODE_REV_MII 2 -+ -+/* Values of CLK_SKEW_IN */ -+#define CLK_SKEW_IN_NO_CHANGE 0 -+#define CLK_SKEW_IN_DELAY_100PPS 1 -+#define CLK_SKEW_IN_DELAY_200PPS 2 -+#define CLK_SKEW_IN_REVERSE 3 -+ -+/* Values of CLK_SKEW_OUT */ -+#define CLK_SKEW_OUT_NO_CHANGE 0 -+#define CLK_SKEW_OUT_DELAY_100PPS 1 -+#define CLK_SKEW_OUT_DELAY_200PPS 2 -+#define CLK_SKEW_OUT_REVERSE 3 -+ -+#define HWTRAP_REG 0x7800 -+/* MT7530 Modified Hardware Trap Status Registers */ -+#define MHWTRAP_REG 0x7804 -+#define CHG_TRAP BIT(16) -+#define LOOPDET_DIS BIT(14) -+#define P5_INTF_SEL_S 13 -+#define P5_INTF_SEL_M 0x2000 -+#define SMI_ADDR_S 11 -+#define SMI_ADDR_M 0x1800 -+#define XTAL_FSEL_S 9 -+#define XTAL_FSEL_M 0x600 -+#define P6_INTF_DIS BIT(8) -+#define P5_INTF_MODE_S 7 -+#define P5_INTF_MODE_M 0x80 -+#define P5_INTF_DIS BIT(6) -+#define C_MDIO_BPS BIT(5) -+#define CHIP_MODE_S 0 -+#define CHIP_MODE_M 0x0f -+ -+/* P5_INTF_SEL: Interface type of Port5 */ -+#define P5_INTF_SEL_GPHY 0 -+#define P5_INTF_SEL_GMAC5 1 -+ -+/* P5_INTF_MODE: Interface mode of Port5 */ -+#define P5_INTF_MODE_GMII_MII 0 -+#define P5_INTF_MODE_RGMII 1 -+ -+#define MT7530_P6ECR 0x7830 -+#define P6_INTF_MODE_M 0x3 -+#define P6_INTF_MODE_S 0 -+ -+/* P6_INTF_MODE: Interface mode of Port6 */ -+#define P6_INTF_MODE_RGMII 0 -+#define P6_INTF_MODE_TRGMII 1 -+ -+#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8) -+#define RD_TAP_S 0 -+#define RD_TAP_M 0x7f -+ -+#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8) -+/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */ -+ -+/* TOP Signals Status Register */ -+#define MT7531_TOP_SIG_SR 0x780c -+#define PAD_MCM_SMI_EN BIT(0) -+#define PAD_DUAL_SGMII_EN BIT(1) -+ -+/* MT7531 PLLGP Registers */ -+#define MT7531_PLLGP_EN 0x7820 -+#define EN_COREPLL BIT(2) -+#define SW_CLKSW BIT(1) -+#define SW_PLLGP BIT(0) -+ -+#define MT7531_PLLGP_CR0 0x78a8 -+#define RG_COREPLL_EN BIT(22) -+#define RG_COREPLL_POSDIV_S 23 -+#define RG_COREPLL_POSDIV_M 0x3800000 -+#define RG_COREPLL_SDM_PCW_S 1 -+#define RG_COREPLL_SDM_PCW_M 0x3ffffe -+#define RG_COREPLL_SDM_PCW_CHG BIT(0) -+ -+/* MT7531 RGMII and SGMII PLL clock */ -+#define MT7531_ANA_PLLGP_CR2 0x78b0 -+#define MT7531_ANA_PLLGP_CR5 0x78bc -+ -+/* MT7531 GPIO GROUP IOLB SMT0 Control */ -+#define MT7531_SMT0_IOLB 0x7f04 -+#define SMT_IOLB_5_SMI_MDC_EN BIT(5) -+ -+/* MT7530 GPHY MDIO MMD Registers */ -+#define CORE_PLL_GROUP2 0x401 -+#define RG_SYSPLL_EN_NORMAL BIT(15) -+#define RG_SYSPLL_VODEN BIT(14) -+#define RG_SYSPLL_POSDIV_S 5 -+#define RG_SYSPLL_POSDIV_M 0x60 -+ -+#define CORE_PLL_GROUP4 0x403 -+#define MT7531_BYPASS_MODE BIT(4) -+#define MT7531_POWER_ON_OFF BIT(5) -+#define RG_SYSPLL_DDSFBK_EN BIT(12) -+#define RG_SYSPLL_BIAS_EN BIT(11) -+#define RG_SYSPLL_BIAS_LPF_EN BIT(10) -+ -+#define CORE_PLL_GROUP5 0x404 -+#define RG_LCDDS_PCW_NCPO1_S 0 -+#define RG_LCDDS_PCW_NCPO1_M 0xffff -+ -+#define CORE_PLL_GROUP6 0x405 -+#define RG_LCDDS_PCW_NCPO0_S 0 -+#define RG_LCDDS_PCW_NCPO0_M 0xffff -+ -+#define CORE_PLL_GROUP7 0x406 -+#define RG_LCDDS_PWDB BIT(15) -+#define RG_LCDDS_ISO_EN BIT(13) -+#define RG_LCCDS_C_S 4 -+#define RG_LCCDS_C_M 0x70 -+#define RG_LCDDS_PCW_NCPO_CHG BIT(3) -+ -+#define CORE_PLL_GROUP10 0x409 -+#define RG_LCDDS_SSC_DELTA_S 0 -+#define RG_LCDDS_SSC_DELTA_M 0xfff -+ -+#define CORE_PLL_GROUP11 0x40a -+#define RG_LCDDS_SSC_DELTA1_S 0 -+#define RG_LCDDS_SSC_DELTA1_M 0xfff -+ -+#define CORE_GSWPLL_GRP1 0x40d -+#define RG_GSWPLL_POSDIV_200M_S 12 -+#define RG_GSWPLL_POSDIV_200M_M 0x3000 -+#define RG_GSWPLL_EN_PRE BIT(11) -+#define RG_GSWPLL_FBKDIV_200M_S 0 -+#define RG_GSWPLL_FBKDIV_200M_M 0xff -+ -+#define CORE_GSWPLL_GRP2 0x40e -+#define RG_GSWPLL_POSDIV_500M_S 8 -+#define RG_GSWPLL_POSDIV_500M_M 0x300 -+#define RG_GSWPLL_FBKDIV_500M_S 0 -+#define RG_GSWPLL_FBKDIV_500M_M 0xff -+ -+#define CORE_TRGMII_GSW_CLK_CG 0x410 -+#define REG_GSWCK_EN BIT(0) -+#define REG_TRGMIICK_EN BIT(1) -+ -+/* Extend PHY Control Register 3 */ -+#define PHY_EXT_REG_14 0x14 -+ -+/* Fields of PHY_EXT_REG_14 */ -+#define PHY_EN_DOWN_SHFIT BIT(4) -+ -+/* Extend PHY Control Register 4 */ -+#define PHY_EXT_REG_17 0x17 -+ -+/* Fields of PHY_EXT_REG_17 */ -+#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4) -+ -+/* PHY RXADC Control Register 7 */ -+#define PHY_DEV1E_REG_0C6 0x0c6 -+ -+/* Fields of PHY_DEV1E_REG_0C6 */ -+#define PHY_POWER_SAVING_S 8 -+#define PHY_POWER_SAVING_M 0x300 -+#define PHY_POWER_SAVING_TX 0x0 -+ -+struct mt753x_switch_priv { -+ struct mtk_eth_switch_priv epriv; -+ struct mii_dev *mdio_bus; -+ u32 smi_addr; -+ u32 phy_base; -+ u32 pmcr; -+ -+ int (*reg_read)(struct mt753x_switch_priv *priv, u32 reg, u32 *data); -+ int (*reg_write)(struct mt753x_switch_priv *priv, u32 reg, u32 data); -+}; -+ -+int __mt753x_mdio_reg_read(struct mtk_eth_priv *priv, u32 smi_addr, u32 reg, -+ u32 *data); -+int mt753x_mdio_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data); -+int mt753x_mdio_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data); -+ -+int mt753x_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data); -+int mt753x_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data); -+void mt753x_reg_rmw(struct mt753x_switch_priv *priv, u32 reg, u32 clr, u32 set); -+ -+int mt7531_mii_read(struct mt753x_switch_priv *priv, u8 phy, u8 reg); -+int mt7531_mii_write(struct mt753x_switch_priv *priv, u8 phy, u8 reg, u16 val); -+int mt7531_mmd_read(struct mt753x_switch_priv *priv, u8 addr, u8 devad, -+ u16 reg); -+int mt7531_mmd_write(struct mt753x_switch_priv *priv, u8 addr, u8 devad, -+ u16 reg, u16 val); -+ -+int mt7531_mdio_register(struct mt753x_switch_priv *priv); -+ -+void mt753x_port_isolation(struct mt753x_switch_priv *priv); -+ -+#endif /* _MTK_ETH_MT753X_H_ */ ---- /dev/null -+++ b/drivers/net/mtk_eth/mt7988.c -@@ -0,0 +1,160 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2025 MediaTek Inc. -+ * -+ * Author: Weijie Gao -+ * Author: Mark Lee -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "mtk_eth.h" -+#include "mt753x.h" -+ -+static int mt7988_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data) -+{ -+ *data = readl(priv->epriv.ethsys_base + GSW_BASE + reg); -+ -+ return 0; -+} -+ -+static int mt7988_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data) -+{ -+ writel(data, priv->epriv.ethsys_base + GSW_BASE + reg); -+ -+ return 0; -+} -+ -+static void mt7988_phy_setting(struct mt753x_switch_priv *priv) -+{ -+ u16 val; -+ u32 i; -+ -+ for (i = 0; i < MT753X_NUM_PHYS; i++) { -+ /* Enable HW auto downshift */ -+ mt7531_mii_write(priv, i, 0x1f, 0x1); -+ val = mt7531_mii_read(priv, i, PHY_EXT_REG_14); -+ val |= PHY_EN_DOWN_SHFIT; -+ mt7531_mii_write(priv, i, PHY_EXT_REG_14, val); -+ -+ /* PHY link down power saving enable */ -+ val = mt7531_mii_read(priv, i, PHY_EXT_REG_17); -+ val |= PHY_LINKDOWN_POWER_SAVING_EN; -+ mt7531_mii_write(priv, i, PHY_EXT_REG_17, val); -+ } -+} -+ -+static void mt7988_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) -+{ -+ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; -+ u32 pmcr = FORCE_MODE_LNK; -+ -+ if (enable) -+ pmcr = priv->pmcr; -+ -+ mt7988_reg_write(priv, PMCR_REG(6), pmcr); -+} -+ -+static int mt7988_setup(struct mtk_eth_switch_priv *swpriv) -+{ -+ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; -+ u16 phy_addr, phy_val; -+ u32 pmcr; -+ int i; -+ -+ priv->smi_addr = MT753X_DFL_SMI_ADDR; -+ priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK; -+ priv->reg_read = mt7988_reg_read; -+ priv->reg_write = mt7988_reg_write; -+ -+ /* Turn off PHYs */ -+ for (i = 0; i < MT753X_NUM_PHYS; i++) { -+ phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); -+ phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); -+ phy_val |= BMCR_PDOWN; -+ mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); -+ } -+ -+ switch (priv->epriv.phy_interface) { -+ case PHY_INTERFACE_MODE_USXGMII: -+ /* Use CPU bridge instead of actual USXGMII path */ -+ -+ /* Disable GDM1 RX CRC stripping */ -+ /* mtk_fe_rmw(priv, 0x500, BIT(16), 0); */ -+ -+ /* Set GDM1 no drop */ -+ mtk_fe_rmw(priv->epriv.eth, PSE_NO_DROP_CFG_REG, 0, -+ PSE_NO_DROP_GDM1); -+ -+ /* Enable GSW CPU bridge as USXGMII */ -+ /* mtk_fe_rmw(priv, 0x504, BIT(31), BIT(31)); */ -+ -+ /* Enable GDM1 to GSW CPU bridge */ -+ mtk_gmac_rmw(priv->epriv.eth, GMAC_MAC_MISC_REG, 0, BIT(0)); -+ -+ /* XGMAC force link up */ -+ mtk_gmac_rmw(priv->epriv.eth, GMAC_XGMAC_STS_REG, 0, -+ P1_XGMAC_FORCE_LINK); -+ -+ /* Setup GSW CPU bridge IPG */ -+ mtk_gmac_rmw(priv->epriv.eth, GMAC_GSW_CFG_REG, -+ GSWTX_IPG_M | GSWRX_IPG_M, -+ (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S)); -+ break; -+ default: -+ printf("Error: MT7988 GSW does not support %s interface\n", -+ phy_string_for_interface(priv->epriv.phy_interface)); -+ break; -+ } -+ -+ pmcr = MT7988_FORCE_MODE | -+ (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | -+ MAC_MODE | MAC_TX_EN | MAC_RX_EN | -+ BKOFF_EN | BACKPR_EN | -+ FORCE_RX_FC | FORCE_TX_FC | -+ (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | -+ FORCE_LINK; -+ -+ priv->pmcr = pmcr; -+ -+ /* Keep MAC link down before starting eth */ -+ mt7988_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); -+ -+ /* Enable port isolation to block inter-port communication */ -+ mt753x_port_isolation(priv); -+ -+ /* Turn on PHYs */ -+ for (i = 0; i < MT753X_NUM_PHYS; i++) { -+ phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); -+ phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); -+ phy_val &= ~BMCR_PDOWN; -+ mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); -+ } -+ -+ mt7988_phy_setting(priv); -+ -+ return mt7531_mdio_register(priv); -+} -+ -+static int mt7531_cleanup(struct mtk_eth_switch_priv *swpriv) -+{ -+ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; -+ -+ mdio_unregister(priv->mdio_bus); -+ -+ return 0; -+} -+ -+MTK_ETH_SWITCH(mt7988) = { -+ .name = "mt7988", -+ .desc = "MediaTek MT7988 built-in switch", -+ .priv_size = sizeof(struct mt753x_switch_priv), -+ .reset_wait_time = 50, -+ -+ .setup = mt7988_setup, -+ .cleanup = mt7531_cleanup, -+ .mac_control = mt7988_mac_control, -+}; ---- a/drivers/net/mtk_eth.c -+++ /dev/null -@@ -1,2280 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0 --/* -- * Copyright (C) 2018 MediaTek Inc. -- * -- * Author: Weijie Gao -- * Author: Mark Lee -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include -- --#include "mtk_eth.h" -- --#define NUM_TX_DESC 32 --#define NUM_RX_DESC 32 --#define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN) --#define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) --#define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) -- --#define MT753X_NUM_PHYS 5 --#define MT753X_NUM_PORTS 7 --#define MT753X_DFL_SMI_ADDR 31 --#define MT753X_SMI_ADDR_MASK 0x1f -- --#define MT753X_PHY_ADDR(base, addr) \ -- (((base) + (addr)) & 0x1f) -- --#define GDMA_FWD_TO_CPU \ -- (0x20000000 | \ -- GDM_ICS_EN | \ -- GDM_TCS_EN | \ -- GDM_UCS_EN | \ -- STRP_CRC | \ -- (DP_PDMA << MYMAC_DP_S) | \ -- (DP_PDMA << BC_DP_S) | \ -- (DP_PDMA << MC_DP_S) | \ -- (DP_PDMA << UN_DP_S)) -- --#define GDMA_BRIDGE_TO_CPU \ -- (0xC0000000 | \ -- GDM_ICS_EN | \ -- GDM_TCS_EN | \ -- GDM_UCS_EN | \ -- (DP_PDMA << MYMAC_DP_S) | \ -- (DP_PDMA << BC_DP_S) | \ -- (DP_PDMA << MC_DP_S) | \ -- (DP_PDMA << UN_DP_S)) -- --#define GDMA_FWD_DISCARD \ -- (0x20000000 | \ -- GDM_ICS_EN | \ -- GDM_TCS_EN | \ -- GDM_UCS_EN | \ -- STRP_CRC | \ -- (DP_DISCARD << MYMAC_DP_S) | \ -- (DP_DISCARD << BC_DP_S) | \ -- (DP_DISCARD << MC_DP_S) | \ -- (DP_DISCARD << UN_DP_S)) -- --enum mtk_switch { -- SW_NONE, -- SW_MT7530, -- SW_MT7531, -- SW_MT7988, --}; -- --/* struct mtk_soc_data - This is the structure holding all differences -- * among various plaforms -- * @caps Flags shown the extra capability for the SoC -- * @ana_rgc3: The offset for register ANA_RGC3 related to -- * sgmiisys syscon -- * @gdma_count: Number of GDMAs -- * @pdma_base: Register base of PDMA block -- * @txd_size: Tx DMA descriptor size. -- * @rxd_size: Rx DMA descriptor size. -- */ --struct mtk_soc_data { -- u32 caps; -- u32 ana_rgc3; -- u32 gdma_count; -- u32 pdma_base; -- u32 txd_size; -- u32 rxd_size; --}; -- --struct mtk_eth_priv { -- char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); -- -- void *tx_ring_noc; -- void *rx_ring_noc; -- -- int rx_dma_owner_idx0; -- int tx_cpu_owner_idx0; -- -- void __iomem *fe_base; -- void __iomem *gmac_base; -- void __iomem *sgmii_base; -- void __iomem *gsw_base; -- -- struct regmap *ethsys_regmap; -- -- struct regmap *infra_regmap; -- -- struct regmap *usxgmii_regmap; -- struct regmap *xfi_pextp_regmap; -- struct regmap *xfi_pll_regmap; -- struct regmap *toprgu_regmap; -- -- struct mii_dev *mdio_bus; -- int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg); -- int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val); -- int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); -- int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, -- u16 val); -- -- const struct mtk_soc_data *soc; -- int gmac_id; -- int force_mode; -- int speed; -- int duplex; -- int mdc; -- bool pn_swap; -- -- struct phy_device *phydev; -- int phy_interface; -- int phy_addr; -- -- enum mtk_switch sw; -- int (*switch_init)(struct mtk_eth_priv *priv); -- void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable); -- u32 mt753x_smi_addr; -- u32 mt753x_phy_base; -- u32 mt753x_pmcr; -- u32 mt753x_reset_wait_time; -- -- struct gpio_desc rst_gpio; -- int mcm; -- -- struct reset_ctl rst_fe; -- struct reset_ctl rst_mcm; --}; -- --static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val) --{ -- writel(val, priv->fe_base + priv->soc->pdma_base + reg); --} -- --static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, -- u32 set) --{ -- clrsetbits_le32(priv->fe_base + priv->soc->pdma_base + reg, clr, set); --} -- --static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg, -- u32 val) --{ -- u32 gdma_base; -- -- if (no == 2) -- gdma_base = GDMA3_BASE; -- else if (no == 1) -- gdma_base = GDMA2_BASE; -- else -- gdma_base = GDMA1_BASE; -- -- writel(val, priv->fe_base + gdma_base + reg); --} -- --static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) --{ -- clrsetbits_le32(priv->fe_base + reg, clr, set); --} -- --static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg) --{ -- return readl(priv->gmac_base + reg); --} -- --static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val) --{ -- writel(val, priv->gmac_base + reg); --} -- --static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) --{ -- clrsetbits_le32(priv->gmac_base + reg, clr, set); --} -- --static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, -- u32 set) --{ -- uint val; -- -- regmap_read(priv->ethsys_regmap, reg, &val); -- val &= ~clr; -- val |= set; -- regmap_write(priv->ethsys_regmap, reg, val); --} -- --static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, -- u32 set) --{ -- uint val; -- -- regmap_read(priv->infra_regmap, reg, &val); -- val &= ~clr; -- val |= set; -- regmap_write(priv->infra_regmap, reg, val); --} -- --static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg) --{ -- return readl(priv->gsw_base + reg); --} -- --static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val) --{ -- writel(val, priv->gsw_base + reg); --} -- --/* Direct MDIO clause 22/45 access via SoC */ --static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, -- u32 cmd, u32 st) --{ -- int ret; -- u32 val; -- -- val = (st << MDIO_ST_S) | -- ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | -- (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | -- (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); -- -- if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) -- val |= data & MDIO_RW_DATA_M; -- -- mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST); -- -- ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG, -- PHY_ACS_ST, 0, 5000, 0); -- if (ret) { -- pr_warn("MDIO access timeout\n"); -- return ret; -- } -- -- if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { -- val = mtk_gmac_read(priv, GMAC_PIAC_REG); -- return val & MDIO_RW_DATA_M; -- } -- -- return 0; --} -- --/* Direct MDIO clause 22 read via SoC */ --static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) --{ -- return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22); --} -- --/* Direct MDIO clause 22 write via SoC */ --static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data) --{ -- return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22); --} -- --/* Direct MDIO clause 45 read via SoC */ --static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) --{ -- int ret; -- -- ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); -- if (ret) -- return ret; -- -- return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45, -- MDIO_ST_C45); --} -- --/* Direct MDIO clause 45 write via SoC */ --static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, -- u16 reg, u16 val) --{ -- int ret; -- -- ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); -- if (ret) -- return ret; -- -- return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE, -- MDIO_ST_C45); --} -- --/* Indirect MDIO clause 45 read via MII registers */ --static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, -- u16 reg) --{ -- int ret; -- -- ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, -- (MMD_ADDR << MMD_CMD_S) | -- ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); -- if (ret) -- return ret; -- -- ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); -- if (ret) -- return ret; -- -- ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, -- (MMD_DATA << MMD_CMD_S) | -- ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); -- if (ret) -- return ret; -- -- return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG); --} -- --/* Indirect MDIO clause 45 write via MII registers */ --static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, -- u16 reg, u16 val) --{ -- int ret; -- -- ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, -- (MMD_ADDR << MMD_CMD_S) | -- ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); -- if (ret) -- return ret; -- -- ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); -- if (ret) -- return ret; -- -- ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, -- (MMD_DATA << MMD_CMD_S) | -- ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); -- if (ret) -- return ret; -- -- return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val); --} -- --/* -- * MT7530 Internal Register Address Bits -- * ------------------------------------------------------------------- -- * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 | -- * |----------------------------------------|---------------|--------| -- * | Page Address | Reg Address | Unused | -- * ------------------------------------------------------------------- -- */ -- --static int mt753x_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data) --{ -- int ret, low_word, high_word; -- -- if (priv->sw == SW_MT7988) { -- *data = mtk_gsw_read(priv, reg); -- return 0; -- } -- -- /* Write page address */ -- ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); -- if (ret) -- return ret; -- -- /* Read low word */ -- low_word = mtk_mii_read(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf); -- if (low_word < 0) -- return low_word; -- -- /* Read high word */ -- high_word = mtk_mii_read(priv, priv->mt753x_smi_addr, 0x10); -- if (high_word < 0) -- return high_word; -- -- if (data) -- *data = ((u32)high_word << 16) | (low_word & 0xffff); -- -- return 0; --} -- --static int mt753x_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data) --{ -- int ret; -- -- if (priv->sw == SW_MT7988) { -- mtk_gsw_write(priv, reg, data); -- return 0; -- } -- -- /* Write page address */ -- ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); -- if (ret) -- return ret; -- -- /* Write low word */ -- ret = mtk_mii_write(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf, -- data & 0xffff); -- if (ret) -- return ret; -- -- /* Write high word */ -- return mtk_mii_write(priv, priv->mt753x_smi_addr, 0x10, data >> 16); --} -- --static void mt753x_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, -- u32 set) --{ -- u32 val; -- -- mt753x_reg_read(priv, reg, &val); -- val &= ~clr; -- val |= set; -- mt753x_reg_write(priv, reg, val); --} -- --/* Indirect MDIO clause 22/45 access */ --static int mt7531_mii_rw(struct mtk_eth_priv *priv, int phy, int reg, u16 data, -- u32 cmd, u32 st) --{ -- ulong timeout; -- u32 val, timeout_ms; -- int ret = 0; -- -- val = (st << MDIO_ST_S) | -- ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | -- ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | -- ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); -- -- if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) -- val |= data & MDIO_RW_DATA_M; -- -- mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST); -- -- timeout_ms = 100; -- timeout = get_timer(0); -- while (1) { -- mt753x_reg_read(priv, MT7531_PHY_IAC, &val); -- -- if ((val & PHY_ACS_ST) == 0) -- break; -- -- if (get_timer(timeout) > timeout_ms) -- return -ETIMEDOUT; -- } -- -- if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { -- mt753x_reg_read(priv, MT7531_PHY_IAC, &val); -- ret = val & MDIO_RW_DATA_M; -- } -- -- return ret; --} -- --static int mt7531_mii_ind_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) --{ -- u8 phy_addr; -- -- if (phy >= MT753X_NUM_PHYS) -- return -EINVAL; -- -- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy); -- -- return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ, -- MDIO_ST_C22); --} -- --static int mt7531_mii_ind_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, -- u16 val) --{ -- u8 phy_addr; -- -- if (phy >= MT753X_NUM_PHYS) -- return -EINVAL; -- -- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy); -- -- return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE, -- MDIO_ST_C22); --} -- --static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, -- u16 reg) --{ -- u8 phy_addr; -- int ret; -- -- if (addr >= MT753X_NUM_PHYS) -- return -EINVAL; -- -- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr); -- -- ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, -- MDIO_ST_C45); -- if (ret) -- return ret; -- -- return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45, -- MDIO_ST_C45); --} -- --static int mt7531_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, -- u16 reg, u16 val) --{ -- u8 phy_addr; -- int ret; -- -- if (addr >= MT753X_NUM_PHYS) -- return 0; -- -- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr); -- -- ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, -- MDIO_ST_C45); -- if (ret) -- return ret; -- -- return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE, -- MDIO_ST_C45); --} -- --static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) --{ -- struct mtk_eth_priv *priv = bus->priv; -- -- if (devad < 0) -- return priv->mii_read(priv, addr, reg); -- else -- return priv->mmd_read(priv, addr, devad, reg); --} -- --static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, -- u16 val) --{ -- struct mtk_eth_priv *priv = bus->priv; -- -- if (devad < 0) -- return priv->mii_write(priv, addr, reg, val); -- else -- return priv->mmd_write(priv, addr, devad, reg, val); --} -- --static int mtk_mdio_register(struct udevice *dev) --{ -- struct mtk_eth_priv *priv = dev_get_priv(dev); -- struct mii_dev *mdio_bus = mdio_alloc(); -- int ret; -- -- if (!mdio_bus) -- return -ENOMEM; -- -- /* Assign MDIO access APIs according to the switch/phy */ -- switch (priv->sw) { -- case SW_MT7530: -- priv->mii_read = mtk_mii_read; -- priv->mii_write = mtk_mii_write; -- priv->mmd_read = mtk_mmd_ind_read; -- priv->mmd_write = mtk_mmd_ind_write; -- break; -- case SW_MT7531: -- case SW_MT7988: -- priv->mii_read = mt7531_mii_ind_read; -- priv->mii_write = mt7531_mii_ind_write; -- priv->mmd_read = mt7531_mmd_ind_read; -- priv->mmd_write = mt7531_mmd_ind_write; -- break; -- default: -- priv->mii_read = mtk_mii_read; -- priv->mii_write = mtk_mii_write; -- priv->mmd_read = mtk_mmd_read; -- priv->mmd_write = mtk_mmd_write; -- } -- -- mdio_bus->read = mtk_mdio_read; -- mdio_bus->write = mtk_mdio_write; -- snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name); -- -- mdio_bus->priv = (void *)priv; -- -- ret = mdio_register(mdio_bus); -- -- if (ret) -- return ret; -- -- priv->mdio_bus = mdio_bus; -- -- return 0; --} -- --static int mt753x_core_reg_read(struct mtk_eth_priv *priv, u32 reg) --{ -- u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0); -- -- return priv->mmd_read(priv, phy_addr, 0x1f, reg); --} -- --static void mt753x_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val) --{ -- u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0); -- -- priv->mmd_write(priv, phy_addr, 0x1f, reg, val); --} -- --static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode) --{ -- u32 ncpo1, ssc_delta; -- -- switch (mode) { -- case PHY_INTERFACE_MODE_RGMII: -- ncpo1 = 0x0c80; -- ssc_delta = 0x87; -- break; -- default: -- printf("error: xMII mode %d not supported\n", mode); -- return -EINVAL; -- } -- -- /* Disable MT7530 core clock */ -- mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0); -- -- /* Disable MT7530 PLL */ -- mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1, -- (2 << RG_GSWPLL_POSDIV_200M_S) | -- (32 << RG_GSWPLL_FBKDIV_200M_S)); -- -- /* For MT7530 core clock = 500Mhz */ -- mt753x_core_reg_write(priv, CORE_GSWPLL_GRP2, -- (1 << RG_GSWPLL_POSDIV_500M_S) | -- (25 << RG_GSWPLL_FBKDIV_500M_S)); -- -- /* Enable MT7530 PLL */ -- mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1, -- (2 << RG_GSWPLL_POSDIV_200M_S) | -- (32 << RG_GSWPLL_FBKDIV_200M_S) | -- RG_GSWPLL_EN_PRE); -- -- udelay(20); -- -- mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); -- -- /* Setup the MT7530 TRGMII Tx Clock */ -- mt753x_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1); -- mt753x_core_reg_write(priv, CORE_PLL_GROUP6, 0); -- mt753x_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta); -- mt753x_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta); -- mt753x_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | -- RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); -- -- mt753x_core_reg_write(priv, CORE_PLL_GROUP2, -- RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | -- (1 << RG_SYSPLL_POSDIV_S)); -- -- mt753x_core_reg_write(priv, CORE_PLL_GROUP7, -- RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) | -- RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); -- -- /* Enable MT7530 core clock */ -- mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, -- REG_GSWCK_EN | REG_TRGMIICK_EN); -- -- return 0; --} -- --static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable) --{ -- u32 pmcr = FORCE_MODE; -- -- if (enable) -- pmcr = priv->mt753x_pmcr; -- -- mt753x_reg_write(priv, PMCR_REG(6), pmcr); --} -- --static int mt7530_setup(struct mtk_eth_priv *priv) --{ -- u16 phy_addr, phy_val; -- u32 val, txdrv; -- int i; -- -- if (!MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) { -- /* Select 250MHz clk for RGMII mode */ -- mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG, -- ETHSYS_TRGMII_CLK_SEL362_5, 0); -- -- txdrv = 8; -- } else { -- txdrv = 4; -- } -- -- /* Modify HWTRAP first to allow direct access to internal PHYs */ -- mt753x_reg_read(priv, HWTRAP_REG, &val); -- val |= CHG_TRAP; -- val &= ~C_MDIO_BPS; -- mt753x_reg_write(priv, MHWTRAP_REG, val); -- -- /* Calculate the phy base address */ -- val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3; -- priv->mt753x_phy_base = (val | 0x7) + 1; -- -- /* Turn off PHYs */ -- for (i = 0; i < MT753X_NUM_PHYS; i++) { -- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); -- phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); -- phy_val |= BMCR_PDOWN; -- priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); -- } -- -- /* Force MAC link down before reset */ -- mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); -- mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); -- -- /* MT7530 reset */ -- mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); -- udelay(100); -- -- val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | -- MAC_MODE | FORCE_MODE | -- MAC_TX_EN | MAC_RX_EN | -- BKOFF_EN | BACKPR_EN | -- (SPEED_1000M << FORCE_SPD_S) | -- FORCE_DPX | FORCE_LINK; -- -- /* MT7530 Port6: Forced 1000M/FD, FC disabled */ -- priv->mt753x_pmcr = val; -- -- /* MT7530 Port5: Forced link down */ -- mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); -- -- /* Keep MAC link down before starting eth */ -- mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); -- -- /* MT7530 Port6: Set to RGMII */ -- mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII); -- -- /* Hardware Trap: Enable Port6, Disable Port5 */ -- mt753x_reg_read(priv, HWTRAP_REG, &val); -- val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS | -- (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) | -- (P5_INTF_MODE_RGMII << P5_INTF_MODE_S); -- val &= ~(C_MDIO_BPS | P6_INTF_DIS); -- mt753x_reg_write(priv, MHWTRAP_REG, val); -- -- /* Setup switch core pll */ -- mt7530_pad_clk_setup(priv, priv->phy_interface); -- -- /* Lower Tx Driving for TRGMII path */ -- for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) -- mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i), -- (txdrv << TD_DM_DRVP_S) | -- (txdrv << TD_DM_DRVN_S)); -- -- for (i = 0 ; i < NUM_TRGMII_CTRL; i++) -- mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16); -- -- /* Turn on PHYs */ -- for (i = 0; i < MT753X_NUM_PHYS; i++) { -- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); -- phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); -- phy_val &= ~BMCR_PDOWN; -- priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); -- } -- -- return 0; --} -- --static void mt7531_core_pll_setup(struct mtk_eth_priv *priv, int mcm) --{ -- /* Step 1 : Disable MT7531 COREPLL */ -- mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0); -- -- /* Step 2: switch to XTAL output */ -- mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW); -- -- mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0); -- -- /* Step 3: disable PLLGP and enable program PLLGP */ -- mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP); -- -- /* Step 4: program COREPLL output frequency to 500MHz */ -- mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M, -- 2 << RG_COREPLL_POSDIV_S); -- udelay(25); -- -- /* Currently, support XTAL 25Mhz only */ -- mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M, -- 0x140000 << RG_COREPLL_SDM_PCW_S); -- -- /* Set feedback divide ratio update signal to high */ -- mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, -- RG_COREPLL_SDM_PCW_CHG); -- -- /* Wait for at least 16 XTAL clocks */ -- udelay(10); -- -- /* Step 5: set feedback divide ratio update signal to low */ -- mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0); -- -- /* add enable 325M clock for SGMII */ -- mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); -- -- /* add enable 250SSC clock for RGMII */ -- mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); -- -- /*Step 6: Enable MT7531 PLL */ -- mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN); -- -- mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL); -- -- udelay(25); --} -- --static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv, -- u32 port) --{ -- if (port != 5 && port != 6) { -- printf("mt7531: port %d is not a SGMII port\n", port); -- return -EINVAL; -- } -- -- /* Set SGMII GEN2 speed(2.5G) */ -- mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, -- FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); -- -- /* Disable SGMII AN */ -- mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), -- SGMII_AN_ENABLE, 0); -- -- /* SGMII force mode setting */ -- mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE); -- -- /* Release PHYA power down state */ -- mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port), -- SGMII_PHYA_PWD, 0); -- -- return 0; --} -- --static int mt7531_port_rgmii_init(struct mtk_eth_priv *priv, u32 port) --{ -- u32 val; -- -- if (port != 5) { -- printf("error: RGMII mode is not available for port %d\n", -- port); -- return -EINVAL; -- } -- -- mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val); -- val |= GP_CLK_EN; -- val &= ~GP_MODE_M; -- val |= GP_MODE_RGMII << GP_MODE_S; -- val |= TXCLK_NO_REVERSE; -- val |= RXCLK_NO_DELAY; -- val &= ~CLK_SKEW_IN_M; -- val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S; -- val &= ~CLK_SKEW_OUT_M; -- val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S; -- mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val); -- -- return 0; --} -- --static void mt7531_phy_setting(struct mtk_eth_priv *priv) --{ -- int i; -- u32 val; -- -- for (i = 0; i < MT753X_NUM_PHYS; i++) { -- /* Enable HW auto downshift */ -- priv->mii_write(priv, i, 0x1f, 0x1); -- val = priv->mii_read(priv, i, PHY_EXT_REG_14); -- val |= PHY_EN_DOWN_SHFIT; -- priv->mii_write(priv, i, PHY_EXT_REG_14, val); -- -- /* PHY link down power saving enable */ -- val = priv->mii_read(priv, i, PHY_EXT_REG_17); -- val |= PHY_LINKDOWN_POWER_SAVING_EN; -- priv->mii_write(priv, i, PHY_EXT_REG_17, val); -- -- val = priv->mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6); -- val &= ~PHY_POWER_SAVING_M; -- val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S; -- priv->mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val); -- } --} -- --static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable) --{ -- u32 pmcr = FORCE_MODE_LNK; -- -- if (enable) -- pmcr = priv->mt753x_pmcr; -- -- mt753x_reg_write(priv, PMCR_REG(5), pmcr); -- mt753x_reg_write(priv, PMCR_REG(6), pmcr); --} -- --static int mt7531_setup(struct mtk_eth_priv *priv) --{ -- u16 phy_addr, phy_val; -- u32 val; -- u32 pmcr; -- u32 port5_sgmii; -- int i; -- -- priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) & -- MT753X_SMI_ADDR_MASK; -- -- /* Turn off PHYs */ -- for (i = 0; i < MT753X_NUM_PHYS; i++) { -- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); -- phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); -- phy_val |= BMCR_PDOWN; -- priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); -- } -- -- /* Force MAC link down before reset */ -- mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); -- mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); -- -- /* Switch soft reset */ -- mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); -- udelay(100); -- -- /* Enable MDC input Schmitt Trigger */ -- mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN, -- SMT_IOLB_5_SMI_MDC_EN); -- -- mt7531_core_pll_setup(priv, priv->mcm); -- -- mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val); -- port5_sgmii = !!(val & PAD_DUAL_SGMII_EN); -- -- /* port5 support either RGMII or SGMII, port6 only support SGMII. */ -- switch (priv->phy_interface) { -- case PHY_INTERFACE_MODE_RGMII: -- if (!port5_sgmii) -- mt7531_port_rgmii_init(priv, 5); -- break; -- case PHY_INTERFACE_MODE_2500BASEX: -- mt7531_port_sgmii_init(priv, 6); -- if (port5_sgmii) -- mt7531_port_sgmii_init(priv, 5); -- break; -- default: -- break; -- } -- -- pmcr = MT7531_FORCE_MODE | -- (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | -- MAC_MODE | MAC_TX_EN | MAC_RX_EN | -- BKOFF_EN | BACKPR_EN | -- FORCE_RX_FC | FORCE_TX_FC | -- (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | -- FORCE_LINK; -- -- priv->mt753x_pmcr = pmcr; -- -- /* Keep MAC link down before starting eth */ -- mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); -- mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); -- -- /* Turn on PHYs */ -- for (i = 0; i < MT753X_NUM_PHYS; i++) { -- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); -- phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); -- phy_val &= ~BMCR_PDOWN; -- priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); -- } -- -- mt7531_phy_setting(priv); -- -- /* Enable Internal PHYs */ -- val = mt753x_core_reg_read(priv, CORE_PLL_GROUP4); -- val |= MT7531_BYPASS_MODE; -- val &= ~MT7531_POWER_ON_OFF; -- mt753x_core_reg_write(priv, CORE_PLL_GROUP4, val); -- -- return 0; --} -- --static void mt7988_phy_setting(struct mtk_eth_priv *priv) --{ -- u16 val; -- u32 i; -- -- for (i = 0; i < MT753X_NUM_PHYS; i++) { -- /* Enable HW auto downshift */ -- priv->mii_write(priv, i, 0x1f, 0x1); -- val = priv->mii_read(priv, i, PHY_EXT_REG_14); -- val |= PHY_EN_DOWN_SHFIT; -- priv->mii_write(priv, i, PHY_EXT_REG_14, val); -- -- /* PHY link down power saving enable */ -- val = priv->mii_read(priv, i, PHY_EXT_REG_17); -- val |= PHY_LINKDOWN_POWER_SAVING_EN; -- priv->mii_write(priv, i, PHY_EXT_REG_17, val); -- } --} -- --static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable) --{ -- u32 pmcr = FORCE_MODE_LNK; -- -- if (enable) -- pmcr = priv->mt753x_pmcr; -- -- mt753x_reg_write(priv, PMCR_REG(6), pmcr); --} -- --static int mt7988_setup(struct mtk_eth_priv *priv) --{ -- u16 phy_addr, phy_val; -- u32 pmcr; -- int i; -- -- priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE; -- -- priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) & -- MT753X_SMI_ADDR_MASK; -- -- /* Turn off PHYs */ -- for (i = 0; i < MT753X_NUM_PHYS; i++) { -- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); -- phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); -- phy_val |= BMCR_PDOWN; -- priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); -- } -- -- switch (priv->phy_interface) { -- case PHY_INTERFACE_MODE_USXGMII: -- /* Use CPU bridge instead of actual USXGMII path */ -- -- /* Set GDM1 no drop */ -- mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1); -- -- /* Enable GDM1 to GSW CPU bridge */ -- mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0)); -- -- /* XGMAC force link up */ -- mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK); -- -- /* Setup GSW CPU bridge IPG */ -- mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M, -- (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S)); -- break; -- default: -- printf("Error: MT7988 GSW does not support %s interface\n", -- phy_string_for_interface(priv->phy_interface)); -- break; -- } -- -- pmcr = MT7988_FORCE_MODE | -- (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | -- MAC_MODE | MAC_TX_EN | MAC_RX_EN | -- BKOFF_EN | BACKPR_EN | -- FORCE_RX_FC | FORCE_TX_FC | -- (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | -- FORCE_LINK; -- -- priv->mt753x_pmcr = pmcr; -- -- /* Keep MAC link down before starting eth */ -- mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); -- -- /* Turn on PHYs */ -- for (i = 0; i < MT753X_NUM_PHYS; i++) { -- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); -- phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); -- phy_val &= ~BMCR_PDOWN; -- priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); -- } -- -- mt7988_phy_setting(priv); -- -- return 0; --} -- --static int mt753x_switch_init(struct mtk_eth_priv *priv) --{ -- int ret; -- int i; -- -- /* Global reset switch */ -- if (priv->mcm) { -- reset_assert(&priv->rst_mcm); -- udelay(1000); -- reset_deassert(&priv->rst_mcm); -- mdelay(priv->mt753x_reset_wait_time); -- } else if (dm_gpio_is_valid(&priv->rst_gpio)) { -- dm_gpio_set_value(&priv->rst_gpio, 0); -- udelay(1000); -- dm_gpio_set_value(&priv->rst_gpio, 1); -- mdelay(priv->mt753x_reset_wait_time); -- } -- -- ret = priv->switch_init(priv); -- if (ret) -- return ret; -- -- /* Set port isolation */ -- for (i = 0; i < MT753X_NUM_PORTS; i++) { -- /* Set port matrix mode */ -- if (i != 6) -- mt753x_reg_write(priv, PCR_REG(i), -- (0x40 << PORT_MATRIX_S)); -- else -- mt753x_reg_write(priv, PCR_REG(i), -- (0x3f << PORT_MATRIX_S)); -- -- /* Set port mode to user port */ -- mt753x_reg_write(priv, PVC_REG(i), -- (0x8100 << STAG_VPID_S) | -- (VLAN_ATTR_USER << VLAN_ATTR_S)); -- } -- -- return 0; --} -- --static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv) --{ -- u16 lcl_adv = 0, rmt_adv = 0; -- u8 flowctrl; -- u32 mcr; -- -- mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id)); -- mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC); -- -- if (priv->phydev->duplex) { -- if (priv->phydev->pause) -- rmt_adv = LPA_PAUSE_CAP; -- if (priv->phydev->asym_pause) -- rmt_adv |= LPA_PAUSE_ASYM; -- -- if (priv->phydev->advertising & ADVERTISED_Pause) -- lcl_adv |= ADVERTISE_PAUSE_CAP; -- if (priv->phydev->advertising & ADVERTISED_Asym_Pause) -- lcl_adv |= ADVERTISE_PAUSE_ASYM; -- -- flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); -- -- if (flowctrl & FLOW_CTRL_TX) -- mcr |= XGMAC_FORCE_TX_FC; -- if (flowctrl & FLOW_CTRL_RX) -- mcr |= XGMAC_FORCE_RX_FC; -- -- debug("rx pause %s, tx pause %s\n", -- flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", -- flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); -- } -- -- mcr &= ~(XGMAC_TRX_DISABLE); -- mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr); --} -- --static void mtk_phy_link_adjust(struct mtk_eth_priv *priv) --{ -- u16 lcl_adv = 0, rmt_adv = 0; -- u8 flowctrl; -- u32 mcr; -- -- mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | -- (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) | -- MAC_MODE | FORCE_MODE | -- MAC_TX_EN | MAC_RX_EN | -- DEL_RXFIFO_CLR | -- BKOFF_EN | BACKPR_EN; -- -- switch (priv->phydev->speed) { -- case SPEED_10: -- mcr |= (SPEED_10M << FORCE_SPD_S); -- break; -- case SPEED_100: -- mcr |= (SPEED_100M << FORCE_SPD_S); -- break; -- case SPEED_1000: -- case SPEED_2500: -- mcr |= (SPEED_1000M << FORCE_SPD_S); -- break; -- }; -- -- if (priv->phydev->link) -- mcr |= FORCE_LINK; -- -- if (priv->phydev->duplex) { -- mcr |= FORCE_DPX; -- -- if (priv->phydev->pause) -- rmt_adv = LPA_PAUSE_CAP; -- if (priv->phydev->asym_pause) -- rmt_adv |= LPA_PAUSE_ASYM; -- -- if (priv->phydev->advertising & ADVERTISED_Pause) -- lcl_adv |= ADVERTISE_PAUSE_CAP; -- if (priv->phydev->advertising & ADVERTISED_Asym_Pause) -- lcl_adv |= ADVERTISE_PAUSE_ASYM; -- -- flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); -- -- if (flowctrl & FLOW_CTRL_TX) -- mcr |= FORCE_TX_FC; -- if (flowctrl & FLOW_CTRL_RX) -- mcr |= FORCE_RX_FC; -- -- debug("rx pause %s, tx pause %s\n", -- flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", -- flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); -- } -- -- mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); --} -- --static int mtk_phy_start(struct mtk_eth_priv *priv) --{ -- struct phy_device *phydev = priv->phydev; -- int ret; -- -- ret = phy_startup(phydev); -- -- if (ret) { -- debug("Could not initialize PHY %s\n", phydev->dev->name); -- return ret; -- } -- -- if (!phydev->link) { -- debug("%s: link down.\n", phydev->dev->name); -- return 0; -- } -- -- if (!priv->force_mode) { -- if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || -- priv->phy_interface == PHY_INTERFACE_MODE_XGMII) -- mtk_xphy_link_adjust(priv); -- else -- mtk_phy_link_adjust(priv); -- } -- -- debug("Speed: %d, %s duplex%s\n", phydev->speed, -- (phydev->duplex) ? "full" : "half", -- (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); -- -- return 0; --} -- --static int mtk_phy_probe(struct udevice *dev) --{ -- struct mtk_eth_priv *priv = dev_get_priv(dev); -- struct phy_device *phydev; -- -- phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev, -- priv->phy_interface); -- if (!phydev) -- return -ENODEV; -- -- phydev->supported &= PHY_GBIT_FEATURES; -- phydev->advertising = phydev->supported; -- -- priv->phydev = phydev; -- phy_config(phydev); -- -- return 0; --} -- --static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) --{ -- /* Set SGMII GEN1 speed(1G) */ -- clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK); -- -- /* Enable SGMII AN */ -- setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, -- SGMII_AN_ENABLE); -- -- /* SGMII AN mode setting */ -- writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); -- -- /* SGMII PN SWAP setting */ -- if (priv->pn_swap) { -- setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL, -- SGMII_PN_SWAP_TX_RX); -- } -- -- /* Release PHYA power down state */ -- clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, -- SGMII_PHYA_PWD, 0); --} -- --static void mtk_sgmii_force_init(struct mtk_eth_priv *priv) --{ -- /* Set SGMII GEN2 speed(2.5G) */ -- clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, -- SGMSYS_SPEED_MASK, -- FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); -- -- /* Disable SGMII AN */ -- clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, -- SGMII_AN_ENABLE, 0); -- -- /* SGMII force mode setting */ -- writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); -- -- /* SGMII PN SWAP setting */ -- if (priv->pn_swap) { -- setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL, -- SGMII_PN_SWAP_TX_RX); -- } -- -- /* Release PHYA power down state */ -- clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, -- SGMII_PHYA_PWD, 0); --} -- --static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv) --{ -- u32 val = 0; -- -- /* Add software workaround for USXGMII PLL TCL issue */ -- regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8, -- RG_XFI_PLL_ANA_SWWA); -- -- regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val); -- val |= RG_XFI_PLL_EN; -- regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val); --} -- --static void mtk_usxgmii_reset(struct mtk_eth_priv *priv) --{ -- switch (priv->gmac_id) { -- case 1: -- regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004); -- regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004); -- regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000); -- regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000); -- regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000); -- break; -- case 2: -- regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002); -- regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002); -- regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000); -- regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000); -- regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000); -- break; -- } -- -- mdelay(10); --} -- --static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv) --{ -- regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D); -- regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); -- regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000); -- ndelay(1020); -- regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000); -- ndelay(1020); -- regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000); -- -- regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); -- regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); -- regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); -- regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); -- regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); -- regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); -- regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); -- regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); -- regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); -- regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); -- regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); -- regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); -- regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); -- regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); -- regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); -- regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); -- regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); -- regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); -- regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); -- regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); -- regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); -- regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); -- regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); -- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); -- ndelay(1020); -- regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); -- regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); -- regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); -- regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); -- regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); -- regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); -- regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); -- regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000); -- regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000); -- regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA); -- regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); -- regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); -- regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); -- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); -- udelay(150); -- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); -- ndelay(1020); -- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); -- udelay(15); -- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); -- ndelay(1020); -- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); -- udelay(100); -- regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); -- regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); -- regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); -- udelay(400); --} -- --static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv) --{ -- regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C); -- regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); -- regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000); -- ndelay(1020); -- regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000); -- ndelay(1020); -- -- regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); -- regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); -- regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); -- regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); -- regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); -- regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); -- regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); -- regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); -- regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); -- regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); -- regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); -- regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); -- regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); -- regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); -- regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); -- regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); -- regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); -- regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); -- regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); -- regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); -- regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); -- regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); -- regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); -- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); -- ndelay(1020); -- regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); -- regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); -- regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); -- regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); -- regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); -- regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); -- regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); -- regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100); -- regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000); -- regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000); -- regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); -- if (priv->gmac_id == 2) -- regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400); -- regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); -- regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); -- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); -- udelay(150); -- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); -- ndelay(1020); -- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); -- udelay(15); -- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); -- ndelay(1020); -- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); -- udelay(100); -- regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); -- regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); -- regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); -- udelay(400); --} -- --static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) --{ -- mtk_xfi_pll_enable(priv); -- mtk_usxgmii_reset(priv); -- mtk_usxgmii_setup_phya_an_10000(priv); --} -- --static void mtk_10gbaser_init(struct mtk_eth_priv *priv) --{ -- mtk_xfi_pll_enable(priv); -- mtk_usxgmii_reset(priv); -- mtk_usxgmii_setup_phya_force_10000(priv); --} -- --static int mtk_mac_init(struct mtk_eth_priv *priv) --{ -- int i, sgmii_sel_mask = 0, ge_mode = 0; -- u32 mcr; -- -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) { -- mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG, -- INFRA_MISC2_BONDING_OPTION, priv->gmac_id); -- } -- -- switch (priv->phy_interface) { -- case PHY_INTERFACE_MODE_RGMII_RXID: -- case PHY_INTERFACE_MODE_RGMII: -- ge_mode = GE_MODE_RGMII; -- break; -- case PHY_INTERFACE_MODE_SGMII: -- case PHY_INTERFACE_MODE_2500BASEX: -- if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { -- printf("Error: SGMII is not supported on this platform\n"); -- return -ENOTSUPP; -- } -- -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) { -- mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK, -- SGMII_QPHY_SEL); -- } -- -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) -- sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; -- -- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask, -- SYSCFG1_SGMII_SEL(priv->gmac_id)); -- -- if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) -- mtk_sgmii_an_init(priv); -- else -- mtk_sgmii_force_init(priv); -- -- ge_mode = GE_MODE_RGMII; -- break; -- case PHY_INTERFACE_MODE_MII: -- case PHY_INTERFACE_MODE_GMII: -- ge_mode = GE_MODE_MII; -- break; -- case PHY_INTERFACE_MODE_RMII: -- ge_mode = GE_MODE_RMII; -- break; -- default: -- break; -- } -- -- /* set the gmac to the right mode */ -- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, -- SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), -- ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id)); -- -- if (priv->force_mode) { -- mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | -- (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) | -- MAC_MODE | FORCE_MODE | -- MAC_TX_EN | MAC_RX_EN | -- BKOFF_EN | BACKPR_EN | -- FORCE_LINK; -- -- switch (priv->speed) { -- case SPEED_10: -- mcr |= SPEED_10M << FORCE_SPD_S; -- break; -- case SPEED_100: -- mcr |= SPEED_100M << FORCE_SPD_S; -- break; -- case SPEED_1000: -- case SPEED_2500: -- mcr |= SPEED_1000M << FORCE_SPD_S; -- break; -- } -- -- if (priv->duplex) -- mcr |= FORCE_DPX; -- -- mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); -- } -- -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC1_TRGMII) && -- !MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) { -- /* Lower Tx Driving for TRGMII path */ -- for (i = 0 ; i < NUM_TRGMII_CTRL; i++) -- mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i), -- (8 << TD_DM_DRVP_S) | -- (8 << TD_DM_DRVN_S)); -- -- mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0, -- RX_RST | RXC_DQSISEL); -- mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0); -- } -- -- return 0; --} -- --static int mtk_xmac_init(struct mtk_eth_priv *priv) --{ -- u32 force_link = 0; -- -- if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { -- printf("Error: 10Gb interface is not supported on this platform\n"); -- return -ENOTSUPP; -- } -- -- switch (priv->phy_interface) { -- case PHY_INTERFACE_MODE_USXGMII: -- mtk_usxgmii_an_init(priv); -- break; -- case PHY_INTERFACE_MODE_10GBASER: -- mtk_10gbaser_init(priv); -- break; -- default: -- break; -- } -- -- /* Set GMAC to the correct mode */ -- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, -- SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), -- 0); -- -- if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && -- priv->gmac_id == 1) { -- mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX, -- NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL); -- } -- -- if (priv->phy_interface == PHY_INTERFACE_MODE_XGMII || -- priv->gmac_id == 2) -- force_link = XGMAC_FORCE_LINK(priv->gmac_id); -- -- mtk_gmac_rmw(priv, XGMAC_STS(priv->gmac_id), -- XGMAC_FORCE_LINK(priv->gmac_id), force_link); -- -- /* Force GMAC link down */ -- mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE); -- -- return 0; --} -- --static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) --{ -- char *pkt_base = priv->pkt_pool; -- struct mtk_tx_dma_v2 *txd; -- struct mtk_rx_dma_v2 *rxd; -- int i; -- -- mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0); -- udelay(500); -- -- memset(priv->tx_ring_noc, 0, NUM_TX_DESC * priv->soc->txd_size); -- memset(priv->rx_ring_noc, 0, NUM_RX_DESC * priv->soc->rxd_size); -- memset(priv->pkt_pool, 0xff, TOTAL_PKT_BUF_SIZE); -- -- flush_dcache_range((ulong)pkt_base, -- (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE)); -- -- priv->rx_dma_owner_idx0 = 0; -- priv->tx_cpu_owner_idx0 = 0; -- -- for (i = 0; i < NUM_TX_DESC; i++) { -- txd = priv->tx_ring_noc + i * priv->soc->txd_size; -- -- txd->txd1 = virt_to_phys(pkt_base); -- txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0; -- -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -- txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ? -- 15 : priv->gmac_id + 1); -- else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -- txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1); -- else -- txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1); -- -- pkt_base += PKTSIZE_ALIGN; -- } -- -- for (i = 0; i < NUM_RX_DESC; i++) { -- rxd = priv->rx_ring_noc + i * priv->soc->rxd_size; -- -- rxd->rxd1 = virt_to_phys(pkt_base); -- -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -- MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -- rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -- else -- rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -- -- pkt_base += PKTSIZE_ALIGN; -- } -- -- mtk_pdma_write(priv, TX_BASE_PTR_REG(0), -- virt_to_phys(priv->tx_ring_noc)); -- mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC); -- mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); -- -- mtk_pdma_write(priv, RX_BASE_PTR_REG(0), -- virt_to_phys(priv->rx_ring_noc)); -- mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC); -- mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1); -- -- mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0); --} -- --static void mtk_eth_mdc_init(struct mtk_eth_priv *priv) --{ -- u32 divider; -- -- if (priv->mdc == 0) -- return; -- -- divider = min_t(u32, DIV_ROUND_UP(MDC_MAX_FREQ, priv->mdc), MDC_MAX_DIVIDER); -- -- /* Configure MDC turbo mode */ -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -- mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, MISC_MDC_TURBO); -- else -- mtk_gmac_rmw(priv, GMAC_PPSC_REG, 0, MISC_MDC_TURBO); -- -- /* Configure MDC divider */ -- mtk_gmac_rmw(priv, GMAC_PPSC_REG, PHY_MDC_CFG, -- FIELD_PREP(PHY_MDC_CFG, divider)); --} -- --static int mtk_eth_start(struct udevice *dev) --{ -- struct mtk_eth_priv *priv = dev_get_priv(dev); -- int i, ret; -- -- /* Reset FE */ -- reset_assert(&priv->rst_fe); -- udelay(1000); -- reset_deassert(&priv->rst_fe); -- mdelay(10); -- -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -- MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -- setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2); -- -- /* Packets forward to PDMA */ -- mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU); -- -- for (i = 0; i < priv->soc->gdma_count; i++) { -- if (i == priv->gmac_id) -- continue; -- -- mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); -- } -- -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) { -- if (priv->sw == SW_MT7988 && priv->gmac_id == 0) { -- mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, -- GDMA_BRIDGE_TO_CPU); -- -- mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, -- GDMA_CPU_BRIDGE_EN); -- } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || -- priv->phy_interface == PHY_INTERFACE_MODE_XGMII) && -- priv->gmac_id != 0) { -- mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, -- GDMA_CPU_BRIDGE_EN); -- } -- } -- -- udelay(500); -- -- mtk_eth_fifo_init(priv); -- -- if (priv->switch_mac_control) -- priv->switch_mac_control(priv, true); -- -- /* Start PHY */ -- if (priv->sw == SW_NONE) { -- ret = mtk_phy_start(priv); -- if (ret) -- return ret; -- } -- -- mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0, -- TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); -- udelay(500); -- -- return 0; --} -- --static void mtk_eth_stop(struct udevice *dev) --{ -- struct mtk_eth_priv *priv = dev_get_priv(dev); -- -- if (priv->switch_mac_control) -- priv->switch_mac_control(priv, false); -- -- mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, -- TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0); -- udelay(500); -- -- wait_for_bit_le32(priv->fe_base + priv->soc->pdma_base + PDMA_GLO_CFG_REG, -- RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0); --} -- --static int mtk_eth_write_hwaddr(struct udevice *dev) --{ -- struct eth_pdata *pdata = dev_get_plat(dev); -- struct mtk_eth_priv *priv = dev_get_priv(dev); -- unsigned char *mac = pdata->enetaddr; -- u32 macaddr_lsb, macaddr_msb; -- -- macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1]; -- macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) | -- ((u32)mac[4] << 8) | (u32)mac[5]; -- -- mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb); -- mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb); -- -- return 0; --} -- --static int mtk_eth_send(struct udevice *dev, void *packet, int length) --{ -- struct mtk_eth_priv *priv = dev_get_priv(dev); -- u32 idx = priv->tx_cpu_owner_idx0; -- struct mtk_tx_dma_v2 *txd; -- void *pkt_base; -- -- txd = priv->tx_ring_noc + idx * priv->soc->txd_size; -- -- if (!(txd->txd2 & PDMA_TXD2_DDONE)) { -- debug("mtk-eth: TX DMA descriptor ring is full\n"); -- return -EPERM; -- } -- -- pkt_base = (void *)phys_to_virt(txd->txd1); -- memcpy(pkt_base, packet, length); -- flush_dcache_range((ulong)pkt_base, (ulong)pkt_base + -- roundup(length, ARCH_DMA_MINALIGN)); -- -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -- MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -- txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length); -- else -- txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length); -- -- priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; -- mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); -- -- return 0; --} -- --static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp) --{ -- struct mtk_eth_priv *priv = dev_get_priv(dev); -- u32 idx = priv->rx_dma_owner_idx0; -- struct mtk_rx_dma_v2 *rxd; -- uchar *pkt_base; -- u32 length; -- -- rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; -- -- if (!(rxd->rxd2 & PDMA_RXD2_DDONE)) { -- debug("mtk-eth: RX DMA descriptor ring is empty\n"); -- return -EAGAIN; -- } -- -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -- MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -- length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2); -- else -- length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2); -- -- pkt_base = (void *)phys_to_virt(rxd->rxd1); -- invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base + -- roundup(length, ARCH_DMA_MINALIGN)); -- -- if (packetp) -- *packetp = pkt_base; -- -- return length; --} -- --static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length) --{ -- struct mtk_eth_priv *priv = dev_get_priv(dev); -- u32 idx = priv->rx_dma_owner_idx0; -- struct mtk_rx_dma_v2 *rxd; -- -- rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; -- -- invalidate_dcache_range((ulong)rxd->rxd1, -- (ulong)rxd->rxd1 + PKTSIZE_ALIGN); -- -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -- MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -- rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -- else -- rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -- -- mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx); -- priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC; -- -- return 0; --} -- --static int mtk_eth_probe(struct udevice *dev) --{ -- struct eth_pdata *pdata = dev_get_plat(dev); -- struct mtk_eth_priv *priv = dev_get_priv(dev); -- ulong iobase = pdata->iobase; -- int ret; -- -- /* Frame Engine Register Base */ -- priv->fe_base = (void *)iobase; -- -- /* GMAC Register Base */ -- priv->gmac_base = (void *)(iobase + GMAC_BASE); -- -- /* MDIO register */ -- ret = mtk_mdio_register(dev); -- if (ret) -- return ret; -- -- /* Prepare for tx/rx rings */ -- priv->tx_ring_noc = (void *) -- noncached_alloc(priv->soc->txd_size * NUM_TX_DESC, -- ARCH_DMA_MINALIGN); -- priv->rx_ring_noc = (void *) -- noncached_alloc(priv->soc->rxd_size * NUM_RX_DESC, -- ARCH_DMA_MINALIGN); -- -- /* Set MDC divider */ -- mtk_eth_mdc_init(priv); -- -- /* Set MAC mode */ -- if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || -- priv->phy_interface == PHY_INTERFACE_MODE_XGMII) -- ret = mtk_xmac_init(priv); -- else -- ret = mtk_mac_init(priv); -- -- if (ret) -- return ret; -- -- /* Probe phy if switch is not specified */ -- if (priv->sw == SW_NONE) -- return mtk_phy_probe(dev); -- -- /* Initialize switch */ -- return mt753x_switch_init(priv); --} -- --static int mtk_eth_remove(struct udevice *dev) --{ -- struct mtk_eth_priv *priv = dev_get_priv(dev); -- -- /* MDIO unregister */ -- mdio_unregister(priv->mdio_bus); -- mdio_free(priv->mdio_bus); -- -- /* Stop possibly started DMA */ -- mtk_eth_stop(dev); -- -- return 0; --} -- --static int mtk_eth_of_to_plat(struct udevice *dev) --{ -- struct eth_pdata *pdata = dev_get_plat(dev); -- struct mtk_eth_priv *priv = dev_get_priv(dev); -- struct ofnode_phandle_args args; -- struct regmap *regmap; -- const char *str; -- ofnode subnode; -- int ret; -- -- priv->soc = (const struct mtk_soc_data *)dev_get_driver_data(dev); -- if (!priv->soc) { -- dev_err(dev, "missing soc compatible data\n"); -- return -EINVAL; -- } -- -- pdata->iobase = (phys_addr_t)dev_remap_addr(dev); -- -- /* get corresponding ethsys phandle */ -- ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0, -- &args); -- if (ret) -- return ret; -- -- priv->ethsys_regmap = syscon_node_to_regmap(args.node); -- if (IS_ERR(priv->ethsys_regmap)) -- return PTR_ERR(priv->ethsys_regmap); -- -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) { -- /* get corresponding infracfg phandle */ -- ret = dev_read_phandle_with_args(dev, "mediatek,infracfg", -- NULL, 0, 0, &args); -- -- if (ret) -- return ret; -- -- priv->infra_regmap = syscon_node_to_regmap(args.node); -- if (IS_ERR(priv->infra_regmap)) -- return PTR_ERR(priv->infra_regmap); -- } -- -- /* Reset controllers */ -- ret = reset_get_by_name(dev, "fe", &priv->rst_fe); -- if (ret) { -- printf("error: Unable to get reset ctrl for frame engine\n"); -- return ret; -- } -- -- priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0); -- -- priv->mdc = 0; -- subnode = ofnode_find_subnode(dev_ofnode(dev), "mdio"); -- if (ofnode_valid(subnode)) { -- priv->mdc = ofnode_read_u32_default(subnode, "clock-frequency", 2500000); -- if (priv->mdc > MDC_MAX_FREQ || -- priv->mdc < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { -- printf("error: MDIO clock frequency out of range\n"); -- return -EINVAL; -- } -- } -- -- /* Interface mode is required */ -- pdata->phy_interface = dev_read_phy_mode(dev); -- priv->phy_interface = pdata->phy_interface; -- if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) { -- printf("error: phy-mode is not set\n"); -- return -EINVAL; -- } -- -- /* Force mode or autoneg */ -- subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link"); -- if (ofnode_valid(subnode)) { -- priv->force_mode = 1; -- priv->speed = ofnode_read_u32_default(subnode, "speed", 0); -- priv->duplex = ofnode_read_bool(subnode, "full-duplex"); -- -- if (priv->speed != SPEED_10 && priv->speed != SPEED_100 && -- priv->speed != SPEED_1000 && priv->speed != SPEED_2500 && -- priv->speed != SPEED_10000) { -- printf("error: no valid speed set in fixed-link\n"); -- return -EINVAL; -- } -- } -- -- if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII || -- priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) && -- IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { -- /* get corresponding sgmii phandle */ -- ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", -- NULL, 0, 0, &args); -- if (ret) -- return ret; -- -- regmap = syscon_node_to_regmap(args.node); -- -- if (IS_ERR(regmap)) -- return PTR_ERR(regmap); -- -- priv->sgmii_base = regmap_get_range(regmap, 0); -- -- if (!priv->sgmii_base) { -- dev_err(dev, "Unable to find sgmii\n"); -- return -ENODEV; -- } -- -- /* Upstream linux use mediatek,pnswap instead of pn_swap */ -- priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || -- ofnode_read_bool(args.node, "mediatek,pnswap"); -- } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && -- IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { -- /* get corresponding usxgmii phandle */ -- ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", -- NULL, 0, 0, &args); -- if (ret) -- return ret; -- -- priv->usxgmii_regmap = syscon_node_to_regmap(args.node); -- if (IS_ERR(priv->usxgmii_regmap)) -- return PTR_ERR(priv->usxgmii_regmap); -- -- /* get corresponding xfi_pextp phandle */ -- ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp", -- NULL, 0, 0, &args); -- if (ret) -- return ret; -- -- priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node); -- if (IS_ERR(priv->xfi_pextp_regmap)) -- return PTR_ERR(priv->xfi_pextp_regmap); -- -- /* get corresponding xfi_pll phandle */ -- ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll", -- NULL, 0, 0, &args); -- if (ret) -- return ret; -- -- priv->xfi_pll_regmap = syscon_node_to_regmap(args.node); -- if (IS_ERR(priv->xfi_pll_regmap)) -- return PTR_ERR(priv->xfi_pll_regmap); -- -- /* get corresponding toprgu phandle */ -- ret = dev_read_phandle_with_args(dev, "mediatek,toprgu", -- NULL, 0, 0, &args); -- if (ret) -- return ret; -- -- priv->toprgu_regmap = syscon_node_to_regmap(args.node); -- if (IS_ERR(priv->toprgu_regmap)) -- return PTR_ERR(priv->toprgu_regmap); -- } -- -- /* check for switch first, otherwise phy will be used */ -- priv->sw = SW_NONE; -- priv->switch_init = NULL; -- priv->switch_mac_control = NULL; -- str = dev_read_string(dev, "mediatek,switch"); -- -- if (str) { -- if (!strcmp(str, "mt7530")) { -- priv->sw = SW_MT7530; -- priv->switch_init = mt7530_setup; -- priv->switch_mac_control = mt7530_mac_control; -- priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; -- priv->mt753x_reset_wait_time = 1000; -- } else if (!strcmp(str, "mt7531")) { -- priv->sw = SW_MT7531; -- priv->switch_init = mt7531_setup; -- priv->switch_mac_control = mt7531_mac_control; -- priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; -- priv->mt753x_reset_wait_time = 200; -- } else if (!strcmp(str, "mt7988")) { -- priv->sw = SW_MT7988; -- priv->switch_init = mt7988_setup; -- priv->switch_mac_control = mt7988_mac_control; -- priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; -- priv->mt753x_reset_wait_time = 50; -- } else { -- printf("error: unsupported switch\n"); -- return -EINVAL; -- } -- -- priv->mcm = dev_read_bool(dev, "mediatek,mcm"); -- if (priv->mcm) { -- ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm); -- if (ret) { -- printf("error: no reset ctrl for mcm\n"); -- return ret; -- } -- } else { -- gpio_request_by_name(dev, "reset-gpios", 0, -- &priv->rst_gpio, GPIOD_IS_OUT); -- } -- } else { -- ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, -- 0, &args); -- if (ret) { -- printf("error: phy-handle is not specified\n"); -- return ret; -- } -- -- priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1); -- if (priv->phy_addr < 0) { -- printf("error: phy address is not specified\n"); -- return ret; -- } -- } -- -- return 0; --} -- --static const struct mtk_soc_data mt7988_data = { -- .caps = MT7988_CAPS, -- .ana_rgc3 = 0x128, -- .gdma_count = 3, -- .pdma_base = PDMA_V3_BASE, -- .txd_size = sizeof(struct mtk_tx_dma_v2), -- .rxd_size = sizeof(struct mtk_rx_dma_v2), --}; -- --static const struct mtk_soc_data mt7986_data = { -- .caps = MT7986_CAPS, -- .ana_rgc3 = 0x128, -- .gdma_count = 2, -- .pdma_base = PDMA_V2_BASE, -- .txd_size = sizeof(struct mtk_tx_dma_v2), -- .rxd_size = sizeof(struct mtk_rx_dma_v2), --}; -- --static const struct mtk_soc_data mt7981_data = { -- .caps = MT7981_CAPS, -- .ana_rgc3 = 0x128, -- .gdma_count = 2, -- .pdma_base = PDMA_V2_BASE, -- .txd_size = sizeof(struct mtk_tx_dma_v2), -- .rxd_size = sizeof(struct mtk_rx_dma_v2), --}; -- --static const struct mtk_soc_data mt7629_data = { -- .caps = MT7629_CAPS, -- .ana_rgc3 = 0x128, -- .gdma_count = 2, -- .pdma_base = PDMA_V1_BASE, -- .txd_size = sizeof(struct mtk_tx_dma), -- .rxd_size = sizeof(struct mtk_rx_dma), --}; -- --static const struct mtk_soc_data mt7623_data = { -- .caps = MT7623_CAPS, -- .gdma_count = 2, -- .pdma_base = PDMA_V1_BASE, -- .txd_size = sizeof(struct mtk_tx_dma), -- .rxd_size = sizeof(struct mtk_rx_dma), --}; -- --static const struct mtk_soc_data mt7622_data = { -- .caps = MT7622_CAPS, -- .ana_rgc3 = 0x2028, -- .gdma_count = 2, -- .pdma_base = PDMA_V1_BASE, -- .txd_size = sizeof(struct mtk_tx_dma), -- .rxd_size = sizeof(struct mtk_rx_dma), --}; -- --static const struct mtk_soc_data mt7621_data = { -- .caps = MT7621_CAPS, -- .gdma_count = 2, -- .pdma_base = PDMA_V1_BASE, -- .txd_size = sizeof(struct mtk_tx_dma), -- .rxd_size = sizeof(struct mtk_rx_dma), --}; -- --static const struct udevice_id mtk_eth_ids[] = { -- { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data }, -- { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data }, -- { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data }, -- { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, -- { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data }, -- { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data }, -- { .compatible = "mediatek,mt7621-eth", .data = (ulong)&mt7621_data }, -- {} --}; -- --static const struct eth_ops mtk_eth_ops = { -- .start = mtk_eth_start, -- .stop = mtk_eth_stop, -- .send = mtk_eth_send, -- .recv = mtk_eth_recv, -- .free_pkt = mtk_eth_free_pkt, -- .write_hwaddr = mtk_eth_write_hwaddr, --}; -- --U_BOOT_DRIVER(mtk_eth) = { -- .name = "mtk-eth", -- .id = UCLASS_ETH, -- .of_match = mtk_eth_ids, -- .of_to_plat = mtk_eth_of_to_plat, -- .plat_auto = sizeof(struct eth_pdata), -- .probe = mtk_eth_probe, -- .remove = mtk_eth_remove, -- .ops = &mtk_eth_ops, -- .priv_auto = sizeof(struct mtk_eth_priv), -- .flags = DM_FLAG_ALLOC_PRIV_DMA, --}; ---- /dev/null -+++ b/drivers/net/mtk_eth/mtk_eth.c -@@ -0,0 +1,1563 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2025 MediaTek Inc. -+ * -+ * Author: Weijie Gao -+ * Author: Mark Lee -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "mtk_eth.h" -+ -+#define NUM_TX_DESC 32 -+#define NUM_RX_DESC 32 -+#define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN) -+#define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) -+#define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) -+ -+#define GDMA_FWD_TO_CPU \ -+ (0x20000000 | \ -+ GDM_ICS_EN | \ -+ GDM_TCS_EN | \ -+ GDM_UCS_EN | \ -+ STRP_CRC | \ -+ (DP_PDMA << MYMAC_DP_S) | \ -+ (DP_PDMA << BC_DP_S) | \ -+ (DP_PDMA << MC_DP_S) | \ -+ (DP_PDMA << UN_DP_S)) -+ -+#define GDMA_BRIDGE_TO_CPU \ -+ (0xC0000000 | \ -+ GDM_ICS_EN | \ -+ GDM_TCS_EN | \ -+ GDM_UCS_EN | \ -+ (DP_PDMA << MYMAC_DP_S) | \ -+ (DP_PDMA << BC_DP_S) | \ -+ (DP_PDMA << MC_DP_S) | \ -+ (DP_PDMA << UN_DP_S)) -+ -+#define GDMA_FWD_DISCARD \ -+ (0x20000000 | \ -+ GDM_ICS_EN | \ -+ GDM_TCS_EN | \ -+ GDM_UCS_EN | \ -+ STRP_CRC | \ -+ (DP_DISCARD << MYMAC_DP_S) | \ -+ (DP_DISCARD << BC_DP_S) | \ -+ (DP_DISCARD << MC_DP_S) | \ -+ (DP_DISCARD << UN_DP_S)) -+ -+struct mtk_eth_priv { -+ char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); -+ -+ void *tx_ring_noc; -+ void *rx_ring_noc; -+ -+ int rx_dma_owner_idx0; -+ int tx_cpu_owner_idx0; -+ -+ void __iomem *fe_base; -+ void __iomem *gmac_base; -+ void __iomem *sgmii_base; -+ -+ struct regmap *ethsys_regmap; -+ -+ struct regmap *infra_regmap; -+ -+ struct regmap *usxgmii_regmap; -+ struct regmap *xfi_pextp_regmap; -+ struct regmap *xfi_pll_regmap; -+ struct regmap *toprgu_regmap; -+ -+ struct mii_dev *mdio_bus; -+ -+ const struct mtk_soc_data *soc; -+ int gmac_id; -+ int force_mode; -+ int speed; -+ int duplex; -+ int mdc; -+ bool pn_swap; -+ -+ struct phy_device *phydev; -+ int phy_interface; -+ int phy_addr; -+ -+ struct mtk_eth_switch_priv *swpriv; -+ const char *swname; -+ -+ struct gpio_desc rst_gpio; -+ int mcm; -+ -+ struct reset_ctl rst_fe; -+ struct reset_ctl rst_mcm; -+}; -+ -+static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val) -+{ -+ writel(val, priv->fe_base + priv->soc->pdma_base + reg); -+} -+ -+static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, -+ u32 set) -+{ -+ clrsetbits_le32(priv->fe_base + priv->soc->pdma_base + reg, clr, set); -+} -+ -+static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg, -+ u32 val) -+{ -+ u32 gdma_base; -+ -+ if (no == 2) -+ gdma_base = GDMA3_BASE; -+ else if (no == 1) -+ gdma_base = GDMA2_BASE; -+ else -+ gdma_base = GDMA1_BASE; -+ -+ writel(val, priv->fe_base + gdma_base + reg); -+} -+ -+void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) -+{ -+ clrsetbits_le32(priv->fe_base + reg, clr, set); -+} -+ -+static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg) -+{ -+ return readl(priv->gmac_base + reg); -+} -+ -+static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val) -+{ -+ writel(val, priv->gmac_base + reg); -+} -+ -+void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) -+{ -+ clrsetbits_le32(priv->gmac_base + reg, clr, set); -+} -+ -+void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) -+{ -+ uint val; -+ -+ regmap_read(priv->ethsys_regmap, reg, &val); -+ val &= ~clr; -+ val |= set; -+ regmap_write(priv->ethsys_regmap, reg, val); -+} -+ -+static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, -+ u32 set) -+{ -+ uint val; -+ -+ regmap_read(priv->infra_regmap, reg, &val); -+ val &= ~clr; -+ val |= set; -+ regmap_write(priv->infra_regmap, reg, val); -+} -+ -+/* Direct MDIO clause 22/45 access via SoC */ -+static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, -+ u32 cmd, u32 st) -+{ -+ int ret; -+ u32 val; -+ -+ val = (st << MDIO_ST_S) | -+ ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | -+ (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | -+ (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); -+ -+ if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) -+ val |= data & MDIO_RW_DATA_M; -+ -+ mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST); -+ -+ ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG, -+ PHY_ACS_ST, 0, 5000, 0); -+ if (ret) { -+ pr_warn("MDIO access timeout\n"); -+ return ret; -+ } -+ -+ if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { -+ val = mtk_gmac_read(priv, GMAC_PIAC_REG); -+ return val & MDIO_RW_DATA_M; -+ } -+ -+ return 0; -+} -+ -+/* Direct MDIO clause 22 read via SoC */ -+int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) -+{ -+ return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22); -+} -+ -+/* Direct MDIO clause 22 write via SoC */ -+int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data) -+{ -+ return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22); -+} -+ -+/* Direct MDIO clause 45 read via SoC */ -+int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) -+{ -+ int ret; -+ -+ ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); -+ if (ret) -+ return ret; -+ -+ return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45, -+ MDIO_ST_C45); -+} -+ -+/* Direct MDIO clause 45 write via SoC */ -+int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, -+ u16 val) -+{ -+ int ret; -+ -+ ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); -+ if (ret) -+ return ret; -+ -+ return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE, -+ MDIO_ST_C45); -+} -+ -+/* Indirect MDIO clause 45 read via MII registers */ -+int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) -+{ -+ int ret; -+ -+ ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, -+ (MMD_ADDR << MMD_CMD_S) | -+ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, -+ (MMD_DATA << MMD_CMD_S) | -+ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); -+ if (ret) -+ return ret; -+ -+ return mtk_mii_read(priv, addr, MII_MMD_ADDR_DATA_REG); -+} -+ -+/* Indirect MDIO clause 45 write via MII registers */ -+int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, -+ u16 val) -+{ -+ int ret; -+ -+ ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, -+ (MMD_ADDR << MMD_CMD_S) | -+ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, -+ (MMD_DATA << MMD_CMD_S) | -+ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); -+ if (ret) -+ return ret; -+ -+ return mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val); -+} -+ -+static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) -+{ -+ struct mtk_eth_priv *priv = bus->priv; -+ -+ if (devad < 0) -+ return mtk_mii_read(priv, addr, reg); -+ -+ return mtk_mmd_read(priv, addr, devad, reg); -+} -+ -+static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, -+ u16 val) -+{ -+ struct mtk_eth_priv *priv = bus->priv; -+ -+ if (devad < 0) -+ return mtk_mii_write(priv, addr, reg, val); -+ -+ return mtk_mmd_write(priv, addr, devad, reg, val); -+} -+ -+static int mtk_mdio_register(struct udevice *dev) -+{ -+ struct mtk_eth_priv *priv = dev_get_priv(dev); -+ struct mii_dev *mdio_bus = mdio_alloc(); -+ int ret; -+ -+ if (!mdio_bus) -+ return -ENOMEM; -+ -+ mdio_bus->read = mtk_mdio_read; -+ mdio_bus->write = mtk_mdio_write; -+ snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name); -+ -+ mdio_bus->priv = (void *)priv; -+ -+ ret = mdio_register(mdio_bus); -+ -+ if (ret) -+ return ret; -+ -+ priv->mdio_bus = mdio_bus; -+ -+ return 0; -+} -+ -+static int mtk_switch_init(struct mtk_eth_priv *priv) -+{ -+ struct mtk_eth_switch *swdrvs = ll_entry_start(struct mtk_eth_switch, -+ mtk_eth_switch); -+ const u32 n_swdrvs = ll_entry_count(struct mtk_eth_switch, -+ mtk_eth_switch); -+ struct mtk_eth_switch *tmp, *swdrv = NULL; -+ u32 reset_wait_time = 500; -+ size_t priv_size; -+ int ret; -+ -+ if (strcmp(priv->swname, "auto")) { -+ for (tmp = swdrvs; tmp < swdrvs + n_swdrvs; tmp++) { -+ if (!strcmp(tmp->name, priv->swname)) { -+ swdrv = tmp; -+ break; -+ } -+ } -+ } -+ -+ if (swdrv) -+ reset_wait_time = swdrv->reset_wait_time; -+ -+ /* Global reset switch */ -+ if (priv->mcm) { -+ reset_assert(&priv->rst_mcm); -+ udelay(1000); -+ reset_deassert(&priv->rst_mcm); -+ mdelay(reset_wait_time); -+ } else if (dm_gpio_is_valid(&priv->rst_gpio)) { -+ dm_gpio_set_value(&priv->rst_gpio, 0); -+ udelay(1000); -+ dm_gpio_set_value(&priv->rst_gpio, 1); -+ mdelay(reset_wait_time); -+ } -+ -+ if (!swdrv) { -+ for (tmp = swdrvs; tmp < swdrvs + n_swdrvs; tmp++) { -+ if (!tmp->detect) -+ continue; -+ -+ ret = tmp->detect(priv); -+ if (!ret) { -+ swdrv = tmp; -+ break; -+ } -+ } -+ -+ if (!swdrv) { -+ printf("Error: unable to detect switch\n"); -+ return -ENODEV; -+ } -+ } else { -+ if (swdrv->detect) { -+ ret = swdrv->detect(priv); -+ if (ret) { -+ printf("Error: switch probing failed\n"); -+ return -ENODEV; -+ } -+ } -+ } -+ -+ printf("%s\n", swdrv->desc); -+ -+ priv_size = swdrv->priv_size; -+ if (priv_size < sizeof(struct mtk_eth_switch_priv)) -+ priv_size = sizeof(struct mtk_eth_switch_priv); -+ -+ priv->swpriv = calloc(1, priv_size); -+ if (!priv->swpriv) { -+ printf("Error: no memory for switch data\n"); -+ return -ENOMEM; -+ } -+ -+ priv->swpriv->eth = priv; -+ priv->swpriv->soc = priv->soc; -+ priv->swpriv->phy_interface = priv->phy_interface; -+ priv->swpriv->sw = swdrv; -+ priv->swpriv->ethsys_base = regmap_get_range(priv->ethsys_regmap, 0); -+ -+ ret = swdrv->setup(priv->swpriv); -+ if (ret) { -+ free(priv->swpriv); -+ priv->swpriv = NULL; -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv) -+{ -+ u16 lcl_adv = 0, rmt_adv = 0; -+ u8 flowctrl; -+ u32 mcr; -+ -+ mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id)); -+ mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC); -+ -+ if (priv->phydev->duplex) { -+ if (priv->phydev->pause) -+ rmt_adv = LPA_PAUSE_CAP; -+ if (priv->phydev->asym_pause) -+ rmt_adv |= LPA_PAUSE_ASYM; -+ -+ if (priv->phydev->advertising & ADVERTISED_Pause) -+ lcl_adv |= ADVERTISE_PAUSE_CAP; -+ if (priv->phydev->advertising & ADVERTISED_Asym_Pause) -+ lcl_adv |= ADVERTISE_PAUSE_ASYM; -+ -+ flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); -+ -+ if (flowctrl & FLOW_CTRL_TX) -+ mcr |= XGMAC_FORCE_TX_FC; -+ if (flowctrl & FLOW_CTRL_RX) -+ mcr |= XGMAC_FORCE_RX_FC; -+ -+ debug("rx pause %s, tx pause %s\n", -+ flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", -+ flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); -+ } -+ -+ mcr &= ~(XGMAC_TRX_DISABLE); -+ mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr); -+} -+ -+static void mtk_phy_link_adjust(struct mtk_eth_priv *priv) -+{ -+ u16 lcl_adv = 0, rmt_adv = 0; -+ u8 flowctrl; -+ u32 mcr; -+ -+ mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | -+ (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) | -+ MAC_MODE | FORCE_MODE | -+ MAC_TX_EN | MAC_RX_EN | -+ DEL_RXFIFO_CLR | -+ BKOFF_EN | BACKPR_EN; -+ -+ switch (priv->phydev->speed) { -+ case SPEED_10: -+ mcr |= (SPEED_10M << FORCE_SPD_S); -+ break; -+ case SPEED_100: -+ mcr |= (SPEED_100M << FORCE_SPD_S); -+ break; -+ case SPEED_1000: -+ case SPEED_2500: -+ mcr |= (SPEED_1000M << FORCE_SPD_S); -+ break; -+ }; -+ -+ if (priv->phydev->link) -+ mcr |= FORCE_LINK; -+ -+ if (priv->phydev->duplex) { -+ mcr |= FORCE_DPX; -+ -+ if (priv->phydev->pause) -+ rmt_adv = LPA_PAUSE_CAP; -+ if (priv->phydev->asym_pause) -+ rmt_adv |= LPA_PAUSE_ASYM; -+ -+ if (priv->phydev->advertising & ADVERTISED_Pause) -+ lcl_adv |= ADVERTISE_PAUSE_CAP; -+ if (priv->phydev->advertising & ADVERTISED_Asym_Pause) -+ lcl_adv |= ADVERTISE_PAUSE_ASYM; -+ -+ flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); -+ -+ if (flowctrl & FLOW_CTRL_TX) -+ mcr |= FORCE_TX_FC; -+ if (flowctrl & FLOW_CTRL_RX) -+ mcr |= FORCE_RX_FC; -+ -+ debug("rx pause %s, tx pause %s\n", -+ flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", -+ flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); -+ } -+ -+ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); -+} -+ -+static int mtk_phy_start(struct mtk_eth_priv *priv) -+{ -+ struct phy_device *phydev = priv->phydev; -+ int ret; -+ -+ ret = phy_startup(phydev); -+ -+ if (ret) { -+ debug("Could not initialize PHY %s\n", phydev->dev->name); -+ return ret; -+ } -+ -+ if (!phydev->link) { -+ debug("%s: link down.\n", phydev->dev->name); -+ return 0; -+ } -+ -+ if (!priv->force_mode) { -+ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || -+ priv->phy_interface == PHY_INTERFACE_MODE_XGMII) -+ mtk_xphy_link_adjust(priv); -+ else -+ mtk_phy_link_adjust(priv); -+ } -+ -+ debug("Speed: %d, %s duplex%s\n", phydev->speed, -+ (phydev->duplex) ? "full" : "half", -+ (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); -+ -+ return 0; -+} -+ -+static int mtk_phy_probe(struct udevice *dev) -+{ -+ struct mtk_eth_priv *priv = dev_get_priv(dev); -+ struct phy_device *phydev; -+ -+ phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev, -+ priv->phy_interface); -+ if (!phydev) -+ return -ENODEV; -+ -+ phydev->supported &= PHY_GBIT_FEATURES; -+ phydev->advertising = phydev->supported; -+ -+ priv->phydev = phydev; -+ phy_config(phydev); -+ -+ return 0; -+} -+ -+static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) -+{ -+ /* Set SGMII GEN1 speed(1G) */ -+ clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK); -+ -+ /* Enable SGMII AN */ -+ setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, -+ SGMII_AN_ENABLE); -+ -+ /* SGMII AN mode setting */ -+ writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); -+ -+ /* SGMII PN SWAP setting */ -+ if (priv->pn_swap) { -+ setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL, -+ SGMII_PN_SWAP_TX_RX); -+ } -+ -+ /* Release PHYA power down state */ -+ clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, -+ SGMII_PHYA_PWD, 0); -+} -+ -+static void mtk_sgmii_force_init(struct mtk_eth_priv *priv) -+{ -+ /* Set SGMII GEN2 speed(2.5G) */ -+ clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, -+ SGMSYS_SPEED_MASK, -+ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); -+ -+ /* Disable SGMII AN */ -+ clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, -+ SGMII_AN_ENABLE, 0); -+ -+ /* SGMII force mode setting */ -+ writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); -+ -+ /* SGMII PN SWAP setting */ -+ if (priv->pn_swap) { -+ setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL, -+ SGMII_PN_SWAP_TX_RX); -+ } -+ -+ /* Release PHYA power down state */ -+ clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, -+ SGMII_PHYA_PWD, 0); -+} -+ -+static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv) -+{ -+ u32 val = 0; -+ -+ /* Add software workaround for USXGMII PLL TCL issue */ -+ regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8, -+ RG_XFI_PLL_ANA_SWWA); -+ -+ regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val); -+ val |= RG_XFI_PLL_EN; -+ regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val); -+} -+ -+static void mtk_usxgmii_reset(struct mtk_eth_priv *priv) -+{ -+ switch (priv->gmac_id) { -+ case 1: -+ regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004); -+ regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004); -+ regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000); -+ regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000); -+ regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000); -+ break; -+ case 2: -+ regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002); -+ regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002); -+ regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000); -+ regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000); -+ regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000); -+ break; -+ } -+ -+ mdelay(10); -+} -+ -+static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv) -+{ -+ regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D); -+ regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); -+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000); -+ ndelay(1020); -+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000); -+ ndelay(1020); -+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000); -+ -+ regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); -+ regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); -+ regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); -+ regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); -+ regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); -+ regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); -+ regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); -+ regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); -+ regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); -+ regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); -+ regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); -+ regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); -+ regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); -+ regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); -+ regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); -+ regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); -+ regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); -+ regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); -+ regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); -+ regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); -+ regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); -+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); -+ regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); -+ ndelay(1020); -+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); -+ regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); -+ regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); -+ regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); -+ regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); -+ regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); -+ regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); -+ regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000); -+ regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000); -+ regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA); -+ regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); -+ regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); -+ regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); -+ udelay(150); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); -+ udelay(15); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); -+ ndelay(1020); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); -+ udelay(100); -+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); -+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); -+ regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv) -+{ -+ regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C); -+ regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); -+ regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000); -+ ndelay(1020); -+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000); -+ ndelay(1020); -+ -+ regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); -+ regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); -+ regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); -+ regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); -+ regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); -+ regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); -+ regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); -+ regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); -+ regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); -+ regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); -+ regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); -+ regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); -+ regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); -+ regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); -+ regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); -+ regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); -+ regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); -+ regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); -+ regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); -+ regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); -+ regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); -+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); -+ regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); -+ ndelay(1020); -+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); -+ regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); -+ regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); -+ regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); -+ regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); -+ regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); -+ regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); -+ regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100); -+ regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000); -+ regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000); -+ regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); -+ if (priv->gmac_id == 2) -+ regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400); -+ regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); -+ regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); -+ udelay(150); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); -+ udelay(15); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); -+ ndelay(1020); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); -+ udelay(100); -+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); -+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); -+ regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) -+{ -+ mtk_xfi_pll_enable(priv); -+ mtk_usxgmii_reset(priv); -+ mtk_usxgmii_setup_phya_an_10000(priv); -+} -+ -+static void mtk_10gbaser_init(struct mtk_eth_priv *priv) -+{ -+ mtk_xfi_pll_enable(priv); -+ mtk_usxgmii_reset(priv); -+ mtk_usxgmii_setup_phya_force_10000(priv); -+} -+ -+static int mtk_mac_init(struct mtk_eth_priv *priv) -+{ -+ int i, sgmii_sel_mask = 0, ge_mode = 0; -+ u32 mcr; -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) { -+ mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG, -+ INFRA_MISC2_BONDING_OPTION, priv->gmac_id); -+ } -+ -+ switch (priv->phy_interface) { -+ case PHY_INTERFACE_MODE_RGMII_RXID: -+ case PHY_INTERFACE_MODE_RGMII: -+ ge_mode = GE_MODE_RGMII; -+ break; -+ case PHY_INTERFACE_MODE_SGMII: -+ case PHY_INTERFACE_MODE_2500BASEX: -+ if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { -+ printf("Error: SGMII is not supported on this platform\n"); -+ return -ENOTSUPP; -+ } -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) { -+ mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK, -+ SGMII_QPHY_SEL); -+ } -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) -+ sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; -+ -+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask, -+ SYSCFG1_SGMII_SEL(priv->gmac_id)); -+ -+ if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) -+ mtk_sgmii_an_init(priv); -+ else -+ mtk_sgmii_force_init(priv); -+ -+ ge_mode = GE_MODE_RGMII; -+ break; -+ case PHY_INTERFACE_MODE_MII: -+ case PHY_INTERFACE_MODE_GMII: -+ ge_mode = GE_MODE_MII; -+ break; -+ case PHY_INTERFACE_MODE_RMII: -+ ge_mode = GE_MODE_RMII; -+ break; -+ default: -+ break; -+ } -+ -+ /* set the gmac to the right mode */ -+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, -+ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), -+ ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id)); -+ -+ if (priv->force_mode) { -+ mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | -+ (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) | -+ MAC_MODE | FORCE_MODE | -+ MAC_TX_EN | MAC_RX_EN | -+ BKOFF_EN | BACKPR_EN | -+ FORCE_LINK; -+ -+ switch (priv->speed) { -+ case SPEED_10: -+ mcr |= SPEED_10M << FORCE_SPD_S; -+ break; -+ case SPEED_100: -+ mcr |= SPEED_100M << FORCE_SPD_S; -+ break; -+ case SPEED_1000: -+ case SPEED_2500: -+ mcr |= SPEED_1000M << FORCE_SPD_S; -+ break; -+ } -+ -+ if (priv->duplex) -+ mcr |= FORCE_DPX; -+ -+ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); -+ } -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC1_TRGMII) && -+ !MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) { -+ /* Lower Tx Driving for TRGMII path */ -+ for (i = 0 ; i < NUM_TRGMII_CTRL; i++) -+ mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i), -+ (8 << TD_DM_DRVP_S) | -+ (8 << TD_DM_DRVN_S)); -+ -+ mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0, -+ RX_RST | RXC_DQSISEL); -+ mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0); -+ } -+ -+ return 0; -+} -+ -+static int mtk_xmac_init(struct mtk_eth_priv *priv) -+{ -+ u32 force_link = 0; -+ -+ if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { -+ printf("Error: 10Gb interface is not supported on this platform\n"); -+ return -ENOTSUPP; -+ } -+ -+ switch (priv->phy_interface) { -+ case PHY_INTERFACE_MODE_USXGMII: -+ mtk_usxgmii_an_init(priv); -+ break; -+ case PHY_INTERFACE_MODE_10GBASER: -+ mtk_10gbaser_init(priv); -+ break; -+ default: -+ break; -+ } -+ -+ /* Set GMAC to the correct mode */ -+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, -+ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), -+ 0); -+ -+ if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && -+ priv->gmac_id == 1) { -+ mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX, -+ NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL); -+ } -+ -+ if (priv->phy_interface == PHY_INTERFACE_MODE_XGMII || -+ priv->gmac_id == 2) -+ force_link = XGMAC_FORCE_LINK(priv->gmac_id); -+ -+ mtk_gmac_rmw(priv, XGMAC_STS(priv->gmac_id), -+ XGMAC_FORCE_LINK(priv->gmac_id), force_link); -+ -+ /* Force GMAC link down */ -+ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE); -+ -+ return 0; -+} -+ -+static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) -+{ -+ char *pkt_base = priv->pkt_pool; -+ struct mtk_tx_dma_v2 *txd; -+ struct mtk_rx_dma_v2 *rxd; -+ int i; -+ -+ mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0); -+ udelay(500); -+ -+ memset(priv->tx_ring_noc, 0, NUM_TX_DESC * priv->soc->txd_size); -+ memset(priv->rx_ring_noc, 0, NUM_RX_DESC * priv->soc->rxd_size); -+ memset(priv->pkt_pool, 0xff, TOTAL_PKT_BUF_SIZE); -+ -+ flush_dcache_range((ulong)pkt_base, -+ (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE)); -+ -+ priv->rx_dma_owner_idx0 = 0; -+ priv->tx_cpu_owner_idx0 = 0; -+ -+ for (i = 0; i < NUM_TX_DESC; i++) { -+ txd = priv->tx_ring_noc + i * priv->soc->txd_size; -+ -+ txd->txd1 = virt_to_phys(pkt_base); -+ txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0; -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -+ txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ? -+ 15 : priv->gmac_id + 1); -+ else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1); -+ else -+ txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1); -+ -+ pkt_base += PKTSIZE_ALIGN; -+ } -+ -+ for (i = 0; i < NUM_RX_DESC; i++) { -+ rxd = priv->rx_ring_noc + i * priv->soc->rxd_size; -+ -+ rxd->rxd1 = virt_to_phys(pkt_base); -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -+ rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -+ else -+ rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -+ -+ pkt_base += PKTSIZE_ALIGN; -+ } -+ -+ mtk_pdma_write(priv, TX_BASE_PTR_REG(0), -+ virt_to_phys(priv->tx_ring_noc)); -+ mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC); -+ mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); -+ -+ mtk_pdma_write(priv, RX_BASE_PTR_REG(0), -+ virt_to_phys(priv->rx_ring_noc)); -+ mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC); -+ mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1); -+ -+ mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0); -+} -+ -+static void mtk_eth_mdc_init(struct mtk_eth_priv *priv) -+{ -+ u32 divider; -+ -+ if (priv->mdc == 0) -+ return; -+ -+ divider = min_t(u32, DIV_ROUND_UP(MDC_MAX_FREQ, priv->mdc), MDC_MAX_DIVIDER); -+ -+ /* Configure MDC turbo mode */ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -+ mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, MISC_MDC_TURBO); -+ else -+ mtk_gmac_rmw(priv, GMAC_PPSC_REG, 0, MISC_MDC_TURBO); -+ -+ /* Configure MDC divider */ -+ mtk_gmac_rmw(priv, GMAC_PPSC_REG, PHY_MDC_CFG, -+ FIELD_PREP(PHY_MDC_CFG, divider)); -+} -+ -+static int mtk_eth_start(struct udevice *dev) -+{ -+ struct mtk_eth_priv *priv = dev_get_priv(dev); -+ int i, ret; -+ -+ /* Reset FE */ -+ reset_assert(&priv->rst_fe); -+ udelay(1000); -+ reset_deassert(&priv->rst_fe); -+ mdelay(10); -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -+ setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2); -+ -+ /* Packets forward to PDMA */ -+ mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU); -+ -+ for (i = 0; i < priv->soc->gdma_count; i++) { -+ if (i == priv->gmac_id) -+ continue; -+ -+ mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); -+ } -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) { -+ if (priv->swpriv && !strcmp(priv->swpriv->sw->name, "mt7988") && -+ priv->gmac_id == 0) { -+ mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, -+ GDMA_BRIDGE_TO_CPU); -+ -+ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, -+ GDMA_CPU_BRIDGE_EN); -+ } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || -+ priv->phy_interface == PHY_INTERFACE_MODE_XGMII) && -+ priv->gmac_id != 0) { -+ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, -+ GDMA_CPU_BRIDGE_EN); -+ } -+ } -+ -+ udelay(500); -+ -+ mtk_eth_fifo_init(priv); -+ -+ if (priv->swpriv) { -+ /* Enable communication with switch */ -+ if (priv->swpriv->sw->mac_control) -+ priv->swpriv->sw->mac_control(priv->swpriv, true); -+ } else { -+ /* Start PHY */ -+ ret = mtk_phy_start(priv); -+ if (ret) -+ return ret; -+ } -+ -+ mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0, -+ TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); -+ udelay(500); -+ -+ return 0; -+} -+ -+static void mtk_eth_stop(struct udevice *dev) -+{ -+ struct mtk_eth_priv *priv = dev_get_priv(dev); -+ -+ if (priv->swpriv) { -+ if (priv->swpriv->sw->mac_control) -+ priv->swpriv->sw->mac_control(priv->swpriv, false); -+ } -+ -+ mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, -+ TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0); -+ udelay(500); -+ -+ wait_for_bit_le32(priv->fe_base + priv->soc->pdma_base + PDMA_GLO_CFG_REG, -+ RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0); -+} -+ -+static int mtk_eth_write_hwaddr(struct udevice *dev) -+{ -+ struct eth_pdata *pdata = dev_get_plat(dev); -+ struct mtk_eth_priv *priv = dev_get_priv(dev); -+ unsigned char *mac = pdata->enetaddr; -+ u32 macaddr_lsb, macaddr_msb; -+ -+ macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1]; -+ macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) | -+ ((u32)mac[4] << 8) | (u32)mac[5]; -+ -+ mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb); -+ mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb); -+ -+ return 0; -+} -+ -+static int mtk_eth_send(struct udevice *dev, void *packet, int length) -+{ -+ struct mtk_eth_priv *priv = dev_get_priv(dev); -+ u32 idx = priv->tx_cpu_owner_idx0; -+ struct mtk_tx_dma_v2 *txd; -+ void *pkt_base; -+ -+ txd = priv->tx_ring_noc + idx * priv->soc->txd_size; -+ -+ if (!(txd->txd2 & PDMA_TXD2_DDONE)) { -+ debug("mtk-eth: TX DMA descriptor ring is full\n"); -+ return -EPERM; -+ } -+ -+ pkt_base = (void *)phys_to_virt(txd->txd1); -+ memcpy(pkt_base, packet, length); -+ flush_dcache_range((ulong)pkt_base, (ulong)pkt_base + -+ roundup(length, ARCH_DMA_MINALIGN)); -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -+ txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length); -+ else -+ txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length); -+ -+ priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; -+ mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); -+ -+ return 0; -+} -+ -+static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp) -+{ -+ struct mtk_eth_priv *priv = dev_get_priv(dev); -+ u32 idx = priv->rx_dma_owner_idx0; -+ struct mtk_rx_dma_v2 *rxd; -+ uchar *pkt_base; -+ u32 length; -+ -+ rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; -+ -+ if (!(rxd->rxd2 & PDMA_RXD2_DDONE)) { -+ debug("mtk-eth: RX DMA descriptor ring is empty\n"); -+ return -EAGAIN; -+ } -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -+ length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2); -+ else -+ length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2); -+ -+ pkt_base = (void *)phys_to_virt(rxd->rxd1); -+ invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base + -+ roundup(length, ARCH_DMA_MINALIGN)); -+ -+ if (packetp) -+ *packetp = pkt_base; -+ -+ return length; -+} -+ -+static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length) -+{ -+ struct mtk_eth_priv *priv = dev_get_priv(dev); -+ u32 idx = priv->rx_dma_owner_idx0; -+ struct mtk_rx_dma_v2 *rxd; -+ -+ rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; -+ -+ invalidate_dcache_range((ulong)rxd->rxd1, -+ (ulong)rxd->rxd1 + PKTSIZE_ALIGN); -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -+ rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -+ else -+ rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -+ -+ mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx); -+ priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC; -+ -+ return 0; -+} -+ -+static int mtk_eth_probe(struct udevice *dev) -+{ -+ struct eth_pdata *pdata = dev_get_plat(dev); -+ struct mtk_eth_priv *priv = dev_get_priv(dev); -+ ulong iobase = pdata->iobase; -+ int ret; -+ -+ /* Frame Engine Register Base */ -+ priv->fe_base = (void *)iobase; -+ -+ /* GMAC Register Base */ -+ priv->gmac_base = (void *)(iobase + GMAC_BASE); -+ -+ /* MDIO register */ -+ ret = mtk_mdio_register(dev); -+ if (ret) -+ return ret; -+ -+ /* Prepare for tx/rx rings */ -+ priv->tx_ring_noc = (void *) -+ noncached_alloc(priv->soc->txd_size * NUM_TX_DESC, -+ ARCH_DMA_MINALIGN); -+ priv->rx_ring_noc = (void *) -+ noncached_alloc(priv->soc->rxd_size * NUM_RX_DESC, -+ ARCH_DMA_MINALIGN); -+ -+ /* Set MDC divider */ -+ mtk_eth_mdc_init(priv); -+ -+ /* Set MAC mode */ -+ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || -+ priv->phy_interface == PHY_INTERFACE_MODE_XGMII) -+ ret = mtk_xmac_init(priv); -+ else -+ ret = mtk_mac_init(priv); -+ -+ if (ret) -+ return ret; -+ -+ /* Probe phy if switch is not specified */ -+ if (!priv->swname) -+ return mtk_phy_probe(dev); -+ -+ /* Initialize switch */ -+ return mtk_switch_init(priv); -+} -+ -+static int mtk_eth_remove(struct udevice *dev) -+{ -+ struct mtk_eth_priv *priv = dev_get_priv(dev); -+ -+ /* MDIO unregister */ -+ mdio_unregister(priv->mdio_bus); -+ mdio_free(priv->mdio_bus); -+ -+ /* Stop possibly started DMA */ -+ mtk_eth_stop(dev); -+ -+ if (priv->swpriv) { -+ if (priv->swpriv->sw->cleanup) -+ priv->swpriv->sw->cleanup(priv->swpriv); -+ free(priv->swpriv); -+ } -+ -+ return 0; -+} -+ -+static int mtk_eth_of_to_plat(struct udevice *dev) -+{ -+ struct eth_pdata *pdata = dev_get_plat(dev); -+ struct mtk_eth_priv *priv = dev_get_priv(dev); -+ struct ofnode_phandle_args args; -+ struct regmap *regmap; -+ ofnode subnode; -+ int ret; -+ -+ priv->soc = (const struct mtk_soc_data *)dev_get_driver_data(dev); -+ if (!priv->soc) { -+ dev_err(dev, "missing soc compatible data\n"); -+ return -EINVAL; -+ } -+ -+ pdata->iobase = (phys_addr_t)dev_remap_addr(dev); -+ -+ /* get corresponding ethsys phandle */ -+ ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0, -+ &args); -+ if (ret) -+ return ret; -+ -+ priv->ethsys_regmap = syscon_node_to_regmap(args.node); -+ if (IS_ERR(priv->ethsys_regmap)) -+ return PTR_ERR(priv->ethsys_regmap); -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) { -+ /* get corresponding infracfg phandle */ -+ ret = dev_read_phandle_with_args(dev, "mediatek,infracfg", -+ NULL, 0, 0, &args); -+ -+ if (ret) -+ return ret; -+ -+ priv->infra_regmap = syscon_node_to_regmap(args.node); -+ if (IS_ERR(priv->infra_regmap)) -+ return PTR_ERR(priv->infra_regmap); -+ } -+ -+ /* Reset controllers */ -+ ret = reset_get_by_name(dev, "fe", &priv->rst_fe); -+ if (ret) { -+ printf("error: Unable to get reset ctrl for frame engine\n"); -+ return ret; -+ } -+ -+ priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0); -+ -+ priv->mdc = 0; -+ subnode = ofnode_find_subnode(dev_ofnode(dev), "mdio"); -+ if (ofnode_valid(subnode)) { -+ priv->mdc = ofnode_read_u32_default(subnode, "clock-frequency", 2500000); -+ if (priv->mdc > MDC_MAX_FREQ || -+ priv->mdc < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { -+ printf("error: MDIO clock frequency out of range\n"); -+ return -EINVAL; -+ } -+ } -+ -+ /* Interface mode is required */ -+ pdata->phy_interface = dev_read_phy_mode(dev); -+ priv->phy_interface = pdata->phy_interface; -+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) { -+ printf("error: phy-mode is not set\n"); -+ return -EINVAL; -+ } -+ -+ /* Force mode or autoneg */ -+ subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link"); -+ if (ofnode_valid(subnode)) { -+ priv->force_mode = 1; -+ priv->speed = ofnode_read_u32_default(subnode, "speed", 0); -+ priv->duplex = ofnode_read_bool(subnode, "full-duplex"); -+ -+ if (priv->speed != SPEED_10 && priv->speed != SPEED_100 && -+ priv->speed != SPEED_1000 && priv->speed != SPEED_2500 && -+ priv->speed != SPEED_10000) { -+ printf("error: no valid speed set in fixed-link\n"); -+ return -EINVAL; -+ } -+ } -+ -+ if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) && -+ IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { -+ /* get corresponding sgmii phandle */ -+ ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", -+ NULL, 0, 0, &args); -+ if (ret) -+ return ret; -+ -+ regmap = syscon_node_to_regmap(args.node); -+ -+ if (IS_ERR(regmap)) -+ return PTR_ERR(regmap); -+ -+ priv->sgmii_base = regmap_get_range(regmap, 0); -+ -+ if (!priv->sgmii_base) { -+ dev_err(dev, "Unable to find sgmii\n"); -+ return -ENODEV; -+ } -+ -+ /* Upstream linux use mediatek,pnswap instead of pn_swap */ -+ priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || -+ ofnode_read_bool(args.node, "mediatek,pnswap"); -+ } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && -+ IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { -+ /* get corresponding usxgmii phandle */ -+ ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", -+ NULL, 0, 0, &args); -+ if (ret) -+ return ret; -+ -+ priv->usxgmii_regmap = syscon_node_to_regmap(args.node); -+ if (IS_ERR(priv->usxgmii_regmap)) -+ return PTR_ERR(priv->usxgmii_regmap); -+ -+ /* get corresponding xfi_pextp phandle */ -+ ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp", -+ NULL, 0, 0, &args); -+ if (ret) -+ return ret; -+ -+ priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node); -+ if (IS_ERR(priv->xfi_pextp_regmap)) -+ return PTR_ERR(priv->xfi_pextp_regmap); -+ -+ /* get corresponding xfi_pll phandle */ -+ ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll", -+ NULL, 0, 0, &args); -+ if (ret) -+ return ret; -+ -+ priv->xfi_pll_regmap = syscon_node_to_regmap(args.node); -+ if (IS_ERR(priv->xfi_pll_regmap)) -+ return PTR_ERR(priv->xfi_pll_regmap); -+ -+ /* get corresponding toprgu phandle */ -+ ret = dev_read_phandle_with_args(dev, "mediatek,toprgu", -+ NULL, 0, 0, &args); -+ if (ret) -+ return ret; -+ -+ priv->toprgu_regmap = syscon_node_to_regmap(args.node); -+ if (IS_ERR(priv->toprgu_regmap)) -+ return PTR_ERR(priv->toprgu_regmap); -+ } -+ -+ priv->swname = dev_read_string(dev, "mediatek,switch"); -+ if (priv->swname) { -+ priv->mcm = dev_read_bool(dev, "mediatek,mcm"); -+ if (priv->mcm) { -+ ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm); -+ if (ret) { -+ printf("error: no reset ctrl for mcm\n"); -+ return ret; -+ } -+ } else { -+ gpio_request_by_name(dev, "reset-gpios", 0, -+ &priv->rst_gpio, GPIOD_IS_OUT); -+ } -+ } else { -+ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, -+ 0, &args); -+ if (ret) { -+ printf("error: phy-handle is not specified\n"); -+ return ret; -+ } -+ -+ priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1); -+ if (priv->phy_addr < 0) { -+ printf("error: phy address is not specified\n"); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+static const struct mtk_soc_data mt7988_data = { -+ .caps = MT7988_CAPS, -+ .ana_rgc3 = 0x128, -+ .gdma_count = 3, -+ .pdma_base = PDMA_V3_BASE, -+ .txd_size = sizeof(struct mtk_tx_dma_v2), -+ .rxd_size = sizeof(struct mtk_rx_dma_v2), -+}; -+ -+static const struct mtk_soc_data mt7986_data = { -+ .caps = MT7986_CAPS, -+ .ana_rgc3 = 0x128, -+ .gdma_count = 2, -+ .pdma_base = PDMA_V2_BASE, -+ .txd_size = sizeof(struct mtk_tx_dma_v2), -+ .rxd_size = sizeof(struct mtk_rx_dma_v2), -+}; -+ -+static const struct mtk_soc_data mt7981_data = { -+ .caps = MT7981_CAPS, -+ .ana_rgc3 = 0x128, -+ .gdma_count = 2, -+ .pdma_base = PDMA_V2_BASE, -+ .txd_size = sizeof(struct mtk_tx_dma_v2), -+ .rxd_size = sizeof(struct mtk_rx_dma_v2), -+}; -+ -+static const struct mtk_soc_data mt7629_data = { -+ .caps = MT7629_CAPS, -+ .ana_rgc3 = 0x128, -+ .gdma_count = 2, -+ .pdma_base = PDMA_V1_BASE, -+ .txd_size = sizeof(struct mtk_tx_dma), -+ .rxd_size = sizeof(struct mtk_rx_dma), -+}; -+ -+static const struct mtk_soc_data mt7623_data = { -+ .caps = MT7623_CAPS, -+ .gdma_count = 2, -+ .pdma_base = PDMA_V1_BASE, -+ .txd_size = sizeof(struct mtk_tx_dma), -+ .rxd_size = sizeof(struct mtk_rx_dma), -+}; -+ -+static const struct mtk_soc_data mt7622_data = { -+ .caps = MT7622_CAPS, -+ .ana_rgc3 = 0x2028, -+ .gdma_count = 2, -+ .pdma_base = PDMA_V1_BASE, -+ .txd_size = sizeof(struct mtk_tx_dma), -+ .rxd_size = sizeof(struct mtk_rx_dma), -+}; -+ -+static const struct mtk_soc_data mt7621_data = { -+ .caps = MT7621_CAPS, -+ .gdma_count = 2, -+ .pdma_base = PDMA_V1_BASE, -+ .txd_size = sizeof(struct mtk_tx_dma), -+ .rxd_size = sizeof(struct mtk_rx_dma), -+}; -+ -+static const struct udevice_id mtk_eth_ids[] = { -+ { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data }, -+ { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data }, -+ { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data }, -+ { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, -+ { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data }, -+ { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data }, -+ { .compatible = "mediatek,mt7621-eth", .data = (ulong)&mt7621_data }, -+ {} -+}; -+ -+static const struct eth_ops mtk_eth_ops = { -+ .start = mtk_eth_start, -+ .stop = mtk_eth_stop, -+ .send = mtk_eth_send, -+ .recv = mtk_eth_recv, -+ .free_pkt = mtk_eth_free_pkt, -+ .write_hwaddr = mtk_eth_write_hwaddr, -+}; -+ -+U_BOOT_DRIVER(mtk_eth) = { -+ .name = "mtk-eth", -+ .id = UCLASS_ETH, -+ .of_match = mtk_eth_ids, -+ .of_to_plat = mtk_eth_of_to_plat, -+ .plat_auto = sizeof(struct eth_pdata), -+ .probe = mtk_eth_probe, -+ .remove = mtk_eth_remove, -+ .ops = &mtk_eth_ops, -+ .priv_auto = sizeof(struct mtk_eth_priv), -+ .flags = DM_FLAG_ALLOC_PRIV_DMA, -+}; ---- a/drivers/net/mtk_eth.h -+++ /dev/null -@@ -1,600 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0 */ --/* -- * Copyright (C) 2018 MediaTek Inc. -- * -- * Author: Weijie Gao -- * Author: Mark Lee -- */ -- --#ifndef _MTK_ETH_H_ --#define _MTK_ETH_H_ -- --#include --#include -- --enum mkt_eth_capabilities { -- MTK_TRGMII_BIT, -- MTK_TRGMII_MT7621_CLK_BIT, -- MTK_U3_COPHY_V2_BIT, -- MTK_INFRA_BIT, -- MTK_NETSYS_V2_BIT, -- MTK_NETSYS_V3_BIT, -- -- /* PATH BITS */ -- MTK_ETH_PATH_GMAC1_TRGMII_BIT, -- MTK_ETH_PATH_GMAC2_SGMII_BIT, -- MTK_ETH_PATH_MT7622_SGMII_BIT, -- MTK_ETH_PATH_MT7629_GMAC2_BIT, --}; -- --#define MTK_TRGMII BIT(MTK_TRGMII_BIT) --#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) --#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) --#define MTK_INFRA BIT(MTK_INFRA_BIT) --#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) --#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) -- --/* Supported path present on SoCs */ --#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) -- --#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) --#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) --#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) -- --#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) -- --#define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA) -- --#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) -- --#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) -- --#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII) -- --#define MT7623_CAPS (MTK_GMAC1_TRGMII) -- --#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA) -- --#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) -- --#define MT7986_CAPS (MTK_NETSYS_V2) -- --#define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA) -- --/* Frame Engine Register Bases */ --#define PDMA_V1_BASE 0x0800 --#define PDMA_V2_BASE 0x6000 --#define PDMA_V3_BASE 0x6800 --#define GDMA1_BASE 0x0500 --#define GDMA2_BASE 0x1500 --#define GDMA3_BASE 0x0540 --#define GMAC_BASE 0x10000 --#define GSW_BASE 0x20000 -- --/* Ethernet subsystem registers */ -- --#define ETHSYS_SYSCFG1_REG 0x14 --#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) --#define SYSCFG1_GE_MODE_M 0x3 --#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8) --#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac)) -- --#define ETHSYS_CLKCFG0_REG 0x2c --#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) -- --/* Top misc registers */ --#define TOPMISC_NETSYS_PCS_MUX 0x84 --#define NETSYS_PCS_MUX_MASK GENMASK(1, 0) --#define MUX_G2_USXGMII_SEL BIT(1) --#define MUX_HSGMII1_G1_SEL BIT(0) -- --#define USB_PHY_SWITCH_REG 0x218 --#define QPHY_SEL_MASK 0x3 --#define SGMII_QPHY_SEL 0x2 -- --#define MT7629_INFRA_MISC2_REG 0x70c --#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0) -- --/* SYSCFG1_GE_MODE: GE Modes */ --#define GE_MODE_RGMII 0 --#define GE_MODE_MII 1 --#define GE_MODE_MII_PHY 2 --#define GE_MODE_RMII 3 -- --/* SGMII subsystem config registers */ --#define SGMSYS_PCS_CONTROL_1 0x0 --#define SGMII_LINK_STATUS BIT(18) --#define SGMII_AN_ENABLE BIT(12) --#define SGMII_AN_RESTART BIT(9) -- --#define SGMSYS_SGMII_MODE 0x20 --#define SGMII_AN_MODE 0x31120103 --#define SGMII_FORCE_MODE 0x31120019 -- --#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 --#define SGMII_PHYA_PWD BIT(4) -- --#define SGMSYS_QPHY_WRAP_CTRL 0xec --#define SGMII_PN_SWAP_TX_RX 0x03 -- --#define SGMSYS_GEN2_SPEED 0x2028 --#define SGMSYS_GEN2_SPEED_V2 0x128 --#define SGMSYS_SPEED_MASK GENMASK(3, 2) --#define SGMSYS_SPEED_2500 1 -- --/* USXGMII subsystem config registers */ --/* Register to control USXGMII XFI PLL digital */ --#define XFI_PLL_DIG_GLB8 0x08 --#define RG_XFI_PLL_EN BIT(31) -- --/* Register to control USXGMII XFI PLL analog */ --#define XFI_PLL_ANA_GLB8 0x108 --#define RG_XFI_PLL_ANA_SWWA 0x02283248 -- --/* Frame Engine Registers */ --#define PSE_NO_DROP_CFG_REG 0x108 --#define PSE_NO_DROP_GDM1 BIT(1) -- --#define FE_GLO_MISC_REG 0x124 --#define PDMA_VER_V2 BIT(4) -- --/* PDMA */ --#define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10) --#define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10) --#define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10) --#define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10) -- --#define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10) --#define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10) --#define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10) --#define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10) -- --#define PDMA_GLO_CFG_REG 0x204 --#define TX_WB_DDONE BIT(6) --#define RX_DMA_BUSY BIT(3) --#define RX_DMA_EN BIT(2) --#define TX_DMA_BUSY BIT(1) --#define TX_DMA_EN BIT(0) -- --#define PDMA_RST_IDX_REG 0x208 --#define RST_DRX_IDX0 BIT(16) --#define RST_DTX_IDX0 BIT(0) -- --/* GDMA */ --#define GDMA_IG_CTRL_REG 0x000 --#define GDM_ICS_EN BIT(22) --#define GDM_TCS_EN BIT(21) --#define GDM_UCS_EN BIT(20) --#define STRP_CRC BIT(16) --#define MYMAC_DP_S 12 --#define MYMAC_DP_M 0xf000 --#define BC_DP_S 8 --#define BC_DP_M 0xf00 --#define MC_DP_S 4 --#define MC_DP_M 0xf0 --#define UN_DP_S 0 --#define UN_DP_M 0x0f -- --#define GDMA_EG_CTRL_REG 0x004 --#define GDMA_CPU_BRIDGE_EN BIT(31) -- --#define GDMA_MAC_LSB_REG 0x008 -- --#define GDMA_MAC_MSB_REG 0x00c -- --/* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */ --#define DP_PDMA 0 --#define DP_GDMA1 1 --#define DP_GDMA2 2 --#define DP_PPE 4 --#define DP_QDMA 5 --#define DP_DISCARD 7 -- --/* GMAC Registers */ -- --#define GMAC_PPSC_REG 0x0000 --#define PHY_MDC_CFG GENMASK(29, 24) --#define MDC_TURBO BIT(20) --#define MDC_MAX_FREQ 25000000 --#define MDC_MAX_DIVIDER 63 -- --#define GMAC_PIAC_REG 0x0004 --#define PHY_ACS_ST BIT(31) --#define MDIO_REG_ADDR_S 25 --#define MDIO_REG_ADDR_M 0x3e000000 --#define MDIO_PHY_ADDR_S 20 --#define MDIO_PHY_ADDR_M 0x1f00000 --#define MDIO_CMD_S 18 --#define MDIO_CMD_M 0xc0000 --#define MDIO_ST_S 16 --#define MDIO_ST_M 0x30000 --#define MDIO_RW_DATA_S 0 --#define MDIO_RW_DATA_M 0xffff -- --#define GMAC_XGMAC_STS_REG 0x000c --#define P1_XGMAC_FORCE_LINK BIT(15) -- --#define GMAC_MAC_MISC_REG 0x0010 --#define MISC_MDC_TURBO BIT(4) -- --#define GMAC_GSW_CFG_REG 0x0080 --#define GSWTX_IPG_M 0xF0000 --#define GSWTX_IPG_S 16 --#define GSWRX_IPG_M 0xF --#define GSWRX_IPG_S 0 -- --/* MDIO_CMD: MDIO commands */ --#define MDIO_CMD_ADDR 0 --#define MDIO_CMD_WRITE 1 --#define MDIO_CMD_READ 2 --#define MDIO_CMD_READ_C45 3 -- --/* MDIO_ST: MDIO start field */ --#define MDIO_ST_C45 0 --#define MDIO_ST_C22 1 -- --#define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100) --#define MAC_RX_PKT_LEN_S 24 --#define MAC_RX_PKT_LEN_M 0x3000000 --#define IPG_CFG_S 18 --#define IPG_CFG_M 0xc0000 --#define MAC_MODE BIT(16) --#define FORCE_MODE BIT(15) --#define MAC_TX_EN BIT(14) --#define MAC_RX_EN BIT(13) --#define DEL_RXFIFO_CLR BIT(12) --#define BKOFF_EN BIT(9) --#define BACKPR_EN BIT(8) --#define FORCE_RX_FC BIT(5) --#define FORCE_TX_FC BIT(4) --#define FORCE_SPD_S 2 --#define FORCE_SPD_M 0x0c --#define FORCE_DPX BIT(1) --#define FORCE_LINK BIT(0) -- --/* Values of IPG_CFG */ --#define IPG_96BIT 0 --#define IPG_96BIT_WITH_SHORT_IPG 1 --#define IPG_64BIT 2 -- --/* MAC_RX_PKT_LEN: Max RX packet length */ --#define MAC_RX_PKT_LEN_1518 0 --#define MAC_RX_PKT_LEN_1536 1 --#define MAC_RX_PKT_LEN_1552 2 --#define MAC_RX_PKT_LEN_JUMBO 3 -- --/* FORCE_SPD: Forced link speed */ --#define SPEED_10M 0 --#define SPEED_100M 1 --#define SPEED_1000M 2 -- --#define GMAC_TRGMII_RCK_CTRL 0x300 --#define RX_RST BIT(31) --#define RXC_DQSISEL BIT(30) -- --#define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8) --#define TD_DM_DRVN_S 4 --#define TD_DM_DRVN_M 0xf0 --#define TD_DM_DRVP_S 0 --#define TD_DM_DRVP_M 0x0f -- --/* XGMAC Status Registers */ --#define XGMAC_STS(x) (((x) == 2) ? 0x001C : 0x000C) --#define XGMAC_FORCE_LINK(x) (((x) == 1) ? BIT(31) : BIT(15)) -- --/* XGMAC Registers */ --#define XGMAC_PORT_MCR(x) (0x2000 + (((x) - 1) * 0x1000)) --#define XGMAC_TRX_DISABLE 0xf --#define XGMAC_FORCE_TX_FC BIT(5) --#define XGMAC_FORCE_RX_FC BIT(4) -- --/* MT7530 Registers */ -- --#define PCR_REG(p) (0x2004 + (p) * 0x100) --#define PORT_MATRIX_S 16 --#define PORT_MATRIX_M 0xff0000 -- --#define PVC_REG(p) (0x2010 + (p) * 0x100) --#define STAG_VPID_S 16 --#define STAG_VPID_M 0xffff0000 --#define VLAN_ATTR_S 6 --#define VLAN_ATTR_M 0xc0 -- --/* VLAN_ATTR: VLAN attributes */ --#define VLAN_ATTR_USER 0 --#define VLAN_ATTR_STACK 1 --#define VLAN_ATTR_TRANSLATION 2 --#define VLAN_ATTR_TRANSPARENT 3 -- --#define PMCR_REG(p) (0x3000 + (p) * 0x100) --/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR -- * MT7531 specific fields are defined below -- */ --#define FORCE_MODE_EEE1G BIT(25) --#define FORCE_MODE_EEE100 BIT(26) --#define FORCE_MODE_TX_FC BIT(27) --#define FORCE_MODE_RX_FC BIT(28) --#define FORCE_MODE_DPX BIT(29) --#define FORCE_MODE_SPD BIT(30) --#define FORCE_MODE_LNK BIT(31) --#define MT7531_FORCE_MODE FORCE_MODE_EEE1G | FORCE_MODE_EEE100 |\ -- FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ -- FORCE_MODE_DPX | FORCE_MODE_SPD | \ -- FORCE_MODE_LNK --#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ -- FORCE_MODE_DPX | FORCE_MODE_SPD | \ -- FORCE_MODE_LNK -- --/* MT7531 SGMII Registers */ --#define MT7531_SGMII_REG_BASE 0x5000 --#define MT7531_SGMII_REG_PORT_BASE 0x1000 --#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ -- (p) * MT7531_SGMII_REG_PORT_BASE + (r)) --#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00) --#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20) --#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8) --#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128) --/* XXX: all fields of MT7531 SGMII are defined under SGMSYS */ -- --/* MT753x System Control Register */ --#define SYS_CTRL_REG 0x7000 --#define SW_PHY_RST BIT(2) --#define SW_SYS_RST BIT(1) --#define SW_REG_RST BIT(0) -- --/* MT7531 */ --#define MT7531_PHY_IAC 0x701c --/* XXX: all fields are defined under GMAC_PIAC_REG */ -- --#define MT7531_CLKGEN_CTRL 0x7500 --#define CLK_SKEW_OUT_S 8 --#define CLK_SKEW_OUT_M 0x300 --#define CLK_SKEW_IN_S 6 --#define CLK_SKEW_IN_M 0xc0 --#define RXCLK_NO_DELAY BIT(5) --#define TXCLK_NO_REVERSE BIT(4) --#define GP_MODE_S 1 --#define GP_MODE_M 0x06 --#define GP_CLK_EN BIT(0) -- --/* Values of GP_MODE */ --#define GP_MODE_RGMII 0 --#define GP_MODE_MII 1 --#define GP_MODE_REV_MII 2 -- --/* Values of CLK_SKEW_IN */ --#define CLK_SKEW_IN_NO_CHANGE 0 --#define CLK_SKEW_IN_DELAY_100PPS 1 --#define CLK_SKEW_IN_DELAY_200PPS 2 --#define CLK_SKEW_IN_REVERSE 3 -- --/* Values of CLK_SKEW_OUT */ --#define CLK_SKEW_OUT_NO_CHANGE 0 --#define CLK_SKEW_OUT_DELAY_100PPS 1 --#define CLK_SKEW_OUT_DELAY_200PPS 2 --#define CLK_SKEW_OUT_REVERSE 3 -- --#define HWTRAP_REG 0x7800 --/* MT7530 Modified Hardware Trap Status Registers */ --#define MHWTRAP_REG 0x7804 --#define CHG_TRAP BIT(16) --#define LOOPDET_DIS BIT(14) --#define P5_INTF_SEL_S 13 --#define P5_INTF_SEL_M 0x2000 --#define SMI_ADDR_S 11 --#define SMI_ADDR_M 0x1800 --#define XTAL_FSEL_S 9 --#define XTAL_FSEL_M 0x600 --#define P6_INTF_DIS BIT(8) --#define P5_INTF_MODE_S 7 --#define P5_INTF_MODE_M 0x80 --#define P5_INTF_DIS BIT(6) --#define C_MDIO_BPS BIT(5) --#define CHIP_MODE_S 0 --#define CHIP_MODE_M 0x0f -- --/* P5_INTF_SEL: Interface type of Port5 */ --#define P5_INTF_SEL_GPHY 0 --#define P5_INTF_SEL_GMAC5 1 -- --/* P5_INTF_MODE: Interface mode of Port5 */ --#define P5_INTF_MODE_GMII_MII 0 --#define P5_INTF_MODE_RGMII 1 -- --#define MT7530_P6ECR 0x7830 --#define P6_INTF_MODE_M 0x3 --#define P6_INTF_MODE_S 0 -- --/* P6_INTF_MODE: Interface mode of Port6 */ --#define P6_INTF_MODE_RGMII 0 --#define P6_INTF_MODE_TRGMII 1 -- --#define NUM_TRGMII_CTRL 5 -- --#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8) --#define RD_TAP_S 0 --#define RD_TAP_M 0x7f -- --#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8) --/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */ -- --/* TOP Signals Status Register */ --#define MT7531_TOP_SIG_SR 0x780c --#define PAD_MCM_SMI_EN BIT(0) --#define PAD_DUAL_SGMII_EN BIT(1) -- --/* MT7531 PLLGP Registers */ --#define MT7531_PLLGP_EN 0x7820 --#define EN_COREPLL BIT(2) --#define SW_CLKSW BIT(1) --#define SW_PLLGP BIT(0) -- --#define MT7531_PLLGP_CR0 0x78a8 --#define RG_COREPLL_EN BIT(22) --#define RG_COREPLL_POSDIV_S 23 --#define RG_COREPLL_POSDIV_M 0x3800000 --#define RG_COREPLL_SDM_PCW_S 1 --#define RG_COREPLL_SDM_PCW_M 0x3ffffe --#define RG_COREPLL_SDM_PCW_CHG BIT(0) -- --/* MT7531 RGMII and SGMII PLL clock */ --#define MT7531_ANA_PLLGP_CR2 0x78b0 --#define MT7531_ANA_PLLGP_CR5 0x78bc -- --/* MT7531 GPIO GROUP IOLB SMT0 Control */ --#define MT7531_SMT0_IOLB 0x7f04 --#define SMT_IOLB_5_SMI_MDC_EN BIT(5) -- --/* MT7530 GPHY MDIO Indirect Access Registers */ --#define MII_MMD_ACC_CTL_REG 0x0d --#define MMD_CMD_S 14 --#define MMD_CMD_M 0xc000 --#define MMD_DEVAD_S 0 --#define MMD_DEVAD_M 0x1f -- --/* MMD_CMD: MMD commands */ --#define MMD_ADDR 0 --#define MMD_DATA 1 --#define MMD_DATA_RW_POST_INC 2 --#define MMD_DATA_W_POST_INC 3 -- --#define MII_MMD_ADDR_DATA_REG 0x0e -- --/* MT7530 GPHY MDIO MMD Registers */ --#define CORE_PLL_GROUP2 0x401 --#define RG_SYSPLL_EN_NORMAL BIT(15) --#define RG_SYSPLL_VODEN BIT(14) --#define RG_SYSPLL_POSDIV_S 5 --#define RG_SYSPLL_POSDIV_M 0x60 -- --#define CORE_PLL_GROUP4 0x403 --#define MT7531_BYPASS_MODE BIT(4) --#define MT7531_POWER_ON_OFF BIT(5) --#define RG_SYSPLL_DDSFBK_EN BIT(12) --#define RG_SYSPLL_BIAS_EN BIT(11) --#define RG_SYSPLL_BIAS_LPF_EN BIT(10) -- --#define CORE_PLL_GROUP5 0x404 --#define RG_LCDDS_PCW_NCPO1_S 0 --#define RG_LCDDS_PCW_NCPO1_M 0xffff -- --#define CORE_PLL_GROUP6 0x405 --#define RG_LCDDS_PCW_NCPO0_S 0 --#define RG_LCDDS_PCW_NCPO0_M 0xffff -- --#define CORE_PLL_GROUP7 0x406 --#define RG_LCDDS_PWDB BIT(15) --#define RG_LCDDS_ISO_EN BIT(13) --#define RG_LCCDS_C_S 4 --#define RG_LCCDS_C_M 0x70 --#define RG_LCDDS_PCW_NCPO_CHG BIT(3) -- --#define CORE_PLL_GROUP10 0x409 --#define RG_LCDDS_SSC_DELTA_S 0 --#define RG_LCDDS_SSC_DELTA_M 0xfff -- --#define CORE_PLL_GROUP11 0x40a --#define RG_LCDDS_SSC_DELTA1_S 0 --#define RG_LCDDS_SSC_DELTA1_M 0xfff -- --#define CORE_GSWPLL_GRP1 0x40d --#define RG_GSWPLL_POSDIV_200M_S 12 --#define RG_GSWPLL_POSDIV_200M_M 0x3000 --#define RG_GSWPLL_EN_PRE BIT(11) --#define RG_GSWPLL_FBKDIV_200M_S 0 --#define RG_GSWPLL_FBKDIV_200M_M 0xff -- --#define CORE_GSWPLL_GRP2 0x40e --#define RG_GSWPLL_POSDIV_500M_S 8 --#define RG_GSWPLL_POSDIV_500M_M 0x300 --#define RG_GSWPLL_FBKDIV_500M_S 0 --#define RG_GSWPLL_FBKDIV_500M_M 0xff -- --#define CORE_TRGMII_GSW_CLK_CG 0x410 --#define REG_GSWCK_EN BIT(0) --#define REG_TRGMIICK_EN BIT(1) -- --/* Extend PHY Control Register 3 */ --#define PHY_EXT_REG_14 0x14 -- --/* Fields of PHY_EXT_REG_14 */ --#define PHY_EN_DOWN_SHFIT BIT(4) -- --/* Extend PHY Control Register 4 */ --#define PHY_EXT_REG_17 0x17 -- --/* Fields of PHY_EXT_REG_17 */ --#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4) -- --/* PHY RXADC Control Register 7 */ --#define PHY_DEV1E_REG_0C6 0x0c6 -- --/* Fields of PHY_DEV1E_REG_0C6 */ --#define PHY_POWER_SAVING_S 8 --#define PHY_POWER_SAVING_M 0x300 --#define PHY_POWER_SAVING_TX 0x0 -- --/* PDMA descriptors */ --struct mtk_rx_dma { -- unsigned int rxd1; -- unsigned int rxd2; -- unsigned int rxd3; -- unsigned int rxd4; --} __packed __aligned(4); -- --struct mtk_rx_dma_v2 { -- unsigned int rxd1; -- unsigned int rxd2; -- unsigned int rxd3; -- unsigned int rxd4; -- unsigned int rxd5; -- unsigned int rxd6; -- unsigned int rxd7; -- unsigned int rxd8; --} __packed __aligned(4); -- --struct mtk_tx_dma { -- unsigned int txd1; -- unsigned int txd2; -- unsigned int txd3; -- unsigned int txd4; --} __packed __aligned(4); -- --struct mtk_tx_dma_v2 { -- unsigned int txd1; -- unsigned int txd2; -- unsigned int txd3; -- unsigned int txd4; -- unsigned int txd5; -- unsigned int txd6; -- unsigned int txd7; -- unsigned int txd8; --} __packed __aligned(4); -- --/* PDMA TXD fields */ --#define PDMA_TXD2_DDONE BIT(31) --#define PDMA_TXD2_LS0 BIT(30) --#define PDMA_V1_TXD2_SDL0_M GENMASK(29, 16) --#define PDMA_V1_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V1_TXD2_SDL0_M, (_v)) --#define PDMA_V2_TXD2_SDL0_M GENMASK(23, 8) --#define PDMA_V2_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V2_TXD2_SDL0_M, (_v)) -- --#define PDMA_V1_TXD4_FPORT_M GENMASK(27, 25) --#define PDMA_V1_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V1_TXD4_FPORT_M, (_v)) --#define PDMA_V2_TXD4_FPORT_M GENMASK(27, 24) --#define PDMA_V2_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD4_FPORT_M, (_v)) -- --#define PDMA_V2_TXD5_FPORT_M GENMASK(19, 16) --#define PDMA_V2_TXD5_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD5_FPORT_M, (_v)) -- --/* PDMA RXD fields */ --#define PDMA_RXD2_DDONE BIT(31) --#define PDMA_RXD2_LS0 BIT(30) --#define PDMA_V1_RXD2_PLEN0_M GENMASK(29, 16) --#define PDMA_V1_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V1_RXD2_PLEN0_M, (_v)) --#define PDMA_V1_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V1_RXD2_PLEN0_M, (_v)) --#define PDMA_V2_RXD2_PLEN0_M GENMASK(23, 8) --#define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v)) --#define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v)) -- --#endif /* _MTK_ETH_H_ */ ---- /dev/null -+++ b/drivers/net/mtk_eth/mtk_eth.h -@@ -0,0 +1,429 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2025 MediaTek Inc. -+ * -+ * Author: Weijie Gao -+ * Author: Mark Lee -+ */ -+ -+#ifndef _MTK_ETH_H_ -+#define _MTK_ETH_H_ -+ -+#include -+#include -+#include -+ -+struct mtk_eth_priv; -+struct mtk_eth_switch_priv; -+ -+/* struct mtk_soc_data - This is the structure holding all differences -+ * among various plaforms -+ * @caps Flags shown the extra capability for the SoC -+ * @ana_rgc3: The offset for register ANA_RGC3 related to -+ * sgmiisys syscon -+ * @gdma_count: Number of GDMAs -+ * @pdma_base: Register base of PDMA block -+ * @txd_size: Tx DMA descriptor size. -+ * @rxd_size: Rx DMA descriptor size. -+ */ -+struct mtk_soc_data { -+ u32 caps; -+ u32 ana_rgc3; -+ u32 gdma_count; -+ u32 pdma_base; -+ u32 txd_size; -+ u32 rxd_size; -+}; -+ -+struct mtk_eth_switch { -+ const char *name; -+ const char *desc; -+ size_t priv_size; -+ u32 reset_wait_time; -+ -+ int (*detect)(struct mtk_eth_priv *priv); -+ int (*setup)(struct mtk_eth_switch_priv *priv); -+ int (*cleanup)(struct mtk_eth_switch_priv *priv); -+ void (*mac_control)(struct mtk_eth_switch_priv *priv, bool enable); -+}; -+ -+#define MTK_ETH_SWITCH(__name) \ -+ ll_entry_declare(struct mtk_eth_switch, __name, mtk_eth_switch) -+ -+struct mtk_eth_switch_priv { -+ struct mtk_eth_priv *eth; -+ const struct mtk_eth_switch *sw; -+ const struct mtk_soc_data *soc; -+ void *ethsys_base; -+ int phy_interface; -+}; -+ -+enum mkt_eth_capabilities { -+ MTK_TRGMII_BIT, -+ MTK_TRGMII_MT7621_CLK_BIT, -+ MTK_U3_COPHY_V2_BIT, -+ MTK_INFRA_BIT, -+ MTK_NETSYS_V2_BIT, -+ MTK_NETSYS_V3_BIT, -+ -+ /* PATH BITS */ -+ MTK_ETH_PATH_GMAC1_TRGMII_BIT, -+ MTK_ETH_PATH_GMAC2_SGMII_BIT, -+ MTK_ETH_PATH_MT7622_SGMII_BIT, -+ MTK_ETH_PATH_MT7629_GMAC2_BIT, -+}; -+ -+#define MTK_TRGMII BIT(MTK_TRGMII_BIT) -+#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) -+#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) -+#define MTK_INFRA BIT(MTK_INFRA_BIT) -+#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) -+#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) -+ -+/* Supported path present on SoCs */ -+#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) -+#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) -+#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) -+#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) -+ -+#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) -+ -+#define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA) -+ -+#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) -+ -+#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) -+ -+#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII) -+ -+#define MT7623_CAPS (MTK_GMAC1_TRGMII) -+ -+#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA) -+ -+#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) -+ -+#define MT7986_CAPS (MTK_NETSYS_V2) -+ -+#define MT7987_CAPS (MTK_NETSYS_V3 | MTK_GMAC2_U3_QPHY | MTK_INFRA) -+ -+#define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA) -+ -+/* Frame Engine Register Bases */ -+#define PDMA_V1_BASE 0x0800 -+#define PDMA_V2_BASE 0x6000 -+#define PDMA_V3_BASE 0x6800 -+#define GDMA1_BASE 0x0500 -+#define GDMA2_BASE 0x1500 -+#define GDMA3_BASE 0x0540 -+#define GMAC_BASE 0x10000 -+#define GSW_BASE 0x20000 -+ -+/* Ethernet subsystem registers */ -+#define ETHSYS_SYSCFG1_REG 0x14 -+#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) -+#define SYSCFG1_GE_MODE_M 0x3 -+#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8) -+#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac)) -+ -+#define ETHSYS_CLKCFG0_REG 0x2c -+#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) -+ -+/* Top misc registers */ -+#define TOPMISC_NETSYS_PCS_MUX 0x84 -+#define NETSYS_PCS_MUX_MASK GENMASK(1, 0) -+#define MUX_G2_USXGMII_SEL BIT(1) -+#define MUX_HSGMII1_G1_SEL BIT(0) -+ -+#define USB_PHY_SWITCH_REG 0x218 -+#define QPHY_SEL_MASK 0x3 -+#define SGMII_QPHY_SEL 0x2 -+ -+#define MT7629_INFRA_MISC2_REG 0x70c -+#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0) -+ -+/* SYSCFG1_GE_MODE: GE Modes */ -+#define GE_MODE_RGMII 0 -+#define GE_MODE_MII 1 -+#define GE_MODE_MII_PHY 2 -+#define GE_MODE_RMII 3 -+ -+/* SGMII subsystem config registers */ -+#define SGMSYS_PCS_CONTROL_1 0x0 -+#define SGMII_LINK_STATUS BIT(18) -+#define SGMII_AN_ENABLE BIT(12) -+#define SGMII_AN_RESTART BIT(9) -+ -+#define SGMSYS_SGMII_MODE 0x20 -+#define SGMII_AN_MODE 0x31120103 -+#define SGMII_FORCE_MODE 0x31120019 -+ -+#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 -+#define SGMII_PHYA_PWD BIT(4) -+ -+#define SGMSYS_QPHY_WRAP_CTRL 0xec -+#define SGMII_PN_SWAP_TX_RX 0x03 -+ -+#define SGMSYS_GEN2_SPEED 0x2028 -+#define SGMSYS_GEN2_SPEED_V2 0x128 -+#define SGMSYS_SPEED_MASK GENMASK(3, 2) -+#define SGMSYS_SPEED_2500 1 -+ -+/* USXGMII subsystem config registers */ -+/* Register to control USXGMII XFI PLL digital */ -+#define XFI_PLL_DIG_GLB8 0x08 -+#define RG_XFI_PLL_EN BIT(31) -+ -+/* Register to control USXGMII XFI PLL analog */ -+#define XFI_PLL_ANA_GLB8 0x108 -+#define RG_XFI_PLL_ANA_SWWA 0x02283248 -+ -+/* Frame Engine Registers */ -+#define PSE_NO_DROP_CFG_REG 0x108 -+#define PSE_NO_DROP_GDM1 BIT(1) -+ -+#define FE_GLO_MISC_REG 0x124 -+#define PDMA_VER_V2 BIT(4) -+ -+/* PDMA */ -+#define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10) -+#define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10) -+#define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10) -+#define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10) -+ -+#define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10) -+#define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10) -+#define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10) -+#define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10) -+ -+#define PDMA_GLO_CFG_REG 0x204 -+#define TX_WB_DDONE BIT(6) -+#define RX_DMA_BUSY BIT(3) -+#define RX_DMA_EN BIT(2) -+#define TX_DMA_BUSY BIT(1) -+#define TX_DMA_EN BIT(0) -+ -+#define PDMA_RST_IDX_REG 0x208 -+#define RST_DRX_IDX0 BIT(16) -+#define RST_DTX_IDX0 BIT(0) -+ -+/* GDMA */ -+#define GDMA_IG_CTRL_REG 0x000 -+#define GDM_ICS_EN BIT(22) -+#define GDM_TCS_EN BIT(21) -+#define GDM_UCS_EN BIT(20) -+#define STRP_CRC BIT(16) -+#define MYMAC_DP_S 12 -+#define MYMAC_DP_M 0xf000 -+#define BC_DP_S 8 -+#define BC_DP_M 0xf00 -+#define MC_DP_S 4 -+#define MC_DP_M 0xf0 -+#define UN_DP_S 0 -+#define UN_DP_M 0x0f -+ -+#define GDMA_EG_CTRL_REG 0x004 -+#define GDMA_CPU_BRIDGE_EN BIT(31) -+ -+#define GDMA_MAC_LSB_REG 0x008 -+ -+#define GDMA_MAC_MSB_REG 0x00c -+ -+/* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */ -+#define DP_PDMA 0 -+#define DP_GDMA1 1 -+#define DP_GDMA2 2 -+#define DP_PPE 4 -+#define DP_QDMA 5 -+#define DP_DISCARD 7 -+ -+/* GMAC Registers */ -+#define GMAC_PPSC_REG 0x0000 -+#define PHY_MDC_CFG GENMASK(29, 24) -+#define MDC_TURBO BIT(20) -+#define MDC_MAX_FREQ 25000000 -+#define MDC_MAX_DIVIDER 63 -+ -+#define GMAC_PIAC_REG 0x0004 -+#define PHY_ACS_ST BIT(31) -+#define MDIO_REG_ADDR_S 25 -+#define MDIO_REG_ADDR_M 0x3e000000 -+#define MDIO_PHY_ADDR_S 20 -+#define MDIO_PHY_ADDR_M 0x1f00000 -+#define MDIO_CMD_S 18 -+#define MDIO_CMD_M 0xc0000 -+#define MDIO_ST_S 16 -+#define MDIO_ST_M 0x30000 -+#define MDIO_RW_DATA_S 0 -+#define MDIO_RW_DATA_M 0xffff -+ -+#define GMAC_XGMAC_STS_REG 0x000c -+#define P1_XGMAC_FORCE_LINK BIT(15) -+ -+#define GMAC_MAC_MISC_REG 0x0010 -+#define MISC_MDC_TURBO BIT(4) -+ -+#define GMAC_GSW_CFG_REG 0x0080 -+#define GSWTX_IPG_M 0xF0000 -+#define GSWTX_IPG_S 16 -+#define GSWRX_IPG_M 0xF -+#define GSWRX_IPG_S 0 -+ -+/* MDIO_CMD: MDIO commands */ -+#define MDIO_CMD_ADDR 0 -+#define MDIO_CMD_WRITE 1 -+#define MDIO_CMD_READ 2 -+#define MDIO_CMD_READ_C45 3 -+ -+/* MDIO_ST: MDIO start field */ -+#define MDIO_ST_C45 0 -+#define MDIO_ST_C22 1 -+ -+#define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100) -+#define MAC_RX_PKT_LEN_S 24 -+#define MAC_RX_PKT_LEN_M 0x3000000 -+#define IPG_CFG_S 18 -+#define IPG_CFG_M 0xc0000 -+#define MAC_MODE BIT(16) -+#define FORCE_MODE BIT(15) -+#define MAC_TX_EN BIT(14) -+#define MAC_RX_EN BIT(13) -+#define DEL_RXFIFO_CLR BIT(12) -+#define BKOFF_EN BIT(9) -+#define BACKPR_EN BIT(8) -+#define FORCE_RX_FC BIT(5) -+#define FORCE_TX_FC BIT(4) -+#define FORCE_SPD_S 2 -+#define FORCE_SPD_M 0x0c -+#define FORCE_DPX BIT(1) -+#define FORCE_LINK BIT(0) -+ -+/* Values of IPG_CFG */ -+#define IPG_96BIT 0 -+#define IPG_96BIT_WITH_SHORT_IPG 1 -+#define IPG_64BIT 2 -+ -+/* MAC_RX_PKT_LEN: Max RX packet length */ -+#define MAC_RX_PKT_LEN_1518 0 -+#define MAC_RX_PKT_LEN_1536 1 -+#define MAC_RX_PKT_LEN_1552 2 -+#define MAC_RX_PKT_LEN_JUMBO 3 -+ -+/* FORCE_SPD: Forced link speed */ -+#define SPEED_10M 0 -+#define SPEED_100M 1 -+#define SPEED_1000M 2 -+ -+#define GMAC_TRGMII_RCK_CTRL 0x300 -+#define RX_RST BIT(31) -+#define RXC_DQSISEL BIT(30) -+ -+#define NUM_TRGMII_CTRL 5 -+ -+#define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8) -+#define TD_DM_DRVN_S 4 -+#define TD_DM_DRVN_M 0xf0 -+#define TD_DM_DRVP_S 0 -+#define TD_DM_DRVP_M 0x0f -+ -+/* XGMAC Status Registers */ -+#define XGMAC_STS(x) (((x) == 2) ? 0x001C : 0x000C) -+#define XGMAC_FORCE_LINK(x) (((x) == 1) ? BIT(31) : BIT(15)) -+ -+/* XGMAC Registers */ -+#define XGMAC_PORT_MCR(x) (0x2000 + (((x) - 1) * 0x1000)) -+#define XGMAC_TRX_DISABLE 0xf -+#define XGMAC_FORCE_TX_FC BIT(5) -+#define XGMAC_FORCE_RX_FC BIT(4) -+ -+/* MDIO Indirect Access Registers */ -+#define MII_MMD_ACC_CTL_REG 0x0d -+#define MMD_CMD_S 14 -+#define MMD_CMD_M 0xc000 -+#define MMD_DEVAD_S 0 -+#define MMD_DEVAD_M 0x1f -+ -+/* MMD_CMD: MMD commands */ -+#define MMD_ADDR 0 -+#define MMD_DATA 1 -+#define MMD_DATA_RW_POST_INC 2 -+#define MMD_DATA_W_POST_INC 3 -+ -+#define MII_MMD_ADDR_DATA_REG 0x0e -+ -+/* PDMA descriptors */ -+struct mtk_rx_dma { -+ unsigned int rxd1; -+ unsigned int rxd2; -+ unsigned int rxd3; -+ unsigned int rxd4; -+} __packed __aligned(4); -+ -+struct mtk_rx_dma_v2 { -+ unsigned int rxd1; -+ unsigned int rxd2; -+ unsigned int rxd3; -+ unsigned int rxd4; -+ unsigned int rxd5; -+ unsigned int rxd6; -+ unsigned int rxd7; -+ unsigned int rxd8; -+} __packed __aligned(4); -+ -+struct mtk_tx_dma { -+ unsigned int txd1; -+ unsigned int txd2; -+ unsigned int txd3; -+ unsigned int txd4; -+} __packed __aligned(4); -+ -+struct mtk_tx_dma_v2 { -+ unsigned int txd1; -+ unsigned int txd2; -+ unsigned int txd3; -+ unsigned int txd4; -+ unsigned int txd5; -+ unsigned int txd6; -+ unsigned int txd7; -+ unsigned int txd8; -+} __packed __aligned(4); -+ -+/* PDMA TXD fields */ -+#define PDMA_TXD2_DDONE BIT(31) -+#define PDMA_TXD2_LS0 BIT(30) -+#define PDMA_V1_TXD2_SDL0_M GENMASK(29, 16) -+#define PDMA_V1_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V1_TXD2_SDL0_M, (_v)) -+#define PDMA_V2_TXD2_SDL0_M GENMASK(23, 8) -+#define PDMA_V2_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V2_TXD2_SDL0_M, (_v)) -+ -+#define PDMA_V1_TXD4_FPORT_M GENMASK(27, 25) -+#define PDMA_V1_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V1_TXD4_FPORT_M, (_v)) -+#define PDMA_V2_TXD4_FPORT_M GENMASK(27, 24) -+#define PDMA_V2_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD4_FPORT_M, (_v)) -+ -+#define PDMA_V2_TXD5_FPORT_M GENMASK(19, 16) -+#define PDMA_V2_TXD5_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD5_FPORT_M, (_v)) -+ -+/* PDMA RXD fields */ -+#define PDMA_RXD2_DDONE BIT(31) -+#define PDMA_RXD2_LS0 BIT(30) -+#define PDMA_V1_RXD2_PLEN0_M GENMASK(29, 16) -+#define PDMA_V1_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V1_RXD2_PLEN0_M, (_v)) -+#define PDMA_V1_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V1_RXD2_PLEN0_M, (_v)) -+#define PDMA_V2_RXD2_PLEN0_M GENMASK(23, 8) -+#define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v)) -+#define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v)) -+ -+void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); -+void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); -+void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); -+ -+int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg); -+int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data); -+int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); -+int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, -+ u16 val); -+int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); -+int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, -+ u16 val); -+ -+#endif /* _MTK_ETH_H_ */ diff --git a/package/boot/uboot-mediatek/patches/061-02-net-mediatek-add-support-for-MediaTek-MT7987-SoC.patch b/package/boot/uboot-mediatek/patches/061-02-net-mediatek-add-support-for-MediaTek-MT7987-SoC.patch deleted file mode 100644 index 183c7129ab..0000000000 --- a/package/boot/uboot-mediatek/patches/061-02-net-mediatek-add-support-for-MediaTek-MT7987-SoC.patch +++ /dev/null @@ -1,63 +0,0 @@ -From fe106f2093733b8bd61946372945dfea552b4755 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 10 Jan 2025 16:41:20 +0800 -Subject: [PATCH 2/3] net: mediatek: add support for MediaTek MT7987 SoC - -This patch adds support for MediaTek MT7987. - -MT7987 features MediaTek NETSYS v3, similar to MT7988, features three GMACs -which support 2.5Gb HSGMII. One 2.5Gb PHY is also embedded an can be -connected to a dedicated GMAC. - -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth/Kconfig | 4 ++-- - drivers/net/mtk_eth/mtk_eth.c | 10 ++++++++++ - 2 files changed, 12 insertions(+), 2 deletions(-) - ---- a/drivers/net/mtk_eth/Kconfig -+++ b/drivers/net/mtk_eth/Kconfig -@@ -16,7 +16,7 @@ config MTK_ETH_SGMII - - config MTK_ETH_XGMII - bool -- default y if TARGET_MT7988 -+ default y if TARGET_MT7987 || TARGET_MT7988 - - config MTK_ETH_SWITCH_MT7530 - bool "Support for MediaTek MT7530 ethernet switch" -@@ -25,7 +25,7 @@ config MTK_ETH_SWITCH_MT7530 - config MTK_ETH_SWITCH_MT7531 - bool "Support for MediaTek MT7531 ethernet switch" - default y if TARGET_MT7622 || TARGET_MT7629 || TARGET_MT7981 || \ -- TARGET_MT7986 -+ TARGET_MT7986 || TARGET_MT7987 - - config MTK_ETH_SWITCH_MT7988 - bool "Support for MediaTek MT7988 built-in ethernet switch" ---- a/drivers/net/mtk_eth/mtk_eth.c -+++ b/drivers/net/mtk_eth/mtk_eth.c -@@ -1477,6 +1477,15 @@ static const struct mtk_soc_data mt7988_ - .rxd_size = sizeof(struct mtk_rx_dma_v2), - }; - -+static const struct mtk_soc_data mt7987_data = { -+ .caps = MT7987_CAPS, -+ .ana_rgc3 = 0x128, -+ .gdma_count = 3, -+ .pdma_base = PDMA_V3_BASE, -+ .txd_size = sizeof(struct mtk_tx_dma_v2), -+ .rxd_size = sizeof(struct mtk_rx_dma_v2), -+}; -+ - static const struct mtk_soc_data mt7986_data = { - .caps = MT7986_CAPS, - .ana_rgc3 = 0x128, -@@ -1531,6 +1540,7 @@ static const struct mtk_soc_data mt7621_ - - static const struct udevice_id mtk_eth_ids[] = { - { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data }, -+ { .compatible = "mediatek,mt7987-eth", .data = (ulong)&mt7987_data }, - { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data }, - { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data }, - { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, diff --git a/package/boot/uboot-mediatek/patches/061-03-net-mediatek-add-support-for-Airoha-AN8855-ethernet-.patch b/package/boot/uboot-mediatek/patches/061-03-net-mediatek-add-support-for-Airoha-AN8855-ethernet-.patch deleted file mode 100644 index 8e4f4391b1..0000000000 --- a/package/boot/uboot-mediatek/patches/061-03-net-mediatek-add-support-for-Airoha-AN8855-ethernet-.patch +++ /dev/null @@ -1,1133 +0,0 @@ -From cedafee9ff39d13aaf8b80361b673445a85f117e Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 10 Jan 2025 16:41:24 +0800 -Subject: [PATCH 3/3] net: mediatek: add support for Airoha AN8855 ethernet - switch - -Airoha AN8855 is a 5-port gigabit switch with a 2.5G HSGMII CPU port - -Signed-off-by: Weijie Gao ---- - drivers/net/mtk_eth/Kconfig | 4 + - drivers/net/mtk_eth/Makefile | 1 + - drivers/net/mtk_eth/an8855.c | 1096 ++++++++++++++++++++++++++++++++++ - 3 files changed, 1101 insertions(+) - create mode 100644 drivers/net/mtk_eth/an8855.c - ---- a/drivers/net/mtk_eth/Kconfig -+++ b/drivers/net/mtk_eth/Kconfig -@@ -32,4 +32,8 @@ config MTK_ETH_SWITCH_MT7988 - depends on TARGET_MT7988 - default y - -+config MTK_ETH_SWITCH_AN8855 -+ bool "Support for Airoha AN8855 ethernet switch" -+ default y if TARGET_MT7981 || TARGET_MT7987 -+ - endif # MEDIATEK_ETH ---- a/drivers/net/mtk_eth/Makefile -+++ b/drivers/net/mtk_eth/Makefile -@@ -7,3 +7,4 @@ obj-y += mtk_eth.o - obj-$(CONFIG_MTK_ETH_SWITCH_MT7530) += mt753x.o mt7530.o - obj-$(CONFIG_MTK_ETH_SWITCH_MT7531) += mt753x.o mt7531.o - obj-$(CONFIG_MTK_ETH_SWITCH_MT7988) += mt753x.o mt7988.o -+obj-$(CONFIG_MTK_ETH_SWITCH_AN8855) += an8855.o ---- /dev/null -+++ b/drivers/net/mtk_eth/an8855.c -@@ -0,0 +1,1096 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2025 MediaTek Inc. -+ * -+ * Author: Neal Yen -+ * Author: Weijie Gao -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "mtk_eth.h" -+ -+/* AN8855 Register Definitions */ -+#define AN8855_SYS_CTRL_REG 0x100050c0 -+#define AN8855_SW_SYS_RST BIT(31) -+ -+#define AN8855_PMCR_REG(p) (0x10210000 + (p) * 0x200) -+#define AN8855_FORCE_MODE_LNK BIT(31) -+#define AN8855_FORCE_MODE 0xb31593f0 -+ -+#define AN8855_PORT_CTRL_BASE (0x10208000) -+#define AN8855_PORT_CTRL_REG(p, r) (AN8855_PORT_CTRL_BASE + (p) * 0x200 + (r)) -+ -+#define AN8855_PORTMATRIX_REG(p) AN8855_PORT_CTRL_REG(p, 0x44) -+ -+#define AN8855_PVC(p) AN8855_PORT_CTRL_REG(p, 0x10) -+#define AN8855_STAG_VPID_S 16 -+#define AN8855_STAG_VPID_M 0xffff0000 -+#define AN8855_VLAN_ATTR_S 6 -+#define AN8855_VLAN_ATTR_M 0xc0 -+ -+#define VLAN_ATTR_USER 0 -+ -+#define AN8855_INT_MASK 0x100050F0 -+#define AN8855_INT_SYS_BIT BIT(15) -+ -+#define AN8855_RG_CLK_CPU_ICG 0x10005034 -+#define AN8855_MCU_ENABLE BIT(3) -+ -+#define AN8855_RG_TIMER_CTL 0x1000a100 -+#define AN8855_WDOG_ENABLE BIT(25) -+ -+#define AN8855_CKGCR 0x10213e1c -+ -+#define AN8855_SCU_BASE 0x10000000 -+#define AN8855_RG_RGMII_TXCK_C (AN8855_SCU_BASE + 0x1d0) -+#define AN8855_RG_GPIO_LED_MODE (AN8855_SCU_BASE + 0x0054) -+#define AN8855_RG_GPIO_LED_SEL(i) (AN8855_SCU_BASE + (0x0058 + ((i) * 4))) -+#define AN8855_RG_INTB_MODE (AN8855_SCU_BASE + 0x0080) -+#define AN8855_RG_GDMP_RAM (AN8855_SCU_BASE + 0x10000) -+#define AN8855_RG_GPIO_L_INV (AN8855_SCU_BASE + 0x0010) -+#define AN8855_RG_GPIO_CTRL (AN8855_SCU_BASE + 0xa300) -+#define AN8855_RG_GPIO_DATA (AN8855_SCU_BASE + 0xa304) -+#define AN8855_RG_GPIO_OE (AN8855_SCU_BASE + 0xa314) -+ -+#define AN8855_HSGMII_AN_CSR_BASE 0x10220000 -+#define AN8855_SGMII_REG_AN0 (AN8855_HSGMII_AN_CSR_BASE + 0x000) -+#define AN8855_SGMII_REG_AN_13 (AN8855_HSGMII_AN_CSR_BASE + 0x034) -+#define AN8855_SGMII_REG_AN_FORCE_CL37 (AN8855_HSGMII_AN_CSR_BASE + 0x060) -+ -+#define AN8855_HSGMII_CSR_PCS_BASE 0x10220000 -+#define AN8855_RG_HSGMII_PCS_CTROL_1 (AN8855_HSGMII_CSR_PCS_BASE + 0xa00) -+#define AN8855_RG_AN_SGMII_MODE_FORCE (AN8855_HSGMII_CSR_PCS_BASE + 0xa24) -+ -+#define AN8855_MULTI_SGMII_CSR_BASE 0x10224000 -+#define AN8855_SGMII_STS_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x018) -+#define AN8855_MSG_RX_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x100) -+#define AN8855_MSG_RX_LIK_STS_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x514) -+#define AN8855_MSG_RX_LIK_STS_2 (AN8855_MULTI_SGMII_CSR_BASE + 0x51c) -+#define AN8855_PHY_RX_FORCE_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x520) -+ -+#define AN8855_XFI_CSR_PCS_BASE 0x10225000 -+#define AN8855_RG_USXGMII_AN_CONTROL_0 (AN8855_XFI_CSR_PCS_BASE + 0xbf8) -+ -+#define AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 -+#define AN8855_RG_RATE_ADAPT_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x000) -+#define AN8855_RATE_ADP_P0_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x100) -+#define AN8855_MII_RA_AN_ENABLE (AN8855_MULTI_PHY_RA_CSR_BASE + 0x300) -+ -+#define AN8855_QP_DIG_CSR_BASE 0x1022a000 -+#define AN8855_QP_CK_RST_CTRL_4 (AN8855_QP_DIG_CSR_BASE + 0x310) -+#define AN8855_QP_DIG_MODE_CTRL_0 (AN8855_QP_DIG_CSR_BASE + 0x324) -+#define AN8855_QP_DIG_MODE_CTRL_1 (AN8855_QP_DIG_CSR_BASE + 0x330) -+ -+#define AN8855_QP_PMA_TOP_BASE 0x1022e000 -+#define AN8855_PON_RXFEDIG_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x100) -+#define AN8855_PON_RXFEDIG_CTRL_9 (AN8855_QP_PMA_TOP_BASE + 0x124) -+ -+#define AN8855_SS_LCPLL_PWCTL_SETTING_2 (AN8855_QP_PMA_TOP_BASE + 0x208) -+#define AN8855_SS_LCPLL_TDC_FLT_2 (AN8855_QP_PMA_TOP_BASE + 0x230) -+#define AN8855_SS_LCPLL_TDC_FLT_5 (AN8855_QP_PMA_TOP_BASE + 0x23c) -+#define AN8855_SS_LCPLL_TDC_PCW_1 (AN8855_QP_PMA_TOP_BASE + 0x248) -+#define AN8855_INTF_CTRL_8 (AN8855_QP_PMA_TOP_BASE + 0x320) -+#define AN8855_INTF_CTRL_9 (AN8855_QP_PMA_TOP_BASE + 0x324) -+#define AN8855_PLL_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x400) -+#define AN8855_PLL_CTRL_2 (AN8855_QP_PMA_TOP_BASE + 0x408) -+#define AN8855_PLL_CTRL_3 (AN8855_QP_PMA_TOP_BASE + 0x40c) -+#define AN8855_PLL_CTRL_4 (AN8855_QP_PMA_TOP_BASE + 0x410) -+#define AN8855_PLL_CK_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x414) -+#define AN8855_RX_DLY_0 (AN8855_QP_PMA_TOP_BASE + 0x614) -+#define AN8855_RX_CTRL_2 (AN8855_QP_PMA_TOP_BASE + 0x630) -+#define AN8855_RX_CTRL_5 (AN8855_QP_PMA_TOP_BASE + 0x63c) -+#define AN8855_RX_CTRL_6 (AN8855_QP_PMA_TOP_BASE + 0x640) -+#define AN8855_RX_CTRL_7 (AN8855_QP_PMA_TOP_BASE + 0x644) -+#define AN8855_RX_CTRL_8 (AN8855_QP_PMA_TOP_BASE + 0x648) -+#define AN8855_RX_CTRL_26 (AN8855_QP_PMA_TOP_BASE + 0x690) -+#define AN8855_RX_CTRL_42 (AN8855_QP_PMA_TOP_BASE + 0x6d0) -+ -+#define AN8855_QP_ANA_CSR_BASE 0x1022f000 -+#define AN8855_RG_QP_RX_DAC_EN (AN8855_QP_ANA_CSR_BASE + 0x00) -+#define AN8855_RG_QP_RXAFE_RESERVE (AN8855_QP_ANA_CSR_BASE + 0x04) -+#define AN8855_RG_QP_CDR_LPF_MJV_LIM (AN8855_QP_ANA_CSR_BASE + 0x0c) -+#define AN8855_RG_QP_CDR_LPF_SETVALUE (AN8855_QP_ANA_CSR_BASE + 0x14) -+#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 (AN8855_QP_ANA_CSR_BASE + 0x18) -+#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE (AN8855_QP_ANA_CSR_BASE + 0x1c) -+#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF (AN8855_QP_ANA_CSR_BASE + 0x20) -+#define AN8855_RG_QP_TX_MODE_16B_EN (AN8855_QP_ANA_CSR_BASE + 0x28) -+#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL (AN8855_QP_ANA_CSR_BASE + 0x3c) -+#define AN8855_RG_QP_PLL_SDM_ORD (AN8855_QP_ANA_CSR_BASE + 0x40) -+ -+#define AN8855_ETHER_SYS_BASE 0x1028c800 -+#define RG_GPHY_AFE_PWD (AN8855_ETHER_SYS_BASE + 0x40) -+ -+#define AN8855_PKG_SEL 0x10000094 -+#define PAG_SEL_AN8855H 0x2 -+ -+/* PHY LED Register bitmap of define */ -+#define PHY_LED_CTRL_SELECT 0x3e8 -+#define PHY_SINGLE_LED_ON_CTRL(i) (0x3e0 + ((i) * 2)) -+#define PHY_SINGLE_LED_BLK_CTRL(i) (0x3e1 + ((i) * 2)) -+#define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2)) -+#define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2)) -+ -+#define PHY_PMA_CTRL (0x340) -+ -+#define PHY_DEV1F 0x1f -+ -+#define PHY_LED_ON_CTRL(i) (0x24 + ((i) * 2)) -+#define LED_ON_EN (1 << 15) -+#define LED_ON_POL (1 << 14) -+#define LED_ON_EVT_MASK (0x7f) -+ -+/* LED ON Event */ -+#define LED_ON_EVT_FORCE (1 << 6) -+#define LED_ON_EVT_LINK_HD (1 << 5) -+#define LED_ON_EVT_LINK_FD (1 << 4) -+#define LED_ON_EVT_LINK_DOWN (1 << 3) -+#define LED_ON_EVT_LINK_10M (1 << 2) -+#define LED_ON_EVT_LINK_100M (1 << 1) -+#define LED_ON_EVT_LINK_1000M (1 << 0) -+ -+#define PHY_LED_BLK_CTRL(i) (0x25 + ((i) * 2)) -+#define LED_BLK_EVT_MASK (0x3ff) -+/* LED Blinking Event */ -+#define LED_BLK_EVT_FORCE (1 << 9) -+#define LED_BLK_EVT_10M_RX_ACT (1 << 5) -+#define LED_BLK_EVT_10M_TX_ACT (1 << 4) -+#define LED_BLK_EVT_100M_RX_ACT (1 << 3) -+#define LED_BLK_EVT_100M_TX_ACT (1 << 2) -+#define LED_BLK_EVT_1000M_RX_ACT (1 << 1) -+#define LED_BLK_EVT_1000M_TX_ACT (1 << 0) -+ -+#define PHY_LED_BCR (0x21) -+#define LED_BCR_EXT_CTRL (1 << 15) -+#define LED_BCR_CLK_EN (1 << 3) -+#define LED_BCR_TIME_TEST (1 << 2) -+#define LED_BCR_MODE_MASK (3) -+#define LED_BCR_MODE_DISABLE (0) -+ -+#define PHY_LED_ON_DUR (0x22) -+#define LED_ON_DUR_MASK (0xffff) -+ -+#define PHY_LED_BLK_DUR (0x23) -+#define LED_BLK_DUR_MASK (0xffff) -+ -+#define PHY_LED_BLINK_DUR_CTRL (0x720) -+ -+/* Definition of LED */ -+#define LED_ON_EVENT (LED_ON_EVT_LINK_1000M | \ -+ LED_ON_EVT_LINK_100M | LED_ON_EVT_LINK_10M |\ -+ LED_ON_EVT_LINK_HD | LED_ON_EVT_LINK_FD) -+ -+#define LED_BLK_EVENT (LED_BLK_EVT_1000M_TX_ACT | \ -+ LED_BLK_EVT_1000M_RX_ACT | \ -+ LED_BLK_EVT_100M_TX_ACT | \ -+ LED_BLK_EVT_100M_RX_ACT | \ -+ LED_BLK_EVT_10M_TX_ACT | \ -+ LED_BLK_EVT_10M_RX_ACT) -+ -+#define LED_FREQ AIR_LED_BLK_DUR_64M -+ -+#define AN8855_NUM_PHYS 5 -+#define AN8855_NUM_PORTS 6 -+#define AN8855_PHY_ADDR(base, addr) (((base) + (addr)) & 0x1f) -+ -+/* PHY LED Register bitmap of define */ -+#define PHY_LED_CTRL_SELECT 0x3e8 -+#define PHY_SINGLE_LED_ON_CTRL(i) (0x3e0 + ((i) * 2)) -+#define PHY_SINGLE_LED_BLK_CTRL(i) (0x3e1 + ((i) * 2)) -+#define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2)) -+#define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2)) -+ -+/* AN8855 LED */ -+enum an8855_led_blk_dur { -+ AIR_LED_BLK_DUR_32M, -+ AIR_LED_BLK_DUR_64M, -+ AIR_LED_BLK_DUR_128M, -+ AIR_LED_BLK_DUR_256M, -+ AIR_LED_BLK_DUR_512M, -+ AIR_LED_BLK_DUR_1024M, -+ AIR_LED_BLK_DUR_LAST -+}; -+ -+enum an8855_led_polarity { -+ LED_LOW, -+ LED_HIGH, -+}; -+ -+enum an8855_led_mode { -+ AN8855_LED_MODE_DISABLE, -+ AN8855_LED_MODE_USER_DEFINE, -+ AN8855_LED_MODE_LAST -+}; -+ -+enum phy_led_idx { -+ P0_LED0, -+ P0_LED1, -+ P0_LED2, -+ P0_LED3, -+ P1_LED0, -+ P1_LED1, -+ P1_LED2, -+ P1_LED3, -+ P2_LED0, -+ P2_LED1, -+ P2_LED2, -+ P2_LED3, -+ P3_LED0, -+ P3_LED1, -+ P3_LED2, -+ P3_LED3, -+ P4_LED0, -+ P4_LED1, -+ P4_LED2, -+ P4_LED3, -+ PHY_LED_MAX -+}; -+ -+struct an8855_led_cfg { -+ u16 en; -+ u8 phy_led_idx; -+ u16 pol; -+ u16 on_cfg; -+ u16 blk_cfg; -+ u8 led_freq; -+}; -+ -+struct an8855_switch_priv { -+ struct mtk_eth_switch_priv epriv; -+ struct mii_dev *mdio_bus; -+ u32 phy_base; -+}; -+ -+/* AN8855 Reference Board */ -+static const struct an8855_led_cfg led_cfg[] = { -+/************************************************************************* -+ * Enable, LED idx, LED Polarity, LED ON event, LED Blink event LED Freq -+ ************************************************************************* -+ */ -+ /* GPIO0 */ -+ {1, P4_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO1 */ -+ {1, P4_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO2 */ -+ {1, P0_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO3 */ -+ {1, P0_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO4 */ -+ {1, P1_LED0, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO5 */ -+ {1, P1_LED1, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO6 */ -+ {0, PHY_LED_MAX, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO7 */ -+ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO8 */ -+ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO9 */ -+ {1, P2_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO10 */ -+ {1, P2_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO11 */ -+ {1, P3_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO12 */ -+ {1, P3_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO13 */ -+ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO14 */ -+ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO15 */ -+ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO16 */ -+ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO17 */ -+ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO18 */ -+ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO19 */ -+ {0, PHY_LED_MAX, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+ /* GPIO20 */ -+ {0, PHY_LED_MAX, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, -+}; -+ -+static int __an8855_reg_read(struct mtk_eth_priv *priv, u8 phy_base, u32 reg, u32 *data) -+{ -+ int ret, low_word, high_word; -+ -+ ret = mtk_mii_write(priv, phy_base, 0x1f, 0x4); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv, phy_base, 0x10, 0); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv, phy_base, 0x15, ((reg >> 16) & 0xFFFF)); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv, phy_base, 0x16, (reg & 0xFFFF)); -+ if (ret) -+ return ret; -+ -+ low_word = mtk_mii_read(priv, phy_base, 0x18); -+ if (low_word < 0) -+ return low_word; -+ -+ high_word = mtk_mii_read(priv, phy_base, 0x17); -+ if (high_word < 0) -+ return high_word; -+ -+ ret = mtk_mii_write(priv, phy_base, 0x1f, 0); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv, phy_base, 0x10, 0); -+ if (ret) -+ return ret; -+ -+ if (data) -+ *data = ((u32)high_word << 16) | (low_word & 0xffff); -+ -+ return 0; -+} -+ -+static int an8855_reg_read(struct an8855_switch_priv *priv, u32 reg, u32 *data) -+{ -+ return __an8855_reg_read(priv->epriv.eth, priv->phy_base, reg, data); -+} -+ -+static int an8855_reg_write(struct an8855_switch_priv *priv, u32 reg, u32 data) -+{ -+ int ret; -+ -+ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x1f, 0x4); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x10, 0); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x11, -+ ((reg >> 16) & 0xFFFF)); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x12, -+ (reg & 0xFFFF)); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x13, -+ ((data >> 16) & 0xFFFF)); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x14, -+ (data & 0xFFFF)); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x1f, 0); -+ if (ret) -+ return ret; -+ -+ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x10, 0); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static int an8855_phy_cl45_read(struct an8855_switch_priv *priv, int port, -+ int devad, int regnum, u16 *data) -+{ -+ u16 phy_addr = AN8855_PHY_ADDR(priv->phy_base, port); -+ -+ *data = mtk_mmd_ind_read(priv->epriv.eth, phy_addr, devad, regnum); -+ -+ return 0; -+} -+ -+static int an8855_phy_cl45_write(struct an8855_switch_priv *priv, int port, -+ int devad, int regnum, u16 data) -+{ -+ u16 phy_addr = AN8855_PHY_ADDR(priv->phy_base, port); -+ -+ mtk_mmd_ind_write(priv->epriv.eth, phy_addr, devad, regnum, data); -+ -+ return 0; -+} -+ -+static int an8855_port_sgmii_init(struct an8855_switch_priv *priv, u32 port) -+{ -+ u32 val = 0; -+ -+ if (port != 5) { -+ printf("an8855: port %d is not a SGMII port\n", port); -+ return -EINVAL; -+ } -+ -+ /* PLL */ -+ an8855_reg_read(priv, AN8855_QP_DIG_MODE_CTRL_1, &val); -+ val &= ~(0x3 << 2); -+ val |= (0x1 << 2); -+ an8855_reg_write(priv, AN8855_QP_DIG_MODE_CTRL_1, val); -+ -+ /* PLL - LPF */ -+ an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); -+ val &= ~(0x3 << 0); -+ val |= (0x1 << 0); -+ val &= ~(0x7 << 2); -+ val |= (0x5 << 2); -+ val &= ~GENMASK(7, 6); -+ val &= ~(0x7 << 8); -+ val |= (0x3 << 8); -+ val |= BIT(29); -+ val &= ~GENMASK(13, 12); -+ an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); -+ -+ /* PLL - ICO */ -+ an8855_reg_read(priv, AN8855_PLL_CTRL_4, &val); -+ val |= BIT(2); -+ an8855_reg_write(priv, AN8855_PLL_CTRL_4, val); -+ -+ an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); -+ val &= ~BIT(14); -+ an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); -+ -+ /* PLL - CHP */ -+ an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); -+ val &= ~(0xf << 16); -+ val |= (0x6 << 16); -+ an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); -+ -+ /* PLL - PFD */ -+ an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); -+ val &= ~(0x3 << 20); -+ val |= (0x1 << 20); -+ val &= ~(0x3 << 24); -+ val |= (0x1 << 24); -+ val &= ~BIT(26); -+ an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); -+ -+ /* PLL - POSTDIV */ -+ an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); -+ val |= BIT(22); -+ val &= ~BIT(27); -+ val &= ~BIT(28); -+ an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); -+ -+ /* PLL - SDM */ -+ an8855_reg_read(priv, AN8855_PLL_CTRL_4, &val); -+ val &= ~GENMASK(4, 3); -+ an8855_reg_write(priv, AN8855_PLL_CTRL_4, val); -+ -+ an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); -+ val &= ~BIT(30); -+ an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); -+ -+ an8855_reg_read(priv, AN8855_SS_LCPLL_PWCTL_SETTING_2, &val); -+ val &= ~(0x3 << 16); -+ val |= (0x1 << 16); -+ an8855_reg_write(priv, AN8855_SS_LCPLL_PWCTL_SETTING_2, val); -+ -+ an8855_reg_write(priv, AN8855_SS_LCPLL_TDC_FLT_2, 0x7a000000); -+ an8855_reg_write(priv, AN8855_SS_LCPLL_TDC_PCW_1, 0x7a000000); -+ -+ an8855_reg_read(priv, AN8855_SS_LCPLL_TDC_FLT_5, &val); -+ val &= ~BIT(24); -+ an8855_reg_write(priv, AN8855_SS_LCPLL_TDC_FLT_5, val); -+ -+ an8855_reg_read(priv, AN8855_PLL_CK_CTRL_0, &val); -+ val &= ~BIT(8); -+ an8855_reg_write(priv, AN8855_PLL_CK_CTRL_0, val); -+ -+ /* PLL - SS */ -+ an8855_reg_read(priv, AN8855_PLL_CTRL_3, &val); -+ val &= ~GENMASK(15, 0); -+ an8855_reg_write(priv, AN8855_PLL_CTRL_3, val); -+ -+ an8855_reg_read(priv, AN8855_PLL_CTRL_4, &val); -+ val &= ~GENMASK(1, 0); -+ an8855_reg_write(priv, AN8855_PLL_CTRL_4, val); -+ -+ an8855_reg_read(priv, AN8855_PLL_CTRL_3, &val); -+ val &= ~GENMASK(31, 16); -+ an8855_reg_write(priv, AN8855_PLL_CTRL_3, val); -+ -+ /* PLL - TDC */ -+ an8855_reg_read(priv, AN8855_PLL_CK_CTRL_0, &val); -+ val &= ~BIT(9); -+ an8855_reg_write(priv, AN8855_PLL_CK_CTRL_0, val); -+ -+ an8855_reg_read(priv, AN8855_RG_QP_PLL_SDM_ORD, &val); -+ val |= BIT(3); -+ val |= BIT(4); -+ an8855_reg_write(priv, AN8855_RG_QP_PLL_SDM_ORD, val); -+ -+ an8855_reg_read(priv, AN8855_RG_QP_RX_DAC_EN, &val); -+ val &= ~(0x3 << 16); -+ val |= (0x2 << 16); -+ an8855_reg_write(priv, AN8855_RG_QP_RX_DAC_EN, val); -+ -+ /* TCL Disable (only for Co-SIM) */ -+ an8855_reg_read(priv, AN8855_PON_RXFEDIG_CTRL_0, &val); -+ val &= ~BIT(12); -+ an8855_reg_write(priv, AN8855_PON_RXFEDIG_CTRL_0, val); -+ -+ /* TX Init */ -+ an8855_reg_read(priv, AN8855_RG_QP_TX_MODE_16B_EN, &val); -+ val &= ~BIT(0); -+ val &= ~(0xffff << 16); -+ val |= (0x4 << 16); -+ an8855_reg_write(priv, AN8855_RG_QP_TX_MODE_16B_EN, val); -+ -+ /* RX Control */ -+ an8855_reg_read(priv, AN8855_RG_QP_RXAFE_RESERVE, &val); -+ val |= BIT(11); -+ an8855_reg_write(priv, AN8855_RG_QP_RXAFE_RESERVE, val); -+ -+ an8855_reg_read(priv, AN8855_RG_QP_CDR_LPF_MJV_LIM, &val); -+ val &= ~(0x3 << 4); -+ val |= (0x1 << 4); -+ an8855_reg_write(priv, AN8855_RG_QP_CDR_LPF_MJV_LIM, val); -+ -+ an8855_reg_read(priv, AN8855_RG_QP_CDR_LPF_SETVALUE, &val); -+ val &= ~(0xf << 25); -+ val |= (0x1 << 25); -+ val &= ~(0x7 << 29); -+ val |= (0x3 << 29); -+ an8855_reg_write(priv, AN8855_RG_QP_CDR_LPF_SETVALUE, val); -+ -+ an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, &val); -+ val &= ~(0x1f << 8); -+ val |= (0xf << 8); -+ an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, val); -+ -+ an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, &val); -+ val &= ~(0x3f << 0); -+ val |= (0x19 << 0); -+ val &= ~BIT(6); -+ an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, val); -+ -+ an8855_reg_read(priv, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF, &val); -+ val &= ~(0x7f << 6); -+ val |= (0x21 << 6); -+ val &= ~(0x3 << 16); -+ val |= (0x2 << 16); -+ val &= ~BIT(13); -+ an8855_reg_write(priv, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF, val); -+ -+ an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, &val); -+ val &= ~BIT(30); -+ an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, val); -+ -+ an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, &val); -+ val &= ~(0x7 << 24); -+ val |= (0x4 << 24); -+ an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, val); -+ -+ an8855_reg_read(priv, AN8855_PLL_CTRL_0, &val); -+ val |= BIT(0); -+ an8855_reg_write(priv, AN8855_PLL_CTRL_0, val); -+ -+ an8855_reg_read(priv, AN8855_RX_CTRL_26, &val); -+ val &= ~BIT(23); -+ val |= BIT(26); -+ an8855_reg_write(priv, AN8855_RX_CTRL_26, val); -+ -+ an8855_reg_read(priv, AN8855_RX_DLY_0, &val); -+ val &= ~(0xff << 0); -+ val |= (0x6f << 0); -+ val |= GENMASK(13, 8); -+ an8855_reg_write(priv, AN8855_RX_DLY_0, val); -+ -+ an8855_reg_read(priv, AN8855_RX_CTRL_42, &val); -+ val &= ~(0x1fff << 0); -+ val |= (0x150 << 0); -+ an8855_reg_write(priv, AN8855_RX_CTRL_42, val); -+ -+ an8855_reg_read(priv, AN8855_RX_CTRL_2, &val); -+ val &= ~(0x1fff << 16); -+ val |= (0x150 << 16); -+ an8855_reg_write(priv, AN8855_RX_CTRL_2, val); -+ -+ an8855_reg_read(priv, AN8855_PON_RXFEDIG_CTRL_9, &val); -+ val &= ~(0x7 << 0); -+ val |= (0x1 << 0); -+ an8855_reg_write(priv, AN8855_PON_RXFEDIG_CTRL_9, val); -+ -+ an8855_reg_read(priv, AN8855_RX_CTRL_8, &val); -+ val &= ~(0xfff << 16); -+ val |= (0x200 << 16); -+ val &= ~(0x7fff << 14); -+ val |= (0xfff << 14); -+ an8855_reg_write(priv, AN8855_RX_CTRL_8, val); -+ -+ /* Frequency memter */ -+ an8855_reg_read(priv, AN8855_RX_CTRL_5, &val); -+ val &= ~(0xfffff << 10); -+ val |= (0x10 << 10); -+ an8855_reg_write(priv, AN8855_RX_CTRL_5, val); -+ -+ an8855_reg_read(priv, AN8855_RX_CTRL_6, &val); -+ val &= ~(0xfffff << 0); -+ val |= (0x64 << 0); -+ an8855_reg_write(priv, AN8855_RX_CTRL_6, val); -+ -+ an8855_reg_read(priv, AN8855_RX_CTRL_7, &val); -+ val &= ~(0xfffff << 0); -+ val |= (0x2710 << 0); -+ an8855_reg_write(priv, AN8855_RX_CTRL_7, val); -+ -+ /* PCS Init */ -+ an8855_reg_read(priv, AN8855_RG_HSGMII_PCS_CTROL_1, &val); -+ val &= ~BIT(30); -+ an8855_reg_write(priv, AN8855_RG_HSGMII_PCS_CTROL_1, val); -+ -+ /* Rate Adaption */ -+ an8855_reg_read(priv, AN8855_RATE_ADP_P0_CTRL_0, &val); -+ val &= ~BIT(31); -+ an8855_reg_write(priv, AN8855_RATE_ADP_P0_CTRL_0, val); -+ -+ an8855_reg_read(priv, AN8855_RG_RATE_ADAPT_CTRL_0, &val); -+ val |= BIT(0); -+ val |= BIT(4); -+ val |= GENMASK(27, 26); -+ an8855_reg_write(priv, AN8855_RG_RATE_ADAPT_CTRL_0, val); -+ -+ /* Disable AN */ -+ an8855_reg_read(priv, AN8855_SGMII_REG_AN0, &val); -+ val &= ~BIT(12); -+ an8855_reg_write(priv, AN8855_SGMII_REG_AN0, val); -+ -+ /* Force Speed */ -+ an8855_reg_read(priv, AN8855_SGMII_STS_CTRL_0, &val); -+ val |= BIT(2); -+ val |= GENMASK(5, 4); -+ an8855_reg_write(priv, AN8855_SGMII_STS_CTRL_0, val); -+ -+ /* bypass flow control to MAC */ -+ an8855_reg_write(priv, AN8855_MSG_RX_LIK_STS_0, 0x01010107); -+ an8855_reg_write(priv, AN8855_MSG_RX_LIK_STS_2, 0x00000EEF); -+ -+ return 0; -+} -+ -+static void an8855_led_set_usr_def(struct an8855_switch_priv *priv, u8 entity, -+ enum an8855_led_polarity pol, u16 on_evt, -+ u16 blk_evt, u8 led_freq) -+{ -+ u32 cl45_data; -+ -+ if (pol == LED_HIGH) -+ on_evt |= LED_ON_POL; -+ else -+ on_evt &= ~LED_ON_POL; -+ -+ /* LED on event */ -+ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, -+ PHY_SINGLE_LED_ON_CTRL(entity % 4), -+ on_evt | LED_ON_EN); -+ -+ /* LED blink event */ -+ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, -+ PHY_SINGLE_LED_BLK_CTRL(entity % 4), -+ blk_evt); -+ -+ /* LED freq */ -+ switch (led_freq) { -+ case AIR_LED_BLK_DUR_32M: -+ cl45_data = 0x30e; -+ break; -+ -+ case AIR_LED_BLK_DUR_64M: -+ cl45_data = 0x61a; -+ break; -+ -+ case AIR_LED_BLK_DUR_128M: -+ cl45_data = 0xc35; -+ break; -+ -+ case AIR_LED_BLK_DUR_256M: -+ cl45_data = 0x186a; -+ break; -+ -+ case AIR_LED_BLK_DUR_512M: -+ cl45_data = 0x30d4; -+ break; -+ -+ case AIR_LED_BLK_DUR_1024M: -+ cl45_data = 0x61a8; -+ break; -+ -+ default: -+ cl45_data = 0; -+ break; -+ } -+ -+ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, -+ PHY_SINGLE_LED_BLK_DUR(entity % 4), -+ cl45_data); -+ -+ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, -+ PHY_SINGLE_LED_ON_DUR(entity % 4), -+ (cl45_data >> 1)); -+ -+ /* Disable DATA & BAD_SSD for port LED blink behavior */ -+ cl45_data = mtk_mmd_ind_read(priv->epriv.eth, (entity / 4), 0x1e, PHY_PMA_CTRL); -+ cl45_data &= ~BIT(0); -+ cl45_data &= ~BIT(15); -+ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, PHY_PMA_CTRL, cl45_data); -+} -+ -+static int an8855_led_set_mode(struct an8855_switch_priv *priv, u8 mode) -+{ -+ u16 cl45_data; -+ -+ an8855_phy_cl45_read(priv, 0, 0x1f, PHY_LED_BCR, &cl45_data); -+ -+ switch (mode) { -+ case AN8855_LED_MODE_DISABLE: -+ cl45_data &= ~LED_BCR_EXT_CTRL; -+ cl45_data &= ~LED_BCR_MODE_MASK; -+ cl45_data |= LED_BCR_MODE_DISABLE; -+ break; -+ -+ case AN8855_LED_MODE_USER_DEFINE: -+ cl45_data |= LED_BCR_EXT_CTRL; -+ cl45_data |= LED_BCR_CLK_EN; -+ break; -+ -+ default: -+ printf("an8855: LED mode%d is not supported!\n", mode); -+ return -EINVAL; -+ } -+ -+ an8855_phy_cl45_write(priv, 0, 0x1f, PHY_LED_BCR, cl45_data); -+ -+ return 0; -+} -+ -+static int an8855_led_set_state(struct an8855_switch_priv *priv, u8 entity, -+ u8 state) -+{ -+ u16 cl45_data = 0; -+ -+ /* Change to per port contorl */ -+ an8855_phy_cl45_read(priv, (entity / 4), 0x1e, PHY_LED_CTRL_SELECT, -+ &cl45_data); -+ -+ if (state == 1) -+ cl45_data |= (1 << (entity % 4)); -+ else -+ cl45_data &= ~(1 << (entity % 4)); -+ -+ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, PHY_LED_CTRL_SELECT, -+ cl45_data); -+ -+ /* LED enable setting */ -+ an8855_phy_cl45_read(priv, (entity / 4), 0x1e, -+ PHY_SINGLE_LED_ON_CTRL(entity % 4), &cl45_data); -+ -+ if (state == 1) -+ cl45_data |= LED_ON_EN; -+ else -+ cl45_data &= ~LED_ON_EN; -+ -+ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, -+ PHY_SINGLE_LED_ON_CTRL(entity % 4), cl45_data); -+ -+ return 0; -+} -+ -+static int an8855_led_init(struct an8855_switch_priv *priv) -+{ -+ u32 val, id, tmp_id = 0; -+ int ret; -+ -+ ret = an8855_led_set_mode(priv, AN8855_LED_MODE_USER_DEFINE); -+ if (ret) { -+ printf("an8855: led_set_mode failed with %d!\n", ret); -+ return ret; -+ } -+ -+ for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { -+ ret = an8855_led_set_state(priv, led_cfg[id].phy_led_idx, -+ led_cfg[id].en); -+ if (ret != 0) { -+ printf("an8855: led_set_state failed with %d!\n", ret); -+ return ret; -+ } -+ -+ if (led_cfg[id].en == 1) { -+ an8855_led_set_usr_def(priv, -+ led_cfg[id].phy_led_idx, -+ led_cfg[id].pol, -+ led_cfg[id].on_cfg, -+ led_cfg[id].blk_cfg, -+ led_cfg[id].led_freq); -+ } -+ } -+ -+ /* Setting for System LED & Loop LED */ -+ an8855_reg_write(priv, AN8855_RG_GPIO_OE, 0x0); -+ an8855_reg_write(priv, AN8855_RG_GPIO_CTRL, 0x0); -+ an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, 0); -+ -+ an8855_reg_write(priv, AN8855_RG_GPIO_CTRL, 0x1001); -+ an8855_reg_read(priv, AN8855_RG_GPIO_DATA, &val); -+ val |= GENMASK(3, 1); -+ val &= ~(BIT(0)); -+ val &= ~(BIT(6)); -+ an8855_reg_write(priv, AN8855_RG_GPIO_DATA, val); -+ -+ an8855_reg_read(priv, AN8855_RG_GPIO_OE, &val); -+ val |= 0x41; -+ an8855_reg_write(priv, AN8855_RG_GPIO_OE, val); -+ -+ /* Mapping between GPIO & LED */ -+ val = 0; -+ for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { -+ /* Skip GPIO6, due to GPIO6 does not support PORT LED */ -+ if (id == 6) -+ continue; -+ -+ if (led_cfg[id].en == 1) { -+ if (id < 7) -+ val |= led_cfg[id].phy_led_idx << ((id % 4) * 8); -+ else -+ val |= led_cfg[id].phy_led_idx << (((id - 1) % 4) * 8); -+ } -+ -+ if (id < 7) -+ tmp_id = id; -+ else -+ tmp_id = id - 1; -+ -+ if ((tmp_id % 4) == 0x3) { -+ an8855_reg_write(priv, -+ AN8855_RG_GPIO_LED_SEL(tmp_id / 4), -+ val); -+ val = 0; -+ } -+ } -+ -+ /* Turn on LAN LED mode */ -+ val = 0; -+ for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { -+ if (led_cfg[id].en == 1) -+ val |= 0x1 << id; -+ } -+ an8855_reg_write(priv, AN8855_RG_GPIO_LED_MODE, val); -+ -+ /* Force clear blink pulse for per port LED */ -+ an8855_phy_cl45_write(priv, 0, 0x1f, PHY_LED_BLINK_DUR_CTRL, 0x1f); -+ udelay(1000); -+ an8855_phy_cl45_write(priv, 0, 0x1f, PHY_LED_BLINK_DUR_CTRL, 0); -+ -+ return 0; -+} -+ -+static void an8855_port_isolation(struct an8855_switch_priv *priv) -+{ -+ u32 i; -+ -+ for (i = 0; i < AN8855_NUM_PORTS; i++) { -+ /* Set port matrix mode */ -+ if (i != 5) -+ an8855_reg_write(priv, AN8855_PORTMATRIX_REG(i), 0x20); -+ else -+ an8855_reg_write(priv, AN8855_PORTMATRIX_REG(i), 0x1f); -+ -+ /* Set port mode to user port */ -+ an8855_reg_write(priv, AN8855_PVC(i), -+ (0x8100 << AN8855_STAG_VPID_S) | -+ (VLAN_ATTR_USER << AN8855_VLAN_ATTR_S)); -+ } -+} -+ -+static void an8855_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) -+{ -+ struct an8855_switch_priv *priv = (struct an8855_switch_priv *)swpriv; -+ u32 pmcr = AN8855_FORCE_MODE_LNK; -+ -+ if (enable) -+ pmcr = AN8855_FORCE_MODE; -+ -+ an8855_reg_write(priv, AN8855_PMCR_REG(5), pmcr); -+} -+ -+static int an8855_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) -+{ -+ struct an8855_switch_priv *priv = bus->priv; -+ -+ if (devad < 0) -+ return mtk_mii_read(priv->epriv.eth, addr, reg); -+ -+ return mtk_mmd_ind_read(priv->epriv.eth, addr, devad, reg); -+} -+ -+static int an8855_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, -+ u16 val) -+{ -+ struct an8855_switch_priv *priv = bus->priv; -+ -+ if (devad < 0) -+ return mtk_mii_write(priv->epriv.eth, addr, reg, val); -+ -+ return mtk_mmd_ind_write(priv->epriv.eth, addr, devad, reg, val); -+} -+ -+static int an8855_mdio_register(struct an8855_switch_priv *priv) -+{ -+ struct mii_dev *mdio_bus = mdio_alloc(); -+ int ret; -+ -+ if (!mdio_bus) -+ return -ENOMEM; -+ -+ mdio_bus->read = an8855_mdio_read; -+ mdio_bus->write = an8855_mdio_write; -+ snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name); -+ -+ mdio_bus->priv = priv; -+ -+ ret = mdio_register(mdio_bus); -+ if (ret) { -+ mdio_free(mdio_bus); -+ return ret; -+ } -+ -+ priv->mdio_bus = mdio_bus; -+ -+ return 0; -+} -+ -+static int an8855_setup(struct mtk_eth_switch_priv *swpriv) -+{ -+ struct an8855_switch_priv *priv = (struct an8855_switch_priv *)swpriv; -+ u16 phy_addr, phy_val; -+ u32 i, id, val = 0; -+ int ret; -+ -+ priv->phy_base = 1; -+ -+ /* Turn off PHYs */ -+ for (i = 0; i < AN8855_NUM_PHYS; i++) { -+ phy_addr = AN8855_PHY_ADDR(priv->phy_base, i); -+ phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); -+ phy_val |= BMCR_PDOWN; -+ mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); -+ } -+ -+ /* Force MAC link down before reset */ -+ an8855_reg_write(priv, AN8855_PMCR_REG(5), AN8855_FORCE_MODE_LNK); -+ -+ /* Switch soft reset */ -+ an8855_reg_write(priv, AN8855_SYS_CTRL_REG, AN8855_SW_SYS_RST); -+ udelay(100000); -+ -+ an8855_reg_read(priv, AN8855_PKG_SEL, &val); -+ if ((val & 0x7) == PAG_SEL_AN8855H) { -+ /* Release power down */ -+ an8855_reg_write(priv, RG_GPHY_AFE_PWD, 0x0); -+ -+ /* Invert for LED activity change */ -+ an8855_reg_read(priv, AN8855_RG_GPIO_L_INV, &val); -+ for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { -+ if ((led_cfg[id].pol == LED_HIGH) && -+ (led_cfg[id].en == 1)) -+ val |= 0x1 << id; -+ } -+ an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, (val | 0x1)); -+ -+ /* MCU NOP CMD */ -+ an8855_reg_write(priv, AN8855_RG_GDMP_RAM, 0x846); -+ an8855_reg_write(priv, AN8855_RG_GDMP_RAM + 4, 0x4a); -+ -+ /* Enable MCU */ -+ an8855_reg_read(priv, AN8855_RG_CLK_CPU_ICG, &val); -+ an8855_reg_write(priv, AN8855_RG_CLK_CPU_ICG, -+ val | AN8855_MCU_ENABLE); -+ udelay(1000); -+ -+ /* Disable MCU watchdog */ -+ an8855_reg_read(priv, AN8855_RG_TIMER_CTL, &val); -+ an8855_reg_write(priv, AN8855_RG_TIMER_CTL, -+ (val & (~AN8855_WDOG_ENABLE))); -+ -+ /* LED settings for T830 reference board */ -+ ret = an8855_led_init(priv); -+ if (ret < 0) { -+ printf("an8855: an8855_led_init failed with %d\n", ret); -+ return ret; -+ } -+ } -+ -+ switch (priv->epriv.phy_interface) { -+ case PHY_INTERFACE_MODE_2500BASEX: -+ an8855_port_sgmii_init(priv, 5); -+ break; -+ -+ default: -+ break; -+ } -+ -+ an8855_reg_read(priv, AN8855_CKGCR, &val); -+ val &= ~(0x3); -+ an8855_reg_write(priv, AN8855_CKGCR, val); -+ -+ /* Enable port isolation to block inter-port communication */ -+ an8855_port_isolation(priv); -+ -+ /* Turn on PHYs */ -+ for (i = 0; i < AN8855_NUM_PHYS; i++) { -+ phy_addr = AN8855_PHY_ADDR(priv->phy_base, i); -+ phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); -+ phy_val &= ~BMCR_PDOWN; -+ mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); -+ } -+ -+ return an8855_mdio_register(priv); -+} -+ -+static int an8855_cleanup(struct mtk_eth_switch_priv *swpriv) -+{ -+ struct an8855_switch_priv *priv = (struct an8855_switch_priv *)swpriv; -+ -+ mdio_unregister(priv->mdio_bus); -+ -+ return 0; -+} -+ -+static int an8855_detect(struct mtk_eth_priv *priv) -+{ -+ int ret; -+ u32 val; -+ -+ ret = __an8855_reg_read(priv, 1, 0x10005000, &val); -+ if (ret) -+ return ret; -+ -+ if (val == 0x8855) -+ return 0; -+ -+ return -ENODEV; -+} -+ -+MTK_ETH_SWITCH(an8855) = { -+ .name = "an8855", -+ .desc = "Airoha AN8855", -+ .priv_size = sizeof(struct an8855_switch_priv), -+ .reset_wait_time = 100, -+ -+ .detect = an8855_detect, -+ .setup = an8855_setup, -+ .cleanup = an8855_cleanup, -+ .mac_control = an8855_mac_control, -+}; diff --git a/package/boot/uboot-mediatek/patches/070-01-board-mediatek-mt7622-remove-board_late_init.patch b/package/boot/uboot-mediatek/patches/070-01-board-mediatek-mt7622-remove-board_late_init.patch deleted file mode 100644 index 374093734f..0000000000 --- a/package/boot/uboot-mediatek/patches/070-01-board-mediatek-mt7622-remove-board_late_init.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 92090b92fab207250d5b8d5a4a36aa34f5a91f19 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:16:33 +0800 -Subject: [PATCH 01/15] board: mediatek: mt7622: remove board_late_init - -The function board_late_init defined for mt7622 is useless now. Just -remove it. - -Signed-off-by: Weijie Gao ---- - board/mediatek/mt7622/mt7622_rfb.c | 7 ------- - 1 file changed, 7 deletions(-) - ---- a/board/mediatek/mt7622/mt7622_rfb.c -+++ b/board/mediatek/mt7622/mt7622_rfb.c -@@ -15,10 +15,3 @@ int board_init(void) - { - return 0; - } -- --int board_late_init(void) --{ -- gd->env_valid = 1; //to load environment variable from persistent store -- env_relocate(); -- return 0; --} diff --git a/package/boot/uboot-mediatek/patches/070-02-clk-mediatek-fix-uninitialized-fields-issue-in-INFRA.patch b/package/boot/uboot-mediatek/patches/070-02-clk-mediatek-fix-uninitialized-fields-issue-in-INFRA.patch deleted file mode 100644 index 4e16fe78d4..0000000000 --- a/package/boot/uboot-mediatek/patches/070-02-clk-mediatek-fix-uninitialized-fields-issue-in-INFRA.patch +++ /dev/null @@ -1,48 +0,0 @@ -From b033dfb21df8ae876ec69d84bc8c5fafd7aa8ced Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:16:38 +0800 -Subject: [PATCH 02/15] clk: mediatek: fix uninitialized fields issue in - INFRA_MUX struct - -This patch adds missing initialization of fields in INFRA_MUX struct -which caused uart broken after any other infra mux being enabled by -'clk_prepare_enable' - -Signed-off-by: Sam Shih -Signed-off-by: Weijie Gao ---- - drivers/clk/mediatek/clk-mt7981.c | 1 + - drivers/clk/mediatek/clk-mt7986.c | 1 + - drivers/clk/mediatek/clk-mt7988.c | 1 + - 3 files changed, 3 insertions(+) - ---- a/drivers/clk/mediatek/clk-mt7981.c -+++ b/drivers/clk/mediatek/clk-mt7981.c -@@ -359,6 +359,7 @@ static const struct mtk_parent infra_pci - .id = _id, .mux_reg = (_reg) + 0x8, \ - .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ - .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ -+ .gate_shift = -1, .upd_shift = -1, \ - .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ - } ---- a/drivers/clk/mediatek/clk-mt7986.c -+++ b/drivers/clk/mediatek/clk-mt7986.c -@@ -366,6 +366,7 @@ static const struct mtk_parent infra_pci - .id = _id, .mux_reg = (_reg) + 0x8, \ - .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ - .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ -+ .gate_shift = -1, .upd_shift = -1, \ - .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ - } ---- a/drivers/clk/mediatek/clk-mt7988.c -+++ b/drivers/clk/mediatek/clk-mt7988.c -@@ -485,6 +485,7 @@ static const int infra_pcie_gfmux_tl_ck_ - .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \ - .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ - .mux_mask = BIT(_width) - 1, .parent = _parents, \ -+ .gate_shift = -1, .upd_shift = -1, \ - .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ - } diff --git a/package/boot/uboot-mediatek/patches/070-03-configs-mt7629-move-image-load-address-to-0x42000000.patch b/package/boot/uboot-mediatek/patches/070-03-configs-mt7629-move-image-load-address-to-0x42000000.patch deleted file mode 100644 index b17986ead5..0000000000 --- a/package/boot/uboot-mediatek/patches/070-03-configs-mt7629-move-image-load-address-to-0x42000000.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 7958b41b8c6a15c3c993affd2091f8c921b6a8a1 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:17:38 +0800 -Subject: [PATCH 03/15] configs: mt7629: move image load address to 0x42000000 - -Update the image load address to ensure it matches the mt7629 NOR -controller's DMA alignment requirements. - -Signed-off-by: Sam Shih -Signed-off-by: Weijie Gao ---- - configs/mt7629_rfb_defconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/configs/mt7629_rfb_defconfig -+++ b/configs/mt7629_rfb_defconfig -@@ -18,7 +18,7 @@ CONFIG_SPL_STACK=0x106000 - CONFIG_SPL_TEXT_BASE=0x201000 - CONFIG_SPL_STACK_R=y - CONFIG_SYS_BOOTM_LEN=0x4000000 --CONFIG_SYS_LOAD_ADDR=0x42007f1c -+CONFIG_SYS_LOAD_ADDR=0x42000000 - CONFIG_SPL_PAYLOAD="u-boot-lzma.img" - CONFIG_BUILD_TARGET="u-boot-mtk.bin" - CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin" diff --git a/package/boot/uboot-mediatek/patches/070-04-configs-mt7988-move-image-load-address-to-0x44000000.patch b/package/boot/uboot-mediatek/patches/070-04-configs-mt7988-move-image-load-address-to-0x44000000.patch deleted file mode 100644 index e03c9b0305..0000000000 --- a/package/boot/uboot-mediatek/patches/070-04-configs-mt7988-move-image-load-address-to-0x44000000.patch +++ /dev/null @@ -1,24 +0,0 @@ -From c7a3761ddfce2bd56ad319a254d5269cb26fa18f Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:17:44 +0800 -Subject: [PATCH 04/15] configs: mt7988: move image load address to 0x44000000 - -This patch sets mt7988 image load address to 0x44000000 to support loading -larger images. - -Signed-off-by: Weijie Gao ---- - configs/mt7988_rfb_defconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/configs/mt7988_rfb_defconfig -+++ b/configs/mt7988_rfb_defconfig -@@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 - CONFIG_NR_DRAM_BANKS=1 - CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb" - CONFIG_TARGET_MT7988=y --CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SYS_LOAD_ADDR=0x44000000 - CONFIG_DEBUG_UART_BASE=0x11000000 - CONFIG_DEBUG_UART_CLOCK=40000000 - CONFIG_DEBUG_UART=y diff --git a/package/boot/uboot-mediatek/patches/070-05-spi-mtk_spim-add-support-to-use-DT-live-tree.patch b/package/boot/uboot-mediatek/patches/070-05-spi-mtk_spim-add-support-to-use-DT-live-tree.patch deleted file mode 100644 index 4b90136687..0000000000 --- a/package/boot/uboot-mediatek/patches/070-05-spi-mtk_spim-add-support-to-use-DT-live-tree.patch +++ /dev/null @@ -1,23 +0,0 @@ -From a2c2ac46ca4c4ef5fe043e584cf867a20e93226d Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:17:51 +0800 -Subject: [PATCH 05/15] spi: mtk_spim: add support to use DT live tree - -Change devfdt_get_addr_ptr to dev_read_addr_ptr to support DT live tree. - -Signed-off-by: Weijie Gao ---- - drivers/spi/mtk_spim.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/spi/mtk_spim.c -+++ b/drivers/spi/mtk_spim.c -@@ -648,7 +648,7 @@ static int mtk_spim_probe(struct udevice - struct mtk_spim_priv *priv = dev_get_priv(dev); - int ret; - -- priv->base = devfdt_get_addr_ptr(dev); -+ priv->base = dev_read_addr_ptr(dev); - if (!priv->base) - return -EINVAL; - diff --git a/package/boot/uboot-mediatek/patches/070-06-spi-mtk_spim-check-slave-device-mode-in-spi-mem-s-su.patch b/package/boot/uboot-mediatek/patches/070-06-spi-mtk_spim-check-slave-device-mode-in-spi-mem-s-su.patch deleted file mode 100644 index c30105bb5f..0000000000 --- a/package/boot/uboot-mediatek/patches/070-06-spi-mtk_spim-check-slave-device-mode-in-spi-mem-s-su.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 7725d4ba16577b74567f7cffb2faffa8bdc5ad61 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:17:55 +0800 -Subject: [PATCH 06/15] spi: mtk_spim: check slave device mode in spi-mem's - supports_op - -Call spi_mem_default_supports_op() in supports_op to honor the -slave's supported single/dual/quad mode settings. - -Signed-off-by: SkyLake.Huang -Signed-off-by: Weijie Gao ---- - drivers/spi/mtk_spim.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/spi/mtk_spim.c -+++ b/drivers/spi/mtk_spim.c -@@ -359,6 +359,9 @@ static bool mtk_spim_supports_op(struct - struct udevice *bus = dev_get_parent(slave->dev); - struct mtk_spim_priv *priv = dev_get_priv(bus); - -+ if (!spi_mem_default_supports_op(slave, op)) -+ return false; -+ - if (op->cmd.buswidth == 0 || op->cmd.buswidth > 4 || - op->addr.buswidth > 4 || op->dummy.buswidth > 4 || - op->data.buswidth > 4) diff --git a/package/boot/uboot-mediatek/patches/070-07-arm-dts-mediatek-add-quad-mode-capabilities-for-SPI-.patch b/package/boot/uboot-mediatek/patches/070-07-arm-dts-mediatek-add-quad-mode-capabilities-for-SPI-.patch deleted file mode 100644 index bfcbd644aa..0000000000 --- a/package/boot/uboot-mediatek/patches/070-07-arm-dts-mediatek-add-quad-mode-capabilities-for-SPI-.patch +++ /dev/null @@ -1,96 +0,0 @@ -From c7a602028669f4409538c3ce0a63c4054d0f2b7a Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:18:01 +0800 -Subject: [PATCH 07/15] arm: dts: mediatek: add quad mode capabilities for SPI - flashes - -Explicitly add quad mode capabilities or the SPI controller may -start transfer in single mode. - -Signed-off-by: SkyLake.Huang -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7981-rfb.dts | 4 ++++ - arch/arm/dts/mt7986a-rfb.dts | 4 ++++ - arch/arm/dts/mt7986b-rfb.dts | 4 ++++ - arch/arm/dts/mt7988-rfb.dts | 4 ++++ - 4 files changed, 16 insertions(+) - ---- a/arch/arm/dts/mt7981-rfb.dts -+++ b/arch/arm/dts/mt7981-rfb.dts -@@ -143,6 +143,8 @@ - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; - }; - }; - -@@ -164,6 +166,8 @@ - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <52000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; - }; - }; - ---- a/arch/arm/dts/mt7986a-rfb.dts -+++ b/arch/arm/dts/mt7986a-rfb.dts -@@ -190,12 +190,16 @@ - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <52000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; - }; - - spi_nand@1 { - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <52000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; - }; - }; - ---- a/arch/arm/dts/mt7986b-rfb.dts -+++ b/arch/arm/dts/mt7986b-rfb.dts -@@ -177,12 +177,16 @@ - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <52000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; - }; - - spi_nand@1 { - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <52000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; - }; - }; - ---- a/arch/arm/dts/mt7988-rfb.dts -+++ b/arch/arm/dts/mt7988-rfb.dts -@@ -144,6 +144,8 @@ - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; - }; - }; - -@@ -165,6 +167,8 @@ - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <52000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; - }; - }; - diff --git a/package/boot/uboot-mediatek/patches/070-08-pwm-mediatek-add-pwm3-support-for-mt7981.patch b/package/boot/uboot-mediatek/patches/070-08-pwm-mediatek-add-pwm3-support-for-mt7981.patch deleted file mode 100644 index a11742a213..0000000000 --- a/package/boot/uboot-mediatek/patches/070-08-pwm-mediatek-add-pwm3-support-for-mt7981.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 7071ba2658ef6175183cc5dc85819293811490b3 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:18:06 +0800 -Subject: [PATCH 08/15] pwm: mediatek: add pwm3 support for mt7981 - -This patch adds pwm channel 2 (pwm3) support for mt7981 - -Signed-off-by: Sam Shih -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7981-emmc-rfb.dts | 8 ++++++++ - arch/arm/dts/mt7981-rfb.dts | 8 ++++++++ - arch/arm/dts/mt7981-sd-rfb.dts | 8 ++++++++ - arch/arm/dts/mt7981.dtsi | 10 ++++++++-- - drivers/pwm/pwm-mtk.c | 2 +- - 5 files changed, 33 insertions(+), 3 deletions(-) - ---- a/arch/arm/dts/mt7981-emmc-rfb.dts -+++ b/arch/arm/dts/mt7981-emmc-rfb.dts -@@ -95,6 +95,14 @@ - }; - }; - -+ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */ -+ three_pwm_pins_1: three-pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_0", "pwm1_1", "pwm2"; -+ }; -+ }; -+ - mmc0_pins_default: mmc0default { - mux { - function = "flash"; ---- a/arch/arm/dts/mt7981-rfb.dts -+++ b/arch/arm/dts/mt7981-rfb.dts -@@ -123,6 +123,14 @@ - groups = "pwm0_1", "pwm1_0", "pwm2"; - }; - }; -+ -+ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */ -+ three_pwm_pins_1: three-pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_0", "pwm1_1", "pwm2"; -+ }; -+ }; - }; - - &spi0 { ---- a/arch/arm/dts/mt7981-sd-rfb.dts -+++ b/arch/arm/dts/mt7981-sd-rfb.dts -@@ -95,6 +95,14 @@ - }; - }; - -+ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */ -+ three_pwm_pins_1: three-pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0_0", "pwm1_1", "pwm2"; -+ }; -+ }; -+ - mmc0_pins_default: mmc0default { - mux { - function = "flash"; ---- a/arch/arm/dts/mt7981.dtsi -+++ b/arch/arm/dts/mt7981.dtsi -@@ -137,8 +137,14 @@ - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>, - <&infracfg CLK_INFRA_PWM3_CK>; -- assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>; -- assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>; -+ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>, -+ <&infracfg CLK_INFRA_PWM1_SEL>, -+ <&infracfg CLK_INFRA_PWM2_SEL>, -+ <&infracfg CLK_INFRA_PWM3_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, -+ <&topckgen CLK_TOP_PWM_SEL>, -+ <&topckgen CLK_TOP_PWM_SEL>, -+ <&topckgen CLK_TOP_PWM_SEL>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; - status = "disabled"; - }; ---- a/drivers/pwm/pwm-mtk.c -+++ b/drivers/pwm/pwm-mtk.c -@@ -192,7 +192,7 @@ static const struct mtk_pwm_soc mt7629_d - }; - - static const struct mtk_pwm_soc mt7981_data = { -- .num_pwms = 2, -+ .num_pwms = 3, - .pwm45_fixup = false, - .reg_ver = PWM_REG_V2, - }; diff --git a/package/boot/uboot-mediatek/patches/070-09-pci-mediatek-add-support-for-multiple-ports-in-media.patch b/package/boot/uboot-mediatek/patches/070-09-pci-mediatek-add-support-for-multiple-ports-in-media.patch deleted file mode 100644 index cc23dda975..0000000000 --- a/package/boot/uboot-mediatek/patches/070-09-pci-mediatek-add-support-for-multiple-ports-in-media.patch +++ /dev/null @@ -1,61 +0,0 @@ -From dfbadb86b3bc43c004671ab6eb46ee160a192e98 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:18:11 +0800 -Subject: [PATCH 09/15] pci: mediatek: add support for multiple ports in - mediatek pcie gen3 driver - -One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0 -on this port represents the controller itself and bus 1 represents -the external PCIe device. - -If multiple PCIe controllers are probed in U-Boot, U-Boot will use -bus numbers greater than 2 as input parameters. Therefore, we should -convert the BDF bus number to either 0 or 1 by subtracting the -offset by controller->seq_. - -Signed-off-by: Sam Shih -Signed-off-by: Weijie Gao ---- - drivers/pci/pcie_mediatek_gen3.c | 24 ++++++++++++++++++++++++ - 1 file changed, 24 insertions(+) - ---- a/drivers/pci/pcie_mediatek_gen3.c -+++ b/drivers/pci/pcie_mediatek_gen3.c -@@ -83,6 +83,28 @@ struct mtk_pcie { - struct phy phy; - }; - -+static pci_dev_t convert_bdf(const struct udevice *controller, pci_dev_t bdf) -+{ -+ int bdfs[3]; -+ -+ bdfs[0] = PCI_BUS(bdf); -+ bdfs[1] = PCI_DEV(bdf); -+ bdfs[2] = PCI_FUNC(bdf); -+ -+ /* -+ * One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0 on -+ * this port represents the controller itself and bus 1 represents the -+ * external PCIe device. If multiple PCIe controllers are probed in U-Boot, -+ * U-Boot will use bus numbers greater than 2 as input parameters. Therefore, -+ * we should convert the BDF bus number to either 0 or 1 by subtracting the -+ * offset by controller->seq_ -+ */ -+ -+ bdfs[0] = bdfs[0] - controller->seq_; -+ -+ return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]); -+} -+ - static void mtk_pcie_config_tlp_header(const struct udevice *bus, - pci_dev_t devfn, - int where, int size) -@@ -91,6 +113,8 @@ static void mtk_pcie_config_tlp_header(c - int bytes; - u32 val; - -+ devfn = convert_bdf(bus, devfn); -+ - size = 1 << size; - bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3); - diff --git a/package/boot/uboot-mediatek/patches/070-10-arm-dts-mediatek-add-pcie-support-for-mt7988.patch b/package/boot/uboot-mediatek/patches/070-10-arm-dts-mediatek-add-pcie-support-for-mt7988.patch deleted file mode 100644 index 0b72a0d232..0000000000 --- a/package/boot/uboot-mediatek/patches/070-10-arm-dts-mediatek-add-pcie-support-for-mt7988.patch +++ /dev/null @@ -1,219 +0,0 @@ -From 4064eb22e221ce93fef7f1ec3b13ac670c6b20e2 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:18:17 +0800 -Subject: [PATCH 10/15] arm: dts: mediatek: add pcie support for mt7988 - -This patch adds PCIe support for mt7988 - -Signed-off-by: Sam Shih -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7988-rfb.dts | 18 ++++ - arch/arm/dts/mt7988.dtsi | 162 ++++++++++++++++++++++++++++++++++++ - 2 files changed, 180 insertions(+) - ---- a/arch/arm/dts/mt7988-rfb.dts -+++ b/arch/arm/dts/mt7988-rfb.dts -@@ -63,6 +63,24 @@ - }; - }; - -+&pcie0 { -+ status = "okay"; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; -+ -+/* PCIE2 not working in u-boot */ -+&pcie2 { -+ status = "disabled"; -+}; -+ -+/* PCIE3 not working in u-boot */ -+&pcie3 { -+ status = "disabled"; -+}; -+ - &pinctrl { - i2c1_pins: i2c1-pins { - mux { ---- a/arch/arm/dts/mt7988.dtsi -+++ b/arch/arm/dts/mt7988.dtsi -@@ -188,6 +188,152 @@ - status = "okay"; - }; - -+ pcie2: pcie@11280000 { -+ compatible = "mediatek,mt7988-pcie", -+ "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0 0x11280000 0 0x2000>; -+ reg-names = "pcie-mac"; -+ linux,pci-domain = <3>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x20200000 0 0x20200000 0 0x07e00000>; -+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, -+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, -+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, -+ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", -+ "top_133m"; -+ phys = <&xphyu3port0 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ -+ status = "disabled"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc2 0>, -+ <0 0 0 2 &pcie_intc2 1>, -+ <0 0 0 3 &pcie_intc2 2>, -+ <0 0 0 4 &pcie_intc2 3>; -+ -+ pcie_intc2: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie3: pcie@11290000 { -+ compatible = "mediatek,mt7988-pcie", -+ "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0 0x11290000 0 0x2000>; -+ reg-names = "pcie-mac"; -+ linux,pci-domain = <2>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x28200000 0 0x28200000 0 0x07e00000>; -+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, -+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, -+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, -+ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", -+ "top_133m"; -+ use-dedicated-phy; -+ -+ status = "disabled"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc3 0>, -+ <0 0 0 2 &pcie_intc3 1>, -+ <0 0 0 3 &pcie_intc3 2>, -+ <0 0 0 4 &pcie_intc3 3>; -+ pcie_intc3: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie0: pcie@11300000 { -+ compatible = "mediatek,mt7988-pcie", -+ "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0 0x11300000 0 0x2000>; -+ reg-names = "pcie-mac"; -+ linux,pci-domain = <0>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x30200000 0 0x30200000 0 0x07e00000>; -+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, -+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, -+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, -+ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", -+ "top_133m"; -+ use-dedicated-phy; -+ -+ status = "disabled"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc0 0>, -+ <0 0 0 2 &pcie_intc0 1>, -+ <0 0 0 3 &pcie_intc0 2>, -+ <0 0 0 4 &pcie_intc0 3>; -+ pcie_intc0: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie1: pcie@11310000 { -+ compatible = "mediatek,mt7988-pcie", -+ "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0 0x11310000 0 0x2000>; -+ reg-names = "pcie-mac"; -+ linux,pci-domain = <1>; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x38200000 0 0x38200000 0 0x07e00000>; -+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, -+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, -+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, -+ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", -+ "top_133m"; -+ use-dedicated-phy; -+ -+ status = "disabled"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc1 0>, -+ <0 0 0 2 &pcie_intc1 1>, -+ <0 0 0 3 &pcie_intc1 2>, -+ <0 0 0 4 &pcie_intc1 3>; -+ pcie_intc1: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ - usbtphy: usb-phy@11c50000 { - compatible = "mediatek,mt7988", - "mediatek,generic-tphy-v2"; -@@ -214,6 +360,22 @@ - status = "okay"; - }; - }; -+ -+ xphy: xphy@11e10000 { -+ compatible = "mediatek,mt7988", "mediatek,xsphy"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ xphyu3port0: usb-phy@11e13000 { -+ reg = <0 0x11e13400 0 0x500>; -+ clocks = <&dummy_clk>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ status = "okay"; -+ }; -+ }; - - xfi_pextp0: syscon@11f20000 { - compatible = "mediatek,mt7988-xfi_pextp_0", "syscon"; diff --git a/package/boot/uboot-mediatek/patches/070-11-arm-dts-medaitek-fix-internal-switch-link-speed-of-m.patch b/package/boot/uboot-mediatek/patches/070-11-arm-dts-medaitek-fix-internal-switch-link-speed-of-m.patch deleted file mode 100644 index 73caeca7ca..0000000000 --- a/package/boot/uboot-mediatek/patches/070-11-arm-dts-medaitek-fix-internal-switch-link-speed-of-m.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 4a85182570200bf5e87e2a9920e9d28e968bc6e0 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:18:22 +0800 -Subject: [PATCH 11/15] arm: dts: medaitek: fix internal switch link speed of - mt7988 - -The CPU port of mt7988 internal switch uses 10Gb link speed. - -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7988-rfb.dts | 2 +- - arch/arm/dts/mt7988-sd-rfb.dts | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/dts/mt7988-rfb.dts -+++ b/arch/arm/dts/mt7988-rfb.dts -@@ -57,7 +57,7 @@ - mediatek,switch = "mt7988"; - - fixed-link { -- speed = <1000>; -+ speed = <10000>; - full-duplex; - pause; - }; ---- a/arch/arm/dts/mt7988-sd-rfb.dts -+++ b/arch/arm/dts/mt7988-sd-rfb.dts -@@ -48,7 +48,7 @@ - mediatek,switch = "mt7988"; - - fixed-link { -- speed = <1000>; -+ speed = <10000>; - full-duplex; - pause; - }; diff --git a/package/boot/uboot-mediatek/patches/070-12-arm-dts-mediatek-add-support-for-all-three-GMACs-for.patch b/package/boot/uboot-mediatek/patches/070-12-arm-dts-mediatek-add-support-for-all-three-GMACs-for.patch deleted file mode 100644 index f1c9aaa76f..0000000000 --- a/package/boot/uboot-mediatek/patches/070-12-arm-dts-mediatek-add-support-for-all-three-GMACs-for.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 64cf3dd0ef520a81a27359d83d58b64939e2aa06 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:18:27 +0800 -Subject: [PATCH 12/15] arm: dts: mediatek: add support for all three GMACs for - mt7988 - -This patch add all three GMACs nodes for mt7988. Each GMAC can be -configured to connect to different ethernet switches/PHYs. - -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7988-rfb.dts | 3 +-- - arch/arm/dts/mt7988-sd-rfb.dts | 3 +-- - arch/arm/dts/mt7988.dtsi | 42 ++++++++++++++++++++++++++++++++-- - 3 files changed, 42 insertions(+), 6 deletions(-) - ---- a/arch/arm/dts/mt7988-rfb.dts -+++ b/arch/arm/dts/mt7988-rfb.dts -@@ -50,9 +50,8 @@ - status = "okay"; - }; - --ð { -+ð0 { - status = "okay"; -- mediatek,gmac-id = <0>; - phy-mode = "usxgmii"; - mediatek,switch = "mt7988"; - ---- a/arch/arm/dts/mt7988-sd-rfb.dts -+++ b/arch/arm/dts/mt7988-sd-rfb.dts -@@ -41,9 +41,8 @@ - status = "okay"; - }; - --ð { -+ð0 { - status = "okay"; -- mediatek,gmac-id = <0>; - phy-mode = "usxgmii"; - mediatek,switch = "mt7988"; - ---- a/arch/arm/dts/mt7988.dtsi -+++ b/arch/arm/dts/mt7988.dtsi -@@ -587,11 +587,11 @@ - #reset-cells = <1>; - }; - -- eth: ethernet@15100000 { -+ eth0: ethernet@15110100 { - compatible = "mediatek,mt7988-eth", "syscon"; - reg = <0 0x15100000 0 0x20000>; -+ mediatek,gmac-id = <0>; - mediatek,ethsys = <ðdma>; -- mediatek,sgmiisys = <&sgmiisys0>; - mediatek,usxgmiisys = <&usxgmiisys0>; - mediatek,xfi_pextp = <&xfi_pextp0>; - mediatek,xfi_pll = <&xfi_pll>; -@@ -602,6 +602,44 @@ - #address-cells = <1>; - #size-cells = <0>; - mediatek,mcm; -+ status = "disabled"; -+ }; -+ -+ eth1: ethernet@15110200 { -+ compatible = "mediatek,mt7988-eth", "syscon"; -+ reg = <0 0x15100000 0 0x20000>; -+ mediatek,gmac-id = <1>; -+ mediatek,ethsys = <ðdma>; -+ mediatek,sgmiisys = <&sgmiisys1>; -+ mediatek,usxgmiisys = <&usxgmiisys1>; -+ mediatek,xfi_pextp = <&xfi_pextp1>; -+ mediatek,xfi_pll = <&xfi_pll>; -+ mediatek,infracfg = <&topmisc>; -+ mediatek,toprgu = <&watchdog>; -+ resets = <ðdma ETHDMA_FE_RST>; -+ reset-names = "fe"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ mediatek,mcm; -+ status = "disabled"; -+ }; -+ -+ eth2: ethernet@15110300 { -+ compatible = "mediatek,mt7988-eth", "syscon"; -+ reg = <0 0x15100000 0 0x20000>; -+ mediatek,gmac-id = <2>; -+ mediatek,ethsys = <ðdma>; -+ mediatek,sgmiisys = <&sgmiisys0>; -+ mediatek,usxgmiisys = <&usxgmiisys0>; -+ mediatek,xfi_pextp = <&xfi_pextp0>; -+ mediatek,xfi_pll = <&xfi_pll>; -+ mediatek,infracfg = <&topmisc>; -+ mediatek,toprgu = <&watchdog>; -+ resets = <ðdma ETHDMA_FE_RST>; -+ reset-names = "fe"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ mediatek,mcm; - status = "disabled"; - }; - }; diff --git a/package/boot/uboot-mediatek/patches/070-13-arm-dts-medaitek-add-flash-interface-driving-setting.patch b/package/boot/uboot-mediatek/patches/070-13-arm-dts-medaitek-add-flash-interface-driving-setting.patch deleted file mode 100644 index ec948ef207..0000000000 --- a/package/boot/uboot-mediatek/patches/070-13-arm-dts-medaitek-add-flash-interface-driving-setting.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 1090c6df3767da2c56d5827ba65ce91af8745420 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:18:41 +0800 -Subject: [PATCH 13/15] arm: dts: medaitek: add flash interface driving - settings for mt7988 - -Add driving settings for both SPI and SD/eMMC interfaces to support ensure -flash devices is accessible for ram-booting. - -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7988-rfb.dts | 32 ++++++++++++++++++++++++++++++++ - 1 file changed, 32 insertions(+) - ---- a/arch/arm/dts/mt7988-rfb.dts -+++ b/arch/arm/dts/mt7988-rfb.dts -@@ -101,6 +101,19 @@ - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; -+ -+ conf-pu { -+ pins = "SPI0_CSB", "SPI0_HOLD", "SPI0_WP"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; -+ - }; - - spi2_pins: spi2-pins { -@@ -108,6 +121,18 @@ - function = "spi"; - groups = "spi2", "spi2_wp_hold"; - }; -+ -+ conf-pu { -+ pins = "SPI2_CSB", "SPI2_HOLD", "SPI2_WP"; -+ drive-strength = ; -+ bias-pull-up = ; -+ }; -+ -+ conf-pd { -+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; -+ drive-strength = ; -+ bias-pull-down = ; -+ }; - }; - - mmc0_pins_default: mmc0default { -@@ -121,18 +146,25 @@ - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; -+ drive-strength = ; -+ mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - - conf-clk { - pins = "EMMC_CK"; -+ drive-strength = ; -+ mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - - conf-dsl { - pins = "EMMC_DSL"; -+ mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - - conf-rst { - pins = "EMMC_RSTB"; -+ drive-strength = ; -+ mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - }; - }; diff --git a/package/boot/uboot-mediatek/patches/070-14-arm-dts-mediatek-update-mt7981-mmc-node.patch b/package/boot/uboot-mediatek/patches/070-14-arm-dts-mediatek-update-mt7981-mmc-node.patch deleted file mode 100644 index a6b47d7cc8..0000000000 --- a/package/boot/uboot-mediatek/patches/070-14-arm-dts-mediatek-update-mt7981-mmc-node.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 140303d0308738dfb04059333c9fc25b5159a776 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:18:55 +0800 -Subject: [PATCH 14/15] arm: dts: mediatek: update mt7981 mmc node - -1. Fix mmc clock order of mt7981 to match the clock name -2. Limit the max clock of SD to 50MHz to meet SD Card Spec 2.0 -3. Increase the CLK pin driving strength to 8mA - -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7981-sd-rfb.dts | 6 ++++-- - arch/arm/dts/mt7981.dtsi | 12 ++++++------ - 2 files changed, 10 insertions(+), 8 deletions(-) - ---- a/arch/arm/dts/mt7981-sd-rfb.dts -+++ b/arch/arm/dts/mt7981-sd-rfb.dts -@@ -118,7 +118,7 @@ - }; - conf-clk { - pins = "SPI1_CS"; -- drive-strength = ; -+ drive-strength = ; - bias-pull-down = ; - }; - conf-rst { -@@ -140,10 +140,12 @@ - }; - - &mmc0 { -+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>, -+ <&topckgen CLK_TOP_CB_NET2_D2>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_default>; - bus-width = <4>; -- max-frequency = <52000000>; -+ max-frequency = <50000000>; - cap-sd-highspeed; - r_smpl = <0>; - vmmc-supply = <®_3p3v>; ---- a/arch/arm/dts/mt7981.dtsi -+++ b/arch/arm/dts/mt7981.dtsi -@@ -306,13 +306,13 @@ - reg = <0x11230000 0x1000>, - <0x11C20000 0x1000>; - interrupts = ; -- clocks = <&topckgen CLK_TOP_EMMC_400M>, -- <&topckgen CLK_TOP_EMMC_208M>, -+ clocks = <&topckgen CLK_TOP_EMMC_208M>, -+ <&topckgen CLK_TOP_EMMC_400M>, - <&infracfg CLK_INFRA_MSDC_CK>; -- assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>, -- <&topckgen CLK_TOP_EMMC_208M_SEL>; -- assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>, -- <&topckgen CLK_TOP_CB_M_D2>; -+ assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, -+ <&topckgen CLK_TOP_EMMC_400M_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, -+ <&topckgen CLK_TOP_CB_NET2_D2>; - clock-names = "source", "hclk", "source_cg"; - status = "disabled"; - }; diff --git a/package/boot/uboot-mediatek/patches/070-15-MAINTAINERS-update-file-list-for-MediaTek-ARM-platfo.patch b/package/boot/uboot-mediatek/patches/070-15-MAINTAINERS-update-file-list-for-MediaTek-ARM-platfo.patch deleted file mode 100644 index 81fcac7819..0000000000 --- a/package/boot/uboot-mediatek/patches/070-15-MAINTAINERS-update-file-list-for-MediaTek-ARM-platfo.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 8707ea0360046522d0784135b6c9a7c564f9515c Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 17 Jan 2025 17:18:59 +0800 -Subject: [PATCH 15/15] MAINTAINERS: update file list for MediaTek ARM platform - -Add driver files for MediaTek ARM platform - -Signed-off-by: Weijie Gao ---- - MAINTAINERS | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -412,9 +412,13 @@ F: drivers/mmc/mtk-sd.c - F: drivers/phy/phy-mtk-* - F: drivers/pinctrl/mediatek/ - F: drivers/power/domain/mtk-power-domain.c -+F: drivers/pci/pcie_mediatek_gen3.c -+F: drivers/pci/pcie_mediatek.c -+F: drivers/pwm/pwm-mtk.c - F: drivers/ram/mediatek/ - F: drivers/spi/mtk_snfi_spi.c - F: drivers/spi/mtk_spim.c -+F: drivers/spi/mtk_snor.c - F: drivers/timer/mtk_timer.c - F: drivers/usb/host/xhci-mtk.c - F: drivers/usb/mtu3/ -@@ -422,6 +426,7 @@ F: drivers/watchdog/mtk_wdt.c - F: drivers/net/mtk_eth.c - F: drivers/net/mtk_eth.h - F: drivers/reset/reset-mediatek.c -+F: drivers/serial/serial_mtk.c - F: include/dt-bindings/clock/mediatek,* - F: include/dt-bindings/power/mediatek,* - F: tools/mtk_image.c diff --git a/package/boot/uboot-mediatek/patches/071-01-pinctrl-mediatek-update-mt7981-pinctrl-driver-based-.patch b/package/boot/uboot-mediatek/patches/071-01-pinctrl-mediatek-update-mt7981-pinctrl-driver-based-.patch deleted file mode 100644 index e6d0ec35fa..0000000000 --- a/package/boot/uboot-mediatek/patches/071-01-pinctrl-mediatek-update-mt7981-pinctrl-driver-based-.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 24e660265f11dad63687c5529cf732538946a197 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Fri, 24 Jan 2025 11:39:02 +0800 -Subject: [PATCH] pinctrl: mediatek: update mt7981 pinctrl driver based on - upstream kernel - -Update mt7981 pinctrl driver based on upstream kernel - -Signed-off-by: Sam Shih -Signed-off-by: Weijie Gao ---- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 51 ++++++++++++++++++++--- - 1 file changed, 45 insertions(+), 6 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -569,6 +569,11 @@ static const struct mtk_pin_desc mt7981_ - MT7981_TYPE1_PIN(56, "WF_HB10"), - }; - -+/* List all groups consisting of these pins dedicated to the enablement of -+ * certain hardware block and the corresponding mode for all of the pins. -+ * The hardware probably has multiple combinations of these pinouts. -+ */ -+ - /* WA_AICE */ - static const int mt7981_wa_aice1_pins[] = { 0, 1, }; - static const int mt7981_wa_aice1_funcs[] = { 2, 2, }; -@@ -632,6 +637,9 @@ static const int mt7981_wo0_jtag_1_funcs - static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; - static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; - -+static const int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; -+static const int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; -+ - /* GBE_LED0 */ - static const int mt7981_gbe_led0_pins[] = { 8, }; - static const int mt7981_gbe_led0_funcs[] = { 3, }; -@@ -718,6 +726,17 @@ static const int mt7981_drv_vbus_pins[] - static const int mt7981_drv_vbus_funcs[] = { 1, }; - - /* EMMC */ -+static const int mt7981_emmc_reset_pins[] = { 15, }; -+static const int mt7981_emmc_reset_funcs[] = { 2, }; -+ -+static const int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, }; -+static const int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, }; -+ -+static const int mt7981_emmc_8_pins[] = { -+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; -+static const int mt7981_emmc_8_funcs[] = { -+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -+ - static const int mt7981_emmc_45_pins[] = { - 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; - static const int mt7981_emmc_45_funcs[] = { -@@ -754,6 +773,12 @@ static const int mt7981_uart1_0_funcs[] - static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; - static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; - -+static const int mt7981_uart1_2_pins[] = { 9, 10, }; -+static const int mt7981_uart1_2_funcs[] = { 2, 2, }; -+ -+static const int mt7981_uart1_3_pins[] = { 26, 27, }; -+static const int mt7981_uart1_3_funcs[] = { 2, 2, }; -+ - /* UART2 */ - static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; - static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; -@@ -832,6 +857,8 @@ static const struct mtk_group_desc mt798 - PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), - /* @GPIO(4,7) WM_JTAG(3) */ - PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), -+ /* @GPIO(4,5) WM_JTAG(4) */ -+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), - /* @GPIO(8) GBE_LED0(3) */ - PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), - /* @GPIO(4,6) PTA_EXT(4) */ -@@ -844,7 +871,7 @@ static const struct mtk_group_desc mt798 - PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), - /* @GPIO(6,7) I2C(5) */ - PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), -- /* @GPIO(8): DFD_NTRST(6) */ -+ /* @GPIO(0,1,4,5): DFD_NTRST(6) */ - PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), - /* @GPIO(9,10): WM_AICE(2) */ - PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), -@@ -870,6 +897,12 @@ static const struct mtk_group_desc mt798 - PINCTRL_PIN_GROUP("udi", mt7981_udi), - /* @GPIO(14) DRV_VBUS(1) */ - PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), -+ /* @GPIO(15): EMMC_RSTB(2) */ -+ PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset), -+ /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ -+ PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4), -+ /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ -+ PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8), - /* @GPIO(15,25): EMMC(2) */ - PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), - /* @GPIO(16,21): SNFI(3) */ -@@ -888,8 +921,12 @@ static const struct mtk_group_desc mt798 - PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), - /* @GPIO(26,29): UART1(2) */ - PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), -+ /* @GPIO(9,10): UART1(2) */ -+ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), -+ /* @GPIO(26,27): UART1(2) */ -+ PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3), - /* @GPIO(22,25): UART2(3) */ -- PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_1), -+ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), - /* @GPIO(22,24) PTA_EXT(4) */ - PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), - /* @GPIO(20,21): WM_UART(4) */ -@@ -964,9 +1001,10 @@ static const struct mtk_io_type_desc mt7 - */ - static const char *const mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", - "wm_aice1_1", "wa_aice3", "wm_aice1_2", }; --static const char *const mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", -- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", -- "uart1_0", "uart1_1", "uart2_0", "wm_aurt_1", "wm_aurt_2", "uart0", }; -+static const char *const mt7981_uart_groups[] = { "net_wo0_uart_txd_0", -+ "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", "uart0", "uart1_0", -+ "uart1_1", "uart1_2", "uart1_3", "uart2_0", "uart2_0_tx_rx", "uart2_1", -+ "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; - static const char *const mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; - static const char *const mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; - static const char *const mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", -@@ -986,7 +1024,8 @@ static const char *const mt7981_i2c_grou - static const char *const mt7981_pcm_groups[] = { "pcm", }; - static const char *const mt7981_udi_groups[] = { "udi", }; - static const char *const mt7981_usb_groups[] = { "drv_vbus", }; --static const char *const mt7981_flash_groups[] = { "emmc_45", "snfi", }; -+static const char *const mt7981_flash_groups[] = { "emmc_reset", "emmc_4", -+ "emmc_8", "emmc_45", "snfi", }; - static const char *const mt7981_ethernet_groups[] = { "smi_mdc_mdio", - "gbe_ext_mdc_mdio", "wf0_mode1", "wf0_mode3", "mt7531_int", }; - static const char *const mt7981_ant_groups[] = { "ant_sel", }; diff --git a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch index 946248bbb4..e0edda8d70 100644 --- a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch +++ b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch @@ -19,7 +19,7 @@ Signed-off-by: Weijie Gao --- a/env/Kconfig +++ b/env/Kconfig -@@ -61,7 +61,7 @@ config ENV_IS_DEFAULT +@@ -74,7 +74,7 @@ config ENV_IS_DEFAULT !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \ !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \ !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \ @@ -28,7 +28,7 @@ Signed-off-by: Weijie Gao select ENV_IS_NOWHERE config ENV_IS_NOWHERE -@@ -254,6 +254,27 @@ config ENV_IS_IN_MMC +@@ -267,6 +267,27 @@ config ENV_IS_IN_MMC offset: "u-boot,mmc-env-offset", "u-boot,mmc-env-offset-redundant". CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND are not used. @@ -56,7 +56,7 @@ Signed-off-by: Weijie Gao config ENV_IS_IN_NAND bool "Environment in a NAND device" depends on !CHAIN_OF_TRUST -@@ -561,10 +582,16 @@ config ENV_ADDR_REDUND +@@ -574,10 +595,16 @@ config ENV_ADDR_REDUND Offset from the start of the device (or partition) of the redundant environment location. @@ -74,7 +74,7 @@ Signed-off-by: Weijie Gao default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH default 0xF0000 if ARCH_SUNXI -@@ -622,6 +649,12 @@ config ENV_SECT_SIZE +@@ -635,6 +662,12 @@ config ENV_SECT_SIZE help Size of the sector containing the environment. diff --git a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch index 3792fae430..381ceb29de 100644 --- a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch +++ b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch @@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao --- a/common/board_r.c +++ b/common/board_r.c -@@ -381,6 +381,20 @@ static int initr_nand(void) +@@ -378,6 +378,20 @@ static int initr_nand(void) } #endif @@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao #if defined(CONFIG_CMD_ONENAND) /* go init the NAND */ static int initr_onenand(void) -@@ -694,6 +708,9 @@ static init_fnc_t init_sequence_r[] = { +@@ -693,6 +707,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_CMD_ONENAND initr_onenand, #endif diff --git a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch index ab5df08c5c..6d89c7480e 100644 --- a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch +++ b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -1492,6 +1492,12 @@ config CMD_NAND_TORTURE +@@ -1525,6 +1525,12 @@ config CMD_NAND_WATCH endif # CMD_NAND @@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao depends on NVME --- a/cmd/Makefile +++ b/cmd/Makefile -@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o +@@ -130,6 +130,7 @@ obj-y += legacy-mtd-utils.o endif obj-$(CONFIG_CMD_MUX) += mux.o obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch index 0943a63217..a772b485f4 100644 --- a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch +++ b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch @@ -20,7 +20,7 @@ Signed-off-by: SkyLake.Huang --- a/cmd/mtd.c +++ b/cmd/mtd.c -@@ -730,6 +730,42 @@ out_put_mtd: +@@ -728,6 +728,42 @@ out_put_mtd: return CMD_RET_SUCCESS; } @@ -63,7 +63,7 @@ Signed-off-by: SkyLake.Huang #ifdef CONFIG_AUTO_COMPLETE static int mtd_name_complete(int argc, char *const argv[], char last_char, int maxv, char *cmdv[]) -@@ -777,6 +813,7 @@ U_BOOT_LONGHELP(mtd, +@@ -775,6 +811,7 @@ U_BOOT_LONGHELP(mtd, "\n" "Specific functions:\n" "mtd bad \n" @@ -71,7 +71,7 @@ Signed-off-by: SkyLake.Huang #if CONFIG_IS_ENABLED(CMD_MTD_OTP) "mtd otpread [u|f] \n" "mtd otpwrite \n" -@@ -817,4 +854,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils" +@@ -815,4 +852,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils" U_BOOT_SUBCMD_MKENT_COMPLETE(erase, 4, 0, do_mtd_erase, mtd_name_complete), U_BOOT_SUBCMD_MKENT_COMPLETE(bad, 2, 1, do_mtd_bad, diff --git a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch index fd95cc2a8b..a02a59a057 100644 --- a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch +++ b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch @@ -18,7 +18,7 @@ Signed-off-by: Weijie Gao --- a/env/Kconfig +++ b/env/Kconfig -@@ -61,7 +61,7 @@ config ENV_IS_DEFAULT +@@ -74,7 +74,7 @@ config ENV_IS_DEFAULT !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \ !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \ !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \ @@ -27,7 +27,7 @@ Signed-off-by: Weijie Gao select ENV_IS_NOWHERE config ENV_IS_NOWHERE -@@ -305,6 +305,21 @@ config ENV_IS_IN_NAND +@@ -318,6 +318,21 @@ config ENV_IS_IN_NAND Currently, CONFIG_ENV_OFFSET_REDUND is not supported when using CONFIG_ENV_OFFSET_OOB. @@ -49,7 +49,7 @@ Signed-off-by: Weijie Gao config ENV_RANGE hex "Length of the region in which the environment can be written" depends on ENV_IS_IN_NAND -@@ -591,7 +606,7 @@ config ENV_MTD_NAME +@@ -604,7 +619,7 @@ config ENV_MTD_NAME config ENV_OFFSET hex "Environment offset" depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \ diff --git a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch index 419673f7e2..83a5a3f234 100644 --- a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch +++ b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch @@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -1492,6 +1492,14 @@ config CMD_NAND_TORTURE +@@ -1525,6 +1525,14 @@ config CMD_NAND_WATCH endif # CMD_NAND @@ -43,7 +43,7 @@ Signed-off-by: Weijie Gao bool "nmbm" --- a/cmd/Makefile +++ b/cmd/Makefile -@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o +@@ -130,6 +130,7 @@ obj-y += legacy-mtd-utils.o endif obj-$(CONFIG_CMD_MUX) += mux.o obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch deleted file mode 100644 index 7daae5c484..0000000000 --- a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch +++ /dev/null @@ -1,206 +0,0 @@ -From 5a15437610e8e8c68dc347845a83d0cbad80ca08 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 19 Jan 2021 10:58:48 +0800 -Subject: [PATCH 51/71] cmd: bootmenu: add ability to select item by shortkey - -Add ability to use shortkey to select item for bootmenu command - -Signed-off-by: Weijie Gao ---- - cmd/bootmenu.c | 28 +++++++++++++++++++++++--- - common/menu.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++ - include/cli.h | 2 ++ - include/menu.h | 3 +++ - 4 files changed, 84 insertions(+), 3 deletions(-) - ---- a/cmd/bootmenu.c -+++ b/cmd/bootmenu.c -@@ -114,6 +114,8 @@ static char *bootmenu_choice_entry(void - ++menu->active; - /* no menu key selected, regenerate menu */ - return NULL; -+ case BKEY_CHOICE: -+ menu->active = cch->choice; - case BKEY_SELECT: - iter = menu->first; - for (i = 0; i < menu->active; ++i) -@@ -182,6 +184,9 @@ static int prepare_bootmenu_entry(struct - unsigned short int i = *index; - struct bootmenu_entry *entry = NULL; - struct bootmenu_entry *iter = *current; -+ char *choice_option; -+ char choice_char; -+ int len; - - while ((option = bootmenu_getoption(i))) { - -@@ -196,11 +201,28 @@ static int prepare_bootmenu_entry(struct - if (!entry) - return -ENOMEM; - -- entry->title = strndup(option, sep - option); -+ /* Add BKEY_CHOICE support: '%c. %s\0' : len --> len + 4 */ -+ len = sep - option + 4; -+ -+ choice_option = malloc(len); -+ if (!choice_option) { -+ free(entry->title); -+ free(entry); -+ return -ENOMEM; -+ } -+ -+ if (!get_choice_char(i, &choice_char)) -+ len = snprintf(choice_option, len, "%c. %s", choice_char, option); -+ else -+ len = snprintf(choice_option, len, " %s", option); -+ -+ entry->title = strndup(choice_option, len); -+ - if (!entry->title) { - free(entry); - return -ENOMEM; - } -+ free(choice_option); - - entry->command = strdup(sep + 1); - if (!entry->command) { -@@ -382,9 +404,9 @@ static struct bootmenu_data *bootmenu_cr - - /* Add Quit entry if exiting bootmenu is disabled */ - if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE)) -- entry->title = strdup("Exit"); -+ entry->title = strdup("0. Exit"); - else -- entry->title = strdup("Quit"); -+ entry->title = strdup("0. Quit"); - - if (!entry->title) { - free(entry); ---- a/common/menu.c -+++ b/common/menu.c -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -49,6 +50,33 @@ struct menu { - int item_cnt; - }; - -+const char choice_chars[] = { -+ '1', '2', '3', '4', '5', '6', '7', '8', '9', -+ 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', -+ 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', -+ 'u', 'v', 'w', 'x', 'y', 'z' -+}; -+ -+static int find_choice(char choice) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(choice_chars); i++) -+ if (tolower(choice) == choice_chars[i]) -+ return i; -+ -+ return -1; -+} -+ -+int get_choice_char(int index, char *result) -+{ -+ if (index < ARRAY_SIZE(choice_chars)) -+ *result = choice_chars[index]; -+ else -+ return -1; -+ return 0; -+} -+ - /* - * An iterator function for menu items. callback will be called for each item - * in m, with m, a pointer to the item, and extra being passed to callback. If -@@ -441,6 +469,7 @@ enum bootmenu_key bootmenu_autoboot_loop - { - enum bootmenu_key key = BKEY_NONE; - int i, c; -+ int choice; - - while (menu->delay > 0) { - if (ansi) -@@ -458,6 +487,18 @@ enum bootmenu_key bootmenu_autoboot_loop - menu->delay = -1; - c = getchar(); - -+ choice = find_choice(c); -+ if ((choice >= 0 && -+ choice < menu->count - 1)) { -+ cch->choice = choice; -+ key = BKEY_CHOICE; -+ break; -+ } else if (c == '0') { -+ cch->choice = menu->count - 1; -+ key = BKEY_CHOICE; -+ break; -+ } -+ - ichar = cli_ch_process(cch, c); - - switch (ichar) { -@@ -537,6 +578,7 @@ enum bootmenu_key bootmenu_loop(struct b - { - enum bootmenu_key key; - int c, errchar = 0; -+ int choice; - - c = cli_ch_process(cch, 0); - if (!c) { -@@ -548,6 +590,18 @@ enum bootmenu_key bootmenu_loop(struct b - } - if (!c) { - c = getchar(); -+ -+ choice = find_choice(c); -+ if ((choice >= 0 && -+ choice < menu->count - 1)) { -+ cch->choice = choice; -+ return BKEY_CHOICE; -+ -+ } else if (c == '0') { -+ cch->choice = menu->count - 1; -+ return BKEY_CHOICE; -+ } -+ - c = cli_ch_process(cch, c); - } - } ---- a/include/cli.h -+++ b/include/cli.h -@@ -23,6 +23,8 @@ struct cli_ch_state { - char esc_save[8]; - int emit_upto; - bool emitting; -+ /* mediatek bootmenu choice feature */ -+ char choice; - }; - - /** ---- a/include/menu.h -+++ b/include/menu.h -@@ -37,6 +37,8 @@ int menu_default_choice(struct menu *m, - */ - int menu_show(int bootdelay); - -+int get_choice_char(int index, char *result); -+ - struct bootmenu_data { - int delay; /* delay for autoboot */ - int active; /* active menu entry */ -@@ -51,6 +53,7 @@ enum bootmenu_key { - BKEY_UP, - BKEY_DOWN, - BKEY_SELECT, -+ BKEY_CHOICE, - BKEY_QUIT, - BKEY_SAVE, - diff --git a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch deleted file mode 100644 index 8c2bcd5437..0000000000 --- a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch +++ /dev/null @@ -1,274 +0,0 @@ -From 452dc98572f8353f77551bcce5a2ca8cd050f498 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 3 Mar 2021 10:48:53 +0800 -Subject: [PATCH 53/71] board: mt7629: add support for booting from SPI-NAND - -Add support for mt7629 to boot from SPI-NAND. -Add a new defconfig for mt7629+spi-nand configuration. - -Signed-off-by: Weijie Gao ---- - arch/arm/dts/mt7629-rfb-u-boot.dtsi | 8 ++ - arch/arm/dts/mt7629-rfb.dts | 10 +++ - arch/arm/dts/mt7629.dtsi | 16 ++++ - arch/arm/mach-mediatek/Kconfig | 4 +- - board/mediatek/mt7629/Kconfig | 40 ++++++++++ - board/mediatek/mt7629/mt7629_rfb.c | 5 ++ - configs/mt7629_nand_rfb_defconfig | 113 ++++++++++++++++++++++++++++ - 7 files changed, 195 insertions(+), 1 deletion(-) - create mode 100644 board/mediatek/mt7629/Kconfig - create mode 100644 configs/mt7629_nand_rfb_defconfig - ---- a/arch/arm/dts/mt7629-rfb-u-boot.dtsi -+++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi -@@ -40,3 +40,11 @@ - &snfi { - bootph-all; - }; -+ -+&pinctrl { -+ u-boot,dm-pre-reloc; -+}; -+ -+&snand { -+ u-boot,dm-pre-reloc; -+}; ---- a/arch/arm/dts/mt7629-rfb.dts -+++ b/arch/arm/dts/mt7629-rfb.dts -@@ -47,9 +47,12 @@ - }; - - snfi_pins: snfi-pins { -+ u-boot,dm-pre-reloc; -+ - mux { - function = "flash"; - groups = "snfi"; -+ u-boot,dm-pre-reloc; - }; - }; - -@@ -102,6 +105,13 @@ - }; - }; - -+&snand { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&snfi_pins>; -+ status = "okay"; -+ quad-spi; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; ---- a/arch/arm/dts/mt7629.dtsi -+++ b/arch/arm/dts/mt7629.dtsi -@@ -229,6 +229,22 @@ - #size-cells = <0>; - }; - -+ snand: snand@1100d000 { -+ compatible = "mediatek,mt7629-snand"; -+ reg = <0x1100d000 0x1000>, -+ <0x1100e000 0x1000>; -+ reg-names = "nfi", "ecc"; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, -+ <&pericfg CLK_PERI_SNFI_PD>, -+ <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfi_clk", "pad_clk", "ecc_clk"; -+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>, -+ <&topckgen CLK_TOP_NFI_INFRA_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>, -+ <&topckgen CLK_TOP_UNIVPLL2_D8>; -+ status = "disabled"; -+ }; -+ - snor: snor@11014000 { - compatible = "mediatek,mtk-snor"; - reg = <0x11014000 0x1000>; ---- a/arch/arm/mach-mediatek/Kconfig -+++ b/arch/arm/mach-mediatek/Kconfig -@@ -148,9 +148,11 @@ config SYS_CONFIG_NAME - - config MTK_BROM_HEADER_INFO - string -- default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 -+ default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622 - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 - default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988 - default "lk=1" if TARGET_MT7623 - -+source "board/mediatek/mt7629/Kconfig" -+ - endif ---- /dev/null -+++ b/board/mediatek/mt7629/Kconfig -@@ -0,0 +1,40 @@ -+if TARGET_MT7629 -+ -+config MTK_BROM_HEADER_INFO -+ string -+ default "media=nor" if BOOT_FROM_SNOR -+ default "media=snand;nandinfo=2k+64" if BOOT_FROM_SNAND_2K_64 -+ default "media=snand;nandinfo=2k+128" if BOOT_FROM_SNAND_2K_128 -+ default "media=snand;nandinfo=4k+128" if BOOT_FROM_SNAND_4K_128 -+ default "media=snand;nandinfo=4k+256" if BOOT_FROM_SNAND_4K_256 -+ -+choice -+ prompt "Boot device" -+ default BOOT_FROM_SNOR -+ -+config BOOT_FROM_SNOR -+ bool "SPI-NOR" -+ -+config BOOT_FROM_SNAND_2K_64 -+ bool "SPI-NAND (2K+64)" -+ select MT7629_BOOT_FROM_SNAND -+ -+config BOOT_FROM_SNAND_2K_128 -+ bool "SPI-NAND (2K+128)" -+ select MT7629_BOOT_FROM_SNAND -+ -+config BOOT_FROM_SNAND_4K_128 -+ bool "SPI-NAND (4K+128)" -+ select MT7629_BOOT_FROM_SNAND -+ -+config BOOT_FROM_SNAND_4K_256 -+ bool "SPI-NAND (4K+256)" -+ select MT7629_BOOT_FROM_SNAND -+ -+endchoice -+ -+config MT7629_BOOT_FROM_SNAND -+ bool -+ default n -+ -+endif ---- a/board/mediatek/mt7629/mt7629_rfb.c -+++ b/board/mediatek/mt7629/mt7629_rfb.c -@@ -15,3 +15,8 @@ int board_init(void) - - return 0; - } -+ -+uint32_t spl_nand_get_uboot_raw_page(void) -+{ -+ return CONFIG_SPL_PAD_TO; -+} ---- /dev/null -+++ b/configs/mt7629_nand_rfb_defconfig -@@ -0,0 +1,113 @@ -+CONFIG_ARM=y -+CONFIG_SYS_ARCH_TIMER=y -+CONFIG_SYS_THUMB_BUILD=y -+CONFIG_ARCH_MEDIATEK=y -+CONFIG_TEXT_BASE=0x41e00000 -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_SIZE=0x20000 -+CONFIG_ENV_OFFSET=0x0 -+CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb" -+CONFIG_SPL_TEXT_BASE=0x201000 -+CONFIG_TARGET_MT7629=y -+CONFIG_BOOT_FROM_SNAND_2K_64=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x40800000 -+CONFIG_SYS_LOAD_ADDR=0x42007f1c -+CONFIG_SPL_PAYLOAD="u-boot.img" -+CONFIG_BUILD_TARGET="u-boot-mtk.bin" -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41fffef0 -+CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin" -+CONFIG_FIT=y -+# CONFIG_AUTOBOOT is not set -+CONFIG_DEFAULT_FDT_FILE="mt7629-rfb" -+CONFIG_SYS_CONSOLE_IS_IN_ENV=y -+# CONFIG_DISPLAY_BOARDINFO is not set -+CONFIG_SPL_MAX_SIZE=0x20000 -+CONFIG_SPL_FOOTPRINT_LIMIT=y -+CONFIG_SPL_MAX_FOOTPRINT=0x20000 -+CONFIG_SPL_SYS_MALLOC_SIMPLE=y -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK=0x106000 -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_MTD_SUPPORT=y -+CONFIG_SPL_NAND_SUPPORT=y -+CONFIG_SPL_WATCHDOG=y -+CONFIG_HUSH_PARSER=y -+CONFIG_SYS_PROMPT="U-Boot> " -+# CONFIG_BOOTM_NETBSD is not set -+# CONFIG_BOOTM_PLAN9 is not set -+# CONFIG_BOOTM_RTEMS is not set -+# CONFIG_BOOTM_VXWORKS is not set -+CONFIG_SYS_BOOTM_LEN=0x4000000 -+CONFIG_CMD_BOOTMENU=y -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_XIMG is not set -+CONFIG_CMD_BIND=y -+CONFIG_CMD_DM=y -+# CONFIG_CMD_FLASH is not set -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+# CONFIG_CMD_NFS is not set -+CONFIG_CMD_PING=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_LOG=y -+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-parents" -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MTD=y -+CONFIG_ENV_MTD_NAME="u-boot-env" -+CONFIG_ENV_SIZE_REDUND=0x40000 -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_DM_SEQ_ALIAS=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+# CONFIG_MMC is not set -+CONFIG_MTD=y -+CONFIG_DM_MTD=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SPL_MTK_SPI_NAND=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_SPL_PINCONF=y -+CONFIG_PINCTRL_MT7629=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_SPI_MEM=y -+CONFIG_MTK_SNFI_SPI=y -+CONFIG_SYSRESET=y -+CONFIG_SPL_SYSRESET=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_USB=y -+# CONFIG_SPL_DM_USB is not set -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_MTK=y -+CONFIG_USB_STORAGE=y -+CONFIG_WDT_MTK=y -+# CONFIG_SHA256 is not set -+# CONFIG_SPL_SHA1 is not set -+CONFIG_LZMA=y -+CONFIG_SPL_LZMA=y -+# CONFIG_EFI_LOADER is not set diff --git a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch index a2c36d8e6b..63083555bf 100644 --- a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch +++ b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch @@ -18,9 +18,9 @@ Signed-off-by: Weijie Gao --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1195,6 +1195,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1136,6 +1136,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt7622-bananapi-bpi-r64.dtb \ mt7623n-bananapi-bpi-r2.dtb \ - mt7629-rfb.dtb \ mt7981-rfb.dtb \ + mt7981-snfi-nand-rfb.dtb \ mt7981-emmc-rfb.dtb \ @@ -65,7 +65,7 @@ Signed-off-by: Weijie Gao + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; @@ -73,7 +73,7 @@ Signed-off-by: Weijie Gao + }; +}; + -+&pinctrl { ++&pio { + snfi_pins: snfi-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch index ae69334be6..b740bb7abd 100644 --- a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch +++ b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig -@@ -876,6 +876,14 @@ config MMC_MTK +@@ -868,6 +868,14 @@ config MMC_MTK This is needed if support for any SD/SDIO/MMC devices is required. If unsure, say N. @@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao config FSL_SDHC_V2_3 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile -@@ -84,3 +84,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm +@@ -85,3 +85,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o obj-$(CONFIG_MMC_MTK) += mtk-sd.o obj-$(CONFIG_MMC_SDHCI_F_SDH30) += f_sdh30.o @@ -42,7 +42,7 @@ Signed-off-by: Weijie Gao +endif --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c -@@ -783,18 +783,24 @@ static int msdc_ops_send_cmd(struct udev +@@ -784,18 +784,24 @@ static int msdc_ops_send_cmd(struct udev if (cmd_ret && !(cmd_ret == -EIO && (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || diff --git a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch index 6eac7e11ad..0133e09e95 100644 --- a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch +++ b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch @@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao --- a/env/Kconfig +++ b/env/Kconfig -@@ -688,6 +688,12 @@ config ENV_UBI_VOLUME_REDUND +@@ -701,6 +701,12 @@ config ENV_UBI_VOLUME_REDUND help Name of the redundant volume that you want to store the environment in. diff --git a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch index cdb83005d9..fc3d6b0b91 100644 --- a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch +++ b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch @@ -74,9 +74,9 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support DECLARE_GLOBAL_DATA_PTR; int board_init(void) -@@ -20,3 +25,36 @@ uint32_t spl_nand_get_uboot_raw_page(voi - { - return CONFIG_SPL_PAD_TO; +@@ -15,3 +20,36 @@ int board_init(void) + + return 0; } + +int board_nmbm_init(void) diff --git a/package/boot/uboot-mediatek/patches/103-02-mt7981-enable-pstore.patch b/package/boot/uboot-mediatek/patches/103-02-mt7981-enable-pstore.patch index 81bf3d4eed..8eaa91f53f 100644 --- a/package/boot/uboot-mediatek/patches/103-02-mt7981-enable-pstore.patch +++ b/package/boot/uboot-mediatek/patches/103-02-mt7981-enable-pstore.patch @@ -1,6 +1,6 @@ --- a/arch/arm/dts/mt7981.dtsi +++ b/arch/arm/dts/mt7981.dtsi -@@ -32,6 +32,35 @@ +@@ -33,6 +33,35 @@ }; }; diff --git a/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch b/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch index 67bf1955c2..3a3f8d0e1e 100644 --- a/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch +++ b/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch @@ -1,6 +1,6 @@ --- a/configs/mt7981_rfb_defconfig +++ b/configs/mt7981_rfb_defconfig -@@ -31,6 +31,9 @@ CONFIG_CMD_MTD=y +@@ -30,6 +30,9 @@ CONFIG_CMD_MTD=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_PING=y CONFIG_CMD_SMC=y diff --git a/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch index 608eff64d6..5979abbf39 100644 --- a/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch +++ b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch @@ -87,7 +87,7 @@ CONFIG_HEXDUMP=y --- a/configs/mt7981_rfb_defconfig +++ b/configs/mt7981_rfb_defconfig -@@ -6,39 +6,79 @@ CONFIG_TEXT_BASE=0x41e00000 +@@ -6,38 +6,78 @@ CONFIG_TEXT_BASE=0x41e00000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_DEVICE_TREE="mt7981-rfb" @@ -97,7 +97,6 @@ CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_DEBUG_UART=y - # CONFIG_EFI_LOADER is not set -# CONFIG_AUTOBOOT is not set +CONFIG_FIT=y +CONFIG_SPI_BOOT=y @@ -169,7 +168,7 @@ # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_DM_MTD=y -@@ -63,6 +103,7 @@ CONFIG_PINCTRL_MT7981=y +@@ -62,6 +102,7 @@ CONFIG_PINCTRL_MT7981=y CONFIG_POWER_DOMAIN=y CONFIG_MTK_POWER_DOMAIN=y CONFIG_DM_SERIAL=y diff --git a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch index d04a61432e..a06935f53e 100644 --- a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch +++ b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch @@ -1,6 +1,6 @@ --- a/tools/image-host.c +++ b/tools/image-host.c -@@ -1162,6 +1162,7 @@ static int fit_config_add_verification_d +@@ -1175,6 +1175,7 @@ static int fit_config_add_verification_d * 2) get public key (X509_get_pubkey) * 3) provide der format (d2i_RSAPublicKey) */ @@ -8,7 +8,7 @@ static int read_pub_key(const char *keydir, const void *name, unsigned char **pubkey, int *pubkey_len) { -@@ -1215,6 +1216,13 @@ err_cert: +@@ -1228,6 +1229,13 @@ err_cert: fclose(f); return ret; } diff --git a/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch b/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch index 2a71a4eb92..b7fc8f45a5 100644 --- a/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch +++ b/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch @@ -58,7 +58,7 @@ Signed-off-by: Weijie Gao --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -83,6 +83,37 @@ config PHY_ADIN +@@ -79,6 +79,37 @@ config PHY_ADIN help Add support for configuring RGMII on Analog Devices ADIN PHYs. diff --git a/package/boot/uboot-mediatek/patches/170-cmd-bootmenu-permit-to-select-bootmenu-entry-with.patch b/package/boot/uboot-mediatek/patches/170-cmd-bootmenu-permit-to-select-bootmenu-entry-with.patch new file mode 100644 index 0000000000..a06682a0b8 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/170-cmd-bootmenu-permit-to-select-bootmenu-entry-with.patch @@ -0,0 +1,261 @@ +From 16fd9af92b7ed93ece62fa8d1bef341455d773cf Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Sat, 24 May 2025 23:23:53 +0200 +Subject: [PATCH v2] cmd: bootmenu: permit to select bootmenu entry with a + shortcut + +Permit to select a bootmenu entry with a key shortcut. This is +especially useful in production or testing scenario to automate flashing +procedure or testing procedure. + +The boot entry are changed to append the shortcut key to it. + +Example: + 1. Run default boot command. + 2. Boot system via TFTP. + 3. Boot production system from NAND. + 4. Boot recovery system from NAND. + 5. Load production system via TFTP then write to NAND. + 6. Load recovery system via TFTP then write to NAND. + 7. Load BL31+U-Boot FIP via TFTP then write to NAND. + 8. Load BL2 preloader via TFTP then write to NAND. + 9. Reboot. + a. Reset all settings to factory defaults. + 0. Exit + +0 is always reserved for Exit to console. +On pressing the keyboard key 2, the bootmenu entry 2 is selected and +executed. + +Up to 34 key shortcut (0 excluded as reserved) are supported from 1-9 +and a-z. +If a shortcut key not present in the bootmenu list is pressed, it is +simply ignored and eventually the autoboot is interrupted. + +Capital A-Z are converted to lower a-z and the related option is +selected. + +Suggested-by: Weijie Gao +Signed-off-by: Christian Marangi +--- +Changes v2: +- Fix spelling mistake +- Fix case with '0' + + cmd/bootmenu.c | 41 ++++++++++++++++++++++++++++++++++++++--- + common/menu.c | 44 ++++++++++++++++++++++++++++++++++++++++++-- + include/cli.h | 2 ++ + include/menu.h | 3 +++ + 4 files changed, 85 insertions(+), 5 deletions(-) + +--- a/cmd/bootmenu.c ++++ b/cmd/bootmenu.c +@@ -114,6 +114,14 @@ static char *bootmenu_choice_entry(void + ++menu->active; + /* no menu key selected, regenerate menu */ + return NULL; ++ case BKEY_SHORTCUT: ++ /* invalid shortcut, regenerate menu */ ++ if (cch->shortcut_key >= menu->count - 1) ++ return NULL; ++ /* shortcut_key value for Exit is is -1 */ ++ menu->active = cch->shortcut_key < 0 ? menu->count - 1 : ++ cch->shortcut_key; ++ fallthrough; + case BKEY_SELECT: + iter = menu->first; + for (i = 0; i < menu->active; ++i) +@@ -161,6 +169,21 @@ static void bootmenu_destroy(struct boot + free(menu); + } + ++static char bootmenu_entry_shortcut_key(int index) ++{ ++ switch (index) { ++ /* 1-9 shortcut key (0 reserved) */ ++ case 0 ... 8: ++ return '1' + index; ++ /* a-z shortcut key */ ++ case 9 ... 34: ++ return 'a' + index - 9; ++ /* We support shortcut for up to 34 options (0 reserved) */ ++ default: ++ return -ENOENT; ++ } ++} ++ + /** + * prepare_bootmenu_entry() - generate the bootmenu_xx entries + * +@@ -184,6 +207,8 @@ static int prepare_bootmenu_entry(struct + struct bootmenu_entry *iter = *current; + + while ((option = bootmenu_getoption(i))) { ++ char shortcut_key; ++ int len; + + /* bootmenu_[num] format is "[title]=[commands]" */ + sep = strchr(option, '='); +@@ -196,12 +221,22 @@ static int prepare_bootmenu_entry(struct + if (!entry) + return -ENOMEM; + +- entry->title = strndup(option, sep - option); ++ /* Add shotcut key option: %c. %s\0 */ ++ len = sep - option + 4; ++ ++ entry->title = malloc(len); + if (!entry->title) { + free(entry); + return -ENOMEM; + } + ++ shortcut_key = bootmenu_entry_shortcut_key(i); ++ /* Use emtpy space if entry doesn't support shortcut key */ ++ snprintf(entry->title, len, "%c%c %s", ++ shortcut_key > 0 ? shortcut_key : ' ', ++ shortcut_key > 0 ? '.' : ' ', ++ option); ++ + entry->command = strdup(sep + 1); + if (!entry->command) { + free(entry->title); +@@ -388,9 +423,9 @@ static struct bootmenu_data *bootmenu_cr + + /* Add Quit entry if exiting bootmenu is disabled */ + if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE)) +- entry->title = strdup("Exit"); ++ entry->title = strdup("0. Exit"); + else +- entry->title = strdup("Quit"); ++ entry->title = strdup("0. Quit"); + + if (!entry->title) { + free(entry); +--- a/common/menu.c ++++ b/common/menu.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -436,6 +437,29 @@ int menu_destroy(struct menu *m) + return 1; + } + ++static int bootmenu_conv_shortcut_key(struct bootmenu_data *menu, int ichar) ++{ ++ int shortcut_key; ++ ++ ichar = tolower(ichar); ++ switch (ichar) { ++ /* a-z for bootmenu entry > 9 */ ++ case 'a' ... 'z': ++ shortcut_key = ichar - 'a' + 9; ++ break; ++ /* 1-9 for bootmenu entry <= 9 */ ++ case '1' ... '9': ++ shortcut_key = ichar - '1'; ++ break; ++ /* Reserve 0 for last option (aka Exit) */ ++ case '0': ++ default: ++ return -1; ++ } ++ ++ return shortcut_key; ++} ++ + enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, + struct cli_ch_state *cch) + { +@@ -443,12 +467,12 @@ enum bootmenu_key bootmenu_autoboot_loop + int i, c; + + while (menu->delay > 0) { ++ int ichar; ++ + if (ansi) + printf(ANSI_CURSOR_POSITION, menu->count + 5, 3); + printf("Hit any key to stop autoboot: %d ", menu->delay); + for (i = 0; i < 100; ++i) { +- int ichar; +- + if (!tstc()) { + schedule(); + mdelay(10); +@@ -470,6 +494,11 @@ enum bootmenu_key bootmenu_autoboot_loop + case 0x3: /* ^C */ + key = BKEY_QUIT; + break; ++ case 'A' ... 'Z': ++ case 'a' ... 'z': ++ case '0' ... '9': ++ key = BKEY_SHORTCUT; ++ break; + default: + key = BKEY_NONE; + break; +@@ -477,6 +506,9 @@ enum bootmenu_key bootmenu_autoboot_loop + break; + } + ++ if (key == BKEY_SHORTCUT) ++ cch->shortcut_key = bootmenu_conv_shortcut_key(menu, ichar); ++ + if (menu->delay < 0) + break; + +@@ -524,6 +556,11 @@ enum bootmenu_key bootmenu_conv_key(int + case ' ': + key = BKEY_SPACE; + break; ++ case 'A' ... 'Z': ++ case 'a' ... 'z': ++ case '0' ... '9': ++ key = BKEY_SHORTCUT; ++ break; + default: + key = BKEY_NONE; + break; +@@ -554,5 +591,8 @@ enum bootmenu_key bootmenu_loop(struct b + + key = bootmenu_conv_key(c); + ++ if (key == BKEY_SHORTCUT) ++ cch->shortcut_key = bootmenu_conv_shortcut_key(menu, c); ++ + return key; + } +--- a/include/cli.h ++++ b/include/cli.h +@@ -17,12 +17,14 @@ + * @esc_save: Escape characters collected so far + * @emit_upto: Next index to emit from esc_save + * @emitting: true if emitting from esc_save ++ * @shortcut_key: Selected shortcut option index + */ + struct cli_ch_state { + int esc_len; + char esc_save[8]; + int emit_upto; + bool emitting; ++ int shortcut_key; + }; + + /** +--- a/include/menu.h ++++ b/include/menu.h +@@ -54,6 +54,9 @@ enum bootmenu_key { + BKEY_QUIT, + BKEY_SAVE, + ++ /* shortcut key to select menu option directly */ ++ BKEY_SHORTCUT, ++ + /* 'extra' keys, which are used by menus but not cedit */ + BKEY_PLUS, + BKEY_MINUS, diff --git a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch index 082f99b767..27cea2fa4e 100644 --- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch +++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch @@ -70,7 +70,7 @@ { --- a/boot/image-fit.c +++ b/boot/image-fit.c -@@ -2047,6 +2047,47 @@ static const char *fit_get_image_type_pr +@@ -2054,6 +2054,47 @@ static const char *fit_get_image_type_pr return "unknown"; } @@ -101,7 +101,7 @@ + (noffset >= 0) && (ndepth > 0); + noffset = fdt_next_node(fit, noffset, &ndepth)) { + if (ndepth == 1) { -+ ret = fit_image_get_data_and_size(fit, noffset, &data, &data_size); ++ ret = fit_image_get_data(fit, noffset, &data, &data_size); + if (ret) + goto out; + @@ -120,7 +120,7 @@ int arch, int ph_type, int bootstage_id, --- a/include/image.h +++ b/include/image.h -@@ -1112,6 +1112,7 @@ int fit_parse_subimage(const char *spec, +@@ -1113,6 +1113,7 @@ int fit_parse_subimage(const char *spec, ulong *addr, const char **image_name); int fit_get_subimage_count(const void *fit, int images_noffset); diff --git a/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch b/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch index 1c1071bafc..3a66aa298a 100644 --- a/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch +++ b/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch @@ -1,6 +1,6 @@ --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c -@@ -463,7 +463,11 @@ static void menu_display_statusline(stru +@@ -482,7 +482,11 @@ static void menu_display_statusline(stru printf(ANSI_CURSOR_POSITION, 1, 1); puts(ANSI_CLEAR_LINE); printf(ANSI_CURSOR_POSITION, 2, 3); @@ -13,7 +13,7 @@ puts(ANSI_CLEAR_LINE_TO_END); printf(ANSI_CURSOR_POSITION, 3, 1); puts(ANSI_CLEAR_LINE); -@@ -548,6 +552,7 @@ static enum bootmenu_ret bootmenu_show(i +@@ -573,6 +577,7 @@ static enum bootmenu_ret bootmenu_show(i return BOOTMENU_RET_FAIL; } @@ -23,7 +23,7 @@ goto cleanup; --- a/include/menu.h +++ b/include/menu.h -@@ -45,6 +45,7 @@ struct bootmenu_data { +@@ -43,6 +43,7 @@ struct bootmenu_data { int last_active; /* last active menu entry */ int count; /* total count of menu entries */ struct bootmenu_entry *first; /* first menu entry */ diff --git a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch index 85d65ab48b..2b3a15fc59 100644 --- a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch +++ b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch @@ -1,6 +1,6 @@ --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -692,6 +692,12 @@ config CMD_ENV_EXISTS +@@ -707,6 +707,12 @@ config CMD_ENV_EXISTS Check if a variable is defined in the environment for use in shell scripting. @@ -76,7 +76,7 @@ #if defined(CONFIG_CMD_ENV_CALLBACK) static int print_static_binding(const char *var_name, const char *callback_name, void *priv) -@@ -1089,6 +1143,9 @@ static struct cmd_tbl cmd_env_sub[] = { +@@ -1092,6 +1146,9 @@ static struct cmd_tbl cmd_env_sub[] = { U_BOOT_CMD_MKENT(load, 1, 0, do_env_load, "", ""), #endif U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""), @@ -86,7 +86,7 @@ #if defined(CONFIG_CMD_RUN) U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""), #endif -@@ -1172,6 +1229,9 @@ U_BOOT_LONGHELP(env, +@@ -1176,6 +1233,9 @@ U_BOOT_LONGHELP(env, #if defined(CONFIG_CMD_NVEDIT_EFI) "env print -e [-guid guid] [-n] [name ...] - print UEFI environment\n" #endif @@ -96,7 +96,7 @@ #if defined(CONFIG_CMD_RUN) "env run var [...] - run commands in an environment variable\n" #endif -@@ -1280,6 +1340,17 @@ U_BOOT_CMD( +@@ -1284,6 +1344,17 @@ U_BOOT_CMD( ); #endif diff --git a/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch index c2ecbb2c33..3f180340fc 100644 --- a/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch +++ b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch @@ -16,7 +16,7 @@ Reviewed-by: Tom Rini --- a/boot/image-fdt.c +++ b/boot/image-fdt.c -@@ -612,6 +612,12 @@ int image_setup_libfdt(struct bootm_head +@@ -613,6 +613,12 @@ int image_setup_libfdt(struct bootm_head images->fit_uname_cfg, strlen(images->fit_uname_cfg) + 1, 1); diff --git a/package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch b/package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch deleted file mode 100644 index 6ed50907e3..0000000000 --- a/package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch +++ /dev/null @@ -1,71 +0,0 @@ -From cca5775031e4890f195246772e00f7f4ae7438f6 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 19 Feb 2024 05:52:24 +0100 -Subject: [PATCH 1/2] mt7981.dtsi: add USB nodes - -Signed-off-by: John Crispin ---- - arch/arm/dts/mt7981.dtsi | 47 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 47 insertions(+) - ---- a/arch/arm/dts/mt7981.dtsi -+++ b/arch/arm/dts/mt7981.dtsi -@@ -6,6 +6,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -346,4 +347,50 @@ - status = "disabled"; - }; - -+ xhci: xhci@11200000 { -+ compatible = "mediatek,mt7981-xhci", -+ "mediatek,mtk-xhci"; -+ reg = <0x11200000 0x2e00>, -+ <0x11203e00 0x0100>; -+ reg-names = "mac", "ippc"; -+ interrupts = ; -+ phys = <&u2port0 PHY_TYPE_USB2>, -+ <&u3port0 PHY_TYPE_USB3>; -+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, -+ <&infracfg CLK_INFRA_IUSB_CK>, -+ <&infracfg CLK_INFRA_IUSB_133_CK>, -+ <&infracfg CLK_INFRA_IUSB_66M_CK>, -+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>; -+ clock-names = "sys_ck", -+ "ref_ck", -+ "mcu_ck", -+ "dma_ck", -+ "xhci_ck"; -+ mediatek,u3p-dis-msk = <0x1>; -+ status = "okay"; -+ }; -+ -+ usbtphy: usb-phy@11e10000 { -+ compatible = "mediatek,mt7981", -+ "mediatek,generic-tphy-v2"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ status = "okay"; -+ -+ u2port0: usb-phy@11e10000 { -+ reg = <0x11e10000 0x700>; -+ clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ status = "okay"; -+ }; -+ -+ u3port0: usb-phy@11e10700 { -+ reg = <0x11e10700 0x900>; -+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ status = "okay"; -+ }; -+ }; - }; diff --git a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch index 66dd43da4b..2835e19b06 100644 --- a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch +++ b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch @@ -48,9 +48,9 @@ #ifdef CONFIG_ENABLE_NAND_NMBM --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -155,4 +155,11 @@ config MTK_BROM_HEADER_INFO - - source "board/mediatek/mt7629/Kconfig" +@@ -170,4 +170,11 @@ config MTK_TZ_MOVABLE + select OF_SYSTEM_SETUP + bool +config RESET_BUTTON_LABEL + string "Button to trigger factory reset" diff --git a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch index b3c2abf751..ff9aebdcaf 100644 --- a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch +++ b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch @@ -331,14 +331,14 @@ +}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1192,6 +1192,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1134,6 +1134,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ + mt7622-linksys-e8450-ubi.dtb \ mt7623n-bananapi-bpi-r2.dtb \ - mt7629-rfb.dtb \ mt7981-rfb.dtb \ + mt7981-snfi-nand-rfb.dtb \ --- /dev/null +++ b/defenvs/linksys_e8450_env @@ -0,0 +1,55 @@ diff --git a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch index fe31a8b015..44f8f6ee33 100644 --- a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch +++ b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch @@ -742,15 +742,15 @@ +}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1193,6 +1193,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1135,6 +1135,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ mt7622-linksys-e8450-ubi.dtb \ + mt7622-ubnt-unifi-6-lr.dtb \ + mt7622-ubnt-unifi-6-lr-v3.dtb \ mt7623n-bananapi-bpi-r2.dtb \ - mt7629-rfb.dtb \ mt7981-rfb.dtb \ + mt7981-snfi-nand-rfb.dtb \ --- /dev/null +++ b/defenvs/ubnt_unifi-6-lr_env @@ -0,0 +1,50 @@ @@ -920,7 +920,7 @@ DECLARE_GLOBAL_DATA_PTR; -@@ -405,6 +406,20 @@ static int initr_onenand(void) +@@ -402,6 +403,20 @@ static int initr_onenand(void) } #endif @@ -941,7 +941,7 @@ #ifdef CONFIG_MMC static int initr_mmc(void) { -@@ -711,6 +726,9 @@ static init_fnc_t init_sequence_r[] = { +@@ -710,6 +725,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_NMBM_MTD initr_nmbm, #endif diff --git a/package/boot/uboot-mediatek/patches/429-add-netcore-n60.patch b/package/boot/uboot-mediatek/patches/429-add-netcore-n60.patch index 52dc53045b..ca7ddd9ab2 100644 --- a/package/boot/uboot-mediatek/patches/429-add-netcore-n60.patch +++ b/package/boot/uboot-mediatek/patches/429-add-netcore-n60.patch @@ -165,13 +165,13 @@ + factory { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; + @@ -180,12 +180,12 @@ + + status_red { + label = "red:status"; -+ gpios = <&gpio 29 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 29 GPIO_ACTIVE_LOW>; + }; + + status_green { + label = "green:status"; -+ gpios = <&gpio 32 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 32 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -206,7 +206,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -214,7 +214,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch b/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch index e7ed1dc66a..5e5ec1f012 100644 --- a/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch +++ b/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch @@ -139,12 +139,12 @@ + compatible = "gpio-keys"; + factory { + label = "reset"; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + mesh { + label = "mesh"; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; @@ -166,7 +166,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -174,7 +174,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spic_pins: spi1-pins-func-1 { + mux { + function = "spi"; diff --git a/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch b/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch index 9c787a567d..2e6d843720 100644 --- a/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch +++ b/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch @@ -427,19 +427,19 @@ + factory { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + turbo { + label = "turbo"; + linux,code = ; -+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + }; + @@ -448,17 +448,17 @@ + + status_red { + label = "red:status"; -+ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; + + status_green { + label = "green:status"; -+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 8 GPIO_ACTIVE_HIGH>; + }; + + turbo { + label = "green:turbo"; -+ gpios = <&gpio 12 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 12 GPIO_ACTIVE_HIGH>; + }; + }; +}; @@ -479,7 +479,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -487,7 +487,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch b/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch index a7f56fe360..152c2f9c4b 100644 --- a/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch +++ b/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch @@ -160,13 +160,13 @@ + factory { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + @@ -175,12 +175,12 @@ + + status_red { + label = "red:status"; -+ gpios = <&gpio 3 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 3 GPIO_ACTIVE_LOW>; + }; + + status_green { + label = "green:status"; -+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -201,7 +201,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -209,7 +209,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch b/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch index 5011d67976..0011c4f6dc 100644 --- a/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch +++ b/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch @@ -164,13 +164,13 @@ + + reset { + label = "reset"; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + mesh { + label = "mesh"; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; @@ -181,22 +181,22 @@ + + led_system_blue { + label = "blue:system"; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led_system_yellow { + label = "yellow:system"; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + led_network_blue { + label = "blue:network"; -+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + led_network_yellow { + label = "yellow:network"; -+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -217,7 +217,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -225,7 +225,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch b/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch index 041ab1caa8..f87752189b 100644 --- a/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch +++ b/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch @@ -160,13 +160,13 @@ + factory { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + @@ -175,12 +175,12 @@ + + status_red { + label = "red:status"; -+ gpios = <&gpio 4 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 4 GPIO_ACTIVE_LOW>; + }; + + status_green { + label = "green:status"; -+ gpios = <&gpio 5 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -201,7 +201,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -209,7 +209,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch b/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch index 22e96bba97..975445aafe 100644 --- a/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch +++ b/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch @@ -46,7 +46,7 @@ + + wps { + label = "reset"; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; @@ -56,12 +56,12 @@ + + led_status_blue: green { + label = "blue:status"; -+ gpios = <&gpio 28 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 28 GPIO_ACTIVE_LOW>; + }; + + led_status_white: blue { + label = "white:status"; -+ gpios = <&gpio 27 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 27 GPIO_ACTIVE_LOW>; + }; + }; + @@ -77,7 +77,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 18 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -85,7 +85,7 @@ + }; +}; + -+&pinctrl { ++&pio { + mmc0_pins_default: mmc0default { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch b/package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch index 0b060c570c..d655ca4109 100644 --- a/package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch +++ b/package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch @@ -286,14 +286,14 @@ + button-reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-mesh { + label = "mesh"; + linux,code = ; + linux,input-type = ; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + @@ -302,17 +302,17 @@ + + led-0 { + label = "green:status"; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "blue:status"; -+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + + led-2 { + label = "red:status"; -+ gpios = <&gpio 35 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 35 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -322,7 +322,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -368,7 +368,7 @@ + status = "okay"; +}; + -+&pinctrl { ++&pio { + mmc0_pins_default: mmc0default { + mux { + function = "flash"; @@ -402,7 +402,7 @@ +/dts-v1/; +#include "mt7981-cmcc-rax3000m.dtsi" + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/438-add-jcg_q30-pro.patch b/package/boot/uboot-mediatek/patches/438-add-jcg_q30-pro.patch index 325a646aea..2d28b082a3 100644 --- a/package/boot/uboot-mediatek/patches/438-add-jcg_q30-pro.patch +++ b/package/boot/uboot-mediatek/patches/438-add-jcg_q30-pro.patch @@ -160,7 +160,7 @@ + factory { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + @@ -169,12 +169,12 @@ + + status_red { + label = "red:status"; -+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 8 GPIO_ACTIVE_HIGH>; + }; + + status_blue { + label = "blue:status"; -+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 13 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -195,7 +195,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -203,7 +203,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch b/package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch index 881a6b1962..520bac5899 100644 --- a/package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch +++ b/package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch @@ -163,13 +163,13 @@ + compatible = "gpio-keys"; + factory { + label = "reset"; -+ gpios = <&gpio 21 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 21 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; -+ gpios = <&gpio 56 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 56 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; @@ -179,13 +179,13 @@ + + led_status_green: pwr { + label = "green:status"; -+ gpios = <&gpio 13 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_sfp_green: sfp { + label = "green:sfp"; -+ gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; @@ -207,7 +207,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -215,7 +215,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spic_pins: spi1-pins-func-1 { + mux { + function = "spi"; diff --git a/package/boot/uboot-mediatek/patches/440-add-xiaomi_mi-router-ax3000t.patch b/package/boot/uboot-mediatek/patches/440-add-xiaomi_mi-router-ax3000t.patch index 5dfb2dd56b..61854c5e5d 100644 --- a/package/boot/uboot-mediatek/patches/440-add-xiaomi_mi-router-ax3000t.patch +++ b/package/boot/uboot-mediatek/patches/440-add-xiaomi_mi-router-ax3000t.patch @@ -143,13 +143,13 @@ + + reset { + label = "reset"; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + mesh { + label = "mesh"; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; @@ -160,12 +160,12 @@ + + led_status_blue { + label = "blue:status"; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led_status_yellow { + label = "yellow:status"; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -180,7 +180,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "auto"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -188,7 +188,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spic_pins: spi1-pins-func-1 { + mux { + function = "spi"; diff --git a/package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch b/package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch index 2a64762e5c..f3d1bae946 100644 --- a/package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch +++ b/package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch @@ -143,13 +143,13 @@ + button-joylink { + label = "joylink"; + linux,code = ; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + button-reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + }; + @@ -158,19 +158,19 @@ + + led-0 { + label = "blue:status"; -+ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + label = "red:status"; -+ gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 11 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-2 { + label = "green:status"; -+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; @@ -199,7 +199,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -220,7 +220,7 @@ + status = "okay"; +}; + -+&pinctrl { ++&pio { + mmc0_pins_default: mmc0default { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch b/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch index c11cf22d46..95e86f0997 100644 --- a/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch +++ b/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch @@ -443,7 +443,7 @@ + button-reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + }; + @@ -452,17 +452,17 @@ + + status_led: led-0 { + label = "green:status"; -+ gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "blue:wlan2g"; -+ gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 1 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "blue:wlan5g"; -+ gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + }; + }; + @@ -500,7 +500,7 @@ + + airoha,rx-pol-reverse; + -+ reset-gpios = <&gpio 49 GPIO_ACTIVE_LOW>; ++ reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + }; @@ -519,7 +519,7 @@ + status = "okay"; +}; + -+&pinctrl { ++&pio { + mdio_pins: mdio-pins { + mux { + function = "eth"; diff --git a/package/boot/uboot-mediatek/patches/443-add-nokia_ea0326gmp.patch b/package/boot/uboot-mediatek/patches/443-add-nokia_ea0326gmp.patch index 8f63adb5ab..16967ce77c 100644 --- a/package/boot/uboot-mediatek/patches/443-add-nokia_ea0326gmp.patch +++ b/package/boot/uboot-mediatek/patches/443-add-nokia_ea0326gmp.patch @@ -141,13 +141,13 @@ + button-reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + @@ -156,37 +156,37 @@ + + power_led: led-0 { + label = "green:power"; -+ gpios = <&gpio 4 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 4 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + label = "green:wan"; -+ gpios = <&gpio 5 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-2 { + label = "red:wan"; -+ gpios = <&gpio 6 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-3 { + label = "green:lan"; -+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-4 { + label = "green:wlan"; -+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 8 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-5 { + label = "green:wps"; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; @@ -197,7 +197,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -205,7 +205,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/444-add-abt_asr3000.patch b/package/boot/uboot-mediatek/patches/444-add-abt_asr3000.patch index e89bad5856..7d0bef8bec 100644 --- a/package/boot/uboot-mediatek/patches/444-add-abt_asr3000.patch +++ b/package/boot/uboot-mediatek/patches/444-add-abt_asr3000.patch @@ -110,7 +110,7 @@ +CONFIG_HEXDUMP=y --- /dev/null +++ b/arch/arm/dts/mt7981-abt-asr3000.dts -@@ -0,0 +1,176 @@ +@@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; @@ -137,18 +137,17 @@ + gpio-keys { + compatible = "gpio-keys"; + -+ + button-reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "mesh"; + linux,code = ; + linux,input-type = ; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + @@ -157,31 +156,31 @@ + + led-0 { + label = "red:wan"; -+ gpios = <&gpio 4 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-1 { + label = "green:wan"; -+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 8 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + mesh_led: led-2 { + label = "green:mesh"; -+ gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 15 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-3 { + label = "green:wlan2g"; -+ gpios = <&gpio 34 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 34 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-4 { + label = "green:wlan5g"; -+ gpios = <&gpio 35 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 35 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; @@ -192,7 +191,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -200,7 +199,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/445-add-cudy_tr3000-v1.patch b/package/boot/uboot-mediatek/patches/445-add-cudy_tr3000-v1.patch index b490a31db7..0cc023170e 100644 --- a/package/boot/uboot-mediatek/patches/445-add-cudy_tr3000-v1.patch +++ b/package/boot/uboot-mediatek/patches/445-add-cudy_tr3000-v1.patch @@ -140,14 +140,14 @@ + button-reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-mode { + label = "mode"; + linux,code = ; + linux,input-type = ; -+ gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + debounce-interval = <60>; + }; + }; @@ -157,13 +157,13 @@ + + led_status: led-0 { + label = "red:power"; -+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 11 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + label = "white:status"; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; @@ -184,7 +184,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/445-add-netis-nx31.patch b/package/boot/uboot-mediatek/patches/445-add-netis-nx31.patch index 3422bd42ac..76d7f648c5 100644 --- a/package/boot/uboot-mediatek/patches/445-add-netis-nx31.patch +++ b/package/boot/uboot-mediatek/patches/445-add-netis-nx31.patch @@ -143,13 +143,13 @@ + button-0 { + label = "mesh"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-1 { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + @@ -158,22 +158,22 @@ + + led-0 { + label = "blue:wlan2g"; -+ gpios = <&gpio 5 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "blue:status"; -+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + led-2 { + label = "blue:wan"; -+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 8 GPIO_ACTIVE_LOW>; + }; + + led-3 { + label = "blue:wlan5g"; -+ gpios = <&gpio 34 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 34 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -188,7 +188,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -196,7 +196,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/446-add-cmcc_a10.patch b/package/boot/uboot-mediatek/patches/446-add-cmcc_a10.patch index 87542c38b9..0e545ffd35 100644 --- a/package/boot/uboot-mediatek/patches/446-add-cmcc_a10.patch +++ b/package/boot/uboot-mediatek/patches/446-add-cmcc_a10.patch @@ -139,13 +139,13 @@ + button-reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + @@ -154,19 +154,19 @@ + + led-0 { + label = "blue:status"; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + running_led: led-1 { + label = "green:status"; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + boot_led: led-2 { + label = "red:status"; -+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 11 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; @@ -177,7 +177,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -185,7 +185,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/447-add-livinet_zr-3020.patch b/package/boot/uboot-mediatek/patches/447-add-livinet_zr-3020.patch index bb296dc3aa..8993235783 100644 --- a/package/boot/uboot-mediatek/patches/447-add-livinet_zr-3020.patch +++ b/package/boot/uboot-mediatek/patches/447-add-livinet_zr-3020.patch @@ -140,13 +140,13 @@ + button-reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + @@ -155,49 +155,49 @@ + + led-0 { + label = "red:d8"; -+ gpios = <&gpio 6 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-1 { + label = "blue:internet"; -+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + running_led: led-2 { + label = "blue:running"; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + upgrade_led: led-3 { + label = "green:upgrade"; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + boot_led: led-4 { + label = "red:boot"; -+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 11 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-5 { + label = "blue:d7"; -+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-6 { + label = "blue:wlan2g"; -+ gpios = <&gpio 34 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 34 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-7 { + label = "blue:wlan5g"; -+ gpios = <&gpio 35 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 35 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; @@ -208,7 +208,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -216,7 +216,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/448-add-imou_lc-hx3001.patch b/package/boot/uboot-mediatek/patches/448-add-imou_lc-hx3001.patch index ec3744b34b..e3a20c3549 100644 --- a/package/boot/uboot-mediatek/patches/448-add-imou_lc-hx3001.patch +++ b/package/boot/uboot-mediatek/patches/448-add-imou_lc-hx3001.patch @@ -141,14 +141,14 @@ + button-reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-mesh { + label = "mesh"; + linux,code = ; + linux,input-type = ; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + @@ -157,31 +157,31 @@ + + power_led: led-0 { + label = "green:power"; -+ gpios = <&gpio 4 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 4 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + label = "green:wan"; -+ gpios = <&gpio 5 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-2 { + label = "red:wan"; -+ gpios = <&gpio 6 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-3 { + label = "green:lan"; -+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-4 { + label = "green:wlan"; -+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 8 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; @@ -192,7 +192,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -200,7 +200,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/449-add-cetron_ct3003.patch b/package/boot/uboot-mediatek/patches/449-add-cetron_ct3003.patch index 4049e088e2..a497406f90 100644 --- a/package/boot/uboot-mediatek/patches/449-add-cetron_ct3003.patch +++ b/package/boot/uboot-mediatek/patches/449-add-cetron_ct3003.patch @@ -140,13 +140,13 @@ + button-reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; -+ gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + }; + }; + @@ -155,13 +155,13 @@ + + led_status_red: led-0 { + label = "red:status"; -+ gpios = <&gpio 3 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 3 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_status_green: led-1 { + label = "green:status"; -+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; @@ -172,7 +172,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -180,7 +180,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch index efa98a5198..a9401b5a72 100644 --- a/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch +++ b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch @@ -671,7 +671,7 @@ + wps { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 14 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 14 GPIO_ACTIVE_LOW>; + }; + }; + @@ -680,12 +680,12 @@ + + led_status_green: led-green { + label = "green:status"; -+ gpios = <&gpio 79 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 79 GPIO_ACTIVE_HIGH>; + }; + + led_status_blue: led-blue { + label = "blue:status"; -+ gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 63 GPIO_ACTIVE_HIGH>; + }; + }; +}; @@ -713,7 +713,7 @@ + }; +}; + -+&pinctrl { ++&pio { + i2c1_pins: i2c1-pins { + mux { + function = "i2c"; diff --git a/package/boot/uboot-mediatek/patches/451-add-tplink-xtr8488.patch b/package/boot/uboot-mediatek/patches/451-add-tplink-xtr8488.patch index a42dfc373b..13d9875258 100644 --- a/package/boot/uboot-mediatek/patches/451-add-tplink-xtr8488.patch +++ b/package/boot/uboot-mediatek/patches/451-add-tplink-xtr8488.patch @@ -165,19 +165,19 @@ + reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 15 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 15 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; -+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 16 GPIO_ACTIVE_LOW>; + }; + + turbo { + label = "turbo"; + linux,code = ; -+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + }; + @@ -186,17 +186,17 @@ + + status_red { + label = "red:status"; -+ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; + + status_green { + label = "green:status"; -+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 8 GPIO_ACTIVE_HIGH>; + }; + + turbo { + label = "green:turbo"; -+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -217,7 +217,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 6 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -225,7 +225,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/452-add-xiaomi-redmi-ax6s.patch b/package/boot/uboot-mediatek/patches/452-add-xiaomi-redmi-ax6s.patch index 8319ba6839..0583babacd 100644 --- a/package/boot/uboot-mediatek/patches/452-add-xiaomi-redmi-ax6s.patch +++ b/package/boot/uboot-mediatek/patches/452-add-xiaomi-redmi-ax6s.patch @@ -15,14 +15,14 @@ Subject: [PATCH] add xiaomi redmi ax6s --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1195,6 +1195,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1137,6 +1137,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-linksys-e8450-ubi.dtb \ mt7622-ubnt-unifi-6-lr.dtb \ mt7622-ubnt-unifi-6-lr-v3.dtb \ + mt7622-xiaomi-redmi-router-ax6s.dtb \ mt7623n-bananapi-bpi-r2.dtb \ - mt7629-rfb.dtb \ mt7981-rfb.dtb \ + mt7981-snfi-nand-rfb.dtb \ --- /dev/null +++ b/arch/arm/dts/mt7622-xiaomi-redmi-router-ax6s.dts @@ -0,0 +1,166 @@ diff --git a/package/boot/uboot-mediatek/patches/453-add-openwrt-one.patch b/package/boot/uboot-mediatek/patches/453-add-openwrt-one.patch index 8401aae0b0..a190980342 100644 --- a/package/boot/uboot-mediatek/patches/453-add-openwrt-one.patch +++ b/package/boot/uboot-mediatek/patches/453-add-openwrt-one.patch @@ -31,13 +31,13 @@ + + user { + label = "front"; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + reset { + label = "back"; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; @@ -47,17 +47,17 @@ + + red { + label = "red"; -+ gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 9 GPIO_ACTIVE_HIGH>; + }; + + white { + label = "white"; -+ gpios = <&gpio 13 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 13 GPIO_ACTIVE_HIGH>; + }; + + green { + label = "green"; -+ gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 15 GPIO_ACTIVE_HIGH>; + }; + }; +}; @@ -78,7 +78,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/454-add-glinet-x3000.patch b/package/boot/uboot-mediatek/patches/454-add-glinet-x3000.patch index 58a4e15613..c4b3a1e3fc 100644 --- a/package/boot/uboot-mediatek/patches/454-add-glinet-x3000.patch +++ b/package/boot/uboot-mediatek/patches/454-add-glinet-x3000.patch @@ -39,7 +39,7 @@ + reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + @@ -48,42 +48,42 @@ + + wifi2g { + label = "green:wifi2g"; -+ gpios = <&gpio 30 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 30 GPIO_ACTIVE_LOW>; + }; + + wifi5g { + label = "green:wifi5g"; -+ gpios = <&gpio 38 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 38 GPIO_ACTIVE_LOW>; + }; + + 5g_led1 { + label = "green:5g:led1"; -+ gpios = <&gpio 6 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 6 GPIO_ACTIVE_LOW>; + }; + + 5g_led2 { + label = "green:5g:led2"; -+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + 5g_led3 { + label = "green:5g:led3"; -+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 8 GPIO_ACTIVE_LOW>; + }; + + 5g_led4 { + label = "green:5g:led4"; -+ gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 4 GPIO_ACTIVE_HIGH>; + }; + + power { + label = "green:power"; -+ gpios = <&gpio 39 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 39 GPIO_ACTIVE_LOW>; + }; + + wan { + label = "green:wan"; -+ gpios = <&gpio 31 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 31 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -115,7 +115,7 @@ + status = "okay"; +}; + -+&pinctrl { ++&pio { + mmc0_pins_default: mmc0-pins-default { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/456-add-arcadyan-mozart.patch b/package/boot/uboot-mediatek/patches/456-add-arcadyan-mozart.patch index 2e9259a926..edfb015944 100644 --- a/package/boot/uboot-mediatek/patches/456-add-arcadyan-mozart.patch +++ b/package/boot/uboot-mediatek/patches/456-add-arcadyan-mozart.patch @@ -117,7 +117,7 @@ +CONFIG_HEXDUMP=y --- /dev/null +++ b/defenvs/arcadyan_mozart_env -@@ -0,0 +1,55 @@ +@@ -0,0 +1,59 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 +loadaddr=0x50000000 @@ -127,6 +127,7 @@ +bootconf_extra= +bootdelay=0 +bootfile=immortalwrt-mediatek-filogic-arcadyan_mozart-initramfs.itb ++bootfile_gpt=immortalwrt-mediatek-filogic-arcadyan_mozart-emmc-gpt.bin +bootfile_bl2=immortalwrt-mediatek-filogic-arcadyan_mozart-emmc-preloader.bin +bootfile_fip=immortalwrt-mediatek-filogic-arcadyan_mozart-emmc-bl31-uboot.fip +bootfile_upg=immortalwrt-mediatek-filogic-arcadyan_mozart-squashfs-sysupgrade.itb @@ -145,8 +146,9 @@ +bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return +bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return +bootmenu_7=Load BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return -+bootmenu_8=Reboot.=reset -+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++bootmenu_8=Load GPT Table via TFTP then write to eMMC.=run boot_tftp_write_gpt ; run bootmenu_confirm_return ++bootmenu_9=Reboot.=reset ++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset +boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever +boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf#$bootconf_extra ; led $bootled_pwr off @@ -156,6 +158,7 @@ +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_extra ; fi +boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi +boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip ++boot_tftp_write_gpt=tftpboot $loadaddr $bootfile_gpt && run emmc_write_gpt +boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf +mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size @@ -165,6 +168,7 @@ +reset_factory=eraseenv && reset +emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol +emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++emmc_write_gpt=mmc erase 0x0 0x22 && mmc write $fileaddr 0x0 0x22 +emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 +emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 +emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol @@ -220,7 +224,7 @@ + wps { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 143 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 143 GPIO_ACTIVE_LOW>; + }; + }; + @@ -229,17 +233,17 @@ + + led-red { + label = "red:status"; -+ gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 29 GPIO_ACTIVE_HIGH>; + }; + + led-green { + label = "blue:status"; -+ gpios = <&gpio 30 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 30 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + label = "blue:status"; -+ gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 31 GPIO_ACTIVE_HIGH>; + }; + }; +}; @@ -261,7 +265,7 @@ + }; +}; + -+&pinctrl { ++&pio { + mmc0_pins_default: mmc0default { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/457-initialized-the-watchdog-subsystem-later.patch b/package/boot/uboot-mediatek/patches/457-initialized-the-watchdog-subsystem-later.patch index 118959b8ee..cecfd5a63b 100644 --- a/package/boot/uboot-mediatek/patches/457-initialized-the-watchdog-subsystem-later.patch +++ b/package/boot/uboot-mediatek/patches/457-initialized-the-watchdog-subsystem-later.patch @@ -13,7 +13,7 @@ Signed-off-by: Enrico Mioso --- a/common/board_r.c +++ b/common/board_r.c -@@ -682,19 +682,13 @@ static init_fnc_t init_sequence_r[] = { +@@ -681,19 +681,13 @@ static init_fnc_t init_sequence_r[] = { serial_initialize, initr_announce, dm_announce, @@ -33,7 +33,7 @@ Signed-off-by: Enrico Mioso #if defined(CONFIG_PCI_INIT_R) && defined(CONFIG_SYS_EARLY_PCI_INIT) /* * Do early PCI configuration _before_ the flash gets initialised, -@@ -709,7 +703,6 @@ static init_fnc_t init_sequence_r[] = { +@@ -708,7 +702,6 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_MTD_NOR_FLASH initr_flash, #endif @@ -41,7 +41,7 @@ Signed-off-by: Enrico Mioso #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86) /* initialize higher level parts of CPU like time base and timers */ cpu_init_r, -@@ -738,6 +731,10 @@ static init_fnc_t init_sequence_r[] = { +@@ -737,6 +730,10 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_PVBLOCK initr_pvblock, #endif diff --git a/package/boot/uboot-mediatek/patches/458-add-GatoNetworks-GDSP.patch b/package/boot/uboot-mediatek/patches/458-add-GatoNetworks-GDSP.patch index e796f1ab18..38d0e206a0 100644 --- a/package/boot/uboot-mediatek/patches/458-add-GatoNetworks-GDSP.patch +++ b/package/boot/uboot-mediatek/patches/458-add-GatoNetworks-GDSP.patch @@ -44,7 +44,7 @@ Signed-off-by: Enrico Mioso + reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + @@ -53,47 +53,47 @@ Signed-off-by: Enrico Mioso + + sim1 { + label = "sim1"; -+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 13 GPIO_ACTIVE_LOW>; + }; + + sim2 { + label = "sim2"; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + + sg1 { + label = "sg1"; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + sg2 { + label = "sg2"; -+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + sg3 { + label = "sg3"; -+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + + sg4 { + label = "sg4"; -+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + sg5 { + label = "sg5"; -+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 8 GPIO_ACTIVE_LOW>; + }; + + sg6 { + label = "sg6"; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + }; + gpio-watchdog { + compatible = "linux,wdt-gpio"; -+ gpios = <&gpio 6 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 6 GPIO_ACTIVE_LOW>; + hw_algo = "toggle"; + hw_margin_ms = <25000>; + always-running; @@ -106,7 +106,7 @@ Signed-off-by: Enrico Mioso + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -166,7 +166,7 @@ Signed-off-by: Enrico Mioso + }; +}; + -+&pinctrl { ++&pio { + uart1_pins: uart1-pins { + mux { + function = "uart"; diff --git a/package/boot/uboot-mediatek/patches/459-add-mercusys-mr90x-v1.patch b/package/boot/uboot-mediatek/patches/459-add-mercusys-mr90x-v1.patch index 2e09dcb065..d10ef15e33 100644 --- a/package/boot/uboot-mediatek/patches/459-add-mercusys-mr90x-v1.patch +++ b/package/boot/uboot-mediatek/patches/459-add-mercusys-mr90x-v1.patch @@ -144,7 +144,7 @@ + reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; + @@ -153,32 +153,32 @@ + + led-0 { + label = "green:lan2"; -+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "green:lan1"; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-2 { + label = "green:lan0"; -+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + + led-3 { + label = "green:wan"; -+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 13 GPIO_ACTIVE_LOW>; + }; + + led-4 { + label = "amber:status"; -+ gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 16 GPIO_ACTIVE_HIGH>; + }; + + led_status_green: led-5 { + label = "green:status"; -+ gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 17 GPIO_ACTIVE_HIGH>; + }; + }; +}; @@ -198,7 +198,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -206,7 +206,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/460-add-routerich-ax3000.patch b/package/boot/uboot-mediatek/patches/460-add-routerich-ax3000.patch index a8c3ab2225..ce677faec3 100644 --- a/package/boot/uboot-mediatek/patches/460-add-routerich-ax3000.patch +++ b/package/boot/uboot-mediatek/patches/460-add-routerich-ax3000.patch @@ -143,13 +143,13 @@ + button-0 { + label = "mesh"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-1 { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + @@ -158,47 +158,47 @@ + + led-0 { + label = "red:wlan5g"; -+ gpios = <&gpio 5 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "red:wan"; -+ gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 6 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "blue:power"; -+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + led-3 { + label = "blue:lan1"; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-4 { + label = "blue:lan2"; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + led-5 { + label = "blue:lan3"; -+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + led-6 { + label = "blue:wan"; -+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + + led-7 { + label = "blue:wlan2g"; -+ gpios = <&gpio 34 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 34 GPIO_ACTIVE_LOW>; + }; + + led-8 { + label = "blue:mesh"; -+ gpios = <&gpio 35 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 35 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -213,7 +213,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -221,7 +221,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/461-add-asus-zenwifi-bt8.patch b/package/boot/uboot-mediatek/patches/461-add-asus-zenwifi-bt8.patch index ff7487313f..a325092c7d 100644 --- a/package/boot/uboot-mediatek/patches/461-add-asus-zenwifi-bt8.patch +++ b/package/boot/uboot-mediatek/patches/461-add-asus-zenwifi-bt8.patch @@ -1,6 +1,6 @@ --- /dev/null +++ b/configs/mt7988a_asus_zenwifi-bt8_defconfig -@@ -0,0 +1,133 @@ +@@ -0,0 +1,130 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y @@ -11,10 +11,10 @@ +CONFIG_DEFAULT_DEVICE_TREE="mt7988a-asus-zenwifi-bt8" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TARGET_MT7988=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 +CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x50000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y @@ -50,14 +50,14 @@ +CONFIG_CMD_PCI=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_USB=y -+CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_RARP=y -+CONFIG_CMD_PING=y +CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y -+CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PSTORE=y @@ -88,8 +88,6 @@ +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.254" -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y @@ -133,7 +131,6 @@ +CONFIG_USB_STORAGE=y +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_LMB_MAX_REGIONS=64 --- /dev/null +++ b/asus_zenwifi-bt8_env @@ -0,0 +1,56 @@ @@ -244,13 +241,13 @@ + reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 13 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; -+ gpios = <&gpio 14 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 14 GPIO_ACTIVE_LOW>; + }; + }; + @@ -259,17 +256,17 @@ + + led_status_red: led-red { + label = "red:status"; -+ gpios = <&gpio 57 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 57 GPIO_ACTIVE_HIGH>; + }; + + led_status_green: led-green { + label = "green:status"; -+ gpios = <&gpio 21 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 21 GPIO_ACTIVE_HIGH>; + }; + + led_status_blue: led-blue { + label = "blue:status"; -+ gpios = <&gpio 59 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 59 GPIO_ACTIVE_HIGH>; + }; + }; +}; @@ -291,7 +288,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi0_pins: spi0-pins { + mux { + function = "spi"; diff --git a/package/boot/uboot-mediatek/patches/462-add-netcore-n60-pro.patch b/package/boot/uboot-mediatek/patches/462-add-netcore-n60-pro.patch index d50b86abe6..b30184e60e 100644 --- a/package/boot/uboot-mediatek/patches/462-add-netcore-n60-pro.patch +++ b/package/boot/uboot-mediatek/patches/462-add-netcore-n60-pro.patch @@ -1,3 +1,4 @@ +Add test header. --- /dev/null +++ b/configs/mt7986_netcore_n60-pro_defconfig @@ -0,0 +1,128 @@ @@ -165,13 +166,13 @@ + button-reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + button-mesh { + label = "mesh"; + linux,code = ; -+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; + @@ -180,27 +181,27 @@ + + led-0 { + label = "blue:wlan"; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + power_led: led-1 { + label = "blue:power"; -+ gpios = <&gpio 29 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 29 GPIO_ACTIVE_LOW>; + }; + + led-2 { + label = "blue:status"; -+ gpios = <&gpio 30 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 30 GPIO_ACTIVE_LOW>; + }; + + led-3 { + label = "blue:mesh"; -+ gpios = <&gpio 31 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 31 GPIO_ACTIVE_LOW>; + }; + + led-4 { + label = "blue:wan"; -+ gpios = <&gpio 32 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 32 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -221,7 +222,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -229,7 +230,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; diff --git a/package/boot/uboot-mediatek/patches/463-add-snr-snr-cpe-ax2.patch b/package/boot/uboot-mediatek/patches/463-add-snr-snr-cpe-ax2.patch new file mode 100644 index 0000000000..87ef150368 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/463-add-snr-snr-cpe-ax2.patch @@ -0,0 +1,349 @@ +--- /dev/null ++++ b/configs/mt7981_snr_snr-cpe-ax2_defconfig +@@ -0,0 +1,106 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981-snr_snr-cpe-ax2" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007ef00 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-snr_snr-cpe-ax2.dtb" ++CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_CPU=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/snr_snr-cpe-ax2_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++# CONFIG_MMC is not set ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_SERIAL_RX_BUFFER=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPIM=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y +--- /dev/null ++++ b/arch/arm/dts/mt7981-snr_snr-cpe-ax2.dts +@@ -0,0 +1,177 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2025 ++ * Author: Nikolay March ++ */ ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include ++#include ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "SNR SNR-CPE-AX2"; ++ compatible = "snr,snr-cpe-ax2", "mediatek,mt7981"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ button-0 { ++ label = "mesh"; ++ linux,code = ; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; ++ }; ++ ++ button-1 { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ label = "red:status"; ++ gpios = <&pio 4 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-1 { ++ label = "red:status_1"; ++ gpios = <&pio 5 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-2 { ++ label = "blue:wlan_2ghz"; ++ gpios = <&pio 6 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-3 { ++ label = "blue:wlan_5ghz"; ++ gpios = <&pio 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-4 { ++ label = "blue:status"; ++ gpios = <&pio 9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-5 { ++ label = "blue:wan"; ++ gpios = <&pio 10 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-6 { ++ label = "blue:status_1"; ++ gpios = <&pio 11 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ }; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x0 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env (unused)"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@160000 { ++ label = "Factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "FIP"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x7a80000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/defenvs/snr_snr-cpe-ax2_env +@@ -0,0 +1,57 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootcmd=run check_buttons ; if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=immortalwrt-mediatek-filogic-snr_snr-cpe-ax2-initramfs-recovery.itb ++bootfile_bl2=immortalwrt-mediatek-filogic-snr_snr-cpe-ax2-preloader.bin ++bootfile_fip=immortalwrt-mediatek-filogic-snr_snr-cpe-ax2-bl31-uboot.fip ++bootfile_upg=immortalwrt-mediatek-filogic-snr_snr-cpe-ax2-squashfs-sysupgrade.itb ++bootled_status=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_status on ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_status on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led bootled_status off ++boot_recovery=led $bootled_status on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led bootled_status off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_status on ; while true ; do run boot_tftp ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++check_buttons=if button reset ; then run boot_tftp ; fi ++ethaddr_factory=mtd read Factory 0x40080000 0xe000 0x20000 && env readmem -b ethaddr 0x40080000 0x6 ; setenv ethaddr_factory ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase FIP && mtd write FIP $loadaddr ++mtd_write_bl2=mtd erase BL2 && mtd write BL2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" diff --git a/package/boot/uboot-mediatek/patches/470-add-konka_komi-a31.patch b/package/boot/uboot-mediatek/patches/470-add-konka_komi-a31.patch index d523542aaf..784d0dc918 100644 --- a/package/boot/uboot-mediatek/patches/470-add-konka_komi-a31.patch +++ b/package/boot/uboot-mediatek/patches/470-add-konka_komi-a31.patch @@ -382,13 +382,13 @@ + label = "mesh"; + linux,code = ; + linux,input-type = ; -+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + + button-reset { + label = "reset"; + linux,code = ; -+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + @@ -397,19 +397,19 @@ + + green_led: led-0 { + label = "green:status"; -+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 8 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-1 { + label = "blue:status"; -+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>; ++ gpios = <&pio 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + red_led: led-2 { + label = "red:status"; -+ gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 34 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; @@ -420,7 +420,7 @@ + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; -+ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; @@ -428,7 +428,7 @@ + }; +}; + -+&pinctrl { ++&pio { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; @@ -540,7 +540,7 @@ + status = "okay"; +}; + -+&pinctrl { ++&pio { + mmc0_pins_default: mmc0default { + mux { + function = "flash"; @@ -578,7 +578,7 @@ +/dts-v1/; +#include "mt7981-konka-komi-a31.dts" + -+&pinctrl { ++&pio { + spi2_flash_pins: spi2-spi2-pins { + mux { + function = "spi"; diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-photonicat.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-photonicat.dts index 530f26c6a4..34a47e2904 100644 --- a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-photonicat.dts +++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-photonicat.dts @@ -53,6 +53,7 @@ clock-names = "ext_clock"; pinctrl-names = "default"; pinctrl-0 = <&wifi_enable_h &clk32k_out1>; + post-power-on-delay-ms = <200>; reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; }; @@ -135,6 +136,7 @@ regulator-name = "vcc3v3_pi6c"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; vin-supply = <&vcc_syson>; }; @@ -146,6 +148,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; vin-supply = <&vcc3v3_pi6c>; }; @@ -357,6 +360,10 @@ }; &pcie3x2 { + max-link-speed = <1>; + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1m0_pins>; reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; @@ -459,7 +466,6 @@ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; sd-uhs-sdr25; sd-uhs-sdr50; - sd-uhs-sdr104; vmmc-supply = <&vcc3v3_sys>; vqmmc-supply = <&vcc_1v8>; #address-cells = <1>; diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile index 5531de2794..49a7815005 100644 --- a/package/boot/uboot-sunxi/Makefile +++ b/package/boot/uboot-sunxi/Makefile @@ -92,6 +92,12 @@ define U-Boot/Bananapro BUILD_DEVICES:=lemaker_bananapro endef +define U-Boot/beelink_x2 + BUILD_SUBTARGET:=cortexa7 + NAME:=Beelink X2 (H3) + BUILD_DEVICES:=roofull_beelink-x2 +endef + define U-Boot/Cubieboard BUILD_SUBTARGET:=cortexa8 NAME:=Cubieboard @@ -388,6 +394,7 @@ UBOOT_TARGETS := \ bananapi_p2_zero \ Bananapi_M2_Ultra \ Bananapro \ + beelink_x2 \ Cubieboard \ Cubieboard2 \ Cubietruck \ diff --git a/package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic index 5a9db754cd..9b1fb912e9 100644 --- a/package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic +++ b/package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic @@ -49,6 +49,7 @@ netis,nx31|\ nokia,ea0326gmp|\ qihoo,360t7|\ routerich,ax3000-ubootmod|\ +snr,snr-cpe-ax2|\ tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ tplink,tl-xdr6088|\ diff --git a/package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq60xx b/package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq60xx index 77587b4922..0c43cbd0c6 100644 --- a/package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq60xx +++ b/package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq60xx @@ -7,21 +7,6 @@ touch /etc/config/ubootenv board=$(board_name) -ubootenv_add_mtd() { - local idx="$(find_mtd_index "${1}")" - [ -n "$idx" ] && ubootenv_add_uci_config "/dev/mtd$idx" "${2}" "${3}" "${4}" -} - -ubootenv_add_sys_mtd() { - local idx="$(find_mtd_index "${1}")" - [ -n "$idx" ] && ubootenv_add_uci_sys_config "/dev/mtd$idx" "${2}" "${3}" "${4}" -} - -ubootenv_add_mmc() { - local mmcpart="$(find_mmc_part "${1}")" - [ -n "$mmcpart" ] && ubootenv_add_uci_config "$mmcpart" "${2}" "${3}" "${4}" "${5}" -} - case "$board" in 8devices,mango-dvk|\ 8devices,mango-dvk-sfp|\ @@ -39,7 +24,8 @@ netgear,wax214|\ netgear,wax610|\ netgear,wax610y|\ tplink,eap610od|\ -tplink,eap623od-hd-v1) +tplink,eap623od-hd-v1|\ +tplink,eap625od-hd-v1) ubootenv_add_mtd "0:appsblenv" "0x0" "0x40000" "0x20000" ;; linksys,mr7350|\ diff --git a/package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq807x b/package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq807x index f3299932e8..92730a9c10 100644 --- a/package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq807x +++ b/package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq807x @@ -7,21 +7,6 @@ touch /etc/config/ubootenv board=$(board_name) -ubootenv_add_mtd() { - local idx="$(find_mtd_index "${1}")" - [ -n "$idx" ] && ubootenv_add_uci_config "/dev/mtd$idx" "${2}" "${3}" "${4}" -} - -ubootenv_add_sys_mtd() { - local idx="$(find_mtd_index "${1}")" - [ -n "$idx" ] && ubootenv_add_uci_sys_config "/dev/mtd$idx" "${2}" "${3}" "${4}" -} - -ubootenv_add_mmc() { - local mmcpart="$(find_mmc_part "${1}")" - [ -n "$mmcpart" ] && ubootenv_add_uci_config "$mmcpart" "${2}" "${3}" "${4}" "${5}" -} - case "$board" in aliyun,ap8220|\ compex,wpq873|\ diff --git a/package/boot/uboot-tools/uboot-envtools/files/uboot-envtools.sh b/package/boot/uboot-tools/uboot-envtools/files/uboot-envtools.sh index 980c9962b1..57c0f3db01 100644 --- a/package/boot/uboot-tools/uboot-envtools/files/uboot-envtools.sh +++ b/package/boot/uboot-tools/uboot-envtools/files/uboot-envtools.sh @@ -44,3 +44,18 @@ ubootenv_add_app_config() { config_get numsec "$1" numsec grep -q "^[[:space:]]*${dev}[[:space:]]*${offset}" "/etc/fw_${cfgtype#uboot}.config" || echo "$dev $offset $envsize $secsize $numsec" >>"/etc/fw_${cfgtype#uboot}.config" } + +ubootenv_add_mtd() { + local idx="$(find_mtd_index "${1}")" + [ -n "$idx" ] && ubootenv_add_uci_config "/dev/mtd$idx" "${2}" "${3}" "${4}" "${5}" +} + +ubootenv_add_sys_mtd() { + local idx="$(find_mtd_index "${1}")" + [ -n "$idx" ] && ubootenv_add_uci_sys_config "/dev/mtd$idx" "${2}" "${3}" "${4}" "${5}" +} + +ubootenv_add_mmc() { + local mmcpart="$(find_mmc_part "${1}")" + [ -n "$mmcpart" ] && ubootenv_add_uci_config "$mmcpart" "${2}" "${3}" "${4}" "${5}" +} diff --git a/package/devel/kselftests-bpf/Makefile b/package/devel/kselftests-bpf/Makefile index d69e1e6dc3..d2d988eb38 100644 --- a/package/devel/kselftests-bpf/Makefile +++ b/package/devel/kselftests-bpf/Makefile @@ -24,7 +24,7 @@ define Package/kselftests-bpf SECTION:=devel CATEGORY:=Development DEPENDS:= \ - +libelf +zlib +libpthread +librt @!IN_SDK \ + +libelf +zlib +libpthread +librt +!LINUX_6_6:libpcap @!IN_SDK \ @KERNEL_DEBUG_FS @KERNEL_DEBUG_INFO_BTF @KERNEL_BPF_EVENTS TITLE:=Linux Kernel Selftests (BPF) URL:=http://www.kernel.org @@ -34,13 +34,15 @@ define Package/kselftests-bpf/description kselftests-bpf is the Linux kernel BPF test suite endef -EXE_TARGETS = test_verifier +EXE_TARGETS:= \ + test_verifier -MOD_TARGETS = $(if $(call kernel_patchver_ge,6.4),bpf_testmod.ko) +MOD_TARGETS:= \ + bpf_testmod.ko MAKE_PATH:=tools/testing/selftests/bpf -MAKE_VARS = \ +MAKE_VARS:= \ ARCH="$(LINUX_KARCH)" \ CROSS_COMPILE="$(TARGET_CROSS)" \ EXTRA_CFLAGS="$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)" \ @@ -48,7 +50,7 @@ MAKE_VARS = \ TOOLCHAIN_INCLUDE="$(TOOLCHAIN_INC_DIRS)" \ KBUILD_OUTPUT="$(LINUX_DIR)" -MAKE_FLAGS = \ +MAKE_FLAGS:= \ $(if $(findstring c,$(OPENWRT_VERBOSE)),V=1,V='') \ OUTPUT=$(PKG_BUILD_DIR) @@ -67,7 +69,7 @@ define Package/kselftests-bpf/install $(foreach tgt,$(EXE_TARGETS), \ $(INSTALL_BIN) \ $(PKG_BUILD_DIR)/$(tgt) $(1)/usr/libexec/$(PKG_NAME); \ -) + ) endef $(eval $(call BuildPackage,kselftests-bpf)) diff --git a/package/firmware/ipq-wifi/Makefile b/package/firmware/ipq-wifi/Makefile index 2f89e5d222..a3b8f84382 100644 --- a/package/firmware/ipq-wifi/Makefile +++ b/package/firmware/ipq-wifi/Makefile @@ -6,9 +6,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/firmware/qca-wireless.git -PKG_SOURCE_DATE:=2025-05-13 -PKG_SOURCE_VERSION:=dae5a57ea2c28eea409c51cdcb1b57ecbb366a26 -PKG_MIRROR_HASH:=9a9a63cc41a8d992658149bf6a6dd2287d022cd8829a4c4a62a4a4449c88f31a +PKG_SOURCE_DATE:=2025-05-30 +PKG_SOURCE_VERSION:=fde3d2a7ce59be389224304049a4a5b9ca49a45e +PKG_MIRROR_HASH:=2e149366118192d4976baf42ac23d22ef32e477feb111d2756a2411278b6cf46 PKG_FLAGS:=nonshared include $(INCLUDE_DIR)/package.mk @@ -28,6 +28,7 @@ endef ALLWIFIBOARDS:= \ 8devices_mango \ + alfa-network_ap120c-ax \ aliyun_ap8220 \ arcadyan_aw1000 \ asus_rt-ax89x \ @@ -74,6 +75,7 @@ ALLWIFIBOARDS:= \ tplink_eap623od-hd-v1 \ tplink_eap625od-hd-v1 \ tplink_eap660hd-v1 \ + tplink_archer-c6-v2 \ wallys_dr40x9 \ xiaomi_ax3600 \ xiaomi_ax9000 \ @@ -191,6 +193,7 @@ endef # board-. $(eval $(call generate-ipq-wifi-package,8devices_mango,8devices Mango)) +$(eval $(call generate-ipq-wifi-package,alfa-network_ap120c-ax,ALFA Network AP120C-AX)) $(eval $(call generate-ipq-wifi-package,aliyun_ap8220,Aliyun AP8220)) $(eval $(call generate-ipq-wifi-package,arcadyan_aw1000,Arcadyan AW1000)) $(eval $(call generate-ipq-wifi-package,asus_rt-ax89x,Asus RT-AX89X)) @@ -237,6 +240,7 @@ $(eval $(call generate-ipq-wifi-package,tplink_eap620hd-v1,TP-Link EAP620 HD v1) $(eval $(call generate-ipq-wifi-package,tplink_eap623od-hd-v1,TP-Link EAP623-Outdoor HD v1)) $(eval $(call generate-ipq-wifi-package,tplink_eap625od-hd-v1,TP-Link EAP625-Outdoor HD v1)) $(eval $(call generate-ipq-wifi-package,tplink_eap660hd-v1,TP-Link EAP660 HD v1)) +$(eval $(call generate-ipq-wifi-package,tplink_archer-c6-v2,TP-Link Archer C6 V2)) $(eval $(call generate-ipq-wifi-package,wallys_dr40x9,Wallys DR40X9)) $(eval $(call generate-ipq-wifi-package,xiaomi_ax3600,Xiaomi AX3600)) $(eval $(call generate-ipq-wifi-package,xiaomi_ax9000,Xiaomi AX9000)) diff --git a/package/kernel/linux/modules/other.mk b/package/kernel/linux/modules/other.mk index 61e395813b..f703cbb816 100644 --- a/package/kernel/linux/modules/other.mk +++ b/package/kernel/linux/modules/other.mk @@ -714,10 +714,7 @@ define KernelPackage/zram/config if PACKAGE_kmod-zram if !LINUX_6_6 config KERNEL_ZRAM_BACKEND_LZO - bool "lzo and lzo-rle compression support" if KERNEL_ZRAM_BACKEND_LZ4 || \ - KERNEL_ZRAM_BACKEND_LZ4HC || KERNEL_ZRAM_BACKEND_ZSTD - default !KERNEL_ZRAM_BACKEND_LZ4 && \ - !KERNEL_ZRAM_BACKEND_LZ4HC && !KERNEL_ZRAM_BACKEND_ZSTD + bool "lzo and lzo-rle compression support" config KERNEL_ZRAM_BACKEND_LZ4 bool "lz4 compression support" @@ -728,6 +725,12 @@ define KernelPackage/zram/config config KERNEL_ZRAM_BACKEND_ZSTD bool "zstd compression support" + config KERNEL_ZRAM_BACKEND_FORCE_LZO + def_bool !KERNEL_ZRAM_BACKEND_LZ4 && \ + !KERNEL_ZRAM_BACKEND_LZ4HC && \ + !KERNEL_ZRAM_BACKEND_ZSTD + select KERNEL_ZRAM_BACKEND_LZO + endif choice prompt "ZRAM Default compressor" diff --git a/package/kernel/linux/modules/video.mk b/package/kernel/linux/modules/video.mk index ed231506ba..bd3de79f11 100644 --- a/package/kernel/linux/modules/video.mk +++ b/package/kernel/linux/modules/video.mk @@ -372,7 +372,8 @@ $(eval $(call KernelPackage,drm-exec)) define KernelPackage/drm-gem-shmem-helper SUBMENU:=$(VIDEO_MENU) TITLE:=GEM shmem helper functions - DEPENDS:=@DISPLAY_SUPPORT +kmod-drm + DEPENDS:=@DISPLAY_SUPPORT +kmod-drm +!LINUX_6_6:kmod-drm-kms-helper \ + +!LINUX_6_6:kmod-fb-sys-fops +!LINUX_6_6:kmod-fb-sys-ram KCONFIG:=CONFIG_DRM_GEM_SHMEM_HELPER FILES:=$(LINUX_DIR)/drivers/gpu/drm/drm_shmem_helper.ko AUTOLOAD:=$(call AutoProbe,drm_shmem_helper) @@ -702,7 +703,7 @@ $(eval $(call KernelPackage,drm-panfrost)) define KernelPackage/drm-panthor SUBMENU:=$(VIDEO_MENU) TITLE:=DRM support for ARM Mali CSF-based GPUs - DEPENDS:=@LINUX_6_12 @TARGET_rockchip +kmod-drm +kmod-drm-exec \ + DEPENDS:=@TARGET_rockchip +kmod-drm +kmod-drm-exec \ +kmod-drm-gem-shmem-helper +panthor-firmware KCONFIG:= \ CONFIG_DRM_GPUVM \ diff --git a/package/kernel/mac80211/patches/nss/ath11k/999-901-ath11k-NSS-use-ath11k_nss_get_arvif_from_dev.patch b/package/kernel/mac80211/patches/nss/ath11k/999-901-ath11k-NSS-use-ath11k_nss_get_arvif_from_dev.patch index b50dcdd0d8..ab45267f05 100644 --- a/package/kernel/mac80211/patches/nss/ath11k/999-901-ath11k-NSS-use-ath11k_nss_get_arvif_from_dev.patch +++ b/package/kernel/mac80211/patches/nss/ath11k/999-901-ath11k-NSS-use-ath11k_nss_get_arvif_from_dev.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath11k/nss.c +++ b/drivers/net/wireless/ath/ath11k/nss.c -@@ -978,36 +978,20 @@ ath11k_nss_vdev_data_receive(struct net_ +@@ -907,36 +907,20 @@ ath11k_nss_vdev_data_receive(struct net_ __attribute__((unused)) struct napi_struct *napi) { struct wireless_dev *wdev = NULL; @@ -40,7 +40,7 @@ ab = arvif->ar->ab; skb->dev = dev; -@@ -1016,7 +1000,7 @@ ath11k_nss_vdev_data_receive(struct net_ +@@ -945,7 +929,7 @@ ath11k_nss_vdev_data_receive(struct net_ ath11k_dbg_dump(ab, ATH11K_DBG_DP_RX, "", "dp rx msdu from nss: ", skb->data, skb->len); diff --git a/package/kernel/mac80211/patches/nss/ath11k/999-903-ath11k-use-ath11k_sta_to_arsta.patch b/package/kernel/mac80211/patches/nss/ath11k/999-903-ath11k-use-ath11k_sta_to_arsta.patch index 5bea6ad101..4a0a656b1f 100644 --- a/package/kernel/mac80211/patches/nss/ath11k/999-903-ath11k-use-ath11k_sta_to_arsta.patch +++ b/package/kernel/mac80211/patches/nss/ath11k/999-903-ath11k-use-ath11k_sta_to_arsta.patch @@ -11,7 +11,7 @@ --- a/drivers/net/wireless/ath/ath11k/dp_rx.c +++ b/drivers/net/wireless/ath/ath11k/dp_rx.c -@@ -1575,7 +1575,7 @@ static void ath11k_dp_ppdu_stats_flush_t +@@ -1576,7 +1576,7 @@ static void ath11k_dp_ppdu_stats_flush_t goto exit; sta = peer->sta; @@ -20,7 +20,7 @@ memset(&status, 0, sizeof(status)); -@@ -1941,7 +1941,7 @@ ath11k_dp_rx_ppdu_stats_update_tx_comp_s +@@ -1942,7 +1942,7 @@ ath11k_dp_rx_ppdu_stats_update_tx_comp_s } sta = peer->sta; @@ -29,7 +29,7 @@ memset(&status, 0, sizeof(status)); -@@ -3000,8 +3000,7 @@ static void ath11k_dp_rx_h_mpdu(struct a +@@ -2984,8 +2984,7 @@ static void ath11k_dp_rx_h_mpdu(struct a msdu->protocol = eth_type_trans(msdu, msdu->dev); napi_gro_receive(rxcb->napi, msdu); if (peer->sta) @@ -39,7 +39,7 @@ return; } } -@@ -3752,7 +3751,7 @@ static void ath11k_dp_rx_update_user_sta +@@ -3736,7 +3735,7 @@ static void ath11k_dp_rx_update_user_sta return; } @@ -48,7 +48,7 @@ rx_stats = arsta->rx_stats; if (ar->ab->nss.enabled) -@@ -6445,7 +6444,7 @@ int ath11k_dp_rx_process_mon_status(stru +@@ -6429,7 +6428,7 @@ int ath11k_dp_rx_process_mon_status(stru if ((ppdu_info->fc_valid) && (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) { if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) { diff --git a/package/kernel/mac80211/patches/nss/ath11k/999-904-ath11k-nss-use-wrapper-to-avoid-cast.patch b/package/kernel/mac80211/patches/nss/ath11k/999-904-ath11k-nss-use-wrapper-to-avoid-cast.patch index b335d05d12..fea19f2910 100644 --- a/package/kernel/mac80211/patches/nss/ath11k/999-904-ath11k-nss-use-wrapper-to-avoid-cast.patch +++ b/package/kernel/mac80211/patches/nss/ath11k/999-904-ath11k-nss-use-wrapper-to-avoid-cast.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath11k/nss.c +++ b/drivers/net/wireless/ath/ath11k/nss.c -@@ -313,13 +313,14 @@ static void ath11k_nss_peer_mem_free(str +@@ -307,13 +307,14 @@ static void ath11k_nss_peer_mem_free(str /*-----------------------------Events/Callbacks------------------------------*/ @@ -16,7 +16,7 @@ if (!ab) return; -@@ -519,6 +520,17 @@ ath11k_nss_wifili_ext_callback_fn(struct +@@ -505,6 +506,17 @@ ath11k_nss_wifili_ext_callback_fn(struct } } @@ -34,7 +34,7 @@ void ath11k_nss_vdev_cfg_cb(void *app_data, struct nss_cmn_msg *msg) { struct ath11k_vif *arvif = (struct ath11k_vif *)app_data; -@@ -1431,7 +1443,7 @@ int ath11k_nss_mesh_exception_flags(stru +@@ -1360,7 +1372,7 @@ int ath11k_nss_mesh_exception_flags(stru nss_tx_status_t status; int ret = 0; @@ -43,7 +43,7 @@ status = (nss_tx_status_t)nss_wifi_meshmgr_mesh_path_exception(arvif->nss.mesh_handle, nss_msg, msg_cb, arvif->ar->ab); -@@ -1532,7 +1544,7 @@ static int ath11k_nss_mesh_mpath_add(str +@@ -1461,7 +1473,7 @@ static int ath11k_nss_mesh_mpath_add(str if (!msg) return -ENOMEM; @@ -52,7 +52,7 @@ ether_addr_copy(msg->dest_mac_addr, path->mesh_da); ether_addr_copy(msg->next_hop_mac_addr, path->next_hop); -@@ -1578,7 +1590,7 @@ static int ath11k_nss_mesh_mpath_update( +@@ -1507,7 +1519,7 @@ static int ath11k_nss_mesh_mpath_update( if (!msg) return -ENOMEM; @@ -61,7 +61,7 @@ ether_addr_copy(msg->dest_mac_addr, path->mesh_da); ether_addr_copy(msg->next_hop_mac_addr, path->next_hop); -@@ -1634,7 +1646,7 @@ static int ath11k_nss_mesh_mpath_del(str +@@ -1563,7 +1575,7 @@ static int ath11k_nss_mesh_mpath_del(str if (!msg) return -ENOMEM; @@ -70,7 +70,7 @@ ether_addr_copy(msg->mesh_dest_mac_addr, path->mesh_da); ether_addr_copy(msg->next_hop_mac_addr, path->next_hop); -@@ -1670,7 +1682,7 @@ static int ath11k_nss_mesh_mpp_add_cmd(s +@@ -1599,7 +1611,7 @@ static int ath11k_nss_mesh_mpp_add_cmd(s if (!msg) return -ENOMEM; @@ -79,7 +79,7 @@ ether_addr_copy(msg->dest_mac_addr, path->da); ether_addr_copy(msg->mesh_dest_mac, path->mesh_da); -@@ -1706,7 +1718,7 @@ static int ath11k_nss_mesh_mpp_update_cm +@@ -1635,7 +1647,7 @@ static int ath11k_nss_mesh_mpp_update_cm if (!msg) return -ENOMEM; @@ -88,7 +88,7 @@ ether_addr_copy(msg->dest_mac_addr, path->da); ether_addr_copy(msg->mesh_dest_mac, path->mesh_da); -@@ -1744,7 +1756,7 @@ static int ath11k_nss_mesh_mpp_del_cmd(s +@@ -1673,7 +1685,7 @@ static int ath11k_nss_mesh_mpp_del_cmd(s if (!msg) return -ENOMEM; @@ -97,7 +97,7 @@ ether_addr_copy(msg->dest_mac_addr, path->da); ether_addr_copy(msg->mesh_dest_mac_addr, path->mesh_da); -@@ -1933,7 +1945,7 @@ void ath11k_nss_mpp_timer_cb(struct time +@@ -1862,7 +1874,7 @@ void ath11k_nss_mpp_timer_cb(struct time LIST_HEAD(local_entry); nss_tx_status_t status; @@ -106,7 +106,7 @@ if (!arvif->nss.mpp_dump_req) arvif->nss.mpp_dump_num_entries = 0; -@@ -3067,7 +3079,7 @@ int ath11k_nss_ext_vdev_wds_4addr_allow( +@@ -2996,7 +3008,7 @@ int ath11k_nss_ext_vdev_wds_4addr_allow( cfg_4addr_msg->if_num = arvif->nss.if_num; cfg_4addr_msg->enable = true; @@ -115,7 +115,7 @@ nss_cmn_msg_init(&wlmsg->cm, ar->ab->nss.if_num, NSS_WIFILI_PEER_4ADDR_EVENT_MSG, -@@ -3467,7 +3479,7 @@ int ath11k_nss_set_peer_sec_type(struct +@@ -3396,7 +3408,7 @@ int ath11k_nss_set_peer_sec_type(struct memcpy(&sec_msg->mic_key[0], mic_key, NSS_WIFILI_MIC_KEY_LEN); } @@ -124,7 +124,7 @@ nss_cmn_msg_init(&wlmsg->cm, ar->ab->nss.if_num, NSS_WIFILI_PEER_SECURITY_TYPE_MSG, -@@ -3506,7 +3518,7 @@ int ath11k_nss_set_peer_authorize(struct +@@ -3435,7 +3447,7 @@ int ath11k_nss_set_peer_authorize(struct auth_msg->peer_id = peer_id; auth_msg->auth_flag = 1; @@ -133,16 +133,16 @@ nss_cmn_msg_init(&wlmsg->cm, ar->ab->nss.if_num, NSS_WIFILI_PEER_UPDATE_AUTH_FLAG, -@@ -3738,7 +3750,7 @@ int ath11k_nss_peer_delete(struct ath11k +@@ -3667,7 +3679,7 @@ int ath11k_nss_peer_delete(struct ath11k peer_msg->vdev_id = peer->vdev_id; peer_msg->peer_id = peer->peer_id; - msg_cb = (nss_wifili_msg_callback_t)ath11k_nss_wifili_event_receive; + msg_cb = ath11k_nss_wifili_event_receive; - nss_cmn_msg_init(&wlmsg->cm, ar->ab->nss.if_num, + nss_cmn_msg_init(&wlmsg->cm, ab->nss.if_num, NSS_WIFILI_PEER_DELETE_MSG, -@@ -3836,7 +3848,7 @@ int ath11k_nss_peer_create(struct ath11k +@@ -3765,7 +3777,7 @@ int ath11k_nss_peer_create(struct ath11k peer_msg->nss_peer_mem = peer->nss.paddr; peer_msg->psta_vdev_id = peer->vdev_id; @@ -151,7 +151,7 @@ nss_cmn_msg_init(&wlmsg->cm, ab->nss.if_num, NSS_WIFILI_PEER_CREATE_MSG, -@@ -3904,7 +3916,7 @@ int ath11k_nss_add_wds_peer(struct ath11 +@@ -3833,7 +3845,7 @@ int ath11k_nss_add_wds_peer(struct ath11 ether_addr_copy(wds_peer_msg->peer_mac, peer->addr); ether_addr_copy(wds_peer_msg->dest_mac, dest_mac); @@ -160,7 +160,7 @@ nss_cmn_msg_init(&wlmsg->cm, ab->nss.if_num, NSS_WIFILI_WDS_PEER_ADD_MSG, -@@ -3950,7 +3962,7 @@ int ath11k_nss_update_wds_peer(struct at +@@ -3879,7 +3891,7 @@ int ath11k_nss_update_wds_peer(struct at ether_addr_copy(wds_peer_msg->peer_mac, peer->addr); ether_addr_copy(wds_peer_msg->dest_mac, dest_mac); @@ -169,7 +169,7 @@ nss_cmn_msg_init(&wlmsg->cm, ab->nss.if_num, NSS_WIFILI_WDS_PEER_UPDATE_MSG, -@@ -4001,7 +4013,7 @@ int ath11k_nss_map_wds_peer(struct ath11 +@@ -3930,7 +3942,7 @@ int ath11k_nss_map_wds_peer(struct ath11 ether_addr_copy(wds_peer_map_msg->dest_mac, dest_mac); @@ -178,7 +178,7 @@ nss_cmn_msg_init(&wlmsg->cm, ab->nss.if_num, NSS_WIFILI_WDS_PEER_MAP_MSG, -@@ -4047,7 +4059,7 @@ int ath11k_nss_del_wds_peer(struct ath11 +@@ -3976,7 +3988,7 @@ int ath11k_nss_del_wds_peer(struct ath11 ether_addr_copy(wds_peer_msg->peer_mac, peer_addr); ether_addr_copy(wds_peer_msg->dest_mac, dest_mac); @@ -187,7 +187,7 @@ nss_cmn_msg_init(&wlmsg->cm, ab->nss.if_num, NSS_WIFILI_WDS_PEER_DEL_MSG, -@@ -4361,7 +4373,7 @@ static int ath11k_nss_mesh_capability(st +@@ -4290,7 +4302,7 @@ static int ath11k_nss_mesh_capability(st if (!wlmsg) return -ENOMEM; @@ -196,7 +196,7 @@ reinit_completion(&ab->nss.complete); -@@ -4478,7 +4490,7 @@ static int ath11k_nss_init(struct ath11k +@@ -4407,7 +4419,7 @@ static int ath11k_nss_init(struct ath11k /* register callbacks for events and exceptions with nss */ nss_contex = nss_register_wifili_if(ab->nss.if_num, NULL, @@ -205,7 +205,7 @@ (nss_wifili_msg_callback_t)ath11k_nss_wifili_event_receive, (struct net_device *)ab, features); -@@ -4497,7 +4509,7 @@ static int ath11k_nss_init(struct ath11k +@@ -4426,7 +4438,7 @@ static int ath11k_nss_init(struct ath11k */ ab->nss.ctx = nss_contex; @@ -214,7 +214,7 @@ /* Initialize the common part of the wlmsg */ nss_cmn_msg_init(&wlmsg->cm, ab->nss.if_num, -@@ -4569,7 +4581,7 @@ static int ath11k_nss_stats_cfg(struct a +@@ -4497,7 +4509,7 @@ static int ath11k_nss_stats_cfg(struct a stats_cfg = &wlmsg->msg.scm; stats_cfg->cfg = enable; @@ -223,7 +223,7 @@ nss_cmn_msg_init(&wlmsg->cm, ab->nss.if_num, nss_msg, -@@ -4679,7 +4691,7 @@ int ath11k_nss_pdev_init(struct ath11k_b +@@ -4606,7 +4618,7 @@ int ath11k_nss_pdev_init(struct ath11k_b refill_ring_id = ar->dp.rx_refill_buf_ring.refill_buf_ring.ring_id; ath11k_nss_fill_srng_info(ab, refill_ring_id, &pdevmsg->rxdma_ring); @@ -232,7 +232,7 @@ nss_cmn_msg_init(&wlmsg->cm, ab->nss.if_num, NSS_WIFILI_PDEV_INIT_MSG, -@@ -4753,7 +4765,7 @@ int ath11k_nss_start(struct ath11k_base +@@ -4680,7 +4692,7 @@ int ath11k_nss_start(struct ath11k_base if (!wlmsg) return -ENOMEM; @@ -241,7 +241,7 @@ /* Empty message for NSS Start message */ nss_cmn_msg_init(&wlmsg->cm, ab->nss.if_num, -@@ -4811,7 +4823,7 @@ static void ath11k_nss_reset(struct ath1 +@@ -4738,7 +4750,7 @@ static void ath11k_nss_reset(struct ath1 return; } @@ -250,7 +250,7 @@ /* Empty message for NSS Reset message */ nss_cmn_msg_init(&wlmsg->cm, ab->nss.if_num, -@@ -4864,7 +4876,7 @@ static int ath11k_nss_stop(struct ath11k +@@ -4791,7 +4803,7 @@ static int ath11k_nss_stop(struct ath11k if (!wlmsg) return -ENOMEM; @@ -259,7 +259,7 @@ /* Empty message for Stop command */ nss_cmn_msg_init(&wlmsg->cm, ab->nss.if_num, -@@ -4931,7 +4943,7 @@ int ath11k_nss_pdev_deinit(struct ath11k +@@ -4858,7 +4870,7 @@ int ath11k_nss_pdev_deinit(struct ath11k deinit = &wlmsg->msg.pdevdeinit; deinit->ifnum = radio_id; diff --git a/package/kernel/mac80211/patches/nss/ath11k/999-907-ath11k-Enable-NSS-for-ipq5018-qcn6122.patch b/package/kernel/mac80211/patches/nss/ath11k/999-907-ath11k-Enable-NSS-for-ipq5018-qcn6122.patch index 1677fc85c1..141dd7bb02 100644 --- a/package/kernel/mac80211/patches/nss/ath11k/999-907-ath11k-Enable-NSS-for-ipq5018-qcn6122.patch +++ b/package/kernel/mac80211/patches/nss/ath11k/999-907-ath11k-Enable-NSS-for-ipq5018-qcn6122.patch @@ -37,7 +37,7 @@ ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, --- a/drivers/net/wireless/ath/ath11k/nss.c +++ b/drivers/net/wireless/ath/ath11k/nss.c -@@ -4324,6 +4324,8 @@ static int ath11k_nss_get_target_type(st +@@ -4253,6 +4253,8 @@ static int ath11k_nss_get_target_type(st return ATH11K_WIFILI_TARGET_TYPE_QCN9074; case ATH11K_HW_IPQ5018_HW10: return ATH11K_WIFILI_TARGET_TYPE_QCA5018; @@ -46,7 +46,7 @@ default: ath11k_warn(ab, "NSS Offload not supported for this HW\n"); return ATH11K_WIFILI_TARGET_TYPE_UNKNOWN; -@@ -4338,6 +4340,7 @@ static int ath11k_nss_get_interface_type +@@ -4267,6 +4269,7 @@ static int ath11k_nss_get_interface_type case ATH11K_HW_IPQ5018_HW10: return NSS_WIFILI_INTERNAL_INTERFACE; case ATH11K_HW_QCN9074_HW10: diff --git a/package/kernel/mac80211/patches/nss/ath11k/999-920-ath11k-add-kernel-6_12.patch b/package/kernel/mac80211/patches/nss/ath11k/999-920-ath11k-add-kernel-6_12.patch index 2050eaf844..76e8ebf4ef 100644 --- a/package/kernel/mac80211/patches/nss/ath11k/999-920-ath11k-add-kernel-6_12.patch +++ b/package/kernel/mac80211/patches/nss/ath11k/999-920-ath11k-add-kernel-6_12.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath11k/core.c +++ b/drivers/net/wireless/ath/ath11k/core.c -@@ -2428,13 +2428,13 @@ err_sc_free: +@@ -2431,13 +2431,13 @@ err_sc_free: } EXPORT_SYMBOL(ath11k_core_alloc); @@ -18,7 +18,7 @@ } --- a/drivers/net/wireless/ath/ath11k/dp_rx.c +++ b/drivers/net/wireless/ath/ath11k/dp_rx.c -@@ -1823,7 +1823,7 @@ struct htt_ppdu_stats_info *ath11k_dp_ht +@@ -1824,7 +1824,7 @@ struct htt_ppdu_stats_info *ath11k_dp_ht return ppdu_info; } @@ -27,7 +27,7 @@ struct htt_ppdu_user_stats* usr_stats) { peer->ppdu_stats_delayba.reserved0 = usr_stats->rate.reserved0; -@@ -1838,7 +1838,7 @@ void ath11k_copy_to_delay_stats(struct a +@@ -1839,7 +1839,7 @@ void ath11k_copy_to_delay_stats(struct a peer->delayba_flag = true; } @@ -36,7 +36,7 @@ struct htt_ppdu_user_stats* usr_stats) { usr_stats->rate.reserved0 = peer->ppdu_stats_delayba.reserved0; -@@ -6305,7 +6305,7 @@ static void ath11k_dp_rx_mon_dest_proces +@@ -6289,7 +6289,7 @@ static void ath11k_dp_rx_mon_dest_proces } } @@ -58,7 +58,7 @@ int i; --- a/drivers/net/wireless/ath/ath11k/nss.c +++ b/drivers/net/wireless/ath/ath11k/nss.c -@@ -313,7 +313,7 @@ static void ath11k_nss_peer_mem_free(str +@@ -307,7 +307,7 @@ static void ath11k_nss_peer_mem_free(str /*-----------------------------Events/Callbacks------------------------------*/ @@ -67,7 +67,7 @@ { u32 msg_type = msg->cm.type; enum nss_cmn_response response = msg->cm.response; -@@ -424,7 +424,7 @@ void ath11k_nss_wifili_event_receive(voi +@@ -418,7 +418,7 @@ void ath11k_nss_wifili_event_receive(voi } } @@ -75,8 +75,8 @@ +static void ath11k_nss_process_mic_error(struct ath11k_base *ab, struct sk_buff *skb) { struct ath11k_vif *arvif; - struct ath11k *ar; -@@ -531,7 +531,7 @@ static inline void ath11k_nss_wifili_ext + struct ath11k_peer *peer = NULL; +@@ -517,7 +517,7 @@ static inline void ath11k_nss_wifili_ext ath11k_nss_wifili_ext_callback_fn(ab, skb, napi); } @@ -85,7 +85,7 @@ { struct ath11k_vif *arvif = (struct ath11k_vif *)app_data; -@@ -1075,7 +1075,7 @@ ath11k_nss_ext_vdev_data_receive(struct +@@ -1004,7 +1004,7 @@ ath11k_nss_ext_vdev_data_receive(struct #ifdef CPTCFG_ATH11K_NSS_MESH_SUPPORT /*------Mesh offload------*/ @@ -94,7 +94,7 @@ struct nss_cmn_msg *cmn_msg) { struct nss_wifi_mesh_msg *msg = (struct nss_wifi_mesh_msg *)cmn_msg; -@@ -1936,7 +1936,7 @@ int ath11k_nss_dump_mpp_request(struct a +@@ -1865,7 +1865,7 @@ int ath11k_nss_dump_mpp_request(struct a return 0; } @@ -103,7 +103,7 @@ { nss_wifi_mesh_msg_callback_t msg_cb; struct arvif_nss *nss = from_timer(nss, timer,mpp_expiry_timer); -@@ -2607,7 +2607,7 @@ static void ath11k_nss_mesh_vdev_free(st +@@ -2536,7 +2536,7 @@ static void ath11k_nss_mesh_vdev_free(st } #endif @@ -112,7 +112,7 @@ { struct ath11k_base *ab = arvif->ar->ab; nss_tx_status_t status; -@@ -2639,7 +2639,7 @@ void ath11k_nss_vdev_free(struct ath11k_ +@@ -2568,7 +2568,7 @@ void ath11k_nss_vdev_free(struct ath11k_ } #ifdef CPTCFG_ATH11K_NSS_MESH_SUPPORT @@ -121,7 +121,7 @@ { struct arvif_nss *nss; -@@ -4624,7 +4624,7 @@ void ath11k_nss_peer_stats_enable(struct +@@ -4552,7 +4552,7 @@ void ath11k_nss_peer_stats_enable(struct ATH11K_NSS_STATS_ENABLE); } @@ -130,7 +130,7 @@ { struct ath11k *ar = ab->pdevs[radio_id].ar; struct nss_wifili_pdev_init_msg *pdevmsg; -@@ -4757,7 +4757,7 @@ dealloc: +@@ -4684,7 +4684,7 @@ dealloc: /* TODO : Check if start, reset and stop messages can be done using single function as * body is similar, having it now for clarity */ @@ -139,7 +139,7 @@ { struct nss_wifili_msg *wlmsg = NULL; nss_wifili_msg_callback_t msg_cb; -@@ -4922,7 +4922,7 @@ free: +@@ -4849,7 +4849,7 @@ free: return ret; } diff --git a/package/kernel/mac80211/patches/nss/subsys/657-mac80211-Avoid-encapsulation-of-EAPOL-frames-if-OFFL.patch b/package/kernel/mac80211/patches/nss/subsys/657-mac80211-Avoid-encapsulation-of-EAPOL-frames-if-OFFL.patch index 080634bcf7..37bab87471 100644 --- a/package/kernel/mac80211/patches/nss/subsys/657-mac80211-Avoid-encapsulation-of-EAPOL-frames-if-OFFL.patch +++ b/package/kernel/mac80211/patches/nss/subsys/657-mac80211-Avoid-encapsulation-of-EAPOL-frames-if-OFFL.patch @@ -20,7 +20,7 @@ Signed-off-by: Aaradhana Sahu --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h -@@ -2081,6 +2081,11 @@ netdev_tx_t ieee80211_subif_start_xmit(s +@@ -2088,6 +2088,11 @@ netdev_tx_t ieee80211_subif_start_xmit(s struct net_device *dev); netdev_tx_t ieee80211_subif_start_xmit_8023(struct sk_buff *skb, struct net_device *dev); diff --git a/package/kernel/mac80211/patches/nss/subsys/785-wifi-mac80211-Add-mac-hw-flag-to-avoid-queue-skb.patch b/package/kernel/mac80211/patches/nss/subsys/785-wifi-mac80211-Add-mac-hw-flag-to-avoid-queue-skb.patch index cc58c55a57..f185ded166 100644 --- a/package/kernel/mac80211/patches/nss/subsys/785-wifi-mac80211-Add-mac-hw-flag-to-avoid-queue-skb.patch +++ b/package/kernel/mac80211/patches/nss/subsys/785-wifi-mac80211-Add-mac-hw-flag-to-avoid-queue-skb.patch @@ -123,7 +123,7 @@ Signed-off-by: Yuvasree Sivasankaran * for MLO STA, the SA should be the AP MLD address, but --- a/net/mac80211/cfg.c +++ b/net/mac80211/cfg.c -@@ -4601,6 +4601,9 @@ static int ieee80211_get_txq_stats(struc +@@ -4622,6 +4622,9 @@ static int ieee80211_get_txq_stats(struc struct ieee80211_sub_if_data *sdata; int ret = 0; diff --git a/package/kernel/mac80211/patches/subsys/350-mac80211-allow-scanning-while-on-radar-channel.patch b/package/kernel/mac80211/patches/subsys/350-mac80211-allow-scanning-while-on-radar-channel.patch new file mode 100644 index 0000000000..d469955a90 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/350-mac80211-allow-scanning-while-on-radar-channel.patch @@ -0,0 +1,372 @@ +--- a/net/mac80211/cfg.c ++++ b/net/mac80211/cfg.c +@@ -3473,6 +3473,27 @@ static int ieee80211_set_bitrate_mask(st + return 0; + } + ++bool ieee80211_scanning_busy(struct ieee80211_local *local, ++ struct cfg80211_chan_def *chandef) ++{ ++ struct cfg80211_scan_request *scan_req; ++ struct wiphy *wiphy = local->hw.wiphy; ++ u32 mask; ++ ++ if (list_empty(&local->roc_list) && !local->scanning) ++ return false; ++ ++ if (!wiphy->n_radio) ++ return true; ++ ++ mask = ieee80211_offchannel_radio_mask(local); ++ scan_req = wiphy_dereference(wiphy, local->scan_req); ++ if (scan_req) ++ mask |= ieee80211_scan_req_radio_mask(local, scan_req); ++ ++ return mask & ieee80211_chandef_radio_mask(local, chandef); ++} ++ + static int ieee80211_start_radar_detection(struct wiphy *wiphy, + struct net_device *dev, + struct cfg80211_chan_def *chandef, +@@ -3486,7 +3507,7 @@ static int ieee80211_start_radar_detecti + + lockdep_assert_wiphy(local->hw.wiphy); + +- if (!list_empty(&local->roc_list) || local->scanning) ++ if (ieee80211_scanning_busy(local, chandef)) + return -EBUSY; + + link_data = sdata_dereference(sdata->link[link_id], sdata); +@@ -3978,7 +3999,7 @@ __ieee80211_channel_switch(struct wiphy + + lockdep_assert_wiphy(local->hw.wiphy); + +- if (!list_empty(&local->roc_list) || local->scanning) ++ if (ieee80211_scanning_busy(local, ¶ms->chandef)) + return -EBUSY; + + if (sdata->wdev.links[link_id].cac_started) +--- a/net/mac80211/chan.c ++++ b/net/mac80211/chan.c +@@ -629,14 +629,24 @@ ieee80211_find_chanctx(struct ieee80211_ + return NULL; + } + +-bool ieee80211_is_radar_required(struct ieee80211_local *local) ++bool ieee80211_is_radar_required(struct ieee80211_local *local, u32 radio_mask) + { ++ struct ieee80211_chanctx_conf *conf; + struct ieee80211_link_data *link; + + lockdep_assert_wiphy(local->hw.wiphy); + + for_each_sdata_link(local, link) { +- if (link->radar_required) ++ if (!link->radar_required) ++ continue; ++ if (!local->hw.wiphy->n_radio) ++ return true; ++ ++ conf = wiphy_dereference(local->hw.wiphy, link->conf->chanctx_conf); ++ if (!conf) ++ continue; ++ ++ if (conf->radio_idx >= 0 && (radio_mask & BIT(conf->radio_idx))) + return true; + } + +--- a/net/mac80211/ieee80211_i.h ++++ b/net/mac80211/ieee80211_i.h +@@ -1947,6 +1947,12 @@ int ieee80211_mesh_finish_csa(struct iee + u64 *changed); + + /* scan/BSS handling */ ++u32 ieee80211_scan_req_radio_mask(struct ieee80211_local *local, ++ struct cfg80211_scan_request *req); ++bool ieee80211_scanning_busy(struct ieee80211_local *local, ++ struct cfg80211_chan_def *chandef); ++u32 ieee80211_can_leave_ch(struct ieee80211_sub_if_data *sdata, ++ u32 radio_mask); + void ieee80211_scan_work(struct wiphy *wiphy, struct wiphy_work *work); + int ieee80211_request_ibss_scan(struct ieee80211_sub_if_data *sdata, + const u8 *ssid, u8 ssid_len, +@@ -1985,6 +1991,7 @@ void ieee80211_sched_scan_stopped_work(s + /* off-channel/mgmt-tx */ + void ieee80211_offchannel_stop_vifs(struct ieee80211_local *local); + void ieee80211_offchannel_return(struct ieee80211_local *local); ++u32 ieee80211_offchannel_radio_mask(struct ieee80211_local *local); + void ieee80211_roc_setup(struct ieee80211_local *local); + void ieee80211_start_next_roc(struct ieee80211_local *local); + void ieee80211_reconfig_roc(struct ieee80211_local *local); +@@ -2629,6 +2636,8 @@ bool ieee80211_chandef_s1g_oper(const st + struct cfg80211_chan_def *chandef); + void ieee80211_chandef_downgrade(struct cfg80211_chan_def *chandef, + struct ieee80211_conn_settings *conn); ++u32 ieee80211_chandef_radio_mask(struct ieee80211_local *local, ++ struct cfg80211_chan_def *chandef); + static inline void + ieee80211_chanreq_downgrade(struct ieee80211_chan_req *chanreq, + struct ieee80211_conn_settings *conn) +@@ -2685,7 +2694,7 @@ void ieee80211_recalc_chanctx_min_def(st + struct ieee80211_chanctx *ctx, + struct ieee80211_link_data *rsvd_for, + bool check_reserved); +-bool ieee80211_is_radar_required(struct ieee80211_local *local); ++bool ieee80211_is_radar_required(struct ieee80211_local *local, u32 radio_mask); + + void ieee80211_dfs_cac_timer_work(struct wiphy *wiphy, struct wiphy_work *work); + void ieee80211_dfs_cac_cancel(struct ieee80211_local *local, +--- a/net/mac80211/offchannel.c ++++ b/net/mac80211/offchannel.c +@@ -168,6 +168,35 @@ void ieee80211_offchannel_return(struct + false); + } + ++u32 ieee80211_offchannel_radio_mask(struct ieee80211_local *local) ++{ ++ const struct wiphy_radio *radio; ++ struct ieee80211_roc_work *roc; ++ u32 mask = 0; ++ int r; ++ ++ for (r = 0; r < local->hw.wiphy->n_radio; r++) { ++ radio = &local->hw.wiphy->radio[r]; ++ ++ list_for_each_entry(roc, &local->roc_list, list) { ++ struct cfg80211_chan_def chandef = {}; ++ ++ if (!roc->started) ++ continue; ++ ++ cfg80211_chandef_create(&chandef, roc->chan, ++ NL80211_CHAN_NO_HT); ++ if (!cfg80211_radio_chandef_valid(radio, &chandef)) ++ continue; ++ ++ mask |= BIT(r); ++ break; ++ } ++ } ++ ++ return mask; ++} ++ + static void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc) + { + /* was never transmitted */ +@@ -566,7 +595,9 @@ static int ieee80211_start_roc_work(stru + enum ieee80211_roc_type type) + { + struct ieee80211_roc_work *roc, *tmp; ++ struct cfg80211_chan_def chandef = {}; + bool queued = false, combine_started = true; ++ u32 radio_mask; + int ret; + + lockdep_assert_wiphy(local->hw.wiphy); +@@ -578,6 +609,12 @@ static int ieee80211_start_roc_work(stru + if (!local->emulate_chanctx && !local->ops->remain_on_channel) + return -EOPNOTSUPP; + ++ cfg80211_chandef_create(&chandef, channel, NL80211_CHAN_NO_HT); ++ radio_mask = ieee80211_chandef_radio_mask(local, &chandef); ++ if (!ieee80211_can_leave_ch(sdata, radio_mask) && ++ !ieee80211_scanning_busy(local, &chandef)) ++ return -EBUSY; ++ + roc = kzalloc(sizeof(*roc), GFP_KERNEL); + if (!roc) + return -ENOMEM; +@@ -613,8 +650,7 @@ static int ieee80211_start_roc_work(stru + } + + /* if there's no need to queue, handle it immediately */ +- if (list_empty(&local->roc_list) && +- !local->scanning && !ieee80211_is_radar_required(local)) { ++ if (list_empty(&local->roc_list) && !local->scanning) { + /* if not HW assist, just queue & schedule work */ + if (!local->ops->remain_on_channel) { + list_add_tail(&roc->list, &local->roc_list); +--- a/net/mac80211/scan.c ++++ b/net/mac80211/scan.c +@@ -571,36 +571,83 @@ static int ieee80211_start_sw_scan(struc + return 0; + } + +-static bool __ieee80211_can_leave_ch(struct ieee80211_sub_if_data *sdata) ++u32 ieee80211_scan_req_radio_mask(struct ieee80211_local *local, ++ struct cfg80211_scan_request *req) ++{ ++ const struct wiphy_radio *radio; ++ u32 mask = 0; ++ int i, r; ++ ++ for (r = 0; r < local->hw.wiphy->n_radio; r++) { ++ radio = &local->hw.wiphy->radio[r]; ++ ++ for (i = 0; i < req->n_channels; i++) { ++ struct cfg80211_chan_def chandef = {}; ++ ++ chandef.chan = req->channels[i]; ++ cfg80211_chandef_create(&chandef, req->channels[i], ++ NL80211_CHAN_NO_HT); ++ if (!cfg80211_radio_chandef_valid(radio, &chandef)) ++ continue; ++ ++ mask |= BIT(r); ++ break; ++ } ++ } ++ ++ return mask; ++} ++ ++u32 ieee80211_can_leave_ch(struct ieee80211_sub_if_data *sdata, ++ u32 radio_mask) + { + struct ieee80211_local *local = sdata->local; + struct ieee80211_sub_if_data *sdata_iter; ++ struct wiphy *wiphy = local->hw.wiphy; ++ struct ieee80211_chanctx_conf *conf; ++ struct ieee80211_link_data *link; + unsigned int link_id; + + lockdep_assert_wiphy(local->hw.wiphy); + +- if (!ieee80211_is_radar_required(local)) ++ if (!ieee80211_is_radar_required(local, radio_mask)) + return true; + + if (!regulatory_pre_cac_allowed(local->hw.wiphy)) + return false; + + list_for_each_entry(sdata_iter, &local->interfaces, list) { +- for_each_valid_link(&sdata_iter->wdev, link_id) +- if (sdata_iter->wdev.links[link_id].cac_started) ++ for_each_valid_link(&sdata_iter->wdev, link_id) { ++ if (!sdata_iter->wdev.links[link_id].cac_started) ++ continue; ++ ++ if (!wiphy->n_radio) + return false; ++ ++ link = sdata_dereference(sdata->link[link_id], sdata); ++ if (!link) ++ continue; ++ ++ conf = wiphy_dereference(wiphy, link->conf->chanctx_conf); ++ if (!conf) ++ continue; ++ ++ if (conf->radio_idx >= 0 && ++ (radio_mask & BIT(conf->radio_idx))) ++ return false; ++ } + } + + return true; + } + + static bool ieee80211_can_scan(struct ieee80211_local *local, +- struct ieee80211_sub_if_data *sdata) ++ struct ieee80211_sub_if_data *sdata, ++ u32 radio_mask) + { +- if (!__ieee80211_can_leave_ch(sdata)) +- return false; +- +- if (!list_empty(&local->roc_list)) ++ if (!list_empty(&local->roc_list) && ++ (!local->hw.wiphy->n_radio || ++ (radio_mask & ieee80211_offchannel_radio_mask(local)))) + return false; + + if (sdata->vif.type == NL80211_IFTYPE_STATION && +@@ -612,15 +659,22 @@ static bool ieee80211_can_scan(struct ie + + void ieee80211_run_deferred_scan(struct ieee80211_local *local) + { ++ struct ieee80211_sub_if_data *sdata; ++ struct cfg80211_scan_request *req; ++ u32 radio_mask; ++ + lockdep_assert_wiphy(local->hw.wiphy); + +- if (!local->scan_req || local->scanning) ++ req = wiphy_dereference(local->hw.wiphy, local->scan_req); ++ if (!req || local->scanning) ++ return; ++ ++ radio_mask = ieee80211_scan_req_radio_mask(local, req); ++ sdata = wiphy_dereference(local->hw.wiphy, local->scan_sdata); ++ if (!ieee80211_can_leave_ch(sdata, radio_mask)) + return; + +- if (!ieee80211_can_scan(local, +- rcu_dereference_protected( +- local->scan_sdata, +- lockdep_is_held(&local->hw.wiphy->mtx)))) ++ if (!ieee80211_can_scan(local, sdata, radio_mask)) + return; + + wiphy_delayed_work_queue(local->hw.wiphy, &local->scan_work, +@@ -703,6 +757,7 @@ static int __ieee80211_start_scan(struct + { + struct ieee80211_local *local = sdata->local; + bool hw_scan = local->ops->hw_scan; ++ u32 radio_mask; + int rc; + + lockdep_assert_wiphy(local->hw.wiphy); +@@ -717,10 +772,11 @@ static int __ieee80211_start_scan(struct + !(sdata->vif.active_links & BIT(req->tsf_report_link_id))) + return -EINVAL; + +- if (!__ieee80211_can_leave_ch(sdata)) ++ radio_mask = ieee80211_scan_req_radio_mask(local, req); ++ if (!ieee80211_can_leave_ch(sdata, radio_mask)) + return -EBUSY; + +- if (!ieee80211_can_scan(local, sdata)) { ++ if (!ieee80211_can_scan(local, sdata, radio_mask)) { + /* wait for the work to finish/time out */ + rcu_assign_pointer(local->scan_req, req); + rcu_assign_pointer(local->scan_sdata, sdata); +--- a/net/mac80211/util.c ++++ b/net/mac80211/util.c +@@ -3644,6 +3644,23 @@ again: + WARN_ON_ONCE(!cfg80211_chandef_valid(c)); + } + ++u32 ieee80211_chandef_radio_mask(struct ieee80211_local *local, ++ struct cfg80211_chan_def *chandef) ++{ ++ struct wiphy *wiphy = local->hw.wiphy; ++ const struct wiphy_radio *radio; ++ u32 mask = 0; ++ int i; ++ ++ for (i = 0; i < wiphy->n_radio; i++) { ++ radio = &wiphy->radio[i]; ++ if (cfg80211_radio_chandef_valid(radio, chandef)) ++ mask |= BIT(i); ++ } ++ ++ return mask; ++} ++ + /* + * Returns true if smps_mode_new is strictly more restrictive than + * smps_mode_old. +--- a/net/wireless/util.c ++++ b/net/wireless/util.c +@@ -2911,6 +2911,9 @@ bool cfg80211_radio_chandef_valid(const + { + u32 freq, width; + ++ if (!cfg80211_chandef_valid(chandef)) ++ return false; ++ + freq = ieee80211_chandef_to_khz(chandef); + width = nl80211_chan_width_to_mhz(chandef->width); + if (!ieee80211_radio_freq_range_valid(radio, freq, width)) diff --git a/package/network/config/wifi-scripts/files-ucode/lib/netifd/wireless/mac80211.sh b/package/network/config/wifi-scripts/files-ucode/lib/netifd/wireless/mac80211.sh index 9b86abcee5..b658b26a7c 100755 --- a/package/network/config/wifi-scripts/files-ucode/lib/netifd/wireless/mac80211.sh +++ b/package/network/config/wifi-scripts/files-ucode/lib/netifd/wireless/mac80211.sh @@ -283,7 +283,7 @@ function setup() { idx[mode] ??= 0; let mode_idx = idx[mode]++; - if (!v.config.ifname) + if (!v.config.ifname) v.config.ifname = data.ifname_prefix + mode + mode_idx; push(active_ifnames, v.config.ifname); diff --git a/package/network/config/wifi-scripts/files-ucode/usr/share/ucode/wifi/hostapd.uc b/package/network/config/wifi-scripts/files-ucode/usr/share/ucode/wifi/hostapd.uc index 223f84f7d7..848f02d323 100644 --- a/package/network/config/wifi-scripts/files-ucode/usr/share/ucode/wifi/hostapd.uc +++ b/package/network/config/wifi-scripts/files-ucode/usr/share/ucode/wifi/hostapd.uc @@ -272,7 +272,7 @@ function device_htmode_append(config) { ]; for (let k, v in eht_center_seg0_map) - if (v[0] <= config.channel) { + if (config.channel <= v[0]) { config.eht_oper_centr_freq_seg0_idx = v[1]; break; } diff --git a/package/network/ipv6/6in4/files/6in4.sh b/package/network/ipv6/6in4/files/6in4.sh index dd055ecb63..0f76c94672 100755 --- a/package/network/ipv6/6in4/files/6in4.sh +++ b/package/network/ipv6/6in4/files/6in4.sh @@ -128,7 +128,7 @@ proto_6in4_setup() { } local url="$http://ipv4.tunnelbroker.net/nic/update?hostname=$tunnelid" - + test_6in4_rfc1918 "$ipaddr" && { local url="${url}&myip=${ipaddr}" } diff --git a/package/network/services/dnsmasq/files/dnsmasq.init b/package/network/services/dnsmasq/files/dnsmasq.init index 058f7a9fce..1e4cd902b7 100755 --- a/package/network/services/dnsmasq/files/dnsmasq.init +++ b/package/network/services/dnsmasq/files/dnsmasq.init @@ -597,10 +597,20 @@ dhcp_add() { nettag="${networkid:+set:${networkid},}" # make sure the DHCP range is not empty - if [ "$dhcpv4" != "disabled" ] && ipcalc "$ipaddr/$prefix_or_netmask" "$start" "$limit" ; then - [ "$dynamicdhcpv4" = "0" ] && END="static" + if [ "$dhcpv4" != "disabled" ]; then + unset START + unset END + unset NETMASK + ipcalc "$ipaddr/$prefix_or_netmask" "$start" "$limit" - xappend "--dhcp-range=$tags$nettag$START,$END,$NETMASK,$leasetime${options:+ $options}" + if [ -z "$START" ] || [ -z "$END" ] || [ -z "$NETMASK" ]; then + logger -t dnsmasq \ + "unable to set dhcp-range for dhcp uci config section '$cfg'" \ + "on interface '$ifname', please check your config" + else + [ "$dynamicdhcpv4" = "0" ] && END="static" + xappend "--dhcp-range=$tags$nettag$START,$END,$NETMASK,$leasetime${options:+ $options}" + fi fi if [ "$dynamicdhcpv6" = "0" ] ; then diff --git a/package/network/services/hostapd/Makefile b/package/network/services/hostapd/Makefile index 2e04540675..62c0a1952f 100644 --- a/package/network/services/hostapd/Makefile +++ b/package/network/services/hostapd/Makefile @@ -9,9 +9,9 @@ PKG_RELEASE:=2 PKG_SOURCE_URL:=https://w1.fi/hostap.git PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2025-02-09 -PKG_SOURCE_VERSION:=c8c7d56a3d3c4ca79bcbb6a87f372ce4bc2e9f11 -PKG_MIRROR_HASH:=fafdef456a545bd1de0cbd7b68b520e5be7e70ad1aab7ef051b1fc5ccaaa012a +PKG_SOURCE_DATE:=2025-05-23 +PKG_SOURCE_VERSION:=4b8ac10cb77c3d4dbf7ccefbe697dc0578da374c +PKG_MIRROR_HASH:=25a77ae4b26adef9c0d71c3b175445f246a4530e63563e81b8e19c2436934100 PKG_MAINTAINER:=Felix Fietkau PKG_LICENSE:=BSD-3-Clause diff --git a/package/network/services/hostapd/patches/010-mesh-Allow-DFS-channels-to-be-selected-if-dfs-is-ena.patch b/package/network/services/hostapd/patches/010-mesh-Allow-DFS-channels-to-be-selected-if-dfs-is-ena.patch index 9eef846f82..fc54e9d785 100644 --- a/package/network/services/hostapd/patches/010-mesh-Allow-DFS-channels-to-be-selected-if-dfs-is-ena.patch +++ b/package/network/services/hostapd/patches/010-mesh-Allow-DFS-channels-to-be-selected-if-dfs-is-ena.patch @@ -14,7 +14,7 @@ Signed-off-by: Peter Oh --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -2972,7 +2972,7 @@ static int drv_supports_vht(struct wpa_s +@@ -2963,7 +2963,7 @@ static int drv_supports_vht(struct wpa_s } @@ -23,7 +23,7 @@ Signed-off-by: Peter Oh { int i; -@@ -2981,7 +2981,10 @@ static bool ibss_mesh_is_80mhz_avail(int +@@ -2972,7 +2972,10 @@ static bool ibss_mesh_is_80mhz_avail(int chan = hw_get_channel_chan(mode, i, NULL); if (!chan || @@ -35,42 +35,44 @@ Signed-off-by: Peter Oh return false; } -@@ -3108,7 +3111,7 @@ static void ibss_mesh_select_40mhz(struc +@@ -3099,7 +3102,7 @@ static void ibss_mesh_select_40mhz(struc const struct wpa_ssid *ssid, struct hostapd_hw_modes *mode, struct hostapd_freq_params *freq, -- int obss_scan) { -+ int obss_scan, bool dfs_enabled) { +- int obss_scan, bool is_6ghz) ++ int obss_scan, bool is_6ghz, bool dfs_enabled) + { int chan_idx; struct hostapd_channel_data *pri_chan = NULL, *sec_chan = NULL; - int i, res; -@@ -3132,8 +3135,11 @@ static void ibss_mesh_select_40mhz(struc +@@ -3130,8 +3133,11 @@ static void ibss_mesh_select_40mhz(struc return; /* Check primary channel flags */ - if (pri_chan->flag & (HOSTAPD_CHAN_DISABLED | HOSTAPD_CHAN_NO_IR)) +- return; + if (pri_chan->flag & HOSTAPD_CHAN_DISABLED) - return; ++ return; + if (pri_chan->flag & (HOSTAPD_CHAN_RADAR | HOSTAPD_CHAN_NO_IR)) + if (!dfs_enabled) + return; #ifdef CONFIG_HT_OVERRIDES if (ssid->disable_ht40) -@@ -3159,8 +3165,11 @@ static void ibss_mesh_select_40mhz(struc +@@ -3166,8 +3172,11 @@ static void ibss_mesh_select_40mhz(struc return; /* Check secondary channel flags */ - if (sec_chan->flag & (HOSTAPD_CHAN_DISABLED | HOSTAPD_CHAN_NO_IR)) +- return; + if (sec_chan->flag & HOSTAPD_CHAN_DISABLED) - return; ++ return; + if (sec_chan->flag & (HOSTAPD_CHAN_RADAR | HOSTAPD_CHAN_NO_IR)) + if (!dfs_enabled) + return; - if (ht40 == -1) { - if (!(pri_chan->flag & HOSTAPD_CHAN_HT40MINUS)) -@@ -3236,7 +3245,7 @@ static bool ibss_mesh_select_80_160mhz(s + if (freq->ht_enabled) { + if (ht40 == -1) { +@@ -3245,7 +3254,7 @@ static bool ibss_mesh_select_80_160mhz(s const struct wpa_ssid *ssid, struct hostapd_hw_modes *mode, struct hostapd_freq_params *freq, @@ -79,7 +81,7 @@ Signed-off-by: Peter Oh static const int bw80[] = { 5180, 5260, 5500, 5580, 5660, 5745, 5825, 5955, 6035, 6115, 6195, 6275, 6355, 6435, -@@ -3286,7 +3295,7 @@ static bool ibss_mesh_select_80_160mhz(s +@@ -3298,7 +3307,7 @@ static bool ibss_mesh_select_80_160mhz(s goto skip_80mhz; /* Use 40 MHz if channel not usable */ @@ -88,37 +90,40 @@ Signed-off-by: Peter Oh goto skip_80mhz; chwidth = CONF_OPER_CHWIDTH_80MHZ; -@@ -3300,7 +3309,7 @@ static bool ibss_mesh_select_80_160mhz(s - if ((mode->he_capab[ieee80211_mode].phy_cap[ - HE_PHYCAP_CHANNEL_WIDTH_SET_IDX] & - HE_PHYCAP_CHANNEL_WIDTH_SET_160MHZ_IN_5G) && is_6ghz && -- ibss_mesh_is_80mhz_avail(channel + 16, mode)) { -+ ibss_mesh_is_80mhz_avail(channel + 16, mode, dfs_enabled)) { +@@ -3340,7 +3349,7 @@ static bool ibss_mesh_select_80_160mhz(s + HE_PHYCAP_CHANNEL_WIDTH_SET_160MHZ_IN_5G) && + (ssid->max_oper_chwidth == CONF_OPER_CHWIDTH_160MHZ || + ssid->max_oper_chwidth == CONF_OPER_CHWIDTH_320MHZ) && +- ibss_mesh_is_80mhz_avail(channel + 16 * offset_in_160, mode)) { ++ ibss_mesh_is_80mhz_avail(channel + 16 * offset_in_160, mode, dfs_enabled)) { for (j = 0; j < ARRAY_SIZE(bw160); j++) { - if (freq->freq == bw160[j]) { - chwidth = CONF_OPER_CHWIDTH_160MHZ; -@@ -3317,9 +3326,9 @@ static bool ibss_mesh_select_80_160mhz(s - if ((mode->eht_capab[ieee80211_mode].phy_cap[ - EHT_PHYCAP_320MHZ_IN_6GHZ_SUPPORT_IDX] & + u8 start_chan; + +@@ -3363,11 +3372,11 @@ static bool ibss_mesh_select_80_160mhz(s EHT_PHYCAP_320MHZ_IN_6GHZ_SUPPORT_MASK) && is_6ghz && -- ibss_mesh_is_80mhz_avail(channel + 16, mode) && -- ibss_mesh_is_80mhz_avail(channel + 32, mode) && -- ibss_mesh_is_80mhz_avail(channel + 48, mode)) { -+ ibss_mesh_is_80mhz_avail(channel + 16, mode, dfs_enabled) && -+ ibss_mesh_is_80mhz_avail(channel + 32, mode, dfs_enabled) && -+ ibss_mesh_is_80mhz_avail(channel + 48, mode, dfs_enabled)) { + ssid->max_oper_chwidth == CONF_OPER_CHWIDTH_320MHZ && + ibss_mesh_is_80mhz_avail(channel + 16 - +- 64 * ((offset_in_320 + 1) / 4), mode) && ++ 64 * ((offset_in_320 + 1) / 4), mode, dfs_enabled) && + ibss_mesh_is_80mhz_avail(channel + 32 - +- 64 * ((offset_in_320 + 2) / 4), mode) && ++ 64 * ((offset_in_320 + 2) / 4), mode, dfs_enabled) && + ibss_mesh_is_80mhz_avail(channel + 48 - +- 64 * ((offset_in_320 + 3) / 4), mode)) { ++ 64 * ((offset_in_320 + 3) / 4), mode, dfs_enabled)) { for (j = 0; j < ARRAY_SIZE(bw320); j += 2) { if (freq->freq >= bw320[j] && freq->freq <= bw320[j + 1]) { -@@ -3348,10 +3357,12 @@ static bool ibss_mesh_select_80_160mhz(s +@@ -3396,10 +3405,12 @@ static bool ibss_mesh_select_80_160mhz(s if (!chan) continue; - if (chan->flag & (HOSTAPD_CHAN_DISABLED | - HOSTAPD_CHAN_NO_IR | - HOSTAPD_CHAN_RADAR)) +- continue; + if (chan->flag & HOSTAPD_CHAN_DISABLED) - continue; ++ continue; + if (chan->flag & (HOSTAPD_CHAN_RADAR | + HOSTAPD_CHAN_NO_IR)) + if (!dfs_enabled) @@ -126,7 +131,7 @@ Signed-off-by: Peter Oh /* Found a suitable second segment for 80+80 */ chwidth = CONF_OPER_CHWIDTH_80P80MHZ; -@@ -3406,6 +3417,7 @@ void ibss_mesh_setup_freq(struct wpa_sup +@@ -3454,6 +3465,7 @@ void ibss_mesh_setup_freq(struct wpa_sup int obss_scan = 1; u8 channel; bool is_6ghz, is_24ghz; @@ -134,12 +139,12 @@ Signed-off-by: Peter Oh freq->freq = ssid->frequency; -@@ -3448,9 +3460,9 @@ void ibss_mesh_setup_freq(struct wpa_sup - freq->channel = channel; - /* Setup higher BW only for 5 GHz */ +@@ -3497,9 +3509,9 @@ void ibss_mesh_setup_freq(struct wpa_sup + /* Setup higher BW only for 5 and 6 GHz */ if (mode->mode == HOSTAPD_MODE_IEEE80211A) { -- ibss_mesh_select_40mhz(wpa_s, ssid, mode, freq, obss_scan); -+ ibss_mesh_select_40mhz(wpa_s, ssid, mode, freq, obss_scan, dfs_enabled); + ibss_mesh_select_40mhz(wpa_s, ssid, mode, freq, obss_scan, +- is_6ghz); ++ is_6ghz, dfs_enabled); if (!ibss_mesh_select_80_160mhz(wpa_s, ssid, mode, freq, - ieee80211_mode, is_6ghz)) + ieee80211_mode, is_6ghz, dfs_enabled)) diff --git a/package/network/services/hostapd/patches/011-mesh-use-deterministic-channel-on-channel-switch.patch b/package/network/services/hostapd/patches/011-mesh-use-deterministic-channel-on-channel-switch.patch index 9d925cd8c6..ea67d653a3 100644 --- a/package/network/services/hostapd/patches/011-mesh-use-deterministic-channel-on-channel-switch.patch +++ b/package/network/services/hostapd/patches/011-mesh-use-deterministic-channel-on-channel-switch.patch @@ -68,7 +68,7 @@ Signed-off-by: Markus Theil chan_idx, num_available_chandefs); --- a/src/drivers/driver_nl80211.c +++ b/src/drivers/driver_nl80211.c -@@ -11656,6 +11656,10 @@ static int nl80211_switch_channel(void * +@@ -11592,6 +11592,10 @@ static int nl80211_switch_channel(void * if (ret) goto error; diff --git a/package/network/services/hostapd/patches/021-fix-sta-add-after-previous-connection.patch b/package/network/services/hostapd/patches/021-fix-sta-add-after-previous-connection.patch index a5aa688efb..090df4d5c9 100644 --- a/package/network/services/hostapd/patches/021-fix-sta-add-after-previous-connection.patch +++ b/package/network/services/hostapd/patches/021-fix-sta-add-after-previous-connection.patch @@ -4,7 +4,7 @@ Subject: [PATCH] fix adding back stations after a missed deauth/disassoc --- a/src/ap/ieee802_11.c +++ b/src/ap/ieee802_11.c -@@ -4894,6 +4894,13 @@ static int add_associated_sta(struct hos +@@ -5033,6 +5033,13 @@ static int add_associated_sta(struct hos * drivers to accept the STA parameter configuration. Since this is * after a new FT-over-DS exchange, a new TK has been derived, so key * reinstallation is not a concern for this case. @@ -18,7 +18,7 @@ Subject: [PATCH] fix adding back stations after a missed deauth/disassoc */ wpa_printf(MSG_DEBUG, "Add associated STA " MACSTR " (added_unassoc=%d auth_alg=%u ft_over_ds=%u reassoc=%d authorized=%d ft_tk=%d fils_tk=%d)", -@@ -4907,7 +4914,8 @@ static int add_associated_sta(struct hos +@@ -5046,7 +5053,8 @@ static int add_associated_sta(struct hos (!(sta->flags & WLAN_STA_AUTHORIZED) || (reassoc && sta->ft_over_ds && sta->auth_alg == WLAN_AUTH_FT) || (!wpa_auth_sta_ft_tk_already_set(sta->wpa_sm) && diff --git a/package/network/services/hostapd/patches/050-Fix-OpenWrt-13156.patch b/package/network/services/hostapd/patches/050-Fix-OpenWrt-13156.patch index 584dd3b2f8..252929a64d 100644 --- a/package/network/services/hostapd/patches/050-Fix-OpenWrt-13156.patch +++ b/package/network/services/hostapd/patches/050-Fix-OpenWrt-13156.patch @@ -20,7 +20,7 @@ Signed-off-by: Stijn Tintel --- a/src/ap/hostapd.c +++ b/src/ap/hostapd.c -@@ -4075,6 +4075,8 @@ int hostapd_remove_iface(struct hapd_int +@@ -4091,6 +4091,8 @@ int hostapd_remove_iface(struct hapd_int void hostapd_new_assoc_sta(struct hostapd_data *hapd, struct sta_info *sta, int reassoc) { @@ -29,7 +29,7 @@ Signed-off-by: Stijn Tintel if (hapd->tkip_countermeasures) { hostapd_drv_sta_deauth(hapd, sta->addr, WLAN_REASON_MICHAEL_MIC_FAILURE); -@@ -4082,10 +4084,16 @@ void hostapd_new_assoc_sta(struct hostap +@@ -4098,10 +4100,16 @@ void hostapd_new_assoc_sta(struct hostap } #ifdef CONFIG_IEEE80211BE @@ -51,7 +51,7 @@ Signed-off-by: Stijn Tintel ap_sta_clear_assoc_timeout(hapd, sta); --- a/src/ap/sta_info.c +++ b/src/ap/sta_info.c -@@ -1552,9 +1552,6 @@ bool ap_sta_set_authorized_flag(struct h +@@ -1553,9 +1553,6 @@ bool ap_sta_set_authorized_flag(struct h mld_assoc_link_id = -2; } #endif /* CONFIG_IEEE80211BE */ diff --git a/package/network/services/hostapd/patches/051-nl80211-add-extra-ies-only-if-allowed-by-driver.patch b/package/network/services/hostapd/patches/051-nl80211-add-extra-ies-only-if-allowed-by-driver.patch index cba6614633..b4709cf504 100644 --- a/package/network/services/hostapd/patches/051-nl80211-add-extra-ies-only-if-allowed-by-driver.patch +++ b/package/network/services/hostapd/patches/051-nl80211-add-extra-ies-only-if-allowed-by-driver.patch @@ -26,7 +26,7 @@ Signed-off-by: David Bauer --- a/src/drivers/driver.h +++ b/src/drivers/driver.h -@@ -2411,6 +2411,9 @@ struct wpa_driver_capa { +@@ -2441,6 +2441,9 @@ struct wpa_driver_capa { /** Maximum number of iterations in a single scan plan */ u32 max_sched_scan_plan_iterations; @@ -38,7 +38,7 @@ Signed-off-by: David Bauer --- a/src/drivers/driver_nl80211_capa.c +++ b/src/drivers/driver_nl80211_capa.c -@@ -984,6 +984,10 @@ static int wiphy_info_handler(struct nl_ +@@ -981,6 +981,10 @@ static int wiphy_info_handler(struct nl_ nla_get_u32(tb[NL80211_ATTR_MAX_SCAN_PLAN_ITERATIONS]); } diff --git a/package/network/services/hostapd/patches/110-mbedtls-TLS-crypto-option-initial-port.patch b/package/network/services/hostapd/patches/110-mbedtls-TLS-crypto-option-initial-port.patch index ab05c92d36..d90298c97d 100644 --- a/package/network/services/hostapd/patches/110-mbedtls-TLS-crypto-option-initial-port.patch +++ b/package/network/services/hostapd/patches/110-mbedtls-TLS-crypto-option-initial-port.patch @@ -7772,7 +7772,7 @@ Signed-off-by: Glenn Strauss CONFIG_SIM_SIMULATOR=y --- a/wpa_supplicant/Makefile +++ b/wpa_supplicant/Makefile -@@ -1232,6 +1232,29 @@ endif +@@ -1234,6 +1234,29 @@ endif CFLAGS += -DTLS_DEFAULT_CIPHERS=\"$(CONFIG_TLS_DEFAULT_CIPHERS)\" endif @@ -7802,7 +7802,7 @@ Signed-off-by: Glenn Strauss ifeq ($(CONFIG_TLS), gnutls) ifndef CONFIG_CRYPTO # default to libgcrypt -@@ -1424,9 +1447,11 @@ endif +@@ -1426,9 +1449,11 @@ endif ifneq ($(CONFIG_TLS), openssl) ifneq ($(CONFIG_TLS), wolfssl) @@ -7814,7 +7814,7 @@ Signed-off-by: Glenn Strauss ifdef CONFIG_OPENSSL_INTERNAL_AES_WRAP # Seems to be needed at least with BoringSSL NEED_INTERNAL_AES_WRAP=y -@@ -1440,9 +1465,11 @@ endif +@@ -1442,9 +1467,11 @@ endif ifdef NEED_INTERNAL_AES_WRAP ifneq ($(CONFIG_TLS), linux) @@ -7826,7 +7826,7 @@ Signed-off-by: Glenn Strauss ifdef NEED_AES_EAX AESOBJS += ../src/crypto/aes-eax.o NEED_AES_CTR=y -@@ -1452,35 +1479,45 @@ AESOBJS += ../src/crypto/aes-siv.o +@@ -1454,35 +1481,45 @@ AESOBJS += ../src/crypto/aes-siv.o NEED_AES_CTR=y endif ifdef NEED_AES_CTR @@ -7872,7 +7872,7 @@ Signed-off-by: Glenn Strauss ifdef NEED_AES_ENC ifdef CONFIG_INTERNAL_AES AESOBJS += ../src/crypto/aes-internal-enc.o -@@ -1495,12 +1532,16 @@ ifneq ($(CONFIG_TLS), openssl) +@@ -1497,12 +1534,16 @@ ifneq ($(CONFIG_TLS), openssl) ifneq ($(CONFIG_TLS), linux) ifneq ($(CONFIG_TLS), gnutls) ifneq ($(CONFIG_TLS), wolfssl) @@ -7889,7 +7889,7 @@ Signed-off-by: Glenn Strauss ifdef CONFIG_INTERNAL_SHA1 SHA1OBJS += ../src/crypto/sha1-internal.o ifdef NEED_FIPS186_2_PRF -@@ -1512,29 +1553,37 @@ CFLAGS += -DCONFIG_NO_PBKDF2 +@@ -1514,29 +1555,37 @@ CFLAGS += -DCONFIG_NO_PBKDF2 else ifneq ($(CONFIG_TLS), openssl) ifneq ($(CONFIG_TLS), wolfssl) @@ -7927,7 +7927,7 @@ Signed-off-by: Glenn Strauss ifdef NEED_MD5 ifdef CONFIG_INTERNAL_MD5 MD5OBJS += ../src/crypto/md5-internal.o -@@ -1589,12 +1638,17 @@ ifneq ($(CONFIG_TLS), openssl) +@@ -1591,12 +1640,17 @@ ifneq ($(CONFIG_TLS), openssl) ifneq ($(CONFIG_TLS), linux) ifneq ($(CONFIG_TLS), gnutls) ifneq ($(CONFIG_TLS), wolfssl) @@ -7945,7 +7945,7 @@ Signed-off-by: Glenn Strauss ifdef CONFIG_INTERNAL_SHA256 SHA256OBJS += ../src/crypto/sha256-internal.o endif -@@ -1607,50 +1661,68 @@ CFLAGS += -DCONFIG_INTERNAL_SHA512 +@@ -1609,50 +1663,68 @@ CFLAGS += -DCONFIG_INTERNAL_SHA512 SHA256OBJS += ../src/crypto/sha512-internal.o endif ifdef NEED_TLS_PRF_SHA256 @@ -8014,7 +8014,7 @@ Signed-off-by: Glenn Strauss ifdef NEED_ASN1 OBJS += ../src/tls/asn1.o -@@ -1825,10 +1897,12 @@ ifdef CONFIG_FIPS +@@ -1827,10 +1899,12 @@ ifdef CONFIG_FIPS CFLAGS += -DCONFIG_FIPS ifneq ($(CONFIG_TLS), openssl) ifneq ($(CONFIG_TLS), wolfssl) diff --git a/package/network/services/hostapd/patches/120-mbedtls-fips186_2_prf.patch b/package/network/services/hostapd/patches/120-mbedtls-fips186_2_prf.patch index 5534de7efa..71b06401cd 100644 --- a/package/network/services/hostapd/patches/120-mbedtls-fips186_2_prf.patch +++ b/package/network/services/hostapd/patches/120-mbedtls-fips186_2_prf.patch @@ -101,7 +101,7 @@ Signed-off-by: Glenn Strauss --- a/wpa_supplicant/Makefile +++ b/wpa_supplicant/Makefile -@@ -1243,10 +1243,6 @@ endif +@@ -1245,10 +1245,6 @@ endif OBJS += ../src/crypto/crypto_$(CONFIG_CRYPTO).o OBJS_p += ../src/crypto/crypto_$(CONFIG_CRYPTO).o OBJS_priv += ../src/crypto/crypto_$(CONFIG_CRYPTO).o diff --git a/package/network/services/hostapd/patches/140-tests-Makefile-make-run-tests-with-CONFIG_TLS.patch b/package/network/services/hostapd/patches/140-tests-Makefile-make-run-tests-with-CONFIG_TLS.patch index babc2a568d..548358db38 100644 --- a/package/network/services/hostapd/patches/140-tests-Makefile-make-run-tests-with-CONFIG_TLS.patch +++ b/package/network/services/hostapd/patches/140-tests-Makefile-make-run-tests-with-CONFIG_TLS.patch @@ -739,7 +739,7 @@ Signed-off-by: Glenn Strauss params = hostapd.wpa2_eap_params(ssid="test-wpa2-eap") hostapd.add_ap(apdev[0], params) -@@ -3581,7 +3626,7 @@ def test_ap_wpa2_eap_ikev2_oom(dev, apde +@@ -3588,7 +3633,7 @@ def test_ap_wpa2_eap_ikev2_oom(dev, apde dev[0].request("REMOVE_NETWORK all") tls = dev[0].request("GET tls_library") @@ -748,7 +748,7 @@ Signed-off-by: Glenn Strauss tests = [(1, "os_get_random;dh_init")] else: tests = [(1, "crypto_dh_init;dh_init")] -@@ -4901,7 +4946,7 @@ def test_ap_wpa2_eap_tls_intermediate_ca +@@ -4908,7 +4953,7 @@ def test_ap_wpa2_eap_tls_intermediate_ca params["private_key"] = "auth_serv/iCA-server/server.key" hostapd.add_ap(apdev[0], params) tls = dev[0].request("GET tls_library") @@ -757,7 +757,7 @@ Signed-off-by: Glenn Strauss ca_cert = "auth_serv/iCA-user/ca-and-root.pem" client_cert = "auth_serv/iCA-user/user_and_ica.pem" else: -@@ -4967,6 +5012,7 @@ def test_ap_wpa2_eap_tls_intermediate_ca +@@ -4974,6 +5019,7 @@ def test_ap_wpa2_eap_tls_intermediate_ca run_ap_wpa2_eap_tls_intermediate_ca_ocsp(dev, apdev, params, "-sha1") def run_ap_wpa2_eap_tls_intermediate_ca_ocsp(dev, apdev, params, md): @@ -765,7 +765,7 @@ Signed-off-by: Glenn Strauss params = int_eap_server_params() params["ca_cert"] = "auth_serv/iCA-server/ca-and-root.pem" params["server_cert"] = "auth_serv/iCA-server/server.pem" -@@ -4976,7 +5022,7 @@ def run_ap_wpa2_eap_tls_intermediate_ca_ +@@ -4983,7 +5029,7 @@ def run_ap_wpa2_eap_tls_intermediate_ca_ try: hostapd.add_ap(apdev[0], params) tls = dev[0].request("GET tls_library") @@ -774,7 +774,7 @@ Signed-off-by: Glenn Strauss ca_cert = "auth_serv/iCA-user/ca-and-root.pem" client_cert = "auth_serv/iCA-user/user_and_ica.pem" else: -@@ -5012,7 +5058,7 @@ def run_ap_wpa2_eap_tls_intermediate_ca_ +@@ -5019,7 +5065,7 @@ def run_ap_wpa2_eap_tls_intermediate_ca_ try: hostapd.add_ap(apdev[0], params) tls = dev[0].request("GET tls_library") @@ -783,7 +783,7 @@ Signed-off-by: Glenn Strauss ca_cert = "auth_serv/iCA-user/ca-and-root.pem" client_cert = "auth_serv/iCA-user/user_and_ica.pem" else: -@@ -5062,7 +5108,7 @@ def test_ap_wpa2_eap_tls_intermediate_ca +@@ -5069,7 +5115,7 @@ def test_ap_wpa2_eap_tls_intermediate_ca try: hostapd.add_ap(apdev[0], params) tls = dev[0].request("GET tls_library") @@ -792,7 +792,7 @@ Signed-off-by: Glenn Strauss ca_cert = "auth_serv/iCA-user/ca-and-root.pem" client_cert = "auth_serv/iCA-user/user_and_ica.pem" else: -@@ -5129,7 +5175,7 @@ def test_ap_wpa2_eap_tls_intermediate_ca +@@ -5136,7 +5182,7 @@ def test_ap_wpa2_eap_tls_intermediate_ca hostapd.add_ap(apdev[0], params) tls = dev[0].request("GET tls_library") @@ -801,7 +801,7 @@ Signed-off-by: Glenn Strauss ca_cert = "auth_serv/iCA-user/ca-and-root.pem" client_cert = "auth_serv/iCA-user/user_and_ica.pem" else: -@@ -5387,6 +5433,7 @@ def test_ap_wpa2_eap_ttls_server_cert_ek +@@ -5394,6 +5440,7 @@ def test_ap_wpa2_eap_ttls_server_cert_ek def test_ap_wpa2_eap_ttls_server_pkcs12(dev, apdev): """WPA2-Enterprise using EAP-TTLS and server PKCS#12 file""" @@ -809,7 +809,7 @@ Signed-off-by: Glenn Strauss skip_with_fips(dev[0]) params = int_eap_server_params() del params["server_cert"] -@@ -5399,6 +5446,7 @@ def test_ap_wpa2_eap_ttls_server_pkcs12( +@@ -5406,6 +5453,7 @@ def test_ap_wpa2_eap_ttls_server_pkcs12( def test_ap_wpa2_eap_ttls_server_pkcs12_extra(dev, apdev): """EAP-TTLS and server PKCS#12 file with extra certs""" @@ -817,7 +817,7 @@ Signed-off-by: Glenn Strauss skip_with_fips(dev[0]) params = int_eap_server_params() del params["server_cert"] -@@ -5421,6 +5469,7 @@ def test_ap_wpa2_eap_ttls_dh_params_serv +@@ -5428,6 +5476,7 @@ def test_ap_wpa2_eap_ttls_dh_params_serv def test_ap_wpa2_eap_ttls_dh_params_dsa_server(dev, apdev): """WPA2-Enterprise using EAP-TTLS and alternative server dhparams (DSA)""" @@ -825,7 +825,7 @@ Signed-off-by: Glenn Strauss params = int_eap_server_params() params["dh_file"] = "auth_serv/dsaparam.pem" hapd = hostapd.add_ap(apdev[0], params) -@@ -5732,8 +5781,8 @@ def test_ap_wpa2_eap_non_ascii_identity2 +@@ -5739,8 +5788,8 @@ def test_ap_wpa2_eap_non_ascii_identity2 def test_openssl_cipher_suite_config_wpas(dev, apdev): """OpenSSL cipher suite configuration on wpa_supplicant""" tls = dev[0].request("GET tls_library") @@ -836,7 +836,7 @@ Signed-off-by: Glenn Strauss params = hostapd.wpa2_eap_params(ssid="test-wpa2-eap") hapd = hostapd.add_ap(apdev[0], params) eap_connect(dev[0], hapd, "TTLS", "pap user", -@@ -5759,14 +5808,14 @@ def test_openssl_cipher_suite_config_wpa +@@ -5766,14 +5815,14 @@ def test_openssl_cipher_suite_config_wpa def test_openssl_cipher_suite_config_hapd(dev, apdev): """OpenSSL cipher suite configuration on hostapd""" tls = dev[0].request("GET tls_library") @@ -855,7 +855,7 @@ Signed-off-by: Glenn Strauss eap_connect(dev[0], hapd, "TTLS", "pap user", anonymous_identity="ttls", password="password", ca_cert="auth_serv/ca.pem", phase2="auth=PAP") -@@ -6209,13 +6258,17 @@ def test_ap_wpa2_eap_tls_versions(dev, a +@@ -6216,13 +6265,17 @@ def test_ap_wpa2_eap_tls_versions(dev, a if tls.startswith("wolfSSL"): check_tls_ver(dev[0], hapd, "tls_disable_tlsv1_0=1 tls_disable_tlsv1_1=1", "TLSv1.2") @@ -878,7 +878,7 @@ Signed-off-by: Glenn Strauss if "run=OpenSSL 1.1.1" in tls or "run=OpenSSL 3." in tls or \ tls.startswith("wolfSSL"): check_tls_ver(dev[0], hapd, -@@ -6238,6 +6291,11 @@ def test_ap_wpa2_eap_tls_versions_server +@@ -6245,6 +6298,11 @@ def test_ap_wpa2_eap_tls_versions_server tests = [("TLSv1", "[ENABLE-TLSv1.0][DISABLE-TLSv1.1][DISABLE-TLSv1.2][DISABLE-TLSv1.3]"), ("TLSv1.1", "[ENABLE-TLSv1.0][ENABLE-TLSv1.1][DISABLE-TLSv1.2][DISABLE-TLSv1.3]"), ("TLSv1.2", "[ENABLE-TLSv1.0][ENABLE-TLSv1.1][ENABLE-TLSv1.2][DISABLE-TLSv1.3]")] @@ -890,7 +890,7 @@ Signed-off-by: Glenn Strauss for exp, flags in tests: hapd.disable() hapd.set("tls_flags", flags) -@@ -7318,6 +7376,7 @@ def test_ap_wpa2_eap_assoc_rsn(dev, apde +@@ -7325,6 +7383,7 @@ def test_ap_wpa2_eap_assoc_rsn(dev, apde def test_eap_tls_ext_cert_check(dev, apdev): """EAP-TLS and external server certification validation""" # With internal server certificate chain validation @@ -898,7 +898,7 @@ Signed-off-by: Glenn Strauss id = dev[0].connect("test-wpa2-eap", key_mgmt="WPA-EAP", eap="TLS", identity="tls user", ca_cert="auth_serv/ca.pem", -@@ -7330,6 +7389,7 @@ def test_eap_tls_ext_cert_check(dev, apd +@@ -7337,6 +7396,7 @@ def test_eap_tls_ext_cert_check(dev, apd def test_eap_ttls_ext_cert_check(dev, apdev): """EAP-TTLS and external server certification validation""" # Without internal server certificate chain validation @@ -906,7 +906,7 @@ Signed-off-by: Glenn Strauss id = dev[0].connect("test-wpa2-eap", key_mgmt="WPA-EAP", eap="TTLS", identity="pap user", anonymous_identity="ttls", password="password", phase2="auth=PAP", -@@ -7340,6 +7400,7 @@ def test_eap_ttls_ext_cert_check(dev, ap +@@ -7347,6 +7407,7 @@ def test_eap_ttls_ext_cert_check(dev, ap def test_eap_peap_ext_cert_check(dev, apdev): """EAP-PEAP and external server certification validation""" # With internal server certificate chain validation @@ -914,7 +914,7 @@ Signed-off-by: Glenn Strauss id = dev[0].connect("test-wpa2-eap", key_mgmt="WPA-EAP", eap="PEAP", identity="user", anonymous_identity="peap", ca_cert="auth_serv/ca.pem", -@@ -7350,6 +7411,7 @@ def test_eap_peap_ext_cert_check(dev, ap +@@ -7357,6 +7418,7 @@ def test_eap_peap_ext_cert_check(dev, ap def test_eap_fast_ext_cert_check(dev, apdev): """EAP-FAST and external server certification validation""" @@ -922,7 +922,7 @@ Signed-off-by: Glenn Strauss check_eap_capa(dev[0], "FAST") # With internal server certificate chain validation dev[0].request("SET blob fast_pac_auth_ext ") -@@ -7364,10 +7426,6 @@ def test_eap_fast_ext_cert_check(dev, ap +@@ -7371,10 +7433,6 @@ def test_eap_fast_ext_cert_check(dev, ap run_ext_cert_check(dev, apdev, id) def run_ext_cert_check(dev, apdev, net_id): @@ -1124,7 +1124,7 @@ Signed-off-by: Glenn Strauss heavy_groups = [14, 15, 16] suitable_groups = [15, 16, 17, 18, 19, 20, 21] groups = [str(g) for g in sae_groups] -@@ -2248,6 +2253,8 @@ def run_sae_pwe_group(dev, apdev, group) +@@ -2285,6 +2290,8 @@ def run_sae_pwe_group(dev, apdev, group) logger.info("Add Brainpool EC groups since OpenSSL is new enough") elif tls.startswith("wolfSSL"): logger.info("Make sure Brainpool EC groups were enabled when compiling wolfSSL") @@ -1144,7 +1144,7 @@ Signed-off-by: Glenn Strauss if not tls.startswith("OpenSSL"): raise HwsimSkip("TLS library not supported for Suite B: " + tls) supported = False -@@ -520,6 +522,7 @@ def test_suite_b_192_rsa_insufficient_dh +@@ -539,6 +541,7 @@ def test_suite_b_192_rsa_insufficient_dh dev[0].connect("test-suite-b", key_mgmt="WPA-EAP-SUITE-B-192", ieee80211w="2", @@ -1289,7 +1289,7 @@ Signed-off-by: Glenn Strauss if (need_more_data) { --- a/wpa_supplicant/Makefile +++ b/wpa_supplicant/Makefile -@@ -1190,6 +1190,7 @@ TLS_FUNCS=y +@@ -1192,6 +1192,7 @@ TLS_FUNCS=y endif ifeq ($(CONFIG_TLS), wolfssl) @@ -1297,7 +1297,7 @@ Signed-off-by: Glenn Strauss CFLAGS += -DCRYPTO_RSA_OAEP_SHA256 ifdef TLS_FUNCS CFLAGS += -DWOLFSSL_DER_LOAD -@@ -1206,6 +1207,7 @@ LIBS_p += -lwolfssl -lm +@@ -1208,6 +1209,7 @@ LIBS_p += -lwolfssl -lm endif ifeq ($(CONFIG_TLS), openssl) @@ -1305,7 +1305,7 @@ Signed-off-by: Glenn Strauss CFLAGS += -DCRYPTO_RSA_OAEP_SHA256 ifdef TLS_FUNCS CFLAGS += -DEAP_TLS_OPENSSL -@@ -1233,6 +1235,7 @@ CFLAGS += -DTLS_DEFAULT_CIPHERS=\"$(CONF +@@ -1235,6 +1237,7 @@ CFLAGS += -DTLS_DEFAULT_CIPHERS=\"$(CONF endif ifeq ($(CONFIG_TLS), mbedtls) @@ -1313,7 +1313,7 @@ Signed-off-by: Glenn Strauss ifndef CONFIG_CRYPTO CONFIG_CRYPTO=mbedtls endif -@@ -1252,6 +1255,7 @@ endif +@@ -1254,6 +1257,7 @@ endif endif ifeq ($(CONFIG_TLS), gnutls) @@ -1321,7 +1321,7 @@ Signed-off-by: Glenn Strauss ifndef CONFIG_CRYPTO # default to libgcrypt CONFIG_CRYPTO=gnutls -@@ -1282,6 +1286,7 @@ endif +@@ -1284,6 +1288,7 @@ endif endif ifeq ($(CONFIG_TLS), internal) @@ -1329,7 +1329,7 @@ Signed-off-by: Glenn Strauss ifndef CONFIG_CRYPTO CONFIG_CRYPTO=internal endif -@@ -1362,6 +1367,7 @@ endif +@@ -1364,6 +1369,7 @@ endif endif ifeq ($(CONFIG_TLS), linux) diff --git a/package/network/services/hostapd/patches/150-add-NULL-checks-encountered-during-tests-hwsim.patch b/package/network/services/hostapd/patches/150-add-NULL-checks-encountered-during-tests-hwsim.patch index e562c2dd2a..0b0737e760 100644 --- a/package/network/services/hostapd/patches/150-add-NULL-checks-encountered-during-tests-hwsim.patch +++ b/package/network/services/hostapd/patches/150-add-NULL-checks-encountered-during-tests-hwsim.patch @@ -29,7 +29,7 @@ Signed-off-by: Glenn Strauss wpa_printf(MSG_DEBUG, "DPP: Generating a keypair"); --- a/src/common/sae.c +++ b/src/common/sae.c -@@ -1284,6 +1284,13 @@ void sae_deinit_pt(struct sae_pt *pt) +@@ -1287,6 +1287,13 @@ void sae_deinit_pt(struct sae_pt *pt) static int sae_derive_commit_element_ecc(struct sae_data *sae, struct crypto_bignum *mask) { diff --git a/package/network/services/hostapd/patches/170-hostapd-update-cfs0-and-cfs1-for-160MHz.patch b/package/network/services/hostapd/patches/170-hostapd-update-cfs0-and-cfs1-for-160MHz.patch index d9cdb1d3eb..8ad4bae33c 100644 --- a/package/network/services/hostapd/patches/170-hostapd-update-cfs0-and-cfs1-for-160MHz.patch +++ b/package/network/services/hostapd/patches/170-hostapd-update-cfs0-and-cfs1-for-160MHz.patch @@ -29,7 +29,7 @@ Signed-off-by: P Praneesh --- a/hostapd/config_file.c +++ b/hostapd/config_file.c -@@ -1229,6 +1229,8 @@ static int hostapd_config_vht_capab(stru +@@ -1225,6 +1225,8 @@ static int hostapd_config_vht_capab(stru conf->vht_capab |= VHT_CAP_RX_ANTENNA_PATTERN; if (os_strstr(capab, "[TX-ANTENNA-PATTERN]")) conf->vht_capab |= VHT_CAP_TX_ANTENNA_PATTERN; @@ -100,7 +100,7 @@ Signed-off-by: P Praneesh u8 *pos = eid; enum oper_chan_width oper_chwidth = hostapd_get_oper_chwidth(hapd->iconf); -@@ -110,6 +123,7 @@ u8 * hostapd_eid_vht_operation(struct ho +@@ -113,6 +126,7 @@ u8 * hostapd_eid_vht_operation(struct ho oper->vht_op_info_chan_center_freq_seg1_idx = seg1; oper->vht_op_info_chwidth = oper_chwidth; @@ -108,7 +108,7 @@ Signed-off-by: P Praneesh if (oper_chwidth == CONF_OPER_CHWIDTH_160MHZ) { /* * Convert 160 MHz channel width to new style as interop -@@ -123,6 +137,9 @@ u8 * hostapd_eid_vht_operation(struct ho +@@ -126,6 +140,9 @@ u8 * hostapd_eid_vht_operation(struct ho oper->vht_op_info_chan_center_freq_seg0_idx -= 8; else oper->vht_op_info_chan_center_freq_seg0_idx += 8; @@ -120,7 +120,7 @@ Signed-off-by: P Praneesh * Convert 80+80 MHz channel width to new style as interop --- a/src/common/hw_features_common.c +++ b/src/common/hw_features_common.c -@@ -923,6 +923,7 @@ int ieee80211ac_cap_check(u32 hw, u32 co +@@ -924,6 +924,7 @@ int ieee80211ac_cap_check(u32 hw, u32 co VHT_CAP_CHECK(VHT_CAP_VHT_LINK_ADAPTATION_VHT_MRQ_MFB); VHT_CAP_CHECK(VHT_CAP_RX_ANTENNA_PATTERN); VHT_CAP_CHECK(VHT_CAP_TX_ANTENNA_PATTERN); @@ -130,7 +130,7 @@ Signed-off-by: P Praneesh #undef VHT_CAP_CHECK_MAX --- a/src/common/ieee802_11_defs.h +++ b/src/common/ieee802_11_defs.h -@@ -1420,6 +1420,8 @@ struct ieee80211_ampe_ie { +@@ -1421,6 +1421,8 @@ struct ieee80211_ampe_ie { #define VHT_CAP_VHT_LINK_ADAPTATION_VHT_MRQ_MFB ((u32) BIT(26) | BIT(27)) #define VHT_CAP_RX_ANTENNA_PATTERN ((u32) BIT(28)) #define VHT_CAP_TX_ANTENNA_PATTERN ((u32) BIT(29)) diff --git a/package/network/services/hostapd/patches/200-multicall.patch b/package/network/services/hostapd/patches/200-multicall.patch index 7472dc63e6..85c9180576 100644 --- a/package/network/services/hostapd/patches/200-multicall.patch +++ b/package/network/services/hostapd/patches/200-multicall.patch @@ -94,7 +94,7 @@ This allows building both hostapd and wpa_supplicant as a single binary if (c < 0) --- a/src/ap/drv_callbacks.c +++ b/src/ap/drv_callbacks.c -@@ -2537,8 +2537,8 @@ static void hostapd_mld_iface_disable(st +@@ -2523,8 +2523,8 @@ static void hostapd_mld_iface_disable(st #endif /* CONFIG_IEEE80211BE */ @@ -105,7 +105,7 @@ This allows building both hostapd and wpa_supplicant as a single binary { struct hostapd_data *hapd = ctx; struct sta_info *sta; -@@ -2896,7 +2896,7 @@ void wpa_supplicant_event(void *ctx, enu +@@ -2882,7 +2882,7 @@ void wpa_supplicant_event(void *ctx, enu } @@ -116,7 +116,7 @@ This allows building both hostapd and wpa_supplicant as a single binary struct hapd_interfaces *interfaces = ctx; --- a/src/drivers/driver.h +++ b/src/drivers/driver.h -@@ -7072,8 +7072,8 @@ union wpa_event_data { +@@ -7105,8 +7105,8 @@ union wpa_event_data { * Driver wrapper code should call this function whenever an event is received * from the driver. */ @@ -127,7 +127,7 @@ This allows building both hostapd and wpa_supplicant as a single binary /** * wpa_supplicant_event_global - Report a driver event for wpa_supplicant -@@ -7085,7 +7085,7 @@ void wpa_supplicant_event(void *ctx, enu +@@ -7118,7 +7118,7 @@ void wpa_supplicant_event(void *ctx, enu * Same as wpa_supplicant_event(), but we search for the interface in * wpa_global. */ @@ -169,7 +169,7 @@ This allows building both hostapd and wpa_supplicant as a single binary OBJS += ibss_rsn.o endif -@@ -982,6 +985,10 @@ ifdef CONFIG_DYNAMIC_EAP_METHODS +@@ -984,6 +987,10 @@ ifdef CONFIG_DYNAMIC_EAP_METHODS CFLAGS += -DCONFIG_DYNAMIC_EAP_METHODS LIBS += -ldl -rdynamic endif @@ -180,7 +180,7 @@ This allows building both hostapd and wpa_supplicant as a single binary endif ifdef CONFIG_AP -@@ -989,9 +996,11 @@ NEED_EAP_COMMON=y +@@ -991,9 +998,11 @@ NEED_EAP_COMMON=y NEED_RSN_AUTHENTICATOR=y CFLAGS += -DCONFIG_AP OBJS += ap.o @@ -192,7 +192,7 @@ This allows building both hostapd and wpa_supplicant as a single binary OBJS += ../src/ap/hostapd.o OBJS += ../src/ap/wpa_auth_glue.o OBJS += ../src/ap/utils.o -@@ -1082,6 +1091,12 @@ endif +@@ -1084,6 +1093,12 @@ endif ifdef CONFIG_HS20 OBJS += ../src/ap/hs20.o endif @@ -205,7 +205,7 @@ This allows building both hostapd and wpa_supplicant as a single binary endif ifdef CONFIG_MBO -@@ -1091,7 +1106,9 @@ NEED_GAS=y +@@ -1093,7 +1108,9 @@ NEED_GAS=y endif ifdef NEED_RSN_AUTHENTICATOR @@ -215,7 +215,7 @@ This allows building both hostapd and wpa_supplicant as a single binary NEED_AES_WRAP=y OBJS += ../src/ap/wpa_auth.o OBJS += ../src/ap/wpa_auth_ie.o -@@ -2082,6 +2099,12 @@ wpa_priv: $(BCHECK) $(OBJS_priv) +@@ -2084,6 +2101,12 @@ wpa_priv: $(BCHECK) $(OBJS_priv) _OBJS_VAR := OBJS include ../src/objs.mk @@ -228,7 +228,7 @@ This allows building both hostapd and wpa_supplicant as a single binary wpa_supplicant: $(BCHECK) $(OBJS) $(EXTRA_progs) $(Q)$(LDO) $(LDFLAGS) -o wpa_supplicant $(OBJS) $(LIBS) $(EXTRALIBS) @$(E) " LD " $@ -@@ -2214,6 +2237,12 @@ eap_gpsk.so: $(SRC_EAP_GPSK) +@@ -2216,6 +2239,12 @@ eap_gpsk.so: $(SRC_EAP_GPSK) $(Q)sed -e 's|\@BINDIR\@|$(BINDIR)|g' $< >$@ @$(E) " sed" $< @@ -278,7 +278,7 @@ This allows building both hostapd and wpa_supplicant as a single binary os_memset(&eapol_test, 0, sizeof(eapol_test)); --- a/wpa_supplicant/events.c +++ b/wpa_supplicant/events.c -@@ -6170,8 +6170,8 @@ static int wpas_pasn_auth(struct wpa_sup +@@ -6175,8 +6175,8 @@ static int wpas_pasn_auth(struct wpa_sup #endif /* CONFIG_PASN */ @@ -289,7 +289,7 @@ This allows building both hostapd and wpa_supplicant as a single binary { struct wpa_supplicant *wpa_s = ctx; int resched; -@@ -7134,7 +7134,7 @@ void wpa_supplicant_event(void *ctx, enu +@@ -7139,7 +7139,7 @@ void wpa_supplicant_event(void *ctx, enu } @@ -331,7 +331,7 @@ This allows building both hostapd and wpa_supplicant as a single binary os_memset(&global, 0, sizeof(global)); --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -8062,7 +8062,6 @@ struct wpa_interface * wpa_supplicant_ma +@@ -8100,7 +8100,6 @@ struct wpa_interface * wpa_supplicant_ma return NULL; } @@ -339,7 +339,7 @@ This allows building both hostapd and wpa_supplicant as a single binary /** * wpa_supplicant_match_existing - Match existing interfaces * @global: Pointer to global data from wpa_supplicant_init() -@@ -8097,6 +8096,11 @@ static int wpa_supplicant_match_existing +@@ -8135,6 +8134,11 @@ static int wpa_supplicant_match_existing #endif /* CONFIG_MATCH_IFACE */ @@ -351,7 +351,7 @@ This allows building both hostapd and wpa_supplicant as a single binary /** * wpa_supplicant_add_iface - Add a new network interface -@@ -8353,6 +8357,8 @@ struct wpa_global * wpa_supplicant_init( +@@ -8391,6 +8395,8 @@ struct wpa_global * wpa_supplicant_init( #ifndef CONFIG_NO_WPA_MSG wpa_msg_register_ifname_cb(wpa_supplicant_msg_ifname_cb); #endif /* CONFIG_NO_WPA_MSG */ diff --git a/package/network/services/hostapd/patches/201-lto-jobserver-support.patch b/package/network/services/hostapd/patches/201-lto-jobserver-support.patch index 7911071e0f..531852cf21 100644 --- a/package/network/services/hostapd/patches/201-lto-jobserver-support.patch +++ b/package/network/services/hostapd/patches/201-lto-jobserver-support.patch @@ -25,7 +25,7 @@ Subject: [PATCH] hostapd: build with LTO enabled (using jobserver for parallel NOBJS = nt_password_hash.o ../src/crypto/ms_funcs.o $(SHA1OBJS) --- a/wpa_supplicant/Makefile +++ b/wpa_supplicant/Makefile -@@ -2106,31 +2106,31 @@ wpa_supplicant_multi.a: .config $(BCHECK +@@ -2108,31 +2108,31 @@ wpa_supplicant_multi.a: .config $(BCHECK @$(AR) cr $@ wpa_supplicant_multi.o $(OBJS) wpa_supplicant: $(BCHECK) $(OBJS) $(EXTRA_progs) diff --git a/package/network/services/hostapd/patches/211-ctrl-make-WNM_AP-functions-dependant-on-CONFIG_AP.patch b/package/network/services/hostapd/patches/211-ctrl-make-WNM_AP-functions-dependant-on-CONFIG_AP.patch index f7d3984c60..4e67a0a56c 100644 --- a/package/network/services/hostapd/patches/211-ctrl-make-WNM_AP-functions-dependant-on-CONFIG_AP.patch +++ b/package/network/services/hostapd/patches/211-ctrl-make-WNM_AP-functions-dependant-on-CONFIG_AP.patch @@ -13,7 +13,7 @@ Signed-off-by: David Bauer --- a/wpa_supplicant/ctrl_iface.c +++ b/wpa_supplicant/ctrl_iface.c -@@ -13566,7 +13566,7 @@ char * wpa_supplicant_ctrl_iface_process +@@ -13513,7 +13513,7 @@ char * wpa_supplicant_ctrl_iface_process if (wpas_ctrl_iface_coloc_intf_report(wpa_s, buf + 18)) reply_len = -1; #endif /* CONFIG_WNM */ @@ -22,7 +22,7 @@ Signed-off-by: David Bauer } else if (os_strncmp(buf, "DISASSOC_IMMINENT ", 18) == 0) { if (ap_ctrl_iface_disassoc_imminent(wpa_s, buf + 18)) reply_len = -1; -@@ -13576,7 +13576,7 @@ char * wpa_supplicant_ctrl_iface_process +@@ -13523,7 +13523,7 @@ char * wpa_supplicant_ctrl_iface_process } else if (os_strncmp(buf, "BSS_TM_REQ ", 11) == 0) { if (ap_ctrl_iface_bss_tm_req(wpa_s, buf + 11)) reply_len = -1; diff --git a/package/network/services/hostapd/patches/212-Move-definition-of-WLAN_SUPP_RATES_MAX-to-defs.h.patch b/package/network/services/hostapd/patches/212-Move-definition-of-WLAN_SUPP_RATES_MAX-to-defs.h.patch index 2961749c39..cb3bea7771 100644 --- a/package/network/services/hostapd/patches/212-Move-definition-of-WLAN_SUPP_RATES_MAX-to-defs.h.patch +++ b/package/network/services/hostapd/patches/212-Move-definition-of-WLAN_SUPP_RATES_MAX-to-defs.h.patch @@ -43,7 +43,7 @@ Signed-off-by: Eneas U de Queiroz struct mbo_non_pref_chan_info { --- a/src/common/defs.h +++ b/src/common/defs.h -@@ -63,6 +63,10 @@ +@@ -62,6 +62,10 @@ WPA_KEY_MGMT_FT_FILS_SHA256 | \ WPA_KEY_MGMT_FT_FILS_SHA384) diff --git a/package/network/services/hostapd/patches/252-disable_ctrl_iface_mib.patch b/package/network/services/hostapd/patches/252-disable_ctrl_iface_mib.patch index c5cf70d54d..eec53455b0 100644 --- a/package/network/services/hostapd/patches/252-disable_ctrl_iface_mib.patch +++ b/package/network/services/hostapd/patches/252-disable_ctrl_iface_mib.patch @@ -16,7 +16,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality else --- a/hostapd/ctrl_iface.c +++ b/hostapd/ctrl_iface.c -@@ -4087,6 +4087,7 @@ static int hostapd_ctrl_iface_receive_pr +@@ -4063,6 +4063,7 @@ static int hostapd_ctrl_iface_receive_pr reply_size); } else if (os_strcmp(buf, "STATUS-DRIVER") == 0) { reply_len = hostapd_drv_status(hapd, reply, reply_size); @@ -24,7 +24,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality } else if (os_strcmp(buf, "MIB") == 0) { reply_len = ieee802_11_get_mib(hapd, reply, reply_size); if (reply_len >= 0) { -@@ -4128,6 +4129,7 @@ static int hostapd_ctrl_iface_receive_pr +@@ -4104,6 +4105,7 @@ static int hostapd_ctrl_iface_receive_pr } else if (os_strncmp(buf, "STA-NEXT ", 9) == 0) { reply_len = hostapd_ctrl_iface_sta_next(hapd, buf + 9, reply, reply_size); @@ -113,7 +113,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality if (os_snprintf_error(buflen - len, ret)) --- a/src/ap/ieee802_1x.c +++ b/src/ap/ieee802_1x.c -@@ -2867,6 +2867,7 @@ static const char * bool_txt(bool val) +@@ -2831,6 +2831,7 @@ static const char * bool_txt(bool val) return val ? "TRUE" : "FALSE"; } @@ -121,7 +121,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality int ieee802_1x_get_mib(struct hostapd_data *hapd, char *buf, size_t buflen) { -@@ -3053,6 +3054,7 @@ int ieee802_1x_get_mib_sta(struct hostap +@@ -3017,6 +3018,7 @@ int ieee802_1x_get_mib_sta(struct hostap return len; } @@ -131,7 +131,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality static void ieee802_1x_wnm_notif_send(void *eloop_ctx, void *timeout_ctx) --- a/src/ap/wpa_auth.c +++ b/src/ap/wpa_auth.c -@@ -6178,6 +6178,7 @@ static const char * wpa_bool_txt(int val +@@ -6233,6 +6233,7 @@ static const char * wpa_bool_txt(int val return val ? "TRUE" : "FALSE"; } @@ -139,7 +139,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality #define RSN_SUITE "%02x-%02x-%02x-%d" #define RSN_SUITE_ARG(s) \ -@@ -6330,7 +6331,7 @@ int wpa_get_mib_sta(struct wpa_state_mac +@@ -6385,7 +6386,7 @@ int wpa_get_mib_sta(struct wpa_state_mac return len; } @@ -150,7 +150,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality { --- a/src/rsn_supp/wpa.c +++ b/src/rsn_supp/wpa.c -@@ -4195,6 +4195,8 @@ static u32 wpa_key_mgmt_suite(struct wpa +@@ -4189,6 +4189,8 @@ static u32 wpa_key_mgmt_suite(struct wpa } @@ -159,7 +159,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality #define RSN_SUITE "%02x-%02x-%02x-%d" #define RSN_SUITE_ARG(s) \ ((s) >> 24) & 0xff, ((s) >> 16) & 0xff, ((s) >> 8) & 0xff, (s) & 0xff -@@ -4276,6 +4278,7 @@ int wpa_sm_get_mib(struct wpa_sm *sm, ch +@@ -4270,6 +4272,7 @@ int wpa_sm_get_mib(struct wpa_sm *sm, ch return (int) len; } @@ -169,7 +169,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality --- a/wpa_supplicant/Makefile +++ b/wpa_supplicant/Makefile -@@ -1040,6 +1040,9 @@ ifdef CONFIG_FILS +@@ -1042,6 +1042,9 @@ ifdef CONFIG_FILS OBJS += ../src/ap/fils_hlp.o endif ifdef CONFIG_CTRL_IFACE @@ -192,7 +192,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality char *buf, size_t buflen) --- a/wpa_supplicant/ctrl_iface.c +++ b/wpa_supplicant/ctrl_iface.c -@@ -2357,7 +2357,7 @@ static int wpa_supplicant_ctrl_iface_sta +@@ -2374,7 +2374,7 @@ static int wpa_supplicant_ctrl_iface_sta pos += ret; } @@ -201,7 +201,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality if (wpa_s->ap_iface) { pos += ap_ctrl_iface_wpa_get_status(wpa_s, pos, end - pos, -@@ -12876,6 +12876,7 @@ char * wpa_supplicant_ctrl_iface_process +@@ -12842,6 +12842,7 @@ char * wpa_supplicant_ctrl_iface_process reply_len = -1; } else if (os_strncmp(buf, "NOTE ", 5) == 0) { wpa_printf(MSG_INFO, "NOTE: %s", buf + 5); @@ -209,7 +209,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality } else if (os_strcmp(buf, "MIB") == 0) { reply_len = wpa_sm_get_mib(wpa_s->wpa, reply, reply_size); if (reply_len >= 0) { -@@ -12888,6 +12889,7 @@ char * wpa_supplicant_ctrl_iface_process +@@ -12854,6 +12855,7 @@ char * wpa_supplicant_ctrl_iface_process reply_size - reply_len); #endif /* CONFIG_MACSEC */ } @@ -217,7 +217,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality } else if (os_strncmp(buf, "STATUS", 6) == 0) { reply_len = wpa_supplicant_ctrl_iface_status( wpa_s, buf + 6, reply, reply_size); -@@ -13394,6 +13396,7 @@ char * wpa_supplicant_ctrl_iface_process +@@ -13341,6 +13343,7 @@ char * wpa_supplicant_ctrl_iface_process reply_len = wpa_supplicant_ctrl_iface_bss( wpa_s, buf + 4, reply, reply_size); #ifdef CONFIG_AP @@ -225,7 +225,7 @@ Subject: [PATCH] Remove some unnecessary control interface functionality } else if (os_strcmp(buf, "STA-FIRST") == 0) { reply_len = ap_ctrl_iface_sta_first(wpa_s, reply, reply_size); } else if (os_strncmp(buf, "STA ", 4) == 0) { -@@ -13402,12 +13405,15 @@ char * wpa_supplicant_ctrl_iface_process +@@ -13349,12 +13352,15 @@ char * wpa_supplicant_ctrl_iface_process } else if (os_strncmp(buf, "STA-NEXT ", 9) == 0) { reply_len = ap_ctrl_iface_sta_next(wpa_s, buf + 9, reply, reply_size); diff --git a/package/network/services/hostapd/patches/300-noscan.patch b/package/network/services/hostapd/patches/300-noscan.patch index ebedb2603c..6d97691855 100644 --- a/package/network/services/hostapd/patches/300-noscan.patch +++ b/package/network/services/hostapd/patches/300-noscan.patch @@ -5,7 +5,7 @@ Subject: [PATCH] Add noscan, no_ht_coex config options --- a/hostapd/config_file.c +++ b/hostapd/config_file.c -@@ -3747,6 +3747,10 @@ static int hostapd_config_fill(struct ho +@@ -3518,6 +3518,10 @@ static int hostapd_config_fill(struct ho if (bss->ocv && !bss->ieee80211w) bss->ieee80211w = 1; #endif /* CONFIG_OCV */ @@ -18,7 +18,7 @@ Subject: [PATCH] Add noscan, no_ht_coex config options } else if (os_strcmp(buf, "ht_capab") == 0) { --- a/src/ap/ap_config.h +++ b/src/ap/ap_config.h -@@ -1125,6 +1125,8 @@ struct hostapd_config { +@@ -1105,6 +1105,8 @@ struct hostapd_config { int ht_op_mode_fixed; u16 ht_capab; diff --git a/package/network/services/hostapd/patches/301-mesh-noscan.patch b/package/network/services/hostapd/patches/301-mesh-noscan.patch index 175b76c60b..1c2eedda42 100644 --- a/package/network/services/hostapd/patches/301-mesh-noscan.patch +++ b/package/network/services/hostapd/patches/301-mesh-noscan.patch @@ -5,7 +5,7 @@ Subject: [PATCH] Allow HT40 also on 2.4GHz if noscan option is set, which also --- a/wpa_supplicant/config.c +++ b/wpa_supplicant/config.c -@@ -2668,6 +2668,7 @@ static const struct parse_data ssid_fiel +@@ -2642,6 +2642,7 @@ static const struct parse_data ssid_fiel #else /* CONFIG_MESH */ { INT_RANGE(mode, 0, 4) }, #endif /* CONFIG_MESH */ @@ -15,17 +15,17 @@ Subject: [PATCH] Allow HT40 also on 2.4GHz if noscan option is set, which also { STR(id_str) }, --- a/wpa_supplicant/config_file.c +++ b/wpa_supplicant/config_file.c -@@ -867,6 +867,7 @@ static void wpa_config_write_network(FIL - #endif /* IEEE8021X_EAPOL */ +@@ -868,6 +868,7 @@ static void wpa_config_write_network(FIL INT(mode); + #ifdef CONFIG_MESH INT(no_auto_peer); + INT(noscan); INT_DEF(mesh_fwding, DEFAULT_MESH_FWDING); + #endif /* CONFIG_MESH */ INT(frequency); - INT(enable_edmg); --- a/wpa_supplicant/config_ssid.h +++ b/wpa_supplicant/config_ssid.h -@@ -1063,6 +1063,8 @@ struct wpa_ssid { +@@ -1071,6 +1071,8 @@ struct wpa_ssid { */ int no_auto_peer; @@ -36,7 +36,7 @@ Subject: [PATCH] Allow HT40 also on 2.4GHz if noscan option is set, which also * --- a/wpa_supplicant/mesh.c +++ b/wpa_supplicant/mesh.c -@@ -509,6 +509,8 @@ static int wpa_supplicant_mesh_init(stru +@@ -538,6 +538,8 @@ static int wpa_supplicant_mesh_init(stru frequency); goto out_free; } @@ -47,7 +47,7 @@ Subject: [PATCH] Allow HT40 also on 2.4GHz if noscan option is set, which also /* --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -3044,7 +3044,7 @@ static bool ibss_mesh_can_use_vht(struct +@@ -3035,7 +3035,7 @@ static bool ibss_mesh_can_use_vht(struct const struct wpa_ssid *ssid, struct hostapd_hw_modes *mode) { @@ -56,16 +56,16 @@ Subject: [PATCH] Allow HT40 also on 2.4GHz if noscan option is set, which also return false; if (!drv_supports_vht(wpa_s, ssid)) -@@ -3117,7 +3117,7 @@ static void ibss_mesh_select_40mhz(struc +@@ -3109,7 +3109,7 @@ static void ibss_mesh_select_40mhz(struc int i, res; unsigned int j; - static const int ht40plus[] = { + static const int ht40plus_5ghz[] = { - 36, 44, 52, 60, 100, 108, 116, 124, 132, 140, + 1, 2, 3, 4, 5, 6, 7, 36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173, 184, 192 }; - int ht40 = -1; -@@ -3414,7 +3414,7 @@ void ibss_mesh_setup_freq(struct wpa_sup + static const int ht40plus_6ghz[] = { +@@ -3462,7 +3462,7 @@ void ibss_mesh_setup_freq(struct wpa_sup int ieee80211_mode = wpas_mode_to_ieee80211_mode(ssid->mode); enum hostapd_hw_mode hw_mode; struct hostapd_hw_modes *mode = NULL; @@ -74,12 +74,12 @@ Subject: [PATCH] Allow HT40 also on 2.4GHz if noscan option is set, which also u8 channel; bool is_6ghz, is_24ghz; bool dfs_enabled = wpa_s->conf->country[0] && (wpa_s->drv_flags & WPA_DRIVER_FLAGS_RADAR); -@@ -3458,6 +3458,8 @@ void ibss_mesh_setup_freq(struct wpa_sup +@@ -3506,6 +3506,8 @@ void ibss_mesh_setup_freq(struct wpa_sup freq->he_enabled = ibss_mesh_can_use_he(wpa_s, ssid, mode, ieee80211_mode); freq->channel = channel; + if (mode->mode == HOSTAPD_MODE_IEEE80211G && ssid->noscan) -+ ibss_mesh_select_40mhz(wpa_s, ssid, mode, freq, obss_scan, dfs_enabled); - /* Setup higher BW only for 5 GHz */ ++ ibss_mesh_select_40mhz(wpa_s, ssid, mode, freq, obss_scan, is_6ghz, dfs_enabled); + /* Setup higher BW only for 5 and 6 GHz */ if (mode->mode == HOSTAPD_MODE_IEEE80211A) { - ibss_mesh_select_40mhz(wpa_s, ssid, mode, freq, obss_scan, dfs_enabled); + ibss_mesh_select_40mhz(wpa_s, ssid, mode, freq, obss_scan, diff --git a/package/network/services/hostapd/patches/310-rescan_immediately.patch b/package/network/services/hostapd/patches/310-rescan_immediately.patch index 83b616116f..15c74a71ae 100644 --- a/package/network/services/hostapd/patches/310-rescan_immediately.patch +++ b/package/network/services/hostapd/patches/310-rescan_immediately.patch @@ -5,7 +5,7 @@ Subject: [PATCH] rescan_immediately.patch --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -6342,7 +6342,7 @@ wpa_supplicant_alloc(struct wpa_supplica +@@ -6381,7 +6381,7 @@ wpa_supplicant_alloc(struct wpa_supplica if (wpa_s == NULL) return NULL; wpa_s->scan_req = INITIAL_SCAN_REQ; diff --git a/package/network/services/hostapd/patches/350-nl80211_del_beacon_bss.patch b/package/network/services/hostapd/patches/350-nl80211_del_beacon_bss.patch index 6b3baea558..814b15f819 100644 --- a/package/network/services/hostapd/patches/350-nl80211_del_beacon_bss.patch +++ b/package/network/services/hostapd/patches/350-nl80211_del_beacon_bss.patch @@ -4,8 +4,8 @@ Subject: [PATCH] nl80211_del_beacon_bss.patch --- a/src/drivers/driver_nl80211.c +++ b/src/drivers/driver_nl80211.c -@@ -6381,8 +6381,7 @@ static void nl80211_teardown_ap(struct i - nl80211_mgmt_unsubscribe(bss, "AP teardown"); +@@ -6340,8 +6340,7 @@ static void nl80211_teardown_ap(struct i + } nl80211_put_wiphy_data_ap(bss); - if (bss->flink) diff --git a/package/network/services/hostapd/patches/360-acs_retry.patch b/package/network/services/hostapd/patches/360-acs_retry.patch new file mode 100644 index 0000000000..e858ac24e7 --- /dev/null +++ b/package/network/services/hostapd/patches/360-acs_retry.patch @@ -0,0 +1,23 @@ +--- a/src/ap/acs.h ++++ b/src/ap/acs.h +@@ -15,7 +15,7 @@ + enum hostapd_chan_status acs_init(struct hostapd_iface *iface); + void acs_cleanup(struct hostapd_iface *iface); + +-#define ACS_SCAN_RETRY_MAX_COUNT 15 ++#define ACS_SCAN_RETRY_MAX_COUNT 50 + #define ACS_SCAN_RETRY_INTERVAL 5 + + #else /* CONFIG_ACS */ +--- a/src/drivers/driver_nl80211_scan.c ++++ b/src/drivers/driver_nl80211_scan.c +@@ -455,6 +455,9 @@ int wpa_driver_nl80211_scan(struct i802_ + } + #endif /* CONFIG_IEEE80211BE */ + ++ if (ret == -EBUSY) ++ goto fail; ++ + /* + * mac80211 does not allow scan requests in AP mode, so + * try to do this in station mode. diff --git a/package/network/services/hostapd/patches/460-wpa_supplicant-add-new-config-params-to-be-used-with.patch b/package/network/services/hostapd/patches/460-wpa_supplicant-add-new-config-params-to-be-used-with.patch index bedac7f606..e22da80341 100644 --- a/package/network/services/hostapd/patches/460-wpa_supplicant-add-new-config-params-to-be-used-with.patch +++ b/package/network/services/hostapd/patches/460-wpa_supplicant-add-new-config-params-to-be-used-with.patch @@ -14,7 +14,7 @@ Signed-hostap: Antonio Quartulli --- a/src/drivers/driver.h +++ b/src/drivers/driver.h -@@ -1012,6 +1012,9 @@ struct wpa_driver_associate_params { +@@ -1018,6 +1018,9 @@ struct wpa_driver_associate_params { * responsible for selecting with which BSS to associate. */ const u8 *bssid; @@ -34,7 +34,7 @@ Signed-hostap: Antonio Quartulli #include "config.h" -@@ -2449,6 +2450,97 @@ static char * wpa_config_write_mac_value +@@ -2423,6 +2424,97 @@ static char * wpa_config_write_mac_value #endif /* NO_CONFIG_WRITE */ @@ -132,7 +132,7 @@ Signed-hostap: Antonio Quartulli /* Helper macros for network block parser */ #ifdef OFFSET -@@ -2744,6 +2836,8 @@ static const struct parse_data ssid_fiel +@@ -2718,6 +2810,8 @@ static const struct parse_data ssid_fiel { INT(ap_max_inactivity) }, { INT(dtim_period) }, { INT(beacon_int) }, @@ -155,7 +155,7 @@ Signed-hostap: Antonio Quartulli * macsec_policy - Determines the policy for MACsec secure session --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -4635,6 +4635,12 @@ static void wpas_start_assoc_cb(struct w +@@ -4674,6 +4674,12 @@ static void wpas_start_assoc_cb(struct w params.beacon_int = ssid->beacon_int; else params.beacon_int = wpa_s->conf->beacon_int; diff --git a/package/network/services/hostapd/patches/463-add-mcast_rate-to-11s.patch b/package/network/services/hostapd/patches/463-add-mcast_rate-to-11s.patch index b30e0409a6..917b4ac3b6 100644 --- a/package/network/services/hostapd/patches/463-add-mcast_rate-to-11s.patch +++ b/package/network/services/hostapd/patches/463-add-mcast_rate-to-11s.patch @@ -19,7 +19,7 @@ Tested-by: Simon Wunderlich --- a/src/drivers/driver.h +++ b/src/drivers/driver.h -@@ -1932,6 +1932,7 @@ struct wpa_driver_mesh_join_params { +@@ -1959,6 +1959,7 @@ struct wpa_driver_mesh_join_params { #define WPA_DRIVER_MESH_FLAG_AMPE 0x00000008 unsigned int flags; bool handle_dfs; @@ -29,7 +29,7 @@ Tested-by: Simon Wunderlich struct wpa_driver_set_key_params { --- a/src/drivers/driver_nl80211.c +++ b/src/drivers/driver_nl80211.c -@@ -12333,6 +12333,18 @@ static int nl80211_put_mesh_id(struct nl +@@ -12269,6 +12269,18 @@ static int nl80211_put_mesh_id(struct nl } @@ -48,7 +48,7 @@ Tested-by: Simon Wunderlich static int nl80211_put_mesh_config(struct nl_msg *msg, struct wpa_driver_mesh_bss_params *params) { -@@ -12394,6 +12406,7 @@ static int nl80211_join_mesh(struct i802 +@@ -12330,6 +12342,7 @@ static int nl80211_join_mesh(struct i802 nl80211_put_basic_rates(msg, params->basic_rates) || nl80211_put_mesh_id(msg, params->meshid, params->meshid_len) || nl80211_put_beacon_int(msg, params->beacon_int) || @@ -58,7 +58,7 @@ Tested-by: Simon Wunderlich --- a/wpa_supplicant/mesh.c +++ b/wpa_supplicant/mesh.c -@@ -636,6 +636,7 @@ int wpa_supplicant_join_mesh(struct wpa_ +@@ -665,6 +665,7 @@ int wpa_supplicant_join_mesh(struct wpa_ params->meshid = ssid->ssid; params->meshid_len = ssid->ssid_len; diff --git a/package/network/services/hostapd/patches/464-fix-mesh-obss-check.patch b/package/network/services/hostapd/patches/464-fix-mesh-obss-check.patch index 1975c2b178..a60397ce12 100644 --- a/package/network/services/hostapd/patches/464-fix-mesh-obss-check.patch +++ b/package/network/services/hostapd/patches/464-fix-mesh-obss-check.patch @@ -5,7 +5,7 @@ Subject: [PATCH] Fix issues with disabling obss scan when using fixed_freq on --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -3421,6 +3421,10 @@ void ibss_mesh_setup_freq(struct wpa_sup +@@ -3469,6 +3469,10 @@ void ibss_mesh_setup_freq(struct wpa_sup freq->freq = ssid->frequency; diff --git a/package/network/services/hostapd/patches/465-hostapd-config-support-random-BSS-color.patch b/package/network/services/hostapd/patches/465-hostapd-config-support-random-BSS-color.patch index 1696202445..d14a4c63f7 100644 --- a/package/network/services/hostapd/patches/465-hostapd-config-support-random-BSS-color.patch +++ b/package/network/services/hostapd/patches/465-hostapd-config-support-random-BSS-color.patch @@ -13,7 +13,7 @@ Signed-off-by: David Bauer --- a/hostapd/config_file.c +++ b/hostapd/config_file.c -@@ -3801,6 +3801,8 @@ static int hostapd_config_fill(struct ho +@@ -3572,6 +3572,8 @@ static int hostapd_config_fill(struct ho } else if (os_strcmp(buf, "he_bss_color") == 0) { conf->he_op.he_bss_color = atoi(pos) & 0x3f; conf->he_op.he_bss_color_disabled = 0; diff --git a/package/network/services/hostapd/patches/600-ubus_support.patch b/package/network/services/hostapd/patches/600-ubus_support.patch index 9310fd2d15..90560b2124 100644 --- a/package/network/services/hostapd/patches/600-ubus_support.patch +++ b/package/network/services/hostapd/patches/600-ubus_support.patch @@ -53,7 +53,7 @@ probe/assoc/auth requests via object subscribe. } --- a/src/ap/beacon.c +++ b/src/ap/beacon.c -@@ -1437,6 +1437,12 @@ void handle_probe_req(struct hostapd_dat +@@ -1438,6 +1438,12 @@ void handle_probe_req(struct hostapd_dat int mld_id; u16 links; #endif /* CONFIG_IEEE80211BE */ @@ -66,7 +66,7 @@ probe/assoc/auth requests via object subscribe. if (hapd->iconf->rssi_ignore_probe_request && ssi_signal && ssi_signal < hapd->iconf->rssi_ignore_probe_request) -@@ -1623,6 +1629,12 @@ void handle_probe_req(struct hostapd_dat +@@ -1624,6 +1630,12 @@ void handle_probe_req(struct hostapd_dat } #endif /* CONFIG_P2P */ @@ -92,7 +92,7 @@ probe/assoc/auth requests via object subscribe. return 0; --- a/src/ap/drv_callbacks.c +++ b/src/ap/drv_callbacks.c -@@ -317,6 +317,10 @@ int hostapd_notif_assoc(struct hostapd_d +@@ -330,6 +330,10 @@ int hostapd_notif_assoc(struct hostapd_d struct hostapd_iface *iface = hapd->iface; #endif /* CONFIG_OWE */ bool updated = false; @@ -103,7 +103,7 @@ probe/assoc/auth requests via object subscribe. if (addr == NULL) { /* -@@ -461,6 +465,12 @@ int hostapd_notif_assoc(struct hostapd_d +@@ -468,6 +472,12 @@ int hostapd_notif_assoc(struct hostapd_d goto fail; } @@ -116,7 +116,7 @@ probe/assoc/auth requests via object subscribe. #ifdef CONFIG_P2P if (elems.p2p) { wpabuf_free(sta->p2p_ie); -@@ -1385,6 +1395,7 @@ void hostapd_event_ch_switch(struct host +@@ -1371,6 +1381,7 @@ void hostapd_event_ch_switch(struct host wpa_msg(hapd->msg_ctx, MSG_INFO, AP_CSA_FINISHED "freq=%d dfs=%d", freq, is_dfs); @@ -159,7 +159,7 @@ probe/assoc/auth requests via object subscribe. if (iface->is_no_ir) { hostapd_set_state(iface, HAPD_IFACE_NO_IR); -@@ -3501,6 +3506,7 @@ void hostapd_interface_deinit_free(struc +@@ -3517,6 +3522,7 @@ void hostapd_interface_deinit_free(struc (unsigned int) iface->conf->num_bss); driver = iface->bss[0]->driver; drv_priv = iface->bss[0]->drv_priv; @@ -195,7 +195,7 @@ probe/assoc/auth requests via object subscribe. struct hostapd_iface * hostapd_alloc_iface(void); --- a/src/ap/ieee802_11.c +++ b/src/ap/ieee802_11.c -@@ -2941,7 +2941,7 @@ static void handle_auth(struct hostapd_d +@@ -3091,7 +3091,7 @@ static void handle_auth(struct hostapd_d u16 auth_alg, auth_transaction, status_code; u16 resp = WLAN_STATUS_SUCCESS; struct sta_info *sta = NULL; @@ -204,7 +204,7 @@ probe/assoc/auth requests via object subscribe. u16 fc; const u8 *challenge = NULL; u8 resp_ies[2 + WLAN_AUTH_CHALLENGE_LEN]; -@@ -2952,6 +2952,11 @@ static void handle_auth(struct hostapd_d +@@ -3102,6 +3102,11 @@ static void handle_auth(struct hostapd_d #ifdef CONFIG_IEEE80211BE bool mld_sta = false; #endif /* CONFIG_IEEE80211BE */ @@ -216,7 +216,7 @@ probe/assoc/auth requests via object subscribe. if (len < IEEE80211_HDRLEN + sizeof(mgmt->u.auth)) { wpa_printf(MSG_INFO, "handle_auth - too short payload (len=%lu)", -@@ -3148,6 +3153,13 @@ static void handle_auth(struct hostapd_d +@@ -3298,6 +3303,13 @@ static void handle_auth(struct hostapd_d resp = WLAN_STATUS_UNSPECIFIED_FAILURE; goto fail; } @@ -230,7 +230,7 @@ probe/assoc/auth requests via object subscribe. if (res == HOSTAPD_ACL_PENDING) return; -@@ -5477,7 +5489,7 @@ static void handle_assoc(struct hostapd_ +@@ -5616,7 +5628,7 @@ static void handle_assoc(struct hostapd_ int resp = WLAN_STATUS_SUCCESS; u16 reply_res = WLAN_STATUS_UNSPECIFIED_FAILURE; const u8 *pos; @@ -239,7 +239,7 @@ probe/assoc/auth requests via object subscribe. struct sta_info *sta; u8 *tmp = NULL; #ifdef CONFIG_FILS -@@ -5719,6 +5731,11 @@ static void handle_assoc(struct hostapd_ +@@ -5858,6 +5870,11 @@ static void handle_assoc(struct hostapd_ left = res; } #endif /* CONFIG_FILS */ @@ -251,7 +251,7 @@ probe/assoc/auth requests via object subscribe. /* followed by SSID and Supported rates; and HT capabilities if 802.11n * is used */ -@@ -5826,6 +5843,13 @@ static void handle_assoc(struct hostapd_ +@@ -5965,6 +5982,13 @@ static void handle_assoc(struct hostapd_ if (set_beacon) ieee802_11_update_beacons(hapd->iface); @@ -265,7 +265,7 @@ probe/assoc/auth requests via object subscribe. fail: /* -@@ -6055,6 +6079,7 @@ static void handle_disassoc(struct hosta +@@ -6194,6 +6218,7 @@ static void handle_disassoc(struct hosta (unsigned long) len); return; } @@ -273,7 +273,7 @@ probe/assoc/auth requests via object subscribe. sta = ap_get_sta(hapd, mgmt->sa); if (!sta) { -@@ -6086,6 +6111,8 @@ static void handle_deauth(struct hostapd +@@ -6225,6 +6250,8 @@ static void handle_deauth(struct hostapd /* Clear the PTKSA cache entries for PASN */ ptksa_cache_flush(hapd->ptksa, mgmt->sa, WPA_CIPHER_NONE); @@ -305,7 +305,7 @@ probe/assoc/auth requests via object subscribe. wpa_printf(MSG_DEBUG, "RRM action %u is not supported", --- a/src/ap/sta_info.c +++ b/src/ap/sta_info.c -@@ -543,6 +543,7 @@ void ap_handle_timer(void *eloop_ctx, vo +@@ -544,6 +544,7 @@ void ap_handle_timer(void *eloop_ctx, vo hostapd_logger(hapd, sta->addr, HOSTAPD_MODULE_IEEE80211, HOSTAPD_LEVEL_INFO, "deauthenticated due to " "local deauth request"); @@ -313,7 +313,7 @@ probe/assoc/auth requests via object subscribe. ap_free_sta(hapd, sta); return; } -@@ -700,6 +701,7 @@ skip_poll: +@@ -701,6 +702,7 @@ skip_poll: mlme_deauthenticate_indication( hapd, sta, WLAN_REASON_PREV_AUTH_NOT_VALID); @@ -321,7 +321,7 @@ probe/assoc/auth requests via object subscribe. ap_free_sta(hapd, sta); break; } -@@ -1588,15 +1590,28 @@ void ap_sta_set_authorized_event(struct +@@ -1589,15 +1591,28 @@ void ap_sta_set_authorized_event(struct os_snprintf(buf, sizeof(buf), MACSTR, MAC2STR(sta->addr)); if (authorized) { @@ -350,7 +350,7 @@ probe/assoc/auth requests via object subscribe. #ifdef CONFIG_P2P if (wpa_auth_get_ip_addr(sta->wpa_sm, ip_addr_buf) == 0) { os_snprintf(ip_addr, sizeof(ip_addr), -@@ -1607,6 +1622,13 @@ void ap_sta_set_authorized_event(struct +@@ -1608,6 +1623,13 @@ void ap_sta_set_authorized_event(struct } #endif /* CONFIG_P2P */ @@ -364,7 +364,7 @@ probe/assoc/auth requests via object subscribe. keyid = ap_sta_wpa_get_keyid(hapd, sta); if (keyid) { os_snprintf(keyid_buf, sizeof(keyid_buf), -@@ -1625,17 +1647,19 @@ void ap_sta_set_authorized_event(struct +@@ -1626,17 +1648,19 @@ void ap_sta_set_authorized_event(struct dpp_pkhash, SHA256_MAC_LEN); } @@ -390,7 +390,7 @@ probe/assoc/auth requests via object subscribe. hapd->msg_ctx_parent != hapd->msg_ctx) --- a/src/ap/sta_info.h +++ b/src/ap/sta_info.h -@@ -305,6 +305,7 @@ struct sta_info { +@@ -302,6 +302,7 @@ struct sta_info { #endif /* CONFIG_TESTING_OPTIONS */ #ifdef CONFIG_AIRTIME_POLICY unsigned int airtime_weight; @@ -478,7 +478,7 @@ probe/assoc/auth requests via object subscribe. } --- a/src/ap/wpa_auth_glue.c +++ b/src/ap/wpa_auth_glue.c -@@ -331,6 +331,7 @@ static void hostapd_wpa_auth_psk_failure +@@ -320,6 +320,7 @@ static void hostapd_wpa_auth_psk_failure struct hostapd_data *hapd = ctx; wpa_msg(hapd->msg_ctx, MSG_INFO, AP_STA_POSSIBLE_PSK_MISMATCH MACSTR, MAC2STR(addr)); @@ -650,7 +650,7 @@ probe/assoc/auth requests via object subscribe. ifdef CONFIG_CODE_COVERAGE CFLAGS += -O0 -fprofile-arcs -ftest-coverage -U_FORTIFY_SOURCE LIBS += -lgcov -@@ -1044,6 +1051,9 @@ ifdef CONFIG_CTRL_IFACE_MIB +@@ -1046,6 +1053,9 @@ ifdef CONFIG_CTRL_IFACE_MIB CFLAGS += -DCONFIG_CTRL_IFACE_MIB endif OBJS += ../src/ap/ctrl_iface_ap.o @@ -683,7 +683,7 @@ probe/assoc/auth requests via object subscribe. break; --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -8195,6 +8195,8 @@ struct wpa_supplicant * wpa_supplicant_a +@@ -8233,6 +8233,8 @@ struct wpa_supplicant * wpa_supplicant_a } #endif /* CONFIG_P2P */ @@ -692,7 +692,7 @@ probe/assoc/auth requests via object subscribe. return wpa_s; } -@@ -8221,6 +8223,8 @@ int wpa_supplicant_remove_iface(struct w +@@ -8259,6 +8261,8 @@ int wpa_supplicant_remove_iface(struct w struct wpa_supplicant *parent = wpa_s->parent; #endif /* CONFIG_MESH */ @@ -701,7 +701,7 @@ probe/assoc/auth requests via object subscribe. /* Remove interface from the global list of interfaces */ prev = global->ifaces; if (prev == wpa_s) { -@@ -8567,8 +8571,12 @@ int wpa_supplicant_run(struct wpa_global +@@ -8605,8 +8609,12 @@ int wpa_supplicant_run(struct wpa_global eloop_register_signal_terminate(wpa_supplicant_terminate, global); eloop_register_signal_reconfig(wpa_supplicant_reconfig, global); @@ -733,7 +733,7 @@ probe/assoc/auth requests via object subscribe. }; -@@ -705,6 +708,7 @@ struct wpa_supplicant { +@@ -696,6 +699,7 @@ struct wpa_supplicant { unsigned char own_addr[ETH_ALEN]; unsigned char perm_addr[ETH_ALEN]; char ifname[100]; diff --git a/package/network/services/hostapd/patches/601-ucode_support.patch b/package/network/services/hostapd/patches/601-ucode_support.patch index cd713ea286..7bf464f2d9 100644 --- a/package/network/services/hostapd/patches/601-ucode_support.patch +++ b/package/network/services/hostapd/patches/601-ucode_support.patch @@ -34,7 +34,7 @@ as adding/removing interfaces. ifdef CONFIG_CODE_COVERAGE --- a/hostapd/ctrl_iface.c +++ b/hostapd/ctrl_iface.c -@@ -6031,6 +6031,7 @@ try_again: +@@ -6004,6 +6004,7 @@ try_again: return -1; } @@ -42,7 +42,7 @@ as adding/removing interfaces. wpa_msg_register_cb(hostapd_ctrl_iface_msg_cb); return 0; -@@ -6132,6 +6133,7 @@ fail: +@@ -6105,6 +6106,7 @@ fail: os_free(fname); interface->global_ctrl_sock = s; @@ -157,7 +157,7 @@ as adding/removing interfaces. { #ifdef CONFIG_OWE /* Check whether the enabled BSS can complete OWE transition mode -@@ -2975,7 +2981,7 @@ hostapd_alloc_bss_data(struct hostapd_if +@@ -2976,7 +2982,7 @@ hostapd_alloc_bss_data(struct hostapd_if } @@ -166,7 +166,7 @@ as adding/removing interfaces. { if (!hapd) return; -@@ -4035,7 +4041,8 @@ int hostapd_remove_iface(struct hapd_int +@@ -4051,7 +4057,8 @@ int hostapd_remove_iface(struct hapd_int hapd_iface = interfaces->iface[i]; if (hapd_iface == NULL) return -1; @@ -232,7 +232,7 @@ as adding/removing interfaces. void hostapd_switch_color(struct hostapd_data *hapd, u64 bitmap); --- a/src/drivers/driver.h +++ b/src/drivers/driver.h -@@ -4003,6 +4003,25 @@ struct wpa_driver_ops { +@@ -4036,6 +4036,25 @@ struct wpa_driver_ops { const char *ifname); /** @@ -258,7 +258,7 @@ as adding/removing interfaces. * set_sta_vlan - Bind a station into a specific interface (AP only) * @priv: Private driver interface data * @ifname: Interface (main or virtual BSS or VLAN) -@@ -6818,6 +6837,7 @@ union wpa_event_data { +@@ -6851,6 +6870,7 @@ union wpa_event_data { /** * struct ch_switch @@ -266,7 +266,7 @@ as adding/removing interfaces. * @freq: Frequency of new channel in MHz * @ht_enabled: Whether this is an HT channel * @ch_offset: Secondary channel offset -@@ -6828,6 +6848,7 @@ union wpa_event_data { +@@ -6861,6 +6881,7 @@ union wpa_event_data { * @punct_bitmap: Puncturing bitmap */ struct ch_switch { @@ -314,7 +314,7 @@ as adding/removing interfaces. err.err = -ENOMEM; s_nl_cb = nl_socket_get_cb(nl_handle); -@@ -546,6 +563,7 @@ int send_and_recv_glb(struct nl80211_glo +@@ -552,6 +569,7 @@ int send_and_recv_glb(struct nl80211_glo err.err_info = err_info; err.drv = drv; @@ -322,7 +322,7 @@ as adding/removing interfaces. nl_cb_err(cb, NL_CB_CUSTOM, error_handler, &err); nl_cb_set(cb, NL_CB_FINISH, NL_CB_CUSTOM, finish_handler, &err.err); if (ack_handler_custom) { -@@ -949,6 +967,7 @@ nl80211_get_wiphy_data_ap(struct i802_bs +@@ -955,6 +973,7 @@ nl80211_get_wiphy_data_ap(struct i802_bs os_free(w); return NULL; } @@ -330,7 +330,7 @@ as adding/removing interfaces. nl_cb_set(w->nl_cb, NL_CB_SEQ_CHECK, NL_CB_CUSTOM, no_seq_check, NULL); nl_cb_set(w->nl_cb, NL_CB_VALID, NL_CB_CUSTOM, -@@ -1364,7 +1383,7 @@ static void wpa_driver_nl80211_event_rtm +@@ -1370,7 +1389,7 @@ static void wpa_driver_nl80211_event_rtm } wpa_printf(MSG_DEBUG, "nl80211: Interface down (%s/%s)", namebuf, ifname); @@ -339,7 +339,7 @@ as adding/removing interfaces. wpa_printf(MSG_DEBUG, "nl80211: Not the main interface (%s) - do not indicate interface down", drv->first_bss->ifname); -@@ -1400,7 +1419,7 @@ static void wpa_driver_nl80211_event_rtm +@@ -1406,7 +1425,7 @@ static void wpa_driver_nl80211_event_rtm } wpa_printf(MSG_DEBUG, "nl80211: Interface up (%s/%s)", namebuf, ifname); @@ -348,7 +348,7 @@ as adding/removing interfaces. wpa_printf(MSG_DEBUG, "nl80211: Not the main interface (%s) - do not indicate interface up", drv->first_bss->ifname); -@@ -2046,6 +2065,7 @@ static int wpa_driver_nl80211_init_nl_gl +@@ -2052,6 +2071,7 @@ static int wpa_driver_nl80211_init_nl_gl genl_family_put(family); nl_cache_free(cache); @@ -356,7 +356,7 @@ as adding/removing interfaces. nl_cb_set(global->nl_cb, NL_CB_SEQ_CHECK, NL_CB_CUSTOM, no_seq_check, NULL); nl_cb_set(global->nl_cb, NL_CB_VALID, NL_CB_CUSTOM, -@@ -2216,6 +2236,7 @@ static int nl80211_init_bss(struct i802_ +@@ -2222,6 +2242,7 @@ static int nl80211_init_bss(struct i802_ if (!bss->nl_cb) return -1; @@ -364,7 +364,7 @@ as adding/removing interfaces. nl_cb_set(bss->nl_cb, NL_CB_SEQ_CHECK, NL_CB_CUSTOM, no_seq_check, NULL); nl_cb_set(bss->nl_cb, NL_CB_VALID, NL_CB_CUSTOM, -@@ -8844,6 +8865,7 @@ static void *i802_init(struct hostapd_da +@@ -8763,6 +8784,7 @@ static void *i802_init(struct hostapd_da char master_ifname[IFNAMSIZ]; int ifindex, br_ifindex = 0; int br_added = 0; @@ -372,7 +372,7 @@ as adding/removing interfaces. bss = wpa_driver_nl80211_drv_init(hapd, params->ifname, params->global_priv, 1, -@@ -8904,21 +8926,17 @@ static void *i802_init(struct hostapd_da +@@ -8823,21 +8845,17 @@ static void *i802_init(struct hostapd_da (params->num_bridge == 0 || !params->bridge[0])) add_ifidx(drv, br_ifindex, drv->ifindex); @@ -404,7 +404,7 @@ as adding/removing interfaces. } if (drv->capa.flags2 & WPA_DRIVER_FLAGS2_CONTROL_PORT_RX) { -@@ -9287,6 +9305,50 @@ static int wpa_driver_nl80211_if_remove( +@@ -9210,6 +9228,50 @@ static int wpa_driver_nl80211_if_remove( return 0; } @@ -455,7 +455,7 @@ as adding/removing interfaces. static int cookie_handler(struct nl_msg *msg, void *arg) { -@@ -11150,6 +11212,37 @@ static bool nl80211_is_drv_shared(void * +@@ -11088,6 +11150,37 @@ static bool nl80211_is_drv_shared(void * #endif /* CONFIG_IEEE80211BE */ @@ -493,7 +493,7 @@ as adding/removing interfaces. static int driver_nl80211_send_mlme(void *priv, const u8 *data, size_t data_len, int noack, unsigned int freq, -@@ -14874,6 +14967,8 @@ const struct wpa_driver_ops wpa_driver_n +@@ -14813,6 +14906,8 @@ const struct wpa_driver_ops wpa_driver_n .set_acl = wpa_driver_nl80211_set_acl, .if_add = wpa_driver_nl80211_if_add, .if_remove = driver_nl80211_if_remove, @@ -504,7 +504,7 @@ as adding/removing interfaces. .sta_add = wpa_driver_nl80211_sta_add, --- a/src/drivers/driver_nl80211_event.c +++ b/src/drivers/driver_nl80211_event.c -@@ -1199,6 +1199,7 @@ static void mlme_event_ch_switch(struct +@@ -1213,6 +1213,7 @@ static void mlme_event_ch_switch(struct struct nlattr *bw, struct nlattr *cf1, struct nlattr *cf2, struct nlattr *punct_bitmap, @@ -512,7 +512,7 @@ as adding/removing interfaces. int finished) { struct i802_bss *bss; -@@ -1262,6 +1263,8 @@ static void mlme_event_ch_switch(struct +@@ -1278,6 +1279,8 @@ static void mlme_event_ch_switch(struct data.ch_switch.cf1 = nla_get_u32(cf1); if (cf2) data.ch_switch.cf2 = nla_get_u32(cf2); @@ -521,7 +521,7 @@ as adding/removing interfaces. if (link) { data.ch_switch.link_id = nla_get_u8(link); -@@ -4114,6 +4117,7 @@ static void do_process_drv_event(struct +@@ -4129,6 +4132,7 @@ static void do_process_drv_event(struct tb[NL80211_ATTR_CENTER_FREQ1], tb[NL80211_ATTR_CENTER_FREQ2], tb[NL80211_ATTR_PUNCT_BITMAP], @@ -529,7 +529,7 @@ as adding/removing interfaces. 0); break; case NL80211_CMD_CH_SWITCH_NOTIFY: -@@ -4126,6 +4130,7 @@ static void do_process_drv_event(struct +@@ -4141,6 +4145,7 @@ static void do_process_drv_event(struct tb[NL80211_ATTR_CENTER_FREQ1], tb[NL80211_ATTR_CENTER_FREQ2], tb[NL80211_ATTR_PUNCT_BITMAP], @@ -610,7 +610,7 @@ as adding/removing interfaces. endif ifdef CONFIG_CODE_COVERAGE -@@ -1054,6 +1066,9 @@ OBJS += ../src/ap/ctrl_iface_ap.o +@@ -1056,6 +1068,9 @@ OBJS += ../src/ap/ctrl_iface_ap.o ifdef CONFIG_UBUS OBJS += ../src/ap/ubus.o endif @@ -622,7 +622,7 @@ as adding/removing interfaces. CFLAGS += -DEAP_SERVER -DEAP_SERVER_IDENTITY --- a/wpa_supplicant/events.c +++ b/wpa_supplicant/events.c -@@ -6206,6 +6206,7 @@ void supplicant_event(void *ctx, enum wp +@@ -6211,6 +6211,7 @@ void supplicant_event(void *ctx, enum wp event_to_string(event), event); #endif /* CONFIG_NO_STDOUT_DEBUG */ @@ -632,7 +632,7 @@ as adding/removing interfaces. #ifdef CONFIG_FST --- a/wpa_supplicant/wpa_supplicant.c +++ b/wpa_supplicant/wpa_supplicant.c -@@ -1256,6 +1256,7 @@ void wpa_supplicant_set_state(struct wpa +@@ -1271,6 +1271,7 @@ void wpa_supplicant_set_state(struct wpa sme_sched_obss_scan(wpa_s, 0); } wpa_s->wpa_state = state; @@ -640,7 +640,7 @@ as adding/removing interfaces. #ifdef CONFIG_BGSCAN if (state == WPA_COMPLETED && wpa_s->current_ssid != wpa_s->bgscan_ssid) -@@ -8196,6 +8197,7 @@ struct wpa_supplicant * wpa_supplicant_a +@@ -8234,6 +8235,7 @@ struct wpa_supplicant * wpa_supplicant_a #endif /* CONFIG_P2P */ wpas_ubus_add_bss(wpa_s); @@ -648,7 +648,7 @@ as adding/removing interfaces. return wpa_s; } -@@ -8223,6 +8225,7 @@ int wpa_supplicant_remove_iface(struct w +@@ -8261,6 +8263,7 @@ int wpa_supplicant_remove_iface(struct w struct wpa_supplicant *parent = wpa_s->parent; #endif /* CONFIG_MESH */ @@ -656,7 +656,7 @@ as adding/removing interfaces. wpas_ubus_free_bss(wpa_s); /* Remove interface from the global list of interfaces */ -@@ -8533,6 +8536,7 @@ struct wpa_global * wpa_supplicant_init( +@@ -8571,6 +8574,7 @@ struct wpa_global * wpa_supplicant_init( eloop_register_timeout(WPA_SUPPLICANT_CLEANUP_INTERVAL, 0, wpas_periodic, global, NULL); @@ -664,7 +664,7 @@ as adding/removing interfaces. return global; } -@@ -8571,12 +8575,8 @@ int wpa_supplicant_run(struct wpa_global +@@ -8609,12 +8613,8 @@ int wpa_supplicant_run(struct wpa_global eloop_register_signal_terminate(wpa_supplicant_terminate, global); eloop_register_signal_reconfig(wpa_supplicant_reconfig, global); @@ -677,7 +677,7 @@ as adding/removing interfaces. return 0; } -@@ -8609,6 +8609,8 @@ void wpa_supplicant_deinit(struct wpa_gl +@@ -8647,6 +8647,8 @@ void wpa_supplicant_deinit(struct wpa_gl wpas_notify_supplicant_deinitialized(global); @@ -696,7 +696,7 @@ as adding/removing interfaces. extern const char *const wpa_supplicant_version; extern const char *const wpa_supplicant_license; -@@ -709,6 +710,7 @@ struct wpa_supplicant { +@@ -700,6 +701,7 @@ struct wpa_supplicant { unsigned char perm_addr[ETH_ALEN]; char ifname[100]; struct wpas_ubus_bss ubus; @@ -706,7 +706,7 @@ as adding/removing interfaces. #endif /* CONFIG_MATCH_IFACE */ --- a/src/ap/ieee802_11.c +++ b/src/ap/ieee802_11.c -@@ -555,12 +555,17 @@ const char * sae_get_password(struct hos +@@ -631,12 +631,17 @@ const char * sae_get_password(struct hos struct sae_pt **s_pt, const struct sae_pk **s_pk) { @@ -722,10 +722,10 @@ as adding/removing interfaces. + if (sta && sta->use_sta_psk) + goto use_sta_psk; + - for (pw = hapd->conf->sae_passwords; pw; pw = pw->next) { - if (!is_broadcast_ether_addr(pw->peer_addr) && - (!sta || -@@ -582,12 +587,30 @@ const char * sae_get_password(struct hos + /* With sae_track_password functionality enabled, try to first find the + * next viable wildcard-address password if a password identifier was + * not used. Select an wildcard-addr entry if the STA is known to have +@@ -697,12 +702,30 @@ const char * sae_get_password(struct hos pt = hapd->conf->ssid.pt; } @@ -758,7 +758,7 @@ as adding/removing interfaces. } } -@@ -3273,6 +3296,12 @@ static void handle_auth(struct hostapd_d +@@ -3429,6 +3452,12 @@ static void handle_auth(struct hostapd_d goto fail; } @@ -773,7 +773,7 @@ as adding/removing interfaces. --- a/src/ap/sta_info.c +++ b/src/ap/sta_info.c -@@ -475,6 +475,11 @@ void ap_free_sta(struct hostapd_data *ha +@@ -476,6 +476,11 @@ void ap_free_sta(struct hostapd_data *ha forced_memzero(sta->last_tk, WPA_TK_MAX_LEN); #endif /* CONFIG_TESTING_OPTIONS */ @@ -785,7 +785,7 @@ as adding/removing interfaces. os_free(sta); } -@@ -1574,6 +1579,8 @@ void ap_sta_set_authorized_event(struct +@@ -1575,6 +1580,8 @@ void ap_sta_set_authorized_event(struct #endif /* CONFIG_P2P */ const u8 *ip_ptr = NULL; @@ -796,7 +796,7 @@ as adding/removing interfaces. if (sta->p2p_ie != NULL && --- a/src/ap/sta_info.h +++ b/src/ap/sta_info.h -@@ -181,6 +181,9 @@ struct sta_info { +@@ -180,6 +180,9 @@ struct sta_info { int vlan_id_bound; /* updated by ap_sta_bind_vlan() */ /* PSKs from RADIUS authentication server */ struct hostapd_sta_wpa_psk_short *psk; @@ -808,7 +808,7 @@ as adding/removing interfaces. char *radius_cui; /* Chargeable-User-Identity from RADIUS */ --- a/src/ap/wpa_auth_glue.c +++ b/src/ap/wpa_auth_glue.c -@@ -403,6 +403,7 @@ static const u8 * hostapd_wpa_auth_get_p +@@ -392,6 +392,7 @@ static const u8 * hostapd_wpa_auth_get_p struct sta_info *sta = ap_get_sta(hapd, addr); const u8 *psk; @@ -816,7 +816,7 @@ as adding/removing interfaces. if (vlan_id) *vlan_id = 0; if (psk_len) -@@ -449,13 +450,18 @@ static const u8 * hostapd_wpa_auth_get_p +@@ -438,13 +439,18 @@ static const u8 * hostapd_wpa_auth_get_p * returned psk which should not be returned again. * logic list (all hostapd_get_psk; all sta->psk) */ @@ -836,7 +836,7 @@ as adding/removing interfaces. if (pos->is_passphrase) { if (pbkdf2_sha1(pos->passphrase, hapd->conf->ssid.ssid, -@@ -469,9 +475,13 @@ static const u8 * hostapd_wpa_auth_get_p +@@ -458,9 +464,13 @@ static const u8 * hostapd_wpa_auth_get_p } if (pos->psk == prev_psk) { psk = pos->next ? pos->next->psk : NULL; diff --git a/package/network/services/hostapd/patches/701-reload_config_inline.patch b/package/network/services/hostapd/patches/701-reload_config_inline.patch index 2c2b9d4c30..9c142d1ab6 100644 --- a/package/network/services/hostapd/patches/701-reload_config_inline.patch +++ b/package/network/services/hostapd/patches/701-reload_config_inline.patch @@ -8,7 +8,7 @@ as adding/removing interfaces. --- a/hostapd/config_file.c +++ b/hostapd/config_file.c -@@ -5223,7 +5223,12 @@ struct hostapd_config * hostapd_config_r +@@ -4981,7 +4981,12 @@ struct hostapd_config * hostapd_config_r int errors = 0; size_t i; diff --git a/package/network/services/hostapd/patches/710-vlan_no_bridge.patch b/package/network/services/hostapd/patches/710-vlan_no_bridge.patch index 750d159f8d..fb0a5d4a95 100644 --- a/package/network/services/hostapd/patches/710-vlan_no_bridge.patch +++ b/package/network/services/hostapd/patches/710-vlan_no_bridge.patch @@ -8,7 +8,7 @@ was provided by the config --- a/hostapd/config_file.c +++ b/hostapd/config_file.c -@@ -3644,6 +3644,8 @@ static int hostapd_config_fill(struct ho +@@ -3415,6 +3415,8 @@ static int hostapd_config_fill(struct ho #ifndef CONFIG_NO_VLAN } else if (os_strcmp(buf, "dynamic_vlan") == 0) { bss->ssid.dynamic_vlan = atoi(pos); @@ -19,7 +19,7 @@ was provided by the config } else if (os_strcmp(buf, "vlan_file") == 0) { --- a/src/ap/ap_config.h +++ b/src/ap/ap_config.h -@@ -121,6 +121,7 @@ struct hostapd_ssid { +@@ -120,6 +120,7 @@ struct hostapd_ssid { #define DYNAMIC_VLAN_OPTIONAL 1 #define DYNAMIC_VLAN_REQUIRED 2 int dynamic_vlan; diff --git a/package/network/services/hostapd/patches/711-wds_bridge_force.patch b/package/network/services/hostapd/patches/711-wds_bridge_force.patch index 7c5a3998f0..c71318be85 100644 --- a/package/network/services/hostapd/patches/711-wds_bridge_force.patch +++ b/package/network/services/hostapd/patches/711-wds_bridge_force.patch @@ -11,7 +11,7 @@ instead rely entirely on netifd handling this properly --- a/hostapd/config_file.c +++ b/hostapd/config_file.c -@@ -2472,6 +2472,8 @@ static int hostapd_config_fill(struct ho +@@ -2241,6 +2241,8 @@ static int hostapd_config_fill(struct ho sizeof(conf->bss[0]->iface)); } else if (os_strcmp(buf, "bridge") == 0) { os_strlcpy(bss->bridge, pos, sizeof(bss->bridge)); @@ -22,7 +22,7 @@ instead rely entirely on netifd handling this properly } else if (os_strcmp(buf, "vlan_bridge") == 0) { --- a/src/ap/ap_drv_ops.c +++ b/src/ap/ap_drv_ops.c -@@ -394,8 +394,6 @@ int hostapd_set_wds_sta(struct hostapd_d +@@ -390,8 +390,6 @@ int hostapd_set_wds_sta(struct hostapd_d return -1; if (hapd->conf->wds_bridge[0]) bridge = hapd->conf->wds_bridge; diff --git a/package/network/services/hostapd/patches/720-iface_max_num_sta.patch b/package/network/services/hostapd/patches/720-iface_max_num_sta.patch index 022b2d9621..6a22a610c5 100644 --- a/package/network/services/hostapd/patches/720-iface_max_num_sta.patch +++ b/package/network/services/hostapd/patches/720-iface_max_num_sta.patch @@ -8,7 +8,7 @@ full device, e.g. in order to deal with hardware/driver limitations --- a/hostapd/config_file.c +++ b/hostapd/config_file.c -@@ -3088,6 +3088,14 @@ static int hostapd_config_fill(struct ho +@@ -2857,6 +2857,14 @@ static int hostapd_config_fill(struct ho line, bss->max_num_sta, MAX_STA_COUNT); return 1; } @@ -25,7 +25,7 @@ full device, e.g. in order to deal with hardware/driver limitations } else if (os_strcmp(buf, "extended_key_id") == 0) { --- a/src/ap/ap_config.h +++ b/src/ap/ap_config.h -@@ -1089,6 +1089,8 @@ struct hostapd_config { +@@ -1069,6 +1069,8 @@ struct hostapd_config { unsigned int track_sta_max_num; unsigned int track_sta_max_age; @@ -36,7 +36,7 @@ full device, e.g. in order to deal with hardware/driver limitations * ' ' (ascii 32): all environments --- a/src/ap/beacon.c +++ b/src/ap/beacon.c -@@ -1653,7 +1653,7 @@ void handle_probe_req(struct hostapd_dat +@@ -1654,7 +1654,7 @@ void handle_probe_req(struct hostapd_dat if (hapd->conf->no_probe_resp_if_max_sta && is_multicast_ether_addr(mgmt->da) && is_multicast_ether_addr(mgmt->bssid) && diff --git a/package/network/services/hostapd/patches/730-ft_iface.patch b/package/network/services/hostapd/patches/730-ft_iface.patch index 4226a59d66..e5d29c30f2 100644 --- a/package/network/services/hostapd/patches/730-ft_iface.patch +++ b/package/network/services/hostapd/patches/730-ft_iface.patch @@ -8,7 +8,7 @@ a VLAN interface on top of the bridge, instead of using the bridge directly --- a/hostapd/config_file.c +++ b/hostapd/config_file.c -@@ -3285,6 +3285,8 @@ static int hostapd_config_fill(struct ho +@@ -3054,6 +3054,8 @@ static int hostapd_config_fill(struct ho wpa_printf(MSG_INFO, "Line %d: Obsolete peerkey parameter ignored", line); #ifdef CONFIG_IEEE80211R_AP @@ -19,7 +19,7 @@ a VLAN interface on top of the bridge, instead of using the bridge directly hexstr2bin(pos, bss->mobility_domain, --- a/src/ap/ap_config.h +++ b/src/ap/ap_config.h -@@ -283,6 +283,7 @@ struct airtime_sta_weight { +@@ -285,6 +285,7 @@ struct airtime_sta_weight { struct hostapd_bss_config { char iface[IFNAMSIZ + 1]; char bridge[IFNAMSIZ + 1]; @@ -29,7 +29,7 @@ a VLAN interface on top of the bridge, instead of using the bridge directly int bridge_hairpin; /* hairpin_mode on bridge members */ --- a/src/ap/wpa_auth_glue.c +++ b/src/ap/wpa_auth_glue.c -@@ -1829,8 +1829,12 @@ int hostapd_setup_wpa(struct hostapd_dat +@@ -1834,8 +1834,12 @@ int hostapd_setup_wpa(struct hostapd_dat wpa_key_mgmt_ft(hapd->conf->wpa_key_mgmt)) { const char *ft_iface; diff --git a/package/network/services/hostapd/patches/740-snoop_iface.patch b/package/network/services/hostapd/patches/740-snoop_iface.patch index 0d7024af8f..1933247f8c 100644 --- a/package/network/services/hostapd/patches/740-snoop_iface.patch +++ b/package/network/services/hostapd/patches/740-snoop_iface.patch @@ -8,7 +8,7 @@ untagged DHCP packets --- a/hostapd/config_file.c +++ b/hostapd/config_file.c -@@ -2476,6 +2476,8 @@ static int hostapd_config_fill(struct ho +@@ -2245,6 +2245,8 @@ static int hostapd_config_fill(struct ho os_strlcpy(bss->wds_bridge, pos, sizeof(bss->wds_bridge)); } else if (os_strcmp(buf, "bridge_hairpin") == 0) { bss->bridge_hairpin = atoi(pos); @@ -19,7 +19,7 @@ untagged DHCP packets } else if (os_strcmp(buf, "wds_bridge") == 0) { --- a/src/ap/ap_config.h +++ b/src/ap/ap_config.h -@@ -284,6 +284,7 @@ struct hostapd_bss_config { +@@ -286,6 +286,7 @@ struct hostapd_bss_config { char iface[IFNAMSIZ + 1]; char bridge[IFNAMSIZ + 1]; char ft_iface[IFNAMSIZ + 1]; @@ -112,7 +112,7 @@ untagged DHCP packets hapd->x_snoop_initialized = false; --- a/src/drivers/driver.h +++ b/src/drivers/driver.h -@@ -4429,7 +4429,7 @@ struct wpa_driver_ops { +@@ -4462,7 +4462,7 @@ struct wpa_driver_ops { * Returns: 0 on success, negative (<0) on failure */ int (*br_set_net_param)(void *priv, enum drv_br_net_param param, @@ -123,7 +123,7 @@ untagged DHCP packets * get_wowlan - Get wake-on-wireless status --- a/src/drivers/driver_nl80211.c +++ b/src/drivers/driver_nl80211.c -@@ -12853,7 +12853,7 @@ static const char * drv_br_net_param_str +@@ -12789,7 +12789,7 @@ static const char * drv_br_net_param_str static int wpa_driver_br_set_net_param(void *priv, enum drv_br_net_param param, @@ -132,7 +132,7 @@ untagged DHCP packets { struct i802_bss *bss = priv; char path[128]; -@@ -12879,8 +12879,11 @@ static int wpa_driver_br_set_net_param(v +@@ -12815,8 +12815,11 @@ static int wpa_driver_br_set_net_param(v return -EINVAL; } diff --git a/package/network/services/hostapd/patches/760-dynamic_own_ip.patch b/package/network/services/hostapd/patches/760-dynamic_own_ip.patch index 7f1dc11755..f46ba6b2e7 100644 --- a/package/network/services/hostapd/patches/760-dynamic_own_ip.patch +++ b/package/network/services/hostapd/patches/760-dynamic_own_ip.patch @@ -7,7 +7,7 @@ Some servers use the NAS-IP-Address attribute as a destination address --- a/hostapd/config_file.c +++ b/hostapd/config_file.c -@@ -2863,6 +2863,8 @@ static int hostapd_config_fill(struct ho +@@ -2632,6 +2632,8 @@ static int hostapd_config_fill(struct ho } else if (os_strcmp(buf, "iapp_interface") == 0) { wpa_printf(MSG_INFO, "DEPRECATED: iapp_interface not used"); #endif /* CONFIG_IAPP */ @@ -18,7 +18,7 @@ Some servers use the NAS-IP-Address attribute as a destination address wpa_printf(MSG_ERROR, --- a/src/ap/ap_config.h +++ b/src/ap/ap_config.h -@@ -310,6 +310,7 @@ struct hostapd_bss_config { +@@ -312,6 +312,7 @@ struct hostapd_bss_config { unsigned int eap_sim_db_timeout; int eap_server_erp; /* Whether ERP is enabled on internal EAP server */ struct hostapd_ip_addr own_ip_addr; @@ -28,7 +28,7 @@ Some servers use the NAS-IP-Address attribute as a destination address int radius_require_message_authenticator; --- a/src/ap/ieee802_1x.c +++ b/src/ap/ieee802_1x.c -@@ -598,6 +598,10 @@ int add_common_radius_attr(struct hostap +@@ -597,6 +597,10 @@ int add_common_radius_attr(struct hostap struct hostapd_radius_attr *attr; int len; @@ -50,7 +50,7 @@ Some servers use the NAS-IP-Address attribute as a destination address /** * conf - RADIUS client configuration (list of RADIUS servers to use) */ -@@ -819,6 +821,30 @@ static void radius_close_acct_socket(str +@@ -822,6 +824,30 @@ static void radius_close_acct_socket(str /** @@ -81,7 +81,7 @@ Some servers use the NAS-IP-Address attribute as a destination address * radius_client_send - Send a RADIUS request * @radius: RADIUS client context from radius_client_init() * @msg: RADIUS message to be sent -@@ -1714,6 +1740,10 @@ radius_change_server(struct radius_clien +@@ -1733,6 +1759,10 @@ radius_change_server(struct radius_clien wpa_printf(MSG_DEBUG, "RADIUS local address: %s:%u", inet_ntoa(claddr.sin_addr), ntohs(claddr.sin_port)); @@ -92,7 +92,7 @@ Some servers use the NAS-IP-Address attribute as a destination address } break; #ifdef CONFIG_IPV6 -@@ -1725,6 +1755,10 @@ radius_change_server(struct radius_clien +@@ -1744,6 +1774,10 @@ radius_change_server(struct radius_clien inet_ntop(AF_INET6, &claddr6.sin6_addr, abuf, sizeof(abuf)), ntohs(claddr6.sin6_port)); diff --git a/package/network/services/hostapd/patches/762-AP-don-t-ignore-probe-requests-with-invalid-DSSS-par.patch b/package/network/services/hostapd/patches/762-AP-don-t-ignore-probe-requests-with-invalid-DSSS-par.patch index 03b333138a..e673002139 100644 --- a/package/network/services/hostapd/patches/762-AP-don-t-ignore-probe-requests-with-invalid-DSSS-par.patch +++ b/package/network/services/hostapd/patches/762-AP-don-t-ignore-probe-requests-with-invalid-DSSS-par.patch @@ -28,7 +28,7 @@ Signed-off-by: David Bauer --- a/src/ap/beacon.c +++ b/src/ap/beacon.c -@@ -1496,7 +1496,7 @@ void handle_probe_req(struct hostapd_dat +@@ -1497,7 +1497,7 @@ void handle_probe_req(struct hostapd_dat * is less likely to see them (Probe Request frame sent on a * neighboring, but partially overlapping, channel). */ diff --git a/package/network/services/hostapd/patches/763-radius-wispr.patch b/package/network/services/hostapd/patches/763-radius-wispr.patch index e8967a8547..1b1797318c 100644 --- a/package/network/services/hostapd/patches/763-radius-wispr.patch +++ b/package/network/services/hostapd/patches/763-radius-wispr.patch @@ -1,6 +1,6 @@ --- a/src/ap/ieee802_1x.c +++ b/src/ap/ieee802_1x.c -@@ -2033,6 +2033,25 @@ static int ieee802_1x_update_vlan(struct +@@ -2000,6 +2000,25 @@ static int ieee802_1x_update_vlan(struct } #endif /* CONFIG_NO_VLAN */ @@ -26,7 +26,7 @@ /** * ieee802_1x_receive_auth - Process RADIUS frames from Authentication Server -@@ -2149,6 +2168,7 @@ ieee802_1x_receive_auth(struct radius_ms +@@ -2116,6 +2135,7 @@ ieee802_1x_receive_auth(struct radius_ms ieee802_1x_check_hs20(hapd, sta, msg, session_timeout_set ? (int) session_timeout : -1); @@ -46,7 +46,7 @@ enum mesh_plink_state plink_state; --- a/src/radius/radius.c +++ b/src/radius/radius.c -@@ -1339,6 +1339,35 @@ radius_msg_get_cisco_keys(struct radius_ +@@ -1377,6 +1377,35 @@ radius_msg_get_cisco_keys(struct radius_ return keys; } @@ -84,7 +84,7 @@ const u8 *req_authenticator, --- a/src/radius/radius.h +++ b/src/radius/radius.h -@@ -233,6 +233,10 @@ enum { +@@ -232,6 +232,10 @@ enum { RADIUS_VENDOR_ATTR_WFA_HS20_T_C_URL = 10, }; @@ -95,7 +95,7 @@ #ifdef _MSC_VER #pragma pack(pop) #endif /* _MSC_VER */ -@@ -306,6 +310,7 @@ radius_msg_get_ms_keys(struct radius_msg +@@ -304,6 +308,7 @@ radius_msg_get_ms_keys(struct radius_msg struct radius_ms_mppe_keys * radius_msg_get_cisco_keys(struct radius_msg *msg, struct radius_msg *sent_msg, const u8 *secret, size_t secret_len); diff --git a/package/network/services/hostapd/patches/770-radius_server.patch b/package/network/services/hostapd/patches/770-radius_server.patch index 53d162e916..d6fdb167f6 100644 --- a/package/network/services/hostapd/patches/770-radius_server.patch +++ b/package/network/services/hostapd/patches/770-radius_server.patch @@ -56,7 +56,7 @@ handle reload. /** * struct radius_session - Internal RADIUS server data for a session */ -@@ -90,7 +96,7 @@ struct radius_session { +@@ -89,7 +95,7 @@ struct radius_session { unsigned int macacl:1; unsigned int t_c_filtering:1; @@ -65,7 +65,7 @@ handle reload. u32 t_c_timestamp; /* Last read T&C timestamp from user DB */ }; -@@ -394,6 +400,7 @@ static void radius_server_session_free(s +@@ -373,6 +379,7 @@ static void radius_server_session_free(s radius_msg_free(sess->last_reply); os_free(sess->username); os_free(sess->nas_ip); @@ -73,7 +73,7 @@ handle reload. os_free(sess); data->num_sess--; } -@@ -554,6 +561,36 @@ radius_server_erp_find_key(struct radius +@@ -533,6 +540,36 @@ radius_server_erp_find_key(struct radius } #endif /* CONFIG_ERP */ @@ -110,7 +110,7 @@ handle reload. static struct radius_session * radius_server_get_new_session(struct radius_server_data *data, -@@ -607,7 +644,7 @@ radius_server_get_new_session(struct rad +@@ -586,7 +623,7 @@ radius_server_get_new_session(struct rad eap_user_free(tmp); return NULL; } @@ -119,7 +119,7 @@ handle reload. sess->macacl = tmp->macacl; eap_user_free(tmp); -@@ -1123,11 +1160,10 @@ radius_server_encapsulate_eap(struct rad +@@ -923,11 +960,10 @@ radius_server_encapsulate_eap(struct rad } if (code == RADIUS_CODE_ACCESS_ACCEPT) { @@ -135,7 +135,7 @@ handle reload. wpa_printf(MSG_ERROR, "Could not add RADIUS attribute"); radius_msg_free(msg); return NULL; -@@ -1221,11 +1257,10 @@ radius_server_macacl(struct radius_serve +@@ -1023,11 +1059,10 @@ radius_server_macacl(struct radius_serve } if (code == RADIUS_CODE_ACCESS_ACCEPT) { @@ -151,12 +151,12 @@ handle reload. wpa_printf(MSG_ERROR, "Could not add RADIUS attribute"); radius_msg_free(msg); return NULL; -@@ -2527,7 +2562,7 @@ static int radius_server_get_eap_user(vo +@@ -2335,7 +2370,7 @@ static int radius_server_get_eap_user(vo ret = data->get_eap_user(data->conf_ctx, identity, identity_len, phase2, user); if (ret == 0 && user) { - sess->accept_attr = user->accept_attr; + sess->accept_attr = radius_server_copy_attr(user->accept_attr); - sess->remediation = user->remediation; sess->macacl = user->macacl; sess->t_c_timestamp = user->t_c_timestamp; + } diff --git a/package/network/services/hostapd/patches/780-Implement-APuP-Access-Point-Micro-Peering.patch b/package/network/services/hostapd/patches/780-Implement-APuP-Access-Point-Micro-Peering.patch index d21027636a..72c48a3d00 100644 --- a/package/network/services/hostapd/patches/780-Implement-APuP-Access-Point-Micro-Peering.patch +++ b/package/network/services/hostapd/patches/780-Implement-APuP-Access-Point-Micro-Peering.patch @@ -53,7 +53,7 @@ Hotfix-by: Sebastian Gottschall https://github.com/mirror/dd-wrt/commit/0c3001a6 --- a/hostapd/config_file.c +++ b/hostapd/config_file.c -@@ -5216,6 +5216,15 @@ static int hostapd_config_fill(struct ho +@@ -4974,6 +4974,15 @@ static int hostapd_config_fill(struct ho bss->mld_indicate_disabled = atoi(pos); #endif /* CONFIG_TESTING_OPTIONS */ #endif /* CONFIG_IEEE80211BE */ @@ -71,7 +71,7 @@ Hotfix-by: Sebastian Gottschall https://github.com/mirror/dd-wrt/commit/0c3001a6 "Line %d: unknown configuration item '%s'", --- a/src/ap/ap_config.h +++ b/src/ap/ap_config.h -@@ -1002,6 +1002,35 @@ struct hostapd_bss_config { +@@ -982,6 +982,35 @@ struct hostapd_bss_config { int mbssid_index; bool spp_amsdu; @@ -109,7 +109,7 @@ Hotfix-by: Sebastian Gottschall https://github.com/mirror/dd-wrt/commit/0c3001a6 /** --- a/src/ap/ap_drv_ops.c +++ b/src/ap/ap_drv_ops.c -@@ -389,13 +389,39 @@ int hostapd_set_wds_sta(struct hostapd_d +@@ -385,13 +385,39 @@ int hostapd_set_wds_sta(struct hostapd_d const u8 *addr, int aid, int val) { const char *bridge = NULL; @@ -373,7 +373,7 @@ Hotfix-by: Sebastian Gottschall https://github.com/mirror/dd-wrt/commit/0c3001a6 #ifdef CONFIG_FILS static struct wpabuf * -@@ -3664,8 +3667,8 @@ static u16 check_multi_ap(struct hostapd +@@ -3820,8 +3823,8 @@ static u16 check_multi_ap(struct hostapd } @@ -384,7 +384,7 @@ Hotfix-by: Sebastian Gottschall https://github.com/mirror/dd-wrt/commit/0c3001a6 { /* Supported rates not used in IEEE 802.11ad/DMG */ if (hapd->iface->current_mode && -@@ -4105,7 +4108,7 @@ static int __check_assoc_ies(struct host +@@ -4263,7 +4266,7 @@ static int __check_assoc_ies(struct host elems->ext_capab_len); if (resp != WLAN_STATUS_SUCCESS) return resp; @@ -393,7 +393,7 @@ Hotfix-by: Sebastian Gottschall https://github.com/mirror/dd-wrt/commit/0c3001a6 if (resp != WLAN_STATUS_SUCCESS) return resp; -@@ -6175,6 +6178,11 @@ static void handle_beacon(struct hostapd +@@ -6314,6 +6317,11 @@ static void handle_beacon(struct hostapd 0); ap_list_process_beacon(hapd->iface, mgmt, &elems, fi); @@ -407,7 +407,7 @@ Hotfix-by: Sebastian Gottschall https://github.com/mirror/dd-wrt/commit/0c3001a6 --- a/src/ap/ieee802_11.h +++ b/src/ap/ieee802_11.h -@@ -108,6 +108,8 @@ int hostapd_process_ml_assoc_req_addr(st +@@ -114,6 +114,8 @@ int hostapd_process_ml_assoc_req_addr(st const u8 *basic_mle, size_t basic_mle_len, u8 *mld_addr); int hostapd_get_aid(struct hostapd_data *hapd, struct sta_info *sta); @@ -418,7 +418,7 @@ Hotfix-by: Sebastian Gottschall https://github.com/mirror/dd-wrt/commit/0c3001a6 u16 copy_sta_vendor_vht(struct hostapd_data *hapd, struct sta_info *sta, --- a/src/drivers/driver.h +++ b/src/drivers/driver.h -@@ -4123,7 +4123,7 @@ struct wpa_driver_ops { +@@ -4156,7 +4156,7 @@ struct wpa_driver_ops { * Returns: 0 on success, -1 on failure */ int (*set_wds_sta)(void *priv, const u8 *addr, int aid, int val, @@ -429,7 +429,7 @@ Hotfix-by: Sebastian Gottschall https://github.com/mirror/dd-wrt/commit/0c3001a6 * send_action - Transmit an Action frame --- a/src/drivers/driver_nl80211.c +++ b/src/drivers/driver_nl80211.c -@@ -8699,25 +8699,15 @@ static int have_ifidx(struct wpa_driver_ +@@ -8615,25 +8615,15 @@ static int have_ifidx(struct wpa_driver_ static int i802_set_wds_sta(void *priv, const u8 *addr, int aid, int val, diff --git a/package/network/services/hostapd/patches/803-hostapd-fix-80211be-build.patch b/package/network/services/hostapd/patches/803-hostapd-fix-80211be-build.patch index 85c745d187..d2b7b0b414 100644 --- a/package/network/services/hostapd/patches/803-hostapd-fix-80211be-build.patch +++ b/package/network/services/hostapd/patches/803-hostapd-fix-80211be-build.patch @@ -1,6 +1,6 @@ --- a/src/ap/sta_info.c +++ b/src/ap/sta_info.c -@@ -1970,3 +1970,22 @@ void ap_sta_free_sta_profile(struct mld_ +@@ -1971,3 +1971,22 @@ void ap_sta_free_sta_profile(struct mld_ } } #endif /* CONFIG_IEEE80211BE */ @@ -25,7 +25,7 @@ + --- a/src/ap/sta_info.h +++ b/src/ap/sta_info.h -@@ -414,23 +414,8 @@ int ap_sta_re_add(struct hostapd_data *h +@@ -411,23 +411,8 @@ int ap_sta_re_add(struct hostapd_data *h void ap_free_sta_pasn(struct hostapd_data *hapd, struct sta_info *sta); diff --git a/package/network/services/hostapd/patches/804-hostapd-revert-ACS-Validate-6-GHz-AP-criteria-before.patch b/package/network/services/hostapd/patches/804-hostapd-revert-ACS-Validate-6-GHz-AP-criteria-before.patch new file mode 100644 index 0000000000..5e6badde8d --- /dev/null +++ b/package/network/services/hostapd/patches/804-hostapd-revert-ACS-Validate-6-GHz-AP-criteria-before.patch @@ -0,0 +1,56 @@ +From bc40770144e52d1103d1098dfe59da6108a6413b Mon Sep 17 00:00:00 2001 +From: Agustin Lorenzo +Date: Tue, 22 Apr 2025 22:13:58 +0200 +Subject: [PATCH] hostapd: revert "ACS: Validate 6 GHz AP criteria before ACS" + +By OpenWrt's design, hostapd runs in a single global instance for all radios supported by the device, rather than one instance per radio like hostapd usually does. + +This reverts commit 02a8d40c9ffb2987c291ea96cf7be7c012b359a3. +--- + src/ap/ap_config.c | 2 +- + src/ap/ap_config.h | 1 - + src/ap/ap_drv_ops.c | 6 ++---- + 3 files changed, 3 insertions(+), 6 deletions(-) + +--- a/src/ap/ap_config.c ++++ b/src/ap/ap_config.c +@@ -1198,7 +1198,7 @@ static bool hostapd_sae_pk_password_with + #endif /* CONFIG_SAE_PK */ + + +-bool hostapd_config_check_bss_6g(struct hostapd_bss_config *bss) ++static bool hostapd_config_check_bss_6g(struct hostapd_bss_config *bss) + { + if (bss->wpa != WPA_PROTO_RSN) { + wpa_printf(MSG_ERROR, +--- a/src/ap/ap_config.h ++++ b/src/ap/ap_config.h +@@ -1436,6 +1436,5 @@ int hostapd_add_acl_maclist(struct mac_a + int vlan_id, const u8 *addr); + void hostapd_remove_acl_mac(struct mac_acl_entry **acl, int *num, + const u8 *addr); +-bool hostapd_config_check_bss_6g(struct hostapd_bss_config *bss); + + #endif /* HOSTAPD_CONFIG_H */ +--- a/src/ap/ap_drv_ops.c ++++ b/src/ap/ap_drv_ops.c +@@ -1175,9 +1175,6 @@ void hostapd_get_hw_mode_any_channels(st + { + int i; + bool is_no_ir = false; +- bool allow_6g_acs = hostapd_config_check_bss_6g(hapd->conf) && +- (hapd->iface->conf->ieee80211ax || +- hapd->iface->conf->ieee80211be); + + for (i = 0; i < mode->num_channels; i++) { + struct hostapd_channel_data *chan = &mode->channels[i]; +@@ -1198,7 +1195,8 @@ void hostapd_get_hw_mode_any_channels(st + if (is_6ghz_freq(chan->freq) && + ((hapd->iface->conf->acs_exclude_6ghz_non_psc && + !is_6ghz_psc_frequency(chan->freq)) || +- !allow_6g_acs)) ++ (!hapd->iface->conf->ieee80211ax && ++ !hapd->iface->conf->ieee80211be))) + continue; + if ((!(chan->flag & HOSTAPD_CHAN_DISABLED) || allow_disabled) && + !(hapd->iface->conf->acs_exclude_dfs && diff --git a/package/network/services/hostapd/patches/900-hostapd-update-muedca-params.patch b/package/network/services/hostapd/patches/900-hostapd-update-muedca-params.patch index 684122d5be..7b181d004b 100644 --- a/package/network/services/hostapd/patches/900-hostapd-update-muedca-params.patch +++ b/package/network/services/hostapd/patches/900-hostapd-update-muedca-params.patch @@ -1,6 +1,6 @@ --- a/hostapd/ctrl_iface.c +++ b/hostapd/ctrl_iface.c -@@ -1314,6 +1314,11 @@ static int hostapd_ctrl_iface_set(struct +@@ -1290,6 +1290,11 @@ static int hostapd_ctrl_iface_set(struct } else if (os_strncmp(cmd, "wme_ac_", 7) == 0 || os_strncmp(cmd, "wmm_ac_", 7) == 0) { hapd->parameter_set_count++; @@ -22,7 +22,7 @@ #include "wps/wps.h" #include "fst/fst.h" #include "wnm_ap.h" -@@ -2316,6 +2317,47 @@ static void hostapd_event_wds_sta_interf +@@ -2320,6 +2321,47 @@ static void hostapd_event_wds_sta_interf ifname, MAC2STR(addr)); } @@ -70,7 +70,7 @@ #ifdef CONFIG_OWE static int hostapd_notif_update_dh_ie(struct hostapd_data *hapd, -@@ -2874,6 +2916,9 @@ void hostapd_wpa_event(void *ctx, enum w +@@ -2878,6 +2920,9 @@ void hostapd_wpa_event(void *ctx, enum w hapd->conf->iface); hostapd_event_color_change(hapd, true); break; @@ -82,7 +82,7 @@ case EVENT_MLD_INTERFACE_FREED: --- a/src/ap/hostapd.c +++ b/src/ap/hostapd.c -@@ -4511,6 +4511,10 @@ static int hostapd_fill_csa_settings(str +@@ -4646,6 +4646,10 @@ static int hostapd_fill_csa_settings(str hapd->cs_count = settings->cs_count; hapd->cs_block_tx = settings->block_tx; @@ -103,7 +103,7 @@ static u8 ieee80211_he_ppet_size(u8 ppe_thres_hdr, const u8 *phy_cap_info) { -@@ -291,9 +292,16 @@ u8 * hostapd_eid_he_operation(struct hos +@@ -294,9 +295,16 @@ u8 * hostapd_eid_he_operation(struct hos u8 * hostapd_eid_he_mu_edca_parameter_set(struct hostapd_data *hapd, u8 *eid) { struct ieee80211_he_mu_edca_parameter_set *edca; @@ -157,7 +157,7 @@ size_t len); --- a/src/drivers/driver.h +++ b/src/drivers/driver.h -@@ -5980,6 +5980,16 @@ enum wpa_event_type { +@@ -6111,6 +6111,16 @@ enum wpa_event_type { EVENT_LINK_CH_SWITCH_STARTED, /** @@ -174,7 +174,7 @@ * EVENT_TID_LINK_MAP - MLD event to set TID-to-link mapping * * This event is used by the driver to indicate the received TID-to-link -@@ -6963,6 +6973,16 @@ union wpa_event_data { +@@ -7094,6 +7104,16 @@ union wpa_event_data { struct pasn_auth pasn_auth; /** @@ -211,7 +211,7 @@ C2S(NL80211_CMD_SET_HW_TIMESTAMP) C2S(NL80211_CMD_LINKS_REMOVED) C2S(NL80211_CMD_SET_TID_TO_LINK_MAPPING) -@@ -3650,6 +3651,35 @@ static void nl80211_port_authorized(stru +@@ -3725,6 +3726,35 @@ static void nl80211_port_authorized(stru wpa_supplicant_event(drv->ctx, EVENT_PORT_AUTHORIZED, &event); } @@ -247,7 +247,7 @@ static void nl80211_sta_opmode_change_event(struct wpa_driver_nl80211_data *drv, struct nlattr **tb) -@@ -4177,6 +4207,9 @@ static void do_process_drv_event(struct +@@ -4252,6 +4282,9 @@ static void do_process_drv_event(struct case NL80211_CMD_LINKS_REMOVED: wpa_supplicant_event(drv->ctx, EVENT_LINK_RECONFIG, NULL); break; @@ -259,9 +259,9 @@ "(cmd=%d)", cmd); --- a/src/drivers/nl80211_copy.h +++ b/src/drivers/nl80211_copy.h -@@ -1329,6 +1329,11 @@ - * %NL80211_ATTR_MLO_TTLM_ULINK attributes are used to specify the - * TID to Link mapping for downlink/uplink traffic. +@@ -1336,6 +1336,11 @@ + * control EPCS configuration. Used to notify userland on the current state + * of EPCS. * + * @NL80211_CMD_UPDATE_HE_MUEDCA_PARAMS: Updated MU-EDCA parameters from driver. + * This event is used to update MU-EDCA parameters in Beacon frame, which @@ -271,15 +271,15 @@ * @NL80211_CMD_MAX: highest used command number * @__NL80211_CMD_AFTER_LAST: internal use */ -@@ -1586,6 +1591,7 @@ enum nl80211_commands { - - NL80211_CMD_SET_TID_TO_LINK_MAPPING, +@@ -1596,6 +1601,7 @@ enum nl80211_commands { + NL80211_CMD_ASSOC_MLO_RECONF, + NL80211_CMD_EPCS_CFG, + NL80211_CMD_UPDATE_HE_MUEDCA_PARAMS, /* add new commands above here */ /* used to define NL80211_CMD_MAX below */ -@@ -2816,6 +2822,9 @@ enum nl80211_commands { +@@ -2826,6 +2832,9 @@ enum nl80211_commands { * the incoming frame RX timestamp. * @NL80211_ATTR_TD_BITMAP: Transition Disable bitmap, for subsequent * (re)associations. @@ -289,9 +289,9 @@ * * @NL80211_ATTR_PUNCT_BITMAP: (u32) Preamble puncturing bitmap, lowest * bit corresponds to the lowest 20 MHz channel. Each bit set to 1 -@@ -3416,6 +3425,7 @@ enum nl80211_attrs { - NL80211_ATTR_WIPHY_RADIOS, - NL80211_ATTR_WIPHY_INTERFACE_COMBINATIONS, +@@ -3456,6 +3465,7 @@ enum nl80211_attrs { + + NL80211_ATTR_ASSOC_MLD_EXT_CAPA_OPS, + NL80211_ATTR_HE_MUEDCA_PARAMS, /* add attributes here, update the policy in nl80211.c */ diff --git a/package/network/services/hostapd/patches/901-fix-SME-Authentication-request-to-the-driver-failed.patch b/package/network/services/hostapd/patches/901-fix-SME-Authentication-request-to-the-driver-failed.patch index f35b5564af..0ca8529bd7 100644 --- a/package/network/services/hostapd/patches/901-fix-SME-Authentication-request-to-the-driver-failed.patch +++ b/package/network/services/hostapd/patches/901-fix-SME-Authentication-request-to-the-driver-failed.patch @@ -1,7 +1,7 @@ reverted: ---- b/src/drivers/driver_nl80211.c -+++ a/src/drivers/driver_nl80211.c -@@ -4039,33 +4039,6 @@ +--- a/src/drivers/driver_nl80211.c ++++ b/src/drivers/driver_nl80211.c +@@ -4070,33 +4070,6 @@ static enum nl80211_auth_type get_nl_aut } @@ -35,7 +35,7 @@ reverted: static int wpa_driver_nl80211_authenticate( struct i802_bss *bss, struct wpa_driver_auth_params *params) { -@@ -4167,10 +4140,6 @@ +@@ -4198,10 +4171,6 @@ retry: goto fail; } @@ -46,7 +46,7 @@ reverted: if (params->mld && params->ap_mld_addr) { wpa_printf(MSG_DEBUG, " * MLD: link_id=%u, MLD addr=" MACSTR, params->mld_link_id, MAC2STR(params->ap_mld_addr)); -@@ -7509,10 +7478,6 @@ +@@ -7454,10 +7423,6 @@ static int wpa_driver_nl80211_associate( if (ret) goto fail; @@ -57,7 +57,7 @@ reverted: if (params->mgmt_frame_protection == MGMT_FRAME_PROTECTION_REQUIRED && nla_put_u32(msg, NL80211_ATTR_USE_MFP, NL80211_MFP_REQUIRED)) goto fail; -@@ -10103,7 +10068,6 @@ +@@ -10102,7 +10067,6 @@ static int nl80211_set_param(void *priv, { struct i802_bss *bss = priv; struct wpa_driver_nl80211_data *drv = bss->drv; @@ -65,7 +65,7 @@ reverted: if (param == NULL) return 0; -@@ -10177,33 +10141,6 @@ +@@ -10173,33 +10137,6 @@ static int nl80211_set_param(void *priv, if (os_strstr(param, "rsn_override_in_driver=1")) drv->capa.flags2 |= WPA_DRIVER_FLAGS2_RSN_OVERRIDE_STA; @@ -99,10 +99,9 @@ reverted: return 0; } -reverted: ---- b/src/drivers/driver_nl80211.h -+++ a/src/drivers/driver_nl80211.h -@@ -202,8 +202,6 @@ +--- a/src/drivers/driver_nl80211.h ++++ b/src/drivers/driver_nl80211.h +@@ -201,8 +201,6 @@ struct wpa_driver_nl80211_data { unsigned int qca_ap_allowed_freqs:1; unsigned int connect_ext_vendor_cmd_avail:1; diff --git a/package/network/services/ppp/files/etc/ppp/options.pptp b/package/network/services/ppp/files/etc/ppp/options.pptp index 46a3f48112..a4705bc0e1 100644 --- a/package/network/services/ppp/files/etc/ppp/options.pptp +++ b/package/network/services/ppp/files/etc/ppp/options.pptp @@ -3,5 +3,7 @@ noauth nobsdcomp nodeflate idle 0 -mppe required,no40,no56,stateless +nomppe-40 +require-mppe-128 +nomppe-stateful maxfail 0 diff --git a/package/network/services/umdns/Makefile b/package/network/services/umdns/Makefile index 60e0eb9ac4..c5affc841e 100644 --- a/package/network/services/umdns/Makefile +++ b/package/network/services/umdns/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_URL=$(PROJECT_GIT)/project/mdnsd.git PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2025-02-10 -PKG_SOURCE_VERSION:=c5ca22a71b2ecb83a2a28b46391dac443be315c2 -PKG_MIRROR_HASH:=2d595fa1e58f028a7ff6813b110ee6bcbc8e6ccce81b2792200508c6db9c276a +PKG_SOURCE_DATE:=2025-05-29 +PKG_SOURCE_VERSION:=2b28094d31caa75cd60ef86f0a27a793beaff968 +PKG_MIRROR_HASH:=0b5ce35a6d2e7c9861d291807c2e2b8f436fcef2776e5f5ecaf1466c28e8351a PKG_MAINTAINER:=John Crispin PKG_LICENSE:=LGPL-2.1 diff --git a/package/network/services/umdns/files/umdns.init b/package/network/services/umdns/files/umdns.init index 0516192fa2..6abb258bc4 100644 --- a/package/network/services/umdns/files/umdns.init +++ b/package/network/services/umdns/files/umdns.init @@ -60,7 +60,7 @@ start_service() { procd_add_raw_trigger "instance.update" 5000 "/bin/ubus" "call" "umdns" "reload" procd_close_trigger [ "$(uci get umdns.@umdns[-1].jail)" = 1 ] && { - procd_add_jail umdns ubus log + procd_add_jail umdns ubus log udebug [ -d /etc/umdns ] && procd_add_jail_mount "/etc/umdns" } procd_close_instance diff --git a/package/network/services/unetmsg/files/usr/share/ucode/unetmsg/unetmsgd-remote.uc b/package/network/services/unetmsg/files/usr/share/ucode/unetmsg/unetmsgd-remote.uc index 65cdfac04a..b6bf33b399 100644 --- a/package/network/services/unetmsg/files/usr/share/ucode/unetmsg/unetmsgd-remote.uc +++ b/package/network/services/unetmsg/files/usr/share/ucode/unetmsg/unetmsgd-remote.uc @@ -300,6 +300,7 @@ function network_open_channel(net, name, peer) return; core.dbg(`Try to connect to ${name}\n`); + sock.setopt(socket.SOL_TCP, socket.TCP_USER_TIMEOUT, 30 * 1000); sock.connect(addr); let auth_data_cb = (msg) => { if (!network_auth_valid(sock_data.name, sock_data.id, msg.token)) diff --git a/package/network/utils/uqmi/files/lib/netifd/proto/qmi.sh b/package/network/utils/uqmi/files/lib/netifd/proto/qmi.sh index b08b225104..a6a3fdaa69 100755 --- a/package/network/utils/uqmi/files/lib/netifd/proto/qmi.sh +++ b/package/network/utils/uqmi/files/lib/netifd/proto/qmi.sh @@ -107,7 +107,7 @@ proto_qmi_setup() { # Check if UIM application is stuck in illegal state local uim_state_timeout=0 while true; do - json_load "$(uqmi -s -d "$device" -t 1000 --uim-get-sim-state)" + json_load "$(uqmi -s -d "$device" -t 2000 --uim-get-sim-state)" json_get_var card_application_state card_application_state # SIM card is either completely absent or state is labeled as illegal @@ -122,7 +122,7 @@ proto_qmi_setup() { if [ "$uim_state_timeout" -lt "$timeout" ] || [ "$timeout" = "0" ]; then let uim_state_timeout++ - sleep 1 + sleep 5 continue fi diff --git a/package/system/procd/Makefile b/package/system/procd/Makefile index 0e9097f6ad..7a3ff1e1c3 100644 --- a/package/system/procd/Makefile +++ b/package/system/procd/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/procd.git -PKG_MIRROR_HASH:=6c3cbc18ac23f925199308e40e78b423858d3abe3a396078fbd142996d266642 -PKG_SOURCE_DATE:=2025-03-13 -PKG_SOURCE_VERSION:=891094aefcb28a376a43b7c539f599a8e0987e4d +PKG_MIRROR_HASH:=08f1bb20ca729839eb2070fea623d2f18024225b599651abaead8f49ae8d1b15 +PKG_SOURCE_DATE:=2025-05-31 +PKG_SOURCE_VERSION:=59d22013f9dd38f60b0f953534601532dd429c28 CMAKE_INSTALL:=1 PKG_LICENSE:=GPL-2.0 diff --git a/package/system/procd/files/procd.sh b/package/system/procd/files/procd.sh index 0f9405a222..54177ee064 100644 --- a/package/system/procd/files/procd.sh +++ b/package/system/procd/files/procd.sh @@ -188,11 +188,12 @@ _procd_add_jail() { json_add_string name "$1" shift - + for a in $@; do case $a in log) json_add_boolean "log" "1";; ubus) json_add_boolean "ubus" "1";; + udebug) json_add_boolean "udebug" "1";; procfs) json_add_boolean "procfs" "1";; sysfs) json_add_boolean "sysfs" "1";; ronly) json_add_boolean "ronly" "1";; diff --git a/package/utils/cli/files/usr/share/ucode/cli/types.uc b/package/utils/cli/files/usr/share/ucode/cli/types.uc index 46c563dfb3..10b004d1ad 100644 --- a/package/utils/cli/files/usr/share/ucode/cli/types.uc +++ b/package/utils/cli/files/usr/share/ucode/cli/types.uc @@ -64,12 +64,13 @@ const types = { return val; let list = this.value; + if (type(list) == "object") + list = keys(list); if (this.ignore_case) { val = lc(val); val = filter(list, (v) => val == lc(v))[0]; } else { - if (index(list, val) < 0) - val = null; + val = filter(list, (v) => val == v)[0]; } if (val == null) diff --git a/scripts/combined-ext-image.sh b/scripts/combined-ext-image.sh index c20203f23b..d46e32cf1d 100755 --- a/scripts/combined-ext-image.sh +++ b/scripts/combined-ext-image.sh @@ -9,7 +9,7 @@ # Write image header followed by all specified files # The header is padded to 64k, format is: # CE magic word ("Combined Extended Image") (2 bytes) -# file format version field (2 bytes) +# file format version field (2 bytes) # short description of the target device (32 bytes) # number of files following the header (2 byte) # name of the first file (32 bytes) @@ -20,7 +20,7 @@ # md5 checksum of the Nth file (32 bytes) ## version history -# * version 1: initial file format with num files / name / length / md5 checksum +# * version 1: initial file format with num files / name / length / md5 checksum set -e diff --git a/scripts/patch-kernel.sh b/scripts/patch-kernel.sh index 52750dde6e..504b207864 100755 --- a/scripts/patch-kernel.sh +++ b/scripts/patch-kernel.sh @@ -18,25 +18,25 @@ if [ ! -d "${patchdir}" ] ; then echo "Aborting. '${patchdir}' is not a directory." exit 1 fi - -for i in ${patchdir}/${patchpattern} ; do + +for i in ${patchdir}/${patchpattern} ; do case "$i" in *.gz) - type="gzip"; uncomp="gunzip -dc"; ;; + type="gzip"; uncomp="gunzip -dc"; ;; *.bz) - type="bzip"; uncomp="bunzip -dc"; ;; + type="bzip"; uncomp="bunzip -dc"; ;; *.bz2) - type="bzip2"; uncomp="bunzip2 -dc"; ;; + type="bzip2"; uncomp="bunzip2 -dc"; ;; *.zip) - type="zip"; uncomp="unzip -d"; ;; + type="zip"; uncomp="unzip -d"; ;; *.Z) - type="compress"; uncomp="uncompress -c"; ;; + type="compress"; uncomp="uncompress -c"; ;; *) - type="plaintext"; uncomp="cat"; ;; + type="plaintext"; uncomp="cat"; ;; esac - [ -d "${i}" ] && echo "Ignoring subdirectory ${i}" && continue + [ -d "${i}" ] && echo "Ignoring subdirectory ${i}" && continue echo "" - echo "Applying ${i} using ${type}: " + echo "Applying ${i} using ${type}: " ${uncomp} ${i} | ${PATCH:-patch} -f -p1 -d ${targetdir} if [ $? != 0 ] ; then echo "Patch failed! Please fix $i!" diff --git a/scripts/rstrip.sh b/scripts/rstrip.sh index 2aa7e96fda..db7b7b67c8 100755 --- a/scripts/rstrip.sh +++ b/scripts/rstrip.sh @@ -1,5 +1,5 @@ #!/usr/bin/env bash -# +# # Copyright (C) 2006 OpenWrt.org # # This is free software, licensed under the GNU General Public License v2. diff --git a/target/linux/armsr/image/Makefile b/target/linux/armsr/image/Makefile index a7254729d2..011d30d19d 100644 --- a/target/linux/armsr/image/Makefile +++ b/target/linux/armsr/image/Makefile @@ -12,7 +12,6 @@ GRUB_TERMINAL_CONFIG = GRUB_CONSOLE_CMDLINE = earlycon ifneq ($(CONFIG_GRUB_CONSOLE),) - GRUB_CONSOLE_CMDLINE += console=tty1 GRUB_TERMINALS += console endif diff --git a/target/linux/armsr/modules.mk b/target/linux/armsr/modules.mk index d570d7f74e..33e8ac266d 100644 --- a/target/linux/armsr/modules.mk +++ b/target/linux/armsr/modules.mk @@ -297,11 +297,11 @@ define KernelPackage/renesas-net-avb FILES=$(LINUX_DIR)/drivers/net/ethernet/renesas/ravb.ko AUTOLOAD:=$(call AutoProbe,ravb) endef - + define KernelPackage/renesas-net-avb/description Support Renesas RZ platform Ethernet module endef - + $(eval $(call KernelPackage,renesas-net-avb)) define KernelPackage/wdt-sp805 diff --git a/target/linux/armsr/patches-6.6/300-printk-always-setup-default-consoles.patch b/target/linux/armsr/patches-6.6/300-printk-always-setup-default-consoles.patch new file mode 100644 index 0000000000..c7a119cff1 --- /dev/null +++ b/target/linux/armsr/patches-6.6/300-printk-always-setup-default-consoles.patch @@ -0,0 +1,47 @@ +From 0059efbd0f9c291795078fb4e50722641d525f38 Mon Sep 17 00:00:00 2001 +From: Mathew McBride +Date: Thu, 16 Jan 2025 11:48:44 +1100 +Subject: [PATCH] printk: always setup default (tty0 + stdout / SPCR) consoles + when no console= present + +(This is a hack specific to OpenWrt's armsr target) + +This change resolves a difference in behaviour between arm64 ACPI +and DT systems. +Our usecase is to ensure the system console is always present +regardless of display mode (serial port or screen). + +Both ACPI and DT have mechanisms to setup a serial console from +information passed by firmware (SPCR and stdout-path respectively). + +On ACPI systems, the SPCR table is parsed very early on in the kernel +boot which prevents the screen console (tty0) from appearing if it is +not explicitly set. + +We would like to avoid specifying console= arguments as there are many +possible configurations on the serial side (like ttyS0, ttyAMA0, ttymxc0 +etc.). + +If the kernel does not consume the serial port in SPCR/stdout-path, +then the 'default' settings from the firmware (baud rate etc.) are lost. + +If the system administrator explicitly specifies a console= argument, +then the old behaviour is returned. + +Signed-off-by: Mathew McBride +Link: https://github.com/openwrt/openwrt/pull/17012#issuecomment-2591751115 +--- + kernel/printk/printk.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/kernel/printk/printk.c ++++ b/kernel/printk/printk.c +@@ -3505,7 +3505,7 @@ void register_console(struct console *ne + * Note that a console with tty binding will have CON_CONSDEV + * flag set and will be first in the list. + */ +- if (preferred_console < 0) { ++ if (!console_set_on_cmdline) { + if (hlist_empty(&console_list) || !console_first()->device || + console_first()->flags & CON_BOOT) { + try_enable_default_console(newcon); diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts index 66ae2d1ffd..36281f4caa 100644 --- a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts +++ b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts @@ -89,6 +89,7 @@ reg = <0x0000 0 0 0 0>; nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>; nvmem-cell-names = "pre-calibration", "mac-address"; + qcom,ath10k-calibration-variant = "TP-Link-Archer-c6-v2"; }; }; diff --git a/target/linux/ath79/image/generic-tp-link.mk b/target/linux/ath79/image/generic-tp-link.mk index b7ea8380de..53adc145f3 100644 --- a/target/linux/ath79/image/generic-tp-link.mk +++ b/target/linux/ath79/image/generic-tp-link.mk @@ -104,7 +104,7 @@ define Device/tplink_archer-c6-v2 DEVICE_MODEL := Archer C6 DEVICE_VARIANT := v2 (EU/RU/JP) TPLINK_BOARD_ID := ARCHER-C6-V2 - DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct + DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct -ath10k-board-qca9888 ipq-wifi-tplink_archer-c6-v2 endef TARGET_DEVICES += tplink_archer-c6-v2 diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk index 5d23f5cb93..36e00ad2d9 100644 --- a/target/linux/ath79/image/generic.mk +++ b/target/linux/ath79/image/generic.mk @@ -1102,6 +1102,7 @@ define Device/dlink_dap-13xx IMAGES += factory.bin IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \ append-rootfs | pad-rootfs | check-size | mkdapimg2 0xE0000 + DEFAULT := n endef define Device/dlink_dap-1330-a1 diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk index 0408d6ad82..d910aa7c88 100644 --- a/target/linux/ath79/image/nand.mk +++ b/target/linux/ath79/image/nand.mk @@ -318,6 +318,7 @@ define Device/meraki_mr18 KERNEL_INITRAMFS := $$(KERNEL) IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata SUPPORTED_DEVICES += mr18 + DEFAULT := n endef TARGET_DEVICES += meraki_mr18 diff --git a/target/linux/ath79/patches-6.12/900-unaligned_access_hacks.patch b/target/linux/ath79/patches-6.12/900-unaligned_access_hacks.patch index 364f8c5922..224b8097e2 100644 --- a/target/linux/ath79/patches-6.12/900-unaligned_access_hacks.patch +++ b/target/linux/ath79/patches-6.12/900-unaligned_access_hacks.patch @@ -323,7 +323,7 @@ SVN-Revision: 35130 SKB_DROP_REASON_IP_INHDR); --- a/include/linux/types.h +++ b/include/linux/types.h -@@ -247,5 +247,11 @@ typedef void (*swap_func_t)(void *a, voi +@@ -248,5 +248,11 @@ typedef void (*swap_func_t)(void *a, voi typedef int (*cmp_r_func_t)(const void *a, const void *b, const void *priv); typedef int (*cmp_func_t)(const void *a, const void *b); @@ -750,7 +750,7 @@ SVN-Revision: 35130 EXPORT_SYMBOL(xfrm_parse_spi); --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c -@@ -4321,14 +4321,16 @@ static bool tcp_parse_aligned_timestamp( +@@ -4329,14 +4329,16 @@ static bool tcp_parse_aligned_timestamp( { const __be32 *ptr = (const __be32 *)(th + 1); diff --git a/target/linux/ath79/patches-6.6/900-unaligned_access_hacks.patch b/target/linux/ath79/patches-6.6/900-unaligned_access_hacks.patch index 870567c058..bc1c1dd82d 100644 --- a/target/linux/ath79/patches-6.6/900-unaligned_access_hacks.patch +++ b/target/linux/ath79/patches-6.6/900-unaligned_access_hacks.patch @@ -323,7 +323,7 @@ SVN-Revision: 35130 SKB_DROP_REASON_IP_INHDR); --- a/include/linux/types.h +++ b/include/linux/types.h -@@ -244,5 +244,11 @@ typedef void (*swap_func_t)(void *a, voi +@@ -245,5 +245,11 @@ typedef void (*swap_func_t)(void *a, voi typedef int (*cmp_r_func_t)(const void *a, const void *b, const void *priv); typedef int (*cmp_func_t)(const void *a, const void *b); diff --git a/target/linux/bcm27xx/bcm2709/config-6.12 b/target/linux/bcm27xx/bcm2709/config-6.12 index 0e448f851b..ce80932aa5 100644 --- a/target/linux/bcm27xx/bcm2709/config-6.12 +++ b/target/linux/bcm27xx/bcm2709/config-6.12 @@ -32,6 +32,7 @@ CONFIG_ARM_LPAE=y CONFIG_ARM_PAN=y CONFIG_ARM_PATCH_IDIV=y CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_PMUV3 is not set CONFIG_ARM_RASPBERRYPI_CPUFREQ=y CONFIG_ARM_THUMB=y CONFIG_ARM_TIMER_SP804=y diff --git a/target/linux/bcm27xx/config-6.12 b/target/linux/bcm27xx/config-6.12 index d6e576cca7..157d532cae 100644 --- a/target/linux/bcm27xx/config-6.12 +++ b/target/linux/bcm27xx/config-6.12 @@ -4,8 +4,8 @@ # CONFIG_COMMON_CLK_RP1_SDIO is not set # CONFIG_COMMON_CLK_RP1_SDIO is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set -# CONFIG_DRM_PANEL_ILITEK_ILI9806E_SPI is not set # CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E_SPI is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_TPO_Y17P is not set # CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN is not set diff --git a/target/linux/bcm27xx/patches-6.12/950-0016-drm-atomic-helpers-remove-legacy_cursor_update-hacks.patch b/target/linux/bcm27xx/patches-6.12/950-0016-drm-atomic-helpers-remove-legacy_cursor_update-hacks.patch index e3bfcbb3e2..fb66aaceba 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0016-drm-atomic-helpers-remove-legacy_cursor_update-hacks.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0016-drm-atomic-helpers-remove-legacy_cursor_update-hacks.patch @@ -59,7 +59,7 @@ Signed-off-by: Maxime Ripard --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c -@@ -1656,13 +1656,6 @@ drm_atomic_helper_wait_for_vblanks(struc +@@ -1684,13 +1684,6 @@ drm_atomic_helper_wait_for_vblanks(struc int i, ret; unsigned int crtc_mask = 0; @@ -73,7 +73,7 @@ Signed-off-by: Maxime Ripard for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state, new_crtc_state, i) { if (!new_crtc_state->active) continue; -@@ -2311,12 +2304,6 @@ int drm_atomic_helper_setup_commit(struc +@@ -2339,12 +2332,6 @@ int drm_atomic_helper_setup_commit(struc complete_all(&commit->flip_done); continue; } diff --git a/target/linux/bcm27xx/patches-6.12/950-0057-MMC-added-alternative-MMC-driver.patch b/target/linux/bcm27xx/patches-6.12/950-0057-MMC-added-alternative-MMC-driver.patch index d69891d8f5..57f8f2f970 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0057-MMC-added-alternative-MMC-driver.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0057-MMC-added-alternative-MMC-driver.patch @@ -285,7 +285,7 @@ Signed-off-by: Phil Elwell static inline int mmc_blk_part_switch(struct mmc_card *card, unsigned int part_type); static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, -@@ -3309,6 +3316,8 @@ static int mmc_blk_probe(struct mmc_card +@@ -3313,6 +3320,8 @@ static int mmc_blk_probe(struct mmc_card { struct mmc_blk_data *md; int ret = 0; @@ -294,7 +294,7 @@ Signed-off-by: Phil Elwell /* * Check that the card supports the command class(es) we need. -@@ -3316,7 +3325,16 @@ static int mmc_blk_probe(struct mmc_card +@@ -3320,7 +3329,16 @@ static int mmc_blk_probe(struct mmc_card if (!(card->csd.cmdclass & CCC_BLOCK_READ)) return -ENODEV; @@ -312,7 +312,7 @@ Signed-off-by: Phil Elwell card->complete_wq = alloc_workqueue("mmc_complete", WQ_MEM_RECLAIM | WQ_HIGHPRI, 0); -@@ -3331,6 +3349,17 @@ static int mmc_blk_probe(struct mmc_card +@@ -3335,6 +3353,17 @@ static int mmc_blk_probe(struct mmc_card goto out_free; } @@ -1991,7 +1991,7 @@ Signed-off-by: Phil Elwell #define MAX_TUNING_LOOP 40 -@@ -3194,7 +3194,7 @@ static void sdhci_timeout_timer(struct t +@@ -3199,7 +3199,7 @@ static void sdhci_timeout_timer(struct t spin_lock_irqsave(&host->lock, flags); if (host->cmd && !sdhci_data_line_cmd(host->cmd)) { @@ -2000,7 +2000,7 @@ Signed-off-by: Phil Elwell mmc_hostname(host->mmc)); sdhci_err_stats_inc(host, REQ_TIMEOUT); sdhci_dumpregs(host); -@@ -3217,7 +3217,7 @@ static void sdhci_timeout_data_timer(str +@@ -3222,7 +3222,7 @@ static void sdhci_timeout_data_timer(str if (host->data || host->data_cmd || (host->cmd && sdhci_data_line_cmd(host->cmd))) { diff --git a/target/linux/bcm27xx/patches-6.12/950-0103-media-adv7180-Default-to-the-first-valid-input.patch b/target/linux/bcm27xx/patches-6.12/950-0103-media-adv7180-Default-to-the-first-valid-input.patch index c294e5286a..52a113906f 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0103-media-adv7180-Default-to-the-first-valid-input.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0103-media-adv7180-Default-to-the-first-valid-input.patch @@ -16,7 +16,7 @@ Signed-off-by: Dave Stevenson --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c -@@ -1352,6 +1352,7 @@ static const struct adv7180_chip_info ad +@@ -1362,6 +1362,7 @@ static const struct adv7180_chip_info ad static int init_device(struct adv7180_state *state) { int ret; @@ -24,7 +24,7 @@ Signed-off-by: Dave Stevenson mutex_lock(&state->mutex); -@@ -1399,6 +1400,18 @@ static int init_device(struct adv7180_st +@@ -1409,6 +1410,18 @@ static int init_device(struct adv7180_st goto out_unlock; } diff --git a/target/linux/bcm27xx/patches-6.12/950-0104-media-adv7180-Add-YPrPb-support-for-ADV7282M.patch b/target/linux/bcm27xx/patches-6.12/950-0104-media-adv7180-Add-YPrPb-support-for-ADV7282M.patch index 1552f6358c..8669c93edb 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0104-media-adv7180-Add-YPrPb-support-for-ADV7282M.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0104-media-adv7180-Add-YPrPb-support-for-ADV7282M.patch @@ -14,7 +14,7 @@ Signed-off-by: Dave Stevenson --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c -@@ -1341,6 +1341,7 @@ static const struct adv7180_chip_info ad +@@ -1351,6 +1351,7 @@ static const struct adv7180_chip_info ad BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | diff --git a/target/linux/bcm27xx/patches-6.12/950-0130-drm-v3d-Clock-V3D-down-when-not-in-use.patch b/target/linux/bcm27xx/patches-6.12/950-0130-drm-v3d-Clock-V3D-down-when-not-in-use.patch index 6cc36e1c29..71284d9f7e 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0130-drm-v3d-Clock-V3D-down-when-not-in-use.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0130-drm-v3d-Clock-V3D-down-when-not-in-use.patch @@ -37,7 +37,7 @@ Signed-off-by: popcornmix --- a/drivers/gpu/drm/v3d/v3d_drv.c +++ b/drivers/gpu/drm/v3d/v3d_drv.c -@@ -321,6 +321,21 @@ static int v3d_platform_drm_probe(struct +@@ -331,6 +331,21 @@ static int v3d_platform_drm_probe(struct } } @@ -59,7 +59,7 @@ Signed-off-by: popcornmix if (v3d->ver < 41) { ret = map_regs(v3d, &v3d->gca_regs, "gca"); if (ret) -@@ -349,6 +364,8 @@ static int v3d_platform_drm_probe(struct +@@ -360,6 +375,8 @@ static int v3d_platform_drm_probe(struct ret = v3d_sysfs_init(dev); if (ret) goto drm_unregister; diff --git a/target/linux/bcm27xx/patches-6.12/950-0131-drm-v3d-Switch-clock-setting-to-new-api.patch b/target/linux/bcm27xx/patches-6.12/950-0131-drm-v3d-Switch-clock-setting-to-new-api.patch index a1675a1cd2..6bdc6483e7 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0131-drm-v3d-Switch-clock-setting-to-new-api.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0131-drm-v3d-Switch-clock-setting-to-new-api.patch @@ -41,7 +41,7 @@ Signed-off-by: Maxime Ripard struct drm_device *drm; struct v3d_dev *v3d; int ret; -@@ -327,7 +333,20 @@ static int v3d_platform_drm_probe(struct +@@ -337,7 +343,20 @@ static int v3d_platform_drm_probe(struct dev_err(dev, "Failed to get clock (%ld)\n", PTR_ERR(v3d->clk)); return PTR_ERR(v3d->clk); } @@ -63,7 +63,7 @@ Signed-off-by: Maxime Ripard /* For downclocking, drop it to the minimum frequency we can get from * the CPRMAN clock generator dividing off our parent. The divider is * 4 bits, but ask for just higher than that so that rounding doesn't -@@ -364,7 +383,7 @@ static int v3d_platform_drm_probe(struct +@@ -375,7 +394,7 @@ static int v3d_platform_drm_probe(struct ret = v3d_sysfs_init(dev); if (ret) goto drm_unregister; diff --git a/target/linux/bcm27xx/patches-6.12/950-0136-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch b/target/linux/bcm27xx/patches-6.12/950-0136-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch index 28ca11aeb6..d2b8704308 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0136-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0136-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch @@ -426,7 +426,7 @@ Signed-off-by: Naushir Patuck +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -21548,6 +21548,14 @@ T: git git://linuxtv.org/media.git +@@ -21550,6 +21550,14 @@ T: git git://linuxtv.org/media.git F: Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml F: drivers/media/i2c/imx415.c diff --git a/target/linux/bcm27xx/patches-6.12/950-0137-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch b/target/linux/bcm27xx/patches-6.12/950-0137-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch index 52a8922e70..3b90b2ee86 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0137-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0137-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch @@ -193,7 +193,7 @@ media: i2c: imx519: Squash fixes +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -21556,6 +21556,14 @@ T: git git://linuxtv.org/media_tree.git +@@ -21558,6 +21558,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/imx477.yaml F: drivers/media/i2c/imx477.c diff --git a/target/linux/bcm27xx/patches-6.12/950-0147-Documentation-devicetree-Add-documentation-for-imx37.patch b/target/linux/bcm27xx/patches-6.12/950-0147-Documentation-devicetree-Add-documentation-for-imx37.patch index c7c3c5ab15..e66b500f3a 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0147-Documentation-devicetree-Add-documentation-for-imx37.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0147-Documentation-devicetree-Add-documentation-for-imx37.patch @@ -132,7 +132,7 @@ Signed-off-by: David Plowman +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -21553,6 +21553,7 @@ M: Raspberry Pi Kernel Maintenance static const struct vchiq_platform_info bcm2835_info = { .cache_line_size = 32, -@@ -1760,6 +1761,7 @@ static int vchiq_probe(struct platform_d +@@ -1759,6 +1760,7 @@ static int vchiq_probe(struct platform_d vchiq_debugfs_init(&mgmt->state); @@ -29,7 +29,7 @@ Signed-off-by: Dave Stevenson bcm2835_audio = vchiq_device_register(&pdev->dev, "bcm2835-audio"); bcm2835_camera = vchiq_device_register(&pdev->dev, "bcm2835-camera"); -@@ -1778,6 +1780,7 @@ static void vchiq_remove(struct platform +@@ -1777,6 +1779,7 @@ static void vchiq_remove(struct platform vchiq_device_unregister(bcm2835_audio); vchiq_device_unregister(bcm2835_camera); diff --git a/target/linux/bcm27xx/patches-6.12/950-0155-staging-vchiq_arm-Register-bcm2835-codec-as-a-platfo.patch b/target/linux/bcm27xx/patches-6.12/950-0155-staging-vchiq_arm-Register-bcm2835-codec-as-a-platfo.patch index 874bf15d34..acc70e2977 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0155-staging-vchiq_arm-Register-bcm2835-codec-as-a-platfo.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0155-staging-vchiq_arm-Register-bcm2835-codec-as-a-platfo.patch @@ -22,7 +22,7 @@ Signed-off-by: Dave Stevenson static struct vchiq_device *vcsm_cma; static const struct vchiq_platform_info bcm2835_info = { -@@ -1762,6 +1763,7 @@ static int vchiq_probe(struct platform_d +@@ -1761,6 +1762,7 @@ static int vchiq_probe(struct platform_d vchiq_debugfs_init(&mgmt->state); vcsm_cma = vchiq_device_register(&pdev->dev, "vcsm-cma"); @@ -30,7 +30,7 @@ Signed-off-by: Dave Stevenson bcm2835_audio = vchiq_device_register(&pdev->dev, "bcm2835-audio"); bcm2835_camera = vchiq_device_register(&pdev->dev, "bcm2835-camera"); -@@ -1780,6 +1782,7 @@ static void vchiq_remove(struct platform +@@ -1779,6 +1781,7 @@ static void vchiq_remove(struct platform vchiq_device_unregister(bcm2835_audio); vchiq_device_unregister(bcm2835_camera); diff --git a/target/linux/bcm27xx/patches-6.12/950-0157-phy-broadcom-split-out-the-BCM54213PE-from-the-BCM54.patch b/target/linux/bcm27xx/patches-6.12/950-0157-phy-broadcom-split-out-the-BCM54213PE-from-the-BCM54.patch index 9d17df4a18..950e93c5db 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0157-phy-broadcom-split-out-the-BCM54213PE-from-the-BCM54.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0157-phy-broadcom-split-out-the-BCM54213PE-from-the-BCM54.patch @@ -50,7 +50,7 @@ Signed-off-by: Jonathan Bell .phy_id_mask = 0xfffffff0, .name = "Broadcom BCM5461", @@ -1728,7 +1736,8 @@ module_phy_driver(broadcom_drivers); - static struct mdio_device_id __maybe_unused broadcom_tbl[] = { + static const struct mdio_device_id __maybe_unused broadcom_tbl[] = { { PHY_ID_BCM5411, 0xfffffff0 }, { PHY_ID_BCM5421, 0xfffffff0 }, - { PHY_ID_BCM54210E, 0xfffffff0 }, diff --git a/target/linux/bcm27xx/patches-6.12/950-0161-staging-vchiq_arm-Set-up-dma-ranges-on-child-devices.patch b/target/linux/bcm27xx/patches-6.12/950-0161-staging-vchiq_arm-Set-up-dma-ranges-on-child-devices.patch index 0c7fd01ec8..b2b470eaeb 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0161-staging-vchiq_arm-Set-up-dma-ranges-on-child-devices.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0161-staging-vchiq_arm-Set-up-dma-ranges-on-child-devices.patch @@ -234,7 +234,7 @@ Signed-off-by: Phil Elwell dev_dbg(&pdev->dev, "arm: vchiq_init - done (slots %pK, phys %pad)\n", vchiq_slot_zero, &slot_phys); -@@ -1711,6 +1777,7 @@ void vchiq_platform_conn_state_changed(s +@@ -1710,6 +1776,7 @@ void vchiq_platform_conn_state_changed(s static const struct of_device_id vchiq_of_match[] = { { .compatible = "brcm,bcm2835-vchiq", .data = &bcm2835_info }, { .compatible = "brcm,bcm2836-vchiq", .data = &bcm2836_info }, diff --git a/target/linux/bcm27xx/patches-6.12/950-0163-staging-vchiq-Load-bcm2835_isp-driver-from-vchiq.patch b/target/linux/bcm27xx/patches-6.12/950-0163-staging-vchiq-Load-bcm2835_isp-driver-from-vchiq.patch index 1ba21abf1d..c9394bc85b 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0163-staging-vchiq-Load-bcm2835_isp-driver-from-vchiq.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0163-staging-vchiq-Load-bcm2835_isp-driver-from-vchiq.patch @@ -21,7 +21,7 @@ Signed-off-by: Naushir Patuck static struct vchiq_device *vcsm_cma; static const struct vchiq_platform_info bcm2835_info = { -@@ -1858,6 +1859,7 @@ static int vchiq_probe(struct platform_d +@@ -1857,6 +1858,7 @@ static int vchiq_probe(struct platform_d bcm2835_codec = vchiq_device_register(&pdev->dev, "bcm2835-codec"); bcm2835_audio = vchiq_device_register(&pdev->dev, "bcm2835-audio"); bcm2835_camera = vchiq_device_register(&pdev->dev, "bcm2835-camera"); @@ -29,7 +29,7 @@ Signed-off-by: Naushir Patuck return 0; -@@ -1872,6 +1874,7 @@ static void vchiq_remove(struct platform +@@ -1871,6 +1873,7 @@ static void vchiq_remove(struct platform struct vchiq_drv_mgmt *mgmt = dev_get_drvdata(&pdev->dev); struct vchiq_arm_state *arm_state; diff --git a/target/linux/bcm27xx/patches-6.12/950-0295-media-adv7180-Nasty-hack-to-allow-input-selection.patch b/target/linux/bcm27xx/patches-6.12/950-0295-media-adv7180-Nasty-hack-to-allow-input-selection.patch index 30170d377f..c36033642b 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0295-media-adv7180-Nasty-hack-to-allow-input-selection.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0295-media-adv7180-Nasty-hack-to-allow-input-selection.patch @@ -30,7 +30,7 @@ Signed-off-by: Dave Stevenson struct adv7180_state; #define ADV7180_FLAG_RESET_POWERED BIT(0) -@@ -407,10 +411,24 @@ out: +@@ -408,10 +412,24 @@ out: return ret; } @@ -56,7 +56,7 @@ Signed-off-by: Dave Stevenson if (ret) return ret; -@@ -436,7 +454,11 @@ static int adv7180_program_std(struct ad +@@ -437,7 +455,11 @@ static int adv7180_program_std(struct ad static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std) { struct adv7180_state *state = to_state(sd); @@ -69,7 +69,7 @@ Signed-off-by: Dave Stevenson if (ret) return ret; -@@ -458,6 +480,8 @@ static int adv7180_g_std(struct v4l2_sub +@@ -459,6 +481,8 @@ static int adv7180_g_std(struct v4l2_sub { struct adv7180_state *state = to_state(sd); @@ -78,7 +78,7 @@ Signed-off-by: Dave Stevenson *norm = state->curr_norm; return 0; -@@ -895,6 +919,8 @@ static int adv7180_s_stream(struct v4l2_ +@@ -900,6 +924,8 @@ static int adv7180_s_stream(struct v4l2_ return 0; } diff --git a/target/linux/bcm27xx/patches-6.12/950-0303-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch b/target/linux/bcm27xx/patches-6.12/950-0303-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch index 891caa5b34..6329c752e6 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0303-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0303-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch @@ -137,7 +137,7 @@ Signed-off-by: Dave Stevenson +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -21597,6 +21597,14 @@ T: git git://linuxtv.org/media_tree.git +@@ -21599,6 +21599,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/imx519.yaml F: drivers/media/i2c/imx519.c diff --git a/target/linux/bcm27xx/patches-6.12/950-0315-media-i2c-imx219-Correct-the-minimum-vblanking-value.patch b/target/linux/bcm27xx/patches-6.12/950-0315-media-i2c-imx219-Correct-the-minimum-vblanking-value.patch deleted file mode 100644 index f82c2434e3..0000000000 --- a/target/linux/bcm27xx/patches-6.12/950-0315-media-i2c-imx219-Correct-the-minimum-vblanking-value.patch +++ /dev/null @@ -1,25 +0,0 @@ -From d2a776c4d38ccf0435083a90f51ed8886dd7aac9 Mon Sep 17 00:00:00 2001 -From: David Plowman -Date: Tue, 25 Jan 2022 15:48:53 +0000 -Subject: [PATCH] media: i2c: imx219: Correct the minimum vblanking value - -The datasheet for this sensor documents the minimum vblanking as being -32 lines. It does fix some problems with occasional black lines at the -bottom of images (tested on Raspberry Pi). - -Signed-off-by: David Plowman ---- - drivers/media/i2c/imx219.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/media/i2c/imx219.c -+++ b/drivers/media/i2c/imx219.c -@@ -74,7 +74,7 @@ - #define IMX219_REG_VTS CCI_REG16(0x0160) - #define IMX219_VTS_MAX 0xffff - --#define IMX219_VBLANK_MIN 4 -+#define IMX219_VBLANK_MIN 32 - - /* HBLANK control - read only */ - #define IMX219_PPL_DEFAULT 3448 diff --git a/target/linux/bcm27xx/patches-6.12/950-0318-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch b/target/linux/bcm27xx/patches-6.12/950-0318-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch index 49f631167b..ae1b01f6d5 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0318-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0318-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch @@ -271,7 +271,7 @@ Signed-off-by: Naushir Patuck +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -21602,7 +21602,7 @@ M: Raspberry Pi Kernel Maintenance if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c -@@ -3647,6 +3647,48 @@ static int xhci_align_td(struct xhci_hcd +@@ -3657,6 +3657,48 @@ static int xhci_align_td(struct xhci_hcd return 1; } @@ -124,7 +124,7 @@ Signed-off-by: Jonathan Bell /* This is very similar to what ehci-q.c qtd_fill() does */ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, int slot_id, unsigned int ep_index) -@@ -3801,6 +3843,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd * +@@ -3811,6 +3853,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd * } check_trb_math(urb, enqd_len); @@ -133,7 +133,7 @@ Signed-off-by: Jonathan Bell giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, start_cycle, start_trb); return 0; -@@ -3949,6 +3993,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd * +@@ -3959,6 +4003,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd * /* Event on completion */ field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); diff --git a/target/linux/bcm27xx/patches-6.12/950-0344-sdhci-Add-SD-Express-hook.patch b/target/linux/bcm27xx/patches-6.12/950-0344-sdhci-Add-SD-Express-hook.patch index 543a2239cf..7b843a0c09 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0344-sdhci-Add-SD-Express-hook.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0344-sdhci-Add-SD-Express-hook.patch @@ -27,7 +27,7 @@ sdhci: remove PYA0_INTR_BUG quirk. Add quirks to disable some of the higher SDR .postinit = dwcmshc_rk35xx_postinit, --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c -@@ -3032,6 +3032,15 @@ static void sdhci_card_event(struct mmc_ +@@ -3037,6 +3037,15 @@ static void sdhci_card_event(struct mmc_ spin_unlock_irqrestore(&host->lock, flags); } @@ -43,7 +43,7 @@ sdhci: remove PYA0_INTR_BUG quirk. Add quirks to disable some of the higher SDR static const struct mmc_host_ops sdhci_ops = { .request = sdhci_request, .post_req = sdhci_post_req, -@@ -3047,6 +3056,7 @@ static const struct mmc_host_ops sdhci_o +@@ -3052,6 +3061,7 @@ static const struct mmc_host_ops sdhci_o .execute_tuning = sdhci_execute_tuning, .card_event = sdhci_card_event, .card_busy = sdhci_card_busy, @@ -51,7 +51,7 @@ sdhci: remove PYA0_INTR_BUG quirk. Add quirks to disable some of the higher SDR }; /*****************************************************************************\ -@@ -4565,6 +4575,15 @@ int sdhci_setup_host(struct sdhci_host * +@@ -4570,6 +4580,15 @@ int sdhci_setup_host(struct sdhci_host * !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) mmc->caps |= MMC_CAP_UHS_DDR50; diff --git a/target/linux/bcm27xx/patches-6.12/950-0396-drivers-mmc-sdhci-add-SPURIOUS_INT_RESP-quirk.patch b/target/linux/bcm27xx/patches-6.12/950-0396-drivers-mmc-sdhci-add-SPURIOUS_INT_RESP-quirk.patch index 93a9205f4a..e79dbb75d6 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0396-drivers-mmc-sdhci-add-SPURIOUS_INT_RESP-quirk.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0396-drivers-mmc-sdhci-add-SPURIOUS_INT_RESP-quirk.patch @@ -36,7 +36,7 @@ Signed-off-by: Jonathan Bell sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); return true; -@@ -3291,6 +3297,11 @@ static void sdhci_cmd_irq(struct sdhci_h +@@ -3296,6 +3302,11 @@ static void sdhci_cmd_irq(struct sdhci_h if (intmask & SDHCI_INT_TIMEOUT) { host->cmd->error = -ETIMEDOUT; sdhci_err_stats_inc(host, CMD_TIMEOUT); diff --git a/target/linux/bcm27xx/patches-6.12/950-0401-xhci-Use-more-event-ring-segment-table-entries.patch b/target/linux/bcm27xx/patches-6.12/950-0401-xhci-Use-more-event-ring-segment-table-entries.patch index 29357c0757..6baba3b443 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0401-xhci-Use-more-event-ring-segment-table-entries.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0401-xhci-Use-more-event-ring-segment-table-entries.patch @@ -21,7 +21,7 @@ Signed-off-by: Jonathan Bell --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1392,7 +1392,7 @@ struct urb_priv { +@@ -1395,7 +1395,7 @@ struct urb_priv { }; /* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */ diff --git a/target/linux/bcm27xx/patches-6.12/950-0406-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch b/target/linux/bcm27xx/patches-6.12/950-0406-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch index 6e055038bb..70e51011e4 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0406-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0406-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch @@ -67,7 +67,7 @@ Signed-off-by: Jacopo Mondi +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -20060,6 +20060,13 @@ S: Supported +@@ -20062,6 +20062,13 @@ S: Supported F: drivers/iio/light/rohm-bu27008.c F: drivers/iio/light/rohm-bu27034.c diff --git a/target/linux/bcm27xx/patches-6.12/950-0409-media-i2c-adv7180-Use-MEDIA_BUS_FMT_UYVY8_1X16-for-C.patch b/target/linux/bcm27xx/patches-6.12/950-0409-media-i2c-adv7180-Use-MEDIA_BUS_FMT_UYVY8_1X16-for-C.patch index 9b86b31a5d..5790d79ade 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0409-media-i2c-adv7180-Use-MEDIA_BUS_FMT_UYVY8_1X16-for-C.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0409-media-i2c-adv7180-Use-MEDIA_BUS_FMT_UYVY8_1X16-for-C.patch @@ -17,7 +17,7 @@ Signed-off-by: Dave Stevenson --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c -@@ -732,10 +732,15 @@ static int adv7180_enum_mbus_code(struct +@@ -737,10 +737,15 @@ static int adv7180_enum_mbus_code(struct struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) { @@ -34,7 +34,7 @@ Signed-off-by: Dave Stevenson return 0; } -@@ -745,7 +750,10 @@ static int adv7180_mbus_fmt(struct v4l2_ +@@ -750,7 +755,10 @@ static int adv7180_mbus_fmt(struct v4l2_ { struct adv7180_state *state = to_state(sd); diff --git a/target/linux/bcm27xx/patches-6.12/950-0410-media-i2c-adv7180-Add-support-for-V4L2_CID_LINK_FREQ.patch b/target/linux/bcm27xx/patches-6.12/950-0410-media-i2c-adv7180-Add-support-for-V4L2_CID_LINK_FREQ.patch index c0df6346e8..4bc7a684eb 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0410-media-i2c-adv7180-Add-support-for-V4L2_CID_LINK_FREQ.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0410-media-i2c-adv7180-Add-support-for-V4L2_CID_LINK_FREQ.patch @@ -32,7 +32,7 @@ Signed-off-by: Dave Stevenson static int dbg_input; module_param(dbg_input, int, 0644); MODULE_PARM_DESC(dbg_input, "Input number (0-31)"); -@@ -228,6 +238,7 @@ struct adv7180_state { +@@ -229,6 +239,7 @@ struct adv7180_state { const struct adv7180_chip_info *chip_info; enum v4l2_field field; bool force_bt656_4; @@ -40,7 +40,7 @@ Signed-off-by: Dave Stevenson }; #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \ struct adv7180_state, \ -@@ -629,6 +640,9 @@ static int adv7180_s_ctrl(struct v4l2_ct +@@ -630,6 +641,9 @@ static int adv7180_s_ctrl(struct v4l2_ct if (ret) return ret; @@ -50,7 +50,7 @@ Signed-off-by: Dave Stevenson val = ctrl->val; switch (ctrl->id) { case V4L2_CID_BRIGHTNESS: -@@ -670,6 +684,7 @@ static int adv7180_s_ctrl(struct v4l2_ct +@@ -671,6 +685,7 @@ static int adv7180_s_ctrl(struct v4l2_ct ret = -EINVAL; } @@ -58,7 +58,7 @@ Signed-off-by: Dave Stevenson mutex_unlock(&state->mutex); return ret; } -@@ -690,7 +705,7 @@ static const struct v4l2_ctrl_config adv +@@ -691,7 +706,7 @@ static const struct v4l2_ctrl_config adv static int adv7180_init_controls(struct adv7180_state *state) { @@ -67,9 +67,9 @@ Signed-off-by: Dave Stevenson v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN, -@@ -712,6 +727,17 @@ static int adv7180_init_controls(struct - 0, ARRAY_SIZE(test_pattern_menu) - 1, - test_pattern_menu); +@@ -717,6 +732,17 @@ static int adv7180_init_controls(struct + test_pattern_menu); + } + if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { + state->link_freq = @@ -85,7 +85,7 @@ Signed-off-by: Dave Stevenson state->sd.ctrl_handler = &state->ctrl_hdl; if (state->ctrl_hdl.error) { int err = state->ctrl_hdl.error; -@@ -844,6 +870,10 @@ static int adv7180_set_pad_format(struct +@@ -849,6 +875,10 @@ static int adv7180_set_pad_format(struct adv7180_set_power(state, false); adv7180_set_field_mode(state); adv7180_set_power(state, true); diff --git a/target/linux/bcm27xx/patches-6.12/950-0437-mmc-sdhci-extend-maximum-ADMA-transfer-length-to-4Mi.patch b/target/linux/bcm27xx/patches-6.12/950-0437-mmc-sdhci-extend-maximum-ADMA-transfer-length-to-4Mi.patch index dc580e53ee..6a1c5a1be1 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0437-mmc-sdhci-extend-maximum-ADMA-transfer-length-to-4Mi.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0437-mmc-sdhci-extend-maximum-ADMA-transfer-length-to-4Mi.patch @@ -23,7 +23,7 @@ Signed-off-by: Jonathan Bell BUG_ON(data->blksz > host->mmc->max_blk_size); BUG_ON(data->blocks > 65535); -@@ -4709,11 +4709,16 @@ int sdhci_setup_host(struct sdhci_host * +@@ -4714,11 +4714,16 @@ int sdhci_setup_host(struct sdhci_host * spin_lock_init(&host->lock); /* diff --git a/target/linux/bcm27xx/patches-6.12/950-0482-spi-dt-bindings-Add-RPI-RP2040-GPIO-Bridge.patch b/target/linux/bcm27xx/patches-6.12/950-0482-spi-dt-bindings-Add-RPI-RP2040-GPIO-Bridge.patch index 69f1b6f200..4a3fd18513 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0482-spi-dt-bindings-Add-RPI-RP2040-GPIO-Bridge.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0482-spi-dt-bindings-Add-RPI-RP2040-GPIO-Bridge.patch @@ -94,7 +94,7 @@ Signed-off-by: Richard Oliver + --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -19353,6 +19353,11 @@ L: linux-edac@vger.kernel.org +@@ -19355,6 +19355,11 @@ L: linux-edac@vger.kernel.org S: Maintained F: drivers/ras/amd/fmpm.c diff --git a/target/linux/bcm27xx/patches-6.12/950-0483-spi-Add-a-driver-for-the-RPI-RP2040-GPIO-bridge.patch b/target/linux/bcm27xx/patches-6.12/950-0483-spi-Add-a-driver-for-the-RPI-RP2040-GPIO-bridge.patch index 28943e1d54..088410484b 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0483-spi-Add-a-driver-for-the-RPI-RP2040-GPIO-bridge.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0483-spi-Add-a-driver-for-the-RPI-RP2040-GPIO-bridge.patch @@ -42,7 +42,7 @@ Signed-off-by: Richard Oliver --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -19357,6 +19357,7 @@ RASPBERRY PI RP2040 GPIO BRIDGE DRIVER +@@ -19359,6 +19359,7 @@ RASPBERRY PI RP2040 GPIO BRIDGE DRIVER M: Raspberry Pi Kernel Maintenance S: Maintained F: Documentation/devicetree/bindings/spi/raspberrypi,rp2040-gpio-bridge.yaml diff --git a/target/linux/bcm27xx/patches-6.12/950-0504-media-dt-bindings-i2c-Add-Sony-IMX500.patch b/target/linux/bcm27xx/patches-6.12/950-0504-media-dt-bindings-i2c-Add-Sony-IMX500.patch index e61900b6c8..4818c64bf2 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0504-media-dt-bindings-i2c-Add-Sony-IMX500.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0504-media-dt-bindings-i2c-Add-Sony-IMX500.patch @@ -150,7 +150,7 @@ Signed-off-by: Richard Oliver + --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -21602,6 +21602,13 @@ F: Documentation/devicetree/bindings/med +@@ -21604,6 +21604,13 @@ F: Documentation/devicetree/bindings/med F: Documentation/devicetree/bindings/media/i2c/imx477.yaml F: drivers/media/i2c/imx477.c diff --git a/target/linux/bcm27xx/patches-6.12/950-0505-media-i2c-Add-driver-for-Sony-IMX500-sensor.patch b/target/linux/bcm27xx/patches-6.12/950-0505-media-i2c-Add-driver-for-Sony-IMX500-sensor.patch index d895a9c8e1..08b57ed3b0 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0505-media-i2c-Add-driver-for-Sony-IMX500-sensor.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0505-media-i2c-Add-driver-for-Sony-IMX500-sensor.patch @@ -58,7 +58,7 @@ Signed-off-by: Naushir Patuck --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -21608,6 +21608,7 @@ L: linux-media@vger.kernel.org +@@ -21610,6 +21610,7 @@ L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/sony,imx500.yaml diff --git a/target/linux/bcm27xx/patches-6.12/950-0534-drivers-usb-xhci-set-HID-bit-in-streaming-endpoint-c.patch b/target/linux/bcm27xx/patches-6.12/950-0534-drivers-usb-xhci-set-HID-bit-in-streaming-endpoint-c.patch index 70c09d06d2..9a052443c0 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0534-drivers-usb-xhci-set-HID-bit-in-streaming-endpoint-c.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0534-drivers-usb-xhci-set-HID-bit-in-streaming-endpoint-c.patch @@ -45,7 +45,7 @@ Signed-off-by: Jonathan Bell --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -465,6 +465,8 @@ struct xhci_ep_ctx { +@@ -468,6 +468,8 @@ struct xhci_ep_ctx { #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ #define EP_HAS_LSA (1 << 15) diff --git a/target/linux/bcm27xx/patches-6.12/950-0765-drm-gem-Create-a-drm_gem_object_init_with_mnt-functi.patch b/target/linux/bcm27xx/patches-6.12/950-0765-drm-gem-Create-a-drm_gem_object_init_with_mnt-functi.patch index d2355fbe78..5cbc75da2f 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0765-drm-gem-Create-a-drm_gem_object_init_with_mnt-functi.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0765-drm-gem-Create-a-drm_gem_object_init_with_mnt-functi.patch @@ -88,7 +88,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20240923141348.2422499-5-mca /** --- a/include/drm/drm_gem.h +++ b/include/drm/drm_gem.h -@@ -473,6 +473,9 @@ void drm_gem_object_release(struct drm_g +@@ -474,6 +474,9 @@ void drm_gem_object_release(struct drm_g void drm_gem_object_free(struct kref *kref); int drm_gem_object_init(struct drm_device *dev, struct drm_gem_object *obj, size_t size); diff --git a/target/linux/bcm27xx/patches-6.12/950-0834-media-platform-Add-Raspberry-Pi-HEVC-decoder-driver.patch b/target/linux/bcm27xx/patches-6.12/950-0834-media-platform-Add-Raspberry-Pi-HEVC-decoder-driver.patch index d1f2745be8..459c9ea358 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0834-media-platform-Add-Raspberry-Pi-HEVC-decoder-driver.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0834-media-platform-Add-Raspberry-Pi-HEVC-decoder-driver.patch @@ -36,7 +36,7 @@ Signed-off-by: Dave Stevenson --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -19359,6 +19359,16 @@ S: Maintained +@@ -19361,6 +19361,16 @@ S: Maintained F: Documentation/devicetree/bindings/spi/raspberrypi,rp2040-gpio-bridge.yaml F: drivers/spi/spi-rp2040-gpio-bridge.c diff --git a/target/linux/bcm27xx/patches-6.12/950-0857-drm-v3d-Add-clock-handling.patch b/target/linux/bcm27xx/patches-6.12/950-0857-drm-v3d-Add-clock-handling.patch deleted file mode 100644 index 73f9c362e6..0000000000 --- a/target/linux/bcm27xx/patches-6.12/950-0857-drm-v3d-Add-clock-handling.patch +++ /dev/null @@ -1,99 +0,0 @@ -From d3976b4e3830d608c155713dd2f7c36839897ec5 Mon Sep 17 00:00:00 2001 -From: Stefan Wahren -Date: Sat, 1 Feb 2025 13:50:46 +0100 -Subject: [PATCH] drm/v3d: Add clock handling -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Since the initial commit 57692c94dcbe ("drm/v3d: Introduce a new DRM driver -for Broadcom V3D V3.x+") the struct v3d_dev reserved a pointer for -an optional V3D clock. But there wasn't any code, which fetched it. -So add the missing clock handling before accessing any V3D registers. - -Signed-off-by: Stefan Wahren -Reviewed-by: Maíra Canal -Signed-off-by: Maíra Canal -Link: https://patchwork.freedesktop.org/patch/msgid/20250201125046.33030-1-wahrenst@gmx.net ---- - drivers/gpu/drm/v3d/v3d_drv.c | 25 ++++++++++++++++++++----- - 1 file changed, 20 insertions(+), 5 deletions(-) - ---- a/drivers/gpu/drm/v3d/v3d_drv.c -+++ b/drivers/gpu/drm/v3d/v3d_drv.c -@@ -304,11 +304,21 @@ static int v3d_platform_drm_probe(struct - if (ret) - return ret; - -+ v3d->clk = devm_clk_get_optional(dev, NULL); -+ if (IS_ERR(v3d->clk)) -+ return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n"); -+ -+ ret = clk_prepare_enable(v3d->clk); -+ if (ret) { -+ dev_err(&pdev->dev, "Couldn't enable the V3D clock\n"); -+ return ret; -+ } -+ - mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); - mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); - ret = dma_set_mask_and_coherent(dev, mask); - if (ret) -- return ret; -+ goto clk_disable; - - v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); - -@@ -328,14 +338,14 @@ static int v3d_platform_drm_probe(struct - ret = PTR_ERR(v3d->reset); - - if (ret == -EPROBE_DEFER) -- return ret; -+ goto clk_disable; - - v3d->reset = NULL; - ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); - if (ret) { - dev_err(dev, - "Failed to get reset control or bridge regs\n"); -- return ret; -+ goto clk_disable; - } - } - -@@ -370,14 +380,15 @@ static int v3d_platform_drm_probe(struct - if (v3d->ver < 41) { - ret = map_regs(v3d, &v3d->gca_regs, "gca"); - if (ret) -- return ret; -+ goto clk_disable; - } - - v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, - GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); - if (!v3d->mmu_scratch) { - dev_err(dev, "Failed to allocate MMU scratch page\n"); -- return -ENOMEM; -+ ret = -ENOMEM; -+ goto clk_disable; - } - - ret = v3d_gem_init(drm); -@@ -408,6 +419,8 @@ gem_destroy: - v3d_gem_destroy(drm); - dma_free: - dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); -+clk_disable: -+ clk_disable_unprepare(v3d->clk); - return ret; - } - -@@ -425,6 +438,8 @@ static void v3d_platform_drm_remove(stru - - dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, - v3d->mmu_scratch_paddr); -+ -+ clk_disable_unprepare(v3d->clk); - } - - static struct platform_driver v3d_platform_driver = { diff --git a/target/linux/bcm27xx/patches-6.12/950-0874-PCI-brcmstb-Expand-inbound-window-size-up-to-64GB.patch b/target/linux/bcm27xx/patches-6.12/950-0874-PCI-brcmstb-Expand-inbound-window-size-up-to-64GB.patch deleted file mode 100644 index d9c3a62e8e..0000000000 --- a/target/linux/bcm27xx/patches-6.12/950-0874-PCI-brcmstb-Expand-inbound-window-size-up-to-64GB.patch +++ /dev/null @@ -1,38 +0,0 @@ -From f46dc47bb16ebca678b357c38d16d586357ffbeb Mon Sep 17 00:00:00 2001 -From: Stanimir Varbanov -Date: Mon, 24 Feb 2025 10:35:58 +0200 -Subject: [PATCH] PCI: brcmstb: Expand inbound window size up to 64GB -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The BCM2712 memory map can support up to 64GB of system memory, thus -expand the inbound window size in calculation helper function. - -The change is safe for the currently supported SoCs that have smaller -inbound window sizes. - -Signed-off-by: Stanimir Varbanov -Reviewed-by: Florian Fainelli -Reviewed-by: Jim Quinlan -Tested-by: Ivan T. Ivanov -Link: https://lore.kernel.org/r/20250120130119.671119-6-svarbanov@suse.de -[kwilczynski: commit log] -Signed-off-by: Krzysztof Wilczyński ---- - drivers/pci/controller/pcie-brcmstb.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/pci/controller/pcie-brcmstb.c -+++ b/drivers/pci/controller/pcie-brcmstb.c -@@ -304,8 +304,8 @@ static int brcm_pcie_encode_ibar_size(u6 - if (log2_in >= 12 && log2_in <= 15) - /* Covers 4KB to 32KB (inclusive) */ - return (log2_in - 12) + 0x1c; -- else if (log2_in >= 16 && log2_in <= 35) -- /* Covers 64KB to 32GB, (inclusive) */ -+ else if (log2_in >= 16 && log2_in <= 36) -+ /* Covers 64KB to 64GB, (inclusive) */ - return log2_in - 15; - /* Something is awry so disable */ - return 0; diff --git a/target/linux/bcm27xx/patches-6.12/950-0877-PCI-brcmstb-Adding-a-softdep-to-MIP-MSI-X-driver.patch b/target/linux/bcm27xx/patches-6.12/950-0877-PCI-brcmstb-Adding-a-softdep-to-MIP-MSI-X-driver.patch deleted file mode 100644 index f480952b14..0000000000 --- a/target/linux/bcm27xx/patches-6.12/950-0877-PCI-brcmstb-Adding-a-softdep-to-MIP-MSI-X-driver.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d0b8d7cc6cb1120acca237958d3d88bfcd75976a Mon Sep 17 00:00:00 2001 -From: Stanimir Varbanov -Date: Mon, 24 Feb 2025 10:35:56 +0200 -Subject: [PATCH] PCI: brcmstb: Adding a softdep to MIP MSI-X driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -In case brcmstb PCIe driver and MIP MSI-X interrupt controller -drivers are built as modules there could be a race in probing. - -To avoid this add a softdep to MIP driver to guarantee that MIP -driver will be load first. - -Signed-off-by: Stanimir Varbanov -Reviewed-by: Florian Fainelli -Tested-by: Ivan T. Ivanov -Link: https://lore.kernel.org/r/20250120130119.671119-9-svarbanov@suse.de -[kwilczynski: commit log] -Signed-off-by: Krzysztof Wilczyński ---- - drivers/pci/controller/pcie-brcmstb.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/pci/controller/pcie-brcmstb.c -+++ b/drivers/pci/controller/pcie-brcmstb.c -@@ -2004,3 +2004,4 @@ module_platform_driver(brcm_pcie_driver) - MODULE_LICENSE("GPL"); - MODULE_DESCRIPTION("Broadcom STB PCIe RC driver"); - MODULE_AUTHOR("Broadcom"); -+MODULE_SOFTDEP("pre: irq_bcm2712_mip"); diff --git a/target/linux/bcm27xx/patches-6.12/950-0959-media-imx335-Support-vertical-flip.patch b/target/linux/bcm27xx/patches-6.12/950-0959-media-imx335-Support-vertical-flip.patch index a5f9b2866e..8d5815ecd5 100644 --- a/target/linux/bcm27xx/patches-6.12/950-0959-media-imx335-Support-vertical-flip.patch +++ b/target/linux/bcm27xx/patches-6.12/950-0959-media-imx335-Support-vertical-flip.patch @@ -142,7 +142,7 @@ Reviewed-by: Kieran Bingham static int imx335_update_test_pattern(struct imx335 *imx335, u32 pattern_index) { int ret = 0; -@@ -585,6 +641,10 @@ static int imx335_set_ctrl(struct v4l2_c +@@ -594,6 +650,10 @@ static int imx335_set_ctrl(struct v4l2_c ret = imx335_update_exp_gain(imx335, exposure, analog_gain); break; @@ -153,7 +153,7 @@ Reviewed-by: Kieran Bingham case V4L2_CID_TEST_PATTERN: ret = imx335_update_test_pattern(imx335, ctrl->val); -@@ -1166,7 +1226,7 @@ static int imx335_init_controls(struct i +@@ -1175,7 +1235,7 @@ static int imx335_init_controls(struct i return ret; /* v4l2_fwnode_device_properties can add two more controls */ @@ -162,7 +162,7 @@ Reviewed-by: Kieran Bingham if (ret) return ret; -@@ -1201,6 +1261,13 @@ static int imx335_init_controls(struct i +@@ -1210,6 +1270,13 @@ static int imx335_init_controls(struct i v4l2_ctrl_cluster(2, &imx335->exp_ctrl); diff --git a/target/linux/bcm27xx/patches-6.12/950-0960-media-imx335-Set-vblank-immediately.patch b/target/linux/bcm27xx/patches-6.12/950-0960-media-imx335-Set-vblank-immediately.patch deleted file mode 100644 index f70ee2148a..0000000000 --- a/target/linux/bcm27xx/patches-6.12/950-0960-media-imx335-Set-vblank-immediately.patch +++ /dev/null @@ -1,52 +0,0 @@ -From a9a2c30bb67cbf1e03d312e02eb659ef9673b123 Mon Sep 17 00:00:00 2001 -From: Paul Elder -Date: Fri, 14 Feb 2025 18:03:53 +0900 -Subject: [PATCH] media: imx335: Set vblank immediately - -When the vblank v4l2 control is set, it does not get written to the -hardware immediately. It only gets updated when exposure is set. Change -the behavior such that the vblank is written immediately when the -control is set. - -Commit c0aa40f45fef ("media: imx335: Set vblank immediately")' upstream - -Signed-off-by: Paul Elder ---- - drivers/media/i2c/imx335.c | 19 +++++++++++++------ - 1 file changed, 13 insertions(+), 6 deletions(-) - ---- a/drivers/media/i2c/imx335.c -+++ b/drivers/media/i2c/imx335.c -@@ -615,12 +615,12 @@ static int imx335_set_ctrl(struct v4l2_c - imx335->vblank, - imx335->vblank + imx335->cur_mode->height); - -- return __v4l2_ctrl_modify_range(imx335->exp_ctrl, -- IMX335_EXPOSURE_MIN, -- imx335->vblank + -- imx335->cur_mode->height - -- IMX335_EXPOSURE_OFFSET, -- 1, IMX335_EXPOSURE_DEFAULT); -+ __v4l2_ctrl_modify_range(imx335->exp_ctrl, -+ IMX335_EXPOSURE_MIN, -+ imx335->vblank + -+ imx335->cur_mode->height - -+ IMX335_EXPOSURE_OFFSET, -+ 1, IMX335_EXPOSURE_DEFAULT); - } - - /* -@@ -631,6 +631,13 @@ static int imx335_set_ctrl(struct v4l2_c - return 0; - - switch (ctrl->id) { -+ case V4L2_CID_VBLANK: -+ exposure = imx335->exp_ctrl->val; -+ analog_gain = imx335->again_ctrl->val; -+ -+ ret = imx335_update_exp_gain(imx335, exposure, analog_gain); -+ -+ break; - case V4L2_CID_EXPOSURE: - exposure = ctrl->val; - analog_gain = imx335->again_ctrl->val; diff --git a/target/linux/bcm27xx/patches-6.12/950-1003-drivers-media-i2c-imx335-Fix-frame-size-enumeration.patch b/target/linux/bcm27xx/patches-6.12/950-1003-drivers-media-i2c-imx335-Fix-frame-size-enumeration.patch index e55c49476f..89701b06c8 100644 --- a/target/linux/bcm27xx/patches-6.12/950-1003-drivers-media-i2c-imx335-Fix-frame-size-enumeration.patch +++ b/target/linux/bcm27xx/patches-6.12/950-1003-drivers-media-i2c-imx335-Fix-frame-size-enumeration.patch @@ -22,7 +22,7 @@ Signed-off-by: Kieran Bingham --- a/drivers/media/i2c/imx335.c +++ b/drivers/media/i2c/imx335.c -@@ -718,7 +718,8 @@ static int imx335_enum_frame_size(struct +@@ -720,7 +720,8 @@ static int imx335_enum_frame_size(struct struct imx335 *imx335 = to_imx335(sd); u32 code; diff --git a/target/linux/bmips/Makefile b/target/linux/bmips/Makefile index 3e3106cc0c..f7e0a3cd01 100644 --- a/target/linux/bmips/Makefile +++ b/target/linux/bmips/Makefile @@ -9,7 +9,7 @@ BOARDNAME:=Broadcom BMIPS SUBTARGETS:=bcm6318 bcm6328 bcm6358 bcm6362 bcm6368 bcm63268 FEATURES:=gpio squashfs usb -KERNEL_PATCHVER:=6.6 +KERNEL_PATCHVER:=6.12 define Target/Description Build firmware images for BCM33xx cable modem chips, diff --git a/target/linux/bmips/bcm6318/config-6.6 b/target/linux/bmips/bcm6318/config-6.12 similarity index 97% rename from target/linux/bmips/bcm6318/config-6.6 rename to target/linux/bmips/bcm6318/config-6.12 index e01970155d..0851a2eb69 100644 --- a/target/linux/bmips/bcm6318/config-6.6 +++ b/target/linux/bmips/bcm6318/config-6.12 @@ -44,10 +44,9 @@ CONFIG_CPU_RMAP=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_CPUFREQ=y CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y CONFIG_CRC16=y CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_GF128MUL=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 @@ -57,6 +56,7 @@ CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_ZSTD=y CONFIG_CSRC_R4K=y CONFIG_DEBUG_INFO=y +CONFIG_DMA_NEED_SYNC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DTC=y # CONFIG_DT_BCM93384WVG is not set @@ -124,7 +124,6 @@ CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y -CONFIG_KEXEC_CORE=y # CONFIG_LEDS_SERCOMM_MSP430 is not set CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y @@ -209,7 +208,6 @@ CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHYLIB_LEDS=y CONFIG_PHYLINK=y -CONFIG_PHYSICAL_START=0x80010000 CONFIG_PHY_BCM63XX_USBH=y # CONFIG_PHY_BRCM_SATA is not set CONFIG_PINCTRL=y @@ -229,8 +227,6 @@ CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_SUPPLY=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PROC_VMCORE=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y @@ -250,7 +246,6 @@ CONFIG_SGL_ALLOC=y CONFIG_SMP=y CONFIG_SMP_UP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BCM63XX=y CONFIG_SPI=y # CONFIG_SPI_BCM63XX is not set CONFIG_SPI_BCM63XX_HSSPI=y diff --git a/target/linux/bmips/bcm63268/base-files/etc/board.d/03_gpio_switches b/target/linux/bmips/bcm63268/base-files/etc/board.d/03_gpio_switches index 75ac111b0c..2e754ad498 100644 --- a/target/linux/bmips/bcm63268/base-files/etc/board.d/03_gpio_switches +++ b/target/linux/bmips/bcm63268/base-files/etc/board.d/03_gpio_switches @@ -2,12 +2,21 @@ . /lib/functions/uci-defaults.sh +KERNEL_MAJOR=$(uname -r | awk -F '.' '{print $1}') +KERNEL_MINOR=$(uname -r | awk -F '.' '{print $2}') + board_config_update +if [ "${KERNEL_MAJOR}" -ge "6" ] && [ "${KERNEL_MINOR}" -ge "12" ]; then + GPIO_BASE=512 +else + GPIO_BASE=460 +fi + case "$(board_name)" in sercomm,h500-s-lowi |\ sercomm,h500-s-vfes) - ucidef_add_gpio_switch "qtn_power" "Quantenna Module Power" "480" "1" + ucidef_add_gpio_switch "qtn_power" "Quantenna Module Power" "$(($GPIO_BASE + 20))" "1" ;; esac diff --git a/target/linux/bmips/bcm63268/config-6.6 b/target/linux/bmips/bcm63268/config-6.12 similarity index 97% rename from target/linux/bmips/bcm63268/config-6.6 rename to target/linux/bmips/bcm63268/config-6.12 index 00609efc15..2cc5a85d08 100644 --- a/target/linux/bmips/bcm63268/config-6.6 +++ b/target/linux/bmips/bcm63268/config-6.12 @@ -44,10 +44,9 @@ CONFIG_CPU_RMAP=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_CPUFREQ=y CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y CONFIG_CRC16=y CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_GF128MUL=y @@ -58,6 +57,7 @@ CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_ZSTD=y CONFIG_CSRC_R4K=y CONFIG_DEBUG_INFO=y +CONFIG_DMA_NEED_SYNC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DTC=y # CONFIG_DT_BCM93384WVG is not set @@ -127,7 +127,6 @@ CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y -CONFIG_KEXEC_CORE=y # CONFIG_LEDS_SERCOMM_MSP430 is not set CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y @@ -223,7 +222,6 @@ CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHYLIB_LEDS=y CONFIG_PHYLINK=y -CONFIG_PHYSICAL_START=0x80010000 CONFIG_PHY_BCM63XX_USBH=y # CONFIG_PHY_BRCM_SATA is not set CONFIG_PINCTRL=y @@ -243,8 +241,6 @@ CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_SUPPLY=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PROC_VMCORE=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y @@ -264,7 +260,6 @@ CONFIG_SGL_ALLOC=y CONFIG_SMP=y CONFIG_SMP_UP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BCM63XX=y CONFIG_SPI=y CONFIG_SPI_BCM63XX=y CONFIG_SPI_BCM63XX_HSSPI=y diff --git a/target/linux/bmips/bcm6328/config-6.6 b/target/linux/bmips/bcm6328/config-6.12 similarity index 97% rename from target/linux/bmips/bcm6328/config-6.6 rename to target/linux/bmips/bcm6328/config-6.12 index ac6c5d4ab4..00582dd277 100644 --- a/target/linux/bmips/bcm6328/config-6.6 +++ b/target/linux/bmips/bcm6328/config-6.12 @@ -44,10 +44,9 @@ CONFIG_CPU_RMAP=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_CPUFREQ=y CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y CONFIG_CRC16=y CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_GF128MUL=y @@ -58,6 +57,7 @@ CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_ZSTD=y CONFIG_CSRC_R4K=y CONFIG_DEBUG_INFO=y +CONFIG_DMA_NEED_SYNC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DTC=y # CONFIG_DT_BCM93384WVG is not set @@ -125,7 +125,6 @@ CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y -CONFIG_KEXEC_CORE=y # CONFIG_LEDS_SERCOMM_MSP430 is not set CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y @@ -222,7 +221,6 @@ CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHYLIB_LEDS=y CONFIG_PHYLINK=y -CONFIG_PHYSICAL_START=0x80010000 CONFIG_PHY_BCM63XX_USBH=y # CONFIG_PHY_BRCM_SATA is not set CONFIG_PINCTRL=y @@ -242,8 +240,6 @@ CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_SUPPLY=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PROC_VMCORE=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y @@ -263,7 +259,6 @@ CONFIG_SGL_ALLOC=y CONFIG_SMP=y CONFIG_SMP_UP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BCM63XX=y CONFIG_SPI=y # CONFIG_SPI_BCM63XX is not set CONFIG_SPI_BCM63XX_HSSPI=y diff --git a/target/linux/bmips/bcm6358/config-6.6 b/target/linux/bmips/bcm6358/config-6.12 similarity index 97% rename from target/linux/bmips/bcm6358/config-6.6 rename to target/linux/bmips/bcm6358/config-6.12 index 395f68c6c6..9829ecad47 100644 --- a/target/linux/bmips/bcm6358/config-6.6 +++ b/target/linux/bmips/bcm6358/config-6.12 @@ -11,6 +11,7 @@ CONFIG_BCM6345_EXT_IRQ=y CONFIG_BCM6345_L1_IRQ=y CONFIG_BCM6348_ENET=y # CONFIG_BCM6368_ENETSW is not set +# CONFIG_BCM63XX_POWER is not set CONFIG_BCM7038_WDT=y CONFIG_BLK_MQ_PCI=y CONFIG_BLK_PM=y @@ -42,10 +43,9 @@ CONFIG_CPU_RMAP=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_CPUFREQ=y CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y CONFIG_CRC16=y CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_GF128MUL=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 @@ -55,6 +55,7 @@ CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_ZSTD=y CONFIG_CSRC_R4K=y CONFIG_DEBUG_INFO=y +CONFIG_DMA_NEED_SYNC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DTC=y # CONFIG_DT_BCM93384WVG is not set @@ -122,7 +123,6 @@ CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y -CONFIG_KEXEC_CORE=y # CONFIG_LEDS_SERCOMM_MSP430 is not set CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y @@ -205,7 +205,6 @@ CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHYLIB_LEDS=y CONFIG_PHYLINK=y -CONFIG_PHYSICAL_START=0x80010000 CONFIG_PHY_BCM63XX_USBH=y # CONFIG_PHY_BRCM_SATA is not set CONFIG_PINCTRL=y @@ -223,8 +222,6 @@ CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_SUPPLY=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PROC_VMCORE=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y @@ -244,7 +241,6 @@ CONFIG_SGL_ALLOC=y CONFIG_SMP=y CONFIG_SMP_UP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y -# CONFIG_SOC_BCM63XX is not set CONFIG_SPI=y CONFIG_SPI_BCM63XX=y CONFIG_SPI_MASTER=y diff --git a/target/linux/bmips/bcm6362/config-6.6 b/target/linux/bmips/bcm6362/config-6.12 similarity index 97% rename from target/linux/bmips/bcm6362/config-6.6 rename to target/linux/bmips/bcm6362/config-6.12 index 06b5e06dd3..a247ee77b6 100644 --- a/target/linux/bmips/bcm6362/config-6.6 +++ b/target/linux/bmips/bcm6362/config-6.12 @@ -44,10 +44,9 @@ CONFIG_CPU_RMAP=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_CPUFREQ=y CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y CONFIG_CRC16=y CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_GF128MUL=y @@ -58,6 +57,7 @@ CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_ZSTD=y CONFIG_CSRC_R4K=y CONFIG_DEBUG_INFO=y +CONFIG_DMA_NEED_SYNC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DTC=y # CONFIG_DT_BCM93384WVG is not set @@ -127,7 +127,6 @@ CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y -CONFIG_KEXEC_CORE=y # CONFIG_LEDS_SERCOMM_MSP430 is not set CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y @@ -223,7 +222,6 @@ CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHYLIB_LEDS=y CONFIG_PHYLINK=y -CONFIG_PHYSICAL_START=0x80010000 CONFIG_PHY_BCM63XX_USBH=y # CONFIG_PHY_BRCM_SATA is not set CONFIG_PINCTRL=y @@ -243,8 +241,6 @@ CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_SUPPLY=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PROC_VMCORE=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y @@ -264,7 +260,6 @@ CONFIG_SGL_ALLOC=y CONFIG_SMP=y CONFIG_SMP_UP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BCM63XX=y CONFIG_SPI=y CONFIG_SPI_BCM63XX=y CONFIG_SPI_BCM63XX_HSSPI=y diff --git a/target/linux/bmips/bcm6368/config-6.6 b/target/linux/bmips/bcm6368/config-6.12 similarity index 97% rename from target/linux/bmips/bcm6368/config-6.6 rename to target/linux/bmips/bcm6368/config-6.12 index c191ba2a79..ffe3317b50 100644 --- a/target/linux/bmips/bcm6368/config-6.6 +++ b/target/linux/bmips/bcm6368/config-6.12 @@ -12,6 +12,7 @@ CONFIG_BCM6345_EXT_IRQ=y CONFIG_BCM6345_L1_IRQ=y # CONFIG_BCM6348_ENET is not set CONFIG_BCM6368_ENETSW=y +# CONFIG_BCM63XX_POWER is not set CONFIG_BCM7038_WDT=y CONFIG_BLK_MQ_PCI=y CONFIG_BLK_PM=y @@ -43,10 +44,9 @@ CONFIG_CPU_RMAP=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_CPUFREQ=y CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y CONFIG_CRC16=y CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_GF128MUL=y @@ -57,6 +57,7 @@ CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_ZSTD=y CONFIG_CSRC_R4K=y CONFIG_DEBUG_INFO=y +CONFIG_DMA_NEED_SYNC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DTC=y # CONFIG_DT_BCM93384WVG is not set @@ -126,7 +127,6 @@ CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y -CONFIG_KEXEC_CORE=y # CONFIG_LEDS_SERCOMM_MSP430 is not set CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y @@ -221,7 +221,6 @@ CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHYLIB_LEDS=y CONFIG_PHYLINK=y -CONFIG_PHYSICAL_START=0x80010000 CONFIG_PHY_BCM63XX_USBH=y # CONFIG_PHY_BRCM_SATA is not set CONFIG_PINCTRL=y @@ -239,8 +238,6 @@ CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_SUPPLY=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PROC_VMCORE=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y @@ -260,7 +257,6 @@ CONFIG_SGL_ALLOC=y CONFIG_SMP=y CONFIG_SMP_UP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y -# CONFIG_SOC_BCM63XX is not set CONFIG_SPI=y CONFIG_SPI_BCM63XX=y CONFIG_SPI_MASTER=y diff --git a/target/linux/bmips/patches-6.6/100-irqchip-add-support-for-bcm6345-style-external-inter.patch b/target/linux/bmips/patches-6.12/100-irqchip-add-support-for-bcm6345-style-external-inter.patch similarity index 99% rename from target/linux/bmips/patches-6.6/100-irqchip-add-support-for-bcm6345-style-external-inter.patch rename to target/linux/bmips/patches-6.12/100-irqchip-add-support-for-bcm6345-style-external-inter.patch index 9516e1c80c..5829fee2ed 100644 --- a/target/linux/bmips/patches-6.6/100-irqchip-add-support-for-bcm6345-style-external-inter.patch +++ b/target/linux/bmips/patches-6.12/100-irqchip-add-support-for-bcm6345-style-external-inter.patch @@ -50,7 +50,7 @@ Signed-off-by: Jonas Gorski +}; --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig -@@ -111,6 +111,10 @@ config I8259 +@@ -109,6 +109,10 @@ config I8259 bool select IRQ_DOMAIN diff --git a/target/linux/bmips/patches-6.12/110-net-dsa-b53-do-not-enable-EEE-on-bcm63xx.patch b/target/linux/bmips/patches-6.12/110-net-dsa-b53-do-not-enable-EEE-on-bcm63xx.patch new file mode 100644 index 0000000000..96a9d9ff14 --- /dev/null +++ b/target/linux/bmips/patches-6.12/110-net-dsa-b53-do-not-enable-EEE-on-bcm63xx.patch @@ -0,0 +1,41 @@ +From 2ba8f6d6759ec0bb1eaf3840eb2201a5d4931126 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 19 May 2025 19:45:48 +0200 +Subject: [PATCH] net: dsa: b53: do not enable EEE on bcm63xx + +BCM63xx internal switches do not support EEE, but provide multiple RGMII +ports where external PHYs may be connected. If one of these PHYs are EEE +capable, we may try to enable EEE for the MACs, which then hangs the +system on access of the (non-existent) EEE registers. + +Fix this by checking if the switch actually supports EEE before +attempting to configure it. + +Fixes: 22256b0afb12 ("net: dsa: b53: Move EEE functions to b53") +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +--- + drivers/net/dsa/b53/b53_common.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -2353,6 +2353,9 @@ int b53_eee_init(struct dsa_switch *ds, + { + int ret; + ++ if (!b53_support_eee(ds, port)) ++ return 0; ++ + ret = phy_init_eee(phy, false); + if (ret) + return 0; +@@ -2367,7 +2370,7 @@ bool b53_support_eee(struct dsa_switch * + { + struct b53_device *dev = ds->priv; + +- return !is5325(dev) && !is5365(dev); ++ return !is5325(dev) && !is5365(dev) && !is63xx(dev); + } + EXPORT_SYMBOL(b53_support_eee); + diff --git a/target/linux/bmips/patches-6.12/111-net-dsa-b53-allow-RGMII-for-bcm63xx-RGMII-ports.patch b/target/linux/bmips/patches-6.12/111-net-dsa-b53-allow-RGMII-for-bcm63xx-RGMII-ports.patch new file mode 100644 index 0000000000..8ef8f1c10b --- /dev/null +++ b/target/linux/bmips/patches-6.12/111-net-dsa-b53-allow-RGMII-for-bcm63xx-RGMII-ports.patch @@ -0,0 +1,34 @@ +From b1308c8642f6a75b4494370784fba86dd2f0b0e0 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 19 May 2025 19:45:50 +0200 +Subject: [PATCH] net: dsa: b53: allow RGMII for bcm63xx RGMII ports + +Add RGMII to supported interfaces for BCM63xx RGMII ports so they can be +actually used in RGMII mode. + +Without this, phylink will fail to configure them: + +[ 3.580000] b53-switch 10700000.switch GbE3 (uninitialized): validation of rgmii with support 0000000,00000000,00000000,000062ff and advertisement 0000000,00000000,00000000,000062ff failed: -EINVAL +[ 3.600000] b53-switch 10700000.switch GbE3 (uninitialized): failed to connect to PHY: -EINVAL +[ 3.610000] b53-switch 10700000.switch GbE3 (uninitialized): error -22 setting up PHY for tree 0, switch 0, port 4 + +Fixes: ce3bf94871f7 ("net: dsa: b53: add support for BCM63xx RGMIIs") +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +--- + drivers/net/dsa/b53/b53_common.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -1462,6 +1462,10 @@ static void b53_phylink_get_caps(struct + __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces); + ++ /* BCM63xx RGMII ports support RGMII */ ++ if (is63xx(dev) && port >= B53_63XX_RGMII0) ++ phy_interface_set_rgmii(config->supported_interfaces); ++ + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100; + diff --git a/target/linux/bmips/patches-6.6/200-mips-bmips-automatically-detect-CPU-frequency.patch b/target/linux/bmips/patches-6.12/200-mips-bmips-automatically-detect-CPU-frequency.patch similarity index 100% rename from target/linux/bmips/patches-6.6/200-mips-bmips-automatically-detect-CPU-frequency.patch rename to target/linux/bmips/patches-6.12/200-mips-bmips-automatically-detect-CPU-frequency.patch diff --git a/target/linux/bmips/patches-6.6/201-mips-bmips-automatically-detect-RAM-size.patch b/target/linux/bmips/patches-6.12/201-mips-bmips-automatically-detect-RAM-size.patch similarity index 100% rename from target/linux/bmips/patches-6.6/201-mips-bmips-automatically-detect-RAM-size.patch rename to target/linux/bmips/patches-6.12/201-mips-bmips-automatically-detect-RAM-size.patch diff --git a/target/linux/bmips/patches-6.6/202-mips-bmips-tweak-Kconfig-options.patch b/target/linux/bmips/patches-6.12/202-mips-bmips-tweak-Kconfig-options.patch similarity index 92% rename from target/linux/bmips/patches-6.6/202-mips-bmips-tweak-Kconfig-options.patch rename to target/linux/bmips/patches-6.12/202-mips-bmips-tweak-Kconfig-options.patch index 3c6a0eb7a0..e7a69b8184 100644 --- a/target/linux/bmips/patches-6.6/202-mips-bmips-tweak-Kconfig-options.patch +++ b/target/linux/bmips/patches-6.12/202-mips-bmips-tweak-Kconfig-options.patch @@ -13,7 +13,7 @@ Signed-off-by: Álvaro Fernández Rojas --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -272,19 +272,13 @@ config BMIPS_GENERIC +@@ -259,19 +259,13 @@ config BMIPS_GENERIC select SYNC_R4K select COMMON_CLK select BCM6345_L1_IRQ @@ -33,7 +33,7 @@ Signed-off-by: Álvaro Fernández Rojas select SWAP_IO_SPACE select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN -@@ -294,6 +288,7 @@ config BMIPS_GENERIC +@@ -281,6 +275,7 @@ config BMIPS_GENERIC select HAVE_PCI select PCI_DRIVERS_GENERIC select FW_CFE @@ -43,7 +43,7 @@ Signed-off-by: Álvaro Fernández Rojas BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig -@@ -124,7 +124,6 @@ config BCM6345_L1_IRQ +@@ -122,7 +122,6 @@ config BCM6345_L1_IRQ config BCM7038_L1_IRQ tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" depends on ARCH_BRCMSTB || BMIPS_GENERIC @@ -51,7 +51,7 @@ Signed-off-by: Álvaro Fernández Rojas select GENERIC_IRQ_CHIP select IRQ_DOMAIN select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP -@@ -132,14 +131,12 @@ config BCM7038_L1_IRQ +@@ -130,14 +129,12 @@ config BCM7038_L1_IRQ config BCM7120_L2_IRQ tristate "Broadcom STB 7120-style L2 interrupt controller driver" depends on ARCH_BRCMSTB || BMIPS_GENERIC diff --git a/target/linux/bmips/patches-6.6/500-net-broadcom-add-BCM6368-enetsw-controller-driver.patch b/target/linux/bmips/patches-6.12/500-net-broadcom-add-BCM6368-enetsw-controller-driver.patch similarity index 100% rename from target/linux/bmips/patches-6.6/500-net-broadcom-add-BCM6368-enetsw-controller-driver.patch rename to target/linux/bmips/patches-6.12/500-net-broadcom-add-BCM6368-enetsw-controller-driver.patch diff --git a/target/linux/bmips/patches-6.6/501-net-broadcom-add-BCM6348-enet-controller-driver.patch b/target/linux/bmips/patches-6.12/501-net-broadcom-add-BCM6348-enet-controller-driver.patch similarity index 100% rename from target/linux/bmips/patches-6.6/501-net-broadcom-add-BCM6348-enet-controller-driver.patch rename to target/linux/bmips/patches-6.12/501-net-broadcom-add-BCM6348-enet-controller-driver.patch diff --git a/target/linux/bmips/patches-6.6/502-net-mdio-mux-bcm6368-allow-disabling.patch b/target/linux/bmips/patches-6.12/502-net-mdio-mux-bcm6368-allow-disabling.patch similarity index 100% rename from target/linux/bmips/patches-6.6/502-net-mdio-mux-bcm6368-allow-disabling.patch rename to target/linux/bmips/patches-6.12/502-net-mdio-mux-bcm6368-allow-disabling.patch diff --git a/target/linux/bmips/patches-6.6/600-mips-bmips-add-pci-support.patch b/target/linux/bmips/patches-6.12/600-mips-bmips-add-pci-support.patch similarity index 96% rename from target/linux/bmips/patches-6.6/600-mips-bmips-add-pci-support.patch rename to target/linux/bmips/patches-6.12/600-mips-bmips-add-pci-support.patch index f28dda908d..76833e3e2d 100644 --- a/target/linux/bmips/patches-6.6/600-mips-bmips-add-pci-support.patch +++ b/target/linux/bmips/patches-6.12/600-mips-bmips-add-pci-support.patch @@ -14,7 +14,7 @@ Signed-off-by: Álvaro Fernández Rojas --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -286,7 +286,6 @@ config BMIPS_GENERIC +@@ -273,7 +273,6 @@ config BMIPS_GENERIC select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN select HARDIRQS_SW_RESEND select HAVE_PCI diff --git a/target/linux/bmips/patches-6.6/601-pci-controllers-add-bcm6328-pcie-support.patch b/target/linux/bmips/patches-6.12/601-pci-controllers-add-bcm6328-pcie-support.patch similarity index 100% rename from target/linux/bmips/patches-6.6/601-pci-controllers-add-bcm6328-pcie-support.patch rename to target/linux/bmips/patches-6.12/601-pci-controllers-add-bcm6328-pcie-support.patch diff --git a/target/linux/bmips/patches-6.6/602-pci-controllers-add-bcm6318-pcie-support.patch b/target/linux/bmips/patches-6.12/602-pci-controllers-add-bcm6318-pcie-support.patch similarity index 100% rename from target/linux/bmips/patches-6.6/602-pci-controllers-add-bcm6318-pcie-support.patch rename to target/linux/bmips/patches-6.12/602-pci-controllers-add-bcm6318-pcie-support.patch diff --git a/target/linux/bmips/patches-6.6/603-pci-controllers-add-bcm6348-pci-support.patch b/target/linux/bmips/patches-6.12/603-pci-controllers-add-bcm6348-pci-support.patch similarity index 100% rename from target/linux/bmips/patches-6.6/603-pci-controllers-add-bcm6348-pci-support.patch rename to target/linux/bmips/patches-6.12/603-pci-controllers-add-bcm6348-pci-support.patch diff --git a/target/linux/bmips/patches-6.6/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch b/target/linux/bmips/patches-6.12/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch similarity index 78% rename from target/linux/bmips/patches-6.6/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch rename to target/linux/bmips/patches-6.12/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch index 0b9a29b18f..8e92e39675 100644 --- a/target/linux/bmips/patches-6.6/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch +++ b/target/linux/bmips/patches-6.12/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch @@ -17,7 +17,7 @@ Signed-off-by: Álvaro Fernández Rojas --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -299,6 +299,15 @@ config LEDS_COBALT_RAQ +@@ -328,6 +328,15 @@ config LEDS_COBALT_RAQ help This option enables support for the Cobalt Raq series LEDs. @@ -27,19 +27,19 @@ Signed-off-by: Álvaro Fernández Rojas + depends on SPI + depends on OF + help -+ This option enables support for the Sercomm MSP430G2513 SPI LED ++ This option enables support for the Sercomm MSP430G2513 SPI LED + controllers. + - config LEDS_SUNFIRE - tristate "LED support for SunFire servers." - depends on LEDS_CLASS + config LEDS_SUN50I_A100 + tristate "LED support for Allwinner A100 RGB LED controller" + depends on LEDS_CLASS_MULTICOLOR --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile -@@ -78,6 +78,7 @@ obj-$(CONFIG_LEDS_POWERNV) += leds-powe +@@ -81,6 +81,7 @@ obj-$(CONFIG_LEDS_POWERNV) += leds-powe obj-$(CONFIG_LEDS_PWM) += leds-pwm.o obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o +obj-$(CONFIG_LEDS_SERCOMM_MSP430) += leds-sercomm-msp430.o + obj-$(CONFIG_LEDS_SUN50I_A100) += leds-sun50i-a100.o obj-$(CONFIG_LEDS_ST1202) += leds-st1202.o obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o - obj-$(CONFIG_LEDS_SYSCON) += leds-syscon.o diff --git a/target/linux/bmips/patches-6.6/800-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch b/target/linux/bmips/patches-6.12/800-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch similarity index 100% rename from target/linux/bmips/patches-6.6/800-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch rename to target/linux/bmips/patches-6.12/800-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch diff --git a/target/linux/bmips/patches-6.6/210-revert-macronix-nand-block-protection.patch b/target/linux/bmips/patches-6.6/210-revert-macronix-nand-block-protection.patch deleted file mode 100644 index 2298c8ea31..0000000000 --- a/target/linux/bmips/patches-6.6/210-revert-macronix-nand-block-protection.patch +++ /dev/null @@ -1,114 +0,0 @@ -From 5a37811de679bff03e9c5a746f75574910ede964 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 22 Mar 2023 20:52:13 +0100 -Subject: [PATCH] Revert "mtd: rawnand: Macronix: Add support for block - protection" -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This reverts commit 03a539c7a118427a6609a26461358c56ac8f3a06. - -Macronix block protection doesn't seem to be supported on Sercomm H-500s -devices since it hangs the device. - -Signed-off-by: Álvaro Fernández Rojas ---- - drivers/mtd/nand/raw/nand_macronix.c | 72 ---------------------------- - 1 file changed, 72 deletions(-) - ---- a/drivers/mtd/nand/raw/nand_macronix.c -+++ b/drivers/mtd/nand/raw/nand_macronix.c -@@ -13,10 +13,6 @@ - #define MACRONIX_READ_RETRY_BIT BIT(0) - #define MACRONIX_NUM_READ_RETRY_MODES 6 - --#define ONFI_FEATURE_ADDR_MXIC_PROTECTION 0xA0 --#define MXIC_BLOCK_PROTECTION_ALL_LOCK 0x38 --#define MXIC_BLOCK_PROTECTION_ALL_UNLOCK 0x0 -- - #define ONFI_FEATURE_ADDR_MXIC_RANDOMIZER 0xB0 - #define MACRONIX_RANDOMIZER_BIT BIT(1) - #define MACRONIX_RANDOMIZER_ENPGM BIT(0) -@@ -189,73 +185,6 @@ static void macronix_nand_fix_broken_get - ONFI_FEATURE_ADDR_TIMING_MODE, 1); - } - --/* -- * Macronix NAND supports Block Protection by Protectoin(PT) pin; -- * active high at power-on which protects the entire chip even the #WP is -- * disabled. Lock/unlock protection area can be partition according to -- * protection bits, i.e. upper 1/2 locked, upper 1/4 locked and so on. -- */ --static int mxic_nand_lock(struct nand_chip *chip, loff_t ofs, uint64_t len) --{ -- u8 feature[ONFI_SUBFEATURE_PARAM_LEN]; -- int ret; -- -- feature[0] = MXIC_BLOCK_PROTECTION_ALL_LOCK; -- nand_select_target(chip, 0); -- ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION, -- feature); -- nand_deselect_target(chip); -- if (ret) -- pr_err("%s all blocks failed\n", __func__); -- -- return ret; --} -- --static int mxic_nand_unlock(struct nand_chip *chip, loff_t ofs, uint64_t len) --{ -- u8 feature[ONFI_SUBFEATURE_PARAM_LEN]; -- int ret; -- -- feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK; -- nand_select_target(chip, 0); -- ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION, -- feature); -- nand_deselect_target(chip); -- if (ret) -- pr_err("%s all blocks failed\n", __func__); -- -- return ret; --} -- --static void macronix_nand_block_protection_support(struct nand_chip *chip) --{ -- u8 feature[ONFI_SUBFEATURE_PARAM_LEN]; -- int ret; -- -- bitmap_set(chip->parameters.get_feature_list, -- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1); -- -- feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK; -- nand_select_target(chip, 0); -- ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION, -- feature); -- nand_deselect_target(chip); -- if (ret || feature[0] != MXIC_BLOCK_PROTECTION_ALL_LOCK) { -- if (ret) -- pr_err("Block protection check failed\n"); -- -- bitmap_clear(chip->parameters.get_feature_list, -- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1); -- return; -- } -- -- bitmap_set(chip->parameters.set_feature_list, -- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1); -- -- chip->ops.lock_area = mxic_nand_lock; -- chip->ops.unlock_area = mxic_nand_unlock; --} -- - static int nand_power_down_op(struct nand_chip *chip) - { - int ret; -@@ -488,7 +417,6 @@ static int macronix_nand_init(struct nan - - macronix_nand_fix_broken_get_timings(chip); - macronix_nand_onfi_init(chip); -- macronix_nand_block_protection_support(chip); - macronix_nand_deep_power_down_support(chip); - macronix_nand_setup_otp(chip); - diff --git a/target/linux/d1/config-6.12 b/target/linux/d1/config-6.12 index 676fe26bbe..9a49062a3e 100644 --- a/target/linux/d1/config-6.12 +++ b/target/linux/d1/config-6.12 @@ -46,7 +46,35 @@ CONFIG_CRC16=y CONFIG_CRC32_SLICEBY8=y CONFIG_CRC7=y CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_DEV_ALLWINNER=y +# CONFIG_CRYPTO_DEV_SUN4I_SS is not set +CONFIG_CRYPTO_DEV_SUN8I_CE=y +# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y +CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y +# CONFIG_CRYPTO_DEV_SUN8I_SS is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ENGINE=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y CONFIG_DECOMPRESS_GZIP=y CONFIG_DMADEVICES=y CONFIG_DMA_DIRECT_REMAP=y @@ -168,8 +196,6 @@ CONFIG_JBD2=y CONFIG_KALLSYMS=y # CONFIG_KERNEL_UNCOMPRESSED is not set # CONFIG_KEYBOARD_SUN4I_LRADC is not set -# CONFIG_LEDS_PWM_MULTICOLOR is not set -# CONFIG_LEDS_SUN50I_A100 is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 CONFIG_LIBFDT=y @@ -262,6 +288,8 @@ CONFIG_PINCTRL_SUN20I_D1=y # CONFIG_PINCTRL_SUN9I_A80 is not set # CONFIG_PINCTRL_SUN9I_A80_R is not set CONFIG_PINCTRL_SUNXI=y +CONFIG_PM=y +CONFIG_PM_CLK=y CONFIG_PORTABLE=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POWER_RESET=y @@ -279,7 +307,6 @@ CONFIG_PWM=y # CONFIG_PWM_SUN4I is not set # CONFIG_PWM_SUN8I_V536 is not set CONFIG_PWM_SYSFS=y -# CONFIG_PWM_XILINX is not set CONFIG_RATIONAL=y CONFIG_RCU_TRACE=y CONFIG_REALTEK_PHY=y @@ -366,6 +393,7 @@ CONFIG_STMMAC_PLATFORM=y CONFIG_SUN20I_D1_CCU=y CONFIG_SUN20I_D1_R_CCU=y CONFIG_SUN20I_GPADC=y +CONFIG_SUN20I_PPU=y # CONFIG_SUN4I_EMAC is not set CONFIG_SUN4I_TIMER=y CONFIG_SUN50I_IOMMU=y diff --git a/target/linux/d1/image/Makefile b/target/linux/d1/image/Makefile index 5bca3fbc15..b16cdde6ad 100644 --- a/target/linux/d1/image/Makefile +++ b/target/linux/d1/image/Makefile @@ -87,6 +87,7 @@ define Device/allwinner_d1-nezha DEVICE_MODEL := D1 DEVICE_DTS := allwinner/sun20i-d1-nezha SUPPORTED_DEVICES += nezha + DEVICE_PACKAGES += kmod-gpio-pcf857x UBOOT := nezha endef TARGET_DEVICES += allwinner_d1-nezha diff --git a/target/linux/d1/patches-6.12/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch b/target/linux/d1/patches-6.12/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch index 6d1562233a..25cb88436a 100644 --- a/target/linux/d1/patches-6.12/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch +++ b/target/linux/d1/patches-6.12/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch @@ -16,7 +16,7 @@ Signed-off-by: Maksim Kiselev --- a/sound/soc/sunxi/sun4i-codec.c +++ b/sound/soc/sunxi/sun4i-codec.c -@@ -228,15 +228,65 @@ +@@ -229,16 +229,66 @@ /* TODO H3 DAP (Digital Audio Processing) bits */ @@ -76,6 +76,7 @@ Signed-off-by: Maksim Kiselev + struct clk *clk_module_dac; struct reset_control *rst; struct gpio_desc *gpio_pa; + struct gpio_desc *gpio_hp; + const struct sun4i_codec_quirks *quirks; - /* ADC_FIFOC register is at different offset on different SoCs */ @@ -84,7 +85,7 @@ Signed-off-by: Maksim Kiselev struct regmap_field *reg_adc_fifoc; struct snd_dmaengine_dai_dma_data capture_dma_data; -@@ -246,33 +296,33 @@ struct sun4i_codec { +@@ -248,33 +298,33 @@ struct sun4i_codec { static void sun4i_codec_start_playback(struct sun4i_codec *scodec) { /* Flush TX FIFO */ @@ -126,7 +127,7 @@ Signed-off-by: Maksim Kiselev } static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd, -@@ -321,8 +371,8 @@ static int sun4i_codec_prepare_capture(s +@@ -323,8 +373,8 @@ static int sun4i_codec_prepare_capture(s /* Set RX FIFO trigger level */ regmap_field_update_bits(scodec->reg_adc_fifoc, @@ -137,7 +138,7 @@ Signed-off-by: Maksim Kiselev /* * FIXME: Undocumented in the datasheet, but -@@ -356,13 +406,13 @@ static int sun4i_codec_prepare_playback( +@@ -358,13 +408,13 @@ static int sun4i_codec_prepare_playback( u32 val; /* Flush the TX FIFO */ @@ -156,7 +157,7 @@ Signed-off-by: Maksim Kiselev if (substream->runtime->rate > 32000) /* Use 64 bits FIR filter */ -@@ -371,13 +421,12 @@ static int sun4i_codec_prepare_playback( +@@ -373,13 +423,12 @@ static int sun4i_codec_prepare_playback( /* Use 32 bits FIR filter */ val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION); @@ -174,7 +175,7 @@ Signed-off-by: Maksim Kiselev return 0; }; -@@ -472,30 +521,32 @@ static int sun4i_codec_hw_params_capture +@@ -474,30 +523,32 @@ static int sun4i_codec_hw_params_capture 7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS, hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS); @@ -218,7 +219,7 @@ Signed-off-by: Maksim Kiselev scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; } -@@ -510,9 +561,9 @@ static int sun4i_codec_hw_params_playbac +@@ -512,9 +563,9 @@ static int sun4i_codec_hw_params_playbac u32 val; /* Set DAC sample rate */ @@ -231,7 +232,7 @@ Signed-off-by: Maksim Kiselev /* Set the number of channels we want to use */ if (params_channels(params) == 1) -@@ -520,27 +571,26 @@ static int sun4i_codec_hw_params_playbac +@@ -522,27 +573,26 @@ static int sun4i_codec_hw_params_playbac else val = 0; @@ -269,7 +270,7 @@ Signed-off-by: Maksim Kiselev scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; } -@@ -561,7 +611,11 @@ static int sun4i_codec_hw_params(struct +@@ -563,7 +613,11 @@ static int sun4i_codec_hw_params(struct if (!clk_freq) return -EINVAL; @@ -282,7 +283,7 @@ Signed-off-by: Maksim Kiselev if (ret) return ret; -@@ -587,10 +641,14 @@ static int sun4i_codec_startup(struct sn +@@ -589,10 +643,14 @@ static int sun4i_codec_startup(struct sn * Stop issuing DRQ when we have room for less than 16 samples * in our TX FIFO */ @@ -300,7 +301,7 @@ Signed-off-by: Maksim Kiselev } static void sun4i_codec_shutdown(struct snd_pcm_substream *substream, -@@ -599,7 +657,11 @@ static void sun4i_codec_shutdown(struct +@@ -601,7 +659,11 @@ static void sun4i_codec_shutdown(struct struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); @@ -313,7 +314,7 @@ Signed-off-by: Maksim Kiselev } static const struct snd_soc_dai_ops sun4i_codec_dai_ops = { -@@ -1216,6 +1278,55 @@ static const struct snd_soc_component_dr +@@ -1218,6 +1280,55 @@ static const struct snd_soc_component_dr .endianness = 1, }; @@ -369,7 +370,7 @@ Signed-off-by: Maksim Kiselev static const struct snd_soc_component_driver sun4i_codec_component = { .name = "sun4i-codec", .legacy_dai_naming = 1, -@@ -1518,6 +1629,66 @@ static struct snd_soc_card *sun8i_v3s_co +@@ -1564,6 +1675,66 @@ static struct snd_soc_card *sun8i_v3s_co return card; }; @@ -436,7 +437,7 @@ Signed-off-by: Maksim Kiselev static const struct regmap_config sun4i_codec_regmap_config = { .reg_bits = 32, .reg_stride = 4, -@@ -1560,21 +1731,22 @@ static const struct regmap_config sun8i_ +@@ -1606,21 +1777,22 @@ static const struct regmap_config sun8i_ .max_register = SUN8I_H3_CODEC_ADC_DBG, }; @@ -467,7 +468,7 @@ Signed-off-by: Maksim Kiselev .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA, }; -@@ -1583,7 +1755,11 @@ static const struct sun4i_codec_quirks s +@@ -1629,7 +1801,11 @@ static const struct sun4i_codec_quirks s .regmap_config = &sun6i_codec_regmap_config, .codec = &sun6i_codec_codec, .create_card = sun6i_codec_create_card, @@ -479,7 +480,7 @@ Signed-off-by: Maksim Kiselev .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, .has_reset = true, -@@ -1593,7 +1769,11 @@ static const struct sun4i_codec_quirks s +@@ -1639,7 +1815,11 @@ static const struct sun4i_codec_quirks s .regmap_config = &sun7i_codec_regmap_config, .codec = &sun7i_codec_codec, .create_card = sun4i_codec_create_card, @@ -491,7 +492,7 @@ Signed-off-by: Maksim Kiselev .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA, }; -@@ -1602,7 +1782,11 @@ static const struct sun4i_codec_quirks s +@@ -1648,7 +1828,11 @@ static const struct sun4i_codec_quirks s .regmap_config = &sun8i_a23_codec_regmap_config, .codec = &sun8i_a23_codec_codec, .create_card = sun8i_a23_codec_create_card, @@ -503,7 +504,7 @@ Signed-off-by: Maksim Kiselev .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, .has_reset = true, -@@ -1617,7 +1801,11 @@ static const struct sun4i_codec_quirks s +@@ -1663,7 +1847,11 @@ static const struct sun4i_codec_quirks s */ .codec = &sun8i_a23_codec_codec, .create_card = sun8i_h3_codec_create_card, @@ -515,7 +516,7 @@ Signed-off-by: Maksim Kiselev .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA, .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, .has_reset = true, -@@ -1631,12 +1819,31 @@ static const struct sun4i_codec_quirks s +@@ -1677,12 +1865,31 @@ static const struct sun4i_codec_quirks s */ .codec = &sun8i_a23_codec_codec, .create_card = sun8i_v3s_codec_create_card, @@ -547,7 +548,7 @@ Signed-off-by: Maksim Kiselev static const struct of_device_id sun4i_codec_of_match[] = { { .compatible = "allwinner,sun4i-a10-codec", -@@ -1662,6 +1869,10 @@ static const struct of_device_id sun4i_c +@@ -1708,6 +1915,10 @@ static const struct of_device_id sun4i_c .compatible = "allwinner,sun8i-v3s-codec", .data = &sun8i_v3s_codec_quirks, }, @@ -558,7 +559,7 @@ Signed-off-by: Maksim Kiselev {} }; MODULE_DEVICE_TABLE(of, sun4i_codec_of_match); -@@ -1690,6 +1901,7 @@ static int sun4i_codec_probe(struct plat +@@ -1736,6 +1947,7 @@ static int sun4i_codec_probe(struct plat dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); return -ENODEV; } @@ -566,7 +567,7 @@ Signed-off-by: Maksim Kiselev scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base, quirks->regmap_config); -@@ -1705,10 +1917,24 @@ static int sun4i_codec_probe(struct plat +@@ -1751,10 +1963,24 @@ static int sun4i_codec_probe(struct plat return PTR_ERR(scodec->clk_apb); } @@ -595,7 +596,7 @@ Signed-off-by: Maksim Kiselev } if (quirks->has_reset) { -@@ -1737,6 +1963,16 @@ static int sun4i_codec_probe(struct plat +@@ -1790,6 +2016,16 @@ static int sun4i_codec_probe(struct plat dev_err(&pdev->dev, "Failed to create regmap fields: %d\n", ret); return ret; diff --git a/target/linux/gemini/Makefile b/target/linux/gemini/Makefile index ddfe67be2b..03dde94052 100644 --- a/target/linux/gemini/Makefile +++ b/target/linux/gemini/Makefile @@ -11,7 +11,7 @@ FEATURES:=squashfs pci rtc usb usbgadget dt gpio display ext4 rootfs-part boot-p CPU_TYPE:=fa526 SUBTARGETS:=generic -KERNEL_PATCHVER:=6.6 +KERNEL_PATCHVER:=6.12 define Target/Description Build firmware images for the StorLink/Cortina Gemini CS351x ARM FA526 CPU diff --git a/target/linux/gemini/config-6.6 b/target/linux/gemini/config-6.12 similarity index 99% rename from target/linux/gemini/config-6.6 rename to target/linux/gemini/config-6.12 index 04bb2b70ca..658aff1322 100644 --- a/target/linux/gemini/config-6.6 +++ b/target/linux/gemini/config-6.12 @@ -260,7 +260,6 @@ CONFIG_LOGO_LINUX_CLUT224=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LZ4_DECOMPRESS=y CONFIG_LZO_DECOMPRESS=y -CONFIG_MARVELL_PHY=y CONFIG_MDIO_BITBANG=y CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y @@ -355,7 +354,6 @@ CONFIG_RD_LZ4=y CONFIG_RD_LZMA=y CONFIG_RD_LZO=y CONFIG_RD_XZ=y -CONFIG_REALTEK_PHY=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_MMIO=y @@ -437,7 +435,6 @@ CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_VIDEO_CMDLINE=y CONFIG_VIDEO_NOMODESET=y -CONFIG_VITESSE_PHY=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_VT=y CONFIG_VT_CONSOLE=y diff --git a/target/linux/gemini/image/Makefile b/target/linux/gemini/image/Makefile index c5d09e7120..fe84a84676 100644 --- a/target/linux/gemini/image/Makefile +++ b/target/linux/gemini/image/Makefile @@ -170,7 +170,7 @@ define Device/dlink_dns-313 DEVICE_VENDOR := D-Link DEVICE_MODEL := DNS-313 1-Bay Network Storage Enclosure DEVICE_DTS := gemini-dlink-dns-313 - DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES) usbgadget-acm + DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES) usbgadget-acm kmod-phy-realtek BLOCKSIZE := 1k FILESYSTEMS := ext4 IMAGES := factory.bin.gz @@ -186,7 +186,7 @@ define Device/storlink-reference FILESYSTEMS := squashfs IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to 6144k | \ storlink-default-images $(1) - DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES) + DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES) kmod-phy-realtek endef define Device/itian_sq201 @@ -194,7 +194,7 @@ define Device/itian_sq201 DEVICE_VENDOR := ITian DEVICE_MODEL := Square One SQ201 DEVICE_DTS := gemini-sq201 - DEVICE_PACKAGES += kmod-rt61-pci kmod-usb2-pci + DEVICE_PACKAGES += kmod-rt61-pci kmod-usb2-pci kmod-phy-marvell endef TARGET_DEVICES += itian_sq201 @@ -203,6 +203,7 @@ define Device/raidsonic_ib-4220-b DEVICE_VENDOR := Raidsonic DEVICE_MODEL := NAS IB-4220-B DEVICE_DTS := gemini-nas4220b + DEVICE_PACKAGES += kmod-phy-marvell endef TARGET_DEVICES += raidsonic_ib-4220-b @@ -211,6 +212,7 @@ define Device/storlink_sl93512r DEVICE_VENDOR := StorLink DEVICE_MODEL := SL93512r DEVICE_DTS := gemini-sl93512r + DEVICE_PACKAGES += kmod-phy-marvell endef TARGET_DEVICES += storlink_sl93512r diff --git a/target/linux/gemini/patches-6.12/0001-net-ethernet-cortina-Use-TOE-TSO-on-all-TCP.patch b/target/linux/gemini/patches-6.12/0001-net-ethernet-cortina-Use-TOE-TSO-on-all-TCP.patch new file mode 100644 index 0000000000..b7cf748ffe --- /dev/null +++ b/target/linux/gemini/patches-6.12/0001-net-ethernet-cortina-Use-TOE-TSO-on-all-TCP.patch @@ -0,0 +1,122 @@ +From 4d5c3828a8dd0062eeeb56b7d857a76130c3683c Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Tue, 8 Apr 2025 11:26:58 +0200 +Subject: [PATCH 1/2] net: ethernet: cortina: Use TOE/TSO on all TCP + +It is desireable to push the hardware accelerator to also +process non-segmented TCP frames: we pass the skb->len +to the "TOE/TSO" offloader and it will handle them. + +Without this quirk the driver becomes unstable and lock +up and and crash. + +I do not know exactly why, but it is probably due to the +TOE (TCP offload engine) feature that is coupled with the +segmentation feature - it is not possible to turn one +part off and not the other, either both TOE and TSO are +active, or neither of them. + +Not having the TOE part active seems detrimental, as if +that hardware feature is not really supposed to be turned +off. + +The datasheet says: + + "Based on packet parsing and TCP connection/NAT table + lookup results, the NetEngine puts the packets + belonging to the same TCP connection to the same queue + for the software to process. The NetEngine puts + incoming packets to the buffer or series of buffers + for a jumbo packet. With this hardware acceleration, + IP/TCP header parsing, checksum validation and + connection lookup are offloaded from the software + processing." + +After numerous tests with the hardware locking up after +something between minutes and hours depending on load +using iperf3 I have concluded this is necessary to stabilize +the hardware. + +Signed-off-by: Linus Walleij +Link: https://patch.msgid.link/20250408-gemini-ethernet-tso-always-v1-1-e669f932359c@linaro.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/cortina/gemini.c | 37 +++++++++++++++++++++------ + 1 file changed, 29 insertions(+), 8 deletions(-) + +--- a/drivers/net/ethernet/cortina/gemini.c ++++ b/drivers/net/ethernet/cortina/gemini.c +@@ -1143,6 +1143,7 @@ static int gmac_map_tx_bufs(struct net_d + struct gmac_txdesc *txd; + skb_frag_t *skb_frag; + dma_addr_t mapping; ++ bool tcp = false; + void *buffer; + u16 mss; + int ret; +@@ -1150,6 +1151,13 @@ static int gmac_map_tx_bufs(struct net_d + word1 = skb->len; + word3 = SOF_BIT; + ++ /* Determine if we are doing TCP */ ++ if (skb->protocol == htons(ETH_P_IP)) ++ tcp = (ip_hdr(skb)->protocol == IPPROTO_TCP); ++ else ++ /* IPv6 */ ++ tcp = (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP); ++ + mss = skb_shinfo(skb)->gso_size; + if (mss) { + /* This means we are dealing with TCP and skb->len is the +@@ -1162,8 +1170,26 @@ static int gmac_map_tx_bufs(struct net_d + mss, skb->len); + word1 |= TSS_MTU_ENABLE_BIT; + word3 |= mss; ++ } else if (tcp) { ++ /* Even if we are not using TSO, use the hardware offloader ++ * for transferring the TCP frame: this hardware has partial ++ * TCP awareness (called TOE - TCP Offload Engine) and will ++ * according to the datasheet put packets belonging to the ++ * same TCP connection in the same queue for the TOE/TSO ++ * engine to process. The engine will deal with chopping ++ * up frames that exceed ETH_DATA_LEN which the ++ * checksumming engine cannot handle (see below) into ++ * manageable chunks. It flawlessly deals with quite big ++ * frames and frames containing custom DSA EtherTypes. ++ */ ++ mss = netdev->mtu + skb_tcp_all_headers(skb); ++ mss = min(mss, skb->len); ++ netdev_dbg(netdev, "TOE/TSO len %04x mtu %04x mss %04x\n", ++ skb->len, netdev->mtu, mss); ++ word1 |= TSS_MTU_ENABLE_BIT; ++ word3 |= mss; + } else if (skb->len >= ETH_FRAME_LEN) { +- /* Hardware offloaded checksumming isn't working on frames ++ /* Hardware offloaded checksumming isn't working on non-TCP frames + * bigger than 1514 bytes. A hypothesis about this is that the + * checksum buffer is only 1518 bytes, so when the frames get + * bigger they get truncated, or the last few bytes get +@@ -1180,21 +1206,16 @@ static int gmac_map_tx_bufs(struct net_d + } + + if (skb->ip_summed == CHECKSUM_PARTIAL) { +- int tcp = 0; +- + /* We do not switch off the checksumming on non TCP/UDP + * frames: as is shown from tests, the checksumming engine + * is smart enough to see that a frame is not actually TCP + * or UDP and then just pass it through without any changes + * to the frame. + */ +- if (skb->protocol == htons(ETH_P_IP)) { ++ if (skb->protocol == htons(ETH_P_IP)) + word1 |= TSS_IP_CHKSUM_BIT; +- tcp = ip_hdr(skb)->protocol == IPPROTO_TCP; +- } else { /* IPv6 */ ++ else + word1 |= TSS_IPV6_ENABLE_BIT; +- tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP; +- } + + word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT; + } diff --git a/target/linux/gemini/patches-6.6/300-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch b/target/linux/gemini/patches-6.12/300-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch similarity index 88% rename from target/linux/gemini/patches-6.6/300-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch rename to target/linux/gemini/patches-6.12/300-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch index 613c3a842f..23a314d326 100644 --- a/target/linux/gemini/patches-6.6/300-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch +++ b/target/linux/gemini/patches-6.12/300-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch @@ -1,7 +1,7 @@ -From c1aa34cd568bc7b86b82353034070c32b6ebe6db Mon Sep 17 00:00:00 2001 +From 0890faebd0155f57ef34fb1e766fd3ed8a127595 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 11 Mar 2019 15:44:29 +0100 -Subject: [PATCH] ARM: dts: Augment DIR-685 partition table for OpenWrt +Subject: [PATCH 2/2] ARM: dts: Augment DIR-685 partition table for OpenWrt Rename the firmware partition so that the firmware MTD splitter will do its job, drop the rootfs arguments as diff --git a/target/linux/gemini/patches-6.6/0002-ARM-dts-gemini-Map-reset-keys-to-KEY_RESTART.patch b/target/linux/gemini/patches-6.6/0002-ARM-dts-gemini-Map-reset-keys-to-KEY_RESTART.patch deleted file mode 100644 index 1d1ee2b46c..0000000000 --- a/target/linux/gemini/patches-6.6/0002-ARM-dts-gemini-Map-reset-keys-to-KEY_RESTART.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 091cde88b5ff2a2ca5739ce41f9cf5640a95222f Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Sun, 11 Feb 2024 22:24:25 +0100 -Subject: [PATCH] ARM: dts: gemini: Map reset keys to KEY_RESTART - -This maps the misc "reset", "setup" and "facory reset" keys to the -only key a standard userspace is likely to understand: KEY_RESTART. -On OpenWrt this will simply restart the system under controlled -forms. - -Signed-off-by: Linus Walleij -Link: https://lore.kernel.org/r/20240211-gemini-dts-v1-3-6c09adeb4c2e@linaro.org ---- - arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts | 4 ++-- - arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts | 4 ++-- - arch/arm/boot/dts/gemini/gemini-sl93512r.dts | 2 +- - arch/arm/boot/dts/gemini/gemini-sq201.dts | 2 +- - arch/arm/boot/dts/gemini/gemini-wbd111.dts | 4 ++-- - arch/arm/boot/dts/gemini/gemini-wbd222.dts | 4 ++-- - 6 files changed, 10 insertions(+), 10 deletions(-) - ---- a/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts -+++ b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts -@@ -27,10 +27,10 @@ - gpio_keys { - compatible = "gpio-keys"; - -- button-esc { -+ button-reset { - debounce-interval = <100>; - wakeup-source; -- linux,code = ; -+ linux,code = ; - label = "reset"; - /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */ - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts -+++ b/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts -@@ -33,10 +33,10 @@ - gpio_keys { - compatible = "gpio-keys"; - -- button-esc { -+ button-reset { - debounce-interval = <100>; - wakeup-source; -- linux,code = ; -+ linux,code = ; - label = "reset"; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - }; ---- a/arch/arm/boot/dts/gemini/gemini-sl93512r.dts -+++ b/arch/arm/boot/dts/gemini/gemini-sl93512r.dts -@@ -43,7 +43,7 @@ - button-setup { - debounce-interval = <50>; - wakeup-source; -- linux,code = ; -+ linux,code = ; - label = "factory reset"; - /* Conflict with NAND flash */ - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/gemini/gemini-sq201.dts -+++ b/arch/arm/boot/dts/gemini/gemini-sq201.dts -@@ -30,7 +30,7 @@ - button-setup { - debounce-interval = <100>; - wakeup-source; -- linux,code = ; -+ linux,code = ; - label = "factory reset"; - /* Conflict with NAND flash */ - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/gemini/gemini-wbd111.dts -+++ b/arch/arm/boot/dts/gemini/gemini-wbd111.dts -@@ -28,10 +28,10 @@ - gpio_keys { - compatible = "gpio-keys"; - -- button-setup { -+ button-reset { - debounce-interval = <100>; - wakeup-source; -- linux,code = ; -+ linux,code = ; - label = "reset"; - /* Conflict with ICE */ - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/gemini/gemini-wbd222.dts -+++ b/arch/arm/boot/dts/gemini/gemini-wbd222.dts -@@ -27,10 +27,10 @@ - gpio_keys { - compatible = "gpio-keys"; - -- button-setup { -+ button-reset { - debounce-interval = <100>; - wakeup-source; -- linux,code = ; -+ linux,code = ; - label = "reset"; - /* Conflict with ICE */ - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; diff --git a/target/linux/gemini/patches-6.6/0005-net-ethernet-cortina-Use-TSO-also-on-common-TCP.patch b/target/linux/gemini/patches-6.6/0005-net-ethernet-cortina-Use-TSO-also-on-common-TCP.patch deleted file mode 100644 index c690b8fddb..0000000000 --- a/target/linux/gemini/patches-6.6/0005-net-ethernet-cortina-Use-TSO-also-on-common-TCP.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 91fb8a7328dda827bc6c0da240a1eb17028416cd Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Thu, 9 May 2024 23:59:28 +0200 -Subject: [PATCH 2/5] net: ethernet: cortina: Use TSO also on common TCP - -It is possible to push the segment offloader to also -process non-segmented frames: just pass the skb->len -or desired MSS to the offloader and it will handle them. - -This is especially good if the user sets up the MTU -and the frames get big, because the checksumming engine -cannot handle any frames bigger than 1518 bytes, so -segmenting them all to be at max that will be helpful -for the hardware, which only need to quirk odd frames -such as big UDP ping packets. - -The vendor driver always uses the TSO like this, and -the driver seems more stable after this, so apparently -the hardware may have been engineered to always use -the TSO on anything it can handle. - -Signed-off-by: Linus Walleij ---- - drivers/net/ethernet/cortina/gemini.c | 31 +++++++++++++++++++++------ - 1 file changed, 24 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/cortina/gemini.c -+++ b/drivers/net/ethernet/cortina/gemini.c -@@ -1148,6 +1148,7 @@ static int gmac_map_tx_bufs(struct net_d - struct gmac_txdesc *txd; - skb_frag_t *skb_frag; - dma_addr_t mapping; -+ bool tcp = false; - void *buffer; - u16 mss; - int ret; -@@ -1155,6 +1156,13 @@ static int gmac_map_tx_bufs(struct net_d - word1 = skb->len; - word3 = SOF_BIT; - -+ /* Determine if we are doing TCP */ -+ if (skb->protocol == htons(ETH_P_IP)) -+ tcp = (ip_hdr(skb)->protocol == IPPROTO_TCP); -+ else -+ /* IPv6 */ -+ tcp = (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP); -+ - mss = skb_shinfo(skb)->gso_size; - if (mss) { - /* This means we are dealing with TCP and skb->len is the -@@ -1167,6 +1175,20 @@ static int gmac_map_tx_bufs(struct net_d - mss, skb->len); - word1 |= TSS_MTU_ENABLE_BIT; - word3 |= mss; -+ } else if (tcp) { -+ /* Even if we are not using TSO, use the segment offloader -+ * for transferring the TCP frame: the TSO engine will deal -+ * with chopping up frames that exceed ETH_DATA_LEN which -+ * the checksumming engine cannot handle (see below) into -+ * manageable chunks. It flawlessly deals with quite big -+ * frames and frames containing custom DSA EtherTypes. -+ */ -+ mss = netdev->mtu + skb_tcp_all_headers(skb); -+ mss = min(mss, skb->len); -+ netdev_dbg(netdev, "botched TSO len %04x mtu %04x mss %04x\n", -+ skb->len, netdev->mtu, mss); -+ word1 |= TSS_MTU_ENABLE_BIT; -+ word3 |= mss; - } else if (skb->len >= ETH_FRAME_LEN) { - /* Hardware offloaded checksumming isn't working on frames - * bigger than 1514 bytes. A hypothesis about this is that the -@@ -1185,21 +1207,16 @@ static int gmac_map_tx_bufs(struct net_d - } - - if (skb->ip_summed == CHECKSUM_PARTIAL) { -- int tcp = 0; -- - /* We do not switch off the checksumming on non TCP/UDP - * frames: as is shown from tests, the checksumming engine - * is smart enough to see that a frame is not actually TCP - * or UDP and then just pass it through without any changes - * to the frame. - */ -- if (skb->protocol == htons(ETH_P_IP)) { -+ if (skb->protocol == htons(ETH_P_IP)) - word1 |= TSS_IP_CHKSUM_BIT; -- tcp = ip_hdr(skb)->protocol == IPPROTO_TCP; -- } else { /* IPv6 */ -+ else - word1 |= TSS_IPV6_ENABLE_BIT; -- tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP; -- } - - word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT; - } diff --git a/target/linux/gemini/patches-6.6/0006-net-ethernet-cortina-Rename-adjust-link-callback.patch b/target/linux/gemini/patches-6.6/0006-net-ethernet-cortina-Rename-adjust-link-callback.patch deleted file mode 100644 index bbdef8fefc..0000000000 --- a/target/linux/gemini/patches-6.6/0006-net-ethernet-cortina-Rename-adjust-link-callback.patch +++ /dev/null @@ -1,36 +0,0 @@ -From fa01c904b844e6033445f75b0b4d46a8e83b6086 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Fri, 10 May 2024 19:48:27 +0200 -Subject: [PATCH 3/5] net: ethernet: cortina: Rename adjust link callback - -The callback passed to of_phy_get_and_connect() in the -Cortina Gemini driver is called "gmac_speed_set" which is -archaic, rename it to "gmac_adjust_link" following the -pattern of most other drivers. - -Reviewed-by: Andrew Lunn -Signed-off-by: Linus Walleij ---- - drivers/net/ethernet/cortina/gemini.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/cortina/gemini.c -+++ b/drivers/net/ethernet/cortina/gemini.c -@@ -288,7 +288,7 @@ static void gmac_set_flow_control(struct - spin_unlock_irqrestore(&port->config_lock, flags); - } - --static void gmac_speed_set(struct net_device *netdev) -+static void gmac_adjust_link(struct net_device *netdev) - { - struct gemini_ethernet_port *port = netdev_priv(netdev); - struct phy_device *phydev = netdev->phydev; -@@ -367,7 +367,7 @@ static int gmac_setup_phy(struct net_dev - - phy = of_phy_get_and_connect(netdev, - dev->of_node, -- gmac_speed_set); -+ gmac_adjust_link); - if (!phy) - return -ENODEV; - netdev->phydev = phy; diff --git a/target/linux/gemini/patches-6.6/0007-net-ethernet-cortina-Use-negotiated-TX-RX-pause.patch b/target/linux/gemini/patches-6.6/0007-net-ethernet-cortina-Use-negotiated-TX-RX-pause.patch deleted file mode 100644 index a1b8707f72..0000000000 --- a/target/linux/gemini/patches-6.6/0007-net-ethernet-cortina-Use-negotiated-TX-RX-pause.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 50ac9765c674bac803719c6b8294670edc6df31d Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Fri, 10 May 2024 19:44:39 +0200 -Subject: [PATCH 4/5] net: ethernet: cortina: Use negotiated TX/RX pause - -Instead of directly poking into registers of the PHY, use -the existing function to query phylib about this directly. - -Suggested-by: Andrew Lunn -Reviewed-by: Andrew Lunn -Signed-off-by: Linus Walleij ---- - drivers/net/ethernet/cortina/gemini.c | 15 +++++---------- - 1 file changed, 5 insertions(+), 10 deletions(-) - ---- a/drivers/net/ethernet/cortina/gemini.c -+++ b/drivers/net/ethernet/cortina/gemini.c -@@ -293,8 +293,8 @@ static void gmac_adjust_link(struct net_ - struct gemini_ethernet_port *port = netdev_priv(netdev); - struct phy_device *phydev = netdev->phydev; - union gmac_status status, old_status; -- int pause_tx = 0; -- int pause_rx = 0; -+ bool pause_tx = false; -+ bool pause_rx = false; - - status.bits32 = readl(port->gmac_base + GMAC_STATUS); - old_status.bits32 = status.bits32; -@@ -329,14 +329,9 @@ static void gmac_adjust_link(struct net_ - } - - if (phydev->duplex == DUPLEX_FULL) { -- u16 lcladv = phy_read(phydev, MII_ADVERTISE); -- u16 rmtadv = phy_read(phydev, MII_LPA); -- u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); -- -- if (cap & FLOW_CTRL_RX) -- pause_rx = 1; -- if (cap & FLOW_CTRL_TX) -- pause_tx = 1; -+ phy_get_pause(phydev, &pause_tx, &pause_rx); -+ netdev_dbg(netdev, "set negotiated pause params pause TX = %s, pause RX = %s\n", -+ pause_tx ? "ON" : "OFF", pause_rx ? "ON" : "OFF"); - } - - gmac_set_flow_control(netdev, pause_tx, pause_rx); diff --git a/target/linux/gemini/patches-6.6/0008-net-ethernet-cortina-Implement-.set_pauseparam.patch b/target/linux/gemini/patches-6.6/0008-net-ethernet-cortina-Implement-.set_pauseparam.patch deleted file mode 100644 index ad7594e855..0000000000 --- a/target/linux/gemini/patches-6.6/0008-net-ethernet-cortina-Implement-.set_pauseparam.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 4eed4b87f17d10b7586349c13c3a30f9c24c9ba4 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Wed, 8 May 2024 23:21:17 +0200 -Subject: [PATCH 5/5] net: ethernet: cortina: Implement .set_pauseparam() - -The Cortina Gemini ethernet can very well set up TX or RX -pausing, so add this functionality to the driver in a -.set_pauseparam() callback. Essentially just call down to -phylib and let phylib deal with this, .adjust_link() -will respect the setting from phylib. - -Signed-off-by: Linus Walleij ---- - drivers/net/ethernet/cortina/gemini.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/net/ethernet/cortina/gemini.c -+++ b/drivers/net/ethernet/cortina/gemini.c -@@ -2143,6 +2143,19 @@ static void gmac_get_pauseparam(struct n - pparam->autoneg = true; - } - -+static int gmac_set_pauseparam(struct net_device *netdev, -+ struct ethtool_pauseparam *pparam) -+{ -+ struct phy_device *phydev = netdev->phydev; -+ -+ if (!pparam->autoneg) -+ return -EOPNOTSUPP; -+ -+ phy_set_asym_pause(phydev, pparam->rx_pause, pparam->tx_pause); -+ -+ return 0; -+} -+ - static void gmac_get_ringparam(struct net_device *netdev, - struct ethtool_ringparam *rp, - struct kernel_ethtool_ringparam *kernel_rp, -@@ -2263,6 +2276,7 @@ static const struct ethtool_ops gmac_351 - .set_link_ksettings = gmac_set_ksettings, - .nway_reset = gmac_nway_reset, - .get_pauseparam = gmac_get_pauseparam, -+ .set_pauseparam = gmac_set_pauseparam, - .get_ringparam = gmac_get_ringparam, - .set_ringparam = gmac_set_ringparam, - .get_coalesce = gmac_get_coalesce, diff --git a/target/linux/generic/backport-6.12/330-v6.13-jiffies-Define-secs_to_jiffies.patch b/target/linux/generic/backport-6.12/330-v6.13-jiffies-Define-secs_to_jiffies.patch new file mode 100644 index 0000000000..ad9af1d4bb --- /dev/null +++ b/target/linux/generic/backport-6.12/330-v6.13-jiffies-Define-secs_to_jiffies.patch @@ -0,0 +1,60 @@ +From b35108a51cf7bab58d7eace1267d7965978bcdb8 Mon Sep 17 00:00:00 2001 +From: Easwar Hariharan +Date: Wed, 30 Oct 2024 17:47:35 +0000 +Subject: [PATCH] jiffies: Define secs_to_jiffies() + +secs_to_jiffies() is defined in hci_event.c and cannot be reused by +other call sites. Hoist it into the core code to allow conversion of the +~1150 usages of msecs_to_jiffies() that either: + + - use a multiplier value of 1000 or equivalently MSEC_PER_SEC, or + - have timeouts that are denominated in seconds (i.e. end in 000) + +It's implemented as a macro to allow usage in static initializers. + +This will also allow conversion of yet more sites that use (sec * HZ) +directly, and improve their readability. + +Suggested-by: Michael Kelley +Signed-off-by: Easwar Hariharan +Signed-off-by: Thomas Gleixner +Reviewed-by: Luiz Augusto von Dentz +Link: https://lore.kernel.org/all/20241030-open-coded-timeouts-v3-1-9ba123facf88@linux.microsoft.com +--- + include/linux/jiffies.h | 13 +++++++++++++ + net/bluetooth/hci_event.c | 2 -- + 2 files changed, 13 insertions(+), 2 deletions(-) + +--- a/include/linux/jiffies.h ++++ b/include/linux/jiffies.h +@@ -526,6 +526,19 @@ static __always_inline unsigned long mse + } + } + ++/** ++ * secs_to_jiffies: - convert seconds to jiffies ++ * @_secs: time in seconds ++ * ++ * Conversion is done by simple multiplication with HZ ++ * ++ * secs_to_jiffies() is defined as a macro rather than a static inline ++ * function so it can be used in static initializers. ++ * ++ * Return: jiffies value ++ */ ++#define secs_to_jiffies(_secs) ((_secs) * HZ) ++ + extern unsigned long __usecs_to_jiffies(const unsigned int u); + #if !(USEC_PER_SEC % HZ) + static inline unsigned long _usecs_to_jiffies(const unsigned int u) +--- a/net/bluetooth/hci_event.c ++++ b/net/bluetooth/hci_event.c +@@ -42,8 +42,6 @@ + #define ZERO_KEY "\x00\x00\x00\x00\x00\x00\x00\x00" \ + "\x00\x00\x00\x00\x00\x00\x00\x00" + +-#define secs_to_jiffies(_secs) msecs_to_jiffies((_secs) * 1000) +- + /* Handle HCI Event packets */ + + static void *hci_ev_skb_pull(struct hci_dev *hdev, struct sk_buff *skb, diff --git a/target/linux/generic/backport-6.12/331-v6.14-jiffies-Cast-to-unsigned-long-in-secs_to_jiffies-con.patch b/target/linux/generic/backport-6.12/331-v6.14-jiffies-Cast-to-unsigned-long-in-secs_to_jiffies-con.patch new file mode 100644 index 0000000000..cddd558dee --- /dev/null +++ b/target/linux/generic/backport-6.12/331-v6.14-jiffies-Cast-to-unsigned-long-in-secs_to_jiffies-con.patch @@ -0,0 +1,35 @@ +From bb2784d9ab49587ba4fbff37a319fff2924db289 Mon Sep 17 00:00:00 2001 +From: Easwar Hariharan +Date: Thu, 30 Jan 2025 19:26:58 +0000 +Subject: [PATCH] jiffies: Cast to unsigned long in secs_to_jiffies() + conversion + +While converting users of msecs_to_jiffies(), lkp reported that some range +checks would always be true because of the mismatch between the implied int +value of secs_to_jiffies() vs the unsigned long return value of the +msecs_to_jiffies() calls it was replacing. + +Fix this by casting the secs_to_jiffies() input value to unsigned long. + +Fixes: b35108a51cf7ba ("jiffies: Define secs_to_jiffies()") +Reported-by: kernel test robot +Signed-off-by: Easwar Hariharan +Signed-off-by: Thomas Gleixner +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/all/20250130192701.99626-1-eahariha@linux.microsoft.com +Closes: https://lore.kernel.org/oe-kbuild-all/202501301334.NB6NszQR-lkp@intel.com/ +--- + include/linux/jiffies.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/include/linux/jiffies.h ++++ b/include/linux/jiffies.h +@@ -537,7 +537,7 @@ static __always_inline unsigned long mse + * + * Return: jiffies value + */ +-#define secs_to_jiffies(_secs) ((_secs) * HZ) ++#define secs_to_jiffies(_secs) (unsigned long)((_secs) * HZ) + + extern unsigned long __usecs_to_jiffies(const unsigned int u); + #if !(USEC_PER_SEC % HZ) diff --git a/target/linux/generic/backport-6.12/410-v6.13-01-block-add-support-for-defining-read-only-partitions.patch b/target/linux/generic/backport-6.12/410-v6.13-01-block-add-support-for-defining-read-only-partitions.patch index d40a483fd3..7dd0031264 100644 --- a/target/linux/generic/backport-6.12/410-v6.13-01-block-add-support-for-defining-read-only-partitions.patch +++ b/target/linux/generic/backport-6.12/410-v6.13-01-block-add-support-for-defining-read-only-partitions.patch @@ -19,7 +19,7 @@ Signed-off-by: Jens Axboe --- a/block/blk.h +++ b/block/blk.h -@@ -555,6 +555,7 @@ void blk_free_ext_minor(unsigned int min +@@ -556,6 +556,7 @@ void blk_free_ext_minor(unsigned int min #define ADDPART_FLAG_NONE 0 #define ADDPART_FLAG_RAID 1 #define ADDPART_FLAG_WHOLEDISK 2 diff --git a/target/linux/generic/backport-6.12/420-01-v6.16-mtd-rawnand-brcmnand-remove-unused-parameters.patch b/target/linux/generic/backport-6.12/420-01-v6.16-mtd-rawnand-brcmnand-remove-unused-parameters.patch new file mode 100644 index 0000000000..3bc6038711 --- /dev/null +++ b/target/linux/generic/backport-6.12/420-01-v6.16-mtd-rawnand-brcmnand-remove-unused-parameters.patch @@ -0,0 +1,88 @@ +From 56fce75470041b5b0d92ae10637416e1a4cceb1b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 14 May 2025 08:14:54 +0200 +Subject: [PATCH] mtd: rawnand: brcmnand: remove unused parameters +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +last_cmd and last_byte are now unused brcmnand_host members. +last_addr is only written and never read so we can remove it too. + +Signed-off-by: Álvaro Fernández Rojas +Reviewed-by: Florian Fainelli +Reviewed-by: William Zhang +Signed-off-by: Miquel Raynal +--- + drivers/mtd/nand/raw/brcmnand/brcmnand.c | 24 ++++++------------------ + 1 file changed, 6 insertions(+), 18 deletions(-) + +--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c ++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c +@@ -310,9 +310,6 @@ struct brcmnand_host { + struct platform_device *pdev; + int cs; + +- unsigned int last_cmd; +- unsigned int last_byte; +- u64 last_addr; + struct brcmnand_cfg hwcfg; + struct brcmnand_controller *ctrl; + }; +@@ -2233,14 +2230,11 @@ static int brcmnand_read_page(struct nan + int oob_required, int page) + { + struct mtd_info *mtd = nand_to_mtd(chip); +- struct brcmnand_host *host = nand_get_controller_data(chip); + u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; + u64 addr = (u64)page << chip->page_shift; + +- host->last_addr = addr; +- +- return brcmnand_read(mtd, chip, host->last_addr, +- mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); ++ return brcmnand_read(mtd, chip, addr, mtd->writesize >> FC_SHIFT, ++ (u32 *)buf, oob); + } + + static int brcmnand_read_page_raw(struct nand_chip *chip, uint8_t *buf, +@@ -2252,11 +2246,9 @@ static int brcmnand_read_page_raw(struct + int ret; + u64 addr = (u64)page << chip->page_shift; + +- host->last_addr = addr; +- + brcmnand_set_ecc_enabled(host, 0); +- ret = brcmnand_read(mtd, chip, host->last_addr, +- mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); ++ ret = brcmnand_read(mtd, chip, addr, mtd->writesize >> FC_SHIFT, ++ (u32 *)buf, oob); + brcmnand_set_ecc_enabled(host, 1); + return ret; + } +@@ -2363,13 +2355,10 @@ static int brcmnand_write_page(struct na + int oob_required, int page) + { + struct mtd_info *mtd = nand_to_mtd(chip); +- struct brcmnand_host *host = nand_get_controller_data(chip); + void *oob = oob_required ? chip->oob_poi : NULL; + u64 addr = (u64)page << chip->page_shift; + +- host->last_addr = addr; +- +- return brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); ++ return brcmnand_write(mtd, chip, addr, (const u32 *)buf, oob); + } + + static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, +@@ -2381,9 +2370,8 @@ static int brcmnand_write_page_raw(struc + u64 addr = (u64)page << chip->page_shift; + int ret = 0; + +- host->last_addr = addr; + brcmnand_set_ecc_enabled(host, 0); +- ret = brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); ++ ret = brcmnand_write(mtd, chip, addr, (const u32 *)buf, oob); + brcmnand_set_ecc_enabled(host, 1); + + return ret; diff --git a/target/linux/generic/backport-6.12/420-02-v6.16-mtd-nand-brcmnand-fix-NAND-timeout-when-accessing-eM.patch b/target/linux/generic/backport-6.12/420-02-v6.16-mtd-nand-brcmnand-fix-NAND-timeout-when-accessing-eM.patch new file mode 100644 index 0000000000..d3dbde8b9e --- /dev/null +++ b/target/linux/generic/backport-6.12/420-02-v6.16-mtd-nand-brcmnand-fix-NAND-timeout-when-accessing-eM.patch @@ -0,0 +1,30 @@ +From 528b541b71cf03e263272b051b70696f92258e9d Mon Sep 17 00:00:00 2001 +From: David Regan +Date: Thu, 22 May 2025 10:25:17 -0700 +Subject: [PATCH] mtd: nand: brcmnand: fix NAND timeout when accessing eMMC + +When booting a board to NAND and accessing NAND while eMMC +transactions are occurring the NAND will sometimes timeout. This +is due to both NAND and eMMC controller sharing the same data bus +on BCMBCA chips. Fix is to extend NAND timeout to allow eMMC +transactions time to complete. + +Signed-off-by: David Regan +Reviewed-by: William Zhang +Reviewed-by: Florian Fainelli +Signed-off-by: Miquel Raynal +--- + drivers/mtd/nand/raw/brcmnand/brcmnand.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c ++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c +@@ -101,7 +101,7 @@ struct brcm_nand_dma_desc { + #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024) + + #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY) +-#define NAND_POLL_STATUS_TIMEOUT_MS 100 ++#define NAND_POLL_STATUS_TIMEOUT_MS 500 + + #define EDU_CMD_WRITE 0x00 + #define EDU_CMD_READ 0x01 diff --git a/target/linux/generic/backport-6.12/420-03-v6.16-mtd-rawnand-brcmnand-legacy-exec_op-implementation.patch b/target/linux/generic/backport-6.12/420-03-v6.16-mtd-rawnand-brcmnand-legacy-exec_op-implementation.patch new file mode 100644 index 0000000000..6c75c2bbf2 --- /dev/null +++ b/target/linux/generic/backport-6.12/420-03-v6.16-mtd-rawnand-brcmnand-legacy-exec_op-implementation.patch @@ -0,0 +1,299 @@ +From 3bfb22cecfe6b6f0d8ee56ef4b533cf68599c5d9 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 21 May 2025 10:03:25 +0200 +Subject: [PATCH] mtd: rawnand: brcmnand: legacy exec_op implementation +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Commit 3c8260ce7663 ("mtd: rawnand: brcmnand: exec_op implementation") +removed legacy interface functions, breaking < v5.0 controllers support. +In order to fix older controllers we need to add an alternative exec_op +implementation which doesn't rely on low level registers. + +Fixes: 3c8260ce7663 ("mtd: rawnand: brcmnand: exec_op implementation") +Signed-off-by: Álvaro Fernández Rojas +Reviewed-by: David Regan +Reviewed-by: Florian Fainelli +Reviewed-by: William Zhang +Signed-off-by: Miquel Raynal +--- + drivers/mtd/nand/raw/brcmnand/brcmnand.c | 222 ++++++++++++++++++++++- + 1 file changed, 215 insertions(+), 7 deletions(-) + +--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c ++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c +@@ -65,6 +65,7 @@ module_param(wp_on, int, 0444); + #define CMD_PARAMETER_READ 0x0e + #define CMD_PARAMETER_CHANGE_COL 0x0f + #define CMD_LOW_LEVEL_OP 0x10 ++#define CMD_NOT_SUPPORTED 0xff + + struct brcm_nand_dma_desc { + u32 next_desc; +@@ -199,6 +200,30 @@ static const u16 flash_dma_regs_v4[] = { + [FLASH_DMA_CURRENT_DESC_EXT] = 0x34, + }; + ++/* Native command conversion for legacy controllers (< v5.0) */ ++static const u8 native_cmd_conv[] = { ++ [NAND_CMD_READ0] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_READ1] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_RNDOUT] = CMD_PARAMETER_CHANGE_COL, ++ [NAND_CMD_PAGEPROG] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_READOOB] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_ERASE1] = CMD_BLOCK_ERASE, ++ [NAND_CMD_STATUS] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_SEQIN] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_RNDIN] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_READID] = CMD_DEVICE_ID_READ, ++ [NAND_CMD_ERASE2] = CMD_NULL, ++ [NAND_CMD_PARAM] = CMD_PARAMETER_READ, ++ [NAND_CMD_GET_FEATURES] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_SET_FEATURES] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_RESET] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_READSTART] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_READCACHESEQ] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_READCACHEEND] = CMD_NOT_SUPPORTED, ++ [NAND_CMD_RNDOUTSTART] = CMD_NULL, ++ [NAND_CMD_CACHEDPROG] = CMD_NOT_SUPPORTED, ++}; ++ + /* Controller feature flags */ + enum { + BRCMNAND_HAS_1K_SECTORS = BIT(0), +@@ -237,6 +262,12 @@ struct brcmnand_controller { + /* List of NAND hosts (one for each chip-select) */ + struct list_head host_list; + ++ /* Functions to be called from exec_op */ ++ int (*check_instr)(struct nand_chip *chip, ++ const struct nand_operation *op); ++ int (*exec_instr)(struct nand_chip *chip, ++ const struct nand_operation *op); ++ + /* EDU info, per-transaction */ + const u16 *edu_offsets; + void __iomem *edu_base; +@@ -2478,18 +2509,190 @@ static int brcmnand_op_is_reset(const st + return 0; + } + ++static int brcmnand_check_instructions(struct nand_chip *chip, ++ const struct nand_operation *op) ++{ ++ return 0; ++} ++ ++static int brcmnand_exec_instructions(struct nand_chip *chip, ++ const struct nand_operation *op) ++{ ++ struct brcmnand_host *host = nand_get_controller_data(chip); ++ unsigned int i; ++ int ret = 0; ++ ++ for (i = 0; i < op->ninstrs; i++) { ++ ret = brcmnand_exec_instr(host, i, op); ++ if (ret) ++ break; ++ } ++ ++ return ret; ++} ++ ++static int brcmnand_check_instructions_legacy(struct nand_chip *chip, ++ const struct nand_operation *op) ++{ ++ const struct nand_op_instr *instr; ++ unsigned int i; ++ u8 cmd; ++ ++ for (i = 0; i < op->ninstrs; i++) { ++ instr = &op->instrs[i]; ++ ++ switch (instr->type) { ++ case NAND_OP_CMD_INSTR: ++ cmd = native_cmd_conv[instr->ctx.cmd.opcode]; ++ if (cmd == CMD_NOT_SUPPORTED) ++ return -EOPNOTSUPP; ++ break; ++ case NAND_OP_ADDR_INSTR: ++ case NAND_OP_DATA_IN_INSTR: ++ case NAND_OP_WAITRDY_INSTR: ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ } ++ ++ return 0; ++} ++ ++static int brcmnand_exec_instructions_legacy(struct nand_chip *chip, ++ const struct nand_operation *op) ++{ ++ struct mtd_info *mtd = nand_to_mtd(chip); ++ struct brcmnand_host *host = nand_get_controller_data(chip); ++ struct brcmnand_controller *ctrl = host->ctrl; ++ const struct nand_op_instr *instr; ++ unsigned int i, j; ++ u8 cmd = CMD_NULL, last_cmd = CMD_NULL; ++ int ret = 0; ++ u64 last_addr; ++ ++ for (i = 0; i < op->ninstrs; i++) { ++ instr = &op->instrs[i]; ++ ++ if (instr->type == NAND_OP_CMD_INSTR) { ++ cmd = native_cmd_conv[instr->ctx.cmd.opcode]; ++ if (cmd == CMD_NOT_SUPPORTED) { ++ dev_err(ctrl->dev, "unsupported cmd=%d\n", ++ instr->ctx.cmd.opcode); ++ ret = -EOPNOTSUPP; ++ break; ++ } ++ } else if (instr->type == NAND_OP_ADDR_INSTR) { ++ u64 addr = 0; ++ ++ if (cmd == CMD_NULL) ++ continue; ++ ++ if (instr->ctx.addr.naddrs > 8) { ++ dev_err(ctrl->dev, "unsupported naddrs=%u\n", ++ instr->ctx.addr.naddrs); ++ ret = -EOPNOTSUPP; ++ break; ++ } ++ ++ for (j = 0; j < instr->ctx.addr.naddrs; j++) ++ addr |= (instr->ctx.addr.addrs[j]) << (j << 3); ++ ++ if (cmd == CMD_BLOCK_ERASE) ++ addr <<= chip->page_shift; ++ else if (cmd == CMD_PARAMETER_CHANGE_COL) ++ addr &= ~((u64)(FC_BYTES - 1)); ++ ++ brcmnand_set_cmd_addr(mtd, addr); ++ brcmnand_send_cmd(host, cmd); ++ last_addr = addr; ++ last_cmd = cmd; ++ cmd = CMD_NULL; ++ brcmnand_waitfunc(chip); ++ ++ if (last_cmd == CMD_PARAMETER_READ || ++ last_cmd == CMD_PARAMETER_CHANGE_COL) { ++ /* Copy flash cache word-wise */ ++ u32 *flash_cache = (u32 *)ctrl->flash_cache; ++ ++ brcmnand_soc_data_bus_prepare(ctrl->soc, true); ++ ++ /* ++ * Must cache the FLASH_CACHE now, since changes in ++ * SECTOR_SIZE_1K may invalidate it ++ */ ++ for (j = 0; j < FC_WORDS; j++) ++ /* ++ * Flash cache is big endian for parameter pages, at ++ * least on STB SoCs ++ */ ++ flash_cache[j] = be32_to_cpu(brcmnand_read_fc(ctrl, j)); ++ ++ brcmnand_soc_data_bus_unprepare(ctrl->soc, true); ++ } ++ } else if (instr->type == NAND_OP_DATA_IN_INSTR) { ++ u8 *in = instr->ctx.data.buf.in; ++ ++ if (last_cmd == CMD_DEVICE_ID_READ) { ++ u32 val; ++ ++ if (instr->ctx.data.len > 8) { ++ dev_err(ctrl->dev, "unsupported len=%u\n", ++ instr->ctx.data.len); ++ ret = -EOPNOTSUPP; ++ break; ++ } ++ ++ for (j = 0; j < instr->ctx.data.len; j++) { ++ if (j == 0) ++ val = brcmnand_read_reg(ctrl, BRCMNAND_ID); ++ else if (j == 4) ++ val = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT); ++ ++ in[j] = (val >> (24 - ((j % 4) << 3))) & 0xff; ++ } ++ } else if (last_cmd == CMD_PARAMETER_READ || ++ last_cmd == CMD_PARAMETER_CHANGE_COL) { ++ u64 addr; ++ u32 offs; ++ ++ for (j = 0; j < instr->ctx.data.len; j++) { ++ addr = last_addr + j; ++ offs = addr & (FC_BYTES - 1); ++ ++ if (j > 0 && offs == 0) ++ nand_change_read_column_op(chip, addr, NULL, 0, ++ false); ++ ++ in[j] = ctrl->flash_cache[offs]; ++ } ++ } ++ } else if (instr->type == NAND_OP_WAITRDY_INSTR) { ++ ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); ++ if (ret) ++ break; ++ } else { ++ dev_err(ctrl->dev, "unsupported instruction type: %d\n", instr->type); ++ ret = -EOPNOTSUPP; ++ break; ++ } ++ } ++ ++ return ret; ++} ++ + static int brcmnand_exec_op(struct nand_chip *chip, + const struct nand_operation *op, + bool check_only) + { + struct brcmnand_host *host = nand_get_controller_data(chip); ++ struct brcmnand_controller *ctrl = host->ctrl; + struct mtd_info *mtd = nand_to_mtd(chip); + u8 *status; +- unsigned int i; + int ret = 0; + + if (check_only) +- return 0; ++ return ctrl->check_instr(chip, op); + + if (brcmnand_op_is_status(op)) { + status = op->instrs[1].ctx.data.buf.in; +@@ -2513,11 +2716,7 @@ static int brcmnand_exec_op(struct nand_ + if (op->deassert_wp) + brcmnand_wp(mtd, 0); + +- for (i = 0; i < op->ninstrs; i++) { +- ret = brcmnand_exec_instr(host, i, op); +- if (ret) +- break; +- } ++ ret = ctrl->exec_instr(chip, op); + + if (op->deassert_wp) + brcmnand_wp(mtd, 1); +@@ -3130,6 +3329,15 @@ int brcmnand_probe(struct platform_devic + if (ret) + goto err; + ++ /* Only v5.0+ controllers have low level ops support */ ++ if (ctrl->nand_version >= 0x0500) { ++ ctrl->check_instr = brcmnand_check_instructions; ++ ctrl->exec_instr = brcmnand_exec_instructions; ++ } else { ++ ctrl->check_instr = brcmnand_check_instructions_legacy; ++ ctrl->exec_instr = brcmnand_exec_instructions_legacy; ++ } ++ + /* + * Most chips have this cache at a fixed offset within 'nand' block. + * Some must specify this region separately. diff --git a/target/linux/generic/backport-6.12/421-01-v6.16-spi-bcm63xx-spi-fix-shared-reset.patch b/target/linux/generic/backport-6.12/421-01-v6.16-spi-bcm63xx-spi-fix-shared-reset.patch new file mode 100644 index 0000000000..e886350d26 --- /dev/null +++ b/target/linux/generic/backport-6.12/421-01-v6.16-spi-bcm63xx-spi-fix-shared-reset.patch @@ -0,0 +1,32 @@ +From 5ad20e3d8cfe3b2e42bbddc7e0ebaa74479bb589 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Thu, 29 May 2025 15:09:14 +0200 +Subject: [PATCH] spi: bcm63xx-spi: fix shared reset +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Some bmips SoCs (bcm6362, bcm63268) share the same SPI reset for both SPI +and HSSPI controllers, so reset shouldn't be exclusive. + +Fixes: 38807adeaf1e ("spi: bcm63xx-spi: add reset support") +Reported-by: Jonas Gorski +Signed-off-by: Álvaro Fernández Rojas +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250529130915.2519590-2-noltari@gmail.com +Signed-off-by: Mark Brown +--- + drivers/spi/spi-bcm63xx.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/spi/spi-bcm63xx.c ++++ b/drivers/spi/spi-bcm63xx.c +@@ -523,7 +523,7 @@ static int bcm63xx_spi_probe(struct plat + return PTR_ERR(clk); + } + +- reset = devm_reset_control_get_optional_exclusive(dev, NULL); ++ reset = devm_reset_control_get_optional_shared(dev, NULL); + if (IS_ERR(reset)) + return PTR_ERR(reset); + diff --git a/target/linux/generic/backport-6.12/421-02-v6.16-spi-bcm63xx-hsspi-fix-shared-reset.patch b/target/linux/generic/backport-6.12/421-02-v6.16-spi-bcm63xx-hsspi-fix-shared-reset.patch new file mode 100644 index 0000000000..3c30269d07 --- /dev/null +++ b/target/linux/generic/backport-6.12/421-02-v6.16-spi-bcm63xx-hsspi-fix-shared-reset.patch @@ -0,0 +1,32 @@ +From 3d6d84c8f2f66d3fd6a43a1e2ce8e6b54c573960 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Thu, 29 May 2025 15:09:15 +0200 +Subject: [PATCH] spi: bcm63xx-hsspi: fix shared reset +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Some bmips SoCs (bcm6362, bcm63268) share the same SPI reset for both SPI +and HSSPI controllers, so reset shouldn't be exclusive. + +Fixes: 0eeadddbf09a ("spi: bcm63xx-hsspi: add reset support") +Reported-by: Jonas Gorski +Signed-off-by: Álvaro Fernández Rojas +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250529130915.2519590-3-noltari@gmail.com +Signed-off-by: Mark Brown +--- + drivers/spi/spi-bcm63xx-hsspi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/spi/spi-bcm63xx-hsspi.c ++++ b/drivers/spi/spi-bcm63xx-hsspi.c +@@ -745,7 +745,7 @@ static int bcm63xx_hsspi_probe(struct pl + if (IS_ERR(clk)) + return PTR_ERR(clk); + +- reset = devm_reset_control_get_optional_exclusive(dev, NULL); ++ reset = devm_reset_control_get_optional_shared(dev, NULL); + if (IS_ERR(reset)) + return PTR_ERR(reset); + diff --git a/target/linux/generic/backport-6.12/700-01-v6.14-net-dsa-add-hook-to-determine-whether-EEE-is-support.patch b/target/linux/generic/backport-6.12/700-01-v6.14-net-dsa-add-hook-to-determine-whether-EEE-is-support.patch new file mode 100644 index 0000000000..446f918fa0 --- /dev/null +++ b/target/linux/generic/backport-6.12/700-01-v6.14-net-dsa-add-hook-to-determine-whether-EEE-is-support.patch @@ -0,0 +1,54 @@ +From 9723a77318b7c0cfd06ea207e52a042f8c815318 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 10 Dec 2024 14:18:16 +0000 +Subject: [PATCH] net: dsa: add hook to determine whether EEE is supported + +Add a hook to determine whether the switch supports EEE. This will +return false if the switch does not, or true if it does. If the +method is not implemented, we assume (currently) that the switch +supports EEE. + +Signed-off-by: Russell King (Oracle) +Reviewed-by: Florian Fainelli +Reviewed-by: Vladimir Oltean +Link: https://patch.msgid.link/E1tL144-006cZD-El@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +--- + include/net/dsa.h | 1 + + net/dsa/user.c | 8 ++++++++ + 2 files changed, 9 insertions(+) + +--- a/include/net/dsa.h ++++ b/include/net/dsa.h +@@ -1003,6 +1003,7 @@ struct dsa_switch_ops { + /* + * Port's MAC EEE settings + */ ++ bool (*support_eee)(struct dsa_switch *ds, int port); + int (*set_mac_eee)(struct dsa_switch *ds, int port, + struct ethtool_keee *e); + int (*get_mac_eee)(struct dsa_switch *ds, int port, +--- a/net/dsa/user.c ++++ b/net/dsa/user.c +@@ -1231,6 +1231,10 @@ static int dsa_user_set_eee(struct net_d + struct dsa_switch *ds = dp->ds; + int ret; + ++ /* Check whether the switch supports EEE */ ++ if (ds->ops->support_eee && !ds->ops->support_eee(ds, dp->index)) ++ return -EOPNOTSUPP; ++ + /* Port's PHY and MAC both need to be EEE capable */ + if (!dev->phydev || !dp->pl) + return -ENODEV; +@@ -1251,6 +1255,10 @@ static int dsa_user_get_eee(struct net_d + struct dsa_switch *ds = dp->ds; + int ret; + ++ /* Check whether the switch supports EEE */ ++ if (ds->ops->support_eee && !ds->ops->support_eee(ds, dp->index)) ++ return -EOPNOTSUPP; ++ + /* Port's PHY and MAC both need to be EEE capable */ + if (!dev->phydev || !dp->pl) + return -ENODEV; diff --git a/target/linux/generic/backport-6.12/700-02-v6.14-net-dsa-provide-implementation-of-.support_eee.patch b/target/linux/generic/backport-6.12/700-02-v6.14-net-dsa-provide-implementation-of-.support_eee.patch new file mode 100644 index 0000000000..d7342daa0b --- /dev/null +++ b/target/linux/generic/backport-6.12/700-02-v6.14-net-dsa-provide-implementation-of-.support_eee.patch @@ -0,0 +1,53 @@ +From 99379f587278c818777cb4778e2c79c6c1440c65 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 10 Dec 2024 14:18:21 +0000 +Subject: [PATCH] net: dsa: provide implementation of .support_eee() + +Provide a trivial implementation for the .support_eee() method which +switch drivers can use to simply indicate that they support EEE on +all their user ports. + +Signed-off-by: Russell King (Oracle) +Reviewed-by: Florian Fainelli +Reviewed-by: Vladimir Oltean +Link: https://patch.msgid.link/E1tL149-006cZJ-JJ@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +--- + include/net/dsa.h | 1 + + net/dsa/port.c | 16 ++++++++++++++++ + 2 files changed, 17 insertions(+) + +--- a/include/net/dsa.h ++++ b/include/net/dsa.h +@@ -1399,5 +1399,6 @@ static inline bool dsa_user_dev_check(co + + netdev_tx_t dsa_enqueue_skb(struct sk_buff *skb, struct net_device *dev); + void dsa_port_phylink_mac_change(struct dsa_switch *ds, int port, bool up); ++bool dsa_supports_eee(struct dsa_switch *ds, int port); + + #endif +--- a/net/dsa/port.c ++++ b/net/dsa/port.c +@@ -1589,6 +1589,22 @@ dsa_port_phylink_mac_select_pcs(struct p + return pcs; + } + ++/* dsa_supports_eee - indicate that EEE is supported ++ * @ds: pointer to &struct dsa_switch ++ * @port: port index ++ * ++ * A default implementation for the .support_eee() DSA operations member, ++ * which drivers can use to indicate that they support EEE on all of their ++ * user ports. ++ * ++ * Returns: true ++ */ ++bool dsa_supports_eee(struct dsa_switch *ds, int port) ++{ ++ return true; ++} ++EXPORT_SYMBOL_GPL(dsa_supports_eee); ++ + static void dsa_port_phylink_mac_config(struct phylink_config *config, + unsigned int mode, + const struct phylink_link_state *state) diff --git a/target/linux/generic/backport-6.12/710-01-v6.13-net-dsa-use-ethtool-string-helpers.patch b/target/linux/generic/backport-6.12/710-01-v6.13-net-dsa-use-ethtool-string-helpers.patch new file mode 100644 index 0000000000..003a896f30 --- /dev/null +++ b/target/linux/generic/backport-6.12/710-01-v6.13-net-dsa-use-ethtool-string-helpers.patch @@ -0,0 +1,30 @@ +From f12b363887c706c40611fba645265527a8415832 Mon Sep 17 00:00:00 2001 +From: Rosen Penev +Date: Sun, 27 Oct 2024 21:48:28 -0700 +Subject: [PATCH] net: dsa: use ethtool string helpers + +These are the preferred way to copy ethtool strings. + +Avoids incrementing pointers all over the place. + +Signed-off-by: Rosen Penev +(for hellcreek driver) +Reviewed-by: Kurt Kanzenbach +Link: https://patch.msgid.link/20241028044828.1639668-1-rosenp@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -1061,8 +1061,7 @@ void b53_get_strings(struct dsa_switch * + + if (stringset == ETH_SS_STATS) { + for (i = 0; i < mib_size; i++) +- strscpy(data + i * ETH_GSTRING_LEN, +- mibs[i].name, ETH_GSTRING_LEN); ++ ethtool_puts(&data, mibs[i].name); + } else if (stringset == ETH_SS_PHY_STATS) { + phydev = b53_get_phy_device(ds, port); + if (!phydev) diff --git a/target/linux/generic/backport-6.12/710-02-v6.14-net-dsa-b53-bcm_sf2-implement-.support_eee-method.patch b/target/linux/generic/backport-6.12/710-02-v6.14-net-dsa-b53-bcm_sf2-implement-.support_eee-method.patch new file mode 100644 index 0000000000..ca0f61013c --- /dev/null +++ b/target/linux/generic/backport-6.12/710-02-v6.14-net-dsa-b53-bcm_sf2-implement-.support_eee-method.patch @@ -0,0 +1,69 @@ +From c86692fc2cb77d94dd8c166c2b9017f196d02a84 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 10 Dec 2024 14:18:26 +0000 +Subject: [PATCH] net: dsa: b53/bcm_sf2: implement .support_eee() method + +Implement the .support_eee() method to indicate that EEE is not +supported by two switch variants, rather than making these checks in +the .set_mac_eee() and .get_mac_eee() methods. + +Signed-off-by: Russell King (Oracle) +Reviewed-by: Florian Fainelli +Reviewed-by: Vladimir Oltean +Link: https://patch.msgid.link/E1tL14E-006cZU-Nc@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 13 +++++++------ + drivers/net/dsa/b53/b53_priv.h | 1 + + 2 files changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -2358,13 +2358,16 @@ int b53_eee_init(struct dsa_switch *ds, + } + EXPORT_SYMBOL(b53_eee_init); + +-int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) ++bool b53_support_eee(struct dsa_switch *ds, int port) + { + struct b53_device *dev = ds->priv; + +- if (is5325(dev) || is5365(dev)) +- return -EOPNOTSUPP; ++ return !is5325(dev) && !is5365(dev); ++} ++EXPORT_SYMBOL(b53_support_eee); + ++int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) ++{ + return 0; + } + EXPORT_SYMBOL(b53_get_mac_eee); +@@ -2374,9 +2377,6 @@ int b53_set_mac_eee(struct dsa_switch *d + struct b53_device *dev = ds->priv; + struct ethtool_keee *p = &dev->ports[port].eee; + +- if (is5325(dev) || is5365(dev)) +- return -EOPNOTSUPP; +- + p->eee_enabled = e->eee_enabled; + b53_eee_enable_set(ds, port, e->eee_enabled); + +@@ -2433,6 +2433,7 @@ static const struct dsa_switch_ops b53_s + .port_setup = b53_setup_port, + .port_enable = b53_enable_port, + .port_disable = b53_disable_port, ++ .support_eee = b53_support_eee, + .get_mac_eee = b53_get_mac_eee, + .set_mac_eee = b53_set_mac_eee, + .port_bridge_join = b53_br_join, +--- a/drivers/net/dsa/b53/b53_priv.h ++++ b/drivers/net/dsa/b53/b53_priv.h +@@ -387,6 +387,7 @@ int b53_enable_port(struct dsa_switch *d + void b53_disable_port(struct dsa_switch *ds, int port); + void b53_brcm_hdr_setup(struct dsa_switch *ds, int port); + int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy); ++bool b53_support_eee(struct dsa_switch *ds, int port); + int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e); + int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e); + diff --git a/target/linux/generic/backport-6.12/710-03-v6.15-net-dsa-b53-mdio-add-support-for-BCM53101.patch b/target/linux/generic/backport-6.12/710-03-v6.15-net-dsa-b53-mdio-add-support-for-BCM53101.patch new file mode 100644 index 0000000000..900117af5e --- /dev/null +++ b/target/linux/generic/backport-6.12/710-03-v6.15-net-dsa-b53-mdio-add-support-for-BCM53101.patch @@ -0,0 +1,76 @@ +From c4f873c2b65c839ff5e7c996bd9ef5a1e7eae11a Mon Sep 17 00:00:00 2001 +From: Torben Nielsen +Date: Mon, 17 Feb 2025 09:05:01 +0100 +Subject: [PATCH] net: dsa: b53: mdio: add support for BCM53101 + +BCM53101 is a ethernet switch, very similar to the BCM53115. +Enable support for it, in the existing b53 dsa driver. + +Signed-off-by: Torben Nielsen +Signed-off-by: Claus Stovgaard +Link: https://patch.msgid.link/20250217080503.1390282-1-claus.stovgaard@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 14 ++++++++++++++ + drivers/net/dsa/b53/b53_mdio.c | 1 + + drivers/net/dsa/b53/b53_priv.h | 2 ++ + 3 files changed, 17 insertions(+) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -2552,6 +2552,19 @@ static const struct b53_chip_data b53_sw + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, + }, + { ++ .chip_id = BCM53101_DEVICE_ID, ++ .dev_name = "BCM53101", ++ .vlans = 4096, ++ .enabled_ports = 0x11f, ++ .arl_bins = 4, ++ .arl_buckets = 512, ++ .vta_regs = B53_VTA_REGS, ++ .imp_port = 8, ++ .duplex_reg = B53_DUPLEX_STAT_GE, ++ .jumbo_pm_reg = B53_JUMBO_PORT_MASK, ++ .jumbo_size_reg = B53_JUMBO_MAX_SIZE, ++ }, ++ { + .chip_id = BCM53115_DEVICE_ID, + .dev_name = "BCM53115", + .vlans = 4096, +@@ -2932,6 +2945,7 @@ int b53_switch_detect(struct b53_device + return ret; + + switch (id32) { ++ case BCM53101_DEVICE_ID: + case BCM53115_DEVICE_ID: + case BCM53125_DEVICE_ID: + case BCM53128_DEVICE_ID: +--- a/drivers/net/dsa/b53/b53_mdio.c ++++ b/drivers/net/dsa/b53/b53_mdio.c +@@ -374,6 +374,7 @@ static void b53_mdio_shutdown(struct mdi + + static const struct of_device_id b53_of_match[] = { + { .compatible = "brcm,bcm5325" }, ++ { .compatible = "brcm,bcm53101" }, + { .compatible = "brcm,bcm53115" }, + { .compatible = "brcm,bcm53125" }, + { .compatible = "brcm,bcm53128" }, +--- a/drivers/net/dsa/b53/b53_priv.h ++++ b/drivers/net/dsa/b53/b53_priv.h +@@ -66,6 +66,7 @@ enum { + BCM5395_DEVICE_ID = 0x95, + BCM5397_DEVICE_ID = 0x97, + BCM5398_DEVICE_ID = 0x98, ++ BCM53101_DEVICE_ID = 0x53101, + BCM53115_DEVICE_ID = 0x53115, + BCM53125_DEVICE_ID = 0x53125, + BCM53128_DEVICE_ID = 0x53128, +@@ -190,6 +191,7 @@ static inline int is531x5(struct b53_dev + { + return dev->chip_id == BCM53115_DEVICE_ID || + dev->chip_id == BCM53125_DEVICE_ID || ++ dev->chip_id == BCM53101_DEVICE_ID || + dev->chip_id == BCM53128_DEVICE_ID || + dev->chip_id == BCM53134_DEVICE_ID; + } diff --git a/target/linux/generic/backport-6.12/710-04-v6.16-net-dsa-b53-implement-setting-ageing-time.patch b/target/linux/generic/backport-6.12/710-04-v6.16-net-dsa-b53-implement-setting-ageing-time.patch new file mode 100644 index 0000000000..75b5b040fd --- /dev/null +++ b/target/linux/generic/backport-6.12/710-04-v6.16-net-dsa-b53-implement-setting-ageing-time.patch @@ -0,0 +1,105 @@ +From e39d14a760c039af0653e3df967e7525413924a0 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 10 May 2025 11:22:11 +0200 +Subject: [PATCH] net: dsa: b53: implement setting ageing time + +b53 supported switches support configuring ageing time between 1 and +1,048,575 seconds, so add an appropriate setter. + +This allows b53 to pass the FDB learning test for both vlan aware and +vlan unaware bridges. + +Signed-off-by: Jonas Gorski +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250510092211.276541-1-jonas.gorski@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/b53/b53_common.c | 28 ++++++++++++++++++++++++++++ + drivers/net/dsa/b53/b53_priv.h | 1 + + drivers/net/dsa/b53/b53_regs.h | 7 +++++++ + 3 files changed, 36 insertions(+) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1202,6 +1203,10 @@ static int b53_setup(struct dsa_switch * + */ + ds->untag_vlan_aware_bridge_pvid = true; + ++ /* Ageing time is set in seconds */ ++ ds->ageing_time_min = 1 * 1000; ++ ds->ageing_time_max = AGE_TIME_MAX * 1000; ++ + ret = b53_reset_switch(dev); + if (ret) { + dev_err(ds->dev, "failed to reset switch\n"); +@@ -2412,6 +2417,28 @@ static int b53_get_max_mtu(struct dsa_sw + return B53_MAX_MTU; + } + ++int b53_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) ++{ ++ struct b53_device *dev = ds->priv; ++ u32 atc; ++ int reg; ++ ++ if (is63xx(dev)) ++ reg = B53_AGING_TIME_CONTROL_63XX; ++ else ++ reg = B53_AGING_TIME_CONTROL; ++ ++ atc = DIV_ROUND_CLOSEST(msecs, 1000); ++ ++ if (!is5325(dev) && !is5365(dev)) ++ atc |= AGE_CHANGE; ++ ++ b53_write32(dev, B53_MGMT_PAGE, reg, atc); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(b53_set_ageing_time); ++ + static const struct phylink_mac_ops b53_phylink_mac_ops = { + .mac_select_pcs = b53_phylink_mac_select_pcs, + .mac_config = b53_phylink_mac_config, +@@ -2436,6 +2463,7 @@ static const struct dsa_switch_ops b53_s + .support_eee = b53_support_eee, + .get_mac_eee = b53_get_mac_eee, + .set_mac_eee = b53_set_mac_eee, ++ .set_ageing_time = b53_set_ageing_time, + .port_bridge_join = b53_br_join, + .port_bridge_leave = b53_br_leave, + .port_pre_bridge_flags = b53_br_flags_pre, +--- a/drivers/net/dsa/b53/b53_priv.h ++++ b/drivers/net/dsa/b53/b53_priv.h +@@ -343,6 +343,7 @@ void b53_get_strings(struct dsa_switch * + void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data); + int b53_get_sset_count(struct dsa_switch *ds, int port, int sset); + void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data); ++int b53_set_ageing_time(struct dsa_switch *ds, unsigned int msecs); + int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, + bool *tx_fwd_offload, struct netlink_ext_ack *extack); + void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge); +--- a/drivers/net/dsa/b53/b53_regs.h ++++ b/drivers/net/dsa/b53/b53_regs.h +@@ -220,6 +220,13 @@ + #define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */ + #define BRCM_HDR_P7_EN BIT(2) /* Enable tagging on port 7 */ + ++/* Aging Time control register (32 bit) */ ++#define B53_AGING_TIME_CONTROL 0x06 ++#define B53_AGING_TIME_CONTROL_63XX 0x08 ++#define AGE_CHANGE BIT(20) ++#define AGE_TIME_MASK 0x7ffff ++#define AGE_TIME_MAX 1048575 ++ + /* Mirror capture control register (16 bit) */ + #define B53_MIR_CAP_CTL 0x10 + #define CAP_PORT_MASK 0xf diff --git a/target/linux/generic/backport-6.12/711-01-v6.16-net-dsa-tag_brcm-legacy-fix-pskb_may_pull-length.patch b/target/linux/generic/backport-6.12/711-01-v6.16-net-dsa-tag_brcm-legacy-fix-pskb_may_pull-length.patch new file mode 100644 index 0000000000..9fa88d2d3f --- /dev/null +++ b/target/linux/generic/backport-6.12/711-01-v6.16-net-dsa-tag_brcm-legacy-fix-pskb_may_pull-length.patch @@ -0,0 +1,31 @@ +From efdddc4484859082da6c7877ed144c8121c8ea55 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Thu, 29 May 2025 14:44:06 +0200 +Subject: [PATCH] net: dsa: tag_brcm: legacy: fix pskb_may_pull length +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BRCM_LEG_PORT_ID was incorrectly used for pskb_may_pull length. +The correct check is BRCM_LEG_TAG_LEN + VLAN_HLEN, or 10 bytes. + +Fixes: 964dbf186eaa ("net: dsa: tag_brcm: add support for legacy tags") +Signed-off-by: Álvaro Fernández Rojas +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250529124406.2513779-1-noltari@gmail.com +Signed-off-by: Jakub Kicinski +--- + net/dsa/tag_brcm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/net/dsa/tag_brcm.c ++++ b/net/dsa/tag_brcm.c +@@ -257,7 +257,7 @@ static struct sk_buff *brcm_leg_tag_rcv( + int source_port; + u8 *brcm_tag; + +- if (unlikely(!pskb_may_pull(skb, BRCM_LEG_PORT_ID))) ++ if (unlikely(!pskb_may_pull(skb, BRCM_LEG_TAG_LEN + VLAN_HLEN))) + return NULL; + + brcm_tag = dsa_etype_header_pos_rx(skb); diff --git a/target/linux/generic/backport-6.12/720-v6.13-net-phy-mediatek-ge-soc-Fix-coding-style.patch b/target/linux/generic/backport-6.12/720-v6.13-net-phy-mediatek-ge-soc-Fix-coding-style.patch new file mode 100644 index 0000000000..25bd96fa1f --- /dev/null +++ b/target/linux/generic/backport-6.12/720-v6.13-net-phy-mediatek-ge-soc-Fix-coding-style.patch @@ -0,0 +1,88 @@ +From 277f96c1f3f71d6e1d3bcf650d7cd84c1442210f Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 17 Oct 2024 11:22:11 +0800 +Subject: [PATCH 01/20] net: phy: mediatek-ge-soc: Fix coding style + +This patch fixes spelling errors, re-arrange vars with +reverse Xmas tree and remove unnecessary parens in +mediatek-ge-soc.c. + +Signed-off-by: SkyLake.Huang +Reviewed-by: Simon Horman +Signed-off-by: Andrew Lunn +--- + drivers/net/phy/mediatek-ge-soc.c | 36 ++++++++++++++++--------------- + 1 file changed, 19 insertions(+), 17 deletions(-) + +--- a/drivers/net/phy/mediatek-ge-soc.c ++++ b/drivers/net/phy/mediatek-ge-soc.c +@@ -408,16 +408,17 @@ static int tx_offset_cal_efuse(struct ph + + static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) + { +- int i; +- int bias[16] = {}; +- const int vals_9461[16] = { 7, 1, 4, 7, +- 7, 1, 4, 7, +- 7, 1, 4, 7, +- 7, 1, 4, 7 }; + const int vals_9481[16] = { 10, 6, 6, 10, + 10, 6, 6, 10, + 10, 6, 6, 10, + 10, 6, 6, 10 }; ++ const int vals_9461[16] = { 7, 1, 4, 7, ++ 7, 1, 4, 7, ++ 7, 1, 4, 7, ++ 7, 1, 4, 7 }; ++ int bias[16] = {}; ++ int i; ++ + switch (phydev->drv->phy_id) { + case MTK_GPHY_ID_MT7981: + /* We add some calibration to efuse values +@@ -1069,10 +1070,10 @@ static int start_cal(struct phy_device * + + static int mt798x_phy_calibration(struct phy_device *phydev) + { ++ struct nvmem_cell *cell; + int ret = 0; +- u32 *buf; + size_t len; +- struct nvmem_cell *cell; ++ u32 *buf; + + cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); + if (IS_ERR(cell)) { +@@ -1210,14 +1211,15 @@ static int mt798x_phy_led_brightness_set + return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF)); + } + +-static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | +- BIT(TRIGGER_NETDEV_HALF_DUPLEX) | +- BIT(TRIGGER_NETDEV_LINK) | +- BIT(TRIGGER_NETDEV_LINK_10) | +- BIT(TRIGGER_NETDEV_LINK_100) | +- BIT(TRIGGER_NETDEV_LINK_1000) | +- BIT(TRIGGER_NETDEV_RX) | +- BIT(TRIGGER_NETDEV_TX)); ++static const unsigned long supported_triggers = ++ BIT(TRIGGER_NETDEV_FULL_DUPLEX) | ++ BIT(TRIGGER_NETDEV_HALF_DUPLEX) | ++ BIT(TRIGGER_NETDEV_LINK) | ++ BIT(TRIGGER_NETDEV_LINK_10) | ++ BIT(TRIGGER_NETDEV_LINK_100) | ++ BIT(TRIGGER_NETDEV_LINK_1000) | ++ BIT(TRIGGER_NETDEV_RX) | ++ BIT(TRIGGER_NETDEV_TX); + + static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules) +@@ -1415,7 +1417,7 @@ static int mt7988_phy_probe_shared(struc + * LED_C and LED_D respectively. At the same time those pins are used to + * bootstrap configuration of the reference clock source (LED_A), + * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). +- * In practise this is done using a LED and a resistor pulling the pin ++ * In practice this is done using a LED and a resistor pulling the pin + * either to GND or to VIO. + * The detected value at boot time is accessible at run-time using the + * TPBANK0 register located in the gpio base of the pinctrl, in order diff --git a/target/linux/generic/backport-6.12/721-v6.13-net-phy-mediatek-ge-soc-Shrink-line-wrapping-to-80-c.patch b/target/linux/generic/backport-6.12/721-v6.13-net-phy-mediatek-ge-soc-Shrink-line-wrapping-to-80-c.patch new file mode 100644 index 0000000000..fbf3a99bd7 --- /dev/null +++ b/target/linux/generic/backport-6.12/721-v6.13-net-phy-mediatek-ge-soc-Shrink-line-wrapping-to-80-c.patch @@ -0,0 +1,271 @@ +From c0dc1b412f9d840c51c5ee8927bf066e15a59550 Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 17 Oct 2024 11:22:12 +0800 +Subject: [PATCH 02/20] net: phy: mediatek-ge-soc: Shrink line wrapping to 80 + characters + +This patch shrinks line wrapping to 80 chars. Also, in +tx_amp_fill_result(), use FIELD_PREP() to prettify code. + +Signed-off-by: SkyLake.Huang +Reviewed-by: Simon Horman +Signed-off-by: Andrew Lunn +--- + drivers/net/phy/mediatek-ge-soc.c | 125 +++++++++++++++++++++--------- + 1 file changed, 88 insertions(+), 37 deletions(-) + +--- a/drivers/net/phy/mediatek-ge-soc.c ++++ b/drivers/net/phy/mediatek-ge-soc.c +@@ -342,7 +342,8 @@ static int cal_cycle(struct phy_device * + ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_AD_CAL_CLK, reg_val, + reg_val & MTK_PHY_DA_CAL_CLK, 500, +- ANALOG_INTERNAL_OPERATION_MAX_US, false); ++ ANALOG_INTERNAL_OPERATION_MAX_US, ++ false); + if (ret) { + phydev_err(phydev, "Calibration cycle timeout\n"); + return ret; +@@ -441,40 +442,72 @@ static int tx_amp_fill_result(struct phy + } + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, +- MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); ++ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, ++ buf[0] + bias[0])); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, +- MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); ++ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, ++ buf[0] + bias[1])); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, +- MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); ++ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, ++ buf[0] + bias[2])); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, +- MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); ++ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK, ++ buf[0] + bias[3])); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, +- MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); ++ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, ++ buf[1] + bias[4])); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, +- MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); ++ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, ++ buf[1] + bias[5])); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, +- MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); ++ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, ++ buf[1] + bias[6])); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, +- MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); ++ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK, ++ buf[1] + bias[7])); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, +- MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); ++ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, ++ buf[2] + bias[8])); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, +- MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); ++ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, ++ buf[2] + bias[9])); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, +- MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); ++ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, ++ buf[2] + bias[10])); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, +- MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); ++ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK, ++ buf[2] + bias[11])); + + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, +- MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); ++ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, ++ buf[3] + bias[12])); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, +- MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); ++ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, ++ buf[3] + bias[13])); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, +- MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); ++ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, ++ buf[3] + bias[14])); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, +- MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); ++ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK, ++ buf[3] + bias[15])); + + return 0; + } +@@ -663,7 +696,8 @@ static int tx_vcm_cal_sw(struct phy_devi + goto restore; + + /* We calibrate TX-VCM in different logic. Check upper index and then +- * lower index. If this calibration is valid, apply lower index's result. ++ * lower index. If this calibration is valid, apply lower index's ++ * result. + */ + ret = upper_ret - lower_ret; + if (ret == 1) { +@@ -692,7 +726,8 @@ static int tx_vcm_cal_sw(struct phy_devi + } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && + lower_ret == 0) { + ret = 0; +- phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", ++ phydev_warn(phydev, ++ "TX-VCM SW cal result at high margin 0x%x\n", + upper_idx); + } else { + ret = -EINVAL; +@@ -796,7 +831,8 @@ static void mt7981_phy_finetune(struct p + + /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, +- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, ++ MTK_PHY_TR_OPEN_LOOP_EN_MASK | ++ MTK_PHY_LPF_X_AVERAGE_MASK, + BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); + + /* rg_tr_lpf_cnt_val = 512 */ +@@ -865,7 +901,8 @@ static void mt7988_phy_finetune(struct p + + /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, +- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, ++ MTK_PHY_TR_OPEN_LOOP_EN_MASK | ++ MTK_PHY_LPF_X_AVERAGE_MASK, + BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); + + /* rg_tr_lpf_cnt_val = 1023 */ +@@ -977,7 +1014,8 @@ static void mt798x_phy_eee(struct phy_de + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); +- __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, ++ __phy_modify(phydev, MTK_PHY_LPI_REG_14, ++ MTK_PHY_LPI_WAKE_TIMER_1000_MASK, + FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); + + __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, +@@ -987,7 +1025,8 @@ static void mt798x_phy_eee(struct phy_de + phy_modify_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, + MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, +- FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); ++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ 0xff)); + } + + static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, +@@ -1147,7 +1186,8 @@ static int mt798x_phy_hw_led_on_set(stru + (index ? 16 : 0), &priv->led_state); + if (changed) + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? +- MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, ++ MTK_PHY_LED1_ON_CTRL : ++ MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED_ON_MASK, + on ? MTK_PHY_LED_ON_FORCE_ON : 0); + else +@@ -1157,7 +1197,8 @@ static int mt798x_phy_hw_led_on_set(stru + static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, + bool blinking) + { +- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0); ++ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + ++ (index ? 16 : 0); + struct mtk_socphy_priv *priv = phydev->priv; + bool changed; + +@@ -1170,8 +1211,10 @@ static int mt798x_phy_hw_led_blink_set(s + (index ? 16 : 0), &priv->led_state); + if (changed) + return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? +- MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL, +- blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0); ++ MTK_PHY_LED1_BLINK_CTRL : ++ MTK_PHY_LED0_BLINK_CTRL, ++ blinking ? ++ MTK_PHY_LED_BLINK_FORCE_BLINK : 0); + else + return 0; + } +@@ -1237,7 +1280,8 @@ static int mt798x_phy_led_hw_is_supporte + static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, + unsigned long *rules) + { +- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0); ++ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + ++ (index ? 16 : 0); + unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); + unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); + struct mtk_socphy_priv *priv = phydev->priv; +@@ -1258,8 +1302,8 @@ static int mt798x_phy_led_hw_control_get + if (blink < 0) + return -EIO; + +- if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX | +- MTK_PHY_LED_ON_LINKDOWN)) || ++ if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | ++ MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) || + (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX))) + set_bit(bit_netdev, &priv->led_state); + else +@@ -1333,17 +1377,23 @@ static int mt798x_phy_led_hw_control_set + + if (rules & BIT(TRIGGER_NETDEV_RX)) { + blink |= (on & MTK_PHY_LED_ON_LINK) ? +- (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10RX : 0) | +- ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100RX : 0) | +- ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000RX : 0)) : ++ (((on & MTK_PHY_LED_ON_LINK10) ? ++ MTK_PHY_LED_BLINK_10RX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK100) ? ++ MTK_PHY_LED_BLINK_100RX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK1000) ? ++ MTK_PHY_LED_BLINK_1000RX : 0)) : + MTK_PHY_LED_BLINK_RX; + } + + if (rules & BIT(TRIGGER_NETDEV_TX)) { + blink |= (on & MTK_PHY_LED_ON_LINK) ? +- (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10TX : 0) | +- ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100TX : 0) | +- ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000TX : 0)) : ++ (((on & MTK_PHY_LED_ON_LINK10) ? ++ MTK_PHY_LED_BLINK_10TX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK100) ? ++ MTK_PHY_LED_BLINK_100TX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK1000) ? ++ MTK_PHY_LED_BLINK_1000TX : 0)) : + MTK_PHY_LED_BLINK_TX; + } + +@@ -1400,7 +1450,8 @@ static int mt7988_phy_fix_leds_polaritie + /* Only now setup pinctrl to avoid bogus blinking */ + pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); + if (IS_ERR(pinctrl)) +- dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n"); ++ dev_err(&phydev->mdio.bus->dev, ++ "Failed to setup PHY LED pinctrl\n"); + + return 0; + } diff --git a/target/linux/generic/backport-6.12/722-v6.13-net-phy-mediatek-ge-soc-Propagate-error-code-correct.patch b/target/linux/generic/backport-6.12/722-v6.13-net-phy-mediatek-ge-soc-Propagate-error-code-correct.patch new file mode 100644 index 0000000000..1f6f5f5df6 --- /dev/null +++ b/target/linux/generic/backport-6.12/722-v6.13-net-phy-mediatek-ge-soc-Propagate-error-code-correct.patch @@ -0,0 +1,40 @@ +From bcbbfb4f62c4ba35783cc617997a2e92d91e3940 Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 17 Oct 2024 11:22:13 +0800 +Subject: [PATCH 03/20] net: phy: mediatek-ge-soc: Propagate error code + correctly in cal_cycle() + +This patch propagates error code correctly in cal_cycle() +and improve with FIELD_GET(). + +Signed-off-by: SkyLake.Huang +Reviewed-by: Simon Horman +Signed-off-by: Andrew Lunn +--- + drivers/net/phy/mediatek-ge-soc.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/drivers/net/phy/mediatek-ge-soc.c ++++ b/drivers/net/phy/mediatek-ge-soc.c +@@ -110,7 +110,7 @@ + #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) + + #define MTK_PHY_RG_AD_CAL_COMP 0x17a +-#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) ++#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8) + + #define MTK_PHY_RG_AD_CAL_CLK 0x17b + #define MTK_PHY_DA_CAL_CLK BIT(0) +@@ -351,8 +351,10 @@ static int cal_cycle(struct phy_device * + + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, + MTK_PHY_DA_CALIN_FLAG); +- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> +- MTK_PHY_AD_CAL_COMP_OUT_SHIFT; ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); ++ if (ret < 0) ++ return ret; ++ ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret); + phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); + + return ret; diff --git a/target/linux/generic/backport-6.12/723-v6.13-net-phy-mediatek-Re-organize-MediaTek-ethernet-phy-d.patch b/target/linux/generic/backport-6.12/723-v6.13-net-phy-mediatek-Re-organize-MediaTek-ethernet-phy-d.patch new file mode 100644 index 0000000000..7161ffe069 --- /dev/null +++ b/target/linux/generic/backport-6.12/723-v6.13-net-phy-mediatek-Re-organize-MediaTek-ethernet-phy-d.patch @@ -0,0 +1,3565 @@ +From e062f073dc0df4fcd338043cb0b69b6bcd31e4af Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Sat, 9 Nov 2024 00:34:51 +0800 +Subject: [PATCH 04/20] net: phy: mediatek: Re-organize MediaTek ethernet phy + drivers + +Re-organize MediaTek ethernet phy driver files and get ready to integrate +some common functions and add new 2.5G phy driver. +mtk-ge.c: MT7530 Gphy on MT7621 & MT7531 Gphy +mtk-ge-soc.c: Built-in Gphy on MT7981 & Built-in switch Gphy on MT7988 +mtk-2p5ge.c: Planned for built-in 2.5G phy on MT7988 + +Reviewed-by: Andrew Lunn +Signed-off-by: SkyLake.Huang +Signed-off-by: David S. Miller +--- + MAINTAINERS | 4 ++-- + drivers/net/phy/Kconfig | 17 +------------- + drivers/net/phy/Makefile | 3 +-- + drivers/net/phy/mediatek/Kconfig | 22 +++++++++++++++++++ + drivers/net/phy/mediatek/Makefile | 3 +++ + .../mtk-ge-soc.c} | 0 + .../phy/{mediatek-ge.c => mediatek/mtk-ge.c} | 0 + 7 files changed, 29 insertions(+), 20 deletions(-) + create mode 100644 drivers/net/phy/mediatek/Kconfig + create mode 100644 drivers/net/phy/mediatek/Makefile + rename drivers/net/phy/{mediatek-ge-soc.c => mediatek/mtk-ge-soc.c} (100%) + rename drivers/net/phy/{mediatek-ge.c => mediatek/mtk-ge.c} (100%) + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -14427,8 +14427,8 @@ M: Qingfang Deng + M: SkyLake Huang + L: netdev@vger.kernel.org + S: Maintained +-F: drivers/net/phy/mediatek-ge-soc.c +-F: drivers/net/phy/mediatek-ge.c ++F: drivers/net/phy/mediatek/mtk-ge-soc.c ++F: drivers/net/phy/mediatek/mtk-ge.c + F: drivers/phy/mediatek/phy-mtk-xfi-tphy.c + + MEDIATEK I2C CONTROLLER DRIVER +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -266,22 +266,7 @@ config MAXLINEAR_GPHY + Support for the Maxlinear GPY115, GPY211, GPY212, GPY215, + GPY241, GPY245 PHYs. + +-config MEDIATEK_GE_PHY +- tristate "MediaTek Gigabit Ethernet PHYs" +- help +- Supports the MediaTek Gigabit Ethernet PHYs. +- +-config MEDIATEK_GE_SOC_PHY +- tristate "MediaTek SoC Ethernet PHYs" +- depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST +- depends on NVMEM_MTK_EFUSE +- help +- Supports MediaTek SoC built-in Gigabit Ethernet PHYs. +- +- Include support for built-in Ethernet PHYs which are present in +- the MT7981 and MT7988 SoCs. These PHYs need calibration data +- present in the SoCs efuse and will dynamically calibrate VCM +- (common-mode voltage) during startup. ++source "drivers/net/phy/mediatek/Kconfig" + + config MICREL_PHY + tristate "Micrel PHYs" +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -74,8 +74,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o + obj-$(CONFIG_MARVELL_88Q2XXX_PHY) += marvell-88q2xxx.o + obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o + obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o +-obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o +-obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o ++obj-y += mediatek/ + obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o + obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o + obj-$(CONFIG_MICREL_PHY) += micrel.o +--- /dev/null ++++ b/drivers/net/phy/mediatek/Kconfig +@@ -0,0 +1,22 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++config MEDIATEK_GE_PHY ++ tristate "MediaTek Gigabit Ethernet PHYs" ++ help ++ Supports the MediaTek non-built-in Gigabit Ethernet PHYs. ++ ++ Non-built-in Gigabit Ethernet PHYs include mt7530/mt7531. ++ You may find mt7530 inside mt7621. This driver shares some ++ common operations with MediaTek SoC built-in Gigabit ++ Ethernet PHYs. ++ ++config MEDIATEK_GE_SOC_PHY ++ tristate "MediaTek SoC Ethernet PHYs" ++ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST ++ depends on NVMEM_MTK_EFUSE ++ help ++ Supports MediaTek SoC built-in Gigabit Ethernet PHYs. ++ ++ Include support for built-in Ethernet PHYs which are present in ++ the MT7981 and MT7988 SoCs. These PHYs need calibration data ++ present in the SoCs efuse and will dynamically calibrate VCM ++ (common-mode voltage) during startup. +--- /dev/null ++++ b/drivers/net/phy/mediatek/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o ++obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o +--- a/drivers/net/phy/mediatek-ge-soc.c ++++ /dev/null +@@ -1,1610 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#define MTK_GPHY_ID_MT7981 0x03a29461 +-#define MTK_GPHY_ID_MT7988 0x03a29481 +- +-#define MTK_EXT_PAGE_ACCESS 0x1f +-#define MTK_PHY_PAGE_STANDARD 0x0000 +-#define MTK_PHY_PAGE_EXTENDED_3 0x0003 +- +-#define MTK_PHY_LPI_REG_14 0x14 +-#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) +- +-#define MTK_PHY_LPI_REG_1c 0x1c +-#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) +- +-#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 +-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 +- +-#define ANALOG_INTERNAL_OPERATION_MAX_US 20 +-#define TXRESERVE_MIN 0 +-#define TXRESERVE_MAX 7 +- +-#define MTK_PHY_ANARG_RG 0x10 +-#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) +- +-/* Registers on MDIO_MMD_VEND1 */ +-#define MTK_PHY_TXVLD_DA_RG 0x12 +-#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) +-#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) +- +-#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 +-#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) +-#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) +- +-#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 +-#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) +-#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) +- +-#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 +-#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) +-#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) +- +-#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 +-#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) +-#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) +- +-#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 +-#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) +-#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) +- +-#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 +-#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) +-#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) +- +-#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 +-#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) +-#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) +- +-#define MTK_PHY_RXADC_CTRL_RG7 0xc6 +-#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) +- +-#define MTK_PHY_RXADC_CTRL_RG9 0xc8 +-#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) +-#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) +-#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) +-#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) +- +-#define MTK_PHY_LDO_OUTPUT_V 0xd7 +- +-#define MTK_PHY_RG_ANA_CAL_RG0 0xdb +-#define MTK_PHY_RG_CAL_CKINV BIT(12) +-#define MTK_PHY_RG_ANA_CALEN BIT(8) +-#define MTK_PHY_RG_ZCALEN_A BIT(0) +- +-#define MTK_PHY_RG_ANA_CAL_RG1 0xdc +-#define MTK_PHY_RG_ZCALEN_B BIT(12) +-#define MTK_PHY_RG_ZCALEN_C BIT(8) +-#define MTK_PHY_RG_ZCALEN_D BIT(4) +-#define MTK_PHY_RG_TXVOS_CALEN BIT(0) +- +-#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 +-#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) +- +-#define MTK_PHY_RG_TX_FILTER 0xfe +- +-#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 +-#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) +-#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) +- +-#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 +-#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) +- +-#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 +-#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) +- +-#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 +-#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) +-#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) +- +-#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 +-#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) +-#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) +- +-#define MTK_PHY_RG_AD_CAL_COMP 0x17a +-#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8) +- +-#define MTK_PHY_RG_AD_CAL_CLK 0x17b +-#define MTK_PHY_DA_CAL_CLK BIT(0) +- +-#define MTK_PHY_RG_AD_CALIN 0x17c +-#define MTK_PHY_DA_CALIN_FLAG BIT(0) +- +-#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d +-#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) +- +-#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e +-#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) +- +-#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f +-#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) +- +-#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 +-#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) +- +-#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 +-#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) +- +-#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 +-#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) +- +-#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 +-#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) +- +-#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 +-#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) +- +-#define MTK_PHY_RG_DEV1E_REG19b 0x19b +-#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) +- +-#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a +-#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b +-#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c +-#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d +-#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e +-#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f +-#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 +-#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 +-#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 +-#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 +- +-#define MTK_PHY_RG_DEV1E_REG234 0x234 +-#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) +-#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) +-#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) +- +-#define MTK_PHY_RG_LPF_CNT_VAL 0x235 +- +-#define MTK_PHY_RG_DEV1E_REG238 0x238 +-#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) +-#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) +- +-#define MTK_PHY_RG_DEV1E_REG239 0x239 +-#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) +-#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) +- +-#define MTK_PHY_RG_DEV1E_REG27C 0x27c +-#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) +-#define MTK_PHY_RG_DEV1E_REG27D 0x27d +-#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) +- +-#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 +-#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) +-#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) +- +-#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 +-#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) +-#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) +-#define MTK_PHY_LPI_TR_READY BIT(9) +-#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) +- +-#define MTK_PHY_RG_DEV1E_REG323 0x323 +-#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) +-#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) +- +-#define MTK_PHY_RG_DEV1E_REG324 0x324 +-#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) +-#define MTK_PHY_SMI_DET_MAX_EN BIT(8) +- +-#define MTK_PHY_RG_DEV1E_REG326 0x326 +-#define MTK_PHY_LPI_MODE_SD_ON BIT(0) +-#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) +-#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) +-#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) +-#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) +- +-#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 +-#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 +- +-#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d +-#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e +-#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f +-#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 +- +-/* Registers on MDIO_MMD_VEND2 */ +-#define MTK_PHY_LED0_ON_CTRL 0x24 +-#define MTK_PHY_LED1_ON_CTRL 0x26 +-#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) +-#define MTK_PHY_LED_ON_LINK1000 BIT(0) +-#define MTK_PHY_LED_ON_LINK100 BIT(1) +-#define MTK_PHY_LED_ON_LINK10 BIT(2) +-#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\ +- MTK_PHY_LED_ON_LINK100 |\ +- MTK_PHY_LED_ON_LINK1000) +-#define MTK_PHY_LED_ON_LINKDOWN BIT(3) +-#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ +-#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ +-#define MTK_PHY_LED_ON_FORCE_ON BIT(6) +-#define MTK_PHY_LED_ON_POLARITY BIT(14) +-#define MTK_PHY_LED_ON_ENABLE BIT(15) +- +-#define MTK_PHY_LED0_BLINK_CTRL 0x25 +-#define MTK_PHY_LED1_BLINK_CTRL 0x27 +-#define MTK_PHY_LED_BLINK_1000TX BIT(0) +-#define MTK_PHY_LED_BLINK_1000RX BIT(1) +-#define MTK_PHY_LED_BLINK_100TX BIT(2) +-#define MTK_PHY_LED_BLINK_100RX BIT(3) +-#define MTK_PHY_LED_BLINK_10TX BIT(4) +-#define MTK_PHY_LED_BLINK_10RX BIT(5) +-#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\ +- MTK_PHY_LED_BLINK_100RX |\ +- MTK_PHY_LED_BLINK_1000RX) +-#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\ +- MTK_PHY_LED_BLINK_100TX |\ +- MTK_PHY_LED_BLINK_1000TX) +-#define MTK_PHY_LED_BLINK_COLLISION BIT(6) +-#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) +-#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) +-#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) +- +-#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) +- +-#define MTK_PHY_RG_BG_RASEL 0x115 +-#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) +- +-/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */ +-#define RG_GPIO_MISC_TPBANK0 0x6f0 +-#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) +- +-/* These macro privides efuse parsing for internal phy. */ +-#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) +-#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) +-#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) +-#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) +-#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) +- +-#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) +-#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) +-#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) +-#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) +-#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) +- +-#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) +-#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) +- +-#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) +-#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) +- +-enum { +- NO_PAIR, +- PAIR_A, +- PAIR_B, +- PAIR_C, +- PAIR_D, +-}; +- +-enum calibration_mode { +- EFUSE_K, +- SW_K +-}; +- +-enum CAL_ITEM { +- REXT, +- TX_OFFSET, +- TX_AMP, +- TX_R50, +- TX_VCM +-}; +- +-enum CAL_MODE { +- EFUSE_M, +- SW_M +-}; +- +-#define MTK_PHY_LED_STATE_FORCE_ON 0 +-#define MTK_PHY_LED_STATE_FORCE_BLINK 1 +-#define MTK_PHY_LED_STATE_NETDEV 2 +- +-struct mtk_socphy_priv { +- unsigned long led_state; +-}; +- +-struct mtk_socphy_shared { +- u32 boottrap; +- struct mtk_socphy_priv priv[4]; +-}; +- +-static int mtk_socphy_read_page(struct phy_device *phydev) +-{ +- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +-} +- +-static int mtk_socphy_write_page(struct phy_device *phydev, int page) +-{ +- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); +-} +- +-/* One calibration cycle consists of: +- * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high +- * until AD_CAL_COMP is ready to output calibration result. +- * 2.Wait until DA_CAL_CLK is available. +- * 3.Fetch AD_CAL_COMP_OUT. +- */ +-static int cal_cycle(struct phy_device *phydev, int devad, +- u32 regnum, u16 mask, u16 cal_val) +-{ +- int reg_val; +- int ret; +- +- phy_modify_mmd(phydev, devad, regnum, +- mask, cal_val); +- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, +- MTK_PHY_DA_CALIN_FLAG); +- +- ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_AD_CAL_CLK, reg_val, +- reg_val & MTK_PHY_DA_CAL_CLK, 500, +- ANALOG_INTERNAL_OPERATION_MAX_US, +- false); +- if (ret) { +- phydev_err(phydev, "Calibration cycle timeout\n"); +- return ret; +- } +- +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, +- MTK_PHY_DA_CALIN_FLAG); +- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); +- if (ret < 0) +- return ret; +- ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret); +- phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); +- +- return ret; +-} +- +-static int rext_fill_result(struct phy_device *phydev, u16 *buf) +-{ +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, +- MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); +- phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, +- MTK_PHY_RG_BG_RASEL_MASK, buf[1]); +- +- return 0; +-} +- +-static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) +-{ +- u16 rext_cal_val[2]; +- +- rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); +- rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); +- rext_fill_result(phydev, rext_cal_val); +- +- return 0; +-} +- +-static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) +-{ +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, +- MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, +- MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, +- MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, +- MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); +- +- return 0; +-} +- +-static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) +-{ +- u16 tx_offset_cal_val[4]; +- +- tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); +- tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); +- tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); +- tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); +- +- tx_offset_fill_result(phydev, tx_offset_cal_val); +- +- return 0; +-} +- +-static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) +-{ +- const int vals_9481[16] = { 10, 6, 6, 10, +- 10, 6, 6, 10, +- 10, 6, 6, 10, +- 10, 6, 6, 10 }; +- const int vals_9461[16] = { 7, 1, 4, 7, +- 7, 1, 4, 7, +- 7, 1, 4, 7, +- 7, 1, 4, 7 }; +- int bias[16] = {}; +- int i; +- +- switch (phydev->drv->phy_id) { +- case MTK_GPHY_ID_MT7981: +- /* We add some calibration to efuse values +- * due to board level influence. +- * GBE: +7, TBT: +1, HBT: +4, TST: +7 +- */ +- memcpy(bias, (const void *)vals_9461, sizeof(bias)); +- break; +- case MTK_GPHY_ID_MT7988: +- memcpy(bias, (const void *)vals_9481, sizeof(bias)); +- break; +- } +- +- /* Prevent overflow */ +- for (i = 0; i < 12; i++) { +- if (buf[i >> 2] + bias[i] > 63) { +- buf[i >> 2] = 63; +- bias[i] = 0; +- } +- } +- +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, +- MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, +- buf[0] + bias[0])); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, +- MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, +- buf[0] + bias[1])); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, +- MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, +- buf[0] + bias[2])); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, +- MTK_PHY_DA_TX_I2MPB_A_TST_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK, +- buf[0] + bias[3])); +- +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, +- MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, +- buf[1] + bias[4])); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, +- MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, +- buf[1] + bias[5])); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, +- MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, +- buf[1] + bias[6])); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, +- MTK_PHY_DA_TX_I2MPB_B_TST_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK, +- buf[1] + bias[7])); +- +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, +- MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, +- buf[2] + bias[8])); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, +- MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, +- buf[2] + bias[9])); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, +- MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, +- buf[2] + bias[10])); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, +- MTK_PHY_DA_TX_I2MPB_C_TST_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK, +- buf[2] + bias[11])); +- +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, +- MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, +- buf[3] + bias[12])); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, +- MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, +- buf[3] + bias[13])); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, +- MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, +- buf[3] + bias[14])); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, +- MTK_PHY_DA_TX_I2MPB_D_TST_MASK, +- FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK, +- buf[3] + bias[15])); +- +- return 0; +-} +- +-static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) +-{ +- u16 tx_amp_cal_val[4]; +- +- tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); +- tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); +- tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); +- tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); +- tx_amp_fill_result(phydev, tx_amp_cal_val); +- +- return 0; +-} +- +-static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, +- u8 txg_calen_x) +-{ +- int bias = 0; +- u16 reg, val; +- +- if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) +- bias = -1; +- +- val = clamp_val(bias + tx_r50_cal_val, 0, 63); +- +- switch (txg_calen_x) { +- case PAIR_A: +- reg = MTK_PHY_DA_TX_R50_PAIR_A; +- break; +- case PAIR_B: +- reg = MTK_PHY_DA_TX_R50_PAIR_B; +- break; +- case PAIR_C: +- reg = MTK_PHY_DA_TX_R50_PAIR_C; +- break; +- case PAIR_D: +- reg = MTK_PHY_DA_TX_R50_PAIR_D; +- break; +- default: +- return -EINVAL; +- } +- +- phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); +- +- return 0; +-} +- +-static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, +- u8 txg_calen_x) +-{ +- u16 tx_r50_cal_val; +- +- switch (txg_calen_x) { +- case PAIR_A: +- tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); +- break; +- case PAIR_B: +- tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); +- break; +- case PAIR_C: +- tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); +- break; +- case PAIR_D: +- tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); +- break; +- default: +- return -EINVAL; +- } +- tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); +- +- return 0; +-} +- +-static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) +-{ +- u8 lower_idx, upper_idx, txreserve_val; +- u8 lower_ret, upper_ret; +- int ret; +- +- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, +- MTK_PHY_RG_ANA_CALEN); +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, +- MTK_PHY_RG_CAL_CKINV); +- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, +- MTK_PHY_RG_TXVOS_CALEN); +- +- switch (rg_txreserve_x) { +- case PAIR_A: +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_DASN_DAC_IN0_A, +- MTK_PHY_DASN_DAC_IN0_A_MASK); +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_DASN_DAC_IN1_A, +- MTK_PHY_DASN_DAC_IN1_A_MASK); +- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_ANA_CAL_RG0, +- MTK_PHY_RG_ZCALEN_A); +- break; +- case PAIR_B: +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_DASN_DAC_IN0_B, +- MTK_PHY_DASN_DAC_IN0_B_MASK); +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_DASN_DAC_IN1_B, +- MTK_PHY_DASN_DAC_IN1_B_MASK); +- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_ANA_CAL_RG1, +- MTK_PHY_RG_ZCALEN_B); +- break; +- case PAIR_C: +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_DASN_DAC_IN0_C, +- MTK_PHY_DASN_DAC_IN0_C_MASK); +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_DASN_DAC_IN1_C, +- MTK_PHY_DASN_DAC_IN1_C_MASK); +- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_ANA_CAL_RG1, +- MTK_PHY_RG_ZCALEN_C); +- break; +- case PAIR_D: +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_DASN_DAC_IN0_D, +- MTK_PHY_DASN_DAC_IN0_D_MASK); +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_DASN_DAC_IN1_D, +- MTK_PHY_DASN_DAC_IN1_D_MASK); +- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_ANA_CAL_RG1, +- MTK_PHY_RG_ZCALEN_D); +- break; +- default: +- ret = -EINVAL; +- goto restore; +- } +- +- lower_idx = TXRESERVE_MIN; +- upper_idx = TXRESERVE_MAX; +- +- phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); +- while ((upper_idx - lower_idx) > 1) { +- txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); +- ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, +- MTK_PHY_DA_RX_PSBN_TBT_MASK | +- MTK_PHY_DA_RX_PSBN_HBT_MASK | +- MTK_PHY_DA_RX_PSBN_GBE_MASK | +- MTK_PHY_DA_RX_PSBN_LP_MASK, +- txreserve_val << 12 | txreserve_val << 8 | +- txreserve_val << 4 | txreserve_val); +- if (ret == 1) { +- upper_idx = txreserve_val; +- upper_ret = ret; +- } else if (ret == 0) { +- lower_idx = txreserve_val; +- lower_ret = ret; +- } else { +- goto restore; +- } +- } +- +- if (lower_idx == TXRESERVE_MIN) { +- lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RXADC_CTRL_RG9, +- MTK_PHY_DA_RX_PSBN_TBT_MASK | +- MTK_PHY_DA_RX_PSBN_HBT_MASK | +- MTK_PHY_DA_RX_PSBN_GBE_MASK | +- MTK_PHY_DA_RX_PSBN_LP_MASK, +- lower_idx << 12 | lower_idx << 8 | +- lower_idx << 4 | lower_idx); +- ret = lower_ret; +- } else if (upper_idx == TXRESERVE_MAX) { +- upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RXADC_CTRL_RG9, +- MTK_PHY_DA_RX_PSBN_TBT_MASK | +- MTK_PHY_DA_RX_PSBN_HBT_MASK | +- MTK_PHY_DA_RX_PSBN_GBE_MASK | +- MTK_PHY_DA_RX_PSBN_LP_MASK, +- upper_idx << 12 | upper_idx << 8 | +- upper_idx << 4 | upper_idx); +- ret = upper_ret; +- } +- if (ret < 0) +- goto restore; +- +- /* We calibrate TX-VCM in different logic. Check upper index and then +- * lower index. If this calibration is valid, apply lower index's +- * result. +- */ +- ret = upper_ret - lower_ret; +- if (ret == 1) { +- ret = 0; +- /* Make sure we use upper_idx in our calibration system */ +- cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, +- MTK_PHY_DA_RX_PSBN_TBT_MASK | +- MTK_PHY_DA_RX_PSBN_HBT_MASK | +- MTK_PHY_DA_RX_PSBN_GBE_MASK | +- MTK_PHY_DA_RX_PSBN_LP_MASK, +- upper_idx << 12 | upper_idx << 8 | +- upper_idx << 4 | upper_idx); +- phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); +- } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && +- lower_ret == 1) { +- ret = 0; +- cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, +- MTK_PHY_DA_RX_PSBN_TBT_MASK | +- MTK_PHY_DA_RX_PSBN_HBT_MASK | +- MTK_PHY_DA_RX_PSBN_GBE_MASK | +- MTK_PHY_DA_RX_PSBN_LP_MASK, +- lower_idx << 12 | lower_idx << 8 | +- lower_idx << 4 | lower_idx); +- phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", +- lower_idx); +- } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && +- lower_ret == 0) { +- ret = 0; +- phydev_warn(phydev, +- "TX-VCM SW cal result at high margin 0x%x\n", +- upper_idx); +- } else { +- ret = -EINVAL; +- } +- +-restore: +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, +- MTK_PHY_RG_ANA_CALEN); +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, +- MTK_PHY_RG_TXVOS_CALEN); +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, +- MTK_PHY_RG_ZCALEN_A); +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, +- MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | +- MTK_PHY_RG_ZCALEN_D); +- +- return ret; +-} +- +-static void mt798x_phy_common_finetune(struct phy_device *phydev) +-{ +- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ +- __phy_write(phydev, 0x11, 0xc71); +- __phy_write(phydev, 0x12, 0xc); +- __phy_write(phydev, 0x10, 0x8fae); +- +- /* EnabRandUpdTrig = 1 */ +- __phy_write(phydev, 0x11, 0x2f00); +- __phy_write(phydev, 0x12, 0xe); +- __phy_write(phydev, 0x10, 0x8fb0); +- +- /* NormMseLoThresh = 85 */ +- __phy_write(phydev, 0x11, 0x55a0); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x83aa); +- +- /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */ +- __phy_write(phydev, 0x11, 0x240); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x9680); +- +- /* TrFreeze = 0 (mt7988 default) */ +- __phy_write(phydev, 0x11, 0x0); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x9686); +- +- /* SSTrKp100 = 5 */ +- /* SSTrKf100 = 6 */ +- /* SSTrKp1000Mas = 5 */ +- /* SSTrKf1000Mas = 6 */ +- /* SSTrKp1000Slv = 5 */ +- /* SSTrKf1000Slv = 6 */ +- __phy_write(phydev, 0x11, 0xbaef); +- __phy_write(phydev, 0x12, 0x2e); +- __phy_write(phydev, 0x10, 0x968c); +- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); +-} +- +-static void mt7981_phy_finetune(struct phy_device *phydev) +-{ +- u16 val[8] = { 0x01ce, 0x01c1, +- 0x020f, 0x0202, +- 0x03d0, 0x03c0, +- 0x0013, 0x0005 }; +- int i, k; +- +- /* 100M eye finetune: +- * Keep middle level of TX MLT3 shapper as default. +- * Only change TX MLT3 overshoot level here. +- */ +- for (k = 0, i = 1; i < 12; i++) { +- if (i % 3 == 0) +- continue; +- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); +- } +- +- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- /* ResetSyncOffset = 6 */ +- __phy_write(phydev, 0x11, 0x600); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x8fc0); +- +- /* VgaDecRate = 1 */ +- __phy_write(phydev, 0x11, 0x4c2a); +- __phy_write(phydev, 0x12, 0x3e); +- __phy_write(phydev, 0x10, 0x8fa4); +- +- /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, +- * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 +- */ +- __phy_write(phydev, 0x11, 0xd10a); +- __phy_write(phydev, 0x12, 0x34); +- __phy_write(phydev, 0x10, 0x8f82); +- +- /* VcoSlicerThreshBitsHigh */ +- __phy_write(phydev, 0x11, 0x5555); +- __phy_write(phydev, 0x12, 0x55); +- __phy_write(phydev, 0x10, 0x8ec0); +- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); +- +- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, +- MTK_PHY_TR_OPEN_LOOP_EN_MASK | +- MTK_PHY_LPF_X_AVERAGE_MASK, +- BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); +- +- /* rg_tr_lpf_cnt_val = 512 */ +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); +- +- /* IIR2 related */ +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); +- +- /* FFE peaking */ +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, +- MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, +- MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); +- +- /* Disable LDO pump */ +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); +- /* Adjust LDO output voltage */ +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); +-} +- +-static void mt7988_phy_finetune(struct phy_device *phydev) +-{ +- u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, +- 0x020d, 0x0206, 0x0384, 0x03d0, +- 0x03c6, 0x030a, 0x0011, 0x0005 }; +- int i; +- +- /* Set default MLT3 shaper first */ +- for (i = 0; i < 12; i++) +- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); +- +- /* TCT finetune */ +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); +- +- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- /* ResetSyncOffset = 5 */ +- __phy_write(phydev, 0x11, 0x500); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x8fc0); +- +- /* VgaDecRate is 1 at default on mt7988 */ +- +- /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7, +- * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7 +- */ +- __phy_write(phydev, 0x11, 0xb90a); +- __phy_write(phydev, 0x12, 0x6f); +- __phy_write(phydev, 0x10, 0x8f82); +- +- /* RemAckCntLimitCtrl = 1 */ +- __phy_write(phydev, 0x11, 0xfbba); +- __phy_write(phydev, 0x12, 0xc3); +- __phy_write(phydev, 0x10, 0x87f8); +- +- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); +- +- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, +- MTK_PHY_TR_OPEN_LOOP_EN_MASK | +- MTK_PHY_LPF_X_AVERAGE_MASK, +- BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); +- +- /* rg_tr_lpf_cnt_val = 1023 */ +- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); +-} +- +-static void mt798x_phy_eee(struct phy_device *phydev) +-{ +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, +- MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | +- MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, +- FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | +- FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); +- +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, +- MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, +- FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, +- 0xff)); +- +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_TESTMUX_ADC_CTRL, +- MTK_PHY_RG_TXEN_DIG_MASK); +- +- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); +- +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); +- +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, +- MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | +- MTK_PHY_LPI_SLV_SEND_TX_EN, +- FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); +- +- /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, +- MTK_PHY_LPI_TXPCS_LOC_RCV); +- +- /* This also fixes some IoT issues, such as CH340 */ +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, +- MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, +- FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | +- FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); +- +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, +- MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, +- FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, +- 0x33) | +- MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | +- MTK_PHY_LPI_VCO_EEE_STG0_EN); +- +- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, +- MTK_PHY_EEE_WAKE_MAS_INT_DC | +- MTK_PHY_EEE_WAKE_SLV_INT_DC); +- +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, +- MTK_PHY_SMI_DETCNT_MAX_MASK, +- FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | +- MTK_PHY_SMI_DET_MAX_EN); +- +- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, +- MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | +- MTK_PHY_TREC_UPDATE_ENAB_CLR | +- MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | +- MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); +- +- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- /* Regsigdet_sel_1000 = 0 */ +- __phy_write(phydev, 0x11, 0xb); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x9690); +- +- /* REG_EEE_st2TrKf1000 = 2 */ +- __phy_write(phydev, 0x11, 0x114f); +- __phy_write(phydev, 0x12, 0x2); +- __phy_write(phydev, 0x10, 0x969a); +- +- /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ +- __phy_write(phydev, 0x11, 0x3028); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x969e); +- +- /* RegEEE_slv_wake_int_timer_tar = 8 */ +- __phy_write(phydev, 0x11, 0x5010); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x96a0); +- +- /* RegEEE_trfreeze_timer2 = 586 */ +- __phy_write(phydev, 0x11, 0x24a); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x96a8); +- +- /* RegEEE100Stg1_tar = 16 */ +- __phy_write(phydev, 0x11, 0x3210); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x96b8); +- +- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ +- __phy_write(phydev, 0x11, 0x1463); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x96ca); +- +- /* DfeTailEnableVgaThresh1000 = 27 */ +- __phy_write(phydev, 0x11, 0x36); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x8f80); +- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); +- +- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); +- __phy_modify(phydev, MTK_PHY_LPI_REG_14, +- MTK_PHY_LPI_WAKE_TIMER_1000_MASK, +- FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); +- +- __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, +- FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); +- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); +- +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, +- MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, +- MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, +- FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, +- 0xff)); +-} +- +-static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, +- u8 start_pair, u8 end_pair) +-{ +- u8 pair_n; +- int ret; +- +- for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { +- /* TX_OFFSET & TX_AMP have no SW calibration. */ +- switch (cal_item) { +- case TX_VCM: +- ret = tx_vcm_cal_sw(phydev, pair_n); +- break; +- default: +- return -EINVAL; +- } +- if (ret) +- return ret; +- } +- return 0; +-} +- +-static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, +- u8 start_pair, u8 end_pair, u32 *buf) +-{ +- u8 pair_n; +- int ret; +- +- for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { +- /* TX_VCM has no efuse calibration. */ +- switch (cal_item) { +- case REXT: +- ret = rext_cal_efuse(phydev, buf); +- break; +- case TX_OFFSET: +- ret = tx_offset_cal_efuse(phydev, buf); +- break; +- case TX_AMP: +- ret = tx_amp_cal_efuse(phydev, buf); +- break; +- case TX_R50: +- ret = tx_r50_cal_efuse(phydev, buf, pair_n); +- break; +- default: +- return -EINVAL; +- } +- if (ret) +- return ret; +- } +- +- return 0; +-} +- +-static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, +- enum CAL_MODE cal_mode, u8 start_pair, +- u8 end_pair, u32 *buf) +-{ +- int ret; +- +- switch (cal_mode) { +- case EFUSE_M: +- ret = cal_efuse(phydev, cal_item, start_pair, +- end_pair, buf); +- break; +- case SW_M: +- ret = cal_sw(phydev, cal_item, start_pair, end_pair); +- break; +- default: +- return -EINVAL; +- } +- +- if (ret) { +- phydev_err(phydev, "cal %d failed\n", cal_item); +- return -EIO; +- } +- +- return 0; +-} +- +-static int mt798x_phy_calibration(struct phy_device *phydev) +-{ +- struct nvmem_cell *cell; +- int ret = 0; +- size_t len; +- u32 *buf; +- +- cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); +- if (IS_ERR(cell)) { +- if (PTR_ERR(cell) == -EPROBE_DEFER) +- return PTR_ERR(cell); +- return 0; +- } +- +- buf = (u32 *)nvmem_cell_read(cell, &len); +- if (IS_ERR(buf)) +- return PTR_ERR(buf); +- nvmem_cell_put(cell); +- +- if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { +- phydev_err(phydev, "invalid efuse data\n"); +- ret = -EINVAL; +- goto out; +- } +- +- ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); +- if (ret) +- goto out; +- ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); +- if (ret) +- goto out; +- ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); +- if (ret) +- goto out; +- ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); +- if (ret) +- goto out; +- ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); +- if (ret) +- goto out; +- +-out: +- kfree(buf); +- return ret; +-} +- +-static int mt798x_phy_config_init(struct phy_device *phydev) +-{ +- switch (phydev->drv->phy_id) { +- case MTK_GPHY_ID_MT7981: +- mt7981_phy_finetune(phydev); +- break; +- case MTK_GPHY_ID_MT7988: +- mt7988_phy_finetune(phydev); +- break; +- } +- +- mt798x_phy_common_finetune(phydev); +- mt798x_phy_eee(phydev); +- +- return mt798x_phy_calibration(phydev); +-} +- +-static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index, +- bool on) +-{ +- unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); +- struct mtk_socphy_priv *priv = phydev->priv; +- bool changed; +- +- if (on) +- changed = !test_and_set_bit(bit_on, &priv->led_state); +- else +- changed = !!test_and_clear_bit(bit_on, &priv->led_state); +- +- changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + +- (index ? 16 : 0), &priv->led_state); +- if (changed) +- return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? +- MTK_PHY_LED1_ON_CTRL : +- MTK_PHY_LED0_ON_CTRL, +- MTK_PHY_LED_ON_MASK, +- on ? MTK_PHY_LED_ON_FORCE_ON : 0); +- else +- return 0; +-} +- +-static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, +- bool blinking) +-{ +- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + +- (index ? 16 : 0); +- struct mtk_socphy_priv *priv = phydev->priv; +- bool changed; +- +- if (blinking) +- changed = !test_and_set_bit(bit_blink, &priv->led_state); +- else +- changed = !!test_and_clear_bit(bit_blink, &priv->led_state); +- +- changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV + +- (index ? 16 : 0), &priv->led_state); +- if (changed) +- return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? +- MTK_PHY_LED1_BLINK_CTRL : +- MTK_PHY_LED0_BLINK_CTRL, +- blinking ? +- MTK_PHY_LED_BLINK_FORCE_BLINK : 0); +- else +- return 0; +-} +- +-static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, +- unsigned long *delay_on, +- unsigned long *delay_off) +-{ +- bool blinking = false; +- int err = 0; +- +- if (index > 1) +- return -EINVAL; +- +- if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { +- blinking = true; +- *delay_on = 50; +- *delay_off = 50; +- } +- +- err = mt798x_phy_hw_led_blink_set(phydev, index, blinking); +- if (err) +- return err; +- +- return mt798x_phy_hw_led_on_set(phydev, index, false); +-} +- +-static int mt798x_phy_led_brightness_set(struct phy_device *phydev, +- u8 index, enum led_brightness value) +-{ +- int err; +- +- err = mt798x_phy_hw_led_blink_set(phydev, index, false); +- if (err) +- return err; +- +- return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF)); +-} +- +-static const unsigned long supported_triggers = +- BIT(TRIGGER_NETDEV_FULL_DUPLEX) | +- BIT(TRIGGER_NETDEV_HALF_DUPLEX) | +- BIT(TRIGGER_NETDEV_LINK) | +- BIT(TRIGGER_NETDEV_LINK_10) | +- BIT(TRIGGER_NETDEV_LINK_100) | +- BIT(TRIGGER_NETDEV_LINK_1000) | +- BIT(TRIGGER_NETDEV_RX) | +- BIT(TRIGGER_NETDEV_TX); +- +-static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, +- unsigned long rules) +-{ +- if (index > 1) +- return -EINVAL; +- +- /* All combinations of the supported triggers are allowed */ +- if (rules & ~supported_triggers) +- return -EOPNOTSUPP; +- +- return 0; +-}; +- +-static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, +- unsigned long *rules) +-{ +- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + +- (index ? 16 : 0); +- unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); +- unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); +- struct mtk_socphy_priv *priv = phydev->priv; +- int on, blink; +- +- if (index > 1) +- return -EINVAL; +- +- on = phy_read_mmd(phydev, MDIO_MMD_VEND2, +- index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); +- +- if (on < 0) +- return -EIO; +- +- blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, +- index ? MTK_PHY_LED1_BLINK_CTRL : +- MTK_PHY_LED0_BLINK_CTRL); +- if (blink < 0) +- return -EIO; +- +- if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | +- MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) || +- (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX))) +- set_bit(bit_netdev, &priv->led_state); +- else +- clear_bit(bit_netdev, &priv->led_state); +- +- if (on & MTK_PHY_LED_ON_FORCE_ON) +- set_bit(bit_on, &priv->led_state); +- else +- clear_bit(bit_on, &priv->led_state); +- +- if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) +- set_bit(bit_blink, &priv->led_state); +- else +- clear_bit(bit_blink, &priv->led_state); +- +- if (!rules) +- return 0; +- +- if (on & MTK_PHY_LED_ON_LINK) +- *rules |= BIT(TRIGGER_NETDEV_LINK); +- +- if (on & MTK_PHY_LED_ON_LINK10) +- *rules |= BIT(TRIGGER_NETDEV_LINK_10); +- +- if (on & MTK_PHY_LED_ON_LINK100) +- *rules |= BIT(TRIGGER_NETDEV_LINK_100); +- +- if (on & MTK_PHY_LED_ON_LINK1000) +- *rules |= BIT(TRIGGER_NETDEV_LINK_1000); +- +- if (on & MTK_PHY_LED_ON_FDX) +- *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); +- +- if (on & MTK_PHY_LED_ON_HDX) +- *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); +- +- if (blink & MTK_PHY_LED_BLINK_RX) +- *rules |= BIT(TRIGGER_NETDEV_RX); +- +- if (blink & MTK_PHY_LED_BLINK_TX) +- *rules |= BIT(TRIGGER_NETDEV_TX); +- +- return 0; +-}; +- +-static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, +- unsigned long rules) +-{ +- unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); +- struct mtk_socphy_priv *priv = phydev->priv; +- u16 on = 0, blink = 0; +- int ret; +- +- if (index > 1) +- return -EINVAL; +- +- if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) +- on |= MTK_PHY_LED_ON_FDX; +- +- if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) +- on |= MTK_PHY_LED_ON_HDX; +- +- if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) +- on |= MTK_PHY_LED_ON_LINK10; +- +- if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) +- on |= MTK_PHY_LED_ON_LINK100; +- +- if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) +- on |= MTK_PHY_LED_ON_LINK1000; +- +- if (rules & BIT(TRIGGER_NETDEV_RX)) { +- blink |= (on & MTK_PHY_LED_ON_LINK) ? +- (((on & MTK_PHY_LED_ON_LINK10) ? +- MTK_PHY_LED_BLINK_10RX : 0) | +- ((on & MTK_PHY_LED_ON_LINK100) ? +- MTK_PHY_LED_BLINK_100RX : 0) | +- ((on & MTK_PHY_LED_ON_LINK1000) ? +- MTK_PHY_LED_BLINK_1000RX : 0)) : +- MTK_PHY_LED_BLINK_RX; +- } +- +- if (rules & BIT(TRIGGER_NETDEV_TX)) { +- blink |= (on & MTK_PHY_LED_ON_LINK) ? +- (((on & MTK_PHY_LED_ON_LINK10) ? +- MTK_PHY_LED_BLINK_10TX : 0) | +- ((on & MTK_PHY_LED_ON_LINK100) ? +- MTK_PHY_LED_BLINK_100TX : 0) | +- ((on & MTK_PHY_LED_ON_LINK1000) ? +- MTK_PHY_LED_BLINK_1000TX : 0)) : +- MTK_PHY_LED_BLINK_TX; +- } +- +- if (blink || on) +- set_bit(bit_netdev, &priv->led_state); +- else +- clear_bit(bit_netdev, &priv->led_state); +- +- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? +- MTK_PHY_LED1_ON_CTRL : +- MTK_PHY_LED0_ON_CTRL, +- MTK_PHY_LED_ON_FDX | +- MTK_PHY_LED_ON_HDX | +- MTK_PHY_LED_ON_LINK, +- on); +- +- if (ret) +- return ret; +- +- return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? +- MTK_PHY_LED1_BLINK_CTRL : +- MTK_PHY_LED0_BLINK_CTRL, blink); +-}; +- +-static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) +-{ +- struct mtk_socphy_shared *priv = phydev->shared->priv; +- u32 polarities; +- +- if (led_num == 0) +- polarities = ~(priv->boottrap); +- else +- polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; +- +- if (polarities & BIT(phydev->mdio.addr)) +- return true; +- +- return false; +-} +- +-static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) +-{ +- struct pinctrl *pinctrl; +- int index; +- +- /* Setup LED polarity according to bootstrap use of LED pins */ +- for (index = 0; index < 2; ++index) +- phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? +- MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, +- MTK_PHY_LED_ON_POLARITY, +- mt7988_phy_led_get_polarity(phydev, index) ? +- MTK_PHY_LED_ON_POLARITY : 0); +- +- /* Only now setup pinctrl to avoid bogus blinking */ +- pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); +- if (IS_ERR(pinctrl)) +- dev_err(&phydev->mdio.bus->dev, +- "Failed to setup PHY LED pinctrl\n"); +- +- return 0; +-} +- +-static int mt7988_phy_probe_shared(struct phy_device *phydev) +-{ +- struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); +- struct mtk_socphy_shared *shared = phydev->shared->priv; +- struct regmap *regmap; +- u32 reg; +- int ret; +- +- /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, +- * LED_C and LED_D respectively. At the same time those pins are used to +- * bootstrap configuration of the reference clock source (LED_A), +- * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). +- * In practice this is done using a LED and a resistor pulling the pin +- * either to GND or to VIO. +- * The detected value at boot time is accessible at run-time using the +- * TPBANK0 register located in the gpio base of the pinctrl, in order +- * to read it here it needs to be referenced by a phandle called +- * 'mediatek,pio' in the MDIO bus hosting the PHY. +- * The 4 bits in TPBANK0 are kept as package shared data and are used to +- * set LED polarity for each of the LED0. +- */ +- regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); +- if (IS_ERR(regmap)) +- return PTR_ERR(regmap); +- +- ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); +- if (ret) +- return ret; +- +- shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); +- +- return 0; +-} +- +-static void mt798x_phy_leds_state_init(struct phy_device *phydev) +-{ +- int i; +- +- for (i = 0; i < 2; ++i) +- mt798x_phy_led_hw_control_get(phydev, i, NULL); +-} +- +-static int mt7988_phy_probe(struct phy_device *phydev) +-{ +- struct mtk_socphy_shared *shared; +- struct mtk_socphy_priv *priv; +- int err; +- +- if (phydev->mdio.addr > 3) +- return -EINVAL; +- +- err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, +- sizeof(struct mtk_socphy_shared)); +- if (err) +- return err; +- +- if (phy_package_probe_once(phydev)) { +- err = mt7988_phy_probe_shared(phydev); +- if (err) +- return err; +- } +- +- shared = phydev->shared->priv; +- priv = &shared->priv[phydev->mdio.addr]; +- +- phydev->priv = priv; +- +- mt798x_phy_leds_state_init(phydev); +- +- err = mt7988_phy_fix_leds_polarities(phydev); +- if (err) +- return err; +- +- /* Disable TX power saving at probing to: +- * 1. Meet common mode compliance test criteria +- * 2. Make sure that TX-VCM calibration works fine +- */ +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, +- MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); +- +- return mt798x_phy_calibration(phydev); +-} +- +-static int mt7981_phy_probe(struct phy_device *phydev) +-{ +- struct mtk_socphy_priv *priv; +- +- priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), +- GFP_KERNEL); +- if (!priv) +- return -ENOMEM; +- +- phydev->priv = priv; +- +- mt798x_phy_leds_state_init(phydev); +- +- return mt798x_phy_calibration(phydev); +-} +- +-static struct phy_driver mtk_socphy_driver[] = { +- { +- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), +- .name = "MediaTek MT7981 PHY", +- .config_init = mt798x_phy_config_init, +- .config_intr = genphy_no_config_intr, +- .handle_interrupt = genphy_handle_interrupt_no_ack, +- .probe = mt7981_phy_probe, +- .suspend = genphy_suspend, +- .resume = genphy_resume, +- .read_page = mtk_socphy_read_page, +- .write_page = mtk_socphy_write_page, +- .led_blink_set = mt798x_phy_led_blink_set, +- .led_brightness_set = mt798x_phy_led_brightness_set, +- .led_hw_is_supported = mt798x_phy_led_hw_is_supported, +- .led_hw_control_set = mt798x_phy_led_hw_control_set, +- .led_hw_control_get = mt798x_phy_led_hw_control_get, +- }, +- { +- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), +- .name = "MediaTek MT7988 PHY", +- .config_init = mt798x_phy_config_init, +- .config_intr = genphy_no_config_intr, +- .handle_interrupt = genphy_handle_interrupt_no_ack, +- .probe = mt7988_phy_probe, +- .suspend = genphy_suspend, +- .resume = genphy_resume, +- .read_page = mtk_socphy_read_page, +- .write_page = mtk_socphy_write_page, +- .led_blink_set = mt798x_phy_led_blink_set, +- .led_brightness_set = mt798x_phy_led_brightness_set, +- .led_hw_is_supported = mt798x_phy_led_hw_is_supported, +- .led_hw_control_set = mt798x_phy_led_hw_control_set, +- .led_hw_control_get = mt798x_phy_led_hw_control_get, +- }, +-}; +- +-module_phy_driver(mtk_socphy_driver); +- +-static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { +- { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, +- { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, +- { } +-}; +- +-MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); +-MODULE_AUTHOR("Daniel Golle "); +-MODULE_AUTHOR("SkyLake Huang "); +-MODULE_LICENSE("GPL"); +- +-MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); +--- a/drivers/net/phy/mediatek-ge.c ++++ /dev/null +@@ -1,111 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-#include +-#include +-#include +- +-#define MTK_EXT_PAGE_ACCESS 0x1f +-#define MTK_PHY_PAGE_STANDARD 0x0000 +-#define MTK_PHY_PAGE_EXTENDED 0x0001 +-#define MTK_PHY_PAGE_EXTENDED_2 0x0002 +-#define MTK_PHY_PAGE_EXTENDED_3 0x0003 +-#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 +-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 +- +-static int mtk_gephy_read_page(struct phy_device *phydev) +-{ +- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +-} +- +-static int mtk_gephy_write_page(struct phy_device *phydev, int page) +-{ +- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); +-} +- +-static void mtk_gephy_config_init(struct phy_device *phydev) +-{ +- /* Enable HW auto downshift */ +- phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); +- +- /* Increase SlvDPSready time */ +- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- __phy_write(phydev, 0x10, 0xafae); +- __phy_write(phydev, 0x12, 0x2f); +- __phy_write(phydev, 0x10, 0x8fae); +- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); +- +- /* Adjust 100_mse_threshold */ +- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); +- +- /* Disable mcc */ +- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); +-} +- +-static int mt7530_phy_config_init(struct phy_device *phydev) +-{ +- mtk_gephy_config_init(phydev); +- +- /* Increase post_update_timer */ +- phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b); +- +- return 0; +-} +- +-static int mt7531_phy_config_init(struct phy_device *phydev) +-{ +- mtk_gephy_config_init(phydev); +- +- /* PHY link down power saving enable */ +- phy_set_bits(phydev, 0x17, BIT(4)); +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); +- +- /* Set TX Pair delay selection */ +- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); +- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); +- +- return 0; +-} +- +-static struct phy_driver mtk_gephy_driver[] = { +- { +- PHY_ID_MATCH_EXACT(0x03a29412), +- .name = "MediaTek MT7530 PHY", +- .config_init = mt7530_phy_config_init, +- /* Interrupts are handled by the switch, not the PHY +- * itself. +- */ +- .config_intr = genphy_no_config_intr, +- .handle_interrupt = genphy_handle_interrupt_no_ack, +- .suspend = genphy_suspend, +- .resume = genphy_resume, +- .read_page = mtk_gephy_read_page, +- .write_page = mtk_gephy_write_page, +- }, +- { +- PHY_ID_MATCH_EXACT(0x03a29441), +- .name = "MediaTek MT7531 PHY", +- .config_init = mt7531_phy_config_init, +- /* Interrupts are handled by the switch, not the PHY +- * itself. +- */ +- .config_intr = genphy_no_config_intr, +- .handle_interrupt = genphy_handle_interrupt_no_ack, +- .suspend = genphy_suspend, +- .resume = genphy_resume, +- .read_page = mtk_gephy_read_page, +- .write_page = mtk_gephy_write_page, +- }, +-}; +- +-module_phy_driver(mtk_gephy_driver); +- +-static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { +- { PHY_ID_MATCH_EXACT(0x03a29441) }, +- { PHY_ID_MATCH_EXACT(0x03a29412) }, +- { } +-}; +- +-MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver"); +-MODULE_AUTHOR("DENG, Qingfang "); +-MODULE_LICENSE("GPL"); +- +-MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl); +--- /dev/null ++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c +@@ -0,0 +1,1610 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MTK_GPHY_ID_MT7981 0x03a29461 ++#define MTK_GPHY_ID_MT7988 0x03a29481 ++ ++#define MTK_EXT_PAGE_ACCESS 0x1f ++#define MTK_PHY_PAGE_STANDARD 0x0000 ++#define MTK_PHY_PAGE_EXTENDED_3 0x0003 ++ ++#define MTK_PHY_LPI_REG_14 0x14 ++#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) ++ ++#define MTK_PHY_LPI_REG_1c 0x1c ++#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) ++ ++#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 ++#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 ++ ++#define ANALOG_INTERNAL_OPERATION_MAX_US 20 ++#define TXRESERVE_MIN 0 ++#define TXRESERVE_MAX 7 ++ ++#define MTK_PHY_ANARG_RG 0x10 ++#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) ++ ++/* Registers on MDIO_MMD_VEND1 */ ++#define MTK_PHY_TXVLD_DA_RG 0x12 ++#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) ++#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 ++#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) ++#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 ++#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 ++#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 ++#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 ++#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 ++#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 ++#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) ++#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) ++ ++#define MTK_PHY_RXADC_CTRL_RG7 0xc6 ++#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) ++ ++#define MTK_PHY_RXADC_CTRL_RG9 0xc8 ++#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) ++#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) ++#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) ++#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) ++ ++#define MTK_PHY_LDO_OUTPUT_V 0xd7 ++ ++#define MTK_PHY_RG_ANA_CAL_RG0 0xdb ++#define MTK_PHY_RG_CAL_CKINV BIT(12) ++#define MTK_PHY_RG_ANA_CALEN BIT(8) ++#define MTK_PHY_RG_ZCALEN_A BIT(0) ++ ++#define MTK_PHY_RG_ANA_CAL_RG1 0xdc ++#define MTK_PHY_RG_ZCALEN_B BIT(12) ++#define MTK_PHY_RG_ZCALEN_C BIT(8) ++#define MTK_PHY_RG_ZCALEN_D BIT(4) ++#define MTK_PHY_RG_TXVOS_CALEN BIT(0) ++ ++#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 ++#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) ++ ++#define MTK_PHY_RG_TX_FILTER 0xfe ++ ++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 ++#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) ++#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) ++ ++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 ++#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) ++ ++#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 ++#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) ++ ++#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 ++#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) ++#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) ++ ++#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 ++#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) ++#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) ++ ++#define MTK_PHY_RG_AD_CAL_COMP 0x17a ++#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8) ++ ++#define MTK_PHY_RG_AD_CAL_CLK 0x17b ++#define MTK_PHY_DA_CAL_CLK BIT(0) ++ ++#define MTK_PHY_RG_AD_CALIN 0x17c ++#define MTK_PHY_DA_CALIN_FLAG BIT(0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d ++#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e ++#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f ++#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 ++#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 ++#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 ++#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 ++#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 ++#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) ++ ++#define MTK_PHY_RG_DEV1E_REG19b 0x19b ++#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) ++ ++#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a ++#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b ++#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c ++#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d ++#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e ++#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f ++#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 ++#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 ++#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 ++#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 ++ ++#define MTK_PHY_RG_DEV1E_REG234 0x234 ++#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) ++#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) ++#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) ++ ++#define MTK_PHY_RG_LPF_CNT_VAL 0x235 ++ ++#define MTK_PHY_RG_DEV1E_REG238 0x238 ++#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) ++#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) ++ ++#define MTK_PHY_RG_DEV1E_REG239 0x239 ++#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) ++#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) ++ ++#define MTK_PHY_RG_DEV1E_REG27C 0x27c ++#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) ++#define MTK_PHY_RG_DEV1E_REG27D 0x27d ++#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) ++ ++#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 ++#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) ++#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) ++ ++#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 ++#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) ++#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) ++#define MTK_PHY_LPI_TR_READY BIT(9) ++#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) ++ ++#define MTK_PHY_RG_DEV1E_REG323 0x323 ++#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) ++#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) ++ ++#define MTK_PHY_RG_DEV1E_REG324 0x324 ++#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) ++#define MTK_PHY_SMI_DET_MAX_EN BIT(8) ++ ++#define MTK_PHY_RG_DEV1E_REG326 0x326 ++#define MTK_PHY_LPI_MODE_SD_ON BIT(0) ++#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) ++#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) ++#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) ++#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) ++ ++#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 ++#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 ++ ++#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d ++#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e ++#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f ++#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 ++ ++/* Registers on MDIO_MMD_VEND2 */ ++#define MTK_PHY_LED0_ON_CTRL 0x24 ++#define MTK_PHY_LED1_ON_CTRL 0x26 ++#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) ++#define MTK_PHY_LED_ON_LINK1000 BIT(0) ++#define MTK_PHY_LED_ON_LINK100 BIT(1) ++#define MTK_PHY_LED_ON_LINK10 BIT(2) ++#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\ ++ MTK_PHY_LED_ON_LINK100 |\ ++ MTK_PHY_LED_ON_LINK1000) ++#define MTK_PHY_LED_ON_LINKDOWN BIT(3) ++#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ ++#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ ++#define MTK_PHY_LED_ON_FORCE_ON BIT(6) ++#define MTK_PHY_LED_ON_POLARITY BIT(14) ++#define MTK_PHY_LED_ON_ENABLE BIT(15) ++ ++#define MTK_PHY_LED0_BLINK_CTRL 0x25 ++#define MTK_PHY_LED1_BLINK_CTRL 0x27 ++#define MTK_PHY_LED_BLINK_1000TX BIT(0) ++#define MTK_PHY_LED_BLINK_1000RX BIT(1) ++#define MTK_PHY_LED_BLINK_100TX BIT(2) ++#define MTK_PHY_LED_BLINK_100RX BIT(3) ++#define MTK_PHY_LED_BLINK_10TX BIT(4) ++#define MTK_PHY_LED_BLINK_10RX BIT(5) ++#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\ ++ MTK_PHY_LED_BLINK_100RX |\ ++ MTK_PHY_LED_BLINK_1000RX) ++#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\ ++ MTK_PHY_LED_BLINK_100TX |\ ++ MTK_PHY_LED_BLINK_1000TX) ++#define MTK_PHY_LED_BLINK_COLLISION BIT(6) ++#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) ++#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) ++#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) ++ ++#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) ++ ++#define MTK_PHY_RG_BG_RASEL 0x115 ++#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) ++ ++/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */ ++#define RG_GPIO_MISC_TPBANK0 0x6f0 ++#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) ++ ++/* These macro privides efuse parsing for internal phy. */ ++#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) ++#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) ++#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) ++#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) ++#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) ++ ++#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) ++#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) ++#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) ++#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) ++#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) ++ ++#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) ++#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) ++ ++#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) ++#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) ++ ++enum { ++ NO_PAIR, ++ PAIR_A, ++ PAIR_B, ++ PAIR_C, ++ PAIR_D, ++}; ++ ++enum calibration_mode { ++ EFUSE_K, ++ SW_K ++}; ++ ++enum CAL_ITEM { ++ REXT, ++ TX_OFFSET, ++ TX_AMP, ++ TX_R50, ++ TX_VCM ++}; ++ ++enum CAL_MODE { ++ EFUSE_M, ++ SW_M ++}; ++ ++#define MTK_PHY_LED_STATE_FORCE_ON 0 ++#define MTK_PHY_LED_STATE_FORCE_BLINK 1 ++#define MTK_PHY_LED_STATE_NETDEV 2 ++ ++struct mtk_socphy_priv { ++ unsigned long led_state; ++}; ++ ++struct mtk_socphy_shared { ++ u32 boottrap; ++ struct mtk_socphy_priv priv[4]; ++}; ++ ++static int mtk_socphy_read_page(struct phy_device *phydev) ++{ ++ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); ++} ++ ++static int mtk_socphy_write_page(struct phy_device *phydev, int page) ++{ ++ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); ++} ++ ++/* One calibration cycle consists of: ++ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high ++ * until AD_CAL_COMP is ready to output calibration result. ++ * 2.Wait until DA_CAL_CLK is available. ++ * 3.Fetch AD_CAL_COMP_OUT. ++ */ ++static int cal_cycle(struct phy_device *phydev, int devad, ++ u32 regnum, u16 mask, u16 cal_val) ++{ ++ int reg_val; ++ int ret; ++ ++ phy_modify_mmd(phydev, devad, regnum, ++ mask, cal_val); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, ++ MTK_PHY_DA_CALIN_FLAG); ++ ++ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_AD_CAL_CLK, reg_val, ++ reg_val & MTK_PHY_DA_CAL_CLK, 500, ++ ANALOG_INTERNAL_OPERATION_MAX_US, ++ false); ++ if (ret) { ++ phydev_err(phydev, "Calibration cycle timeout\n"); ++ return ret; ++ } ++ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, ++ MTK_PHY_DA_CALIN_FLAG); ++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); ++ if (ret < 0) ++ return ret; ++ ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret); ++ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); ++ ++ return ret; ++} ++ ++static int rext_fill_result(struct phy_device *phydev, u16 *buf) ++{ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, ++ MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, ++ MTK_PHY_RG_BG_RASEL_MASK, buf[1]); ++ ++ return 0; ++} ++ ++static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) ++{ ++ u16 rext_cal_val[2]; ++ ++ rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); ++ rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); ++ rext_fill_result(phydev, rext_cal_val); ++ ++ return 0; ++} ++ ++static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) ++{ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, ++ MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, ++ MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, ++ MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, ++ MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); ++ ++ return 0; ++} ++ ++static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) ++{ ++ u16 tx_offset_cal_val[4]; ++ ++ tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); ++ tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); ++ tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); ++ tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); ++ ++ tx_offset_fill_result(phydev, tx_offset_cal_val); ++ ++ return 0; ++} ++ ++static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) ++{ ++ const int vals_9481[16] = { 10, 6, 6, 10, ++ 10, 6, 6, 10, ++ 10, 6, 6, 10, ++ 10, 6, 6, 10 }; ++ const int vals_9461[16] = { 7, 1, 4, 7, ++ 7, 1, 4, 7, ++ 7, 1, 4, 7, ++ 7, 1, 4, 7 }; ++ int bias[16] = {}; ++ int i; ++ ++ switch (phydev->drv->phy_id) { ++ case MTK_GPHY_ID_MT7981: ++ /* We add some calibration to efuse values ++ * due to board level influence. ++ * GBE: +7, TBT: +1, HBT: +4, TST: +7 ++ */ ++ memcpy(bias, (const void *)vals_9461, sizeof(bias)); ++ break; ++ case MTK_GPHY_ID_MT7988: ++ memcpy(bias, (const void *)vals_9481, sizeof(bias)); ++ break; ++ } ++ ++ /* Prevent overflow */ ++ for (i = 0; i < 12; i++) { ++ if (buf[i >> 2] + bias[i] > 63) { ++ buf[i >> 2] = 63; ++ bias[i] = 0; ++ } ++ } ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, ++ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, ++ buf[0] + bias[0])); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, ++ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, ++ buf[0] + bias[1])); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, ++ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, ++ buf[0] + bias[2])); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, ++ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK, ++ buf[0] + bias[3])); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, ++ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, ++ buf[1] + bias[4])); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, ++ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, ++ buf[1] + bias[5])); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, ++ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, ++ buf[1] + bias[6])); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, ++ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK, ++ buf[1] + bias[7])); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, ++ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, ++ buf[2] + bias[8])); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, ++ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, ++ buf[2] + bias[9])); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, ++ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, ++ buf[2] + bias[10])); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, ++ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK, ++ buf[2] + bias[11])); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, ++ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, ++ buf[3] + bias[12])); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, ++ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, ++ buf[3] + bias[13])); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, ++ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, ++ buf[3] + bias[14])); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, ++ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, ++ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK, ++ buf[3] + bias[15])); ++ ++ return 0; ++} ++ ++static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) ++{ ++ u16 tx_amp_cal_val[4]; ++ ++ tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); ++ tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); ++ tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); ++ tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); ++ tx_amp_fill_result(phydev, tx_amp_cal_val); ++ ++ return 0; ++} ++ ++static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, ++ u8 txg_calen_x) ++{ ++ int bias = 0; ++ u16 reg, val; ++ ++ if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) ++ bias = -1; ++ ++ val = clamp_val(bias + tx_r50_cal_val, 0, 63); ++ ++ switch (txg_calen_x) { ++ case PAIR_A: ++ reg = MTK_PHY_DA_TX_R50_PAIR_A; ++ break; ++ case PAIR_B: ++ reg = MTK_PHY_DA_TX_R50_PAIR_B; ++ break; ++ case PAIR_C: ++ reg = MTK_PHY_DA_TX_R50_PAIR_C; ++ break; ++ case PAIR_D: ++ reg = MTK_PHY_DA_TX_R50_PAIR_D; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); ++ ++ return 0; ++} ++ ++static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, ++ u8 txg_calen_x) ++{ ++ u16 tx_r50_cal_val; ++ ++ switch (txg_calen_x) { ++ case PAIR_A: ++ tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); ++ break; ++ case PAIR_B: ++ tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); ++ break; ++ case PAIR_C: ++ tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); ++ break; ++ case PAIR_D: ++ tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); ++ break; ++ default: ++ return -EINVAL; ++ } ++ tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); ++ ++ return 0; ++} ++ ++static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) ++{ ++ u8 lower_idx, upper_idx, txreserve_val; ++ u8 lower_ret, upper_ret; ++ int ret; ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ANA_CALEN); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_CAL_CKINV); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_TXVOS_CALEN); ++ ++ switch (rg_txreserve_x) { ++ case PAIR_A: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_A, ++ MTK_PHY_DASN_DAC_IN0_A_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_A, ++ MTK_PHY_DASN_DAC_IN1_A_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ZCALEN_A); ++ break; ++ case PAIR_B: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_B, ++ MTK_PHY_DASN_DAC_IN0_B_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_B, ++ MTK_PHY_DASN_DAC_IN1_B_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_B); ++ break; ++ case PAIR_C: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_C, ++ MTK_PHY_DASN_DAC_IN0_C_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_C, ++ MTK_PHY_DASN_DAC_IN1_C_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_C); ++ break; ++ case PAIR_D: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN0_D, ++ MTK_PHY_DASN_DAC_IN0_D_MASK); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DASN_DAC_IN1_D, ++ MTK_PHY_DASN_DAC_IN1_D_MASK); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_D); ++ break; ++ default: ++ ret = -EINVAL; ++ goto restore; ++ } ++ ++ lower_idx = TXRESERVE_MIN; ++ upper_idx = TXRESERVE_MAX; ++ ++ phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); ++ while ((upper_idx - lower_idx) > 1) { ++ txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); ++ ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ txreserve_val << 12 | txreserve_val << 8 | ++ txreserve_val << 4 | txreserve_val); ++ if (ret == 1) { ++ upper_idx = txreserve_val; ++ upper_ret = ret; ++ } else if (ret == 0) { ++ lower_idx = txreserve_val; ++ lower_ret = ret; ++ } else { ++ goto restore; ++ } ++ } ++ ++ if (lower_idx == TXRESERVE_MIN) { ++ lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ lower_idx << 12 | lower_idx << 8 | ++ lower_idx << 4 | lower_idx); ++ ret = lower_ret; ++ } else if (upper_idx == TXRESERVE_MAX) { ++ upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ upper_idx << 12 | upper_idx << 8 | ++ upper_idx << 4 | upper_idx); ++ ret = upper_ret; ++ } ++ if (ret < 0) ++ goto restore; ++ ++ /* We calibrate TX-VCM in different logic. Check upper index and then ++ * lower index. If this calibration is valid, apply lower index's ++ * result. ++ */ ++ ret = upper_ret - lower_ret; ++ if (ret == 1) { ++ ret = 0; ++ /* Make sure we use upper_idx in our calibration system */ ++ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ upper_idx << 12 | upper_idx << 8 | ++ upper_idx << 4 | upper_idx); ++ phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); ++ } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && ++ lower_ret == 1) { ++ ret = 0; ++ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, ++ MTK_PHY_DA_RX_PSBN_TBT_MASK | ++ MTK_PHY_DA_RX_PSBN_HBT_MASK | ++ MTK_PHY_DA_RX_PSBN_GBE_MASK | ++ MTK_PHY_DA_RX_PSBN_LP_MASK, ++ lower_idx << 12 | lower_idx << 8 | ++ lower_idx << 4 | lower_idx); ++ phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", ++ lower_idx); ++ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && ++ lower_ret == 0) { ++ ret = 0; ++ phydev_warn(phydev, ++ "TX-VCM SW cal result at high margin 0x%x\n", ++ upper_idx); ++ } else { ++ ret = -EINVAL; ++ } ++ ++restore: ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ANA_CALEN); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_TXVOS_CALEN); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, ++ MTK_PHY_RG_ZCALEN_A); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, ++ MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | ++ MTK_PHY_RG_ZCALEN_D); ++ ++ return ret; ++} ++ ++static void mt798x_phy_common_finetune(struct phy_device *phydev) ++{ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ ++ __phy_write(phydev, 0x11, 0xc71); ++ __phy_write(phydev, 0x12, 0xc); ++ __phy_write(phydev, 0x10, 0x8fae); ++ ++ /* EnabRandUpdTrig = 1 */ ++ __phy_write(phydev, 0x11, 0x2f00); ++ __phy_write(phydev, 0x12, 0xe); ++ __phy_write(phydev, 0x10, 0x8fb0); ++ ++ /* NormMseLoThresh = 85 */ ++ __phy_write(phydev, 0x11, 0x55a0); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x83aa); ++ ++ /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */ ++ __phy_write(phydev, 0x11, 0x240); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9680); ++ ++ /* TrFreeze = 0 (mt7988 default) */ ++ __phy_write(phydev, 0x11, 0x0); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9686); ++ ++ /* SSTrKp100 = 5 */ ++ /* SSTrKf100 = 6 */ ++ /* SSTrKp1000Mas = 5 */ ++ /* SSTrKf1000Mas = 6 */ ++ /* SSTrKp1000Slv = 5 */ ++ /* SSTrKf1000Slv = 6 */ ++ __phy_write(phydev, 0x11, 0xbaef); ++ __phy_write(phydev, 0x12, 0x2e); ++ __phy_write(phydev, 0x10, 0x968c); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++} ++ ++static void mt7981_phy_finetune(struct phy_device *phydev) ++{ ++ u16 val[8] = { 0x01ce, 0x01c1, ++ 0x020f, 0x0202, ++ 0x03d0, 0x03c0, ++ 0x0013, 0x0005 }; ++ int i, k; ++ ++ /* 100M eye finetune: ++ * Keep middle level of TX MLT3 shapper as default. ++ * Only change TX MLT3 overshoot level here. ++ */ ++ for (k = 0, i = 1; i < 12; i++) { ++ if (i % 3 == 0) ++ continue; ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); ++ } ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* ResetSyncOffset = 6 */ ++ __phy_write(phydev, 0x11, 0x600); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8fc0); ++ ++ /* VgaDecRate = 1 */ ++ __phy_write(phydev, 0x11, 0x4c2a); ++ __phy_write(phydev, 0x12, 0x3e); ++ __phy_write(phydev, 0x10, 0x8fa4); ++ ++ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, ++ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 ++ */ ++ __phy_write(phydev, 0x11, 0xd10a); ++ __phy_write(phydev, 0x12, 0x34); ++ __phy_write(phydev, 0x10, 0x8f82); ++ ++ /* VcoSlicerThreshBitsHigh */ ++ __phy_write(phydev, 0x11, 0x5555); ++ __phy_write(phydev, 0x12, 0x55); ++ __phy_write(phydev, 0x10, 0x8ec0); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, ++ MTK_PHY_TR_OPEN_LOOP_EN_MASK | ++ MTK_PHY_LPF_X_AVERAGE_MASK, ++ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); ++ ++ /* rg_tr_lpf_cnt_val = 512 */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); ++ ++ /* IIR2 related */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); ++ ++ /* FFE peaking */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, ++ MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, ++ MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); ++ ++ /* Disable LDO pump */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); ++ /* Adjust LDO output voltage */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); ++} ++ ++static void mt7988_phy_finetune(struct phy_device *phydev) ++{ ++ u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, ++ 0x020d, 0x0206, 0x0384, 0x03d0, ++ 0x03c6, 0x030a, 0x0011, 0x0005 }; ++ int i; ++ ++ /* Set default MLT3 shaper first */ ++ for (i = 0; i < 12; i++) ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); ++ ++ /* TCT finetune */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* ResetSyncOffset = 5 */ ++ __phy_write(phydev, 0x11, 0x500); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8fc0); ++ ++ /* VgaDecRate is 1 at default on mt7988 */ ++ ++ /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7, ++ * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7 ++ */ ++ __phy_write(phydev, 0x11, 0xb90a); ++ __phy_write(phydev, 0x12, 0x6f); ++ __phy_write(phydev, 0x10, 0x8f82); ++ ++ /* RemAckCntLimitCtrl = 1 */ ++ __phy_write(phydev, 0x11, 0xfbba); ++ __phy_write(phydev, 0x12, 0xc3); ++ __phy_write(phydev, 0x10, 0x87f8); ++ ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, ++ MTK_PHY_TR_OPEN_LOOP_EN_MASK | ++ MTK_PHY_LPF_X_AVERAGE_MASK, ++ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); ++ ++ /* rg_tr_lpf_cnt_val = 1023 */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); ++} ++ ++static void mt798x_phy_eee(struct phy_device *phydev) ++{ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, ++ MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | ++ MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | ++ FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, ++ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ 0xff)); ++ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_TESTMUX_ADC_CTRL, ++ MTK_PHY_RG_TXEN_DIG_MASK); ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); ++ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, ++ MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | ++ MTK_PHY_LPI_SLV_SEND_TX_EN, ++ FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); ++ ++ /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, ++ MTK_PHY_LPI_TXPCS_LOC_RCV); ++ ++ /* This also fixes some IoT issues, such as CH340 */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, ++ MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, ++ FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | ++ FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, ++ MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, ++ FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, ++ 0x33) | ++ MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | ++ MTK_PHY_LPI_VCO_EEE_STG0_EN); ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, ++ MTK_PHY_EEE_WAKE_MAS_INT_DC | ++ MTK_PHY_EEE_WAKE_SLV_INT_DC); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, ++ MTK_PHY_SMI_DETCNT_MAX_MASK, ++ FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | ++ MTK_PHY_SMI_DET_MAX_EN); ++ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, ++ MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | ++ MTK_PHY_TREC_UPDATE_ENAB_CLR | ++ MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | ++ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* Regsigdet_sel_1000 = 0 */ ++ __phy_write(phydev, 0x11, 0xb); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9690); ++ ++ /* REG_EEE_st2TrKf1000 = 2 */ ++ __phy_write(phydev, 0x11, 0x114f); ++ __phy_write(phydev, 0x12, 0x2); ++ __phy_write(phydev, 0x10, 0x969a); ++ ++ /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ ++ __phy_write(phydev, 0x11, 0x3028); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x969e); ++ ++ /* RegEEE_slv_wake_int_timer_tar = 8 */ ++ __phy_write(phydev, 0x11, 0x5010); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96a0); ++ ++ /* RegEEE_trfreeze_timer2 = 586 */ ++ __phy_write(phydev, 0x11, 0x24a); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96a8); ++ ++ /* RegEEE100Stg1_tar = 16 */ ++ __phy_write(phydev, 0x11, 0x3210); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96b8); ++ ++ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ ++ __phy_write(phydev, 0x11, 0x1463); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x96ca); ++ ++ /* DfeTailEnableVgaThresh1000 = 27 */ ++ __phy_write(phydev, 0x11, 0x36); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8f80); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); ++ __phy_modify(phydev, MTK_PHY_LPI_REG_14, ++ MTK_PHY_LPI_WAKE_TIMER_1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); ++ ++ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, ++ FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, ++ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, ++ 0xff)); ++} ++ ++static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, ++ u8 start_pair, u8 end_pair) ++{ ++ u8 pair_n; ++ int ret; ++ ++ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { ++ /* TX_OFFSET & TX_AMP have no SW calibration. */ ++ switch (cal_item) { ++ case TX_VCM: ++ ret = tx_vcm_cal_sw(phydev, pair_n); ++ break; ++ default: ++ return -EINVAL; ++ } ++ if (ret) ++ return ret; ++ } ++ return 0; ++} ++ ++static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, ++ u8 start_pair, u8 end_pair, u32 *buf) ++{ ++ u8 pair_n; ++ int ret; ++ ++ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { ++ /* TX_VCM has no efuse calibration. */ ++ switch (cal_item) { ++ case REXT: ++ ret = rext_cal_efuse(phydev, buf); ++ break; ++ case TX_OFFSET: ++ ret = tx_offset_cal_efuse(phydev, buf); ++ break; ++ case TX_AMP: ++ ret = tx_amp_cal_efuse(phydev, buf); ++ break; ++ case TX_R50: ++ ret = tx_r50_cal_efuse(phydev, buf, pair_n); ++ break; ++ default: ++ return -EINVAL; ++ } ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, ++ enum CAL_MODE cal_mode, u8 start_pair, ++ u8 end_pair, u32 *buf) ++{ ++ int ret; ++ ++ switch (cal_mode) { ++ case EFUSE_M: ++ ret = cal_efuse(phydev, cal_item, start_pair, ++ end_pair, buf); ++ break; ++ case SW_M: ++ ret = cal_sw(phydev, cal_item, start_pair, end_pair); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (ret) { ++ phydev_err(phydev, "cal %d failed\n", cal_item); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++static int mt798x_phy_calibration(struct phy_device *phydev) ++{ ++ struct nvmem_cell *cell; ++ int ret = 0; ++ size_t len; ++ u32 *buf; ++ ++ cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); ++ if (IS_ERR(cell)) { ++ if (PTR_ERR(cell) == -EPROBE_DEFER) ++ return PTR_ERR(cell); ++ return 0; ++ } ++ ++ buf = (u32 *)nvmem_cell_read(cell, &len); ++ if (IS_ERR(buf)) ++ return PTR_ERR(buf); ++ nvmem_cell_put(cell); ++ ++ if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { ++ phydev_err(phydev, "invalid efuse data\n"); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); ++ if (ret) ++ goto out; ++ ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); ++ if (ret) ++ goto out; ++ ++out: ++ kfree(buf); ++ return ret; ++} ++ ++static int mt798x_phy_config_init(struct phy_device *phydev) ++{ ++ switch (phydev->drv->phy_id) { ++ case MTK_GPHY_ID_MT7981: ++ mt7981_phy_finetune(phydev); ++ break; ++ case MTK_GPHY_ID_MT7988: ++ mt7988_phy_finetune(phydev); ++ break; ++ } ++ ++ mt798x_phy_common_finetune(phydev); ++ mt798x_phy_eee(phydev); ++ ++ return mt798x_phy_calibration(phydev); ++} ++ ++static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index, ++ bool on) ++{ ++ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); ++ struct mtk_socphy_priv *priv = phydev->priv; ++ bool changed; ++ ++ if (on) ++ changed = !test_and_set_bit(bit_on, &priv->led_state); ++ else ++ changed = !!test_and_clear_bit(bit_on, &priv->led_state); ++ ++ changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + ++ (index ? 16 : 0), &priv->led_state); ++ if (changed) ++ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_ON_CTRL : ++ MTK_PHY_LED0_ON_CTRL, ++ MTK_PHY_LED_ON_MASK, ++ on ? MTK_PHY_LED_ON_FORCE_ON : 0); ++ else ++ return 0; ++} ++ ++static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, ++ bool blinking) ++{ ++ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + ++ (index ? 16 : 0); ++ struct mtk_socphy_priv *priv = phydev->priv; ++ bool changed; ++ ++ if (blinking) ++ changed = !test_and_set_bit(bit_blink, &priv->led_state); ++ else ++ changed = !!test_and_clear_bit(bit_blink, &priv->led_state); ++ ++ changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV + ++ (index ? 16 : 0), &priv->led_state); ++ if (changed) ++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_BLINK_CTRL : ++ MTK_PHY_LED0_BLINK_CTRL, ++ blinking ? ++ MTK_PHY_LED_BLINK_FORCE_BLINK : 0); ++ else ++ return 0; ++} ++ ++static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, ++ unsigned long *delay_on, ++ unsigned long *delay_off) ++{ ++ bool blinking = false; ++ int err = 0; ++ ++ if (index > 1) ++ return -EINVAL; ++ ++ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { ++ blinking = true; ++ *delay_on = 50; ++ *delay_off = 50; ++ } ++ ++ err = mt798x_phy_hw_led_blink_set(phydev, index, blinking); ++ if (err) ++ return err; ++ ++ return mt798x_phy_hw_led_on_set(phydev, index, false); ++} ++ ++static int mt798x_phy_led_brightness_set(struct phy_device *phydev, ++ u8 index, enum led_brightness value) ++{ ++ int err; ++ ++ err = mt798x_phy_hw_led_blink_set(phydev, index, false); ++ if (err) ++ return err; ++ ++ return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF)); ++} ++ ++static const unsigned long supported_triggers = ++ BIT(TRIGGER_NETDEV_FULL_DUPLEX) | ++ BIT(TRIGGER_NETDEV_HALF_DUPLEX) | ++ BIT(TRIGGER_NETDEV_LINK) | ++ BIT(TRIGGER_NETDEV_LINK_10) | ++ BIT(TRIGGER_NETDEV_LINK_100) | ++ BIT(TRIGGER_NETDEV_LINK_1000) | ++ BIT(TRIGGER_NETDEV_RX) | ++ BIT(TRIGGER_NETDEV_TX); ++ ++static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, ++ unsigned long rules) ++{ ++ if (index > 1) ++ return -EINVAL; ++ ++ /* All combinations of the supported triggers are allowed */ ++ if (rules & ~supported_triggers) ++ return -EOPNOTSUPP; ++ ++ return 0; ++}; ++ ++static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, ++ unsigned long *rules) ++{ ++ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + ++ (index ? 16 : 0); ++ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); ++ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); ++ struct mtk_socphy_priv *priv = phydev->priv; ++ int on, blink; ++ ++ if (index > 1) ++ return -EINVAL; ++ ++ on = phy_read_mmd(phydev, MDIO_MMD_VEND2, ++ index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); ++ ++ if (on < 0) ++ return -EIO; ++ ++ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, ++ index ? MTK_PHY_LED1_BLINK_CTRL : ++ MTK_PHY_LED0_BLINK_CTRL); ++ if (blink < 0) ++ return -EIO; ++ ++ if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | ++ MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) || ++ (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX))) ++ set_bit(bit_netdev, &priv->led_state); ++ else ++ clear_bit(bit_netdev, &priv->led_state); ++ ++ if (on & MTK_PHY_LED_ON_FORCE_ON) ++ set_bit(bit_on, &priv->led_state); ++ else ++ clear_bit(bit_on, &priv->led_state); ++ ++ if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) ++ set_bit(bit_blink, &priv->led_state); ++ else ++ clear_bit(bit_blink, &priv->led_state); ++ ++ if (!rules) ++ return 0; ++ ++ if (on & MTK_PHY_LED_ON_LINK) ++ *rules |= BIT(TRIGGER_NETDEV_LINK); ++ ++ if (on & MTK_PHY_LED_ON_LINK10) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_10); ++ ++ if (on & MTK_PHY_LED_ON_LINK100) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_100); ++ ++ if (on & MTK_PHY_LED_ON_LINK1000) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_1000); ++ ++ if (on & MTK_PHY_LED_ON_FDX) ++ *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); ++ ++ if (on & MTK_PHY_LED_ON_HDX) ++ *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); ++ ++ if (blink & MTK_PHY_LED_BLINK_RX) ++ *rules |= BIT(TRIGGER_NETDEV_RX); ++ ++ if (blink & MTK_PHY_LED_BLINK_TX) ++ *rules |= BIT(TRIGGER_NETDEV_TX); ++ ++ return 0; ++}; ++ ++static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, ++ unsigned long rules) ++{ ++ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); ++ struct mtk_socphy_priv *priv = phydev->priv; ++ u16 on = 0, blink = 0; ++ int ret; ++ ++ if (index > 1) ++ return -EINVAL; ++ ++ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) ++ on |= MTK_PHY_LED_ON_FDX; ++ ++ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) ++ on |= MTK_PHY_LED_ON_HDX; ++ ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) ++ on |= MTK_PHY_LED_ON_LINK10; ++ ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) ++ on |= MTK_PHY_LED_ON_LINK100; ++ ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) ++ on |= MTK_PHY_LED_ON_LINK1000; ++ ++ if (rules & BIT(TRIGGER_NETDEV_RX)) { ++ blink |= (on & MTK_PHY_LED_ON_LINK) ? ++ (((on & MTK_PHY_LED_ON_LINK10) ? ++ MTK_PHY_LED_BLINK_10RX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK100) ? ++ MTK_PHY_LED_BLINK_100RX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK1000) ? ++ MTK_PHY_LED_BLINK_1000RX : 0)) : ++ MTK_PHY_LED_BLINK_RX; ++ } ++ ++ if (rules & BIT(TRIGGER_NETDEV_TX)) { ++ blink |= (on & MTK_PHY_LED_ON_LINK) ? ++ (((on & MTK_PHY_LED_ON_LINK10) ? ++ MTK_PHY_LED_BLINK_10TX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK100) ? ++ MTK_PHY_LED_BLINK_100TX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK1000) ? ++ MTK_PHY_LED_BLINK_1000TX : 0)) : ++ MTK_PHY_LED_BLINK_TX; ++ } ++ ++ if (blink || on) ++ set_bit(bit_netdev, &priv->led_state); ++ else ++ clear_bit(bit_netdev, &priv->led_state); ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_ON_CTRL : ++ MTK_PHY_LED0_ON_CTRL, ++ MTK_PHY_LED_ON_FDX | ++ MTK_PHY_LED_ON_HDX | ++ MTK_PHY_LED_ON_LINK, ++ on); ++ ++ if (ret) ++ return ret; ++ ++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_BLINK_CTRL : ++ MTK_PHY_LED0_BLINK_CTRL, blink); ++}; ++ ++static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) ++{ ++ struct mtk_socphy_shared *priv = phydev->shared->priv; ++ u32 polarities; ++ ++ if (led_num == 0) ++ polarities = ~(priv->boottrap); ++ else ++ polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; ++ ++ if (polarities & BIT(phydev->mdio.addr)) ++ return true; ++ ++ return false; ++} ++ ++static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) ++{ ++ struct pinctrl *pinctrl; ++ int index; ++ ++ /* Setup LED polarity according to bootstrap use of LED pins */ ++ for (index = 0; index < 2; ++index) ++ phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, ++ MTK_PHY_LED_ON_POLARITY, ++ mt7988_phy_led_get_polarity(phydev, index) ? ++ MTK_PHY_LED_ON_POLARITY : 0); ++ ++ /* Only now setup pinctrl to avoid bogus blinking */ ++ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); ++ if (IS_ERR(pinctrl)) ++ dev_err(&phydev->mdio.bus->dev, ++ "Failed to setup PHY LED pinctrl\n"); ++ ++ return 0; ++} ++ ++static int mt7988_phy_probe_shared(struct phy_device *phydev) ++{ ++ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); ++ struct mtk_socphy_shared *shared = phydev->shared->priv; ++ struct regmap *regmap; ++ u32 reg; ++ int ret; ++ ++ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, ++ * LED_C and LED_D respectively. At the same time those pins are used to ++ * bootstrap configuration of the reference clock source (LED_A), ++ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). ++ * In practice this is done using a LED and a resistor pulling the pin ++ * either to GND or to VIO. ++ * The detected value at boot time is accessible at run-time using the ++ * TPBANK0 register located in the gpio base of the pinctrl, in order ++ * to read it here it needs to be referenced by a phandle called ++ * 'mediatek,pio' in the MDIO bus hosting the PHY. ++ * The 4 bits in TPBANK0 are kept as package shared data and are used to ++ * set LED polarity for each of the LED0. ++ */ ++ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); ++ if (ret) ++ return ret; ++ ++ shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); ++ ++ return 0; ++} ++ ++static void mt798x_phy_leds_state_init(struct phy_device *phydev) ++{ ++ int i; ++ ++ for (i = 0; i < 2; ++i) ++ mt798x_phy_led_hw_control_get(phydev, i, NULL); ++} ++ ++static int mt7988_phy_probe(struct phy_device *phydev) ++{ ++ struct mtk_socphy_shared *shared; ++ struct mtk_socphy_priv *priv; ++ int err; ++ ++ if (phydev->mdio.addr > 3) ++ return -EINVAL; ++ ++ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, ++ sizeof(struct mtk_socphy_shared)); ++ if (err) ++ return err; ++ ++ if (phy_package_probe_once(phydev)) { ++ err = mt7988_phy_probe_shared(phydev); ++ if (err) ++ return err; ++ } ++ ++ shared = phydev->shared->priv; ++ priv = &shared->priv[phydev->mdio.addr]; ++ ++ phydev->priv = priv; ++ ++ mt798x_phy_leds_state_init(phydev); ++ ++ err = mt7988_phy_fix_leds_polarities(phydev); ++ if (err) ++ return err; ++ ++ /* Disable TX power saving at probing to: ++ * 1. Meet common mode compliance test criteria ++ * 2. Make sure that TX-VCM calibration works fine ++ */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, ++ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); ++ ++ return mt798x_phy_calibration(phydev); ++} ++ ++static int mt7981_phy_probe(struct phy_device *phydev) ++{ ++ struct mtk_socphy_priv *priv; ++ ++ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ phydev->priv = priv; ++ ++ mt798x_phy_leds_state_init(phydev); ++ ++ return mt798x_phy_calibration(phydev); ++} ++ ++static struct phy_driver mtk_socphy_driver[] = { ++ { ++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), ++ .name = "MediaTek MT7981 PHY", ++ .config_init = mt798x_phy_config_init, ++ .config_intr = genphy_no_config_intr, ++ .handle_interrupt = genphy_handle_interrupt_no_ack, ++ .probe = mt7981_phy_probe, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_page = mtk_socphy_read_page, ++ .write_page = mtk_socphy_write_page, ++ .led_blink_set = mt798x_phy_led_blink_set, ++ .led_brightness_set = mt798x_phy_led_brightness_set, ++ .led_hw_is_supported = mt798x_phy_led_hw_is_supported, ++ .led_hw_control_set = mt798x_phy_led_hw_control_set, ++ .led_hw_control_get = mt798x_phy_led_hw_control_get, ++ }, ++ { ++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), ++ .name = "MediaTek MT7988 PHY", ++ .config_init = mt798x_phy_config_init, ++ .config_intr = genphy_no_config_intr, ++ .handle_interrupt = genphy_handle_interrupt_no_ack, ++ .probe = mt7988_phy_probe, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_page = mtk_socphy_read_page, ++ .write_page = mtk_socphy_write_page, ++ .led_blink_set = mt798x_phy_led_blink_set, ++ .led_brightness_set = mt798x_phy_led_brightness_set, ++ .led_hw_is_supported = mt798x_phy_led_hw_is_supported, ++ .led_hw_control_set = mt798x_phy_led_hw_control_set, ++ .led_hw_control_get = mt798x_phy_led_hw_control_get, ++ }, ++}; ++ ++module_phy_driver(mtk_socphy_driver); ++ ++static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { ++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, ++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, ++ { } ++}; ++ ++MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); ++MODULE_AUTHOR("Daniel Golle "); ++MODULE_AUTHOR("SkyLake Huang "); ++MODULE_LICENSE("GPL"); ++ ++MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); +--- /dev/null ++++ b/drivers/net/phy/mediatek/mtk-ge.c +@@ -0,0 +1,111 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++#include ++#include ++#include ++ ++#define MTK_EXT_PAGE_ACCESS 0x1f ++#define MTK_PHY_PAGE_STANDARD 0x0000 ++#define MTK_PHY_PAGE_EXTENDED 0x0001 ++#define MTK_PHY_PAGE_EXTENDED_2 0x0002 ++#define MTK_PHY_PAGE_EXTENDED_3 0x0003 ++#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 ++#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 ++ ++static int mtk_gephy_read_page(struct phy_device *phydev) ++{ ++ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); ++} ++ ++static int mtk_gephy_write_page(struct phy_device *phydev, int page) ++{ ++ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); ++} ++ ++static void mtk_gephy_config_init(struct phy_device *phydev) ++{ ++ /* Enable HW auto downshift */ ++ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); ++ ++ /* Increase SlvDPSready time */ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ __phy_write(phydev, 0x10, 0xafae); ++ __phy_write(phydev, 0x12, 0x2f); ++ __phy_write(phydev, 0x10, 0x8fae); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ /* Adjust 100_mse_threshold */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); ++ ++ /* Disable mcc */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); ++} ++ ++static int mt7530_phy_config_init(struct phy_device *phydev) ++{ ++ mtk_gephy_config_init(phydev); ++ ++ /* Increase post_update_timer */ ++ phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b); ++ ++ return 0; ++} ++ ++static int mt7531_phy_config_init(struct phy_device *phydev) ++{ ++ mtk_gephy_config_init(phydev); ++ ++ /* PHY link down power saving enable */ ++ phy_set_bits(phydev, 0x17, BIT(4)); ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); ++ ++ /* Set TX Pair delay selection */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); ++ ++ return 0; ++} ++ ++static struct phy_driver mtk_gephy_driver[] = { ++ { ++ PHY_ID_MATCH_EXACT(0x03a29412), ++ .name = "MediaTek MT7530 PHY", ++ .config_init = mt7530_phy_config_init, ++ /* Interrupts are handled by the switch, not the PHY ++ * itself. ++ */ ++ .config_intr = genphy_no_config_intr, ++ .handle_interrupt = genphy_handle_interrupt_no_ack, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_page = mtk_gephy_read_page, ++ .write_page = mtk_gephy_write_page, ++ }, ++ { ++ PHY_ID_MATCH_EXACT(0x03a29441), ++ .name = "MediaTek MT7531 PHY", ++ .config_init = mt7531_phy_config_init, ++ /* Interrupts are handled by the switch, not the PHY ++ * itself. ++ */ ++ .config_intr = genphy_no_config_intr, ++ .handle_interrupt = genphy_handle_interrupt_no_ack, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_page = mtk_gephy_read_page, ++ .write_page = mtk_gephy_write_page, ++ }, ++}; ++ ++module_phy_driver(mtk_gephy_driver); ++ ++static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { ++ { PHY_ID_MATCH_EXACT(0x03a29441) }, ++ { PHY_ID_MATCH_EXACT(0x03a29412) }, ++ { } ++}; ++ ++MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver"); ++MODULE_AUTHOR("DENG, Qingfang "); ++MODULE_LICENSE("GPL"); ++ ++MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl); diff --git a/target/linux/generic/backport-6.12/724-v6.13-net-phy-mediatek-Move-LED-helper-functions-into-mtk-.patch b/target/linux/generic/backport-6.12/724-v6.13-net-phy-mediatek-Move-LED-helper-functions-into-mtk-.patch new file mode 100644 index 0000000000..63407ac55c --- /dev/null +++ b/target/linux/generic/backport-6.12/724-v6.13-net-phy-mediatek-Move-LED-helper-functions-into-mtk-.patch @@ -0,0 +1,774 @@ +From 71d88c7409b91c853d7f9c933f5e27933d656e5e Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Sat, 9 Nov 2024 00:34:52 +0800 +Subject: [PATCH 05/20] net: phy: mediatek: Move LED helper functions into mtk + phy lib + +This patch creates mtk-phy-lib.c & mtk-phy.h and integrates mtk-ge-soc.c's +LED helper functions so that we can use those helper functions in other +MTK's ethernet phy driver. + +Reviewed-by: Andrew Lunn +Signed-off-by: SkyLake.Huang +Signed-off-by: David S. Miller +--- + MAINTAINERS | 2 + + drivers/net/phy/mediatek/Kconfig | 4 + + drivers/net/phy/mediatek/Makefile | 1 + + drivers/net/phy/mediatek/mtk-ge-soc.c | 280 +++---------------------- + drivers/net/phy/mediatek/mtk-phy-lib.c | 254 ++++++++++++++++++++++ + drivers/net/phy/mediatek/mtk.h | 86 ++++++++ + 6 files changed, 372 insertions(+), 255 deletions(-) + create mode 100644 drivers/net/phy/mediatek/mtk-phy-lib.c + create mode 100644 drivers/net/phy/mediatek/mtk.h + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -14428,7 +14428,9 @@ M: SkyLake Huang + #include + ++#include "mtk.h" ++ + #define MTK_GPHY_ID_MT7981 0x03a29461 + #define MTK_GPHY_ID_MT7988 0x03a29481 + +@@ -210,41 +212,6 @@ + #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 + + /* Registers on MDIO_MMD_VEND2 */ +-#define MTK_PHY_LED0_ON_CTRL 0x24 +-#define MTK_PHY_LED1_ON_CTRL 0x26 +-#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) +-#define MTK_PHY_LED_ON_LINK1000 BIT(0) +-#define MTK_PHY_LED_ON_LINK100 BIT(1) +-#define MTK_PHY_LED_ON_LINK10 BIT(2) +-#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\ +- MTK_PHY_LED_ON_LINK100 |\ +- MTK_PHY_LED_ON_LINK1000) +-#define MTK_PHY_LED_ON_LINKDOWN BIT(3) +-#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ +-#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ +-#define MTK_PHY_LED_ON_FORCE_ON BIT(6) +-#define MTK_PHY_LED_ON_POLARITY BIT(14) +-#define MTK_PHY_LED_ON_ENABLE BIT(15) +- +-#define MTK_PHY_LED0_BLINK_CTRL 0x25 +-#define MTK_PHY_LED1_BLINK_CTRL 0x27 +-#define MTK_PHY_LED_BLINK_1000TX BIT(0) +-#define MTK_PHY_LED_BLINK_1000RX BIT(1) +-#define MTK_PHY_LED_BLINK_100TX BIT(2) +-#define MTK_PHY_LED_BLINK_100RX BIT(3) +-#define MTK_PHY_LED_BLINK_10TX BIT(4) +-#define MTK_PHY_LED_BLINK_10RX BIT(5) +-#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\ +- MTK_PHY_LED_BLINK_100RX |\ +- MTK_PHY_LED_BLINK_1000RX) +-#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\ +- MTK_PHY_LED_BLINK_100TX |\ +- MTK_PHY_LED_BLINK_1000TX) +-#define MTK_PHY_LED_BLINK_COLLISION BIT(6) +-#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) +-#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) +-#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) +- + #define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) + + #define MTK_PHY_RG_BG_RASEL 0x115 +@@ -299,14 +266,6 @@ enum CAL_MODE { + SW_M + }; + +-#define MTK_PHY_LED_STATE_FORCE_ON 0 +-#define MTK_PHY_LED_STATE_FORCE_BLINK 1 +-#define MTK_PHY_LED_STATE_NETDEV 2 +- +-struct mtk_socphy_priv { +- unsigned long led_state; +-}; +- + struct mtk_socphy_shared { + u32 boottrap; + struct mtk_socphy_priv priv[4]; +@@ -1172,76 +1131,23 @@ static int mt798x_phy_config_init(struct + return mt798x_phy_calibration(phydev); + } + +-static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index, +- bool on) +-{ +- unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); +- struct mtk_socphy_priv *priv = phydev->priv; +- bool changed; +- +- if (on) +- changed = !test_and_set_bit(bit_on, &priv->led_state); +- else +- changed = !!test_and_clear_bit(bit_on, &priv->led_state); +- +- changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + +- (index ? 16 : 0), &priv->led_state); +- if (changed) +- return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? +- MTK_PHY_LED1_ON_CTRL : +- MTK_PHY_LED0_ON_CTRL, +- MTK_PHY_LED_ON_MASK, +- on ? MTK_PHY_LED_ON_FORCE_ON : 0); +- else +- return 0; +-} +- +-static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, +- bool blinking) +-{ +- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + +- (index ? 16 : 0); +- struct mtk_socphy_priv *priv = phydev->priv; +- bool changed; +- +- if (blinking) +- changed = !test_and_set_bit(bit_blink, &priv->led_state); +- else +- changed = !!test_and_clear_bit(bit_blink, &priv->led_state); +- +- changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV + +- (index ? 16 : 0), &priv->led_state); +- if (changed) +- return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? +- MTK_PHY_LED1_BLINK_CTRL : +- MTK_PHY_LED0_BLINK_CTRL, +- blinking ? +- MTK_PHY_LED_BLINK_FORCE_BLINK : 0); +- else +- return 0; +-} +- + static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, + unsigned long *delay_on, + unsigned long *delay_off) + { + bool blinking = false; +- int err = 0; +- +- if (index > 1) +- return -EINVAL; ++ int err; + +- if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { +- blinking = true; +- *delay_on = 50; +- *delay_off = 50; +- } ++ err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking); ++ if (err < 0) ++ return err; + +- err = mt798x_phy_hw_led_blink_set(phydev, index, blinking); ++ err = mtk_phy_hw_led_blink_set(phydev, index, blinking); + if (err) + return err; + +- return mt798x_phy_hw_led_on_set(phydev, index, false); ++ return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, ++ false); + } + + static int mt798x_phy_led_brightness_set(struct phy_device *phydev, +@@ -1249,11 +1155,12 @@ static int mt798x_phy_led_brightness_set + { + int err; + +- err = mt798x_phy_hw_led_blink_set(phydev, index, false); ++ err = mtk_phy_hw_led_blink_set(phydev, index, false); + if (err) + return err; + +- return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF)); ++ return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, ++ (value != LED_OFF)); + } + + static const unsigned long supported_triggers = +@@ -1269,155 +1176,26 @@ static const unsigned long supported_tri + static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules) + { +- if (index > 1) +- return -EINVAL; +- +- /* All combinations of the supported triggers are allowed */ +- if (rules & ~supported_triggers) +- return -EOPNOTSUPP; +- +- return 0; +-}; ++ return mtk_phy_led_hw_is_supported(phydev, index, rules, ++ supported_triggers); ++} + + static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, + unsigned long *rules) + { +- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + +- (index ? 16 : 0); +- unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); +- unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); +- struct mtk_socphy_priv *priv = phydev->priv; +- int on, blink; +- +- if (index > 1) +- return -EINVAL; +- +- on = phy_read_mmd(phydev, MDIO_MMD_VEND2, +- index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); +- +- if (on < 0) +- return -EIO; +- +- blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, +- index ? MTK_PHY_LED1_BLINK_CTRL : +- MTK_PHY_LED0_BLINK_CTRL); +- if (blink < 0) +- return -EIO; +- +- if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | +- MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) || +- (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX))) +- set_bit(bit_netdev, &priv->led_state); +- else +- clear_bit(bit_netdev, &priv->led_state); +- +- if (on & MTK_PHY_LED_ON_FORCE_ON) +- set_bit(bit_on, &priv->led_state); +- else +- clear_bit(bit_on, &priv->led_state); +- +- if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) +- set_bit(bit_blink, &priv->led_state); +- else +- clear_bit(bit_blink, &priv->led_state); +- +- if (!rules) +- return 0; +- +- if (on & MTK_PHY_LED_ON_LINK) +- *rules |= BIT(TRIGGER_NETDEV_LINK); +- +- if (on & MTK_PHY_LED_ON_LINK10) +- *rules |= BIT(TRIGGER_NETDEV_LINK_10); +- +- if (on & MTK_PHY_LED_ON_LINK100) +- *rules |= BIT(TRIGGER_NETDEV_LINK_100); +- +- if (on & MTK_PHY_LED_ON_LINK1000) +- *rules |= BIT(TRIGGER_NETDEV_LINK_1000); +- +- if (on & MTK_PHY_LED_ON_FDX) +- *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); +- +- if (on & MTK_PHY_LED_ON_HDX) +- *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); +- +- if (blink & MTK_PHY_LED_BLINK_RX) +- *rules |= BIT(TRIGGER_NETDEV_RX); +- +- if (blink & MTK_PHY_LED_BLINK_TX) +- *rules |= BIT(TRIGGER_NETDEV_TX); +- +- return 0; ++ return mtk_phy_led_hw_ctrl_get(phydev, index, rules, ++ MTK_GPHY_LED_ON_SET, ++ MTK_GPHY_LED_RX_BLINK_SET, ++ MTK_GPHY_LED_TX_BLINK_SET); + }; + + static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, + unsigned long rules) + { +- unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); +- struct mtk_socphy_priv *priv = phydev->priv; +- u16 on = 0, blink = 0; +- int ret; +- +- if (index > 1) +- return -EINVAL; +- +- if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) +- on |= MTK_PHY_LED_ON_FDX; +- +- if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) +- on |= MTK_PHY_LED_ON_HDX; +- +- if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) +- on |= MTK_PHY_LED_ON_LINK10; +- +- if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) +- on |= MTK_PHY_LED_ON_LINK100; +- +- if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) +- on |= MTK_PHY_LED_ON_LINK1000; +- +- if (rules & BIT(TRIGGER_NETDEV_RX)) { +- blink |= (on & MTK_PHY_LED_ON_LINK) ? +- (((on & MTK_PHY_LED_ON_LINK10) ? +- MTK_PHY_LED_BLINK_10RX : 0) | +- ((on & MTK_PHY_LED_ON_LINK100) ? +- MTK_PHY_LED_BLINK_100RX : 0) | +- ((on & MTK_PHY_LED_ON_LINK1000) ? +- MTK_PHY_LED_BLINK_1000RX : 0)) : +- MTK_PHY_LED_BLINK_RX; +- } +- +- if (rules & BIT(TRIGGER_NETDEV_TX)) { +- blink |= (on & MTK_PHY_LED_ON_LINK) ? +- (((on & MTK_PHY_LED_ON_LINK10) ? +- MTK_PHY_LED_BLINK_10TX : 0) | +- ((on & MTK_PHY_LED_ON_LINK100) ? +- MTK_PHY_LED_BLINK_100TX : 0) | +- ((on & MTK_PHY_LED_ON_LINK1000) ? +- MTK_PHY_LED_BLINK_1000TX : 0)) : +- MTK_PHY_LED_BLINK_TX; +- } +- +- if (blink || on) +- set_bit(bit_netdev, &priv->led_state); +- else +- clear_bit(bit_netdev, &priv->led_state); +- +- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? +- MTK_PHY_LED1_ON_CTRL : +- MTK_PHY_LED0_ON_CTRL, +- MTK_PHY_LED_ON_FDX | +- MTK_PHY_LED_ON_HDX | +- MTK_PHY_LED_ON_LINK, +- on); +- +- if (ret) +- return ret; +- +- return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? +- MTK_PHY_LED1_BLINK_CTRL : +- MTK_PHY_LED0_BLINK_CTRL, blink); ++ return mtk_phy_led_hw_ctrl_set(phydev, index, rules, ++ MTK_GPHY_LED_ON_SET, ++ MTK_GPHY_LED_RX_BLINK_SET, ++ MTK_GPHY_LED_TX_BLINK_SET); + }; + + static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) +@@ -1492,14 +1270,6 @@ static int mt7988_phy_probe_shared(struc + return 0; + } + +-static void mt798x_phy_leds_state_init(struct phy_device *phydev) +-{ +- int i; +- +- for (i = 0; i < 2; ++i) +- mt798x_phy_led_hw_control_get(phydev, i, NULL); +-} +- + static int mt7988_phy_probe(struct phy_device *phydev) + { + struct mtk_socphy_shared *shared; +@@ -1525,7 +1295,7 @@ static int mt7988_phy_probe(struct phy_d + + phydev->priv = priv; + +- mt798x_phy_leds_state_init(phydev); ++ mtk_phy_leds_state_init(phydev); + + err = mt7988_phy_fix_leds_polarities(phydev); + if (err) +@@ -1552,7 +1322,7 @@ static int mt7981_phy_probe(struct phy_d + + phydev->priv = priv; + +- mt798x_phy_leds_state_init(phydev); ++ mtk_phy_leds_state_init(phydev); + + return mt798x_phy_calibration(phydev); + } +--- /dev/null ++++ b/drivers/net/phy/mediatek/mtk-phy-lib.c +@@ -0,0 +1,254 @@ ++// SPDX-License-Identifier: GPL-2.0 ++#include ++#include ++ ++#include ++ ++#include "mtk.h" ++ ++int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, ++ unsigned long rules, ++ unsigned long supported_triggers) ++{ ++ if (index > 1) ++ return -EINVAL; ++ ++ /* All combinations of the supported triggers are allowed */ ++ if (rules & ~supported_triggers) ++ return -EOPNOTSUPP; ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(mtk_phy_led_hw_is_supported); ++ ++int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index, ++ unsigned long *rules, u16 on_set, ++ u16 rx_blink_set, u16 tx_blink_set) ++{ ++ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + ++ (index ? 16 : 0); ++ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); ++ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); ++ struct mtk_socphy_priv *priv = phydev->priv; ++ int on, blink; ++ ++ if (index > 1) ++ return -EINVAL; ++ ++ on = phy_read_mmd(phydev, MDIO_MMD_VEND2, ++ index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); ++ ++ if (on < 0) ++ return -EIO; ++ ++ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, ++ index ? MTK_PHY_LED1_BLINK_CTRL : ++ MTK_PHY_LED0_BLINK_CTRL); ++ if (blink < 0) ++ return -EIO; ++ ++ if ((on & (on_set | MTK_PHY_LED_ON_FDX | ++ MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) || ++ (blink & (rx_blink_set | tx_blink_set))) ++ set_bit(bit_netdev, &priv->led_state); ++ else ++ clear_bit(bit_netdev, &priv->led_state); ++ ++ if (on & MTK_PHY_LED_ON_FORCE_ON) ++ set_bit(bit_on, &priv->led_state); ++ else ++ clear_bit(bit_on, &priv->led_state); ++ ++ if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) ++ set_bit(bit_blink, &priv->led_state); ++ else ++ clear_bit(bit_blink, &priv->led_state); ++ ++ if (!rules) ++ return 0; ++ ++ if (on & on_set) ++ *rules |= BIT(TRIGGER_NETDEV_LINK); ++ ++ if (on & MTK_PHY_LED_ON_LINK10) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_10); ++ ++ if (on & MTK_PHY_LED_ON_LINK100) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_100); ++ ++ if (on & MTK_PHY_LED_ON_LINK1000) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_1000); ++ ++ if (on & MTK_PHY_LED_ON_LINK2500) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_2500); ++ ++ if (on & MTK_PHY_LED_ON_FDX) ++ *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); ++ ++ if (on & MTK_PHY_LED_ON_HDX) ++ *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); ++ ++ if (blink & rx_blink_set) ++ *rules |= BIT(TRIGGER_NETDEV_RX); ++ ++ if (blink & tx_blink_set) ++ *rules |= BIT(TRIGGER_NETDEV_TX); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_get); ++ ++int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index, ++ unsigned long rules, u16 on_set, ++ u16 rx_blink_set, u16 tx_blink_set) ++{ ++ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); ++ struct mtk_socphy_priv *priv = phydev->priv; ++ u16 on = 0, blink = 0; ++ int ret; ++ ++ if (index > 1) ++ return -EINVAL; ++ ++ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) ++ on |= MTK_PHY_LED_ON_FDX; ++ ++ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) ++ on |= MTK_PHY_LED_ON_HDX; ++ ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) ++ on |= MTK_PHY_LED_ON_LINK10; ++ ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) ++ on |= MTK_PHY_LED_ON_LINK100; ++ ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) ++ on |= MTK_PHY_LED_ON_LINK1000; ++ ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) ++ on |= MTK_PHY_LED_ON_LINK2500; ++ ++ if (rules & BIT(TRIGGER_NETDEV_RX)) { ++ blink |= (on & on_set) ? ++ (((on & MTK_PHY_LED_ON_LINK10) ? ++ MTK_PHY_LED_BLINK_10RX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK100) ? ++ MTK_PHY_LED_BLINK_100RX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK1000) ? ++ MTK_PHY_LED_BLINK_1000RX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK2500) ? ++ MTK_PHY_LED_BLINK_2500RX : 0)) : ++ rx_blink_set; ++ } ++ ++ if (rules & BIT(TRIGGER_NETDEV_TX)) { ++ blink |= (on & on_set) ? ++ (((on & MTK_PHY_LED_ON_LINK10) ? ++ MTK_PHY_LED_BLINK_10TX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK100) ? ++ MTK_PHY_LED_BLINK_100TX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK1000) ? ++ MTK_PHY_LED_BLINK_1000TX : 0) | ++ ((on & MTK_PHY_LED_ON_LINK2500) ? ++ MTK_PHY_LED_BLINK_2500TX : 0)) : ++ tx_blink_set; ++ } ++ ++ if (blink || on) ++ set_bit(bit_netdev, &priv->led_state); ++ else ++ clear_bit(bit_netdev, &priv->led_state); ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, ++ MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX | on_set, ++ on); ++ ++ if (ret) ++ return ret; ++ ++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_BLINK_CTRL : ++ MTK_PHY_LED0_BLINK_CTRL, blink); ++} ++EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_set); ++ ++int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on, ++ unsigned long *delay_off, bool *blinking) ++{ ++ if (index > 1) ++ return -EINVAL; ++ ++ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { ++ *blinking = true; ++ *delay_on = 50; ++ *delay_off = 50; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(mtk_phy_led_num_dly_cfg); ++ ++int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index, ++ u16 led_on_mask, bool on) ++{ ++ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); ++ struct mtk_socphy_priv *priv = phydev->priv; ++ bool changed; ++ ++ if (on) ++ changed = !test_and_set_bit(bit_on, &priv->led_state); ++ else ++ changed = !!test_and_clear_bit(bit_on, &priv->led_state); ++ ++ changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + ++ (index ? 16 : 0), &priv->led_state); ++ if (changed) ++ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_ON_CTRL : ++ MTK_PHY_LED0_ON_CTRL, ++ led_on_mask, ++ on ? MTK_PHY_LED_ON_FORCE_ON : 0); ++ else ++ return 0; ++} ++EXPORT_SYMBOL_GPL(mtk_phy_hw_led_on_set); ++ ++int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, bool blinking) ++{ ++ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + ++ (index ? 16 : 0); ++ struct mtk_socphy_priv *priv = phydev->priv; ++ bool changed; ++ ++ if (blinking) ++ changed = !test_and_set_bit(bit_blink, &priv->led_state); ++ else ++ changed = !!test_and_clear_bit(bit_blink, &priv->led_state); ++ ++ changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV + ++ (index ? 16 : 0), &priv->led_state); ++ if (changed) ++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_BLINK_CTRL : ++ MTK_PHY_LED0_BLINK_CTRL, ++ blinking ? ++ MTK_PHY_LED_BLINK_FORCE_BLINK : 0); ++ else ++ return 0; ++} ++EXPORT_SYMBOL_GPL(mtk_phy_hw_led_blink_set); ++ ++void mtk_phy_leds_state_init(struct phy_device *phydev) ++{ ++ int i; ++ ++ for (i = 0; i < 2; ++i) ++ phydev->drv->led_hw_control_get(phydev, i, NULL); ++} ++EXPORT_SYMBOL_GPL(mtk_phy_leds_state_init); ++ ++MODULE_DESCRIPTION("MediaTek Ethernet PHY driver common"); ++MODULE_AUTHOR("Sky Huang "); ++MODULE_AUTHOR("Daniel Golle "); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/drivers/net/phy/mediatek/mtk.h +@@ -0,0 +1,86 @@ ++/* SPDX-License-Identifier: GPL-2.0 ++ * ++ * Common definition for Mediatek Ethernet PHYs ++ * Author: SkyLake Huang ++ * Copyright (c) 2024 MediaTek Inc. ++ */ ++ ++#ifndef _MTK_EPHY_H_ ++#define _MTK_EPHY_H_ ++ ++#define MTK_EXT_PAGE_ACCESS 0x1f ++ ++/* Registers on MDIO_MMD_VEND2 */ ++#define MTK_PHY_LED0_ON_CTRL 0x24 ++#define MTK_PHY_LED1_ON_CTRL 0x26 ++#define MTK_GPHY_LED_ON_MASK GENMASK(6, 0) ++#define MTK_2P5GPHY_LED_ON_MASK GENMASK(7, 0) ++#define MTK_PHY_LED_ON_LINK1000 BIT(0) ++#define MTK_PHY_LED_ON_LINK100 BIT(1) ++#define MTK_PHY_LED_ON_LINK10 BIT(2) ++#define MTK_PHY_LED_ON_LINKDOWN BIT(3) ++#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ ++#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ ++#define MTK_PHY_LED_ON_FORCE_ON BIT(6) ++#define MTK_PHY_LED_ON_LINK2500 BIT(7) ++#define MTK_PHY_LED_ON_POLARITY BIT(14) ++#define MTK_PHY_LED_ON_ENABLE BIT(15) ++ ++#define MTK_PHY_LED0_BLINK_CTRL 0x25 ++#define MTK_PHY_LED1_BLINK_CTRL 0x27 ++#define MTK_PHY_LED_BLINK_1000TX BIT(0) ++#define MTK_PHY_LED_BLINK_1000RX BIT(1) ++#define MTK_PHY_LED_BLINK_100TX BIT(2) ++#define MTK_PHY_LED_BLINK_100RX BIT(3) ++#define MTK_PHY_LED_BLINK_10TX BIT(4) ++#define MTK_PHY_LED_BLINK_10RX BIT(5) ++#define MTK_PHY_LED_BLINK_COLLISION BIT(6) ++#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) ++#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) ++#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) ++#define MTK_PHY_LED_BLINK_2500TX BIT(10) ++#define MTK_PHY_LED_BLINK_2500RX BIT(11) ++ ++#define MTK_GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK1000 | \ ++ MTK_PHY_LED_ON_LINK100 | \ ++ MTK_PHY_LED_ON_LINK10) ++#define MTK_GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \ ++ MTK_PHY_LED_BLINK_100RX | \ ++ MTK_PHY_LED_BLINK_10RX) ++#define MTK_GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \ ++ MTK_PHY_LED_BLINK_100RX | \ ++ MTK_PHY_LED_BLINK_10RX) ++ ++#define MTK_2P5GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK2500 | \ ++ MTK_GPHY_LED_ON_SET) ++#define MTK_2P5GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \ ++ MTK_GPHY_LED_RX_BLINK_SET) ++#define MTK_2P5GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \ ++ MTK_GPHY_LED_TX_BLINK_SET) ++ ++#define MTK_PHY_LED_STATE_FORCE_ON 0 ++#define MTK_PHY_LED_STATE_FORCE_BLINK 1 ++#define MTK_PHY_LED_STATE_NETDEV 2 ++ ++struct mtk_socphy_priv { ++ unsigned long led_state; ++}; ++ ++int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, ++ unsigned long rules, ++ unsigned long supported_triggers); ++int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index, ++ unsigned long rules, u16 on_set, ++ u16 rx_blink_set, u16 tx_blink_set); ++int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index, ++ unsigned long *rules, u16 on_set, ++ u16 rx_blink_set, u16 tx_blink_set); ++int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on, ++ unsigned long *delay_off, bool *blinking); ++int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index, ++ u16 led_on_mask, bool on); ++int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, ++ bool blinking); ++void mtk_phy_leds_state_init(struct phy_device *phydev); ++ ++#endif /* _MTK_EPHY_H_ */ diff --git a/target/linux/generic/backport-6.12/725-v6.13-net-phy-mediatek-Improve-readability-of-mtk-phy-lib..patch b/target/linux/generic/backport-6.12/725-v6.13-net-phy-mediatek-Improve-readability-of-mtk-phy-lib..patch new file mode 100644 index 0000000000..19f3a84ad9 --- /dev/null +++ b/target/linux/generic/backport-6.12/725-v6.13-net-phy-mediatek-Improve-readability-of-mtk-phy-lib..patch @@ -0,0 +1,72 @@ +From 3efd0595fc7aaae300f5d9f4f0ae86f432c8d2c7 Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Sat, 9 Nov 2024 00:34:53 +0800 +Subject: [PATCH 06/20] net: phy: mediatek: Improve readability of + mtk-phy-lib.c's mtk_phy_led_hw_ctrl_set() + +This patch removes parens around TRIGGER_NETDEV_RX/TRIGGER_NETDEV_TX in +mtk_phy_led_hw_ctrl_set(), which improves readability. + +Reviewed-by: Andrew Lunn +Signed-off-by: SkyLake.Huang +Signed-off-by: David S. Miller +--- + drivers/net/phy/mediatek/mtk-phy-lib.c | 44 ++++++++++++++------------ + 1 file changed, 24 insertions(+), 20 deletions(-) + +--- a/drivers/net/phy/mediatek/mtk-phy-lib.c ++++ b/drivers/net/phy/mediatek/mtk-phy-lib.c +@@ -129,29 +129,33 @@ int mtk_phy_led_hw_ctrl_set(struct phy_d + on |= MTK_PHY_LED_ON_LINK2500; + + if (rules & BIT(TRIGGER_NETDEV_RX)) { +- blink |= (on & on_set) ? +- (((on & MTK_PHY_LED_ON_LINK10) ? +- MTK_PHY_LED_BLINK_10RX : 0) | +- ((on & MTK_PHY_LED_ON_LINK100) ? +- MTK_PHY_LED_BLINK_100RX : 0) | +- ((on & MTK_PHY_LED_ON_LINK1000) ? +- MTK_PHY_LED_BLINK_1000RX : 0) | +- ((on & MTK_PHY_LED_ON_LINK2500) ? +- MTK_PHY_LED_BLINK_2500RX : 0)) : +- rx_blink_set; ++ if (on & on_set) { ++ if (on & MTK_PHY_LED_ON_LINK10) ++ blink |= MTK_PHY_LED_BLINK_10RX; ++ if (on & MTK_PHY_LED_ON_LINK100) ++ blink |= MTK_PHY_LED_BLINK_100RX; ++ if (on & MTK_PHY_LED_ON_LINK1000) ++ blink |= MTK_PHY_LED_BLINK_1000RX; ++ if (on & MTK_PHY_LED_ON_LINK2500) ++ blink |= MTK_PHY_LED_BLINK_2500RX; ++ } else { ++ blink |= rx_blink_set; ++ } + } + + if (rules & BIT(TRIGGER_NETDEV_TX)) { +- blink |= (on & on_set) ? +- (((on & MTK_PHY_LED_ON_LINK10) ? +- MTK_PHY_LED_BLINK_10TX : 0) | +- ((on & MTK_PHY_LED_ON_LINK100) ? +- MTK_PHY_LED_BLINK_100TX : 0) | +- ((on & MTK_PHY_LED_ON_LINK1000) ? +- MTK_PHY_LED_BLINK_1000TX : 0) | +- ((on & MTK_PHY_LED_ON_LINK2500) ? +- MTK_PHY_LED_BLINK_2500TX : 0)) : +- tx_blink_set; ++ if (on & on_set) { ++ if (on & MTK_PHY_LED_ON_LINK10) ++ blink |= MTK_PHY_LED_BLINK_10TX; ++ if (on & MTK_PHY_LED_ON_LINK100) ++ blink |= MTK_PHY_LED_BLINK_100TX; ++ if (on & MTK_PHY_LED_ON_LINK1000) ++ blink |= MTK_PHY_LED_BLINK_1000TX; ++ if (on & MTK_PHY_LED_ON_LINK2500) ++ blink |= MTK_PHY_LED_BLINK_2500TX; ++ } else { ++ blink |= tx_blink_set; ++ } + } + + if (blink || on) diff --git a/target/linux/generic/backport-6.12/726-v6.13-net-phy-mediatek-Integrate-read-write-page-helper-fu.patch b/target/linux/generic/backport-6.12/726-v6.13-net-phy-mediatek-Integrate-read-write-page-helper-fu.patch new file mode 100644 index 0000000000..a5828bc759 --- /dev/null +++ b/target/linux/generic/backport-6.12/726-v6.13-net-phy-mediatek-Integrate-read-write-page-helper-fu.patch @@ -0,0 +1,153 @@ +From 50a97d716105a5f35aaecca0bdfe8e23cba0e87f Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Sat, 9 Nov 2024 00:34:54 +0800 +Subject: [PATCH 07/20] net: phy: mediatek: Integrate read/write page helper + functions + +This patch integrates read/write page helper functions as MTK phy lib. +They are basically the same in mtk-ge.c & mtk-ge-soc.c. + +Signed-off-by: SkyLake.Huang +Signed-off-by: David S. Miller +--- + drivers/net/phy/mediatek/Kconfig | 1 + + drivers/net/phy/mediatek/mtk-ge-soc.c | 18 ++++-------------- + drivers/net/phy/mediatek/mtk-ge.c | 20 ++++++-------------- + drivers/net/phy/mediatek/mtk-phy-lib.c | 12 ++++++++++++ + drivers/net/phy/mediatek/mtk.h | 3 +++ + 5 files changed, 26 insertions(+), 28 deletions(-) + +--- a/drivers/net/phy/mediatek/Kconfig ++++ b/drivers/net/phy/mediatek/Kconfig +@@ -4,6 +4,7 @@ config MTK_NET_PHYLIB + + config MEDIATEK_GE_PHY + tristate "MediaTek Gigabit Ethernet PHYs" ++ select MTK_NET_PHYLIB + help + Supports the MediaTek non-built-in Gigabit Ethernet PHYs. + +--- a/drivers/net/phy/mediatek/mtk-ge-soc.c ++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c +@@ -271,16 +271,6 @@ struct mtk_socphy_shared { + struct mtk_socphy_priv priv[4]; + }; + +-static int mtk_socphy_read_page(struct phy_device *phydev) +-{ +- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +-} +- +-static int mtk_socphy_write_page(struct phy_device *phydev, int page) +-{ +- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); +-} +- + /* One calibration cycle consists of: + * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high + * until AD_CAL_COMP is ready to output calibration result. +@@ -1337,8 +1327,8 @@ static struct phy_driver mtk_socphy_driv + .probe = mt7981_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, +- .read_page = mtk_socphy_read_page, +- .write_page = mtk_socphy_write_page, ++ .read_page = mtk_phy_read_page, ++ .write_page = mtk_phy_write_page, + .led_blink_set = mt798x_phy_led_blink_set, + .led_brightness_set = mt798x_phy_led_brightness_set, + .led_hw_is_supported = mt798x_phy_led_hw_is_supported, +@@ -1354,8 +1344,8 @@ static struct phy_driver mtk_socphy_driv + .probe = mt7988_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, +- .read_page = mtk_socphy_read_page, +- .write_page = mtk_socphy_write_page, ++ .read_page = mtk_phy_read_page, ++ .write_page = mtk_phy_write_page, + .led_blink_set = mt798x_phy_led_blink_set, + .led_brightness_set = mt798x_phy_led_brightness_set, + .led_hw_is_supported = mt798x_phy_led_hw_is_supported, +--- a/drivers/net/phy/mediatek/mtk-ge.c ++++ b/drivers/net/phy/mediatek/mtk-ge.c +@@ -3,6 +3,8 @@ + #include + #include + ++#include "mtk.h" ++ + #define MTK_EXT_PAGE_ACCESS 0x1f + #define MTK_PHY_PAGE_STANDARD 0x0000 + #define MTK_PHY_PAGE_EXTENDED 0x0001 +@@ -11,16 +13,6 @@ + #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 + #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 + +-static int mtk_gephy_read_page(struct phy_device *phydev) +-{ +- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +-} +- +-static int mtk_gephy_write_page(struct phy_device *phydev, int page) +-{ +- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); +-} +- + static void mtk_gephy_config_init(struct phy_device *phydev) + { + /* Enable HW auto downshift */ +@@ -77,8 +69,8 @@ static struct phy_driver mtk_gephy_drive + .handle_interrupt = genphy_handle_interrupt_no_ack, + .suspend = genphy_suspend, + .resume = genphy_resume, +- .read_page = mtk_gephy_read_page, +- .write_page = mtk_gephy_write_page, ++ .read_page = mtk_phy_read_page, ++ .write_page = mtk_phy_write_page, + }, + { + PHY_ID_MATCH_EXACT(0x03a29441), +@@ -91,8 +83,8 @@ static struct phy_driver mtk_gephy_drive + .handle_interrupt = genphy_handle_interrupt_no_ack, + .suspend = genphy_suspend, + .resume = genphy_resume, +- .read_page = mtk_gephy_read_page, +- .write_page = mtk_gephy_write_page, ++ .read_page = mtk_phy_read_page, ++ .write_page = mtk_phy_write_page, + }, + }; + +--- a/drivers/net/phy/mediatek/mtk-phy-lib.c ++++ b/drivers/net/phy/mediatek/mtk-phy-lib.c +@@ -6,6 +6,18 @@ + + #include "mtk.h" + ++int mtk_phy_read_page(struct phy_device *phydev) ++{ ++ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); ++} ++EXPORT_SYMBOL_GPL(mtk_phy_read_page); ++ ++int mtk_phy_write_page(struct phy_device *phydev, int page) ++{ ++ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); ++} ++EXPORT_SYMBOL_GPL(mtk_phy_write_page); ++ + int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules, + unsigned long supported_triggers) +--- a/drivers/net/phy/mediatek/mtk.h ++++ b/drivers/net/phy/mediatek/mtk.h +@@ -66,6 +66,9 @@ struct mtk_socphy_priv { + unsigned long led_state; + }; + ++int mtk_phy_read_page(struct phy_device *phydev); ++int mtk_phy_write_page(struct phy_device *phydev, int page); ++ + int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules, + unsigned long supported_triggers); diff --git a/target/linux/generic/backport-6.12/727-v6.13-net-phy-mediatek-add-MT7530-MT7531-s-PHY-ID-macros.patch b/target/linux/generic/backport-6.12/727-v6.13-net-phy-mediatek-add-MT7530-MT7531-s-PHY-ID-macros.patch new file mode 100644 index 0000000000..1c8738408b --- /dev/null +++ b/target/linux/generic/backport-6.12/727-v6.13-net-phy-mediatek-add-MT7530-MT7531-s-PHY-ID-macros.patch @@ -0,0 +1,56 @@ +From e6579df175d5b1baa605c82f8e759542262637cf Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Sat, 9 Nov 2024 00:34:55 +0800 +Subject: [PATCH 08/20] net: phy: mediatek: add MT7530 & MT7531's PHY ID macros + +This patch adds MT7530 & MT7531's PHY ID macros in mtk-ge.c so that +it follows the same rule of mtk-ge-soc.c. + +Reviewed-by: Andrew Lunn +Signed-off-by: SkyLake.Huang +Signed-off-by: David S. Miller +--- + drivers/net/phy/mediatek/mtk-ge.c | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +--- a/drivers/net/phy/mediatek/mtk-ge.c ++++ b/drivers/net/phy/mediatek/mtk-ge.c +@@ -5,6 +5,9 @@ + + #include "mtk.h" + ++#define MTK_GPHY_ID_MT7530 0x03a29412 ++#define MTK_GPHY_ID_MT7531 0x03a29441 ++ + #define MTK_EXT_PAGE_ACCESS 0x1f + #define MTK_PHY_PAGE_STANDARD 0x0000 + #define MTK_PHY_PAGE_EXTENDED 0x0001 +@@ -59,7 +62,7 @@ static int mt7531_phy_config_init(struct + + static struct phy_driver mtk_gephy_driver[] = { + { +- PHY_ID_MATCH_EXACT(0x03a29412), ++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530), + .name = "MediaTek MT7530 PHY", + .config_init = mt7530_phy_config_init, + /* Interrupts are handled by the switch, not the PHY +@@ -73,7 +76,7 @@ static struct phy_driver mtk_gephy_drive + .write_page = mtk_phy_write_page, + }, + { +- PHY_ID_MATCH_EXACT(0x03a29441), ++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531), + .name = "MediaTek MT7531 PHY", + .config_init = mt7531_phy_config_init, + /* Interrupts are handled by the switch, not the PHY +@@ -91,8 +94,8 @@ static struct phy_driver mtk_gephy_drive + module_phy_driver(mtk_gephy_driver); + + static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { +- { PHY_ID_MATCH_EXACT(0x03a29441) }, +- { PHY_ID_MATCH_EXACT(0x03a29412) }, ++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530) }, ++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531) }, + { } + }; + diff --git a/target/linux/generic/backport-6.12/728-v6.14-net-phy-Constify-struct-mdio_device_id.patch b/target/linux/generic/backport-6.12/728-v6.14-net-phy-Constify-struct-mdio_device_id.patch new file mode 100644 index 0000000000..669b58d22a --- /dev/null +++ b/target/linux/generic/backport-6.12/728-v6.14-net-phy-Constify-struct-mdio_device_id.patch @@ -0,0 +1,700 @@ +From e127f7380aaf2cd1614961d826a4af7ab297d37f Mon Sep 17 00:00:00 2001 +From: Christophe JAILLET +Date: Sun, 12 Jan 2025 15:14:50 +0100 +Subject: [PATCH 09/20] net: phy: Constify struct mdio_device_id + +'struct mdio_device_id' is not modified in these drivers. + +Constifying these structures moves some data to a read-only section, so +increase overall security. + +On a x86_64, with allmodconfig, as an example: +Before: +====== + text data bss dec hex filename + 27014 12792 0 39806 9b7e drivers/net/phy/broadcom.o + +After: +===== + text data bss dec hex filename + 27206 12600 0 39806 9b7e drivers/net/phy/broadcom.o + +Signed-off-by: Christophe JAILLET +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/403c381b7d9156b67ad68ffc44b8eee70c5e86a9.1736691226.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/adin.c | 2 +- + drivers/net/phy/adin1100.c | 2 +- + drivers/net/phy/air_en8811h.c | 2 +- + drivers/net/phy/amd.c | 2 +- + drivers/net/phy/aquantia/aquantia_main.c | 2 +- + drivers/net/phy/ax88796b.c | 2 +- + drivers/net/phy/bcm-cygnus.c | 2 +- + drivers/net/phy/bcm54140.c | 2 +- + drivers/net/phy/bcm63xx.c | 2 +- + drivers/net/phy/bcm7xxx.c | 2 +- + drivers/net/phy/bcm84881.c | 2 +- + drivers/net/phy/broadcom.c | 2 +- + drivers/net/phy/cicada.c | 2 +- + drivers/net/phy/cortina.c | 2 +- + drivers/net/phy/davicom.c | 2 +- + drivers/net/phy/dp83640.c | 2 +- + drivers/net/phy/dp83822.c | 2 +- + drivers/net/phy/dp83848.c | 2 +- + drivers/net/phy/dp83867.c | 2 +- + drivers/net/phy/dp83869.c | 2 +- + drivers/net/phy/dp83tc811.c | 2 +- + drivers/net/phy/dp83td510.c | 2 +- + drivers/net/phy/dp83tg720.c | 2 +- + drivers/net/phy/et1011c.c | 2 +- + drivers/net/phy/icplus.c | 2 +- + drivers/net/phy/intel-xway.c | 2 +- + drivers/net/phy/lxt.c | 2 +- + drivers/net/phy/marvell-88q2xxx.c | 2 +- + drivers/net/phy/marvell-88x2222.c | 2 +- + drivers/net/phy/marvell.c | 2 +- + drivers/net/phy/marvell10g.c | 2 +- + drivers/net/phy/mediatek/mtk-ge-soc.c | 2 +- + drivers/net/phy/mediatek/mtk-ge.c | 2 +- + drivers/net/phy/meson-gxl.c | 2 +- + drivers/net/phy/micrel.c | 2 +- + drivers/net/phy/microchip.c | 2 +- + drivers/net/phy/microchip_t1.c | 2 +- + drivers/net/phy/microchip_t1s.c | 2 +- + drivers/net/phy/mscc/mscc_main.c | 2 +- + drivers/net/phy/mxl-gpy.c | 2 +- + drivers/net/phy/national.c | 2 +- + drivers/net/phy/ncn26000.c | 2 +- + drivers/net/phy/nxp-c45-tja11xx.c | 2 +- + drivers/net/phy/nxp-cbtx.c | 2 +- + drivers/net/phy/nxp-tja11xx.c | 2 +- + drivers/net/phy/qcom/at803x.c | 2 +- + drivers/net/phy/qcom/qca807x.c | 2 +- + drivers/net/phy/qcom/qca808x.c | 2 +- + drivers/net/phy/qcom/qca83xx.c | 2 +- + drivers/net/phy/qsemi.c | 2 +- + drivers/net/phy/rockchip.c | 2 +- + drivers/net/phy/smsc.c | 2 +- + drivers/net/phy/ste10Xp.c | 2 +- + drivers/net/phy/teranetics.c | 2 +- + drivers/net/phy/uPD60620.c | 2 +- + drivers/net/phy/vitesse.c | 2 +- + 56 files changed, 56 insertions(+), 56 deletions(-) + +--- a/drivers/net/phy/adin.c ++++ b/drivers/net/phy/adin.c +@@ -1040,7 +1040,7 @@ static struct phy_driver adin_driver[] = + + module_phy_driver(adin_driver); + +-static struct mdio_device_id __maybe_unused adin_tbl[] = { ++static const struct mdio_device_id __maybe_unused adin_tbl[] = { + { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) }, + { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) }, + { } +--- a/drivers/net/phy/adin1100.c ++++ b/drivers/net/phy/adin1100.c +@@ -340,7 +340,7 @@ static struct phy_driver adin_driver[] = + + module_phy_driver(adin_driver); + +-static struct mdio_device_id __maybe_unused adin_tbl[] = { ++static const struct mdio_device_id __maybe_unused adin_tbl[] = { + { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100) }, + { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1110) }, + { PHY_ID_MATCH_MODEL(PHY_ID_ADIN2111) }, +--- a/drivers/net/phy/air_en8811h.c ++++ b/drivers/net/phy/air_en8811h.c +@@ -1075,7 +1075,7 @@ static struct phy_driver en8811h_driver[ + + module_phy_driver(en8811h_driver); + +-static struct mdio_device_id __maybe_unused en8811h_tbl[] = { ++static const struct mdio_device_id __maybe_unused en8811h_tbl[] = { + { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) }, + { } + }; +--- a/drivers/net/phy/amd.c ++++ b/drivers/net/phy/amd.c +@@ -111,7 +111,7 @@ static struct phy_driver am79c_drivers[] + + module_phy_driver(am79c_drivers); + +-static struct mdio_device_id __maybe_unused amd_tbl[] = { ++static const struct mdio_device_id __maybe_unused amd_tbl[] = { + { PHY_ID_AC101L, 0xfffffff0 }, + { PHY_ID_AM79C874, 0xfffffff0 }, + { } +--- a/drivers/net/phy/aquantia/aquantia_main.c ++++ b/drivers/net/phy/aquantia/aquantia_main.c +@@ -1096,7 +1096,7 @@ static struct phy_driver aqr_driver[] = + + module_phy_driver(aqr_driver); + +-static struct mdio_device_id __maybe_unused aqr_tbl[] = { ++static const struct mdio_device_id __maybe_unused aqr_tbl[] = { + { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, +--- a/drivers/net/phy/ax88796b.c ++++ b/drivers/net/phy/ax88796b.c +@@ -121,7 +121,7 @@ static struct phy_driver asix_driver[] = + + module_phy_driver(asix_driver); + +-static struct mdio_device_id __maybe_unused asix_tbl[] = { ++static const struct mdio_device_id __maybe_unused asix_tbl[] = { + { PHY_ID_MATCH_EXACT(PHY_ID_ASIX_AX88772A) }, + { PHY_ID_MATCH_EXACT(PHY_ID_ASIX_AX88772C) }, + { PHY_ID_ASIX_AX88796B, 0xfffffff0 }, +--- a/drivers/net/phy/bcm-cygnus.c ++++ b/drivers/net/phy/bcm-cygnus.c +@@ -278,7 +278,7 @@ static struct phy_driver bcm_cygnus_phy_ + } + }; + +-static struct mdio_device_id __maybe_unused bcm_cygnus_phy_tbl[] = { ++static const struct mdio_device_id __maybe_unused bcm_cygnus_phy_tbl[] = { + { PHY_ID_BCM_CYGNUS, 0xfffffff0, }, + { PHY_ID_BCM_OMEGA, 0xfffffff0, }, + { } +--- a/drivers/net/phy/bcm54140.c ++++ b/drivers/net/phy/bcm54140.c +@@ -883,7 +883,7 @@ static struct phy_driver bcm54140_driver + }; + module_phy_driver(bcm54140_drivers); + +-static struct mdio_device_id __maybe_unused bcm54140_tbl[] = { ++static const struct mdio_device_id __maybe_unused bcm54140_tbl[] = { + { PHY_ID_BCM54140, BCM54140_PHY_ID_MASK }, + { } + }; +--- a/drivers/net/phy/bcm63xx.c ++++ b/drivers/net/phy/bcm63xx.c +@@ -93,7 +93,7 @@ static struct phy_driver bcm63xx_driver[ + + module_phy_driver(bcm63xx_driver); + +-static struct mdio_device_id __maybe_unused bcm63xx_tbl[] = { ++static const struct mdio_device_id __maybe_unused bcm63xx_tbl[] = { + { 0x00406000, 0xfffffc00 }, + { 0x002bdc00, 0xfffffc00 }, + { } +--- a/drivers/net/phy/bcm7xxx.c ++++ b/drivers/net/phy/bcm7xxx.c +@@ -929,7 +929,7 @@ static struct phy_driver bcm7xxx_driver[ + BCM7XXX_16NM_EPHY(PHY_ID_BCM7712, "Broadcom BCM7712"), + }; + +-static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = { ++static const struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = { + { PHY_ID_BCM72113, 0xfffffff0 }, + { PHY_ID_BCM72116, 0xfffffff0, }, + { PHY_ID_BCM72165, 0xfffffff0, }, +--- a/drivers/net/phy/bcm84881.c ++++ b/drivers/net/phy/bcm84881.c +@@ -252,7 +252,7 @@ static struct phy_driver bcm84881_driver + module_phy_driver(bcm84881_drivers); + + /* FIXME: module auto-loading for Clause 45 PHYs seems non-functional */ +-static struct mdio_device_id __maybe_unused bcm84881_tbl[] = { ++static const struct mdio_device_id __maybe_unused bcm84881_tbl[] = { + { 0xae025150, 0xfffffff0 }, + { }, + }; +--- a/drivers/net/phy/broadcom.c ++++ b/drivers/net/phy/broadcom.c +@@ -1717,7 +1717,7 @@ static struct phy_driver broadcom_driver + + module_phy_driver(broadcom_drivers); + +-static struct mdio_device_id __maybe_unused broadcom_tbl[] = { ++static const struct mdio_device_id __maybe_unused broadcom_tbl[] = { + { PHY_ID_BCM5411, 0xfffffff0 }, + { PHY_ID_BCM5421, 0xfffffff0 }, + { PHY_ID_BCM54210E, 0xfffffff0 }, +--- a/drivers/net/phy/cicada.c ++++ b/drivers/net/phy/cicada.c +@@ -145,7 +145,7 @@ static struct phy_driver cis820x_driver[ + + module_phy_driver(cis820x_driver); + +-static struct mdio_device_id __maybe_unused cicada_tbl[] = { ++static const struct mdio_device_id __maybe_unused cicada_tbl[] = { + { 0x000fc410, 0x000ffff0 }, + { 0x000fc440, 0x000fffc0 }, + { } +--- a/drivers/net/phy/cortina.c ++++ b/drivers/net/phy/cortina.c +@@ -87,7 +87,7 @@ static struct phy_driver cortina_driver[ + + module_phy_driver(cortina_driver); + +-static struct mdio_device_id __maybe_unused cortina_tbl[] = { ++static const struct mdio_device_id __maybe_unused cortina_tbl[] = { + { PHY_ID_CS4340, 0xffffffff}, + {}, + }; +--- a/drivers/net/phy/davicom.c ++++ b/drivers/net/phy/davicom.c +@@ -209,7 +209,7 @@ static struct phy_driver dm91xx_driver[] + + module_phy_driver(dm91xx_driver); + +-static struct mdio_device_id __maybe_unused davicom_tbl[] = { ++static const struct mdio_device_id __maybe_unused davicom_tbl[] = { + { 0x0181b880, 0x0ffffff0 }, + { 0x0181b8b0, 0x0ffffff0 }, + { 0x0181b8a0, 0x0ffffff0 }, +--- a/drivers/net/phy/dp83640.c ++++ b/drivers/net/phy/dp83640.c +@@ -1548,7 +1548,7 @@ MODULE_LICENSE("GPL"); + module_init(dp83640_init); + module_exit(dp83640_exit); + +-static struct mdio_device_id __maybe_unused dp83640_tbl[] = { ++static const struct mdio_device_id __maybe_unused dp83640_tbl[] = { + { DP83640_PHY_ID, 0xfffffff0 }, + { } + }; +--- a/drivers/net/phy/dp83822.c ++++ b/drivers/net/phy/dp83822.c +@@ -825,7 +825,7 @@ static struct phy_driver dp83822_driver[ + }; + module_phy_driver(dp83822_driver); + +-static struct mdio_device_id __maybe_unused dp83822_tbl[] = { ++static const struct mdio_device_id __maybe_unused dp83822_tbl[] = { + { DP83822_PHY_ID, 0xfffffff0 }, + { DP83825I_PHY_ID, 0xfffffff0 }, + { DP83826C_PHY_ID, 0xfffffff0 }, +--- a/drivers/net/phy/dp83848.c ++++ b/drivers/net/phy/dp83848.c +@@ -123,7 +123,7 @@ static int dp83848_config_init(struct ph + return 0; + } + +-static struct mdio_device_id __maybe_unused dp83848_tbl[] = { ++static const struct mdio_device_id __maybe_unused dp83848_tbl[] = { + { TI_DP83848C_PHY_ID, 0xfffffff0 }, + { NS_DP83848C_PHY_ID, 0xfffffff0 }, + { TI_DP83620_PHY_ID, 0xfffffff0 }, +--- a/drivers/net/phy/dp83867.c ++++ b/drivers/net/phy/dp83867.c +@@ -1210,7 +1210,7 @@ static struct phy_driver dp83867_driver[ + }; + module_phy_driver(dp83867_driver); + +-static struct mdio_device_id __maybe_unused dp83867_tbl[] = { ++static const struct mdio_device_id __maybe_unused dp83867_tbl[] = { + { DP83867_PHY_ID, 0xfffffff0 }, + { } + }; +--- a/drivers/net/phy/dp83869.c ++++ b/drivers/net/phy/dp83869.c +@@ -928,7 +928,7 @@ static struct phy_driver dp83869_driver[ + }; + module_phy_driver(dp83869_driver); + +-static struct mdio_device_id __maybe_unused dp83869_tbl[] = { ++static const struct mdio_device_id __maybe_unused dp83869_tbl[] = { + { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) }, + { PHY_ID_MATCH_MODEL(DP83561_PHY_ID) }, + { } +--- a/drivers/net/phy/dp83tc811.c ++++ b/drivers/net/phy/dp83tc811.c +@@ -403,7 +403,7 @@ static struct phy_driver dp83811_driver[ + }; + module_phy_driver(dp83811_driver); + +-static struct mdio_device_id __maybe_unused dp83811_tbl[] = { ++static const struct mdio_device_id __maybe_unused dp83811_tbl[] = { + { DP83TC811_PHY_ID, 0xfffffff0 }, + { }, + }; +--- a/drivers/net/phy/dp83td510.c ++++ b/drivers/net/phy/dp83td510.c +@@ -605,7 +605,7 @@ static struct phy_driver dp83td510_drive + } }; + module_phy_driver(dp83td510_driver); + +-static struct mdio_device_id __maybe_unused dp83td510_tbl[] = { ++static const struct mdio_device_id __maybe_unused dp83td510_tbl[] = { + { PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID) }, + { } + }; +--- a/drivers/net/phy/dp83tg720.c ++++ b/drivers/net/phy/dp83tg720.c +@@ -361,7 +361,7 @@ static struct phy_driver dp83tg720_drive + } }; + module_phy_driver(dp83tg720_driver); + +-static struct mdio_device_id __maybe_unused dp83tg720_tbl[] = { ++static const struct mdio_device_id __maybe_unused dp83tg720_tbl[] = { + { PHY_ID_MATCH_MODEL(DP83TG720S_PHY_ID) }, + { } + }; +--- a/drivers/net/phy/et1011c.c ++++ b/drivers/net/phy/et1011c.c +@@ -94,7 +94,7 @@ static struct phy_driver et1011c_driver[ + + module_phy_driver(et1011c_driver); + +-static struct mdio_device_id __maybe_unused et1011c_tbl[] = { ++static const struct mdio_device_id __maybe_unused et1011c_tbl[] = { + { 0x0282f014, 0xfffffff0 }, + { } + }; +--- a/drivers/net/phy/icplus.c ++++ b/drivers/net/phy/icplus.c +@@ -624,7 +624,7 @@ static struct phy_driver icplus_driver[] + + module_phy_driver(icplus_driver); + +-static struct mdio_device_id __maybe_unused icplus_tbl[] = { ++static const struct mdio_device_id __maybe_unused icplus_tbl[] = { + { PHY_ID_MATCH_MODEL(IP175C_PHY_ID) }, + { PHY_ID_MATCH_MODEL(IP1001_PHY_ID) }, + { PHY_ID_MATCH_EXACT(IP101A_PHY_ID) }, +--- a/drivers/net/phy/intel-xway.c ++++ b/drivers/net/phy/intel-xway.c +@@ -456,7 +456,7 @@ static struct phy_driver xway_gphy[] = { + }; + module_phy_driver(xway_gphy); + +-static struct mdio_device_id __maybe_unused xway_gphy_tbl[] = { ++static const struct mdio_device_id __maybe_unused xway_gphy_tbl[] = { + { PHY_ID_PHY11G_1_3, 0xffffffff }, + { PHY_ID_PHY22F_1_3, 0xffffffff }, + { PHY_ID_PHY11G_1_4, 0xffffffff }, +--- a/drivers/net/phy/lxt.c ++++ b/drivers/net/phy/lxt.c +@@ -348,7 +348,7 @@ static struct phy_driver lxt97x_driver[] + + module_phy_driver(lxt97x_driver); + +-static struct mdio_device_id __maybe_unused lxt_tbl[] = { ++static const struct mdio_device_id __maybe_unused lxt_tbl[] = { + { 0x78100000, 0xfffffff0 }, + { 0x001378e0, 0xfffffff0 }, + { 0x00137a10, 0xfffffff0 }, +--- a/drivers/net/phy/marvell-88q2xxx.c ++++ b/drivers/net/phy/marvell-88q2xxx.c +@@ -940,7 +940,7 @@ static struct phy_driver mv88q2xxx_drive + + module_phy_driver(mv88q2xxx_driver); + +-static struct mdio_device_id __maybe_unused mv88q2xxx_tbl[] = { ++static const struct mdio_device_id __maybe_unused mv88q2xxx_tbl[] = { + { MARVELL_PHY_ID_88Q2110, MARVELL_PHY_ID_MASK }, + { MARVELL_PHY_ID_88Q2220, MARVELL_PHY_ID_MASK }, + { /*sentinel*/ } +--- a/drivers/net/phy/marvell-88x2222.c ++++ b/drivers/net/phy/marvell-88x2222.c +@@ -613,7 +613,7 @@ static struct phy_driver mv2222_drivers[ + }; + module_phy_driver(mv2222_drivers); + +-static struct mdio_device_id __maybe_unused mv2222_tbl[] = { ++static const struct mdio_device_id __maybe_unused mv2222_tbl[] = { + { MARVELL_PHY_ID_88X2222, MARVELL_PHY_ID_MASK }, + { } + }; +--- a/drivers/net/phy/marvell.c ++++ b/drivers/net/phy/marvell.c +@@ -4133,7 +4133,7 @@ static struct phy_driver marvell_drivers + + module_phy_driver(marvell_drivers); + +-static struct mdio_device_id __maybe_unused marvell_tbl[] = { ++static const struct mdio_device_id __maybe_unused marvell_tbl[] = { + { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK }, + { MARVELL_PHY_ID_88E3082, MARVELL_PHY_ID_MASK }, + { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK }, +--- a/drivers/net/phy/marvell10g.c ++++ b/drivers/net/phy/marvell10g.c +@@ -1484,7 +1484,7 @@ static struct phy_driver mv3310_drivers[ + + module_phy_driver(mv3310_drivers); + +-static struct mdio_device_id __maybe_unused mv3310_tbl[] = { ++static const struct mdio_device_id __maybe_unused mv3310_tbl[] = { + { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK }, + { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, + { }, +--- a/drivers/net/phy/mediatek/mtk-ge-soc.c ++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c +@@ -1356,7 +1356,7 @@ static struct phy_driver mtk_socphy_driv + + module_phy_driver(mtk_socphy_driver); + +-static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { ++static const struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, + { } +--- a/drivers/net/phy/mediatek/mtk-ge.c ++++ b/drivers/net/phy/mediatek/mtk-ge.c +@@ -93,7 +93,7 @@ static struct phy_driver mtk_gephy_drive + + module_phy_driver(mtk_gephy_driver); + +-static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { ++static const struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530) }, + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531) }, + { } +--- a/drivers/net/phy/meson-gxl.c ++++ b/drivers/net/phy/meson-gxl.c +@@ -221,7 +221,7 @@ static struct phy_driver meson_gxl_phy[] + }, + }; + +-static struct mdio_device_id __maybe_unused meson_gxl_tbl[] = { ++static const struct mdio_device_id __maybe_unused meson_gxl_tbl[] = { + { PHY_ID_MATCH_VENDOR(0x01814400) }, + { PHY_ID_MATCH_VENDOR(0x01803301) }, + { } +--- a/drivers/net/phy/micrel.c ++++ b/drivers/net/phy/micrel.c +@@ -5691,7 +5691,7 @@ MODULE_DESCRIPTION("Micrel PHY driver"); + MODULE_AUTHOR("David J. Choi"); + MODULE_LICENSE("GPL"); + +-static struct mdio_device_id __maybe_unused micrel_tbl[] = { ++static const struct mdio_device_id __maybe_unused micrel_tbl[] = { + { PHY_ID_KSZ9021, 0x000ffffe }, + { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, + { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, +--- a/drivers/net/phy/microchip.c ++++ b/drivers/net/phy/microchip.c +@@ -508,7 +508,7 @@ static struct phy_driver microchip_phy_d + + module_phy_driver(microchip_phy_driver); + +-static struct mdio_device_id __maybe_unused microchip_tbl[] = { ++static const struct mdio_device_id __maybe_unused microchip_tbl[] = { + { 0x0007c132, 0xfffffff2 }, + { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X_TX) }, + { } +--- a/drivers/net/phy/microchip_t1.c ++++ b/drivers/net/phy/microchip_t1.c +@@ -1886,7 +1886,7 @@ static struct phy_driver microchip_t1_ph + + module_phy_driver(microchip_t1_phy_driver); + +-static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = { ++static const struct mdio_device_id __maybe_unused microchip_t1_tbl[] = { + { PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) }, + { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) }, + { PHY_ID_MATCH_MODEL(PHY_ID_LAN887X) }, +--- a/drivers/net/phy/microchip_t1s.c ++++ b/drivers/net/phy/microchip_t1s.c +@@ -323,7 +323,7 @@ static struct phy_driver microchip_t1s_d + + module_phy_driver(microchip_t1s_driver); + +-static struct mdio_device_id __maybe_unused tbl[] = { ++static const struct mdio_device_id __maybe_unused tbl[] = { + { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) }, + { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0) }, + { } +--- a/drivers/net/phy/mscc/mscc_main.c ++++ b/drivers/net/phy/mscc/mscc_main.c +@@ -2700,7 +2700,7 @@ static struct phy_driver vsc85xx_driver[ + + module_phy_driver(vsc85xx_driver); + +-static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = { ++static const struct mdio_device_id __maybe_unused vsc85xx_tbl[] = { + { PHY_ID_MATCH_VENDOR(PHY_VENDOR_MSCC) }, + { } + }; +--- a/drivers/net/phy/mxl-gpy.c ++++ b/drivers/net/phy/mxl-gpy.c +@@ -1047,7 +1047,7 @@ static struct phy_driver gpy_drivers[] = + }; + module_phy_driver(gpy_drivers); + +-static struct mdio_device_id __maybe_unused gpy_tbl[] = { ++static const struct mdio_device_id __maybe_unused gpy_tbl[] = { + {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)}, + {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK}, + {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)}, +--- a/drivers/net/phy/national.c ++++ b/drivers/net/phy/national.c +@@ -173,7 +173,7 @@ MODULE_DESCRIPTION("NatSemi PHY driver") + MODULE_AUTHOR("Stuart Menefy"); + MODULE_LICENSE("GPL"); + +-static struct mdio_device_id __maybe_unused ns_tbl[] = { ++static const struct mdio_device_id __maybe_unused ns_tbl[] = { + { DP83865_PHY_ID, 0xfffffff0 }, + { } + }; +--- a/drivers/net/phy/ncn26000.c ++++ b/drivers/net/phy/ncn26000.c +@@ -159,7 +159,7 @@ static struct phy_driver ncn26000_driver + + module_phy_driver(ncn26000_driver); + +-static struct mdio_device_id __maybe_unused ncn26000_tbl[] = { ++static const struct mdio_device_id __maybe_unused ncn26000_tbl[] = { + { PHY_ID_MATCH_MODEL(PHY_ID_NCN26000) }, + { } + }; +--- a/drivers/net/phy/nxp-c45-tja11xx.c ++++ b/drivers/net/phy/nxp-c45-tja11xx.c +@@ -2102,7 +2102,7 @@ static struct phy_driver nxp_c45_driver[ + + module_phy_driver(nxp_c45_driver); + +-static struct mdio_device_id __maybe_unused nxp_c45_tbl[] = { ++static const struct mdio_device_id __maybe_unused nxp_c45_tbl[] = { + { PHY_ID_MATCH_MODEL(PHY_ID_TJA_1103) }, + { PHY_ID_MATCH_MODEL(PHY_ID_TJA_1120) }, + { /*sentinel*/ }, +--- a/drivers/net/phy/nxp-cbtx.c ++++ b/drivers/net/phy/nxp-cbtx.c +@@ -215,7 +215,7 @@ static struct phy_driver cbtx_driver[] = + + module_phy_driver(cbtx_driver); + +-static struct mdio_device_id __maybe_unused cbtx_tbl[] = { ++static const struct mdio_device_id __maybe_unused cbtx_tbl[] = { + { PHY_ID_MATCH_MODEL(PHY_ID_CBTX_SJA1110) }, + { }, + }; +--- a/drivers/net/phy/nxp-tja11xx.c ++++ b/drivers/net/phy/nxp-tja11xx.c +@@ -888,7 +888,7 @@ static struct phy_driver tja11xx_driver[ + + module_phy_driver(tja11xx_driver); + +-static struct mdio_device_id __maybe_unused tja11xx_tbl[] = { ++static const struct mdio_device_id __maybe_unused tja11xx_tbl[] = { + { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) }, + { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) }, + { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) }, +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c +@@ -1098,7 +1098,7 @@ static struct phy_driver at803x_driver[] + + module_phy_driver(at803x_driver); + +-static struct mdio_device_id __maybe_unused atheros_tbl[] = { ++static const struct mdio_device_id __maybe_unused atheros_tbl[] = { + { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, + { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, + { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, +--- a/drivers/net/phy/qcom/qca807x.c ++++ b/drivers/net/phy/qcom/qca807x.c +@@ -828,7 +828,7 @@ static struct phy_driver qca807x_drivers + }; + module_phy_driver(qca807x_drivers); + +-static struct mdio_device_id __maybe_unused qca807x_tbl[] = { ++static const struct mdio_device_id __maybe_unused qca807x_tbl[] = { + { PHY_ID_MATCH_EXACT(PHY_ID_QCA8072) }, + { PHY_ID_MATCH_EXACT(PHY_ID_QCA8075) }, + { } +--- a/drivers/net/phy/qcom/qca808x.c ++++ b/drivers/net/phy/qcom/qca808x.c +@@ -655,7 +655,7 @@ static struct phy_driver qca808x_driver[ + + module_phy_driver(qca808x_driver); + +-static struct mdio_device_id __maybe_unused qca808x_tbl[] = { ++static const struct mdio_device_id __maybe_unused qca808x_tbl[] = { + { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, + { } + }; +--- a/drivers/net/phy/qcom/qca83xx.c ++++ b/drivers/net/phy/qcom/qca83xx.c +@@ -261,7 +261,7 @@ static struct phy_driver qca83xx_driver[ + + module_phy_driver(qca83xx_driver); + +-static struct mdio_device_id __maybe_unused qca83xx_tbl[] = { ++static const struct mdio_device_id __maybe_unused qca83xx_tbl[] = { + { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, + { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, + { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, +--- a/drivers/net/phy/qsemi.c ++++ b/drivers/net/phy/qsemi.c +@@ -155,7 +155,7 @@ static struct phy_driver qs6612_driver[] + + module_phy_driver(qs6612_driver); + +-static struct mdio_device_id __maybe_unused qs6612_tbl[] = { ++static const struct mdio_device_id __maybe_unused qs6612_tbl[] = { + { 0x00181440, 0xfffffff0 }, + { } + }; +--- a/drivers/net/phy/rockchip.c ++++ b/drivers/net/phy/rockchip.c +@@ -188,7 +188,7 @@ static struct phy_driver rockchip_phy_dr + + module_phy_driver(rockchip_phy_driver); + +-static struct mdio_device_id __maybe_unused rockchip_phy_tbl[] = { ++static const struct mdio_device_id __maybe_unused rockchip_phy_tbl[] = { + { INTERNAL_EPHY_ID, 0xfffffff0 }, + { } + }; +--- a/drivers/net/phy/smsc.c ++++ b/drivers/net/phy/smsc.c +@@ -837,7 +837,7 @@ MODULE_DESCRIPTION("SMSC PHY driver"); + MODULE_AUTHOR("Herbert Valerio Riedel"); + MODULE_LICENSE("GPL"); + +-static struct mdio_device_id __maybe_unused smsc_tbl[] = { ++static const struct mdio_device_id __maybe_unused smsc_tbl[] = { + { 0x0007c0a0, 0xfffffff0 }, + { 0x0007c0b0, 0xfffffff0 }, + { 0x0007c0c0, 0xfffffff0 }, +--- a/drivers/net/phy/ste10Xp.c ++++ b/drivers/net/phy/ste10Xp.c +@@ -124,7 +124,7 @@ static struct phy_driver ste10xp_pdriver + + module_phy_driver(ste10xp_pdriver); + +-static struct mdio_device_id __maybe_unused ste10Xp_tbl[] = { ++static const struct mdio_device_id __maybe_unused ste10Xp_tbl[] = { + { STE101P_PHY_ID, 0xfffffff0 }, + { STE100P_PHY_ID, 0xffffffff }, + { } +--- a/drivers/net/phy/teranetics.c ++++ b/drivers/net/phy/teranetics.c +@@ -87,7 +87,7 @@ static struct phy_driver teranetics_driv + + module_phy_driver(teranetics_driver); + +-static struct mdio_device_id __maybe_unused teranetics_tbl[] = { ++static const struct mdio_device_id __maybe_unused teranetics_tbl[] = { + { PHY_ID_TN2020, 0xffffffff }, + { } + }; +--- a/drivers/net/phy/uPD60620.c ++++ b/drivers/net/phy/uPD60620.c +@@ -90,7 +90,7 @@ static struct phy_driver upd60620_driver + + module_phy_driver(upd60620_driver); + +-static struct mdio_device_id __maybe_unused upd60620_tbl[] = { ++static const struct mdio_device_id __maybe_unused upd60620_tbl[] = { + { UPD60620_PHY_ID, 0xfffffffe }, + { } + }; +--- a/drivers/net/phy/vitesse.c ++++ b/drivers/net/phy/vitesse.c +@@ -674,7 +674,7 @@ static struct phy_driver vsc82xx_driver[ + + module_phy_driver(vsc82xx_driver); + +-static struct mdio_device_id __maybe_unused vitesse_tbl[] = { ++static const struct mdio_device_id __maybe_unused vitesse_tbl[] = { + { PHY_ID_VSC8234, 0x000ffff0 }, + { PHY_ID_VSC8244, 0x000fffc0 }, + { PHY_ID_VSC8572, 0x000ffff0 }, diff --git a/target/linux/generic/backport-6.12/729-v6.15-net-phy-mediatek-Change-to-more-meaningful-macros.patch b/target/linux/generic/backport-6.12/729-v6.15-net-phy-mediatek-Change-to-more-meaningful-macros.patch new file mode 100644 index 0000000000..545e92987f --- /dev/null +++ b/target/linux/generic/backport-6.12/729-v6.15-net-phy-mediatek-Change-to-more-meaningful-macros.patch @@ -0,0 +1,146 @@ +From 7e06c3dbfa5f1e39eba92eb79d854fab2a7ad5fe Mon Sep 17 00:00:00 2001 +From: Sky Huang +Date: Thu, 13 Feb 2025 16:05:49 +0800 +Subject: [PATCH 10/20] net: phy: mediatek: Change to more meaningful macros + +Replace magic number with more meaningful macros in mtk-ge.c. +Also, move some common macros into mtk-phy-lib.c. + +Signed-off-by: Sky Huang +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/20250213080553.921434-2-SkyLake.Huang@mediatek.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/mediatek/mtk-ge-soc.c | 1 - + drivers/net/phy/mediatek/mtk-ge.c | 71 +++++++++++++++++++++------ + drivers/net/phy/mediatek/mtk.h | 2 + + 3 files changed, 57 insertions(+), 17 deletions(-) + +--- a/drivers/net/phy/mediatek/mtk-ge-soc.c ++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c +@@ -24,7 +24,6 @@ + #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) + + #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 +-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 + + #define ANALOG_INTERNAL_OPERATION_MAX_US 20 + #define TXRESERVE_MIN 0 +--- a/drivers/net/phy/mediatek/mtk-ge.c ++++ b/drivers/net/phy/mediatek/mtk-ge.c +@@ -8,18 +8,38 @@ + #define MTK_GPHY_ID_MT7530 0x03a29412 + #define MTK_GPHY_ID_MT7531 0x03a29441 + +-#define MTK_EXT_PAGE_ACCESS 0x1f +-#define MTK_PHY_PAGE_STANDARD 0x0000 +-#define MTK_PHY_PAGE_EXTENDED 0x0001 +-#define MTK_PHY_PAGE_EXTENDED_2 0x0002 +-#define MTK_PHY_PAGE_EXTENDED_3 0x0003 +-#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 +-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 ++#define MTK_PHY_PAGE_EXTENDED_1 0x0001 ++#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14 ++#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4) ++ ++#define MTK_PHY_PAGE_EXTENDED_2 0x0002 ++#define MTK_PHY_PAGE_EXTENDED_3 0x0003 ++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11 ++ ++#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 ++ ++/* Registers on MDIO_MMD_VEND1 */ ++#define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13 ++#define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14 ++#define MTK_TX_DELAY_PAIR_B_MASK GENMASK(10, 8) ++#define MTK_TX_DELAY_PAIR_D_MASK GENMASK(2, 0) ++ ++#define MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL 0xa6 ++#define MTK_MCC_NEARECHO_OFFSET_MASK GENMASK(15, 8) ++ ++#define MTK_PHY_RXADC_CTRL_RG7 0xc6 ++#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) ++ ++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123 0x123 ++#define MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK GENMASK(15, 8) ++#define MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK GENMASK(7, 0) + + static void mtk_gephy_config_init(struct phy_device *phydev) + { + /* Enable HW auto downshift */ +- phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); ++ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1, ++ MTK_PHY_AUX_CTRL_AND_STATUS, ++ 0, MTK_PHY_ENABLE_DOWNSHIFT); + + /* Increase SlvDPSready time */ + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +@@ -29,10 +49,20 @@ static void mtk_gephy_config_init(struct + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + /* Adjust 100_mse_threshold */ +- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); +- +- /* Disable mcc */ +- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123, ++ MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK | ++ MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK, ++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK, ++ 0xff) | ++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK, ++ 0xff)); ++ ++ /* If echo time is narrower than 0x3, it will be regarded as noise */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, ++ MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL, ++ MTK_MCC_NEARECHO_OFFSET_MASK, ++ FIELD_PREP(MTK_MCC_NEARECHO_OFFSET_MASK, 0x3)); + } + + static int mt7530_phy_config_init(struct phy_device *phydev) +@@ -40,7 +70,8 @@ static int mt7530_phy_config_init(struct + mtk_gephy_config_init(phydev); + + /* Increase post_update_timer */ +- phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b); ++ phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, ++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11, 0x4b); + + return 0; + } +@@ -51,11 +82,19 @@ static int mt7531_phy_config_init(struct + + /* PHY link down power saving enable */ + phy_set_bits(phydev, 0x17, BIT(4)); +- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, ++ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, ++ FIELD_PREP(MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3)); + + /* Set TX Pair delay selection */ +- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); +- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL, ++ MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK, ++ FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) | ++ FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4)); ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL, ++ MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK, ++ FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) | ++ FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4)); + + return 0; + } +--- a/drivers/net/phy/mediatek/mtk.h ++++ b/drivers/net/phy/mediatek/mtk.h +@@ -9,6 +9,8 @@ + #define _MTK_EPHY_H_ + + #define MTK_EXT_PAGE_ACCESS 0x1f ++#define MTK_PHY_PAGE_STANDARD 0x0000 ++#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 + + /* Registers on MDIO_MMD_VEND2 */ + #define MTK_PHY_LED0_ON_CTRL 0x24 diff --git a/target/linux/generic/backport-6.12/730-v6.15-net-phy-mediatek-Add-token-ring-access-helper-functi.patch b/target/linux/generic/backport-6.12/730-v6.15-net-phy-mediatek-Add-token-ring-access-helper-functi.patch new file mode 100644 index 0000000000..40ce29fc51 --- /dev/null +++ b/target/linux/generic/backport-6.12/730-v6.15-net-phy-mediatek-Add-token-ring-access-helper-functi.patch @@ -0,0 +1,448 @@ +From 6e7370079669b0d55c9464bb7c3fb8fb7368b912 Mon Sep 17 00:00:00 2001 +From: Sky Huang +Date: Thu, 13 Feb 2025 16:05:50 +0800 +Subject: [PATCH 11/20] net: phy: mediatek: Add token ring access helper + functions in mtk-phy-lib + +This patch adds TR(token ring) manipulations and adds correct +macro names for those magic numbers. TR is a way to access +proprietary registers on page 52b5. Use these helper functions +so we can see which fields we're going to modify/set/clear. + +TR functions with __* prefix mean that the operations inside +aren't wrapped by page select/restore functions. + +This patch doesn't really change registers' settings but just +enhances readability and maintainability. + +Signed-off-by: Sky Huang +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/20250213080553.921434-3-SkyLake.Huang@mediatek.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/mediatek/mtk-ge-soc.c | 231 +++++++++++++++++-------- + drivers/net/phy/mediatek/mtk-ge.c | 11 +- + drivers/net/phy/mediatek/mtk-phy-lib.c | 63 +++++++ + drivers/net/phy/mediatek/mtk.h | 5 + + 4 files changed, 230 insertions(+), 80 deletions(-) + +--- a/drivers/net/phy/mediatek/mtk-ge-soc.c ++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c +@@ -25,6 +25,90 @@ + + #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 + ++/* Registers on Token Ring debug nodes */ ++/* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */ ++/* NormMseLoThresh */ ++#define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8) ++ ++/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */ ++/* RemAckCntLimitCtrl */ ++#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1) ++ ++/* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */ ++/* VcoSlicerThreshBitsHigh */ ++#define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0) ++ ++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */ ++/* DfeTailEnableVgaThresh1000 */ ++#define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1) ++ ++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */ ++/* MrvlTrFix100Kp */ ++#define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20) ++/* MrvlTrFix100Kf */ ++#define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17) ++/* MrvlTrFix1000Kp */ ++#define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14) ++/* MrvlTrFix1000Kf */ ++#define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11) ++ ++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */ ++/* VgaDecRate */ ++#define VGA_DECIMATION_RATE_MASK GENMASK(8, 5) ++ ++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */ ++/* SlvDSPreadyTime */ ++#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15) ++/* MasDSPreadyTime */ ++#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7) ++ ++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */ ++/* ResetSyncOffset */ ++#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8) ++ ++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */ ++/* FfeUpdGainForceVal */ ++#define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7) ++/* FfeUpdGainForce */ ++#define FFE_UPDATE_GAIN_FORCE BIT(6) ++ ++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */ ++/* SS: Steady-state, KP: Proportional Gain */ ++/* SSTrKp100 */ ++#define SS_TR_KP100_MASK GENMASK(21, 19) ++/* SSTrKf100 */ ++#define SS_TR_KF100_MASK GENMASK(18, 16) ++/* SSTrKp1000Mas */ ++#define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13) ++/* SSTrKf1000Mas */ ++#define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10) ++/* SSTrKp1000Slv */ ++#define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7) ++/* SSTrKf1000Slv */ ++#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4) ++ ++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */ ++/* RegEEE_st2TrKf1000 */ ++#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11) ++ ++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */ ++/* RegEEE_slv_waketr_timer_tar */ ++#define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11) ++/* RegEEE_slv_remtx_timer_tar */ ++#define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1) ++ ++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */ ++/* RegEEE_slv_wake_int_timer_tar */ ++#define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1) ++ ++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */ ++/* RegEEE_trfreeze_timer2 */ ++#define TR_FREEZE_TIMER2_MASK GENMASK(9, 0) ++ ++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */ ++/* RegEEE100Stg1_tar */ ++#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0) ++ + #define ANALOG_INTERNAL_OPERATION_MAX_US 20 + #define TXRESERVE_MIN 0 + #define TXRESERVE_MAX 7 +@@ -700,40 +784,41 @@ restore: + static void mt798x_phy_common_finetune(struct phy_device *phydev) + { + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ +- __phy_write(phydev, 0x11, 0xc71); +- __phy_write(phydev, 0x12, 0xc); +- __phy_write(phydev, 0x10, 0x8fae); ++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x17, ++ SLAVE_DSP_READY_TIME_MASK | MASTER_DSP_READY_TIME_MASK, ++ FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) | ++ FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18)); + + /* EnabRandUpdTrig = 1 */ + __phy_write(phydev, 0x11, 0x2f00); + __phy_write(phydev, 0x12, 0xe); + __phy_write(phydev, 0x10, 0x8fb0); + +- /* NormMseLoThresh = 85 */ +- __phy_write(phydev, 0x11, 0x55a0); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x83aa); +- +- /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */ +- __phy_write(phydev, 0x11, 0x240); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x9680); ++ __mtk_tr_modify(phydev, 0x0, 0x7, 0x15, ++ NORMAL_MSE_LO_THRESH_MASK, ++ FIELD_PREP(NORMAL_MSE_LO_THRESH_MASK, 0x55)); ++ ++ __mtk_tr_modify(phydev, 0x2, 0xd, 0x0, ++ FFE_UPDATE_GAIN_FORCE_VAL_MASK, ++ FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) | ++ FFE_UPDATE_GAIN_FORCE); + + /* TrFreeze = 0 (mt7988 default) */ + __phy_write(phydev, 0x11, 0x0); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x9686); + +- /* SSTrKp100 = 5 */ +- /* SSTrKf100 = 6 */ +- /* SSTrKp1000Mas = 5 */ +- /* SSTrKf1000Mas = 6 */ +- /* SSTrKp1000Slv = 5 */ +- /* SSTrKf1000Slv = 6 */ +- __phy_write(phydev, 0x11, 0xbaef); +- __phy_write(phydev, 0x12, 0x2e); +- __phy_write(phydev, 0x10, 0x968c); ++ __mtk_tr_modify(phydev, 0x2, 0xd, 0x6, ++ SS_TR_KP100_MASK | SS_TR_KF100_MASK | ++ SS_TR_KP1000_MASTER_MASK | SS_TR_KF1000_MASTER_MASK | ++ SS_TR_KP1000_SLAVE_MASK | SS_TR_KF1000_SLAVE_MASK, ++ FIELD_PREP(SS_TR_KP100_MASK, 0x5) | ++ FIELD_PREP(SS_TR_KF100_MASK, 0x6) | ++ FIELD_PREP(SS_TR_KP1000_MASTER_MASK, 0x5) | ++ FIELD_PREP(SS_TR_KF1000_MASTER_MASK, 0x6) | ++ FIELD_PREP(SS_TR_KP1000_SLAVE_MASK, 0x5) | ++ FIELD_PREP(SS_TR_KF1000_SLAVE_MASK, 0x6)); ++ + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + } + +@@ -756,27 +841,29 @@ static void mt7981_phy_finetune(struct p + } + + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- /* ResetSyncOffset = 6 */ +- __phy_write(phydev, 0x11, 0x600); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x8fc0); +- +- /* VgaDecRate = 1 */ +- __phy_write(phydev, 0x11, 0x4c2a); +- __phy_write(phydev, 0x12, 0x3e); +- __phy_write(phydev, 0x10, 0x8fa4); ++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x20, ++ RESET_SYNC_OFFSET_MASK, ++ FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x6)); ++ ++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x12, ++ VGA_DECIMATION_RATE_MASK, ++ FIELD_PREP(VGA_DECIMATION_RATE_MASK, 0x1)); + + /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, + * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 + */ +- __phy_write(phydev, 0x11, 0xd10a); +- __phy_write(phydev, 0x12, 0x34); +- __phy_write(phydev, 0x10, 0x8f82); ++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x1, ++ MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK | ++ MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK, ++ FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x3) | ++ FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x2) | ++ FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x3) | ++ FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x2)); + + /* VcoSlicerThreshBitsHigh */ +- __phy_write(phydev, 0x11, 0x5555); +- __phy_write(phydev, 0x12, 0x55); +- __phy_write(phydev, 0x10, 0x8ec0); ++ __mtk_tr_modify(phydev, 0x1, 0xd, 0x20, ++ VCO_SLICER_THRESH_HIGH_MASK, ++ FIELD_PREP(VCO_SLICER_THRESH_HIGH_MASK, 0x555555)); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ +@@ -828,25 +915,23 @@ static void mt7988_phy_finetune(struct p + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); + + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- /* ResetSyncOffset = 5 */ +- __phy_write(phydev, 0x11, 0x500); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x8fc0); ++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x20, ++ RESET_SYNC_OFFSET_MASK, ++ FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x5)); + + /* VgaDecRate is 1 at default on mt7988 */ + +- /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7, +- * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7 +- */ +- __phy_write(phydev, 0x11, 0xb90a); +- __phy_write(phydev, 0x12, 0x6f); +- __phy_write(phydev, 0x10, 0x8f82); +- +- /* RemAckCntLimitCtrl = 1 */ +- __phy_write(phydev, 0x11, 0xfbba); +- __phy_write(phydev, 0x12, 0xc3); +- __phy_write(phydev, 0x10, 0x87f8); +- ++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x1, ++ MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK | ++ MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK, ++ FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x6) | ++ FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x7) | ++ FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x6) | ++ FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x7)); ++ ++ __mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, ++ REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, ++ FIELD_PREP(REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 0x1)); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ +@@ -927,40 +1012,36 @@ static void mt798x_phy_eee(struct phy_de + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x9690); + +- /* REG_EEE_st2TrKf1000 = 2 */ +- __phy_write(phydev, 0x11, 0x114f); +- __phy_write(phydev, 0x12, 0x2); +- __phy_write(phydev, 0x10, 0x969a); +- +- /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ +- __phy_write(phydev, 0x11, 0x3028); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x969e); +- +- /* RegEEE_slv_wake_int_timer_tar = 8 */ +- __phy_write(phydev, 0x11, 0x5010); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x96a0); +- +- /* RegEEE_trfreeze_timer2 = 586 */ +- __phy_write(phydev, 0x11, 0x24a); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x96a8); +- +- /* RegEEE100Stg1_tar = 16 */ +- __phy_write(phydev, 0x11, 0x3210); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x96b8); ++ __mtk_tr_modify(phydev, 0x2, 0xd, 0xd, ++ EEE1000_STAGE2_TR_KF_MASK, ++ FIELD_PREP(EEE1000_STAGE2_TR_KF_MASK, 0x2)); ++ ++ __mtk_tr_modify(phydev, 0x2, 0xd, 0xf, ++ SLAVE_WAKETR_TIMER_MASK | SLAVE_REMTX_TIMER_MASK, ++ FIELD_PREP(SLAVE_WAKETR_TIMER_MASK, 0x6) | ++ FIELD_PREP(SLAVE_REMTX_TIMER_MASK, 0x14)); ++ ++ __mtk_tr_modify(phydev, 0x2, 0xd, 0x10, ++ SLAVE_WAKEINT_TIMER_MASK, ++ FIELD_PREP(SLAVE_WAKEINT_TIMER_MASK, 0x8)); ++ ++ __mtk_tr_modify(phydev, 0x2, 0xd, 0x14, ++ TR_FREEZE_TIMER2_MASK, ++ FIELD_PREP(TR_FREEZE_TIMER2_MASK, 0x24a)); ++ ++ __mtk_tr_modify(phydev, 0x2, 0xd, 0x1c, ++ EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK, ++ FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK, ++ 0x10)); + + /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ + __phy_write(phydev, 0x11, 0x1463); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x96ca); + +- /* DfeTailEnableVgaThresh1000 = 27 */ +- __phy_write(phydev, 0x11, 0x36); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x8f80); ++ __mtk_tr_modify(phydev, 0x1, 0xf, 0x0, ++ DFE_TAIL_EANBLE_VGA_TRHESH_1000, ++ FIELD_PREP(DFE_TAIL_EANBLE_VGA_TRHESH_1000, 0x1b)); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); +--- a/drivers/net/phy/mediatek/mtk-ge.c ++++ b/drivers/net/phy/mediatek/mtk-ge.c +@@ -18,6 +18,10 @@ + + #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 + ++/* Registers on Token Ring debug nodes */ ++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */ ++#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15) ++ + /* Registers on MDIO_MMD_VEND1 */ + #define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13 + #define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14 +@@ -42,11 +46,8 @@ static void mtk_gephy_config_init(struct + 0, MTK_PHY_ENABLE_DOWNSHIFT); + + /* Increase SlvDPSready time */ +- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- __phy_write(phydev, 0x10, 0xafae); +- __phy_write(phydev, 0x12, 0x2f); +- __phy_write(phydev, 0x10, 0x8fae); +- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ mtk_tr_modify(phydev, 0x1, 0xf, 0x17, SLAVE_DSP_READY_TIME_MASK, ++ FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x5e)); + + /* Adjust 100_mse_threshold */ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, +--- a/drivers/net/phy/mediatek/mtk-phy-lib.c ++++ b/drivers/net/phy/mediatek/mtk-phy-lib.c +@@ -6,6 +6,69 @@ + + #include "mtk.h" + ++/* Difference between functions with mtk_tr* and __mtk_tr* prefixes is ++ * mtk_tr* functions: wrapped by page switching operations ++ * __mtk_tr* functions: no page switching operations ++ */ ++ ++static void __mtk_tr_access(struct phy_device *phydev, bool read, u8 ch_addr, ++ u8 node_addr, u8 data_addr) ++{ ++ u16 tr_cmd = BIT(15); /* bit 14 & 0 are reserved */ ++ ++ if (read) ++ tr_cmd |= BIT(13); ++ ++ tr_cmd |= (((ch_addr & 0x3) << 11) | ++ ((node_addr & 0xf) << 7) | ++ ((data_addr & 0x3f) << 1)); ++ dev_dbg(&phydev->mdio.dev, "tr_cmd: 0x%x\n", tr_cmd); ++ __phy_write(phydev, 0x10, tr_cmd); ++} ++ ++static void __mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr, ++ u8 data_addr, u16 *tr_high, u16 *tr_low) ++{ ++ __mtk_tr_access(phydev, true, ch_addr, node_addr, data_addr); ++ *tr_low = __phy_read(phydev, 0x11); ++ *tr_high = __phy_read(phydev, 0x12); ++ dev_dbg(&phydev->mdio.dev, "tr_high read: 0x%x, tr_low read: 0x%x\n", ++ *tr_high, *tr_low); ++} ++ ++static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr, ++ u8 data_addr, u32 tr_data) ++{ ++ __phy_write(phydev, 0x11, tr_data & 0xffff); ++ __phy_write(phydev, 0x12, tr_data >> 16); ++ dev_dbg(&phydev->mdio.dev, "tr_high write: 0x%x, tr_low write: 0x%x\n", ++ tr_data >> 16, tr_data & 0xffff); ++ __mtk_tr_access(phydev, false, ch_addr, node_addr, data_addr); ++} ++ ++void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, ++ u8 data_addr, u32 mask, u32 set) ++{ ++ u32 tr_data; ++ u16 tr_high; ++ u16 tr_low; ++ ++ __mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low); ++ tr_data = (tr_high << 16) | tr_low; ++ tr_data = (tr_data & ~mask) | set; ++ __mtk_tr_write(phydev, ch_addr, node_addr, data_addr, tr_data); ++} ++EXPORT_SYMBOL_GPL(__mtk_tr_modify); ++ ++void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, ++ u8 data_addr, u32 mask, u32 set) ++{ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, mask, set); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++} ++EXPORT_SYMBOL_GPL(mtk_tr_modify); ++ + int mtk_phy_read_page(struct phy_device *phydev) + { + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +--- a/drivers/net/phy/mediatek/mtk.h ++++ b/drivers/net/phy/mediatek/mtk.h +@@ -68,6 +68,11 @@ struct mtk_socphy_priv { + unsigned long led_state; + }; + ++void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, ++ u8 data_addr, u32 mask, u32 set); ++void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, ++ u8 data_addr, u32 mask, u32 set); ++ + int mtk_phy_read_page(struct phy_device *phydev); + int mtk_phy_write_page(struct phy_device *phydev, int page); + diff --git a/target/linux/generic/backport-6.12/731-v6.15-net-phy-mediatek-Add-token-ring-set-bit-operation-su.patch b/target/linux/generic/backport-6.12/731-v6.15-net-phy-mediatek-Add-token-ring-set-bit-operation-su.patch new file mode 100644 index 0000000000..972a9c0a7e --- /dev/null +++ b/target/linux/generic/backport-6.12/731-v6.15-net-phy-mediatek-Add-token-ring-set-bit-operation-su.patch @@ -0,0 +1,73 @@ +From c7e2fb3421ef5ebbb4c91f44bd735ab10edd755a Mon Sep 17 00:00:00 2001 +From: Sky Huang +Date: Thu, 13 Feb 2025 16:05:51 +0800 +Subject: [PATCH 12/20] net: phy: mediatek: Add token ring set bit operation + support + +Previously in mtk-ge-soc.c, we set some register bits via token +ring, which were implemented in three __phy_write(). +Now we can do the same thing via __mtk_tr_set_bits() helper. + +Signed-off-by: Sky Huang +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/20250213080553.921434-4-SkyLake.Huang@mediatek.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/mediatek/mtk-ge-soc.c | 10 ++++++---- + drivers/net/phy/mediatek/mtk-phy-lib.c | 7 +++++++ + drivers/net/phy/mediatek/mtk.h | 2 ++ + 3 files changed, 15 insertions(+), 4 deletions(-) + +--- a/drivers/net/phy/mediatek/mtk-ge-soc.c ++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c +@@ -62,6 +62,10 @@ + /* MasDSPreadyTime */ + #define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7) + ++/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */ ++/* EnabRandUpdTrig */ ++#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER BIT(8) ++ + /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */ + /* ResetSyncOffset */ + #define RESET_SYNC_OFFSET_MASK GENMASK(11, 8) +@@ -789,10 +793,8 @@ static void mt798x_phy_common_finetune(s + FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) | + FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18)); + +- /* EnabRandUpdTrig = 1 */ +- __phy_write(phydev, 0x11, 0x2f00); +- __phy_write(phydev, 0x12, 0xe); +- __phy_write(phydev, 0x10, 0x8fb0); ++ __mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18, ++ ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER); + + __mtk_tr_modify(phydev, 0x0, 0x7, 0x15, + NORMAL_MSE_LO_THRESH_MASK, +--- a/drivers/net/phy/mediatek/mtk-phy-lib.c ++++ b/drivers/net/phy/mediatek/mtk-phy-lib.c +@@ -69,6 +69,13 @@ void mtk_tr_modify(struct phy_device *ph + } + EXPORT_SYMBOL_GPL(mtk_tr_modify); + ++void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, ++ u8 data_addr, u32 set) ++{ ++ __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, 0, set); ++} ++EXPORT_SYMBOL_GPL(__mtk_tr_set_bits); ++ + int mtk_phy_read_page(struct phy_device *phydev) + { + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +--- a/drivers/net/phy/mediatek/mtk.h ++++ b/drivers/net/phy/mediatek/mtk.h +@@ -72,6 +72,8 @@ void __mtk_tr_modify(struct phy_device * + u8 data_addr, u32 mask, u32 set); + void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr, u32 mask, u32 set); ++void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, ++ u8 data_addr, u32 set); + + int mtk_phy_read_page(struct phy_device *phydev); + int mtk_phy_write_page(struct phy_device *phydev, int page); diff --git a/target/linux/generic/backport-6.12/732-v6.15-net-phy-mediatek-Add-token-ring-clear-bit-operation-.patch b/target/linux/generic/backport-6.12/732-v6.15-net-phy-mediatek-Add-token-ring-clear-bit-operation-.patch new file mode 100644 index 0000000000..47d891ea69 --- /dev/null +++ b/target/linux/generic/backport-6.12/732-v6.15-net-phy-mediatek-Add-token-ring-clear-bit-operation-.patch @@ -0,0 +1,122 @@ +From 7851c73a416b15aff6f9ada9c88affc5f48ff011 Mon Sep 17 00:00:00 2001 +From: Sky Huang +Date: Thu, 13 Feb 2025 16:05:52 +0800 +Subject: [PATCH 13/20] net: phy: mediatek: Add token ring clear bit operation + support + +Similar to __mtk_tr_set_bits() support. Previously in mtk-ge-soc.c, +we clear some register bits via token ring, which were also implemented +in three __phy_write(). Now we can do the same thing via +__mtk_tr_clr_bits() helper. + +Signed-off-by: Sky Huang +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/20250213080553.921434-5-SkyLake.Huang@mediatek.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/mediatek/mtk-ge-soc.c | 30 +++++++++++++++----------- + drivers/net/phy/mediatek/mtk-phy-lib.c | 7 ++++++ + drivers/net/phy/mediatek/mtk.h | 2 ++ + 3 files changed, 27 insertions(+), 12 deletions(-) + +--- a/drivers/net/phy/mediatek/mtk-ge-soc.c ++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c +@@ -76,6 +76,10 @@ + /* FfeUpdGainForce */ + #define FFE_UPDATE_GAIN_FORCE BIT(6) + ++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */ ++/* TrFreeze */ ++#define TR_FREEZE_MASK GENMASK(11, 0) ++ + /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */ + /* SS: Steady-state, KP: Proportional Gain */ + /* SSTrKp100 */ +@@ -91,6 +95,11 @@ + /* SSTrKf1000Slv */ + #define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4) + ++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */ ++/* clear this bit if wanna select from AFE */ ++/* Regsigdet_sel_1000 */ ++#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE BIT(4) ++ + /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */ + /* RegEEE_st2TrKf1000 */ + #define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11) +@@ -113,6 +122,10 @@ + /* RegEEE100Stg1_tar */ + #define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0) + ++/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */ ++/* REGEEE_wake_slv_tr_wait_dfesigdet_en */ ++#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN BIT(11) ++ + #define ANALOG_INTERNAL_OPERATION_MAX_US 20 + #define TXRESERVE_MIN 0 + #define TXRESERVE_MAX 7 +@@ -805,10 +818,7 @@ static void mt798x_phy_common_finetune(s + FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) | + FFE_UPDATE_GAIN_FORCE); + +- /* TrFreeze = 0 (mt7988 default) */ +- __phy_write(phydev, 0x11, 0x0); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x9686); ++ __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK); + + __mtk_tr_modify(phydev, 0x2, 0xd, 0x6, + SS_TR_KP100_MASK | SS_TR_KF100_MASK | +@@ -1009,10 +1019,8 @@ static void mt798x_phy_eee(struct phy_de + MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); + + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- /* Regsigdet_sel_1000 = 0 */ +- __phy_write(phydev, 0x11, 0xb); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x9690); ++ __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8, ++ EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE); + + __mtk_tr_modify(phydev, 0x2, 0xd, 0xd, + EEE1000_STAGE2_TR_KF_MASK, +@@ -1036,10 +1044,8 @@ static void mt798x_phy_eee(struct phy_de + FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK, + 0x10)); + +- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ +- __phy_write(phydev, 0x11, 0x1463); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x96ca); ++ __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25, ++ WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN); + + __mtk_tr_modify(phydev, 0x1, 0xf, 0x0, + DFE_TAIL_EANBLE_VGA_TRHESH_1000, +--- a/drivers/net/phy/mediatek/mtk-phy-lib.c ++++ b/drivers/net/phy/mediatek/mtk-phy-lib.c +@@ -76,6 +76,13 @@ void __mtk_tr_set_bits(struct phy_device + } + EXPORT_SYMBOL_GPL(__mtk_tr_set_bits); + ++void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, ++ u8 data_addr, u32 clr) ++{ ++ __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, clr, 0); ++} ++EXPORT_SYMBOL_GPL(__mtk_tr_clr_bits); ++ + int mtk_phy_read_page(struct phy_device *phydev) + { + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +--- a/drivers/net/phy/mediatek/mtk.h ++++ b/drivers/net/phy/mediatek/mtk.h +@@ -74,6 +74,8 @@ void mtk_tr_modify(struct phy_device *ph + u8 data_addr, u32 mask, u32 set); + void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, + u8 data_addr, u32 set); ++void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, ++ u8 data_addr, u32 clr); + + int mtk_phy_read_page(struct phy_device *phydev); + int mtk_phy_write_page(struct phy_device *phydev, int page); diff --git a/target/linux/generic/backport-6.12/733-v6.15-net-phy-mediatek-Move-some-macros-to-phy-lib-for-lat.patch b/target/linux/generic/backport-6.12/733-v6.15-net-phy-mediatek-Move-some-macros-to-phy-lib-for-lat.patch new file mode 100644 index 0000000000..858de093a2 --- /dev/null +++ b/target/linux/generic/backport-6.12/733-v6.15-net-phy-mediatek-Move-some-macros-to-phy-lib-for-lat.patch @@ -0,0 +1,45 @@ +From bae8c61522c4d5a5250a24dcb57d120ea593fab1 Mon Sep 17 00:00:00 2001 +From: Sky Huang +Date: Thu, 13 Feb 2025 16:05:53 +0800 +Subject: [PATCH 14/20] net: phy: mediatek: Move some macros to phy-lib for + later use + +Move some macros to phy-lib because MediaTek's 2.5G built-in +ethernet PHY will also use them. + +Signed-off-by: Sky Huang +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/20250213080553.921434-6-SkyLake.Huang@mediatek.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/mediatek/mtk-ge.c | 4 ---- + drivers/net/phy/mediatek/mtk.h | 4 ++++ + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/net/phy/mediatek/mtk-ge.c ++++ b/drivers/net/phy/mediatek/mtk-ge.c +@@ -8,10 +8,6 @@ + #define MTK_GPHY_ID_MT7530 0x03a29412 + #define MTK_GPHY_ID_MT7531 0x03a29441 + +-#define MTK_PHY_PAGE_EXTENDED_1 0x0001 +-#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14 +-#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4) +- + #define MTK_PHY_PAGE_EXTENDED_2 0x0002 + #define MTK_PHY_PAGE_EXTENDED_3 0x0003 + #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11 +--- a/drivers/net/phy/mediatek/mtk.h ++++ b/drivers/net/phy/mediatek/mtk.h +@@ -8,7 +8,11 @@ + #ifndef _MTK_EPHY_H_ + #define _MTK_EPHY_H_ + ++#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14 ++#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4) ++ + #define MTK_EXT_PAGE_ACCESS 0x1f ++#define MTK_PHY_PAGE_EXTENDED_1 0x0001 + #define MTK_PHY_PAGE_STANDARD 0x0000 + #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 + diff --git a/target/linux/generic/backport-6.12/735-v6.16-net-phy-mediatek-permit-to-compile-test-GE-SOC-PHY-d.patch b/target/linux/generic/backport-6.12/735-v6.16-net-phy-mediatek-permit-to-compile-test-GE-SOC-PHY-d.patch new file mode 100644 index 0000000000..9778ea158b --- /dev/null +++ b/target/linux/generic/backport-6.12/735-v6.16-net-phy-mediatek-permit-to-compile-test-GE-SOC-PHY-d.patch @@ -0,0 +1,37 @@ +From e5566162af8b9690e096d2e6089e4ed955a0d13d Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 10 Apr 2025 12:04:03 +0200 +Subject: [PATCH] net: phy: mediatek: permit to compile test GE SOC PHY driver + +When commit 462a3daad679 ("net: phy: mediatek: fix compile-test +dependencies") fixed the dependency, it should have also introduced +an or on COMPILE_TEST to permit this driver to be compile-tested even if +NVMEM_MTK_EFUSE wasn't selected. The driver makes use of NVMEM API that +are always compiled (return error) so the driver can actually be +compiled even without that config. + +Fix and simplify the dependency condition of this kernel config. + +Fixes: 462a3daad679 ("net: phy: mediatek: fix compile-test dependencies") +Acked-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: Christian Marangi +Acked-by: Arnd Bergmann +Link: https://patch.msgid.link/20250410100410.348-1-ansuelsmth@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/mediatek/Kconfig | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/net/phy/mediatek/Kconfig ++++ b/drivers/net/phy/mediatek/Kconfig +@@ -15,8 +15,7 @@ config MEDIATEK_GE_PHY + + config MEDIATEK_GE_SOC_PHY + tristate "MediaTek SoC Ethernet PHYs" +- depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST +- depends on NVMEM_MTK_EFUSE ++ depends on (ARM64 && ARCH_MEDIATEK && NVMEM_MTK_EFUSE) || COMPILE_TEST + select MTK_NET_PHYLIB + help + Supports MediaTek SoC built-in Gigabit Ethernet PHYs. diff --git a/target/linux/generic/backport-6.12/736-v6.16-net-phy-mediatek-add-Airoha-PHY-ID-to-SoC-driver.patch b/target/linux/generic/backport-6.12/736-v6.16-net-phy-mediatek-add-Airoha-PHY-ID-to-SoC-driver.patch new file mode 100644 index 0000000000..5498ecbd21 --- /dev/null +++ b/target/linux/generic/backport-6.12/736-v6.16-net-phy-mediatek-add-Airoha-PHY-ID-to-SoC-driver.patch @@ -0,0 +1,129 @@ +From 4590c8bc10951feee3e439bf7fff1b458c2e6fad Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 10 Apr 2025 12:04:04 +0200 +Subject: [PATCH 17/20] net: phy: mediatek: add Airoha PHY ID to SoC driver + +Airoha AN7581 SoC ship with a Switch based on the MT753x Switch embedded +in other SoC like the MT7581 and the MT7988. Similar to these they +require configuring some pin to enable LED PHYs. + +Add support for the PHY ID for the Airoha embedded Switch and define a +simple probe function to toggle these pins. Also fill the LED functions +and add dedicated function to define LED polarity. + +Reviewed-by: Andrew Lunn +Signed-off-by: Christian Marangi +Link: https://patch.msgid.link/20250410100410.348-2-ansuelsmth@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/mediatek/Kconfig | 4 +- + drivers/net/phy/mediatek/mtk-ge-soc.c | 62 +++++++++++++++++++++++++++ + 2 files changed, 65 insertions(+), 1 deletion(-) + +--- a/drivers/net/phy/mediatek/Kconfig ++++ b/drivers/net/phy/mediatek/Kconfig +@@ -15,7 +15,9 @@ config MEDIATEK_GE_PHY + + config MEDIATEK_GE_SOC_PHY + tristate "MediaTek SoC Ethernet PHYs" +- depends on (ARM64 && ARCH_MEDIATEK && NVMEM_MTK_EFUSE) || COMPILE_TEST ++ depends on ARM64 || COMPILE_TEST ++ depends on ARCH_AIROHA || (ARCH_MEDIATEK && NVMEM_MTK_EFUSE) || \ ++ COMPILE_TEST + select MTK_NET_PHYLIB + help + Supports MediaTek SoC built-in Gigabit Ethernet PHYs. +--- a/drivers/net/phy/mediatek/mtk-ge-soc.c ++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c +@@ -10,8 +10,11 @@ + + #include "mtk.h" + ++#define MTK_PHY_MAX_LEDS 2 ++ + #define MTK_GPHY_ID_MT7981 0x03a29461 + #define MTK_GPHY_ID_MT7988 0x03a29481 ++#define MTK_GPHY_ID_AN7581 0x03a294c1 + + #define MTK_EXT_PAGE_ACCESS 0x1f + #define MTK_PHY_PAGE_STANDARD 0x0000 +@@ -1405,6 +1408,53 @@ static int mt7981_phy_probe(struct phy_d + return mt798x_phy_calibration(phydev); + } + ++static int an7581_phy_probe(struct phy_device *phydev) ++{ ++ struct mtk_socphy_priv *priv; ++ struct pinctrl *pinctrl; ++ ++ /* Toggle pinctrl to enable PHY LED */ ++ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); ++ if (IS_ERR(pinctrl)) ++ dev_err(&phydev->mdio.bus->dev, ++ "Failed to setup PHY LED pinctrl\n"); ++ ++ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ phydev->priv = priv; ++ ++ return 0; ++} ++ ++static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index, ++ unsigned long modes) ++{ ++ u32 mode; ++ u16 val; ++ ++ if (index >= MTK_PHY_MAX_LEDS) ++ return -EINVAL; ++ ++ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { ++ switch (mode) { ++ case PHY_LED_ACTIVE_LOW: ++ val = MTK_PHY_LED_ON_POLARITY; ++ break; ++ case PHY_LED_ACTIVE_HIGH: ++ val = 0; ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ ++ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? ++ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, ++ MTK_PHY_LED_ON_POLARITY, val); ++} ++ + static struct phy_driver mtk_socphy_driver[] = { + { + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), +@@ -1440,6 +1490,17 @@ static struct phy_driver mtk_socphy_driv + .led_hw_control_set = mt798x_phy_led_hw_control_set, + .led_hw_control_get = mt798x_phy_led_hw_control_get, + }, ++ { ++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581), ++ .name = "Airoha AN7581 PHY", ++ .probe = an7581_phy_probe, ++ .led_blink_set = mt798x_phy_led_blink_set, ++ .led_brightness_set = mt798x_phy_led_brightness_set, ++ .led_hw_is_supported = mt798x_phy_led_hw_is_supported, ++ .led_hw_control_set = mt798x_phy_led_hw_control_set, ++ .led_hw_control_get = mt798x_phy_led_hw_control_get, ++ .led_polarity_set = an7581_phy_led_polarity_set, ++ }, + }; + + module_phy_driver(mtk_socphy_driver); +@@ -1447,6 +1508,7 @@ module_phy_driver(mtk_socphy_driver); + static const struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, ++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581) }, + { } + }; + diff --git a/target/linux/generic/backport-6.12/737-v6.16-net-phy-mediatek-init-val-in-.phy_led_polarity_set-f.patch b/target/linux/generic/backport-6.12/737-v6.16-net-phy-mediatek-init-val-in-.phy_led_polarity_set-f.patch new file mode 100644 index 0000000000..1b1dda2327 --- /dev/null +++ b/target/linux/generic/backport-6.12/737-v6.16-net-phy-mediatek-init-val-in-.phy_led_polarity_set-f.patch @@ -0,0 +1,40 @@ +From 34501d047ac0a6cbb13285ba9d15f75c1deb7da7 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Tue, 15 Apr 2025 12:53:05 +0200 +Subject: [PATCH 18/20] net: phy: mediatek: init val in .phy_led_polarity_set + for AN7581 + +Fix smatch warning for uninitialised val in .phy_led_polarity_set for +AN7581 driver. + +Correctly init to 0 to set polarity high by default. + +Reported-by: Simon Horman +Fixes: 6a325aed130b ("net: phy: mediatek: add Airoha PHY ID to SoC driver") +Signed-off-by: Christian Marangi +Link: https://patch.msgid.link/20250415105313.3409-1-ansuelsmth@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/mediatek/mtk-ge-soc.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/net/phy/mediatek/mtk-ge-soc.c ++++ b/drivers/net/phy/mediatek/mtk-ge-soc.c +@@ -1431,8 +1431,8 @@ static int an7581_phy_probe(struct phy_d + static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index, + unsigned long modes) + { ++ u16 val = 0; + u32 mode; +- u16 val; + + if (index >= MTK_PHY_MAX_LEDS) + return -EINVAL; +@@ -1443,7 +1443,6 @@ static int an7581_phy_led_polarity_set(s + val = MTK_PHY_LED_ON_POLARITY; + break; + case PHY_LED_ACTIVE_HIGH: +- val = 0; + break; + default: + return -EINVAL; diff --git a/target/linux/generic/backport-6.12/753-v6.15-net-ethernet-mediatek-add-EEE-support.patch b/target/linux/generic/backport-6.12/753-v6.15-net-ethernet-mediatek-add-EEE-support.patch index 9d26480bdf..2ca3f2ef00 100644 --- a/target/linux/generic/backport-6.12/753-v6.15-net-ethernet-mediatek-add-EEE-support.patch +++ b/target/linux/generic/backport-6.12/753-v6.15-net-ethernet-mediatek-add-EEE-support.patch @@ -43,7 +43,7 @@ Signed-off-by: Qingfang Deng return phylink_ethtool_set_pauseparam(mac->phylink, pause); } -+static int mtk_get_eee(struct net_device *dev, struct ethtool_eee *eee) ++static int mtk_get_eee(struct net_device *dev, struct ethtool_keee *eee) +{ + struct mtk_mac *mac = netdev_priv(dev); + u32 reg; @@ -60,7 +60,7 @@ Signed-off-by: Qingfang Deng + return 0; +} + -+static int mtk_set_eee(struct net_device *dev, struct ethtool_eee *eee) ++static int mtk_set_eee(struct net_device *dev, struct ethtool_keee *eee) +{ + struct mtk_mac *mac = netdev_priv(dev); + u32 txidle_thd_ms, reg; diff --git a/target/linux/generic/backport-6.12/780-01-v6.13-r8169-remove-original-workaround-for-RTL8125-broken-.patch b/target/linux/generic/backport-6.12/780-01-v6.13-r8169-remove-original-workaround-for-RTL8125-broken-.patch index 46d41fb262..080dae31e6 100644 --- a/target/linux/generic/backport-6.12/780-01-v6.13-r8169-remove-original-workaround-for-RTL8125-broken-.patch +++ b/target/linux/generic/backport-6.12/780-01-v6.13-r8169-remove-original-workaround-for-RTL8125-broken-.patch @@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c -@@ -4777,11 +4777,7 @@ static void r8169_phylink_handler(struct +@@ -4804,11 +4804,7 @@ static void r8169_phylink_handler(struct if (netif_carrier_ok(ndev)) { rtl_link_chg_patch(tp); pm_request_resume(d); diff --git a/target/linux/generic/backport-6.12/780-02-v6.13-r8169-enable-SG-TSO-on-selected-chip-versions-per-de.patch b/target/linux/generic/backport-6.12/780-02-v6.13-r8169-enable-SG-TSO-on-selected-chip-versions-per-de.patch index 5a27cc4b52..f7d2d23c2a 100644 --- a/target/linux/generic/backport-6.12/780-02-v6.13-r8169-enable-SG-TSO-on-selected-chip-versions-per-de.patch +++ b/target/linux/generic/backport-6.12/780-02-v6.13-r8169-enable-SG-TSO-on-selected-chip-versions-per-de.patch @@ -20,7 +20,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c -@@ -5489,11 +5489,6 @@ static int rtl_init_one(struct pci_dev * +@@ -5517,11 +5517,6 @@ static int rtl_init_one(struct pci_dev * dev->features |= dev->hw_features; @@ -32,7 +32,7 @@ Signed-off-by: David S. Miller if (rtl_chip_supports_csum_v2(tp)) { dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); -@@ -5504,6 +5499,17 @@ static int rtl_init_one(struct pci_dev * +@@ -5532,6 +5527,17 @@ static int rtl_init_one(struct pci_dev * netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); } diff --git a/target/linux/generic/backport-6.12/780-03-v6.13-r8169-implement-additional-ethtool-stats-ops.patch b/target/linux/generic/backport-6.12/780-03-v6.13-r8169-implement-additional-ethtool-stats-ops.patch index bb0b77e6a3..cef8e1e471 100644 --- a/target/linux/generic/backport-6.12/780-03-v6.13-r8169-implement-additional-ethtool-stats-ops.patch +++ b/target/linux/generic/backport-6.12/780-03-v6.13-r8169-implement-additional-ethtool-stats-ops.patch @@ -118,7 +118,7 @@ Signed-off-by: Jakub Kicinski }; static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) -@@ -3893,6 +3972,9 @@ static void rtl_hw_start_8125(struct rtl +@@ -3920,6 +3999,9 @@ static void rtl_hw_start_8125(struct rtl break; } diff --git a/target/linux/generic/backport-6.12/780-04-v6.13-r8169-don-t-take-RTNL-lock-in-rtl_task.patch b/target/linux/generic/backport-6.12/780-04-v6.13-r8169-don-t-take-RTNL-lock-in-rtl_task.patch index 77e7b4321e..ef360d062a 100644 --- a/target/linux/generic/backport-6.12/780-04-v6.13-r8169-don-t-take-RTNL-lock-in-rtl_task.patch +++ b/target/linux/generic/backport-6.12/780-04-v6.13-r8169-don-t-take-RTNL-lock-in-rtl_task.patch @@ -18,7 +18,7 @@ Signed-off-by: Andrew Lunn --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c -@@ -4800,10 +4800,8 @@ static void rtl_task(struct work_struct +@@ -4827,10 +4827,8 @@ static void rtl_task(struct work_struct container_of(work, struct rtl8169_private, wk.work); int ret; @@ -30,7 +30,7 @@ Signed-off-by: Andrew Lunn if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { /* if chip isn't accessible, reset bus to revive it */ -@@ -4812,7 +4810,7 @@ static void rtl_task(struct work_struct +@@ -4839,7 +4837,7 @@ static void rtl_task(struct work_struct if (ret < 0) { netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); netif_device_detach(tp->dev); @@ -39,7 +39,7 @@ Signed-off-by: Andrew Lunn } } -@@ -4831,8 +4829,6 @@ reset: +@@ -4858,8 +4856,6 @@ reset: } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { rtl_reset_work(tp); } diff --git a/target/linux/generic/backport-6.12/780-05-v6.13-replace-custom-flag-with-disable_work-et-al.patch b/target/linux/generic/backport-6.12/780-05-v6.13-replace-custom-flag-with-disable_work-et-al.patch index f6409c321c..304515fe81 100644 --- a/target/linux/generic/backport-6.12/780-05-v6.13-replace-custom-flag-with-disable_work-et-al.patch +++ b/target/linux/generic/backport-6.12/780-05-v6.13-replace-custom-flag-with-disable_work-et-al.patch @@ -39,7 +39,7 @@ Signed-off-by: Andrew Lunn } static void rtl8169_init_phy(struct rtl8169_private *tp) -@@ -4800,9 +4797,6 @@ static void rtl_task(struct work_struct +@@ -4827,9 +4824,6 @@ static void rtl_task(struct work_struct container_of(work, struct rtl8169_private, wk.work); int ret; @@ -49,7 +49,7 @@ Signed-off-by: Andrew Lunn if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { /* if chip isn't accessible, reset bus to revive it */ if (RTL_R32(tp, TxConfig) == ~0) { -@@ -4886,6 +4880,7 @@ static int r8169_phy_connect(struct rtl8 +@@ -4913,6 +4907,7 @@ static int r8169_phy_connect(struct rtl8 static void rtl8169_down(struct rtl8169_private *tp) { @@ -57,7 +57,7 @@ Signed-off-by: Andrew Lunn /* Clear all task flags */ bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); -@@ -4914,7 +4909,7 @@ static void rtl8169_up(struct rtl8169_pr +@@ -4941,7 +4936,7 @@ static void rtl8169_up(struct rtl8169_pr phy_resume(tp->phydev); rtl8169_init_phy(tp); napi_enable(&tp->napi); @@ -66,7 +66,7 @@ Signed-off-by: Andrew Lunn rtl_reset_work(tp); phy_start(tp->phydev); -@@ -4931,8 +4926,6 @@ static int rtl8169_close(struct net_devi +@@ -4958,8 +4953,6 @@ static int rtl8169_close(struct net_devi rtl8169_down(tp); rtl8169_rx_clear(tp); @@ -75,7 +75,7 @@ Signed-off-by: Andrew Lunn free_irq(tp->irq, tp); phy_disconnect(tp->phydev); -@@ -5165,7 +5158,7 @@ static void rtl_remove_one(struct pci_de +@@ -5192,7 +5185,7 @@ static void rtl_remove_one(struct pci_de if (pci_dev_run_wake(pdev)) pm_runtime_get_noresume(&pdev->dev); @@ -84,7 +84,7 @@ Signed-off-by: Andrew Lunn if (IS_ENABLED(CONFIG_R8169_LEDS)) r8169_remove_leds(tp->leds); -@@ -5542,6 +5535,7 @@ static int rtl_init_one(struct pci_dev * +@@ -5570,6 +5563,7 @@ static int rtl_init_one(struct pci_dev * tp->irq = pci_irq_vector(pdev, 0); INIT_WORK(&tp->wk.work, rtl_task); diff --git a/target/linux/generic/backport-6.12/780-09-v6.13-r8169-add-support-for-RTL8125D.patch b/target/linux/generic/backport-6.12/780-09-v6.13-r8169-add-support-for-RTL8125D.patch index 8bb9916cee..627c2befdd 100644 --- a/target/linux/generic/backport-6.12/780-09-v6.13-r8169-add-support-for-RTL8125D.patch +++ b/target/linux/generic/backport-6.12/780-09-v6.13-r8169-add-support-for-RTL8125D.patch @@ -86,7 +86,7 @@ Signed-off-by: Jakub Kicinski RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | RX_PAUSE_SLOT_ON); break; -@@ -3871,6 +3872,12 @@ static void rtl_hw_start_8125b(struct rt +@@ -3897,6 +3898,12 @@ static void rtl_hw_start_8125b(struct rt rtl_hw_start_8125_common(tp); } @@ -98,8 +98,8 @@ Signed-off-by: Jakub Kicinski + static void rtl_hw_start_8126a(struct rtl8169_private *tp) { - rtl_set_def_aspm_entry_latency(tp); -@@ -3919,6 +3926,7 @@ static void rtl_hw_config(struct rtl8169 + rtl_disable_zrxdc_timeout(tp); +@@ -3946,6 +3953,7 @@ static void rtl_hw_config(struct rtl8169 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, @@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a, [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a, }; -@@ -3936,6 +3944,7 @@ static void rtl_hw_start_8125(struct rtl +@@ -3963,6 +3971,7 @@ static void rtl_hw_start_8125(struct rtl /* disable interrupt coalescing */ switch (tp->mac_version) { case RTL_GIGA_MAC_VER_61: diff --git a/target/linux/generic/backport-6.12/780-14-v6.13-r8169-improve-initialization-of-RSS-registers-on-RTL.patch b/target/linux/generic/backport-6.12/780-14-v6.13-r8169-improve-initialization-of-RSS-registers-on-RTL.patch index fc6ea34b59..f8777b897a 100644 --- a/target/linux/generic/backport-6.12/780-14-v6.13-r8169-improve-initialization-of-RSS-registers-on-RTL.patch +++ b/target/linux/generic/backport-6.12/780-14-v6.13-r8169-improve-initialization-of-RSS-registers-on-RTL.patch @@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski EEE_TXIDLE_TIMER_8125 = 0x6048, }; -@@ -3765,8 +3767,8 @@ static void rtl_hw_start_8125_common(str +@@ -3791,8 +3793,8 @@ static void rtl_hw_start_8125_common(str rtl_pcie_state_l2l3_disable(tp); RTL_W16(tp, 0x382, 0x221b); diff --git a/target/linux/generic/backport-6.12/780-15-v6.13-r8169-remove-leftover-locks-after-reverted-change.patch b/target/linux/generic/backport-6.12/780-15-v6.13-r8169-remove-leftover-locks-after-reverted-change.patch index d8a3eb0029..7af3abacfb 100644 --- a/target/linux/generic/backport-6.12/780-15-v6.13-r8169-remove-leftover-locks-after-reverted-change.patch +++ b/target/linux/generic/backport-6.12/780-15-v6.13-r8169-remove-leftover-locks-after-reverted-change.patch @@ -102,7 +102,7 @@ Signed-off-by: Jakub Kicinski switch (tp->mac_version) { case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: -@@ -5451,8 +5428,6 @@ static int rtl_init_one(struct pci_dev * +@@ -5479,8 +5456,6 @@ static int rtl_init_one(struct pci_dev * tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; tp->ocp_base = OCP_STD_PHY_BASE; diff --git a/target/linux/generic/backport-6.12/780-20-v6.13-r8169-copy-vendor-driver-2.5G-5G-EEE-advertisement-c.patch b/target/linux/generic/backport-6.12/780-20-v6.13-r8169-copy-vendor-driver-2.5G-5G-EEE-advertisement-c.patch index 96518cc6c4..a88283903a 100644 --- a/target/linux/generic/backport-6.12/780-20-v6.13-r8169-copy-vendor-driver-2.5G-5G-EEE-advertisement-c.patch +++ b/target/linux/generic/backport-6.12/780-20-v6.13-r8169-copy-vendor-driver-2.5G-5G-EEE-advertisement-c.patch @@ -22,7 +22,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c -@@ -5227,6 +5227,11 @@ static int r8169_mdio_register(struct rt +@@ -5255,6 +5255,11 @@ static int r8169_mdio_register(struct rt phy_support_eee(tp->phydev); phy_support_asym_pause(tp->phydev); diff --git a/target/linux/generic/backport-6.12/780-21-v6.14-r8169-remove-unused-flag-RTL_FLAG_TASK_RESET_NO_QUEU.patch b/target/linux/generic/backport-6.12/780-21-v6.14-r8169-remove-unused-flag-RTL_FLAG_TASK_RESET_NO_QUEU.patch index 5b1e633a63..ad938baec0 100644 --- a/target/linux/generic/backport-6.12/780-21-v6.14-r8169-remove-unused-flag-RTL_FLAG_TASK_RESET_NO_QUEU.patch +++ b/target/linux/generic/backport-6.12/780-21-v6.14-r8169-remove-unused-flag-RTL_FLAG_TASK_RESET_NO_QUEU.patch @@ -24,7 +24,7 @@ Signed-off-by: Jakub Kicinski RTL_FLAG_TASK_TX_TIMEOUT, RTL_FLAG_MAX }; -@@ -4722,8 +4721,6 @@ static void rtl_task(struct work_struct +@@ -4749,8 +4748,6 @@ static void rtl_task(struct work_struct reset: rtl_reset_work(tp); netif_wake_queue(tp->dev); diff --git a/target/linux/generic/backport-6.12/780-22-v6.14-r8169-remove-support-for-chip-version-11.patch b/target/linux/generic/backport-6.12/780-22-v6.14-r8169-remove-support-for-chip-version-11.patch index e67e41d676..6753d70ab8 100644 --- a/target/linux/generic/backport-6.12/780-22-v6.14-r8169-remove-support-for-chip-version-11.patch +++ b/target/linux/generic/backport-6.12/780-22-v6.14-r8169-remove-support-for-chip-version-11.patch @@ -47,7 +47,7 @@ Signed-off-by: Jakub Kicinski * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, */ -@@ -3802,7 +3801,6 @@ static void rtl_hw_config(struct rtl8169 +@@ -3829,7 +3828,6 @@ static void rtl_hw_config(struct rtl8169 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, [RTL_GIGA_MAC_VER_10] = NULL, @@ -55,7 +55,7 @@ Signed-off-by: Jakub Kicinski [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, -@@ -4678,12 +4676,6 @@ static irqreturn_t rtl8169_interrupt(int +@@ -4705,12 +4703,6 @@ static irqreturn_t rtl8169_interrupt(int if (status & LinkChg) phy_mac_interrupt(tp->phydev); @@ -68,7 +68,7 @@ Signed-off-by: Jakub Kicinski rtl_irq_disable(tp); napi_schedule(&tp->napi); out: -@@ -5099,9 +5091,6 @@ static void rtl_set_irq_mask(struct rtl8 +@@ -5126,9 +5118,6 @@ static void rtl_set_irq_mask(struct rtl8 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) tp->irq_mask |= SYSErr | RxFIFOOver; @@ -78,7 +78,7 @@ Signed-off-by: Jakub Kicinski } static int rtl_alloc_irq(struct rtl8169_private *tp) -@@ -5295,7 +5284,6 @@ static int rtl_jumbo_max(struct rtl8169_ +@@ -5323,7 +5312,6 @@ static int rtl_jumbo_max(struct rtl8169_ case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: return JUMBO_7K; /* RTL8168b */ diff --git a/target/linux/generic/backport-6.12/780-23-v6.14-r8169-adjust-version-numbering-for-RTL8126.patch b/target/linux/generic/backport-6.12/780-23-v6.14-r8169-adjust-version-numbering-for-RTL8126.patch index f769744444..c3a82985f1 100644 --- a/target/linux/generic/backport-6.12/780-23-v6.14-r8169-adjust-version-numbering-for-RTL8126.patch +++ b/target/linux/generic/backport-6.12/780-23-v6.14-r8169-adjust-version-numbering-for-RTL8126.patch @@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); -@@ -2900,7 +2900,7 @@ static void rtl_enable_exit_l1(struct rt +@@ -2926,7 +2926,7 @@ static void rtl_enable_exit_l1(struct rt case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: rtl_eri_set_bits(tp, 0xd4, 0x0c00); break; @@ -116,7 +116,7 @@ Signed-off-by: Jakub Kicinski r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); break; default: -@@ -2914,7 +2914,7 @@ static void rtl_disable_exit_l1(struct r +@@ -2940,7 +2940,7 @@ static void rtl_disable_exit_l1(struct r case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: rtl_eri_clear_bits(tp, 0xd4, 0x1f00); break; @@ -125,7 +125,7 @@ Signed-off-by: Jakub Kicinski r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); break; default: -@@ -2940,8 +2940,8 @@ static void rtl_hw_aspm_clkreq_enable(st +@@ -2966,8 +2966,8 @@ static void rtl_hw_aspm_clkreq_enable(st rtl_mod_config5(tp, 0, ASPM_en); switch (tp->mac_version) { @@ -136,7 +136,7 @@ Signed-off-by: Jakub Kicinski val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; RTL_W8(tp, INT_CFG0_8125, val8); break; -@@ -2952,7 +2952,7 @@ static void rtl_hw_aspm_clkreq_enable(st +@@ -2978,7 +2978,7 @@ static void rtl_hw_aspm_clkreq_enable(st switch (tp->mac_version) { case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: @@ -145,7 +145,7 @@ Signed-off-by: Jakub Kicinski /* reset ephy tx/rx disable timer */ r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); /* chip can trigger L1.2 */ -@@ -2964,7 +2964,7 @@ static void rtl_hw_aspm_clkreq_enable(st +@@ -2990,7 +2990,7 @@ static void rtl_hw_aspm_clkreq_enable(st } else { switch (tp->mac_version) { case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: @@ -154,7 +154,7 @@ Signed-off-by: Jakub Kicinski r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); break; default: -@@ -2972,8 +2972,8 @@ static void rtl_hw_aspm_clkreq_enable(st +@@ -2998,8 +2998,8 @@ static void rtl_hw_aspm_clkreq_enable(st } switch (tp->mac_version) { @@ -165,7 +165,7 @@ Signed-off-by: Jakub Kicinski val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; RTL_W8(tp, INT_CFG0_8125, val8); break; -@@ -3693,12 +3693,12 @@ static void rtl_hw_start_8125_common(str +@@ -3719,12 +3719,12 @@ static void rtl_hw_start_8125_common(str /* disable new tx descriptor format */ r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); @@ -182,7 +182,7 @@ Signed-off-by: Jakub Kicinski r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); else if (tp->mac_version == RTL_GIGA_MAC_VER_63) r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); -@@ -3716,8 +3716,8 @@ static void rtl_hw_start_8125_common(str +@@ -3742,8 +3742,8 @@ static void rtl_hw_start_8125_common(str r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); @@ -193,7 +193,7 @@ Signed-off-by: Jakub Kicinski r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); else r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); -@@ -3836,8 +3836,8 @@ static void rtl_hw_config(struct rtl8169 +@@ -3863,8 +3863,8 @@ static void rtl_hw_config(struct rtl8169 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, @@ -204,7 +204,7 @@ Signed-off-by: Jakub Kicinski }; if (hw_configs[tp->mac_version]) -@@ -3858,8 +3858,8 @@ static void rtl_hw_start_8125(struct rtl +@@ -3885,8 +3885,8 @@ static void rtl_hw_start_8125(struct rtl RTL_W32(tp, i, 0); break; case RTL_GIGA_MAC_VER_63: @@ -215,7 +215,7 @@ Signed-off-by: Jakub Kicinski for (i = 0xa00; i < 0xa80; i += 4) RTL_W32(tp, i, 0); RTL_W16(tp, INT_CFG1_8125, 0x0000); -@@ -4091,7 +4091,7 @@ static void rtl8169_cleanup(struct rtl81 +@@ -4118,7 +4118,7 @@ static void rtl8169_cleanup(struct rtl81 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); break; @@ -224,7 +224,7 @@ Signed-off-by: Jakub Kicinski rtl_enable_rxdvgate(tp); fsleep(2000); break; -@@ -4248,7 +4248,7 @@ static unsigned int rtl_quirk_packet_pad +@@ -4275,7 +4275,7 @@ static unsigned int rtl_quirk_packet_pad switch (tp->mac_version) { case RTL_GIGA_MAC_VER_34: @@ -233,7 +233,7 @@ Signed-off-by: Jakub Kicinski padto = max_t(unsigned int, padto, ETH_ZLEN); break; default: -@@ -5265,7 +5265,7 @@ static void rtl_hw_initialize(struct rtl +@@ -5293,7 +5293,7 @@ static void rtl_hw_initialize(struct rtl case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: rtl_hw_init_8168g(tp); break; diff --git a/target/linux/generic/backport-6.12/780-24-v6.14-r8169-add-support-for-RTL8125D-rev.b.patch b/target/linux/generic/backport-6.12/780-24-v6.14-r8169-add-support-for-RTL8125D-rev.b.patch index eb565b751d..e53d93f213 100644 --- a/target/linux/generic/backport-6.12/780-24-v6.14-r8169-add-support-for-RTL8125D-rev.b.patch +++ b/target/linux/generic/backport-6.12/780-24-v6.14-r8169-add-support-for-RTL8125D-rev.b.patch @@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 }, /* 8125B family. */ -@@ -3836,6 +3840,7 @@ static void rtl_hw_config(struct rtl8169 +@@ -3863,6 +3867,7 @@ static void rtl_hw_config(struct rtl8169 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, @@ -70,7 +70,7 @@ Signed-off-by: Jakub Kicinski [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, [RTL_GIGA_MAC_VER_71] = rtl_hw_start_8126a, }; -@@ -3854,6 +3859,7 @@ static void rtl_hw_start_8125(struct rtl +@@ -3881,6 +3886,7 @@ static void rtl_hw_start_8125(struct rtl switch (tp->mac_version) { case RTL_GIGA_MAC_VER_61: case RTL_GIGA_MAC_VER_64: diff --git a/target/linux/generic/backport-6.12/780-25-v6.14-r8169-add-support-for-RTL8125BP-rev.b.patch b/target/linux/generic/backport-6.12/780-25-v6.14-r8169-add-support-for-RTL8125BP-rev.b.patch index 35b68bb9c9..e358951f9d 100644 --- a/target/linux/generic/backport-6.12/780-25-v6.14-r8169-add-support-for-RTL8125BP-rev.b.patch +++ b/target/linux/generic/backport-6.12/780-25-v6.14-r8169-add-support-for-RTL8125BP-rev.b.patch @@ -127,7 +127,7 @@ Signed-off-by: Paolo Abeni /* 8125D family. */ { 0x7cf, 0x689, RTL_GIGA_MAC_VER_65 }, { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 }, -@@ -3841,6 +3869,7 @@ static void rtl_hw_config(struct rtl8169 +@@ -3868,6 +3896,7 @@ static void rtl_hw_config(struct rtl8169 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8125d, @@ -135,7 +135,7 @@ Signed-off-by: Paolo Abeni [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, [RTL_GIGA_MAC_VER_71] = rtl_hw_start_8126a, }; -@@ -3860,6 +3889,7 @@ static void rtl_hw_start_8125(struct rtl +@@ -3887,6 +3916,7 @@ static void rtl_hw_start_8125(struct rtl case RTL_GIGA_MAC_VER_61: case RTL_GIGA_MAC_VER_64: case RTL_GIGA_MAC_VER_65: diff --git a/target/linux/generic/backport-6.12/780-27-v6.15-r8169-don-t-scan-PHY-addresses-0.patch b/target/linux/generic/backport-6.12/780-27-v6.15-r8169-don-t-scan-PHY-addresses-0.patch deleted file mode 100644 index b6ddc76ca8..0000000000 --- a/target/linux/generic/backport-6.12/780-27-v6.15-r8169-don-t-scan-PHY-addresses-0.patch +++ /dev/null @@ -1,26 +0,0 @@ -From faac69a4ae5abb49e62c79c66b51bb905c9aa5ec Mon Sep 17 00:00:00 2001 -From: Heiner Kallweit -Date: Tue, 4 Feb 2025 07:58:17 +0100 -Subject: [PATCH] r8169: don't scan PHY addresses > 0 - -The PHY address is a dummy, because r8169 PHY access registers -don't support a PHY address. Therefore scan address 0 only. - -Signed-off-by: Heiner Kallweit -Reviewed-by: Andrew Lunn -Link: https://patch.msgid.link/830637dd-4016-4a68-92b3-618fcac6589d@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/realtek/r8169_main.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/ethernet/realtek/r8169_main.c -+++ b/drivers/net/ethernet/realtek/r8169_main.c -@@ -5222,6 +5222,7 @@ static int r8169_mdio_register(struct rt - new_bus->priv = tp; - new_bus->parent = &pdev->dev; - new_bus->irq[0] = PHY_MAC_INTERRUPT; -+ new_bus->phy_mask = GENMASK(31, 1); - snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", - pci_domain_nr(pdev->bus), pci_dev_id(pdev)); - diff --git a/target/linux/generic/backport-6.12/780-29-v6.15-r8169-add-PHY-c45-ops-for-MDIO_MMD_VENDOR2-registers.patch b/target/linux/generic/backport-6.12/780-29-v6.15-r8169-add-PHY-c45-ops-for-MDIO_MMD_VENDOR2-registers.patch index 165d7da1be..1fe7f8c2be 100644 --- a/target/linux/generic/backport-6.12/780-29-v6.15-r8169-add-PHY-c45-ops-for-MDIO_MMD_VENDOR2-registers.patch +++ b/target/linux/generic/backport-6.12/780-29-v6.15-r8169-add-PHY-c45-ops-for-MDIO_MMD_VENDOR2-registers.patch @@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c -@@ -5200,6 +5200,33 @@ static int r8169_mdio_write_reg(struct m +@@ -5227,6 +5227,33 @@ static int r8169_mdio_write_reg(struct m return 0; } @@ -53,7 +53,7 @@ Signed-off-by: Jakub Kicinski static int r8169_mdio_register(struct rtl8169_private *tp) { struct pci_dev *pdev = tp->pci_dev; -@@ -5230,6 +5257,11 @@ static int r8169_mdio_register(struct rt +@@ -5257,6 +5284,11 @@ static int r8169_mdio_register(struct rt new_bus->read = r8169_mdio_read_reg; new_bus->write = r8169_mdio_write_reg; diff --git a/target/linux/generic/backport-6.12/780-30-v6.15-r8169-increase-max-jumbo-packet-size-on-RTL8125-RTL8.patch b/target/linux/generic/backport-6.12/780-30-v6.15-r8169-increase-max-jumbo-packet-size-on-RTL8125-RTL8.patch index 559f742ebe..571022051b 100644 --- a/target/linux/generic/backport-6.12/780-30-v6.15-r8169-increase-max-jumbo-packet-size-on-RTL8125-RTL8.patch +++ b/target/linux/generic/backport-6.12/780-30-v6.15-r8169-increase-max-jumbo-packet-size-on-RTL8125-RTL8.patch @@ -28,7 +28,7 @@ Signed-off-by: Jakub Kicinski static const struct { const char *name; -@@ -5359,6 +5360,9 @@ static int rtl_jumbo_max(struct rtl8169_ +@@ -5386,6 +5387,9 @@ static int rtl_jumbo_max(struct rtl8169_ /* RTL8168c */ case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: return JUMBO_6K; diff --git a/target/linux/generic/backport-6.12/780-31-v6.15-r8169-switch-away-from-deprecated-pcim_iomap_table.patch b/target/linux/generic/backport-6.12/780-31-v6.15-r8169-switch-away-from-deprecated-pcim_iomap_table.patch index 93b79d7823..039e6596ac 100644 --- a/target/linux/generic/backport-6.12/780-31-v6.15-r8169-switch-away-from-deprecated-pcim_iomap_table.patch +++ b/target/linux/generic/backport-6.12/780-31-v6.15-r8169-switch-away-from-deprecated-pcim_iomap_table.patch @@ -17,7 +17,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c -@@ -5446,11 +5446,10 @@ static int rtl_init_one(struct pci_dev * +@@ -5473,11 +5473,10 @@ static int rtl_init_one(struct pci_dev * if (region < 0) return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); diff --git a/target/linux/generic/backport-6.12/780-32-v6.15-r8169-enable-RTL8168H-RTL8168EP-RTL8168FP-ASPM-suppo.patch b/target/linux/generic/backport-6.12/780-32-v6.15-r8169-enable-RTL8168H-RTL8168EP-RTL8168FP-ASPM-suppo.patch index 5c6ce70d29..7cc6556dd7 100644 --- a/target/linux/generic/backport-6.12/780-32-v6.15-r8169-enable-RTL8168H-RTL8168EP-RTL8168FP-ASPM-suppo.patch +++ b/target/linux/generic/backport-6.12/780-32-v6.15-r8169-enable-RTL8168H-RTL8168EP-RTL8168FP-ASPM-suppo.patch @@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c -@@ -5397,7 +5397,7 @@ done: +@@ -5424,7 +5424,7 @@ done: /* register is set if system vendor successfully tested ASPM 1.2 */ static bool rtl_aspm_is_safe(struct rtl8169_private *tp) { diff --git a/target/linux/generic/backport-6.12/780-33-v6.15-r8169-disable-RTL8126-ZRX-DC-timeout.patch b/target/linux/generic/backport-6.12/780-33-v6.15-r8169-disable-RTL8126-ZRX-DC-timeout.patch deleted file mode 100644 index 1f4240e879..0000000000 --- a/target/linux/generic/backport-6.12/780-33-v6.15-r8169-disable-RTL8126-ZRX-DC-timeout.patch +++ /dev/null @@ -1,60 +0,0 @@ -From b48688ea3c9ac8d5d910c6e91fb7f80d846581f0 Mon Sep 17 00:00:00 2001 -From: ChunHao Lin -Date: Tue, 18 Mar 2025 16:37:21 +0800 -Subject: [PATCH] r8169: disable RTL8126 ZRX-DC timeout - -Disable it due to it dose not meet ZRX-DC specification. If it is enabled, -device will exit L1 substate every 100ms. Disable it for saving more power -in L1 substate. - -Signed-off-by: ChunHao Lin -Reviewed-by: Heiner Kallweit -Link: https://patch.msgid.link/20250318083721.4127-3-hau@realtek.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/realtek/r8169_main.c | 27 +++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - ---- a/drivers/net/ethernet/realtek/r8169_main.c -+++ b/drivers/net/ethernet/realtek/r8169_main.c -@@ -2852,6 +2852,32 @@ static u32 rtl_csi_read(struct rtl8169_p - RTL_R32(tp, CSIDR) : ~0; - } - -+static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp) -+{ -+ struct pci_dev *pdev = tp->pci_dev; -+ u32 csi; -+ int rc; -+ u8 val; -+ -+#define RTL_GEN3_RELATED_OFF 0x0890 -+#define RTL_GEN3_ZRXDC_NONCOMPL 0x1 -+ if (pdev->cfg_size > RTL_GEN3_RELATED_OFF) { -+ rc = pci_read_config_byte(pdev, RTL_GEN3_RELATED_OFF, &val); -+ if (rc == PCIBIOS_SUCCESSFUL) { -+ val &= ~RTL_GEN3_ZRXDC_NONCOMPL; -+ rc = pci_write_config_byte(pdev, RTL_GEN3_RELATED_OFF, -+ val); -+ if (rc == PCIBIOS_SUCCESSFUL) -+ return; -+ } -+ } -+ -+ netdev_notice_once(tp->dev, -+ "No native access to PCI extended config space, falling back to CSI\n"); -+ csi = rtl_csi_read(tp, RTL_GEN3_RELATED_OFF); -+ rtl_csi_write(tp, RTL_GEN3_RELATED_OFF, csi & ~RTL_GEN3_ZRXDC_NONCOMPL); -+} -+ - static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) - { - struct pci_dev *pdev = tp->pci_dev; -@@ -3824,6 +3850,7 @@ static void rtl_hw_start_8125d(struct rt - - static void rtl_hw_start_8126a(struct rtl8169_private *tp) - { -+ rtl_disable_zrxdc_timeout(tp); - rtl_set_def_aspm_entry_latency(tp); - rtl_hw_start_8125_common(tp); - } diff --git a/target/linux/generic/backport-6.12/781-10-v6.14-net-phy-move-realtek-PHY-driver-to-its-own-subdirect.patch b/target/linux/generic/backport-6.12/781-10-v6.14-net-phy-move-realtek-PHY-driver-to-its-own-subdirect.patch index 5f0b61e0ce..633468f93a 100644 --- a/target/linux/generic/backport-6.12/781-10-v6.14-net-phy-move-realtek-PHY-driver-to-its-own-subdirect.patch +++ b/target/linux/generic/backport-6.12/781-10-v6.14-net-phy-move-realtek-PHY-driver-to-its-own-subdirect.patch @@ -24,7 +24,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -358,10 +358,7 @@ config QSEMI_PHY +@@ -343,10 +343,7 @@ config QSEMI_PHY help Currently supports the qs6612 @@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski tristate "Renesas PHYs" --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -95,7 +95,7 @@ obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o +@@ -94,7 +94,7 @@ obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o obj-y += qcom/ obj-$(CONFIG_QSEMI_PHY) += qsemi.o diff --git a/target/linux/generic/backport-6.12/807-v6.15-power-supply-sysfs-remove-duplicate-nul-termination-to-fix-build-with-GCC15.patch b/target/linux/generic/backport-6.12/807-v6.15-power-supply-sysfs-remove-duplicate-nul-termination-to-fix-build-with-GCC15.patch new file mode 100644 index 0000000000..48f9c1c264 --- /dev/null +++ b/target/linux/generic/backport-6.12/807-v6.15-power-supply-sysfs-remove-duplicate-nul-termination-to-fix-build-with-GCC15.patch @@ -0,0 +1,39 @@ +From 77f5bb150132bbbcd6bc37ffdc80c9e140e373a4 Mon Sep 17 00:00:00 2001 +From: Kees Cook +Date: Wed, 16 Apr 2025 15:27:41 -0700 +Subject: [PATCH] power: supply: sysfs: Remove duplicate NUL termination + +GCC 15's new -Wunterminated-string-initialization notices that one of +the sysfs attr strings would lack the implicit trailing NUL byte during +initialization: + +drivers/power/supply/power_supply_sysfs.c:183:57: warning: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute (32 chars into 31 available) [-Wunterminated-string-initialization] + 183 | POWER_SUPPLY_ATTR(CHARGE_CONTROL_START_THRESHOLD), + | ^ +drivers/power/supply/power_supply_sysfs.c:36:23: note: in definition of macro '_POWER_SUPPLY_ATTR' + 36 | .attr_name = #_name "\0", \ + | ^~~~~ +drivers/power/supply/power_supply_sysfs.c:183:9: note: in expansion of macro 'POWER_SUPPLY_ATTR' + 183 | POWER_SUPPLY_ATTR(CHARGE_CONTROL_START_THRESHOLD), + | ^~~~~~~~~~~~~~~~~ + +However, the macro used was explicitly adding a trailing NUL byte (which +is not needed). Remove this to avoid the GCC warning. No binary +differences are seen after this change (there was always run for a NUL +byte, it's just that the _second_ NUL byte was getting truncated). + +Signed-off-by: Kees Cook +Link: https://lore.kernel.org/r/20250416222740.work.569-kees@kernel.org +Signed-off-by: Sebastian Reichel + +--- a/drivers/power/supply/power_supply_sysfs.c ++++ b/drivers/power/supply/power_supply_sysfs.c +@@ -33,7 +33,7 @@ struct power_supply_attr { + [POWER_SUPPLY_PROP_ ## _name] = \ + { \ + .prop_name = #_name, \ +- .attr_name = #_name "\0", \ ++ .attr_name = #_name, \ + .text_values = _text, \ + .text_values_len = _len, \ + } diff --git a/target/linux/generic/backport-6.6/0080-v6.9-smp-Avoid-setup_max_cpus_namespace_collision_shadowing.patch b/target/linux/generic/backport-6.6/0080-v6.9-smp-Avoid-setup_max_cpus_namespace_collision_shadowing.patch index 54ebaa1a80..c8cef08935 100644 --- a/target/linux/generic/backport-6.6/0080-v6.9-smp-Avoid-setup_max_cpus_namespace_collision_shadowing.patch +++ b/target/linux/generic/backport-6.6/0080-v6.9-smp-Avoid-setup_max_cpus_namespace_collision_shadowing.patch @@ -21,7 +21,7 @@ Cc: linux-kernel@vger.kernel.org --- a/include/linux/cpu.h +++ b/include/linux/cpu.h -@@ -109,7 +109,7 @@ void notify_cpu_starting(unsigned int cp +@@ -111,7 +111,7 @@ void notify_cpu_starting(unsigned int cp extern void cpu_maps_update_begin(void); extern void cpu_maps_update_done(void); int bringup_hibernate_cpu(unsigned int sleep_cpu); diff --git a/target/linux/generic/backport-6.6/330-v6.13-jiffies-Define-secs_to_jiffies.patch b/target/linux/generic/backport-6.6/330-v6.13-jiffies-Define-secs_to_jiffies.patch new file mode 100644 index 0000000000..117409abfb --- /dev/null +++ b/target/linux/generic/backport-6.6/330-v6.13-jiffies-Define-secs_to_jiffies.patch @@ -0,0 +1,60 @@ +From b35108a51cf7bab58d7eace1267d7965978bcdb8 Mon Sep 17 00:00:00 2001 +From: Easwar Hariharan +Date: Wed, 30 Oct 2024 17:47:35 +0000 +Subject: [PATCH] jiffies: Define secs_to_jiffies() + +secs_to_jiffies() is defined in hci_event.c and cannot be reused by +other call sites. Hoist it into the core code to allow conversion of the +~1150 usages of msecs_to_jiffies() that either: + + - use a multiplier value of 1000 or equivalently MSEC_PER_SEC, or + - have timeouts that are denominated in seconds (i.e. end in 000) + +It's implemented as a macro to allow usage in static initializers. + +This will also allow conversion of yet more sites that use (sec * HZ) +directly, and improve their readability. + +Suggested-by: Michael Kelley +Signed-off-by: Easwar Hariharan +Signed-off-by: Thomas Gleixner +Reviewed-by: Luiz Augusto von Dentz +Link: https://lore.kernel.org/all/20241030-open-coded-timeouts-v3-1-9ba123facf88@linux.microsoft.com +--- + include/linux/jiffies.h | 13 +++++++++++++ + net/bluetooth/hci_event.c | 2 -- + 2 files changed, 13 insertions(+), 2 deletions(-) + +--- a/include/linux/jiffies.h ++++ b/include/linux/jiffies.h +@@ -523,6 +523,19 @@ static __always_inline unsigned long mse + } + } + ++/** ++ * secs_to_jiffies: - convert seconds to jiffies ++ * @_secs: time in seconds ++ * ++ * Conversion is done by simple multiplication with HZ ++ * ++ * secs_to_jiffies() is defined as a macro rather than a static inline ++ * function so it can be used in static initializers. ++ * ++ * Return: jiffies value ++ */ ++#define secs_to_jiffies(_secs) ((_secs) * HZ) ++ + extern unsigned long __usecs_to_jiffies(const unsigned int u); + #if !(USEC_PER_SEC % HZ) + static inline unsigned long _usecs_to_jiffies(const unsigned int u) +--- a/net/bluetooth/hci_event.c ++++ b/net/bluetooth/hci_event.c +@@ -43,8 +43,6 @@ + #define ZERO_KEY "\x00\x00\x00\x00\x00\x00\x00\x00" \ + "\x00\x00\x00\x00\x00\x00\x00\x00" + +-#define secs_to_jiffies(_secs) msecs_to_jiffies((_secs) * 1000) +- + /* Handle HCI Event packets */ + + static void *hci_ev_skb_pull(struct hci_dev *hdev, struct sk_buff *skb, diff --git a/target/linux/generic/backport-6.6/331-v6.14-jiffies-Cast-to-unsigned-long-in-secs_to_jiffies-con.patch b/target/linux/generic/backport-6.6/331-v6.14-jiffies-Cast-to-unsigned-long-in-secs_to_jiffies-con.patch new file mode 100644 index 0000000000..9e15195ab5 --- /dev/null +++ b/target/linux/generic/backport-6.6/331-v6.14-jiffies-Cast-to-unsigned-long-in-secs_to_jiffies-con.patch @@ -0,0 +1,35 @@ +From bb2784d9ab49587ba4fbff37a319fff2924db289 Mon Sep 17 00:00:00 2001 +From: Easwar Hariharan +Date: Thu, 30 Jan 2025 19:26:58 +0000 +Subject: [PATCH] jiffies: Cast to unsigned long in secs_to_jiffies() + conversion + +While converting users of msecs_to_jiffies(), lkp reported that some range +checks would always be true because of the mismatch between the implied int +value of secs_to_jiffies() vs the unsigned long return value of the +msecs_to_jiffies() calls it was replacing. + +Fix this by casting the secs_to_jiffies() input value to unsigned long. + +Fixes: b35108a51cf7ba ("jiffies: Define secs_to_jiffies()") +Reported-by: kernel test robot +Signed-off-by: Easwar Hariharan +Signed-off-by: Thomas Gleixner +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/all/20250130192701.99626-1-eahariha@linux.microsoft.com +Closes: https://lore.kernel.org/oe-kbuild-all/202501301334.NB6NszQR-lkp@intel.com/ +--- + include/linux/jiffies.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/include/linux/jiffies.h ++++ b/include/linux/jiffies.h +@@ -534,7 +534,7 @@ static __always_inline unsigned long mse + * + * Return: jiffies value + */ +-#define secs_to_jiffies(_secs) ((_secs) * HZ) ++#define secs_to_jiffies(_secs) (unsigned long)((_secs) * HZ) + + extern unsigned long __usecs_to_jiffies(const unsigned int u); + #if !(USEC_PER_SEC % HZ) diff --git a/target/linux/generic/backport-6.6/421-01-v6.16-spi-bcm63xx-spi-fix-shared-reset.patch b/target/linux/generic/backport-6.6/421-01-v6.16-spi-bcm63xx-spi-fix-shared-reset.patch new file mode 100644 index 0000000000..e886350d26 --- /dev/null +++ b/target/linux/generic/backport-6.6/421-01-v6.16-spi-bcm63xx-spi-fix-shared-reset.patch @@ -0,0 +1,32 @@ +From 5ad20e3d8cfe3b2e42bbddc7e0ebaa74479bb589 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Thu, 29 May 2025 15:09:14 +0200 +Subject: [PATCH] spi: bcm63xx-spi: fix shared reset +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Some bmips SoCs (bcm6362, bcm63268) share the same SPI reset for both SPI +and HSSPI controllers, so reset shouldn't be exclusive. + +Fixes: 38807adeaf1e ("spi: bcm63xx-spi: add reset support") +Reported-by: Jonas Gorski +Signed-off-by: Álvaro Fernández Rojas +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250529130915.2519590-2-noltari@gmail.com +Signed-off-by: Mark Brown +--- + drivers/spi/spi-bcm63xx.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/spi/spi-bcm63xx.c ++++ b/drivers/spi/spi-bcm63xx.c +@@ -523,7 +523,7 @@ static int bcm63xx_spi_probe(struct plat + return PTR_ERR(clk); + } + +- reset = devm_reset_control_get_optional_exclusive(dev, NULL); ++ reset = devm_reset_control_get_optional_shared(dev, NULL); + if (IS_ERR(reset)) + return PTR_ERR(reset); + diff --git a/target/linux/generic/backport-6.6/421-02-v6.16-spi-bcm63xx-hsspi-fix-shared-reset.patch b/target/linux/generic/backport-6.6/421-02-v6.16-spi-bcm63xx-hsspi-fix-shared-reset.patch new file mode 100644 index 0000000000..3c30269d07 --- /dev/null +++ b/target/linux/generic/backport-6.6/421-02-v6.16-spi-bcm63xx-hsspi-fix-shared-reset.patch @@ -0,0 +1,32 @@ +From 3d6d84c8f2f66d3fd6a43a1e2ce8e6b54c573960 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Thu, 29 May 2025 15:09:15 +0200 +Subject: [PATCH] spi: bcm63xx-hsspi: fix shared reset +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Some bmips SoCs (bcm6362, bcm63268) share the same SPI reset for both SPI +and HSSPI controllers, so reset shouldn't be exclusive. + +Fixes: 0eeadddbf09a ("spi: bcm63xx-hsspi: add reset support") +Reported-by: Jonas Gorski +Signed-off-by: Álvaro Fernández Rojas +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250529130915.2519590-3-noltari@gmail.com +Signed-off-by: Mark Brown +--- + drivers/spi/spi-bcm63xx-hsspi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/spi/spi-bcm63xx-hsspi.c ++++ b/drivers/spi/spi-bcm63xx-hsspi.c +@@ -745,7 +745,7 @@ static int bcm63xx_hsspi_probe(struct pl + if (IS_ERR(clk)) + return PTR_ERR(clk); + +- reset = devm_reset_control_get_optional_exclusive(dev, NULL); ++ reset = devm_reset_control_get_optional_shared(dev, NULL); + if (IS_ERR(reset)) + return PTR_ERR(reset); + diff --git a/target/linux/generic/backport-6.6/700-v6.10-net-create-a-dummy-net_device-allocator.patch b/target/linux/generic/backport-6.6/700-v6.10-net-create-a-dummy-net_device-allocator.patch index dd0640e2ee..9e0bd14acf 100644 --- a/target/linux/generic/backport-6.6/700-v6.10-net-create-a-dummy-net_device-allocator.patch +++ b/target/linux/generic/backport-6.6/700-v6.10-net-create-a-dummy-net_device-allocator.patch @@ -37,7 +37,7 @@ Signed-off-by: David S. Miller --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -4569,6 +4569,9 @@ static inline void netif_addr_unlock_bh( +@@ -4580,6 +4580,9 @@ static inline void netif_addr_unlock_bh( void ether_setup(struct net_device *dev); diff --git a/target/linux/generic/backport-6.6/725-01-v6.16-net-dsa-tag_brcm-legacy-fix-pskb_may_pull-length.patch b/target/linux/generic/backport-6.6/725-01-v6.16-net-dsa-tag_brcm-legacy-fix-pskb_may_pull-length.patch new file mode 100644 index 0000000000..9fa88d2d3f --- /dev/null +++ b/target/linux/generic/backport-6.6/725-01-v6.16-net-dsa-tag_brcm-legacy-fix-pskb_may_pull-length.patch @@ -0,0 +1,31 @@ +From efdddc4484859082da6c7877ed144c8121c8ea55 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Thu, 29 May 2025 14:44:06 +0200 +Subject: [PATCH] net: dsa: tag_brcm: legacy: fix pskb_may_pull length +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BRCM_LEG_PORT_ID was incorrectly used for pskb_may_pull length. +The correct check is BRCM_LEG_TAG_LEN + VLAN_HLEN, or 10 bytes. + +Fixes: 964dbf186eaa ("net: dsa: tag_brcm: add support for legacy tags") +Signed-off-by: Álvaro Fernández Rojas +Reviewed-by: Florian Fainelli +Link: https://patch.msgid.link/20250529124406.2513779-1-noltari@gmail.com +Signed-off-by: Jakub Kicinski +--- + net/dsa/tag_brcm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/net/dsa/tag_brcm.c ++++ b/net/dsa/tag_brcm.c +@@ -257,7 +257,7 @@ static struct sk_buff *brcm_leg_tag_rcv( + int source_port; + u8 *brcm_tag; + +- if (unlikely(!pskb_may_pull(skb, BRCM_LEG_PORT_ID))) ++ if (unlikely(!pskb_may_pull(skb, BRCM_LEG_TAG_LEN + VLAN_HLEN))) + return NULL; + + brcm_tag = dsa_etype_header_pos_rx(skb); diff --git a/target/linux/generic/backport-6.6/751-01-v6.8-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch b/target/linux/generic/backport-6.6/751-01-v6.8-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch index ab12cc925f..7d232563ca 100644 --- a/target/linux/generic/backport-6.6/751-01-v6.8-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch +++ b/target/linux/generic/backport-6.6/751-01-v6.8-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch @@ -280,8 +280,8 @@ Signed-off-by: Jakub Kicinski ring->dma, ring->phys); ring->dma = NULL; } -@@ -3124,7 +3124,7 @@ static void mtk_dma_free(struct mtk_eth - netdev_reset_queue(eth->netdev[i]); +@@ -3132,7 +3132,7 @@ static void mtk_dma_free(struct mtk_eth + if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { dma_free_coherent(eth->dma_dev, - MTK_QDMA_RING_SIZE * soc->txrx.txd_size, @@ -289,7 +289,7 @@ Signed-off-by: Jakub Kicinski eth->scratch_ring, eth->phy_scratch_ring); eth->scratch_ring = NULL; eth->phy_scratch_ring = 0; -@@ -3174,7 +3174,7 @@ static irqreturn_t mtk_handle_irq_rx(int +@@ -3182,7 +3182,7 @@ static irqreturn_t mtk_handle_irq_rx(int eth->rx_events++; if (likely(napi_schedule_prep(ð->rx_napi))) { @@ -298,7 +298,7 @@ Signed-off-by: Jakub Kicinski __napi_schedule(ð->rx_napi); } -@@ -3200,9 +3200,9 @@ static irqreturn_t mtk_handle_irq(int ir +@@ -3208,9 +3208,9 @@ static irqreturn_t mtk_handle_irq(int ir const struct mtk_reg_map *reg_map = eth->soc->reg_map; if (mtk_r32(eth, reg_map->pdma.irq_mask) & @@ -310,7 +310,7 @@ Signed-off-by: Jakub Kicinski mtk_handle_irq_rx(irq, _eth); } if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { -@@ -3220,10 +3220,10 @@ static void mtk_poll_controller(struct n +@@ -3228,10 +3228,10 @@ static void mtk_poll_controller(struct n struct mtk_eth *eth = mac->hw; mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); @@ -323,7 +323,7 @@ Signed-off-by: Jakub Kicinski } #endif -@@ -3387,7 +3387,7 @@ static int mtk_open(struct net_device *d +@@ -3395,7 +3395,7 @@ static int mtk_open(struct net_device *d napi_enable(ð->tx_napi); napi_enable(ð->rx_napi); mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); @@ -332,7 +332,7 @@ Signed-off-by: Jakub Kicinski refcount_set(ð->dma_refcnt, 1); } else -@@ -3471,7 +3471,7 @@ static int mtk_stop(struct net_device *d +@@ -3479,7 +3479,7 @@ static int mtk_stop(struct net_device *d mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); @@ -341,7 +341,7 @@ Signed-off-by: Jakub Kicinski napi_disable(ð->tx_napi); napi_disable(ð->rx_napi); -@@ -3947,9 +3947,9 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -3955,9 +3955,9 @@ static int mtk_hw_init(struct mtk_eth *e /* FE int grouping */ mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); @@ -353,7 +353,7 @@ Signed-off-by: Jakub Kicinski mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); if (mtk_is_netsys_v3_or_greater(eth)) { -@@ -5057,11 +5057,15 @@ static const struct mtk_soc_data mt2701_ +@@ -5065,11 +5065,15 @@ static const struct mtk_soc_data mt2701_ .required_clks = MT7623_CLKS_BITMAP, .required_pctl = true, .version = 1, @@ -374,7 +374,7 @@ Signed-off-by: Jakub Kicinski .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5077,11 +5081,15 @@ static const struct mtk_soc_data mt7621_ +@@ -5085,11 +5089,15 @@ static const struct mtk_soc_data mt7621_ .offload_version = 1, .hash_offset = 2, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, @@ -395,7 +395,7 @@ Signed-off-by: Jakub Kicinski .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5099,11 +5107,15 @@ static const struct mtk_soc_data mt7622_ +@@ -5107,11 +5115,15 @@ static const struct mtk_soc_data mt7622_ .hash_offset = 2, .has_accounting = true, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, @@ -416,7 +416,7 @@ Signed-off-by: Jakub Kicinski .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5120,11 +5132,15 @@ static const struct mtk_soc_data mt7623_ +@@ -5128,11 +5140,15 @@ static const struct mtk_soc_data mt7623_ .hash_offset = 2, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, .disable_pll_modes = true, @@ -437,7 +437,7 @@ Signed-off-by: Jakub Kicinski .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5139,11 +5155,15 @@ static const struct mtk_soc_data mt7629_ +@@ -5147,11 +5163,15 @@ static const struct mtk_soc_data mt7629_ .required_pctl = false, .has_accounting = true, .version = 1, @@ -458,7 +458,7 @@ Signed-off-by: Jakub Kicinski .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5161,11 +5181,15 @@ static const struct mtk_soc_data mt7981_ +@@ -5169,11 +5189,15 @@ static const struct mtk_soc_data mt7981_ .hash_offset = 4, .has_accounting = true, .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, @@ -479,7 +479,7 @@ Signed-off-by: Jakub Kicinski .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_len_offset = 8, }, -@@ -5183,11 +5207,15 @@ static const struct mtk_soc_data mt7986_ +@@ -5191,11 +5215,15 @@ static const struct mtk_soc_data mt7986_ .hash_offset = 4, .has_accounting = true, .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, @@ -500,7 +500,7 @@ Signed-off-by: Jakub Kicinski .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_len_offset = 8, }, -@@ -5205,11 +5233,15 @@ static const struct mtk_soc_data mt7988_ +@@ -5213,11 +5241,15 @@ static const struct mtk_soc_data mt7988_ .hash_offset = 4, .has_accounting = true, .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, @@ -521,7 +521,7 @@ Signed-off-by: Jakub Kicinski .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_len_offset = 8, }, -@@ -5222,11 +5254,15 @@ static const struct mtk_soc_data rt5350_ +@@ -5230,11 +5262,15 @@ static const struct mtk_soc_data rt5350_ .required_clks = MT7628_CLKS_BITMAP, .required_pctl = false, .version = 1, diff --git a/target/linux/generic/backport-6.6/751-02-v6.8-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch b/target/linux/generic/backport-6.6/751-02-v6.8-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch index 27c512864e..3531399b83 100644 --- a/target/linux/generic/backport-6.6/751-02-v6.8-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch +++ b/target/linux/generic/backport-6.6/751-02-v6.8-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch @@ -85,7 +85,7 @@ Signed-off-by: Jakub Kicinski rxd->rxd5 = 0; rxd->rxd6 = 0; rxd->rxd7 = 0; -@@ -3893,7 +3893,7 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -3901,7 +3901,7 @@ static int mtk_hw_init(struct mtk_eth *e else mtk_hw_reset(eth); @@ -94,7 +94,7 @@ Signed-off-by: Jakub Kicinski /* Set FE to PDMAv2 if necessary */ val = mtk_r32(eth, MTK_FE_GLO_MISC); mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); -@@ -5187,11 +5187,11 @@ static const struct mtk_soc_data mt7981_ +@@ -5195,11 +5195,11 @@ static const struct mtk_soc_data mt7981_ .dma_len_offset = 8, }, .rx = { @@ -110,7 +110,7 @@ Signed-off-by: Jakub Kicinski }, }; -@@ -5213,11 +5213,11 @@ static const struct mtk_soc_data mt7986_ +@@ -5221,11 +5221,11 @@ static const struct mtk_soc_data mt7986_ .dma_len_offset = 8, }, .rx = { diff --git a/target/linux/generic/backport-6.6/752-25-v6.10-net-ethernet-mtk_eth_soc-handle-dma-buffer-size-soc-.patch b/target/linux/generic/backport-6.6/752-25-v6.10-net-ethernet-mtk_eth_soc-handle-dma-buffer-size-soc-.patch index 27dac7214b..0df5a680b3 100644 --- a/target/linux/generic/backport-6.6/752-25-v6.10-net-ethernet-mtk_eth_soc-handle-dma-buffer-size-soc-.patch +++ b/target/linux/generic/backport-6.6/752-25-v6.10-net-ethernet-mtk_eth_soc-handle-dma-buffer-size-soc-.patch @@ -169,7 +169,7 @@ Signed-off-by: David S. Miller } ring->frag_size = mtk_max_frag_size(rx_data_len); -@@ -3143,7 +3150,10 @@ static void mtk_dma_free(struct mtk_eth +@@ -3151,7 +3158,10 @@ static void mtk_dma_free(struct mtk_eth mtk_rx_clean(eth, ð->rx_ring[i], false); } @@ -181,7 +181,7 @@ Signed-off-by: David S. Miller } static bool mtk_hw_reset_check(struct mtk_eth *eth) -@@ -5065,11 +5075,14 @@ static const struct mtk_soc_data mt2701_ +@@ -5073,11 +5083,14 @@ static const struct mtk_soc_data mt2701_ .desc_size = sizeof(struct mtk_tx_dma), .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, @@ -196,7 +196,7 @@ Signed-off-by: David S. Miller .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5089,11 +5102,14 @@ static const struct mtk_soc_data mt7621_ +@@ -5097,11 +5110,14 @@ static const struct mtk_soc_data mt7621_ .desc_size = sizeof(struct mtk_tx_dma), .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, @@ -211,7 +211,7 @@ Signed-off-by: David S. Miller .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5115,11 +5131,14 @@ static const struct mtk_soc_data mt7622_ +@@ -5123,11 +5139,14 @@ static const struct mtk_soc_data mt7622_ .desc_size = sizeof(struct mtk_tx_dma), .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, @@ -226,7 +226,7 @@ Signed-off-by: David S. Miller .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5140,11 +5159,14 @@ static const struct mtk_soc_data mt7623_ +@@ -5148,11 +5167,14 @@ static const struct mtk_soc_data mt7623_ .desc_size = sizeof(struct mtk_tx_dma), .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, @@ -241,7 +241,7 @@ Signed-off-by: David S. Miller .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5163,11 +5185,14 @@ static const struct mtk_soc_data mt7629_ +@@ -5171,11 +5193,14 @@ static const struct mtk_soc_data mt7629_ .desc_size = sizeof(struct mtk_tx_dma), .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, @@ -256,7 +256,7 @@ Signed-off-by: David S. Miller .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, }, -@@ -5189,6 +5214,8 @@ static const struct mtk_soc_data mt7981_ +@@ -5197,6 +5222,8 @@ static const struct mtk_soc_data mt7981_ .desc_size = sizeof(struct mtk_tx_dma_v2), .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_len_offset = 8, @@ -265,7 +265,7 @@ Signed-off-by: David S. Miller }, .rx = { .desc_size = sizeof(struct mtk_rx_dma), -@@ -5196,6 +5223,7 @@ static const struct mtk_soc_data mt7981_ +@@ -5204,6 +5231,7 @@ static const struct mtk_soc_data mt7981_ .dma_l4_valid = RX_DMA_L4_VALID_V2, .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, @@ -273,7 +273,7 @@ Signed-off-by: David S. Miller }, }; -@@ -5215,6 +5243,8 @@ static const struct mtk_soc_data mt7986_ +@@ -5223,6 +5251,8 @@ static const struct mtk_soc_data mt7986_ .desc_size = sizeof(struct mtk_tx_dma_v2), .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_len_offset = 8, @@ -282,7 +282,7 @@ Signed-off-by: David S. Miller }, .rx = { .desc_size = sizeof(struct mtk_rx_dma), -@@ -5222,6 +5252,7 @@ static const struct mtk_soc_data mt7986_ +@@ -5230,6 +5260,7 @@ static const struct mtk_soc_data mt7986_ .dma_l4_valid = RX_DMA_L4_VALID_V2, .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, @@ -290,7 +290,7 @@ Signed-off-by: David S. Miller }, }; -@@ -5241,6 +5272,8 @@ static const struct mtk_soc_data mt7988_ +@@ -5249,6 +5280,8 @@ static const struct mtk_soc_data mt7988_ .desc_size = sizeof(struct mtk_tx_dma_v2), .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_len_offset = 8, @@ -299,7 +299,7 @@ Signed-off-by: David S. Miller }, .rx = { .desc_size = sizeof(struct mtk_rx_dma_v2), -@@ -5248,6 +5281,7 @@ static const struct mtk_soc_data mt7988_ +@@ -5256,6 +5289,7 @@ static const struct mtk_soc_data mt7988_ .dma_l4_valid = RX_DMA_L4_VALID_V2, .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_len_offset = 8, @@ -307,7 +307,7 @@ Signed-off-by: David S. Miller }, }; -@@ -5262,6 +5296,7 @@ static const struct mtk_soc_data rt5350_ +@@ -5270,6 +5304,7 @@ static const struct mtk_soc_data rt5350_ .desc_size = sizeof(struct mtk_tx_dma), .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, @@ -315,7 +315,7 @@ Signed-off-by: David S. Miller }, .rx = { .desc_size = sizeof(struct mtk_rx_dma), -@@ -5269,6 +5304,7 @@ static const struct mtk_soc_data rt5350_ +@@ -5277,6 +5312,7 @@ static const struct mtk_soc_data rt5350_ .dma_l4_valid = RX_DMA_L4_VALID_PDMA, .dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_len_offset = 16, diff --git a/target/linux/generic/backport-6.6/752-26-v6.10-net-ethernet-mtk_eth_soc-ppe-add-support-for-multipl.patch b/target/linux/generic/backport-6.6/752-26-v6.10-net-ethernet-mtk_eth_soc-ppe-add-support-for-multipl.patch index 1c5a7ae100..3ff126939b 100644 --- a/target/linux/generic/backport-6.6/752-26-v6.10-net-ethernet-mtk_eth_soc-ppe-add-support-for-multipl.patch +++ b/target/linux/generic/backport-6.6/752-26-v6.10-net-ethernet-mtk_eth_soc-ppe-add-support-for-multipl.patch @@ -85,7 +85,7 @@ Signed-off-by: Jakub Kicinski skb_record_rx_queue(skb, 0); napi_gro_receive(napi, skb); -@@ -3280,37 +3291,27 @@ static int mtk_start_dma(struct mtk_eth +@@ -3288,37 +3299,27 @@ static int mtk_start_dma(struct mtk_eth return 0; } @@ -134,7 +134,7 @@ Signed-off-by: Jakub Kicinski } -@@ -3370,7 +3371,10 @@ static int mtk_open(struct net_device *d +@@ -3378,7 +3379,10 @@ static int mtk_open(struct net_device *d { struct mtk_mac *mac = netdev_priv(dev); struct mtk_eth *eth = mac->hw; @@ -146,7 +146,7 @@ Signed-off-by: Jakub Kicinski err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); if (err) { -@@ -3394,18 +3398,38 @@ static int mtk_open(struct net_device *d +@@ -3402,18 +3406,38 @@ static int mtk_open(struct net_device *d for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) mtk_ppe_start(eth->ppe[i]); @@ -190,7 +190,7 @@ Signed-off-by: Jakub Kicinski phylink_start(mac->phylink); netif_tx_start_all_queues(dev); -@@ -3482,7 +3506,8 @@ static int mtk_stop(struct net_device *d +@@ -3490,7 +3514,8 @@ static int mtk_stop(struct net_device *d if (!refcount_dec_and_test(ð->dma_refcnt)) return 0; @@ -200,7 +200,7 @@ Signed-off-by: Jakub Kicinski mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); -@@ -4977,23 +5002,24 @@ static int mtk_probe(struct platform_dev +@@ -4985,23 +5010,24 @@ static int mtk_probe(struct platform_dev } if (eth->soc->offload_version) { @@ -233,7 +233,7 @@ Signed-off-by: Jakub Kicinski } for (i = 0; i < MTK_MAX_DEVS; i++) { -@@ -5096,6 +5122,7 @@ static const struct mtk_soc_data mt7621_ +@@ -5104,6 +5130,7 @@ static const struct mtk_soc_data mt7621_ .required_pctl = false, .version = 1, .offload_version = 1, @@ -241,7 +241,7 @@ Signed-off-by: Jakub Kicinski .hash_offset = 2, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, .tx = { -@@ -5124,6 +5151,7 @@ static const struct mtk_soc_data mt7622_ +@@ -5132,6 +5159,7 @@ static const struct mtk_soc_data mt7622_ .required_pctl = false, .version = 1, .offload_version = 2, @@ -249,7 +249,7 @@ Signed-off-by: Jakub Kicinski .hash_offset = 2, .has_accounting = true, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, -@@ -5152,6 +5180,7 @@ static const struct mtk_soc_data mt7623_ +@@ -5160,6 +5188,7 @@ static const struct mtk_soc_data mt7623_ .required_pctl = true, .version = 1, .offload_version = 1, @@ -257,7 +257,7 @@ Signed-off-by: Jakub Kicinski .hash_offset = 2, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, .disable_pll_modes = true, -@@ -5207,6 +5236,7 @@ static const struct mtk_soc_data mt7981_ +@@ -5215,6 +5244,7 @@ static const struct mtk_soc_data mt7981_ .required_pctl = false, .version = 2, .offload_version = 2, @@ -265,7 +265,7 @@ Signed-off-by: Jakub Kicinski .hash_offset = 4, .has_accounting = true, .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, -@@ -5236,6 +5266,7 @@ static const struct mtk_soc_data mt7986_ +@@ -5244,6 +5274,7 @@ static const struct mtk_soc_data mt7986_ .required_pctl = false, .version = 2, .offload_version = 2, @@ -273,7 +273,7 @@ Signed-off-by: Jakub Kicinski .hash_offset = 4, .has_accounting = true, .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, -@@ -5265,6 +5296,7 @@ static const struct mtk_soc_data mt7988_ +@@ -5273,6 +5304,7 @@ static const struct mtk_soc_data mt7988_ .required_pctl = false, .version = 3, .offload_version = 2, diff --git a/target/linux/generic/backport-6.6/752-28-v6.10-net-ethernet-mediatek-Allow-gaps-in-MAC-allocation.patch b/target/linux/generic/backport-6.6/752-28-v6.10-net-ethernet-mediatek-Allow-gaps-in-MAC-allocation.patch index 77061eb355..27ad9dca2c 100644 --- a/target/linux/generic/backport-6.6/752-28-v6.10-net-ethernet-mediatek-Allow-gaps-in-MAC-allocation.patch +++ b/target/linux/generic/backport-6.6/752-28-v6.10-net-ethernet-mediatek-Allow-gaps-in-MAC-allocation.patch @@ -21,7 +21,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3400,7 +3400,7 @@ static int mtk_open(struct net_device *d +@@ -3408,7 +3408,7 @@ static int mtk_open(struct net_device *d for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) diff --git a/target/linux/generic/backport-6.6/752-30-v6.10-net-ethernet-mtk_eth_soc-implement-.-get-set-_pausep.patch b/target/linux/generic/backport-6.6/752-30-v6.10-net-ethernet-mtk_eth_soc-implement-.-get-set-_pausep.patch index 272ceb3b45..b16910e18e 100644 --- a/target/linux/generic/backport-6.6/752-30-v6.10-net-ethernet-mtk_eth_soc-implement-.-get-set-_pausep.patch +++ b/target/linux/generic/backport-6.6/752-30-v6.10-net-ethernet-mtk_eth_soc-implement-.-get-set-_pausep.patch @@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -4482,6 +4482,20 @@ static int mtk_set_rxnfc(struct net_devi +@@ -4490,6 +4490,20 @@ static int mtk_set_rxnfc(struct net_devi return ret; } @@ -41,7 +41,7 @@ Signed-off-by: Jakub Kicinski static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, struct net_device *sb_dev) { -@@ -4510,8 +4524,10 @@ static const struct ethtool_ops mtk_etht +@@ -4518,8 +4532,10 @@ static const struct ethtool_ops mtk_etht .get_strings = mtk_get_strings, .get_sset_count = mtk_get_sset_count, .get_ethtool_stats = mtk_get_ethtool_stats, diff --git a/target/linux/generic/backport-6.6/753-v6.15-net-ethernet-mediatek-add-EEE-support.patch b/target/linux/generic/backport-6.6/753-v6.15-net-ethernet-mediatek-add-EEE-support.patch index 009f211a2c..8066fbf3ad 100644 --- a/target/linux/generic/backport-6.6/753-v6.15-net-ethernet-mediatek-add-EEE-support.patch +++ b/target/linux/generic/backport-6.6/753-v6.15-net-ethernet-mediatek-add-EEE-support.patch @@ -39,7 +39,7 @@ Signed-off-by: Qingfang Deng mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK; mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); } -@@ -4496,6 +4506,61 @@ static int mtk_set_pauseparam(struct net +@@ -4504,6 +4514,61 @@ static int mtk_set_pauseparam(struct net return phylink_ethtool_set_pauseparam(mac->phylink, pause); } @@ -101,7 +101,7 @@ Signed-off-by: Qingfang Deng static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, struct net_device *sb_dev) { -@@ -4528,6 +4593,8 @@ static const struct ethtool_ops mtk_etht +@@ -4536,6 +4601,8 @@ static const struct ethtool_ops mtk_etht .set_pauseparam = mtk_set_pauseparam, .get_rxnfc = mtk_get_rxnfc, .set_rxnfc = mtk_set_rxnfc, @@ -110,7 +110,7 @@ Signed-off-by: Qingfang Deng }; static const struct net_device_ops mtk_netdev_ops = { -@@ -4588,6 +4655,8 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4596,6 +4663,8 @@ static int mtk_add_mac(struct mtk_eth *e } mac = netdev_priv(eth->netdev[id]); eth->mac[id] = mac; diff --git a/target/linux/generic/backport-6.6/807-v6.15-power-supply-sysfs-remove-duplicate-nul-termination-to-fix-build-with-GCC15.patch b/target/linux/generic/backport-6.6/807-v6.15-power-supply-sysfs-remove-duplicate-nul-termination-to-fix-build-with-GCC15.patch new file mode 100644 index 0000000000..c462183853 --- /dev/null +++ b/target/linux/generic/backport-6.6/807-v6.15-power-supply-sysfs-remove-duplicate-nul-termination-to-fix-build-with-GCC15.patch @@ -0,0 +1,39 @@ +From 77f5bb150132bbbcd6bc37ffdc80c9e140e373a4 Mon Sep 17 00:00:00 2001 +From: Kees Cook +Date: Wed, 16 Apr 2025 15:27:41 -0700 +Subject: [PATCH] power: supply: sysfs: Remove duplicate NUL termination + +GCC 15's new -Wunterminated-string-initialization notices that one of +the sysfs attr strings would lack the implicit trailing NUL byte during +initialization: + +drivers/power/supply/power_supply_sysfs.c:183:57: warning: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute (32 chars into 31 available) [-Wunterminated-string-initialization] + 183 | POWER_SUPPLY_ATTR(CHARGE_CONTROL_START_THRESHOLD), + | ^ +drivers/power/supply/power_supply_sysfs.c:36:23: note: in definition of macro '_POWER_SUPPLY_ATTR' + 36 | .attr_name = #_name "\0", \ + | ^~~~~ +drivers/power/supply/power_supply_sysfs.c:183:9: note: in expansion of macro 'POWER_SUPPLY_ATTR' + 183 | POWER_SUPPLY_ATTR(CHARGE_CONTROL_START_THRESHOLD), + | ^~~~~~~~~~~~~~~~~ + +However, the macro used was explicitly adding a trailing NUL byte (which +is not needed). Remove this to avoid the GCC warning. No binary +differences are seen after this change (there was always run for a NUL +byte, it's just that the _second_ NUL byte was getting truncated). + +Signed-off-by: Kees Cook +Link: https://lore.kernel.org/r/20250416222740.work.569-kees@kernel.org +Signed-off-by: Sebastian Reichel + +--- a/drivers/power/supply/power_supply_sysfs.c ++++ b/drivers/power/supply/power_supply_sysfs.c +@@ -32,7 +32,7 @@ struct power_supply_attr { + [POWER_SUPPLY_PROP_ ## _name] = \ + { \ + .prop_name = #_name, \ +- .attr_name = #_name "\0", \ ++ .attr_name = #_name, \ + .text_values = _text, \ + .text_values_len = _len, \ + } diff --git a/target/linux/generic/backport-6.6/920-v6.12-clk-provide-devm_clk_get_optional_enabled_with_rate.patch b/target/linux/generic/backport-6.6/920-v6.12-clk-provide-devm_clk_get_optional_enabled_with_rate.patch new file mode 100644 index 0000000000..4a8e5c4c6e --- /dev/null +++ b/target/linux/generic/backport-6.6/920-v6.12-clk-provide-devm_clk_get_optional_enabled_with_rate.patch @@ -0,0 +1,104 @@ +From 9934a1bd45b2b03f6d1204a6ae2780d3b009799f Mon Sep 17 00:00:00 2001 +From: Bartosz Golaszewski +Date: Mon, 5 Aug 2024 10:57:31 +0200 +Subject: [PATCH] clk: provide devm_clk_get_optional_enabled_with_rate() + +There are clock users in the kernel that can't use +devm_clk_get_optional_enabled() as they need to set rate after getting +the clock and before enabling it. Provide a managed helper that wraps +these operations in the correct order. + +Signed-off-by: Bartosz Golaszewski +Link: https://lore.kernel.org/r/20240805-clk-new-helper-v2-1-e5fdd1e1d729@linaro.org +Signed-off-by: Stephen Boyd +--- + drivers/clk/clk-devres.c | 28 ++++++++++++++++++++++++++++ + include/linux/clk.h | 33 +++++++++++++++++++++++++++++++++ + 2 files changed, 61 insertions(+) + +--- a/drivers/clk/clk-devres.c ++++ b/drivers/clk/clk-devres.c +@@ -99,6 +99,34 @@ struct clk *devm_clk_get_optional_enable + } + EXPORT_SYMBOL_GPL(devm_clk_get_optional_enabled); + ++struct clk *devm_clk_get_optional_enabled_with_rate(struct device *dev, ++ const char *id, ++ unsigned long rate) ++{ ++ struct clk *clk; ++ int ret; ++ ++ clk = __devm_clk_get(dev, id, clk_get_optional, NULL, ++ clk_disable_unprepare); ++ if (IS_ERR(clk)) ++ return ERR_CAST(clk); ++ ++ ret = clk_set_rate(clk, rate); ++ if (ret) ++ goto out_put_clk; ++ ++ ret = clk_prepare_enable(clk); ++ if (ret) ++ goto out_put_clk; ++ ++ return clk; ++ ++out_put_clk: ++ devm_clk_put(dev, clk); ++ return ERR_PTR(ret); ++} ++EXPORT_SYMBOL_GPL(devm_clk_get_optional_enabled_with_rate); ++ + struct clk_bulk_devres { + struct clk_bulk_data *clks; + int num_clks; +--- a/include/linux/clk.h ++++ b/include/linux/clk.h +@@ -608,6 +608,32 @@ struct clk *devm_clk_get_optional_prepar + struct clk *devm_clk_get_optional_enabled(struct device *dev, const char *id); + + /** ++ * devm_clk_get_optional_enabled_with_rate - devm_clk_get_optional() + ++ * clk_set_rate() + ++ * clk_prepare_enable() ++ * @dev: device for clock "consumer" ++ * @id: clock consumer ID ++ * @rate: new clock rate ++ * ++ * Context: May sleep. ++ * ++ * Return: a struct clk corresponding to the clock producer, or ++ * valid IS_ERR() condition containing errno. The implementation ++ * uses @dev and @id to determine the clock consumer, and thereby ++ * the clock producer. If no such clk is found, it returns NULL ++ * which serves as a dummy clk. That's the only difference compared ++ * to devm_clk_get_enabled(). ++ * ++ * The returned clk (if valid) is prepared and enabled and rate was set. ++ * ++ * The clock will automatically be disabled, unprepared and freed ++ * when the device is unbound from the bus. ++ */ ++struct clk *devm_clk_get_optional_enabled_with_rate(struct device *dev, ++ const char *id, ++ unsigned long rate); ++ ++/** + * devm_get_clk_from_child - lookup and obtain a managed reference to a + * clock producer from child node. + * @dev: device for clock "consumer" +@@ -948,6 +974,13 @@ static inline struct clk *devm_clk_get_o + { + return NULL; + } ++ ++static inline struct clk * ++devm_clk_get_optional_enabled_with_rate(struct device *dev, const char *id, ++ unsigned long rate) ++{ ++ return NULL; ++} + + static inline int __must_check devm_clk_bulk_get(struct device *dev, int num_clks, + struct clk_bulk_data *clks) diff --git a/target/linux/generic/config-6.12 b/target/linux/generic/config-6.12 index 61a6150520..3434ac461e 100644 --- a/target/linux/generic/config-6.12 +++ b/target/linux/generic/config-6.12 @@ -436,8 +436,8 @@ CONFIG_ARM_GIC_MAX_NR=1 # CONFIG_ARM_MHU is not set CONFIG_ARM_MODULE_PLTS=y # CONFIG_ARM_NI is not set -# CONFIG_ARM_PATCH_PHYS_VIRT is not set # CONFIG_ARM_PAN is not set +# CONFIG_ARM_PATCH_PHYS_VIRT is not set # CONFIG_ARM_PSCI is not set # CONFIG_ARM_PSCI_CHECKER is not set # CONFIG_ARM_PSCI_CPUIDLE is not set @@ -1957,6 +1957,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_FS is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_FB is not set +# CONFIG_FBNIC is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_ARC is not set # CONFIG_FB_ARK is not set @@ -6163,6 +6164,7 @@ CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y # CONFIG_SND_SOC_MT8188 is not set # CONFIG_SND_SOC_MT8192 is not set # CONFIG_SND_SOC_MT8195 is not set +# CONFIG_SND_SOC_MT8365 is not set # CONFIG_SND_SOC_MTK_BTCVSD is not set # CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set @@ -6424,6 +6426,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_SSB_SDIOHOST is not set # CONFIG_SSFDC is not set # CONFIG_SSIF_IPMI_BMC is not set +CONFIG_STACKDEPOT_MAX_FRAMES=64 # CONFIG_STACKPROTECTOR is not set # CONFIG_STACKPROTECTOR_PER_TASK is not set # CONFIG_STACKPROTECTOR_STRONG is not set diff --git a/target/linux/generic/files/drivers/net/phy/rtl8261n/phy_rtl826xb_patch.c b/target/linux/generic/files/drivers/net/phy/rtl8261n/phy_rtl826xb_patch.c index 90a792a17b..0bfd93033f 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8261n/phy_rtl826xb_patch.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8261n/phy_rtl826xb_patch.c @@ -66,7 +66,7 @@ static uint16 _phy_rtl826xb_mmd_convert(uint16 page, uint16 addr) return reg; } -int32 +static int32 _phy_rtl826xb_patch_wait(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data, uint32 mask, uint8 patch_mode) { int32 ret = 0; @@ -211,7 +211,7 @@ _phy_rtl826xb_patch_wait(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mm return RT_ERR_OK; } -int32 +static int32 _phy_rtl826xb_patch_wait_not_equal(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data, uint32 mask, uint8 patch_mode) { int32 ret = 0; @@ -355,7 +355,7 @@ _phy_rtl826xb_patch_wait_not_equal(uint32 unit, rtk_port_t port, uint32 mmdAddr, return RT_ERR_OK; } -int32 +static int32 _phy_rtl826xb_patch_top_get(uint32 unit, rtk_port_t port, uint32 topPage, uint32 topReg, uint32 *pData) { int32 ret = 0; @@ -368,7 +368,7 @@ _phy_rtl826xb_patch_top_get(uint32 unit, rtk_port_t port, uint32 topPage, uint32 return RT_ERR_OK; } -int32 +static int32 _phy_rtl826xb_patch_top_set(uint32 unit, rtk_port_t port, uint32 topPage, uint32 topReg, uint32 wData) { int32 ret = 0; @@ -378,7 +378,7 @@ _phy_rtl826xb_patch_top_set(uint32 unit, rtk_port_t port, uint32 topPage, uint32 return RT_ERR_OK; } -int32 +static int32 _phy_rtl826xb_patch_sds_get(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 *pData) { int32 ret = 0; @@ -393,7 +393,7 @@ _phy_rtl826xb_patch_sds_get(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 return _phy_rtl826xb_patch_wait(unit, port, PHY_MMD_VEND1, 0x143, 0, BIT_15, PHY_PATCH_MODE_NORMAL); } -int32 +static int32 _phy_rtl826xb_patch_sds_set(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 wData, uint8 patch_mode) { int32 ret = 0; @@ -693,7 +693,7 @@ static int32 _phy_rtl826xb_flow_s(uint32 unit, rtk_port_t port, uint8 portOffset return RT_ERR_OK; } -int32 phy_rtl826xb_patch_op(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_hwpatch_t *pPatch_data, uint8 patch_mode) +static int32 phy_rtl826xb_patch_op(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_hwpatch_t *pPatch_data, uint8 patch_mode) { int32 ret = RT_ERR_OK; uint32 rData = 0, wData = 0; @@ -803,7 +803,7 @@ int32 phy_rtl826xb_patch_op(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_ return ret; } -int32 phy_rtl826xb_patch_flow(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_flow, uint8 patch_mode) +static int32 phy_rtl826xb_patch_flow(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_flow, uint8 patch_mode) { int32 ret = RT_ERR_OK; diff --git a/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_osal.c b/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_osal.c index bf3ac4b124..35339400d0 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_osal.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_osal.c @@ -7,6 +7,7 @@ #include "type.h" #include "error.h" #include "rtk_phylib_def.h" +#include "rtk_osal.h" #include #include diff --git a/target/linux/generic/hack-6.12/499-LEGACY-block-partitions-populate-fwnode.patch b/target/linux/generic/hack-6.12/499-LEGACY-block-partitions-populate-fwnode.patch new file mode 100644 index 0000000000..f7ec9efba7 --- /dev/null +++ b/target/linux/generic/hack-6.12/499-LEGACY-block-partitions-populate-fwnode.patch @@ -0,0 +1,130 @@ +From: Daniel Golle +Subject: [PATCH] LEGACY block: partitions: populate fwnode + +Assign matching firmware nodes to block partitions in order to allow +them to be referenced e.g. as NVMEM providers. + +REMOVE THIS PATCH ONCE ALL TARGETS ARE USING LINUX 6.12 AND ALL BOARDS +HAVE MIGRATED TO UPSTREAM DT BINDINGS. + +Signed-off-by: Daniel Golle +--- a/block/partitions/core.c ++++ b/block/partitions/core.c +@@ -11,6 +11,8 @@ + #include + #include + #include ++#include ++ + #include "check.h" + + static int (*const check_part[])(struct parsed_partitions *) = { +@@ -285,6 +287,74 @@ static ssize_t whole_disk_show(struct de + } + static const DEVICE_ATTR(whole_disk, 0444, whole_disk_show, NULL); + ++static bool part_meta_match(const char *attr, const char *member, size_t length) ++{ ++ /* check if length of attr exceeds specified maximum length */ ++ if (strnlen(attr, length) == length) ++ return false; ++ ++ /* return true if strings match */ ++ return !strncmp(attr, member, length); ++} ++ ++static struct fwnode_handle *find_partition_fwnode(struct block_device *bdev) ++{ ++ struct fwnode_handle *fw_parts, *fw_part; ++ struct device *ddev = disk_to_dev(bdev->bd_disk); ++ const char *partname, *uuid; ++ u32 partno; ++ bool got_uuid, got_partname, got_partno; ++ ++ fw_parts = device_get_named_child_node(ddev, "partitions"); ++ if (!fw_parts) ++ return NULL; ++ ++ fwnode_for_each_child_node(fw_parts, fw_part) { ++ got_uuid = false; ++ got_partname = false; ++ got_partno = false; ++ /* ++ * In case 'uuid' is defined in the partitions firmware node ++ * require partition meta info being present and the specified ++ * uuid to match. ++ */ ++ got_uuid = !fwnode_property_read_string(fw_part, "uuid", &uuid); ++ if (got_uuid && (!bdev->bd_meta_info || ++ !part_meta_match(uuid, bdev->bd_meta_info->uuid, ++ PARTITION_META_INFO_UUIDLTH))) ++ continue; ++ ++ /* ++ * In case 'partname' is defined in the partitions firmware node ++ * require partition meta info being present and the specified ++ * volname to match. ++ */ ++ got_partname = !fwnode_property_read_string(fw_part, "partname", ++ &partname); ++ if (got_partname && (!bdev->bd_meta_info || ++ !part_meta_match(partname, ++ bdev->bd_meta_info->volname, ++ PARTITION_META_INFO_VOLNAMELTH))) ++ continue; ++ ++ /* ++ * In case 'partno' is defined in the partitions firmware node ++ * the specified partno needs to match. ++ */ ++ got_partno = !fwnode_property_read_u32(fw_part, "partno", &partno); ++ if (got_partno && bdev_partno(bdev) != partno) ++ continue; ++ ++ /* Skip if no matching criteria is present in firmware node */ ++ if (!got_uuid && !got_partname && !got_partno) ++ continue; ++ ++ return fw_part; ++ } ++ ++ return NULL; ++} ++ + /* + * Must be called either with open_mutex held, before a disk can be opened or + * after all disk users are gone. +@@ -361,6 +431,9 @@ static struct block_device *add_partitio + goto out_put; + } + ++ if (!pdev->fwnode && !pdev->of_node) ++ device_set_node(pdev, find_partition_fwnode(bdev)); ++ + /* delay uevent until 'holders' subdir is created */ + dev_set_uevent_suppress(pdev, 1); + err = device_add(pdev); +--- a/drivers/mmc/core/bus.c ++++ b/drivers/mmc/core/bus.c +@@ -368,6 +368,8 @@ int mmc_add_card(struct mmc_card *card) + + mmc_add_card_debugfs(card); + card->dev.of_node = mmc_of_find_child_device(card->host, 0); ++ if (card->dev.of_node && !card->dev.fwnode) ++ card->dev.fwnode = &card->dev.of_node->fwnode; + + device_enable_async_suspend(&card->dev); + +--- a/drivers/mmc/core/block.c ++++ b/drivers/mmc/core/block.c +@@ -2679,6 +2679,10 @@ static struct mmc_blk_data *mmc_blk_allo + if (area_type == MMC_BLK_DATA_AREA_MAIN) + dev_set_drvdata(&card->dev, md); + disk_fwnode = mmc_blk_get_partitions_node(parent, subname); ++ if (!disk_fwnode) ++ disk_fwnode = device_get_named_child_node(subname ? md->parent->parent : ++ md->parent, ++ subname ? subname : "block"); + ret = add_disk_fwnode(md->parent, md->disk, mmc_disk_attr_groups, + disk_fwnode); + if (ret) diff --git a/target/linux/generic/hack-6.12/610-net-page_pool-try-to-free-deferred-skbs-while-waitin.patch b/target/linux/generic/hack-6.12/610-net-page_pool-try-to-free-deferred-skbs-while-waitin.patch index 9537bb76e3..3d27c92141 100644 --- a/target/linux/generic/hack-6.12/610-net-page_pool-try-to-free-deferred-skbs-while-waitin.patch +++ b/target/linux/generic/hack-6.12/610-net-page_pool-try-to-free-deferred-skbs-while-waitin.patch @@ -16,7 +16,7 @@ Signed-off-by: Felix Fietkau --- a/net/core/page_pool.c +++ b/net/core/page_pool.c -@@ -1063,7 +1063,7 @@ static void page_pool_release_retry(stru +@@ -1064,7 +1064,7 @@ static void page_pool_release_retry(stru struct delayed_work *dwq = to_delayed_work(wq); struct page_pool *pool = container_of(dwq, typeof(*pool), release_dw); void *netdev; @@ -25,7 +25,7 @@ Signed-off-by: Felix Fietkau inflight = page_pool_release(pool); /* In rare cases, a driver bug may cause inflight to go negative. -@@ -1075,6 +1075,17 @@ static void page_pool_release_retry(stru +@@ -1076,6 +1076,17 @@ static void page_pool_release_retry(stru if (inflight <= 0) return; diff --git a/target/linux/generic/hack-6.12/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch b/target/linux/generic/hack-6.12/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch index 7443ad2f50..98c4186a3e 100644 --- a/target/linux/generic/hack-6.12/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch +++ b/target/linux/generic/hack-6.12/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch @@ -52,7 +52,7 @@ Signed-off-by: Daniel Golle }; module_phy_driver(aqr_driver); -@@ -1226,6 +1252,8 @@ static struct mdio_device_id __maybe_unu +@@ -1226,6 +1252,8 @@ static const struct mdio_device_id __may { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, diff --git a/target/linux/generic/hack-6.12/735-net-phy-realtek-rtl8261n.patch b/target/linux/generic/hack-6.12/735-net-phy-realtek-rtl8261n.patch index e7372dc2cc..616db25890 100644 --- a/target/linux/generic/hack-6.12/735-net-phy-realtek-rtl8261n.patch +++ b/target/linux/generic/hack-6.12/735-net-phy-realtek-rtl8261n.patch @@ -1,6 +1,6 @@ --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -434,6 +434,8 @@ config QSEMI_PHY +@@ -419,6 +419,8 @@ config QSEMI_PHY source "drivers/net/phy/realtek/Kconfig" @@ -11,7 +11,7 @@ help --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -111,6 +111,7 @@ obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja +@@ -110,6 +110,7 @@ obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja obj-y += qcom/ obj-$(CONFIG_QSEMI_PHY) += qsemi.o obj-$(CONFIG_REALTEK_PHY) += realtek/ diff --git a/target/linux/generic/hack-6.12/766-net-phy-mediatek-ge-add-LED-configuration-interface.patch b/target/linux/generic/hack-6.12/766-net-phy-mediatek-ge-add-LED-configuration-interface.patch index 95134083fa..2eeca8fd77 100644 --- a/target/linux/generic/hack-6.12/766-net-phy-mediatek-ge-add-LED-configuration-interface.patch +++ b/target/linux/generic/hack-6.12/766-net-phy-mediatek-ge-add-LED-configuration-interface.patch @@ -12,18 +12,18 @@ plans on integrating their own framework for handling these LEDs. Signed-off-by: David Bauer --- - drivers/net/phy/mediatek-ge.c | 33 +++++++++++++++++++++++++++++++++ + drivers/net/phy/mediatek/mtk-ge.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) ---- a/drivers/net/phy/mediatek-ge.c -+++ b/drivers/net/phy/mediatek-ge.c +--- a/drivers/net/phy/mediatek/mtk-ge.c ++++ b/drivers/net/phy/mediatek/mtk-ge.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include -@@ -50,6 +51,36 @@ static int mt7530_phy_config_init(struct +@@ -73,6 +74,36 @@ static int mt7530_phy_config_init(struct return 0; } @@ -60,9 +60,9 @@ Signed-off-by: David Bauer static int mt7531_phy_config_init(struct phy_device *phydev) { mtk_gephy_config_init(phydev); -@@ -62,6 +93,9 @@ static int mt7531_phy_config_init(struct - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); +@@ -93,6 +124,9 @@ static int mt7531_phy_config_init(struct + FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) | + FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4)); + /* LED Config*/ + mt7530_led_config_of(phydev); diff --git a/target/linux/generic/hack-6.12/902-debloat_proc.patch b/target/linux/generic/hack-6.12/902-debloat_proc.patch index b62738748f..a135684460 100644 --- a/target/linux/generic/hack-6.12/902-debloat_proc.patch +++ b/target/linux/generic/hack-6.12/902-debloat_proc.patch @@ -235,7 +235,7 @@ Signed-off-by: Felix Fietkau if (!pe) --- a/mm/vmalloc.c +++ b/mm/vmalloc.c -@@ -5051,6 +5051,8 @@ static int __init proc_vmalloc_init(void +@@ -5054,6 +5054,8 @@ static int __init proc_vmalloc_init(void { void *priv_data = NULL; @@ -341,7 +341,7 @@ Signed-off-by: Felix Fietkau --- a/net/ipv4/fib_trie.c +++ b/net/ipv4/fib_trie.c -@@ -3037,11 +3037,13 @@ static const struct seq_operations fib_r +@@ -3015,11 +3015,13 @@ static const struct seq_operations fib_r int __net_init fib_proc_init(struct net *net) { @@ -357,7 +357,7 @@ Signed-off-by: Felix Fietkau fib_triestat_seq_show, NULL)) goto out2; -@@ -3052,17 +3054,21 @@ int __net_init fib_proc_init(struct net +@@ -3030,17 +3032,21 @@ int __net_init fib_proc_init(struct net return 0; out3: diff --git a/target/linux/generic/kernel-6.12 b/target/linux/generic/kernel-6.12 index 3f710bc5ee..343c2148fc 100644 --- a/target/linux/generic/kernel-6.12 +++ b/target/linux/generic/kernel-6.12 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.12 = .30 -LINUX_KERNEL_HASH-6.12.30 = df046a48971e40ce0b2e003e7e55b6b1e7da2912120eb216d5d6c8450c9cf82e +LINUX_VERSION-6.12 = .31 +LINUX_KERNEL_HASH-6.12.31 = b04c5b3e5df6e0aa5e9cd1efe527fac99f9dd39a43b97f13b22f8ca93e524ba7 diff --git a/target/linux/generic/kernel-6.6 b/target/linux/generic/kernel-6.6 index e4ac53448d..96534d711c 100644 --- a/target/linux/generic/kernel-6.6 +++ b/target/linux/generic/kernel-6.6 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.6 = .90 -LINUX_KERNEL_HASH-6.6.90 = ff856748671629c1fefef219099e0b4b81131c2d325e768cb0806e204157014e +LINUX_VERSION-6.6 = .92 +LINUX_KERNEL_HASH-6.6.92 = 1d82a82642d281c31d86f7301bc55e12a8a9f9c04532e249ef8ae6fe7dc237ec diff --git a/target/linux/generic/pending-6.12/152-net-wireguard-add-nonstring-annotation-to-fix-build-with-GCC15.patch b/target/linux/generic/pending-6.12/152-net-wireguard-add-nonstring-annotation-to-fix-build-with-GCC15.patch new file mode 100644 index 0000000000..1fdf2f1dbd --- /dev/null +++ b/target/linux/generic/pending-6.12/152-net-wireguard-add-nonstring-annotation-to-fix-build-with-GCC15.patch @@ -0,0 +1,63 @@ +From 71e5da46e78c1cd24e2feed251a2845327447ad8 Mon Sep 17 00:00:00 2001 +From: Kees Cook +Date: Wed, 21 May 2025 23:27:04 +0200 +Subject: wireguard: global: add __nonstring annotations for unterminated + strings + +When a character array without a terminating NUL character has a static +initializer, GCC 15's -Wunterminated-string-initialization will only +warn if the array lacks the "nonstring" attribute[1]. Mark the arrays +with __nonstring to correctly identify the char array as "not a C string" +and thereby eliminate the warning: + +../drivers/net/wireguard/cookie.c:29:56: warning: initializer-string for array of 'unsigned char' truncates NUL terminator but destination lacks 'nonstring' attribute (9 chars into 8 available) [-Wunterminated-string-initialization] + 29 | static const u8 mac1_key_label[COOKIE_KEY_LABEL_LEN] = "mac1----"; + | ^~~~~~~~~~ +../drivers/net/wireguard/cookie.c:30:58: warning: initializer-string for array of 'unsigned char' truncates NUL terminator but destination lacks 'nonstring' attribute (9 chars into 8 available) [-Wunterminated-string-initialization] + 30 | static const u8 cookie_key_label[COOKIE_KEY_LABEL_LEN] = "cookie--"; + | ^~~~~~~~~~ +../drivers/net/wireguard/noise.c:28:38: warning: initializer-string for array of 'unsigned char' truncates NUL terminator but destination lacks 'nonstring' attribute (38 chars into 37 available) [-Wunterminated-string-initialization] + 28 | static const u8 handshake_name[37] = "Noise_IKpsk2_25519_ChaChaPoly_BLAKE2s"; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +../drivers/net/wireguard/noise.c:29:39: warning: initializer-string for array of 'unsigned char' truncates NUL terminator but destination lacks 'nonstring' attribute (35 chars into 34 available) [-Wunterminated-string-initialization] + 29 | static const u8 identifier_name[34] = "WireGuard v1 zx2c4 Jason@zx2c4.com"; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The arrays are always used with their fixed size, so use __nonstring. + +Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117178 [1] +Signed-off-by: Kees Cook +Signed-off-by: Jason A. Donenfeld +Link: https://patch.msgid.link/20250521212707.1767879-3-Jason@zx2c4.com +Signed-off-by: Paolo Abeni +--- + drivers/net/wireguard/cookie.c | 4 ++-- + drivers/net/wireguard/noise.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/net/wireguard/cookie.c ++++ b/drivers/net/wireguard/cookie.c +@@ -26,8 +26,8 @@ void wg_cookie_checker_init(struct cooki + } + + enum { COOKIE_KEY_LABEL_LEN = 8 }; +-static const u8 mac1_key_label[COOKIE_KEY_LABEL_LEN] = "mac1----"; +-static const u8 cookie_key_label[COOKIE_KEY_LABEL_LEN] = "cookie--"; ++static const u8 mac1_key_label[COOKIE_KEY_LABEL_LEN] __nonstring = "mac1----"; ++static const u8 cookie_key_label[COOKIE_KEY_LABEL_LEN] __nonstring = "cookie--"; + + static void precompute_key(u8 key[NOISE_SYMMETRIC_KEY_LEN], + const u8 pubkey[NOISE_PUBLIC_KEY_LEN], +--- a/drivers/net/wireguard/noise.c ++++ b/drivers/net/wireguard/noise.c +@@ -25,8 +25,8 @@ + * <- e, ee, se, psk, {} + */ + +-static const u8 handshake_name[37] = "Noise_IKpsk2_25519_ChaChaPoly_BLAKE2s"; +-static const u8 identifier_name[34] = "WireGuard v1 zx2c4 Jason@zx2c4.com"; ++static const u8 handshake_name[37] __nonstring = "Noise_IKpsk2_25519_ChaChaPoly_BLAKE2s"; ++static const u8 identifier_name[34] __nonstring = "WireGuard v1 zx2c4 Jason@zx2c4.com"; + static u8 handshake_init_hash[NOISE_HASH_LEN] __ro_after_init; + static u8 handshake_init_chaining_key[NOISE_HASH_LEN] __ro_after_init; + static atomic64_t keypair_counter = ATOMIC64_INIT(0); diff --git a/target/linux/generic/pending-6.12/510-block-add-uImage.FIT-subimage-block-driver.patch b/target/linux/generic/pending-6.12/510-block-add-uImage.FIT-subimage-block-driver.patch index b786c2073c..c3d246c5ee 100644 --- a/target/linux/generic/pending-6.12/510-block-add-uImage.FIT-subimage-block-driver.patch +++ b/target/linux/generic/pending-6.12/510-block-add-uImage.FIT-subimage-block-driver.patch @@ -36,7 +36,7 @@ Signed-off-by: Daniel Golle --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -23666,6 +23666,12 @@ F: Documentation/filesystems/ubifs-authe +@@ -23668,6 +23668,12 @@ F: Documentation/filesystems/ubifs-authe F: Documentation/filesystems/ubifs.rst F: fs/ubifs/ diff --git a/target/linux/generic/pending-6.12/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch b/target/linux/generic/pending-6.12/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch index f0e8a63a99..8c7fab9462 100644 --- a/target/linux/generic/pending-6.12/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch +++ b/target/linux/generic/pending-6.12/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch @@ -424,7 +424,7 @@ Signed-off-by: Steven Barth } static int ip6_tnl_newlink(struct net *src_net, struct net_device *dev, -@@ -2083,6 +2302,12 @@ static void ip6_tnl_dellink(struct net_d +@@ -2084,6 +2303,12 @@ static void ip6_tnl_dellink(struct net_d static size_t ip6_tnl_get_size(const struct net_device *dev) { @@ -437,7 +437,7 @@ Signed-off-by: Steven Barth return /* IFLA_IPTUN_LINK */ nla_total_size(4) + -@@ -2112,6 +2337,24 @@ static size_t ip6_tnl_get_size(const str +@@ -2113,6 +2338,24 @@ static size_t ip6_tnl_get_size(const str nla_total_size(0) + /* IFLA_IPTUN_FWMARK */ nla_total_size(4) + @@ -462,7 +462,7 @@ Signed-off-by: Steven Barth 0; } -@@ -2119,6 +2362,9 @@ static int ip6_tnl_fill_info(struct sk_b +@@ -2120,6 +2363,9 @@ static int ip6_tnl_fill_info(struct sk_b { struct ip6_tnl *tunnel = netdev_priv(dev); struct __ip6_tnl_parm *parm = &tunnel->parms; @@ -472,7 +472,7 @@ Signed-off-by: Steven Barth if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) || nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) || -@@ -2128,9 +2374,27 @@ static int ip6_tnl_fill_info(struct sk_b +@@ -2129,9 +2375,27 @@ static int ip6_tnl_fill_info(struct sk_b nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) || nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) || nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) || @@ -501,7 +501,7 @@ Signed-off-by: Steven Barth if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) || -@@ -2170,6 +2434,7 @@ static const struct nla_policy ip6_tnl_p +@@ -2171,6 +2435,7 @@ static const struct nla_policy ip6_tnl_p [IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 }, [IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG }, [IFLA_IPTUN_FWMARK] = { .type = NLA_U32 }, diff --git a/target/linux/generic/pending-6.12/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-6.12/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch index a9aa7a3beb..d10f39cf22 100644 --- a/target/linux/generic/pending-6.12/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch +++ b/target/linux/generic/pending-6.12/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch @@ -66,7 +66,7 @@ Signed-off-by: Jonas Gorski static void rt_fibinfo_free(struct rtable __rcu **rtp) --- a/net/ipv4/fib_trie.c +++ b/net/ipv4/fib_trie.c -@@ -2784,6 +2784,7 @@ static const char *const rtn_type_names[ +@@ -2762,6 +2762,7 @@ static const char *const rtn_type_names[ [RTN_THROW] = "THROW", [RTN_NAT] = "NAT", [RTN_XRESOLVE] = "XRESOLVE", diff --git a/target/linux/generic/pending-6.12/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-6.12/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch index 52a15a6e09..b03b72b33d 100644 --- a/target/linux/generic/pending-6.12/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch +++ b/target/linux/generic/pending-6.12/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch @@ -695,7 +695,7 @@ Signed-off-by: Daniel Golle #define GEPHY_MAC_SEL BIT(1) /* Top misc registers */ -+#define TOP_MISC_NETSYS_PCS_MUX 0x84 ++#define TOP_MISC_NETSYS_PCS_MUX 0x0 +#define NETSYS_PCS_MUX_MASK GENMASK(1, 0) +#define MUX_G2_USXGMII_SEL BIT(1) +#define MUX_HSGMII1_G1_SEL BIT(0) diff --git a/target/linux/generic/pending-6.12/804-nvmem-core-support-mac-base-fixed-layout-cells.patch b/target/linux/generic/pending-6.12/804-nvmem-core-support-mac-base-fixed-layout-cells.patch index 446099a2a9..8f2706e6b4 100644 --- a/target/linux/generic/pending-6.12/804-nvmem-core-support-mac-base-fixed-layout-cells.patch +++ b/target/linux/generic/pending-6.12/804-nvmem-core-support-mac-base-fixed-layout-cells.patch @@ -33,7 +33,7 @@ string. #include #include #include -@@ -797,6 +800,62 @@ static int nvmem_validate_keepouts(struc +@@ -811,6 +814,62 @@ static int nvmem_validate_keepouts(struc return 0; } @@ -96,7 +96,7 @@ string. static int nvmem_add_cells_from_dt(struct nvmem_device *nvmem, struct device_node *np) { struct device *dev = &nvmem->dev; -@@ -836,6 +895,25 @@ static int nvmem_add_cells_from_dt(struc +@@ -852,6 +911,25 @@ static int nvmem_add_cells_from_dt(struc if (nvmem->fixup_dt_cell_info) nvmem->fixup_dt_cell_info(nvmem, &info); diff --git a/target/linux/generic/pending-6.12/809-01-nvmem-core-generalize-mac-base-cells-handling.patch b/target/linux/generic/pending-6.12/809-01-nvmem-core-generalize-mac-base-cells-handling.patch index 139a925ccf..94d43e0ce0 100644 --- a/target/linux/generic/pending-6.12/809-01-nvmem-core-generalize-mac-base-cells-handling.patch +++ b/target/linux/generic/pending-6.12/809-01-nvmem-core-generalize-mac-base-cells-handling.patch @@ -38,7 +38,7 @@ Signed-off-by: Christian Marangi #include #include #include -@@ -800,62 +797,6 @@ static int nvmem_validate_keepouts(struc +@@ -814,62 +811,6 @@ static int nvmem_validate_keepouts(struc return 0; } @@ -101,7 +101,7 @@ Signed-off-by: Christian Marangi static int nvmem_add_cells_from_dt(struct nvmem_device *nvmem, struct device_node *np) { struct device *dev = &nvmem->dev; -@@ -895,24 +836,8 @@ static int nvmem_add_cells_from_dt(struc +@@ -911,24 +852,8 @@ static int nvmem_add_cells_from_dt(struc if (nvmem->fixup_dt_cell_info) nvmem->fixup_dt_cell_info(nvmem, &info); diff --git a/target/linux/generic/pending-6.6/152-net-wireguard-add-nonstring-annotation-to-fix-build-with-GCC15.patch b/target/linux/generic/pending-6.6/152-net-wireguard-add-nonstring-annotation-to-fix-build-with-GCC15.patch new file mode 100644 index 0000000000..1fdf2f1dbd --- /dev/null +++ b/target/linux/generic/pending-6.6/152-net-wireguard-add-nonstring-annotation-to-fix-build-with-GCC15.patch @@ -0,0 +1,63 @@ +From 71e5da46e78c1cd24e2feed251a2845327447ad8 Mon Sep 17 00:00:00 2001 +From: Kees Cook +Date: Wed, 21 May 2025 23:27:04 +0200 +Subject: wireguard: global: add __nonstring annotations for unterminated + strings + +When a character array without a terminating NUL character has a static +initializer, GCC 15's -Wunterminated-string-initialization will only +warn if the array lacks the "nonstring" attribute[1]. Mark the arrays +with __nonstring to correctly identify the char array as "not a C string" +and thereby eliminate the warning: + +../drivers/net/wireguard/cookie.c:29:56: warning: initializer-string for array of 'unsigned char' truncates NUL terminator but destination lacks 'nonstring' attribute (9 chars into 8 available) [-Wunterminated-string-initialization] + 29 | static const u8 mac1_key_label[COOKIE_KEY_LABEL_LEN] = "mac1----"; + | ^~~~~~~~~~ +../drivers/net/wireguard/cookie.c:30:58: warning: initializer-string for array of 'unsigned char' truncates NUL terminator but destination lacks 'nonstring' attribute (9 chars into 8 available) [-Wunterminated-string-initialization] + 30 | static const u8 cookie_key_label[COOKIE_KEY_LABEL_LEN] = "cookie--"; + | ^~~~~~~~~~ +../drivers/net/wireguard/noise.c:28:38: warning: initializer-string for array of 'unsigned char' truncates NUL terminator but destination lacks 'nonstring' attribute (38 chars into 37 available) [-Wunterminated-string-initialization] + 28 | static const u8 handshake_name[37] = "Noise_IKpsk2_25519_ChaChaPoly_BLAKE2s"; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +../drivers/net/wireguard/noise.c:29:39: warning: initializer-string for array of 'unsigned char' truncates NUL terminator but destination lacks 'nonstring' attribute (35 chars into 34 available) [-Wunterminated-string-initialization] + 29 | static const u8 identifier_name[34] = "WireGuard v1 zx2c4 Jason@zx2c4.com"; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The arrays are always used with their fixed size, so use __nonstring. + +Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117178 [1] +Signed-off-by: Kees Cook +Signed-off-by: Jason A. Donenfeld +Link: https://patch.msgid.link/20250521212707.1767879-3-Jason@zx2c4.com +Signed-off-by: Paolo Abeni +--- + drivers/net/wireguard/cookie.c | 4 ++-- + drivers/net/wireguard/noise.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/net/wireguard/cookie.c ++++ b/drivers/net/wireguard/cookie.c +@@ -26,8 +26,8 @@ void wg_cookie_checker_init(struct cooki + } + + enum { COOKIE_KEY_LABEL_LEN = 8 }; +-static const u8 mac1_key_label[COOKIE_KEY_LABEL_LEN] = "mac1----"; +-static const u8 cookie_key_label[COOKIE_KEY_LABEL_LEN] = "cookie--"; ++static const u8 mac1_key_label[COOKIE_KEY_LABEL_LEN] __nonstring = "mac1----"; ++static const u8 cookie_key_label[COOKIE_KEY_LABEL_LEN] __nonstring = "cookie--"; + + static void precompute_key(u8 key[NOISE_SYMMETRIC_KEY_LEN], + const u8 pubkey[NOISE_PUBLIC_KEY_LEN], +--- a/drivers/net/wireguard/noise.c ++++ b/drivers/net/wireguard/noise.c +@@ -25,8 +25,8 @@ + * <- e, ee, se, psk, {} + */ + +-static const u8 handshake_name[37] = "Noise_IKpsk2_25519_ChaChaPoly_BLAKE2s"; +-static const u8 identifier_name[34] = "WireGuard v1 zx2c4 Jason@zx2c4.com"; ++static const u8 handshake_name[37] __nonstring = "Noise_IKpsk2_25519_ChaChaPoly_BLAKE2s"; ++static const u8 identifier_name[34] __nonstring = "WireGuard v1 zx2c4 Jason@zx2c4.com"; + static u8 handshake_init_hash[NOISE_HASH_LEN] __ro_after_init; + static u8 handshake_init_chaining_key[NOISE_HASH_LEN] __ro_after_init; + static atomic64_t keypair_counter = ATOMIC64_INIT(0); diff --git a/target/linux/generic/pending-6.6/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-6.6/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch index 05f64f7587..3b44c9aeab 100644 --- a/target/linux/generic/pending-6.6/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch +++ b/target/linux/generic/pending-6.6/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -5125,6 +5125,8 @@ static int mtk_probe(struct platform_dev +@@ -5133,6 +5133,8 @@ static int mtk_probe(struct platform_dev * for NAPI to work */ init_dummy_netdev(ð->dummy_dev); diff --git a/target/linux/generic/pending-6.6/730-net-ethernet-mtk_eth_soc-reset-all-TX-queues-on-DMA-.patch b/target/linux/generic/pending-6.6/730-net-ethernet-mtk_eth_soc-reset-all-TX-queues-on-DMA-.patch deleted file mode 100644 index 8d8e3d83ba..0000000000 --- a/target/linux/generic/pending-6.6/730-net-ethernet-mtk_eth_soc-reset-all-TX-queues-on-DMA-.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 7d41a5a8e9c91cc6bb011dd953570738583dd091 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 18 Sep 2024 02:01:01 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: reset all TX queues on DMA free - -The purpose of resetting the TX queue is to reset the -byte and packet count as well as to clear the software -flow control XOFF bit. - -MediaTek developers pointed out that netdev_reset_queue would only -resets queue 0 of the network device. -Queues that are not reset may cause unexpected issues. - -Packets may stop being sent after reset and "transmit timeout" log may -be displayed. - -Import fix from MediaTek's SDK to resolve this issue. - -Signed-off-by: Daniel Golle ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 18 ++++++++++++++---- - 1 file changed, 14 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3149,11 +3149,19 @@ static int mtk_dma_init(struct mtk_eth * - static void mtk_dma_free(struct mtk_eth *eth) - { - const struct mtk_soc_data *soc = eth->soc; -- int i; -+ int i, j, txqs = 1; -+ -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) -+ txqs = MTK_QDMA_NUM_QUEUES; -+ -+ for (i = 0; i < MTK_MAX_DEVS; i++) { -+ if (!eth->netdev[i]) -+ continue; -+ -+ for (j = 0; j < txqs; j++) -+ netdev_tx_reset_queue(netdev_get_tx_queue(eth->netdev[i], j)); -+ } - -- for (i = 0; i < MTK_MAX_DEVS; i++) -- if (eth->netdev[i]) -- netdev_reset_queue(eth->netdev[i]); - if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { - dma_free_coherent(eth->dma_dev, - MTK_QDMA_RING_SIZE * soc->tx.desc_size, diff --git a/target/linux/layerscape/image/mkits-multiple-config.sh b/target/linux/layerscape/image/mkits-multiple-config.sh index b2d8f4ef7f..4d9c79d997 100755 --- a/target/linux/layerscape/image/mkits-multiple-config.sh +++ b/target/linux/layerscape/image/mkits-multiple-config.sh @@ -438,7 +438,7 @@ emit_config() { config_name="conf@${1}" if [ ! -z "${11}" ]; then config_name="${11}" - fi + fi if [ -z "${2}" ]; then echo "Error: config has no kernel img, skipping conf node!" return 0 @@ -512,7 +512,7 @@ emit_image_nodes() img_key=$(array_get $a 9) img_sign=$(array_get $a 10) img_cname=$(array_get $a 11) - + img_conf=$(remove_prefix_space $img_conf) img_hash=$(remove_prefix_space $img_hash) diff --git a/target/linux/malta/Makefile b/target/linux/malta/Makefile index 4417c1e0e4..4d5b42b074 100644 --- a/target/linux/malta/Makefile +++ b/target/linux/malta/Makefile @@ -11,6 +11,7 @@ INITRAMFS_EXTRA_FILES:= FEATURES:=cpiogz ext4 ramdisk squashfs targz KERNEL_PATCHVER:=6.6 +KERNEL_TESTING_PATCHVER:=6.12 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/malta/config-6.12 b/target/linux/malta/config-6.12 new file mode 100644 index 0000000000..1fb4a510d5 --- /dev/null +++ b/target/linux/malta/config-6.12 @@ -0,0 +1,276 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ATA=y +CONFIG_ATA_PIIX=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG_COMMON=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BOARD_SCACHE=y +CONFIG_BOOT_ELF32=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUILTIN_DTB=y +CONFIG_CEVT_R4K=y +CONFIG_CLKBLD_I8253=y +CONFIG_CLKEVT_I8253=y +CONFIG_CLKSRC_I8253=y +CONFIG_CLKSRC_MIPS_GIC=y +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_CPU_HAS_SMARTMIPS is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_CPU_MICROMIPS is not set +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS32_3_5_FEATURES is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS32_R5 is not set +# CONFIG_CPU_MIPS32_R5_FEATURES is not set +# CONFIG_CPU_MIPS32_R6 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_MIPS64_R6 is not set +# CONFIG_CPU_MIPSR1 is not set +# CONFIG_CPU_MIPSR2 is not set +# CONFIG_CPU_MIPSR2_IRQ_EI is not set +# CONFIG_CPU_MIPSR2_IRQ_VI is not set +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +# CONFIG_CPU_NEVADA is not set +CONFIG_CPU_R4K_CACHE_TLB=y +# CONFIG_CPU_RM7000 is not set +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CRC16=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_F2FS_FS=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIO_CDEV=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_I8259=y +CONFIG_INPUT=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_ISA_DMA_API=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MD=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_BONITO64=y +CONFIG_MIPS_CLOCK_VSYSCALL=y +CONFIG_MIPS_CM=y +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y +CONFIG_MIPS_CPC=y +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_MIPS_GIC=y +CONFIG_MIPS_L1_CACHE_SHIFT=6 +CONFIG_MIPS_L1_CACHE_SHIFT_6=y +CONFIG_MIPS_MALTA=y +CONFIG_MIPS_MSC=y +CONFIG_MIPS_MT=y +CONFIG_MIPS_MT_FPAFF=y +CONFIG_MIPS_MT_SMP=y +CONFIG_MIPS_NO_APPENDED_DTB=y +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_CFI_STAA=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PATA_LEGACY=y +CONFIG_PATA_TIMINGS=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PCI_GT64XXX_PCI0=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_PIIX4_POWEROFF=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_QFMT_V2=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +CONFIG_QUOTA_TREE=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RELAY=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_SATA_HOST=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y +CONFIG_SYS_HAS_CPU_MIPS32_R5=y +CONFIG_SYS_HAS_CPU_MIPS32_R6=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_SYS_HAS_CPU_MIPS64_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R6=y +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_MICROMIPS=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MIPS_CPS=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_RELOCATABLE=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMARTMIPS=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_SYS_SUPPORTS_VPE_LOADER=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_TARGET_ISA_REV=1 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_VXFS_FS=y +CONFIG_WAR_ICACHE_REFILLS=y +CONFIG_XPS=y +CONFIG_ZBOOT_LOAD_ADDRESS=0x0 diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile index 478b00488b..318f26299d 100644 --- a/target/linux/mediatek/Makefile +++ b/target/linux/mediatek/Makefile @@ -9,6 +9,7 @@ SUBTARGETS:=filogic mt7622 mt7623 mt7629 FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb KERNEL_PATCHVER:=6.6 +KERNEL_TESTING_PATCHVER:=6.12 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ diff --git a/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh b/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh index e9cb4f921d..1a9ddc679d 100644 --- a/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh +++ b/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh @@ -12,6 +12,7 @@ unielec,u7623-02) bananapi,bpi-r3|\ bananapi,bpi-r3-mini|\ bananapi,bpi-r4|\ +bananapi,bpi-r4-2g5|\ bananapi,bpi-r4-poe) [ -z "$(fw_printenv -n ethaddr 2>/dev/null)" ] && fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)" diff --git a/target/linux/mediatek/dts/mt7981a-comfast-cf-e393ax.dts b/target/linux/mediatek/dts/mt7981a-comfast-cf-e393ax.dts index 22e48259e3..8f7598fc7c 100644 --- a/target/linux/mediatek/dts/mt7981a-comfast-cf-e393ax.dts +++ b/target/linux/mediatek/dts/mt7981a-comfast-cf-e393ax.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "COMFAST CF-E393AX"; diff --git a/target/linux/mediatek/dts/mt7981a-edgecore-eap111.dts b/target/linux/mediatek/dts/mt7981a-edgecore-eap111.dts index 0e7c4fe8b5..7844d11eb5 100644 --- a/target/linux/mediatek/dts/mt7981a-edgecore-eap111.dts +++ b/target/linux/mediatek/dts/mt7981a-edgecore-eap111.dts @@ -3,7 +3,7 @@ /dts-v1/; #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Edgecore EAP111"; diff --git a/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000-xe3000-common.dtsi b/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000-xe3000-common.dtsi index 2e6d502cfa..b475775b36 100644 --- a/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000-xe3000-common.dtsi +++ b/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000-xe3000-common.dtsi @@ -2,7 +2,7 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { chosen { diff --git a/target/linux/mediatek/dts/mt7981a-ubnt-unifi-6-plus.dts b/target/linux/mediatek/dts/mt7981a-ubnt-unifi-6-plus.dts index 0e6e0cd964..1d73b0f7f3 100644 --- a/target/linux/mediatek/dts/mt7981a-ubnt-unifi-6-plus.dts +++ b/target/linux/mediatek/dts/mt7981a-ubnt-unifi-6-plus.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Ubiquiti UniFi 6 Plus"; diff --git a/target/linux/mediatek/dts/mt7981b-abt-asr3000.dts b/target/linux/mediatek/dts/mt7981b-abt-asr3000.dts index b0d63975da..2eb616ee39 100644 --- a/target/linux/mediatek/dts/mt7981b-abt-asr3000.dts +++ b/target/linux/mediatek/dts/mt7981b-abt-asr3000.dts @@ -4,7 +4,7 @@ #include #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "ABT ASR3000"; diff --git a/target/linux/mediatek/dts/mt7981b-asus-rt-ax52.dts b/target/linux/mediatek/dts/mt7981b-asus-rt-ax52.dts index 7f4926b493..34cc8ee131 100644 --- a/target/linux/mediatek/dts/mt7981b-asus-rt-ax52.dts +++ b/target/linux/mediatek/dts/mt7981b-asus-rt-ax52.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "ASUS RT-AX52"; compatible = "asus,rt-ax52", "mediatek,mt7981"; diff --git a/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dtsi b/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dtsi index 7e61c55358..cba9bcd875 100644 --- a/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dtsi +++ b/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dtsi @@ -5,7 +5,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { aliases { diff --git a/target/linux/mediatek/dts/mt7981b-cmcc-a10.dtsi b/target/linux/mediatek/dts/mt7981b-cmcc-a10.dtsi index 06d829e087..91644746a6 100644 --- a/target/linux/mediatek/dts/mt7981b-cmcc-a10.dtsi +++ b/target/linux/mediatek/dts/mt7981b-cmcc-a10.dtsi @@ -7,7 +7,7 @@ #include #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { aliases { diff --git a/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts b/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts index 977a613333..a6803fe7da 100644 --- a/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts +++ b/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts @@ -8,7 +8,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "CMCC RAX3000M"; diff --git a/target/linux/mediatek/dts/mt7981b-confiabits-mt7981.dts b/target/linux/mediatek/dts/mt7981b-confiabits-mt7981.dts index 8b9c7a7547..544ece08cd 100644 --- a/target/linux/mediatek/dts/mt7981b-confiabits-mt7981.dts +++ b/target/linux/mediatek/dts/mt7981b-confiabits-mt7981.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" #include #include #include diff --git a/target/linux/mediatek/dts/mt7981b-cudy-ap3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-ap3000-v1.dts index 7101c4bab0..a093ae99a1 100644 --- a/target/linux/mediatek/dts/mt7981b-cudy-ap3000-v1.dts +++ b/target/linux/mediatek/dts/mt7981b-cudy-ap3000-v1.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Cudy AP3000 v1"; diff --git a/target/linux/mediatek/dts/mt7981b-cudy-ap3000outdoor-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-ap3000outdoor-v1.dts index b0c6524554..dbb21797ab 100644 --- a/target/linux/mediatek/dts/mt7981b-cudy-ap3000outdoor-v1.dts +++ b/target/linux/mediatek/dts/mt7981b-cudy-ap3000outdoor-v1.dts @@ -4,7 +4,7 @@ #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Cudy AP3000 Outdoor v1"; diff --git a/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts index cfe9d45630..a4fc33e916 100644 --- a/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts +++ b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Cudy M3000 v1"; diff --git a/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts index 19c004e8fc..e1df653800 100644 --- a/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts +++ b/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts @@ -6,7 +6,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Cudy RE3000 v1"; diff --git a/target/linux/mediatek/dts/mt7981b-cudy-tr3000-v1.dtsi b/target/linux/mediatek/dts/mt7981b-cudy-tr3000-v1.dtsi index 25e0ec0896..d2ad7ab7f5 100644 --- a/target/linux/mediatek/dts/mt7981b-cudy-tr3000-v1.dtsi +++ b/target/linux/mediatek/dts/mt7981b-cudy-tr3000-v1.dtsi @@ -1,10 +1,8 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /dts-v1/; - #include - -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { aliases { diff --git a/target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts index 0f33223bb7..b3864d099d 100644 --- a/target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts +++ b/target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts @@ -4,7 +4,7 @@ #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Cudy WR3000 v1"; diff --git a/target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts index 71760b2088..d34c6f2bbc 100644 --- a/target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts +++ b/target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts @@ -4,7 +4,7 @@ #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Cudy WR3000H v1"; diff --git a/target/linux/mediatek/dts/mt7981b-cudy-wr3000s-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-wr3000s-v1.dts index bdc6188a4a..c866864e35 100644 --- a/target/linux/mediatek/dts/mt7981b-cudy-wr3000s-v1.dts +++ b/target/linux/mediatek/dts/mt7981b-cudy-wr3000s-v1.dts @@ -4,7 +4,7 @@ #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Cudy WR3000S v1"; diff --git a/target/linux/mediatek/dts/mt7981b-dlink-aquila-pro-ai-m30-a1.dts b/target/linux/mediatek/dts/mt7981b-dlink-aquila-pro-ai-m30-a1.dts index be2bfcfb36..66a172b09c 100644 --- a/target/linux/mediatek/dts/mt7981b-dlink-aquila-pro-ai-m30-a1.dts +++ b/target/linux/mediatek/dts/mt7981b-dlink-aquila-pro-ai-m30-a1.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "D-Link AQUILA PRO AI M30 A1"; diff --git a/target/linux/mediatek/dts/mt7981b-gatonetworks-gdsp.dts b/target/linux/mediatek/dts/mt7981b-gatonetworks-gdsp.dts index 219fd89934..ad09ff8bcd 100644 --- a/target/linux/mediatek/dts/mt7981b-gatonetworks-gdsp.dts +++ b/target/linux/mediatek/dts/mt7981b-gatonetworks-gdsp.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "GatoNetworks GDSP"; diff --git a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts index 8c878a5c8e..bd0e03916c 100644 --- a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts +++ b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "GL.iNet GL-MT2500"; diff --git a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt3000.dts b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt3000.dts index 5e718069a2..606e36a5cd 100644 --- a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt3000.dts +++ b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt3000.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "GL.iNet GL-MT3000"; diff --git a/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts b/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts index e3b4e00beb..91ea08fe9b 100644 --- a/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts +++ b/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts @@ -5,7 +5,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "H3C Magic NX30 Pro"; diff --git a/target/linux/mediatek/dts/mt7981b-huasifei-wh3000-emmc.dts b/target/linux/mediatek/dts/mt7981b-huasifei-wh3000-emmc.dts index 93a4f50a13..fa253ed64e 100644 --- a/target/linux/mediatek/dts/mt7981b-huasifei-wh3000-emmc.dts +++ b/target/linux/mediatek/dts/mt7981b-huasifei-wh3000-emmc.dts @@ -5,7 +5,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Huasifei WH3000 eMMC version"; diff --git a/target/linux/mediatek/dts/mt7981b-imou-lc-hx3001.dts b/target/linux/mediatek/dts/mt7981b-imou-lc-hx3001.dts index a5a99d8383..d499ccd774 100644 --- a/target/linux/mediatek/dts/mt7981b-imou-lc-hx3001.dts +++ b/target/linux/mediatek/dts/mt7981b-imou-lc-hx3001.dts @@ -8,7 +8,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Imou LC-HX3001"; diff --git a/target/linux/mediatek/dts/mt7981b-jcg-q30-pro.dts b/target/linux/mediatek/dts/mt7981b-jcg-q30-pro.dts index 3f543b3ad1..e9ac20747e 100644 --- a/target/linux/mediatek/dts/mt7981b-jcg-q30-pro.dts +++ b/target/linux/mediatek/dts/mt7981b-jcg-q30-pro.dts @@ -5,7 +5,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "JCG Q30 PRO"; diff --git a/target/linux/mediatek/dts/mt7981b-keenetic-kn-3811.dts b/target/linux/mediatek/dts/mt7981b-keenetic-kn-3811.dts index 87043ec907..4d82fb8caf 100644 --- a/target/linux/mediatek/dts/mt7981b-keenetic-kn-3811.dts +++ b/target/linux/mediatek/dts/mt7981b-keenetic-kn-3811.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Keenetic KN-3811"; diff --git a/target/linux/mediatek/dts/mt7981b-keenetic-kn-3911.dts b/target/linux/mediatek/dts/mt7981b-keenetic-kn-3911.dts index 8a9bf0f1a9..0fc2cf83f3 100644 --- a/target/linux/mediatek/dts/mt7981b-keenetic-kn-3911.dts +++ b/target/linux/mediatek/dts/mt7981b-keenetic-kn-3911.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Keenetic KN-3911"; diff --git a/target/linux/mediatek/dts/mt7981b-konka-komi-a31.dts b/target/linux/mediatek/dts/mt7981b-konka-komi-a31.dts index ee9415c934..7263a3e07f 100644 --- a/target/linux/mediatek/dts/mt7981b-konka-komi-a31.dts +++ b/target/linux/mediatek/dts/mt7981b-konka-komi-a31.dts @@ -4,7 +4,7 @@ #include #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Konka KOMI A31"; diff --git a/target/linux/mediatek/dts/mt7981b-livinet-zr-3020.dtsi b/target/linux/mediatek/dts/mt7981b-livinet-zr-3020.dtsi index d876375dc5..a9b243c493 100644 --- a/target/linux/mediatek/dts/mt7981b-livinet-zr-3020.dtsi +++ b/target/linux/mediatek/dts/mt7981b-livinet-zr-3020.dtsi @@ -6,7 +6,7 @@ /dts-v1/; #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { aliases { diff --git a/target/linux/mediatek/dts/mt7981b-mercusys-mr80x-v3.dts b/target/linux/mediatek/dts/mt7981b-mercusys-mr80x-v3.dts index 3bd59f75a6..377c1c71fd 100644 --- a/target/linux/mediatek/dts/mt7981b-mercusys-mr80x-v3.dts +++ b/target/linux/mediatek/dts/mt7981b-mercusys-mr80x-v3.dts @@ -4,7 +4,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "MERCUSYS MR80X v3"; compatible = "mercusys,mr80x-v3", "mediatek,mt7981"; diff --git a/target/linux/mediatek/dts/mt7981b-netis-nx31.dts b/target/linux/mediatek/dts/mt7981b-netis-nx31.dts index f5e8990233..c93a3fa018 100644 --- a/target/linux/mediatek/dts/mt7981b-netis-nx31.dts +++ b/target/linux/mediatek/dts/mt7981b-netis-nx31.dts @@ -5,7 +5,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "netis NX31"; diff --git a/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts b/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts index 119ec5711f..7b1561a07d 100644 --- a/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts +++ b/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts @@ -4,7 +4,7 @@ #include #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Nokia EA0326GMP"; diff --git a/target/linux/mediatek/dts/mt7981b-nradio-c8-668gl.dts b/target/linux/mediatek/dts/mt7981b-nradio-c8-668gl.dts index e0110def07..5361809d16 100644 --- a/target/linux/mediatek/dts/mt7981b-nradio-c8-668gl.dts +++ b/target/linux/mediatek/dts/mt7981b-nradio-c8-668gl.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "NRadio C8-668GL"; diff --git a/target/linux/mediatek/dts/mt7981b-openembed-som7981.dts b/target/linux/mediatek/dts/mt7981b-openembed-som7981.dts index 53d376d34c..a2b3e70552 100644 --- a/target/linux/mediatek/dts/mt7981b-openembed-som7981.dts +++ b/target/linux/mediatek/dts/mt7981b-openembed-som7981.dts @@ -5,7 +5,7 @@ #include #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "OpenEmbed SOM7981"; diff --git a/target/linux/mediatek/dts/mt7981b-openwrt-one.dts b/target/linux/mediatek/dts/mt7981b-openwrt-one.dts index ad08525807..d1a24db38a 100644 --- a/target/linux/mediatek/dts/mt7981b-openwrt-one.dts +++ b/target/linux/mediatek/dts/mt7981b-openwrt-one.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "OpenWrt One"; diff --git a/target/linux/mediatek/dts/mt7981b-qihoo-360t7.dts b/target/linux/mediatek/dts/mt7981b-qihoo-360t7.dts index f167600f30..db7fa5e870 100644 --- a/target/linux/mediatek/dts/mt7981b-qihoo-360t7.dts +++ b/target/linux/mediatek/dts/mt7981b-qihoo-360t7.dts @@ -5,7 +5,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Qihoo 360T7"; diff --git a/target/linux/mediatek/dts/mt7981b-routerich-ax3000-common.dtsi b/target/linux/mediatek/dts/mt7981b-routerich-ax3000-common.dtsi index f0b0b9365b..9b41774b88 100644 --- a/target/linux/mediatek/dts/mt7981b-routerich-ax3000-common.dtsi +++ b/target/linux/mediatek/dts/mt7981b-routerich-ax3000-common.dtsi @@ -5,7 +5,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { aliases { diff --git a/target/linux/mediatek/dts/mt7981b-routerich-ax3000-v1.dts b/target/linux/mediatek/dts/mt7981b-routerich-ax3000-v1.dts index ba70fc807b..2643d5dab7 100644 --- a/target/linux/mediatek/dts/mt7981b-routerich-ax3000-v1.dts +++ b/target/linux/mediatek/dts/mt7981b-routerich-ax3000-v1.dts @@ -5,7 +5,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Routerich AX3000 v1"; diff --git a/target/linux/mediatek/dts/mt7981b-snr-snr-cpe-ax2.dts b/target/linux/mediatek/dts/mt7981b-snr-snr-cpe-ax2.dts new file mode 100644 index 0000000000..9ccea15b47 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-snr-snr-cpe-ax2.dts @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; +#include +#include +#include + +#include "mt7981b.dtsi" + +/ { + model = "SNR SNR-CPE-AX2"; + compatible = "snr,snr-cpe-ax2", "mediatek,mt7981"; + + aliases { + label-mac-device = &gmac0; + + led-boot = &led_status; + led-failsafe = &led_fail; + led-running = &led_status; + led-upgrade = &led_fail; + + serial0 = &uart0; + }; + + chosen { + rootdisk = <&ubi_fit_volume>; + stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/fit0 rootwait"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-0 { + label = "mesh"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + }; + + button-1 { + label = "reset"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; // Second WAN led defined below. + gpios = <&pio 4 GPIO_ACTIVE_LOW>; + }; + + led_fail: led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_WLAN_2GHZ; + gpios = <&pio 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + led-3 { + color = ; + function = LED_FUNCTION_WLAN_5GHZ; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led_status: led-4 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-5 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + led-6 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_e000 0>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; +}; + +&mdio_bus { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <0x1f>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4e 0x41 0x4e 0x44>; + spi-cal-addrlen = <5>; + spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env (unused)"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "Factory"; + reg = <0x180000 0x200000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_e000: macaddr@e000 { + compatible = "mac-base"; + reg = <0xe000 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_e006: macaddr@e006 { + compatible = "mac-base"; + reg = <0xe006 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_100004: macaddr@100004 { + compatible = "mac-base"; + reg = <0x100004 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7a80000>; + compatible = "linux,ubi"; + + volumes { + ubi_fit_volume: ubi-volume-fit { + volname = "fit"; + }; + + ubi_ubootenv: ubi-volume-ubootenv { + volname = "ubootenv"; + }; + + ubi_ubootenv2: ubi-volume-ubootenv2 { + volname = "ubootenv2"; + }; + }; + }; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_e006 0>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&ubi_ubootenv { + nvmem-layout { + compatible = "u-boot,env-redundant-bool"; + }; +}; + +&ubi_ubootenv2 { + nvmem-layout { + compatible = "u-boot,env-redundant-bool"; + }; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + nvmem-cell-names = "eeprom"; + nvmem-cells = <&eeprom_factory_0>; + + band@0 { + reg = <0>; + nvmem-cells = <&macaddr_factory_4 0>; + nvmem-cell-names = "mac-address"; + }; + + band@1 { + reg = <1>; + nvmem-cells = <&macaddr_factory_100004 0>; + nvmem-cell-names = "mac-address"; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-tenbay-wr3000k.dts b/target/linux/mediatek/dts/mt7981b-tenbay-wr3000k.dts index 2ae16673af..e372a69a76 100644 --- a/target/linux/mediatek/dts/mt7981b-tenbay-wr3000k.dts +++ b/target/linux/mediatek/dts/mt7981b-tenbay-wr3000k.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Tenbay WR3000K"; diff --git a/target/linux/mediatek/dts/mt7981b-unielec-u7981-01.dtsi b/target/linux/mediatek/dts/mt7981b-unielec-u7981-01.dtsi index 6e6150ba21..ea5ab2d9f2 100644 --- a/target/linux/mediatek/dts/mt7981b-unielec-u7981-01.dtsi +++ b/target/linux/mediatek/dts/mt7981b-unielec-u7981-01.dtsi @@ -4,7 +4,7 @@ */ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Unielec U7981-01 (EMMC)"; compatible = "unielec,u7981-01-emmc", "mediatek,mt7981"; diff --git a/target/linux/mediatek/dts/mt7981b-wavlink-wl-wn573hx3.dts b/target/linux/mediatek/dts/mt7981b-wavlink-wl-wn573hx3.dts index 64e577887a..e5118bc3d1 100644 --- a/target/linux/mediatek/dts/mt7981b-wavlink-wl-wn573hx3.dts +++ b/target/linux/mediatek/dts/mt7981b-wavlink-wl-wn573hx3.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "WAVLINK WL-WN573HX3"; diff --git a/target/linux/mediatek/dts/mt7981b-wavlink-wl-wn586x3.dts b/target/linux/mediatek/dts/mt7981b-wavlink-wl-wn586x3.dts index d6d9a9fee6..9190134e35 100644 --- a/target/linux/mediatek/dts/mt7981b-wavlink-wl-wn586x3.dts +++ b/target/linux/mediatek/dts/mt7981b-wavlink-wl-wn586x3.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "WAVLINK WL-WN586X3"; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi index 511184d771..ceb238bde2 100644 --- a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi +++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi @@ -4,7 +4,7 @@ #include #include -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { aliases { diff --git a/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts b/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts index 485b8dbd36..eada07b7ab 100644 --- a/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts +++ b/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { compatible = "yuncore,ax835", "mediatek,mt7981"; diff --git a/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts index 4b0921656a..d58ea48fc3 100644 --- a/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts +++ b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Zbtlink ZBT-Z8102AX"; diff --git a/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dts b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dts index c313e08288..3dfbbec3cf 100644 --- a/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dts +++ b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Zbtlink ZBT-Z8103AX"; diff --git a/target/linux/mediatek/dts/mt7981b-zyxel-nwa50ax-pro.dts b/target/linux/mediatek/dts/mt7981b-zyxel-nwa50ax-pro.dts index 887455988a..c3c325560c 100644 --- a/target/linux/mediatek/dts/mt7981b-zyxel-nwa50ax-pro.dts +++ b/target/linux/mediatek/dts/mt7981b-zyxel-nwa50ax-pro.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "Zyxel NWA50AX Pro"; diff --git a/target/linux/mediatek/dts/mt7988a-arcadyan-mozart.dts b/target/linux/mediatek/dts/mt7988a-arcadyan-mozart.dts index f6752e340a..f6ee498ae0 100644 --- a/target/linux/mediatek/dts/mt7988a-arcadyan-mozart.dts +++ b/target/linux/mediatek/dts/mt7988a-arcadyan-mozart.dts @@ -11,7 +11,7 @@ model = "MediaTek / Arcadyan - Mozart"; aliases { - serial0 = &uart0; + serial0 = &serial0; led-boot = &led_status_blue; led-failsafe = &led_status_red; led-running = &led_status_green; @@ -59,26 +59,16 @@ gpios = <&pio 13 GPIO_ACTIVE_LOW>; }; }; -}; -&pio { - mdio0_pins: mdio0-pins { - mux { - function = "eth"; - groups = "mdc_mdio0"; - }; + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + #thermal-sensor-cells = <1>; + /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ + cooling-levels = <0 128 255>; + pwms = <&pwm 1 40000 0>; - conf { - groups = "mdc_mdio0"; - drive-strength = ; - }; - }; - - spic_pins: spi1-pins { - mux { - function = "spi"; - groups = "spi1"; - }; + status = "okay"; }; }; @@ -173,12 +163,7 @@ }; }; -&uart1 { - status = "okay"; -}; - -&fan { - pwms = <&pwm 1 40000 0>; +&serial1 { status = "okay"; }; @@ -189,7 +174,7 @@ &spi1 { pinctrl-names = "default"; /* pin shared with snfi */ - pinctrl-0 = <&spic_pins>; + pinctrl-0 = <&spi1_pins>; status = "disabled"; }; diff --git a/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi b/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi index 058a96f253..302e8a8101 100644 --- a/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi +++ b/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi @@ -14,7 +14,7 @@ / { aliases { - serial0 = &uart0; + serial0 = &serial0; label-mac-device = &gmac1; led-boot = &led_sys_green; led-failsafe = &led_sys_blue; @@ -23,7 +23,7 @@ }; chosen { - stdout-path = &uart0; + stdout-path = &serial0; bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf root=PARTLABEL=rootfs"; }; @@ -129,6 +129,32 @@ gpios = <&pio 63 GPIO_ACTIVE_HIGH>; }; }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + #thermal-sensor-cells = <1>; + + pwms = <&pwm 0 40000 0>; + + /** + * set fan speed + * + * 0 = off + * 61 = 24% duty cycle + * 77 = 30% duty cycle + * 102 = 40% duty cycle + * 128 - 50% duty cycle + * 255 = 100% duty cycle + */ + cooling-levels = <61 77 102 128>; + + interrupt-parent = <&pio>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + pulses-per-revolution = <2>; + + status = "okay"; + }; }; &cpu0 { @@ -226,28 +252,6 @@ status = "okay"; }; -&fan { - pwms = <&pwm 0 40000 0>; - - /** - * set fan speed - * - * 0 = off - * 61 = 24% duty cycle - * 77 = 30% duty cycle - * 102 = 40% duty cycle - * 128 - 50% duty cycle - * 255 = 100% duty cycle - */ - cooling-levels = <61 77 102 128>; - - interrupt-parent = <&pio>; - interrupts = <21 IRQ_TYPE_EDGE_FALLING>; - pulses-per-revolution = <2>; - - status = "okay"; -}; - &gmac0 { nvmem-cells = <&macaddr 1>; nvmem-cell-names = "mac-address"; @@ -286,11 +290,13 @@ &gsw_phy1_led0 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; &gsw_phy1_led1 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; @@ -301,11 +307,13 @@ &gsw_phy2_led0 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; &gsw_phy2_led1 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; @@ -316,11 +324,13 @@ &gsw_phy3_led0 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; &gsw_phy3_led1 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; @@ -603,6 +613,81 @@ mediatek,pull-down-adv = <0>; /* bias-disable */ }; + gbe1_led0_pins: gbe1-led0-pins { + mux { + function = "led"; + groups = "gbe1_led0"; + }; + }; + + gbe2_led0_pins: gbe2-led0-pins { + mux { + function = "led"; + groups = "gbe2_led0"; + }; + }; + + gbe3_led0_pins: gbe3-led0-pins { + mux { + function = "led"; + groups = "gbe3_led0"; + }; + }; + + gbe1_led1_pins: gbe1-led1-pins { + mux { + function = "led"; + groups = "gbe1_led1"; + }; + }; + + gbe2_led1_pins: gbe2-led1-pins { + mux { + function = "led"; + groups = "gbe2_led1"; + }; + }; + + gbe3_led1_pins: gbe3-led1-pins { + mux { + function = "led"; + groups = "gbe3_led1"; + }; + }; + + i2c0_pins: i2c0-g0-pins { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; + + i2c1_pins: i2c1-g0-pins { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio0"; + }; + + conf { + groups = "mdc_mdio0"; + drive-strength = ; + }; + }; + + mmc0_pins_emmc_51: mmc0-emmc-51-pins { + mux { + function = "flash"; + groups = "emmc_51"; + }; + }; + pcie0_1_pins: pcie0-pins-g1 { mux { function = "pcie"; @@ -617,6 +702,13 @@ }; }; + spi0_flash_pins: spi0-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + sfp_i2c_pins: sfp-i2c-pins { conf-scl { pins = "LED_A"; @@ -643,6 +735,8 @@ groups = "uart2"; }; }; + + }; &pwm { @@ -700,11 +794,11 @@ status = "okay"; }; -&uart0 { +&serial0 { status = "okay"; }; -&uart1 { +&serial1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; status = "okay"; @@ -712,7 +806,7 @@ /* Airoha AG3352 GPS */ }; -&uart2 { +&serial2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; status = "okay"; @@ -724,6 +818,6 @@ status = "okay"; }; -&xphy { +&xsphy { status = "okay"; }; diff --git a/target/linux/mediatek/dts/mt7988d-asus-zenwifi-bt8.dts b/target/linux/mediatek/dts/mt7988d-asus-zenwifi-bt8.dts index 02c1be1457..1f95a01fbe 100644 --- a/target/linux/mediatek/dts/mt7988d-asus-zenwifi-bt8.dts +++ b/target/linux/mediatek/dts/mt7988d-asus-zenwifi-bt8.dts @@ -21,8 +21,8 @@ compatible = "u-boot-dont-touch-spi-nand"; reg = <0>; spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions"; diff --git a/target/linux/mediatek/dts/mt7988d-asus-zenwifi-bt8.dtsi b/target/linux/mediatek/dts/mt7988d-asus-zenwifi-bt8.dtsi index e865f2a678..20e7a3839c 100644 --- a/target/linux/mediatek/dts/mt7988d-asus-zenwifi-bt8.dtsi +++ b/target/linux/mediatek/dts/mt7988d-asus-zenwifi-bt8.dtsi @@ -78,7 +78,7 @@ / { aliases { - serial0 = &uart0; + serial0 = &serial0; label-mac-device = &gmac0; led-boot = &led_status_green; led-failsafe = &led_status_red; @@ -189,11 +189,6 @@ status = "okay"; }; -&int_2p5g_phy { - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; -}; - &gmac2 { phy-mode = "2500base-x"; phy = <&phy5>; @@ -307,6 +302,32 @@ mediatek,pull-down-adv = <0>; /* bias-disable */ }; + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio0"; + }; + + conf { + groups = "mdc_mdio0"; + drive-strength = ; + }; + }; + + i2c0_pins: i2c0-g0-pins { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; + + spi0_flash_pins: spi0-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + pcie0_1_pins: pcie0-pins-g1 { mux { function = "pcie"; @@ -352,7 +373,7 @@ status = "okay"; }; -&uart0 { +&serial0 { status = "okay"; }; @@ -360,7 +381,7 @@ status = "okay"; }; -&xphy { +&xsphy { status = "okay"; }; diff --git a/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts b/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts index b72ef48bea..0d0ecddfae 100644 --- a/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts +++ b/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts @@ -88,6 +88,13 @@ }; &pio { + i2p5gbe_led0_pins: 2p5gbe-led0-pins { + mux { + function = "led"; + groups = "2p5gbe_led0"; + }; + }; + pcie3_1_pins: pcie3-pins-g1 { mux { function = "pcie"; @@ -129,6 +136,7 @@ &i2p5gbe_led0 { color = ; + function = LED_FUNCTION_LAN; status = "okay"; }; @@ -148,10 +156,10 @@ status = "disabled"; }; -&uart1 { +&serial1 { status = "disabled"; }; -&xphy { +&xsphy { status = "disabled"; }; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso new file mode 100644 index 0000000000..51d5dc661a --- /dev/null +++ b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; + + fragment@0 { + target = <&gmac1>; + __overlay__ { + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + }; + }; + + fragment@1 { + target = <&mdio_bus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>; + reset-delay-us = <600>; + reset-post-delay-us = <20000>; + + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + }; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso new file mode 100644 index 0000000000..4cc3cf1df6 --- /dev/null +++ b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; + + fragment@0 { + target = <&sw_p5>; + __overlay__ { + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&mdio_bus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>; + reset-delay-us = <600>; + reset-post-delay-us = <20000>; + + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + }; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso new file mode 100644 index 0000000000..af4845ec6c --- /dev/null +++ b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/dts-v1/; +/plugin/; + +/ { + compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; + + fragment@0 { + target = <&chosen>; + rootdisk-spim-nand = <&ubi_rootdisk>; + }; + + fragment@1 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + spi_nand: spi_nand@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <10000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x0200000>; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x4000000>; + compatible = "linux,ubi"; + + volumes { + ubi_rootdisk: ubi-volume-fit { + volname = "fit"; + }; + }; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&wifi>; + __overlay__ { + mediatek,mtd-eeprom = <&factory 0x0>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts new file mode 100644 index 0000000000..6fca59d3ef --- /dev/null +++ b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7981b.dtsi" + +/ { + model = "MediaTek MT7981 RFB"; + compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; + + aliases { + serial0 = &uart0; + }; + + chosen: chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/fit0 rootwait"; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + }; +}; + +&mdio_bus { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&crypto { + status = "okay"; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; + +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + cs-gpios = <0>, <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + sw_p5: port@5 { + reg = <5>; + label = "lan5"; + status = "disabled"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&xhci { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts new file mode 100644 index 0000000000..479a5ca2fc --- /dev/null +++ b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ + +#include "mt7986a-rfb.dtsi" + +/ { + compatible = "mediatek,mt7986a-rfb-snand"; +}; + +&spi0 { + status = "okay"; + + spi_nand: spi_nand@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <10000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + }; + partition@380000 { + label = "FIP"; + reg = <0x380000 0x0200000>; + }; + partition@580000 { + label = "ubi"; + reg = <0x580000 0x4000000>; + }; + }; + }; +}; + +&wifi { + mediatek,mtd-eeprom = <&factory 0>; +}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts new file mode 100644 index 0000000000..ea148315f0 --- /dev/null +++ b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ + +#include "mt7986a-rfb.dtsi" + +/ { + compatible = "mediatek,mt7986a-rfb-snor"; +}; + +&spi0 { + status = "okay"; + + spi_nor: spi_nor@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@00000 { + label = "BL2"; + reg = <0x00000 0x0040000>; + }; + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x0010000>; + }; + factory: partition@50000 { + label = "Factory"; + reg = <0x50000 0x00B0000>; + }; + partition@100000 { + label = "FIP"; + reg = <0x100000 0x0080000>; + }; + partition@180000 { + label = "firmware"; + reg = <0x180000 0xE00000>; + }; + }; + }; +}; + +&wifi { + mediatek,mtd-eeprom = <&factory 0>; +}; diff --git a/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi new file mode 100644 index 0000000000..26d560bd4b --- /dev/null +++ b/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7986a.dtsi" + +/ { + model = "MediaTek MT7986a RFB"; + compatible = "mediatek,mt7986a-rfb"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; + +&mdio { + phy5: phy@5 { + compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + + reset-gpios = <&pio 6 1>; + reset-deassert-us = <20000>; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + }; + + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 0>; + }; +}; + +&crypto { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pio { + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + spic_pins_g2: spic-pins-29-to-32 { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf_dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins_g2>; + status = "okay"; + + proslic_spi: proslic_spi@0 { + compatible = "silabs,proslic_spi"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-cpha = <1>; + spi-cpol = <1>; + channel_count = <1>; + debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ + reset_gpio = <&pio 7 0>; + ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ + }; +}; + +&gmac1 { + phy-mode = "2500base-x"; + phy-connection-type = "2500base-x"; + phy-handle = <&phy6>; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "lan6"; + + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; diff --git a/target/linux/mediatek/files-6.12/drivers/mfd/airoha-an8855.c b/target/linux/mediatek/files-6.12/drivers/mfd/airoha-an8855.c new file mode 100644 index 0000000000..eeaea348aa --- /dev/null +++ b/target/linux/mediatek/files-6.12/drivers/mfd/airoha-an8855.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MFD driver for Airoha AN8855 Switch + */ + +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell an8855_mfd_devs[] = { + { + .name = "an8855-efuse", + .of_compatible = "airoha,an8855-efuse", + }, { + .name = "an8855-switch", + .of_compatible = "airoha,an8855-switch", + }, { + .name = "an8855-mdio", + .of_compatible = "airoha,an8855-mdio", + } +}; + +int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id, + u8 page) __must_hold(&priv->bus->mdio_lock) +{ + struct mii_bus *bus = priv->bus; + int ret; + + ret = __mdiobus_write(bus, phy_id, AN8855_PHY_SELECT_PAGE, page); + if (ret < 0) + dev_err_ratelimited(&bus->dev, + "failed to set an8855 mii page\n"); + + /* Cache current page if next mii read/write is for switch */ + priv->current_page = page; + return ret < 0 ? ret : 0; +} +EXPORT_SYMBOL_GPL(an8855_mii_set_page); + +static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg, + u32 *val) __must_hold(&bus->mdio_lock) +{ + int lo, hi, ret; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE, + AN8855_PBUS_MODE_ADDR_FIXED); + if (ret < 0) + goto err; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH, + upper_16_bits(reg)); + if (ret < 0) + goto err; + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW, + lower_16_bits(reg)); + if (ret < 0) + goto err; + + hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH); + if (hi < 0) { + ret = hi; + goto err; + } + lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW); + if (lo < 0) { + ret = lo; + goto err; + } + + *val = ((u16)hi << 16) | ((u16)lo & 0xffff); + + return 0; +err: + dev_err_ratelimited(&bus->dev, + "failed to read an8855 register\n"); + return ret; +} + +static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val) +{ + struct an8855_mfd_priv *priv = ctx; + struct mii_bus *bus = priv->bus; + u16 addr = priv->switch_addr; + int ret; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4); + if (ret < 0) + goto exit; + + ret = an8855_mii_read32(bus, addr, reg, val); + +exit: + mutex_unlock(&bus->mdio_lock); + + return ret < 0 ? ret : 0; +} + +static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg, + u32 val) __must_hold(&bus->mdio_lock) +{ + int ret; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE, + AN8855_PBUS_MODE_ADDR_FIXED); + if (ret < 0) + goto err; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH, + upper_16_bits(reg)); + if (ret < 0) + goto err; + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW, + lower_16_bits(reg)); + if (ret < 0) + goto err; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH, + upper_16_bits(val)); + if (ret < 0) + goto err; + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW, + lower_16_bits(val)); + if (ret < 0) + goto err; + + return 0; +err: + dev_err_ratelimited(&bus->dev, + "failed to write an8855 register\n"); + return ret; +} + +static int +an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val) +{ + struct an8855_mfd_priv *priv = ctx; + struct mii_bus *bus = priv->bus; + u16 addr = priv->switch_addr; + int ret; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4); + if (ret < 0) + goto exit; + + ret = an8855_mii_write32(bus, addr, reg, val); + +exit: + mutex_unlock(&bus->mdio_lock); + + return ret < 0 ? ret : 0; +} + +static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, + uint32_t write_val) +{ + struct an8855_mfd_priv *priv = ctx; + struct mii_bus *bus = priv->bus; + u16 addr = priv->switch_addr; + u32 val; + int ret; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4); + if (ret < 0) + goto exit; + + ret = an8855_mii_read32(bus, addr, reg, &val); + if (ret < 0) + goto exit; + + val &= ~mask; + val |= write_val; + ret = an8855_mii_write32(bus, addr, reg, val); + +exit: + mutex_unlock(&bus->mdio_lock); + + return ret < 0 ? ret : 0; +} + +static const struct regmap_range an8855_readable_ranges[] = { + regmap_reg_range(0x10000000, 0x10000fff), /* SCU */ + regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */ + regmap_reg_range(0x10002000, 0x10002fff), /* MCU */ + regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */ + regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */ + regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */ + regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */ + regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */ + regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */ + regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */ + regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */ + regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */ + regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */ + regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */ + regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */ + regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */ + regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */ + regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */ + regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */ + regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */ + regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */ + regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */ + regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */ + regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */ + regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */ + regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */ + regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */ +}; + +static const struct regmap_access_table an8855_readable_table = { + .yes_ranges = an8855_readable_ranges, + .n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges), +}; + +static const struct regmap_config an8855_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0xbfffffff, + .reg_read = an8855_regmap_read, + .reg_write = an8855_regmap_write, + .reg_update_bits = an8855_regmap_update_bits, + .disable_locking = true, + .rd_table = &an8855_readable_table, +}; + +static int an8855_mfd_probe(struct mdio_device *mdiodev) +{ + struct an8855_mfd_priv *priv; + struct regmap *regmap; + + priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->bus = mdiodev->bus; + priv->dev = &mdiodev->dev; + priv->switch_addr = mdiodev->addr; + /* no DMA for mdiobus, mute warning for DMA mask not set */ + priv->dev->dma_mask = &priv->dev->coherent_dma_mask; + + regmap = devm_regmap_init(priv->dev, NULL, priv, + &an8855_regmap_config); + if (IS_ERR(regmap)) + dev_err_probe(priv->dev, PTR_ERR(priv->dev), + "regmap initialization failed\n"); + + dev_set_drvdata(&mdiodev->dev, priv); + + return devm_mfd_add_devices(priv->dev, PLATFORM_DEVID_AUTO, an8855_mfd_devs, + ARRAY_SIZE(an8855_mfd_devs), NULL, 0, + NULL); +} + +static const struct of_device_id an8855_mfd_of_match[] = { + { .compatible = "airoha,an8855-mfd" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, an8855_mfd_of_match); + +static struct mdio_driver an8855_mfd_driver = { + .probe = an8855_mfd_probe, + .mdiodrv.driver = { + .name = "an8855", + .of_match_table = an8855_mfd_of_match, + }, +}; +mdio_module_driver(an8855_mfd_driver); + +MODULE_AUTHOR("Christian Marangi "); +MODULE_DESCRIPTION("Driver for Airoha AN8855 MFD"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.c b/target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.c new file mode 100644 index 0000000000..e6666d2011 --- /dev/null +++ b/target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.c @@ -0,0 +1,2308 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Airoha AN8855 DSA Switch driver + * Copyright (C) 2023 Min Yao + * Copyright (C) 2024 Christian Marangi + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "an8855.h" + +static const struct an8855_mib_desc an8855_mib[] = { + MIB_DESC(1, AN8855_PORT_MIB_TX_DROP, "TxDrop"), + MIB_DESC(1, AN8855_PORT_MIB_TX_CRC_ERR, "TxCrcErr"), + MIB_DESC(1, AN8855_PORT_MIB_TX_COLLISION, "TxCollision"), + MIB_DESC(1, AN8855_PORT_MIB_TX_OVERSIZE_DROP, "TxOversizeDrop"), + MIB_DESC(2, AN8855_PORT_MIB_TX_BAD_PKT_BYTES, "TxBadPktBytes"), + MIB_DESC(1, AN8855_PORT_MIB_RX_DROP, "RxDrop"), + MIB_DESC(1, AN8855_PORT_MIB_RX_FILTERING, "RxFiltering"), + MIB_DESC(1, AN8855_PORT_MIB_RX_CRC_ERR, "RxCrcErr"), + MIB_DESC(1, AN8855_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"), + MIB_DESC(1, AN8855_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"), + MIB_DESC(1, AN8855_PORT_MIB_RX_ARL_DROP, "RxArlDrop"), + MIB_DESC(1, AN8855_PORT_MIB_FLOW_CONTROL_DROP, "FlowControlDrop"), + MIB_DESC(1, AN8855_PORT_MIB_WRED_DROP, "WredDrop"), + MIB_DESC(1, AN8855_PORT_MIB_MIRROR_DROP, "MirrorDrop"), + MIB_DESC(2, AN8855_PORT_MIB_RX_BAD_PKT_BYTES, "RxBadPktBytes"), + MIB_DESC(1, AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP, "RxsFlowSamplingPktDrop"), + MIB_DESC(1, AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP, "RxsFlowTotalPktDrop"), + MIB_DESC(1, AN8855_PORT_MIB_PORT_CONTROL_DROP, "PortControlDrop"), +}; + +static int +an8855_mib_init(struct an8855_priv *priv) +{ + int ret; + + ret = regmap_write(priv->regmap, AN8855_MIB_CCR, + AN8855_CCR_MIB_ENABLE); + if (ret) + return ret; + + return regmap_write(priv->regmap, AN8855_MIB_CCR, + AN8855_CCR_MIB_ACTIVATE); +} + +static void an8855_fdb_write(struct an8855_priv *priv, u16 vid, + u8 port_mask, const u8 *mac, + bool add) __must_hold(&priv->reg_mutex) +{ + u32 mac_reg[2] = { }; + u32 reg; + + mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC0, mac[0]); + mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC1, mac[1]); + mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC2, mac[2]); + mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC3, mac[3]); + mac_reg[1] |= FIELD_PREP(AN8855_ATA2_MAC4, mac[4]); + mac_reg[1] |= FIELD_PREP(AN8855_ATA2_MAC5, mac[5]); + + regmap_bulk_write(priv->regmap, AN8855_ATA1, mac_reg, + ARRAY_SIZE(mac_reg)); + + reg = AN8855_ATWD_IVL; + if (add) + reg |= AN8855_ATWD_VLD; + reg |= FIELD_PREP(AN8855_ATWD_VID, vid); + reg |= FIELD_PREP(AN8855_ATWD_FID, AN8855_FID_BRIDGED); + regmap_write(priv->regmap, AN8855_ATWD, reg); + regmap_write(priv->regmap, AN8855_ATWD2, + FIELD_PREP(AN8855_ATWD2_PORT, port_mask)); +} + +static void an8855_fdb_read(struct an8855_priv *priv, struct an8855_fdb *fdb) +{ + u32 reg[4]; + + regmap_bulk_read(priv->regmap, AN8855_ATRD0, reg, + ARRAY_SIZE(reg)); + + fdb->live = FIELD_GET(AN8855_ATRD0_LIVE, reg[0]); + fdb->type = FIELD_GET(AN8855_ATRD0_TYPE, reg[0]); + fdb->ivl = FIELD_GET(AN8855_ATRD0_IVL, reg[0]); + fdb->vid = FIELD_GET(AN8855_ATRD0_VID, reg[0]); + fdb->fid = FIELD_GET(AN8855_ATRD0_FID, reg[0]); + fdb->aging = FIELD_GET(AN8855_ATRD1_AGING, reg[1]); + fdb->port_mask = FIELD_GET(AN8855_ATRD3_PORTMASK, reg[3]); + fdb->mac[0] = FIELD_GET(AN8855_ATRD2_MAC0, reg[2]); + fdb->mac[1] = FIELD_GET(AN8855_ATRD2_MAC1, reg[2]); + fdb->mac[2] = FIELD_GET(AN8855_ATRD2_MAC2, reg[2]); + fdb->mac[3] = FIELD_GET(AN8855_ATRD2_MAC3, reg[2]); + fdb->mac[4] = FIELD_GET(AN8855_ATRD1_MAC4, reg[1]); + fdb->mac[5] = FIELD_GET(AN8855_ATRD1_MAC5, reg[1]); + fdb->noarp = !!FIELD_GET(AN8855_ATRD0_ARP, reg[0]); +} + +static int an8855_fdb_cmd(struct an8855_priv *priv, u32 cmd, + u32 *rsp) __must_hold(&priv->reg_mutex) +{ + u32 val; + int ret; + + /* Set the command operating upon the MAC address entries */ + val = AN8855_ATC_BUSY | cmd; + ret = regmap_write(priv->regmap, AN8855_ATC, val); + if (ret) + return ret; + + ret = regmap_read_poll_timeout(priv->regmap, AN8855_ATC, val, + !(val & AN8855_ATC_BUSY), 20, 200000); + if (ret) + return ret; + + if (rsp) + *rsp = val; + + return 0; +} + +static void +an8855_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) +{ + struct dsa_port *dp = dsa_to_port(ds, port); + struct an8855_priv *priv = ds->priv; + bool learning = false; + u32 stp_state; + + switch (state) { + case BR_STATE_DISABLED: + stp_state = AN8855_STP_DISABLED; + break; + case BR_STATE_BLOCKING: + stp_state = AN8855_STP_BLOCKING; + break; + case BR_STATE_LISTENING: + stp_state = AN8855_STP_LISTENING; + break; + case BR_STATE_LEARNING: + stp_state = AN8855_STP_LEARNING; + learning = dp->learning; + break; + case BR_STATE_FORWARDING: + learning = dp->learning; + fallthrough; + default: + stp_state = AN8855_STP_FORWARDING; + break; + } + + regmap_update_bits(priv->regmap, AN8855_SSP_P(port), + AN8855_FID_PST_MASK(AN8855_FID_BRIDGED), + AN8855_FID_PST_VAL(AN8855_FID_BRIDGED, stp_state)); + + regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DIS, + learning ? 0 : AN8855_SA_DIS); +} + +static void an8855_port_fast_age(struct dsa_switch *ds, int port) +{ + struct an8855_priv *priv = ds->priv; + int ret; + + /* Set to clean Dynamic entry */ + ret = regmap_write(priv->regmap, AN8855_ATA2, AN8855_ATA2_TYPE); + if (ret) + return; + + /* Set Port */ + ret = regmap_write(priv->regmap, AN8855_ATWD2, + FIELD_PREP(AN8855_ATWD2_PORT, BIT(port))); + if (ret) + return; + + /* Flush Dynamic entry at port */ + an8855_fdb_cmd(priv, AN8855_ATC_MAT(AND8855_FDB_MAT_MAC_TYPE_PORT) | + AN8855_FDB_FLUSH, NULL); +} + +static int an8855_update_port_member(struct dsa_switch *ds, int port, + const struct net_device *bridge_dev, + bool join) +{ + struct an8855_priv *priv = ds->priv; + bool isolated, other_isolated; + struct dsa_port *dp; + u32 port_mask = 0; + int ret; + + isolated = !!(priv->port_isolated_map & BIT(port)); + + dsa_switch_for_each_user_port(dp, ds) { + if (dp->index == port) + continue; + + if (!dsa_port_offloads_bridge_dev(dp, bridge_dev)) + continue; + + other_isolated = !!(priv->port_isolated_map & BIT(dp->index)); + port_mask |= BIT(dp->index); + /* Add/remove this port to the portvlan mask of the other + * ports in the bridge + */ + if (join && !(isolated && other_isolated)) + ret = regmap_set_bits(priv->regmap, + AN8855_PORTMATRIX_P(dp->index), + FIELD_PREP(AN8855_USER_PORTMATRIX, + BIT(port))); + else + ret = regmap_clear_bits(priv->regmap, + AN8855_PORTMATRIX_P(dp->index), + FIELD_PREP(AN8855_USER_PORTMATRIX, + BIT(port))); + if (ret) + return ret; + } + + /* Add/remove all other ports to this port's portvlan mask */ + return regmap_update_bits(priv->regmap, AN8855_PORTMATRIX_P(port), + AN8855_USER_PORTMATRIX, + join ? port_mask : ~port_mask); +} + +static int an8855_port_pre_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | + BR_BCAST_FLOOD | BR_ISOLATED)) + return -EINVAL; + + return 0; +} + +static int an8855_port_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + struct an8855_priv *priv = ds->priv; + int ret; + + if (flags.mask & BR_LEARNING) { + ret = regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DIS, + flags.val & BR_LEARNING ? 0 : AN8855_SA_DIS); + if (ret) + return ret; + } + + if (flags.mask & BR_FLOOD) { + ret = regmap_update_bits(priv->regmap, AN8855_UNUF, BIT(port), + flags.val & BR_FLOOD ? BIT(port) : 0); + if (ret) + return ret; + } + + if (flags.mask & BR_MCAST_FLOOD) { + ret = regmap_update_bits(priv->regmap, AN8855_UNMF, BIT(port), + flags.val & BR_MCAST_FLOOD ? BIT(port) : 0); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_UNIPMF, BIT(port), + flags.val & BR_MCAST_FLOOD ? BIT(port) : 0); + if (ret) + return ret; + } + + if (flags.mask & BR_BCAST_FLOOD) { + ret = regmap_update_bits(priv->regmap, AN8855_BCF, BIT(port), + flags.val & BR_BCAST_FLOOD ? BIT(port) : 0); + if (ret) + return ret; + } + + if (flags.mask & BR_ISOLATED) { + struct dsa_port *dp = dsa_to_port(ds, port); + struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp); + + if (flags.val & BR_ISOLATED) + priv->port_isolated_map |= BIT(port); + else + priv->port_isolated_map &= ~BIT(port); + + ret = an8855_update_port_member(ds, port, bridge_dev, true); + if (ret) + return ret; + } + + return 0; +} + +static int an8855_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) +{ + struct an8855_priv *priv = ds->priv; + u32 age_count, age_unit, val; + + /* Convert msec in AN8855_L2_AGING_MS_CONSTANT counter */ + val = msecs / AN8855_L2_AGING_MS_CONSTANT; + /* Derive the count unit */ + age_unit = val / FIELD_MAX(AN8855_AGE_UNIT); + /* Get the count in unit, age_unit is always incremented by 1 internally */ + age_count = val / (age_unit + 1); + + return regmap_update_bits(priv->regmap, AN8855_AAC, + AN8855_AGE_CNT | AN8855_AGE_UNIT, + FIELD_PREP(AN8855_AGE_CNT, age_count) | + FIELD_PREP(AN8855_AGE_UNIT, age_unit)); +} + +static int an8855_port_bridge_join(struct dsa_switch *ds, int port, + struct dsa_bridge bridge, + bool *tx_fwd_offload, + struct netlink_ext_ack *extack) +{ + struct an8855_priv *priv = ds->priv; + int ret; + + ret = an8855_update_port_member(ds, port, bridge.dev, true); + if (ret) + return ret; + + /* Set to fallback mode for independent VLAN learning if in a bridge */ + return regmap_update_bits(priv->regmap, AN8855_PCR_P(port), + AN8855_PORT_VLAN, + FIELD_PREP(AN8855_PORT_VLAN, + AN8855_PORT_FALLBACK_MODE)); +} + +static void an8855_port_bridge_leave(struct dsa_switch *ds, int port, + struct dsa_bridge bridge) +{ + struct an8855_priv *priv = ds->priv; + + an8855_update_port_member(ds, port, bridge.dev, false); + + /* When a port is removed from the bridge, the port would be set up + * back to the default as is at initial boot which is a VLAN-unaware + * port. + */ + regmap_update_bits(priv->regmap, AN8855_PCR_P(port), + AN8855_PORT_VLAN, + FIELD_PREP(AN8855_PORT_VLAN, + AN8855_PORT_MATRIX_MODE)); +} + +static int an8855_port_fdb_add(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db) +{ + struct an8855_priv *priv = ds->priv; + u8 port_mask = BIT(port); + int ret; + + /* Set the vid to the port vlan id if no vid is set */ + if (!vid) + vid = AN8855_PORT_VID_DEFAULT; + + mutex_lock(&priv->reg_mutex); + an8855_fdb_write(priv, vid, port_mask, addr, true); + ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL); + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +static int an8855_port_fdb_del(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db) +{ + struct an8855_priv *priv = ds->priv; + u8 port_mask = BIT(port); + int ret; + + /* Set the vid to the port vlan id if no vid is set */ + if (!vid) + vid = AN8855_PORT_VID_DEFAULT; + + mutex_lock(&priv->reg_mutex); + an8855_fdb_write(priv, vid, port_mask, addr, false); + ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL); + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +static int an8855_port_fdb_dump(struct dsa_switch *ds, int port, + dsa_fdb_dump_cb_t *cb, void *data) +{ + struct an8855_priv *priv = ds->priv; + int banks, count = 0; + u32 rsp; + int ret; + int i; + + mutex_lock(&priv->reg_mutex); + + /* Load search port */ + ret = regmap_write(priv->regmap, AN8855_ATWD2, + FIELD_PREP(AN8855_ATWD2_PORT, BIT(port))); + if (ret) + goto exit; + ret = an8855_fdb_cmd(priv, AN8855_ATC_MAT(AND8855_FDB_MAT_MAC_PORT) | + AN8855_FDB_START, &rsp); + if (ret < 0) + goto exit; + + do { + /* From response get the number of banks to read, exit if 0 */ + banks = FIELD_GET(AN8855_ATC_HIT, rsp); + if (!banks) + break; + + /* Each banks have 4 entry */ + for (i = 0; i < 4; i++) { + struct an8855_fdb _fdb = { }; + + count++; + + /* Check if bank is present */ + if (!(banks & BIT(i))) + continue; + + /* Select bank entry index */ + ret = regmap_write(priv->regmap, AN8855_ATRDS, + FIELD_PREP(AN8855_ATRD_SEL, i)); + if (ret) + break; + /* wait 1ms for the bank entry to be filled */ + usleep_range(1000, 1500); + an8855_fdb_read(priv, &_fdb); + + if (!_fdb.live) + continue; + ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, data); + if (ret < 0) + break; + } + + /* Stop if reached max FDB number */ + if (count >= AN8855_NUM_FDB_RECORDS) + break; + + /* Read next bank */ + ret = an8855_fdb_cmd(priv, AN8855_ATC_MAT(AND8855_FDB_MAT_MAC_PORT) | + AN8855_FDB_NEXT, &rsp); + if (ret < 0) + break; + } while (true); + +exit: + mutex_unlock(&priv->reg_mutex); + return ret; +} + +static int an8855_vlan_cmd(struct an8855_priv *priv, enum an8855_vlan_cmd cmd, + u16 vid) __must_hold(&priv->reg_mutex) +{ + u32 val; + int ret; + + val = AN8855_VTCR_BUSY | FIELD_PREP(AN8855_VTCR_FUNC, cmd) | + FIELD_PREP(AN8855_VTCR_VID, vid); + ret = regmap_write(priv->regmap, AN8855_VTCR, val); + if (ret) + return ret; + + return regmap_read_poll_timeout(priv->regmap, AN8855_VTCR, val, + !(val & AN8855_VTCR_BUSY), 20, 200000); +} + +static int an8855_vlan_add(struct an8855_priv *priv, u8 port, u16 vid, + bool untagged) __must_hold(&priv->reg_mutex) +{ + u32 port_mask; + u32 val; + int ret; + + /* Fetch entry */ + ret = an8855_vlan_cmd(priv, AN8855_VTCR_RD_VID, vid); + if (ret) + return ret; + + ret = regmap_read(priv->regmap, AN8855_VARD0, &val); + if (ret) + return ret; + port_mask = FIELD_GET(AN8855_VA0_PORT, val) | BIT(port); + + /* Validate the entry with independent learning, create egress tag per + * VLAN and joining the port as one of the port members. + */ + val = (val & AN8855_VA0_ETAG) | AN8855_VA0_IVL_MAC | + AN8855_VA0_VTAG_EN | AN8855_VA0_VLAN_VALID | + FIELD_PREP(AN8855_VA0_PORT, port_mask) | + FIELD_PREP(AN8855_VA0_FID, AN8855_FID_BRIDGED); + ret = regmap_write(priv->regmap, AN8855_VAWD0, val); + if (ret) + return ret; + ret = regmap_write(priv->regmap, AN8855_VAWD1, 0); + if (ret) + return ret; + + /* CPU port is always taken as a tagged port for serving more than one + * VLANs across and also being applied with egress type stack mode for + * that VLAN tags would be appended after hardware special tag used as + * DSA tag. + */ + if (port == AN8855_CPU_PORT) + val = AN8855_VLAN_EGRESS_STACK; + /* Decide whether adding tag or not for those outgoing packets from the + * port inside the VLAN. + */ + else + val = untagged ? AN8855_VLAN_EGRESS_UNTAG : AN8855_VLAN_EGRESS_TAG; + ret = regmap_update_bits(priv->regmap, AN8855_VAWD0, + AN8855_VA0_ETAG_PORT_MASK(port), + AN8855_VA0_ETAG_PORT_VAL(port, val)); + if (ret) + return ret; + + /* Flush result to hardware */ + return an8855_vlan_cmd(priv, AN8855_VTCR_WR_VID, vid); +} + +static int an8855_vlan_del(struct an8855_priv *priv, u8 port, + u16 vid) __must_hold(&priv->reg_mutex) +{ + u32 port_mask; + u32 val; + int ret; + + /* Fetch entry */ + ret = an8855_vlan_cmd(priv, AN8855_VTCR_RD_VID, vid); + if (ret) + return ret; + + ret = regmap_read(priv->regmap, AN8855_VARD0, &val); + if (ret) + return ret; + port_mask = FIELD_GET(AN8855_VA0_PORT, val) & ~BIT(port); + + if (!(val & AN8855_VA0_VLAN_VALID)) { + dev_err(priv->dev, "Cannot be deleted due to invalid entry\n"); + return -EINVAL; + } + + if (port_mask) { + val = (val & AN8855_VA0_ETAG) | AN8855_VA0_IVL_MAC | + AN8855_VA0_VTAG_EN | AN8855_VA0_VLAN_VALID | + FIELD_PREP(AN8855_VA0_PORT, port_mask); + ret = regmap_write(priv->regmap, AN8855_VAWD0, val); + if (ret) + return ret; + } else { + ret = regmap_write(priv->regmap, AN8855_VAWD0, 0); + if (ret) + return ret; + } + ret = regmap_write(priv->regmap, AN8855_VAWD1, 0); + if (ret) + return ret; + + /* Flush result to hardware */ + return an8855_vlan_cmd(priv, AN8855_VTCR_WR_VID, vid); +} + +static int an8855_port_set_vlan_mode(struct an8855_priv *priv, int port, + enum an8855_port_mode port_mode, + enum an8855_vlan_port_eg_tag eg_tag, + enum an8855_vlan_port_attr vlan_attr, + enum an8855_vlan_port_acc_frm acc_frm) +{ + int ret; + + ret = regmap_update_bits(priv->regmap, AN8855_PCR_P(port), + AN8855_PORT_VLAN, + FIELD_PREP(AN8855_PORT_VLAN, port_mode)); + if (ret) + return ret; + + return regmap_update_bits(priv->regmap, AN8855_PVC_P(port), + AN8855_PVC_EG_TAG | AN8855_VLAN_ATTR | AN8855_ACC_FRM, + FIELD_PREP(AN8855_PVC_EG_TAG, eg_tag) | + FIELD_PREP(AN8855_VLAN_ATTR, vlan_attr) | + FIELD_PREP(AN8855_ACC_FRM, acc_frm)); +} + +static int an8855_port_set_pid(struct an8855_priv *priv, int port, + u16 pid) +{ + int ret; + + ret = regmap_update_bits(priv->regmap, AN8855_PPBV1_P(port), + AN8855_PPBV_G0_PORT_VID, + FIELD_PREP(AN8855_PPBV_G0_PORT_VID, pid)); + if (ret) + return ret; + + return regmap_update_bits(priv->regmap, AN8855_PVID_P(port), + AN8855_G0_PORT_VID, + FIELD_PREP(AN8855_G0_PORT_VID, pid)); +} + +static int an8855_port_vlan_filtering(struct dsa_switch *ds, int port, + bool vlan_filtering, + struct netlink_ext_ack *extack) +{ + struct an8855_priv *priv = ds->priv; + u32 val; + int ret; + + /* The port is being kept as VLAN-unaware port when bridge is + * set up with vlan_filtering not being set, Otherwise, the + * port and the corresponding CPU port is required the setup + * for becoming a VLAN-aware port. + */ + if (vlan_filtering) { + u32 acc_frm; + /* CPU port is set to fallback mode to let untagged + * frames pass through. + */ + ret = an8855_port_set_vlan_mode(priv, AN8855_CPU_PORT, + AN8855_PORT_FALLBACK_MODE, + AN8855_VLAN_EG_CONSISTENT, + AN8855_VLAN_USER, + AN8855_VLAN_ACC_ALL); + if (ret) + return ret; + + ret = regmap_read(priv->regmap, AN8855_PVID_P(port), &val); + if (ret) + return ret; + + /* Only accept tagged frames if PVID is not set */ + if (FIELD_GET(AN8855_G0_PORT_VID, val) != AN8855_PORT_VID_DEFAULT) + acc_frm = AN8855_VLAN_ACC_TAGGED; + else + acc_frm = AN8855_VLAN_ACC_ALL; + + /* Trapped into security mode allows packet forwarding through VLAN + * table lookup. + * Set the port as a user port which is to be able to recognize VID + * from incoming packets before fetching entry within the VLAN table. + */ + ret = an8855_port_set_vlan_mode(priv, port, + AN8855_PORT_SECURITY_MODE, + AN8855_VLAN_EG_DISABLED, + AN8855_VLAN_USER, + acc_frm); + if (ret) + return ret; + } else { + bool disable_cpu_vlan = true; + struct dsa_port *dp; + u32 port_mode; + + /* This is called after .port_bridge_leave when leaving a VLAN-aware + * bridge. Don't set standalone ports to fallback mode. + */ + if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) + port_mode = AN8855_PORT_FALLBACK_MODE; + else + port_mode = AN8855_PORT_MATRIX_MODE; + + /* When a port is removed from the bridge, the port would be set up + * back to the default as is at initial boot which is a VLAN-unaware + * port. + */ + ret = an8855_port_set_vlan_mode(priv, port, port_mode, + AN8855_VLAN_EG_CONSISTENT, + AN8855_VLAN_TRANSPARENT, + AN8855_VLAN_ACC_ALL); + if (ret) + return ret; + + /* Restore default PVID */ + ret = an8855_port_set_pid(priv, port, AN8855_PORT_VID_DEFAULT); + if (ret) + return ret; + + dsa_switch_for_each_user_port(dp, ds) { + if (dsa_port_is_vlan_filtering(dp)) { + disable_cpu_vlan = false; + break; + } + } + + if (disable_cpu_vlan) { + ret = an8855_port_set_vlan_mode(priv, AN8855_CPU_PORT, + AN8855_PORT_MATRIX_MODE, + AN8855_VLAN_EG_CONSISTENT, + AN8855_VLAN_USER, + AN8855_VLAN_ACC_ALL); + if (ret) + return ret; + } + } + + return 0; +} + +static int an8855_port_vlan_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan, + struct netlink_ext_ack *extack) +{ + bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; + bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; + struct an8855_priv *priv = ds->priv; + u32 val; + int ret; + + mutex_lock(&priv->reg_mutex); + ret = an8855_vlan_add(priv, port, vlan->vid, untagged); + mutex_unlock(&priv->reg_mutex); + if (ret) + return ret; + + if (pvid) { + /* Accept all frames if PVID is set */ + regmap_update_bits(priv->regmap, AN8855_PVC_P(port), AN8855_ACC_FRM, + FIELD_PREP(AN8855_ACC_FRM, AN8855_VLAN_ACC_ALL)); + + /* Only configure PVID if VLAN filtering is enabled */ + if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) { + ret = an8855_port_set_pid(priv, port, vlan->vid); + if (ret) + return ret; + } + } else if (vlan->vid) { + ret = regmap_read(priv->regmap, AN8855_PVID_P(port), &val); + if (ret) + return ret; + + if (FIELD_GET(AN8855_G0_PORT_VID, val) != vlan->vid) + return 0; + + /* This VLAN is overwritten without PVID, so unset it */ + if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) { + ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(port), + AN8855_ACC_FRM, + FIELD_PREP(AN8855_ACC_FRM, + AN8855_VLAN_ACC_TAGGED)); + if (ret) + return ret; + } + + ret = an8855_port_set_pid(priv, port, AN8855_PORT_VID_DEFAULT); + if (ret) + return ret; + } + + return 0; +} + +static int an8855_port_vlan_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct an8855_priv *priv = ds->priv; + u32 val; + int ret; + + mutex_lock(&priv->reg_mutex); + ret = an8855_vlan_del(priv, port, vlan->vid); + mutex_unlock(&priv->reg_mutex); + if (ret) + return ret; + + ret = regmap_read(priv->regmap, AN8855_PVID_P(port), &val); + if (ret) + return ret; + + /* PVID is being restored to the default whenever the PVID port + * is being removed from the VLAN. + */ + if (FIELD_GET(AN8855_G0_PORT_VID, val) == vlan->vid) { + /* Only accept tagged frames if the port is VLAN-aware */ + if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) { + ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(port), + AN8855_ACC_FRM, + FIELD_PREP(AN8855_ACC_FRM, + AN8855_VLAN_ACC_TAGGED)); + if (ret) + return ret; + } + + ret = an8855_port_set_pid(priv, port, AN8855_PORT_VID_DEFAULT); + if (ret) + return ret; + } + + return 0; +} + +static int +an8855_port_mdb_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db) +{ + struct an8855_priv *priv = ds->priv; + const u8 *addr = mdb->addr; + u16 vid = mdb->vid; + u8 port_mask = 0; + u32 val; + int ret; + + /* Set the vid to the port vlan id if no vid is set */ + if (!vid) + vid = AN8855_PORT_VID_DEFAULT; + + mutex_lock(&priv->reg_mutex); + + an8855_fdb_write(priv, vid, 0, addr, false); + if (!an8855_fdb_cmd(priv, AN8855_FDB_READ, NULL)) { + ret = regmap_read(priv->regmap, AN8855_ATRD3, &val); + if (ret) + goto exit; + + port_mask = FIELD_GET(AN8855_ATRD3_PORTMASK, val); + } + + port_mask |= BIT(port); + an8855_fdb_write(priv, vid, port_mask, addr, true); + ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL); + +exit: + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +static int +an8855_port_mdb_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db) +{ + struct an8855_priv *priv = ds->priv; + const u8 *addr = mdb->addr; + u16 vid = mdb->vid; + u8 port_mask = 0; + u32 val; + int ret; + + /* Set the vid to the port vlan id if no vid is set */ + if (!vid) + vid = AN8855_PORT_VID_DEFAULT; + + mutex_lock(&priv->reg_mutex); + + an8855_fdb_write(priv, vid, 0, addr, 0); + if (!an8855_fdb_cmd(priv, AN8855_FDB_READ, NULL)) { + ret = regmap_read(priv->regmap, AN8855_ATRD3, &val); + if (ret) + goto exit; + + port_mask = FIELD_GET(AN8855_ATRD3_PORTMASK, val); + } + + port_mask &= ~BIT(port); + an8855_fdb_write(priv, vid, port_mask, addr, port_mask ? true : false); + ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL); + +exit: + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +static int +an8855_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) +{ + struct an8855_priv *priv = ds->priv; + int length; + u32 val; + + /* When a new MTU is set, DSA always set the CPU port's MTU to the + * largest MTU of the slave ports. Because the switch only has a global + * RX length register, only allowing CPU port here is enough. + */ + if (!dsa_is_cpu_port(ds, port)) + return 0; + + /* RX length also includes Ethernet header, MTK tag, and FCS length */ + length = new_mtu + ETH_HLEN + MTK_TAG_LEN + ETH_FCS_LEN; + if (length <= 1522) + val = AN8855_MAX_RX_PKT_1518_1522; + else if (length <= 1536) + val = AN8855_MAX_RX_PKT_1536; + else if (length <= 1552) + val = AN8855_MAX_RX_PKT_1552; + else if (length <= 3072) + val = AN8855_MAX_RX_JUMBO_3K; + else if (length <= 4096) + val = AN8855_MAX_RX_JUMBO_4K; + else if (length <= 5120) + val = AN8855_MAX_RX_JUMBO_5K; + else if (length <= 6144) + val = AN8855_MAX_RX_JUMBO_6K; + else if (length <= 7168) + val = AN8855_MAX_RX_JUMBO_7K; + else if (length <= 8192) + val = AN8855_MAX_RX_JUMBO_8K; + else if (length <= 9216) + val = AN8855_MAX_RX_JUMBO_9K; + else if (length <= 12288) + val = AN8855_MAX_RX_JUMBO_12K; + else if (length <= 15360) + val = AN8855_MAX_RX_JUMBO_15K; + else + val = AN8855_MAX_RX_JUMBO_16K; + + /* Enable JUMBO packet */ + if (length > 1552) + val |= AN8855_MAX_RX_PKT_JUMBO; + + return regmap_update_bits(priv->regmap, AN8855_GMACCR, + AN8855_MAX_RX_JUMBO | AN8855_MAX_RX_PKT_LEN, + val); +} + +static int +an8855_port_max_mtu(struct dsa_switch *ds, int port) +{ + return AN8855_MAX_MTU; +} + +static void +an8855_get_strings(struct dsa_switch *ds, int port, u32 stringset, + uint8_t *data) +{ + int i; + + if (stringset != ETH_SS_STATS) + return; + + for (i = 0; i < ARRAY_SIZE(an8855_mib); i++) + ethtool_puts(&data, an8855_mib[i].name); +} + +static void +an8855_read_port_stats(struct an8855_priv *priv, int port, u32 offset, u8 size, + uint64_t *data) +{ + u32 val, reg = AN8855_PORT_MIB_COUNTER(port) + offset; + + regmap_read(priv->regmap, reg, &val); + *data = val; + + if (size == 2) { + regmap_read(priv->regmap, reg + 4, &val); + *data |= (u64)val << 32; + } +} + +static void +an8855_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) +{ + struct an8855_priv *priv = ds->priv; + const struct an8855_mib_desc *mib; + int i; + + for (i = 0; i < ARRAY_SIZE(an8855_mib); i++) { + mib = &an8855_mib[i]; + + an8855_read_port_stats(priv, port, mib->offset, mib->size, + data + i); + } +} + +static int +an8855_get_sset_count(struct dsa_switch *ds, int port, int sset) +{ + if (sset != ETH_SS_STATS) + return 0; + + return ARRAY_SIZE(an8855_mib); +} + +static void +an8855_get_eth_mac_stats(struct dsa_switch *ds, int port, + struct ethtool_eth_mac_stats *mac_stats) +{ + struct an8855_priv *priv = ds->priv; + + /* MIB counter doesn't provide a FramesTransmittedOK but instead + * provide stats for Unicast, Broadcast and Multicast frames separately. + * To simulate a global frame counter, read Unicast and addition Multicast + * and Broadcast later + */ + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_UNICAST, 1, + &mac_stats->FramesTransmittedOK); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_SINGLE_COLLISION, 1, + &mac_stats->SingleCollisionFrames); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_MULTIPLE_COLLISION, 1, + &mac_stats->MultipleCollisionFrames); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_UNICAST, 1, + &mac_stats->FramesReceivedOK); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_BYTES, 2, + &mac_stats->OctetsTransmittedOK); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_ALIGN_ERR, 1, + &mac_stats->AlignmentErrors); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_DEFERRED, 1, + &mac_stats->FramesWithDeferredXmissions); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_LATE_COLLISION, 1, + &mac_stats->LateCollisions); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION, 1, + &mac_stats->FramesAbortedDueToXSColls); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_BYTES, 2, + &mac_stats->OctetsReceivedOK); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_MULTICAST, 1, + &mac_stats->MulticastFramesXmittedOK); + mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK; + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_BROADCAST, 1, + &mac_stats->BroadcastFramesXmittedOK); + mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK; + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_MULTICAST, 1, + &mac_stats->MulticastFramesReceivedOK); + mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK; + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_BROADCAST, 1, + &mac_stats->BroadcastFramesReceivedOK); + mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK; +} + +static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] = { + { 0, 64 }, + { 65, 127 }, + { 128, 255 }, + { 256, 511 }, + { 512, 1023 }, + { 1024, 1518 }, + { 1519, AN8855_MAX_MTU }, + {} +}; + +static void an8855_get_rmon_stats(struct dsa_switch *ds, int port, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges) +{ + struct an8855_priv *priv = ds->priv; + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_UNDER_SIZE_ERR, 1, + &rmon_stats->undersize_pkts); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_OVER_SZ_ERR, 1, + &rmon_stats->oversize_pkts); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_FRAG_ERR, 1, + &rmon_stats->fragments); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_JABBER_ERR, 1, + &rmon_stats->jabbers); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_64, 1, + &rmon_stats->hist[0]); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127, 1, + &rmon_stats->hist[1]); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255, 1, + &rmon_stats->hist[2]); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511, 1, + &rmon_stats->hist[3]); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1, + &rmon_stats->hist[4]); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518, 1, + &rmon_stats->hist[5]); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX, 1, + &rmon_stats->hist[6]); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_64, 1, + &rmon_stats->hist_tx[0]); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127, 1, + &rmon_stats->hist_tx[1]); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255, 1, + &rmon_stats->hist_tx[2]); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511, 1, + &rmon_stats->hist_tx[3]); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1, + &rmon_stats->hist_tx[4]); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518, 1, + &rmon_stats->hist_tx[5]); + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX, 1, + &rmon_stats->hist_tx[6]); + + *ranges = an8855_rmon_ranges; +} + +static void an8855_get_eth_ctrl_stats(struct dsa_switch *ds, int port, + struct ethtool_eth_ctrl_stats *ctrl_stats) +{ + struct an8855_priv *priv = ds->priv; + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PAUSE, 1, + &ctrl_stats->MACControlFramesTransmitted); + + an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PAUSE, 1, + &ctrl_stats->MACControlFramesReceived); +} + +static int an8855_port_mirror_add(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress, + struct netlink_ext_ack *extack) +{ + struct an8855_priv *priv = ds->priv; + int monitor_port; + u32 val; + int ret; + + /* Check for existent entry */ + if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) + return -EEXIST; + + ret = regmap_read(priv->regmap, AN8855_MIR, &val); + if (ret) + return ret; + + /* AN8855 supports 4 monitor port, but only use first group */ + monitor_port = FIELD_GET(AN8855_MIRROR_PORT, val); + if (val & AN8855_MIRROR_EN && monitor_port != mirror->to_local_port) + return -EEXIST; + + val = AN8855_MIRROR_EN; + val |= FIELD_PREP(AN8855_MIRROR_PORT, mirror->to_local_port); + ret = regmap_update_bits(priv->regmap, AN8855_MIR, + AN8855_MIRROR_EN | AN8855_MIRROR_PORT, + val); + if (ret) + return ret; + + ret = regmap_set_bits(priv->regmap, AN8855_PCR_P(port), + ingress ? AN8855_PORT_RX_MIR : AN8855_PORT_TX_MIR); + if (ret) + return ret; + + if (ingress) + priv->mirror_rx |= BIT(port); + else + priv->mirror_tx |= BIT(port); + + return 0; +} + +static void an8855_port_mirror_del(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror) +{ + struct an8855_priv *priv = ds->priv; + + if (mirror->ingress) + priv->mirror_rx &= ~BIT(port); + else + priv->mirror_tx &= ~BIT(port); + + regmap_clear_bits(priv->regmap, AN8855_PCR_P(port), + mirror->ingress ? AN8855_PORT_RX_MIR : + AN8855_PORT_TX_MIR); + + if (!priv->mirror_rx && !priv->mirror_tx) + regmap_clear_bits(priv->regmap, AN8855_MIR, AN8855_MIRROR_EN); +} + +static int an8855_port_set_status(struct an8855_priv *priv, int port, + bool enable) +{ + if (enable) + return regmap_set_bits(priv->regmap, AN8855_PMCR_P(port), + AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN); + else + return regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port), + AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN); +} + +static int an8855_port_enable(struct dsa_switch *ds, int port, + struct phy_device *phy) +{ + return an8855_port_set_status(ds->priv, port, true); +} + +static void an8855_port_disable(struct dsa_switch *ds, int port) +{ + an8855_port_set_status(ds->priv, port, false); +} + +static u32 en8855_get_phy_flags(struct dsa_switch *ds, int port) +{ + struct an8855_priv *priv = ds->priv; + + /* PHY doesn't need calibration */ + if (!priv->phy_require_calib) + return 0; + + /* Use AN8855_PHY_FLAGS_EN_CALIBRATION to signal + * calibration needed. + */ + return AN8855_PHY_FLAGS_EN_CALIBRATION; +} + +static enum dsa_tag_protocol +an8855_get_tag_protocol(struct dsa_switch *ds, int port, + enum dsa_tag_protocol mp) +{ + return DSA_TAG_PROTO_MTK; +} + +/* Similar to MT7530 also trap link local frame and special frame to CPU */ +static int an8855_trap_special_frames(struct an8855_priv *priv) +{ + int ret; + + /* Trap BPDUs to the CPU port(s) and egress them + * VLAN-untagged. + */ + ret = regmap_update_bits(priv->regmap, AN8855_BPC, + AN8855_BPDU_BPDU_FR | AN8855_BPDU_EG_TAG | + AN8855_BPDU_PORT_FW, + AN8855_BPDU_BPDU_FR | + FIELD_PREP(AN8855_BPDU_EG_TAG, AN8855_VLAN_EG_UNTAGGED) | + FIELD_PREP(AN8855_BPDU_PORT_FW, AN8855_BPDU_CPU_ONLY)); + if (ret) + return ret; + + /* Trap 802.1X PAE frames to the CPU port(s) and egress them + * VLAN-untagged. + */ + ret = regmap_update_bits(priv->regmap, AN8855_PAC, + AN8855_PAE_BPDU_FR | AN8855_PAE_EG_TAG | + AN8855_PAE_PORT_FW, + AN8855_PAE_BPDU_FR | + FIELD_PREP(AN8855_PAE_EG_TAG, AN8855_VLAN_EG_UNTAGGED) | + FIELD_PREP(AN8855_PAE_PORT_FW, AN8855_BPDU_CPU_ONLY)); + if (ret) + return ret; + + /* Trap frames with :01 MAC DAs to the CPU port(s) and egress + * them VLAN-untagged. + */ + ret = regmap_update_bits(priv->regmap, AN8855_RGAC1, + AN8855_R01_BPDU_FR | AN8855_R01_EG_TAG | + AN8855_R01_PORT_FW, + AN8855_R01_BPDU_FR | + FIELD_PREP(AN8855_R01_EG_TAG, AN8855_VLAN_EG_UNTAGGED) | + FIELD_PREP(AN8855_R01_PORT_FW, AN8855_BPDU_CPU_ONLY)); + if (ret) + return ret; + + /* Trap frames with :02 MAC DAs to the CPU port(s) and egress + * them VLAN-untagged. + */ + ret = regmap_update_bits(priv->regmap, AN8855_RGAC1, + AN8855_R02_BPDU_FR | AN8855_R02_EG_TAG | + AN8855_R02_PORT_FW, + AN8855_R02_BPDU_FR | + FIELD_PREP(AN8855_R02_EG_TAG, AN8855_VLAN_EG_UNTAGGED) | + FIELD_PREP(AN8855_R02_PORT_FW, AN8855_BPDU_CPU_ONLY)); + if (ret) + return ret; + + /* Trap frames with :03 MAC DAs to the CPU port(s) and egress + * them VLAN-untagged. + */ + ret = regmap_update_bits(priv->regmap, AN8855_RGAC1, + AN8855_R03_BPDU_FR | AN8855_R03_EG_TAG | + AN8855_R03_PORT_FW, + AN8855_R03_BPDU_FR | + FIELD_PREP(AN8855_R03_EG_TAG, AN8855_VLAN_EG_UNTAGGED) | + FIELD_PREP(AN8855_R03_PORT_FW, AN8855_BPDU_CPU_ONLY)); + if (ret) + return ret; + + /* Trap frames with :0E MAC DAs to the CPU port(s) and egress + * them VLAN-untagged. + */ + return regmap_update_bits(priv->regmap, AN8855_RGAC1, + AN8855_R0E_BPDU_FR | AN8855_R0E_EG_TAG | + AN8855_R0E_PORT_FW, + AN8855_R0E_BPDU_FR | + FIELD_PREP(AN8855_R0E_EG_TAG, AN8855_VLAN_EG_UNTAGGED) | + FIELD_PREP(AN8855_R0E_PORT_FW, AN8855_BPDU_CPU_ONLY)); +} + +static int +an8855_setup_pvid_vlan(struct an8855_priv *priv) +{ + u32 val; + int ret; + + /* Validate the entry with independent learning, keep the original + * ingress tag attribute. + */ + val = AN8855_VA0_IVL_MAC | AN8855_VA0_EG_CON | + FIELD_PREP(AN8855_VA0_FID, AN8855_FID_BRIDGED) | + AN8855_VA0_PORT | AN8855_VA0_VLAN_VALID; + ret = regmap_write(priv->regmap, AN8855_VAWD0, val); + if (ret) + return ret; + + return an8855_vlan_cmd(priv, AN8855_VTCR_WR_VID, + AN8855_PORT_VID_DEFAULT); +} + +static int an8855_setup(struct dsa_switch *ds) +{ + struct an8855_priv *priv = ds->priv; + struct dsa_port *dp; + int ret; + + /* Enable and reset MIB counters */ + ret = an8855_mib_init(priv); + if (ret) + return ret; + + dsa_switch_for_each_user_port(dp, ds) { + /* Disable MAC by default on all user ports */ + ret = an8855_port_set_status(priv, dp->index, false); + if (ret) + return ret; + + /* Individual user ports get connected to CPU port only */ + ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(dp->index), + FIELD_PREP(AN8855_PORTMATRIX, BIT(AN8855_CPU_PORT))); + if (ret) + return ret; + + /* Disable Broadcast Forward on user ports */ + ret = regmap_clear_bits(priv->regmap, AN8855_BCF, BIT(dp->index)); + if (ret) + return ret; + + /* Disable Unknown Unicast Forward on user ports */ + ret = regmap_clear_bits(priv->regmap, AN8855_UNUF, BIT(dp->index)); + if (ret) + return ret; + + /* Disable Unknown Multicast Forward on user ports */ + ret = regmap_clear_bits(priv->regmap, AN8855_UNMF, BIT(dp->index)); + if (ret) + return ret; + + ret = regmap_clear_bits(priv->regmap, AN8855_UNIPMF, BIT(dp->index)); + if (ret) + return ret; + + /* Set default PVID to on all user ports */ + ret = an8855_port_set_pid(priv, dp->index, AN8855_PORT_VID_DEFAULT); + if (ret) + return ret; + } + + /* Enable Airoha header mode on the cpu port */ + ret = regmap_write(priv->regmap, AN8855_PVC_P(AN8855_CPU_PORT), + AN8855_PORT_SPEC_REPLACE_MODE | AN8855_PORT_SPEC_TAG); + if (ret) + return ret; + + /* Unknown multicast frame forwarding to the cpu port */ + ret = regmap_write(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT)); + if (ret) + return ret; + + /* Set CPU port number */ + ret = regmap_update_bits(priv->regmap, AN8855_MFC, + AN8855_CPU_EN | AN8855_CPU_PORT_IDX, + AN8855_CPU_EN | + FIELD_PREP(AN8855_CPU_PORT_IDX, AN8855_CPU_PORT)); + if (ret) + return ret; + + /* CPU port gets connected to all user ports of + * the switch. + */ + ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(AN8855_CPU_PORT), + FIELD_PREP(AN8855_PORTMATRIX, dsa_user_ports(ds))); + if (ret) + return ret; + + /* CPU port is set to fallback mode to let untagged + * frames pass through. + */ + ret = regmap_update_bits(priv->regmap, AN8855_PCR_P(AN8855_CPU_PORT), + AN8855_PORT_VLAN, + FIELD_PREP(AN8855_PORT_VLAN, AN8855_PORT_FALLBACK_MODE)); + if (ret) + return ret; + + /* Enable Broadcast Forward on CPU port */ + ret = regmap_set_bits(priv->regmap, AN8855_BCF, BIT(AN8855_CPU_PORT)); + if (ret) + return ret; + + /* Enable Unknown Unicast Forward on CPU port */ + ret = regmap_set_bits(priv->regmap, AN8855_UNUF, BIT(AN8855_CPU_PORT)); + if (ret) + return ret; + + /* Enable Unknown Multicast Forward on CPU port */ + ret = regmap_set_bits(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT)); + if (ret) + return ret; + + ret = regmap_set_bits(priv->regmap, AN8855_UNIPMF, BIT(AN8855_CPU_PORT)); + if (ret) + return ret; + + /* Setup Trap special frame to CPU rules */ + ret = an8855_trap_special_frames(priv); + if (ret) + return ret; + + dsa_switch_for_each_port(dp, ds) { + /* Disable Learning on all ports. + * Learning on CPU is disabled for fdb isolation and handled by + * assisted_learning_on_cpu_port. + */ + ret = regmap_set_bits(priv->regmap, AN8855_PSC_P(dp->index), + AN8855_SA_DIS); + if (ret) + return ret; + + /* Enable consistent egress tag (for VLAN unware VLAN-passtrough) */ + ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(dp->index), + AN8855_PVC_EG_TAG, + FIELD_PREP(AN8855_PVC_EG_TAG, AN8855_VLAN_EG_CONSISTENT)); + if (ret) + return ret; + } + + /* Setup VLAN for Default PVID */ + ret = an8855_setup_pvid_vlan(priv); + if (ret) + return ret; + + ret = regmap_clear_bits(priv->regmap, AN8855_CKGCR, + AN8855_CKG_LNKDN_GLB_STOP | AN8855_CKG_LNKDN_PORT_STOP); + if (ret) + return ret; + + /* Release global PHY power down */ + ret = regmap_write(priv->regmap, AN8855_RG_GPHY_AFE_PWD, 0x0); + if (ret) + return ret; + + ds->configure_vlan_while_not_filtering = true; + + /* Flush the FDB table */ + ret = an8855_fdb_cmd(priv, AN8855_FDB_FLUSH, NULL); + if (ret < 0) + return ret; + + /* Set min a max ageing value supported */ + ds->ageing_time_min = AN8855_L2_AGING_MS_CONSTANT; + ds->ageing_time_max = FIELD_MAX(AN8855_AGE_CNT) * + FIELD_MAX(AN8855_AGE_UNIT) * + AN8855_L2_AGING_MS_CONSTANT; + + /* Enable assisted learning for fdb isolation */ + ds->assisted_learning_on_cpu_port = true; + + return 0; +} + +static struct phylink_pcs *an8855_phylink_mac_select_pcs(struct phylink_config *config, + phy_interface_t interface) +{ + struct dsa_port *dp = dsa_phylink_to_port(config); + struct an8855_priv *priv = dp->ds->priv; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_2500BASEX: + return &priv->pcs; + default: + return NULL; + } +} + +static void an8855_phylink_mac_config(struct phylink_config *config, + unsigned int mode, + const struct phylink_link_state *state) +{ + struct dsa_port *dp = dsa_phylink_to_port(config); + struct dsa_switch *ds = dp->ds; + struct an8855_priv *priv; + int port = dp->index; + + priv = ds->priv; + + /* Nothing to configure for internal ports */ + if (port != 5) + return; + + regmap_update_bits(priv->regmap, AN8855_PMCR_P(port), + AN8855_PMCR_IFG_XMIT | AN8855_PMCR_MAC_MODE | + AN8855_PMCR_BACKOFF_EN | AN8855_PMCR_BACKPR_EN, + FIELD_PREP(AN8855_PMCR_IFG_XMIT, 0x1) | + AN8855_PMCR_MAC_MODE | AN8855_PMCR_BACKOFF_EN | + AN8855_PMCR_BACKPR_EN); +} + +static void an8855_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) +{ + switch (port) { + case 0: + case 1: + case 2: + case 3: + case 4: + __set_bit(PHY_INTERFACE_MODE_GMII, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + break; + case 5: + phy_interface_set_rgmii(config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_SGMII, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, + config->supported_interfaces); + break; + } + + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD; +} + +static void an8855_phylink_mac_link_down(struct phylink_config *config, + unsigned int mode, + phy_interface_t interface) +{ + struct dsa_port *dp = dsa_phylink_to_port(config); + struct an8855_priv *priv = dp->ds->priv; + + /* With autoneg just disable TX/RX else also force link down */ + if (phylink_autoneg_inband(mode)) { + regmap_clear_bits(priv->regmap, AN8855_PMCR_P(dp->index), + AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN); + } else { + regmap_update_bits(priv->regmap, AN8855_PMCR_P(dp->index), + AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN | + AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK, + AN8855_PMCR_FORCE_MODE); + } +} + +static void an8855_phylink_mac_link_up(struct phylink_config *config, + struct phy_device *phydev, unsigned int mode, + phy_interface_t interface, int speed, + int duplex, bool tx_pause, bool rx_pause) +{ + struct dsa_port *dp = dsa_phylink_to_port(config); + struct an8855_priv *priv = dp->ds->priv; + int port = dp->index; + u32 reg; + + reg = regmap_read(priv->regmap, AN8855_PMCR_P(port), ®); + if (phylink_autoneg_inband(mode)) { + reg &= ~AN8855_PMCR_FORCE_MODE; + } else { + reg |= AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK; + + reg &= ~AN8855_PMCR_FORCE_SPEED; + switch (speed) { + case SPEED_10: + reg |= AN8855_PMCR_FORCE_SPEED_10; + break; + case SPEED_100: + reg |= AN8855_PMCR_FORCE_SPEED_100; + break; + case SPEED_1000: + reg |= AN8855_PMCR_FORCE_SPEED_1000; + break; + case SPEED_2500: + reg |= AN8855_PMCR_FORCE_SPEED_2500; + break; + case SPEED_5000: + dev_err(priv->dev, "Missing support for 5G speed. Aborting...\n"); + return; + } + + reg &= ~AN8855_PMCR_FORCE_FDX; + if (duplex == DUPLEX_FULL) + reg |= AN8855_PMCR_FORCE_FDX; + + reg &= ~AN8855_PMCR_RX_FC_EN; + if (rx_pause || dsa_port_is_cpu(dp)) + reg |= AN8855_PMCR_RX_FC_EN; + + reg &= ~AN8855_PMCR_TX_FC_EN; + if (rx_pause || dsa_port_is_cpu(dp)) + reg |= AN8855_PMCR_TX_FC_EN; + + /* Disable any EEE options */ + reg &= ~(AN8855_PMCR_FORCE_EEE5G | AN8855_PMCR_FORCE_EEE2P5G | + AN8855_PMCR_FORCE_EEE1G | AN8855_PMCR_FORCE_EEE100); + } + + reg |= AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN; + + regmap_write(priv->regmap, AN8855_PMCR_P(port), reg); +} + +static unsigned int an8855_pcs_inband_caps(struct phylink_pcs *pcs, + phy_interface_t interface) +{ + /* SGMII can be configured to use inband with AN result */ + if (interface == PHY_INTERFACE_MODE_SGMII) + return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; + + /* inband is not supported in 2500-baseX and must be disabled */ + return LINK_INBAND_DISABLE; +} + +static void an8855_pcs_get_state(struct phylink_pcs *pcs, + struct phylink_link_state *state) +{ + struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs); + u32 val; + int ret; + + ret = regmap_read(priv->regmap, AN8855_PMSR_P(AN8855_CPU_PORT), &val); + if (ret < 0) { + state->link = false; + return; + } + + state->link = !!(val & AN8855_PMSR_LNK); + state->an_complete = state->link; + state->duplex = (val & AN8855_PMSR_DPX) ? DUPLEX_FULL : + DUPLEX_HALF; + + switch (val & AN8855_PMSR_SPEED) { + case AN8855_PMSR_SPEED_10: + state->speed = SPEED_10; + break; + case AN8855_PMSR_SPEED_100: + state->speed = SPEED_100; + break; + case AN8855_PMSR_SPEED_1000: + state->speed = SPEED_1000; + break; + case AN8855_PMSR_SPEED_2500: + state->speed = SPEED_2500; + break; + case AN8855_PMSR_SPEED_5000: + dev_err(priv->dev, "Missing support for 5G speed. Setting Unknown.\n"); + fallthrough; + default: + state->speed = SPEED_UNKNOWN; + break; + } + + if (val & AN8855_PMSR_RX_FC) + state->pause |= MLO_PAUSE_RX; + if (val & AN8855_PMSR_TX_FC) + state->pause |= MLO_PAUSE_TX; +} + +static int an8855_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac) +{ + struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs); + u32 val; + int ret; + + /* !!! WELCOME TO HELL !!! */ + + /* TX FIR - improve TX EYE */ + ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_10, + AN8855_RG_DA_QP_TX_FIR_C2_SEL | + AN8855_RG_DA_QP_TX_FIR_C2_FORCE | + AN8855_RG_DA_QP_TX_FIR_C1_SEL | + AN8855_RG_DA_QP_TX_FIR_C1_FORCE, + AN8855_RG_DA_QP_TX_FIR_C2_SEL | + FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C2_FORCE, 0x4) | + AN8855_RG_DA_QP_TX_FIR_C1_SEL | + FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C1_FORCE, 0x0)); + if (ret) + return ret; + + if (interface == PHY_INTERFACE_MODE_2500BASEX) + val = 0x0; + else + val = 0xd; + ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_11, + AN8855_RG_DA_QP_TX_FIR_C0B_SEL | + AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, + AN8855_RG_DA_QP_TX_FIR_C0B_SEL | + FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, val)); + if (ret) + return ret; + + /* RX CDR - improve RX Jitter Tolerance */ + if (interface == PHY_INTERFACE_MODE_2500BASEX) + val = 0x5; + else + val = 0x6; + ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_BOT_LIM, + AN8855_RG_QP_CDR_LPF_KP_GAIN | + AN8855_RG_QP_CDR_LPF_KI_GAIN, + FIELD_PREP(AN8855_RG_QP_CDR_LPF_KP_GAIN, val) | + FIELD_PREP(AN8855_RG_QP_CDR_LPF_KI_GAIN, val)); + if (ret) + return ret; + + /* PLL */ + if (interface == PHY_INTERFACE_MODE_2500BASEX) + val = 0x1; + else + val = 0x0; + ret = regmap_update_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_1, + AN8855_RG_TPHY_SPEED, + FIELD_PREP(AN8855_RG_TPHY_SPEED, val)); + if (ret) + return ret; + + /* PLL - LPF */ + ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_RICO_SEL_INTF | + AN8855_RG_DA_QP_PLL_FBKSEL_INTF | + AN8855_RG_DA_QP_PLL_BR_INTF | + AN8855_RG_DA_QP_PLL_BPD_INTF | + AN8855_RG_DA_QP_PLL_BPA_INTF | + AN8855_RG_DA_QP_PLL_BC_INTF, + AN8855_RG_DA_QP_PLL_RICO_SEL_INTF | + FIELD_PREP(AN8855_RG_DA_QP_PLL_FBKSEL_INTF, 0x0) | + FIELD_PREP(AN8855_RG_DA_QP_PLL_BR_INTF, 0x3) | + FIELD_PREP(AN8855_RG_DA_QP_PLL_BPD_INTF, 0x0) | + FIELD_PREP(AN8855_RG_DA_QP_PLL_BPA_INTF, 0x5) | + FIELD_PREP(AN8855_RG_DA_QP_PLL_BC_INTF, 0x1)); + if (ret) + return ret; + + /* PLL - ICO */ + ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_4, + AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF); + if (ret) + return ret; + ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF); + if (ret) + return ret; + + /* PLL - CHP */ + if (interface == PHY_INTERFACE_MODE_2500BASEX) + val = 0x6; + else + val = 0x4; + ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_IR_INTF, + FIELD_PREP(AN8855_RG_DA_QP_PLL_IR_INTF, val)); + if (ret) + return ret; + + /* PLL - PFD */ + ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF | + AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF | + AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, + FIELD_PREP(AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF, 0x1) | + FIELD_PREP(AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, 0x1)); + if (ret) + return ret; + + /* PLL - POSTDIV */ + ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF | + AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF | + AN8855_RG_DA_QP_PLL_PCK_SEL_INTF, + AN8855_RG_DA_QP_PLL_PCK_SEL_INTF); + if (ret) + return ret; + + /* PLL - SDM */ + ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, + FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0)); + if (ret) + return ret; + ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_SDM_IFM_INTF); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_SS_LCPLL_PWCTL_SETTING_2, + AN8855_RG_NCPO_ANA_MSB, + FIELD_PREP(AN8855_RG_NCPO_ANA_MSB, 0x1)); + if (ret) + return ret; + + if (interface == PHY_INTERFACE_MODE_2500BASEX) + val = 0x7a000000; + else + val = 0x48000000; + ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_2, + FIELD_PREP(AN8855_RG_LCPLL_NCPO_VALUE, val)); + if (ret) + return ret; + ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_PCW_1, + FIELD_PREP(AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON, val)); + if (ret) + return ret; + + ret = regmap_clear_bits(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_5, + AN8855_RG_LCPLL_NCPO_CHG); + if (ret) + return ret; + ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0, + AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF); + if (ret) + return ret; + + /* PLL - SS */ + ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3, + AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, + FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, 0x0)); + if (ret) + return ret; + ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_4, + AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, + FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, 0x0)); + if (ret) + return ret; + ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3, + AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, + FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, 0x0)); + if (ret) + return ret; + + /* PLL - TDC */ + ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0, + AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF); + if (ret) + return ret; + + ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD, + AN8855_RG_QP_PLL_SSC_TRI_EN); + if (ret) + return ret; + ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD, + AN8855_RG_QP_PLL_SSC_PHASE_INI); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_RX_DAC_EN, + AN8855_RG_QP_SIGDET_HF, + FIELD_PREP(AN8855_RG_QP_SIGDET_HF, 0x2)); + if (ret) + return ret; + + /* TCL Disable (only for Co-SIM) */ + ret = regmap_clear_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_0, + AN8855_RG_QP_EQ_RX500M_CK_SEL); + if (ret) + return ret; + + /* TX Init */ + if (interface == PHY_INTERFACE_MODE_2500BASEX) + val = 0x4; + else + val = 0x0; + ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_TX_MODE, + AN8855_RG_QP_TX_RESERVE | + AN8855_RG_QP_TX_MODE_16B_EN, + FIELD_PREP(AN8855_RG_QP_TX_RESERVE, val)); + if (ret) + return ret; + + /* RX Control/Init */ + ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_RXAFE_RESERVE, + AN8855_RG_QP_CDR_PD_10B_EN); + if (ret) + return ret; + + if (interface == PHY_INTERFACE_MODE_2500BASEX) + val = 0x1; + else + val = 0x2; + ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_MJV_LIM, + AN8855_RG_QP_CDR_LPF_RATIO, + FIELD_PREP(AN8855_RG_QP_CDR_LPF_RATIO, val)); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_SETVALUE, + AN8855_RG_QP_CDR_PR_BUF_IN_SR | + AN8855_RG_QP_CDR_PR_BETA_SEL, + FIELD_PREP(AN8855_RG_QP_CDR_PR_BUF_IN_SR, 0x6) | + FIELD_PREP(AN8855_RG_QP_CDR_PR_BETA_SEL, 0x1)); + if (ret) + return ret; + + if (interface == PHY_INTERFACE_MODE_2500BASEX) + val = 0xf; + else + val = 0xc; + ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1, + AN8855_RG_QP_CDR_PR_DAC_BAND, + FIELD_PREP(AN8855_RG_QP_CDR_PR_DAC_BAND, val)); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, + AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE | + AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, + FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, 0x19)); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF, + AN8855_RG_QP_CDR_PHYCK_SEL | + AN8855_RG_QP_CDR_PHYCK_RSTB | + AN8855_RG_QP_CDR_PHYCK_DIV, + FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_SEL, 0x2) | + FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_DIV, 0x21)); + if (ret) + return ret; + + ret = regmap_clear_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, + AN8855_RG_QP_CDR_PR_XFICK_EN); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1, + AN8855_RG_QP_CDR_PR_KBAND_DIV, + FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV, 0x4)); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_26, + AN8855_RG_QP_EQ_RETRAIN_ONLY_EN | + AN8855_RG_LINK_NE_EN | + AN8855_RG_LINK_ERRO_EN, + AN8855_RG_QP_EQ_RETRAIN_ONLY_EN | + AN8855_RG_LINK_ERRO_EN); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_RX_DLY_0, + AN8855_RG_QP_RX_SAOSC_EN_H_DLY | + AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, + FIELD_PREP(AN8855_RG_QP_RX_SAOSC_EN_H_DLY, 0x3f) | + FIELD_PREP(AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, 0x6f)); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_42, + AN8855_RG_QP_EQ_EN_DLY, + FIELD_PREP(AN8855_RG_QP_EQ_EN_DLY, 0x150)); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_2, + AN8855_RG_QP_RX_EQ_EN_H_DLY, + FIELD_PREP(AN8855_RG_QP_RX_EQ_EN_H_DLY, 0x150)); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_9, + AN8855_RG_QP_EQ_LEQOSC_DLYCNT, + FIELD_PREP(AN8855_RG_QP_EQ_LEQOSC_DLYCNT, 0x1)); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_8, + AN8855_RG_DA_QP_SAOSC_DONE_TIME | + AN8855_RG_DA_QP_LEQOS_EN_TIME, + FIELD_PREP(AN8855_RG_DA_QP_SAOSC_DONE_TIME, 0x200) | + FIELD_PREP(AN8855_RG_DA_QP_LEQOS_EN_TIME, 0xfff)); + if (ret) + return ret; + + /* Frequency meter */ + if (interface == PHY_INTERFACE_MODE_2500BASEX) + val = 0x10; + else + val = 0x28; + ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_5, + AN8855_RG_FREDET_CHK_CYCLE, + FIELD_PREP(AN8855_RG_FREDET_CHK_CYCLE, val)); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_6, + AN8855_RG_FREDET_GOLDEN_CYCLE, + FIELD_PREP(AN8855_RG_FREDET_GOLDEN_CYCLE, 0x64)); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_7, + AN8855_RG_FREDET_TOLERATE_CYCLE, + FIELD_PREP(AN8855_RG_FREDET_TOLERATE_CYCLE, 0x2710)); + if (ret) + return ret; + + ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_0, + AN8855_RG_PHYA_AUTO_INIT); + if (ret) + return ret; + + /* PCS Init */ + if (interface == PHY_INTERFACE_MODE_SGMII && + neg_mode == PHYLINK_PCS_NEG_INBAND_DISABLED) { + ret = regmap_clear_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_0, + AN8855_RG_SGMII_MODE | AN8855_RG_SGMII_AN_EN); + if (ret) + return ret; + } + + ret = regmap_clear_bits(priv->regmap, AN8855_RG_HSGMII_PCS_CTROL_1, + AN8855_RG_TBI_10B_MODE); + if (ret) + return ret; + + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { + /* Set AN Ability - Interrupt */ + ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN_FORCE_CL37, + AN8855_RG_FORCE_AN_DONE); + if (ret) + return ret; + + ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN_13, + AN8855_SGMII_REMOTE_FAULT_DIS | + AN8855_SGMII_IF_MODE, + AN8855_SGMII_REMOTE_FAULT_DIS | + FIELD_PREP(AN8855_SGMII_IF_MODE, 0xb)); + if (ret) + return ret; + } + + /* Rate Adaption - GMII path config. */ + if (interface == PHY_INTERFACE_MODE_2500BASEX) { + ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0, + AN8855_RG_P0_DIS_MII_MODE); + if (ret) + return ret; + } else { + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { + ret = regmap_set_bits(priv->regmap, AN8855_MII_RA_AN_ENABLE, + AN8855_RG_P0_RA_AN_EN); + if (ret) + return ret; + } else { + ret = regmap_update_bits(priv->regmap, AN8855_RG_AN_SGMII_MODE_FORCE, + AN8855_RG_FORCE_CUR_SGMII_MODE | + AN8855_RG_FORCE_CUR_SGMII_SEL, + AN8855_RG_FORCE_CUR_SGMII_SEL); + if (ret) + return ret; + + ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0, + AN8855_RG_P0_MII_RA_RX_EN | + AN8855_RG_P0_MII_RA_TX_EN | + AN8855_RG_P0_MII_RA_RX_MODE | + AN8855_RG_P0_MII_RA_TX_MODE); + if (ret) + return ret; + } + + ret = regmap_set_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0, + AN8855_RG_P0_MII_MODE); + if (ret) + return ret; + } + + ret = regmap_set_bits(priv->regmap, AN8855_RG_RATE_ADAPT_CTRL_0, + AN8855_RG_RATE_ADAPT_RX_BYPASS | + AN8855_RG_RATE_ADAPT_TX_BYPASS | + AN8855_RG_RATE_ADAPT_RX_EN | + AN8855_RG_RATE_ADAPT_TX_EN); + if (ret) + return ret; + + /* Disable AN if not in autoneg */ + ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN0, BMCR_ANENABLE, + neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? BMCR_ANENABLE : + 0); + if (ret) + return ret; + + if (interface == PHY_INTERFACE_MODE_SGMII) { + /* Follow SDK init flow with restarting AN after AN enable */ + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { + ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN0, + BMCR_ANRESTART); + if (ret) + return ret; + } else { + ret = regmap_set_bits(priv->regmap, AN8855_PHY_RX_FORCE_CTRL_0, + AN8855_RG_FORCE_TXC_SEL); + if (ret) + return ret; + } + } + + /* Force Speed with fixed-link or 2500base-x as doesn't support aneg */ + if (interface == PHY_INTERFACE_MODE_2500BASEX || + neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) { + if (interface == PHY_INTERFACE_MODE_2500BASEX) + val = AN8855_RG_LINK_MODE_P0_SPEED_2500; + else + val = AN8855_RG_LINK_MODE_P0_SPEED_1000; + ret = regmap_update_bits(priv->regmap, AN8855_SGMII_STS_CTRL_0, + AN8855_RG_LINK_MODE_P0 | + AN8855_RG_FORCE_SPD_MODE_P0, + val | AN8855_RG_FORCE_SPD_MODE_P0); + if (ret) + return ret; + } + + /* bypass flow control to MAC */ + ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_0, + AN8855_RG_DPX_STS_P3 | AN8855_RG_DPX_STS_P2 | + AN8855_RG_DPX_STS_P1 | AN8855_RG_TXFC_STS_P0 | + AN8855_RG_RXFC_STS_P0 | AN8855_RG_DPX_STS_P0); + if (ret) + return ret; + ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_2, + AN8855_RG_RXFC_AN_BYPASS_P3 | + AN8855_RG_RXFC_AN_BYPASS_P2 | + AN8855_RG_RXFC_AN_BYPASS_P1 | + AN8855_RG_TXFC_AN_BYPASS_P3 | + AN8855_RG_TXFC_AN_BYPASS_P2 | + AN8855_RG_TXFC_AN_BYPASS_P1 | + AN8855_RG_DPX_AN_BYPASS_P3 | + AN8855_RG_DPX_AN_BYPASS_P2 | + AN8855_RG_DPX_AN_BYPASS_P1 | + AN8855_RG_DPX_AN_BYPASS_P0); + if (ret) + return ret; + + return 0; +} + +static void an8855_pcs_an_restart(struct phylink_pcs *pcs) +{ + return; +} + +static const struct phylink_pcs_ops an8855_pcs_ops = { + .pcs_inband_caps = an8855_pcs_inband_caps, + .pcs_get_state = an8855_pcs_get_state, + .pcs_config = an8855_pcs_config, + .pcs_an_restart = an8855_pcs_an_restart, +}; + +static const struct phylink_mac_ops an8855_phylink_mac_ops = { + .mac_select_pcs = an8855_phylink_mac_select_pcs, + .mac_config = an8855_phylink_mac_config, + .mac_link_down = an8855_phylink_mac_link_down, + .mac_link_up = an8855_phylink_mac_link_up, +}; + +static const struct dsa_switch_ops an8855_switch_ops = { + .get_tag_protocol = an8855_get_tag_protocol, + .setup = an8855_setup, + .get_phy_flags = en8855_get_phy_flags, + .phylink_get_caps = an8855_phylink_get_caps, + .get_strings = an8855_get_strings, + .get_ethtool_stats = an8855_get_ethtool_stats, + .get_sset_count = an8855_get_sset_count, + .get_eth_mac_stats = an8855_get_eth_mac_stats, + .get_eth_ctrl_stats = an8855_get_eth_ctrl_stats, + .get_rmon_stats = an8855_get_rmon_stats, + .port_enable = an8855_port_enable, + .port_disable = an8855_port_disable, + .set_ageing_time = an8855_set_ageing_time, + .port_bridge_join = an8855_port_bridge_join, + .port_bridge_leave = an8855_port_bridge_leave, + .port_fast_age = an8855_port_fast_age, + .port_stp_state_set = an8855_port_stp_state_set, + .port_pre_bridge_flags = an8855_port_pre_bridge_flags, + .port_bridge_flags = an8855_port_bridge_flags, + .port_vlan_filtering = an8855_port_vlan_filtering, + .port_vlan_add = an8855_port_vlan_add, + .port_vlan_del = an8855_port_vlan_del, + .port_fdb_add = an8855_port_fdb_add, + .port_fdb_del = an8855_port_fdb_del, + .port_fdb_dump = an8855_port_fdb_dump, + .port_mdb_add = an8855_port_mdb_add, + .port_mdb_del = an8855_port_mdb_del, + .port_change_mtu = an8855_port_change_mtu, + .port_max_mtu = an8855_port_max_mtu, + .port_mirror_add = an8855_port_mirror_add, + .port_mirror_del = an8855_port_mirror_del, +}; + +static int an8855_read_switch_id(struct an8855_priv *priv) +{ + u32 id; + int ret; + + ret = regmap_read(priv->regmap, AN8855_CREV, &id); + if (ret) + return ret; + + if (id != AN8855_ID) { + dev_err(priv->dev, + "Switch id detected %x but expected %x\n", + id, AN8855_ID); + return -ENODEV; + } + + return 0; +} + +static int an8855_switch_probe(struct platform_device *pdev) +{ + struct an8855_priv *priv; + u32 val; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + priv->phy_require_calib = of_property_read_bool(priv->dev->of_node, + "airoha,ext-surge"); + + priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(priv->reset_gpio)) + return PTR_ERR(priv->reset_gpio); + + /* Get regmap from MFD */ + priv->regmap = dev_get_regmap(priv->dev->parent, NULL); + + if (priv->reset_gpio) { + usleep_range(100000, 150000); + gpiod_set_value_cansleep(priv->reset_gpio, 0); + usleep_range(100000, 150000); + gpiod_set_value_cansleep(priv->reset_gpio, 1); + + /* Poll HWTRAP reg to wait for Switch to fully Init */ + ret = regmap_read_poll_timeout(priv->regmap, AN8855_HWTRAP, val, + val, 20, 200000); + if (ret) + return ret; + } + + ret = an8855_read_switch_id(priv); + if (ret) + return ret; + + priv->ds = devm_kzalloc(priv->dev, sizeof(*priv->ds), GFP_KERNEL); + if (!priv->ds) + return -ENOMEM; + + priv->ds->dev = priv->dev; + priv->ds->num_ports = AN8855_NUM_PORTS; + priv->ds->priv = priv; + priv->ds->ops = &an8855_switch_ops; + devm_mutex_init(priv->dev, &priv->reg_mutex); + priv->ds->phylink_mac_ops = &an8855_phylink_mac_ops; + + priv->pcs.ops = &an8855_pcs_ops; + priv->pcs.neg_mode = true; + priv->pcs.poll = true; + + dev_set_drvdata(priv->dev, priv); + + return dsa_register_switch(priv->ds); +} + +static void an8855_switch_remove(struct platform_device *pdev) +{ + struct an8855_priv *priv = dev_get_drvdata(&pdev->dev); + + if (priv) + dsa_unregister_switch(priv->ds); +} + +static const struct of_device_id an8855_switch_of_match[] = { + { .compatible = "airoha,an8855-switch" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, an8855_switch_of_match); + +static struct platform_driver an8855_switch_driver = { + .probe = an8855_switch_probe, + .remove_new = an8855_switch_remove, + .driver = { + .name = "an8855-switch", + .of_match_table = an8855_switch_of_match, + }, +}; +module_platform_driver(an8855_switch_driver); + +MODULE_AUTHOR("Min Yao "); +MODULE_AUTHOR("Christian Marangi "); +MODULE_DESCRIPTION("Driver for Airoha AN8855 Switch"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.h b/target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.h new file mode 100644 index 0000000000..2462b9d337 --- /dev/null +++ b/target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.h @@ -0,0 +1,783 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Min Yao + * Copyright (C) 2024 Christian Marangi + */ + +#ifndef __AN8855_H +#define __AN8855_H + +#include + +#define AN8855_NUM_PORTS 6 +#define AN8855_CPU_PORT 5 +#define AN8855_NUM_FDB_RECORDS 2048 +#define AN8855_GPHY_SMI_ADDR_DEFAULT 1 +#define AN8855_PORT_VID_DEFAULT 0 + +#define MTK_TAG_LEN 4 +#define AN8855_MAX_MTU (15360 - ETH_HLEN - ETH_FCS_LEN - MTK_TAG_LEN) + +#define AN8855_L2_AGING_MS_CONSTANT 1024 + +#define AN8855_PHY_FLAGS_EN_CALIBRATION BIT(0) + +/* AN8855_SCU 0x10000000 */ +#define AN8855_RG_GPIO_LED_MODE 0x10000054 +#define AN8855_RG_GPIO_LED_SEL(i) (0x10000000 + (0x0058 + ((i) * 4))) +#define AN8855_RG_INTB_MODE 0x10000080 +#define AN8855_RG_RGMII_TXCK_C 0x100001d0 + +#define AN8855_PKG_SEL 0x10000094 +#define AN8855_PAG_SEL_AN8855H 0x2 + +/* Register for hw trap status */ +#define AN8855_HWTRAP 0x1000009c + +#define AN8855_RG_GPIO_L_INV 0x10000010 +#define AN8855_RG_GPIO_CTRL 0x1000a300 +#define AN8855_RG_GPIO_DATA 0x1000a304 +#define AN8855_RG_GPIO_OE 0x1000a314 + +#define AN8855_CREV 0x10005000 +#define AN8855_ID 0x8855 + +/* Register for system reset */ +#define AN8855_RST_CTRL 0x100050c0 +#define AN8855_SYS_CTRL_SYS_RST BIT(31) + +#define AN8855_INT_MASK 0x100050f0 +#define AN8855_INT_SYS BIT(15) + +#define AN8855_RG_CLK_CPU_ICG 0x10005034 +#define AN8855_MCU_ENABLE BIT(3) + +#define AN8855_RG_TIMER_CTL 0x1000a100 +#define AN8855_WDOG_ENABLE BIT(25) + +#define AN8855_RG_GDMP_RAM 0x10010000 + +/* Registers to mac forward control for unknown frames */ +#define AN8855_MFC 0x10200010 +#define AN8855_CPU_EN BIT(15) +#define AN8855_CPU_PORT_IDX GENMASK(12, 8) + +#define AN8855_PAC 0x10200024 +#define AN8855_TAG_PAE_MANG_FR BIT(30) +#define AN8855_TAG_PAE_BPDU_FR BIT(28) +#define AN8855_TAG_PAE_EG_TAG GENMASK(27, 25) +#define AN8855_TAG_PAE_LKY_VLAN BIT(24) +#define AN8855_TAG_PAE_PRI_HIGH BIT(23) +#define AN8855_TAG_PAE_MIR GENMASK(20, 19) +#define AN8855_TAG_PAE_PORT_FW GENMASK(18, 16) +#define AN8855_PAE_MANG_FR BIT(14) +#define AN8855_PAE_BPDU_FR BIT(12) +#define AN8855_PAE_EG_TAG GENMASK(11, 9) +#define AN8855_PAE_LKY_VLAN BIT(8) +#define AN8855_PAE_PRI_HIGH BIT(7) +#define AN8855_PAE_MIR GENMASK(4, 3) +#define AN8855_PAE_PORT_FW GENMASK(2, 0) + +#define AN8855_RGAC1 0x10200028 +#define AN8855_R02_MANG_FR BIT(30) +#define AN8855_R02_BPDU_FR BIT(28) +#define AN8855_R02_EG_TAG GENMASK(27, 25) +#define AN8855_R02_LKY_VLAN BIT(24) +#define AN8855_R02_PRI_HIGH BIT(23) +#define AN8855_R02_MIR GENMASK(20, 19) +#define AN8855_R02_PORT_FW GENMASK(18, 16) +#define AN8855_R01_MANG_FR BIT(14) +#define AN8855_R01_BPDU_FR BIT(12) +#define AN8855_R01_EG_TAG GENMASK(11, 9) +#define AN8855_R01_LKY_VLAN BIT(8) +#define AN8855_R01_PRI_HIGH BIT(7) +#define AN8855_R01_MIR GENMASK(4, 3) +#define AN8855_R01_PORT_FW GENMASK(2, 0) + +#define AN8855_RGAC2 0x1020002c +#define AN8855_R0E_MANG_FR BIT(30) +#define AN8855_R0E_BPDU_FR BIT(28) +#define AN8855_R0E_EG_TAG GENMASK(27, 25) +#define AN8855_R0E_LKY_VLAN BIT(24) +#define AN8855_R0E_PRI_HIGH BIT(23) +#define AN8855_R0E_MIR GENMASK(20, 19) +#define AN8855_R0E_PORT_FW GENMASK(18, 16) +#define AN8855_R03_MANG_FR BIT(14) +#define AN8855_R03_BPDU_FR BIT(12) +#define AN8855_R03_EG_TAG GENMASK(11, 9) +#define AN8855_R03_LKY_VLAN BIT(8) +#define AN8855_R03_PRI_HIGH BIT(7) +#define AN8855_R03_MIR GENMASK(4, 3) +#define AN8855_R03_PORT_FW GENMASK(2, 0) + +#define AN8855_AAC 0x102000a0 +#define AN8855_MAC_AUTO_FLUSH BIT(28) +/* Control Address Table Age time. + * (AN8855_AGE_CNT + 1) * ( AN8855_AGE_UNIT + 1 ) * AN8855_L2_AGING_MS_CONSTANT + */ +#define AN8855_AGE_CNT GENMASK(20, 12) +/* Value in seconds. Value is always incremented of 1 */ +#define AN8855_AGE_UNIT GENMASK(10, 0) + +/* Registers for ARL Unknown Unicast Forward control */ +#define AN8855_UNUF 0x102000b4 + +/* Registers for ARL Unknown Multicast Forward control */ +#define AN8855_UNMF 0x102000b8 + +/* Registers for ARL Broadcast forward control */ +#define AN8855_BCF 0x102000bc + +/* Registers for port address age disable */ +#define AN8855_AGDIS 0x102000c0 + +/* Registers for mirror port control */ +#define AN8855_MIR 0x102000cc +#define AN8855_MIRROR_EN BIT(7) +#define AN8855_MIRROR_PORT GENMASK(4, 0) + +/* Registers for BPDU and PAE frame control*/ +#define AN8855_BPC 0x102000d0 +#define AN8855_BPDU_MANG_FR BIT(14) +#define AN8855_BPDU_BPDU_FR BIT(12) +#define AN8855_BPDU_EG_TAG GENMASK(11, 9) +#define AN8855_BPDU_LKY_VLAN BIT(8) +#define AN8855_BPDU_PRI_HIGH BIT(7) +#define AN8855_BPDU_MIR GENMASK(4, 3) +#define AN8855_BPDU_PORT_FW GENMASK(2, 0) + +/* Registers for IP Unknown Multicast Forward control */ +#define AN8855_UNIPMF 0x102000dc + +enum an8855_bpdu_port_fw { + AN8855_BPDU_FOLLOW_MFC = 0, + AN8855_BPDU_CPU_EXCLUDE = 4, + AN8855_BPDU_CPU_INCLUDE = 5, + AN8855_BPDU_CPU_ONLY = 6, + AN8855_BPDU_DROP = 7, +}; + +/* Register for address table control */ +#define AN8855_ATC 0x10200300 +#define AN8855_ATC_BUSY BIT(31) +#define AN8855_ATC_HASH GENMASK(24, 16) +#define AN8855_ATC_HIT GENMASK(15, 12) +#define AN8855_ATC_MAT_MASK GENMASK(11, 7) +#define AN8855_ATC_MAT(x) FIELD_PREP(AN8855_ATC_MAT_MASK, x) +#define AN8855_ATC_SAT GENMASK(5, 4) +#define AN8855_ATC_CMD GENMASK(2, 0) + +enum an8855_fdb_mat_cmds { + AND8855_FDB_MAT_ALL = 0, + AND8855_FDB_MAT_MAC, /* All MAC address */ + AND8855_FDB_MAT_DYNAMIC_MAC, /* All Dynamic MAC address */ + AND8855_FDB_MAT_STATIC_MAC, /* All Static Mac Address */ + AND8855_FDB_MAT_DIP, /* All DIP/GA address */ + AND8855_FDB_MAT_DIP_IPV4, /* All DIP/GA IPv4 address */ + AND8855_FDB_MAT_DIP_IPV6, /* All DIP/GA IPv6 address */ + AND8855_FDB_MAT_DIP_SIP, /* All DIP_SIP address */ + AND8855_FDB_MAT_DIP_SIP_IPV4, /* All DIP_SIP IPv4 address */ + AND8855_FDB_MAT_DIP_SIP_IPV6, /* All DIP_SIP IPv6 address */ + AND8855_FDB_MAT_MAC_CVID, /* All MAC address with CVID */ + AND8855_FDB_MAT_MAC_FID, /* All MAC address with Filter ID */ + AND8855_FDB_MAT_MAC_PORT, /* All MAC address with port */ + AND8855_FDB_MAT_DIP_SIP_DIP_IPV4, /* All DIP_SIP address with DIP_IPV4 */ + AND8855_FDB_MAT_DIP_SIP_SIP_IPV4, /* All DIP_SIP address with SIP_IPV4 */ + AND8855_FDB_MAT_DIP_SIP_DIP_IPV6, /* All DIP_SIP address with DIP_IPV6 */ + AND8855_FDB_MAT_DIP_SIP_SIP_IPV6, /* All DIP_SIP address with SIP_IPV6 */ + /* All MAC address with MAC type (dynamic or static) with CVID */ + AND8855_FDB_MAT_MAC_TYPE_CVID, + /* All MAC address with MAC type (dynamic or static) with Filter ID */ + AND8855_FDB_MAT_MAC_TYPE_FID, + /* All MAC address with MAC type (dynamic or static) with port */ + AND8855_FDB_MAT_MAC_TYPE_PORT, +}; + +enum an8855_fdb_cmds { + AN8855_FDB_READ = 0, + AN8855_FDB_WRITE = 1, + AN8855_FDB_FLUSH = 2, + AN8855_FDB_START = 4, + AN8855_FDB_NEXT = 5, +}; + +/* Registers for address table access */ +#define AN8855_ATA1 0x10200304 +#define AN8855_ATA1_MAC0 GENMASK(31, 24) +#define AN8855_ATA1_MAC1 GENMASK(23, 16) +#define AN8855_ATA1_MAC2 GENMASK(15, 8) +#define AN8855_ATA1_MAC3 GENMASK(7, 0) +#define AN8855_ATA2 0x10200308 +#define AN8855_ATA2_MAC4 GENMASK(31, 24) +#define AN8855_ATA2_MAC5 GENMASK(23, 16) +#define AN8855_ATA2_UNAUTH BIT(10) +#define AN8855_ATA2_TYPE BIT(9) /* 1: dynamic, 0: static */ +#define AN8855_ATA2_AGE GENMASK(8, 0) + +/* Register for address table write data */ +#define AN8855_ATWD 0x10200324 +#define AN8855_ATWD_FID GENMASK(31, 28) +#define AN8855_ATWD_VID GENMASK(27, 16) +#define AN8855_ATWD_IVL BIT(15) +#define AN8855_ATWD_EG_TAG GENMASK(14, 12) +#define AN8855_ATWD_SA_MIR GENMASK(9, 8) +#define AN8855_ATWD_SA_FWD GENMASK(7, 5) +#define AN8855_ATWD_UPRI GENMASK(4, 2) +#define AN8855_ATWD_LEAKY BIT(1) +#define AN8855_ATWD_VLD BIT(0) /* vid LOAD */ +#define AN8855_ATWD2 0x10200328 +#define AN8855_ATWD2_PORT GENMASK(7, 0) + +/* Registers for table search read address */ +#define AN8855_ATRDS 0x10200330 +#define AN8855_ATRD_SEL GENMASK(1, 0) +#define AN8855_ATRD0 0x10200334 +#define AN8855_ATRD0_FID GENMASK(28, 25) +#define AN8855_ATRD0_VID GENMASK(21, 10) +#define AN8855_ATRD0_IVL BIT(9) +#define AN8855_ATRD0_TYPE GENMASK(4, 3) +#define AN8855_ATRD0_ARP GENMASK(2, 1) +#define AN8855_ATRD0_LIVE BIT(0) +#define AN8855_ATRD1 0x10200338 +#define AN8855_ATRD1_MAC4 GENMASK(31, 24) +#define AN8855_ATRD1_MAC5 GENMASK(23, 16) +#define AN8855_ATRD1_AGING GENMASK(11, 3) +#define AN8855_ATRD2 0x1020033c +#define AN8855_ATRD2_MAC0 GENMASK(31, 24) +#define AN8855_ATRD2_MAC1 GENMASK(23, 16) +#define AN8855_ATRD2_MAC2 GENMASK(15, 8) +#define AN8855_ATRD2_MAC3 GENMASK(7, 0) +#define AN8855_ATRD3 0x10200340 +#define AN8855_ATRD3_PORTMASK GENMASK(7, 0) + +enum an8855_fdb_type { + AN8855_MAC_TB_TY_MAC = 0, + AN8855_MAC_TB_TY_DIP = 1, + AN8855_MAC_TB_TY_DIP_SIP = 2, +}; + +/* Register for vlan table control */ +#define AN8855_VTCR 0x10200600 +#define AN8855_VTCR_BUSY BIT(31) +#define AN8855_VTCR_FUNC GENMASK(15, 12) +#define AN8855_VTCR_VID GENMASK(11, 0) + +enum an8855_vlan_cmd { + /* Read/Write the specified VID entry from VAWD register based + * on VID. + */ + AN8855_VTCR_RD_VID = 0, + AN8855_VTCR_WR_VID = 1, +}; + +/* Register for setup vlan write data */ +#define AN8855_VAWD0 0x10200604 +/* VLAN Member Control */ +#define AN8855_VA0_PORT GENMASK(31, 26) +/* Egress Tag Control */ +#define AN8855_VA0_ETAG GENMASK(23, 12) +#define AN8855_VA0_ETAG_PORT GENMASK(13, 12) +#define AN8855_VA0_ETAG_PORT_SHIFT(port) ((port) * 2) +#define AN8855_VA0_ETAG_PORT_MASK(port) (AN8855_VA0_ETAG_PORT << \ + AN8855_VA0_ETAG_PORT_SHIFT(port)) +#define AN8855_VA0_ETAG_PORT_VAL(port, val) (FIELD_PREP(AN8855_VA0_ETAG_PORT, (val)) << \ + AN8855_VA0_ETAG_PORT_SHIFT(port)) +#define AN8855_VA0_EG_CON BIT(11) +#define AN8855_VA0_VTAG_EN BIT(10) /* Per VLAN Egress Tag Control */ +#define AN8855_VA0_IVL_MAC BIT(5) /* Independent VLAN Learning */ +#define AN8855_VA0_FID GENMASK(4, 1) +#define AN8855_VA0_VLAN_VALID BIT(0) /* VLAN Entry Valid */ +#define AN8855_VAWD1 0x10200608 +#define AN8855_VA1_PORT_STAG BIT(1) + +enum an8855_fid { + AN8855_FID_STANDALONE = 0, + AN8855_FID_BRIDGED = 1, +}; + +/* Same register field of VAWD0 */ +#define AN8855_VARD0 0x10200618 + +enum an8855_vlan_egress_attr { + AN8855_VLAN_EGRESS_UNTAG = 0, + AN8855_VLAN_EGRESS_TAG = 2, + AN8855_VLAN_EGRESS_STACK = 3, +}; + +/* Register for port STP state control */ +#define AN8855_SSP_P(x) (0x10208000 + ((x) * 0x200)) +/* Up to 16 FID supported, each with the same mask */ +#define AN8855_FID_PST GENMASK(1, 0) +#define AN8855_FID_PST_SHIFT(fid) (2 * (fid)) +#define AN8855_FID_PST_MASK(fid) (AN8855_FID_PST << \ + AN8855_FID_PST_SHIFT(fid)) +#define AN8855_FID_PST_VAL(fid, val) (FIELD_PREP(AN8855_FID_PST, (val)) << \ + AN8855_FID_PST_SHIFT(fid)) + +enum an8855_stp_state { + AN8855_STP_DISABLED = 0, + AN8855_STP_BLOCKING = 1, + AN8855_STP_LISTENING = AN8855_STP_BLOCKING, + AN8855_STP_LEARNING = 2, + AN8855_STP_FORWARDING = 3 +}; + +/* Register for port control */ +#define AN8855_PCR_P(x) (0x10208004 + ((x) * 0x200)) +#define AN8855_EG_TAG GENMASK(29, 28) +#define AN8855_PORT_PRI GENMASK(26, 24) +#define AN8855_PORT_TX_MIR BIT(20) +#define AN8855_PORT_RX_MIR BIT(16) +#define AN8855_PORT_VLAN GENMASK(1, 0) + +enum an8855_port_mode { + /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ + AN8855_PORT_MATRIX_MODE = 0, + + /* Fallback Mode: Forward received frames with ingress ports that do + * not belong to the VLAN member. Frames whose VID is not listed on + * the VLAN table are forwarded by the PCR_MATRIX members. + */ + AN8855_PORT_FALLBACK_MODE = 1, + + /* Check Mode: Forward received frames whose ingress do not + * belong to the VLAN member. Discard frames if VID ismiddes on the + * VLAN table. + */ + AN8855_PORT_CHECK_MODE = 2, + + /* Security Mode: Discard any frame due to ingress membership + * violation or VID missed on the VLAN table. + */ + AN8855_PORT_SECURITY_MODE = 3, +}; + +/* Register for port security control */ +#define AN8855_PSC_P(x) (0x1020800c + ((x) * 0x200)) +#define AN8855_SA_DIS BIT(4) + +/* Register for port vlan control */ +#define AN8855_PVC_P(x) (0x10208010 + ((x) * 0x200)) +#define AN8855_PORT_SPEC_REPLACE_MODE BIT(11) +#define AN8855_PVC_EG_TAG GENMASK(10, 8) +#define AN8855_VLAN_ATTR GENMASK(7, 6) +#define AN8855_PORT_SPEC_TAG BIT(5) +#define AN8855_ACC_FRM GENMASK(1, 0) + +enum an8855_vlan_port_eg_tag { + AN8855_VLAN_EG_DISABLED = 0, + AN8855_VLAN_EG_CONSISTENT = 1, + AN8855_VLAN_EG_UNTAGGED = 4, + AN8855_VLAN_EG_SWAP = 5, + AN8855_VLAN_EG_TAGGED = 6, + AN8855_VLAN_EG_STACK = 7, +}; + +enum an8855_vlan_port_attr { + AN8855_VLAN_USER = 0, + AN8855_VLAN_STACK = 1, + AN8855_VLAN_TRANSPARENT = 3, +}; + +enum an8855_vlan_port_acc_frm { + AN8855_VLAN_ACC_ALL = 0, + AN8855_VLAN_ACC_TAGGED = 1, + AN8855_VLAN_ACC_UNTAGGED = 2, +}; + +#define AN8855_PPBV1_P(x) (0x10208014 + ((x) * 0x200)) +#define AN8855_PPBV_G0_PORT_VID GENMASK(11, 0) + +#define AN8855_PORTMATRIX_P(x) (0x10208044 + ((x) * 0x200)) +#define AN8855_PORTMATRIX GENMASK(5, 0) +/* Port matrix without the CPU port that should never be removed */ +#define AN8855_USER_PORTMATRIX GENMASK(4, 0) + +/* Register for port PVID */ +#define AN8855_PVID_P(x) (0x10208048 + ((x) * 0x200)) +#define AN8855_G0_PORT_VID GENMASK(11, 0) + +/* Register for port MAC control register */ +#define AN8855_PMCR_P(x) (0x10210000 + ((x) * 0x200)) +#define AN8855_PMCR_FORCE_MODE BIT(31) +#define AN8855_PMCR_FORCE_SPEED GENMASK(30, 28) +#define AN8855_PMCR_FORCE_SPEED_5000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x4) +#define AN8855_PMCR_FORCE_SPEED_2500 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x3) +#define AN8855_PMCR_FORCE_SPEED_1000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x2) +#define AN8855_PMCR_FORCE_SPEED_100 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1) +#define AN8855_PMCR_FORCE_SPEED_10 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1) +#define AN8855_PMCR_FORCE_FDX BIT(25) +#define AN8855_PMCR_FORCE_LNK BIT(24) +#define AN8855_PMCR_IFG_XMIT GENMASK(21, 20) +#define AN8855_PMCR_EXT_PHY BIT(19) +#define AN8855_PMCR_MAC_MODE BIT(18) +#define AN8855_PMCR_TX_EN BIT(16) +#define AN8855_PMCR_RX_EN BIT(15) +#define AN8855_PMCR_BACKOFF_EN BIT(12) +#define AN8855_PMCR_BACKPR_EN BIT(11) +#define AN8855_PMCR_FORCE_EEE5G BIT(9) +#define AN8855_PMCR_FORCE_EEE2P5G BIT(8) +#define AN8855_PMCR_FORCE_EEE1G BIT(7) +#define AN8855_PMCR_FORCE_EEE100 BIT(6) +#define AN8855_PMCR_TX_FC_EN BIT(5) +#define AN8855_PMCR_RX_FC_EN BIT(4) + +#define AN8855_PMSR_P(x) (0x10210010 + (x) * 0x200) +#define AN8855_PMSR_SPEED GENMASK(30, 28) +#define AN8855_PMSR_SPEED_5000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x4) +#define AN8855_PMSR_SPEED_2500 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x3) +#define AN8855_PMSR_SPEED_1000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x2) +#define AN8855_PMSR_SPEED_100 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x1) +#define AN8855_PMSR_SPEED_10 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x0) +#define AN8855_PMSR_DPX BIT(25) +#define AN8855_PMSR_LNK BIT(24) +#define AN8855_PMSR_EEE1G BIT(7) +#define AN8855_PMSR_EEE100M BIT(6) +#define AN8855_PMSR_RX_FC BIT(5) +#define AN8855_PMSR_TX_FC BIT(4) + +#define AN8855_PMEEECR_P(x) (0x10210004 + (x) * 0x200) +#define AN8855_LPI_MODE_EN BIT(31) +#define AN8855_WAKEUP_TIME_2500 GENMASK(23, 16) +#define AN8855_WAKEUP_TIME_1000 GENMASK(15, 8) +#define AN8855_WAKEUP_TIME_100 GENMASK(7, 0) +#define AN8855_PMEEECR2_P(x) (0x10210008 + (x) * 0x200) +#define AN8855_WAKEUP_TIME_5000 GENMASK(7, 0) + +#define AN8855_GMACCR 0x10213e00 +#define AN8855_MAX_RX_JUMBO GENMASK(7, 4) +/* 2K for 0x0, 0x1, 0x2 */ +#define AN8855_MAX_RX_JUMBO_2K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x0) +#define AN8855_MAX_RX_JUMBO_3K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x3) +#define AN8855_MAX_RX_JUMBO_4K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x4) +#define AN8855_MAX_RX_JUMBO_5K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x5) +#define AN8855_MAX_RX_JUMBO_6K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x6) +#define AN8855_MAX_RX_JUMBO_7K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x7) +#define AN8855_MAX_RX_JUMBO_8K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x8) +#define AN8855_MAX_RX_JUMBO_9K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9) +#define AN8855_MAX_RX_JUMBO_12K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa) +#define AN8855_MAX_RX_JUMBO_15K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb) +#define AN8855_MAX_RX_JUMBO_16K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc) +#define AN8855_MAX_RX_PKT_LEN GENMASK(1, 0) +#define AN8855_MAX_RX_PKT_1518_1522 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x0) +#define AN8855_MAX_RX_PKT_1536 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x1) +#define AN8855_MAX_RX_PKT_1552 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x2) +#define AN8855_MAX_RX_PKT_JUMBO FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x3) + +#define AN8855_CKGCR 0x10213e1c +#define AN8855_LPI_TXIDLE_THD_MASK GENMASK(31, 14) +#define AN8855_CKG_LNKDN_PORT_STOP BIT(1) +#define AN8855_CKG_LNKDN_GLB_STOP BIT(0) + +/* Register for MIB */ +#define AN8855_PORT_MIB_COUNTER(x) (0x10214000 + (x) * 0x200) +/* Each define is an offset of AN8855_PORT_MIB_COUNTER */ +#define AN8855_PORT_MIB_TX_DROP 0x00 +#define AN8855_PORT_MIB_TX_CRC_ERR 0x04 +#define AN8855_PORT_MIB_TX_UNICAST 0x08 +#define AN8855_PORT_MIB_TX_MULTICAST 0x0c +#define AN8855_PORT_MIB_TX_BROADCAST 0x10 +#define AN8855_PORT_MIB_TX_COLLISION 0x14 +#define AN8855_PORT_MIB_TX_SINGLE_COLLISION 0x18 +#define AN8855_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c +#define AN8855_PORT_MIB_TX_DEFERRED 0x20 +#define AN8855_PORT_MIB_TX_LATE_COLLISION 0x24 +#define AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28 +#define AN8855_PORT_MIB_TX_PAUSE 0x2c +#define AN8855_PORT_MIB_TX_PKT_SZ_64 0x30 +#define AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34 +#define AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38 +#define AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3 +#define AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40 +#define AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518 0x44 +#define AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX 0x48 +#define AN8855_PORT_MIB_TX_BYTES 0x4c /* 64 bytes */ +#define AN8855_PORT_MIB_TX_OVERSIZE_DROP 0x54 +#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES 0x58 /* 64 bytes */ +#define AN8855_PORT_MIB_RX_DROP 0x80 +#define AN8855_PORT_MIB_RX_FILTERING 0x84 +#define AN8855_PORT_MIB_RX_UNICAST 0x88 +#define AN8855_PORT_MIB_RX_MULTICAST 0x8c +#define AN8855_PORT_MIB_RX_BROADCAST 0x90 +#define AN8855_PORT_MIB_RX_ALIGN_ERR 0x94 +#define AN8855_PORT_MIB_RX_CRC_ERR 0x98 +#define AN8855_PORT_MIB_RX_UNDER_SIZE_ERR 0x9c +#define AN8855_PORT_MIB_RX_FRAG_ERR 0xa0 +#define AN8855_PORT_MIB_RX_OVER_SZ_ERR 0xa4 +#define AN8855_PORT_MIB_RX_JABBER_ERR 0xa8 +#define AN8855_PORT_MIB_RX_PAUSE 0xac +#define AN8855_PORT_MIB_RX_PKT_SZ_64 0xb0 +#define AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127 0xb4 +#define AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255 0xb8 +#define AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511 0xbc +#define AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xc0 +#define AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518 0xc4 +#define AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX 0xc8 +#define AN8855_PORT_MIB_RX_BYTES 0xcc /* 64 bytes */ +#define AN8855_PORT_MIB_RX_CTRL_DROP 0xd4 +#define AN8855_PORT_MIB_RX_INGRESS_DROP 0xd8 +#define AN8855_PORT_MIB_RX_ARL_DROP 0xdc +#define AN8855_PORT_MIB_FLOW_CONTROL_DROP 0xe0 +#define AN8855_PORT_MIB_WRED_DROP 0xe4 +#define AN8855_PORT_MIB_MIRROR_DROP 0xe8 +#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES 0xec /* 64 bytes */ +#define AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP 0xf4 +#define AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP 0xf8 +#define AN8855_PORT_MIB_PORT_CONTROL_DROP 0xfc +#define AN8855_MIB_CCR 0x10213e30 +#define AN8855_CCR_MIB_ENABLE BIT(31) +#define AN8855_CCR_RX_OCT_CNT_GOOD BIT(7) +#define AN8855_CCR_RX_OCT_CNT_BAD BIT(6) +#define AN8855_CCR_TX_OCT_CNT_GOOD BIT(5) +#define AN8855_CCR_TX_OCT_CNT_BAD BIT(4) +#define AN8855_CCR_RX_OCT_CNT_GOOD_2 BIT(3) +#define AN8855_CCR_RX_OCT_CNT_BAD_2 BIT(2) +#define AN8855_CCR_TX_OCT_CNT_GOOD_2 BIT(1) +#define AN8855_CCR_TX_OCT_CNT_BAD_2 BIT(0) +#define AN8855_CCR_MIB_ACTIVATE (AN8855_CCR_MIB_ENABLE | \ + AN8855_CCR_RX_OCT_CNT_GOOD | \ + AN8855_CCR_RX_OCT_CNT_BAD | \ + AN8855_CCR_TX_OCT_CNT_GOOD | \ + AN8855_CCR_TX_OCT_CNT_BAD | \ + AN8855_CCR_RX_OCT_CNT_BAD_2 | \ + AN8855_CCR_TX_OCT_CNT_BAD_2) +#define AN8855_MIB_CLR 0x10213e34 +#define AN8855_MIB_PORT6_CLR BIT(6) +#define AN8855_MIB_PORT5_CLR BIT(5) +#define AN8855_MIB_PORT4_CLR BIT(4) +#define AN8855_MIB_PORT3_CLR BIT(3) +#define AN8855_MIB_PORT2_CLR BIT(2) +#define AN8855_MIB_PORT1_CLR BIT(1) +#define AN8855_MIB_PORT0_CLR BIT(0) + +/* HSGMII/SGMII Configuration register */ +/* AN8855_HSGMII_AN_CSR_BASE 0x10220000 */ +#define AN8855_SGMII_REG_AN0 0x10220000 +/* AN8855_SGMII_AN_ENABLE BMCR_ANENABLE */ +/* AN8855_SGMII_AN_RESTART BMCR_ANRESTART */ +#define AN8855_SGMII_REG_AN_13 0x10220034 +#define AN8855_SGMII_REMOTE_FAULT_DIS BIT(8) +#define AN8855_SGMII_IF_MODE GENMASK(5, 0) +#define AN8855_SGMII_REG_AN_FORCE_CL37 0x10220060 +#define AN8855_RG_FORCE_AN_DONE BIT(0) + +/* AN8855_HSGMII_CSR_PCS_BASE 0x10220000 */ +#define AN8855_RG_HSGMII_PCS_CTROL_1 0x10220a00 +#define AN8855_RG_TBI_10B_MODE BIT(30) +#define AN8855_RG_AN_SGMII_MODE_FORCE 0x10220a24 +#define AN8855_RG_FORCE_CUR_SGMII_MODE GENMASK(5, 4) +#define AN8855_RG_FORCE_CUR_SGMII_SEL BIT(0) + +/* AN8855_MULTI_SGMII_CSR_BASE 0x10224000 */ +#define AN8855_SGMII_STS_CTRL_0 0x10224018 +#define AN8855_RG_LINK_MODE_P0 GENMASK(5, 4) +#define AN8855_RG_LINK_MODE_P0_SPEED_2500 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x3) +#define AN8855_RG_LINK_MODE_P0_SPEED_1000 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x2) +#define AN8855_RG_LINK_MODE_P0_SPEED_100 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x1) +#define AN8855_RG_LINK_MODE_P0_SPEED_10 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x0) +#define AN8855_RG_FORCE_SPD_MODE_P0 BIT(2) +#define AN8855_MSG_RX_CTRL_0 0x10224100 +#define AN8855_MSG_RX_LIK_STS_0 0x10224514 +#define AN8855_RG_DPX_STS_P3 BIT(24) +#define AN8855_RG_DPX_STS_P2 BIT(16) +#define AN8855_RG_EEE1G_STS_P1 BIT(12) +#define AN8855_RG_DPX_STS_P1 BIT(8) +#define AN8855_RG_TXFC_STS_P0 BIT(2) +#define AN8855_RG_RXFC_STS_P0 BIT(1) +#define AN8855_RG_DPX_STS_P0 BIT(0) +#define AN8855_MSG_RX_LIK_STS_2 0x1022451c +#define AN8855_RG_RXFC_AN_BYPASS_P3 BIT(11) +#define AN8855_RG_RXFC_AN_BYPASS_P2 BIT(10) +#define AN8855_RG_RXFC_AN_BYPASS_P1 BIT(9) +#define AN8855_RG_TXFC_AN_BYPASS_P3 BIT(7) +#define AN8855_RG_TXFC_AN_BYPASS_P2 BIT(6) +#define AN8855_RG_TXFC_AN_BYPASS_P1 BIT(5) +#define AN8855_RG_DPX_AN_BYPASS_P3 BIT(3) +#define AN8855_RG_DPX_AN_BYPASS_P2 BIT(2) +#define AN8855_RG_DPX_AN_BYPASS_P1 BIT(1) +#define AN8855_RG_DPX_AN_BYPASS_P0 BIT(0) +#define AN8855_PHY_RX_FORCE_CTRL_0 0x10224520 +#define AN8855_RG_FORCE_TXC_SEL BIT(4) + +/* AN8855_XFI_CSR_PCS_BASE 0x10225000 */ +#define AN8855_RG_USXGMII_AN_CONTROL_0 0x10225bf8 + +/* AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 */ +#define AN8855_RG_RATE_ADAPT_CTRL_0 0x10226000 +#define AN8855_RG_RATE_ADAPT_RX_BYPASS BIT(27) +#define AN8855_RG_RATE_ADAPT_TX_BYPASS BIT(26) +#define AN8855_RG_RATE_ADAPT_RX_EN BIT(4) +#define AN8855_RG_RATE_ADAPT_TX_EN BIT(0) +#define AN8855_RATE_ADP_P0_CTRL_0 0x10226100 +#define AN8855_RG_P0_DIS_MII_MODE BIT(31) +#define AN8855_RG_P0_MII_MODE BIT(28) +#define AN8855_RG_P0_MII_RA_RX_EN BIT(3) +#define AN8855_RG_P0_MII_RA_TX_EN BIT(2) +#define AN8855_RG_P0_MII_RA_RX_MODE BIT(1) +#define AN8855_RG_P0_MII_RA_TX_MODE BIT(0) +#define AN8855_MII_RA_AN_ENABLE 0x10226300 +#define AN8855_RG_P0_RA_AN_EN BIT(0) + +/* AN8855_QP_DIG_CSR_BASE 0x1022a000 */ +#define AN8855_QP_CK_RST_CTRL_4 0x1022a310 +#define AN8855_QP_DIG_MODE_CTRL_0 0x1022a324 +#define AN8855_RG_SGMII_MODE GENMASK(5, 4) +#define AN8855_RG_SGMII_AN_EN BIT(0) +#define AN8855_QP_DIG_MODE_CTRL_1 0x1022a330 +#define AN8855_RG_TPHY_SPEED GENMASK(3, 2) + +/* AN8855_SERDES_WRAPPER_BASE 0x1022c000 */ +#define AN8855_USGMII_CTRL_0 0x1022c000 + +/* AN8855_QP_PMA_TOP_BASE 0x1022e000 */ +#define AN8855_PON_RXFEDIG_CTRL_0 0x1022e100 +#define AN8855_RG_QP_EQ_RX500M_CK_SEL BIT(12) +#define AN8855_PON_RXFEDIG_CTRL_9 0x1022e124 +#define AN8855_RG_QP_EQ_LEQOSC_DLYCNT GENMASK(2, 0) + +#define AN8855_SS_LCPLL_PWCTL_SETTING_2 0x1022e208 +#define AN8855_RG_NCPO_ANA_MSB GENMASK(17, 16) +#define AN8855_SS_LCPLL_TDC_FLT_2 0x1022e230 +#define AN8855_RG_LCPLL_NCPO_VALUE GENMASK(30, 0) +#define AN8855_SS_LCPLL_TDC_FLT_5 0x1022e23c +#define AN8855_RG_LCPLL_NCPO_CHG BIT(24) +#define AN8855_SS_LCPLL_TDC_PCW_1 0x1022e248 +#define AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0) +#define AN8855_INTF_CTRL_8 0x1022e320 +#define AN8855_INTF_CTRL_9 0x1022e324 +#define AN8855_INTF_CTRL_10 0x1022e328 +#define AN8855_RG_DA_QP_TX_FIR_C2_SEL BIT(29) +#define AN8855_RG_DA_QP_TX_FIR_C2_FORCE GENMASK(28, 24) +#define AN8855_RG_DA_QP_TX_FIR_C1_SEL BIT(21) +#define AN8855_RG_DA_QP_TX_FIR_C1_FORCE GENMASK(20, 16) +#define AN8855_INTF_CTRL_11 0x1022e32c +#define AN8855_RG_DA_QP_TX_FIR_C0B_SEL BIT(6) +#define AN8855_RG_DA_QP_TX_FIR_C0B_FORCE GENMASK(5, 0) +#define AN8855_PLL_CTRL_0 0x1022e400 +#define AN8855_RG_PHYA_AUTO_INIT BIT(0) +#define AN8855_PLL_CTRL_2 0x1022e408 +#define AN8855_RG_DA_QP_PLL_SDM_IFM_INTF BIT(30) +#define AN8855_RG_DA_QP_PLL_RICO_SEL_INTF BIT(29) +#define AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF BIT(28) +#define AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF BIT(27) +#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF BIT(26) +#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF GENMASK(25, 24) +#define AN8855_RG_DA_QP_PLL_PCK_SEL_INTF BIT(22) +#define AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20) +#define AN8855_RG_DA_QP_PLL_IR_INTF GENMASK(19, 16) +#define AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF BIT(14) +#define AN8855_RG_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12) +#define AN8855_RG_DA_QP_PLL_BR_INTF GENMASK(10, 8) +#define AN8855_RG_DA_QP_PLL_BPD_INTF GENMASK(7, 6) +#define AN8855_RG_DA_QP_PLL_BPA_INTF GENMASK(4, 2) +#define AN8855_RG_DA_QP_PLL_BC_INTF GENMASK(1, 0) +#define AN8855_PLL_CTRL_3 0x1022e40c +#define AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16) +#define AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0) +#define AN8855_PLL_CTRL_4 0x1022e410 +#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3) +#define AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF BIT(2) +#define AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF GENMASK(1, 0) +#define AN8855_PLL_CK_CTRL_0 0x1022e414 +#define AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF BIT(9) +#define AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF BIT(8) +#define AN8855_RX_DLY_0 0x1022e614 +#define AN8855_RG_QP_RX_SAOSC_EN_H_DLY GENMASK(13, 8) +#define AN8855_RG_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0) +#define AN8855_RX_CTRL_2 0x1022e630 +#define AN8855_RG_QP_RX_EQ_EN_H_DLY GENMASK(28, 16) +#define AN8855_RX_CTRL_5 0x1022e63c +#define AN8855_RG_FREDET_CHK_CYCLE GENMASK(29, 10) +#define AN8855_RX_CTRL_6 0x1022e640 +#define AN8855_RG_FREDET_GOLDEN_CYCLE GENMASK(19, 0) +#define AN8855_RX_CTRL_7 0x1022e644 +#define AN8855_RG_FREDET_TOLERATE_CYCLE GENMASK(19, 0) +#define AN8855_RX_CTRL_8 0x1022e648 +#define AN8855_RG_DA_QP_SAOSC_DONE_TIME GENMASK(27, 16) +#define AN8855_RG_DA_QP_LEQOS_EN_TIME GENMASK(14, 0) +#define AN8855_RX_CTRL_26 0x1022e690 +#define AN8855_RG_QP_EQ_RETRAIN_ONLY_EN BIT(26) +#define AN8855_RG_LINK_NE_EN BIT(24) +#define AN8855_RG_LINK_ERRO_EN BIT(23) +#define AN8855_RX_CTRL_42 0x1022e6d0 +#define AN8855_RG_QP_EQ_EN_DLY GENMASK(12, 0) + +/* AN8855_QP_ANA_CSR_BASE 0x1022f000 */ +#define AN8855_RG_QP_RX_DAC_EN 0x1022f000 +#define AN8855_RG_QP_SIGDET_HF GENMASK(17, 16) +#define AN8855_RG_QP_RXAFE_RESERVE 0x1022f004 +#define AN8855_RG_QP_CDR_PD_10B_EN BIT(11) +#define AN8855_RG_QP_CDR_LPF_BOT_LIM 0x1022f008 +#define AN8855_RG_QP_CDR_LPF_KP_GAIN GENMASK(26, 24) +#define AN8855_RG_QP_CDR_LPF_KI_GAIN GENMASK(22, 20) +#define AN8855_RG_QP_CDR_LPF_MJV_LIM 0x1022f00c +#define AN8855_RG_QP_CDR_LPF_RATIO GENMASK(5, 4) +#define AN8855_RG_QP_CDR_LPF_SETVALUE 0x1022f014 +#define AN8855_RG_QP_CDR_PR_BUF_IN_SR GENMASK(31, 29) +#define AN8855_RG_QP_CDR_PR_BETA_SEL GENMASK(28, 25) +#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 0x1022f018 +#define AN8855_RG_QP_CDR_PR_KBAND_DIV GENMASK(26, 24) +#define AN8855_RG_QP_CDR_PR_DAC_BAND GENMASK(12, 8) +#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE 0x1022f01c +#define AN8855_RG_QP_CDR_PR_XFICK_EN BIT(30) +#define AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE BIT(6) +#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK GENMASK(5, 0) +#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x1022f020 +#define AN8855_RG_QP_CDR_PHYCK_SEL GENMASK(17, 16) +#define AN8855_RG_QP_CDR_PHYCK_RSTB BIT(13) +#define AN8855_RG_QP_CDR_PHYCK_DIV GENMASK(12, 6) +#define AN8855_RG_QP_TX_MODE 0x1022f028 +#define AN8855_RG_QP_TX_RESERVE GENMASK(31, 16) +#define AN8855_RG_QP_TX_MODE_16B_EN BIT(0) +#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL 0x1022f03c +#define AN8855_RG_QP_PLL_SDM_ORD 0x1022f040 +#define AN8855_RG_QP_PLL_SSC_PHASE_INI BIT(4) +#define AN8855_RG_QP_PLL_SSC_TRI_EN BIT(3) + +/* AN8855_ETHER_SYS_BASE 0x1028c800 */ +#define AN8855_RG_GPHY_AFE_PWD 0x1028c840 +#define AN8855_RG_GPHY_SMI_ADDR 0x1028c848 + +#define MIB_DESC(_s, _o, _n) \ + { \ + .size = (_s), \ + .offset = (_o), \ + .name = (_n), \ + } + +struct an8855_mib_desc { + unsigned int size; + unsigned int offset; + const char *name; +}; + +struct an8855_fdb { + u16 vid; + u8 port_mask; + u16 aging; + u8 mac[6]; + bool noarp; + u8 live; + u8 type; + u8 fid; + u8 ivl; +}; + +struct an8855_priv { + struct device *dev; + struct dsa_switch *ds; + struct regmap *regmap; + struct gpio_desc *reset_gpio; + /* Protect ATU or VLAN table access */ + struct mutex reg_mutex; + + struct phylink_pcs pcs; + + u8 mirror_rx; + u8 mirror_tx; + u8 port_isolated_map; + + bool phy_require_calib; +}; + +#endif /* __AN8855_H */ diff --git a/target/linux/mediatek/files-6.12/drivers/net/mdio/mdio-an8855.c b/target/linux/mediatek/files-6.12/drivers/net/mdio/mdio-an8855.c new file mode 100644 index 0000000000..5feba72c02 --- /dev/null +++ b/target/linux/mediatek/files-6.12/drivers/net/mdio/mdio-an8855.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MDIO passthrough driver for Airoha AN8855 Switch + */ + +#include +#include +#include +#include + +static int an855_phy_restore_page(struct an8855_mfd_priv *priv, + int phy) __must_hold(&priv->bus->mdio_lock) +{ + /* Check PHY page only for addr shared with switch */ + if (phy != priv->switch_addr) + return 0; + + /* Don't restore page if it's not set to switch page */ + if (priv->current_page != FIELD_GET(AN8855_PHY_PAGE, + AN8855_PHY_PAGE_EXTENDED_4)) + return 0; + + /* Restore page to 0, PHY might change page right after but that + * will be ignored as it won't be a switch page. + */ + return an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD); +} + +static int an8855_phy_read(struct mii_bus *bus, int phy, int regnum) +{ + struct an8855_mfd_priv *priv = bus->priv; + struct mii_bus *real_bus = priv->bus; + int ret; + + mutex_lock_nested(&real_bus->mdio_lock, MDIO_MUTEX_NESTED); + + ret = an855_phy_restore_page(priv, phy); + if (ret) + goto exit; + + ret = __mdiobus_read(real_bus, phy, regnum); +exit: + mutex_unlock(&real_bus->mdio_lock); + + return ret; +} + +static int an8855_phy_write(struct mii_bus *bus, int phy, int regnum, u16 val) +{ + struct an8855_mfd_priv *priv = bus->priv; + struct mii_bus *real_bus = priv->bus; + int ret; + + mutex_lock_nested(&real_bus->mdio_lock, MDIO_MUTEX_NESTED); + + ret = an855_phy_restore_page(priv, phy); + if (ret) + goto exit; + + ret = __mdiobus_write(real_bus, phy, regnum, val); +exit: + mutex_unlock(&real_bus->mdio_lock); + + return ret; +} + +static int an8855_mdio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct an8855_mfd_priv *priv; + struct mii_bus *bus; + int ret; + + /* Get priv of MFD */ + priv = dev_get_drvdata(dev->parent); + + bus = devm_mdiobus_alloc(dev); + if (!bus) + return -ENOMEM; + + bus->priv = priv; + bus->name = KBUILD_MODNAME "-mii"; + snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", + priv->switch_addr); + bus->parent = dev; + bus->read = an8855_phy_read; + bus->write = an8855_phy_write; + + ret = devm_of_mdiobus_register(dev, bus, dev->of_node); + if (ret) + return dev_err_probe(dev, ret, "failed to register MDIO bus\n"); + + return ret; +} + +static const struct of_device_id an8855_mdio_of_match[] = { + { .compatible = "airoha,an8855-mdio", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, an8855_mdio_of_match); + +static struct platform_driver an8855_mdio_driver = { + .probe = an8855_mdio_probe, + .driver = { + .name = "an8855-mdio", + .of_match_table = an8855_mdio_of_match, + }, +}; +module_platform_driver(an8855_mdio_driver); + +MODULE_AUTHOR("Christian Marangi "); +MODULE_DESCRIPTION("Driver for AN8855 MDIO passthrough"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c b/target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c new file mode 100644 index 0000000000..7fab0854ef --- /dev/null +++ b/target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Christian Marangi + */ + +#include +#include +#include +#include + +#define AN8855_PHY_SELECT_PAGE 0x1f +#define AN8855_PHY_PAGE GENMASK(2, 0) +#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0) +#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1) + +/* MII Registers Page 1 */ +#define AN8855_PHY_EXT_REG_14 0x14 +#define AN8855_PHY_EN_DOWN_SHIFT BIT(4) + +/* R50 Calibration regs in MDIO_MMD_VEND1 */ +#define AN8855_PHY_R500HM_RSEL_TX_AB 0x174 +#define AN8855_PHY_R50OHM_RSEL_TX_A_EN BIT(15) +#define AN8855_PHY_R50OHM_RSEL_TX_A GENMASK(14, 8) +#define AN8855_PHY_R50OHM_RSEL_TX_B_EN BIT(7) +#define AN8855_PHY_R50OHM_RSEL_TX_B GENMASK(6, 0) +#define AN8855_PHY_R500HM_RSEL_TX_CD 0x175 +#define AN8855_PHY_R50OHM_RSEL_TX_C_EN BIT(15) +#define AN8855_PHY_R50OHM_RSEL_TX_C GENMASK(14, 8) +#define AN8855_PHY_R50OHM_RSEL_TX_D_EN BIT(7) +#define AN8855_PHY_R50OHM_RSEL_TX_D GENMASK(6, 0) + +#define AN8855_SWITCH_EFUSE_R50O GENMASK(30, 24) + +/* PHY TX PAIR DELAY SELECT Register */ +#define AN8855_PHY_TX_PAIR_DLY_SEL_GBE 0x013 +#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_A_GBE GENMASK(14, 12) +#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_B_GBE GENMASK(10, 8) +#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_C_GBE GENMASK(6, 4) +#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_D_GBE GENMASK(2, 0) +/* PHY ADC Register */ +#define AN8855_PHY_RXADC_CTRL 0x0d8 +#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_A BIT(12) +#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_B BIT(8) +#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_C BIT(4) +#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_D BIT(0) +#define AN8855_PHY_RXADC_REV_0 0x0d9 +#define AN8855_PHY_RG_AD_RESERVE0_A GENMASK(15, 8) +#define AN8855_PHY_RG_AD_RESERVE0_B GENMASK(7, 0) +#define AN8855_PHY_RXADC_REV_1 0x0da +#define AN8855_PHY_RG_AD_RESERVE0_C GENMASK(15, 8) +#define AN8855_PHY_RG_AD_RESERVE0_D GENMASK(7, 0) + +#define AN8855_PHY_ID 0xc0ff0410 + +#define AN8855_PHY_FLAGS_EN_CALIBRATION BIT(0) + +struct air_an8855_priv { + u8 calibration_data[4]; +}; + +static const u8 dsa_r50ohm_table[] = { + 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, + 127, 127, 127, 127, 127, 127, 127, 126, 122, 117, + 112, 109, 104, 101, 97, 94, 90, 88, 84, 80, + 78, 74, 72, 68, 66, 64, 61, 58, 56, 53, + 51, 48, 47, 44, 42, 40, 38, 36, 34, 32, + 31, 28, 27, 24, 24, 22, 20, 18, 16, 16, + 14, 12, 11, 9 +}; + +static int en8855_get_r50ohm_val(struct device *dev, const char *calib_name, + u8 *dest) +{ + u32 shift_sel, val; + int ret; + int i; + + ret = nvmem_cell_read_u32(dev, calib_name, &val); + if (ret) + return ret; + + shift_sel = FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val); + for (i = 0; i < ARRAY_SIZE(dsa_r50ohm_table); i++) + if (dsa_r50ohm_table[i] == shift_sel) + break; + + if (i < 8 || i >= ARRAY_SIZE(dsa_r50ohm_table)) + *dest = dsa_r50ohm_table[25]; + else + *dest = dsa_r50ohm_table[i - 8]; + + return 0; +} + +static int an8855_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct device_node *node = dev->of_node; + struct air_an8855_priv *priv; + + /* If we don't have a node, skip calib */ + if (!node) + return 0; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + phydev->priv = priv; + + return 0; +} + +static int an8855_get_downshift(struct phy_device *phydev, u8 *data) +{ + int val; + + val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14); + if (val < 0) + return val; + + *data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT : + DOWNSHIFT_DEV_DISABLE; + + return 0; +} + +static int an8855_set_downshift(struct phy_device *phydev, u8 cnt) +{ + u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0; + + return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, + AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT, + ds); +} + +static int an8855_config_init(struct phy_device *phydev) +{ + struct air_an8855_priv *priv = phydev->priv; + struct device *dev = &phydev->mdio.dev; + int ret; + + /* Enable HW auto downshift */ + ret = an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT); + if (ret) + return ret; + + /* Apply calibration values, if needed. + * AN8855_PHY_FLAGS_EN_CALIBRATION signal this. + */ + if (priv && phydev->dev_flags & AN8855_PHY_FLAGS_EN_CALIBRATION) { + u8 *calibration_data = priv->calibration_data; + + ret = en8855_get_r50ohm_val(dev, "tx_a", &calibration_data[0]); + if (ret) + return ret; + + ret = en8855_get_r50ohm_val(dev, "tx_b", &calibration_data[1]); + if (ret) + return ret; + + ret = en8855_get_r50ohm_val(dev, "tx_c", &calibration_data[2]); + if (ret) + return ret; + + ret = en8855_get_r50ohm_val(dev, "tx_d", &calibration_data[3]); + if (ret) + return ret; + + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R500HM_RSEL_TX_AB, + AN8855_PHY_R50OHM_RSEL_TX_A | AN8855_PHY_R50OHM_RSEL_TX_B, + FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_A, calibration_data[0]) | + FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_B, calibration_data[1])); + if (ret) + return ret; + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R500HM_RSEL_TX_CD, + AN8855_PHY_R50OHM_RSEL_TX_C | AN8855_PHY_R50OHM_RSEL_TX_D, + FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_C, calibration_data[2]) | + FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_D, calibration_data[3])); + if (ret) + return ret; + } + + /* Apply values to reduce signal noise */ + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL_GBE, + FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_A_GBE, 0x4) | + FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_C_GBE, 0x4)); + if (ret) + return ret; + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_CTRL, + AN8855_PHY_RG_AD_SAMNPLE_PHSEL_A | + AN8855_PHY_RG_AD_SAMNPLE_PHSEL_C); + if (ret) + return ret; + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_0, + FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1)); + if (ret) + return ret; + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_1, + FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_C, 0x1)); + if (ret) + return ret; + + return 0; +} + +static int an8855_get_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, void *data) +{ + switch (tuna->id) { + case ETHTOOL_PHY_DOWNSHIFT: + return an8855_get_downshift(phydev, data); + default: + return -EOPNOTSUPP; + } +} + +static int an8855_set_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, const void *data) +{ + switch (tuna->id) { + case ETHTOOL_PHY_DOWNSHIFT: + return an8855_set_downshift(phydev, *(const u8 *)data); + default: + return -EOPNOTSUPP; + } +} + +static int an8855_read_page(struct phy_device *phydev) +{ + return __phy_read(phydev, AN8855_PHY_SELECT_PAGE); +} + +static int an8855_write_page(struct phy_device *phydev, int page) +{ + return __phy_write(phydev, AN8855_PHY_SELECT_PAGE, page); +} + +static struct phy_driver an8855_driver[] = { +{ + PHY_ID_MATCH_EXACT(AN8855_PHY_ID), + .name = "Airoha AN8855 internal PHY", + /* PHY_GBIT_FEATURES */ + .flags = PHY_IS_INTERNAL, + .probe = an8855_probe, + .config_init = an8855_config_init, + .soft_reset = genphy_soft_reset, + .get_tunable = an8855_get_tunable, + .set_tunable = an8855_set_tunable, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_page = an8855_read_page, + .write_page = an8855_write_page, +}, }; + +module_phy_driver(an8855_driver); + +static struct mdio_device_id __maybe_unused an8855_tbl[] = { + { PHY_ID_MATCH_EXACT(AN8855_PHY_ID) }, + { } +}; + +MODULE_DEVICE_TABLE(mdio, an8855_tbl); + +MODULE_DESCRIPTION("Airoha AN8855 PHY driver"); +MODULE_AUTHOR("Christian Marangi "); +MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.12/drivers/nvmem/an8855-efuse.c b/target/linux/mediatek/files-6.12/drivers/nvmem/an8855-efuse.c new file mode 100644 index 0000000000..7940453d6e --- /dev/null +++ b/target/linux/mediatek/files-6.12/drivers/nvmem/an8855-efuse.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Airoha AN8855 Switch EFUSE Driver + */ + +#include +#include +#include +#include +#include + +#define AN8855_EFUSE_CELL 50 + +#define AN8855_EFUSE_DATA0 0x1000a500 +#define AN8855_EFUSE_R50O GENMASK(30, 24) + +static int an8855_efuse_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct regmap *regmap = context; + + return regmap_bulk_read(regmap, AN8855_EFUSE_DATA0 + offset, + val, bytes / sizeof(u32)); +} + +static int an8855_efuse_probe(struct platform_device *pdev) +{ + struct nvmem_config an8855_nvmem_config = { + .name = "an8855-efuse", + .size = AN8855_EFUSE_CELL * sizeof(u32), + .stride = sizeof(u32), + .word_size = sizeof(u32), + .reg_read = an8855_efuse_read, + }; + struct device *dev = &pdev->dev; + struct nvmem_device *nvmem; + + /* Assign NVMEM priv to MFD regmap */ + an8855_nvmem_config.priv = dev_get_regmap(dev->parent, NULL); + an8855_nvmem_config.dev = dev; + nvmem = devm_nvmem_register(dev, &an8855_nvmem_config); + + return PTR_ERR_OR_ZERO(nvmem); +} + +static const struct of_device_id an8855_efuse_of_match[] = { + { .compatible = "airoha,an8855-efuse", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, an8855_efuse_of_match); + +static struct platform_driver an8855_efuse_driver = { + .probe = an8855_efuse_probe, + .driver = { + .name = "an8855-efuse", + .of_match_table = an8855_efuse_of_match, + }, +}; +module_platform_driver(an8855_efuse_driver); + +MODULE_AUTHOR("Christian Marangi "); +MODULE_DESCRIPTION("Driver for AN8855 Switch EFUSE"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.12/include/linux/mfd/airoha-an8855-mfd.h b/target/linux/mediatek/files-6.12/include/linux/mfd/airoha-an8855-mfd.h new file mode 100644 index 0000000000..56061566a0 --- /dev/null +++ b/target/linux/mediatek/files-6.12/include/linux/mfd/airoha-an8855-mfd.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * MFD driver for Airoha AN8855 Switch + */ +#ifndef _LINUX_INCLUDE_MFD_AIROHA_AN8855_MFD_H +#define _LINUX_INCLUDE_MFD_AIROHA_AN8855_MFD_H + +#include + +/* MII Registers */ +#define AN8855_PHY_SELECT_PAGE 0x1f +#define AN8855_PHY_PAGE GENMASK(2, 0) +#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0) +#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1) +#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4) + +/* MII Registers Page 4 */ +#define AN8855_PBUS_MODE 0x10 +#define AN8855_PBUS_MODE_ADDR_FIXED 0x0 +#define AN8855_PBUS_MODE_ADDR_INCR BIT(15) +#define AN8855_PBUS_WR_ADDR_HIGH 0x11 +#define AN8855_PBUS_WR_ADDR_LOW 0x12 +#define AN8855_PBUS_WR_DATA_HIGH 0x13 +#define AN8855_PBUS_WR_DATA_LOW 0x14 +#define AN8855_PBUS_RD_ADDR_HIGH 0x15 +#define AN8855_PBUS_RD_ADDR_LOW 0x16 +#define AN8855_PBUS_RD_DATA_HIGH 0x17 +#define AN8855_PBUS_RD_DATA_LOW 0x18 + +struct an8855_mfd_priv { + struct device *dev; + struct mii_bus *bus; + + unsigned int switch_addr; + u16 current_page; +}; + +int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id, + u8 page); + +#endif diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts index 791b56113a..6fca59d3ef 100644 --- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts +++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include "mt7981.dtsi" +#include "mt7981b.dtsi" / { model = "MediaTek MT7981 RFB"; diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981b.dtsi similarity index 100% rename from target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981.dtsi rename to target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981b.dtsi diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi index 8dba5b4275..a1ff582961 100644 --- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi @@ -23,11 +23,11 @@ led-failsafe = &led_green; led-running = &led_green; led-upgrade = &led_green; - serial0 = &uart0; + serial0 = &serial0; }; chosen { - stdout-path = &uart0; + stdout-path = &serial0; bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait"; rootdisk-spim-nand = <&ubi_rootfs>; }; @@ -75,6 +75,24 @@ default-state = "off"; }; }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; ð { @@ -108,6 +126,7 @@ &gsw_phy0_led0 { status = "okay"; + function = LED_FUNCTION_WAN; color = ; }; @@ -116,8 +135,13 @@ pinctrl-0 = <&gbe1_led0_pins>; }; +&gsw_port1 { + label = "lan1"; +}; + &gsw_phy1_led0 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; @@ -126,8 +150,13 @@ pinctrl-0 = <&gbe2_led0_pins>; }; +&gsw_port2 { + label = "lan2"; +}; + &gsw_phy2_led0 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; @@ -136,8 +165,13 @@ pinctrl-0 = <&gbe3_led0_pins>; }; +&gsw_port3 { + label = "lan3"; +}; + &gsw_phy3_led0 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; @@ -299,23 +333,180 @@ }; &pio { + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio0"; + }; + + conf { + groups = "mdc_mdio0"; + drive-strength = ; + }; + }; + + i2c0_pins: i2c0-pins-g0 { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; + + i2c2_1_pins: i2c2-pins-g1 { + mux { + function = "i2c"; + groups = "i2c2_1"; + }; + }; + + gbe0_led0_pins: gbe0-led0-pins { + mux { + function = "led"; + groups = "gbe0_led0"; + }; + }; + + gbe1_led0_pins: gbe1-led0-pins { + mux { + function = "led"; + groups = "gbe1_led0"; + }; + }; + + gbe2_led0_pins: gbe2-led0-pins { + mux { + function = "led"; + groups = "gbe2_led0"; + }; + }; + + gbe3_led0_pins: gbe3-led0-pins { + mux { + function = "led"; + groups = "gbe3_led0"; + }; + }; + + i2p5gbe_led0_pins: 2p5gbe-led0-pins { + mux { + function = "led"; + groups = "2p5gbe_led0"; + }; + }; + + mmc0_pins_emmc_51: mmc0-pins-emmc-51 { + mux { + function = "flash"; + groups = "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-pins-sdcard { + mux { + function = "flash"; + groups = "sdcard"; + }; + }; + pwm0_pins: pwm0-pins { mux { groups = "pwm0"; function = "pwm"; }; }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; + + uart1_2_lite_pins: uart1-2-lite-pins { + mux { + function = "uart"; + groups = "uart1_2_lite"; + }; + }; + + uart2_3_pins: uart2-3-pins { + mux { + function = "uart"; + groups = "uart2_3"; + }; + }; + + spi0_flash_pins: spi0-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; + pwms = <&pwm 0 50000>; + /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */ + cooling-levels = <0 80 128 255>; + #cooling-cells = <2>; + #thermal-sensor-cells = <1>; + + status = "okay"; + }; }; &pwm { status = "okay"; }; -&fan { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - pwms = <&pwm 0 50000>; - status = "okay"; +&cpu_thermal { + trips { + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_med: active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_med>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + }; }; &ssusb1 { @@ -380,17 +571,19 @@ }; }; -&uart0 { +&serial0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; status = "okay"; }; -&uart1 { +&serial1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart1_2_lite_pins>; }; -&uart2 { +&serial2 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart2_3_pins>; @@ -400,6 +593,6 @@ status = "okay"; }; -&xphy { +&xsphy { status = "okay"; }; diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts index 5012e7a498..a2a45f801c 100644 --- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts +++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts @@ -24,6 +24,136 @@ memory { reg = <0 0x40000000 0 0x40000000>; }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&pio { + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio0"; + }; + + conf { + groups = "mdc_mdio0"; + drive-strength = ; + }; + }; + + gbe0_led0_pins: gbe0-led0-pins { + mux { + function = "led"; + groups = "gbe0_led0"; + }; + }; + + gbe1_led0_pins: gbe1-led0-pins { + mux { + function = "led"; + groups = "gbe1_led0"; + }; + }; + + gbe2_led0_pins: gbe2-led0-pins { + mux { + function = "led"; + groups = "gbe2_led0"; + }; + }; + + gbe3_led0_pins: gbe3-led0-pins { + mux { + function = "led"; + groups = "gbe3_led0"; + }; + }; + + i2c1_sfp_pins: i2c1-sfp-pins-g0 { + mux { + function = "i2c"; + groups = "i2c1_sfp"; + }; + }; + + i2c2_0_pins: i2c2-pins-g0 { + mux { + function = "i2c"; + groups = "i2c2_0"; + }; + }; + + i2c0_pins: i2c0-pins-g0 { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; + + i2c1_pins: i2c1-pins-g0 { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + + i2p5gbe_led0_pins: 2p5gbe-led0-pins { + mux { + function = "led"; + groups = "2p5gbe_led0"; + }; + }; + + mmc0_pins_emmc_51: mmc0-pins-emmc-51 { + mux { + function = "flash"; + groups = "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-pins-sdcard { + mux { + function = "flash"; + groups = "sdcard"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; + + spi0_flash_pins: spi0-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spi1_pins: spi1-pins { + mux { + function = "spi"; + groups = "spi1"; + }; + }; }; ð { @@ -68,8 +198,13 @@ pinctrl-0 = <&gbe0_led0_pins>; }; +&gsw_port0 { + label = "lan0"; +}; + &gsw_phy0_led0 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; @@ -78,8 +213,13 @@ pinctrl-0 = <&gbe1_led0_pins>; }; +&gsw_port1 { + label = "lan1"; +}; + &gsw_phy1_led0 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; @@ -88,8 +228,13 @@ pinctrl-0 = <&gbe2_led0_pins>; }; +&gsw_port2 { + label = "lan2"; +}; + &gsw_phy2_led0 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; @@ -98,8 +243,13 @@ pinctrl-0 = <&gbe3_led0_pins>; }; +&gsw_port3 { + label = "lan3"; +}; + &gsw_phy3_led0 { status = "okay"; + function = LED_FUNCTION_LAN; color = ; }; @@ -187,7 +337,9 @@ status = "okay"; }; -&uart0 { +&serial0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; status = "okay"; }; @@ -195,6 +347,6 @@ status = "okay"; }; -&xphy { +&xsphy { status = "okay"; }; diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 39f8fd2ab1..6d8953c873 100644 --- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -147,15 +147,6 @@ clock-output-names = "clkxtal"; }; - fan: pwm-fan { - compatible = "pwm-fan"; - /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */ - cooling-levels = <0 80 128 255>; - #cooling-cells = <2>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - pmu { compatible = "arm,cortex-a73-pmu"; interrupt-parent = <&gic>; @@ -167,24 +158,6 @@ method = "smc"; }; - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - reserved-memory { ranges; #address-cells = <2>; @@ -296,263 +269,6 @@ interrupt-parent = <&gic>; #interrupt-cells = <2>; - mdio0_pins: mdio0-pins { - mux { - function = "eth"; - groups = "mdc_mdio0"; - }; - - conf { - groups = "mdc_mdio0"; - drive-strength = ; - }; - }; - - i2c0_pins: i2c0-pins-g0 { - mux { - function = "i2c"; - groups = "i2c0_1"; - }; - }; - - i2c1_pins: i2c1-pins-g0 { - mux { - function = "i2c"; - groups = "i2c1_0"; - }; - }; - - i2c1_sfp_pins: i2c1-sfp-pins-g0 { - mux { - function = "i2c"; - groups = "i2c1_sfp"; - }; - }; - - i2c2_pins: i2c2-pins { - mux { - function = "i2c"; - groups = "i2c2"; - }; - }; - - i2c2_0_pins: i2c2-pins-g0 { - mux { - function = "i2c"; - groups = "i2c2_0"; - }; - }; - - i2c2_1_pins: i2c2-pins-g1 { - mux { - function = "i2c"; - groups = "i2c2_1"; - }; - }; - - gbe0_led0_pins: gbe0-led0-pins { - mux { - function = "led"; - groups = "gbe0_led0"; - }; - }; - - gbe1_led0_pins: gbe1-led0-pins { - mux { - function = "led"; - groups = "gbe1_led0"; - }; - }; - - gbe2_led0_pins: gbe2-led0-pins { - mux { - function = "led"; - groups = "gbe2_led0"; - }; - }; - - gbe3_led0_pins: gbe3-led0-pins { - mux { - function = "led"; - groups = "gbe3_led0"; - }; - }; - - gbe0_led1_pins: gbe0-led1-pins { - mux { - function = "led"; - groups = "gbe0_led1"; - }; - }; - - gbe1_led1_pins: gbe1-led1-pins { - mux { - function = "led"; - groups = "gbe1_led1"; - }; - }; - - gbe2_led1_pins: gbe2-led1-pins { - mux { - function = "led"; - groups = "gbe2_led1"; - }; - }; - - gbe3_led1_pins: gbe3-led1-pins { - mux { - function = "led"; - groups = "gbe3_led1"; - }; - }; - - i2p5gbe_led0_pins: 2p5gbe-led0-pins { - mux { - function = "led"; - groups = "2p5gbe_led0"; - }; - }; - - i2p5gbe_led1_pins: 2p5gbe-led1-pins { - mux { - function = "led"; - groups = "2p5gbe_led1"; - }; - }; - - mmc0_pins_emmc_45: mmc0-pins-emmc-45 { - mux { - function = "flash"; - groups = "emmc_45"; - }; - }; - - mmc0_pins_emmc_51: mmc0-pins-emmc-51 { - mux { - function = "flash"; - groups = "emmc_51"; - }; - }; - - mmc0_pins_sdcard: mmc0-pins-sdcard { - mux { - function = "flash"; - groups = "sdcard"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0"; - }; - }; - - uart1_0_pins: uart1-0-pins { - mux { - function = "uart"; - groups = "uart1_0"; - }; - }; - - uart1_1_pins: uart1-1-pins { - mux { - function = "uart"; - groups = "uart1_1"; - }; - }; - - uart1_2_pins: uart1-2-pins { - mux { - function = "uart"; - groups = "uart1_2"; - }; - }; - - uart1_2_lite_pins: uart1-2-lite-pins { - mux { - function = "uart"; - groups = "uart1_2_lite"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2"; - }; - }; - - uart2_0_pins: uart2-0-pins { - mux { - function = "uart"; - groups = "uart2_0"; - }; - }; - - uart2_1_pins: uart2-1-pins { - mux { - function = "uart"; - groups = "uart2_1"; - }; - }; - - uart2_2_pins: uart2-2-pins { - mux { - function = "uart"; - groups = "uart2_2"; - }; - }; - - uart2_3_pins: uart2-3-pins { - mux { - function = "uart"; - groups = "uart2_3"; - }; - }; - - snfi_pins: snfi-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - spi0_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0"; - }; - }; - - spi0_flash_pins: spi0-flash-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; - - spi1_pins: spi1-pins { - mux { - function = "spi"; - groups = "spi1"; - }; - }; - - spi2_pins: spi2-pins { - mux { - function = "spi"; - groups = "spi2"; - }; - }; - - spi2_flash_pins: spi2-flash-pins { - mux { - function = "spi"; - groups = "spi2", "spi2_wp_hold"; - }; - }; - pcie0_pins: pcie0-pins { mux { function = "pcie"; @@ -584,6 +300,13 @@ "pcie_wake_n3_0"; }; }; + + snfi_pins: snfi-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; }; pwm: pwm@10048000 { @@ -661,7 +384,7 @@ #clock-cells = <1>; }; - uart0: serial@11000000 { + serial0: serial@11000000 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart"; reg = <0 0x11000000 0 0x100>; @@ -678,12 +401,10 @@ <&infracfg CLK_INFRA_MUX_UART0_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, <&topckgen CLK_TOP_UART_SEL>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; status = "disabled"; }; - uart1: serial@11000100 { + serial1: serial@11000100 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart"; reg = <0 0x11000100 0 0x100>; @@ -703,7 +424,7 @@ status = "disabled"; }; - uart2: serial@11000200 { + serial2: serial@11000200 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart"; reg = <0 0x11000200 0 0x100>; @@ -824,8 +545,6 @@ "hclk"; #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; status = "disabled"; }; @@ -1154,7 +873,7 @@ #size-cells = <0>; }; - xphy: xphy@11e10000 { + xsphy: xphy@11e10000 { compatible = "mediatek,mt7988", "mediatek,xsphy"; ranges; @@ -1303,28 +1022,24 @@ gsw_port0: port@0 { reg = <0>; - label = "lan0"; phy-mode = "internal"; phy-handle = <&gsw_phy0>; }; gsw_port1: port@1 { reg = <1>; - label = "lan1"; phy-mode = "internal"; phy-handle = <&gsw_phy1>; }; gsw_port2: port@2 { reg = <2>; - label = "lan2"; phy-mode = "internal"; phy-handle = <&gsw_phy2>; }; gsw_port3: port@3 { reg = <3>; - label = "lan3"; phy-mode = "internal"; phy-handle = <&gsw_phy3>; }; @@ -1361,13 +1076,11 @@ gsw_phy0_led0: gsw-phy0-led0@0 { reg = <0>; - function = LED_FUNCTION_LAN; status = "disabled"; }; gsw_phy0_led1: gsw-phy0-led1@1 { reg = <1>; - function = LED_FUNCTION_LAN; status = "disabled"; }; }; @@ -1387,13 +1100,11 @@ gsw_phy1_led0: gsw-phy1-led0@0 { reg = <0>; - function = LED_FUNCTION_LAN; status = "disabled"; }; gsw_phy1_led1: gsw-phy1-led1@1 { reg = <1>; - function = LED_FUNCTION_LAN; status = "disabled"; }; }; @@ -1413,13 +1124,11 @@ gsw_phy2_led0: gsw-phy2-led0@0 { reg = <0>; - function = LED_FUNCTION_LAN; status = "disabled"; }; gsw_phy2_led1: gsw-phy2-led1@1 { reg = <1>; - function = LED_FUNCTION_LAN; status = "disabled"; }; }; @@ -1439,13 +1148,11 @@ gsw_phy3_led0: gsw-phy3-led0@0 { reg = <0>; - function = LED_FUNCTION_LAN; status = "disabled"; }; gsw_phy3_led1: gsw-phy3-led1@1 { reg = <1>; - function = LED_FUNCTION_LAN; status = "disabled"; }; }; @@ -1670,50 +1377,6 @@ hysteresis = <2000>; type = "critical"; }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <40000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-low { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-passive { - /* passive: set fan to cooling level 0 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; }; }; }; diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h index 0a43c0dbd3..1c92188d6b 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h @@ -734,4 +734,8 @@ extern rtk_uint32 rtk_switch_maxLutAddrNumber_get(void); */ rtk_uint32 rtk_switch_isValidTrunkGrpId(rtk_uint32 grpId); +int gsw_debug_proc_init(void); +void gsw_debug_proc_exit(void); +int rtl8367s_swconfig_init(void (*reset_func)(void)); + #endif diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_mii_mgr.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_mii_mgr.h new file mode 100644 index 0000000000..816763fae1 --- /dev/null +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_mii_mgr.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * Unless you and Realtek execute a separate written software license + * agreement governing use of this software, this software is licensed + * to you under the terms of the GNU General Public License version 2, + * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt + * + * $Revision: 76333 $ + * $Date: 2017-03-09 09:33:15 +0800 (g|, 09 T 2017) $ + * + * Purpose : RTL8367C switch MII access + * Feature : MII access functions + * + */ + +#ifndef _RTL8367C_ASICDRV_MII_MGR_H_ +#define _RTL8367C_ASICDRV_MII_MGR_H_ + +#define u32 unsigned int +extern u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data); +extern u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data); + +#endif /*_RTL8367C_ASICDRV_MII_MGR_H_*/ + diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c index 20542f259f..afa3385f30 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c @@ -38,9 +38,7 @@ static init_state_t init_state = INIT_COMPLETED; static init_state_t init_state = INIT_NOT_COMPLETED; #endif -#define AUTO_PROBE (!defined(FORCE_PROBE_RTL8367C) && !defined(FORCE_PROBE_RTL8370B) && !defined(FORCE_PROBE_RTL8364B) && !defined(FORCE_PROBE_RTL8363SC_VB)) - -#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8367C)) +#if ((!defined(FORCE_PROBE_RTL8367C) && !defined(FORCE_PROBE_RTL8370B) && !defined(FORCE_PROBE_RTL8364B) && !defined(FORCE_PROBE_RTL8363SC_VB)) || defined(FORCE_PROBE_RTL8367C)) static rtk_switch_halCtrl_t rtl8367c_hal_Ctrl = { /* Switch Chip */ @@ -109,7 +107,7 @@ static rtk_switch_halCtrl_t rtl8367c_hal_Ctrl = }; #endif -#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8370B)) +#if ((!defined(FORCE_PROBE_RTL8367C) && !defined(FORCE_PROBE_RTL8370B) && !defined(FORCE_PROBE_RTL8364B) && !defined(FORCE_PROBE_RTL8363SC_VB)) || defined(FORCE_PROBE_RTL8370B)) static rtk_switch_halCtrl_t rtl8370b_hal_Ctrl = { /* Switch Chip */ @@ -178,7 +176,7 @@ static rtk_switch_halCtrl_t rtl8370b_hal_Ctrl = }; #endif -#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8364B)) +#if ((!defined(FORCE_PROBE_RTL8367C) && !defined(FORCE_PROBE_RTL8370B) && !defined(FORCE_PROBE_RTL8364B) && !defined(FORCE_PROBE_RTL8363SC_VB)) || defined(FORCE_PROBE_RTL8364B)) static rtk_switch_halCtrl_t rtl8364b_hal_Ctrl = { /* Switch Chip */ @@ -247,7 +245,7 @@ static rtk_switch_halCtrl_t rtl8364b_hal_Ctrl = }; #endif -#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8363SC_VB)) +#if ((!defined(FORCE_PROBE_RTL8367C) && !defined(FORCE_PROBE_RTL8370B) && !defined(FORCE_PROBE_RTL8364B) && !defined(FORCE_PROBE_RTL8363SC_VB)) || defined(FORCE_PROBE_RTL8363SC_VB)) static rtk_switch_halCtrl_t rtl8363sc_vb_hal_Ctrl = { /* Switch Chip */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c index 70e767f422..e707e4b9c5 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c @@ -15,6 +15,8 @@ #include #include +#include + #include "rtk_error.h" @@ -35,10 +37,6 @@ #define MDC_MDIO_WRITE(preamableLength, phyID, regID, data) #define MDC_MDIO_READ(preamableLength, phyID, regID, pData) #else -#define u32 unsigned int -extern u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data); -extern u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data); - #define MDC_MDIO_WRITE(preamableLength, phyID, regID, data) mii_mgr_write(phyID, regID, data) #define MDC_MDIO_READ(preamableLength, phyID, regID, pData) mii_mgr_read(phyID, regID, pData) #endif diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c index 52cd4de394..2f9dc0da6b 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c @@ -19,12 +19,14 @@ #include #include #include +#include #include "./rtl8367c/include/rtk_switch.h" #include "./rtl8367c/include/port.h" #include "./rtl8367c/include/vlan.h" #include "./rtl8367c/include/rtl8367c_asicdrv_port.h" +#include "./rtl8367c/include/rtl8367c_asicdrv_mii_mgr.h" struct rtk_gsw { struct device *dev; @@ -34,13 +36,6 @@ struct rtk_gsw { static struct rtk_gsw *_gsw; -extern int gsw_debug_proc_init(void); -extern void gsw_debug_proc_exit(void); - -#ifdef CONFIG_SWCONFIG -extern int rtl8367s_swconfig_init( void (*reset_func)(void) ); -#endif - /*mii_mgr_read/mii_mgr_write is the callback API for rtl8367 driver*/ unsigned int mii_mgr_read(unsigned int phy_addr,unsigned int phy_register,unsigned int *read_data) { @@ -204,7 +199,7 @@ static void set_rtl8367s_rgmii(void) } -void init_gsw(void) +static void init_gsw(void) { rtl8367s_hw_init(); set_rtl8367s_sgmii(); diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds index fcb05db271..e07bd9e67e 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds @@ -16,7 +16,8 @@ acer,predator-w6d) ucidef_set_led_netdev "internet" "INTERNET" "mdio-bus:06:amber:wan" "eth1" "link_10 link_100 link_1000 tx rx" ucidef_set_led_netdev "internet" "INTERNET" "mdio-bus:06:green:wan" "eth1" "link_2500 tx rx" ;; -asus,rt-ax52) +asus,rt-ax52|\ +snr,snr-cpe-ax2) ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" "link tx rx" ;; asus,tuf-ax4200) @@ -35,8 +36,9 @@ bananapi,bpi-r3-mini) ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan-2" "phy1-ap0" ;; bananapi,bpi-r4|\ +bananapi,bpi-r4-2g5|\ bananapi,bpi-r4-poe) - ucidef_set_led_netdev "wan" "wan" "mt7530-0:00:green:lan" "wan" "link tx rx" + ucidef_set_led_netdev "wan" "wan" "mt7530-0:00:green:wan" "wan" "link tx rx" ucidef_set_led_netdev "lan1" "lan1" "mt7530-0:01:green:lan" "lan1" "link tx rx" ucidef_set_led_netdev "lan2" "lan2" "mt7530-0:02:green:lan" "lan2" "link tx rx" ucidef_set_led_netdev "lan3" "lan3" "mt7530-0:03:green:lan" "lan3" "link tx rx" diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 60a35652f8..8d8cc30833 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -86,6 +86,7 @@ mediatek_setup_interfaces() bananapi,bpi-r4) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 sfp-lan" "wan sfp-wan" ;; + bananapi,bpi-r4-2g5|\ bananapi,bpi-r4-poe) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan sfp-wan" ;; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version b/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version index 46bfd299ee..3c56af753c 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version @@ -18,6 +18,7 @@ case "$(board_name)" in ucidef_set_compat_version "1.1" ;; bananapi,bpi-r4|\ + bananapi,bpi-r4-2g5|\ bananapi,bpi-r4-poe) ucidef_set_compat_version "1.1" ;; diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 684c4b06af..44ce77bb79 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -55,6 +55,7 @@ case "$board" in [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress ;; bananapi,bpi-r4|\ + bananapi,bpi-r4-2g5|\ bananapi,bpi-r4-poe) addr=$(cat /sys/class/net/eth0/address) [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 42498a4765..e1b0153482 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -71,6 +71,7 @@ platform_do_upgrade() { bananapi,bpi-r3|\ bananapi,bpi-r3-mini|\ bananapi,bpi-r4|\ + bananapi,bpi-r4-2g5|\ bananapi,bpi-r4-poe|\ cetron,ct3003-ubootmod|\ cmcc,a10-ubootmod|\ @@ -94,6 +95,7 @@ platform_do_upgrade() { netcore,n60-pro|\ qihoo,360t7|\ routerich,ax3000-ubootmod|\ + snr,snr-cpe-ax2|\ tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ tplink,tl-xdr6088|\ @@ -208,6 +210,7 @@ platform_check_image() { bananapi,bpi-r3|\ bananapi,bpi-r3-mini|\ bananapi,bpi-r4|\ + bananapi,bpi-r4-2g5|\ bananapi,bpi-r4-poe|\ cetron,ct3003-ubootmod|\ cmcc,a10-ubootmod|\ @@ -287,6 +290,7 @@ platform_copy_config() { bananapi,bpi-r3|\ bananapi,bpi-r3-mini|\ bananapi,bpi-r4|\ + bananapi,bpi-r4-2g5|\ bananapi,bpi-r4-poe|\ cmcc,rax3000m|\ cmcc,rax3000me) diff --git a/target/linux/mediatek/filogic/config-6.12 b/target/linux/mediatek/filogic/config-6.12 new file mode 100644 index 0000000000..6fa53b7b84 --- /dev/null +++ b/target/linux/mediatek/filogic/config-6.12 @@ -0,0 +1,532 @@ +CONFIG_64BIT=y +# CONFIG_AHCI_MTK is not set +CONFIG_AIROHA_EN8801SC_PHY=y +CONFIG_AIR_AN8855_PHY=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_FORCE_MAX_ORDER=10 +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PKEY_BITS=3 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_EXECMEM_LATE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PLATFORM_DEVICES=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_52 is not set +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=y +CONFIG_ARM_MEDIATEK_CPUFREQ=y +CONFIG_ARM_PMU=y +CONFIG_ARM_PMUV3=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ATA=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BLOCK_NOTIFIERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y +CONFIG_CC_HAVE_SHADOW_CALL_STACK=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE_OVERRIDE=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_MEDIATEK=y +# CONFIG_COMMON_CLK_MT2712 is not set +# CONFIG_COMMON_CLK_MT6779 is not set +# CONFIG_COMMON_CLK_MT6795 is not set +# CONFIG_COMMON_CLK_MT6797 is not set +# CONFIG_COMMON_CLK_MT7622 is not set +CONFIG_COMMON_CLK_MT7981=y +CONFIG_COMMON_CLK_MT7981_ETHSYS=y +CONFIG_COMMON_CLK_MT7986=y +CONFIG_COMMON_CLK_MT7986_ETHSYS=y +CONFIG_COMMON_CLK_MT7988=y +# CONFIG_COMMON_CLK_MT8173 is not set +# CONFIG_COMMON_CLK_MT8183 is not set +# CONFIG_COMMON_CLK_MT8186 is not set +# CONFIG_COMMON_CLK_MT8195 is not set +# CONFIG_COMMON_CLK_MT8365 is not set +# CONFIG_COMMON_CLK_MT8516 is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +# CONFIG_COMPAT_32BIT_TIME is not set +# CONFIG_COMPRESSED_INSTALL is not set +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRC16=y +CONFIG_CRC_CCITT=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA256_ARM64=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SM4=y +CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y +CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y +CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_MISC=y +CONFIG_DEVFREQ_GOV_PASSIVE=y +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DMADEVICES=y +CONFIG_DMATEST=y +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_OF=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EINT_MTK=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_F2FS_FS=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=4 +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_WATCHDOG=y +CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y +CONFIG_GRO_CELLS=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HISILICON_ERRATUM_162100801 is not set +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MTK=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MT65XX=y +CONFIG_ICPLUS_PHY=y +# CONFIG_IDPF is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_LIB=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_JUMP_LABEL=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SMARTRG_LED=y +CONFIG_LEDS_TRIGGER_PATTERN=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LRU_GEN_WALKS_MMU=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAXLINEAR_GPHY=y +CONFIG_MDIO_AN8855=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEDIATEK_2P5GE_PHY=y +CONFIG_MEDIATEK_GE_PHY=y +CONFIG_MEDIATEK_GE_SOC_PHY=y +CONFIG_MEDIATEK_WATCHDOG=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_MFD_AIROHA_AN8855=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CQHCI=y +CONFIG_MMC_MTK=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_MEDIATEK=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_MTK=y +CONFIG_MTD_NAND_MTK_BMT=y +CONFIG_MTD_PARSER_TRX=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_NVMEM=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_VIRT_CONCAT=y +# CONFIG_MTK_CMDQ is not set +CONFIG_MTK_CPUX_TIMER=y +# CONFIG_MTK_CQDMA is not set +CONFIG_MTK_HSDMA=y +CONFIG_MTK_INFRACFG=y +CONFIG_MTK_LVTS_THERMAL=y +CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y +CONFIG_MTK_NET_PHYLIB=y +CONFIG_MTK_PMIC_WRAP=y +CONFIG_MTK_REGULATOR_COUPLER=y +CONFIG_MTK_SCPSYS=y +CONFIG_MTK_SCPSYS_PM_DOMAINS=y +# CONFIG_MTK_SOCINFO is not set +CONFIG_MTK_SOC_THERMAL=y +# CONFIG_MTK_SVS is not set +CONFIG_MTK_THERMAL=y +CONFIG_MTK_TIMER=y +# CONFIG_MTK_UART_APDMA is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +# CONFIG_NET_AIROHA is not set +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_AN8855=y +CONFIG_NET_DSA_MT7530=y +CONFIG_NET_DSA_MT7530_MDIO=y +CONFIG_NET_DSA_MT7530_MMIO=y +CONFIG_NET_DSA_TAG_MTK=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_MEDIATEK_SOC=y +CONFIG_NET_MEDIATEK_SOC_WED=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_VENDOR_MEDIATEK=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_NVMEM=y +CONFIG_NVMEM_AN8855_EFUSE=y +CONFIG_NVMEM_BLOCK=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_ADTRAN=y +CONFIG_NVMEM_MTK_EFUSE=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_RESOLVE=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEFAULT is not set +CONFIG_PCIEASPM_PERFORMANCE=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIE_MEDIATEK is not set +CONFIG_PCIE_MEDIATEK_GEN3=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCS_MTK_LYNXI=y +CONFIG_PCS_MTK_USXGMII=y +CONFIG_PERF_EVENTS=y +CONFIG_PER_VMA_LOCK=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_MTK_DP is not set +# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set +# CONFIG_PHY_MTK_PCIE is not set +CONFIG_PHY_MTK_TPHY=y +# CONFIG_PHY_MTK_UFS is not set +CONFIG_PHY_MTK_XFI_TPHY=y +CONFIG_PHY_MTK_XSPHY=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_MT2712 is not set +# CONFIG_PINCTRL_MT6765 is not set +# CONFIG_PINCTRL_MT6795 is not set +# CONFIG_PINCTRL_MT6797 is not set +# CONFIG_PINCTRL_MT7622 is not set +CONFIG_PINCTRL_MT7981=y +CONFIG_PINCTRL_MT7986=y +CONFIG_PINCTRL_MT7988=y +# CONFIG_PINCTRL_MT8173 is not set +# CONFIG_PINCTRL_MT8183 is not set +# CONFIG_PINCTRL_MT8186 is not set +# CONFIG_PINCTRL_MT8188 is not set +# CONFIG_PINCTRL_MT8516 is not set +CONFIG_PINCTRL_MTK_MOORE=y +CONFIG_PINCTRL_MTK_V2=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_DEVFREQ=y +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_OPP=y +CONFIG_POLYNOMIAL=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_SUPPLY=y +CONFIG_PRINTK_TIME=y +CONFIG_PSTORE=y +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_MEDIATEK=y +# CONFIG_PWM_MTK_DISP is not set +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RAVE_SP_CORE is not set +CONFIG_REALTEK_PHY=y +CONFIG_REALTEK_PHY_HWMON=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MT6380=y +CONFIG_REGULATOR_RT5190A=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_TI_SYSCON=y +CONFIG_RFS_ACCEL=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MT7622=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTL8261N_PHY=y +# CONFIG_RTL8367S_GSW is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_MC=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOC_BUS=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_MT65XX=y +# CONFIG_SPI_MTK_NOR is not set +CONFIG_SPI_MTK_SNFI=y +CONFIG_SPLIT_PMD_PTLOCKS=y +CONFIG_SPLIT_PTE_PTLOCKS=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +# CONFIG_TEST_FPU is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UCLAMP_TASK is not set +CONFIG_UIMAGE_FIT_BLK=y +# CONFIG_UNMAP_KERNEL_AT_EL0 is not set +CONFIG_USB_SUPPORT=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_VDSO_GETRANDOM=y +CONFIG_VMAP_STACK=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m +CONFIG_WATCHDOG_SYSFS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index eafdd3db54..6c03ef2c12 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -52,6 +52,24 @@ define Build/mt798x-gpt rm $@.tmp endef +# Variation of the normal partition table to account +# for factory and mfgdata partition +# +# Keep fip partition at standard offset to keep consistency +# with uboot commands +define Build/mt7988-mozart-gpt + cp $@ $@.tmp 2>/dev/null || true + ptgen -g -o $@.tmp -a 1 -l 1024 \ + -t 0x83 -N ubootenv -r -p 512k@4M \ + -t 0xef -N fip -r -p 4M@6656k \ + -t 0x83 -N factory -r -p 8M@25M \ + -t 0x2e -N mfgdata -r -p 8M@33M \ + -t 0xef -N recovery -r -p 32M@41M \ + -t 0x2e -N production -p $(CONFIG_TARGET_ROOTFS_PARTSIZE)M@73M + cat $@.tmp >> $@ + rm $@.tmp +endef + define Build/append-openwrt-one-eeprom dd if=$(STAGING_DIR_IMAGE)/mt7981_eeprom_mt7976_dbdc.bin >> $@ endef @@ -245,7 +263,7 @@ define Device/arcadyan_mozart IMAGES := sysupgrade.itb IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata ARTIFACTS := emmc-preloader.bin emmc-bl31-uboot.fip emmc-gpt.bin - ARTIFACT/emmc-gpt.bin := mt798x-gpt emmc + ARTIFACT/emmc-gpt.bin := mt7988-mozart-gpt ARTIFACT/emmc-preloader.bin := mt7988-bl2 emmc-comb ARTIFACT/emmc-bl31-uboot.fip := mt7988-bl31-uboot arcadyan_mozart SUPPORTED_DEVICES += arcadyan,mozart @@ -464,7 +482,7 @@ define Device/bananapi_bpi-r4-common DEVICE_VENDOR := Bananapi DEVICE_DTS_DIR := $(DTS_DIR)/ DEVICE_DTS_LOADADDR := 0x45f00000 - DEVICE_DTS_OVERLAY:= mt7988a-bananapi-bpi-r4-emmc mt7988a-bananapi-bpi-r4-rtc mt7988a-bananapi-bpi-r4-sd mt7988a-bananapi-bpi-r4-wifi-mt7996a + DEVICE_DTS_OVERLAY:= mt7988a-bananapi-bpi-r4-emmc mt7988a-bananapi-bpi-r4-rtc mt7988a-bananapi-bpi-r4-sd DEVICE_DTC_FLAGS := --pad 4096 DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-mux-pca954x kmod-eeprom-at24 kmod-mt7996-firmware kmod-mt7996-233-firmware \ kmod-rtc-pcf8563 kmod-sfp kmod-usb3 e2fsprogs f2fsck mkf2fs mt7988-wo-firmware @@ -514,10 +532,15 @@ TARGET_DEVICES += bananapi_bpi-r4 define Device/bananapi_bpi-r4-poe DEVICE_MODEL := BPi-R4 2.5GE +ifneq ($(CONFIG_LINUX_6_6),) DEVICE_DTS := mt7988a-bananapi-bpi-r4-poe +else + DEVICE_DTS := mt7988a-bananapi-bpi-r4-2g5 +endif DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4-poe $(call Device/bananapi_bpi-r4-common) DEVICE_PACKAGES += mt7988-2p5g-phy-firmware + SUPPORTED_DEVICES += bananapi,bpi-r4-2g5 endef TARGET_DEVICES += bananapi_bpi-r4-poe @@ -1805,6 +1828,31 @@ define Device/ruijie_rg-x60-pro endef TARGET_DEVICES += ruijie_rg-x60-pro +define Device/snr_snr-cpe-ax2 + DEVICE_VENDOR := SNR + DEVICE_MODEL := SNR-CPE-AX2 + DEVICE_DTS := mt7981b-snr-snr-cpe-ax2 + DEVICE_DTS_DIR := ../dts + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | \ + append-metadata + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3 + ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot snr_snr-cpe-ax2 +endef +TARGET_DEVICES += snr_snr-cpe-ax2 + define Device/tenbay_wr3000k DEVICE_VENDOR := Tenbay DEVICE_MODEL := WR3000K diff --git a/target/linux/mediatek/mt7622/config-6.12 b/target/linux/mediatek/mt7622/config-6.12 new file mode 100644 index 0000000000..028f2c2da6 --- /dev/null +++ b/target/linux/mediatek/mt7622/config-6.12 @@ -0,0 +1,516 @@ +CONFIG_64BIT=y +# CONFIG_AHCI_MTK is not set +# CONFIG_AIROHA_EN8801SC_PHY is not set +# CONFIG_AIR_AN8855_PHY is not set +CONFIG_AQUANTIA_PHY=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_FORCE_MAX_ORDER=10 +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PKEY_BITS=3 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_EXECMEM_LATE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PLATFORM_DEVICES=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_52 is not set +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_MEDIATEK_CPUFREQ=y +CONFIG_ARM_PMU=y +CONFIG_ARM_PMUV3=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ATA=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BLOCK_NOTIFIERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y +CONFIG_CC_HAVE_SHADOW_CALL_STACK=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +# CONFIG_CMDLINE_OVERRIDE is not set +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_MEDIATEK=y +CONFIG_COMMON_CLK_MT2712=y +# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set +# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set +# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set +# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set +# CONFIG_COMMON_CLK_MT2712_MMSYS is not set +# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set +# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set +# CONFIG_COMMON_CLK_MT6779 is not set +# CONFIG_COMMON_CLK_MT6795 is not set +# CONFIG_COMMON_CLK_MT6797 is not set +CONFIG_COMMON_CLK_MT7622=y +CONFIG_COMMON_CLK_MT7622_AUDSYS=y +CONFIG_COMMON_CLK_MT7622_ETHSYS=y +CONFIG_COMMON_CLK_MT7622_HIFSYS=y +# CONFIG_COMMON_CLK_MT7981 is not set +# CONFIG_COMMON_CLK_MT7986 is not set +# CONFIG_COMMON_CLK_MT7988 is not set +# CONFIG_COMMON_CLK_MT8173 is not set +# CONFIG_COMMON_CLK_MT8183 is not set +# CONFIG_COMMON_CLK_MT8186 is not set +# CONFIG_COMMON_CLK_MT8195 is not set +# CONFIG_COMMON_CLK_MT8365 is not set +# CONFIG_COMMON_CLK_MT8516 is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +# CONFIG_COMPRESSED_INSTALL is not set +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRC16=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA256_ARM64=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SM4=y +CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y +CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y +CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_MISC=y +CONFIG_DMADEVICES=y +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_OF=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EINT_MTK=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_F2FS_FS=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=4 +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIO_CDEV=y +CONFIG_GRO_CELLS=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HISILICON_ERRATUM_162100801 is not set +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MTK=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MT65XX=y +CONFIG_ICPLUS_PHY=y +# CONFIG_IDPF is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INTEL_XWAY_PHY=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_LIB=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_JUMP_LABEL=y +CONFIG_LEDS_SMARTRG_LED=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LRU_GEN_WALKS_MMU=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAXLINEAR_GPHY=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MEDIATEK_2P5GE_PHY is not set +CONFIG_MEDIATEK_GE_PHY=y +# CONFIG_MEDIATEK_GE_SOC_PHY is not set +CONFIG_MEDIATEK_WATCHDOG=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +# CONFIG_MFD_AIROHA_AN8855 is not set +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CQHCI=y +CONFIG_MMC_MTK=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_MEDIATEK=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_MTK=y +CONFIG_MTD_NAND_MTK_BMT=y +CONFIG_MTD_PARSER_TRX=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_NVMEM=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +# CONFIG_MTK_CMDQ is not set +CONFIG_MTK_CPUX_TIMER=y +# CONFIG_MTK_CQDMA is not set +CONFIG_MTK_HSDMA=y +CONFIG_MTK_INFRACFG=y +# CONFIG_MTK_LVTS_THERMAL is not set +CONFIG_MTK_NET_PHYLIB=y +CONFIG_MTK_PMIC_WRAP=y +CONFIG_MTK_REGULATOR_COUPLER=y +CONFIG_MTK_SCPSYS=y +CONFIG_MTK_SCPSYS_PM_DOMAINS=y +CONFIG_MTK_SOCINFO=y +CONFIG_MTK_SOC_THERMAL=y +# CONFIG_MTK_SVS is not set +CONFIG_MTK_THERMAL=y +CONFIG_MTK_TIMER=y +# CONFIG_MTK_UART_APDMA is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +# CONFIG_NET_AIROHA is not set +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MT7530=y +CONFIG_NET_DSA_MT7530_MDIO=y +# CONFIG_NET_DSA_MT7530_MMIO is not set +CONFIG_NET_DSA_TAG_MTK=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_MEDIATEK_SOC=y +CONFIG_NET_MEDIATEK_SOC_WED=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_VENDOR_MEDIATEK=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +CONFIG_NVMEM_BLOCK=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_ADTRAN=y +CONFIG_NVMEM_MTK_EFUSE=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_RESOLVE=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEFAULT is not set +CONFIG_PCIEASPM_PERFORMANCE=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCS_MTK_LYNXI=y +CONFIG_PERF_EVENTS=y +CONFIG_PER_VMA_LOCK=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_MTK_DP is not set +# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set +# CONFIG_PHY_MTK_PCIE is not set +CONFIG_PHY_MTK_TPHY=y +# CONFIG_PHY_MTK_UFS is not set +# CONFIG_PHY_MTK_XSPHY is not set +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_MT2712 is not set +# CONFIG_PINCTRL_MT6765 is not set +# CONFIG_PINCTRL_MT6795 is not set +# CONFIG_PINCTRL_MT6797 is not set +CONFIG_PINCTRL_MT7622=y +# CONFIG_PINCTRL_MT7981 is not set +# CONFIG_PINCTRL_MT7986 is not set +# CONFIG_PINCTRL_MT7988 is not set +# CONFIG_PINCTRL_MT8173 is not set +# CONFIG_PINCTRL_MT8183 is not set +# CONFIG_PINCTRL_MT8186 is not set +# CONFIG_PINCTRL_MT8188 is not set +# CONFIG_PINCTRL_MT8516 is not set +CONFIG_PINCTRL_MTK_MOORE=y +CONFIG_PINCTRL_MTK_V2=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_OPP=y +CONFIG_POLYNOMIAL=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_SUPPLY=y +CONFIG_PRINTK_TIME=y +CONFIG_PSTORE=y +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_MEDIATEK=y +# CONFIG_PWM_MTK_DISP is not set +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RAVE_SP_CORE is not set +CONFIG_REALTEK_PHY=y +CONFIG_REALTEK_PHY_HWMON=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MT6380=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MT7622=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTL8367S_GSW=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_MC=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOC_BUS=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_MT65XX=y +CONFIG_SPI_MTK_NOR=y +CONFIG_SPI_MTK_SNFI=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +# CONFIG_TEST_FPU is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UCLAMP_TASK is not set +CONFIG_UIMAGE_FIT_BLK=y +# CONFIG_UNMAP_KERNEL_AT_EL0 is not set +CONFIG_USB_SUPPORT=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_VDSO_GETRANDOM=y +CONFIG_VMAP_STACK=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m +CONFIG_WATCHDOG_SYSFS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7623/config-6.12 b/target/linux/mediatek/mt7623/config-6.12 new file mode 100644 index 0000000000..7e0e91c1c5 --- /dev/null +++ b/target/linux/mediatek/mt7623/config-6.12 @@ -0,0 +1,670 @@ +# CONFIG_AIO is not set +# CONFIG_AIROHA_EN8801SC_PHY is not set +# CONFIG_AIR_AN8855_PHY is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +CONFIG_ARM_CPU_SUSPEND=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +# CONFIG_ARM_DEBUG_WX is not set +CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 +CONFIG_ARM_DMA_USE_IOMMU=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_GROUP_RELOCS=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set +CONFIG_ARM_MEDIATEK_CPUFREQ=y +CONFIG_ARM_PAN=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GPIO=y +# CONFIG_BACKLIGHT_KTD2801 is not set +CONFIG_BACKLIGHT_LED=y +# CONFIG_BACKLIGHT_LM3509 is not set +# CONFIG_BACKLIGHT_MP3309C is not set +CONFIG_BACKLIGHT_PWM=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BOUNCE=y +CONFIG_BUFFER_HEAD=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_OVERRIDE is not set +CONFIG_CMDLINE_PARTITION=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_MEDIATEK=y +CONFIG_COMMON_CLK_MT2701=y +CONFIG_COMMON_CLK_MT2701_AUDSYS=y +CONFIG_COMMON_CLK_MT2701_BDPSYS=y +CONFIG_COMMON_CLK_MT2701_ETHSYS=y +CONFIG_COMMON_CLK_MT2701_G3DSYS=y +CONFIG_COMMON_CLK_MT2701_HIFSYS=y +CONFIG_COMMON_CLK_MT2701_IMGSYS=y +CONFIG_COMMON_CLK_MT2701_MMSYS=y +CONFIG_COMMON_CLK_MT2701_VDECSYS=y +# CONFIG_COMMON_CLK_MT6795 is not set +# CONFIG_COMMON_CLK_MT7622 is not set +# CONFIG_COMMON_CLK_MT7629 is not set +# CONFIG_COMMON_CLK_MT7981 is not set +# CONFIG_COMMON_CLK_MT7986 is not set +# CONFIG_COMMON_CLK_MT7988 is not set +# CONFIG_COMMON_CLK_MT8135 is not set +# CONFIG_COMMON_CLK_MT8365 is not set +# CONFIG_COMMON_CLK_MT8516 is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_COREDUMP=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_GENIV=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_ALIGN_RODATA=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_GPIO=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_MISC=y +CONFIG_DEBUG_MT6589_UART0=y +# CONFIG_DEBUG_MT8127_UART0 is not set +# CONFIG_DEBUG_MT8135_UART3 is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_UART_8250=y +CONFIG_DEBUG_UART_8250_SHIFT=2 +CONFIG_DEBUG_UART_PHYS=0x11004000 +CONFIG_DEBUG_UART_VIRT=0xf1004000 +# CONFIG_DEVFREQ_GOV_PASSIVE is not set +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS_HELPERS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DRM=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_BRIDGE_CONNECTOR=y +CONFIG_DRM_DISPLAY_CONNECTOR=y +# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set +# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y +CONFIG_DRM_DISPLAY_HELPER=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_DMA_HELPER=y +CONFIG_DRM_GEM_SHMEM_HELPER=y +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_LIMA=y +CONFIG_DRM_LVDS_CODEC=y +CONFIG_DRM_MEDIATEK=y +# CONFIG_DRM_MEDIATEK_DP is not set +CONFIG_DRM_MEDIATEK_HDMI=y +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_PANEL=y +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set +CONFIG_DRM_PANEL_BRIDGE=y +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set +# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y +# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set +# CONFIG_DRM_PANIC is not set +# CONFIG_DRM_PANTHOR is not set +CONFIG_DRM_SCHED=y +CONFIG_DRM_SIMPLE_BRIDGE=y +# CONFIG_DRM_WERROR is not set +# CONFIG_DRM_XE is not set +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EARLY_PRINTK=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EINT_MTK=y +CONFIG_ELF_CORE=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_EXTCON=y +CONFIG_F2FS_FS=y +CONFIG_FB=y +CONFIG_FB_CORE=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_DEVICE=y +CONFIG_FB_DMAMEM_HELPERS=y +CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y +CONFIG_FB_SYSMEM_FOPS=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GLOB=y +CONFIG_GPIO_CDEV=y +CONFIG_GRO_CELLS=y +# CONFIG_HARDEN_BRANCH_HISTORY is not set +# CONFIG_HARDEN_BRANCH_PREDICTOR is not set +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HDMI=y +CONFIG_HID=y +CONFIG_HID_SUPPORT=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MTK=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MT65XX=y +CONFIG_ICPLUS_PHY=y +# CONFIG_IDPF is not set +CONFIG_IIO=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_IOMMUFD is not set +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_IO_PGTABLE=y +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +CONFIG_KCMP=y +CONFIG_KEYBOARD_MTK_PMIC=y +CONFIG_KMAP_LOCAL=y +CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y +CONFIG_LEDS_MT6323=y +# CONFIG_LEDS_QCOM_LPG is not set +# CONFIG_LEDS_SMARTRG_LED is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_MACH_MT2701 is not set +# CONFIG_MACH_MT6589 is not set +# CONFIG_MACH_MT6592 is not set +CONFIG_MACH_MT7623=y +# CONFIG_MACH_MT7629 is not set +# CONFIG_MACH_MT8127 is not set +# CONFIG_MACH_MT8135 is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_GPIO=y +CONFIG_MEDIATEK_GE_PHY=y +# CONFIG_MEDIATEK_MT6359_AUXADC is not set +CONFIG_MEDIATEK_MT6577_AUXADC=y +CONFIG_MEDIATEK_WATCHDOG=y +CONFIG_MEMORY=y +# CONFIG_MFD_AIROHA_AN8855 is not set +CONFIG_MFD_CORE=y +# CONFIG_MFD_HI6421_SPMI is not set +CONFIG_MFD_MT6397=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CQHCI=y +CONFIG_MMC_MTK=y +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_NAND_ECC_MEDIATEK is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +# CONFIG_MTK_ADSP_MBOX is not set +CONFIG_MTK_CMDQ=y +CONFIG_MTK_CMDQ_MBOX=y +CONFIG_MTK_CPUX_TIMER=y +CONFIG_MTK_CQDMA=y +# CONFIG_MTK_HSDMA is not set +CONFIG_MTK_INFRACFG=y +CONFIG_MTK_IOMMU=y +CONFIG_MTK_IOMMU_V1=y +# CONFIG_MTK_LVTS_THERMAL is not set +CONFIG_MTK_MMSYS=y +CONFIG_MTK_NET_PHYLIB=y +CONFIG_MTK_PMIC_WRAP=y +CONFIG_MTK_REGULATOR_COUPLER=y +CONFIG_MTK_SCPSYS=y +CONFIG_MTK_SCPSYS_PM_DOMAINS=y +CONFIG_MTK_SMI=y +CONFIG_MTK_SOCINFO=y +CONFIG_MTK_SOC_THERMAL=y +# CONFIG_MTK_SVS is not set +CONFIG_MTK_THERMAL=y +CONFIG_MTK_TIMER=y +# CONFIG_MTK_UART_APDMA is not set +# CONFIG_MUSB_PIO_ONLY is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NEON=y +# CONFIG_NET_AIROHA is not set +CONFIG_NET_DEVLINK=y +CONFIG_NET_DEVMEM=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MT7530=y +CONFIG_NET_DSA_MT7530_MDIO=y +# CONFIG_NET_DSA_MT7530_MMIO is not set +CONFIG_NET_DSA_TAG_MTK=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_MEDIATEK_SOC=y +CONFIG_NET_MEDIATEK_SOC_WED=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_VENDOR_MEDIATEK=y +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +# CONFIG_NVMEM_LAYOUT_ADTRAN is not set +CONFIG_NVMEM_MTK_EFUSE=y +# CONFIG_NVMEM_SPMI_SDAM is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_RESOLVE=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCS_MTK_LYNXI=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PER_VMA_LOCK=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +# CONFIG_PHY_MTK_DP is not set +CONFIG_PHY_MTK_HDMI=y +# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set +CONFIG_PHY_MTK_MIPI_DSI=y +# CONFIG_PHY_MTK_PCIE is not set +CONFIG_PHY_MTK_TPHY=y +# CONFIG_PHY_MTK_UFS is not set +# CONFIG_PHY_MTK_XSPHY is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MT2701=y +# CONFIG_PINCTRL_MT6397 is not set +CONFIG_PINCTRL_MT7623=y +CONFIG_PINCTRL_MTK=y +CONFIG_PINCTRL_MTK_MOORE=y +CONFIG_PINCTRL_MTK_V2=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_DEVFREQ=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_MT6323 is not set +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PREEMPT=y +CONFIG_PREEMPTION=y +CONFIG_PREEMPT_BUILD=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_MEDIATEK=y +# CONFIG_PWM_MTK_DISP is not set +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MT6323=y +# CONFIG_REGULATOR_MT6331 is not set +# CONFIG_REGULATOR_MT6332 is not set +# CONFIG_REGULATOR_MT6357 is not set +# CONFIG_REGULATOR_MT6358 is not set +# CONFIG_REGULATOR_MT6380 is not set +# CONFIG_REGULATOR_MT6397 is not set +# CONFIG_REGULATOR_QCOM_LABIBB is not set +# CONFIG_REGULATOR_QCOM_SPMI is not set +# CONFIG_REGULATOR_QCOM_USB_VBUS is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MT6397 is not set +# CONFIG_RTC_DRV_MT7622 is not set +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +# CONFIG_RTL8367S_GSW is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SGL_ALLOC=y +CONFIG_SMP=y +# CONFIG_SMP_ON_UP is not set +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOC_BUS=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_MT65XX=y +# CONFIG_SPI_MTK_NOR is not set +CONFIG_SPLIT_PTE_PTLOCKS=y +CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set +# CONFIG_SPMI_MTK_PMIF is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYNC_FILE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TOUCHSCREEN_EDT_FT5X06=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_UIMAGE_FIT_BLK=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_F_ACM=y +CONFIG_USB_F_ECM=y +CONFIG_USB_F_MASS_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GPIO_VBUS=y +CONFIG_USB_G_MULTI=y +CONFIG_USB_G_MULTI_CDC=y +# CONFIG_USB_G_MULTI_RNDIS is not set +CONFIG_USB_HID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_INVENTRA_DMA=y +CONFIG_USB_LIBCOMPOSITE=y +CONFIG_USB_MUSB_DUAL_ROLE=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_MEDIATEK=y +CONFIG_USB_OTG=y +CONFIG_USB_PHY=y +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_U_ETHER=y +CONFIG_USB_U_SERIAL=y +CONFIG_USE_OF=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VIDEO=y +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7629/config-6.12 b/target/linux/mediatek/mt7629/config-6.12 new file mode 100644 index 0000000000..2098293e69 --- /dev/null +++ b/target/linux/mediatek/mt7629/config-6.12 @@ -0,0 +1,367 @@ +# CONFIG_AIROHA_EN8801SC_PHY is not set +# CONFIG_AIR_AN8855_PHY is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ARM_DEBUG_WX is not set +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_GROUP_RELOCS=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PAN=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_CACHE_L2X0=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CHR_DEV_SCH=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="rootfstype=squashfs,jffs2" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_CMDLINE_OVERRIDE=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_MEDIATEK=y +# CONFIG_COMMON_CLK_MT2701 is not set +# CONFIG_COMMON_CLK_MT6795 is not set +# CONFIG_COMMON_CLK_MT7622 is not set +CONFIG_COMMON_CLK_MT7629=y +CONFIG_COMMON_CLK_MT7629_ETHSYS=y +CONFIG_COMMON_CLK_MT7629_HIFSYS=y +# CONFIG_COMMON_CLK_MT7981 is not set +# CONFIG_COMMON_CLK_MT7986 is not set +# CONFIG_COMMON_CLK_MT7988 is not set +# CONFIG_COMMON_CLK_MT8135 is not set +# CONFIG_COMMON_CLK_MT8365 is not set +# CONFIG_COMMON_CLK_MT8516 is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MISC=y +CONFIG_DEFAULT_HOSTNAME="(mt7629)" +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_OPS_HELPERS=y +CONFIG_DTC=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EINT_MTK=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GPIO_CDEV=y +CONFIG_GRO_CELLS=y +# CONFIG_HARDEN_BRANCH_HISTORY is not set +# CONFIG_HARDEN_BRANCH_PREDICTOR is not set +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MTK=y +CONFIG_HZ_FIXED=0 +# CONFIG_IDPF is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +# CONFIG_LEDS_SMARTRG_LED is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_MACH_MT2701 is not set +# CONFIG_MACH_MT6589 is not set +# CONFIG_MACH_MT6592 is not set +# CONFIG_MACH_MT7623 is not set +CONFIG_MACH_MT7629=y +# CONFIG_MACH_MT8127 is not set +# CONFIG_MACH_MT8135 is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEDIATEK_GE_PHY=y +CONFIG_MEDIATEK_WATCHDOG=y +# CONFIG_MFD_AIROHA_AN8855 is not set +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_MEDIATEK=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_MTK_BMT=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +# CONFIG_MTK_CMDQ is not set +CONFIG_MTK_CPUX_TIMER=y +CONFIG_MTK_INFRACFG=y +CONFIG_MTK_NET_PHYLIB=y +# CONFIG_MTK_PMIC_WRAP is not set +CONFIG_MTK_SCPSYS=y +CONFIG_MTK_SCPSYS_PM_DOMAINS=y +CONFIG_MTK_TIMER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_BPF_LINK=y +# CONFIG_NET_AIROHA is not set +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MT7530=y +CONFIG_NET_DSA_MT7530_MDIO=y +# CONFIG_NET_DSA_MT7530_MMIO is not set +CONFIG_NET_DSA_TAG_MTK=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_MEDIATEK_SOC=y +CONFIG_NET_MEDIATEK_SOC_WED=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_VENDOR_MEDIATEK=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +# CONFIG_NVMEM_LAYOUT_ADTRAN is not set +# CONFIG_NVMEM_MTK_EFUSE is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCS_MTK_LYNXI=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PER_VMA_LOCK=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +# CONFIG_PHY_MTK_DP is not set +# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set +# CONFIG_PHY_MTK_PCIE is not set +CONFIG_PHY_MTK_TPHY=y +# CONFIG_PHY_MTK_UFS is not set +# CONFIG_PHY_MTK_XSPHY is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MT7629=y +CONFIG_PINCTRL_MTK_MOORE=y +CONFIG_PINCTRL_MTK_V2=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_MEDIATEK=y +# CONFIG_PWM_MTK_DISP is not set +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +# CONFIG_RTL8367S_GSW is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_MT65XX=y +CONFIG_SPI_MTK_NOR=y +CONFIG_SPI_MTK_SNFI=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_STACKTRACE=y +# CONFIG_SWAP is not set +CONFIG_SWCONFIG=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_USE_OF=y +# CONFIG_VFP is not set +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/patches-6.12/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch b/target/linux/mediatek/patches-6.12/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch new file mode 100644 index 0000000000..2dcdbcffe4 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch @@ -0,0 +1,151 @@ +From 1673d720b7e2862a5ff1994922558b7427f8a56b Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 17 Dec 2024 09:54:26 +0100 +Subject: [PATCH 1/2] pinctrl: mediatek: add support for MTK_PULL_PD_TYPE + +The MediaTek MT7988 SoC got some pins which only got configurable +pull-down but unlike previous designs there is no pull-up option. +Add new type MTK_PULL_PD_TYPE to support configuring such pins. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/20241217085435.9586-2-linux@fw-web.de +Signed-off-by: Linus Walleij +--- + .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 73 ++++++++++++++++--- + .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 + + 2 files changed, 63 insertions(+), 11 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +@@ -573,7 +573,7 @@ EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_r + */ + static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, +- u32 pullup, u32 arg) ++ u32 pullup, u32 arg, bool pd_only) + { + int err, pu, pd; + +@@ -587,18 +587,34 @@ static int mtk_pinconf_bias_set_pu_pd(st + pu = 0; + pd = 1; + } else { +- err = -EINVAL; +- goto out; ++ return -EINVAL; + } + +- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); +- if (err) +- goto out; ++ if (!pd_only) { ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); ++ if (err) ++ return err; ++ } + +- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); ++ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); ++} ++ ++static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ u32 pullup, u32 arg) ++{ ++ int err, pd; ++ ++ if (arg != MTK_DISABLE && arg != MTK_ENABLE) ++ return -EINVAL; ++ ++ if (arg == MTK_DISABLE || pullup) ++ pd = 0; ++ else if (!pullup) ++ pd = 1; ++ ++ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); + +-out: +- return err; + } + + static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, +@@ -737,7 +753,7 @@ static int mtk_pinconf_bias_set_pu_pd_rs + return err; + } + +- return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable); ++ return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable, false); + } + + int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, +@@ -758,8 +774,14 @@ int mtk_pinconf_bias_set_combo(struct mt + return 0; + } + ++ if (try_all_type & MTK_PULL_PD_TYPE) { ++ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, true); ++ if (!err) ++ return err; ++ } ++ + if (try_all_type & MTK_PULL_PU_PD_TYPE) { +- err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); ++ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, false); + if (!err) + return 0; + } +@@ -878,6 +900,29 @@ out: + return err; + } + ++static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ u32 *pullup, u32 *enable) ++{ ++ int err, pd; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); ++ if (err) ++ goto out; ++ ++ if (pd == 0) { ++ *pullup = 0; ++ *enable = MTK_DISABLE; ++ } else if (pd == 1) { ++ *pullup = 0; ++ *enable = MTK_ENABLE; ++ } else ++ err = -EINVAL; ++ ++out: ++ return err; ++} ++ + static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, + u32 *pullup, u32 *enable) +@@ -947,6 +992,12 @@ int mtk_pinconf_bias_get_combo(struct mt + return 0; + } + ++ if (try_all_type & MTK_PULL_PD_TYPE) { ++ err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable); ++ if (!err) ++ return err; ++ } ++ + if (try_all_type & MTK_PULL_PU_PD_TYPE) { + err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); + if (!err) +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +@@ -24,6 +24,7 @@ + * turned on/off itself. But it can't be selected pull up/down + */ + #define MTK_PULL_RSEL_TYPE BIT(3) ++#define MTK_PULL_PD_TYPE BIT(4) + /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by + * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE. + */ diff --git a/target/linux/mediatek/patches-6.12/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch b/target/linux/mediatek/patches-6.12/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch new file mode 100644 index 0000000000..d94a0ba60b --- /dev/null +++ b/target/linux/mediatek/patches-6.12/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch @@ -0,0 +1,1610 @@ +From 08bec851118226cc8c4397692542b855de2e0d73 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 17 Dec 2024 09:54:27 +0100 +Subject: [PATCH 2/2] pinctrl: mediatek: add MT7988 pinctrl driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add pinctrl driver for the MediaTek MT7988 SoC. + +Signed-off-by: Sam Shih +Signed-off-by: Daniel Golle +[correctly initialise for the function_desc structure] +Signed-off-by: Arınç ÜNAL +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/20241217085435.9586-3-linux@fw-web.de +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/Kconfig | 7 + + drivers/pinctrl/mediatek/Makefile | 1 + + drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1556 +++++++++++++++++++++ + 3 files changed, 1564 insertions(+) + create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7988.c + +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -187,6 +187,13 @@ config PINCTRL_MT7986 + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_MOORE + ++config PINCTRL_MT7988 ++ bool "Mediatek MT7988 pin control" ++ depends on OF ++ depends on ARM64 || COMPILE_TEST ++ default ARM64 && ARCH_MEDIATEK ++ select PINCTRL_MTK_MOORE ++ + config PINCTRL_MT8167 + bool "MediaTek MT8167 pin control" + depends on OF +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl + obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o + obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o + obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o ++obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o + obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o + obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o + obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c +@@ -0,0 +1,1556 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * The MT7988 driver based on Linux generic pinctrl binding. ++ * ++ * Copyright (C) 2020 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++#include "pinctrl-moore.h" ++ ++enum mt7988_pinctrl_reg_page { ++ GPIO_BASE, ++ IOCFG_TR_BASE, ++ IOCFG_BR_BASE, ++ IOCFG_RB_BASE, ++ IOCFG_LB_BASE, ++ IOCFG_TL_BASE, ++}; ++ ++#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) ++ ++#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 32, 0) ++ ++#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 32, 1) ++ ++static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { ++ PIN_FIELD(0, 83, 0x300, 0x10, 0, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { ++ PIN_FIELD(0, 83, 0x0, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { ++ PIN_FIELD(0, 83, 0x200, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { ++ PIN_FIELD(0, 83, 0x100, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { ++ PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1), ++ PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1), ++ PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1), ++ PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1), ++ PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), ++ PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), ++ PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), ++ PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1), ++ PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1), ++ PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1), ++ PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1), ++ PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), ++ PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1), ++ PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1), ++ PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), ++ PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1), ++ PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1), ++ PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1), ++ PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), ++ PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), ++ PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), ++ PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1), ++ PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1), ++ PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1), ++ PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1), ++ PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1), ++ ++ PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1), ++ PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1), ++ PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1), ++ ++ PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), ++ PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), ++ PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), ++ PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1), ++ PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), ++ PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), ++ PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), ++ ++ PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1), ++ PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1), ++ PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1), ++ PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { ++ PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1), ++ PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1), ++ PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1), ++ PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1), ++ PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), ++ PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), ++ PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), ++ PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1), ++ PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1), ++ PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1), ++ PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1), ++ PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), ++ PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1), ++ PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1), ++ PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), ++ PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1), ++ PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1), ++ PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1), ++ PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), ++ PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), ++ PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), ++ PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1), ++ PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1), ++ PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1), ++ PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1), ++ PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1), ++ ++ PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1), ++ PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1), ++ PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1), ++ ++ PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), ++ PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), ++ PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), ++ PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1), ++ PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), ++ PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), ++ PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), ++ ++ PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1), ++ PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1), ++ PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1), ++ PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { ++ PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), ++ PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), ++ PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1), ++ PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1), ++ PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), ++ PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), ++ PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { ++ PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1), ++ PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), ++ PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), ++ PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1), ++ PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1), ++ PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1), ++ PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1), ++ ++ PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), ++ PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), ++ PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), ++ PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1), ++ PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { ++ PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3), ++ PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3), ++ ++ PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), ++ PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), ++ ++ PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), ++ PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), ++ ++ PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), ++ PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), ++ PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), ++ PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), ++ PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3), ++ PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3), ++ PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), ++ PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3), ++ PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3), ++ PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3), ++ PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), ++ PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), ++ PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), ++ PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3), ++ PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3), ++ PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3), ++ PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), ++ PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), ++ PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), ++ PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), ++ PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3), ++ PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3), ++ PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), ++ PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), ++ PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3), ++ PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3), ++ PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3), ++ PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), ++ ++ PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3), ++ PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3), ++ PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), ++ PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3), ++ PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3), ++ PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3), ++ PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), ++ PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), ++ PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), ++ PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3), ++ PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3), ++ PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3), ++ PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3), ++ PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), ++ PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), ++ PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), ++ PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3), ++ PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), ++ PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), ++ PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), ++ ++ PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3), ++ PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3), ++ PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3), ++ PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { ++ PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1), ++ PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1), ++ PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), ++ ++ PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1), ++ PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1), ++ PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), ++ PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1), ++ PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1), ++ PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1), ++ PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), ++ PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1), ++ PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1), ++ PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1), ++ PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1), ++ PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), ++ PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), ++ ++ PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1), ++ PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1), ++ PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1), ++ PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { ++ PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1), ++ PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1), ++ PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1), ++ PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), ++ ++ PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1), ++ PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1), ++ PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), ++ PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1), ++ PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1), ++ PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1), ++ PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), ++ PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), ++ PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1), ++ PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1), ++ PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1), ++ PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1), ++ PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), ++ PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), ++ ++ PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1), ++ PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1), ++ PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1), ++ PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { ++ PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1), ++ PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1), ++ PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1), ++ PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), ++ PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1), ++ PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1), ++ ++ PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), ++ ++ PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), ++ PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), ++ ++ PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), ++ PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), ++ PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), ++ PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), ++ PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1), ++ PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1), ++ PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), ++ PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1), ++ PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1), ++ PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1), ++ PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), ++ PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), ++ PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), ++ PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), ++ PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1), ++ PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1), ++ PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1), ++ PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), ++ PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), ++ PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1), ++ PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1), ++ PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1), ++ PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), ++ ++ PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1), ++ PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1), ++ PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), ++ PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1), ++ PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1), ++ PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1), ++ PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), ++ PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), ++ PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1), ++ PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1), ++ PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1), ++ PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1), ++ PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1), ++ ++ PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1), ++ PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1), ++ ++ PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), ++ PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), ++ ++ PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1), ++ PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1), ++ PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1), ++ PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1), ++}; ++ ++static const unsigned int mt7988_pull_type[] = { ++ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE, /*7*/ ++ MTK_PULL_PU_PD_TYPE, /*8*/ MTK_PULL_PU_PD_TYPE, /*9*/ ++ MTK_PULL_PU_PD_TYPE, /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE, /*13*/ ++ MTK_PULL_PU_PD_TYPE, /*14*/ MTK_PULL_PD_TYPE, /*15*/ ++ MTK_PULL_PD_TYPE, /*16*/ MTK_PULL_PD_TYPE, /*17*/ ++ MTK_PULL_PD_TYPE, /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE, /*63*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE, /*71*/ ++ MTK_PULL_PD_TYPE, /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE, /*75*/ ++ MTK_PULL_PU_PD_TYPE, /*76*/ MTK_PULL_PU_PD_TYPE, /*77*/ ++ MTK_PULL_PU_PD_TYPE, /*78*/ MTK_PULL_PU_PD_TYPE, /*79*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/ ++ MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/ ++}; ++ ++static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { ++ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), ++ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), ++ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), ++ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), ++ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), ++ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), ++ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), ++ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), ++ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), ++ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), ++ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), ++ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), ++}; ++ ++static const struct mtk_pin_desc mt7988_pins[] = { ++ MT7988_PIN(0, "UART2_RXD"), ++ MT7988_PIN(1, "UART2_TXD"), ++ MT7988_PIN(2, "UART2_CTS"), ++ MT7988_PIN(3, "UART2_RTS"), ++ MT7988_PIN(4, "GPIO_A"), ++ MT7988_PIN(5, "SMI_0_MDC"), ++ MT7988_PIN(6, "SMI_0_MDIO"), ++ MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"), ++ MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"), ++ MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"), ++ MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"), ++ MT7988_PIN(11, "GPIO_P"), ++ MT7988_PIN(12, "WATCHDOG"), ++ MT7988_PIN(13, "GPIO_RESET"), ++ MT7988_PIN(14, "GPIO_WPS"), ++ MT7988_PIN(15, "PMIC_I2C_SCL"), ++ MT7988_PIN(16, "PMIC_I2C_SDA"), ++ MT7988_PIN(17, "I2C_1_SCL"), ++ MT7988_PIN(18, "I2C_1_SDA"), ++ MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"), ++ MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"), ++ MT7988_PIN(21, "PWMD1"), ++ MT7988_PIN(22, "SPI0_WP"), ++ MT7988_PIN(23, "SPI0_HOLD"), ++ MT7988_PIN(24, "SPI0_CSB"), ++ MT7988_PIN(25, "SPI0_MISO"), ++ MT7988_PIN(26, "SPI0_MOSI"), ++ MT7988_PIN(27, "SPI0_CLK"), ++ MT7988_PIN(28, "SPI1_CSB"), ++ MT7988_PIN(29, "SPI1_MISO"), ++ MT7988_PIN(30, "SPI1_MOSI"), ++ MT7988_PIN(31, "SPI1_CLK"), ++ MT7988_PIN(32, "SPI2_CLK"), ++ MT7988_PIN(33, "SPI2_MOSI"), ++ MT7988_PIN(34, "SPI2_MISO"), ++ MT7988_PIN(35, "SPI2_CSB"), ++ MT7988_PIN(36, "SPI2_HOLD"), ++ MT7988_PIN(37, "SPI2_WP"), ++ MT7988_PIN(38, "EMMC_RSTB"), ++ MT7988_PIN(39, "EMMC_DSL"), ++ MT7988_PIN(40, "EMMC_CK"), ++ MT7988_PIN(41, "EMMC_CMD"), ++ MT7988_PIN(42, "EMMC_DATA_7"), ++ MT7988_PIN(43, "EMMC_DATA_6"), ++ MT7988_PIN(44, "EMMC_DATA_5"), ++ MT7988_PIN(45, "EMMC_DATA_4"), ++ MT7988_PIN(46, "EMMC_DATA_3"), ++ MT7988_PIN(47, "EMMC_DATA_2"), ++ MT7988_PIN(48, "EMMC_DATA_1"), ++ MT7988_PIN(49, "EMMC_DATA_0"), ++ MT7988_PIN(50, "PCM_FS_I2S_LRCK"), ++ MT7988_PIN(51, "PCM_CLK_I2S_BCLK"), ++ MT7988_PIN(52, "PCM_DRX_I2S_DIN"), ++ MT7988_PIN(53, "PCM_DTX_I2S_DOUT"), ++ MT7988_PIN(54, "PCM_MCK_I2S_MCLK"), ++ MT7988_PIN(55, "UART0_RXD"), ++ MT7988_PIN(56, "UART0_TXD"), ++ MT7988_PIN(57, "PWMD0"), ++ MT7988_PIN(58, "JTAG_JTDI"), ++ MT7988_PIN(59, "JTAG_JTDO"), ++ MT7988_PIN(60, "JTAG_JTMS"), ++ MT7988_PIN(61, "JTAG_JTCLK"), ++ MT7988_PIN(62, "JTAG_JTRST_N"), ++ MT7988_PIN(63, "USB_DRV_VBUS_P1"), ++ MT7988_PIN(64, "LED_A"), ++ MT7988_PIN(65, "LED_B"), ++ MT7988_PIN(66, "LED_C"), ++ MT7988_PIN(67, "LED_D"), ++ MT7988_PIN(68, "LED_E"), ++ MT7988_PIN(69, "GPIO_B"), ++ MT7988_PIN(70, "GPIO_C"), ++ MT7988_PIN(71, "I2C_2_SCL"), ++ MT7988_PIN(72, "I2C_2_SDA"), ++ MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"), ++ MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"), ++ MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"), ++ MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"), ++ MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"), ++ MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"), ++ MT7988_PIN(79, "USB_DRV_VBUS_P0"), ++ MT7988_PIN(80, "UART1_RXD"), ++ MT7988_PIN(81, "UART1_TXD"), ++ MT7988_PIN(82, "UART1_CTS"), ++ MT7988_PIN(83, "UART1_RTS"), ++}; ++ ++/* jtag */ ++static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; ++static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; ++ ++static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; ++static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; ++ ++static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; ++static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; ++ ++static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; ++static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; ++ ++static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; ++static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; ++ ++static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; ++static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; ++ ++/* int_usxgmii */ ++static const int mt7988_int_usxgmii_pins[] = { 2, 3 }; ++static int mt7988_int_usxgmii_funcs[] = { 3, 3 }; ++ ++/* pwm */ ++static const int mt7988_pwm0_pins[] = { 57 }; ++static int mt7988_pwm0_funcs[] = { 1 }; ++ ++static const int mt7988_pwm1_pins[] = { 21 }; ++static int mt7988_pwm1_funcs[] = { 1 }; ++ ++static const int mt7988_pwm2_pins[] = { 80 }; ++static int mt7988_pwm2_funcs[] = { 2 }; ++ ++static const int mt7988_pwm2_0_pins[] = { 58 }; ++static int mt7988_pwm2_0_funcs[] = { 5 }; ++ ++static const int mt7988_pwm3_pins[] = { 81 }; ++static int mt7988_pwm3_funcs[] = { 2 }; ++ ++static const int mt7988_pwm3_0_pins[] = { 59 }; ++static int mt7988_pwm3_0_funcs[] = { 5 }; ++ ++static const int mt7988_pwm4_pins[] = { 82 }; ++static int mt7988_pwm4_funcs[] = { 2 }; ++ ++static const int mt7988_pwm4_0_pins[] = { 60 }; ++static int mt7988_pwm4_0_funcs[] = { 5 }; ++ ++static const int mt7988_pwm5_pins[] = { 83 }; ++static int mt7988_pwm5_funcs[] = { 2 }; ++ ++static const int mt7988_pwm5_0_pins[] = { 61 }; ++static int mt7988_pwm5_0_funcs[] = { 5 }; ++ ++static const int mt7988_pwm6_pins[] = { 69 }; ++static int mt7988_pwm6_funcs[] = { 3 }; ++ ++static const int mt7988_pwm6_0_pins[] = { 62 }; ++static int mt7988_pwm6_0_funcs[] = { 5 }; ++ ++static const int mt7988_pwm7_pins[] = { 70 }; ++static int mt7988_pwm7_funcs[] = { 3 }; ++ ++static const int mt7988_pwm7_0_pins[] = { 4 }; ++static int mt7988_pwm7_0_funcs[] = { 3 }; ++ ++/* dfd */ ++static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; ++static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; ++ ++/* i2c */ ++static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; ++static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; ++ ++static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; ++static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; ++ ++static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; ++static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; ++ ++static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; ++static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; ++ ++static const int mt7988_i2c0_0_pins[] = { 5, 6 }; ++static int mt7988_i2c0_0_funcs[] = { 2, 2 }; ++ ++static const int mt7988_i2c1_sfp_pins[] = { 5, 6 }; ++static int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; ++ ++static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; ++static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; ++ ++static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; ++static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; ++ ++static const int mt7988_i2c0_1_pins[] = { 15, 16 }; ++static int mt7988_i2c0_1_funcs[] = { 1, 1 }; ++ ++static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; ++static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; ++ ++static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; ++static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; ++ ++static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; ++static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; ++ ++static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; ++static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; ++ ++static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; ++static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; ++ ++static const int mt7988_i2c1_0_pins[] = { 17, 18 }; ++static int mt7988_i2c1_0_funcs[] = { 1, 1 }; ++ ++static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; ++static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; ++ ++static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; ++static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; ++ ++static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; ++static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; ++ ++static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; ++static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; ++ ++static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; ++static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; ++ ++static const int mt7988_i2c1_2_pins[] = { 69, 70 }; ++static int mt7988_i2c1_2_funcs[] = { 2, 2 }; ++ ++static const int mt7988_i2c2_0_pins[] = { 69, 70 }; ++static int mt7988_i2c2_0_funcs[] = { 4, 4 }; ++ ++static const int mt7988_i2c2_1_pins[] = { 71, 72 }; ++static int mt7988_i2c2_1_funcs[] = { 1, 1 }; ++ ++/* eth */ ++static const int mt7988_mdc_mdio0_pins[] = { 5, 6 }; ++static int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; ++ ++static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; ++static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; ++ ++static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; ++static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; ++ ++static const int mt7988_mdc_mdio1_pins[] = { 69, 70 }; ++static int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; ++ ++/* pcie */ ++static const int mt7988_pcie_wake_n0_0_pins[] = { 7 }; ++static int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; ++static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_wake_n3_0_pins[] = { 9 }; ++static int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n3_pins[] = { 10 }; ++static int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; ++static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; ++ ++static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; ++static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; ++ ++static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; ++static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; ++ ++static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; ++static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; ++ ++static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; ++static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; ++ ++static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; ++static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; ++ ++static const int mt7988_pcie_wake_n0_1_pins[] = { 13 }; ++static int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; ++ ++static const int mt7988_pcie_wake_n3_1_pins[] = { 14 }; ++static int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; ++ ++static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; ++static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; ++static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; ++static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; ++ ++static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; ++static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; ++static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_wake_n1_0_pins[] = { 75 }; ++static int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n1_pins[] = { 76 }; ++static int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_wake_n2_0_pins[] = { 77 }; ++static int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; ++static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; ++ ++static const int mt7988_pcie_wake_n2_1_pins[] = { 79 }; ++static int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; ++ ++/* pmic */ ++static const int mt7988_pmic_pins[] = { 11 }; ++static int mt7988_pmic_funcs[] = { 1 }; ++ ++/* watchdog */ ++static const int mt7988_watchdog_pins[] = { 12 }; ++static int mt7988_watchdog_funcs[] = { 1 }; ++ ++/* spi */ ++static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; ++static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; ++ ++static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; ++static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; ++static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; ++static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; ++static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; ++ ++/* flash */ ++static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; ++static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; ++ ++static const int mt7988_emmc_45_pins[] = { ++ 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 ++}; ++static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; ++ ++static const int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 }; ++static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 }; ++ ++static const int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43, ++ 44, 45, 46, 47, 48, 49 }; ++static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; ++ ++/* uart */ ++static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; ++static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_tops_uart0_0_pins[] = { 22, 23 }; ++static int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; ++ ++static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; ++static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; ++ ++static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; ++static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; ++ ++static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; ++static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; ++ ++static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; ++static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; ++ ++static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; ++static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; ++ ++static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; ++static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; ++ ++static const int mt7988_tops_uart1_0_pins[] = { 28, 29 }; ++static int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; ++ ++static const int mt7988_tops_uart0_1_pins[] = { 30, 31 }; ++static int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; ++ ++static const int mt7988_tops_uart1_1_pins[] = { 36, 37 }; ++static int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; ++ ++static const int mt7988_uart0_pins[] = { 55, 56 }; ++static int mt7988_uart0_funcs[] = { 1, 1 }; ++ ++static const int mt7988_tops_uart0_2_pins[] = { 55, 56 }; ++static int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; ++ ++static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; ++static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; ++ ++static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; ++static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; ++ ++static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; ++static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; ++ ++static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; ++static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; ++ ++static const int mt7988_uart1_2_lite_pins[] = { 80, 81 }; ++static int mt7988_uart1_2_lite_funcs[] = { 1, 1 }; ++ ++static const int mt7988_tops_uart1_2_pins[] = { 80, 81 }; ++static int mt7988_tops_uart1_2_funcs[] = { 4, 4, }; ++ ++static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; ++static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; ++ ++static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; ++static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; ++ ++static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; ++static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; ++ ++/* udi */ ++static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; ++static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; ++ ++/* i2s */ ++static const int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 }; ++static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 }; ++ ++/* pcm */ ++static const int mt7988_pcm_pins[] = { 50, 51, 52, 53 }; ++static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 }; ++ ++/* led */ ++static const int mt7988_gbe0_led1_pins[] = { 58 }; ++static int mt7988_gbe0_led1_funcs[] = { 6 }; ++static const int mt7988_gbe1_led1_pins[] = { 59 }; ++static int mt7988_gbe1_led1_funcs[] = { 6 }; ++static const int mt7988_gbe2_led1_pins[] = { 60 }; ++static int mt7988_gbe2_led1_funcs[] = { 6 }; ++static const int mt7988_gbe3_led1_pins[] = { 61 }; ++static int mt7988_gbe3_led1_funcs[] = { 6 }; ++ ++static const int mt7988_2p5gbe_led1_pins[] = { 62 }; ++static int mt7988_2p5gbe_led1_funcs[] = { 6 }; ++ ++static const int mt7988_gbe0_led0_pins[] = { 64 }; ++static int mt7988_gbe0_led0_funcs[] = { 1 }; ++static const int mt7988_gbe1_led0_pins[] = { 65 }; ++static int mt7988_gbe1_led0_funcs[] = { 1 }; ++static const int mt7988_gbe2_led0_pins[] = { 66 }; ++static int mt7988_gbe2_led0_funcs[] = { 1 }; ++static const int mt7988_gbe3_led0_pins[] = { 67 }; ++static int mt7988_gbe3_led0_funcs[] = { 1 }; ++ ++static const int mt7988_2p5gbe_led0_pins[] = { 68 }; ++static int mt7988_2p5gbe_led0_funcs[] = { 1 }; ++ ++/* usb */ ++static const int mt7988_drv_vbus_p1_pins[] = { 63 }; ++static int mt7988_drv_vbus_p1_funcs[] = { 1 }; ++ ++static const int mt7988_drv_vbus_pins[] = { 79 }; ++static int mt7988_drv_vbus_funcs[] = { 1 }; ++ ++static const struct group_desc mt7988_groups[] = { ++ /* @GPIO(0,1,2,3): uart2 */ ++ PINCTRL_PIN_GROUP("uart2", mt7988_uart2), ++ /* @GPIO(0,1,2,3,4): tops_jtag0_0 */ ++ PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), ++ /* @GPIO(2,3): int_usxgmii */ ++ PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), ++ /* @GPIO(0,1,2,3,4): dfd */ ++ PINCTRL_PIN_GROUP("dfd", mt7988_dfd), ++ /* @GPIO(0,1): xfi_phy0_i2c0 */ ++ PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), ++ /* @GPIO(0,1): xfi_phy1_i2c0 */ ++ PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), ++ /* @GPIO(3,4): xfi_phy_pll_i2c0 */ ++ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), ++ /* @GPIO(3,4): xfi_phy_pll_i2c1 */ ++ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), ++ /* @GPIO(4): pwm7 */ ++ PINCTRL_PIN_GROUP("pwm7_0", mt7988_pwm7_0), ++ /* @GPIO(5,6) i2c0_0 */ ++ PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), ++ /* @GPIO(5,6) i2c1_sfp */ ++ PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), ++ /* @GPIO(5,6) xfi_pextp_phy0_i2c */ ++ PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), ++ /* @GPIO(5,6) xfi_pextp_phy1_i2c */ ++ PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), ++ /* @GPIO(5,6) mdc_mdio0 */ ++ PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), ++ /* @GPIO(7): pcie_wake_n0_0 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), ++ /* @GPIO(8): pcie_clk_req_n0_0 */ ++ PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), ++ /* @GPIO(9): pcie_wake_n3_0 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), ++ /* @GPIO(10): pcie_clk_req_n3 */ ++ PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), ++ /* @GPIO(10): pcie_clk_req_n0_1 */ ++ PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), ++ /* @GPIO(7,8) pcie_p0_phy_i2c */ ++ PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), ++ /* @GPIO(7,8) pcie_p1_phy_i2c */ ++ PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), ++ /* @GPIO(7,8) pcie_p2_phy_i2c */ ++ PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), ++ /* @GPIO(9,10) pcie_p3_phy_i2c */ ++ PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), ++ /* @GPIO(9,10) ckm_phy_i2c */ ++ PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), ++ /* @GPIO(11): pmic */ ++ PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), ++ /* @GPIO(12): watchdog */ ++ PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), ++ /* @GPIO(13): pcie_wake_n0_1 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), ++ /* @GPIO(14): pcie_wake_n3_1 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), ++ /* @GPIO(15,16) i2c0_1 */ ++ PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), ++ /* @GPIO(15,16) u30_phy_i2c0 */ ++ PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), ++ /* @GPIO(15,16) u32_phy_i2c0 */ ++ PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), ++ /* @GPIO(15,16) xfi_phy0_i2c1 */ ++ PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), ++ /* @GPIO(15,16) xfi_phy1_i2c1 */ ++ PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), ++ /* @GPIO(15,16) xfi_phy_pll_i2c2 */ ++ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), ++ /* @GPIO(17,18) i2c1_0 */ ++ PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), ++ /* @GPIO(17,18) u30_phy_i2c1 */ ++ PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), ++ /* @GPIO(17,18) u32_phy_i2c1 */ ++ PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), ++ /* @GPIO(17,18) xfi_phy_pll_i2c3 */ ++ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), ++ /* @GPIO(17,18) sgmii0_i2c */ ++ PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), ++ /* @GPIO(17,18) sgmii1_i2c */ ++ PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), ++ /* @GPIO(19): pcie_2l_0_pereset */ ++ PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), ++ /* @GPIO(20): pcie_1l_1_pereset */ ++ PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), ++ /* @GPIO(21): pwm1 */ ++ PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), ++ /* @GPIO(22,23) spi0_wp_hold */ ++ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), ++ /* @GPIO(24,25,26,27) spi0 */ ++ PINCTRL_PIN_GROUP("spi0", mt7988_spi0), ++ /* @GPIO(28,29,30,31) spi1 */ ++ PINCTRL_PIN_GROUP("spi1", mt7988_spi1), ++ /* @GPIO(32,33,34,35) spi2 */ ++ PINCTRL_PIN_GROUP("spi2", mt7988_spi2), ++ /* @GPIO(36,37) spi2_wp_hold */ ++ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), ++ /* @GPIO(22,23,24,25,26,27) snfi */ ++ PINCTRL_PIN_GROUP("snfi", mt7988_snfi), ++ /* @GPIO(22,23) tops_uart0_0 */ ++ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), ++ /* @GPIO(28,29,30,31) uart2_0 */ ++ PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), ++ /* @GPIO(32,33,34,35) uart1_0 */ ++ PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), ++ /* @GPIO(32,33,34,35) uart2_1 */ ++ PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), ++ /* @GPIO(28) net_wo0_uart_txd_0 */ ++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), ++ /* @GPIO(29) net_wo1_uart_txd_0 */ ++ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), ++ /* @GPIO(30) net_wo2_uart_txd_0 */ ++ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), ++ /* @GPIO(28,29) tops_uart1_0 */ ++ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), ++ /* @GPIO(30,31) tops_uart0_1 */ ++ PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), ++ /* @GPIO(36,37) tops_uart1_1 */ ++ PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), ++ /* @GPIO(32,33,34,35,36) udi */ ++ PINCTRL_PIN_GROUP("udi", mt7988_udi), ++ /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */ ++ PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), ++ /* @GPIO(32,33,34,35,36,37) sdcard */ ++ PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard), ++ /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */ ++ PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), ++ /* @GPIO(28,29) 2p5g_ext_mdio */ ++ PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), ++ /* @GPIO(30,31) gbe_ext_mdio */ ++ PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), ++ /* @GPIO(50,51,52,53,54) i2s */ ++ PINCTRL_PIN_GROUP("i2s", mt7988_i2s), ++ /* @GPIO(50,51,52,53) pcm */ ++ PINCTRL_PIN_GROUP("pcm", mt7988_pcm), ++ /* @GPIO(55,56) uart0 */ ++ PINCTRL_PIN_GROUP("uart0", mt7988_uart0), ++ /* @GPIO(55,56) tops_uart0_2 */ ++ PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), ++ /* @GPIO(50,51,52,53) uart2_2 */ ++ PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), ++ /* @GPIO(50,51,52,53,54) wo0_jtag */ ++ PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), ++ /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */ ++ PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), ++ /* @GPIO(50,51,52,53,54) wo2_jtag */ ++ PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), ++ /* @GPIO(57) pwm0 */ ++ PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), ++ /* @GPIO(58) pwm2_0 */ ++ PINCTRL_PIN_GROUP("pwm2_0", mt7988_pwm2_0), ++ /* @GPIO(59) pwm3_0 */ ++ PINCTRL_PIN_GROUP("pwm3_0", mt7988_pwm3_0), ++ /* @GPIO(60) pwm4_0 */ ++ PINCTRL_PIN_GROUP("pwm4_0", mt7988_pwm4_0), ++ /* @GPIO(61) pwm5_0 */ ++ PINCTRL_PIN_GROUP("pwm5_0", mt7988_pwm5_0), ++ /* @GPIO(58,59,60,61,62) jtag */ ++ PINCTRL_PIN_GROUP("jtag", mt7988_jtag), ++ /* @GPIO(58,59,60,61,62) tops_jtag0_1 */ ++ PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), ++ /* @GPIO(58,59,60,61) uart2_3 */ ++ PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), ++ /* @GPIO(58,59,60,61) uart1_1 */ ++ PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), ++ /* @GPIO(58,59,60,61) gbe_led1 */ ++ PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1), ++ PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1), ++ PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1), ++ PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1), ++ /* @GPIO(62) pwm6_0 */ ++ PINCTRL_PIN_GROUP("pwm6_0", mt7988_pwm6_0), ++ /* @GPIO(62) 2p5gbe_led1 */ ++ PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), ++ /* @GPIO(64,65,66,67) gbe_led0 */ ++ PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0), ++ PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0), ++ PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0), ++ PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0), ++ /* @GPIO(68) 2p5gbe_led0 */ ++ PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), ++ /* @GPIO(63) drv_vbus_p1 */ ++ PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), ++ /* @GPIO(63) pcie_clk_req_n2_1 */ ++ PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), ++ /* @GPIO(69, 70) mdc_mdio1 */ ++ PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), ++ /* @GPIO(69, 70) i2c1_2 */ ++ PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), ++ /* @GPIO(69) pwm6 */ ++ PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), ++ /* @GPIO(70) pwm7 */ ++ PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), ++ /* @GPIO(69,70) i2c2_0 */ ++ PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), ++ /* @GPIO(71,72) i2c2_1 */ ++ PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), ++ /* @GPIO(73) pcie_2l_1_pereset */ ++ PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), ++ /* @GPIO(74) pcie_1l_0_pereset */ ++ PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), ++ /* @GPIO(75) pcie_wake_n1_0 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), ++ /* @GPIO(76) pcie_clk_req_n1 */ ++ PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), ++ /* @GPIO(77) pcie_wake_n2_0 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), ++ /* @GPIO(78) pcie_clk_req_n2_0 */ ++ PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), ++ /* @GPIO(79) drv_vbus */ ++ PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), ++ /* @GPIO(79) pcie_wake_n2_1 */ ++ PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), ++ /* @GPIO(80,81,82,83) uart1_2 */ ++ PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), ++ /* @GPIO(80,81) uart1_2_lite */ ++ PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite), ++ /* @GPIO(80) pwm2 */ ++ PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), ++ /* @GPIO(81) pwm3 */ ++ PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), ++ /* @GPIO(82) pwm4 */ ++ PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), ++ /* @GPIO(83) pwm5 */ ++ PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), ++ /* @GPIO(80) net_wo0_uart_txd_0 */ ++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), ++ /* @GPIO(81) net_wo1_uart_txd_0 */ ++ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), ++ /* @GPIO(82) net_wo2_uart_txd_0 */ ++ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), ++ /* @GPIO(80,81) tops_uart1_2 */ ++ PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), ++ /* @GPIO(80) net_wo0_uart_txd_1 */ ++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), ++ /* @GPIO(81) net_wo1_uart_txd_1 */ ++ PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), ++ /* @GPIO(82) net_wo2_uart_txd_1 */ ++ PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), ++}; ++ ++/* Joint those groups owning the same capability in user point of view which ++ * allows that people tend to use through the device tree. ++ */ ++static const char * const mt7988_jtag_groups[] = { ++ "tops_jtag0_0", "wo0_jtag", "wo1_jtag", ++ "wo2_jtag", "jtag", "tops_jtag0_1", ++}; ++static const char * const mt7988_int_usxgmii_groups[] = { ++ "int_usxgmii", ++}; ++static const char * const mt7988_pwm_groups[] = { ++ "pwm0", "pwm1", "pwm2", "pwm2_0", "pwm3", "pwm3_0", "pwm4", "pwm4_0", ++ "pwm5", "pwm5_0", "pwm6", "pwm6_0", "pwm7", "pwm7_0", ++ ++}; ++static const char * const mt7988_dfd_groups[] = { ++ "dfd", ++}; ++static const char * const mt7988_i2c_groups[] = { ++ "xfi_phy0_i2c0", ++ "xfi_phy1_i2c0", ++ "xfi_phy_pll_i2c0", ++ "xfi_phy_pll_i2c1", ++ "i2c0_0", ++ "i2c1_sfp", ++ "xfi_pextp_phy0_i2c", ++ "xfi_pextp_phy1_i2c", ++ "i2c0_1", ++ "u30_phy_i2c0", ++ "u32_phy_i2c0", ++ "xfi_phy0_i2c1", ++ "xfi_phy1_i2c1", ++ "xfi_phy_pll_i2c2", ++ "i2c1_0", ++ "u30_phy_i2c1", ++ "u32_phy_i2c1", ++ "xfi_phy_pll_i2c3", ++ "sgmii0_i2c", ++ "sgmii1_i2c", ++ "i2c1_2", ++ "i2c2_0", ++ "i2c2_1", ++}; ++static const char * const mt7988_ethernet_groups[] = { ++ "mdc_mdio0", ++ "2p5g_ext_mdio", ++ "gbe_ext_mdio", ++ "mdc_mdio1", ++}; ++static const char * const mt7988_pcie_groups[] = { ++ "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", ++ "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", ++ "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", ++ "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset", ++ "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset", ++ "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1", ++ "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", ++ "pcie_clk_req_n0_1" ++}; ++static const char * const mt7988_pmic_groups[] = { ++ "pmic", ++}; ++static const char * const mt7988_wdt_groups[] = { ++ "watchdog", ++}; ++static const char * const mt7988_spi_groups[] = { ++ "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", ++}; ++static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", ++ "emmc_51" }; ++static const char * const mt7988_uart_groups[] = { ++ "uart2", ++ "tops_uart0_0", ++ "uart2_0", ++ "uart1_0", ++ "uart2_1", ++ "net_wo0_uart_txd_0", ++ "net_wo1_uart_txd_0", ++ "net_wo2_uart_txd_0", ++ "tops_uart1_0", ++ "ops_uart0_1", ++ "ops_uart1_1", ++ "uart0", ++ "tops_uart0_2", ++ "uart1_1", ++ "uart2_3", ++ "uart1_2", ++ "uart1_2_lite", ++ "tops_uart1_2", ++ "net_wo0_uart_txd_1", ++ "net_wo1_uart_txd_1", ++ "net_wo2_uart_txd_1", ++}; ++static const char * const mt7988_udi_groups[] = { ++ "udi", ++}; ++static const char * const mt7988_audio_groups[] = { ++ "i2s", "pcm", ++}; ++static const char * const mt7988_led_groups[] = { ++ "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", ++ "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", ++ "wf5g_led0", "wf5g_led1", ++}; ++static const char * const mt7988_usb_groups[] = { ++ "drv_vbus", ++ "drv_vbus_p1", ++}; ++ ++static const struct function_desc mt7988_functions[] = { ++ { { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) }, ++ NULL }, ++ { { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) }, ++ NULL }, ++ { { "int_usxgmii", mt7988_int_usxgmii_groups, ++ ARRAY_SIZE(mt7988_int_usxgmii_groups) }, ++ NULL }, ++ { { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) }, NULL }, ++ { { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) }, NULL }, ++ { { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) }, NULL }, ++ { { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) }, ++ NULL }, ++ { { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) }, ++ NULL }, ++ { { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) }, ++ NULL }, ++ { { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) }, ++ NULL }, ++ { { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) }, NULL }, ++ { { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) }, ++ NULL }, ++ { { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) }, ++ NULL }, ++ { { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) }, NULL }, ++ { { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) }, NULL }, ++ { { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) }, NULL }, ++}; ++ ++static const struct mtk_eint_hw mt7988_eint_hw = { ++ .port_mask = 7, ++ .ports = 7, ++ .ap_num = ARRAY_SIZE(mt7988_pins), ++ .db_cnt = 16, ++}; ++ ++static const char * const mt7988_pinctrl_register_base_names[] = { ++ "gpio", "iocfg_tr", "iocfg_br", ++ "iocfg_rb", "iocfg_lb", "iocfg_tl", ++}; ++ ++static const struct mtk_pin_soc mt7988_data = { ++ .reg_cal = mt7988_reg_cals, ++ .pins = mt7988_pins, ++ .npins = ARRAY_SIZE(mt7988_pins), ++ .grps = mt7988_groups, ++ .ngrps = ARRAY_SIZE(mt7988_groups), ++ .funcs = mt7988_functions, ++ .nfuncs = ARRAY_SIZE(mt7988_functions), ++ .eint_hw = &mt7988_eint_hw, ++ .gpio_m = 0, ++ .ies_present = false, ++ .base_names = mt7988_pinctrl_register_base_names, ++ .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), ++ .bias_disable_set = mtk_pinconf_bias_disable_set, ++ .bias_disable_get = mtk_pinconf_bias_disable_get, ++ .bias_set = mtk_pinconf_bias_set, ++ .bias_get = mtk_pinconf_bias_get, ++ .pull_type = mt7988_pull_type, ++ .bias_set_combo = mtk_pinconf_bias_set_combo, ++ .bias_get_combo = mtk_pinconf_bias_get_combo, ++ .drive_set = mtk_pinconf_drive_set_rev1, ++ .drive_get = mtk_pinconf_drive_get_rev1, ++ .adv_pull_get = mtk_pinconf_adv_pull_get, ++ .adv_pull_set = mtk_pinconf_adv_pull_set, ++}; ++ ++static const struct of_device_id mt7988_pinctrl_of_match[] = { ++ { .compatible = "mediatek,mt7988-pinctrl" }, ++ {} ++}; ++ ++static int mt7988_pinctrl_probe(struct platform_device *pdev) ++{ ++ return mtk_moore_pinctrl_probe(pdev, &mt7988_data); ++} ++ ++static struct platform_driver mt7988_pinctrl_driver = { ++ .driver = { ++ .name = "mt7988-pinctrl", ++ .of_match_table = mt7988_pinctrl_of_match, ++ }, ++ .probe = mt7988_pinctrl_probe, ++}; ++ ++static int __init mt7988_pinctrl_init(void) ++{ ++ return platform_driver_register(&mt7988_pinctrl_driver); ++} ++arch_initcall(mt7988_pinctrl_init); diff --git a/target/linux/mediatek/patches-6.12/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch b/target/linux/mediatek/patches-6.12/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch new file mode 100644 index 0000000000..e615e39345 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch @@ -0,0 +1,41 @@ +From 0e18b099672160698dfbd7c3c82e03e011c907e6 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Wed, 8 Jan 2025 22:52:44 +0100 +Subject: [PATCH] pinctrl: mediatek: Drop mtk_pinconf_bias_set_pd() + +This function is unused and causing compile errors, delete it. + +Reported-by: Stephen Rothwell +Link: https://lore.kernel.org/linux-next/20250106164630.4447cd0d@canb.auug.org.au/ +Signed-off-by: Linus Walleij +--- + .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 18 ------------------ + 1 file changed, 18 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +@@ -599,24 +599,6 @@ static int mtk_pinconf_bias_set_pu_pd(st + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); + } + +-static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw, +- const struct mtk_pin_desc *desc, +- u32 pullup, u32 arg) +-{ +- int err, pd; +- +- if (arg != MTK_DISABLE && arg != MTK_ENABLE) +- return -EINVAL; +- +- if (arg == MTK_DISABLE || pullup) +- pd = 0; +- else if (!pullup) +- pd = 1; +- +- return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); +- +-} +- + static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, + u32 pullup, u32 arg) diff --git a/target/linux/mediatek/patches-6.12/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch b/target/linux/mediatek/patches-6.12/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch new file mode 100644 index 0000000000..2c0afbe01c --- /dev/null +++ b/target/linux/mediatek/patches-6.12/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch @@ -0,0 +1,71 @@ +From 52e2ca3be4b6d451fef0a2cd337157dd021b830f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 5 Jun 2024 10:54:33 +0200 +Subject: [PATCH 01/32] arm64: dts: mediatek: mt7988: add UART controllers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +MT7988 has three on-SoC UART controllers that support M16C450 and +M16550A modes. + +Signed-off-by: Rafał Miłecki +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20240605085433.26513-2-zajec5@gmail.com +Signed-off-by: Matthias Brugger +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 35 ++++++++++++++++++++++- + 1 file changed, 34 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -86,7 +86,7 @@ + #clock-cells = <1>; + }; + +- clock-controller@1001b000 { ++ topckgen: clock-controller@1001b000 { + compatible = "mediatek,mt7988-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; +@@ -124,6 +124,39 @@ + status = "disabled"; + }; + ++ serial@11000000 { ++ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; ++ reg = <0 0x11000000 0 0x100>; ++ interrupts = ; ++ interrupt-names = "uart", "wakeup"; ++ clocks = <&topckgen CLK_TOP_UART_SEL>, ++ <&infracfg CLK_INFRA_52M_UART0_CK>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ ++ serial@11000100 { ++ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; ++ reg = <0 0x11000100 0 0x100>; ++ interrupts = ; ++ interrupt-names = "uart", "wakeup"; ++ clocks = <&topckgen CLK_TOP_UART_SEL>, ++ <&infracfg CLK_INFRA_52M_UART1_CK>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ ++ serial@11000200 { ++ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; ++ reg = <0 0x11000200 0 0x100>; ++ interrupts = ; ++ interrupt-names = "uart", "wakeup"; ++ clocks = <&topckgen CLK_TOP_UART_SEL>, ++ <&infracfg CLK_INFRA_52M_UART2_CK>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ + i2c@11003000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, diff --git a/target/linux/mediatek/patches-6.12/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch b/target/linux/mediatek/patches-6.12/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch new file mode 100644 index 0000000000..bf4e7a3b63 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch @@ -0,0 +1,35 @@ +From 390529e00d5586eb6d7f4c33c23dee7f43ac14e7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Thu, 13 Jun 2024 21:59:33 +0200 +Subject: [PATCH 02/32] arm64: dts: mediatek: mt7988: add efuse block +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +MT7988 (AKA MediaTek Filogic 880) uses efuse for storing calibration +data. + +Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20240613195933.31089-2-zajec5@gmail.com +Signed-off-by: Matthias Brugger +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -234,6 +234,13 @@ + #clock-cells = <1>; + }; + ++ efuse@11f50000 { ++ compatible = "mediatek,mt7988-efuse", "mediatek,efuse"; ++ reg = <0 0x11f50000 0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ + clock-controller@15000000 { + compatible = "mediatek,mt7988-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch b/target/linux/mediatek/patches-6.12/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch new file mode 100644 index 0000000000..90ec3186eb --- /dev/null +++ b/target/linux/mediatek/patches-6.12/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch @@ -0,0 +1,85 @@ +From a01cc71a8c55e7fc12cb37109953ad9c58a12d4f Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 09:54:29 +0100 +Subject: [PATCH 03/32] arm64: dts: mediatek: mt7988: Add pinctrl support + +Add mt7988a pinctrl node. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217085435.9586-5-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 54 +++++++++++++++++++++++ + 1 file changed, 54 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -3,6 +3,7 @@ + #include + #include + #include ++#include + + / { + compatible = "mediatek,mt7988a"; +@@ -105,6 +106,59 @@ + #clock-cells = <1>; + }; + ++ pio: pinctrl@1001f000 { ++ compatible = "mediatek,mt7988-pinctrl"; ++ reg = <0 0x1001f000 0 0x1000>, ++ <0 0x11c10000 0 0x1000>, ++ <0 0x11d00000 0 0x1000>, ++ <0 0x11d20000 0 0x1000>, ++ <0 0x11e00000 0 0x1000>, ++ <0 0x11f00000 0 0x1000>, ++ <0 0x1000b000 0 0x1000>; ++ reg-names = "gpio", "iocfg_tr", ++ "iocfg_br", "iocfg_rb", ++ "iocfg_lb", "iocfg_tl", "eint"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pio 0 0 84>; ++ interrupt-controller; ++ interrupts = ; ++ interrupt-parent = <&gic>; ++ #interrupt-cells = <2>; ++ ++ pcie0_pins: pcie0-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", ++ "pcie_wake_n0_0"; ++ }; ++ }; ++ ++ pcie1_pins: pcie1-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", ++ "pcie_wake_n1_0"; ++ }; ++ }; ++ ++ pcie2_pins: pcie2-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", ++ "pcie_wake_n2_0"; ++ }; ++ }; ++ ++ pcie3_pins: pcie3-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", ++ "pcie_wake_n3_0"; ++ }; ++ }; ++ }; ++ + pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch b/target/linux/mediatek/patches-6.12/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch new file mode 100644 index 0000000000..043530c994 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch @@ -0,0 +1,37 @@ +From b3bb498ff23f5bcaa95614e0f8c9176690af8acb Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:15 +0100 +Subject: [PATCH 04/32] arm64: dts: mediatek: mt7988: Add reserved memory + +Add memory range handled by ATF to not be touched by linux kernel. +ATF is SoC specific and not board-specific so add it to mt7988.dtsi. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-2-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -62,6 +62,18 @@ + method = "smc"; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ ++ secmon@43000000 { ++ reg = <0 0x43000000 0 0x50000>; ++ no-map; ++ }; ++ }; ++ + soc { + compatible = "simple-bus"; + ranges; diff --git a/target/linux/mediatek/patches-6.12/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch b/target/linux/mediatek/patches-6.12/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch new file mode 100644 index 0000000000..a52f443d83 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch @@ -0,0 +1,52 @@ +From de6ba1a3ef621762394e841888de3e0ed127e20a Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:16 +0100 +Subject: [PATCH 05/32] arm64: dts: mediatek: mt7988: Add mmc support + +Add devicetree node for MMC controller. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-3-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 21 ++++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -112,7 +112,7 @@ + #reset-cells = <1>; + }; + +- clock-controller@1001e000 { ++ apmixedsys: clock-controller@1001e000 { + compatible = "mediatek,mt7988-apmixedsys"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; +@@ -293,6 +293,25 @@ + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + }; + ++ mmc0: mmc@11230000 { ++ compatible = "mediatek,mt7988-mmc"; ++ reg = <0 0x11230000 0 0x1000>, ++ <0 0x11D60000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_MSDC400>, ++ <&infracfg CLK_INFRA_MSDC2_HCK>, ++ <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, ++ <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; ++ assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, ++ <&topckgen CLK_TOP_EMMC_400M_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, ++ <&apmixedsys CLK_APMIXED_MSDCPLL>; ++ clock-names = "source", "hclk", "axi_cg", "ahb_cg"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch b/target/linux/mediatek/patches-6.12/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch new file mode 100644 index 0000000000..b878d20f2e --- /dev/null +++ b/target/linux/mediatek/patches-6.12/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch @@ -0,0 +1,62 @@ +From f07e0e093c42736df56f4830179c19f48f8b0725 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:17 +0100 +Subject: [PATCH 06/32] arm64: dts: mediatek: mt7988: Add lvts node + +Add Low Voltage Thermal Sensor (LVTS) node for mt7988 SoC. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-4-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -4,6 +4,7 @@ + #include + #include + #include ++#include + + / { + compatible = "mediatek,mt7988a"; +@@ -97,6 +98,7 @@ + compatible = "mediatek,mt7988-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; ++ #reset-cells = <1>; + }; + + topckgen: clock-controller@1001b000 { +@@ -265,6 +267,17 @@ + status = "disabled"; + }; + ++ lvts: lvts@1100a000 { ++ compatible = "mediatek,mt7988-lvts-ap"; ++ #thermal-sensor-cells = <1>; ++ reg = <0 0x1100a000 0 0x1000>; ++ clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; ++ interrupts = ; ++ resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; ++ nvmem-cells = <&lvts_calibration>; ++ nvmem-cell-names = "lvts-calib-data-1"; ++ }; ++ + usb@11190000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, +@@ -324,6 +337,10 @@ + reg = <0 0x11f50000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ lvts_calibration: calib@918 { ++ reg = <0x918 0x28>; ++ }; + }; + + clock-controller@15000000 { diff --git a/target/linux/mediatek/patches-6.12/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch b/target/linux/mediatek/patches-6.12/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch new file mode 100644 index 0000000000..e0ff078164 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch @@ -0,0 +1,39 @@ +From 122ed9fc41b948d79ac357f95f5438a4bd6786b8 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:18 +0100 +Subject: [PATCH 07/32] arm64: dts: mediatek: mt7988: Add thermal-zone + +Add basic thermal-zone node. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-5-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -358,6 +358,21 @@ + }; + }; + ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <1000>; ++ thermal-sensors = <&lvts 0>; ++ trips { ++ cpu_trip_crit: crit { ++ temperature = <125000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; diff --git a/target/linux/mediatek/patches-6.12/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch b/target/linux/mediatek/patches-6.12/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch new file mode 100644 index 0000000000..551dca3c09 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch @@ -0,0 +1,31 @@ +From 7fa08d530548ed57752703e9f011eeeb809ef9b0 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:20 +0100 +Subject: [PATCH 08/32] arm64: dts: mediatek: mt7988: Add mcu-sys node for cpu + +In preparation for adding support for CPU DVFS and clock tables for it, +add the MCUSYS clock controller node. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-7-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -192,6 +192,12 @@ + status = "disabled"; + }; + ++ mcusys: mcusys@100e0000 { ++ compatible = "mediatek,mt7988-mcusys", "syscon"; ++ reg = <0 0x100e0000 0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ + serial@11000000 { + compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; + reg = <0 0x11000000 0 0x100>; diff --git a/target/linux/mediatek/patches-6.12/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch b/target/linux/mediatek/patches-6.12/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch new file mode 100644 index 0000000000..e2bec750e4 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch @@ -0,0 +1,84 @@ +From b10331c8faa1208c61fb98d9b65da2828e239113 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:21 +0100 +Subject: [PATCH 09/32] arm64: dts: mediatek: mt7988: Add CPU OPP table for + clock scaling + +Add operating points defining frequency/voltages of cpu cores. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-8-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 38 +++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -21,6 +21,10 @@ + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; ++ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, ++ <&topckgen CLK_TOP_XTAL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points-v2 = <&cluster0_opp>; + }; + + cpu@1 { +@@ -28,6 +32,10 @@ + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; ++ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, ++ <&topckgen CLK_TOP_XTAL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points-v2 = <&cluster0_opp>; + }; + + cpu@2 { +@@ -35,6 +43,10 @@ + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; ++ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, ++ <&topckgen CLK_TOP_XTAL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points-v2 = <&cluster0_opp>; + }; + + cpu@3 { +@@ -42,6 +54,32 @@ + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; ++ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, ++ <&topckgen CLK_TOP_XTAL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points-v2 = <&cluster0_opp>; ++ }; ++ ++ cluster0_opp: opp-table-0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-1100000000 { ++ opp-hz = /bits/ 64 <1100000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-1500000000 { ++ opp-hz = /bits/ 64 <1500000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <900000>; ++ }; + }; + }; + diff --git a/target/linux/mediatek/patches-6.12/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch b/target/linux/mediatek/patches-6.12/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch new file mode 100644 index 0000000000..f65d23bc0a --- /dev/null +++ b/target/linux/mediatek/patches-6.12/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch @@ -0,0 +1,34 @@ +From 39bb12c26f556046e55f3638e2e4184bfbfd0564 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:22 +0100 +Subject: [PATCH 10/32] arm64: dts: mediatek: mt7988: Disable usb controllers + by default + +The controllers should be enabled at board level if used. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-9-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -334,6 +334,7 @@ + <&infracfg CLK_INFRA_133M_USB_HCK>, + <&infracfg CLK_INFRA_USB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; ++ status = "disabled"; + }; + + usb@11200000 { +@@ -348,6 +349,7 @@ + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; ++ status = "disabled"; + }; + + mmc0: mmc@11230000 { diff --git a/target/linux/mediatek/patches-6.12/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch b/target/linux/mediatek/patches-6.12/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch new file mode 100644 index 0000000000..c53db06c39 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch @@ -0,0 +1,59 @@ +From 46d056b6c2376d3ef866f9ab5212879c97588892 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:23 +0100 +Subject: [PATCH 11/32] arm64: dts: mediatek: mt7988: Add t-phy for ssusb1 + +USB controller needs phys for working properly. +On mt7988 ssusb0 uses a xs-phy, ssusb uses t-phy. +For now add the t-phy for ssusb1. We can reuse the mt7986 compatible +here. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-10-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 25 +++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -349,6 +349,8 @@ + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; ++ phys = <&tphyu2port0 PHY_TYPE_USB2>, ++ <&tphyu3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + +@@ -371,6 +373,29 @@ + status = "disabled"; + }; + ++ t-phy@11c50000 { ++ compatible = "mediatek,mt7986-tphy", ++ "mediatek,generic-tphy-v2"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ tphyu2port0: usb-phy@11c50000 { ++ reg = <0 0x11c50000 0 0x700>; ++ clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ }; ++ ++ tphyu3port0: usb-phy@11c50700 { ++ reg = <0 0x11c50700 0 0x900>; ++ clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ }; ++ }; ++ + clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch b/target/linux/mediatek/patches-6.12/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch new file mode 100644 index 0000000000..fe27e5223c --- /dev/null +++ b/target/linux/mediatek/patches-6.12/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch @@ -0,0 +1,176 @@ +From aac2eb27ee500ca2828fe0fd1895ec6f9ef83787 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:24 +0100 +Subject: [PATCH 12/32] arm64: dts: mediatek: mt7988: Add pcie nodes + +Add pcie controllers for mt7988. Reuse mt7986 compatible. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-11-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 152 ++++++++++++++++++++++ + 1 file changed, 152 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -373,6 +373,158 @@ + status = "disabled"; + }; + ++ pcie@11280000 { ++ compatible = "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11280000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <3>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x81000000 0x00 0x20000000 0x00 ++ 0x20000000 0x00 0x00200000>, ++ <0x82000000 0x00 0x20200000 0x00 ++ 0x20200000 0x00 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_pins>; ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc2 0>, ++ <0 0 0 2 &pcie_intc2 1>, ++ <0 0 0 3 &pcie_intc2 2>, ++ <0 0 0 4 &pcie_intc2 3>; ++ pcie_intc2: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie@11290000 { ++ compatible = "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11290000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <2>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x81000000 0x00 0x28000000 0x00 ++ 0x28000000 0x00 0x00200000>, ++ <0x82000000 0x00 0x28200000 0x00 ++ 0x28200000 0x00 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_pins>; ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc3 0>, ++ <0 0 0 2 &pcie_intc3 1>, ++ <0 0 0 3 &pcie_intc3 2>, ++ <0 0 0 4 &pcie_intc3 3>; ++ pcie_intc3: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie@11300000 { ++ compatible = "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11300000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <0>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x81000000 0x00 0x30000000 0x00 ++ 0x30000000 0x00 0x00200000>, ++ <0x82000000 0x00 0x30200000 0x00 ++ 0x30200000 0x00 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_pins>; ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc0 0>, ++ <0 0 0 2 &pcie_intc0 1>, ++ <0 0 0 3 &pcie_intc0 2>, ++ <0 0 0 4 &pcie_intc0 3>; ++ pcie_intc0: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie@11310000 { ++ compatible = "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11310000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <1>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x81000000 0x00 0x38000000 0x00 ++ 0x38000000 0x00 0x00200000>, ++ <0x82000000 0x00 0x38200000 0x00 ++ 0x38200000 0x00 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_pins>; ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc1 0>, ++ <0 0 0 2 &pcie_intc1 1>, ++ <0 0 0 3 &pcie_intc1 2>, ++ <0 0 0 4 &pcie_intc1 3>; ++ pcie_intc1: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ + t-phy@11c50000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; diff --git a/target/linux/mediatek/patches-6.12/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch b/target/linux/mediatek/patches-6.12/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch new file mode 100644 index 0000000000..6f0080e6ec --- /dev/null +++ b/target/linux/mediatek/patches-6.12/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch @@ -0,0 +1,211 @@ +From 6b116c43782a153bcde18bd54d3220d81b476859 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 09:54:30 +0100 +Subject: [PATCH 13/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add pinctrl + subnodes for bpi-r4 + +Add board specific pinctrl configurations on Bananapi R4. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217085435.9586-6-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 189 ++++++++++++++++++ + 1 file changed, 189 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -9,3 +9,192 @@ + model = "Banana Pi BPI-R4"; + chassis-type = "embedded"; + }; ++ ++&pio { ++ mdio0_pins: mdio0-pins { ++ mux { ++ function = "eth"; ++ groups = "mdc_mdio0"; ++ }; ++ ++ conf { ++ pins = "SMI_0_MDC", "SMI_0_MDIO"; ++ drive-strength = <8>; ++ }; ++ }; ++ ++ i2c0_pins: i2c0-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c0_1"; ++ }; ++ }; ++ ++ i2c1_pins: i2c1-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_0"; ++ }; ++ }; ++ ++ i2c1_sfp_pins: i2c1-sfp-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_sfp"; ++ }; ++ }; ++ ++ i2c2_0_pins: i2c2-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_0"; ++ }; ++ }; ++ ++ i2c2_1_pins: i2c2-g1-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_1"; ++ }; ++ }; ++ ++ gbe0_led0_pins: gbe0-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe0_led0"; ++ }; ++ }; ++ ++ gbe1_led0_pins: gbe1-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe1_led0"; ++ }; ++ }; ++ ++ gbe2_led0_pins: gbe2-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe2_led0"; ++ }; ++ }; ++ ++ gbe3_led0_pins: gbe3-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe3_led0"; ++ }; ++ }; ++ ++ gbe0_led1_pins: gbe0-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe0_led1"; ++ }; ++ }; ++ ++ gbe1_led1_pins: gbe1-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe1_led1"; ++ }; ++ }; ++ ++ gbe2_led1_pins: gbe2-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe2_led1"; ++ }; ++ }; ++ ++ gbe3_led1_pins: gbe3-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe3_led1"; ++ }; ++ }; ++ ++ i2p5gbe_led0_pins: 2p5gbe-led0-pins { ++ mux { ++ function = "led"; ++ groups = "2p5gbe_led0"; ++ }; ++ }; ++ ++ i2p5gbe_led1_pins: 2p5gbe-led1-pins { ++ mux { ++ function = "led"; ++ groups = "2p5gbe_led1"; ++ }; ++ }; ++ ++ mmc0_pins_emmc_45: mmc0-emmc-45-pins { ++ mux { ++ function = "flash"; ++ groups = "emmc_45"; ++ }; ++ }; ++ ++ mmc0_pins_emmc_51: mmc0-emmc-51-pins { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ }; ++ ++ mmc0_pins_sdcard: mmc0-sdcard-pins { ++ mux { ++ function = "flash"; ++ groups = "sdcard"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0"; ++ }; ++ }; ++ ++ snfi_pins: snfi-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ ++ spi0_pins: spi0-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0"; ++ }; ++ }; ++ ++ spi0_flash_pins: spi0-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ }; ++ ++ spi1_pins: spi1-pins { ++ mux { ++ function = "spi"; ++ groups = "spi1"; ++ }; ++ }; ++ ++ spi2_pins: spi2-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2"; ++ }; ++ }; ++ ++ spi2_flash_pins: spi2-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2", "spi2_wp_hold"; ++ }; ++ }; ++}; diff --git a/target/linux/mediatek/patches-6.12/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch b/target/linux/mediatek/patches-6.12/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch new file mode 100644 index 0000000000..2ce47ed12a --- /dev/null +++ b/target/linux/mediatek/patches-6.12/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch @@ -0,0 +1,25 @@ +From 6b6f2f1ee88b8b5763f4112babbc9fc45a94999a Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:25 +0100 +Subject: [PATCH 14/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable watchdog + +Enable the watchdog on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-12-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -198,3 +198,7 @@ + }; + }; + }; ++ ++&watchdog { ++ status = "okay"; ++}; diff --git a/target/linux/mediatek/patches-6.12/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch b/target/linux/mediatek/patches-6.12/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch new file mode 100644 index 0000000000..fb383d041b --- /dev/null +++ b/target/linux/mediatek/patches-6.12/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch @@ -0,0 +1,48 @@ +From 72b0a6f181c5ca417405e594c80d724baee54813 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:26 +0100 +Subject: [PATCH 15/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add fixed + regulators for 1v8 and 3v3 + +Add regulator nodes used for mmc to Bananapi R4 board. +This board has 1 MMC controller used for SDMMC and eMMC where only one can +be used at one time, selected by hardware switches. SD uses 3v3 for both +supplies and emmc uses both regulators. +So defining both regulators in board dts and referencing them in the dt +overlay. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-13-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -8,6 +8,24 @@ + compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; + model = "Banana Pi BPI-R4"; + chassis-type = "embedded"; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; + }; + + &pio { diff --git a/target/linux/mediatek/patches-6.12/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch b/target/linux/mediatek/patches-6.12/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch new file mode 100644 index 0000000000..3273e7444c --- /dev/null +++ b/target/linux/mediatek/patches-6.12/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch @@ -0,0 +1,54 @@ +From 67511ea667d3c4da827588fd460772562d7b054e Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:28 +0100 +Subject: [PATCH 16/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add thermal + configuration + +Add additional thermal trips to Bananapi R4 board. +SoC only contains the critical trip. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-15-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 28 +++++++++++++++++++ + 1 file changed, 28 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -28,6 +28,34 @@ + }; + }; + ++&cpu_thermal { ++ trips { ++ cpu_trip_hot: hot { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ ++ cpu_trip_active_high: active-high { ++ temperature = <115000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_med: active-med { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_low: active-low { ++ temperature = <40000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++}; ++ + &pio { + mdio0_pins: mdio0-pins { + mux { diff --git a/target/linux/mediatek/patches-6.12/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch b/target/linux/mediatek/patches-6.12/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch new file mode 100644 index 0000000000..c1d872d1db --- /dev/null +++ b/target/linux/mediatek/patches-6.12/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch @@ -0,0 +1,41 @@ +From a9df5ed2333b01546b4f906e2f6fd21dd5b146aa Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:29 +0100 +Subject: [PATCH 17/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable serial0 + debug uart + +Enable the debug uart on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-16-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -245,6 +245,10 @@ + }; + }; + ++&serial0 { ++ status = "okay"; ++}; ++ + &watchdog { + status = "okay"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -236,7 +236,7 @@ + #clock-cells = <1>; + }; + +- serial@11000000 { ++ serial0: serial@11000000 { + compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; + reg = <0 0x11000000 0 0x100>; + interrupts = ; diff --git a/target/linux/mediatek/patches-6.12/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch b/target/linux/mediatek/patches-6.12/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch new file mode 100644 index 0000000000..d75b3e57ad --- /dev/null +++ b/target/linux/mediatek/patches-6.12/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch @@ -0,0 +1,29 @@ +From 3dfb0dcb194e3f32ed931747131be08bfc429522 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:30 +0100 +Subject: [PATCH 18/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add default UART + stdout + +Add chosen node on Bananapi R4 board with stdout and default bootargs. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-17-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -9,6 +9,10 @@ + model = "Banana Pi BPI-R4"; + chassis-type = "embedded"; + ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; diff --git a/target/linux/mediatek/patches-6.12/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch b/target/linux/mediatek/patches-6.12/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch new file mode 100644 index 0000000000..4f48edd412 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch @@ -0,0 +1,72 @@ +From 90d4eb65db14a3f2e776d2a8b1dc832e70198328 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:31 +0100 +Subject: [PATCH 19/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable I2C + controllers + +Enable the I2C0, I2C2 controllers found on the BananaPi R4 board. +Both controllers are not accessible from user and having fixed spare +devices. I2C0 have a pmic connected, I2C2 is used with I2C-multiplexer +for e.g. SFP cages. +The missing I2C1 is connected to GPIO header which can have either GPIO +mode or I2C mode. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-18-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 12 ++++++++++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 +++--- + 2 files changed, 15 insertions(+), 3 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -60,6 +60,18 @@ + }; + }; + ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_1_pins>; ++ status = "okay"; ++}; ++ + &pio { + mdio0_pins: mdio0-pins { + mux { +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -269,7 +269,7 @@ + status = "disabled"; + }; + +- i2c@11003000 { ++ i2c0: i2c@11003000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, + <0 0x10217080 0 0x80>; +@@ -283,7 +283,7 @@ + status = "disabled"; + }; + +- i2c@11004000 { ++ i2c1: i2c@11004000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11004000 0 0x1000>, + <0 0x10217100 0 0x80>; +@@ -297,7 +297,7 @@ + status = "disabled"; + }; + +- i2c@11005000 { ++ i2c2: i2c@11005000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11005000 0 0x1000>, + <0 0x10217180 0 0x80>; diff --git a/target/linux/mediatek/patches-6.12/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch b/target/linux/mediatek/patches-6.12/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch new file mode 100644 index 0000000000..117479b789 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch @@ -0,0 +1,74 @@ +From dde7d741329616025e4cfa350eb3935b495ae140 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:32 +0100 +Subject: [PATCH 20/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add PCA9545 I2C + Mux + +Bananapi R4 uses an i2c multiplexer for SFP slots, rtc and eeprom. +Add its node to the right i2c controller. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-19-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 41 +++++++++++++++++++ + 1 file changed, 41 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -2,6 +2,8 @@ + + /dts-v1/; + ++#include ++ + #include "mt7988a.dtsi" + + / { +@@ -70,6 +72,45 @@ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_1_pins>; + status = "okay"; ++ ++ pca9545: i2c-mux@70 { ++ compatible = "nxp,pca9545"; ++ reg = <0x70>; ++ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ pcf8563: rtc@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ }; ++ ++ eeprom@57 { ++ compatible = "atmel,24c02"; ++ reg = <0x57>; ++ size = <256>; ++ }; ++ ++ }; ++ ++ i2c_sfp1: i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ ++ i2c_sfp2: i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ }; ++ }; + }; + + &pio { diff --git a/target/linux/mediatek/patches-6.12/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch b/target/linux/mediatek/patches-6.12/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch new file mode 100644 index 0000000000..e16b30ef30 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch @@ -0,0 +1,41 @@ +From dfe00be85da20d9823d39775c92139c569a7960d Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:33 +0100 +Subject: [PATCH 21/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable t-phy for + ssusb1 + +Bananapi R4 uses t-phy for usb. Enable its node at board level. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-20-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -306,6 +306,10 @@ + status = "okay"; + }; + ++&tphy { ++ status = "okay"; ++}; ++ + &watchdog { + status = "okay"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -525,7 +525,7 @@ + }; + }; + +- t-phy@11c50000 { ++ tphy: t-phy@11c50000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; diff --git a/target/linux/mediatek/patches-6.12/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch b/target/linux/mediatek/patches-6.12/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch new file mode 100644 index 0000000000..d1892c6cc1 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/041-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-ssusb1-on-b.patch @@ -0,0 +1,41 @@ +From 2b03ef47273db52e0c0010e963c3626e6842204f Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:34 +0100 +Subject: [PATCH 22/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable ssusb1 on + bpi-r4 + +Enable usb on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-21-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -306,6 +306,10 @@ + status = "okay"; + }; + ++&ssusb1 { ++ status = "okay"; ++}; ++ + &tphy { + status = "okay"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -337,7 +337,7 @@ + status = "disabled"; + }; + +- usb@11200000 { ++ ssusb1: usb@11200000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; diff --git a/target/linux/mediatek/patches-6.12/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch b/target/linux/mediatek/patches-6.12/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch new file mode 100644 index 0000000000..4e24607e5d --- /dev/null +++ b/target/linux/mediatek/patches-6.12/042-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pwm.patch @@ -0,0 +1,40 @@ +From b074487a4180aeee440b61fc00a865fc2a4bd32a Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:35 +0100 +Subject: [PATCH 23/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable pwm + +Enable pwm on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-22-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -302,6 +302,10 @@ + }; + }; + ++&pwm { ++ status = "okay"; ++}; ++ + &serial0 { + status = "okay"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -211,7 +211,7 @@ + }; + }; + +- pwm@10048000 { ++ pwm: pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, diff --git a/target/linux/mediatek/patches-6.12/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch b/target/linux/mediatek/patches-6.12/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch new file mode 100644 index 0000000000..a25d235630 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/043-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-pcie.patch @@ -0,0 +1,83 @@ +From 72bc814e8609e8be59dff8bc6e0e185b5005ace8 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 17 Dec 2024 10:12:36 +0100 +Subject: [PATCH 24/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable pcie + +Enable the pci controllers on BPI-R4. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241217091238.16032-23-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 20 +++++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 8 ++++---- + 2 files changed, 24 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -113,6 +113,26 @@ + }; + }; + ++/* mPCIe SIM2 */ ++&pcie0 { ++ status = "okay"; ++}; ++ ++/* mPCIe SIM3 */ ++&pcie1 { ++ status = "okay"; ++}; ++ ++/* M.2 key-B SIM1 */ ++&pcie2 { ++ status = "okay"; ++}; ++ ++/* M.2 key-M SSD */ ++&pcie3 { ++ status = "okay"; ++}; ++ + &pio { + mdio0_pins: mdio0-pins { + mux { +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -373,7 +373,7 @@ + status = "disabled"; + }; + +- pcie@11280000 { ++ pcie2: pcie@11280000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; +@@ -411,7 +411,7 @@ + }; + }; + +- pcie@11290000 { ++ pcie3: pcie@11290000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; +@@ -449,7 +449,7 @@ + }; + }; + +- pcie@11300000 { ++ pcie0: pcie@11300000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; +@@ -487,7 +487,7 @@ + }; + }; + +- pcie@11310000 { ++ pcie1: pcie@11310000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; diff --git a/target/linux/mediatek/patches-6.12/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch b/target/linux/mediatek/patches-6.12/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch new file mode 100644 index 0000000000..26a5990b60 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/044-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-MediaTek-MT668.patch @@ -0,0 +1,96 @@ +From 84087157052afba2f61cea7c99ccabfe9681b643 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 20 Dec 2024 17:38:35 +0100 +Subject: [PATCH 25/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add MediaTek + MT6682A/RT5190A PMIC + +Bananapi R4 Board contains a MT6682A pmic which is compatible to rt5190a. +Add its node to the i2 controller. + +The BananaPi R4 board has a MediaTek MT6682A PMIC, a rebrand of the +Richtek RT5190A chip, connected to the I2C0 bus. + +Add the relevant node and, while at it, also configure the regulators +from this PMIC that are used on this board. + +Only Buck2/Buck3 voltage can be controlled by software. + +BUCK4 input is 5V from BUCK1 output, and the resistor (mapped to RP30/RP31 +on BPI-R4) configures BUCK4 output to 1.8V. +LDO input is 3.3V from 3.3VD, and the resistor (mapped to RP38/RP40 on +BPI-R4) configures LDO output to 1.8V. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241220163838.114786-2-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 50 +++++++++++++++++++ + 1 file changed, 50 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -3,6 +3,7 @@ + /dts-v1/; + + #include ++#include + + #include "mt7988a.dtsi" + +@@ -66,6 +67,55 @@ + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; ++ ++ rt5190a_64: rt5190a@64 { ++ compatible = "richtek,rt5190a"; ++ reg = <0x64>; ++ vin2-supply = <&rt5190_buck1>; ++ vin3-supply = <&rt5190_buck1>; ++ vin4-supply = <&rt5190_buck1>; ++ ++ regulators { ++ rt5190_buck1: buck1 { ++ regulator-name = "rt5190a-buck1"; ++ regulator-min-microvolt = <5090000>; ++ regulator-max-microvolt = <5090000>; ++ regulator-allowed-modes = ++ , ; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ buck2 { ++ regulator-name = "vcore"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ rt5190_buck3: buck3 { ++ regulator-name = "vproc"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ }; ++ buck4 { ++ regulator-name = "rt5190a-buck4"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-allowed-modes = ++ , ; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ldo { ++ regulator-name = "rt5190a-ldo"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ }; ++ }; + }; + + &i2c2 { diff --git a/target/linux/mediatek/patches-6.12/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch b/target/linux/mediatek/patches-6.12/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch new file mode 100644 index 0000000000..c605e90e5d --- /dev/null +++ b/target/linux/mediatek/patches-6.12/045-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-proc-supply-fo.patch @@ -0,0 +1,80 @@ +From c0a17ddd90c2094dfe4610b0d965db8a3b987e32 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 20 Dec 2024 17:38:36 +0100 +Subject: [PATCH 26/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add proc-supply + for cpus + +Add proc-supply property to cpus on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20241220163838.114786-3-linux@fw-web.de +Signed-off-by: AngeloGioacchino Del Regno +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 16 ++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 8 ++++---- + 2 files changed, 20 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -35,6 +35,22 @@ + }; + }; + ++&cpu0 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu1 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu2 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu3 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ + &cpu_thermal { + trips { + cpu_trip_hot: hot { +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -16,7 +16,7 @@ + #address-cells = <1>; + #size-cells = <0>; + +- cpu@0 { ++ cpu0: cpu@0 { + compatible = "arm,cortex-a73"; + reg = <0x0>; + device_type = "cpu"; +@@ -27,7 +27,7 @@ + operating-points-v2 = <&cluster0_opp>; + }; + +- cpu@1 { ++ cpu1: cpu@1 { + compatible = "arm,cortex-a73"; + reg = <0x1>; + device_type = "cpu"; +@@ -38,7 +38,7 @@ + operating-points-v2 = <&cluster0_opp>; + }; + +- cpu@2 { ++ cpu2: cpu@2 { + compatible = "arm,cortex-a73"; + reg = <0x2>; + device_type = "cpu"; +@@ -49,7 +49,7 @@ + operating-points-v2 = <&cluster0_opp>; + }; + +- cpu@3 { ++ cpu3: cpu@3 { + compatible = "arm,cortex-a73"; + reg = <0x3>; + device_type = "cpu"; diff --git a/target/linux/mediatek/patches-6.12/050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch b/target/linux/mediatek/patches-6.12/050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch new file mode 100644 index 0000000000..a543ecbaa3 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/050-v6.16-phy-mediatek-xsphy-support-type-switch-by-pericfg.patch @@ -0,0 +1,169 @@ +From b7ae3528a588a4006ff9c9cc581efa317df1c1ed Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 22 Apr 2025 15:24:29 +0200 +Subject: [PATCH] phy: mediatek: xsphy: support type switch by pericfg + +Patch from Sam Shih found in MediaTek SDK +released under GPL. + +Get syscon and use it to set the PHY type. +Extend support to PCIe and SGMII mode in addition to USB2 and USB3. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +--- + drivers/phy/mediatek/phy-mtk-xsphy.c | 85 +++++++++++++++++++++++++++- + 1 file changed, 84 insertions(+), 1 deletion(-) + +--- a/drivers/phy/mediatek/phy-mtk-xsphy.c ++++ b/drivers/phy/mediatek/phy-mtk-xsphy.c +@@ -11,10 +11,12 @@ + #include + #include + #include ++#include + #include + #include + #include + #include ++#include + + #include "phy-mtk-io.h" + +@@ -81,12 +83,22 @@ + #define XSP_SR_COEF_DIVISOR 1000 + #define XSP_FM_DET_CYCLE_CNT 1024 + ++/* PHY switch between pcie/usb3/sgmii */ ++#define USB_PHY_SWITCH_CTRL 0x0 ++#define RG_PHY_SW_TYPE GENMASK(3, 0) ++#define RG_PHY_SW_PCIE 0x0 ++#define RG_PHY_SW_USB3 0x1 ++#define RG_PHY_SW_SGMII 0x2 ++ + struct xsphy_instance { + struct phy *phy; + void __iomem *port_base; + struct clk *ref_clk; /* reference clock of anolog phy */ + u32 index; + u32 type; ++ struct regmap *type_sw; ++ u32 type_sw_reg; ++ u32 type_sw_index; + /* only for HQA test */ + int efuse_intr; + int efuse_tx_imp; +@@ -259,6 +271,10 @@ static void phy_parse_property(struct mt + inst->efuse_intr, inst->efuse_tx_imp, + inst->efuse_rx_imp); + break; ++ case PHY_TYPE_PCIE: ++ case PHY_TYPE_SGMII: ++ /* nothing to do */ ++ break; + default: + dev_err(xsphy->dev, "incompatible phy type\n"); + return; +@@ -305,6 +321,62 @@ static void u3_phy_props_set(struct mtk_ + RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp); + } + ++/* type switch for usb3/pcie/sgmii */ ++static int phy_type_syscon_get(struct xsphy_instance *instance, ++ struct device_node *dn) ++{ ++ struct of_phandle_args args; ++ int ret; ++ ++ /* type switch function is optional */ ++ if (!of_property_present(dn, "mediatek,syscon-type")) ++ return 0; ++ ++ ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type", ++ 2, 0, &args); ++ if (ret) ++ return ret; ++ ++ instance->type_sw_reg = args.args[0]; ++ instance->type_sw_index = args.args[1] & 0x3; /* <=3 */ ++ instance->type_sw = syscon_node_to_regmap(args.np); ++ of_node_put(args.np); ++ dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n", ++ instance->type_sw_reg, instance->type_sw_index); ++ ++ return PTR_ERR_OR_ZERO(instance->type_sw); ++} ++ ++static int phy_type_set(struct xsphy_instance *instance) ++{ ++ int type; ++ u32 offset; ++ ++ if (!instance->type_sw) ++ return 0; ++ ++ switch (instance->type) { ++ case PHY_TYPE_USB3: ++ type = RG_PHY_SW_USB3; ++ break; ++ case PHY_TYPE_PCIE: ++ type = RG_PHY_SW_PCIE; ++ break; ++ case PHY_TYPE_SGMII: ++ type = RG_PHY_SW_SGMII; ++ break; ++ case PHY_TYPE_USB2: ++ default: ++ return 0; ++ } ++ ++ offset = instance->type_sw_index * BITS_PER_BYTE; ++ regmap_update_bits(instance->type_sw, instance->type_sw_reg, ++ RG_PHY_SW_TYPE << offset, type << offset); ++ ++ return 0; ++} ++ + static int mtk_phy_init(struct phy *phy) + { + struct xsphy_instance *inst = phy_get_drvdata(phy); +@@ -325,6 +397,10 @@ static int mtk_phy_init(struct phy *phy) + case PHY_TYPE_USB3: + u3_phy_props_set(xsphy, inst); + break; ++ case PHY_TYPE_PCIE: ++ case PHY_TYPE_SGMII: ++ /* nothing to do, only used to set type */ ++ break; + default: + dev_err(xsphy->dev, "incompatible phy type\n"); + clk_disable_unprepare(inst->ref_clk); +@@ -403,12 +479,15 @@ static struct phy *mtk_phy_xlate(struct + + inst->type = args->args[0]; + if (!(inst->type == PHY_TYPE_USB2 || +- inst->type == PHY_TYPE_USB3)) { ++ inst->type == PHY_TYPE_USB3 || ++ inst->type == PHY_TYPE_PCIE || ++ inst->type == PHY_TYPE_SGMII)) { + dev_err(dev, "unsupported phy type: %d\n", inst->type); + return ERR_PTR(-EINVAL); + } + + phy_parse_property(xsphy, inst); ++ phy_type_set(inst); + + return inst->phy; + } +@@ -510,6 +589,10 @@ static int mtk_xsphy_probe(struct platfo + dev_err(dev, "failed to get ref_clk(id-%d)\n", port); + return PTR_ERR(inst->ref_clk); + } ++ ++ retval = phy_type_syscon_get(inst, child_np); ++ if (retval) ++ return retval; + } + + provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); diff --git a/target/linux/mediatek/patches-6.12/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch b/target/linux/mediatek/patches-6.12/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch new file mode 100644 index 0000000000..126ae5f2a3 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/060-v6.13-mmc-mtk-sd-add-support-for-mt7988.patch @@ -0,0 +1,28 @@ +From de6840095f8ed542308279c4f24fa42ba27c2dd3 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Sat, 12 Oct 2024 16:38:23 +0200 +Subject: [PATCH] mmc: mtk-sd: add support for mt7988 + +Add support for mmc on MT7988 SoC. + +We can use mt7986 platform data in driver, but mt7988 needs different +clocks so for binding we need own compatible. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Message-ID: <20241012143826.7690-3-linux@fw-web.de> +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -631,6 +631,7 @@ static const struct of_device_id msdc_of + { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, + { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, + { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, ++ { .compatible = "mediatek,mt7988-mmc", .data = &mt7986_compat}, + { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, + { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, + { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, diff --git a/target/linux/mediatek/patches-6.12/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.12/100-dts-update-mt7622-rfb1.patch new file mode 100644 index 0000000000..e00f23aba1 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/100-dts-update-mt7622-rfb1.patch @@ -0,0 +1,107 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -1,7 +1,6 @@ + /* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Ming Huang +- * Sean Wang ++ * Copyright (c) 2018 MediaTek Inc. ++ * Author: Ryder Lee + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ +@@ -24,7 +23,7 @@ + + chosen { + stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; ++ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; + }; + + cpus { +@@ -45,18 +44,18 @@ + key-factory { + label = "factory"; + linux,code = ; +- gpios = <&pio 0 0>; ++ gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + + key-wps { + label = "wps"; + linux,code = ; +- gpios = <&pio 102 0>; ++ gpios = <&pio 102 GPIO_ACTIVE_LOW>; + }; + }; + + memory@40000000 { +- reg = <0 0x40000000 0 0x20000000>; ++ reg = <0 0x40000000 0 0x40000000>; + device_type = "memory"; + }; + +@@ -145,22 +144,22 @@ + + port@0 { + reg = <0>; +- label = "lan0"; ++ label = "lan1"; + }; + + port@1 { + reg = <1>; +- label = "lan1"; ++ label = "lan2"; + }; + + port@2 { + reg = <2>; +- label = "lan2"; ++ label = "lan3"; + }; + + port@3 { + reg = <3>; +- label = "lan3"; ++ label = "lan4"; + }; + + port@4 { +@@ -264,7 +263,22 @@ + status = "okay"; + }; + ++&pcie1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_pins>; ++ status = "okay"; ++}; ++ + &pio { ++ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and ++ * SATA functions. i.e. output-high: PCIe, output-low: SATA ++ */ ++ asm_sel { ++ gpio-hog; ++ gpios = <90 GPIO_ACTIVE_HIGH>; ++ output-high; ++ }; ++ + /* eMMC is shared pin with parallel NAND */ + emmc_pins_default: emmc-pins-default { + mux { +@@ -541,11 +555,11 @@ + }; + + &sata { +- status = "okay"; ++ status = "disabled"; + }; + + &sata_phy { +- status = "okay"; ++ status = "disabled"; + }; + + &spi0 { diff --git a/target/linux/mediatek/patches-6.12/101-dts-update-mt7629-rfb.patch b/target/linux/mediatek/patches-6.12/101-dts-update-mt7629-rfb.patch new file mode 100644 index 0000000000..05dc2583bb --- /dev/null +++ b/target/linux/mediatek/patches-6.12/101-dts-update-mt7629-rfb.patch @@ -0,0 +1,62 @@ +--- a/arch/arm/boot/dts/mediatek/mt7629-rfb.dts ++++ b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts +@@ -18,6 +18,7 @@ + + chosen { + stdout-path = "serial0:115200n8"; ++ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8"; + }; + + gpio-keys { +@@ -70,6 +71,10 @@ + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; ++ ++ nvmem-cells = <&macaddr_factory_2a>; ++ nvmem-cell-names = "mac-address"; ++ + fixed-link { + speed = <2500>; + full-duplex; +@@ -82,6 +87,9 @@ + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&phy0>; ++ ++ nvmem-cells = <&macaddr_factory_24>; ++ nvmem-cell-names = "mac-address"; + }; + + mdio: mdio-bus { +@@ -133,8 +141,9 @@ + }; + + partition@b0000 { +- label = "kernel"; ++ label = "firmware"; + reg = <0xb0000 0xb50000>; ++ compatible = "denx,fit"; + }; + }; + }; +@@ -273,3 +282,19 @@ + pinctrl-0 = <&watchdog_pins>; + status = "okay"; + }; ++ ++&factory { ++ nvmem-layout { ++ compatible = "fixed-layout"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ macaddr_factory_24: macaddr@24 { ++ reg = <0x24 0x6>; ++ }; ++ ++ macaddr_factory_2a: macaddr@2a { ++ reg = <0x2a 0x6>; ++ }; ++ }; ++}; diff --git a/target/linux/mediatek/patches-6.12/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-6.12/103-mt7623-enable-arch-timer.patch new file mode 100644 index 0000000000..04df7b927b --- /dev/null +++ b/target/linux/mediatek/patches-6.12/103-mt7623-enable-arch-timer.patch @@ -0,0 +1,20 @@ +From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Fri, 29 Apr 2022 10:40:56 +0800 +Subject: [PATCH] arm: mediatek: select arch timer for mt7623 + +Signed-off-by: Chuanhong Guo +--- + arch/arm/mach-mediatek/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/mach-mediatek/Kconfig ++++ b/arch/arm/mach-mediatek/Kconfig +@@ -26,6 +26,7 @@ config MACH_MT6592 + config MACH_MT7623 + bool "MediaTek MT7623 SoCs support" + default ARCH_MEDIATEK ++ select HAVE_ARM_ARCH_TIMER + + config MACH_MT7629 + bool "MediaTek MT7629 SoCs support" diff --git a/target/linux/mediatek/patches-6.12/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-6.12/104-mt7622-add-snor-irq.patch new file mode 100644 index 0000000000..d15d989e97 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/104-mt7622-add-snor-irq.patch @@ -0,0 +1,10 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -575,6 +575,7 @@ + compatible = "mediatek,mt7622-nor", + "mediatek,mt8173-nor"; + reg = <0 0x11014000 0 0xe0>; ++ interrupts = ; + clocks = <&pericfg CLK_PERI_FLASH_PD>, + <&topckgen CLK_TOP_FLASH_SEL>; + clock-names = "spi", "sf"; diff --git a/target/linux/mediatek/patches-6.12/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-6.12/105-dts-mt7622-enable-pstore.patch new file mode 100644 index 0000000000..3e36a503ed --- /dev/null +++ b/target/linux/mediatek/patches-6.12/105-dts-mt7622-enable-pstore.patch @@ -0,0 +1,16 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -135,6 +135,13 @@ + #size-cells = <2>; + ranges; + ++ /* 64 KiB reserved for ramoops/pstore */ ++ ramoops@42ff0000 { ++ compatible = "ramoops"; ++ reg = <0 0x42ff0000 0 0x10000>; ++ record-size = <0x1000>; ++ }; ++ + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-6.12/106-dts-mt7622-disable_btif.patch b/target/linux/mediatek/patches-6.12/106-dts-mt7622-disable_btif.patch new file mode 100644 index 0000000000..ac8594b396 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/106-dts-mt7622-disable_btif.patch @@ -0,0 +1,26 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -109,10 +109,6 @@ + status = "disabled"; + }; + +-&btif { +- status = "okay"; +-}; +- + &cir { + pinctrl-names = "default"; + pinctrl-0 = <&irrx_pins>; +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -90,10 +90,6 @@ + status = "disabled"; + }; + +-&btif { +- status = "okay"; +-}; +- + &cir { + pinctrl-names = "default"; + pinctrl-0 = <&irrx_pins>; diff --git a/target/linux/mediatek/patches-6.12/110-dts-fix-bpi2-console.patch b/target/linux/mediatek/patches-6.12/110-dts-fix-bpi2-console.patch new file mode 100644 index 0000000000..d96d3b9581 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/110-dts-fix-bpi2-console.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts +@@ -19,6 +19,7 @@ + + chosen { + stdout-path = "serial2:115200n8"; ++ bootargs = "console=ttyS2,115200n8 console=tty1"; + }; + + connector { diff --git a/target/linux/mediatek/patches-6.12/111-dts-fix-bpi64-console.patch b/target/linux/mediatek/patches-6.12/111-dts-fix-bpi64-console.patch new file mode 100644 index 0000000000..f77f10cb95 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/111-dts-fix-bpi64-console.patch @@ -0,0 +1,11 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -24,7 +24,7 @@ + + chosen { + stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; ++ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; + }; + + cpus { diff --git a/target/linux/mediatek/patches-6.12/112-dts-fix-bpi64-lan-names.patch b/target/linux/mediatek/patches-6.12/112-dts-fix-bpi64-lan-names.patch new file mode 100644 index 0000000000..d83a89e3f7 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/112-dts-fix-bpi64-lan-names.patch @@ -0,0 +1,37 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -20,6 +20,7 @@ + + aliases { + serial0 = &uart0; ++ ethernet0 = &gmac0; + }; + + chosen { +@@ -164,22 +165,22 @@ + + port@1 { + reg = <1>; +- label = "lan0"; ++ label = "lan1"; + }; + + port@2 { + reg = <2>; +- label = "lan1"; ++ label = "lan2"; + }; + + port@3 { + reg = <3>; +- label = "lan2"; ++ label = "lan3"; + }; + + port@4 { + reg = <4>; +- label = "lan3"; ++ label = "lan4"; + }; + + port@5 { diff --git a/target/linux/mediatek/patches-6.12/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-6.12/113-dts-fix-bpi64-leds-and-buttons.patch new file mode 100644 index 0000000000..1cca6f3534 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/113-dts-fix-bpi64-leds-and-buttons.patch @@ -0,0 +1,49 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -21,6 +21,12 @@ + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; ++ led-boot = &led_system_green; ++ led-failsafe = &led_system_blue; ++ led-running = &led_system_green; ++ led-upgrade = &led_system_blue; ++ mmc0 = &mmc0; ++ mmc1 = &mmc1; + }; + + chosen { +@@ -44,8 +50,8 @@ + compatible = "gpio-keys"; + + factory-key { +- label = "factory"; +- linux,code = ; ++ label = "reset"; ++ linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + }; + +@@ -59,17 +65,17 @@ + leds { + compatible = "gpio-leds"; + +- led-0 { ++ led_system_green: led-0 { + label = "bpi-r64:pio:green"; + color = ; + gpios = <&pio 89 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + +- led-1 { +- label = "bpi-r64:pio:red"; +- color = ; +- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; ++ led_system_blue: led-1 { ++ label = "bpi-r64:pio:blue"; ++ color = ; ++ gpios = <&pio 85 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; diff --git a/target/linux/mediatek/patches-6.12/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-6.12/114-dts-bpi64-disable-rtc.patch new file mode 100644 index 0000000000..05ef32f504 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/114-dts-bpi64-disable-rtc.patch @@ -0,0 +1,13 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -599,6 +599,10 @@ + status = "okay"; + }; + ++&rtc { ++ status = "disabled"; ++}; ++ + &sata { + status = "disabled"; + }; diff --git a/target/linux/mediatek/patches-6.12/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch b/target/linux/mediatek/patches-6.12/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch new file mode 100644 index 0000000000..1d53cefd7f --- /dev/null +++ b/target/linux/mediatek/patches-6.12/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch @@ -0,0 +1,33 @@ +From 4c4baed29b168e9bf39545a945a9523ea280cb44 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 1 Feb 2025 04:24:17 +0000 +Subject: [PATCH 1/2] Revert "arm64: dts: mediatek: fix t-phy unit name" + +This reverts commit 963c3b0c47ec29b4c49c9f45965cd066f419d17f. +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -908,7 +908,7 @@ + status = "disabled"; + }; + +- sata_phy: t-phy { ++ sata_phy: t-phy@1a243000 { + compatible = "mediatek,mt7622-tphy", + "mediatek,generic-tphy-v1"; + #address-cells = <2>; +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -428,7 +428,7 @@ + }; + }; + +- pcie_phy: t-phy { ++ pcie_phy: t-phy@11c00000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + ranges; diff --git a/target/linux/mediatek/patches-6.12/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch b/target/linux/mediatek/patches-6.12/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch new file mode 100644 index 0000000000..4ae72fd70a --- /dev/null +++ b/target/linux/mediatek/patches-6.12/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch @@ -0,0 +1,33 @@ +From 98bc223d174c7f544e8f6c4f0caa8fa144f2f4dc Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 28 Jun 2024 12:55:40 +0200 +Subject: [PATCH 2/2] arm64: dts: mediatek: mt7622: readd syscon to pciesys + node + +Sata node reference the pciesys with the property mediatek,phy-node +and that is used as a syscon to access the pciesys regs. + +Readd the syscon compatible to pciesys node to restore correct +functionality of the SATA interface. + +Fixes: 3ba5a6159434 ("arm64: dts: mediatek: mt7622: fix clock controllers") +Reported-by: Frank Wunderlich +Co-developed-by: Frank Wunderlich +Signed-off-by: Frank Wunderlich +Signed-off-by: Christian Marangi +Cc: stable@vger.kernel.org +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -798,7 +798,7 @@ + }; + + pciesys: clock-controller@1a100800 { +- compatible = "mediatek,mt7622-pciesys"; ++ compatible = "mediatek,mt7622-pciesys", "syscon"; + reg = <0 0x1a100800 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; diff --git a/target/linux/mediatek/patches-6.12/117-complete-mt7981b-dtsi.patch b/target/linux/mediatek/patches-6.12/117-complete-mt7981b-dtsi.patch new file mode 100644 index 0000000000..45b9691bc5 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/117-complete-mt7981b-dtsi.patch @@ -0,0 +1,702 @@ +From 3986156b3ba97a9c280f4dfe0efbccf52e1fc488 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 28 Dec 2022 23:44:42 +0000 +Subject: [PATCH] complete mt7981 dts + +working: + * Ethernet (fully working incl. ppe) + * UART + * SPI-NAND flash + * thermal sensors (SoC and mxl-gpy) + * random number generator via SMC + * USB 1.1, 2.0 and 3.0 + * WiFi with MT7976C 2.4G+5G DBDC incl. WED offloading + * PWM + +--- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +@@ -1,7 +1,14 @@ + // SPDX-License-Identifier: GPL-2.0-only OR MIT + + #include ++#include ++#include + #include ++#include ++#include ++#include ++#include ++#include + #include + + / { +@@ -41,6 +48,57 @@ + method = "smc"; + }; + ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */ ++ cooling-levels = <0 128 192 255>; ++ #cooling-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* 64 KiB reserved for ramoops/pstore */ ++ ramoops@42ff0000 { ++ compatible = "ramoops"; ++ reg = <0 0x42ff0000 0 0x10000>; ++ record-size = <0x1000>; ++ }; ++ ++ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ ++ secmon_reserved: secmon@43000000 { ++ reg = <0 0x43000000 0 0x30000>; ++ no-map; ++ }; ++ ++ wmcpu_emi: wmcpu-reserved@47c80000 { ++ reg = <0 0x47c80000 0 0x100000>; ++ no-map; ++ }; ++ ++ wo_emi0: wo-emi@47d80000 { ++ reg = <0 0x47d80000 0 0x40000>; ++ no-map; ++ }; ++ ++ wo_data: wo-data@47dc0000 { ++ reg = <0 0x47dc0000 0 0x240000>; ++ no-map; ++ }; ++ }; ++ + soc { + compatible = "simple-bus"; + ranges; +@@ -76,13 +134,13 @@ + #reset-cells = <1>; + }; + +- clock-controller@1001e000 { +- compatible = "mediatek,mt7981-apmixedsys"; ++ apmixedsys: clock-controller@1001e000 { ++ compatible = "mediatek,mt7981-apmixedsys", "syscon"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + +- pwm@10048000 { ++ pwm: pwm@10048000 { + compatible = "mediatek,mt7981-pwm"; + reg = <0 0x10048000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_PWM_STA>, +@@ -94,7 +152,21 @@ + #pwm-cells = <2>; + }; + +- serial@11002000 { ++ crypto: crypto@10320000 { ++ compatible = "inside-secure,safexcel-eip97"; ++ reg = <0 0x10320000 0 0x40000>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "ring0", "ring1", "ring2", "ring3"; ++ clocks = <&topckgen CLK_TOP_EIP97B>; ++ clock-names = "top_eip97_ck"; ++ assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; ++ }; ++ ++ uart0: serial@11002000 { + compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x100>; + interrupts = ; +@@ -105,7 +177,7 @@ + status = "disabled"; + }; + +- serial@11003000 { ++ uart1: serial@11003000 { + compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x100>; + interrupts = ; +@@ -116,7 +188,7 @@ + status = "disabled"; + }; + +- serial@11004000 { ++ uart2: serial@11004000 { + compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x100>; + interrupts = ; +@@ -127,11 +199,12 @@ + status = "disabled"; + }; + +- i2c@11007000 { ++ i2c0: i2c@11007000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11007000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; ++ clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>, + <&infracfg CLK_INFRA_I2C_MCK_CK>, +@@ -142,7 +215,32 @@ + status = "disabled"; + }; + +- spi@11009000 { ++ thermal: thermal@1100c800 { ++ #thermal-sensor-cells = <1>; ++ compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal"; ++ reg = <0 0x1100c800 0 0x800>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_THERM_CK>, ++ <&infracfg CLK_INFRA_ADC_26M_CK>; ++ clock-names = "therm", "auxadc"; ++ mediatek,auxadc = <&auxadc>; ++ mediatek,apmixedsys = <&apmixedsys>; ++ nvmem-cells = <&thermal_calibration>; ++ nvmem-cell-names = "calibration-data"; ++ }; ++ ++ auxadc: adc@1100d000 { ++ compatible = "mediatek,mt7981-auxadc", ++ "mediatek,mt7986-auxadc", ++ "mediatek,mt7622-auxadc"; ++ reg = <0 0x1100d000 0 0x1000>; ++ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, ++ <&infracfg CLK_INFRA_ADC_FRC_CK>; ++ clock-names = "main", "32k"; ++ #io-channel-cells = <1>; ++ }; ++ ++ spi2: spi@11009000 { + compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x11009000 0 0x1000>; + interrupts = ; +@@ -156,7 +254,7 @@ + status = "disabled"; + }; + +- spi@1100a000 { ++ spi0: spi@1100a000 { + compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x1100a000 0 0x1000>; + interrupts = ; +@@ -170,7 +268,7 @@ + status = "disabled"; + }; + +- spi@1100b000 { ++ spi1: spi@1100b000 { + compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; +@@ -184,6 +282,41 @@ + status = "disabled"; + }; + ++ pcie: pcie@11280000 { ++ compatible = "mediatek,mt7981-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ reg = <0 0x11280000 0 0x4000>; ++ reg-names = "pcie-mac"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x20000000 ++ 0x0 0x20000000 0 0x10000000>; ++ status = "disabled"; ++ ++ clocks = <&infracfg CLK_INFRA_IPCIE_CK>, ++ <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, ++ <&infracfg CLK_INFRA_IPCIER_CK>, ++ <&infracfg CLK_INFRA_IPCIEB_CK>; ++ ++ phys = <&u3port0 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc 0>, ++ <0 0 0 2 &pcie_intc 1>, ++ <0 0 0 3 &pcie_intc 2>, ++ <0 0 0 4 &pcie_intc 3>; ++ pcie_intc: interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ + pio: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0 0x11d00000 0 0x1000>, +@@ -204,6 +337,49 @@ + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; ++ ++ mdio_pins: mdc-mdio-pins { ++ mux { ++ function = "eth"; ++ groups = "smi_mdc_mdio"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0"; ++ }; ++ }; ++ ++ wifi_dbdc_pins: wifi-dbdc-pins { ++ mux { ++ function = "eth"; ++ groups = "wf0_mode1"; ++ }; ++ conf { ++ pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", ++ "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", ++ "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", ++ "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", ++ "WF_CBA_RESETB", "WF_DIG_RESETB"; ++ drive-strength = <4>; ++ }; ++ }; ++ ++ gbe_led0_pins: gbe-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe_led0"; ++ }; ++ }; ++ ++ gbe_led1_pins: gbe-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe_led1"; ++ }; ++ }; + }; + + efuse@11f20000 { +@@ -211,17 +387,316 @@ + reg = <0 0x11f20000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ thermal_calibration: thermal-calib@274 { ++ reg = <0x274 0xc>; ++ }; ++ ++ phy_calibration: phy-calib@8dc { ++ reg = <0x8dc 0x10>; ++ }; ++ ++ comb_rx_imp_p0: usb3-rx-imp@8c8 { ++ reg = <0x8c8 1>; ++ bits = <0 5>; ++ }; ++ ++ comb_tx_imp_p0: usb3-tx-imp@8c8 { ++ reg = <0x8c8 2>; ++ bits = <5 5>; ++ }; ++ ++ comb_intr_p0: usb3-intr@8c9 { ++ reg = <0x8c9 1>; ++ bits = <2 6>; ++ }; + }; + +- clock-controller@15000000 { ++ ethsys: clock-controller@15000000 { + compatible = "mediatek,mt7981-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +- wifi@18000000 { ++ wed: wed@15010000 { ++ compatible = "mediatek,mt7981-wed", ++ "mediatek,mt7986-wed", ++ "syscon"; ++ reg = <0 0x15010000 0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ memory-region = <&wo_emi0>, <&wo_data>; ++ memory-region-names = "wo-emi", "wo-data"; ++ mediatek,wo-ccif = <&wo_ccif0>; ++ mediatek,wo-ilm = <&wo_ilm0>; ++ mediatek,wo-dlm = <&wo_dlm0>; ++ mediatek,wo-cpuboot = <&wo_cpuboot>; ++ }; ++ ++ eth: ethernet@15100000 { ++ compatible = "mediatek,mt7981-eth"; ++ reg = <0 0x15100000 0 0x80000>; ++ interrupts = , ++ , ++ , ++ ; ++ clocks = <ðsys CLK_ETH_FE_EN>, ++ <ðsys CLK_ETH_GP2_EN>, ++ <ðsys CLK_ETH_GP1_EN>, ++ <ðsys CLK_ETH_WOCPU0_EN>, ++ <&sgmiisys0 CLK_SGM0_TX_EN>, ++ <&sgmiisys0 CLK_SGM0_RX_EN>, ++ <&sgmiisys0 CLK_SGM0_CK0_EN>, ++ <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, ++ <&sgmiisys1 CLK_SGM1_TX_EN>, ++ <&sgmiisys1 CLK_SGM1_RX_EN>, ++ <&sgmiisys1 CLK_SGM1_CK1_EN>, ++ <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, ++ <&topckgen CLK_TOP_SGM_REG>, ++ <&topckgen CLK_TOP_NETSYS_SEL>, ++ <&topckgen CLK_TOP_NETSYS_500M_SEL>; ++ clock-names = "fe", "gp2", "gp1", "wocpu0", ++ "sgmii_tx250m", "sgmii_rx250m", ++ "sgmii_cdr_ref", "sgmii_cdr_fb", ++ "sgmii2_tx250m", "sgmii2_rx250m", ++ "sgmii2_cdr_ref", "sgmii2_cdr_fb", ++ "sgmii_ck", "netsys0", "netsys1"; ++ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, ++ <&topckgen CLK_TOP_SGM_325M_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, ++ <&topckgen CLK_TOP_CB_SGM_325M>; ++ mediatek,ethsys = <ðsys>; ++ mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; ++ mediatek,infracfg = <&topmisc>; ++ mediatek,wed = <&wed>; ++ status = "disabled"; ++ ++ mdio_bus: mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ int_gbe_phy: ethernet-phy@0 { ++ reg = <0>; ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ phy-mode = "gmii"; ++ phy-is-integrated; ++ nvmem-cells = <&phy_calibration>; ++ nvmem-cell-names = "phy-cal-data"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ int_gbe_phy_led0: int-gbe-phy-led0@0 { ++ reg = <0>; ++ function = LED_FUNCTION_LAN; ++ pinctrl-0 = <&gbe_led0_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ ++ int_gbe_phy_led1: int-gbe-phy-led1@1 { ++ reg = <1>; ++ function = LED_FUNCTION_LAN; ++ pinctrl-0 = <&gbe_led1_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ wdma: wdma@15104800 { ++ compatible = "mediatek,wed-wdma"; ++ reg = <0 0x15104800 0 0x400>, ++ <0 0x15104c00 0 0x400>; ++ }; ++ ++ ap2woccif: ap2woccif@151a5000 { ++ compatible = "mediatek,ap2woccif"; ++ reg = <0 0x151a5000 0 0x1000>, ++ <0 0x151ad000 0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = , ++ ; ++ }; ++ ++ wo_dlm0: syscon@151e8000 { ++ compatible = "mediatek,mt7986-wo-dlm", "syscon"; ++ reg = <0 0x151e8000 0 0x2000>; ++ }; ++ ++ wo_ilm0: syscon@151e0000 { ++ compatible = "mediatek,mt7986-wo-ilm", "syscon"; ++ reg = <0 0x151e0000 0 0x8000>; ++ }; ++ ++ wo_cpuboot: syscon@15194000 { ++ compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; ++ reg = <0 0x15194000 0 0x1000>; ++ }; ++ ++ wo_ccif0: syscon@151a5000 { ++ compatible = "mediatek,mt7986-wo-ccif", "syscon"; ++ reg = <0 0x151a5000 0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ ++ sgmiisys0: syscon@10060000 { ++ compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon"; ++ reg = <0 0x10060000 0 0x1000>; ++ mediatek,pnswap; ++ #clock-cells = <1>; ++ }; ++ ++ sgmiisys1: syscon@10070000 { ++ compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon"; ++ reg = <0 0x10070000 0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ ++ topmisc: topmisc@11d10000 { ++ compatible = "mediatek,mt7981-topmisc", "syscon"; ++ reg = <0 0x11d10000 0 0x10000>; ++ #clock-cells = <1>; ++ }; ++ ++ snand: snfi@11005000 { ++ compatible = "mediatek,mt7986-snand"; ++ reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; ++ reg-names = "nfi", "ecc"; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, ++ <&infracfg CLK_INFRA_NFI1_CK>, ++ <&infracfg CLK_INFRA_NFI_HCK_CK>; ++ clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; ++ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, ++ <&topckgen CLK_TOP_NFI1X_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>, ++ <&topckgen CLK_TOP_CB_M_D8>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ mmc0: mmc@11230000 { ++ compatible = "mediatek,mt7986-mmc", ++ "mediatek,mt7981-mmc"; ++ reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_MSDC_CK>, ++ <&infracfg CLK_INFRA_MSDC_HCK_CK>, ++ <&infracfg CLK_INFRA_MSDC_66M_CK>, ++ <&infracfg CLK_INFRA_MSDC_133M_CK>; ++ assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, ++ <&topckgen CLK_TOP_EMMC_400M_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, ++ <&topckgen CLK_TOP_CB_NET2_D2>; ++ clock-names = "source", "hclk", "axi_cg", "ahb_cg"; ++ status = "disabled"; ++ }; ++ ++ wed_pcie: wed_pcie@10003000 { ++ compatible = "mediatek,wed_pcie"; ++ reg = <0 0x10003000 0 0x10>; ++ }; ++ ++ consys: consys@10000000 { ++ compatible = "mediatek,mt7981-consys"; ++ reg = <0 0x10000000 0 0x8600000>; ++ memory-region = <&wmcpu_emi>; ++ }; ++ ++ xhci: usb@11200000 { ++ compatible = "mediatek,mt7986-xhci", ++ "mediatek,mtk-xhci"; ++ reg = <0 0x11200000 0 0x2e00>, ++ <0 0x11203e00 0 0x0100>; ++ reg-names = "mac", "ippc"; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, ++ <&infracfg CLK_INFRA_IUSB_CK>, ++ <&infracfg CLK_INFRA_IUSB_133_CK>, ++ <&infracfg CLK_INFRA_IUSB_66M_CK>, ++ <&topckgen CLK_TOP_U2U3_XHCI_SEL>; ++ clock-names = "sys_ck", ++ "ref_ck", ++ "mcu_ck", ++ "dma_ck", ++ "xhci_ck"; ++ phys = <&u2port0 PHY_TYPE_USB2>, ++ <&u3port0 PHY_TYPE_USB3>; ++ vusb33-supply = <®_3p3v>; ++ status = "disabled"; ++ }; ++ ++ usb_phy: usb-phy@11e10000 { ++ compatible = "mediatek,mt7981", ++ "mediatek,generic-tphy-v2"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0x11e10000 0x1700>; ++ status = "disabled"; ++ ++ u2port0: usb-phy@0 { ++ reg = <0x0 0x700>; ++ clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ }; ++ ++ u3port0: usb-phy@700 { ++ reg = <0x700 0x900>; ++ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ mediatek,syscon-type = <&topmisc 0x218 0>; ++ status = "okay"; ++ }; ++ }; ++ ++ ++ afe: audio-controller@11210000 { ++ compatible = "mediatek,mt79xx-audio"; ++ reg = <0 0x11210000 0 0x9000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, ++ <&infracfg CLK_INFRA_AUD_26M_CK>, ++ <&infracfg CLK_INFRA_AUD_L_CK>, ++ <&infracfg CLK_INFRA_AUD_AUD_CK>, ++ <&infracfg CLK_INFRA_AUD_EG2_CK>, ++ <&topckgen CLK_TOP_AUD_SEL>; ++ clock-names = "aud_bus_ck", ++ "aud_26m_ck", ++ "aud_l_ck", ++ "aud_aud_ck", ++ "aud_eg2_ck", ++ "aud_sel"; ++ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, ++ <&topckgen CLK_TOP_A1SYS_SEL>, ++ <&topckgen CLK_TOP_AUD_L_SEL>, ++ <&topckgen CLK_TOP_A_TUNER_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>, ++ <&topckgen CLK_TOP_APLL2_D4>, ++ <&topckgen CLK_TOP_CB_APLL2_196M>, ++ <&topckgen CLK_TOP_APLL2_D4>; ++ status = "disabled"; ++ }; ++ ++ ice: ice_debug { ++ compatible = "mediatek,mt7981-ice_debug", ++ "mediatek,mt2701-ice_debug"; ++ clocks = <&infracfg CLK_INFRA_DBG_CK>; ++ clock-names = "ice_dbg"; ++ }; ++ ++ wifi: wifi@18000000 { + compatible = "mediatek,mt7981-wmac"; ++ pinctrl-0 = <&wifi_dbdc_pins>; ++ pinctrl-names = "dbdc"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; +@@ -234,6 +709,67 @@ + clock-names = "mcu", "ap2conn"; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; + reset-names = "consys"; ++ memory-region = <&wmcpu_emi>; ++ status = "disabled"; ++ }; ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <1000>; ++ thermal-sensors = <&thermal 0>; ++ trips { ++ cpu_trip_crit: crit { ++ temperature = <125000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu_trip_hot: hot { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ ++ cpu_trip_active_high: active-high { ++ temperature = <115000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_med: active-med { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_low: active-low { ++ temperature = <60000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ cpu-active-high { ++ /* active: set fan to cooling level 3 */ ++ cooling-device = <&fan 3 3>; ++ trip = <&cpu_trip_active_high>; ++ }; ++ ++ cpu-active-med { ++ /* active: set fan to cooling level 2 */ ++ cooling-device = <&fan 2 2>; ++ trip = <&cpu_trip_active_med>; ++ }; ++ ++ cpu-active-low { ++ /* passive: set fan to cooling level 1 */ ++ cooling-device = <&fan 1 1>; ++ trip = <&cpu_trip_active_low>; ++ }; ++ }; + }; + }; + +@@ -245,4 +781,8 @@ + , + ; + }; ++ ++ trng { ++ compatible = "mediatek,mt7981-rng"; ++ }; + }; diff --git a/target/linux/mediatek/patches-6.12/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-6.12/121-hack-spi-nand-1b-bbm.patch new file mode 100644 index 0000000000..bb5e1a296e --- /dev/null +++ b/target/linux/mediatek/patches-6.12/121-hack-spi-nand-1b-bbm.patch @@ -0,0 +1,20 @@ +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -893,7 +893,7 @@ static int spinand_mtd_write(struct mtd_ + static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) + { + struct spinand_device *spinand = nand_to_spinand(nand); +- u8 marker[2] = { }; ++ u8 marker[1] = { }; + struct nand_page_io_req req = { + .pos = *pos, + .ooblen = sizeof(marker), +@@ -904,7 +904,7 @@ static bool spinand_isbad(struct nand_de + + spinand_select_target(spinand, pos->target); + spinand_read_page(spinand, &req); +- if (marker[0] != 0xff || marker[1] != 0xff) ++ if (marker[0] != 0xff) + return true; + + return false; diff --git a/target/linux/mediatek/patches-6.12/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-6.12/130-dts-mt7629-add-snand-support.patch new file mode 100644 index 0000000000..c7cd525a5c --- /dev/null +++ b/target/linux/mediatek/patches-6.12/130-dts-mt7629-add-snand-support.patch @@ -0,0 +1,94 @@ +From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001 +From: Xiangsheng Hou +Date: Thu, 6 Jun 2019 16:29:04 +0800 +Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629 + +Signed-off-by: Xiangsheng Hou +--- + arch/arm/boot/dts/mediatek/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/mediatek/mt7629.dtsi | 22 ++++++++++++++++ + 3 files changed, 79 insertions(+) + +--- a/arch/arm/boot/dts/mediatek/mt7629.dtsi ++++ b/arch/arm/boot/dts/mediatek/mt7629.dtsi +@@ -271,6 +271,27 @@ + status = "disabled"; + }; + ++ snfi: spi@1100d000 { ++ compatible = "mediatek,mt7629-snand"; ++ reg = <0x1100d000 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; ++ clock-names = "nfi_clk", "pad_clk"; ++ nand-ecc-engine = <&bch>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ bch: ecc@1100e000 { ++ compatible = "mediatek,mt7622-ecc"; ++ reg = <0x1100e000 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_NFIECC_PD>; ++ clock-names = "nfiecc_clk"; ++ status = "disabled"; ++ }; ++ + spi: spi@1100a000 { + compatible = "mediatek,mt7629-spi", + "mediatek,mt7622-spi"; +--- a/arch/arm/boot/dts/mediatek/mt7629-rfb.dts ++++ b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts +@@ -255,6 +255,50 @@ + }; + }; + ++&bch { ++ status = "okay"; ++}; ++ ++&snfi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&serial_nand_pins>; ++ status = "okay"; ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ nand-ecc-engine = <&snfi>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "Bootloader"; ++ reg = <0x00000 0x0100000>; ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "Config"; ++ reg = <0x100000 0x0040000>; ++ }; ++ ++ partition@140000 { ++ label = "factory"; ++ reg = <0x140000 0x0080000>; ++ }; ++ ++ partition@1c0000 { ++ label = "firmware"; ++ reg = <0x1c0000 0x1000000>; ++ }; ++ }; ++ }; ++}; ++ + &spi { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>; diff --git a/target/linux/mediatek/patches-6.12/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-6.12/131-dts-mt7622-add-snand-support.patch new file mode 100644 index 0000000000..5f4735caa4 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/131-dts-mt7622-add-snand-support.patch @@ -0,0 +1,68 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -558,6 +558,65 @@ + status = "disabled"; + }; + ++&bch { ++ status = "okay"; ++}; ++ ++&snfi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&serial_nand_pins>; ++ status = "okay"; ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ nand-ecc-engine = <&snfi>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "Preloader"; ++ reg = <0x00000 0x0080000>; ++ read-only; ++ }; ++ ++ partition@80000 { ++ label = "ATF"; ++ reg = <0x80000 0x0040000>; ++ }; ++ ++ partition@c0000 { ++ label = "Bootloader"; ++ reg = <0xc0000 0x0080000>; ++ }; ++ ++ partition@140000 { ++ label = "Config"; ++ reg = <0x140000 0x0080000>; ++ }; ++ ++ partition@1c0000 { ++ label = "Factory"; ++ reg = <0x1c0000 0x0100000>; ++ }; ++ ++ partition@200000 { ++ label = "firmware"; ++ reg = <0x2c0000 0x2000000>; ++ }; ++ ++ partition@2200000 { ++ label = "User_data"; ++ reg = <0x22c0000 0x4000000>; ++ }; ++ }; ++ }; ++}; ++ + &spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spic0_pins>; diff --git a/target/linux/mediatek/patches-6.12/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.12/140-dts-fix-wmac-support-for-mt7622-rfb1.patch new file mode 100644 index 0000000000..7167d1a8ef --- /dev/null +++ b/target/linux/mediatek/patches-6.12/140-dts-fix-wmac-support-for-mt7622-rfb1.patch @@ -0,0 +1,18 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -599,7 +599,7 @@ + reg = <0x140000 0x0080000>; + }; + +- partition@1c0000 { ++ factory: partition@1c0000 { + label = "Factory"; + reg = <0x1c0000 0x0100000>; + }; +@@ -660,5 +660,6 @@ + &wmac { + pinctrl-names = "default"; + pinctrl-0 = <&wmac_pins>; ++ mediatek,mtd-eeprom = <&factory 0x0000>; + status = "okay"; + }; diff --git a/target/linux/mediatek/patches-6.12/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.12/150-dts-mt7623-eip97-inside-secure-support.patch new file mode 100644 index 0000000000..d54e3ed1fd --- /dev/null +++ b/target/linux/mediatek/patches-6.12/150-dts-mt7623-eip97-inside-secure-support.patch @@ -0,0 +1,24 @@ +--- a/arch/arm/boot/dts/mediatek/mt7623.dtsi ++++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi +@@ -995,17 +995,15 @@ + }; + + crypto: crypto@1b240000 { +- compatible = "mediatek,eip97-crypto"; ++ compatible = "inside-secure,safexcel-eip97"; + reg = <0 0x1b240000 0 0x20000>; + interrupts = , + , + , +- , +- ; ++ ; ++ interrupt-names = "ring0", "ring1", "ring2", "ring3"; + clocks = <ðsys CLK_ETHSYS_CRYPTO>; +- clock-names = "cryp"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; +- status = "disabled"; ++ status = "okay"; + }; + + bdpsys: syscon@1c000000 { diff --git a/target/linux/mediatek/patches-6.12/160-dts-mt7623-bpi-r2-earlycon.patch b/target/linux/mediatek/patches-6.12/160-dts-mt7623-bpi-r2-earlycon.patch new file mode 100644 index 0000000000..5e02fb56ac --- /dev/null +++ b/target/linux/mediatek/patches-6.12/160-dts-mt7623-bpi-r2-earlycon.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts +@@ -19,7 +19,7 @@ + + chosen { + stdout-path = "serial2:115200n8"; +- bootargs = "console=ttyS2,115200n8 console=tty1"; ++ bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; + }; + + connector { diff --git a/target/linux/mediatek/patches-6.12/161-dts-mt7623-bpi-r2-mmc-device-order.patch b/target/linux/mediatek/patches-6.12/161-dts-mt7623-bpi-r2-mmc-device-order.patch new file mode 100644 index 0000000000..4b48219966 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/161-dts-mt7623-bpi-r2-mmc-device-order.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts +@@ -15,6 +15,8 @@ + + aliases { + serial2 = &uart2; ++ mmc0 = &mmc0; ++ mmc1 = &mmc1; + }; + + chosen { diff --git a/target/linux/mediatek/patches-6.12/162-dts-mt7623-bpi-r2-led-aliases.patch b/target/linux/mediatek/patches-6.12/162-dts-mt7623-bpi-r2-led-aliases.patch new file mode 100644 index 0000000000..2d02a760f0 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/162-dts-mt7623-bpi-r2-led-aliases.patch @@ -0,0 +1,29 @@ +--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts +@@ -17,6 +17,10 @@ + serial2 = &uart2; + mmc0 = &mmc0; + mmc1 = &mmc1; ++ led-boot = &led_system_green; ++ led-failsafe = &led_system_blue; ++ led-running = &led_system_green; ++ led-upgrade = &led_system_blue; + }; + + chosen { +@@ -112,13 +116,13 @@ + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_a>; + +- blue { ++ led_system_blue: blue { + label = "bpi-r2:pio:blue"; + gpios = <&pio 240 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + +- green { ++ led_system_green: green { + label = "bpi-r2:pio:green"; + gpios = <&pio 241 GPIO_ACTIVE_LOW>; + default-state = "off"; diff --git a/target/linux/mediatek/patches-6.12/163-dts-mt7623-bpi-r2-ethernet-alias.patch b/target/linux/mediatek/patches-6.12/163-dts-mt7623-bpi-r2-ethernet-alias.patch new file mode 100644 index 0000000000..b7e4a8c5cc --- /dev/null +++ b/target/linux/mediatek/patches-6.12/163-dts-mt7623-bpi-r2-ethernet-alias.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts +@@ -15,6 +15,7 @@ + + aliases { + serial2 = &uart2; ++ ethernet0 = &gmac0; + mmc0 = &mmc0; + mmc1 = &mmc1; + led-boot = &led_system_green; diff --git a/target/linux/mediatek/patches-6.12/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch b/target/linux/mediatek/patches-6.12/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch new file mode 100644 index 0000000000..be1e130905 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch @@ -0,0 +1,55 @@ +--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts +@@ -26,7 +26,9 @@ + + chosen { + stdout-path = "serial2:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; ++ bootargs = "root=/dev/fit0 rootwait earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; ++ rootdisk-emmc = <&emmc_rootdisk>; ++ rootdisk-sd = <&sd_rootdisk>; + }; + + connector { +@@ -338,6 +340,20 @@ + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ partitions { ++ compatible = "msdos-partitions"; ++ emmc_rootdisk: block-partition-fit { ++ partno = <3>; ++ }; ++ }; ++ }; + }; + + &mmc1 { +@@ -351,6 +367,20 @@ + cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ partitions { ++ compatible = "msdos-partitions"; ++ sd_rootdisk: block-partition-fit { ++ partno = <3>; ++ }; ++ }; ++ }; + }; + + &mt6323keys { diff --git a/target/linux/mediatek/patches-6.12/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch b/target/linux/mediatek/patches-6.12/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch new file mode 100644 index 0000000000..6216f59cfd --- /dev/null +++ b/target/linux/mediatek/patches-6.12/170-arm64-dts-mediatek-mt7988a-bpi-r4-allow-hw-variants-.patch @@ -0,0 +1,876 @@ +From df3c7a5128f88e658bd4519154d5e896519e740a Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 22 Apr 2025 15:24:25 +0200 +Subject: [PATCH 27/32] arm64: dts: mediatek: mt7988a-bpi-r4: allow hw variants + of bpi-r4 + +Sinovoip has released other variants of Bananapi-R4 board. +The known changes affecting only the LAN SFP+ slot which is replaced +by a 2.5G phy with optional PoE. + +Just move the common parts to a new dtsi and keep differences (only +i2c for lan-sfp) in dts. + +Signed-off-by: Frank Wunderlich +Acked-by: Krzysztof Kozlowski +Reviewed-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/Makefile | 6 + + .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts | 11 + + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 400 +----------------- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 399 +++++++++++++++++ + 4 files changed, 421 insertions(+), 395 deletions(-) + create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts + create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi + +--- a/arch/arm64/boot/dts/mediatek/Makefile ++++ b/arch/arm64/boot/dts/mediatek/Makefile +@@ -21,6 +21,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb +@@ -90,3 +93,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pu + # Device tree overlays support + DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@ + DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@ ++DTC_FLAGS_mt7988a-bananapi-bpi-r4 := -@ ++DTC_FLAGS_mt7988a-bananapi-bpi-r4-2g5 := -@ ++DTC_FLAGS_mt8395-radxa-nio-12l := -@ +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts +@@ -0,0 +1,11 @@ ++// SPDX-License-Identifier: GPL-2.0-only OR MIT ++ ++/dts-v1/; ++ ++#include "mt7988a-bananapi-bpi-r4.dtsi" ++ ++/ { ++ compatible = "bananapi,bpi-r4-2g5", "bananapi,bpi-r4", "mediatek,mt7988a"; ++ model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)"; ++ chassis-type = "embedded"; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -2,408 +2,18 @@ + + /dts-v1/; + +-#include +-#include +- +-#include "mt7988a.dtsi" ++#include "mt7988a-bananapi-bpi-r4.dtsi" + + / { + compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; +- model = "Banana Pi BPI-R4"; ++ model = "Banana Pi BPI-R4 (2x SFP+)"; + chassis-type = "embedded"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-1.8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "fixed-3.3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- regulator-always-on; +- }; + }; + +-&cpu0 { +- proc-supply = <&rt5190_buck3>; +-}; +- +-&cpu1 { +- proc-supply = <&rt5190_buck3>; +-}; +- +-&cpu2 { +- proc-supply = <&rt5190_buck3>; +-}; +- +-&cpu3 { +- proc-supply = <&rt5190_buck3>; +-}; +- +-&cpu_thermal { +- trips { +- cpu_trip_hot: hot { +- temperature = <120000>; +- hysteresis = <2000>; +- type = "hot"; +- }; +- +- cpu_trip_active_high: active-high { +- temperature = <115000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_trip_active_med: active-med { +- temperature = <85000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_trip_active_low: active-low { +- temperature = <40000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- }; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +- +- rt5190a_64: rt5190a@64 { +- compatible = "richtek,rt5190a"; +- reg = <0x64>; +- vin2-supply = <&rt5190_buck1>; +- vin3-supply = <&rt5190_buck1>; +- vin4-supply = <&rt5190_buck1>; +- +- regulators { +- rt5190_buck1: buck1 { +- regulator-name = "rt5190a-buck1"; +- regulator-min-microvolt = <5090000>; +- regulator-max-microvolt = <5090000>; +- regulator-allowed-modes = +- , ; +- regulator-boot-on; +- regulator-always-on; +- }; +- buck2 { +- regulator-name = "vcore"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- rt5190_buck3: buck3 { +- regulator-name = "vproc"; +- regulator-min-microvolt = <600000>; +- regulator-max-microvolt = <1400000>; +- regulator-boot-on; +- }; +- buck4 { +- regulator-name = "rt5190a-buck4"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-allowed-modes = +- , ; +- regulator-boot-on; +- regulator-always-on; +- }; +- ldo { +- regulator-name = "rt5190a-ldo"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-boot-on; +- regulator-always-on; +- }; +- }; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_1_pins>; +- status = "okay"; +- +- pca9545: i2c-mux@70 { +- compatible = "nxp,pca9545"; +- reg = <0x70>; +- reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; ++&pca9545 { ++ i2c_sfp2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; +- +- i2c@0 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0>; +- +- pcf8563: rtc@51 { +- compatible = "nxp,pcf8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- }; +- +- eeprom@57 { +- compatible = "atmel,24c02"; +- reg = <0x57>; +- size = <256>; +- }; +- +- }; +- +- i2c_sfp1: i2c@1 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <1>; +- }; +- +- i2c_sfp2: i2c@2 { +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <2>; +- }; +- }; +-}; +- +-/* mPCIe SIM2 */ +-&pcie0 { +- status = "okay"; +-}; +- +-/* mPCIe SIM3 */ +-&pcie1 { +- status = "okay"; +-}; +- +-/* M.2 key-B SIM1 */ +-&pcie2 { +- status = "okay"; +-}; +- +-/* M.2 key-M SSD */ +-&pcie3 { +- status = "okay"; +-}; +- +-&pio { +- mdio0_pins: mdio0-pins { +- mux { +- function = "eth"; +- groups = "mdc_mdio0"; +- }; +- +- conf { +- pins = "SMI_0_MDC", "SMI_0_MDIO"; +- drive-strength = <8>; +- }; +- }; +- +- i2c0_pins: i2c0-g0-pins { +- mux { +- function = "i2c"; +- groups = "i2c0_1"; +- }; +- }; +- +- i2c1_pins: i2c1-g0-pins { +- mux { +- function = "i2c"; +- groups = "i2c1_0"; +- }; +- }; +- +- i2c1_sfp_pins: i2c1-sfp-g0-pins { +- mux { +- function = "i2c"; +- groups = "i2c1_sfp"; +- }; +- }; +- +- i2c2_0_pins: i2c2-g0-pins { +- mux { +- function = "i2c"; +- groups = "i2c2_0"; +- }; ++ reg = <2>; + }; +- +- i2c2_1_pins: i2c2-g1-pins { +- mux { +- function = "i2c"; +- groups = "i2c2_1"; +- }; +- }; +- +- gbe0_led0_pins: gbe0-led0-pins { +- mux { +- function = "led"; +- groups = "gbe0_led0"; +- }; +- }; +- +- gbe1_led0_pins: gbe1-led0-pins { +- mux { +- function = "led"; +- groups = "gbe1_led0"; +- }; +- }; +- +- gbe2_led0_pins: gbe2-led0-pins { +- mux { +- function = "led"; +- groups = "gbe2_led0"; +- }; +- }; +- +- gbe3_led0_pins: gbe3-led0-pins { +- mux { +- function = "led"; +- groups = "gbe3_led0"; +- }; +- }; +- +- gbe0_led1_pins: gbe0-led1-pins { +- mux { +- function = "led"; +- groups = "gbe0_led1"; +- }; +- }; +- +- gbe1_led1_pins: gbe1-led1-pins { +- mux { +- function = "led"; +- groups = "gbe1_led1"; +- }; +- }; +- +- gbe2_led1_pins: gbe2-led1-pins { +- mux { +- function = "led"; +- groups = "gbe2_led1"; +- }; +- }; +- +- gbe3_led1_pins: gbe3-led1-pins { +- mux { +- function = "led"; +- groups = "gbe3_led1"; +- }; +- }; +- +- i2p5gbe_led0_pins: 2p5gbe-led0-pins { +- mux { +- function = "led"; +- groups = "2p5gbe_led0"; +- }; +- }; +- +- i2p5gbe_led1_pins: 2p5gbe-led1-pins { +- mux { +- function = "led"; +- groups = "2p5gbe_led1"; +- }; +- }; +- +- mmc0_pins_emmc_45: mmc0-emmc-45-pins { +- mux { +- function = "flash"; +- groups = "emmc_45"; +- }; +- }; +- +- mmc0_pins_emmc_51: mmc0-emmc-51-pins { +- mux { +- function = "flash"; +- groups = "emmc_51"; +- }; +- }; +- +- mmc0_pins_sdcard: mmc0-sdcard-pins { +- mux { +- function = "flash"; +- groups = "sdcard"; +- }; +- }; +- +- uart0_pins: uart0-pins { +- mux { +- function = "uart"; +- groups = "uart0"; +- }; +- }; +- +- snfi_pins: snfi-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- spi0_pins: spi0-pins { +- mux { +- function = "spi"; +- groups = "spi0"; +- }; +- }; +- +- spi0_flash_pins: spi0-flash-pins { +- mux { +- function = "spi"; +- groups = "spi0", "spi0_wp_hold"; +- }; +- }; +- +- spi1_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1"; +- }; +- }; +- +- spi2_pins: spi2-pins { +- mux { +- function = "spi"; +- groups = "spi2"; +- }; +- }; +- +- spi2_flash_pins: spi2-flash-pins { +- mux { +- function = "spi"; +- groups = "spi2", "spi2_wp_hold"; +- }; +- }; +-}; +- +-&pwm { +- status = "okay"; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&ssusb1 { +- status = "okay"; +-}; +- +-&tphy { +- status = "okay"; +-}; +- +-&watchdog { +- status = "okay"; + }; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -0,0 +1,399 @@ ++// SPDX-License-Identifier: GPL-2.0-only OR MIT ++ ++/dts-v1/; ++ ++#include ++#include ++ ++#include "mt7988a.dtsi" ++ ++/ { ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&cpu0 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu1 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu2 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu3 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu_thermal { ++ trips { ++ cpu_trip_hot: hot { ++ temperature = <120000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ ++ cpu_trip_active_high: active-high { ++ temperature = <115000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_med: active-med { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_trip_active_low: active-low { ++ temperature = <40000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ status = "okay"; ++ ++ rt5190a_64: rt5190a@64 { ++ compatible = "richtek,rt5190a"; ++ reg = <0x64>; ++ vin2-supply = <&rt5190_buck1>; ++ vin3-supply = <&rt5190_buck1>; ++ vin4-supply = <&rt5190_buck1>; ++ ++ regulators { ++ rt5190_buck1: buck1 { ++ regulator-name = "rt5190a-buck1"; ++ regulator-min-microvolt = <5090000>; ++ regulator-max-microvolt = <5090000>; ++ regulator-allowed-modes = ++ , ; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ buck2 { ++ regulator-name = "vcore"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ rt5190_buck3: buck3 { ++ regulator-name = "vproc"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ }; ++ buck4 { ++ regulator-name = "rt5190a-buck4"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-allowed-modes = ++ , ; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ldo { ++ regulator-name = "rt5190a-ldo"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_1_pins>; ++ status = "okay"; ++ ++ pca9545: i2c-mux@70 { ++ compatible = "nxp,pca9545"; ++ reg = <0x70>; ++ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ pcf8563: rtc@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ }; ++ ++ eeprom@57 { ++ compatible = "atmel,24c02"; ++ reg = <0x57>; ++ size = <256>; ++ }; ++ ++ }; ++ ++ i2c_sfp1: i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ }; ++}; ++ ++/* mPCIe SIM2 */ ++&pcie0 { ++ status = "okay"; ++}; ++ ++/* mPCIe SIM3 */ ++&pcie1 { ++ status = "okay"; ++}; ++ ++/* M.2 key-B SIM1 */ ++&pcie2 { ++ status = "okay"; ++}; ++ ++/* M.2 key-M SSD */ ++&pcie3 { ++ status = "okay"; ++}; ++ ++&pio { ++ mdio0_pins: mdio0-pins { ++ mux { ++ function = "eth"; ++ groups = "mdc_mdio0"; ++ }; ++ ++ conf { ++ pins = "SMI_0_MDC", "SMI_0_MDIO"; ++ drive-strength = <8>; ++ }; ++ }; ++ ++ i2c0_pins: i2c0-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c0_1"; ++ }; ++ }; ++ ++ i2c1_pins: i2c1-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_0"; ++ }; ++ }; ++ ++ i2c1_sfp_pins: i2c1-sfp-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_sfp"; ++ }; ++ }; ++ ++ i2c2_0_pins: i2c2-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_0"; ++ }; ++ }; ++ ++ i2c2_1_pins: i2c2-g1-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_1"; ++ }; ++ }; ++ ++ gbe0_led0_pins: gbe0-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe0_led0"; ++ }; ++ }; ++ ++ gbe1_led0_pins: gbe1-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe1_led0"; ++ }; ++ }; ++ ++ gbe2_led0_pins: gbe2-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe2_led0"; ++ }; ++ }; ++ ++ gbe3_led0_pins: gbe3-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe3_led0"; ++ }; ++ }; ++ ++ gbe0_led1_pins: gbe0-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe0_led1"; ++ }; ++ }; ++ ++ gbe1_led1_pins: gbe1-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe1_led1"; ++ }; ++ }; ++ ++ gbe2_led1_pins: gbe2-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe2_led1"; ++ }; ++ }; ++ ++ gbe3_led1_pins: gbe3-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe3_led1"; ++ }; ++ }; ++ ++ i2p5gbe_led0_pins: 2p5gbe-led0-pins { ++ mux { ++ function = "led"; ++ groups = "2p5gbe_led0"; ++ }; ++ }; ++ ++ i2p5gbe_led1_pins: 2p5gbe-led1-pins { ++ mux { ++ function = "led"; ++ groups = "2p5gbe_led1"; ++ }; ++ }; ++ ++ mmc0_pins_emmc_45: mmc0-emmc-45-pins { ++ mux { ++ function = "flash"; ++ groups = "emmc_45"; ++ }; ++ }; ++ ++ mmc0_pins_emmc_51: mmc0-emmc-51-pins { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ }; ++ ++ mmc0_pins_sdcard: mmc0-sdcard-pins { ++ mux { ++ function = "flash"; ++ groups = "sdcard"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0"; ++ }; ++ }; ++ ++ snfi_pins: snfi-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ ++ spi0_pins: spi0-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0"; ++ }; ++ }; ++ ++ spi0_flash_pins: spi0-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ }; ++ ++ spi1_pins: spi1-pins { ++ mux { ++ function = "spi"; ++ groups = "spi1"; ++ }; ++ }; ++ ++ spi2_pins: spi2-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2"; ++ }; ++ }; ++ ++ spi2_flash_pins: spi2-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2", "spi2_wp_hold"; ++ }; ++ }; ++}; ++ ++&pwm { ++ status = "okay"; ++}; ++ ++&serial0 { ++ status = "okay"; ++}; ++ ++&ssusb1 { ++ status = "okay"; ++}; ++ ++&tphy { ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "okay"; ++}; diff --git a/target/linux/mediatek/patches-6.12/171-arm64-dts-mediatek-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch b/target/linux/mediatek/patches-6.12/171-arm64-dts-mediatek-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch new file mode 100644 index 0000000000..fac060ef16 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/171-arm64-dts-mediatek-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch @@ -0,0 +1,74 @@ +From 1861c63ba7bb7f8a5145d4ceabcf346f274da61f Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 22 Apr 2025 15:24:30 +0200 +Subject: [PATCH 28/32] arm64: dts: mediatek: mt7988: Add xsphy for + ssusb0/pcie2 + +First usb and third pcie controller on mt7988 need a xs-phy to work +properly. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 36 +++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -334,6 +334,8 @@ + <&infracfg CLK_INFRA_133M_USB_HCK>, + <&infracfg CLK_INFRA_USB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; ++ phys = <&xphyu2port0 PHY_TYPE_USB2>, ++ <&xphyu3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + +@@ -398,6 +400,9 @@ + pinctrl-0 = <&pcie2_pins>; + status = "disabled"; + ++ phys = <&xphyu3port0 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy"; ++ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc2 0>, +@@ -548,6 +553,37 @@ + }; + }; + ++ ++ topmisc: system-controller@11d10084 { ++ compatible = "mediatek,mt7988-topmisc", ++ "syscon"; ++ reg = <0 0x11d10084 0 0xff80>; ++ }; ++ ++ xs-phy@11e10000 { ++ compatible = "mediatek,mt7988-xsphy", ++ "mediatek,xsphy"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ xphyu2port0: usb-phy@11e10000 { ++ reg = <0 0x11e10000 0 0x400>; ++ clocks = <&infracfg CLK_INFRA_USB_UTMI>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ }; ++ ++ xphyu3port0: usb-phy@11e13000 { ++ reg = <0 0x11e13400 0 0x500>; ++ clocks = <&infracfg CLK_INFRA_USB_PIPE>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ mediatek,syscon-type = <&topmisc 0x194 0>; ++ }; ++ }; ++ + clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/172-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch b/target/linux/mediatek/patches-6.12/172-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch new file mode 100644 index 0000000000..da26a93eb7 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/172-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch @@ -0,0 +1,35 @@ +From d326d21a44fbc48663840316c35524002029fbb1 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 22 Apr 2025 15:24:31 +0200 +Subject: [PATCH 29/32] arm64: dts: mediatek: mt7988a-bpi-r4: enable xsphy + +Enable XS-Phy on Bananapi R4 for pcie2. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++ + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -397,3 +397,7 @@ + &watchdog { + status = "okay"; + }; ++ ++&xsphy { ++ status = "okay"; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -560,7 +560,7 @@ + reg = <0 0x11d10084 0 0xff80>; + }; + +- xs-phy@11e10000 { ++ xsphy: xs-phy@11e10000 { + compatible = "mediatek,mt7988-xsphy", + "mediatek,xsphy"; + #address-cells = <2>; diff --git a/target/linux/mediatek/patches-6.12/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch b/target/linux/mediatek/patches-6.12/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch new file mode 100644 index 0000000000..698f821314 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/173-dts-mt7988a-Add-built-in-ethernet-phy-firmware-node.patch @@ -0,0 +1,27 @@ +From 6cf55d4520eb4ef3ed2cc3726a765a89b0071d8b Mon Sep 17 00:00:00 2001 +From: Sky Huang +Date: Wed, 19 Feb 2025 16:39:09 +0800 +Subject: [PATCH 30/32] dts: mt7988a: Add built-in ethernet phy firmware node + +Add built-in ethernet phy firmware node in mt7988a.dtsi. + +Signed-off-by: Sky Huang +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -322,6 +322,12 @@ + nvmem-cell-names = "lvts-calib-data-1"; + }; + ++ phyfw: phy-firmware@f000000 { ++ compatible = "mediatek,2p5gphy-fw"; ++ reg = <0 0x0f100000 0 0x20000>, ++ <0 0x0f0f0018 0 0x20>; ++ }; ++ + usb@11190000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, diff --git a/target/linux/mediatek/patches-6.12/174-arm64-dts-mediatek-mt7988-add-spi-controllers.patch b/target/linux/mediatek/patches-6.12/174-arm64-dts-mediatek-mt7988-add-spi-controllers.patch new file mode 100644 index 0000000000..a0557ab966 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/174-arm64-dts-mediatek-mt7988-add-spi-controllers.patch @@ -0,0 +1,112 @@ +From patchwork Sun May 11 14:19:20 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084127 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 04/14] arm64: dts: mediatek: mt7988: add spi controllers +Date: Sun, 11 May 2025 16:19:20 +0200 +Message-ID: <20250511141942.10284-5-linux@fw-web.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> +References: <20250511141942.10284-1-linux@fw-web.de> +MIME-Version: 1.0 +X-Mail-ID: 5110cbfc-28b8-49e4-b9da-560d0bd630a5 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +From: Frank Wunderlich + +Add SPI controllers for mt7988. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 45 +++++++++++++++++++++++ + 1 file changed, 45 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -311,6 +311,51 @@ + status = "disabled"; + }; + ++ spi0: spi@11007000 { ++ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; ++ reg = <0 0x11007000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_MPLL_D2>, ++ <&topckgen CLK_TOP_SPI_SEL>, ++ <&infracfg CLK_INFRA_104M_SPI0>, ++ <&infracfg CLK_INFRA_66M_SPI0_HCK>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk", ++ "hclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@11008000 { ++ compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm"; ++ reg = <0 0x11008000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_MPLL_D2>, ++ <&topckgen CLK_TOP_SPIM_MST_SEL>, ++ <&infracfg CLK_INFRA_104M_SPI1>, ++ <&infracfg CLK_INFRA_66M_SPI1_HCK>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk", ++ "hclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@11009000 { ++ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; ++ reg = <0 0x11009000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_MPLL_D2>, ++ <&topckgen CLK_TOP_SPI_SEL>, ++ <&infracfg CLK_INFRA_104M_SPI2_BCK>, ++ <&infracfg CLK_INFRA_66M_SPI2_HCK>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk", ++ "hclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + lvts: lvts@1100a000 { + compatible = "mediatek,mt7988-lvts-ap"; + #thermal-sensor-cells = <1>; diff --git a/target/linux/mediatek/patches-6.12/175-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-to-soc-dtsi.patch b/target/linux/mediatek/patches-6.12/175-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-to-soc-dtsi.patch new file mode 100644 index 0000000000..7dbc1e4286 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/175-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-to-soc-dtsi.patch @@ -0,0 +1,133 @@ +From patchwork Sun May 11 14:19:21 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084155 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 05/14] arm64: dts: mediatek: mt7988: move uart0 and spi1 + pins to soc dtsi +Date: Sun, 11 May 2025 16:19:21 +0200 +Message-ID: <20250511141942.10284-6-linux@fw-web.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> +References: <20250511141942.10284-1-linux@fw-web.de> +MIME-Version: 1.0 +X-Mail-ID: 730e5bd4-362e-4c00-a35e-0ec77e8f4691 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +From: Frank Wunderlich + +In order to use uart0 or spi1 there is only 1 possible pin definition +so move them to soc dtsi to reuse them in other boards and avoiding +conflict if defined twice. + +Suggested-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 14 -------------- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 18 ++++++++++++++++++ + 2 files changed, 18 insertions(+), 14 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -328,13 +328,6 @@ + }; + }; + +- uart0_pins: uart0-pins { +- mux { +- function = "uart"; +- groups = "uart0"; +- }; +- }; +- + snfi_pins: snfi-pins { + mux { + function = "flash"; +@@ -356,13 +349,6 @@ + }; + }; + +- spi1_pins: spi1-pins { +- mux { +- function = "spi"; +- groups = "spi1"; +- }; +- }; +- + spi2_pins: spi2-pins { + mux { + function = "spi"; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -209,6 +209,20 @@ + "pcie_wake_n3_0"; + }; + }; ++ ++ spi1_pins: spi1-pins { ++ mux { ++ function = "spi"; ++ groups = "spi1"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0"; ++ }; ++ }; + }; + + pwm: pwm@10048000 { +@@ -244,6 +258,8 @@ + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_52M_UART0_CK>; + clock-names = "baud", "bus"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; + status = "disabled"; + }; + +@@ -338,6 +354,8 @@ + "hclk"; + #address-cells = <1>; + #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; + status = "disabled"; + }; + diff --git a/target/linux/mediatek/patches-6.12/176-arm64-dts-mediatek-mt7988-add-cci-node.patch b/target/linux/mediatek/patches-6.12/176-arm64-dts-mediatek-mt7988-add-cci-node.patch new file mode 100644 index 0000000000..915c45caeb --- /dev/null +++ b/target/linux/mediatek/patches-6.12/176-arm64-dts-mediatek-mt7988-add-cci-node.patch @@ -0,0 +1,128 @@ +From patchwork Sun May 11 14:19:22 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084106 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 06/14] arm64: dts: mediatek: mt7988: add cci node +Date: Sun, 11 May 2025 16:19:22 +0200 +Message-ID: <20250511141942.10284-7-linux@fw-web.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> +References: <20250511141942.10284-1-linux@fw-web.de> +MIME-Version: 1.0 +X-Mail-ID: beeb7784-23fa-410f-9e58-cc51116d869e +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +From: Frank Wunderlich + +Add cci devicetree node for cpu frequency scaling. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++ + 1 file changed, 33 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -12,6 +12,35 @@ + #address-cells = <2>; + #size-cells = <2>; + ++ cci: cci { ++ compatible = "mediatek,mt8183-cci"; ++ clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, ++ <&topckgen CLK_TOP_XTAL>; ++ clock-names = "cci", "intermediate"; ++ operating-points-v2 = <&cci_opp>; ++ }; ++ ++ cci_opp: opp-table-cci { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ opp-480000000 { ++ opp-hz = /bits/ 64 <480000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-660000000 { ++ opp-hz = /bits/ 64 <660000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-900000000 { ++ opp-hz = /bits/ 64 <900000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp-1080000000 { ++ opp-hz = /bits/ 64 <1080000000>; ++ opp-microvolt = <900000>; ++ }; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; +@@ -25,6 +54,7 @@ + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; ++ mediatek,cci = <&cci>; + }; + + cpu1: cpu@1 { +@@ -36,6 +66,7 @@ + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; ++ mediatek,cci = <&cci>; + }; + + cpu2: cpu@2 { +@@ -47,6 +78,7 @@ + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; ++ mediatek,cci = <&cci>; + }; + + cpu3: cpu@3 { +@@ -58,6 +90,7 @@ + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; ++ mediatek,cci = <&cci>; + }; + + cluster0_opp: opp-table-0 { diff --git a/target/linux/mediatek/patches-6.12/177-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-subnodes.patch b/target/linux/mediatek/patches-6.12/177-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-subnodes.patch new file mode 100644 index 0000000000..dc6df8ee57 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/177-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-subnodes.patch @@ -0,0 +1,85 @@ +From patchwork Sun May 11 14:19:23 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084124 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 07/14] arm64: dts: mediatek: mt7988: add phy calibration + efuse subnodes +Date: Sun, 11 May 2025 16:19:23 +0200 +Message-ID: <20250511141942.10284-8-linux@fw-web.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> +References: <20250511141942.10284-1-linux@fw-web.de> +MIME-Version: 1.0 +X-Mail-ID: b7327c0d-db13-43b6-8ec5-709b71d19c3b +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +From: Frank Wunderlich + +MT7988 contains buildin mt753x switch which needs calibration data from +efuse. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -702,6 +702,22 @@ + lvts_calibration: calib@918 { + reg = <0x918 0x28>; + }; ++ ++ phy_calibration_p0: calib@940 { ++ reg = <0x940 0x10>; ++ }; ++ ++ phy_calibration_p1: calib@954 { ++ reg = <0x954 0x10>; ++ }; ++ ++ phy_calibration_p2: calib@968 { ++ reg = <0x968 0x10>; ++ }; ++ ++ phy_calibration_p3: calib@97c { ++ reg = <0x97c 0x10>; ++ }; + }; + + clock-controller@15000000 { diff --git a/target/linux/mediatek/patches-6.12/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch b/target/linux/mediatek/patches-6.12/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch new file mode 100644 index 0000000000..15c8ad7ea0 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/178-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch @@ -0,0 +1,213 @@ +From patchwork Sun May 11 14:19:24 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084161 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 08/14] arm64: dts: mediatek: mt7988: add basic + ethernet-nodes +Date: Sun, 11 May 2025 16:19:24 +0200 +Message-ID: <20250511141942.10284-9-linux@fw-web.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> +References: <20250511141942.10284-1-linux@fw-web.de> +MIME-Version: 1.0 +X-Mail-ID: 5c8e73b6-e2d6-4898-90c0-375604707c20 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +From: Frank Wunderlich + +Add basic ethernet related nodes. + +Mac1+2 needs pcs (sgmii+usxgmii) to work correctly which will be linked +later when driver is merged. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 124 +++++++++++++++++++++- + 1 file changed, 121 insertions(+), 3 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -686,7 +686,28 @@ + }; + }; + +- clock-controller@11f40000 { ++ xfi_tphy0: phy@11f20000 { ++ compatible = "mediatek,mt7988-xfi-tphy"; ++ reg = <0 0x11f20000 0 0x10000>; ++ resets = <&watchdog 14>; ++ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, ++ <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; ++ clock-names = "xfipll", "topxtal"; ++ mediatek,usxgmii-performance-errata; ++ #phy-cells = <0>; ++ }; ++ ++ xfi_tphy1: phy@11f30000 { ++ compatible = "mediatek,mt7988-xfi-tphy"; ++ reg = <0 0x11f30000 0 0x10000>; ++ resets = <&watchdog 15>; ++ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, ++ <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; ++ clock-names = "xfipll", "topxtal"; ++ #phy-cells = <0>; ++ }; ++ ++ xfi_pll: clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; + resets = <&watchdog 16>; +@@ -720,19 +741,116 @@ + }; + }; + +- clock-controller@15000000 { ++ ethsys: clock-controller@15000000 { + compatible = "mediatek,mt7988-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +- clock-controller@15031000 { ++ ethwarp: clock-controller@15031000 { + compatible = "mediatek,mt7988-ethwarp"; + reg = <0 0x15031000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; ++ ++ eth: ethernet@15100000 { ++ compatible = "mediatek,mt7988-eth"; ++ reg = <0 0x15100000 0 0x80000>, ++ <0 0x15400000 0 0x200000>; ++ interrupts = , ++ , ++ , ++ ; ++ clocks = <ðsys CLK_ETHDMA_CRYPT0_EN>, ++ <ðsys CLK_ETHDMA_FE_EN>, ++ <ðsys CLK_ETHDMA_GP2_EN>, ++ <ðsys CLK_ETHDMA_GP1_EN>, ++ <ðsys CLK_ETHDMA_GP3_EN>, ++ <ðwarp CLK_ETHWARP_WOCPU2_EN>, ++ <ðwarp CLK_ETHWARP_WOCPU1_EN>, ++ <ðwarp CLK_ETHWARP_WOCPU0_EN>, ++ <ðsys CLK_ETHDMA_ESW_EN>, ++ <&topckgen CLK_TOP_ETH_GMII_SEL>, ++ <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, ++ <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, ++ <&topckgen CLK_TOP_ETH_SYS_SEL>, ++ <&topckgen CLK_TOP_ETH_XGMII_SEL>, ++ <&topckgen CLK_TOP_ETH_MII_SEL>, ++ <&topckgen CLK_TOP_NETSYS_SEL>, ++ <&topckgen CLK_TOP_NETSYS_500M_SEL>, ++ <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, ++ <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, ++ <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, ++ <&topckgen CLK_TOP_NETSYS_WARP_SEL>, ++ <ðsys CLK_ETHDMA_XGP1_EN>, ++ <ðsys CLK_ETHDMA_XGP2_EN>, ++ <ðsys CLK_ETHDMA_XGP3_EN>; ++ clock-names = "crypto", "fe", "gp2", "gp1", ++ "gp3", ++ "ethwarp_wocpu2", "ethwarp_wocpu1", ++ "ethwarp_wocpu0", "esw", "top_eth_gmii_sel", ++ "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", ++ "top_eth_sys_sel", "top_eth_xgmii_sel", ++ "top_eth_mii_sel", "top_netsys_sel", ++ "top_netsys_500m_sel", "top_netsys_pao_2x_sel", ++ "top_netsys_sync_250m_sel", ++ "top_netsys_ppefb_250m_sel", ++ "top_netsys_warp_sel","xgp1", "xgp2", "xgp3"; ++ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, ++ <&topckgen CLK_TOP_NETSYS_GSW_SEL>, ++ <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, ++ <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, ++ <&topckgen CLK_TOP_SGM_0_SEL>, ++ <&topckgen CLK_TOP_SGM_1_SEL>; ++ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, ++ <&topckgen CLK_TOP_NET1PLL_D4>, ++ <&topckgen CLK_TOP_NET1PLL_D8_D4>, ++ <&topckgen CLK_TOP_NET1PLL_D8_D4>, ++ <&apmixedsys CLK_APMIXED_SGMPLL>, ++ <&apmixedsys CLK_APMIXED_SGMPLL>; ++ mediatek,ethsys = <ðsys>; ++ mediatek,infracfg = <&topmisc>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gmac0: mac@0 { ++ compatible = "mediatek,eth-mac"; ++ reg = <0>; ++ phy-mode = "internal"; ++ ++ fixed-link { ++ speed = <10000>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ ++ gmac1: mac@1 { ++ compatible = "mediatek,eth-mac"; ++ reg = <1>; ++ status = "disabled"; ++ }; ++ ++ gmac2: mac@2 { ++ compatible = "mediatek,eth-mac"; ++ reg = <2>; ++ status = "disabled"; ++ }; ++ ++ mdio_bus: mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* internal 2.5G PHY */ ++ int_2p5g_phy: ethernet-phy@f { ++ reg = <15>; ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ phy-mode = "internal"; ++ }; ++ }; ++ }; + }; + + thermal-zones { diff --git a/target/linux/mediatek/patches-6.12/179-arm64-dts-mediatek-mt7988-add-switch-node.patch b/target/linux/mediatek/patches-6.12/179-arm64-dts-mediatek-mt7988-add-switch-node.patch new file mode 100644 index 0000000000..de43734c26 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/179-arm64-dts-mediatek-mt7988-add-switch-node.patch @@ -0,0 +1,228 @@ +From patchwork Sun May 11 14:19:25 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084123 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch node +Date: Sun, 11 May 2025 16:19:25 +0200 +Message-ID: <20250511141942.10284-10-linux@fw-web.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> +References: <20250511141942.10284-1-linux@fw-web.de> +MIME-Version: 1.0 +X-Mail-ID: a24ecea1-b7fd-4cb4-a93d-b29036e2e6ac +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +From: Frank Wunderlich + +Add mt7988 builtin mt753x switch nodes. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 166 ++++++++++++++++++++++ + 1 file changed, 166 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -5,6 +5,7 @@ + #include + #include + #include ++#include + + / { + compatible = "mediatek,mt7988a"; +@@ -748,6 +749,159 @@ + #reset-cells = <1>; + }; + ++ switch: switch@15020000 { ++ compatible = "mediatek,mt7988-switch"; ++ reg = <0 0x15020000 0 0x8000>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gsw_port0: port@0 { ++ reg = <0>; ++ phy-mode = "internal"; ++ phy-handle = <&gsw_phy0>; ++ }; ++ ++ gsw_port1: port@1 { ++ reg = <1>; ++ phy-mode = "internal"; ++ phy-handle = <&gsw_phy1>; ++ }; ++ ++ gsw_port2: port@2 { ++ reg = <2>; ++ phy-mode = "internal"; ++ phy-handle = <&gsw_phy2>; ++ }; ++ ++ gsw_port3: port@3 { ++ reg = <3>; ++ phy-mode = "internal"; ++ phy-handle = <&gsw_phy3>; ++ }; ++ ++ port@6 { ++ reg = <6>; ++ ethernet = <&gmac0>; ++ phy-mode = "internal"; ++ ++ fixed-link { ++ speed = <10000>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ }; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mediatek,pio = <&pio>; ++ ++ gsw_phy0: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ interrupts = <0>; ++ phy-mode = "internal"; ++ nvmem-cells = <&phy_calibration_p0>; ++ nvmem-cell-names = "phy-cal-data"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gsw_phy0_led0: led@0 { ++ reg = <0>; ++ status = "disabled"; ++ }; ++ ++ gsw_phy0_led1: led@1 { ++ reg = <1>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ gsw_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ interrupts = <1>; ++ phy-mode = "internal"; ++ nvmem-cells = <&phy_calibration_p1>; ++ nvmem-cell-names = "phy-cal-data"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gsw_phy1_led0: led@0 { ++ reg = <0>; ++ status = "disabled"; ++ }; ++ ++ gsw_phy1_led1: led@1 { ++ reg = <1>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ gsw_phy2: ethernet-phy@2 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <2>; ++ interrupts = <2>; ++ phy-mode = "internal"; ++ nvmem-cells = <&phy_calibration_p2>; ++ nvmem-cell-names = "phy-cal-data"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gsw_phy2_led0: led@0 { ++ reg = <0>; ++ status = "disabled"; ++ }; ++ ++ gsw_phy2_led1: led@1 { ++ reg = <1>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ gsw_phy3: ethernet-phy@3 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <3>; ++ interrupts = <3>; ++ phy-mode = "internal"; ++ nvmem-cells = <&phy_calibration_p3>; ++ nvmem-cell-names = "phy-cal-data"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gsw_phy3_led0: led@0 { ++ reg = <0>; ++ status = "disabled"; ++ }; ++ ++ gsw_phy3_led1: led@1 { ++ reg = <1>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ }; ++ }; ++ + ethwarp: clock-controller@15031000 { + compatible = "mediatek,mt7988-ethwarp"; + reg = <0 0x15031000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/180-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolingmaps.patch b/target/linux/mediatek/patches-6.12/180-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolingmaps.patch new file mode 100644 index 0000000000..4e3d4ae8c0 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/180-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolingmaps.patch @@ -0,0 +1,98 @@ +From patchwork Sun May 11 14:26:50 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084133 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 10/14] arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and + coolingmaps +Date: Sun, 11 May 2025 16:26:50 +0200 +Message-ID: <20250511142655.11007-1-frank-w@public-files.de> +X-Mailer: git-send-email 2.43.0 +MIME-Version: 1.0 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +Add Fan and cooling maps for Bananpi-R4 board. + +Signed-off-by: Frank Wunderlich +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 29 +++++++++++++++++++ + 1 file changed, 29 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -12,6 +12,15 @@ + stdout-path = "serial0:115200n8"; + }; + ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */ ++ cooling-levels = <0 80 128 255>; ++ #cooling-cells = <2>; ++ pwms = <&pwm 0 50000>; ++ status = "okay"; ++ }; ++ + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; +@@ -73,6 +82,26 @@ + type = "active"; + }; + }; ++ ++ cooling-maps { ++ map-cpu-active-high { ++ /* active: set fan to cooling level 2 */ ++ cooling-device = <&fan 3 3>; ++ trip = <&cpu_trip_active_high>; ++ }; ++ ++ map-cpu-active-med { ++ /* active: set fan to cooling level 1 */ ++ cooling-device = <&fan 2 2>; ++ trip = <&cpu_trip_active_med>; ++ }; ++ ++ map-cpu-active-low { ++ /* active: set fan to cooling level 0 */ ++ cooling-device = <&fan 1 1>; ++ trip = <&cpu_trip_active_low>; ++ }; ++ }; + }; + + &i2c0 { diff --git a/target/linux/mediatek/patches-6.12/181-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-nodes.patch b/target/linux/mediatek/patches-6.12/181-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-nodes.patch new file mode 100644 index 0000000000..c5c5e83e92 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/181-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-nodes.patch @@ -0,0 +1,99 @@ +From patchwork Sun May 11 14:26:51 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084136 +Received: from frank-u24 ([194.15.84.99]) by mail.gmx.net (mrgmx104 + [212.227.17.168]) with ESMTPSA (Nemesis) id 1MD9XF-1u5YvB0cIj-00FOt5; Sun, 11 + May 2025 16:27:04 +0200 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 11/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure + spi-nodes +Date: Sun, 11 May 2025 16:26:51 +0200 +Message-ID: <20250511142655.11007-2-frank-w@public-files.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> +References: <20250511142655.11007-1-frank-w@public-files.de> +MIME-Version: 1.0 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +Configure and enable SPI nodes on Bananapi R4 board. + +Signed-off-by: Frank Wunderlich +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 32 +++++++++++++++++++ + 1 file changed, 32 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -401,6 +401,38 @@ + status = "okay"; + }; + ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_flash_pins>; ++ status = "okay"; ++ ++ spi_nand: flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ }; ++}; ++ ++&spi1 { ++ status = "okay"; ++}; ++ ++&spi_nand { ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x200000>; ++ read-only; ++ }; ++ }; ++}; ++ + &ssusb1 { + status = "okay"; + }; diff --git a/target/linux/mediatek/patches-6.12/182-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-for-cci.patch b/target/linux/mediatek/patches-6.12/182-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-for-cci.patch new file mode 100644 index 0000000000..f692a6f1c4 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/182-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-for-cci.patch @@ -0,0 +1,68 @@ +From patchwork Sun May 11 14:26:52 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084137 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 12/14] arm64: dts: mediatek: mt7988a-bpi-r4: add + proc-supply for cci +Date: Sun, 11 May 2025 16:26:52 +0200 +Message-ID: <20250511142655.11007-3-frank-w@public-files.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> +References: <20250511142655.11007-1-frank-w@public-files.de> +MIME-Version: 1.0 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +CCI requires proc-supply. Add it on board level. + +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -40,6 +40,10 @@ + }; + }; + ++&cci { ++ proc-supply = <&rt5190_buck3>; ++}; ++ + &cpu0 { + proc-supply = <&rt5190_buck3>; + }; diff --git a/target/linux/mediatek/patches-6.12/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch b/target/linux/mediatek/patches-6.12/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch new file mode 100644 index 0000000000..9861dc0f5b --- /dev/null +++ b/target/linux/mediatek/patches-6.12/183-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-link-to-gmac.patch @@ -0,0 +1,138 @@ +From patchwork Sun May 11 14:26:53 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084128 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 13/14] arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages + and link to gmac +Date: Sun, 11 May 2025 16:26:53 +0200 +Message-ID: <20250511142655.11007-4-frank-w@public-files.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> +References: <20250511142655.11007-1-frank-w@public-files.de> +MIME-Version: 1.0 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +Add SFP cages to Bananapi-R4 board. The 2.5g phy variant only contains the +wan-SFP, so add this to common dtsi and the lan-sfp only to the dual-SFP +variant. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts | 11 +++++++++++ + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 18 ++++++++++++++++++ + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 18 ++++++++++++++++++ + 3 files changed, 47 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts +@@ -9,3 +9,14 @@ + model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)"; + chassis-type = "embedded"; + }; ++ ++&gmac1 { ++ phy-mode = "internal"; ++ phy-connection-type = "internal"; ++ phy = <&int_2p5g_phy>; ++}; ++ ++&int_2p5g_phy { ++ pinctrl-names = "i2p5gbe-led"; ++ pinctrl-0 = <&i2p5gbe_led0_pins>; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -8,6 +8,24 @@ + compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; + model = "Banana Pi BPI-R4 (2x SFP+)"; + chassis-type = "embedded"; ++ ++ /* SFP2 cage (LAN) */ ++ sfp2: sfp2 { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c_sfp2>; ++ los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>; ++ mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>; ++ tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>; ++ tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>; ++ rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>; ++ maximum-power-milliwatt = <3000>; ++ }; ++}; ++ ++&gmac1 { ++ sfp = <&sfp2>; ++ managed = "in-band-status"; ++ phy-mode = "usxgmii"; + }; + + &pca9545 { +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -38,6 +38,18 @@ + regulator-boot-on; + regulator-always-on; + }; ++ ++ /* SFP1 cage (WAN) */ ++ sfp1: sfp1 { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c_sfp1>; ++ los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; ++ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; ++ tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; ++ tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; ++ rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; ++ maximum-power-milliwatt = <3000>; ++ }; + }; + + &cci { +@@ -108,6 +120,12 @@ + }; + }; + ++&gmac2 { ++ sfp = <&sfp1>; ++ managed = "in-band-status"; ++ phy-mode = "usxgmii"; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; diff --git a/target/linux/mediatek/patches-6.12/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch b/target/linux/mediatek/patches-6.12/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch new file mode 100644 index 0000000000..0bdc6c9a15 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/184-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-phys-and-leds.patch @@ -0,0 +1,113 @@ +From patchwork Sun May 11 14:26:54 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 14084132 +From: Frank Wunderlich +To: Andrew Lunn , + Vladimir Oltean , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Matthias Brugger , + AngeloGioacchino Del Regno +Subject: [PATCH v1 14/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure + switch phys and leds +Date: Sun, 11 May 2025 16:26:54 +0200 +Message-ID: <20250511142655.11007-5-frank-w@public-files.de> +X-Mailer: git-send-email 2.43.0 +In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de> +References: <20250511142655.11007-1-frank-w@public-files.de> +MIME-Version: 1.0 +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, Landen Chao , + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , + netdev@vger.kernel.org, Sean Wang , + Daniel Golle , linux-kernel@vger.kernel.org, + DENG Qingfang , linux-mediatek@lists.infradead.org, + Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, + Felix Fietkau +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +Assign pinctrl to switch phys and leds. + +Signed-off-by: Daniel Golle +Signed-off-by: Frank Wunderlich +--- + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 40 +++++++++++++++++++ + 1 file changed, 40 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -126,6 +126,54 @@ + phy-mode = "usxgmii"; + }; + ++&gsw_phy0 { ++ pinctrl-names = "gbe-led"; ++ label = "wan"; ++ pinctrl-0 = <&gbe0_led0_pins>; ++}; ++ ++&gsw_phy0_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_WAN; ++ color = ; ++}; ++ ++&gsw_phy1 { ++ pinctrl-names = "gbe-led"; ++ label = "lan1"; ++ pinctrl-0 = <&gbe1_led0_pins>; ++}; ++ ++&gsw_phy1_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_phy2 { ++ pinctrl-names = "gbe-led"; ++ label = "lan2"; ++ pinctrl-0 = <&gbe2_led0_pins>; ++}; ++ ++&gsw_phy2_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_phy3 { ++ pinctrl-names = "gbe-led"; ++ label = "lan3"; ++ pinctrl-0 = <&gbe3_led0_pins>; ++}; ++ ++&gsw_phy3_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; diff --git a/target/linux/mediatek/patches-6.12/187-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch b/target/linux/mediatek/patches-6.12/187-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch new file mode 100644 index 0000000000..efa2121812 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/187-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch @@ -0,0 +1,33 @@ +From 109a9c8409f85d777f8ffa3fe145498a1fec0f1e Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 8 May 2025 04:03:58 +0100 +Subject: [PATCH] arm64: dts: mt7988a: add serial1 and serial2 aliases + +Add aliases serial1 and serial2, so boards can make use of the +auxilary UARTs of the MediaTek MT7988 SoC. + +Signed-off-by: Daniel Golle +--- + arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -297,7 +297,7 @@ + status = "disabled"; + }; + +- serial@11000100 { ++ serial1: serial@11000100 { + compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; + reg = <0 0x11000100 0 0x100>; + interrupts = ; +@@ -308,7 +308,7 @@ + status = "disabled"; + }; + +- serial@11000200 { ++ serial2: serial@11000200 { + compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; + reg = <0 0x11000200 0 0x100>; + interrupts = ; diff --git a/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch b/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch new file mode 100644 index 0000000000..7641c36711 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch @@ -0,0 +1,1430 @@ +From bb72bb160130c35fa4b7dedd0f881085f0af1313 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 22 Feb 2023 19:15:49 +0000 +Subject: [PATCH 31/32] dts: arm64: mediatek: add MT7988A reference board + device tree + +Complete device tree include for the MediaTek MT7988A SoC and make use +of it by adding the device tree of the MediaTek MT7988A Reference Board +as well as overlays for various options regarding the connected +network interfaces and storage devices present. + +Available options for GMAC1 (eth0): + * internal 4-port 1GE switch + +Available options for GMAC2 (eth1): + * internal 2.5G PHY + * external MaxLinear 2.5G PHY + * external Aquantia AQR113C PHY + * SFP+ cage + +Available options for GMAC3 (eth2): + * external MaxLinear 2.5G PHY + * external Aquantia AQR113C PHY + * SFP+ cage + +Available storage options: + * eMMC + * SNFI (ECC-less SPI-NAND with BCH done in SoC) + * SPI-NAND (with ECC done by the flash die) + * SPI-NOR + * SD card + +Signed-off-by: Sam Shih +Signed-off-by: Daniel Golle +--- a/arch/arm64/boot/dts/mediatek/Makefile ++++ b/arch/arm64/boot/dts/mediatek/Makefile +@@ -24,6 +24,19 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-b + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb.dtb ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-emmc.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-aqr.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-i2p5g-phy.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-mxl.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-sfp.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-aqr.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-mxl.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-sfp.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-sd.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-snfi-nand.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-spim-nand.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-spim-nor.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso +@@ -0,0 +1,33 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2021 MediaTek Inc. ++ * Author: Frank Wunderlich ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&mmc0>; ++ __overlay__ { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_emmc_51>; ++ pinctrl-1 = <&mmc0_pins_emmc_51>; ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ hs400-ds-delay = <0x12814>; ++ vqmmc-supply = <®_1p8v>; ++ vmmc-supply = <®_3p3v>; ++ non-removable; ++ no-sd; ++ no-sdio; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso +@@ -0,0 +1,41 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&mdio_bus>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* external Aquantia AQR113C */ ++ phy0: ethernet-phy@0 { ++ reg = <0>; ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>; ++ reset-assert-us = <100000>; ++ reset-deassert-us = <221000>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gmac1>; ++ __overlay__ { ++ phy-mode = "usxgmii"; ++ phy-connection-type = "usxgmii"; ++ phy = <&phy0>; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso +@@ -0,0 +1,30 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&gmac1>; ++ __overlay__ { ++ phy-mode = "internal"; ++ phy-connection-type = "internal"; ++ phy = <&int_2p5g_phy>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&int_2p5g_phy>; ++ __overlay__ { ++ pinctrl-names = "i2p5gbe-led"; ++ pinctrl-0 = <&i2p5gbe_led0_pins>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso +@@ -0,0 +1,39 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&mdio_bus>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* external Maxlinear GPY211C */ ++ phy13: ethernet-phy@13 { ++ reg = <13>; ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ phy-mode = "2500base-x"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gmac1>; ++ __overlay__ { ++ phy-mode = "2500base-x"; ++ phy-connection-type = "2500base-x"; ++ phy = <&phy13>; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso +@@ -0,0 +1,47 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&i2c2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sfp_esp1: sfp@1 { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c2>; ++ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; ++ los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>; ++ tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; ++ maximum-power-milliwatt = <3000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gmac1>; ++ __overlay__ { ++ phy-mode = "10gbase-r"; ++ managed = "in-band-status"; ++ sfp = <&sfp_esp1>; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso +@@ -0,0 +1,41 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&mdio_bus>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* external Aquantia AQR113C */ ++ phy8: ethernet-phy@8 { ++ reg = <8>; ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>; ++ reset-assert-us = <100000>; ++ reset-deassert-us = <221000>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gmac2>; ++ __overlay__ { ++ phy-mode = "usxgmii"; ++ phy-connection-type = "usxgmii"; ++ phy = <&phy8>; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso +@@ -0,0 +1,39 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&mdio_bus>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* external Maxlinear GPY211C */ ++ phy5: ethernet-phy@5 { ++ reg = <5>; ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ phy-mode = "2500base-x"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gmac2>; ++ __overlay__ { ++ phy-mode = "2500base-x"; ++ phy-connection-type = "2500base-x"; ++ phy = <&phy5>; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso +@@ -0,0 +1,47 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&i2c1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sfp_esp0: sfp@0 { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c1>; ++ mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>; ++ los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; ++ tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>; ++ maximum-power-milliwatt = <3000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gmac2>; ++ __overlay__ { ++ phy-mode = "10gbase-r"; ++ managed = "in-band-status"; ++ sfp = <&sfp_esp0>; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso +@@ -0,0 +1,31 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 MediaTek Inc. ++ * Author: Frank Wunderlich ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@1 { ++ target-path = <&mmc0>; ++ __overlay__ { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_sdcard>; ++ pinctrl-1 = <&mmc0_pins_sdcard>; ++ cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>; ++ bus-width = <4>; ++ max-frequency = <52000000>; ++ cap-sd-highspeed; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_3p3v>; ++ no-mmc; ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso +@@ -0,0 +1,70 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&snand>; ++ __overlay__ { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ mediatek,nmbm; ++ mediatek,bmt-max-ratio = <1>; ++ mediatek,bmt-max-reserved-blocks = <64>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x00000 0x0100000>; ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x0100000 0x0080000>; ++ }; ++ ++ partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x0400000>; ++ }; ++ ++ partition@580000 { ++ label = "FIP"; ++ reg = <0x580000 0x0200000>; ++ }; ++ ++ partition@780000 { ++ label = "ubi"; ++ reg = <0x780000 0x7080000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&bch>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand-factory.dtso +@@ -0,0 +1,87 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&ubi_part>; ++ ++ __overlay__ { ++ volumes { ++ ubi_factory: ubi-volume-factory { ++ volname = "factory"; ++ ++ nvmem-layout { ++ compatible = "fixed-layout"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ eeprom_wmac: eeprom@0 { ++ reg = <0x0 0x1e00>; ++ }; ++ ++ gmac2_mac: eeprom@fffee { ++ reg = <0xfffee 0x6>; ++ }; ++ ++ gmac1_mac: eeprom@ffff4 { ++ reg = <0xffff4 0x6>; ++ }; ++ ++ gmac0_mac: eeprom@ffffa { ++ reg = <0xffffa 0x6>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pcie0>; ++ __overlay__ { ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ pcie@0,0 { ++ reg = <0x0000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ wifi@0,0 { ++ compatible = "mediatek,mt76"; ++ reg = <0x0000 0 0 0 0>; ++ nvmem-cell-names = "eeprom"; ++ nvmem-cells = <&eeprom_wmac>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gmac0>; ++ __overlay__ { ++ nvmem-cell-names = "mac-address"; ++ nvmem-cells = <&gmac0_mac>; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&gmac1>; ++ __overlay__ { ++ nvmem-cell-names = "mac-address"; ++ nvmem-cells = <&gmac1_mac>; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&gmac2>; ++ __overlay__ { ++ nvmem-cell-names = "mac-address"; ++ nvmem-cells = <&gmac2_mac>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso +@@ -0,0 +1,66 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_flash_pins>; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ mediatek,nmbm; ++ mediatek,bmt-max-ratio = <1>; ++ mediatek,bmt-max-reserved-blocks = <64>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x00000 0x0100000>; ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x0100000 0x0080000>; ++ }; ++ ++ partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x0400000>; ++ }; ++ ++ partition@580000 { ++ label = "FIP"; ++ reg = <0x580000 0x0200000>; ++ }; ++ ++ partition@780000 { ++ label = "ubi"; ++ reg = <0x780000 0x7080000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso +@@ -0,0 +1,61 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&spi2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2_flash_pins>; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "jedec,spi-nor"; ++ spi-cal-enable; ++ spi-cal-mode = "read-data"; ++ spi-cal-datalen = <7>; ++ spi-cal-data = /bits/ 8 < ++ 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ ++ spi-cal-addrlen = <1>; ++ spi-cal-addr = /bits/ 32 <0x0>; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x0 0x40000>; ++ }; ++ partition@40000 { ++ label = "u-boot-env"; ++ reg = <0x40000 0x10000>; ++ }; ++ partition@50000 { ++ label = "Factory"; ++ reg = <0x50000 0x200000>; ++ }; ++ partition@250000 { ++ label = "FIP"; ++ reg = <0x250000 0x80000>; ++ }; ++ partition@2D0000 { ++ label = "firmware"; ++ reg = <0x2d0000 0x1d30000>; ++ }; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts +@@ -0,0 +1,470 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Sam.Shih ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++ ++#include "mt7988a.dtsi" ++ ++/ { ++ model = "MediaTek MT7988A Reference Board"; ++ compatible = "mediatek,mt7988a-rfb", ++ "mediatek,mt7988"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n1 loglevel=8 \ ++ earlycon=uart8250,mmio32,0x11000000 \ ++ pci=pcie_bus_perf"; ++ }; ++ ++ memory { ++ reg = <0 0x40000000 0 0x40000000>; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++ð { ++ pinctrl-0 = <&mdio0_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&gmac0 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu1 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu2 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cpu3 { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++&cci { ++ proc-supply = <&rt5190_buck3>; ++}; ++ ++ð { ++ status = "okay"; ++}; ++ ++&switch { ++ status = "okay"; ++}; ++ ++&gsw_phy0 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe0_led0_pins>; ++}; ++ ++&gsw_phy0_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_port0 { ++ label = "lan0"; ++}; ++ ++&gsw_phy1 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe1_led0_pins>; ++}; ++ ++&gsw_phy1_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_port1 { ++ label = "lan1"; ++}; ++ ++&gsw_phy2 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe2_led0_pins>; ++}; ++ ++&gsw_phy2_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_port2 { ++ label = "lan2"; ++}; ++ ++&gsw_phy3 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe3_led0_pins>; ++}; ++ ++&gsw_phy3_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_port3 { ++ label = "lan3"; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ status = "okay"; ++ ++ rt5190a_64: rt5190a@64 { ++ compatible = "richtek,rt5190a"; ++ reg = <0x64>; ++ /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ ++ vin2-supply = <&rt5190_buck1>; ++ vin3-supply = <&rt5190_buck1>; ++ vin4-supply = <&rt5190_buck1>; ++ ++ regulators { ++ rt5190_buck1: buck1 { ++ regulator-name = "rt5190a-buck1"; ++ regulator-min-microvolt = <5090000>; ++ regulator-max-microvolt = <5090000>; ++ regulator-allowed-modes = ++ ; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ buck2 { ++ regulator-name = "vcore"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ rt5190_buck3: buck3 { ++ regulator-name = "vproc"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ }; ++ buck4 { ++ regulator-name = "rt5190a-buck4"; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-allowed-modes = ++ ; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ldo { ++ regulator-name = "rt5190a-ldo"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; ++ ++&pcie0 { ++ status = "okay"; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++&pcie2 { ++ status = "disabled"; ++}; ++ ++&pcie3 { ++ status = "okay"; ++}; ++ ++&pio { ++ mdio0_pins: mdio0-pins { ++ mux { ++ function = "eth"; ++ groups = "mdc_mdio0"; ++ }; ++ ++ conf { ++ groups = "mdc_mdio0"; ++ drive-strength = ; ++ }; ++ }; ++ ++ gbe0_led0_pins: gbe0-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe0_led0"; ++ }; ++ }; ++ ++ gbe1_led0_pins: gbe1-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe1_led0"; ++ }; ++ }; ++ ++ gbe2_led0_pins: gbe2-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe2_led0"; ++ }; ++ }; ++ ++ gbe3_led0_pins: gbe3-led0-pins { ++ mux { ++ function = "led"; ++ groups = "gbe3_led0"; ++ }; ++ }; ++ ++ gbe0_led1_pins: gbe0-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe0_led1"; ++ }; ++ }; ++ ++ gbe1_led1_pins: gbe1-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe1_led1"; ++ }; ++ }; ++ ++ gbe2_led1_pins: gbe2-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe2_led1"; ++ }; ++ }; ++ ++ gbe3_led1_pins: gbe3-led1-pins { ++ mux { ++ function = "led"; ++ groups = "gbe3_led1"; ++ }; ++ }; ++ ++ i2c0_pins: i2c0-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c0_1"; ++ }; ++ }; ++ ++ i2c1_pins: i2c1-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_0"; ++ }; ++ }; ++ ++ i2c1_sfp_pins: i2c1-sfp-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_sfp"; ++ }; ++ }; ++ ++ i2c2_0_pins: i2c2-g0-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_0"; ++ }; ++ }; ++ ++ i2c2_1_pins: i2c2-g1-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_1"; ++ }; ++ }; ++ ++ i2p5gbe_led0_pins: 2p5gbe-led0-pins { ++ mux { ++ function = "led"; ++ groups = "2p5gbe_led0"; ++ }; ++ }; ++ ++ i2p5gbe_led1_pins: 2p5gbe-led1-pins { ++ mux { ++ function = "led"; ++ groups = "2p5gbe_led1"; ++ }; ++ }; ++ ++ mmc0_pins_emmc_51: mmc0-emmc-51-pins { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ }; ++ ++ mmc0_pins_sdcard: mmc0-sdcard-pins { ++ mux { ++ function = "flash"; ++ groups = "sdcard"; ++ }; ++ }; ++ ++ spi0_pins: spi0-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0"; ++ }; ++ }; ++ ++ spi0_flash_pins: spi0-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ }; ++ ++ spi2_pins: spi2-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2"; ++ }; ++ }; ++ ++ spi2_flash_pins: spi2-flash-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2", "spi2_wp_hold"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0"; ++ }; ++ }; ++ ++ uart1_0_pins: uart1-0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart1_0"; ++ }; ++ }; ++ ++ uart1_1_pins: uart1-1-pins { ++ mux { ++ function = "uart"; ++ groups = "uart1_1"; ++ }; ++ }; ++ ++ uart1_2_pins: uart1-2-pins { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ uart1_2_lite_pins: uart1-2-lite-pins { ++ mux { ++ function = "uart"; ++ groups = "uart1_2_lite"; ++ }; ++ }; ++ ++ uart2_pins: uart2-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2"; ++ }; ++ }; ++ ++ uart2_0_pins: uart2-0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2_0"; ++ }; ++ }; ++ ++ uart2_1_pins: uart2-1-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2_1"; ++ }; ++ }; ++ ++ uart2_2_pins: uart2-2-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2_2"; ++ }; ++ }; ++ ++ uart2_3_pins: uart2-3-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2_3"; ++ }; ++ }; ++}; ++ ++&ssusb0 { ++ status = "okay"; ++}; ++ ++&ssusb1 { ++ status = "okay"; ++}; ++ ++&tphy { ++ status = "okay"; ++}; ++ ++&serial0 { ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "okay"; ++}; ++ ++&xsphy { ++ status = "okay"; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -193,7 +193,7 @@ + }; + + pio: pinctrl@1001f000 { +- compatible = "mediatek,mt7988-pinctrl"; ++ compatible = "mediatek,mt7988-pinctrl", "syscon"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d00000 0 0x1000>, +@@ -212,6 +212,13 @@ + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + ++ snfi_pins: snfi-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; +@@ -278,6 +285,60 @@ + status = "disabled"; + }; + ++ sgmiisys0: syscon@10060000 { ++ compatible = "mediatek,mt7988-sgmiisys", ++ "mediatek,mt7988-sgmiisys0", ++ "syscon", ++ "simple-mfd"; ++ reg = <0 0x10060000 0 0x1000>; ++ resets = <&watchdog 1>; ++ #clock-cells = <1>; ++ ++ sgmiipcs0: pcs { ++ compatible = "mediatek,mt7988-sgmii"; ++ clocks = <&topckgen CLK_TOP_SGM_0_SEL>, ++ <&sgmiisys0 CLK_SGM0_TX_EN>, ++ <&sgmiisys0 CLK_SGM0_RX_EN>; ++ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; ++ #pcs-cells = <0>; ++ }; ++ }; ++ ++ sgmiisys1: syscon@10070000 { ++ compatible = "mediatek,mt7988-sgmiisys", ++ "mediatek,mt7988-sgmiisys1", ++ "syscon", ++ "simple-mfd"; ++ reg = <0 0x10070000 0 0x1000>; ++ resets = <&watchdog 2>; ++ #clock-cells = <1>; ++ ++ sgmiipcs1: pcs { ++ compatible = "mediatek,mt7988-sgmii"; ++ clocks = <&topckgen CLK_TOP_SGM_1_SEL>, ++ <&sgmiisys1 CLK_SGM1_TX_EN>, ++ <&sgmiisys1 CLK_SGM1_RX_EN>; ++ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; ++ #pcs-cells = <0>; ++ }; ++ }; ++ ++ usxgmiisys0: pcs@10080000 { ++ compatible = "mediatek,mt7988-usxgmiisys"; ++ reg = <0 0x10080000 0 0x1000>; ++ resets = <&watchdog 12>; ++ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>; ++ #pcs-cells = <0>; ++ }; ++ ++ usxgmiisys1: pcs@10081000 { ++ compatible = "mediatek,mt7988-usxgmiisys"; ++ reg = <0 0x10081000 0 0x1000>; ++ resets = <&watchdog 13>; ++ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>; ++ #pcs-cells = <0>; ++ }; ++ + mcusys: mcusys@100e0000 { + compatible = "mediatek,mt7988-mcusys", "syscon"; + reg = <0 0x100e0000 0 0x1000>; +@@ -319,6 +380,32 @@ + status = "disabled"; + }; + ++ snand: spi@11001000 { ++ compatible = "mediatek,mt7986-snand"; ++ reg = <0 0x11001000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_SPINFI>, ++ <&infracfg CLK_INFRA_NFI>, ++ <&infracfg CLK_INFRA_66M_NFI_HCK>; ++ clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; ++ nand-ecc-engine = <&bch>; ++ mediatek,quad-spi; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&snfi_pins>; ++ status = "disabled"; ++ }; ++ ++ bch: ecc@11002000 { ++ compatible = "mediatek,mt7686-ecc"; ++ reg = <0 0x11002000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_NFI>; ++ clock-names = "nfiecc_clk"; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@11003000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, +@@ -425,7 +512,7 @@ + <0 0x0f0f0018 0 0x20>; + }; + +- usb@11190000 { ++ ssusb0: usb@11190000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, + <0 0x11193e00 0 0x0100>; +@@ -459,6 +546,35 @@ + status = "disabled"; + }; + ++ afe: audio-controller@11210000 { ++ compatible = "mediatek,mt79xx-audio"; ++ reg = <0 0x11210000 0 0x9000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, ++ <&infracfg CLK_INFRA_AUD_26M>, ++ <&infracfg CLK_INFRA_AUD_L>, ++ <&infracfg CLK_INFRA_AUD_AUD>, ++ <&infracfg CLK_INFRA_AUD_EG2>, ++ <&topckgen CLK_TOP_AUD_SEL>, ++ <&topckgen CLK_TOP_AUD_I2S_M>; ++ clock-names = "aud_bus_ck", ++ "aud_26m_ck", ++ "aud_l_ck", ++ "aud_aud_ck", ++ "aud_eg2_ck", ++ "aud_sel", ++ "aud_i2s_m"; ++ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, ++ <&topckgen CLK_TOP_A1SYS_SEL>, ++ <&topckgen CLK_TOP_AUD_L_SEL>, ++ <&topckgen CLK_TOP_A_TUNER_SEL>; ++ assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, ++ <&topckgen CLK_TOP_APLL2_D4>, ++ <&apmixedsys CLK_APMIXED_APLL2>, ++ <&topckgen CLK_TOP_APLL2_D4>; ++ status = "disabled"; ++ }; ++ + mmc0: mmc@11230000 { + compatible = "mediatek,mt7988-mmc"; + reg = <0 0x11230000 0 0x1000>, +@@ -721,6 +837,10 @@ + #address-cells = <1>; + #size-cells = <1>; + ++ cpufreq_calibration: calib@278 { ++ reg = <0x278 0x1>; ++ }; ++ + lvts_calibration: calib@918 { + reg = <0x918 0x28>; + }; +@@ -984,12 +1104,16 @@ + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; ++ pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>; ++ phys = <&xfi_tphy1>; + status = "disabled"; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; ++ pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>; ++ phys = <&xfi_tphy0>; + status = "disabled"; + }; + +@@ -1002,9 +1126,37 @@ + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2p5gbe_led0: i2p5gbe-led0@0 { ++ reg = <0>; ++ function = LED_FUNCTION_LAN; ++ status = "disabled"; ++ }; ++ ++ i2p5gbe_led1: i2p5gbe-led1@1 { ++ reg = <1>; ++ function = LED_FUNCTION_LAN; ++ status = "disabled"; ++ }; ++ }; + }; + }; + }; ++ ++ crypto: crypto@15600000 { ++ compatible = "inside-secure,safexcel-eip197b"; ++ reg = <0 0x15600000 0 0x180000>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "ring0", "ring1", "ring2", "ring3"; ++ status = "okay"; ++ }; + }; + + thermal-zones { diff --git a/target/linux/mediatek/patches-6.12/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch b/target/linux/mediatek/patches-6.12/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch new file mode 100644 index 0000000000..a2643ea0a3 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch @@ -0,0 +1,487 @@ +From f7fb27b62f0ef45f94f4ec33c608bfad1c7691b3 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 26 Jul 2023 14:56:28 +0100 +Subject: [PATCH 32/32] WIP: add BPi-R4 + +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts +@@ -20,3 +20,16 @@ + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; + }; ++ ++&gmac1 { ++ phy-mode = "internal"; ++ phy-connection-type = "internal"; ++ phy = <&int_2p5g_phy>; ++ openwrt,netdev-name = "lan4"; ++ status = "okay"; ++}; ++ ++&int_2p5g_phy { ++ pinctrl-names = "i2p5gbe-led"; ++ pinctrl-0 = <&i2p5gbe_led0_pins>; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso +@@ -0,0 +1,56 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2021 MediaTek Inc. ++ * Author: Frank Wunderlich ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; ++}; ++ ++&{/soc/mmc@11230000} { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_emmc_51>; ++ pinctrl-1 = <&mmc0_pins_emmc_51>; ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ hs400-ds-delay = <0x12814>; ++ vqmmc-supply = <®_1p8v>; ++ vmmc-supply = <®_3p3v>; ++ non-removable; ++ no-sd; ++ no-sdio; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ partitions { ++ compatible = "gpt-partitions"; ++ ++ block-partition-env { ++ partname = "ubootenv"; ++ nvmem-layout { ++ compatible = "u-boot,env-layout"; ++ }; ++ }; ++ ++ emmc_rootfs: block-partition-production { ++ partname = "production"; ++ }; ++ }; ++ }; ++}; ++ ++&{/chosen} { ++ rootdisk-emmc = <&emmc_rootfs>; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso +@@ -0,0 +1,19 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 ++ * Author: Daniel Golle ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; ++ ++ fragment@0 { ++ target = <&pcf8563>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso +@@ -0,0 +1,54 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 MediaTek Inc. ++ * Author: Frank Wunderlich ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; ++}; ++ ++&{/soc/mmc@11230000} { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_sdcard>; ++ pinctrl-1 = <&mmc0_pins_sdcard>; ++ cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>; ++ bus-width = <4>; ++ max-frequency = <52000000>; ++ cap-sd-highspeed; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_3p3v>; ++ no-mmc; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ partitions { ++ compatible = "gpt-partitions"; ++ ++ block-partition-env { ++ partname = "ubootenv"; ++ nvmem-layout { ++ compatible = "u-boot,env-layout"; ++ }; ++ }; ++ ++ sd_rootfs: block-partition-production { ++ partname = "production"; ++ }; ++ }; ++ }; ++}; ++ ++&{/chosen} { ++ rootdisk-sd = <&sd_rootfs>; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +@@ -35,3 +35,11 @@ + reg = <2>; + }; + }; ++ ++&gmac1 { ++ sfp = <&sfp2>; ++ managed = "in-band-status"; ++ phy-mode = "usxgmii"; ++ openwrt,netdev-name = "sfp-lan"; ++ status = "okay"; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +@@ -3,6 +3,8 @@ + /dts-v1/; + + #include ++#include ++#include + #include + + #include "mt7988a.dtsi" +@@ -10,6 +12,8 @@ + / { + chosen { + stdout-path = "serial0:115200n8"; ++ bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0"; ++ rootdisk-spim-nand = <&ubi_rootfs>; + }; + + fan: pwm-fan { +@@ -50,6 +54,141 @@ + rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <3000>; + }; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ ethernet1 = &gmac1; ++ ethernet2 = &gmac2; ++ serial0 = &serial0; ++ led-boot = &led_green; ++ led-failsafe = &led_green; ++ led-running = &led_green; ++ led-upgrade = &led_green; ++ }; ++ ++ memory { ++ reg = <0x00 0x40000000 0x00 0x10000000>; ++ }; ++ ++ /* SFP1 cage (WAN) */ ++ sfp1: sfp1 { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c_sfp1>; ++ los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; ++ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; ++ tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; ++ tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; ++ rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; ++ maximum-power-milliwatt = <3000>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ wps { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&pio 14 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ ++ led_green: led-green { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&pio 79 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ led_blue: led-blue { ++ function = LED_FUNCTION_WPS; ++ color = ; ++ gpios = <&pio 63 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ }; ++}; ++ ++ð { ++ status = "okay"; ++}; ++ ++&gmac0 { ++ status = "okay"; ++}; ++ ++&gmac2 { ++ sfp = <&sfp1>; ++ managed = "in-band-status"; ++ phy-mode = "usxgmii"; ++ openwrt,netdev-name = "sfp-wan"; ++ status = "okay"; ++}; ++ ++&switch { ++ status = "okay"; ++}; ++ ++&gsw_phy0 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe0_led0_pins>; ++}; ++ ++&gsw_port0 { ++ label = "wan"; ++}; ++ ++&gsw_phy0_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_WAN; ++ color = ; ++}; ++ ++&gsw_phy1 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe1_led0_pins>; ++}; ++ ++&gsw_port1 { ++ label = "lan1"; ++}; ++ ++&gsw_phy1_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_phy2 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe2_led0_pins>; ++}; ++ ++&gsw_port2 { ++ label = "lan2"; ++}; ++ ++&gsw_phy2_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; ++}; ++ ++&gsw_phy3 { ++ pinctrl-names = "gbe-led"; ++ pinctrl-0 = <&gbe3_led0_pins>; ++}; ++ ++&gsw_port3 { ++ label = "lan3"; ++}; ++ ++&gsw_phy3_led0 { ++ status = "okay"; ++ function = LED_FUNCTION_LAN; ++ color = ; + }; + + &cci { +@@ -174,6 +313,10 @@ + color = ; + }; + ++&cci { ++ proc-supply = <&rt5190_buck3>; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +@@ -265,6 +408,14 @@ + #size-cells = <0>; + reg = <1>; + }; ++ ++ i2c_wifi: i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ ++ status = "disabled"; ++ }; + }; + }; + +@@ -364,34 +515,6 @@ + }; + }; + +- gbe0_led1_pins: gbe0-led1-pins { +- mux { +- function = "led"; +- groups = "gbe0_led1"; +- }; +- }; +- +- gbe1_led1_pins: gbe1-led1-pins { +- mux { +- function = "led"; +- groups = "gbe1_led1"; +- }; +- }; +- +- gbe2_led1_pins: gbe2-led1-pins { +- mux { +- function = "led"; +- groups = "gbe2_led1"; +- }; +- }; +- +- gbe3_led1_pins: gbe3-led1-pins { +- mux { +- function = "led"; +- groups = "gbe3_led1"; +- }; +- }; +- + i2p5gbe_led0_pins: 2p5gbe-led0-pins { + mux { + function = "led"; +@@ -399,13 +522,6 @@ + }; + }; + +- i2p5gbe_led1_pins: 2p5gbe-led1-pins { +- mux { +- function = "led"; +- groups = "2p5gbe_led1"; +- }; +- }; +- + mmc0_pins_emmc_45: mmc0-emmc-45-pins { + mux { + function = "flash"; +@@ -427,40 +543,12 @@ + }; + }; + +- snfi_pins: snfi-pins { +- mux { +- function = "flash"; +- groups = "snfi"; +- }; +- }; +- +- spi0_pins: spi0-pins { +- mux { +- function = "spi"; +- groups = "spi0"; +- }; +- }; +- + spi0_flash_pins: spi0-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; +- +- spi2_pins: spi2-pins { +- mux { +- function = "spi"; +- groups = "spi2"; +- }; +- }; +- +- spi2_flash_pins: spi2-flash-pins { +- mux { +- function = "spi"; +- groups = "spi2", "spi2_wp_hold"; +- }; +- }; + }; + + &pwm { +@@ -500,6 +588,32 @@ + reg = <0x0 0x200000>; + read-only; + }; ++ ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0x7e00000>; ++ compatible = "linux,ubi"; ++ ++ volumes { ++ ubi-volume-ubootenv { ++ volname = "ubootenv"; ++ nvmem-layout { ++ compatible = "u-boot,env-redundant-bool-layout"; ++ }; ++ }; ++ ++ ubi-volume-ubootenv2 { ++ volname = "ubootenv2"; ++ nvmem-layout { ++ compatible = "u-boot,env-redundant-bool-layout"; ++ }; ++ }; ++ ++ ubi_rootfs: ubi-volume-fit { ++ volname = "fit"; ++ }; ++ }; ++ }; + }; + }; + diff --git a/target/linux/mediatek/patches-6.12/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-6.12/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch new file mode 100644 index 0000000000..bf6823147e --- /dev/null +++ b/target/linux/mediatek/patches-6.12/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch @@ -0,0 +1,106 @@ +From patchwork Tue Apr 26 19:51:36 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Daniel Golle +X-Patchwork-Id: 12827872 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF + for ; 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Tue, 26 Apr 2022 19:51:57 +0000 +Received: from fudo.makrotopia.org ([2a07:2ec0:3002::71]) + by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) + id 1njRE1-00G03h-9H; Tue, 26 Apr 2022 19:51:55 +0000 +Received: from local + by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) + (Exim 4.94.2) (envelope-from ) + id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200 +Date: Tue, 26 Apr 2022 20:51:36 +0100 +From: Daniel Golle +To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, + linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org +Cc: Rob Herring , + Krzysztof Kozlowski , + Matthias Brugger +Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range +Message-ID: +MIME-Version: 1.0 +Content-Disposition: inline +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220426_125153_359242_EA3D452C +X-CRM114-Status: GOOD ( 12.45 ) +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org + +With the current range specified for the CPU interface there is an +error message at boot: + +GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set + +Setting irqchip.gicv2_force_probe=1 in bootargs results in: + +GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB +GIC: Adjusting CPU interface base to 0x000000001032f000 +GIC: Using split EOI/Deactivate mode + +Using the adjusted CPU interface base and 8K size results in only the +final line remaining and fully working system as well as /proc/interrupts +showing additional IPI3,4,5,6: + +IPI3: 0 0 CPU stop (for crash dump) interrupts +IPI4: 0 0 Timer broadcast interrupts +IPI5: 0 0 IRQ work interrupts +IPI6: 0 0 CPU wake-up interrupts + +Signed-off-by: Daniel Golle +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -345,7 +345,7 @@ + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10310000 0 0x1000>, +- <0 0x10320000 0 0x1000>, ++ <0 0x1032f000 0 0x2000>, + <0 0x10340000 0 0x2000>, + <0 0x10360000 0 0x2000>; + }; diff --git a/target/linux/mediatek/patches-6.12/193-dts-mt7623-thermal_zone_fix.patch b/target/linux/mediatek/patches-6.12/193-dts-mt7623-thermal_zone_fix.patch new file mode 100644 index 0000000000..da9ba5f305 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/193-dts-mt7623-thermal_zone_fix.patch @@ -0,0 +1,48 @@ +From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001 +From: Bruno Umuarama +Date: Thu, 13 Oct 2022 21:18:21 +0000 +Subject: [PATCH] mediatek: mt7623: fix thermal zone +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Raising the temperatures for passive and active trips. @VA1DER +proposed at issue 9396 to remove passive trip. This commit relates to +his suggestion. + +Without this patch. the CPU will be throttled all the way down to 98MHz +if the temperature rises even a degree above the trip point, and it was +further discovered that if the internal temperature of the device is +above the first trip point temperature when it boots then it will start +in a throttled state and even +$ echo disabled > /sys/class/thermal/thermal_zone0/mode +will have no effect. + +The patch increases the passive trip point and active cooling map. The +throttling temperature will then be at 77°C and 82°C, which is still a +low enough temperature for ARM devices to not be in the real danger +zone, and gives some operational headroom. + +Signed-off-by: Bruno Umuarama +--- + arch/arm/boot/dts/mediatek/mt7623.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/mediatek/mt7623.dtsi ++++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi +@@ -160,13 +160,13 @@ + + trips { + cpu_passive: cpu-passive { +- temperature = <57000>; ++ temperature = <77000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_active: cpu-active { +- temperature = <67000>; ++ temperature = <82000>; + hysteresis = <2000>; + type = "active"; + }; diff --git a/target/linux/mediatek/patches-6.12/194-dts-mt7968a-add-ramoops.patch b/target/linux/mediatek/patches-6.12/194-dts-mt7968a-add-ramoops.patch new file mode 100644 index 0000000000..161c1e7516 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/194-dts-mt7968a-add-ramoops.patch @@ -0,0 +1,17 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -68,6 +68,14 @@ + #address-cells = <2>; + #size-cells = <2>; + ranges; ++ ++ /* 64 KiB reserved for ramoops/pstore */ ++ ramoops@42ff0000 { ++ compatible = "ramoops"; ++ reg = <0 0x42ff0000 0 0x10000>; ++ record-size = <0x1000>; ++ }; ++ + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-6.12/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/target/linux/mediatek/patches-6.12/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch new file mode 100644 index 0000000000..8423278033 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch @@ -0,0 +1,196 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +@@ -23,6 +23,10 @@ + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; ++ led-boot = &green_led; ++ led-failsafe = &green_led; ++ led-running = &green_led; ++ led-upgrade = &blue_led; + }; + + chosen { +@@ -418,27 +422,27 @@ + + port@1 { + reg = <1>; +- label = "lan0"; ++ label = "lan1"; + }; + + port@2 { + reg = <2>; +- label = "lan1"; ++ label = "lan2"; + }; + + port@3 { + reg = <3>; +- label = "lan2"; ++ label = "lan3"; + }; + + port@4 { + reg = <4>; +- label = "lan3"; ++ label = "lan4"; + }; + + port5: port@5 { + reg = <5>; +- label = "lan4"; ++ label = "sfp2"; + phy-mode = "2500base-x"; + sfp = <&sfp2>; + managed = "in-band-status"; +@@ -489,9 +493,137 @@ + + &wifi { + status = "okay"; +- pinctrl-names = "default", "dbdc"; ++ pinctrl-names = "default"; + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; +- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; ++ ++ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7 ++ 0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182 ++ 0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2 ++ 0xc2000081 0x82858587 0x87c2c200 0x00818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2 ++ 0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0x000000c3 ++ 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3 ++ 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228 ++ 0x00222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd ++ 0xeeeeeecc 0xccccdddd 0xdddddddd 0x004a5662 0x0000004a 0x56620000 0x004a5662 0x0000004a ++ 0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 ++ 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00000000 0xf0f0cc00 ++ 0x00000000 0x0000aaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb ++ 0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00000000 0x0000aaaa 0xaa000000 0xbbbbbbbb ++ 0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb ++ 0x00000000 0x00000000 0x00000000 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa ++ 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00000000 0x0000eeee 0xeeffffff 0xcccccccc ++ 0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd ++ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 ++ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 ++ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e ++ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 ++ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 ++ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e ++ 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x06000100 0x01050002 0x00ff0300 ++ 0xf900fe03 0x00000000 0x00000000 0x0000009b 0x6e370000 0x00000000 0x00fc0009 0x0a00fe00 ++ 0x060700fe 0x00070800 0x05000b0a 0x00000000 0x00000000 0x000000e2 0x96460000 0x00000000 ++ 0x000400f7 0xf8000300 0xfcfe0003 0x00fbfc00 0xee00e3f2 0x00000000 0x00000000 0x00000011 ++ 0xbb550000 0x00000000 0x000600f6 0xfc000300 0xfbfe0004 0x00fafe00 0xf600ecf2 0x00000000 ++ 0x00000000 0x0000001f 0xbf580000 0x00000000 0x000600f5 0xf6000400 0xf8f90004 0x00f7f800 ++ 0xf700f0f4 0x00000000 0x00000000 0x00000024 0xbe570000 0x00000000 0x000800f8 0xfe000600 ++ 0xf8fd0007 0x00f9fe00 0xf500f0f4 0x00000000 0x00000000 0x0000002d 0xd6610000 0x00000000 ++ 0x000400f7 0xfc000500 0xf7fc0005 0x00f7fc00 0xf900f5f8 0x00000000 0x00000000 0x00000026 ++ 0xd96e0000 0x00000000 0x000400f7 0xf9000600 0xf5f70005 0x00f5f800 0xf900f4f7 0x00000000 ++ 0x00000000 0x0000001b 0xce690000 0x00000000 0x000300f8 0xf8000600 0xf6f60004 0x00f6f700 ++ 0xf900f4f7 0x00000000 0x00000000 0x00000018 0xd8720000 0x00000000 0x00000000 0x02404002 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2 ++ 0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2 ++ 0x3fc140c1 0x41c040c0 0x00000000 0x00000000 0x41c741c7 0xc1c7c1c7 0x00000000 0x00000000 ++ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 ++ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 ++ 0x00a0ce00 0x00000000 0xb6840000 0x00000000 0x00000000 0x00000000 0x18181818 0x18181818 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759 ++ 0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78 ++ 0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848 ++ 0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659 ++ 0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877 ++ 0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849 ++ 0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484 ++ 0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1 ++ 0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000 ++ 0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ++ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; + + led { + led-active-low; +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +@@ -55,6 +55,7 @@ + partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; ++ compatible = "denx,fit"; + }; + }; + }; diff --git a/target/linux/mediatek/patches-6.12/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch b/target/linux/mediatek/patches-6.12/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch new file mode 100644 index 0000000000..f2b9a7093a --- /dev/null +++ b/target/linux/mediatek/patches-6.12/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch @@ -0,0 +1,115 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso +@@ -21,5 +21,24 @@ + non-removable; + no-sd; + no-sdio; ++ #address-cells = <1>; ++ #size-cells = <0>; + status = "okay"; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ partitions { ++ compatible = "gpt-partitions"; ++ ++ emmc_rootdisk: block-partition-production { ++ partname = "production"; ++ }; ++ }; ++ }; ++}; ++ ++&{/chosen} { ++ rootdisk-emmc = <&emmc_rootdisk>; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +@@ -29,25 +29,24 @@ + + partition@0 { + label = "bl2"; +- reg = <0x0 0x100000>; +- read-only; ++ reg = <0x0 0x200000>; + }; + +- partition@100000 { +- label = "reserved"; +- reg = <0x100000 0x280000>; +- }; +- +- partition@380000 { +- label = "fip"; +- reg = <0x380000 0x200000>; +- read-only; +- }; +- +- partition@580000 { ++ partition@200000 { + label = "ubi"; +- reg = <0x580000 0x7a80000>; ++ reg = <0x200000 0x7e00000>; ++ compatible = "linux,ubi"; ++ ++ volumes { ++ nand_rootdisk: ubi-volume-fit { ++ volname = "fit"; ++ }; ++ }; + }; + }; + }; + }; ++ ++&{/chosen} { ++ rootdisk-spim-nand = <&nand_rootdisk>; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +@@ -52,7 +52,7 @@ + reg = <0x180000 0xa80000>; + }; + +- partition@c00000 { ++ nor_rootdisk: partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; + compatible = "denx,fit"; +@@ -60,3 +60,7 @@ + }; + }; + }; ++ ++&{/chosen} { ++ rootdisk-nor = <&nor_rootdisk>; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso +@@ -15,5 +15,24 @@ + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; ++ #address-cells = <1>; ++ #size-cells = <0>; + status = "okay"; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ partitions { ++ compatible = "gpt-partitions"; ++ ++ sd_rootdisk: block-partition-production { ++ partname = "production"; ++ }; ++ }; ++ }; ++}; ++ ++&{/chosen} { ++ rootdisk-sd = <&sd_rootdisk>; + }; diff --git a/target/linux/mediatek/patches-6.12/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-6.12/200-phy-phy-mtk-tphy-Add-hifsys-support.patch new file mode 100644 index 0000000000..b3db243a97 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/200-phy-phy-mtk-tphy-Add-hifsys-support.patch @@ -0,0 +1,66 @@ +From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001 +From: Kristian Evensen +Date: Mon, 30 Apr 2018 14:38:01 +0200 +Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support + +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -18,6 +18,8 @@ + #include + #include + #include ++#include ++#include + + #include "phy-mtk-io.h" + +@@ -271,6 +273,9 @@ + + #define USER_BUF_LEN(count) min_t(size_t, 8, (count)) + ++#define HIF_SYSCFG1 0x14 ++#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20) ++ + enum mtk_phy_version { + MTK_PHY_V1 = 1, + MTK_PHY_V2, +@@ -339,6 +344,7 @@ struct mtk_tphy { + void __iomem *sif_base; /* only shared sif */ + const struct mtk_phy_pdata *pdata; + struct mtk_phy_instance **phys; ++ struct regmap *hif; + int nphys; + int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ + int src_coef; /* coefficient for slew rate calibrate */ +@@ -973,6 +979,10 @@ static void pcie_phy_instance_init(struc + if (tphy->pdata->version != MTK_PHY_V1) + return; + ++ if (tphy->hif) ++ regmap_update_bits(tphy->hif, HIF_SYSCFG1, ++ HIF_SYSCFG1_PHY2_MASK, 0); ++ + mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, + P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, + FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | +@@ -1621,6 +1631,16 @@ static int mtk_tphy_probe(struct platfor + &tphy->src_coef); + } + ++ if (of_find_property(np, "mediatek,phy-switch", NULL)) { ++ tphy->hif = syscon_regmap_lookup_by_phandle(np, ++ "mediatek,phy-switch"); ++ if (IS_ERR(tphy->hif)) { ++ dev_err(&pdev->dev, ++ "missing \"mediatek,phy-switch\" phandle\n"); ++ return PTR_ERR(tphy->hif); ++ } ++ } ++ + port = 0; + for_each_child_of_node_scoped(np, child_np) { + struct mtk_phy_instance *instance; diff --git a/target/linux/mediatek/patches-6.12/255-clk-mediatek-mt7988-infracfg-SPI0-clocks-are-not-critical.patch b/target/linux/mediatek/patches-6.12/255-clk-mediatek-mt7988-infracfg-SPI0-clocks-are-not-critical.patch new file mode 100644 index 0000000000..ed3471933c --- /dev/null +++ b/target/linux/mediatek/patches-6.12/255-clk-mediatek-mt7988-infracfg-SPI0-clocks-are-not-critical.patch @@ -0,0 +1,65 @@ +From patchwork Fri Nov 1 03:19:39 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Daniel Golle +X-Patchwork-Id: 13858671 +Return-Path: + +Date: Fri, 1 Nov 2024 03:19:39 +0000 +From: Daniel Golle +To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, + linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Uwe + =?iso-8859-1?q?Kleine-K=F6nig?= , + Sam Shih , Frank Wunderlich , + Daniel Golle , + AngeloGioacchino Del Regno , + Matthias Brugger , Stephen Boyd , + Michael Turquette +Subject: [PATCH] clk: mediatek: mt7988-infracfg: SPI0 clocks are not critical +Message-ID: +MIME-Version: 1.0 +Content-Disposition: inline +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org + +SPI0 clocks have wrongly been marked as critical while, probably due +to the SPI driver not requesting them. This can (and should) be addressed +in device tree instead. +Remove CLK_IS_CRITICAL flag from clocks related to SPI0. + +Fixes: 4b4719437d85 ("clk: mediatek: add drivers for MT7988 SoC") +Signed-off-by: Daniel Golle +--- + drivers/clk/mediatek/clk-mt7988-infracfg.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c ++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c +@@ -196,12 +196,10 @@ static const struct mtk_gate infra_clks[ + GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), + GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11, + CLK_IS_CRITICAL), +- GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12, +- CLK_IS_CRITICAL), ++ GATE_INFRA2(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12), + GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13), + GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14), +- GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15, +- CLK_IS_CRITICAL), ++ GATE_INFRA2(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15), + GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16), + GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17), + GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18), diff --git a/target/linux/mediatek/patches-6.12/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-6.12/330-snand-mtk-bmt-support.patch new file mode 100644 index 0000000000..270e447a81 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/330-snand-mtk-bmt-support.patch @@ -0,0 +1,34 @@ +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) + { +@@ -1525,6 +1526,7 @@ static int spinand_probe(struct spi_mem + if (ret) + return ret; + ++ mtk_bmt_attach(mtd); + ret = mtd_device_register(mtd, NULL, 0); + if (ret) + goto err_spinand_cleanup; +@@ -1532,6 +1534,7 @@ static int spinand_probe(struct spi_mem + return 0; + + err_spinand_cleanup: ++ mtk_bmt_detach(mtd); + spinand_cleanup(spinand); + + return ret; +@@ -1550,6 +1553,7 @@ static int spinand_remove(struct spi_mem + if (ret) + return ret; + ++ mtk_bmt_detach(mtd); + spinand_cleanup(spinand); + + return 0; diff --git a/target/linux/mediatek/patches-6.12/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-6.12/331-mt7622-rfb1-enable-bmt.patch new file mode 100644 index 0000000000..81136c9a3b --- /dev/null +++ b/target/linux/mediatek/patches-6.12/331-mt7622-rfb1-enable-bmt.patch @@ -0,0 +1,10 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -572,6 +572,7 @@ + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; ++ mediatek,bmt-v2; + + partitions { + compatible = "fixed-partitions"; diff --git a/target/linux/mediatek/patches-6.12/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-6.12/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch new file mode 100644 index 0000000000..ee71d49fe1 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch @@ -0,0 +1,123 @@ +From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001 +From: Davide Fioravanti +Date: Fri, 8 Jan 2021 15:35:24 +0100 +Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA + +Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf + +Signed-off-by: Davide Fioravanti +--- + drivers/mtd/nand/spi/Makefile | 2 +- + drivers/mtd/nand/spi/core.c | 1 + + drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++ + include/linux/mtd/spinand.h | 1 + + 4 files changed, 79 insertions(+), 1 deletion(-) + create mode 100644 drivers/mtd/nand/spi/fidelix.c + +--- a/drivers/mtd/nand/spi/Makefile ++++ b/drivers/mtd/nand/spi/Makefile +@@ -1,4 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 +-spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o foresee.o gigadevice.o ++spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fidelix.o foresee.o gigadevice.o + spinand-objs += macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o + obj-$(CONFIG_MTD_SPI_NAND) += spinand.o +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -1114,6 +1114,7 @@ static const struct spinand_manufacturer + &ato_spinand_manufacturer, + &esmt_c8_spinand_manufacturer, + &etron_spinand_manufacturer, ++ &fidelix_spinand_manufacturer, + &foresee_spinand_manufacturer, + &gigadevice_spinand_manufacturer, + ¯onix_spinand_manufacturer, +--- /dev/null ++++ b/drivers/mtd/nand/spi/fidelix.c +@@ -0,0 +1,76 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2020 Davide Fioravanti ++ */ ++ ++#include ++#include ++#include ++ ++#define SPINAND_MFR_FIDELIX 0xE5 ++#define FIDELIX_ECCSR_MASK 0x0F ++ ++static SPINAND_OP_VARIANTS(read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(write_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(update_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 8; ++ region->length = 8; ++ ++ return 0; ++} ++ ++static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 2; ++ region->length = 6; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = { ++ .ecc = fm35x1ga_ooblayout_ecc, ++ .free = fm35x1ga_ooblayout_free, ++}; ++ ++static const struct spinand_info fidelix_spinand_table[] = { ++ SPINAND_INFO("FM35X1GA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)), ++}; ++ ++static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = { ++}; ++ ++const struct spinand_manufacturer fidelix_spinand_manufacturer = { ++ .id = SPINAND_MFR_FIDELIX, ++ .name = "Fidelix", ++ .chips = fidelix_spinand_table, ++ .nchips = ARRAY_SIZE(fidelix_spinand_table), ++ .ops = &fidelix_spinand_manuf_ops, ++}; +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -264,6 +264,7 @@ extern const struct spinand_manufacturer + extern const struct spinand_manufacturer ato_spinand_manufacturer; + extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; + extern const struct spinand_manufacturer etron_spinand_manufacturer; ++extern const struct spinand_manufacturer fidelix_spinand_manufacturer; + extern const struct spinand_manufacturer foresee_spinand_manufacturer; + extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; + extern const struct spinand_manufacturer macronix_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-6.12/341-mtd-spinand-Support-dosilicon.patch b/target/linux/mediatek/patches-6.12/341-mtd-spinand-Support-dosilicon.patch new file mode 100644 index 0000000000..e803ce07e0 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/341-mtd-spinand-Support-dosilicon.patch @@ -0,0 +1,329 @@ +From cead43cc5781492f2706eeed1157c8986a216bc9 Mon Sep 17 00:00:00 2001 +From: Jon Lin +Date: Sun, 17 Oct 2021 09:51:39 +0800 +Subject: [PATCH] mtd: spinand: Support dosilicon + +DS35X1GA, DS35Q2GA, DS35M1GA, DS35M2GA, DS35Q2GB, DS35M1GB + +Change-Id: I5aeb0219f01dbe98d36b398e66b94ab31b07788e +Signed-off-by: Jon Lin +--- + drivers/mtd/nand/spi/Makefile | 2 +- + drivers/mtd/nand/spi/core.c | 1 + + drivers/mtd/nand/spi/dosilicon.c | 187 +++++++++++++++++++++++++++++++ + include/linux/mtd/spinand.h | 1 + + 4 files changed, 190 insertions(+), 1 deletion(-) + create mode 100644 drivers/mtd/nand/spi/dosilicon.c + +--- a/drivers/mtd/nand/spi/Makefile ++++ b/drivers/mtd/nand/spi/Makefile +@@ -1,4 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 + spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fidelix.o foresee.o gigadevice.o ++spinand-objs += dosilicon.o + spinand-objs += macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o + obj-$(CONFIG_MTD_SPI_NAND) += spinand.o +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -1112,6 +1112,7 @@ static const struct nand_ops spinand_ops + static const struct spinand_manufacturer *spinand_manufacturers[] = { + &alliancememory_spinand_manufacturer, + &ato_spinand_manufacturer, ++ &dosilicon_spinand_manufacturer, + &esmt_c8_spinand_manufacturer, + &etron_spinand_manufacturer, + &fidelix_spinand_manufacturer, +--- /dev/null ++++ b/drivers/mtd/nand/spi/dosilicon.c +@@ -0,0 +1,281 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2020 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++ ++#define SPINAND_MFR_DOSILICON 0xE5 ++ ++#define DOSICON_STATUS_ECC_MASK GENMASK(6, 4) ++#define DOSICON_STATUS_ECC_NO_BITFLIPS (0 << 4) ++#define DOSICON_STATUS_ECC_1TO3_BITFLIPS (1 << 4) ++#define DOSICON_STATUS_ECC_4TO6_BITFLIPS (3 << 4) ++#define DOSICON_STATUS_ECC_7TO8_BITFLIPS (5 << 4) ++ ++static SPINAND_OP_VARIANTS(read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(write_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(update_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static int ds35xxga_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 8; ++ region->length = 8; ++ ++ return 0; ++} ++ ++static int ds35xxga_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 2; ++ region->length = 6; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops ds35xxga_ooblayout = { ++ .ecc = ds35xxga_ooblayout_ecc, ++ .free = ds35xxga_ooblayout_free, ++}; ++ ++static int ds35xxgb_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section) ++ return -ERANGE; ++ ++ region->offset = 64; ++ region->length = 64; ++ ++ return 0; ++} ++ ++static int ds35xxgb_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section) ++ return -ERANGE; ++ ++ /* Reserve 1 bytes for the BBM. */ ++ region->offset = 1; ++ region->length = 63; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops ds35xxgb_ooblayout = { ++ .ecc = ds35xxgb_ooblayout_ecc, ++ .free = ds35xxgb_ooblayout_free, ++}; ++ ++static int ds35xxgb_ecc_get_status(struct spinand_device *spinand, ++ u8 status) ++{ ++ switch (status & DOSICON_STATUS_ECC_MASK) { ++ case STATUS_ECC_NO_BITFLIPS: ++ return 0; ++ ++ case STATUS_ECC_UNCOR_ERROR: ++ return -EBADMSG; ++ ++ case DOSICON_STATUS_ECC_1TO3_BITFLIPS: ++ return 3; ++ ++ case DOSICON_STATUS_ECC_4TO6_BITFLIPS: ++ return 6; ++ ++ case DOSICON_STATUS_ECC_7TO8_BITFLIPS: ++ return 8; ++ ++ default: ++ break; ++ } ++ ++ return -EINVAL; ++} ++ ++static const struct spinand_info dosilicon_spinand_table[] = { ++ SPINAND_INFO("DS35X1GA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxga_ooblayout, NULL)), ++ SPINAND_INFO("DS35Q2GA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x72), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxga_ooblayout, NULL)), ++ SPINAND_INFO("DS35M1GA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x21), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxga_ooblayout, NULL)), ++ SPINAND_INFO("DS35M2GA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxga_ooblayout, NULL)), ++ SPINAND_INFO("DS35Q2GB", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF2), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ++ ds35xxgb_ecc_get_status)), ++ SPINAND_INFO("DS35M1GB", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA1), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ++ ds35xxgb_ecc_get_status)), ++ SPINAND_INFO("DS35Q1GB", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF1), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ++ ds35xxgb_ecc_get_status)), ++ SPINAND_INFO("DS35Q4GM", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF4), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ++ ds35xxgb_ecc_get_status)), ++ SPINAND_INFO("DS35Q12B", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF5), ++ NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ++ ds35xxgb_ecc_get_status)), ++ SPINAND_INFO("DS35M12B", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA5), ++ NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ++ ds35xxgb_ecc_get_status)), ++ SPINAND_INFO("DS35Q1GD-IB", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), ++ SPINAND_INFO("DS35M4GB-IB", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), ++ SPINAND_INFO("DS35Q4GB-IB", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB4), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), ++ SPINAND_INFO("DS35Q12C-IB", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75), ++ NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), ++ SPINAND_INFO("DS35M12C-IB", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25), ++ NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), ++ SPINAND_INFO("DS35Q2GBS", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), ++}; ++ ++static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = { ++}; ++ ++const struct spinand_manufacturer dosilicon_spinand_manufacturer = { ++ .id = SPINAND_MFR_DOSILICON, ++ .name = "dosilicon", ++ .chips = dosilicon_spinand_table, ++ .nchips = ARRAY_SIZE(dosilicon_spinand_table), ++ .ops = &dosilicon_spinand_manuf_ops, ++}; +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -262,6 +262,7 @@ struct spinand_manufacturer { + /* SPI NAND manufacturers */ + extern const struct spinand_manufacturer alliancememory_spinand_manufacturer; + extern const struct spinand_manufacturer ato_spinand_manufacturer; ++extern const struct spinand_manufacturer dosilicon_spinand_manufacturer; + extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; + extern const struct spinand_manufacturer etron_spinand_manufacturer; + extern const struct spinand_manufacturer fidelix_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-6.12/342-mtd-spinand-Support-fmsh.patch b/target/linux/mediatek/patches-6.12/342-mtd-spinand-Support-fmsh.patch new file mode 100644 index 0000000000..655667520b --- /dev/null +++ b/target/linux/mediatek/patches-6.12/342-mtd-spinand-Support-fmsh.patch @@ -0,0 +1,287 @@ +From 205a24e34751220c3ba04f0ac6ecc734e56ed225 Mon Sep 17 00:00:00 2001 +From: Jon Lin +Date: Sun, 17 Oct 2021 09:59:10 +0800 +Subject: [PATCH] mtd: spinand: Support fmsh + +FM25S01A, FM25S02A, FM25S01 + +Change-Id: I7e0ceec39c57dc591d77a4ebde599ad326cf25b7 +Signed-off-by: Jon Lin +--- + drivers/mtd/nand/spi/Makefile | 2 +- + drivers/mtd/nand/spi/core.c | 1 + + drivers/mtd/nand/spi/fmsh.c | 122 ++++++++++++++++++++++++++++++++++ + include/linux/mtd/spinand.h | 1 + + 4 files changed, 125 insertions(+), 1 deletion(-) + create mode 100644 drivers/mtd/nand/spi/fmsh.c + +--- a/drivers/mtd/nand/spi/Makefile ++++ b/drivers/mtd/nand/spi/Makefile +@@ -1,5 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 + spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fidelix.o foresee.o gigadevice.o +-spinand-objs += dosilicon.o ++spinand-objs += dosilicon.o fmsh.o + spinand-objs += macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o + obj-$(CONFIG_MTD_SPI_NAND) += spinand.o +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -1116,6 +1116,7 @@ static const struct spinand_manufacturer + &esmt_c8_spinand_manufacturer, + &etron_spinand_manufacturer, + &fidelix_spinand_manufacturer, ++ &fmsh_spinand_manufacturer, + &foresee_spinand_manufacturer, + &gigadevice_spinand_manufacturer, + ¯onix_spinand_manufacturer, +--- /dev/null ++++ b/drivers/mtd/nand/spi/fmsh.c +@@ -0,0 +1,238 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. ++ * ++ * Authors: ++ * Dingqiang Lin ++ */ ++ ++#include ++#include ++#include ++ ++#define SPINAND_MFR_FMSH 0xA1 ++ ++static SPINAND_OP_VARIANTS(read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(write_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(update_cache_variants, ++ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), ++ SPINAND_PROG_LOAD(false, 0, NULL, 0)); ++ ++static int fm25s01a_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ return -ERANGE; ++} ++ ++static int fm25s01a_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section) ++ return -ERANGE; ++ ++ region->offset = 2; ++ region->length = 62; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops fm25s01a_ooblayout = { ++ .ecc = fm25s01a_ooblayout_ecc, ++ .free = fm25s01a_ooblayout_free, ++}; ++ ++static int fm25s01_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section) ++ return -ERANGE; ++ ++ region->offset = 64; ++ region->length = 64; ++ ++ return 0; ++} ++ ++static int fm25s01_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section) ++ return -ERANGE; ++ ++ region->offset = 2; ++ region->length = 62; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops fm25s01_ooblayout = { ++ .ecc = fm25s01_ooblayout_ecc, ++ .free = fm25s01_ooblayout_free, ++}; ++ ++/* ++ * ecc bits: 0xC0[4,6] ++ * [0b000], No bit errors were detected; ++ * [0b001] and [0b011], 1~6 Bit errors were detected and corrected. Not ++ * reach Flipping Bits; ++ * [0b101], Bit error count equals the bit flip ++ * detection threshold ++ * [0b010], Multiple bit errors were detected and ++ * not corrected. ++ * others, Reserved. ++ */ ++static int fm25s01bi3_ecc_ecc_get_status(struct spinand_device *spinand, ++ u8 status) ++{ ++ struct nand_device *nand = spinand_to_nand(spinand); ++ u8 eccsr = (status & GENMASK(6, 4)) >> 4; ++ ++ if (eccsr <= 1 || eccsr == 3) ++ return eccsr; ++ else if (eccsr == 5) ++ return nanddev_get_ecc_requirements(nand)->strength; ++ else ++ return -EBADMSG; ++} ++ ++static int fm25g0xd_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section) ++ return -ERANGE; ++ ++ region->offset = 64; ++ region->length = 64; ++ ++ return 0; ++} ++ ++static int fm25g0xd_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section) ++ return -ERANGE; ++ ++ /* Reserve 2 bytes for the BBM. */ ++ region->offset = 2; ++ region->length = 62; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops fm25g0xd_ooblayout = { ++ .ecc = fm25g0xd_ooblayout_ecc, ++ .free = fm25g0xd_ooblayout_free, ++}; ++ ++/* ++ * ecc bits: 0xC0[4,6] ++ * [0x0], No bit errors were detected; ++ * [0x001, 0x011], Bit errors were detected and corrected. Not ++ * reach Flipping Bits; ++ * [0x100], Bit error count equals the bit flip ++ * detectionthreshold ++ * [0x101, 0x110], Reserved; ++ * [0x111], Multiple bit errors were detected and ++ * not corrected. ++ */ ++static int fm25g0xd_ecc_get_status(struct spinand_device *spinand, ++ u8 status) ++{ ++ struct nand_device *nand = spinand_to_nand(spinand); ++ u8 eccsr = (status & GENMASK(6, 4)) >> 4; ++ ++ if (eccsr <= 3) ++ return 0; ++ else if (eccsr == 4) ++ return nanddev_get_ecc_requirements(nand)->strength; ++ else ++ return -EBADMSG; ++} ++ ++static const struct spinand_info fmsh_spinand_table[] = { ++ SPINAND_INFO("FM25S01A", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(1, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&fm25s01a_ooblayout, NULL)), ++ SPINAND_INFO("FM25S02A", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE5), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), ++ NAND_ECCREQ(1, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&fm25s01a_ooblayout, NULL)), ++ SPINAND_INFO("FM25S01", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA1), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(1, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&fm25s01_ooblayout, NULL)), ++ SPINAND_INFO("FM25LS01", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA5), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(1, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&fm25s01_ooblayout, NULL)), ++ SPINAND_INFO("FM25S01BI3", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)), ++ SPINAND_INFO("FM25S02BI3-DND-A-G3", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD6), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)), ++ SPINAND_INFO("FM25G02D", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF2), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&fm25g0xd_ooblayout, fm25g0xd_ecc_get_status)), ++}; ++ ++static const struct spinand_manufacturer_ops fmsh_spinand_manuf_ops = { ++}; ++ ++const struct spinand_manufacturer fmsh_spinand_manufacturer = { ++ .id = SPINAND_MFR_FMSH, ++ .name = "FMSH", ++ .chips = fmsh_spinand_table, ++ .nchips = ARRAY_SIZE(fmsh_spinand_table), ++ .ops = &fmsh_spinand_manuf_ops, ++}; +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -266,6 +266,7 @@ extern const struct spinand_manufacturer + extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; + extern const struct spinand_manufacturer etron_spinand_manufacturer; + extern const struct spinand_manufacturer fidelix_spinand_manufacturer; ++extern const struct spinand_manufacturer fmsh_spinand_manufacturer; + extern const struct spinand_manufacturer foresee_spinand_manufacturer; + extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; + extern const struct spinand_manufacturer macronix_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-6.12/343-mtd-spinand-gsto-Add-code.patch b/target/linux/mediatek/patches-6.12/343-mtd-spinand-gsto-Add-code.patch new file mode 100644 index 0000000000..9684d94440 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/343-mtd-spinand-gsto-Add-code.patch @@ -0,0 +1,186 @@ +From 1e5200d59e21c8a8fa63badf415becb2301e78a4 Mon Sep 17 00:00:00 2001 +From: Jon Lin +Date: Thu, 27 Apr 2023 22:00:04 +0800 +Subject: [PATCH] mtd: spinand: gsto: Add code + +GSS01GSAK1, GSS02GSAK1 + +Change-Id: I7ee9048d934694803d6d081cb7d0cdc56f114e79 +Signed-off-by: Jon Lin +--- + drivers/mtd/nand/spi/Makefile | 2 +- + drivers/mtd/nand/spi/core.c | 1 + + drivers/mtd/nand/spi/gsto.c | 90 +++++++++++++++++++++++++++++++++++ + include/linux/mtd/spinand.h | 1 + + 4 files changed, 93 insertions(+), 1 deletion(-) + create mode 100644 drivers/mtd/nand/spi/gsto.c + +--- a/drivers/mtd/nand/spi/Makefile ++++ b/drivers/mtd/nand/spi/Makefile +@@ -1,5 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 + spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fidelix.o foresee.o gigadevice.o +-spinand-objs += dosilicon.o fmsh.o ++spinand-objs += dosilicon.o fmsh.o gsto.o + spinand-objs += macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o + obj-$(CONFIG_MTD_SPI_NAND) += spinand.o +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -1119,6 +1119,7 @@ static const struct spinand_manufacturer + &fmsh_spinand_manufacturer, + &foresee_spinand_manufacturer, + &gigadevice_spinand_manufacturer, ++ &gsto_spinand_manufacturer, + ¯onix_spinand_manufacturer, + µn_spinand_manufacturer, + ¶gon_spinand_manufacturer, +--- /dev/null ++++ b/drivers/mtd/nand/spi/gsto.c +@@ -0,0 +1,137 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2023 Rockchip Electronics Co., Ltd. ++ * ++ * Authors: ++ * Dingqiang Lin ++ */ ++ ++#include ++#include ++#include ++ ++#define SPINAND_MFR_GSTO 0x52 ++ ++static SPINAND_OP_VARIANTS(read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(write_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(update_cache_variants, ++ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), ++ SPINAND_PROG_LOAD(false, 0, NULL, 0)); ++ ++static int gss0xgsak1_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section) ++ return -ERANGE; ++ ++ region->offset = 32; ++ region->length = 32; ++ ++ return 0; ++} ++ ++static int gss0xgsak1_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section) ++ return -ERANGE; ++ ++ region->offset = 2; ++ region->length = 30; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops gss0xgsak1_ooblayout = { ++ .ecc = gss0xgsak1_ooblayout_ecc, ++ .free = gss0xgsak1_ooblayout_free, ++}; ++ ++static int gss0xgsax1_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section) ++ return -ERANGE; ++ ++ region->offset = 64; ++ region->length = 64; ++ ++ return 0; ++} ++ ++static int gss0xgsax1_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section) ++ return -ERANGE; ++ ++ region->offset = 2; ++ region->length = 62; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops gss0xgsax1_ooblayout = { ++ .ecc = gss0xgsax1_ooblayout_ecc, ++ .free = gss0xgsax1_ooblayout_free, ++}; ++ ++static const struct spinand_info gsto_spinand_table[] = { ++ SPINAND_INFO("GSS01GSAK1", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x13), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 10, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&gss0xgsak1_ooblayout, NULL)), ++ SPINAND_INFO("GSS02GSAK1", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x23), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 20, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)), ++ SPINAND_INFO("GSS02GSAX1", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCA, 0x23), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)), ++ SPINAND_INFO("GSS01GSAX1", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCA, 0x13), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)), ++}; ++ ++static const struct spinand_manufacturer_ops gsto_spinand_manuf_ops = { ++}; ++ ++const struct spinand_manufacturer gsto_spinand_manufacturer = { ++ .id = SPINAND_MFR_GSTO, ++ .name = "GSTO", ++ .chips = gsto_spinand_table, ++ .nchips = ARRAY_SIZE(gsto_spinand_table), ++ .ops = &gsto_spinand_manuf_ops, ++}; +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -269,6 +269,7 @@ extern const struct spinand_manufacturer + extern const struct spinand_manufacturer fmsh_spinand_manufacturer; + extern const struct spinand_manufacturer foresee_spinand_manufacturer; + extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; ++extern const struct spinand_manufacturer gsto_spinand_manufacturer; + extern const struct spinand_manufacturer macronix_spinand_manufacturer; + extern const struct spinand_manufacturer micron_spinand_manufacturer; + extern const struct spinand_manufacturer paragon_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-6.12/400-crypto-add-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.12/400-crypto-add-eip97-inside-secure-support.patch new file mode 100644 index 0000000000..5808a93495 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/400-crypto-add-eip97-inside-secure-support.patch @@ -0,0 +1,27 @@ +--- a/drivers/crypto/inside-secure/safexcel.c ++++ b/drivers/crypto/inside-secure/safexcel.c +@@ -608,6 +608,14 @@ static int safexcel_hw_init(struct safex + val |= EIP197_MST_CTRL_TX_MAX_CMD(5); + writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); + } ++ /* ++ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3 ++ */ ++ else { ++ val = 0; ++ val |= EIP97_MST_CTRL_TX_MAX_CMD(4); ++ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); ++ } + + /* Configure wr/rd cache values */ + writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) | +--- a/drivers/crypto/inside-secure/safexcel.h ++++ b/drivers/crypto/inside-secure/safexcel.h +@@ -315,6 +315,7 @@ + #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) + #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) + #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) ++#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4) + #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) + #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) + #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24) diff --git a/target/linux/mediatek/patches-6.12/401-crypto-fix-eip97-cache-incoherent.patch b/target/linux/mediatek/patches-6.12/401-crypto-fix-eip97-cache-incoherent.patch new file mode 100644 index 0000000000..bd22b3699b --- /dev/null +++ b/target/linux/mediatek/patches-6.12/401-crypto-fix-eip97-cache-incoherent.patch @@ -0,0 +1,26 @@ +--- a/drivers/crypto/inside-secure/safexcel.h ++++ b/drivers/crypto/inside-secure/safexcel.h +@@ -743,6 +743,9 @@ struct safexcel_priv_data { + /* Priority we use for advertising our algorithms */ + #define SAFEXCEL_CRA_PRIORITY 300 + ++/* System cache line size */ ++#define SYSTEM_CACHELINE_SIZE 64 ++ + /* SM3 digest result for zero length message */ + #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \ + "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \ +--- a/drivers/crypto/inside-secure/safexcel_hash.c ++++ b/drivers/crypto/inside-secure/safexcel_hash.c +@@ -55,9 +55,9 @@ struct safexcel_ahash_req { + u8 block_sz; /* block size, only set once */ + u8 digest_sz; /* output digest size, only set once */ + __le32 state[SHA3_512_BLOCK_SIZE / +- sizeof(__le32)] __aligned(sizeof(__le32)); ++ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE); + +- u64 len; ++ u64 len __aligned(SYSTEM_CACHELINE_SIZE); + u64 processed; + + u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32)); diff --git a/target/linux/mediatek/patches-6.12/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-6.12/410-bt-mtk-serial-fix.patch new file mode 100644 index 0000000000..3b5f21f9c8 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/410-bt-mtk-serial-fix.patch @@ -0,0 +1,33 @@ +--- a/drivers/tty/serial/8250/8250.h ++++ b/drivers/tty/serial/8250/8250.h +@@ -86,6 +86,7 @@ struct serial8250_config { + * STOP PARITY EPAR SPAR WLEN5 WLEN6 + */ + #define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */ ++#define UART_CAP_NMOD BIT(19) /* UART doesn't do termios */ + + #define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */ + #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */ +--- a/drivers/tty/serial/8250/8250_port.c ++++ b/drivers/tty/serial/8250/8250_port.c +@@ -276,7 +276,7 @@ static const struct serial8250_config ua + .tx_loadsz = 16, + .fcr = UART_FCR_ENABLE_FIFO | + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, +- .flags = UART_CAP_FIFO, ++ .flags = UART_CAP_FIFO | UART_CAP_NMOD, + }, + [PORT_NPCM] = { + .name = "Nuvoton 16550", +@@ -2730,6 +2730,11 @@ serial8250_do_set_termios(struct uart_po + unsigned long flags; + unsigned int baud, quot, frac = 0; + ++ if (up->capabilities & UART_CAP_NMOD) { ++ termios->c_cflag = 0; ++ return; ++ } ++ + if (up->capabilities & UART_CAP_MINI) { + termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR); + if ((termios->c_cflag & CSIZE) == CS5 || diff --git a/target/linux/mediatek/patches-6.12/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch b/target/linux/mediatek/patches-6.12/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch new file mode 100644 index 0000000000..74e9bd9d7a --- /dev/null +++ b/target/linux/mediatek/patches-6.12/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch @@ -0,0 +1,131 @@ +From bfa7cf42e610d820b935b4805aa80484d591cb1f Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 23 Jun 2022 18:29:51 +0800 +Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private + data + +Signed-off-by: SkyLake.Huang +--- + drivers/spi/spi-mt65xx.c | 28 ++++++++++-------------- + include/linux/platform_data/spi-mt65xx.h | 17 -------------- + 2 files changed, 11 insertions(+), 34 deletions(-) + delete mode 100644 include/linux/platform_data/spi-mt65xx.h + +--- a/drivers/spi/spi-mt65xx.c ++++ b/drivers/spi/spi-mt65xx.c +@@ -15,7 +15,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -172,6 +171,8 @@ struct mtk_spi { + struct device *dev; + dma_addr_t tx_dma; + dma_addr_t rx_dma; ++ u32 sample_sel; ++ u32 get_tick_dly; + }; + + static const struct mtk_spi_compatible mtk_common_compat; +@@ -217,15 +218,6 @@ static const struct mtk_spi_compatible m + .no_need_unprepare = true, + }; + +-/* +- * A piece of default chip info unless the platform +- * supplies it. +- */ +-static const struct mtk_chip_config mtk_default_chip_info = { +- .sample_sel = 0, +- .tick_delay = 0, +-}; +- + static const struct of_device_id mtk_spi_of_match[] = { + { .compatible = "mediatek,spi-ipm", + .data = (void *)&mtk_ipm_compat, +@@ -353,7 +345,6 @@ static int mtk_spi_hw_init(struct spi_co + { + u16 cpha, cpol; + u32 reg_val; +- struct mtk_chip_config *chip_config = spi->controller_data; + struct mtk_spi *mdata = spi_controller_get_devdata(host); + + cpha = spi->mode & SPI_CPHA ? 1 : 0; +@@ -403,7 +394,7 @@ static int mtk_spi_hw_init(struct spi_co + else + reg_val &= ~SPI_CMD_CS_POL; + +- if (chip_config->sample_sel) ++ if (mdata->sample_sel) + reg_val |= SPI_CMD_SAMPLE_SEL; + else + reg_val &= ~SPI_CMD_SAMPLE_SEL; +@@ -430,20 +421,20 @@ static int mtk_spi_hw_init(struct spi_co + if (mdata->dev_comp->ipm_design) { + reg_val = readl(mdata->base + SPI_CMD_REG); + reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; +- reg_val |= ((chip_config->tick_delay & 0x7) ++ reg_val |= ((mdata->get_tick_dly & 0x7) + << SPI_CMD_IPM_GET_TICKDLY_OFFSET); + writel(reg_val, mdata->base + SPI_CMD_REG); + } else { + reg_val = readl(mdata->base + SPI_CFG1_REG); + reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; +- reg_val |= ((chip_config->tick_delay & 0x7) ++ reg_val |= ((mdata->get_tick_dly & 0x7) + << SPI_CFG1_GET_TICK_DLY_OFFSET); + writel(reg_val, mdata->base + SPI_CFG1_REG); + } + } else { + reg_val = readl(mdata->base + SPI_CFG1_REG); + reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; +- reg_val |= ((chip_config->tick_delay & 0x3) ++ reg_val |= ((mdata->get_tick_dly & 0x3) + << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); + writel(reg_val, mdata->base + SPI_CFG1_REG); + } +@@ -733,9 +724,6 @@ static int mtk_spi_setup(struct spi_devi + { + struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); + +- if (!spi->controller_data) +- spi->controller_data = (void *)&mtk_default_chip_info; +- + if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0)) + /* CS de-asserted, gpiolib will handle inversion */ + gpiod_direction_output(spi_get_csgpiod(spi, 0), 0); +@@ -1146,6 +1134,11 @@ static int mtk_spi_probe(struct platform + host->use_gpio_descriptors = true; + + mdata = spi_controller_get_devdata(host); ++ ++ /* Set device configs to default first. Calibrate it later. */ ++ mdata->sample_sel = 0; ++ mdata->get_tick_dly = 2; ++ + mdata->dev_comp = device_get_match_data(dev); + + if (mdata->dev_comp->enhance_timing) +--- a/include/linux/platform_data/spi-mt65xx.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-/* +- * MTK SPI bus driver definitions +- * +- * Copyright (c) 2015 MediaTek Inc. +- * Author: Leilk Liu +- */ +- +-#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H +-#define ____LINUX_PLATFORM_DATA_SPI_MTK_H +- +-/* Board specific platform_data */ +-struct mtk_chip_config { +- u32 sample_sel; +- u32 tick_delay; +-}; +-#endif diff --git a/target/linux/mediatek/patches-6.12/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-6.12/432-drivers-spi-Add-support-for-dynamic-calibration.patch new file mode 100644 index 0000000000..9d16a43a28 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/432-drivers-spi-Add-support-for-dynamic-calibration.patch @@ -0,0 +1,236 @@ +From aaff78437f09d4b86da84ce5983fb7c5be0538d2 Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 23 Jun 2022 18:35:52 +0800 +Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration + +Signed-off-by: SkyLake.Huang +--- + drivers/spi/spi.c | 137 ++++++++++++++++++++++++++++++++++++++++ + include/linux/spi/spi.h | 42 ++++++++++++ + 2 files changed, 179 insertions(+) + +--- a/drivers/spi/spi.c ++++ b/drivers/spi/spi.c +@@ -1494,6 +1494,70 @@ static int spi_transfer_wait(struct spi_ + return 0; + } + ++int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi, ++ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv) ++{ ++ int datalen = ctlr->cal_rule->datalen; ++ int addrlen = ctlr->cal_rule->addrlen; ++ u8 *buf; ++ int ret; ++ int i; ++ struct list_head *cal_head, *listptr; ++ struct spi_cal_target *target; ++ ++ /* Calculate calibration result */ ++ int hit_val, total_hit, origin; ++ bool hit; ++ ++ /* Make sure we can start calibration */ ++ if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata) ++ return 0; ++ ++ buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL); ++ if(!buf) ++ return -ENOMEM; ++ ++ ret = ctlr->append_caldata(ctlr); ++ if (ret) ++ goto cal_end; ++ ++ cal_head = ctlr->cal_target; ++ list_for_each(listptr, cal_head) { ++ target = list_entry(listptr, struct spi_cal_target, list); ++ ++ hit = false; ++ hit_val = 0; ++ total_hit = 0; ++ origin = *target->cal_item; ++ ++ for(i=target->cal_min; i<=target->cal_max; i+=target->step) { ++ *target->cal_item = i; ++ ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen); ++ if(ret) ++ break; ++ dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i); ++ if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) { ++ hit = true; ++ hit_val += i; ++ total_hit++; ++ dev_dbg(&spi->dev, "golden data matches data read!\n"); ++ } ++ } ++ if(hit) { ++ *target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit); ++ dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item); ++ } else { ++ *target->cal_item = origin; ++ dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin); ++ } ++ } ++ ++cal_end: ++ kfree(buf); ++ return ret? ret: 0; ++} ++EXPORT_SYMBOL_GPL(spi_do_calibration); ++ + static void _spi_transfer_delay_ns(u32 ns) + { + if (!ns) +@@ -2352,6 +2416,75 @@ void spi_flush_queue(struct spi_controll + /*-------------------------------------------------------------------------*/ + + #if defined(CONFIG_OF) ++static inline void alloc_cal_data(struct list_head **cal_target, ++ struct spi_cal_rule **cal_rule, bool enable) ++{ ++ if(enable) { ++ *cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL); ++ INIT_LIST_HEAD(*cal_target); ++ *cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL); ++ } else { ++ kfree(*cal_target); ++ kfree(*cal_rule); ++ } ++} ++ ++static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi, ++ struct device_node *nc) ++{ ++ u32 value; ++ int rc; ++ const char *cal_mode; ++ ++ rc = of_property_read_bool(nc, "spi-cal-enable"); ++ if (rc) ++ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true); ++ else ++ return 0; ++ ++ rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode); ++ if(!rc) { ++ if(strcmp("read-data", cal_mode) == 0){ ++ ctlr->cal_rule->mode = SPI_CAL_READ_DATA; ++ } else if(strcmp("read-pp", cal_mode) == 0) { ++ ctlr->cal_rule->mode = SPI_CAL_READ_PP; ++ return 0; ++ } else if(strcmp("read-sfdp", cal_mode) == 0){ ++ ctlr->cal_rule->mode = SPI_CAL_READ_SFDP; ++ return 0; ++ } ++ } else ++ goto err; ++ ++ ctlr->cal_rule->datalen = 0; ++ rc = of_property_read_u32(nc, "spi-cal-datalen", &value); ++ if(!rc && value > 0) { ++ ctlr->cal_rule->datalen = value; ++ ++ ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL); ++ rc = of_property_read_u8_array(nc, "spi-cal-data", ++ ctlr->cal_rule->match_data, value); ++ if(rc) ++ kfree(ctlr->cal_rule->match_data); ++ } ++ ++ rc = of_property_read_u32(nc, "spi-cal-addrlen", &value); ++ if(!rc && value > 0) { ++ ctlr->cal_rule->addrlen = value; ++ ++ ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL); ++ rc = of_property_read_u32_array(nc, "spi-cal-addr", ++ ctlr->cal_rule->addr, value); ++ if(rc) ++ kfree(ctlr->cal_rule->addr); ++ } ++ return 0; ++ ++err: ++ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false); ++ return 0; ++} ++ + static void of_spi_parse_dt_cs_delay(struct device_node *nc, + struct spi_delay *delay, const char *prop) + { +@@ -2516,6 +2649,10 @@ of_register_spi_device(struct spi_contro + if (rc) + goto err_out; + ++ rc = of_spi_parse_cal_dt(ctlr, spi, nc); ++ if (rc) ++ goto err_out; ++ + /* Store a pointer to the node in the device structure */ + of_node_get(nc); + +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -348,6 +348,40 @@ struct spi_driver { + struct device_driver driver; + }; + ++enum { ++ SPI_CAL_READ_DATA = 0, ++ SPI_CAL_READ_PP = 1, /* only for SPI-NAND */ ++ SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */ ++}; ++ ++struct nand_addr { ++ unsigned int lun; ++ unsigned int plane; ++ unsigned int eraseblock; ++ unsigned int page; ++ unsigned int dataoffs; ++}; ++ ++/** ++ * Read calibration rule from device dts node. ++ * Once calibration result matches the rule, we regard is as success. ++ */ ++struct spi_cal_rule { ++ int datalen; ++ u8 *match_data; ++ int addrlen; ++ u32 *addr; ++ int mode; ++}; ++ ++struct spi_cal_target { ++ u32 *cal_item; ++ int cal_min; /* min of cal_item */ ++ int cal_max; /* max of cal_item */ ++ int step; /* Increase/decrease cal_item */ ++ struct list_head list; ++}; ++ + #define to_spi_driver(__drv) \ + ( __drv ? container_of_const(__drv, struct spi_driver, driver) : NULL ) + +@@ -754,6 +788,11 @@ struct spi_controller { + void *dummy_rx; + void *dummy_tx; + ++ /* For calibration */ ++ int (*append_caldata)(struct spi_controller *ctlr); ++ struct list_head *cal_target; ++ struct spi_cal_rule *cal_rule; ++ + int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); + + /* +@@ -1657,6 +1696,9 @@ spi_register_board_info(struct spi_board + { return 0; } + #endif + ++extern int spi_do_calibration(struct spi_controller *ctlr, ++ struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv); ++ + /* + * If you're hotplugging an adapter with devices (parport, USB, etc) + * use spi_new_device() to describe each device. You can also call diff --git a/target/linux/mediatek/patches-6.12/433-drivers-spi-mem-Add-spi-calibration-hook.patch b/target/linux/mediatek/patches-6.12/433-drivers-spi-mem-Add-spi-calibration-hook.patch new file mode 100644 index 0000000000..e8377f5c4c --- /dev/null +++ b/target/linux/mediatek/patches-6.12/433-drivers-spi-mem-Add-spi-calibration-hook.patch @@ -0,0 +1,41 @@ +From fa0aaf2a0532053b925f6fbb9c8d0e516370fb68 Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 23 Jun 2022 18:37:55 +0800 +Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook + +Signed-off-by: SkyLake.Huang +--- + drivers/spi/spi-mem.c | 8 ++++++++ + include/linux/spi/spi-mem.h | 4 ++++ + 2 files changed, 12 insertions(+) + +--- a/drivers/spi/spi-mem.c ++++ b/drivers/spi/spi-mem.c +@@ -466,6 +466,14 @@ int spi_mem_exec_op(struct spi_mem *mem, + } + EXPORT_SYMBOL_GPL(spi_mem_exec_op); + ++int spi_mem_do_calibration(struct spi_mem *mem, ++ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), ++ void *priv) ++{ ++ return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv); ++} ++EXPORT_SYMBOL_GPL(spi_mem_do_calibration); ++ + /** + * spi_mem_get_name() - Return the SPI mem device name to be used by the + * upper layer if necessary +--- a/include/linux/spi/spi-mem.h ++++ b/include/linux/spi/spi-mem.h +@@ -372,6 +372,10 @@ bool spi_mem_supports_op(struct spi_mem + int spi_mem_exec_op(struct spi_mem *mem, + const struct spi_mem_op *op); + ++int spi_mem_do_calibration(struct spi_mem *mem, ++ int (*cal_read)(void *, u32 *, int, u8 *, int), ++ void *priv); ++ + const char *spi_mem_get_name(struct spi_mem *mem); + + struct spi_mem_dirmap_desc * diff --git a/target/linux/mediatek/patches-6.12/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch b/target/linux/mediatek/patches-6.12/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch new file mode 100644 index 0000000000..a7815d5ead --- /dev/null +++ b/target/linux/mediatek/patches-6.12/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch @@ -0,0 +1,43 @@ +From 655dfc90d438a8e223317f197b888a92de3df3a1 Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 23 Jun 2022 18:39:03 +0800 +Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration + paramter + +Signed-off-by: SkyLake.Huang +--- + drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/drivers/spi/spi-mt65xx.c ++++ b/drivers/spi/spi-mt65xx.c +@@ -842,6 +842,21 @@ static irqreturn_t mtk_spi_interrupt(int + return IRQ_WAKE_THREAD; + } + ++static int mtk_spi_append_caldata(struct spi_controller *ctlr) ++{ ++ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL); ++ struct mtk_spi *mdata = spi_controller_get_devdata(ctlr); ++ ++ cal_target->cal_item = &mdata->get_tick_dly; ++ cal_target->cal_min = 0; ++ cal_target->cal_max = 7; ++ cal_target->step = 1; ++ ++ list_add(&cal_target->list, ctlr->cal_target); ++ ++ return 0; ++} ++ + static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, + struct spi_mem_op *op) + { +@@ -1132,6 +1147,7 @@ static int mtk_spi_probe(struct platform + host->setup = mtk_spi_setup; + host->set_cs_timing = mtk_spi_set_hw_cs_timing; + host->use_gpio_descriptors = true; ++ host->append_caldata = mtk_spi_append_caldata; + + mdata = spi_controller_get_devdata(host); + diff --git a/target/linux/mediatek/patches-6.12/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch b/target/linux/mediatek/patches-6.12/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch new file mode 100644 index 0000000000..6f58346bfa --- /dev/null +++ b/target/linux/mediatek/patches-6.12/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch @@ -0,0 +1,81 @@ +From eef758fee8d25f56086eaaf7df1edb19929ced1a Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 23 Jun 2022 18:39:56 +0800 +Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for + spinand + +Signed-off-by: SkyLake.Huang +--- + drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 54 insertions(+) + +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -1155,6 +1155,56 @@ static int spinand_manufacturer_match(st + return -EOPNOTSUPP; + } + ++static int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) { ++ struct spinand_device *spinand = (struct spinand_device *)priv; ++ struct device *dev = &spinand->spimem->spi->dev; ++ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen); ++ struct nand_pos pos; ++ struct nand_page_io_req req; ++ u8 status; ++ int ret; ++ ++ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) { ++ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n"); ++ return -EINVAL; ++ } ++ ++ ret = spinand_reset_op(spinand); ++ if (ret) ++ return ret; ++ ++ /* We should store our golden data in first target because ++ * we can't switch target at this moment. ++ */ ++ pos = (struct nand_pos){ ++ .target = 0, ++ .lun = *addr, ++ .plane = *(addr+1), ++ .eraseblock = *(addr+2), ++ .page = *(addr+3), ++ }; ++ ++ req = (struct nand_page_io_req){ ++ .pos = pos, ++ .dataoffs = *(addr+4), ++ .datalen = readlen, ++ .databuf.in = buf, ++ .mode = MTD_OPS_AUTO_OOB, ++ }; ++ ++ ret = spinand_load_page_op(spinand, &req); ++ if (ret) ++ return ret; ++ ++ ret = spinand_wait(spinand, &status); ++ if (ret < 0) ++ return ret; ++ ++ ret = spi_mem_exec_op(spinand->spimem, &op); ++ ++ return 0; ++} ++ + static int spinand_id_detect(struct spinand_device *spinand) + { + u8 *id = spinand->id.data; +@@ -1406,6 +1456,10 @@ static int spinand_init(struct spinand_d + if (!spinand->scratchbuf) + return -ENOMEM; + ++ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand); ++ if (ret) ++ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret); ++ + ret = spinand_detect(spinand); + if (ret) + goto err_free_bufs; diff --git a/target/linux/mediatek/patches-6.12/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch b/target/linux/mediatek/patches-6.12/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch new file mode 100644 index 0000000000..39a4d3759d --- /dev/null +++ b/target/linux/mediatek/patches-6.12/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch @@ -0,0 +1,57 @@ +From 7ec7de94c87654e6cc3f8f604b2f65c003f3e5dc Mon Sep 17 00:00:00 2001 +From: "SkyLake.Huang" +Date: Thu, 23 Jun 2022 18:40:59 +0800 +Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for + spi-nor + +Signed-off-by: SkyLake.Huang +--- + drivers/mtd/nand/spi/core.c | 5 ++++- + drivers/mtd/spi-nor/core.c | 15 +++++++++++++++ + 2 files changed, 19 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -1196,7 +1196,10 @@ static int spinand_cal_read(void *priv, + if (ret) + return ret; + +- ret = spinand_wait(spinand, &status); ++ ret = spinand_wait(spinand, ++ SPINAND_READ_INITIAL_DELAY_US, ++ SPINAND_READ_POLL_DELAY_US, ++ &status); + if (ret < 0) + return ret; + +--- a/drivers/mtd/spi-nor/core.c ++++ b/drivers/mtd/spi-nor/core.c +@@ -3300,6 +3300,18 @@ static const struct flash_info *spi_nor_ + return NULL; + } + ++static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) ++{ ++ struct spi_nor *nor = (struct spi_nor *)priv; ++ ++ nor->reg_proto = SNOR_PROTO_1_1_1; ++ nor->read_proto = SNOR_PROTO_1_1_1; ++ nor->read_opcode = SPINOR_OP_READ; ++ nor->read_dummy = 0; ++ ++ return nor->controller_ops->read(nor, *addr, readlen, buf); ++} ++ + static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, + const char *name) + { +@@ -3474,6 +3486,9 @@ int spi_nor_scan(struct spi_nor *nor, co + if (ret) + return ret; + ++ if(nor->spimem) ++ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor); ++ + info = spi_nor_get_flash_info(nor, name); + if (IS_ERR(info)) + return PTR_ERR(info); diff --git a/target/linux/mediatek/patches-6.12/450-nvmem-add-layout-for-Adtran-devices.patch b/target/linux/mediatek/patches-6.12/450-nvmem-add-layout-for-Adtran-devices.patch new file mode 100644 index 0000000000..e1852e5cd6 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/450-nvmem-add-layout-for-Adtran-devices.patch @@ -0,0 +1,192 @@ +From c22bc82183c2dea64919f975473ec518738baa3e Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 12 Jul 2023 13:38:35 +0100 +Subject: [PATCH] nvmem: add layout for Adtran devices + +Adtran stores unique factory data on GPT partitions on the eMMC. +Using blk-nvmem the 'mfginfo' partition gets exposes as NVMEM provider. + +Add layout driver to parse mfginfo, mainly to provide MAC addresses to +Ethernet and wireless interfaces. + +Variable names are converted to lower-case and '_' is replaced with '-' +in order to comply with the device tree node naming convention. +The main MAC address always ends on a 0 and up to 16 addresses are +alocated for each device to use for various interfaces. + +Implement post-processing function for 'MFG_MAC' variable ('mfg-mac' +node name in device tree) adding the nvmem cell index to the least +significant digit of the MAC address. + +Signed-off-by: Daniel Golle +--- + drivers/nvmem/layouts/Kconfig | 9 +++ + drivers/nvmem/layouts/Makefile | 1 + + drivers/nvmem/layouts/adtran.c | 135 +++++++++++++++++++++++++++++++++ + 3 files changed, 145 insertions(+) + create mode 100644 drivers/nvmem/layouts/adtran.c + +--- a/drivers/nvmem/layouts/Kconfig ++++ b/drivers/nvmem/layouts/Kconfig +@@ -8,6 +8,15 @@ if NVMEM_LAYOUTS + + menu "Layout Types" + ++config NVMEM_LAYOUT_ADTRAN ++ tristate "Adtran mfginfo layout support" ++ select GENERIC_NET_UTILS ++ help ++ Say Y here if you want to support the layout used by Adtran for ++ mfginfo. ++ ++ If unsure, say N. ++ + config NVMEM_LAYOUT_SL28_VPD + tristate "Kontron sl28 VPD layout support" + select CRC8 +--- a/drivers/nvmem/layouts/Makefile ++++ b/drivers/nvmem/layouts/Makefile +@@ -6,4 +6,5 @@ + obj-$(CONFIG_NVMEM_LAYOUT_SL28_VPD) += sl28vpd.o + obj-$(CONFIG_NVMEM_LAYOUT_ONIE_TLV) += onie-tlv.o + obj-$(CONFIG_NVMEM_LAYOUT_U_BOOT_ENV) += u-boot-env.o ++obj-$(CONFIG_NVMEM_LAYOUT_ADTRAN) += adtran.o + obj-$(CONFIG_NVMEM_LAYOUT_ASCII_ENV) += ascii-env.o +--- /dev/null ++++ b/drivers/nvmem/layouts/adtran.c +@@ -0,0 +1,135 @@ ++// SPDX-License-Identifier: GPL-2.0 ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * Adtran devices usually come with a main MAC address ending on 0 and ++ * hence may have up to 16 MAC addresses per device. ++ * The main MAC address is stored as variable MFG_MAC in ASCII format. ++ */ ++static int adtran_mac_address_pp(void *priv, const char *id, int index, ++ unsigned int offset, void *buf, ++ size_t bytes) ++{ ++ u8 mac[ETH_ALEN]; ++ ++ if (WARN_ON(bytes != 3 * ETH_ALEN - 1)) ++ return -EINVAL; ++ ++ if (!mac_pton(buf, mac)) ++ return -EINVAL; ++ ++ if (index) ++ eth_addr_add(mac, index); ++ ++ ether_addr_copy(buf, mac); ++ ++ return 0; ++} ++ ++static int adtran_add_cells(struct nvmem_layout *layout) ++{ ++ struct nvmem_device *nvmem = layout->nvmem; ++ struct nvmem_cell_info info; ++ struct device_node *layout_np; ++ char mfginfo[1024], *c, *t, *p; ++ int ret = -EINVAL; ++ ++ ret = nvmem_device_read(nvmem, 0, sizeof(mfginfo), mfginfo); ++ if (ret < 0) ++ return ret; ++ else if (ret != sizeof(mfginfo)) ++ return -EIO; ++ ++ layout_np = of_nvmem_layout_get_container(nvmem); ++ if (!layout_np) ++ return -ENOENT; ++ ++ c = mfginfo; ++ while (*c != 0xff) { ++ memset(&info, 0, sizeof(info)); ++ if (*c == '#') ++ goto nextline; ++ ++ t = strchr(c, '='); ++ if (!t) ++ goto nextline; ++ ++ *t = '\0'; ++ ++t; ++ info.offset = t - mfginfo; ++ /* process variable name: convert to lower-case, '_' -> '-' */ ++ p = c; ++ do { ++ *p = tolower(*p); ++ if (*p == '_') ++ *p = '-'; ++ } while (*++p); ++ info.name = c; ++ c = strchr(t, 0xa); /* find newline */ ++ if (!c) ++ break; ++ ++ info.bytes = c - t; ++ if (!strcmp(info.name, "mfg-mac")) { ++ info.raw_len = info.bytes; ++ info.bytes = ETH_ALEN; ++ info.read_post_process = adtran_mac_address_pp; ++ } ++ ++ info.np = of_get_child_by_name(layout_np, info.name); ++ ret = nvmem_add_one_cell(nvmem, &info); ++ if (ret) ++ break; ++ ++ ++c; ++ continue; ++ ++nextline: ++ c = strchr(c, 0xa); /* find newline */ ++ if (!c) ++ break; ++ ++c; ++ } ++ ++ of_node_put(layout_np); ++ ++ return ret; ++} ++ ++static int adtran_probe(struct nvmem_layout *layout) ++{ ++ layout->add_cells = adtran_add_cells; ++ ++ return nvmem_layout_register(layout); ++} ++ ++static void adtran_remove(struct nvmem_layout *layout) ++{ ++ nvmem_layout_unregister(layout); ++} ++ ++static const struct of_device_id adtran_of_match_table[] = { ++ { .compatible = "adtran,mfginfo" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, adtran_of_match_table); ++ ++static struct nvmem_layout_driver adtran_layout = { ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "adtran-layout", ++ .of_match_table = adtran_of_match_table, ++ }, ++ .probe = adtran_probe, ++ .remove = adtran_remove, ++}; ++module_nvmem_layout_driver(adtran_layout); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Daniel Golle "); ++MODULE_DESCRIPTION("NVMEM layout driver for Adtran mfginfo"); diff --git a/target/linux/mediatek/patches-6.12/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-6.12/500-gsw-rtl8367s-mt7622-support.patch new file mode 100644 index 0000000000..72a1464966 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/500-gsw-rtl8367s-mt7622-support.patch @@ -0,0 +1,25 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -431,6 +431,12 @@ config ROCKCHIP_PHY + help + Currently supports the integrated Ethernet PHY. + ++config RTL8367S_GSW ++ tristate "rtl8367 Gigabit Switch support for mt7622" ++ depends on NET_VENDOR_MEDIATEK ++ help ++ This driver supports rtl8367s in mt7622 ++ + config SMSC_PHY + tristate "SMSC PHYs" + select CRC16 +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -113,6 +113,7 @@ obj-$(CONFIG_REALTEK_PHY) += realtek/ + obj-y += rtl8261n/ + obj-$(CONFIG_RENESAS_PHY) += uPD60620.o + obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o ++obj-$(CONFIG_RTL8367S_GSW) += rtk/ + obj-$(CONFIG_SMSC_PHY) += smsc.o + obj-$(CONFIG_STE10XP) += ste10Xp.o + obj-$(CONFIG_TERANETICS_PHY) += teranetics.o diff --git a/target/linux/mediatek/patches-6.12/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-6.12/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch new file mode 100644 index 0000000000..1b18679fb3 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch @@ -0,0 +1,34 @@ +From: qizhong cheng +Date: Mon, 27 Dec 2021 21:31:10 +0800 +Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to + stabilize +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Described in PCIe CEM specification sections 2.2 (PERST# Signal) and +2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should +be delayed 100ms (TPVPERL) for the power and clock to become stable. + +Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com +Signed-off-by: qizhong cheng +Signed-off-by: Lorenzo Pieralisi +Acked-by: Pali Rohár +--- + +--- a/drivers/pci/controller/pcie-mediatek.c ++++ b/drivers/pci/controller/pcie-mediatek.c +@@ -700,6 +700,13 @@ static int mtk_pcie_startup_port_v2(stru + */ + msleep(100); + ++ /* ++ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and ++ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should ++ * be delayed 100ms (TPVPERL) for the power and clock to become stable. ++ */ ++ msleep(100); ++ + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ + val = readl(port->base + PCIE_RST_CTRL); + val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | diff --git a/target/linux/mediatek/patches-6.12/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/target/linux/mediatek/patches-6.12/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch new file mode 100644 index 0000000000..d58082aa6f --- /dev/null +++ b/target/linux/mediatek/patches-6.12/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch @@ -0,0 +1,28 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -844,6 +844,12 @@ + #address-cells = <0>; + #interrupt-cells = <1>; + }; ++ ++ slot0: pcie@0,0 { ++ reg = <0x0000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ }; + }; + + pcie1: pcie@1a145000 { +@@ -882,6 +888,12 @@ + #address-cells = <0>; + #interrupt-cells = <1>; + }; ++ ++ slot1: pcie@1,0 { ++ reg = <0x0800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ }; + }; + + sata: sata@1a200000 { diff --git a/target/linux/mediatek/patches-6.12/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-6.12/610-pcie-mediatek-fix-clearing-interrupt-status.patch new file mode 100644 index 0000000000..accc6a6f16 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/610-pcie-mediatek-fix-clearing-interrupt-status.patch @@ -0,0 +1,23 @@ +From: Felix Fietkau +Date: Fri, 4 Sep 2020 18:33:27 +0200 +Subject: [PATCH] pcie-mediatek: fix clearing interrupt status + +Clearing the status needs to happen after running the handler, otherwise +we will get an extra spurious interrupt after the cause has been cleared + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/pci/controller/pcie-mediatek.c ++++ b/drivers/pci/controller/pcie-mediatek.c +@@ -599,9 +599,9 @@ static void mtk_pcie_intr_handler(struct + if (status & INTX_MASK) { + for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { + /* Clear the INTx */ +- writel(1 << bit, port->base + PCIE_INT_STATUS); + generic_handle_domain_irq(port->irq_domain, + bit - INTX_SHIFT); ++ writel(1 << bit, port->base + PCIE_INT_STATUS); + } + } + diff --git a/target/linux/mediatek/patches-6.12/611-pcie-mediatek-gen3-PERST-for-100ms.patch b/target/linux/mediatek/patches-6.12/611-pcie-mediatek-gen3-PERST-for-100ms.patch new file mode 100644 index 0000000000..72437320a0 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/611-pcie-mediatek-gen3-PERST-for-100ms.patch @@ -0,0 +1,17 @@ +--- a/drivers/pci/controller/pcie-mediatek-gen3.c ++++ b/drivers/pci/controller/pcie-mediatek-gen3.c +@@ -416,7 +416,13 @@ static int mtk_pcie_startup_port(struct + msleep(100); + + /* De-assert reset signals */ +- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); ++ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB); ++ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); ++ ++ msleep(100); ++ ++ /* De-assert PERST# signals */ ++ val &= ~(PCIE_PE_RSTB); + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + + /* Check if the link is up or not */ diff --git a/target/linux/mediatek/patches-6.12/700-net-phy-mediatek-Add-2.5Gphy-firmware-dt-bindings-an.patch b/target/linux/mediatek/patches-6.12/700-net-phy-mediatek-Add-2.5Gphy-firmware-dt-bindings-an.patch new file mode 100644 index 0000000000..8c0ded2b37 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/700-net-phy-mediatek-Add-2.5Gphy-firmware-dt-bindings-an.patch @@ -0,0 +1,71 @@ +From 955a80b20fad77dd73ec17ab64d7eb8014cb59c7 Mon Sep 17 00:00:00 2001 +From: Sky Huang +Date: Wed, 19 Feb 2025 16:39:08 +0800 +Subject: [PATCH 19/20] net: phy: mediatek: Add 2.5Gphy firmware dt-bindings + and dts node + +Add 2.5Gphy firmware dt-bindings and dts node since mtk-2p5ge +driver requires firmware to run. Also, update MAINTAINERS for +MediaTek's built-in 2.5Gphy dt-bindings and change MAINTAINER's name. + +Signed-off-by: Sky Huang +--- + .../bindings/net/mediatek,2p5gphy-fw.yaml | 37 +++++++++++++++++++ + MAINTAINERS | 3 +- + 2 files changed, 39 insertions(+), 1 deletion(-) + create mode 100644 Documentation/devicetree/bindings/net/mediatek,2p5gphy-fw.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/mediatek,2p5gphy-fw.yaml +@@ -0,0 +1,37 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/mediatek,2p5gphy-fw.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: MediaTek Built-in 2.5G Ethernet PHY ++ ++maintainers: ++ - Sky Huang ++ ++description: | ++ MediaTek Built-in 2.5G Ethernet PHY needs to load firmware so it can ++ run correctly. ++ ++properties: ++ compatible: ++ const: "mediatek,2p5gphy-fw" ++ ++ reg: ++ items: ++ - description: pmb firmware load address ++ - description: firmware trigger register ++ ++required: ++ - compatible ++ - reg ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phyfw: phy-firmware@f000000 { ++ compatible = "mediatek,2p5gphy-fw"; ++ reg = <0 0x0f100000 0 0x20000>, ++ <0 0x0f0f0018 0 0x20>; ++ }; +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -14426,9 +14426,10 @@ F: include/linux/pcs/pcs-mtk-usxgmii.h + MEDIATEK ETHERNET PHY DRIVERS + M: Daniel Golle + M: Qingfang Deng +-M: SkyLake Huang ++M: Sky Huang + L: netdev@vger.kernel.org + S: Maintained ++F: Documentation/devicetree/bindings/net/mediatek,2p5gphy-fw.yaml + F: drivers/net/phy/mediatek/mtk-ge-soc.c + F: drivers/net/phy/mediatek/mtk-phy-lib.c + F: drivers/net/phy/mediatek/mtk-ge.c diff --git a/target/linux/mediatek/patches-6.12/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch b/target/linux/mediatek/patches-6.12/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch new file mode 100644 index 0000000000..0bb8ba00a3 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch @@ -0,0 +1,399 @@ +From 4eb44972db02c2b704f0ef5c891f29f25440a063 Mon Sep 17 00:00:00 2001 +From: Sky Huang +Date: Wed, 19 Feb 2025 16:39:10 +0800 +Subject: [PATCH 20/20] net: phy: mediatek: add driver for built-in 2.5G + ethernet PHY on MT7988 + +Add support for internal 2.5Gphy on MT7988. This driver will load +necessary firmware and add appropriate time delay to make sure +that firmware works stably. Also, certain control registers will +be set to fix link-up issues. + +Signed-off-by: Sky Huang +--- + MAINTAINERS | 1 + + drivers/net/phy/mediatek/Kconfig | 11 + + drivers/net/phy/mediatek/Makefile | 1 + + drivers/net/phy/mediatek/mtk-2p5ge.c | 342 +++++++++++++++++++++++++++ + 4 files changed, 355 insertions(+) + create mode 100644 drivers/net/phy/mediatek/mtk-2p5ge.c + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -14430,6 +14430,7 @@ M: Sky Huang ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mtk.h" ++ ++#define MTK_2P5GPHY_ID_MT7988 (0x00339c11) ++ ++#define MT7988_2P5GE_PMB_FW "mediatek/mt7988/i2p5ge-phy-pmb.bin" ++#define MT7988_2P5GE_PMB_FW_SIZE (0x20000) ++#define MD32_EN_CFG (0x18) ++#define MD32_EN BIT(0) ++ ++#define BASE100T_STATUS_EXTEND (0x10) ++#define BASE1000T_STATUS_EXTEND (0x11) ++#define EXTEND_CTRL_AND_STATUS (0x16) ++ ++#define PHY_AUX_CTRL_STATUS (0x1d) ++#define PHY_AUX_DPX_MASK GENMASK(5, 5) ++#define PHY_AUX_SPEED_MASK GENMASK(4, 2) ++ ++/* Registers on MDIO_MMD_VEND1 */ ++#define MTK_PHY_LPI_PCS_DSP_CTRL (0x121) ++#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8) ++ ++#define MTK_PHY_HOST_CMD1 0x800e ++#define MTK_PHY_HOST_CMD2 0x800f ++/* Registers on Token Ring debug nodes */ ++/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */ ++#define AUTO_NP_10XEN BIT(6) ++ ++struct mtk_i2p5ge_phy_priv { ++ bool fw_loaded; ++}; ++ ++enum { ++ PHY_AUX_SPD_10 = 0, ++ PHY_AUX_SPD_100, ++ PHY_AUX_SPD_1000, ++ PHY_AUX_SPD_2500, ++}; ++ ++static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev) ++{ ++ struct mtk_i2p5ge_phy_priv *priv = phydev->priv; ++ void __iomem *mcu_csr_base, *pmb_addr; ++ struct device *dev = &phydev->mdio.dev; ++ const struct firmware *fw; ++ struct device_node *np; ++ int ret, i; ++ u32 reg; ++ ++ np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); ++ if (!np) ++ return -ENOENT; ++ ++ pmb_addr = of_iomap(np, 0); ++ if (!pmb_addr) ++ return -ENOMEM; ++ mcu_csr_base = of_iomap(np, 1); ++ if (!mcu_csr_base) { ++ ret = -ENOMEM; ++ goto free_pmb; ++ } ++ ++ ret = request_firmware(&fw, MT7988_2P5GE_PMB_FW, dev); ++ if (ret) { ++ dev_err(dev, "failed to load firmware: %s, ret: %d\n", ++ MT7988_2P5GE_PMB_FW, ret); ++ goto free; ++ } ++ ++ if (fw->size != MT7988_2P5GE_PMB_FW_SIZE) { ++ dev_err(dev, "Firmware size 0x%zx != 0x%x\n", ++ fw->size, MT7988_2P5GE_PMB_FW_SIZE); ++ ret = -EINVAL; ++ goto release_fw; ++ } ++ ++ reg = readw(mcu_csr_base + MD32_EN_CFG); ++ if (reg & MD32_EN) { ++ phy_set_bits(phydev, MII_BMCR, BMCR_RESET); ++ usleep_range(10000, 11000); ++ } ++ phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); ++ ++ /* Write magic number to safely stall MCU */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD1, 0x1100); ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD2, 0x00df); ++ ++ for (i = 0; i < MT7988_2P5GE_PMB_FW_SIZE - 1; i += 4) ++ writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); ++ ++ if (!priv->fw_loaded) ++ dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n", ++ be16_to_cpu(*((__be16 *)(fw->data + ++ MT7988_2P5GE_PMB_FW_SIZE - 8))), ++ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 6), ++ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 5), ++ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 2), ++ *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 1)); ++ ++ writew(reg & ~MD32_EN, mcu_csr_base + MD32_EN_CFG); ++ writew(reg | MD32_EN, mcu_csr_base + MD32_EN_CFG); ++ phy_set_bits(phydev, MII_BMCR, BMCR_RESET); ++ /* We need a delay here to stabilize initialization of MCU */ ++ usleep_range(7000, 8000); ++ ++ priv->fw_loaded = true; ++ ++release_fw: ++ release_firmware(fw); ++free: ++ iounmap(mcu_csr_base); ++free_pmb: ++ iounmap(pmb_addr); ++ ++ return ret; ++} ++ ++static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) ++{ ++ struct pinctrl *pinctrl; ++ int ret; ++ ++ /* Check if PHY interface type is compatible */ ++ if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL) ++ return -ENODEV; ++ ++ ret = mt798x_2p5ge_phy_load_fw(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* Setup LED */ ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, ++ MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 | ++ MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 | ++ MTK_PHY_LED_ON_LINK2500); ++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, ++ MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX); ++ ++ /* Switch pinctrl after setting polarity to avoid bogus blinking */ ++ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led"); ++ if (IS_ERR(pinctrl) && PTR_ERR(pinctrl) != -ENODEV) ++ dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n"); ++ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL, ++ MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0); ++ ++ /* Enable 16-bit next page exchange bit if 1000-BT isn't advertising */ ++ mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, AUTO_NP_10XEN, ++ FIELD_PREP(AUTO_NP_10XEN, 0x1)); ++ ++ /* Enable HW auto downshift */ ++ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1, ++ MTK_PHY_AUX_CTRL_AND_STATUS, ++ 0, MTK_PHY_ENABLE_DOWNSHIFT); ++ ++ return 0; ++} ++ ++static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev) ++{ ++ bool changed = false; ++ u32 adv; ++ int ret; ++ ++ ret = genphy_c45_an_config_aneg(phydev); ++ if (ret < 0) ++ return ret; ++ if (ret > 0) ++ changed = true; ++ ++ /* Clause 45 doesn't define 1000BaseT support. Use Clause 22 instead in ++ * our design. ++ */ ++ adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); ++ ret = phy_modify_changed(phydev, MII_CTRL1000, ADVERTISE_1000FULL, adv); ++ if (ret < 0) ++ return ret; ++ if (ret > 0) ++ changed = true; ++ ++ return __genphy_config_aneg(phydev, changed); ++} ++ ++static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = genphy_c45_pma_read_abilities(phydev); ++ if (ret) ++ return ret; ++ ++ /* This phy can't handle collision, and neither can (XFI)MAC it's ++ * connected to. Although it can do HDX handshake, it doesn't support ++ * CSMA/CD that HDX requires. ++ */ ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, ++ phydev->supported); ++ ++ return 0; ++} ++ ++static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) ++{ ++ int ret; ++ ++ /* When MDIO_STAT1_LSTATUS is raised genphy_c45_read_link(), this phy ++ * actually hasn't finished AN. So use CL22's link update function ++ * instead. ++ */ ++ ret = genphy_update_link(phydev); ++ if (ret) ++ return ret; ++ ++ phydev->speed = SPEED_UNKNOWN; ++ phydev->duplex = DUPLEX_UNKNOWN; ++ phydev->pause = 0; ++ phydev->asym_pause = 0; ++ ++ /* We'll read link speed through vendor specific registers down below. ++ * So remove phy_resolve_aneg_linkmode (AN on) & genphy_c45_read_pma ++ * (AN off). ++ */ ++ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { ++ ret = genphy_c45_read_lpa(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* Clause 45 doesn't define 1000BaseT support. Read the link ++ * partner's 1G advertisement via Clause 22. ++ */ ++ ret = phy_read(phydev, MII_STAT1000); ++ if (ret < 0) ++ return ret; ++ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); ++ } else if (phydev->autoneg == AUTONEG_DISABLE) { ++ linkmode_zero(phydev->lp_advertising); ++ } ++ ++ if (phydev->link) { ++ ret = phy_read(phydev, PHY_AUX_CTRL_STATUS); ++ if (ret < 0) ++ return ret; ++ ++ switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) { ++ case PHY_AUX_SPD_10: ++ phydev->speed = SPEED_10; ++ break; ++ case PHY_AUX_SPD_100: ++ phydev->speed = SPEED_100; ++ break; ++ case PHY_AUX_SPD_1000: ++ phydev->speed = SPEED_1000; ++ break; ++ case PHY_AUX_SPD_2500: ++ phydev->speed = SPEED_2500; ++ break; ++ } ++ ++ phydev->duplex = DUPLEX_FULL; ++ /* FIXME: ++ * The current firmware always enables rate adaptation mode. ++ */ ++ phydev->rate_matching = RATE_MATCH_PAUSE; ++ } ++ ++ return 0; ++} ++ ++static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device *phydev, ++ phy_interface_t iface) ++{ ++ return RATE_MATCH_PAUSE; ++} ++ ++static int mt798x_2p5ge_phy_probe(struct phy_device *phydev) ++{ ++ struct mtk_i2p5ge_phy_priv *priv; ++ ++ priv = devm_kzalloc(&phydev->mdio.dev, ++ sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ switch (phydev->drv->phy_id) { ++ case MTK_2P5GPHY_ID_MT7988: ++ /* The original hardware only sets MDIO_DEVS_PMAPMD */ ++ phydev->c45_ids.mmds_present |= MDIO_DEVS_PCS | ++ MDIO_DEVS_AN | ++ MDIO_DEVS_VEND1 | ++ MDIO_DEVS_VEND2; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ priv->fw_loaded = false; ++ phydev->priv = priv; ++ ++ return 0; ++} ++ ++static struct phy_driver mtk_2p5gephy_driver[] = { ++ { ++ PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7988), ++ .name = "MediaTek MT7988 2.5GbE PHY", ++ .probe = mt798x_2p5ge_phy_probe, ++ .config_init = mt798x_2p5ge_phy_config_init, ++ .config_aneg = mt798x_2p5ge_phy_config_aneg, ++ .get_features = mt798x_2p5ge_phy_get_features, ++ .read_status = mt798x_2p5ge_phy_read_status, ++ .get_rate_matching = mt798x_2p5ge_phy_get_rate_matching, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_page = mtk_phy_read_page, ++ .write_page = mtk_phy_write_page, ++ }, ++}; ++ ++module_phy_driver(mtk_2p5gephy_driver); ++ ++static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = { ++ { PHY_ID_MATCH_VENDOR(0x00339c00) }, ++ { } ++}; ++ ++MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver"); ++MODULE_AUTHOR("SkyLake Huang "); ++MODULE_LICENSE("GPL"); ++ ++MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl); ++MODULE_FIRMWARE(MT7988_2P5GE_PMB_FW); diff --git a/target/linux/mediatek/patches-6.12/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-6.12/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch new file mode 100644 index 0000000000..d85e505d45 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch @@ -0,0 +1,91 @@ +From: Felix Fietkau +Date: Fri, 4 Sep 2020 18:42:42 +0200 +Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA + +It improves performance by eliminating the need for a cache flush for DMA on +attached devices + +Signed-off-by: Felix Fietkau +--- + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -832,6 +832,9 @@ + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; + status = "disabled"; ++ dma-coherent; ++ mediatek,hifsys = <&hifsys>; ++ mediatek,cci-control = <&cci_control2>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; +@@ -876,6 +879,9 @@ + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; + status = "disabled"; ++ dma-coherent; ++ mediatek,hifsys = <&hifsys>; ++ mediatek,cci-control = <&cci_control2>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; +@@ -937,7 +943,7 @@ + }; + + hifsys: clock-controller@1af00000 { +- compatible = "mediatek,mt7622-hifsys"; ++ compatible = "mediatek,mt7622-hifsys", "syscon"; + reg = <0 0x1af00000 0 0x70>; + #clock-cells = <1>; + }; +--- a/drivers/pci/controller/pcie-mediatek.c ++++ b/drivers/pci/controller/pcie-mediatek.c +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -139,6 +140,11 @@ + #define PCIE_LINK_STATUS_V2 0x804 + #define PCIE_PORT_LINKUP_V2 BIT(10) + ++/* DMA channel mapping */ ++#define HIFSYS_DMA_AG_MAP 0x008 ++#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0) ++#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1) ++ + struct mtk_pcie_port; + + /** +@@ -1052,6 +1058,27 @@ static int mtk_pcie_setup(struct mtk_pci + struct mtk_pcie_port *port, *tmp; + int err, slot; + ++ if (of_dma_is_coherent(node)) { ++ struct regmap *con; ++ u32 mask; ++ ++ con = syscon_regmap_lookup_by_phandle(node, ++ "mediatek,cci-control"); ++ /* enable CPU/bus coherency */ ++ if (!IS_ERR(con)) ++ regmap_write(con, 0, 3); ++ ++ con = syscon_regmap_lookup_by_phandle(node, ++ "mediatek,hifsys"); ++ if (IS_ERR(con)) { ++ dev_err(dev, "missing hifsys node\n"); ++ return PTR_ERR(con); ++ } ++ ++ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1; ++ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask); ++ } ++ + slot = of_get_pci_domain_nr(dev->of_node); + if (slot < 0) { + for_each_available_child_of_node(node, child) { diff --git a/target/linux/mediatek/patches-6.12/721-dts-mt7622-mediatek-fix-300mhz.patch b/target/linux/mediatek/patches-6.12/721-dts-mt7622-mediatek-fix-300mhz.patch new file mode 100644 index 0000000000..f9a5fdbd0d --- /dev/null +++ b/target/linux/mediatek/patches-6.12/721-dts-mt7622-mediatek-fix-300mhz.patch @@ -0,0 +1,27 @@ +From: Jip de Beer +Date: Sun, 9 Jan 2022 13:14:04 +0100 +Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts + +The lowest frequency should be 300MHz, since that is the label +assigned to the OPP in the mt7622.dtsi device tree, while there is one +missing zero in the actual value. + +To be clear, the lowest frequency should be 300MHz instead of 30MHz. + +As mentioned @dangowrt on the OpenWrt forum there is no benefit in +leaving 30MHz as the lowest frequency. + +Signed-off-by: Jip de Beer +Signed-off-by: Fritz D. Ansel +--- +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -24,7 +24,7 @@ + compatible = "operating-points-v2"; + opp-shared; + opp-300000000 { +- opp-hz = /bits/ 64 <30000000>; ++ opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000>; + }; + diff --git a/target/linux/mediatek/patches-6.12/722-remove-300Hz-to-prevent-freeze.patch b/target/linux/mediatek/patches-6.12/722-remove-300Hz-to-prevent-freeze.patch new file mode 100644 index 0000000000..52069496ca --- /dev/null +++ b/target/linux/mediatek/patches-6.12/722-remove-300Hz-to-prevent-freeze.patch @@ -0,0 +1,25 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -23,11 +23,17 @@ + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <950000>; +- }; +- ++ /* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low ++ * voltage condition that can cause a hang when rebooting the RT3200/E8450. ++ * ++ * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490 ++ * ++ * opp-300000000 { ++ * opp-hz = /bits/ 64 <300000000>; ++ * opp-microvolt = <950000>; ++ * }; ++ * ++ */ + opp-437500000 { + opp-hz = /bits/ 64 <437500000>; + opp-microvolt = <1000000>; diff --git a/target/linux/mediatek/patches-6.12/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/target/linux/mediatek/patches-6.12/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch new file mode 100644 index 0000000000..d1ac132ac5 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch @@ -0,0 +1,63 @@ +From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 6 Apr 2023 23:36:50 +0100 +Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink + +MAC drivers using phylink expect SGMII in-band-status to be switched off +when attached to a PHY. Make sure this is the case also for mxl-gpy which +keeps SGMII in-band-status in case of SGMII interface mode is used. + +Signed-off-by: Daniel Golle +--- + drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +--- a/drivers/net/phy/mxl-gpy.c ++++ b/drivers/net/phy/mxl-gpy.c +@@ -380,8 +380,11 @@ static bool gpy_2500basex_chk(struct phy + + phydev->speed = SPEED_2500; + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, +- VSPEC1_SGMII_CTRL_ANEN, 0); ++ ++ if (!phydev->phylink) ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, ++ VSPEC1_SGMII_CTRL_ANEN, 0); ++ + return true; + } + +@@ -432,6 +435,14 @@ static int gpy_config_aneg(struct phy_de + u32 adv; + int ret; + ++ /* Disable SGMII auto-negotiation if using phylink */ ++ if (phydev->phylink) { ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, ++ VSPEC1_SGMII_CTRL_ANEN, 0); ++ if (ret < 0) ++ return ret; ++ } ++ + if (phydev->autoneg == AUTONEG_DISABLE) { + /* Configure half duplex with genphy_setup_forced, + * because genphy_c45_pma_setup_forced does not support. +@@ -554,6 +565,8 @@ static int gpy_update_interface(struct p + switch (phydev->speed) { + case SPEED_2500: + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; ++ if (phydev->phylink) ++ break; + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, + VSPEC1_SGMII_CTRL_ANEN, 0); + if (ret < 0) { +@@ -567,7 +580,7 @@ static int gpy_update_interface(struct p + case SPEED_100: + case SPEED_10: + phydev->interface = PHY_INTERFACE_MODE_SGMII; +- if (gpy_sgmii_aneg_en(phydev)) ++ if (phydev->phylink || gpy_sgmii_aneg_en(phydev)) + break; + /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed + * if ANEG is disabled (in 2500-BaseX mode). diff --git a/target/linux/mediatek/patches-6.12/733-net-phy-realtek-add-led-link-select-for-RTL8221.patch b/target/linux/mediatek/patches-6.12/733-net-phy-realtek-add-led-link-select-for-RTL8221.patch new file mode 100644 index 0000000000..3087170998 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/733-net-phy-realtek-add-led-link-select-for-RTL8221.patch @@ -0,0 +1,88 @@ +From f9e17c264d316611c26b98ad1a3ca01c289c67b4 Mon Sep 17 00:00:00 2001 +From: Yangyu Chen +Date: Sun, 23 Apr 2023 20:06:41 +0800 +Subject: [PATCH] net: phy: realtek: add led-link-select for RTL8221 + +RTL8221B PHYs will select the different speeds for 3 LEDs to 10M/100M/1G +respectively by default. Some devices like TP-LINK XDR-6088/XDR-6086 +have only one LED connects to the PHY chip LED0. If we didn't change the +default settings, the LED will only blink at 10M speed. + +This patch allows configuring LED link select bitmask from DT. And it +has been tested with TP-Link XDR6088 with different DT configurations. + +Signed-off-by: Yangyu Chen +--- + drivers/net/phy/realtek.c | 28 +++++++++++++++++++++++++++- + 1 file changed, 27 insertions(+), 1 deletion(-) + +--- a/drivers/net/phy/realtek/realtek_main.c ++++ b/drivers/net/phy/realtek/realtek_main.c +@@ -133,6 +133,12 @@ + #define RTL8221B_PHYCR1_ALDPS_EN BIT(2) + #define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN BIT(12) + ++#define RTL8221B_NR_LEDS 3 ++#define RTL8221B_LED_LINK_SELECT 0xd032 ++#define RTL8221B_LED_LINK_SELECT_OFFSET 0x2 ++#define RTL8221B_LED_ACT_SELECT 0xd040 ++#define RTL8221B_LED_POLARITY_SELECT 0xd044 ++ + #define RTL8366RB_POWER_SAVE 0x15 + #define RTL8366RB_POWER_SAVE_ON BIT(12) + +@@ -1036,6 +1042,45 @@ static int rtl822x_probe(struct phy_devi + return 0; + } + ++static int rtl8221b_config_led(struct phy_device *phydev) { ++ struct device *node = &phydev->mdio.dev; ++ u32 link_select[RTL8221B_NR_LEDS]; ++ u32 act_select, polarity_select; ++ int i, val; ++ ++ val = device_property_read_u32_array(node, "realtek,led-link-select", ++ link_select, RTL8221B_NR_LEDS); ++ if (!val) { ++ for (i = 0; i < RTL8221B_NR_LEDS; i++) { ++ val = phy_write_mmd(phydev, MDIO_MMD_VEND2, ++ RTL8221B_LED_LINK_SELECT + i * RTL8221B_LED_LINK_SELECT_OFFSET, ++ link_select[i]); ++ if (val < 0) ++ return val; ++ } ++ } ++ ++ val = device_property_read_u32(node, ++ "realtek,led-act-select", &act_select); ++ if (!val) { ++ val = phy_write_mmd(phydev, MDIO_MMD_VEND2, ++ RTL8221B_LED_ACT_SELECT, act_select); ++ if (val < 0) ++ return val; ++ } ++ ++ val = device_property_read_u32(node, ++ "realtek,led-polarity-select", &polarity_select); ++ if (!val) { ++ val = phy_write_mmd(phydev, MDIO_MMD_VEND2, ++ RTL8221B_LED_POLARITY_SELECT, polarity_select); ++ if (val < 0) ++ return val; ++ } ++ ++ return 0; ++} ++ + static int rtl822xb_config_init(struct phy_device *phydev) + { + bool has_2500, has_sgmii; +@@ -1126,7 +1171,7 @@ static int rtl822xb_config_init(struct p + if (ret < 0) + return ret; + +- return 0; ++ return rtl8221b_config_led(phydev); + } + + static int rtl822xb_config_init_war(struct phy_device *phydev) diff --git a/target/linux/mediatek/patches-6.12/734-net-phy-add-Airoha-EN8801SC-PHY.patch b/target/linux/mediatek/patches-6.12/734-net-phy-add-Airoha-EN8801SC-PHY.patch new file mode 100644 index 0000000000..079351b7a2 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/734-net-phy-add-Airoha-EN8801SC-PHY.patch @@ -0,0 +1,38 @@ +From 5314e73cb941b47e6866b49b3b78c25e32d62df8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 23 Mar 2024 20:21:14 +0100 +Subject: [PATCH] net: phy: add Airoha EN8801SC PHY + +Airoha EN8801SC Gigabit PHY is used on Edgecore EAP111, so include a +modified version of MTK SDK driver. + +Signed-off-by: Robert Marko +--- + drivers/net/phy/Kconfig | 5 +++++ + drivers/net/phy/Makefile | 1 + + 2 files changed, 6 insertions(+) + +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -153,6 +153,11 @@ endif # RTL8366_SMI + + comment "MII PHY device drivers" + ++config AIROHA_EN8801SC_PHY ++ tristate "Airoha EN8801SC Gigabit PHY" ++ help ++ Currently supports the Airoha EN8801SC PHY. ++ + config AIR_EN8811H_PHY + tristate "Airoha EN8811H 2.5 Gigabit PHY" + help +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -50,6 +50,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) + + obj-$(CONFIG_ADIN_PHY) += adin.o + obj-$(CONFIG_ADIN1100_PHY) += adin1100.o ++obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o + obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o + obj-$(CONFIG_AMD_PHY) += amd.o + obj-$(CONFIG_AMCC_QT2025_PHY) += qt2025.o diff --git a/target/linux/mediatek/patches-6.12/736-net-pcs-mtk_usxgmii-add-polarity-control.patch b/target/linux/mediatek/patches-6.12/736-net-pcs-mtk_usxgmii-add-polarity-control.patch new file mode 100644 index 0000000000..68ee609aac --- /dev/null +++ b/target/linux/mediatek/patches-6.12/736-net-pcs-mtk_usxgmii-add-polarity-control.patch @@ -0,0 +1,56 @@ +--- a/drivers/net/pcs/pcs-mtk-usxgmii.c ++++ b/drivers/net/pcs/pcs-mtk-usxgmii.c +@@ -52,6 +52,12 @@ + #define USXGMII_LPA GENMASK(15, 0) + #define USXGMII_LPA_LATCH BIT(31) + ++/* Register to control PCS polarity */ ++#define RG_PHY_TOP_CTRL0 0x82C ++#define USXGMII_PN_SWAP_MASK GENMASK(1, 0) ++#define USXGMII_PN_SWAP_RX BIT(1) ++#define USXGMII_PN_SWAP_TX BIT(0) ++ + /* Register to read PCS link status */ + #define RG_PCS_RX_STATUS0 0x904 + #define RG_PCS_RX_STATUS_UPDATE BIT(16) +@@ -74,6 +80,7 @@ struct mtk_usxgmii_pcs { + struct clk *clk; + struct reset_control *reset; + phy_interface_t interface; ++ unsigned int polarity; + unsigned int neg_mode; + struct list_head node; + }; +@@ -155,6 +162,10 @@ static int mtk_usxgmii_pcs_config(struct + + mtk_usxgmii_reset(mpcs); + ++ /* Configure the interface polarity */ ++ mtk_m32(mpcs, RG_PHY_TOP_CTRL0, ++ USXGMII_PN_SWAP_MASK, mpcs->polarity); ++ + /* Setup USXGMII AN ctrl */ + mtk_m32(mpcs, RG_PCS_AN_CTRL0, + USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE, +@@ -332,6 +343,7 @@ static const struct phylink_pcs_ops mtk_ + static int mtk_usxgmii_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; + struct mtk_usxgmii_pcs *mpcs; + + mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL); +@@ -342,6 +354,13 @@ static int mtk_usxgmii_probe(struct plat + if (IS_ERR(mpcs->base)) + return PTR_ERR(mpcs->base); + ++ if (of_property_read_bool(np->parent, "mediatek,pnswap")) ++ mpcs->polarity = USXGMII_PN_SWAP_TX | USXGMII_PN_SWAP_RX; ++ else if (of_property_read_bool(np, "mediatek,pnswap-tx")) ++ mpcs->polarity = USXGMII_PN_SWAP_TX; ++ else if (of_property_read_bool(np, "mediatek,pnswap-rx")) ++ mpcs->polarity = USXGMII_PN_SWAP_RX; ++ + mpcs->dev = dev; + mpcs->pcs.ops = &mtk_usxgmii_pcs_ops; + mpcs->pcs.poll = true; diff --git a/target/linux/mediatek/patches-6.12/737-net-dsa-add-Airoha-AN8855.patch b/target/linux/mediatek/patches-6.12/737-net-dsa-add-Airoha-AN8855.patch new file mode 100644 index 0000000000..b0adf04a5b --- /dev/null +++ b/target/linux/mediatek/patches-6.12/737-net-dsa-add-Airoha-AN8855.patch @@ -0,0 +1,309 @@ +From: Christian Marangi +To: Christian Marangi , + Lee Jones , Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Andrew Lunn , + "David S. Miller" , + Eric Dumazet , + Jakub Kicinski , Paolo Abeni , + Vladimir Oltean , + Srinivas Kandagatla , + Heiner Kallweit , + Russell King , + Matthias Brugger , + AngeloGioacchino Del Regno + , + linux-arm-kernel@lists.infradead.org, + linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, + devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, + upstream@airoha.com +Subject: [net-next PATCH v11 0/9] net: dsa: Add Airoha AN8855 support +Date: Mon, 9 Dec 2024 14:44:17 +0100 [thread overview] +Message-ID: <20241209134459.27110-1-ansuelsmth@gmail.com> (raw) + +This small series add the initial support for the Airoha AN8855 Switch. + +It's a 5 port Gigabit Switch with SGMII/HSGMII upstream port. + +This is starting to get in the wild and there are already some router +having this switch chip. + +It's conceptually similar to mediatek switch but register and bits +are different. And there is that massive Hell that is the PCS +configuration. +Saddly for that part we have absolutely NO documentation currently. + +There is this special thing where PHY needs to be calibrated with values +from the switch efuse. (the thing have a whole cpu timer and MCU) + +Changes v11: +- Address reviews from Christophe (spell mistake + dev_err_probe) +- Fix kconfig dependency for MFD driver (depends on MDIO_DEVICE instead of MDIO) + (indirectly fix link error for mdio APIs) +- Fix copy-paste error for MFD driver of_table +- Fix compilation error for PHY (move NVMEM to .config) +- Drop unneeded NVMEM node from MDIO example schema (from Andrew) +- Adapt MFD example schema to MDIO reg property restrictions +Changes v10: +- Entire rework to MFD + split to MDIO, EFUSE, SWITCH separate drivers +- Drop EEE OPs (while Russell finish RFC for EEE changes) +- Use new pcs_inpand OPs +- Drop AN restart function and move to pcs_config +- Enable assisted_learning and disable CPU learn (preparation for fdb_isolation) +- Move EFUSE read in Internal PHY driver to .config to handle EPROBE_DEFER + (needed now that NVMEM driver is register externally instead of internally to switch + node) +Changes v9: +- Error out on using 5G speed as currently not supported +- Add missing MAC_2500FD in phylink mac_capabilities +- Add comment and improve if condition for an8855_phylink_mac_config +Changes v8: +- Add port Fast Age support +- Add support for Port Isolation +- Use correct register for Learning Disable +- Add support for Ageing Time OP +- Set default PVID to 0 by default +- Add mdb OPs +- Add port change MTU +- Fix support for Upper VLAN +Changes v7: +- Fix devm_dsa_register_switch wrong export symbol +Changes v6: +- Drop standard MIB and handle with ethtool OPs (as requested by Jakub) +- Cosmetic: use bool instead of 0 or 1 +Changes v5: +- Add devm_dsa_register_switch() patch +- Add Reviewed-by tag for DT patch +Changes v4: +- Set regmap readable_table static (mute compilation warning) +- Add support for port_bridge flags (LEARNING, FLOOD) +- Reset fdb struct in fdb_dump +- Drop support_asym_pause in port_enable +- Add define for get_phy_flags +- Fix bug for port not inititially part of a bridge + (in an8855_setup the port matrix was always cleared but + the CPU port was never initially added) +- Disable learning and flood for user port by default +- Set CPU port to flood and learning by default +- Correctly AND force duplex and flow control in an8855_phylink_mac_link_up +- Drop RGMII from pcs_config +- Check ret in "Disable AN if not in autoneg" +- Use devm_mutex_init +- Fix typo for AN8855_PORT_CHECK_MODE +- Better define AN8855_STP_LISTENING = AN8855_STP_BLOCKING +- Fix typo in AN8855_PHY_EN_DOWN_SHIFT +- Use paged helper for PHY +- Skip calibration in config_init if priv not defined +Changes v3: +- Out of RFC +- Switch PHY code to select_page API +- Better describe masks and bits in PHY driver for ADC register +- Drop raw values and use define for mii read/write +- Switch to absolute PHY address +- Replace raw values with mask and bits for pcs_config +- Fix typo for ext-surge property name +- Drop support for relocating Switch base PHY address on the bus +Changes v2: +- Drop mutex guard patch +- Drop guard usage in DSA driver +- Use __mdiobus_write/read +- Check return condition and return errors for mii read/write +- Fix wrong logic for EEE +- Fix link_down (don't force link down with autoneg) +- Fix forcing speed on sgmii autoneg +- Better document link speed for sgmii reg +- Use standard define for sgmii reg +- Imlement nvmem support to expose switch EFUSE +- Rework PHY calibration with the use of NVMEM producer/consumer +- Update DT with new NVMEM property +- Move aneg validation for 2500-basex in pcs_config +- Move r50Ohm table and function to PHY driver + +Christian Marangi (9): + dt-bindings: nvmem: Document support for Airoha AN8855 Switch EFUSE + dt-bindings: net: Document support for Airoha AN8855 Switch Virtual + MDIO + dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch + dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC + mfd: an8855: Add support for Airoha AN8855 Switch MFD + net: mdio: Add Airoha AN8855 Switch MDIO Passtrough + nvmem: an8855: Add support for Airoha AN8855 Switch EFUSE + net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver + net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY + + .../bindings/mfd/airoha,an8855-mfd.yaml | 178 ++ + .../bindings/net/airoha,an8855-mdio.yaml | 56 + + .../net/dsa/airoha,an8855-switch.yaml | 105 + + .../bindings/nvmem/airoha,an8855-efuse.yaml | 123 + + MAINTAINERS | 17 + + drivers/mfd/Kconfig | 10 + + drivers/mfd/Makefile | 1 + + drivers/mfd/airoha-an8855.c | 278 ++ + drivers/net/dsa/Kconfig | 9 + + drivers/net/dsa/Makefile | 1 + + drivers/net/dsa/an8855.c | 2310 +++++++++++++++++ + drivers/net/dsa/an8855.h | 783 ++++++ + drivers/net/mdio/Kconfig | 9 + + drivers/net/mdio/Makefile | 1 + + drivers/net/mdio/mdio-an8855.c | 113 + + drivers/net/phy/Kconfig | 5 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/air_an8855.c | 267 ++ + drivers/nvmem/Kconfig | 11 + + drivers/nvmem/Makefile | 2 + + drivers/nvmem/an8855-efuse.c | 63 + + include/linux/mfd/airoha-an8855-mfd.h | 41 + + 22 files changed, 4384 insertions(+) + create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855-mfd.yaml + create mode 100644 Documentation/devicetree/bindings/net/airoha,an8855-mdio.yaml + create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml + create mode 100644 Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml + create mode 100644 drivers/mfd/airoha-an8855.c + create mode 100644 drivers/net/dsa/an8855.c + create mode 100644 drivers/net/dsa/an8855.h + create mode 100644 drivers/net/mdio/mdio-an8855.c + create mode 100644 drivers/net/phy/air_an8855.c + create mode 100644 drivers/nvmem/an8855-efuse.c + create mode 100644 include/linux/mfd/airoha-an8855-mfd.h + +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -53,6 +53,16 @@ config MFD_ALTERA_SYSMGR + using regmap_mmio accesses for ARM32 parts and SMC calls to + EL3 for ARM64 parts. + ++config MFD_AIROHA_AN8855 ++ tristate "Airoha AN8855 Switch MFD" ++ select MFD_CORE ++ select MDIO_DEVICE ++ depends on NETDEVICES && OF ++ help ++ Support for the Airoha AN8855 Switch MFD. This is a SoC Switch ++ that provides various peripherals. Currently it provides a ++ DSA switch and a NVMEM provider. ++ + config MFD_ACT8945A + tristate "Active-semi ACT8945A" + select MFD_CORE +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -9,6 +9,7 @@ obj-$(CONFIG_MFD_88PM800) += 88pm800.o 8 + obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o + obj-$(CONFIG_MFD_88PM886_PMIC) += 88pm886.o + obj-$(CONFIG_MFD_ACT8945A) += act8945a.o ++obj-$(CONFIG_MFD_AIROHA_AN8855) += airoha-an8855.o + obj-$(CONFIG_MFD_SM501) += sm501.o + obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o + obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o +--- a/drivers/net/dsa/Kconfig ++++ b/drivers/net/dsa/Kconfig +@@ -24,6 +24,15 @@ config NET_DSA_LOOP + This enables support for a fake mock-up switch chip which + exercises the DSA APIs. + ++config NET_DSA_AN8855 ++ tristate "Airoha AN8855 Ethernet switch support" ++ depends on MFD_AIROHA_AN8855 ++ depends on NET_DSA ++ select NET_DSA_TAG_MTK ++ help ++ This enables support for the Airoha AN8855 Ethernet switch ++ chip. ++ + source "drivers/net/dsa/hirschmann/Kconfig" + + config NET_DSA_LANTIQ_GSWIP +--- a/drivers/net/dsa/Makefile ++++ b/drivers/net/dsa/Makefile +@@ -5,6 +5,7 @@ obj-$(CONFIG_NET_DSA_LOOP) += dsa_loop.o + ifdef CONFIG_NET_DSA_LOOP + obj-$(CONFIG_FIXED_PHY) += dsa_loop_bdinfo.o + endif ++obj-$(CONFIG_NET_DSA_AN8855) += an8855.o + obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o + obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o + obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o +--- a/drivers/net/mdio/Kconfig ++++ b/drivers/net/mdio/Kconfig +@@ -61,6 +61,15 @@ config MDIO_XGENE + This module provides a driver for the MDIO busses found in the + APM X-Gene SoC's. + ++config MDIO_AN8855 ++ tristate "Airoha AN8855 Switch MDIO bus controller" ++ depends on MFD_AIROHA_AN8855 ++ depends on OF_MDIO ++ help ++ This module provides a driver for the Airoha AN8855 Switch ++ that requires a MDIO passtrough as switch address is shared ++ with the internal PHYs and requires additional page handling. ++ + config MDIO_ASPEED + tristate "ASPEED MDIO bus controller" + depends on ARCH_ASPEED || COMPILE_TEST +--- a/drivers/net/mdio/Makefile ++++ b/drivers/net/mdio/Makefile +@@ -5,6 +5,7 @@ obj-$(CONFIG_ACPI_MDIO) += acpi_mdio.o + obj-$(CONFIG_FWNODE_MDIO) += fwnode_mdio.o + obj-$(CONFIG_OF_MDIO) += of_mdio.o + ++obj-$(CONFIG_MDIO_AN8855) += mdio-an8855.o + obj-$(CONFIG_MDIO_ASPEED) += mdio-aspeed.o + obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o + obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -158,6 +158,11 @@ config AIROHA_EN8801SC_PHY + help + Currently supports the Airoha EN8801SC PHY. + ++config AIR_AN8855_PHY ++ tristate "Airoha AN8855 Internal Gigabit PHY" ++ help ++ Currently supports the internal Airoha AN8855 Switch PHY. ++ + config AIR_EN8811H_PHY + tristate "Airoha EN8811H 2.5 Gigabit PHY" + help +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -51,6 +51,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) + obj-$(CONFIG_ADIN_PHY) += adin.o + obj-$(CONFIG_ADIN1100_PHY) += adin1100.o + obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o ++obj-$(CONFIG_AIR_AN8855_PHY) += air_an8855.o + obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o + obj-$(CONFIG_AMD_PHY) += amd.o + obj-$(CONFIG_AMCC_QT2025_PHY) += qt2025.o +--- a/drivers/nvmem/Kconfig ++++ b/drivers/nvmem/Kconfig +@@ -29,6 +29,17 @@ source "drivers/nvmem/layouts/Kconfig" + + # Devices + ++config NVMEM_AN8855_EFUSE ++ tristate "Airoha AN8855 eFuse support" ++ depends on MFD_AIROHA_AN8855 || COMPILE_TEST ++ help ++ Say y here to enable support for reading eFuses on Airoha AN8855 ++ Switch. These are e.g. used to store factory programmed ++ calibration data required for the PHY. ++ ++ This driver can also be built as a module. If so, the module will ++ be called nvmem-an8855-efuse. ++ + config NVMEM_APPLE_EFUSES + tristate "Apple eFuse support" + depends on ARCH_APPLE || COMPILE_TEST +--- a/drivers/nvmem/Makefile ++++ b/drivers/nvmem/Makefile +@@ -10,6 +10,8 @@ nvmem_layouts-y := layouts.o + obj-y += layouts/ + + # Devices ++obj-$(CONFIG_NVMEM_AN8855_EFUSE) += nvmem-an8855-efuse.o ++nvmem-an8855-efuse-y := an8855-efuse.o + obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o + nvmem-apple-efuses-y := apple-efuses.o + obj-$(CONFIG_NVMEM_BCM_OCOTP) += nvmem-bcm-ocotp.o diff --git a/target/linux/mediatek/patches-6.12/739-net-add-negotiation-of-in-band-capabilities.patch b/target/linux/mediatek/patches-6.12/739-net-add-negotiation-of-in-band-capabilities.patch new file mode 100644 index 0000000000..0c23c5b405 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/739-net-add-negotiation-of-in-band-capabilities.patch @@ -0,0 +1,1242 @@ +From: "Russell King (Oracle)" +To: Andrew Lunn , Heiner Kallweit +Cc: Alexander Couzens , + Andrew Lunn , + AngeloGioacchino Del Regno + , + Broadcom internal kernel review list + , + Daniel Golle , + "David S. Miller" , + Eric Dumazet , + Florian Fainelli , + Ioana Ciornei , + Jakub Kicinski , + Jose Abreu , + linux-arm-kernel@lists.infradead.org, + linux-mediatek@lists.infradead.org, + Marcin Wojtas , + Matthias Brugger , + netdev@vger.kernel.org, Paolo Abeni +Subject: [PATCH RFC net-next 00/16] net: add negotiation of in-band capabilities +Date: Tue, 26 Nov 2024 09:23:48 +0000 [thread overview] +Message-ID: (raw) + +Hi, + +Yes, this is one patch over the limit of 15 for netdev - but I think it's +important to include the last patch to head off review comments like "why +don't you remove phylink_phy_no_inband() in this series?" + +Phylink's handling of in-band has been deficient for a long time, and +people keep hitting problems with it. Notably, situations with the way- +to-late standardized 2500Base-X and whether that should or should not +have in-band enabled. We have also been carrying a hack in the form of +phylink_phy_no_inband() for a PHY that has been used on a SFP module, +but has no in-band capabilities, not even for SGMII. + +When phylink is trying to operate in in-band mode, this series will look +at the capabilities of the MAC-side PCS and PHY, and work out whether +in-band can or should be used, programming the PHY as appropriate. This +includes in-band bypass mode at the PHY. + +We don't... yet... support that on the MAC side PCS, because that +requires yet more complexity. + +Patch 1 passes struct phylink and struct phylink_pcs into +phylink_pcs_neg_mode() so we can look at more state in this function in +a future patch. + +Patch 2 splits "cur_link_an_mode" (the MLO_AN_* mode) into two separate +purposes - a requested and an active mode. The active mode is the one +we will be using for the MAC, which becomes dependent on the result of +in-band negotiation. + +Patch 3 adds debug to phylink_major_config() so we can see what is going +on with the requested and active AN modes. + +Patch 4 adds to phylib a method to get the in-band capabilities of the +PHY from phylib. Patches 5 and 6 add implementations for BCM84881 and +some Marvell PHYs found on SFPs. + +Patch 7 adds to phylib a method to configure the PHY in-band signalling, +and patch 8 implements it for those Marvell PHYs that support the method +in patch 4. + +Patch 9 does the same as patch 4 but for the MAC-side PCS, with patches +10 through 14 adding support to several PCS. + +Patch 15 adds the code to phylink_pcs_neg_mode() which looks at the +capabilities, and works out whether to use in-band or out-band mode for +driving the link between the MAC PCS and PHY. + +Patch 16 removes the phylink_phy_no_inband() hack now that we are +publishing the in-band capabilities from the BCM84881 PHY driver. + + drivers/net/ethernet/marvell/mvneta.c | 27 +- + drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 25 +- + drivers/net/pcs/pcs-lynx.c | 22 ++ + drivers/net/pcs/pcs-mtk-lynxi.c | 16 ++ + drivers/net/pcs/pcs-xpcs.c | 28 ++ + drivers/net/phy/bcm84881.c | 10 + + drivers/net/phy/marvell.c | 48 ++++ + drivers/net/phy/phy.c | 52 ++++ + drivers/net/phy/phylink.c | 352 +++++++++++++++++++----- + include/linux/phy.h | 34 +++ + include/linux/phylink.h | 17 ++ + 11 files changed, 539 insertions(+), 92 deletions(-) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -56,7 +56,8 @@ struct phylink { + struct phy_device *phydev; + phy_interface_t link_interface; /* PHY_INTERFACE_xxx */ + u8 cfg_link_an_mode; /* MLO_AN_xxx */ +- u8 cur_link_an_mode; ++ u8 req_link_an_mode; /* Requested MLO_AN_xxx mode */ ++ u8 act_link_an_mode; /* Active MLO_AN_xxx mode */ + u8 link_port; /* The current non-phy ethtool port */ + __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); + +@@ -74,6 +75,7 @@ struct phylink { + + struct mutex state_mutex; + struct phylink_link_state phy_state; ++ unsigned int phy_ib_mode; + struct work_struct resolve; + unsigned int pcs_neg_mode; + unsigned int pcs_state; +@@ -175,6 +177,24 @@ static const char *phylink_an_mode_str(u + return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown"; + } + ++static const char *phylink_pcs_mode_str(unsigned int mode) ++{ ++ if (!mode) ++ return "none"; ++ ++ if (mode & PHYLINK_PCS_NEG_OUTBAND) ++ return "outband"; ++ ++ if (mode & PHYLINK_PCS_NEG_INBAND) { ++ if (mode & PHYLINK_PCS_NEG_ENABLED) ++ return "inband,an-enabled"; ++ else ++ return "inband,an-disabled"; ++ } ++ ++ return "unknown"; ++} ++ + static unsigned int phylink_interface_signal_rate(phy_interface_t interface) + { + switch (interface) { +@@ -988,6 +1008,15 @@ static void phylink_resolve_an_pause(str + } + } + ++static unsigned int phylink_pcs_inband_caps(struct phylink_pcs *pcs, ++ phy_interface_t interface) ++{ ++ if (pcs && pcs->ops->pcs_inband_caps) ++ return pcs->ops->pcs_inband_caps(pcs, interface); ++ ++ return 0; ++} ++ + static void phylink_pcs_pre_config(struct phylink_pcs *pcs, + phy_interface_t interface) + { +@@ -1041,6 +1070,24 @@ static void phylink_pcs_link_up(struct p + pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex); + } + ++/* Query inband for a specific interface mode, asking the MAC for the ++ * PCS which will be used to handle the interface mode. ++ */ ++static unsigned int phylink_inband_caps(struct phylink *pl, ++ phy_interface_t interface) ++{ ++ struct phylink_pcs *pcs; ++ ++ if (!pl->mac_ops->mac_select_pcs) ++ return 0; ++ ++ pcs = pl->mac_ops->mac_select_pcs(pl->config, interface); ++ if (!pcs) ++ return 0; ++ ++ return phylink_pcs_inband_caps(pcs, interface); ++} ++ + static void phylink_pcs_poll_stop(struct phylink *pl) + { + if (pl->cfg_link_an_mode == MLO_AN_INBAND) +@@ -1082,13 +1129,13 @@ static void phylink_mac_config(struct ph + + phylink_dbg(pl, + "%s: mode=%s/%s/%s adv=%*pb pause=%02x\n", +- __func__, phylink_an_mode_str(pl->cur_link_an_mode), ++ __func__, phylink_an_mode_str(pl->act_link_an_mode), + phy_modes(st.interface), + phy_rate_matching_to_str(st.rate_matching), + __ETHTOOL_LINK_MODE_MASK_NBITS, st.advertising, + st.pause); + +- pl->mac_ops->mac_config(pl->config, pl->cur_link_an_mode, &st); ++ pl->mac_ops->mac_config(pl->config, pl->act_link_an_mode, &st); + } + + static void phylink_pcs_an_restart(struct phylink *pl) +@@ -1096,13 +1143,14 @@ static void phylink_pcs_an_restart(struc + if (pl->pcs && linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, + pl->link_config.advertising) && + phy_interface_mode_is_8023z(pl->link_config.interface) && +- phylink_autoneg_inband(pl->cur_link_an_mode)) ++ phylink_autoneg_inband(pl->act_link_an_mode)) + pl->pcs->ops->pcs_an_restart(pl->pcs); + } + + /** + * phylink_pcs_neg_mode() - helper to determine PCS inband mode +- * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND. ++ * @pl: a pointer to a &struct phylink returned from phylink_create() ++ * @pcs: a pointer to &struct phylink_pcs + * @interface: interface mode to be used + * @advertising: adertisement ethtool link mode mask + * +@@ -1119,11 +1167,21 @@ static void phylink_pcs_an_restart(struc + * Note: this is for cases where the PCS itself is involved in negotiation + * (e.g. Clause 37, SGMII and similar) not Clause 73. + */ +-static unsigned int phylink_pcs_neg_mode(unsigned int mode, +- phy_interface_t interface, +- const unsigned long *advertising) ++static void phylink_pcs_neg_mode(struct phylink *pl, struct phylink_pcs *pcs, ++ phy_interface_t interface, ++ const unsigned long *advertising) + { +- unsigned int neg_mode; ++ unsigned int pcs_ib_caps = 0; ++ unsigned int phy_ib_caps = 0; ++ unsigned int neg_mode, mode; ++ enum { ++ INBAND_CISCO_SGMII, ++ INBAND_BASEX, ++ } type; ++ ++ mode = pl->req_link_an_mode; ++ ++ pl->phy_ib_mode = 0; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: +@@ -1136,10 +1194,7 @@ static unsigned int phylink_pcs_neg_mode + * inband communication. Note: there exist PHYs that run + * with SGMII but do not send the inband data. + */ +- if (!phylink_autoneg_inband(mode)) +- neg_mode = PHYLINK_PCS_NEG_OUTBAND; +- else +- neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; ++ type = INBAND_CISCO_SGMII; + break; + + case PHY_INTERFACE_MODE_1000BASEX: +@@ -1150,21 +1205,143 @@ static unsigned int phylink_pcs_neg_mode + * as well, but drivers may not support this, so may + * need to override this. + */ +- if (!phylink_autoneg_inband(mode)) ++ type = INBAND_BASEX; ++ break; ++ ++ default: ++ pl->pcs_neg_mode = PHYLINK_PCS_NEG_NONE; ++ pl->act_link_an_mode = mode; ++ return; ++ } ++ ++ if (pcs) ++ pcs_ib_caps = phylink_pcs_inband_caps(pcs, interface); ++ ++ if (pl->phydev) ++ phy_ib_caps = phy_inband_caps(pl->phydev, interface); ++ ++ phylink_dbg(pl, "interface %s inband modes: pcs=%02x phy=%02x\n", ++ phy_modes(interface), pcs_ib_caps, phy_ib_caps); ++ ++ if (!phylink_autoneg_inband(mode)) { ++ bool pcs_ib_only = false; ++ bool phy_ib_only = false; ++ ++ if (pcs_ib_caps && pcs_ib_caps != LINK_INBAND_DISABLE) { ++ /* PCS supports reporting in-band capabilities, and ++ * supports more than disable mode. ++ */ ++ if (pcs_ib_caps & LINK_INBAND_DISABLE) ++ neg_mode = PHYLINK_PCS_NEG_OUTBAND; ++ else if (pcs_ib_caps & LINK_INBAND_ENABLE) ++ pcs_ib_only = true; ++ } ++ ++ if (phy_ib_caps && phy_ib_caps != LINK_INBAND_DISABLE) { ++ /* PHY supports in-band capabilities, and supports ++ * more than disable mode. ++ */ ++ if (phy_ib_caps & LINK_INBAND_DISABLE) ++ pl->phy_ib_mode = LINK_INBAND_DISABLE; ++ else if (phy_ib_caps & LINK_INBAND_BYPASS) ++ pl->phy_ib_mode = LINK_INBAND_BYPASS; ++ else if (phy_ib_caps & LINK_INBAND_ENABLE) ++ phy_ib_only = true; ++ } ++ ++ /* If either the PCS or PHY requires inband to be enabled, ++ * this is an invalid configuration. Provide a diagnostic ++ * message for this case, but don't try to force the issue. ++ */ ++ if (pcs_ib_only || phy_ib_only) ++ phylink_warn(pl, ++ "firmware wants %s mode, but %s%s%s requires inband\n", ++ phylink_an_mode_str(mode), ++ pcs_ib_only ? "PCS" : "", ++ pcs_ib_only && phy_ib_only ? " and " : "", ++ phy_ib_only ? "PHY" : ""); ++ ++ neg_mode = PHYLINK_PCS_NEG_OUTBAND; ++ } else if (type == INBAND_CISCO_SGMII || pl->phydev) { ++ /* For SGMII modes which are designed to be used with PHYs, or ++ * Base-X with a PHY, we try to use in-band mode where-ever ++ * possible. However, there are some PHYs e.g. BCM84881 which ++ * do not support in-band. ++ */ ++ const unsigned int inband_ok = LINK_INBAND_ENABLE | ++ LINK_INBAND_BYPASS; ++ const unsigned int outband_ok = LINK_INBAND_DISABLE | ++ LINK_INBAND_BYPASS; ++ /* PCS PHY ++ * D E D E ++ * 0 0 0 0 no information inband enabled ++ * 1 0 0 0 pcs doesn't support outband ++ * 0 1 0 0 pcs required inband enabled ++ * 1 1 0 0 pcs optional inband enabled ++ * 0 0 1 0 phy doesn't support outband ++ * 1 0 1 0 pcs+phy doesn't support outband ++ * 0 1 1 0 pcs required, phy doesn't support, invalid ++ * 1 1 1 0 pcs optional, phy doesn't support, outband ++ * 0 0 0 1 phy required inband enabled ++ * 1 0 0 1 pcs doesn't support, phy required, invalid ++ * 0 1 0 1 pcs+phy required inband enabled ++ * 1 1 0 1 pcs optional, phy required inband enabled ++ * 0 0 1 1 phy optional inband enabled ++ * 1 0 1 1 pcs doesn't support, phy optional, outband ++ * 0 1 1 1 pcs required, phy optional inband enabled ++ * 1 1 1 1 pcs+phy optional inband enabled ++ */ ++ if ((!pcs_ib_caps || pcs_ib_caps & inband_ok) && ++ (!phy_ib_caps || phy_ib_caps & inband_ok)) { ++ /* In-band supported or unknown at both ends. Enable ++ * in-band mode with or without bypass at the PHY. ++ */ ++ if (phy_ib_caps & LINK_INBAND_ENABLE) ++ pl->phy_ib_mode = LINK_INBAND_ENABLE; ++ else if (phy_ib_caps & LINK_INBAND_BYPASS) ++ pl->phy_ib_mode = LINK_INBAND_BYPASS; ++ ++ neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; ++ } else if ((!pcs_ib_caps || pcs_ib_caps & outband_ok) && ++ (!phy_ib_caps || phy_ib_caps & outband_ok)) { ++ /* Either in-band not supported at at least one end. ++ * In-band bypass at the other end is possible. ++ */ ++ if (phy_ib_caps & LINK_INBAND_DISABLE) ++ pl->phy_ib_mode = LINK_INBAND_DISABLE; ++ else if (phy_ib_caps & LINK_INBAND_BYPASS) ++ pl->phy_ib_mode = LINK_INBAND_BYPASS; ++ + neg_mode = PHYLINK_PCS_NEG_OUTBAND; ++ if (pl->phydev) ++ mode = MLO_AN_PHY; ++ } else { ++ /* invalid */ ++ phylink_warn(pl, "%s: incompatible in-band capabilities, trying in-band", ++ phy_modes(interface)); ++ neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; ++ } ++ } else { ++ /* For Base-X without a PHY */ ++ if (pcs_ib_caps == LINK_INBAND_DISABLE) ++ /* If the PCS doesn't support inband, then inband must ++ * be disabled. ++ */ ++ neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED; ++ else if (pcs_ib_caps == LINK_INBAND_ENABLE) ++ /* If the PCS requires inband, then inband must always ++ * be enabled. ++ */ ++ neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; + else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, + advertising)) + neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; + else + neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED; +- break; +- +- default: +- neg_mode = PHYLINK_PCS_NEG_NONE; +- break; + } + +- return neg_mode; ++ pl->pcs_neg_mode = neg_mode; ++ pl->act_link_an_mode = mode; + } + + static void phylink_major_config(struct phylink *pl, bool restart, +@@ -1176,11 +1353,9 @@ static void phylink_major_config(struct + unsigned int neg_mode; + int err; + +- phylink_dbg(pl, "major config %s\n", phy_modes(state->interface)); +- +- pl->pcs_neg_mode = phylink_pcs_neg_mode(pl->cur_link_an_mode, +- state->interface, +- state->advertising); ++ phylink_dbg(pl, "major config, requested %s/%s\n", ++ phylink_an_mode_str(pl->req_link_an_mode), ++ phy_modes(state->interface)); + + if (pl->using_mac_select_pcs) { + pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface); +@@ -1194,10 +1369,17 @@ static void phylink_major_config(struct + pcs_changed = pcs && pl->pcs != pcs; + } + ++ phylink_pcs_neg_mode(pl, pcs, state->interface, state->advertising); ++ ++ phylink_dbg(pl, "major config, active %s/%s/%s\n", ++ phylink_an_mode_str(pl->act_link_an_mode), ++ phylink_pcs_mode_str(pl->pcs_neg_mode), ++ phy_modes(state->interface)); ++ + phylink_pcs_poll_stop(pl); + + if (pl->mac_ops->mac_prepare) { +- err = pl->mac_ops->mac_prepare(pl->config, pl->cur_link_an_mode, ++ err = pl->mac_ops->mac_prepare(pl->config, pl->act_link_an_mode, + state->interface); + if (err < 0) { + phylink_err(pl, "mac_prepare failed: %pe\n", +@@ -1231,7 +1413,7 @@ static void phylink_major_config(struct + if (pl->pcs_state == PCS_STATE_STARTING || pcs_changed) + phylink_pcs_enable(pl->pcs); + +- neg_mode = pl->cur_link_an_mode; ++ neg_mode = pl->act_link_an_mode; + if (pl->pcs && pl->pcs->neg_mode) + neg_mode = pl->pcs_neg_mode; + +@@ -1247,13 +1429,20 @@ static void phylink_major_config(struct + phylink_pcs_an_restart(pl); + + if (pl->mac_ops->mac_finish) { +- err = pl->mac_ops->mac_finish(pl->config, pl->cur_link_an_mode, ++ err = pl->mac_ops->mac_finish(pl->config, pl->act_link_an_mode, + state->interface); + if (err < 0) + phylink_err(pl, "mac_finish failed: %pe\n", + ERR_PTR(err)); + } + ++ if (pl->phydev && pl->phy_ib_mode) { ++ err = phy_config_inband(pl->phydev, pl->phy_ib_mode); ++ if (err < 0) ++ phylink_err(pl, "phy_config_inband: %pe\n", ++ ERR_PTR(err)); ++ } ++ + if (pl->sfp_bus) { + rate_kbd = phylink_interface_signal_rate(state->interface); + if (rate_kbd) +@@ -1278,17 +1467,16 @@ static int phylink_change_inband_advert( + return 0; + + phylink_dbg(pl, "%s: mode=%s/%s adv=%*pb pause=%02x\n", __func__, +- phylink_an_mode_str(pl->cur_link_an_mode), ++ phylink_an_mode_str(pl->req_link_an_mode), + phy_modes(pl->link_config.interface), + __ETHTOOL_LINK_MODE_MASK_NBITS, pl->link_config.advertising, + pl->link_config.pause); + + /* Recompute the PCS neg mode */ +- pl->pcs_neg_mode = phylink_pcs_neg_mode(pl->cur_link_an_mode, +- pl->link_config.interface, +- pl->link_config.advertising); ++ phylink_pcs_neg_mode(pl, pl->pcs, pl->link_config.interface, ++ pl->link_config.advertising); + +- neg_mode = pl->cur_link_an_mode; ++ neg_mode = pl->act_link_an_mode; + if (pl->pcs->neg_mode) + neg_mode = pl->pcs_neg_mode; + +@@ -1353,7 +1541,7 @@ static void phylink_mac_initial_config(s + { + struct phylink_link_state link_state; + +- switch (pl->cur_link_an_mode) { ++ switch (pl->req_link_an_mode) { + case MLO_AN_PHY: + link_state = pl->phy_state; + break; +@@ -1427,14 +1615,14 @@ static void phylink_link_up(struct phyli + + pl->cur_interface = link_state.interface; + +- neg_mode = pl->cur_link_an_mode; ++ neg_mode = pl->act_link_an_mode; + if (pl->pcs && pl->pcs->neg_mode) + neg_mode = pl->pcs_neg_mode; + + phylink_pcs_link_up(pl->pcs, neg_mode, pl->cur_interface, speed, + duplex); + +- pl->mac_ops->mac_link_up(pl->config, pl->phydev, pl->cur_link_an_mode, ++ pl->mac_ops->mac_link_up(pl->config, pl->phydev, pl->act_link_an_mode, + pl->cur_interface, speed, duplex, + !!(link_state.pause & MLO_PAUSE_TX), rx_pause); + +@@ -1454,7 +1642,7 @@ static void phylink_link_down(struct phy + + if (ndev) + netif_carrier_off(ndev); +- pl->mac_ops->mac_link_down(pl->config, pl->cur_link_an_mode, ++ pl->mac_ops->mac_link_down(pl->config, pl->act_link_an_mode, + pl->cur_interface); + phylink_info(pl, "Link is Down\n"); + } +@@ -1481,7 +1669,7 @@ static void phylink_resolve(struct work_ + link_state.link = false; + retrigger = true; + } else { +- switch (pl->cur_link_an_mode) { ++ switch (pl->act_link_an_mode) { + case MLO_AN_PHY: + link_state = pl->phy_state; + phylink_apply_manual_flow(pl, &link_state); +@@ -1671,7 +1859,7 @@ int phylink_set_fixed_link(struct phylin + pl->link_config.an_complete = 1; + + pl->cfg_link_an_mode = MLO_AN_FIXED; +- pl->cur_link_an_mode = pl->cfg_link_an_mode; ++ pl->req_link_an_mode = pl->cfg_link_an_mode; + + return 0; + } +@@ -1766,7 +1954,7 @@ struct phylink *phylink_create(struct ph + } + } + +- pl->cur_link_an_mode = pl->cfg_link_an_mode; ++ pl->req_link_an_mode = pl->cfg_link_an_mode; + + ret = phylink_register_sfp(pl, fwnode); + if (ret < 0) { +@@ -2242,7 +2430,7 @@ void phylink_start(struct phylink *pl) + ASSERT_RTNL(); + + phylink_info(pl, "configuring for %s/%s link mode\n", +- phylink_an_mode_str(pl->cur_link_an_mode), ++ phylink_an_mode_str(pl->req_link_an_mode), + phy_modes(pl->link_config.interface)); + + /* Always set the carrier off */ +@@ -2501,7 +2689,7 @@ int phylink_ethtool_ksettings_get(struct + + linkmode_copy(kset->link_modes.supported, pl->supported); + +- switch (pl->cur_link_an_mode) { ++ switch (pl->act_link_an_mode) { + case MLO_AN_FIXED: + /* We are using fixed settings. Report these as the + * current link settings - and note that these also +@@ -2532,6 +2720,26 @@ int phylink_ethtool_ksettings_get(struct + } + EXPORT_SYMBOL_GPL(phylink_ethtool_ksettings_get); + ++static bool phylink_validate_pcs_inband_autoneg(struct phylink *pl, ++ phy_interface_t interface, ++ unsigned long *adv) ++{ ++ unsigned int inband = phylink_inband_caps(pl, interface); ++ unsigned int mask; ++ ++ /* If the PCS doesn't implement inband support, be permissive. */ ++ if (!inband) ++ return true; ++ ++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, adv)) ++ mask = LINK_INBAND_ENABLE; ++ else ++ mask = LINK_INBAND_DISABLE; ++ ++ /* Check whether the PCS implements the required mode */ ++ return !!(inband & mask); ++} ++ + /** + * phylink_ethtool_ksettings_set() - set the link settings + * @pl: a pointer to a &struct phylink returned from phylink_create() +@@ -2593,7 +2801,7 @@ int phylink_ethtool_ksettings_set(struct + /* If we have a fixed link, refuse to change link parameters. + * If the link parameters match, accept them but do nothing. + */ +- if (pl->cur_link_an_mode == MLO_AN_FIXED) { ++ if (pl->req_link_an_mode == MLO_AN_FIXED) { + if (s->speed != pl->link_config.speed || + s->duplex != pl->link_config.duplex) + return -EINVAL; +@@ -2609,7 +2817,7 @@ int phylink_ethtool_ksettings_set(struct + * is our default case) but do not allow the advertisement to + * be changed. If the advertisement matches, simply return. + */ +- if (pl->cur_link_an_mode == MLO_AN_FIXED) { ++ if (pl->req_link_an_mode == MLO_AN_FIXED) { + if (!linkmode_equal(config.advertising, + pl->link_config.advertising)) + return -EINVAL; +@@ -2649,7 +2857,7 @@ int phylink_ethtool_ksettings_set(struct + linkmode_copy(support, pl->supported); + if (phylink_validate(pl, support, &config)) { + phylink_err(pl, "validation of %s/%s with support %*pb failed\n", +- phylink_an_mode_str(pl->cur_link_an_mode), ++ phylink_an_mode_str(pl->req_link_an_mode), + phy_modes(config.interface), + __ETHTOOL_LINK_MODE_MASK_NBITS, support); + return -EINVAL; +@@ -2667,6 +2875,13 @@ int phylink_ethtool_ksettings_set(struct + phylink_is_empty_linkmode(config.advertising)) + return -EINVAL; + ++ /* Validate the autonegotiation state. We don't have a PHY in this ++ * situation, so the PCS is the media-facing entity. ++ */ ++ if (!phylink_validate_pcs_inband_autoneg(pl, config.interface, ++ config.advertising)) ++ return -EINVAL; ++ + mutex_lock(&pl->state_mutex); + pl->link_config.speed = config.speed; + pl->link_config.duplex = config.duplex; +@@ -2749,7 +2964,7 @@ int phylink_ethtool_set_pauseparam(struc + + ASSERT_RTNL(); + +- if (pl->cur_link_an_mode == MLO_AN_FIXED) ++ if (pl->req_link_an_mode == MLO_AN_FIXED) + return -EOPNOTSUPP; + + if (!phylink_test(pl->supported, Pause) && +@@ -3013,7 +3228,7 @@ static int phylink_mii_read(struct phyli + struct phylink_link_state state; + int val = 0xffff; + +- switch (pl->cur_link_an_mode) { ++ switch (pl->act_link_an_mode) { + case MLO_AN_FIXED: + if (phy_id == 0) { + phylink_get_fixed_state(pl, &state); +@@ -3038,7 +3253,7 @@ static int phylink_mii_read(struct phyli + static int phylink_mii_write(struct phylink *pl, unsigned int phy_id, + unsigned int reg, unsigned int val) + { +- switch (pl->cur_link_an_mode) { ++ switch (pl->act_link_an_mode) { + case MLO_AN_FIXED: + break; + +@@ -3208,10 +3423,11 @@ static phy_interface_t phylink_choose_sf + return interface; + } + +-static void phylink_sfp_set_config(struct phylink *pl, u8 mode, ++static void phylink_sfp_set_config(struct phylink *pl, + unsigned long *supported, + struct phylink_link_state *state) + { ++ u8 mode = MLO_AN_INBAND; + bool changed = false; + + phylink_dbg(pl, "requesting link mode %s/%s with support %*pb\n", +@@ -3228,9 +3444,9 @@ static void phylink_sfp_set_config(struc + changed = true; + } + +- if (pl->cur_link_an_mode != mode || ++ if (pl->req_link_an_mode != mode || + pl->link_config.interface != state->interface) { +- pl->cur_link_an_mode = mode; ++ pl->req_link_an_mode = mode; + pl->link_config.interface = state->interface; + + changed = true; +@@ -3245,8 +3461,7 @@ static void phylink_sfp_set_config(struc + phylink_mac_initial_config(pl, false); + } + +-static int phylink_sfp_config_phy(struct phylink *pl, u8 mode, +- struct phy_device *phy) ++static int phylink_sfp_config_phy(struct phylink *pl, struct phy_device *phy) + { + __ETHTOOL_DECLARE_LINK_MODE_MASK(support1); + __ETHTOOL_DECLARE_LINK_MODE_MASK(support); +@@ -3285,8 +3500,7 @@ static int phylink_sfp_config_phy(struct + ret = phylink_validate(pl, support1, &config); + if (ret) { + phylink_err(pl, +- "validation of %s/%s with support %*pb failed: %pe\n", +- phylink_an_mode_str(mode), ++ "validation of %s with support %*pb failed: %pe\n", + phy_modes(config.interface), + __ETHTOOL_LINK_MODE_MASK_NBITS, support, + ERR_PTR(ret)); +@@ -3295,7 +3509,7 @@ static int phylink_sfp_config_phy(struct + + pl->link_port = pl->sfp_port; + +- phylink_sfp_set_config(pl, mode, support, &config); ++ phylink_sfp_set_config(pl, support, &config); + + return 0; + } +@@ -3351,6 +3565,12 @@ static int phylink_sfp_config_optical(st + phylink_dbg(pl, "optical SFP: chosen %s interface\n", + phy_modes(interface)); + ++ if (!phylink_validate_pcs_inband_autoneg(pl, interface, ++ config.advertising)) { ++ phylink_err(pl, "autoneg setting not compatible with PCS"); ++ return -EINVAL; ++ } ++ + config.interface = interface; + + /* Ignore errors if we're expecting a PHY to attach later */ +@@ -3364,7 +3584,7 @@ static int phylink_sfp_config_optical(st + + pl->link_port = pl->sfp_port; + +- phylink_sfp_set_config(pl, MLO_AN_INBAND, pl->sfp_support, &config); ++ phylink_sfp_set_config(pl, pl->sfp_support, &config); + + return 0; + } +@@ -3435,20 +3655,10 @@ static void phylink_sfp_link_up(void *up + phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_LINK); + } + +-/* The Broadcom BCM84881 in the Methode DM7052 is unable to provide a SGMII +- * or 802.3z control word, so inband will not work. +- */ +-static bool phylink_phy_no_inband(struct phy_device *phy) +-{ +- return phy->is_c45 && phy_id_compare(phy->c45_ids.device_ids[1], +- 0xae025150, 0xfffffff0); +-} +- + static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy) + { + struct phylink *pl = upstream; + phy_interface_t interface; +- u8 mode; + int ret; + + /* +@@ -3460,17 +3670,12 @@ static int phylink_sfp_connect_phy(void + */ + phy_support_asym_pause(phy); + +- if (phylink_phy_no_inband(phy)) +- mode = MLO_AN_PHY; +- else +- mode = MLO_AN_INBAND; +- + /* Set the PHY's host supported interfaces */ + phy_interface_and(phy->host_interfaces, phylink_sfp_interfaces, + pl->config->supported_interfaces); + + /* Do the initial configuration */ +- ret = phylink_sfp_config_phy(pl, mode, phy); ++ ret = phylink_sfp_config_phy(pl, phy); + if (ret < 0) + return ret; + +--- a/drivers/net/phy/phy.c ++++ b/drivers/net/phy/phy.c +@@ -1049,6 +1049,58 @@ static int phy_check_link_status(struct + } + + /** ++ * phy_inband_caps - query which in-band signalling modes are supported ++ * @phydev: a pointer to a &struct phy_device ++ * @interface: the interface mode for the PHY ++ * ++ * Returns zero if it is unknown what in-band signalling is supported by the ++ * PHY (e.g. because the PHY driver doesn't implement the method.) Otherwise, ++ * returns a bit mask of the LINK_INBAND_* values from ++ * &enum link_inband_signalling to describe which inband modes are supported ++ * by the PHY for this interface mode. ++ */ ++unsigned int phy_inband_caps(struct phy_device *phydev, ++ phy_interface_t interface) ++{ ++ if (phydev->drv && phydev->drv->inband_caps) ++ return phydev->drv->inband_caps(phydev, interface); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(phy_inband_caps); ++ ++/** ++ * phy_config_inband - configure the desired PHY in-band mode ++ * @phydev: the phy_device struct ++ * @modes: in-band modes to configure ++ * ++ * Description: disables, enables or enables-with-bypass in-band signalling ++ * between the PHY and host system. ++ * ++ * Returns: zero on success, or negative errno value. ++ */ ++int phy_config_inband(struct phy_device *phydev, unsigned int modes) ++{ ++ int err; ++ ++ if (!!(modes & LINK_INBAND_DISABLE) + ++ !!(modes & LINK_INBAND_ENABLE) + ++ !!(modes & LINK_INBAND_BYPASS) != 1) ++ return -EINVAL; ++ ++ mutex_lock(&phydev->lock); ++ if (!phydev->drv) ++ err = -EIO; ++ else if (!phydev->drv->config_inband) ++ err = -EOPNOTSUPP; ++ else ++ err = phydev->drv->config_inband(phydev, modes); ++ mutex_unlock(&phydev->lock); ++ ++ return err; ++} ++ ++/** + * _phy_start_aneg - start auto-negotiation for this PHY device + * @phydev: the phy_device struct + * +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -819,6 +819,24 @@ struct phy_tdr_config { + #define PHY_PAIR_ALL -1 + + /** ++ * enum link_inband_signalling - in-band signalling modes that are supported ++ * ++ * @LINK_INBAND_DISABLE: in-band signalling can be disabled ++ * @LINK_INBAND_ENABLE: in-band signalling can be enabled without bypass ++ * @LINK_INBAND_BYPASS: in-band signalling can be enabled with bypass ++ * ++ * The possible and required bits can only be used if the valid bit is set. ++ * If possible is clear, that means inband signalling can not be used. ++ * Required is only valid when possible is set, and means that inband ++ * signalling must be used. ++ */ ++enum link_inband_signalling { ++ LINK_INBAND_DISABLE = BIT(0), ++ LINK_INBAND_ENABLE = BIT(1), ++ LINK_INBAND_BYPASS = BIT(2), ++}; ++ ++/** + * struct phy_plca_cfg - Configuration of the PLCA (Physical Layer Collision + * Avoidance) Reconciliation Sublayer. + * +@@ -958,6 +976,19 @@ struct phy_driver { + int (*get_features)(struct phy_device *phydev); + + /** ++ * @inband_caps: query whether in-band is supported for the given PHY ++ * interface mode. Returns a bitmask of bits defined by enum ++ * link_inband_signalling. ++ */ ++ unsigned int (*inband_caps)(struct phy_device *phydev, ++ phy_interface_t interface); ++ ++ /** ++ * @config_inband: configure in-band mode for the PHY ++ */ ++ int (*config_inband)(struct phy_device *phydev, unsigned int modes); ++ ++ /** + * @get_rate_matching: Get the supported type of rate matching for a + * particular phy interface. This is used by phy consumers to determine + * whether to advertise lower-speed modes for that interface. It is +@@ -1842,6 +1873,9 @@ int phy_config_aneg(struct phy_device *p + int _phy_start_aneg(struct phy_device *phydev); + int phy_start_aneg(struct phy_device *phydev); + int phy_aneg_done(struct phy_device *phydev); ++unsigned int phy_inband_caps(struct phy_device *phydev, ++ phy_interface_t interface); ++int phy_config_inband(struct phy_device *phydev, unsigned int modes); + int phy_speed_down(struct phy_device *phydev, bool sync); + int phy_speed_up(struct phy_device *phydev); + bool phy_check_valid(int speed, int duplex, unsigned long *features); +--- a/drivers/net/phy/bcm84881.c ++++ b/drivers/net/phy/bcm84881.c +@@ -235,11 +235,21 @@ static int bcm84881_read_status(struct p + return genphy_c45_read_mdix(phydev); + } + ++/* The Broadcom BCM84881 in the Methode DM7052 is unable to provide a SGMII ++ * or 802.3z control word, so inband will not work. ++ */ ++static unsigned int bcm84881_inband_caps(struct phy_device *phydev, ++ phy_interface_t interface) ++{ ++ return LINK_INBAND_DISABLE; ++} ++ + static struct phy_driver bcm84881_drivers[] = { + { + .phy_id = 0xae025150, + .phy_id_mask = 0xfffffff0, + .name = "Broadcom BCM84881", ++ .inband_caps = bcm84881_inband_caps, + .config_init = bcm84881_config_init, + .probe = bcm84881_probe, + .get_features = bcm84881_get_features, +--- a/drivers/net/phy/marvell.c ++++ b/drivers/net/phy/marvell.c +@@ -716,6 +716,48 @@ static int marvell_config_aneg_fiber(str + return genphy_check_and_restart_aneg(phydev, changed); + } + ++static unsigned int m88e1111_inband_caps(struct phy_device *phydev, ++ phy_interface_t interface) ++{ ++ /* In 1000base-X and SGMII modes, the inband mode can be changed ++ * through the Fibre page BMCR ANENABLE bit. ++ */ ++ if (interface == PHY_INTERFACE_MODE_1000BASEX || ++ interface == PHY_INTERFACE_MODE_SGMII) ++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE | ++ LINK_INBAND_BYPASS; ++ ++ return 0; ++} ++ ++static int m88e1111_config_inband(struct phy_device *phydev, unsigned int modes) ++{ ++ u16 extsr, bmcr; ++ int err; ++ ++ if (phydev->interface != PHY_INTERFACE_MODE_1000BASEX && ++ phydev->interface != PHY_INTERFACE_MODE_SGMII) ++ return -EINVAL; ++ ++ if (modes == LINK_INBAND_BYPASS) ++ extsr = MII_M1111_HWCFG_SERIAL_AN_BYPASS; ++ else ++ extsr = 0; ++ ++ if (modes == LINK_INBAND_DISABLE) ++ bmcr = 0; ++ else ++ bmcr = BMCR_ANENABLE; ++ ++ err = phy_modify(phydev, MII_M1111_PHY_EXT_SR, ++ MII_M1111_HWCFG_SERIAL_AN_BYPASS, extsr); ++ if (err < 0) ++ return extsr; ++ ++ return phy_modify_paged(phydev, MII_MARVELL_FIBER_PAGE, MII_BMCR, ++ BMCR_ANENABLE, bmcr); ++} ++ + static int m88e1111_config_aneg(struct phy_device *phydev) + { + int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR); +@@ -3667,6 +3709,8 @@ static struct phy_driver marvell_drivers + .name = "Marvell 88E1112", + /* PHY_GBIT_FEATURES */ + .probe = marvell_probe, ++ .inband_caps = m88e1111_inband_caps, ++ .config_inband = m88e1111_config_inband, + .config_init = m88e1112_config_init, + .config_aneg = marvell_config_aneg, + .config_intr = marvell_config_intr, +@@ -3688,6 +3732,8 @@ static struct phy_driver marvell_drivers + /* PHY_GBIT_FEATURES */ + .flags = PHY_POLL_CABLE_TEST, + .probe = marvell_probe, ++ .inband_caps = m88e1111_inband_caps, ++ .config_inband = m88e1111_config_inband, + .config_init = m88e1111gbe_config_init, + .config_aneg = m88e1111_config_aneg, + .read_status = marvell_read_status, +@@ -3711,6 +3757,8 @@ static struct phy_driver marvell_drivers + .name = "Marvell 88E1111 (Finisar)", + /* PHY_GBIT_FEATURES */ + .probe = marvell_probe, ++ .inband_caps = m88e1111_inband_caps, ++ .config_inband = m88e1111_config_inband, + .config_init = m88e1111gbe_config_init, + .config_aneg = m88e1111_config_aneg, + .read_status = marvell_read_status, +--- a/include/linux/phylink.h ++++ b/include/linux/phylink.h +@@ -419,6 +419,7 @@ struct phylink_pcs { + /** + * struct phylink_pcs_ops - MAC PCS operations structure. + * @pcs_validate: validate the link configuration. ++ * @pcs_inband_caps: query inband support for interface mode. + * @pcs_enable: enable the PCS. + * @pcs_disable: disable the PCS. + * @pcs_pre_config: pre-mac_config method (for errata) +@@ -434,6 +435,8 @@ struct phylink_pcs { + struct phylink_pcs_ops { + int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported, + const struct phylink_link_state *state); ++ unsigned int (*pcs_inband_caps)(struct phylink_pcs *pcs, ++ phy_interface_t interface); + int (*pcs_enable)(struct phylink_pcs *pcs); + void (*pcs_disable)(struct phylink_pcs *pcs); + void (*pcs_pre_config)(struct phylink_pcs *pcs, +@@ -471,6 +474,20 @@ int pcs_validate(struct phylink_pcs *pcs + const struct phylink_link_state *state); + + /** ++ * pcs_inband_caps - query PCS in-band capabilities for interface mode. ++ * @pcs: a pointer to a &struct phylink_pcs. ++ * @interface: interface mode to be queried ++ * ++ * Returns zero if it is unknown what in-band signalling is supported by the ++ * PHY (e.g. because the PHY driver doesn't implement the method.) Otherwise, ++ * returns a bit mask of the LINK_INBAND_* values from ++ * &enum link_inband_signalling to describe which inband modes are supported ++ * for this interface mode. ++ */ ++unsigned int pcs_inband_caps(struct phylink_pcs *pcs, ++ phy_interface_t interface); ++ ++/** + * pcs_enable() - enable the PCS. + * @pcs: a pointer to a &struct phylink_pcs. + */ +--- a/drivers/net/ethernet/marvell/mvneta.c ++++ b/drivers/net/ethernet/marvell/mvneta.c +@@ -3960,20 +3960,27 @@ static struct mvneta_port *mvneta_pcs_to + return container_of(pcs, struct mvneta_port, phylink_pcs); + } + +-static int mvneta_pcs_validate(struct phylink_pcs *pcs, +- unsigned long *supported, +- const struct phylink_link_state *state) ++static unsigned int mvneta_pcs_inband_caps(struct phylink_pcs *pcs, ++ phy_interface_t interface) + { +- /* We only support QSGMII, SGMII, 802.3z and RGMII modes. +- * When in 802.3z mode, we must have AN enabled: ++ /* When operating in an 802.3z mode, we must have AN enabled: + * "Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ... + * When = 1 (1000BASE-X) this field must be set to 1." ++ * Therefore, inband is "required". + */ +- if (phy_interface_mode_is_8023z(state->interface) && +- !phylink_test(state->advertising, Autoneg)) +- return -EINVAL; ++ if (phy_interface_mode_is_8023z(interface)) ++ return LINK_INBAND_ENABLE; + +- return 0; ++ /* QSGMII, SGMII and RGMII can be configured to use inband ++ * signalling of the AN result. Indicate these as "possible". ++ */ ++ if (interface == PHY_INTERFACE_MODE_SGMII || ++ interface == PHY_INTERFACE_MODE_QSGMII || ++ phy_interface_mode_is_rgmii(interface)) ++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; ++ ++ /* For any other modes, indicate that inband is not supported. */ ++ return LINK_INBAND_DISABLE; + } + + static void mvneta_pcs_get_state(struct phylink_pcs *pcs, +@@ -4071,7 +4078,7 @@ static void mvneta_pcs_an_restart(struct + } + + static const struct phylink_pcs_ops mvneta_phylink_pcs_ops = { +- .pcs_validate = mvneta_pcs_validate, ++ .pcs_inband_caps = mvneta_pcs_inband_caps, + .pcs_get_state = mvneta_pcs_get_state, + .pcs_config = mvneta_pcs_config, + .pcs_an_restart = mvneta_pcs_an_restart, +--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +@@ -6237,19 +6237,26 @@ static const struct phylink_pcs_ops mvpp + .pcs_config = mvpp2_xlg_pcs_config, + }; + +-static int mvpp2_gmac_pcs_validate(struct phylink_pcs *pcs, +- unsigned long *supported, +- const struct phylink_link_state *state) ++static unsigned int mvpp2_gmac_pcs_inband_caps(struct phylink_pcs *pcs, ++ phy_interface_t interface) + { +- /* When in 802.3z mode, we must have AN enabled: ++ /* When operating in an 802.3z mode, we must have AN enabled: + * Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ... + * When = 1 (1000BASE-X) this field must be set to 1. ++ * Therefore, inband is "required". + */ +- if (phy_interface_mode_is_8023z(state->interface) && +- !phylink_test(state->advertising, Autoneg)) +- return -EINVAL; ++ if (phy_interface_mode_is_8023z(interface)) ++ return LINK_INBAND_ENABLE; + +- return 0; ++ /* SGMII and RGMII can be configured to use inband signalling of the ++ * AN result. Indicate these as "possible". ++ */ ++ if (interface == PHY_INTERFACE_MODE_SGMII || ++ phy_interface_mode_is_rgmii(interface)) ++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; ++ ++ /* For any other modes, indicate that inband is not supported. */ ++ return LINK_INBAND_DISABLE; + } + + static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs, +@@ -6356,7 +6363,7 @@ static void mvpp2_gmac_pcs_an_restart(st + } + + static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = { +- .pcs_validate = mvpp2_gmac_pcs_validate, ++ .pcs_inband_caps = mvpp2_gmac_pcs_inband_caps, + .pcs_get_state = mvpp2_gmac_pcs_get_state, + .pcs_config = mvpp2_gmac_pcs_config, + .pcs_an_restart = mvpp2_gmac_pcs_an_restart, +--- a/drivers/net/pcs/pcs-lynx.c ++++ b/drivers/net/pcs/pcs-lynx.c +@@ -35,6 +35,27 @@ enum sgmii_speed { + #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs) + #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs) + ++static unsigned int lynx_pcs_inband_caps(struct phylink_pcs *pcs, ++ phy_interface_t interface) ++{ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_1000BASEX: ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_QSGMII: ++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; ++ ++ case PHY_INTERFACE_MODE_10GBASER: ++ case PHY_INTERFACE_MODE_2500BASEX: ++ return LINK_INBAND_DISABLE; ++ ++ case PHY_INTERFACE_MODE_USXGMII: ++ return LINK_INBAND_ENABLE; ++ ++ default: ++ return 0; ++ } ++} ++ + static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs, + struct phylink_link_state *state) + { +@@ -306,6 +327,7 @@ static void lynx_pcs_link_up(struct phyl + } + + static const struct phylink_pcs_ops lynx_pcs_phylink_ops = { ++ .pcs_inband_caps = lynx_pcs_inband_caps, + .pcs_get_state = lynx_pcs_get_state, + .pcs_config = lynx_pcs_config, + .pcs_an_restart = lynx_pcs_an_restart, +--- a/drivers/net/pcs/pcs-mtk-lynxi.c ++++ b/drivers/net/pcs/pcs-mtk-lynxi.c +@@ -110,6 +110,21 @@ static struct mtk_pcs_lynxi *pcs_to_mtk_ + return container_of(pcs, struct mtk_pcs_lynxi, pcs); + } + ++static unsigned int mtk_pcs_lynxi_inband_caps(struct phylink_pcs *pcs, ++ phy_interface_t interface) ++{ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_1000BASEX: ++ case PHY_INTERFACE_MODE_2500BASEX: ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_QSGMII: ++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; ++ ++ default: ++ return 0; ++ } ++} ++ + static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs, + struct phylink_link_state *state) + { +@@ -302,6 +317,7 @@ static void mtk_pcs_lynxi_disable(struct + } + + static const struct phylink_pcs_ops mtk_pcs_lynxi_ops = { ++ .pcs_inband_caps = mtk_pcs_lynxi_inband_caps, + .pcs_get_state = mtk_pcs_lynxi_get_state, + .pcs_config = mtk_pcs_lynxi_config, + .pcs_an_restart = mtk_pcs_lynxi_restart_an, +--- a/drivers/net/pcs/pcs-xpcs.c ++++ b/drivers/net/pcs/pcs-xpcs.c +@@ -608,6 +608,33 @@ static int xpcs_validate(struct phylink_ + return 0; + } + ++static unsigned int xpcs_inband_caps(struct phylink_pcs *pcs, ++ phy_interface_t interface) ++{ ++ struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); ++ const struct dw_xpcs_compat *compat; ++ ++ compat = xpcs_find_compat(xpcs, interface); ++ if (!compat) ++ return 0; ++ ++ switch (compat->an_mode) { ++ case DW_AN_C73: ++ return LINK_INBAND_ENABLE; ++ ++ case DW_AN_C37_SGMII: ++ case DW_AN_C37_1000BASEX: ++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; ++ ++ case DW_10GBASER: ++ case DW_2500BASEX: ++ return LINK_INBAND_DISABLE; ++ ++ default: ++ return 0; ++ } ++} ++ + void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces) + { + int i, j; +@@ -1365,6 +1392,7 @@ static const struct dw_xpcs_desc xpcs_de + + static const struct phylink_pcs_ops xpcs_phylink_ops = { + .pcs_validate = xpcs_validate, ++ .pcs_inband_caps = xpcs_inband_caps, + .pcs_config = xpcs_config, + .pcs_get_state = xpcs_get_state, + .pcs_an_restart = xpcs_an_restart, diff --git a/target/linux/mediatek/patches-6.12/862-arm64-dts-mt7986-add-afe.patch b/target/linux/mediatek/patches-6.12/862-arm64-dts-mt7986-add-afe.patch new file mode 100644 index 0000000000..1b768f652c --- /dev/null +++ b/target/linux/mediatek/patches-6.12/862-arm64-dts-mt7986-add-afe.patch @@ -0,0 +1,41 @@ +From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Thu, 7 Sep 2023 10:54:37 +0800 +Subject: [PATCH] arm64: dts: mt7986: add afe + +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 23 +++++++++++ + 1 files changed, 23 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -202,6 +202,29 @@ + #interrupt-cells = <2>; + }; + ++ afe: audio-controller@11210000 { ++ compatible = "mediatek,mt7986-afe"; ++ reg = <0 0x11210000 0 0x9000>; ++ #sound-dai-cells = <0>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, ++ <&infracfg CLK_INFRA_AUD_26M_CK>, ++ <&infracfg CLK_INFRA_AUD_L_CK>, ++ <&infracfg CLK_INFRA_AUD_AUD_CK>, ++ <&infracfg CLK_INFRA_AUD_EG2_CK>; ++ clock-names = "aud_bus_ck", ++ "aud_26m_ck", ++ "aud_l_ck", ++ "aud_aud_ck", ++ "aud_eg2_ck"; ++ assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>, ++ <&topckgen CLK_TOP_AUD_L_SEL>, ++ <&topckgen CLK_TOP_A_TUNER_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>, ++ <&apmixedsys CLK_APMIXED_APLL2>, ++ <&topckgen CLK_TOP_APLL2_D4>; ++ }; ++ + pwm: pwm@10048000 { + compatible = "mediatek,mt7986-pwm"; + reg = <0 0x10048000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/863-arm64-dts-mt7986-add-sound-wm8960.patch b/target/linux/mediatek/patches-6.12/863-arm64-dts-mt7986-add-sound-wm8960.patch new file mode 100644 index 0000000000..b16a63ada9 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/863-arm64-dts-mt7986-add-sound-wm8960.patch @@ -0,0 +1,62 @@ +From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Thu, 7 Sep 2023 10:54:37 +0800 +Subject: [PATCH] arm64: dts: mt7986: add sound wm8960 + +--- + .../dts/mediatek/mt7986a-rfb-spim-nand.dts | 39 +++++++++++++++++++ + 1 files changed, 39 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts +@@ -4,6 +4,36 @@ + + / { + compatible = "mediatek,mt7986a-rfb-snand"; ++ ++ sound_wm8960 { ++ compatible = "mediatek,mt7986-wm8960-sound"; ++ audio-routing = "Headphone", "HP_L", ++ "Headphone", "HP_R", ++ "LINPUT1", "AMIC", ++ "RINPUT1", "AMIC"; ++ ++ status = "okay"; ++ ++ platform { ++ sound-dai = <&afe>; ++ }; ++ ++ codec { ++ sound-dai = <&wm8960>; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c_pins>; ++ status = "okay"; ++ ++ wm8960: wm8960@1a { ++ compatible = "wlf,wm8960"; ++ #sound-dai-cells = <0>; ++ reg = <0x1a>; ++ }; + }; + + &spi0 { +@@ -50,3 +80,13 @@ + &wifi { + mediatek,mtd-eeprom = <&factory 0>; + }; ++ ++&pio { ++ i2c_pins: i2c-pins-3-4 { ++ mux { ++ function = "i2c"; ++ groups = "i2c"; ++ }; ++ }; ++}; ++ diff --git a/target/linux/mediatek/patches-6.12/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch b/target/linux/mediatek/patches-6.12/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch new file mode 100644 index 0000000000..af47255c78 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch @@ -0,0 +1,78 @@ +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-respeaker-2mics.dtso +@@ -0,0 +1,65 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 MediaTek Inc. ++ * Author: Maso Huang ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ sound_wm8960 { ++ compatible = "mediatek,mt7986-wm8960-sound"; ++ audio-routing = "Headphone", "HP_L", ++ "Headphone", "HP_R", ++ "LINPUT1", "AMIC", ++ "RINPUT1", "AMIC"; ++ ++ status = "okay"; ++ ++ platform { ++ sound-dai = <&afe>; ++ }; ++ ++ codec { ++ sound-dai = <&wm8960>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c_pins>; ++ clock-frequency = <400000>; ++ status = "okay"; ++ ++ wm8960: wm8960@1a { ++ compatible = "wlf,wm8960"; ++ #sound-dai-cells = <0>; ++ reg = <0x1a>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&pio>; ++ __overlay__ { ++ i2c_pins: i2c-pins-3-4 { ++ mux { ++ function = "i2c"; ++ groups = "i2c"; ++ }; ++ }; ++ }; ++ }; ++}; +--- a/arch/arm64/boot/dts/mediatek/Makefile ++++ b/arch/arm64/boot/dts/mediatek/Makefile +@@ -18,6 +18,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-respeaker-2mics.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb diff --git a/target/linux/mediatek/patches-6.12/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-6.12/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch new file mode 100644 index 0000000000..5bf729f5b9 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch @@ -0,0 +1,65 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -323,7 +323,7 @@ + /* Attention: GPIO 90 is used to switch between PCIe@1,0 and + * SATA functions. i.e. output-high: PCIe, output-low: SATA + */ +- asm_sel { ++ asmsel: asm_sel { + gpio-hog; + gpios = <90 GPIO_ACTIVE_HIGH>; + output-high; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso +@@ -0,0 +1,31 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ ++ ++#include ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; ++ ++ fragment@0 { ++ target = <&asmsel>; ++ __overlay__ { ++ gpios = <90 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&sata>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&sata_phy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ ++ ++#include ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; ++ ++ fragment@0 { ++ target = <&asmsel>; ++ __overlay__ { ++ gpios = <90 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; diff --git a/target/linux/mediatek/patches-6.12/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-6.12/901-arm-add-cmdline-override.patch new file mode 100644 index 0000000000..001c7bf2f0 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/901-arm-add-cmdline-override.patch @@ -0,0 +1,54 @@ +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1505,6 +1505,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN + + endchoice + ++config CMDLINE_OVERRIDE ++ bool "Use alternative cmdline from device tree" ++ help ++ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can ++ be used, this is not a good option for kernels that are shared across ++ devices. This setting enables using "chosen/cmdline-override" as the ++ cmdline if it exists in the device tree. ++ + config CMDLINE + string "Default kernel command string" + default "" +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -1053,6 +1053,17 @@ int __init early_init_dt_scan_chosen(cha + if (p != NULL && l > 0) + strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE)); + ++ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different ++ * device tree option of chosen/bootargs-override. This is ++ * helpful on boards where u-boot sets bootargs, and is unable ++ * to be modified. ++ */ ++#ifdef CONFIG_CMDLINE_OVERRIDE ++ p = of_get_flat_dt_prop(node, "bootargs-override", &l); ++ if (p != NULL && l > 0) ++ strscpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE)); ++#endif ++ + handle_cmdline: + /* + * CONFIG_CMDLINE is meant to be a default in case nothing else +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -2380,6 +2380,14 @@ config CMDLINE_FORCE + + endchoice + ++config CMDLINE_OVERRIDE ++ bool "Use alternative cmdline from device tree" ++ help ++ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can ++ be used, this is not a good option for kernels that are shared across ++ devices. This setting enables using "chosen/cmdline-override" as the ++ cmdline if it exists in the device tree. ++ + config EFI_STUB + bool + diff --git a/target/linux/mediatek/patches-6.12/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-6.12/910-dts-mt7622-bpi-r64-wifi-eeprom.patch new file mode 100644 index 0000000000..e6cb16c3d6 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/910-dts-mt7622-bpi-r64-wifi-eeprom.patch @@ -0,0 +1,31 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -650,5 +650,28 @@ + }; + + &wmac { ++ mediatek,eeprom-data = <0x22760500 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x44000020 0x0 0x10002000 ++ 0x4400 0x4000000 0x0 0x0 ++ 0x200000b3 0x40b6c3c3 0x26000000 0x41c42600 ++ 0x41c4 0x26000000 0xc0c52600 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0xc6c6 ++ 0xc3c3c2c1 0xc300c3 0x818181 0x83c1c182 ++ 0x83838382 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x84002e00 0x90000087 0x8a000000 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0xb000009 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x0 ++ 0x0 0x0 0x0 0x7707>; ++ + status = "okay"; + }; diff --git a/target/linux/mediatek/patches-6.12/911-dts-mt7622-bpi-r64-add-rootdisk.patch b/target/linux/mediatek/patches-6.12/911-dts-mt7622-bpi-r64-add-rootdisk.patch new file mode 100644 index 0000000000..28c26db0ed --- /dev/null +++ b/target/linux/mediatek/patches-6.12/911-dts-mt7622-bpi-r64-add-rootdisk.patch @@ -0,0 +1,109 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -32,6 +32,9 @@ + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; ++ rootdisk-emmc = <&emmc_rootfs>; ++ rootdisk-sd = <&sd_rootfs>; ++ rootdisk-snfi = <&ubi_rootfs>; + }; + + cpus { +@@ -245,6 +248,28 @@ + assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; + non-removable; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ block { ++ compatible = "block-device"; ++ partitions { ++ block-partition-env { ++ partname = "ubootenv"; ++ nvmem-layout { ++ compatible = "u-boot,env"; ++ }; ++ }; ++ emmc_rootfs: block-partition-production { ++ partname = "production"; ++ }; ++ }; ++ }; ++ }; + }; + + &mmc1 { +@@ -260,6 +285,28 @@ + vqmmc-supply = <®_3p3v>; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ block { ++ compatible = "block-device"; ++ partitions { ++ block-partition-env { ++ partname = "ubootenv"; ++ nvmem-layout { ++ compatible = "u-boot,env"; ++ }; ++ }; ++ sd_rootfs: block-partition-production { ++ partname = "production"; ++ }; ++ }; ++ }; ++ }; + }; + + &nandc { +@@ -293,15 +340,30 @@ + read-only; + }; + +- partition@80000 { +- label = "fip"; +- reg = <0x80000 0x200000>; +- read-only; +- }; +- +- ubi: partition@280000 { ++ ubi: partition@80000 { + label = "ubi"; +- reg = <0x280000 0x7d80000>; ++ reg = <0x80000 0x7f80000>; ++ compatible = "linux,ubi"; ++ ++ volumes { ++ ubi-volume-ubootenv { ++ volname = "ubootenv"; ++ nvmem-layout { ++ compatible = "u-boot,env-redundant-bool"; ++ }; ++ }; ++ ++ ubi-volume-ubootenv2 { ++ volname = "ubootenv2"; ++ nvmem-layout { ++ compatible = "u-boot,env-redundant-bool"; ++ }; ++ }; ++ ++ ubi_rootfs: ubi-volume-fit { ++ volname = "fit"; ++ }; ++ }; + }; + }; + }; diff --git a/target/linux/mediatek/patches-6.12/920-block-partitions-msdos-add-OF-node-by-partition-numb.patch b/target/linux/mediatek/patches-6.12/920-block-partitions-msdos-add-OF-node-by-partition-numb.patch new file mode 100644 index 0000000000..f2c3aa4276 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/920-block-partitions-msdos-add-OF-node-by-partition-numb.patch @@ -0,0 +1,98 @@ +From 391630263f08dc853b111c6c3325a0ec510fe5fb Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 9 May 2025 02:38:51 +0100 +Subject: [PATCH] block: partitions: msdos: add OF node by partition number + +A hack for some legacy boards... + +Signed-off-by: Daniel Golle +--- + block/partitions/msdos.c | 66 +++++++++++++++++++++++++++++++++------- + 1 file changed, 55 insertions(+), 11 deletions(-) + +--- a/block/partitions/msdos.c ++++ b/block/partitions/msdos.c +@@ -27,6 +27,7 @@ + */ + #include + #include ++#include + + #include "check.h" + #include "efi.h" +@@ -116,6 +117,26 @@ static void set_info(struct parsed_parti + state->parts[slot].has_info = true; + } + ++static struct device_node *find_partno_of_node(struct device_node *partitions_np, ++ int partno) ++{ ++ int np_partno; ++ ++ if (!partitions_np || ++ !of_device_is_compatible(partitions_np, "msdos-partitions")) ++ return NULL; ++ ++ for_each_available_child_of_node_scoped(partitions_np, np) { ++ if (!of_property_read_u32(np, "partno", &np_partno) && ++ partno != np_partno) ++ continue; ++ ++ return np; ++ } ++ ++ return NULL; ++} ++ + /* + * Create devices for each logical partition in an extended partition. + * The logical partitions form a linked list, with each entry being +@@ -131,6 +152,8 @@ static void parse_extended(struct parsed + sector_t first_sector, sector_t first_size, + u32 disksig) + { ++ struct device *ddev = disk_to_dev(state->disk); ++ struct device_node *partitions_np = of_node_get(ddev->of_node); + struct msdos_partition *p; + Sector sect; + unsigned char *data; +@@ -190,7 +213,8 @@ static void parse_extended(struct parsed + continue; + } + +- put_partition(state, state->next, next, size); ++ of_put_partition(state, state->next, next, size, ++ find_partno_of_node(partitions_np, state->next)); + set_info(state, state->next, disksig); + if (p->sys_ind == LINUX_RAID_PARTITION) + state->parts[state->next].flags = ADDPART_FLAG_RAID; +@@ -580,6 +604,8 @@ static struct { + + int msdos_partition(struct parsed_partitions *state) + { ++ struct device *ddev = disk_to_dev(state->disk); ++ struct device_node *partitions_np = of_node_get(ddev->of_node); + sector_t sector_size; + Sector sect; + unsigned char *data; +@@ -676,14 +702,18 @@ int msdos_partition(struct parsed_partit + sector_t n = 2; + + n = min(size, max(sector_size, n)); +- put_partition(state, slot, start, n); ++ of_put_partition(state, slot, start, n, ++ find_partno_of_node(partitions_np, ++ slot)); + + strlcat(state->pp_buf, " <", PAGE_SIZE); + parse_extended(state, start, size, disksig); + strlcat(state->pp_buf, " >", PAGE_SIZE); + continue; + } +- put_partition(state, slot, start, size); ++ of_put_partition(state, slot, start, size, ++ find_partno_of_node(partitions_np, ++ slot)); + set_info(state, slot, disksig); + if (p->sys_ind == LINUX_RAID_PARTITION) + state->parts[slot].flags = ADDPART_FLAG_RAID; diff --git a/target/linux/mediatek/patches-6.12/930-spi-mt65xx-enable-sel-clk.patch b/target/linux/mediatek/patches-6.12/930-spi-mt65xx-enable-sel-clk.patch new file mode 100644 index 0000000000..52942c2069 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/930-spi-mt65xx-enable-sel-clk.patch @@ -0,0 +1,18 @@ +--- a/drivers/spi/spi-mt65xx.c ++++ b/drivers/spi/spi-mt65xx.c +@@ -1237,8 +1237,15 @@ static int mtk_spi_probe(struct platform + if (ret < 0) + return dev_err_probe(dev, ret, "failed to enable hclk\n"); + ++ ret = clk_prepare_enable(mdata->sel_clk); ++ if (ret < 0) { ++ clk_disable_unprepare(mdata->spi_hclk); ++ return dev_err_probe(dev, ret, "failed to enable sel_clk\n"); ++ } ++ + ret = clk_prepare_enable(mdata->spi_clk); + if (ret < 0) { ++ clk_disable_unprepare(mdata->sel_clk); + clk_disable_unprepare(mdata->spi_hclk); + return dev_err_probe(dev, ret, "failed to enable spi_clk\n"); + } diff --git a/target/linux/mediatek/patches-6.12/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch b/target/linux/mediatek/patches-6.12/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch new file mode 100644 index 0000000000..465f0eaf27 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch @@ -0,0 +1,37 @@ +From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001 +Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> +From: Lorenzo Bianconi +Date: Sun, 12 Mar 2023 16:40:31 +0100 +Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename + mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region + +This is a preliminary patch to move wed ilm/dlm and cpuboot properties in +dedicated dts nodes. + +Signed-off-by: Lorenzo Bianconi +--- + drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c +@@ -234,8 +234,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we + } + + static int +-mtk_wed_get_memory_region(struct mtk_wed_hw *hw, int index, +- struct mtk_wed_wo_memory_region *region) ++mtk_wed_get_reserved_memory_region(struct mtk_wed_hw *hw, int index, ++ struct mtk_wed_wo_memory_region *region) + { + struct reserved_mem *rmem; + struct device_node *np; +@@ -325,7 +325,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed + if (index < 0) + continue; + +- ret = mtk_wed_get_memory_region(wo->hw, index, &mem_region[i]); ++ ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]); + if (ret) + return ret; + } diff --git a/target/linux/mediatek/patches-6.12/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.12/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch new file mode 100644 index 0000000000..a75a297e04 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch @@ -0,0 +1,66 @@ +From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001 +Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org> +From: Lorenzo Bianconi +Date: Sat, 11 Mar 2023 16:32:41 +0100 +Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node + +Signed-off-by: Lorenzo Bianconi +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++---------- + 1 file changed, 11 insertions(+), 10 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -121,12 +121,6 @@ + reg = <0 0x151f8000 0 0x2000>; + no-map; + }; +- +- wo_boot: wo-boot@15194000 { +- reg = <0 0x15194000 0 0x1000>; +- no-map; +- }; +- + }; + + soc { +@@ -533,10 +527,11 @@ + interrupt-parent = <&gic>; + interrupts = ; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, +- <&wo_data>, <&wo_boot>; ++ <&wo_data>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", +- "wo-data", "wo-boot"; ++ "wo-data"; + mediatek,wo-ccif = <&wo_ccif0>; ++ mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + + wed1: wed@15011000 { +@@ -546,10 +541,11 @@ + interrupt-parent = <&gic>; + interrupts = ; + memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, +- <&wo_data>, <&wo_boot>; ++ <&wo_data>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", +- "wo-data", "wo-boot"; ++ "wo-data"; + mediatek,wo-ccif = <&wo_ccif1>; ++ mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + + eth: ethernet@15100000 { +@@ -607,6 +603,11 @@ + interrupts = ; + }; + ++ wo_cpuboot: syscon@15194000 { ++ compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; ++ reg = <0 0x15194000 0 0x1000>; ++ }; ++ + wifi: wifi@18000000 { + compatible = "mediatek,mt7986-wmac"; + reg = <0 0x18000000 0 0x1000000>, diff --git a/target/linux/mediatek/patches-6.12/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch b/target/linux/mediatek/patches-6.12/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch new file mode 100644 index 0000000000..43014c5d12 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch @@ -0,0 +1,103 @@ +From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> +References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> +From: Lorenzo Bianconi +Date: Sat, 11 Mar 2023 18:13:04 +0100 +Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a + dedicated dts node + +Since the cpuboot memory region is not part of the RAM SoC, move cpuboot +in a deidicated syscon node. +This patch helps to keep backward-compatibility with older version of +uboot codebase where we have a limit of 8 reserved-memory dts child +nodes. +Keep backward-compatibility with older dts version where cpuboot was +defined as reserved-memory child node. + +Signed-off-by: Lorenzo Bianconi +--- + drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++---- + drivers/net/ethernet/mediatek/mtk_wed_wo.h | 3 +- + 2 files changed, 30 insertions(+), 7 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c +@@ -32,14 +32,25 @@ static struct mtk_wed_wo_memory_region m + }, + }; + +-static u32 wo_r32(u32 reg) ++static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg) + { +- return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg); ++ u32 val; ++ ++ if (!wo->boot_regmap) ++ return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg); ++ ++ if (regmap_read(wo->boot_regmap, reg, &val)) ++ val = ~0; ++ ++ return val; + } + +-static void wo_w32(u32 reg, u32 val) ++static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val) + { +- writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg); ++ if (wo->boot_regmap) ++ regmap_write(wo->boot_regmap, reg, val); ++ else ++ writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg); + } + + static struct sk_buff * +@@ -317,6 +328,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed + u32 val, boot_cr; + int ret, i; + ++ wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, ++ "mediatek,wo-cpuboot"); ++ + /* load firmware region metadata */ + for (i = 0; i < ARRAY_SIZE(mem_region); i++) { + int index = of_property_match_string(wo->hw->node, +@@ -325,6 +339,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed + if (index < 0) + continue; + ++ if (index == MTK_WED_WO_REGION_BOOT && !IS_ERR(wo->boot_regmap)) ++ continue; ++ + ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]); + if (ret) + return ret; +@@ -373,13 +390,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed + boot_cr = MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR; + else + boot_cr = MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR; +- wo_w32(boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16); ++ wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16); + /* wo firmware reset */ +- wo_w32(MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00); ++ wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00); + +- val = wo_r32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) | ++ val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) | + MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK; +- wo_w32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val); ++ wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val); + out: + release_firmware(fw); + +--- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h ++++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h +@@ -231,6 +231,7 @@ struct mtk_wed_wo_queue { + struct mtk_wed_wo { + struct mtk_wed_hw *hw; + ++ struct regmap *boot_regmap; + struct mtk_wed_wo_queue q_tx; + struct mtk_wed_wo_queue q_rx; + diff --git a/target/linux/mediatek/patches-6.12/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.12/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch new file mode 100644 index 0000000000..641c2597f7 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch @@ -0,0 +1,86 @@ +From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001 +Message-Id: +From: Lorenzo Bianconi +Date: Sun, 12 Mar 2023 18:51:47 +0100 +Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts + node + +Since the ilm memory region is not part of the RAM SoC, move ilm in a +deidicated syscon node. +This patch helps to keep backward-compatibility with older version of +uboot codebase where we have a limit of 8 reserved-memory dts child +nodes. +Keep backward-compatibility with older dts version where ilm was defined +as reserved-memory child node. + +Signed-off-by: Lorenzo Bianconi +--- + drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++--- + 1 file changed, 49 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c +@@ -320,6 +320,39 @@ next: + } + + static int ++mtk_wed_mcu_load_ilm(struct mtk_wed_wo *wo) ++{ ++ struct mtk_wed_wo_memory_region *ilm_region; ++ struct resource res; ++ struct device_node *np; ++ int ret; ++ ++ np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0); ++ if (!np) ++ return 0; ++ ++ ret = of_address_to_resource(np, 0, &res); ++ of_node_put(np); ++ ++ if (ret < 0) ++ return ret; ++ ++ ilm_region = &mem_region[MTK_WED_WO_REGION_ILM]; ++ ilm_region->phy_addr = res.start; ++ ilm_region->size = resource_size(&res); ++ ilm_region->addr = devm_ioremap(wo->hw->dev, res.start, ++ resource_size(&res)); ++ ++ if (!IS_ERR(ilm_region->addr)) ++ return 0; ++ ++ ret = PTR_ERR(ilm_region->addr); ++ ilm_region->addr = NULL; ++ ++ return ret; ++} ++ ++static int + mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo) + { + const struct mtk_wed_fw_trailer *trailer; +@@ -328,14 +361,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed + u32 val, boot_cr; + int ret, i; + ++ mtk_wed_mcu_load_ilm(wo); + wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, + "mediatek,wo-cpuboot"); + + /* load firmware region metadata */ + for (i = 0; i < ARRAY_SIZE(mem_region); i++) { +- int index = of_property_match_string(wo->hw->node, +- "memory-region-names", +- mem_region[i].name); ++ int index; ++ ++ if (mem_region[i].addr) ++ continue; ++ ++ index = of_property_match_string(wo->hw->node, ++ "memory-region-names", ++ mem_region[i].name); + if (index < 0) + continue; + diff --git a/target/linux/mediatek/patches-6.12/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.12/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch new file mode 100644 index 0000000000..abb6591b7d --- /dev/null +++ b/target/linux/mediatek/patches-6.12/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch @@ -0,0 +1,57 @@ +From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: +References: +From: Lorenzo Bianconi +Date: Mon, 13 Mar 2023 15:45:16 +0100 +Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts + node + +Since the dlm memory region is not part of the RAM SoC, move dlm in a +deidicated syscon node. +This patch helps to keep backward-compatibility with older version of +uboot codebase where we have a limit of 8 reserved-memory dts child +nodes. +Keep backward-compatibility with older dts version where dlm was defined +as reserved-memory child node. + +Signed-off-by: Lorenzo Bianconi +--- + drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/drivers/net/ethernet/mediatek/mtk_wed.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed.c +@@ -1322,6 +1322,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device + struct device_node *np; + int index; + ++ np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0); ++ if (np) { ++ struct resource res; ++ int ret; ++ ++ ret = of_address_to_resource(np, 0, &res); ++ of_node_put(np); ++ ++ if (ret < 0) ++ return ret; ++ ++ dev->rro.miod_phys = res.start; ++ goto out; ++ } ++ ++ /* For backward compatibility, we need to check if DLM ++ * node is defined through reserved memory property. ++ */ + index = of_property_match_string(dev->hw->node, "memory-region-names", + "wo-dlm"); + if (index < 0) +@@ -1338,6 +1356,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device + return -ENODEV; + + dev->rro.miod_phys = rmem->base; ++out: + dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys; + + return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring, diff --git a/target/linux/mediatek/patches-6.12/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.12/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch new file mode 100644 index 0000000000..c64b3b37c3 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch @@ -0,0 +1,83 @@ +From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001 +Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org> +From: Lorenzo Bianconi +Date: Mon, 13 Mar 2023 15:10:56 +0100 +Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node + +Since the ilm memory region is not part of the RAM SoC, move ilm in a +deidicated syscon node. +This patch helps to keep backward-compatibility with older version of +uboot codebase where we have a limit of 8 reserved-memory dts child +nodes. + +Signed-off-by: Lorenzo Bianconi +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------ + 1 file changed, 16 insertions(+), 18 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -97,16 +97,6 @@ + no-map; + }; + +- wo_ilm0: wo-ilm@151e0000 { +- reg = <0 0x151e0000 0 0x8000>; +- no-map; +- }; +- +- wo_ilm1: wo-ilm@151f0000 { +- reg = <0 0x151f0000 0 0x8000>; +- no-map; +- }; +- + wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; +@@ -526,11 +516,10 @@ + reg = <0 0x15010000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; +- memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, +- <&wo_data>; +- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", +- "wo-data"; ++ memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; ++ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; + mediatek,wo-ccif = <&wo_ccif0>; ++ mediatek,wo-ilm = <&wo_ilm0>; + mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + +@@ -540,11 +529,10 @@ + reg = <0 0x15011000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; +- memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, +- <&wo_data>; +- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", +- "wo-data"; ++ memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; ++ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; + mediatek,wo-ccif = <&wo_ccif1>; ++ mediatek,wo-ilm = <&wo_ilm1>; + mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + +@@ -603,6 +591,16 @@ + interrupts = ; + }; + ++ wo_ilm0: syscon@151e0000 { ++ compatible = "mediatek,mt7986-wo-ilm", "syscon"; ++ reg = <0 0x151e0000 0 0x8000>; ++ }; ++ ++ wo_ilm1: syscon@151f0000 { ++ compatible = "mediatek,mt7986-wo-ilm", "syscon"; ++ reg = <0 0x151f0000 0 0x8000>; ++ }; ++ + wo_cpuboot: syscon@15194000 { + compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; + reg = <0 0x15194000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.12/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch new file mode 100644 index 0000000000..13fe1f792c --- /dev/null +++ b/target/linux/mediatek/patches-6.12/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch @@ -0,0 +1,81 @@ +From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001 +Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org> +From: Lorenzo Bianconi +Date: Mon, 13 Mar 2023 15:53:30 +0100 +Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node + +Since the dlm memory region is not part of the RAM SoC, move dlm in a +deidicated syscon node. +This patch helps to keep backward-compatibility with older version of +uboot codebase where we have a limit of 8 reserved-memory dts child +nodes. + +Signed-off-by: Lorenzo Bianconi +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++----------- + 1 file changed, 16 insertions(+), 14 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -101,16 +101,6 @@ + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; +- +- wo_dlm0: wo-dlm@151e8000 { +- reg = <0 0x151e8000 0 0x2000>; +- no-map; +- }; +- +- wo_dlm1: wo-dlm@151f8000 { +- reg = <0 0x151f8000 0 0x2000>; +- no-map; +- }; + }; + + soc { +@@ -516,10 +506,11 @@ + reg = <0 0x15010000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; +- memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; +- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; ++ memory-region = <&wo_emi0>, <&wo_data>; ++ memory-region-names = "wo-emi", "wo-data"; + mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-ilm = <&wo_ilm0>; ++ mediatek,wo-dlm = <&wo_dlm0>; + mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + +@@ -529,10 +520,11 @@ + reg = <0 0x15011000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; +- memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; +- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; ++ memory-region = <&wo_emi1>, <&wo_data>; ++ memory-region-names = "wo-emi", "wo-data"; + mediatek,wo-ccif = <&wo_ccif1>; + mediatek,wo-ilm = <&wo_ilm1>; ++ mediatek,wo-dlm = <&wo_dlm1>; + mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + +@@ -601,6 +593,16 @@ + reg = <0 0x151f0000 0 0x8000>; + }; + ++ wo_dlm0: syscon@151e8000 { ++ compatible = "mediatek,mt7986-wo-dlm", "syscon"; ++ reg = <0 0x151e8000 0 0x2000>; ++ }; ++ ++ wo_dlm1: syscon@151f8000 { ++ compatible = "mediatek,mt7986-wo-dlm", "syscon"; ++ reg = <0 0x151f8000 0 0x2000>; ++ }; ++ + wo_cpuboot: syscon@15194000 { + compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; + reg = <0 0x15194000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.12/950-smartrg-i2c-led-driver.patch b/target/linux/mediatek/patches-6.12/950-smartrg-i2c-led-driver.patch new file mode 100644 index 0000000000..faa801fc82 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/950-smartrg-i2c-led-driver.patch @@ -0,0 +1,34 @@ +--- + drivers/leds/Kconfig | 10 ++++++++++ + drivers/leds/Makefile | 1 + + 2 files changed, 11 insertions(+) + +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -977,6 +977,16 @@ source "drivers/leds/flash/Kconfig" + comment "RGB LED drivers" + source "drivers/leds/rgb/Kconfig" + ++config LEDS_SMARTRG_LED ++ tristate "LED support for Adtran SmartRG" ++ depends on LEDS_CLASS && I2C && OF ++ help ++ This option enables support for the Adtran SmartRG platform ++ system LED driver. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called leds-smartrg-system. ++ + comment "LED Triggers" + source "drivers/leds/trigger/Kconfig" + +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -81,6 +81,7 @@ obj-$(CONFIG_LEDS_POWERNV) += leds-powe + obj-$(CONFIG_LEDS_PWM) += leds-pwm.o + obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o + obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o ++obj-$(CONFIG_LEDS_SMARTRG_LED) += leds-smartrg-system.o + obj-$(CONFIG_LEDS_SUN50I_A100) += leds-sun50i-a100.o + obj-$(CONFIG_LEDS_ST1202) += leds-st1202.o + obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o diff --git a/target/linux/mediatek/patches-6.12/955-dts-mt7968a-bpi-r3-add-label-to-gmac-for-sfp1-port.patch b/target/linux/mediatek/patches-6.12/955-dts-mt7968a-bpi-r3-add-label-to-gmac-for-sfp1-port.patch new file mode 100644 index 0000000000..f11cf01686 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/955-dts-mt7968a-bpi-r3-add-label-to-gmac-for-sfp1-port.patch @@ -0,0 +1,10 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +@@ -195,6 +195,7 @@ + phy-mode = "2500base-x"; + sfp = <&sfp1>; + managed = "in-band-status"; ++ openwrt,netdev-name = "sfp1"; + }; + + mdio: mdio-bus { diff --git a/target/linux/mediatek/patches-6.12/960-asus-hack-u-boot-ignore-mtdparts.patch b/target/linux/mediatek/patches-6.12/960-asus-hack-u-boot-ignore-mtdparts.patch new file mode 100644 index 0000000000..9beeb7f50a --- /dev/null +++ b/target/linux/mediatek/patches-6.12/960-asus-hack-u-boot-ignore-mtdparts.patch @@ -0,0 +1,47 @@ +From 30a04cf5b6ffa1249df72ccd98cef05f37890f89 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 6 Feb 2025 05:07:20 +0000 +Subject: [PATCH] mtd: spinand: add work-around to prevent bootloader wiping + mtdparts + +ASUS makes use of U-Boot's fdt_fixup_mtdparts() function which applies +the partitions defined in U-Boot's mtdparts and mtdids environment +variables to the devicetree passed over to Linux. + +The undesired side-effect is that in this way also all additional +properties and child nodes get wiped, preventing NVMEM cells to be +defined for MTD partitions or UBI volumes. + +To work-around this issue, add an additional compatible string +'u-boot-dont-touch-spi-nand' which can be used instead of 'spi-nand' in +case the replacement of the MTD partitions by U-Boot should be skipped +alltogether. + +In practise this is mostly relevant for SPI-NAND which anyway comes only +with two partitions nowadays: 'Bootloader' and 'UBI_DEV'. Hence this +work-around is applicable for SPI-NAND only. Similar work-arounds for +other MTD devices can be created as well should they actually be needed. + +Signed-off-by: Daniel Golle +--- + drivers/mtd/nand/spi/core.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -1622,6 +1622,7 @@ static int spinand_remove(struct spi_mem + + static const struct spi_device_id spinand_ids[] = { + { .name = "spi-nand" }, ++ { .name = "u-boot-dont-touch-spi-nand" }, + { /* sentinel */ }, + }; + MODULE_DEVICE_TABLE(spi, spinand_ids); +@@ -1629,6 +1630,7 @@ MODULE_DEVICE_TABLE(spi, spinand_ids); + #ifdef CONFIG_OF + static const struct of_device_id spinand_of_ids[] = { + { .compatible = "spi-nand" }, ++ { .compatible = "u-boot-dont-touch-spi-nand" }, + { /* sentinel */ }, + }; + MODULE_DEVICE_TABLE(of, spinand_of_ids); diff --git a/target/linux/mvebu/image/cortexa9.mk b/target/linux/mvebu/image/cortexa9.mk index 1716f2f7c8..3c240d0a21 100644 --- a/target/linux/mvebu/image/cortexa9.mk +++ b/target/linux/mvebu/image/cortexa9.mk @@ -459,7 +459,7 @@ define Device/wd_cloud-mirror-gen2 DEVICE_MODEL := MyCloud Mirror Gen 2 (BWVZ/Grand Teton) DEVICE_PACKAGES += -uboot-envtools mkf2fs e2fsprogs \ partx-utils kmod-hwmon-drivetemp -ppp -kmod-nft-offload -dnsmasq \ - -odhcpd-ipv6only + -odhcpd-ipv6only DEVICE_DTS := armada-385-wd_cloud-mirror-gen2 KERNEL_SIZE := 5120k KERNEL := kernel-bin | append-dtb | uImage none diff --git a/target/linux/octeon/config-6.6 b/target/linux/octeon/config-6.6 index d0821b755c..1b4142d2b8 100644 --- a/target/linux/octeon/config-6.6 +++ b/target/linux/octeon/config-6.6 @@ -216,9 +216,9 @@ CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y CONFIG_RANDSTRUCT_NONE=y CONFIG_RAS=y -CONFIG_REGULATOR=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y +CONFIG_REGULATOR=y CONFIG_RELAY=y CONFIG_RFS_ACCEL=y CONFIG_RPS=y diff --git a/target/linux/pistachio/Makefile b/target/linux/pistachio/Makefile index ec003f6ed9..079b5412d4 100644 --- a/target/linux/pistachio/Makefile +++ b/target/linux/pistachio/Makefile @@ -13,6 +13,7 @@ CPU_SUBTYPE:=24kf SUBTARGETS:=generic KERNEL_PATCHVER:=6.6 +KERNEL_TESTING_PATCHVER:=6.12 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/pistachio/config-6.12 b/target/linux/pistachio/config-6.12 new file mode 100644 index 0000000000..d608211a7f --- /dev/null +++ b/target/linux/pistachio/config-6.12 @@ -0,0 +1,359 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +# CONFIG_BOARD_INGENIC is not set +CONFIG_BOARD_SCACHE=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUILTIN_DTB=y +CONFIG_CEVT_R4K=y +CONFIG_CLKSRC_MIPS_GIC=y +CONFIG_CLKSRC_PISTACHIO=y +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_PISTACHIO=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONNECTOR=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +# CONFIG_CPU_HAS_SMARTMIPS is not set +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_MICROMIPS is not set +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS32_R5 is not set +# CONFIG_CPU_MIPS32_R5_FEATURES is not set +# CONFIG_CPU_MIPS32_R6 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_MIPS64_R5 is not set +# CONFIG_CPU_MIPS64_R6 is not set +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_PM=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRC16=y +CONFIG_CRC_CCITT=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CSRC_R4K=y +CONFIG_DEBUG_INFO=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_OF=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_DWMAC_GENERIC=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +# CONFIG_FIT_IMAGE_FDT_BOSTON is not set +# CONFIG_FIT_IMAGE_FDT_JAGUAR2 is not set +# CONFIG_FIT_IMAGE_FDT_LUTON is not set +CONFIG_FIT_IMAGE_FDT_MARDUK=y +# CONFIG_FIT_IMAGE_FDT_NI169445 is not set +# CONFIG_FIT_IMAGE_FDT_OCELOT is not set +# CONFIG_FIT_IMAGE_FDT_SERVAL is not set +# CONFIG_FIT_IMAGE_FDT_XILFPGA is not set +CONFIG_FIXED_PHY=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_IMG=y +CONFIG_IMGPDC_WDT=y +CONFIG_IMG_MDC_DMA=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +# CONFIG_LEGACY_BOARD_OCELOT is not set +# CONFIG_LEGACY_BOARD_SEAD3 is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0 +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_AUTO_PFN_OFFSET=y +CONFIG_MIPS_CLOCK_VSYSCALL=y +CONFIG_MIPS_CM=y +CONFIG_MIPS_CMDLINE_DTB_EXTEND=y +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CPC=y +CONFIG_MIPS_CPS=y +# CONFIG_MIPS_CPS_CPUIDLE is not set +# CONFIG_MIPS_CPS_NS16550_BOOL is not set +CONFIG_MIPS_CPS_PM=y +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_MIPS_GENERIC=y +CONFIG_MIPS_GENERIC_KERNEL=y +CONFIG_MIPS_GIC=y +CONFIG_MIPS_L1_CACHE_SHIFT=7 +CONFIG_MIPS_L1_CACHE_SHIFT_7=y +CONFIG_MIPS_MT=y +CONFIG_MIPS_MT_FPAFF=y +CONFIG_MIPS_MT_SMP=y +CONFIG_MIPS_NO_APPENDED_DTB=y +CONFIG_MIPS_NR_CPU_NR_MAP=4 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MIPS_SPRAM=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_DW=y +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_HI3798MV200 is not set +# CONFIG_MMC_DW_K3 is not set +CONFIG_MMC_DW_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI_DRIVERS_GENERIC=y +CONFIG_PCS_XPCS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHY_PISTACHIO_USB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_PISTACHIO=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_EVENTS=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_IMG=y +CONFIG_PWM_SYSFS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_PISTACHIO=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_INFO=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SCSI_SPI_ATTRS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SC16IS7XX=y +CONFIG_SERIAL_SC16IS7XX_CORE=y +# CONFIG_SERIAL_SC16IS7XX_I2C is not set +CONFIG_SERIAL_SC16IS7XX_SPI=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPI=y +CONFIG_SPI_IMG_SPFI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SRAM=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWPHY=y +CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS32_R5=y +CONFIG_SYS_HAS_CPU_MIPS32_R6=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_SYS_HAS_CPU_MIPS64_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R5=y +CONFIG_SYS_HAS_CPU_MIPS64_R6=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_MICROMIPS=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MIPS_CPS=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_RELOCATABLE=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMARTMIPS=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UHI_BOOT=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_COMMON=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_DUAL_ROLE=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_GADGET=y +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +# CONFIG_VIRT_BOARD_RANCHU is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_WEAK_ORDERING=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_ZBOOT_LOAD_ADDRESS=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/pistachio/patches-6.12/101-dmaengine-img-mdc-Handle-early-status-read.patch b/target/linux/pistachio/patches-6.12/101-dmaengine-img-mdc-Handle-early-status-read.patch new file mode 100644 index 0000000000..abaaae1cc7 --- /dev/null +++ b/target/linux/pistachio/patches-6.12/101-dmaengine-img-mdc-Handle-early-status-read.patch @@ -0,0 +1,68 @@ +From a2dd154377c9aa6ddda00d39b8c7c334e4fa16ff Mon Sep 17 00:00:00 2001 +From: Damien Horsley +Date: Tue, 22 Mar 2016 12:46:09 +0000 +Subject: dmaengine: img-mdc: Handle early status read + +It is possible that mdc_tx_status may be called before the first +node has been read from memory. + +In this case, the residue value stored in the register is undefined. +Return the transfer size instead. + +Signed-off-by: Damien Horsley +--- + drivers/dma/img-mdc-dma.c | 40 ++++++++++++++++++++++++---------------- + 1 file changed, 24 insertions(+), 16 deletions(-) + +--- a/drivers/dma/img-mdc-dma.c ++++ b/drivers/dma/img-mdc-dma.c +@@ -617,25 +617,33 @@ static enum dma_status mdc_tx_status(str + (MDC_CMDS_PROCESSED_CMDS_DONE_MASK + 1); + + /* +- * If the command loaded event hasn't been processed yet, then +- * the difference above includes an extra command. ++ * If the first node has not yet been read from memory, ++ * the residue register value is undefined + */ +- if (!mdesc->cmd_loaded) +- cmds--; +- else +- cmds += mdesc->list_cmds_done; +- +- bytes = mdesc->list_xfer_size; +- ldesc = mdesc->list; +- for (i = 0; i < cmds; i++) { +- bytes -= ldesc->xfer_size + 1; +- ldesc = ldesc->next_desc; +- } +- if (ldesc) { +- if (residue != MDC_TRANSFER_SIZE_MASK) +- bytes -= ldesc->xfer_size - residue; ++ if (!mdesc->cmd_loaded && !cmds) { ++ bytes = mdesc->list_xfer_size; ++ } else { ++ /* ++ * If the command loaded event hasn't been processed yet, then ++ * the difference above includes an extra command. ++ */ ++ if (!mdesc->cmd_loaded) ++ cmds--; + else ++ cmds += mdesc->list_cmds_done; ++ ++ bytes = mdesc->list_xfer_size; ++ ldesc = mdesc->list; ++ for (i = 0; i < cmds; i++) { + bytes -= ldesc->xfer_size + 1; ++ ldesc = ldesc->next_desc; ++ } ++ if (ldesc) { ++ if (residue != MDC_TRANSFER_SIZE_MASK) ++ bytes -= ldesc->xfer_size - residue; ++ else ++ bytes -= ldesc->xfer_size + 1; ++ } + } + } + spin_unlock_irqrestore(&mchan->vc.lock, flags); diff --git a/target/linux/pistachio/patches-6.12/102-spi-img-spfi-Implement-dual-and-quad-mode.patch b/target/linux/pistachio/patches-6.12/102-spi-img-spfi-Implement-dual-and-quad-mode.patch new file mode 100644 index 0000000000..6ec1a2ab12 --- /dev/null +++ b/target/linux/pistachio/patches-6.12/102-spi-img-spfi-Implement-dual-and-quad-mode.patch @@ -0,0 +1,198 @@ +From cd2a6af51553d38072cd31699b58d16ca6176ef5 Mon Sep 17 00:00:00 2001 +From: Ionela Voinescu +Date: Thu, 2 Feb 2017 16:46:14 +0000 +Subject: spi: img-spfi: Implement dual and quad mode + +For dual and quad modes to work the SPFI controller needs +to have information about command/address/dummy bytes in the +transaction register. This information is not relevant for +single mode, and therefore it can have any value in the +allowed range. Therefore, for any read or write transfers of less +than 8 bytes (cmd = 1 byte, addr up to 7 bytes), SPFI will be +configured, but not enabled (unless it is the last transfer in +the queue). The transfer will be enabled by the subsequent tranfer. +A pending transfer is determined by the content of the transaction +register: if command part is set and tsize is not. + +This way we ensure that for dual and quad transactions +the command request size will apear in the command/address part +of the transaction register, while the data size will be in +tsize, all data being sent/received in the same transaction (as +set up in the transaction register). + +Signed-off-by: Ionela Voinescu +Signed-off-by: Ezequiel Garcia +--- + drivers/spi/spi-img-spfi.c | 96 ++++++++++++++++++++++++++++++++++++++++------ + 1 file changed, 85 insertions(+), 11 deletions(-) + +--- a/drivers/spi/spi-img-spfi.c ++++ b/drivers/spi/spi-img-spfi.c +@@ -36,7 +36,8 @@ + #define SPFI_CONTROL_SOFT_RESET BIT(11) + #define SPFI_CONTROL_SEND_DMA BIT(10) + #define SPFI_CONTROL_GET_DMA BIT(9) +-#define SPFI_CONTROL_SE BIT(8) ++#define SPFI_CONTROL_SE BIT(8) ++#define SPFI_CONTROL_TX_RX BIT(1) + #define SPFI_CONTROL_TMODE_SHIFT 5 + #define SPFI_CONTROL_TMODE_MASK 0x7 + #define SPFI_CONTROL_TMODE_SINGLE 0 +@@ -47,6 +48,10 @@ + #define SPFI_TRANSACTION 0x18 + #define SPFI_TRANSACTION_TSIZE_SHIFT 16 + #define SPFI_TRANSACTION_TSIZE_MASK 0xffff ++#define SPFI_TRANSACTION_CMD_SHIFT 13 ++#define SPFI_TRANSACTION_CMD_MASK 0x7 ++#define SPFI_TRANSACTION_ADDR_SHIFT 10 ++#define SPFI_TRANSACTION_ADDR_MASK 0x7 + + #define SPFI_PORT_STATE 0x1c + #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20 +@@ -83,6 +88,7 @@ + */ + #define SPFI_32BIT_FIFO_SIZE 64 + #define SPFI_8BIT_FIFO_SIZE 16 ++#define SPFI_DATA_REQUEST_MAX_SIZE 8 + + struct img_spfi { + struct device *dev; +@@ -99,6 +105,8 @@ struct img_spfi { + struct dma_chan *tx_ch; + bool tx_dma_busy; + bool rx_dma_busy; ++ ++ bool complete; + }; + + static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg) +@@ -115,9 +123,11 @@ static inline void spfi_start(struct img + { + u32 val; + +- val = spfi_readl(spfi, SPFI_CONTROL); +- val |= SPFI_CONTROL_SPFI_EN; +- spfi_writel(spfi, val, SPFI_CONTROL); ++ if (spfi->complete) { ++ val = spfi_readl(spfi, SPFI_CONTROL); ++ val |= SPFI_CONTROL_SPFI_EN; ++ spfi_writel(spfi, val, SPFI_CONTROL); ++ } + } + + static inline void spfi_reset(struct img_spfi *spfi) +@@ -130,12 +140,21 @@ static int spfi_wait_all_done(struct img + { + unsigned long timeout = jiffies + msecs_to_jiffies(50); + ++ if (!(spfi->complete)) ++ return 0; ++ + while (time_before(jiffies, timeout)) { + u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); + + if (status & SPFI_INTERRUPT_ALLDONETRIG) { + spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG, + SPFI_INTERRUPT_CLEAR); ++ /* ++ * Disable SPFI for it not to interfere with ++ * pending transactions ++ */ ++ spfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL) ++ & ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL); + return 0; + } + cpu_relax(); +@@ -441,9 +460,32 @@ static void img_spfi_config(struct spi_c + struct spi_transfer *xfer) + { + struct img_spfi *spfi = spi_controller_get_devdata(spi->controller); +- u32 val, div; ++ u32 val, div, transact; ++ bool is_pending; + + /* ++ * For read or write transfers of less than 8 bytes (cmd = 1 byte, ++ * addr up to 7 bytes), SPFI will be configured, but not enabled ++ * (unless it is the last transfer in the queue).The transfer will ++ * be enabled by the subsequent transfer. ++ * A pending transfer is determined by the content of the ++ * transaction register: if command part is set and tsize ++ * is not ++ */ ++ transact = spfi_readl(spfi, SPFI_TRANSACTION); ++ is_pending = ((transact >> SPFI_TRANSACTION_CMD_SHIFT) & ++ SPFI_TRANSACTION_CMD_MASK) && ++ (!((transact >> SPFI_TRANSACTION_TSIZE_SHIFT) & ++ SPFI_TRANSACTION_TSIZE_MASK)); ++ ++ /* If there are no pending transactions it's OK to soft reset */ ++ if (!is_pending) { ++ /* Start the transaction from a known (reset) state */ ++ spfi_reset(spfi); ++ } ++ ++ /* ++ * Before anything else, set up parameters. + * output = spfi_clk * (BITCLK / 512), where BITCLK must be a + * power of 2 up to 128 + */ +@@ -456,20 +498,52 @@ static void img_spfi_config(struct spi_c + val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT; + spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi_get_chipselect(spi, 0))); + +- spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT, +- SPFI_TRANSACTION); ++ if (!list_is_last(&xfer->transfer_list, &host->cur_msg->transfers) && ++ /* ++ * For duplex mode (both the tx and rx buffers are !NULL) the ++ * CMD, ADDR, and DUMMY byte parts of the transaction register ++ * should always be 0 and therefore the pending transfer ++ * technique cannot be used. ++ */ ++ (xfer->tx_buf) && (!xfer->rx_buf) && ++ (xfer->len <= SPFI_DATA_REQUEST_MAX_SIZE) && !is_pending) { ++ transact = (1 & SPFI_TRANSACTION_CMD_MASK) << ++ SPFI_TRANSACTION_CMD_SHIFT; ++ transact |= ((xfer->len - 1) & SPFI_TRANSACTION_ADDR_MASK) << ++ SPFI_TRANSACTION_ADDR_SHIFT; ++ spfi->complete = false; ++ } else { ++ spfi->complete = true; ++ if (is_pending) { ++ /* Keep setup from pending transfer */ ++ transact |= ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) << ++ SPFI_TRANSACTION_TSIZE_SHIFT); ++ } else { ++ transact = ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) << ++ SPFI_TRANSACTION_TSIZE_SHIFT); ++ } ++ } ++ spfi_writel(spfi, transact, SPFI_TRANSACTION); + + val = spfi_readl(spfi, SPFI_CONTROL); + val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA); +- if (xfer->tx_buf) ++ /* ++ * We set up send DMA for pending transfers also, as ++ * those are always send transfers ++ */ ++ if ((xfer->tx_buf) || is_pending) + val |= SPFI_CONTROL_SEND_DMA; +- if (xfer->rx_buf) ++ if (xfer->tx_buf) ++ val |= SPFI_CONTROL_TX_RX; ++ if (xfer->rx_buf) { + val |= SPFI_CONTROL_GET_DMA; ++ val &= ~SPFI_CONTROL_TX_RX; ++ } + val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT); +- if (xfer->tx_nbits == SPI_NBITS_DUAL && ++ if (xfer->tx_nbits == SPI_NBITS_DUAL || + xfer->rx_nbits == SPI_NBITS_DUAL) + val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT; +- else if (xfer->tx_nbits == SPI_NBITS_QUAD && ++ else if (xfer->tx_nbits == SPI_NBITS_QUAD || + xfer->rx_nbits == SPI_NBITS_QUAD) + val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT; + val |= SPFI_CONTROL_SE; diff --git a/target/linux/pistachio/patches-6.12/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch b/target/linux/pistachio/patches-6.12/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch new file mode 100644 index 0000000000..b3505134b6 --- /dev/null +++ b/target/linux/pistachio/patches-6.12/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch @@ -0,0 +1,64 @@ +From 905ee06a9966113fe51d6bad1819759cb30fd0bd Mon Sep 17 00:00:00 2001 +From: Ionela Voinescu +Date: Tue, 9 Feb 2016 10:18:31 +0000 +Subject: spi: img-spfi: use device 0 configuration for all devices + +Given that we control the chip select line externally +we can use only one parameter register (device 0 parameter +register) and one set of configuration bits (port configuration +bits for device 0) for all devices (all chip select lines). + +Signed-off-by: Ionela Voinescu +--- + drivers/spi/spi-img-spfi.c | 23 ++++++++++++++++------- + 1 file changed, 16 insertions(+), 7 deletions(-) + +--- a/drivers/spi/spi-img-spfi.c ++++ b/drivers/spi/spi-img-spfi.c +@@ -429,18 +429,23 @@ static int img_spfi_prepare(struct spi_c + struct img_spfi *spfi = spi_controller_get_devdata(host); + u32 val; + ++ /* ++ * The chip select line is controlled externally so ++ * we can use the CS0 configuration for all devices ++ */ + val = spfi_readl(spfi, SPFI_PORT_STATE); ++ ++ /* 0 for device selection */ + val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << + SPFI_PORT_STATE_DEV_SEL_SHIFT); +- val |= spi_get_chipselect(msg->spi, 0) << SPFI_PORT_STATE_DEV_SEL_SHIFT; + if (msg->spi->mode & SPI_CPHA) +- val |= SPFI_PORT_STATE_CK_PHASE(spi_get_chipselect(msg->spi, 0)); ++ val |= SPFI_PORT_STATE_CK_PHASE(0); + else +- val &= ~SPFI_PORT_STATE_CK_PHASE(spi_get_chipselect(msg->spi, 0)); ++ val &= ~SPFI_PORT_STATE_CK_PHASE(0); + if (msg->spi->mode & SPI_CPOL) +- val |= SPFI_PORT_STATE_CK_POL(spi_get_chipselect(msg->spi, 0)); ++ val |= SPFI_PORT_STATE_CK_POL(0); + else +- val &= ~SPFI_PORT_STATE_CK_POL(spi_get_chipselect(msg->spi, 0)); ++ val &= ~SPFI_PORT_STATE_CK_POL(0); + spfi_writel(spfi, val, SPFI_PORT_STATE); + + return 0; +@@ -492,11 +497,15 @@ static void img_spfi_config(struct spi_c + div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz); + div = clamp(512 / (1 << get_count_order(div)), 1, 128); + +- val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi_get_chipselect(spi, 0))); ++ /* ++ * The chip select line is controlled externally so ++ * we can use the CS0 parameters for all devices ++ */ ++ val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(0)); + val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK << + SPFI_DEVICE_PARAMETER_BITCLK_SHIFT); + val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT; +- spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi_get_chipselect(spi, 0))); ++ spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(0)); + + if (!list_is_last(&xfer->transfer_list, &host->cur_msg->transfers) && + /* diff --git a/target/linux/pistachio/patches-6.12/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch b/target/linux/pistachio/patches-6.12/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch new file mode 100644 index 0000000000..5418503816 --- /dev/null +++ b/target/linux/pistachio/patches-6.12/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch @@ -0,0 +1,59 @@ +From 56466f505f58f44b69feb7eaed3b506842800456 Mon Sep 17 00:00:00 2001 +From: Ionela Voinescu +Date: Tue, 1 Mar 2016 17:49:45 +0000 +Subject: spi: img-spfi: RX maximum burst size for DMA is 8 + +The depth of the FIFOs is 16 bytes. The DMA request line is tied +to the half full/empty (depending on the use of the TX or RX FIFO) +threshold. For the TX FIFO, if you set a burst size of 8 (equal to +half the depth) the first burst goes into FIFO without any issues, +but due the latency involved (the time the data leaves the DMA +engine to the time it arrives at the FIFO), the DMA might trigger +another burst of 8. But given that there is no space for 2 additonal +bursts of 8, this would result in a failure. Therefore, we have to +keep the burst size for TX to 4 to accomodate for an extra burst. + +For the read (RX) scenario, the DMA request line goes high when +there is at least 8 entries in the FIFO (half full), and we can +program the burst size to be 8 because the risk of accidental burst +does not exist. The DMA engine will not trigger another read until +the read data for all the burst it has sent out has been received. + +While here, move the burst size setting outside of the if/else branches +as they have the same value for both 8 and 32 bit data widths. + +Signed-off-by: Ionela Voinescu +--- + drivers/spi/spi-img-spfi.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/spi/spi-img-spfi.c ++++ b/drivers/spi/spi-img-spfi.c +@@ -338,12 +338,11 @@ static int img_spfi_start_dma(struct spi + if (xfer->len % 4 == 0) { + rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA; + rxconf.src_addr_width = 4; +- rxconf.src_maxburst = 4; + } else { + rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA; + rxconf.src_addr_width = 1; +- rxconf.src_maxburst = 4; + } ++ rxconf.src_maxburst = 8; + dmaengine_slave_config(spfi->rx_ch, &rxconf); + + rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl, +@@ -362,12 +361,11 @@ static int img_spfi_start_dma(struct spi + if (xfer->len % 4 == 0) { + txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA; + txconf.dst_addr_width = 4; +- txconf.dst_maxburst = 4; + } else { + txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA; + txconf.dst_addr_width = 1; +- txconf.dst_maxburst = 4; + } ++ txconf.dst_maxburst = 4; + dmaengine_slave_config(spfi->tx_ch, &txconf); + + txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl, diff --git a/target/linux/pistachio/patches-6.12/106-spi-img-spfi-finish-every-transfer-cleanly.patch b/target/linux/pistachio/patches-6.12/106-spi-img-spfi-finish-every-transfer-cleanly.patch new file mode 100644 index 0000000000..a87594e4c7 --- /dev/null +++ b/target/linux/pistachio/patches-6.12/106-spi-img-spfi-finish-every-transfer-cleanly.patch @@ -0,0 +1,120 @@ +From 5fcca3fd4b621d7b5bdeca18d36dfc6ca6cfe383 Mon Sep 17 00:00:00 2001 +From: Ionela Voinescu +Date: Wed, 10 Aug 2016 11:42:26 +0100 +Subject: spi: img-spfi: finish every transfer cleanly + +Before this change, the interrupt status bit that signaled +the end of a tranfers was cleared in the wait_all_done +function. That functionality triggered issues for DMA +duplex transactions where the wait function was called +twice, in both the TX and RX callbacks. + +In order to fix the issue, clear all interrupt data bits +at the end of a PIO transfer or at the end of both TX and RX +duplex transfers, if the transfer is not a pending tranfer +(command waiting for data). After that, the status register +is checked for new incoming data or new data requests to be +signaled. If SPFI finished cleanly, no new interrupt data +bits should be set. + +Signed-off-by: Ionela Voinescu +--- + drivers/spi/spi-img-spfi.c | 49 +++++++++++++++++++++++++++++++++------------- + 1 file changed, 35 insertions(+), 14 deletions(-) + +--- a/drivers/spi/spi-img-spfi.c ++++ b/drivers/spi/spi-img-spfi.c +@@ -79,6 +79,14 @@ + #define SPFI_INTERRUPT_SDE BIT(1) + #define SPFI_INTERRUPT_SDTRIG BIT(0) + ++#define SPFI_INTERRUPT_DATA_BITS (SPFI_INTERRUPT_SDHF |\ ++ SPFI_INTERRUPT_SDFUL |\ ++ SPFI_INTERRUPT_GDEX32BIT |\ ++ SPFI_INTERRUPT_GDHF |\ ++ SPFI_INTERRUPT_GDFUL |\ ++ SPFI_INTERRUPT_ALLDONETRIG |\ ++ SPFI_INTERRUPT_GDEX8BIT) ++ + /* + * There are four parallel FIFOs of 16 bytes each. The word buffer + * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an +@@ -136,6 +144,23 @@ static inline void spfi_reset(struct img + spfi_writel(spfi, 0, SPFI_CONTROL); + } + ++static inline void spfi_finish(struct img_spfi *spfi) ++{ ++ if (!(spfi->complete)) ++ return; ++ ++ /* Clear data bits as all transfers(TX and RX) have finished */ ++ spfi_writel(spfi, SPFI_INTERRUPT_DATA_BITS, SPFI_INTERRUPT_CLEAR); ++ if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) & SPFI_INTERRUPT_DATA_BITS) { ++ dev_err(spfi->dev, "SPFI did not finish transfer cleanly.\n"); ++ spfi_reset(spfi); ++ } ++ /* Disable SPFI for it not to interfere with pending transactions */ ++ spfi_writel(spfi, ++ spfi_readl(spfi, SPFI_CONTROL) & ~SPFI_CONTROL_SPFI_EN, ++ SPFI_CONTROL); ++} ++ + static int spfi_wait_all_done(struct img_spfi *spfi) + { + unsigned long timeout = jiffies + msecs_to_jiffies(50); +@@ -144,19 +169,9 @@ static int spfi_wait_all_done(struct img + return 0; + + while (time_before(jiffies, timeout)) { +- u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); +- +- if (status & SPFI_INTERRUPT_ALLDONETRIG) { +- spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG, +- SPFI_INTERRUPT_CLEAR); +- /* +- * Disable SPFI for it not to interfere with +- * pending transactions +- */ +- spfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL) +- & ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL); ++ if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) & ++ SPFI_INTERRUPT_ALLDONETRIG) + return 0; +- } + cpu_relax(); + } + +@@ -288,6 +303,8 @@ static int img_spfi_start_pio(struct spi + } + + ret = spfi_wait_all_done(spfi); ++ spfi_finish(spfi); ++ + if (ret < 0) + return ret; + +@@ -303,8 +320,10 @@ static void img_spfi_dma_rx_cb(void *dat + + spin_lock_irqsave(&spfi->lock, flags); + spfi->rx_dma_busy = false; +- if (!spfi->tx_dma_busy) ++ if (!spfi->tx_dma_busy) { ++ spfi_finish(spfi); + spi_finalize_current_transfer(spfi->host); ++ } + spin_unlock_irqrestore(&spfi->lock, flags); + } + +@@ -317,8 +336,10 @@ static void img_spfi_dma_tx_cb(void *dat + + spin_lock_irqsave(&spfi->lock, flags); + spfi->tx_dma_busy = false; +- if (!spfi->rx_dma_busy) ++ if (!spfi->rx_dma_busy) { ++ spfi_finish(spfi); + spi_finalize_current_transfer(spfi->host); ++ } + spin_unlock_irqrestore(&spfi->lock, flags); + } + diff --git a/target/linux/pistachio/patches-6.12/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch b/target/linux/pistachio/patches-6.12/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch new file mode 100644 index 0000000000..6fddbe269a --- /dev/null +++ b/target/linux/pistachio/patches-6.12/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch @@ -0,0 +1,49 @@ +From 3642843a06025ec333d7e92580cf52cb8db2a652 Mon Sep 17 00:00:00 2001 +From: Govindraj Raja +Date: Fri, 8 Jan 2016 16:36:07 +0000 +Subject: clk: pistachio: Fix wrong SDHost card speed + +The SDHost currently clocks the card 4x slower than it +should do, because there is fixed divide by 4 in the +sdhost wrapper that is not present in the clock tree. +To model this add a fixed divide by 4 clock node in +the SDHost clock path. + +This will ensure the right clock frequency is selected when +the mmc driver tries to configure frequency on card insert. + +Signed-off-by: Govindraj Raja +--- + drivers/clk/pistachio/clk-pistachio.c | 3 ++- + include/dt-bindings/clock/pistachio-clk.h | 1 + + 2 files changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/clk/pistachio/clk-pistachio.c ++++ b/drivers/clk/pistachio/clk-pistachio.c +@@ -41,7 +41,7 @@ static struct pistachio_gate pistachio_g + GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div", + 0x104, 22), + GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23), +- GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24), ++ GATE(CLK_SD_HOST, "sd_host", "sd_host_div4", 0x104, 24), + GATE(CLK_BT, "bt", "bt_div", 0x104, 25), + GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26), + GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27), +@@ -51,6 +51,7 @@ static struct pistachio_gate pistachio_g + static struct pistachio_fixed_factor pistachio_ffs[] __initdata = { + FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4), + FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8), ++ FIXED_FACTOR(CLK_SDHOST_DIV4, "sd_host_div4", "sd_host_div", 4), + }; + + static struct pistachio_div pistachio_divs[] __initdata = { +--- a/include/dt-bindings/clock/pistachio-clk.h ++++ b/include/dt-bindings/clock/pistachio-clk.h +@@ -18,6 +18,7 @@ + /* Fixed-factor clocks */ + #define CLK_WIFI_DIV4 16 + #define CLK_WIFI_DIV8 17 ++#define CLK_SDHOST_DIV4 18 + + /* Gate clocks */ + #define CLK_MIPS 32 diff --git a/target/linux/pistachio/patches-6.12/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch b/target/linux/pistachio/patches-6.12/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch new file mode 100644 index 0000000000..faba23c5f1 --- /dev/null +++ b/target/linux/pistachio/patches-6.12/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch @@ -0,0 +1,47 @@ +From 981c1d416af45eff207227aec106381ac23aac99 Mon Sep 17 00:00:00 2001 +From: Ian Pozella +Date: Mon, 20 Feb 2017 10:00:52 +0000 +Subject: MIPS: DTS: img: marduk: switch mmc to 1 bit mode + +The mmc block in Pistachio allows 1 to 8 data bits to be used. +Marduk uses 4 bits allowing the upper 4 bits to be allocated +to the Mikrobus ports. However these bits are still connected +internally meaning the mmc block recieves signals on all data lines +and seems the internal HW CRC checks get corrupted by this erroneous +data. + +We cannot control what data is sent on these lines because they go +to external ports. 1 bit mode does not exhibit the issue hence the +safe default is to use this. If a user knows that in their use case +they will not use the upper bits then they can set to 4 bit mode in +order to improve performance. + +Also make sure that the upper 4 bits don't get allocated to the mmc +driver (the default is to assign all 8 pins) so they can be allocated +to other drivers. Allocating all 4 despite setting 1 bit mode as this +matches what is there in hardware. + +Signed-off-by: Ian Pozella +--- + arch/mips/boot/dts/img/pistachio_marduk.dts | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -118,7 +118,7 @@ + + &sdhost { + status = "okay"; +- bus-width = <4>; ++ bus-width = <1>; + disable-wp; + }; + +@@ -128,6 +128,7 @@ + + &pin_sdhost_data { + drive-strength = <2>; ++ pins = "mfio17", "mfio18", "mfio19", "mfio20"; + }; + + &pwm { diff --git a/target/linux/pistachio/patches-6.12/401-mtd-nor-support-mtd-name-from-device-tree.patch b/target/linux/pistachio/patches-6.12/401-mtd-nor-support-mtd-name-from-device-tree.patch new file mode 100644 index 0000000000..ff686e03a7 --- /dev/null +++ b/target/linux/pistachio/patches-6.12/401-mtd-nor-support-mtd-name-from-device-tree.patch @@ -0,0 +1,61 @@ +From f32bc2aa01edcba2f2ed5db151cf183eac9ef919 Mon Sep 17 00:00:00 2001 +From: Abhimanyu Vishwakarma +Date: Sat, 25 Feb 2017 16:42:50 +0000 +Subject: mtd: nor: support mtd name from device tree + +Signed-off-by: Abhimanyu Vishwakarma +--- + drivers/mtd/spi-nor/spi-nor.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/drivers/spi/spi-mem.c ++++ b/drivers/spi/spi-mem.c +@@ -893,7 +893,9 @@ static int spi_mem_probe(struct spi_devi + { + struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver); + struct spi_controller *ctlr = spi->controller; ++ const char __maybe_unused *of_mtd_name = NULL; + struct spi_mem *mem; ++ int ret; + + mem = devm_kzalloc(&spi->dev, sizeof(*mem), GFP_KERNEL); + if (!mem) +@@ -901,10 +903,15 @@ static int spi_mem_probe(struct spi_devi + + mem->spi = spi; + +- if (ctlr->mem_ops && ctlr->mem_ops->get_name) ++ if (ctlr->mem_ops && ctlr->mem_ops->get_name) { + mem->name = ctlr->mem_ops->get_name(mem); +- else +- mem->name = dev_name(&spi->dev); ++ } else { ++ ret = device_property_read_string(&spi->dev, "linux,mtd-name", &of_mtd_name); ++ if (!ret) ++ mem->name = of_mtd_name; ++ else ++ mem->name = dev_name(&spi->dev); ++ } + + if (IS_ERR_OR_NULL(mem->name)) + return PTR_ERR_OR_ZERO(mem->name); +--- a/drivers/mtd/mtdcore.c ++++ b/drivers/mtd/mtdcore.c +@@ -872,6 +872,17 @@ out_error: + */ + static void mtd_set_dev_defaults(struct mtd_info *mtd) + { ++#ifdef CONFIG_MTD_OF_PARTS ++ const char __maybe_unused *of_mtd_name = NULL; ++ struct device_node *np; ++ ++ np = mtd_get_of_node(mtd); ++ if (np && !mtd->name) { ++ of_property_read_string(np, "linux,mtd-name", &of_mtd_name); ++ if (of_mtd_name) ++ mtd->name = of_mtd_name; ++ } else ++#endif + if (mtd->dev.parent) { + if (!mtd->owner && mtd->dev.parent->driver) + mtd->owner = mtd->dev.parent->driver->owner; diff --git a/target/linux/pistachio/patches-6.12/901-MIPS-DTS-img-marduk-Add-SPI-NAND-flash.patch b/target/linux/pistachio/patches-6.12/901-MIPS-DTS-img-marduk-Add-SPI-NAND-flash.patch new file mode 100644 index 0000000000..4b28f46833 --- /dev/null +++ b/target/linux/pistachio/patches-6.12/901-MIPS-DTS-img-marduk-Add-SPI-NAND-flash.patch @@ -0,0 +1,30 @@ +From 0023c706f7e0f0f02bd48a63a2f3c04c839532ae Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sat, 15 Aug 2020 16:04:53 +0200 +Subject: [PATCH 901/904] MIPS: DTS: img: marduk: Add SPI NAND flash + +Add Gigadevice GD5F4GQ4UCYIGT SPI NAND flash to the device tree. + +The NAND flash chip is connected with quad SPI, but reading currently +fails in quad SPI mode. + +Signed-off-by: Hauke Mehrtens +--- + arch/mips/boot/dts/img/pistachio_marduk.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -89,6 +89,12 @@ + reg = <0>; + spi-max-frequency = <50000000>; + }; ++ ++ flash@1 { ++ compatible = "spi-nand"; ++ reg = <1>; ++ spi-max-frequency = <50000000>; ++ }; + }; + + &uart0 { diff --git a/target/linux/pistachio/patches-6.12/902-MIPS-DTS-img-marduk-Add-Cascoda-CA8210-6LoWPAN.patch b/target/linux/pistachio/patches-6.12/902-MIPS-DTS-img-marduk-Add-Cascoda-CA8210-6LoWPAN.patch new file mode 100644 index 0000000000..d4c4ccac53 --- /dev/null +++ b/target/linux/pistachio/patches-6.12/902-MIPS-DTS-img-marduk-Add-Cascoda-CA8210-6LoWPAN.patch @@ -0,0 +1,43 @@ +From b7700154d75e8d7c9a2022f09c2d5430137606fa Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sat, 15 Aug 2020 16:05:25 +0200 +Subject: [PATCH 902/904] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN + +Add Cascoda CA8210 6LoWPAN controller to device tree. + +Signed-off-by: Hauke Mehrtens +--- + arch/mips/boot/dts/img/pistachio_marduk.dts | 22 +++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -76,6 +76,28 @@ + VDD-supply = <&internal_dac_supply>; + }; + ++&spfi0 { ++ status = "okay"; ++ pinctrl-0 = <&spim0_pins>, <&spim0_cs0_alt_pin>, <&spim0_cs2_alt_pin>, <&spim0_cs3_alt_pin>, <&spim0_cs4_alt_pin>; ++ pinctrl-names = "default"; ++ ++ cs-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>, <&gpio0 2 GPIO_ACTIVE_HIGH>, ++ <&gpio1 12 GPIO_ACTIVE_HIGH>, <&gpio1 13 GPIO_ACTIVE_HIGH>; ++ ++ ca8210: ca8210@0 { ++ status = "okay"; ++ compatible = "cascoda,ca8210"; ++ reg = <0>; ++ spi-max-frequency = <4000000>; ++ spi-cpol; ++ reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; ++ irq-gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; ++ extclock-enable; ++ extclock-freq = <16000000>; ++ extclock-gpio = <2>; ++ }; ++}; ++ + &spfi1 { + status = "okay"; + diff --git a/target/linux/pistachio/patches-6.12/903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch b/target/linux/pistachio/patches-6.12/903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch new file mode 100644 index 0000000000..b1070c3d30 --- /dev/null +++ b/target/linux/pistachio/patches-6.12/903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch @@ -0,0 +1,81 @@ +From ad4eba0c36ce8af6ab9ea1bc163e4c1ac7c271c3 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sat, 15 Aug 2020 16:09:02 +0200 +Subject: [PATCH 903/904] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW + +Add NXP SC16IS752IPW SPI-UART controller to device tree. + +This controller drives 2 UARTs and 7 LEDs on the board. + +Signed-off-by: Hauke Mehrtens +--- + arch/mips/boot/dts/img/pistachio_marduk.dts | 51 +++++++++++++++++++++ + 1 file changed, 51 insertions(+) + +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -46,6 +46,46 @@ + regulator-max-microvolt = <1800000>; + }; + ++ /* EXT clock from ca8210 is fed to sc16is752 */ ++ ca8210_ext_clk: ca8210-ext-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <16000000>; ++ clock-output-names = "ca8210_ext_clock"; ++ }; ++ ++ gpioleds { ++ compatible = "gpio-leds"; ++ user1 { ++ label = "marduk:red:user1"; ++ gpios = <&sc16is752 0 GPIO_ACTIVE_LOW>; ++ }; ++ user2 { ++ label = "marduk:red:user2"; ++ gpios = <&sc16is752 1 GPIO_ACTIVE_LOW>; ++ }; ++ user3 { ++ label = "marduk:red:user3"; ++ gpios = <&sc16is752 2 GPIO_ACTIVE_LOW>; ++ }; ++ user4 { ++ label = "marduk:red:user4"; ++ gpios = <&sc16is752 3 GPIO_ACTIVE_LOW>; ++ }; ++ user5 { ++ label = "marduk:red:user5"; ++ gpios = <&sc16is752 4 GPIO_ACTIVE_LOW>; ++ }; ++ user6 { ++ label = "marduk:red:user6"; ++ gpios = <&sc16is752 5 GPIO_ACTIVE_LOW>; ++ }; ++ user7 { ++ label = "marduk:red:user7"; ++ gpios = <&sc16is752 6 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ + led-controller { + compatible = "pwm-leds"; + +@@ -96,6 +136,17 @@ + extclock-freq = <16000000>; + extclock-gpio = <2>; + }; ++ ++ sc16is752: sc16is752@1 { ++ compatible = "nxp,sc16is752"; ++ reg = <1>; ++ clocks = <&ca8210_ext_clk>; ++ spi-max-frequency = <4000000>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; + }; + + &spfi1 { diff --git a/target/linux/pistachio/patches-6.12/904-MIPS-DTS-img-marduk-Add-partition-name.patch b/target/linux/pistachio/patches-6.12/904-MIPS-DTS-img-marduk-Add-partition-name.patch new file mode 100644 index 0000000000..490027a702 --- /dev/null +++ b/target/linux/pistachio/patches-6.12/904-MIPS-DTS-img-marduk-Add-partition-name.patch @@ -0,0 +1,27 @@ +From ff0e950b605047bf50d470023e0fb2fc2003a0f0 Mon Sep 17 00:00:00 2001 +From: Ian Pozella +Date: Mon, 20 Feb 2017 10:38:07 +0000 +Subject: [PATCH 904/904] MIPS: DTS: img: marduk: Add partition name + +Signed-off-by: Ian Pozella +--- + arch/mips/boot/dts/img/pistachio_marduk.dts | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -161,12 +161,14 @@ + compatible = "spansion,s25fl016k", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; ++ linux,mtd-name = "spi-nor"; + }; + + flash@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <50000000>; ++ linux,mtd-name = "spi-nand"; + }; + }; + diff --git a/target/linux/pistachio/patches-6.12/905-MIPS-DTS-img-marduk-Add-led-aliases.patch b/target/linux/pistachio/patches-6.12/905-MIPS-DTS-img-marduk-Add-led-aliases.patch new file mode 100644 index 0000000000..8c03ddeea2 --- /dev/null +++ b/target/linux/pistachio/patches-6.12/905-MIPS-DTS-img-marduk-Add-led-aliases.patch @@ -0,0 +1,27 @@ +--- a/arch/mips/boot/dts/img/pistachio_marduk.dts ++++ b/arch/mips/boot/dts/img/pistachio_marduk.dts +@@ -19,6 +19,11 @@ + ethernet0 = &enet; + spi0 = &spfi0; + spi1 = &spfi1; ++ ++ led-boot = &led_heartbeat; ++ led-failsafe = &led_heartbeat; ++ led-running = &led_heartbeat; ++ led-upgrade = &led_heartbeat; + }; + + chosen { +@@ -89,11 +94,10 @@ + led-controller { + compatible = "pwm-leds"; + +- led-1 { ++ led_heartbeat: heartbeat { + label = "marduk:red:heartbeat"; + pwms = <&pwm 3 300000>; + max-brightness = <255>; +- linux,default-trigger = "heartbeat"; + }; + }; + diff --git a/target/linux/qualcommax/base-files/etc/init.d/smp_affinity b/target/linux/qualcommax/base-files/etc/init.d/smp_affinity index 4ef580bdaa..21ef2a1cb1 100755 --- a/target/linux/qualcommax/base-files/etc/init.d/smp_affinity +++ b/target/linux/qualcommax/base-files/etc/init.d/smp_affinity @@ -73,26 +73,10 @@ set_affinity() { } enable_affinity() { - # assign 4 rx interrupts to each core - set_affinity 'reo2host-destination-ring1' 0 - set_affinity 'reo2host-destination-ring2' 1 - set_affinity 'reo2host-destination-ring3' 2 - set_affinity 'reo2host-destination-ring4' 3 - - # assign 3 tcl completions to last 3 CPUs - set_affinity 'wbm2host-tx-completions-ring1' 1 - set_affinity 'wbm2host-tx-completions-ring2' 2 - set_affinity 'wbm2host-tx-completions-ring3' 3 - - # assign 3 ppdu mac interrupts to last 3 cores - set_affinity 'ppdu-end-interrupts-mac1' 1 - set_affinity 'ppdu-end-interrupts-mac2' 2 - set_affinity 'ppdu-end-interrupts-mac3' 3 - - # assign 4 lan/wan to core 4 - set_affinity 'edma_txcmpl' 3 - set_affinity 'edma_rxfill' 3 - set_affinity 'edma_rxdesc' 3 + # assign 4 lan/wan + set_affinity 'edma_txcmpl' 1 + set_affinity 'edma_rxfill' 1 + set_affinity 'edma_rxdesc' 1 set_affinity 'edma_misc' 3 } diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts index 7ef9df7b35..db69b84ae0 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts @@ -23,8 +23,8 @@ }; chosen { - bootargs-append = " root=/dev/ubiblock0_1 swiotlb=1 coherent_pool=2M"; stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/ubiblock0_1"; }; keys { @@ -108,6 +108,7 @@ &mdio1 { status = "okay"; + pinctrl-0 = <&mdio1_pins>; pinctrl-names = "default"; reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; @@ -191,6 +192,7 @@ &blsp1_uart1 { status = "okay"; + pinctrl-0 = <&serial_0_pins>; pinctrl-names = "default"; }; @@ -222,11 +224,13 @@ nand@0 { compatible = "spi-nand"; - reg = <0>; #address-cells = <1>; #size-cells = <1>; + reg = <0>; nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { @@ -236,13 +240,9 @@ compatible = "fixed-partitions"; label = "0:ART"; read-only; - #address-cells = <1>; - #size-cells = <1>; nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; macaddr_dp2: macaddr@0 { compatible = "mac-base"; @@ -334,12 +334,6 @@ "ath11k/QCN6122/hw1.0/m3_fw.mdt"; /* B3000 currently doesn't support passing bootargs */ - /*boot-args = < */ - /* type: 0x1 PCIE0 */ - /* length: 4 */ - /* PD id: 3 */ - /* reset GPIO: 15 */ - /* reserved: 0 0>; */ // IPQ5018 q6_wcss_pd1: pd-1 { diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx-base.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx-base.dtsi index a0bd46dc02..35c3d89f5d 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx-base.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx-base.dtsi @@ -17,8 +17,8 @@ }; chosen { - bootargs-append = " root=/dev/ubiblock0_0 coherent_pool=2M"; stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/ubiblock0_0"; }; keys { @@ -126,17 +126,17 @@ nand@0 { compatible = "spi-nand"; - reg = <0>; #address-cells = <1>; #size-cells = <1>; + reg = <0>; nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:SBL1"; @@ -208,8 +208,6 @@ nvmem-layout { compatible = "ascii-eq-delim-env"; - #address-cells = <1>; - #size-cells = <1>; hw_mac_addr: hw_mac_addr { compatible = "mac-base"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx2000.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx2000.dts index 18a8d9d938..cd1789b0bb 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx2000.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx2000.dts @@ -153,14 +153,7 @@ "ath11k/IPQ5018/hw1.0/m3_fw.mdt", "ath11k/QCN6122/hw1.0/m3_fw.mdt"; - /* The QCN6102 radio should map to UPD ID 2. Without */ - /* bootargs, the firmware will expect it to be on UPD ID 3 */ - boot-args = < - /* type: */ 0x1 /* PCIE0 */ - /* length: */ 4 - /* UPD ID: */ 2 - /* reset GPIO: */ 15 - /* reserved: */ 0 0>; + boot-args = <0x1 4 2 15 0 0>; /* type, length, UPD ID, reset GPIO, reserved */ // IPQ5018 q6_wcss_pd1: pd-1 { diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-re-cs-03.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-re-cs-03.dts index 90b2574adc..4946f655be 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-re-cs-03.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-re-cs-03.dts @@ -325,13 +325,7 @@ "IPQ5018/hw1.0/m3_fw.mdt", "QCN6122/hw1.0/m3_fw.mdt"; - -// boot-args = -// ; + boot-args = <0x1 4 3 15 0 0>; /* type, length, UPD ID, reset GPIO, reserved */ // IPQ5018 q6_wcss_pd1: pd-1 { diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-wrc-x3000gs2.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-wrc-x3000gs2.dts index fbdc826800..fd4fd69134 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-wrc-x3000gs2.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-wrc-x3000gs2.dts @@ -24,8 +24,8 @@ }; chosen { - bootargs-append = " root=/dev/ubiblock0_1 coherent_pool=2M"; stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/ubiblock0_1"; }; keys { @@ -158,15 +158,13 @@ pinctrl-names = "default"; status = "okay"; - flash@0 { + nand@0 { compatible = "spi-nand"; - reg = <0>; #address-cells = <1>; #size-cells = <1>; + reg = <0>; nand-ecc-engine = <&qpic_nand>; - - /* strength=8 breaks NAND I/O, use 4 instead */ nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; @@ -177,8 +175,6 @@ partition-0-appsblenv { compatible = "fixed-partitions"; label = "0:appsblenv"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "env-data"; @@ -409,7 +405,7 @@ "ath11k/IPQ5018/hw1.0/m3_fw.mdt", "ath11k/QCN6122/hw1.0/m3_fw.mdt"; - boot-args = <0x2 4 2 18 0 0>; /* pcie:1, len:4, updid:2, reset:gpio18 */ + boot-args = <0x2 4 2 18 0 0>; /* type, length, UPD ID, reset GPIO, reserved */ q6_wcss_pd1: pd-1 { firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-360v6.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-360v6.dts index 99dbafa0fc..7e804e0dc1 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-360v6.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-360v6.dts @@ -99,7 +99,10 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-ap120c-ax.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-ap120c-ax.dts new file mode 100644 index 0000000000..0e7fec0362 --- /dev/null +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-ap120c-ax.dts @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include "ipq6018.dtsi" +#include "ipq6018-ess.dtsi" +#include "ipq6018-nss.dtsi" +#include "ipq6018-common.dtsi" +#include "ipq6018-cp-cpu.dtsi" + +#include +#include +#include + +/ { + model = "ALFA Network AP120C-AX"; + compatible = "alfa-network,ap120c-ax", "qcom,ipq6018"; + + aliases { + serial0 = &blsp1_uart3; + serial1 = &blsp1_uart2; + + led-boot = &led_status_green; + led-failsafe = &led_status_green; + led-running = &led_status_green; + led-upgrade = &led_status_green; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/ubiblock0_1"; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_green: status-green { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + }; + + led_status_wlan2g: status-wlan2g { + color = ; + function = LED_FUNCTION_WLAN_2GHZ; + gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1radio"; + }; + + led_status_wlan5g: status-wlan5g { + color = ; + function = LED_FUNCTION_WLAN_5GHZ; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0radio"; + }; + }; +}; + +&tlmm { + btcoex_pins: btcoex-pins { + mux_0 { + pins = "gpio51"; + function = "pta1_1"; + drive-strength = <6>; + bias-pull-down; + }; + + mux_1 { + pins = "gpio52"; + function = "pta1_2"; + drive-strength = <6>; + bias-pull-down; + }; + + mux_2 { + pins = "gpio53"; + function = "pta1_0"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + btrstint_pins: btrstint-pins { + pins = "gpio78", "gpio79"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + hsuart_pins: hsuart-pins { + pins = "gpio71", "gpio72", "gpio69", "gpio70"; + function = "blsp1_uart"; + drive-strength = <8>; + bias-disable; + }; + + mdio_pins: mdio-pins { + mdc { + pins = "gpio64"; + function = "mdc"; + drive-strength = <8>; + bias-pull-up; + }; + + mdio { + pins = "gpio65"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + spi_pins: spi-pins { + pins = "gpio38", "gpio39", "gpio40", "gpio41"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-pull-down; + }; +}; + +&blsp1_uart2 { + status = "okay"; + + pinctrl-0 = <&hsuart_pins &btcoex_pins &btrstint_pins>; + pinctrl-names = "default"; + + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; +}; + +&blsp1_spi1 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + + partition@0 { + label = "0:SBL1"; + reg = <0x00000000 0x000c0000>; + read-only; + }; + + partition@c0000 { + label = "0:MIBIB"; + reg = <0x000c0000 0x00010000>; + read-only; + }; + + partition@d0000 { + label = "0:BOOTCONFIG"; + reg = <0x000d0000 0x00020000>; + }; + + partition@f0000 { + label = "0:BOOTCONFIG1"; + reg = <0x000f0000 0x00020000>; + }; + + partition@110000 { + label = "0:QSEE"; + reg = <0x00110000 0x001a0000>; + read-only; + }; + + partition@2b0000 { + label = "0:QSEE_1"; + reg = <0x002b0000 0x001a0000>; + read-only; + }; + + partition@450000 { + label = "0:DEVCFG"; + reg = <0x00450000 0x00010000>; + read-only; + }; + + partition@460000 { + label = "0:DEVCFG_1"; + reg = <0x00460000 0x00010000>; + read-only; + }; + + partition@470000 { + label = "0:RPM"; + reg = <0x00470000 0x00040000>; + read-only; + }; + + partition@4b0000 { + label = "0:RPM_1"; + reg = <0x004b0000 0x00040000>; + read-only; + }; + + partition@4f0000 { + label = "0:CDT"; + reg = <0x004f0000 0x00010000>; + read-only; + }; + + partition@500000 { + label = "0:CDT_1"; + reg = <0x00500000 0x00010000>; + read-only; + }; + + partition@510000 { + label = "0:APPSBLENV"; + reg = <0x00510000 0x00010000>; + }; + + partition@520000 { + label = "0:APPSBL"; + reg = <0x00520000 0x000a0000>; + read-only; + }; + + partition@5c0000 { + label = "0:APPSBL_1"; + reg = <0x005c0000 0x000a0000>; + read-only; + }; + + partition@660000 { + label = "0:ART"; + reg = <0x00660000 0x00040000>; + + nvmem-layout { + compatible = "fixed-layout"; + + macaddr_lan: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_wan: macaddr@0 { + reg = <0x0 0x6>; + }; + }; + }; + }; + }; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + reset-post-delay-us = <50000>; + + ethernet-phy-package@0 { + compatible = "qcom,qca8075-package"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + qca8072_3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + + qca8072_4: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&switch { + status = "okay"; + + switch_lan_bmp = ; + switch_wan_bmp = ; + switch_mac_mode = ; + + qcom,port_phyinfo { + port@4 { + port_id = <4>; + phy_address = <3>; + }; + + port@5 { + port_id = <5>; + phy_address = <4>; + }; + }; +}; + +&edma { + status = "okay"; +}; + +&dp4 { + status = "okay"; + + phy-handle = <&qca8072_3>; + label = "lan"; + nvmem-cells = <&macaddr_lan>; + nvmem-cell-names = "mac-address"; +}; + +&dp5 { + status = "okay"; + + phy-handle = <&qca8072_4>; + label = "wan"; + nvmem-cells = <&macaddr_wan>; + nvmem-cell-names = "mac-address"; +}; + +&wifi { + status = "okay"; + + qcom,ath11k-fw-memory-mode = <1>; + qcom,ath11k-calibration-variant = "ALFA-Network-AP120C-AX"; +}; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-cmiot.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-cmiot.dtsi index b9ce0b7c6f..9e43ecfd9d 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-cmiot.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-cmiot.dtsi @@ -152,7 +152,10 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-fap650.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-fap650.dts index b24c4faea8..4c4ac01da0 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-fap650.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-fap650.dts @@ -201,16 +201,14 @@ status = "okay"; flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { reg = <0x00000000 0x000c0000>; @@ -299,6 +297,8 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; @@ -306,8 +306,6 @@ partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "rootfs"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-glinet.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-glinet.dtsi index f6738ab30c..0c9fe8fabb 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-glinet.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-glinet.dtsi @@ -121,17 +121,16 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; - #address-cells = <1>; - #size-cells = <1>; partitions: partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -187,8 +186,6 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; macaddr_wan: macaddr@0 { reg = <0x0 0x6>; @@ -200,8 +197,6 @@ }; }; - /* rootfs defined in variant dts */ - partition@7d00000 { label = "0:ethphyfw"; reg = <0x7d00000 0x0080000>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-mr7350.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-mr7350.dts index fe9669e0a6..52ee3ed051 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-mr7350.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-mr7350.dts @@ -162,26 +162,23 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "qcom,smem-part"; - #address-cells = <1>; - #size-cells = <1>; partition-0-devinfo { label = "devinfo"; read-only; - #address-cells = <1>; - #size-cells = <1>; nvmem-layout { compatible = "ascii-eq-delim-env"; - #address-cells = <1>; - #size-cells = <1>; hw_mac_addr: hw_mac_addr { compatible = "mac-base"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-xiaomi.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-xiaomi.dtsi index 8893c1632b..cfc4f3ceb2 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-xiaomi.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-xiaomi.dtsi @@ -89,7 +89,10 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-mango-dvk.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-mango-dvk.dts index b9afcbe762..4efb49019e 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-mango-dvk.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-mango-dvk.dts @@ -96,16 +96,14 @@ pinctrl-names = "default"; flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <25000000>; #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <25000000>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:SBL1"; @@ -153,8 +151,6 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; macaddr_eth0: macaddr@0 { reg = <0x0 0x6>; @@ -290,6 +286,8 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; @@ -297,8 +295,6 @@ partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "nand_data"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-mr7500.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-mr7500.dts index 76619fcd19..a40530eec0 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-mr7500.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-mr7500.dts @@ -453,26 +453,23 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "qcom,smem-part"; - #address-cells = <1>; - #size-cells = <1>; partition-0-devinfo { label = "devinfo"; read-only; - #address-cells = <1>; - #size-cells = <1>; nvmem-layout { compatible = "ascii-eq-delim-env"; - #address-cells = <1>; - #size-cells = <1>; hw_mac_addr: hw_mac_addr { compatible = "mac-base"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-tplink.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-tplink.dtsi index 55e8ec3d7a..2521329759 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-tplink.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-tplink.dtsi @@ -137,6 +137,8 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-wax214.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-wax214.dts index fc77d12922..99125faccb 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-wax214.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-wax214.dts @@ -144,6 +144,8 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-wax610-base.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-wax610-base.dtsi index 8eb5dbb120..b058b21397 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-wax610-base.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-wax610-base.dtsi @@ -171,7 +171,10 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-xe3-4.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-xe3-4.dts index b0c95c5f79..9607cef3df 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-xe3-4.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-xe3-4.dts @@ -223,27 +223,21 @@ }; &blsp1_spi1 { - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; status = "okay"; + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + linux,modalias = "m25p80", "mx30uf2g18ac", "n25q128a11"; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; reg = <0>; - /* - * U-boot looks for "n25q128a11" node, - * if we don't have it, it will spit out the following warning: - * "ipq: fdt fixup unable to find compatible node". - */ - linux,modalias = "m25p80", "mx30uf2g18ac", "n25q128a11"; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:SBL1"; @@ -367,6 +361,8 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; @@ -374,8 +370,6 @@ partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "rootfs"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-nowifi.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-nowifi.dtsi index b9f172f541..402ac835b2 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-nowifi.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-nowifi.dtsi @@ -1,19 +1,19 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "ipq6018.dtsi" - -&q6_region { - reg = <0x0 0x4ab00000 0x0 0x1000000>; -}; - -&q6_etr_region { - reg = <0x0 0x4bb00000 0x0 0x100000>; -}; - -&m3_dump_region { - reg = <0x0 0x4bc00000 0x0 0x100000>; -}; - -&ramoops_region { - reg = <0x0 0x4bd00000 0x0 0x100000>; -}; +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "ipq6018.dtsi" + +&q6_region { + reg = <0x0 0x4ab00000 0x0 0x1000000>; +}; + +&q6_etr_region { + reg = <0x0 0x4bb00000 0x0 0x100000>; +}; + +&m3_dump_region { + reg = <0x0 0x4bc00000 0x0 0x100000>; +}; + +&ramoops_region { + reg = <0x0 0x4bd00000 0x0 0x100000>; +}; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-cax1800.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-cax1800.dts index e211e0939e..271110a660 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-cax1800.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-cax1800.dts @@ -86,15 +86,16 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "rootfs"; @@ -112,17 +113,15 @@ cs-select = <0>; m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; use-default-sizes; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-rm2-6.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-rm2-6.dts index 876d2d90c9..d857b61950 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-rm2-6.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-rm2-6.dts @@ -105,7 +105,10 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <8>; nand-ecc-step-size = <512>; nand-bus-width = <8>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ap8220.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ap8220.dts index 5051782339..7bd428aa01 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ap8220.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ap8220.dts @@ -38,15 +38,13 @@ flash@0 { compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; reg = <0>; - spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -125,9 +123,9 @@ status = "okay"; nand@0 { - reg = <0>; #address-cells = <1>; #size-cells = <1>; + reg = <0>; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-eap102.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-eap102.dts index 6d6d72cfb0..3c10e9be82 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-eap102.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-eap102.dts @@ -28,15 +28,13 @@ flash@0 { compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; reg = <0>; - spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -176,15 +174,16 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <8>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "rootfs1"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-mf269.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-mf269.dts index 7ad1c8987b..696264a774 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-mf269.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-mf269.dts @@ -105,15 +105,13 @@ flash@0 { compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; reg = <0>; - spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -246,30 +244,21 @@ &qpic_nand { status = "okay"; - /* - * Bootloader will find the NAND DT node by the compatible and - * then "fixup" it by adding the partitions from the SMEM table - * using the legacy bindings thus making it impossible for us - * to change the partition table or utilize NVMEM for calibration. - * So add a dummy partitions node that bootloader will populate - * and set it as disabled so the kernel ignores it instead of - * printing warnings due to the broken way bootloader adds the - * partitions. - */ partitions { status = "disabled"; }; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "fota-flag"; @@ -284,8 +273,6 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; macaddr_mac_0: macaddr@0 { compatible = "mac-base"; @@ -330,12 +317,6 @@ read-only; }; - /* rootfs partition is the result of squashing - * consecutive stock partitions: - * - openwrt_data (25 MiB) - * - data (30 MiB) - * - fota (99 MiB) - */ partition@5fc0000 { label = "rootfs"; reg = <0x5fc0000 0x9a00000>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-xiaomi.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-xiaomi.dtsi index 2d6dcc5630..2c9d24d5e3 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-xiaomi.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-xiaomi.dtsi @@ -59,30 +59,21 @@ &qpic_nand { status = "okay"; - /* - * Bootloader will find the NAND DT node by the compatible and - * then "fixup" it by adding the partitions from the SMEM table - * using the legacy bindings thus making it impossible for us - * to change the partition table or utilize NVMEM for calibration. - * So add a dummy partitions node that bootloader will populate - * and set it as disabled so the kernel ignores it instead of - * printing warnings due to the broken way bootloader adds the - * partitions. - */ partitions { status = "disabled"; }; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -138,8 +129,6 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; macaddr_dp2: macaddr@6 { reg = <0x6 0x6>; @@ -169,20 +158,15 @@ }; partition@900000 { - /* This is crash + crash_syslog parts combined */ label = "pstore"; reg = <0x900000 0x100000>; }; - /* Make the first rootfs a dedicated ubi partition for kernel */ partition@a00000 { label = "ubi_kernel"; reg = <0xa00000 0x23c0000>; }; - /* Place the real rootfs in the original second rootfs and - * expand it to the end of the nand - */ rootfs: partition@2dc0000 { label = "rootfs"; reg = <0x2dc0000 0xd240000>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts index b5e249f72f..4558fff913 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts @@ -194,16 +194,14 @@ cs-gpios = <0>; flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -270,8 +268,6 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; aqr0_fw: firmware@0 { reg = <0x0 0x5fc02>; @@ -285,8 +281,6 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; aqr1_fw: firmware@0 { reg = <0x0 0x5fc02>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-aw1000.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-aw1000.dts index 938882fe4f..3232651d7e 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-aw1000.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-aw1000.dts @@ -187,7 +187,10 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <8>; nand-ecc-step-size = <512>; nand-bus-width = <8>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts index e69283cc0e..3aabe28f20 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts @@ -90,16 +90,14 @@ status = "okay"; flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -226,15 +224,16 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "rootfs_1"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts index a43b85c8b7..b7f8a3fdc4 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts @@ -128,30 +128,21 @@ &qpic_nand { status = "okay"; - /* - * Bootloader will find the NAND DT node by the compatible and - * then "fixup" it by adding the partitions from the SMEM table - * using the legacy bindings thus making it impossible for us - * to change the partition table or utilize NVMEM for calibration. - * So add a dummy partitions node that bootloader will populate - * and set it as disabled so the kernel ignores it instead of - * printing warnings due to the broken way bootloader adds the - * partitions. - */ partitions { status = "disabled"; }; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -261,8 +252,6 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; macaddr_dp1: macaddr@0 { reg = <0x0 0x6>; @@ -296,7 +285,6 @@ }; partition@1080000 { - /* This is crash + crash_syslog parts combined */ label = "pstore"; reg = <0x1080000 0x100000>; }; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-dl-wrx36.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-dl-wrx36.dts index db135c0670..3cac058370 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-dl-wrx36.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-dl-wrx36.dts @@ -91,7 +91,10 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <8>; nand-ecc-step-size = <512>; nand-bus-width = <8>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts index c66b42e532..f18861a757 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts @@ -88,11 +88,11 @@ cs-gpios = <0>; flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; partitions { compatible = "qcom,smem-part"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx5300.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx5300.dts index b84c0d9458..b8ea07bdd2 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx5300.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx5300.dts @@ -33,7 +33,7 @@ chosen { stdout-path = "serial0:115200n8"; - bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro"; + bootargs-append = " root=/dev/ubiblock0_0"; }; keys { @@ -109,33 +109,21 @@ &qpic_nand { status = "okay"; - /* - * Bootloader will find the NAND DT node by the compatible and - * then "fixup" it by adding the partitions from the SMEM table - * using the legacy bindings thus making it impossible for us - * to change the partition table or utilize NVMEM for calibration. - * So add a dummy partitions node that bootloader will populate - * and set it as disabled so the kernel ignores it instead of - * printing warnings due to the broken way bootloader adds the - * partitions. - */ partitions { status = "disabled"; }; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; - #address-cells = <1>; - #size-cells = <1>; - partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -245,8 +233,6 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; caldata_qca9984: caldata@33000 { reg = <0x33000 0x2f20>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx8500.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx8500.dts index 64a4aec0ac..d4975aa403 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx8500.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx8500.dts @@ -28,7 +28,7 @@ chosen { stdout-path = "serial0:115200n8"; - bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro"; + bootargs-append = " root=/dev/ubiblock0_0"; }; gpio-export { @@ -79,33 +79,21 @@ &qpic_nand { status = "okay"; - /* - * Bootloader will find the NAND DT node by the compatible and - * then "fixup" it by adding the partitions from the SMEM table - * using the legacy bindings thus making it impossible for us - * to change the partition table or utilize NVMEM for calibration. - * So add a dummy partitions node that bootloader will populate - * and set it as disabled so the kernel ignores it instead of - * printing warnings due to the broken way bootloader adds the - * partitions. - */ partitions { status = "disabled"; }; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; - #address-cells = <1>; - #size-cells = <1>; - partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -263,8 +251,6 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; aqr_fw: firmware@0 { /* Skip the QCOM MBN Header of 40 bytes */ diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-tplink.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-tplink.dtsi index bf511a1fcf..bea031a754 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-tplink.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-tplink.dtsi @@ -68,7 +68,10 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax218.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax218.dts index ec78cf3839..4f504aa9d5 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax218.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax218.dts @@ -152,7 +152,10 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; @@ -164,8 +167,6 @@ compatible = "fixed-partitions"; label = "0:appsblenv"; read-only; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "env-data"; @@ -174,8 +175,7 @@ nvmem-layout { compatible = "u-boot,env"; - macaddr_ubootenv_ethaddr: ethaddr { - }; + macaddr_ubootenv_ethaddr: ethaddr {}; }; }; }; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax620.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax620.dts index 15643250c3..fbccc65931 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax620.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax620.dts @@ -177,7 +177,10 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts index f90c3e594a..4ec2272b95 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts @@ -115,16 +115,14 @@ status = "okay"; flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -246,15 +244,16 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <8>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "rootfs"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-zbt-z800ax.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-zbt-z800ax.dts index 2353c55607..21e4ffce5c 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-zbt-z800ax.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-zbt-z800ax.dts @@ -122,15 +122,13 @@ flash@0 { compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; reg = <0>; - spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -254,15 +252,16 @@ }; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <8>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "rootfs"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-deco-x80-5g.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-deco-x80-5g.dts index d58c98b7df..97fc3f7ed6 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-deco-x80-5g.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-deco-x80-5g.dts @@ -332,14 +332,16 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { - compatible = "qcom,smem-part"; /* define SMEM partition table */ - + compatible = "qcom,smem-part"; }; }; }; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts index cc6f9198ce..e82b54c4de 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts @@ -66,16 +66,14 @@ cs-gpios = <0>; flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -199,8 +197,6 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; aqr_fw: aqr-fw@0 { /* Skip the QCOM MBN Header of 40 bytes */ diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-netgear.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-netgear.dtsi index 51ca496595..da5a1d7226 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-netgear.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-netgear.dtsi @@ -145,30 +145,21 @@ &qpic_nand { status = "okay"; - /* - * Bootloader will find the NAND DT node by the compatible and - * then "fixup" it by adding the partitions from the SMEM table - * using the legacy bindings thus making it impossible for us - * to change the partition table or utilize NVMEM for calibration. - * So add a dummy partitions node that bootloader will populate - * and set it as disabled so the kernel ignores it instead of - * printing warnings due to the broken way bootloader adds the - * partitions. - */ partitions { status = "disabled"; }; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -294,8 +285,6 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; macaddr_boarddata1_0: macaddr@0 { reg = <0x0 0x6>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nowifi.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nowifi.dtsi index 36bc8a7c54..1192c9cb78 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nowifi.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nowifi.dtsi @@ -1,19 +1,19 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "ipq8074.dtsi" - -&q6_region { - reg = <0x0 0x4b000000 0x0 0x1000000>; -}; - -&q6_etr_region { - reg = <0x0 0x4c000000 0x0 0x100000>; -}; - -&m3_dump_region { - reg = <0x0 0x4c100000 0x0 0x100000>; -}; - -&ramoops_region { - reg = <0x0 0x4c200000 0x0 0x100000>; -}; +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "ipq8074.dtsi" + +&q6_region { + reg = <0x0 0x4b000000 0x0 0x1000000>; +}; + +&q6_etr_region { + reg = <0x0 0x4c000000 0x0 0x100000>; +}; + +&m3_dump_region { + reg = <0x0 0x4c100000 0x0 0x100000>; +}; + +&ramoops_region { + reg = <0x0 0x4c200000 0x0 0x100000>; +}; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts index dddf534907..aa9b6583a7 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts @@ -308,15 +308,16 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; @@ -444,8 +445,6 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; macaddr_lan: macaddr@0 { reg = <0x0 0x6>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rt-ax89x.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rt-ax89x.dts index a21a8c69ff..71ae6fe311 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rt-ax89x.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rt-ax89x.dts @@ -337,15 +337,16 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wax630.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wax630.dts index d7d5629588..8d13c944c4 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wax630.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wax630.dts @@ -234,7 +234,10 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts index ffaec27317..738b95d502 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts @@ -164,7 +164,10 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; @@ -176,8 +179,6 @@ compatible = "fixed-partitions"; label = "0:appsblenv"; read-only; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "env-data"; @@ -186,8 +187,7 @@ nvmem-layout { compatible = "u-boot,env"; - macaddr_appsblenv_ethaddr: ethaddr { - }; + macaddr_appsblenv_ethaddr: ethaddr {}; }; }; }; @@ -197,18 +197,9 @@ &mdio { status = "okay"; + pinctrl-0 = <&mdio_pins>; pinctrl-names = "default"; - /* - * RESET pins of phy chips - * - * WXR-5950AX12 has 2x RESET pins for QCA8075 and AQR113C. - * The pin of QCA8075 is for the chip and not phys in the chip, the - * pin of AQR113C is for 2x chips. So both pins are not appropriate - * to declare them as reset-gpios in phy nodes. - * Multiple entries in reset-gpios of mdio may not be supported, but - * leave the following as-is to show that the those reset pin exists. - */ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>, <&tlmm 63 GPIO_ACTIVE_LOW>; aqr113c_1: ethernet-phy@0 { diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-homewrk.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-homewrk.dts index ebeeb313e4..c9911bcf42 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-homewrk.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-homewrk.dts @@ -22,13 +22,12 @@ status = "okay"; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; - /* - * Some devices use Micron NAND with with 8 bit ECC - * other AMD/Spansion NAND with 4 bit ECC - *nand-ecc-strength = <4>; - *nand-ecc-step-size = <512>; - */ + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4200.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4200.dtsi index 39c339d176..def4e1d025 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4200.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4200.dtsi @@ -37,30 +37,21 @@ &qpic_nand { status = "okay"; - /* - * Bootloader will find the NAND DT node by the compatible and - * then "fixup" it by adding the partitions from the SMEM table - * using the legacy bindings thus making it impossible for us - * to change the partition table or utilize NVMEM for calibration. - * So add a dummy partitions node that bootloader will populate - * and set it as disabled so the kernel ignores it instead of - * printing warnings due to the broken way bootloader adds the - * partitions. - */ partitions { status = "disabled"; }; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; + nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4300.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4300.dts index 672902ea94..919fe6ea99 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4300.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4300.dts @@ -25,34 +25,21 @@ &qpic_nand { status = "okay"; - /* - * Bootloader will find the NAND DT node by the compatible and - * then "fixup" it by adding the partitions from the SMEM table - * using the legacy bindings thus making it impossible for us - * to change the partition table or utilize NVMEM for calibration. - * So add a dummy partitions node that bootloader will populate - * and set it as disabled so the kernel ignores it instead of - * printing warnings due to the broken way bootloader adds the - * partitions. - */ partitions { status = "disabled"; }; nand@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; - /* - * Some devices use Micron NAND with with 8 bit ECC - * other AMD/Spansion NAND with 4 bit ECC - *nand-ecc-strength = <4>; - *nand-ecc-step-size = <512>; - */ + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; partition@0 { label = "0:sbl1"; diff --git a/target/linux/qualcommax/image/ipq60xx.mk b/target/linux/qualcommax/image/ipq60xx.mk index 7278f79db5..31d0422fe5 100644 --- a/target/linux/qualcommax/image/ipq60xx.mk +++ b/target/linux/qualcommax/image/ipq60xx.mk @@ -23,6 +23,19 @@ define Device/8devices_mango-dvk endef TARGET_DEVICES += 8devices_mango-dvk +define Device/alfa-network_ap120c-ax + $(call Device/FitImage) + $(call Device/UbiFit) + DEVICE_VENDOR := ALFA Network + DEVICE_MODEL := AP120C-AX + BLOCKSIZE := 128k + PAGESIZE := 2048 + SOC := ipq6000 + DEVICE_DTS_CONFIG := config@cp03-c1 + DEVICE_PACKAGES := ipq-wifi-alfa-network_ap120c-ax +endef +TARGET_DEVICES += alfa-network_ap120c-ax + define Device/cambiumnetworks_xe3-4 $(call Device/FitImage) $(call Device/UbiFit) @@ -30,8 +43,8 @@ define Device/cambiumnetworks_xe3-4 DEVICE_MODEL := XE3-4 BLOCKSIZE := 128k PAGESIZE := 2048 - DEVICE_DTS_CONFIG := config@cp01-c3-xv3-4 SOC := ipq6010 + DEVICE_DTS_CONFIG := config@cp01-c3-xv3-4 DEVICE_PACKAGES := ipq-wifi-cambiumnetworks_xe34 ath11k-firmware-qcn9074 kmod-ath11k-pci endef TARGET_DEVICES += cambiumnetworks_xe3-4 @@ -42,8 +55,8 @@ define Device/glinet_gl-common DEVICE_VENDOR := GL.iNet BLOCKSIZE := 128k PAGESIZE := 2048 - DEVICE_DTS_CONFIG := config@cp03-c1 SOC := ipq6000 + DEVICE_DTS_CONFIG := config@cp03-c1 IMAGES += factory.bin IMAGE/factory.bin := append-ubi | append-gl-metadata endef @@ -78,9 +91,9 @@ endef define Device/linksys_mr7350 $(call Device/linksys_mr) DEVICE_MODEL := MR7350 + SOC := ipq6000 NAND_SIZE := 256m IMAGE_SIZE := 75776k - SOC := ipq6000 DEVICE_PACKAGES += ipq-wifi-linksys_mr7350 kmod-leds-pca963x endef TARGET_DEVICES += linksys_mr7350 @@ -91,9 +104,7 @@ define Device/linksys_mr7500 SOC := ipq6010 NAND_SIZE := 512m IMAGE_SIZE := 147456k - DEVICE_PACKAGES += ipq-wifi-linksys_mr7500 \ - ath11k-firmware-qcn9074 kmod-ath11k-pci \ - kmod-leds-pwm kmod-phy-aquantia + DEVICE_PACKAGES += ipq-wifi-linksys_mr7500 ath11k-firmware-qcn9074 kmod-ath11k-pci kmod-leds-pwm kmod-phy-aquantia endef TARGET_DEVICES += linksys_mr7500 @@ -104,8 +115,8 @@ define Device/netgear_wax214 DEVICE_MODEL := WAX214 BLOCKSIZE := 128k PAGESIZE := 2048 - DEVICE_DTS_CONFIG := config@cp03-c1 SOC := ipq6010 + DEVICE_DTS_CONFIG := config@cp03-c1 DEVICE_PACKAGES := ipq-wifi-netgear_wax214 endef TARGET_DEVICES += netgear_wax214 @@ -115,8 +126,8 @@ define Device/netgear_wax610-common DEVICE_VENDOR := Netgear BLOCKSIZE := 128k PAGESIZE := 2048 - DEVICE_DTS_CONFIG := config@cp03-c1 SOC := ipq6010 + DEVICE_DTS_CONFIG := config@cp03-c1 KERNEL_IN_UBI := 1 IMAGES += ui-factory.tar IMAGE/ui-factory.tar := append-ubi | qsdk-ipq-factory-nand | pad-to 4096 | wax610-netgear-tar @@ -156,6 +167,7 @@ define Device/tplink_eap6xx-common BLOCKSIZE := 128k PAGESIZE := 2048 SOC := ipq6010 + DEVICE_DTS_CONFIG := config@cp03-c1 DEVICE_PACKAGES := kmod-phy-realtek IMAGES += web-ui-factory.bin IMAGE/web-ui-factory.bin := append-ubi | tplink-image-2022 @@ -202,8 +214,8 @@ define Device/yuncore_fap650 DEVICE_MODEL := FAP650 BLOCKSIZE := 128k PAGESIZE := 2048 - DEVICE_DTS_CONFIG := config@cp03-c1 SOC := ipq6000 + DEVICE_DTS_CONFIG := config@cp03-c1 DEVICE_PACKAGES := ipq-wifi-yuncore_fap650 IMAGES := factory.ubi factory.ubin sysupgrade.bin IMAGE/factory.ubin := append-ubi | qsdk-ipq-factory-nand @@ -267,8 +279,8 @@ define Device/redmi_ax5-jdcloud $(call Device/EmmcImage) DEVICE_VENDOR := Redmi DEVICE_MODEL := AX5 JDCloud - BLOCKSIZE := 128k KERNEL_SIZE := 6144k + BLOCKSIZE := 128k SOC := ipq6000 DEVICE_DTS_CONFIG := config@cp03-c1 DEVICE_PACKAGES := ipq-wifi-redmi_ax5-jdcloud @@ -281,8 +293,8 @@ define Device/link_nn6000-v1 $(call Device/EmmcImage) DEVICE_VENDOR := Link DEVICE_MODEL := NN6000 v1 - BLOCKSIZE := 128k KERNEL_SIZE := 6144k + BLOCKSIZE := 128k SOC := ipq6000 DEVICE_DTS_CONFIG := config@cp03-c2 DEVICE_PACKAGES := ipq-wifi-link_nn6000 @@ -301,8 +313,8 @@ define Device/jdcloud_re-ss-01 $(call Device/EmmcImage) DEVICE_VENDOR := JDCloud DEVICE_MODEL := RE-SS-01 - BLOCKSIZE := 128k KERNEL_SIZE := 6144k + BLOCKSIZE := 128k SOC := ipq6000 DEVICE_DTS_CONFIG := config@cp03-c2 DEVICE_PACKAGES := ipq-wifi-jdcloud_re-ss-01 @@ -315,8 +327,8 @@ define Device/jdcloud_re-cs-02 $(call Device/EmmcImage) DEVICE_VENDOR := JDCloud DEVICE_MODEL := RE-CS-02 - BLOCKSIZE := 128k KERNEL_SIZE := 6144k + BLOCKSIZE := 128k SOC := ipq6010 DEVICE_DTS_CONFIG := config@cp03-c3 DEVICE_PACKAGES := ipq-wifi-jdcloud_re-cs-02 ath11k-firmware-qcn9074 kmod-ath11k-pci luci-app-athena-led luci-i18n-athena-led-zh-cn @@ -329,8 +341,8 @@ define Device/jdcloud_re-cs-07 $(call Device/EmmcImage) DEVICE_VENDOR := JDCloud DEVICE_MODEL := RE-CS-07 - BLOCKSIZE := 128k KERNEL_SIZE := 6144k + BLOCKSIZE := 128k SOC := ipq6010 DEVICE_DTS_CONFIG := config@cp03-c4 DEVICE_PACKAGES := -ath11k-firmware-ipq6018 -ath11k-firmware-qcn9074 -kmod-ath11k -kmod-ath11k-ahb -kmod-ath11k-pci -hostapd-common -wpad-openssl diff --git a/target/linux/qualcommax/ipq60xx/base-files/etc/board.d/02_network b/target/linux/qualcommax/ipq60xx/base-files/etc/board.d/02_network index dedb5f4660..5f33c5bd91 100755 --- a/target/linux/qualcommax/ipq60xx/base-files/etc/board.d/02_network +++ b/target/linux/qualcommax/ipq60xx/base-files/etc/board.d/02_network @@ -16,6 +16,9 @@ ipq60xx_setup_interfaces() glinet,gl-axt1800) ucidef_set_interfaces_lan_wan "lan1 lan2" "wan" ;; + alfa-network,ap120c-ax) + ucidef_set_interfaces_lan_wan "lan" "wan" + ;; cambiumnetworks,xe3-4) ucidef_set_interface_lan "lan1 lan2" "dhcp" ;; @@ -59,6 +62,9 @@ ipq60xx_setup_macs() local label_mac="" case "$board" in + alfa-network,ap120c-ax) + label_mac=$(mtd_get_mac_binary 0:ART 12) + ;; qihoo,360v6) wan_mac=$(mtd_get_mac_ascii factory lanMac) lan_mac=$(macaddr_add "$wan_mac" 1) diff --git a/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata b/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata index 3b035c3172..d2b7a1621d 100755 --- a/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata +++ b/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata @@ -9,7 +9,8 @@ board=$(board_name) case "$FIRMWARE" in "ath11k/IPQ6018/hw1.0/cal-ahb-c000000.wifi.bin") case "$board" in - 8devices,mango-dvk) + 8devices,mango-dvk|\ + alfa-network,ap120c-ax) caldata_extract "0:ART" 0x1000 0x20000 ;; cambiumnetworks,xe3-4) diff --git a/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 01a7d6e165..3a6ad702f7 100755 --- a/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -10,9 +10,14 @@ PHYNBR=${DEVPATH##*/phy} board=$(board_name) case "$board" in + alfa-network,ap120c-ax) + label_mac=$(mtd_get_mac_binary 0:ART 12) + [ "$PHYNBR" = "0" ] && macaddr_add $label_mac 1 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $label_mac 2 > /sys${DEVPATH}/macaddress + ;; cmiot,ax18|\ zn,m2) - label_mac=$(mtd_get_mac_binary "0:art" 0x6) + label_mac=$(mtd_get_mac_binary 0:art 0x6) [ "$PHYNBR" = "0" ] && macaddr_add $label_mac 1 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $label_mac 2 > /sys${DEVPATH}/macaddress ;; @@ -24,7 +29,7 @@ case "$board" in ;; link,nn6000-v1|\ link,nn6000-v2) - label_mac=$(mmc_get_mac_binary "0:ART" 0x18) + label_mac=$(mmc_get_mac_binary 0:ART 0x18) [ "$PHYNBR" = "0" ] && macaddr_add $label_mac 1 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $label_mac 2 > /sys${DEVPATH}/macaddress ;; diff --git a/target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh b/target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh index 24bea6d123..aaea427f9b 100755 --- a/target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh +++ b/target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh @@ -104,8 +104,43 @@ EOF fw_setenv --script /tmp/env_tmp } +alfa_bootconfig_rootfs_rotate() { + local part="$1" + local offs="$2" + + local mtdnum=$(find_mtd_index "$part") + [ -c "/dev/mtd${mtdnum}" ] || return 1 + + dd if=/dev/mtd${mtdnum} of=/tmp/mtd${mtdnum} bs=1k > /dev/null 2>&1 + + local active="$(dd if=/tmp/mtd${mtdnum} bs=1 skip=${offs} count=1 2>/dev/null)" + active=$(printf "%d\n" "\"$active") + + if [ "$active" = "1" ]; then + printf '\x00' | dd of=/tmp/mtd${mtdnum} \ + conv=notrunc bs=1 seek=${offs} > /dev/null 2>&1 + else + printf '\x01' | dd of=/tmp/mtd${mtdnum} \ + conv=notrunc bs=1 seek=${offs} > /dev/null 2>&1 + fi + + mtd -qq write /tmp/mtd${mtdnum} /dev/mtd${mtdnum} 2>/dev/null + + local mtdnum_sec=$(find_mtd_index "${part}1") + [ -c "/dev/mtd${mtdnum_sec}" ] && \ + mtd -qq write \ + /tmp/mtd${mtdnum} /dev/mtd${mtdnum_sec} 2>/dev/null + + return 0 +} + platform_do_upgrade() { case "$(board_name)" in + alfa-network,ap120c-ax) + CI_UBIPART="rootfs_1" + alfa_bootconfig_rootfs_rotate "0:BOOTCONFIG" "148" + nand_do_upgrade "$1" + ;; cambiumnetworks,xe3-4) fw_setenv bootcount 0 nand_do_upgrade "$1" diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network index dd96ec8673..2e6382c62f 100755 --- a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network +++ b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network @@ -84,7 +84,7 @@ ipq807x_setup_macs() case "$board" in aliyun,ap8220) - wan_mac=$(cat /dev/mtd12 | awk -F '\t' '/product.mac/{print $2}') + wan_mac=$(cat $(find_mtd_part product_info) | awk -F '\t' '/product.mac/{print $2}') lan_mac=$(macaddr_add $wan_mac 1) label_mac=$wan_mac ;; @@ -113,7 +113,7 @@ ipq807x_setup_macs() label_mac=$wan_mac ;; verizon,cr1000a) - wan_mac=$(mmc_get_mac_ascii "0:APPSBLENV" baseMAC) + wan_mac=$(mmc_get_mac_ascii 0:APPSBLENV baseMAC) lan_mac=$(macaddr_add "$wan_mac" 1) label_mac=$wan_mac ;; diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index cb7cdb7b4d..a62d25582a 100755 --- a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -11,7 +11,7 @@ board=$(board_name) case "$board" in aliyun,ap8220) - label_mac=$(cat /dev/mtd12 | awk -F '\t' '/product.mac/{print $2}') + label_mac=$(cat $(find_mtd_part product_info) | awk -F '\t' '/product.mac/{print $2}') [ "$PHYNBR" = "0" ] && macaddr_add $label_mac 2 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $label_mac 3 > /sys${DEVPATH}/macaddress ;; @@ -60,7 +60,7 @@ case "$board" in [ "$PHYNBR" = "1" ] && macaddr_add $label_mac 2 > /sys${DEVPATH}/macaddress ;; verizon,cr1000a) - label_mac=$(mmc_get_mac_ascii "0:APPSBLENV" baseMAC) + label_mac=$(mmc_get_mac_ascii 0:APPSBLENV baseMAC) [ "$PHYNBR" = "0" ] && macaddr_add $label_mac 2 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $label_mac 3 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "2" ] && macaddr_add $label_mac 4 > /sys${DEVPATH}/macaddress diff --git a/target/linux/qualcommax/patches-6.12/0110-arm64-dts-qcom-ipq6018-use-msi-parent-for-PCIe.patch b/target/linux/qualcommax/patches-6.12/0110-arm64-dts-qcom-ipq6018-use-msi-parent-for-PCIe.patch new file mode 100644 index 0000000000..960f1293df --- /dev/null +++ b/target/linux/qualcommax/patches-6.12/0110-arm64-dts-qcom-ipq6018-use-msi-parent-for-PCIe.patch @@ -0,0 +1,21 @@ +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -749,7 +749,7 @@ + interrupts = ; + ranges = <0 0 0 0xb00a000 0 0xffd>; + +- v2m@0 { ++ gic_v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x0 0x0 0xffd>; +@@ -911,8 +911,7 @@ + ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, + <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>; + +- interrupts = ; +- interrupt-names = "msi"; ++ msi-parent = <&gic_v2m0>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; diff --git a/target/linux/qualcommax/patches-6.12/0171-clk-qcom-ipq8074-Support-added-for-necessary-clocks-and-reset.patch b/target/linux/qualcommax/patches-6.12/0171-clk-qcom-ipq8074-Support-added-for-necessary-clocks-and-reset.patch new file mode 100644 index 0000000000..33237037a5 --- /dev/null +++ b/target/linux/qualcommax/patches-6.12/0171-clk-qcom-ipq8074-Support-added-for-necessary-clocks-and-reset.patch @@ -0,0 +1,311 @@ +From 6504bc9edeb1a2a54d813f4bb5d0267e7bf827f9 Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Thu, 6 Feb 2020 17:35:42 +0530 +Subject: [PATCH 4/8] clk: ipq8074: Support added for necessary clocks and + reset + +Change-Id: I21a76a44185f766e9b6dcba274392ea8e599718b +Signed-off-by: Praveenkumar I +Signed-off-by: Rajkumar Ayyasamy +--- + drivers/clk/qcom/gcc-ipq8074.c | 238 ++++++++++++++++++- + include/dt-bindings/clock/qcom,gcc-ipq8074.h | 35 ++- + 2 files changed, 258 insertions(+), 15 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -48,6 +48,22 @@ enum { + P_UNIPHY2_TX, + }; + ++static const char * const gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = { ++ "xo", ++ "gpll4", ++ "gpll0", ++ "gpll6", ++ "gpll0_out_main_div2", ++}; ++ ++static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL4, 1 }, ++ { P_GPLL0, 2 }, ++ { P_GPLL6, 3 }, ++ { P_GPLL0_DIV2, 4 }, ++}; ++ + static struct clk_alpha_pll gpll0_main = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], +@@ -629,6 +645,12 @@ static const struct freq_tbl ftbl_pcie_a + { } + }; + ++struct freq_tbl ftbl_pcie_rchng_clk_src[] = { ++ F(19200000, P_XO, 1, 0, 0), ++ F(100000000, P_GPLL0, 8, 0, 0), ++ { } ++}; ++ + static struct clk_rcg2 pcie0_axi_clk_src = { + .cmd_rcgr = 0x75054, + .freq_tbl = ftbl_pcie_axi_clk_src, +@@ -2031,6 +2053,78 @@ static struct clk_rcg2 gp3_clk_src = { + }, + }; + ++struct freq_tbl ftbl_qdss_tsctr_clk_src[] = { ++ F(160000000, P_GPLL0_DIV2, 2.5, 0, 0), ++ F(320000000, P_GPLL0, 2.5, 0, 0), ++ F(600000000, P_GPLL6, 2, 0, 0), ++ { } ++}; ++ ++struct clk_rcg2 qdss_tsctr_clk_src = { ++ .cmd_rcgr = 0x29064, ++ .freq_tbl = ftbl_qdss_tsctr_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "qdss_tsctr_clk_src", ++ .parent_names = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2, ++ .num_parents = 5, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_fixed_factor qdss_dap_sync_clk_src = { ++ .mult = 1, ++ .div = 4, ++ .hw.init = &(struct clk_init_data){ ++ .name = "qdss_dap_sync_clk_src", ++ .parent_names = (const char *[]){ ++ "qdss_tsctr_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_fixed_factor_ops, ++ }, ++}; ++ ++struct freq_tbl ftbl_qdss_at_clk_src[] = { ++ F(66670000, P_GPLL0_DIV2, 6, 0, 0), ++ F(240000000, P_GPLL6, 6, 0, 0), ++ { } ++}; ++ ++struct clk_rcg2 qdss_at_clk_src = { ++ .cmd_rcgr = 0x2900c, ++ .freq_tbl = ftbl_qdss_at_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "qdss_at_clk_src", ++ .parent_names = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2, ++ .num_parents = 5, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++ ++struct freq_tbl ftbl_adss_pwm_clk_src[] = { ++ F(19200000, P_XO, 1, 0, 0), ++ F(200000000, P_GPLL0, 4, 0, 0), ++ { } ++}; ++ ++struct clk_rcg2 adss_pwm_clk_src = { ++ .cmd_rcgr = 0x1c008, ++ .freq_tbl = ftbl_adss_pwm_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "adss_pwm_clk_src", ++ .parent_data = gcc_xo_gpll0, ++ .num_parents = 2, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ + static struct clk_branch gcc_blsp1_ahb_clk = { + .halt_reg = 0x01008, + .clkr = { +@@ -4226,13 +4320,7 @@ static struct clk_branch gcc_gp3_clk = { + }, + }; + +-static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { +- F(19200000, P_XO, 1, 0, 0), +- F(100000000, P_GPLL0, 8, 0, 0), +- { } +-}; +- +-static struct clk_rcg2 pcie0_rchng_clk_src = { ++struct clk_rcg2 pcie0_rchng_clk_src = { + .cmd_rcgr = 0x75070, + .freq_tbl = ftbl_pcie_rchng_clk_src, + .hid_width = 5, +@@ -4324,6 +4412,114 @@ static const struct alpha_pll_config nss + .alpha_en_mask = BIT(24), + }; + ++static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = { ++ .halt_reg = 0x47014, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x47014, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_snoc_bus_timeout2_ahb_clk", ++ .parent_names = (const char *[]){ ++ "usb0_master_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_bus_timeout3_ahb_clk = { ++ .halt_reg = 0x4701C, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x4701C, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_snoc_bus_timeout3_ahb_clk", ++ .parent_names = (const char *[]){ ++ "usb1_master_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_dcc_clk = { ++ .halt_reg = 0x77004, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x77004, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_dcc_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_at_clk = { ++ .halt_reg = 0x29024, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x29024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_at_clk", ++ .parent_names = (const char *[]){ ++ "qdss_at_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_dap_clk = { ++ .halt_reg = 0x29084, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x29084, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_dap_clk", ++ .parent_names = (const char *[]){ ++ "qdss_dap_sync_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_adss_pwm_clk = { ++ .halt_reg = 0x1c020, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x1c020, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_adss_pwm_clk", ++ .parent_names = (const char *[]){ ++ "adss_pwm_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ + static struct clk_hw *gcc_ipq8074_hws[] = { + &gpll0_out_main_div2.hw, + &gpll6_out_main_div2.hw, +@@ -4332,6 +4528,7 @@ static struct clk_hw *gcc_ipq8074_hws[] + &gcc_xo_div4_clk_src.hw, + &nss_noc_clk_src.hw, + &nss_ppe_cdiv_clk_src.hw, ++ &qdss_dap_sync_clk_src.hw, + }; + + static struct clk_regmap *gcc_ipq8074_clks[] = { +@@ -4563,6 +4760,15 @@ static struct clk_regmap *gcc_ipq8074_cl + [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, + [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, + [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr, ++ [GCC_SNOC_BUS_TIMEOUT2_AHB_CLK] = &gcc_snoc_bus_timeout2_ahb_clk.clkr, ++ [GCC_SNOC_BUS_TIMEOUT3_AHB_CLK] = &gcc_snoc_bus_timeout3_ahb_clk.clkr, ++ [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, ++ [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, ++ [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, ++ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, ++ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, ++ [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr, ++ [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, + }; + + static const struct qcom_reset_map gcc_ipq8074_resets[] = { +--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h +@@ -230,10 +230,19 @@ + #define GCC_GP1_CLK 221 + #define GCC_GP2_CLK 222 + #define GCC_GP3_CLK 223 +-#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 +-#define GCC_PCIE0_RCHNG_CLK_SRC 225 +-#define GCC_PCIE0_RCHNG_CLK 226 +-#define GCC_CRYPTO_PPE_CLK 227 ++#define GCC_CRYPTO_PPE_CLK 224 ++#define GCC_PCIE0_RCHNG_CLK_SRC 225 ++#define GCC_PCIE0_RCHNG_CLK 226 ++#define GCC_PCIE0_AXI_S_BRIDGE_CLK 227 ++#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 228 ++#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 229 ++#define GCC_DCC_CLK 230 ++#define ADSS_PWM_CLK_SRC 231 ++#define GCC_ADSS_PWM_CLK 232 ++#define QDSS_TSCTR_CLK_SRC 233 ++#define QDSS_AT_CLK_SRC 234 ++#define GCC_QDSS_AT_CLK 235 ++#define GCC_QDSS_DAP_CLK 236 + + #define GCC_BLSP1_BCR 0 + #define GCC_BLSP1_QUP1_BCR 1 diff --git a/target/linux/qualcommax/patches-6.12/0172-clk-qcom-ipq8074-Fix-gcc_blsp1_ahb_clk-properties.patch b/target/linux/qualcommax/patches-6.12/0172-clk-qcom-ipq8074-Fix-gcc_blsp1_ahb_clk-properties.patch new file mode 100644 index 0000000000..6e4adf685b --- /dev/null +++ b/target/linux/qualcommax/patches-6.12/0172-clk-qcom-ipq8074-Fix-gcc_blsp1_ahb_clk-properties.patch @@ -0,0 +1,41 @@ +From 52315bec6ed633b6a71f28b746029602f8bd70b9 Mon Sep 17 00:00:00 2001 +From: Balaji Prakash J +Date: Wed, 22 Apr 2020 20:35:30 +0530 +Subject: [PATCH] clk: ipq8074: fix gcc_blsp1_ahb_clk properties + +All the voting enabled clocks does not support the enable +from CBCR register. So, updated gcc_blsp1_ahb_clk enable +register and mask to enable bit in APCS_CLOCK_BRANCH_ENA_VOTE. + +Also, the voting controlled clocks are shared among multiple +components like APSS, RPM, NSS, TZ, etc. So, turning the +voting off from APSS does not make the clock off if it has +been voted from another component. Added the flag +BRANCH_HALT_VOTED in order to skip checking the clock +disable status. + +This change is referred from the below commits, +1. 246b4fb3af9bd65d8af794aac2f0e7b1ed9cc2dd +2. c8374157d5ae91d3b3e0d513d62808a798b32d3a + +Signed-off-by: Balaji Prakash J +Change-Id: I505cb560b31ad27a02c165fbe13bb33a2fc7d230 +--- + drivers/clk/qcom/gcc-ipq8074.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -2127,9 +2127,10 @@ struct clk_rcg2 adss_pwm_clk_src = { + + static struct clk_branch gcc_blsp1_ahb_clk = { + .halt_reg = 0x01008, ++ .halt_check = BRANCH_HALT_VOTED, + .clkr = { +- .enable_reg = 0x01008, +- .enable_mask = BIT(0), ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ diff --git a/target/linux/qualcommax/patches-6.12/0600-1-qca-nss-ecm-support-CORE.patch b/target/linux/qualcommax/patches-6.12/0600-1-qca-nss-ecm-support-CORE.patch index 8f4714eb81..fa9b68eedc 100644 --- a/target/linux/qualcommax/patches-6.12/0600-1-qca-nss-ecm-support-CORE.patch +++ b/target/linux/qualcommax/patches-6.12/0600-1-qca-nss-ecm-support-CORE.patch @@ -201,7 +201,7 @@ void fib_del_ifaddr(struct in_ifaddr *, struct in_ifaddr *); --- a/net/bridge/br_private.h +++ b/net/bridge/br_private.h -@@ -2292,4 +2292,6 @@ void br_do_suppress_nd(struct sk_buff *s +@@ -2293,4 +2293,6 @@ void br_do_suppress_nd(struct sk_buff *s u16 vid, struct net_bridge_port *p, struct nd_msg *msg); struct nd_msg *br_is_nd_neigh_msg(struct sk_buff *skb, struct nd_msg *m); bool br_is_neigh_suppress_enabled(const struct net_bridge_port *p, u16 vid); @@ -635,7 +635,7 @@ } --- a/net/ipv4/fib_trie.c +++ b/net/ipv4/fib_trie.c -@@ -1212,6 +1212,9 @@ static bool fib_valid_key_len(u32 key, u +@@ -1196,6 +1196,9 @@ static int fib_insert_alias(struct trie static void fib_remove_alias(struct trie *t, struct key_vector *tp, struct key_vector *l, struct fib_alias *old); @@ -645,7 +645,7 @@ /* Caller must hold RTNL. */ int fib_table_insert(struct net *net, struct fib_table *tb, struct fib_config *cfg, struct netlink_ext_ack *extack) -@@ -1405,6 +1408,9 @@ int fib_table_insert(struct net *net, st +@@ -1386,6 +1389,9 @@ int fib_table_insert(struct net *net, st rtmsg_fib(RTM_NEWROUTE, htonl(key), new_fa, plen, new_fa->tb_id, &cfg->fc_nlinfo, nlflags); succeeded: @@ -655,7 +655,7 @@ return 0; out_remove_new_fa: -@@ -1776,6 +1782,9 @@ int fib_table_delete(struct net *net, st +@@ -1754,6 +1760,9 @@ int fib_table_delete(struct net *net, st if (fa_to_delete->fa_state & FA_S_ACCESSED) rt_cache_flush(cfg->fc_nlinfo.nl_net); @@ -665,7 +665,7 @@ fib_release_info(fa_to_delete->fa_info); alias_free_mem_rcu(fa_to_delete); return 0; -@@ -2408,6 +2417,20 @@ void __init fib_trie_init(void) +@@ -2386,6 +2395,20 @@ void __init fib_trie_init(void) 0, SLAB_PANIC | SLAB_ACCOUNT, NULL); } @@ -760,6 +760,33 @@ } #undef N return "UNKNOWN_NETDEV_EVENT"; +@@ -12053,7 +12054,7 @@ static void __init net_dev_struct_check( + #ifdef CONFIG_NET_XGRESS + CACHELINE_ASSERT_GROUP_MEMBER(struct net_device, net_device_read_tx, tcx_egress); + #endif +- CACHELINE_ASSERT_GROUP_SIZE(struct net_device, net_device_read_tx, 160); ++ CACHELINE_ASSERT_GROUP_SIZE(struct net_device, net_device_read_tx, 192); + + /* TXRX read-mostly hotpath */ + CACHELINE_ASSERT_GROUP_MEMBER(struct net_device, net_device_read_txrx, lstats); +@@ -12062,7 +12063,7 @@ static void __init net_dev_struct_check( + CACHELINE_ASSERT_GROUP_MEMBER(struct net_device, net_device_read_txrx, hard_header_len); + CACHELINE_ASSERT_GROUP_MEMBER(struct net_device, net_device_read_txrx, features); + CACHELINE_ASSERT_GROUP_MEMBER(struct net_device, net_device_read_txrx, ip6_ptr); +- CACHELINE_ASSERT_GROUP_SIZE(struct net_device, net_device_read_txrx, 46); ++ CACHELINE_ASSERT_GROUP_SIZE(struct net_device, net_device_read_txrx, 64); + + /* RX read-mostly hotpath */ + CACHELINE_ASSERT_GROUP_MEMBER(struct net_device, net_device_read_rx, ptype_specific); +@@ -12082,7 +12083,7 @@ static void __init net_dev_struct_check( + #ifdef CONFIG_NET_XGRESS + CACHELINE_ASSERT_GROUP_MEMBER(struct net_device, net_device_read_rx, tcx_ingress); + #endif +- CACHELINE_ASSERT_GROUP_SIZE(struct net_device, net_device_read_rx, 104); ++ CACHELINE_ASSERT_GROUP_SIZE(struct net_device, net_device_read_rx, 128); + } + + /* --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c @@ -993,6 +993,7 @@ void inet6_ifa_finish_destroy(struct ine @@ -895,7 +922,7 @@ NF_SYSCTL_CT_PROTO_TCP_IGNORE_INVALID_RST, NF_SYSCTL_CT_PROTO_TCP_MAX_RETRANS, NF_SYSCTL_CT_PROTO_TIMEOUT_UDP, -@@ -832,6 +833,14 @@ static struct ctl_table nf_ct_sysctl_tab +@@ -836,6 +837,14 @@ static struct ctl_table nf_ct_sysctl_tab .extra1 = SYSCTL_ZERO, .extra2 = SYSCTL_ONE, }, @@ -910,7 +937,7 @@ [NF_SYSCTL_CT_PROTO_TCP_IGNORE_INVALID_RST] = { .procname = "nf_conntrack_tcp_ignore_invalid_rst", .maxlen = sizeof(u8), -@@ -1031,6 +1040,7 @@ static void nf_conntrack_standalone_init +@@ -1037,6 +1046,7 @@ static void nf_conntrack_standalone_init XASSIGN(LOOSE, &tn->tcp_loose); XASSIGN(LIBERAL, &tn->tcp_be_liberal); @@ -920,7 +947,7 @@ #undef XASSIGN --- a/net/ipv4/ip_gre.c +++ b/net/ipv4/ip_gre.c -@@ -685,6 +685,8 @@ static netdev_tx_t ipgre_xmit(struct sk_ +@@ -689,6 +689,8 @@ static netdev_tx_t ipgre_xmit(struct sk_ tunnel->parms.o_flags))) goto free_skb; @@ -929,7 +956,7 @@ __gre_xmit(skb, dev, tnl_params, skb->protocol); return NETDEV_TX_OK; -@@ -769,6 +771,8 @@ static netdev_tx_t gre_tap_xmit(struct s +@@ -773,6 +775,8 @@ static netdev_tx_t gre_tap_xmit(struct s if (skb_cow_head(skb, dev->needed_headroom)) goto free_skb; @@ -938,7 +965,7 @@ __gre_xmit(skb, dev, &tunnel->parms.iph, htons(ETH_P_TEB)); return NETDEV_TX_OK; -@@ -1370,6 +1374,7 @@ static void ipgre_tap_setup(struct net_d +@@ -1374,6 +1378,7 @@ static void ipgre_tap_setup(struct net_d dev->netdev_ops = &gre_tap_netdev_ops; dev->priv_flags &= ~IFF_TX_SKB_SHARING; dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; @@ -948,7 +975,7 @@ --- a/net/ipv6/ip6_gre.c +++ b/net/ipv6/ip6_gre.c -@@ -1935,6 +1935,7 @@ static void ip6gre_tap_setup(struct net_ +@@ -1933,6 +1933,7 @@ static void ip6gre_tap_setup(struct net_ dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; dev->priv_flags &= ~IFF_TX_SKB_SHARING; dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; diff --git a/target/linux/qualcommax/patches-6.12/0603-4-qca-nss-clients-add-iptunnel-support.patch b/target/linux/qualcommax/patches-6.12/0603-4-qca-nss-clients-add-iptunnel-support.patch index a867138e3c..0655564ed0 100644 --- a/target/linux/qualcommax/patches-6.12/0603-4-qca-nss-clients-add-iptunnel-support.patch +++ b/target/linux/qualcommax/patches-6.12/0603-4-qca-nss-clients-add-iptunnel-support.patch @@ -22,7 +22,7 @@ #endif /* __NET_IP_TUNNELS_H */ --- a/net/ipv6/ip6_tunnel.c +++ b/net/ipv6/ip6_tunnel.c -@@ -2411,6 +2411,26 @@ nla_put_failure: +@@ -2412,6 +2412,26 @@ nla_put_failure: return -EMSGSIZE; } @@ -51,7 +51,7 @@ struct ip6_tnl *tunnel = netdev_priv(dev); --- a/net/ipv6/sit.c +++ b/net/ipv6/sit.c -@@ -1734,6 +1734,23 @@ nla_put_failure: +@@ -1735,6 +1735,23 @@ nla_put_failure: return -EMSGSIZE; } diff --git a/target/linux/qualcommax/patches-6.12/0603-7-qca-nss-clients-iptunnel-lock-this-cpu.patch b/target/linux/qualcommax/patches-6.12/0603-7-qca-nss-clients-iptunnel-lock-this-cpu.patch index d26c7e4b7f..24c08b519a 100644 --- a/target/linux/qualcommax/patches-6.12/0603-7-qca-nss-clients-iptunnel-lock-this-cpu.patch +++ b/target/linux/qualcommax/patches-6.12/0603-7-qca-nss-clients-iptunnel-lock-this-cpu.patch @@ -1,6 +1,6 @@ --- a/net/ipv6/ip6_tunnel.c +++ b/net/ipv6/ip6_tunnel.c -@@ -2417,7 +2417,7 @@ nla_put_failure: +@@ -2418,7 +2418,7 @@ nla_put_failure: */ void ip6_update_offload_stats(struct net_device *dev, void *ptr) { @@ -11,7 +11,7 @@ --- a/net/ipv6/sit.c +++ b/net/ipv6/sit.c -@@ -1737,7 +1737,7 @@ nla_put_failure: +@@ -1738,7 +1738,7 @@ nla_put_failure: /* QCA NSS Clients Support - Start */ void ipip6_update_offload_stats(struct net_device *dev, void *ptr) { diff --git a/target/linux/qualcommax/patches-6.12/0604-1-qca-add-mcs-support.patch b/target/linux/qualcommax/patches-6.12/0604-1-qca-add-mcs-support.patch index f240e4219e..08c26b2005 100644 --- a/target/linux/qualcommax/patches-6.12/0604-1-qca-add-mcs-support.patch +++ b/target/linux/qualcommax/patches-6.12/0604-1-qca-add-mcs-support.patch @@ -39,7 +39,7 @@ * added to the bridge private HW address list and all required ports --- a/net/bridge/br_private.h +++ b/net/bridge/br_private.h -@@ -912,6 +912,7 @@ void br_manage_promisc(struct net_bridge +@@ -913,6 +913,7 @@ void br_manage_promisc(struct net_bridge int nbp_backup_change(struct net_bridge_port *p, struct net_device *backup_dev); /* br_input.c */ @@ -47,7 +47,7 @@ int br_handle_frame_finish(struct net *net, struct sock *sk, struct sk_buff *skb); rx_handler_func_t *br_get_rx_handler(const struct net_device *dev); -@@ -2294,4 +2295,14 @@ struct nd_msg *br_is_nd_neigh_msg(struct +@@ -2295,4 +2296,14 @@ struct nd_msg *br_is_nd_neigh_msg(struct bool br_is_neigh_suppress_enabled(const struct net_bridge_port *p, u16 vid); #define __br_get(__hook, __default, __args ...) \ (__hook ? (__hook(__args)) : (__default)) /* QCA NSS ECM support */ diff --git a/target/linux/qualcommax/patches-6.12/0605-1-qca-nss-cfi-support.patch b/target/linux/qualcommax/patches-6.12/0605-1-qca-nss-cfi-support.patch index c439da5336..b275e4a722 100644 --- a/target/linux/qualcommax/patches-6.12/0605-1-qca-nss-cfi-support.patch +++ b/target/linux/qualcommax/patches-6.12/0605-1-qca-nss-cfi-support.patch @@ -33,7 +33,7 @@ #include #include #include -@@ -657,6 +658,7 @@ static int esp_output(struct xfrm_state +@@ -618,6 +619,7 @@ static int esp_output(struct xfrm_state struct ip_esp_hdr *esph; struct crypto_aead *aead; struct esp_info esp; @@ -41,7 +41,7 @@ esp.inplace = true; -@@ -668,6 +670,11 @@ static int esp_output(struct xfrm_state +@@ -629,6 +631,11 @@ static int esp_output(struct xfrm_state aead = x->data; alen = crypto_aead_authsize(aead); @@ -53,7 +53,7 @@ esp.tfclen = 0; if (x->tfcpad) { struct xfrm_dst *dst = (struct xfrm_dst *)skb_dst(skb); -@@ -888,6 +895,7 @@ static int esp_input(struct xfrm_state * +@@ -849,6 +856,7 @@ static int esp_input(struct xfrm_state * u8 *iv; struct scatterlist *sg; int err = -EINVAL; @@ -61,7 +61,7 @@ if (!pskb_may_pull(skb, sizeof(struct ip_esp_hdr) + ivlen)) goto out; -@@ -895,6 +903,12 @@ static int esp_input(struct xfrm_state * +@@ -856,6 +864,12 @@ static int esp_input(struct xfrm_state * if (elen <= 0) goto out; @@ -84,7 +84,7 @@ #include #include #include -@@ -689,6 +690,7 @@ static int esp6_output(struct xfrm_state +@@ -650,6 +651,7 @@ static int esp6_output(struct xfrm_state struct ip_esp_hdr *esph; struct crypto_aead *aead; struct esp_info esp; @@ -92,7 +92,7 @@ esp.inplace = true; -@@ -700,6 +702,11 @@ static int esp6_output(struct xfrm_state +@@ -661,6 +663,11 @@ static int esp6_output(struct xfrm_state aead = x->data; alen = crypto_aead_authsize(aead); @@ -104,7 +104,7 @@ esp.tfclen = 0; if (x->tfcpad) { struct xfrm_dst *dst = (struct xfrm_dst *)skb_dst(skb); -@@ -926,6 +933,7 @@ static int esp6_input(struct xfrm_state +@@ -887,6 +894,7 @@ static int esp6_input(struct xfrm_state __be32 *seqhi; u8 *iv; struct scatterlist *sg; @@ -112,7 +112,7 @@ if (!pskb_may_pull(skb, sizeof(struct ip_esp_hdr) + ivlen)) { ret = -EINVAL; -@@ -937,6 +945,12 @@ static int esp6_input(struct xfrm_state +@@ -898,6 +906,12 @@ static int esp6_input(struct xfrm_state goto out; } diff --git a/target/linux/qualcommax/patches-6.12/0606-1-qca-nss-ecm-bridge-Fixes-for-Bridge-VLAN-Filtering.patch b/target/linux/qualcommax/patches-6.12/0606-1-qca-nss-ecm-bridge-Fixes-for-Bridge-VLAN-Filtering.patch index 0ea88b5d01..c5be95c394 100644 --- a/target/linux/qualcommax/patches-6.12/0606-1-qca-nss-ecm-bridge-Fixes-for-Bridge-VLAN-Filtering.patch +++ b/target/linux/qualcommax/patches-6.12/0606-1-qca-nss-ecm-bridge-Fixes-for-Bridge-VLAN-Filtering.patch @@ -122,7 +122,7 @@ Signed-off-by: Vishnu Vardhan Bantanahal return netdev; --- a/net/bridge/br_private.h +++ b/net/bridge/br_private.h -@@ -1587,6 +1587,7 @@ void br_vlan_fill_forward_path_pvid(stru +@@ -1588,6 +1588,7 @@ void br_vlan_fill_forward_path_pvid(stru int br_vlan_fill_forward_path_mode(struct net_bridge *br, struct net_bridge_port *dst, struct net_device_path *path); diff --git a/target/linux/qualcommax/patches-6.12/0607-1-qca-nss-clients-iptunnel-fixes.patch b/target/linux/qualcommax/patches-6.12/0607-1-qca-nss-clients-iptunnel-fixes.patch index 07c531b9d2..8b4ba93cda 100644 --- a/target/linux/qualcommax/patches-6.12/0607-1-qca-nss-clients-iptunnel-fixes.patch +++ b/target/linux/qualcommax/patches-6.12/0607-1-qca-nss-clients-iptunnel-fixes.patch @@ -130,7 +130,7 @@ Includes iptunnel fixes by integrating the following patches: if (dev) { --- a/net/ipv6/sit.c +++ b/net/ipv6/sit.c -@@ -724,6 +724,8 @@ static int ipip6_rcv(struct sk_buff *skb +@@ -725,6 +725,8 @@ static int ipip6_rcv(struct sk_buff *skb dev_sw_netstats_rx_add(tunnel->dev, skb->len); @@ -139,7 +139,7 @@ Includes iptunnel fixes by integrating the following patches: netif_rx(skb); return 0; -@@ -1033,6 +1035,8 @@ static netdev_tx_t ipip6_tunnel_xmit(str +@@ -1034,6 +1036,8 @@ static netdev_tx_t ipip6_tunnel_xmit(str skb_set_inner_ipproto(skb, IPPROTO_IPV6); diff --git a/target/linux/qualcommax/patches-6.12/0608-1-qca-nss-clients-add-ipsec-support.patch b/target/linux/qualcommax/patches-6.12/0608-1-qca-nss-clients-add-ipsec-support.patch index 80455e6bdf..4bf91648da 100644 --- a/target/linux/qualcommax/patches-6.12/0608-1-qca-nss-clients-add-ipsec-support.patch +++ b/target/linux/qualcommax/patches-6.12/0608-1-qca-nss-clients-add-ipsec-support.patch @@ -111,7 +111,7 @@ Signed-off-by: Pavithra R #endif --- a/include/net/xfrm.h +++ b/include/net/xfrm.h -@@ -304,6 +304,21 @@ struct xfrm_state { +@@ -303,6 +303,21 @@ struct xfrm_state { u8 dir; }; @@ -133,7 +133,7 @@ Signed-off-by: Pavithra R static inline struct net *xs_net(struct xfrm_state *x) { return read_pnet(&x->xs_net); -@@ -312,6 +327,7 @@ static inline struct net *xs_net(struct +@@ -311,6 +326,7 @@ static inline struct net *xs_net(struct /* xflags - make enum if more show up */ #define XFRM_TIME_DEFER 1 #define XFRM_SOFT_EXPIRE 2 @@ -141,7 +141,7 @@ Signed-off-by: Pavithra R enum { XFRM_STATE_VOID, -@@ -413,6 +429,7 @@ int xfrm_state_register_afinfo(struct xf +@@ -412,6 +428,7 @@ int xfrm_state_register_afinfo(struct xf int xfrm_state_unregister_afinfo(struct xfrm_state_afinfo *afinfo); struct xfrm_state_afinfo *xfrm_state_get_afinfo(unsigned int family); struct xfrm_state_afinfo *xfrm_state_afinfo_get_rcu(unsigned int family); @@ -149,7 +149,7 @@ Signed-off-by: Pavithra R struct xfrm_input_afinfo { u8 family; -@@ -443,6 +460,8 @@ struct xfrm_type { +@@ -442,6 +459,8 @@ struct xfrm_type { int (*output)(struct xfrm_state *, struct sk_buff *pskb); int (*reject)(struct xfrm_state *, struct sk_buff *, const struct flowi *); @@ -158,7 +158,7 @@ Signed-off-by: Pavithra R }; int xfrm_register_type(const struct xfrm_type *type, unsigned short family); -@@ -1670,6 +1689,7 @@ struct xfrm_state *xfrm_state_lookup_bya +@@ -1669,6 +1688,7 @@ struct xfrm_state *xfrm_state_lookup_bya const xfrm_address_t *saddr, u8 proto, unsigned short family); @@ -166,7 +166,7 @@ Signed-off-by: Pavithra R #ifdef CONFIG_XFRM_SUB_POLICY void xfrm_tmpl_sort(struct xfrm_tmpl **dst, struct xfrm_tmpl **src, int n, unsigned short family); -@@ -1714,7 +1734,7 @@ void xfrm_sad_getinfo(struct net *net, s +@@ -1713,7 +1733,7 @@ void xfrm_sad_getinfo(struct net *net, s void xfrm_spd_getinfo(struct net *net, struct xfrmk_spdinfo *si); u32 xfrm_replay_seqhi(struct xfrm_state *x, __be32 net_seq); int xfrm_init_replay(struct xfrm_state *x, struct netlink_ext_ack *extack); @@ -177,7 +177,7 @@ Signed-off-by: Pavithra R int xfrm_init_state(struct xfrm_state *x); --- a/net/xfrm/xfrm_policy.c +++ b/net/xfrm/xfrm_policy.c -@@ -4296,6 +4296,10 @@ static int __net_init xfrm_net_init(stru +@@ -4299,6 +4299,10 @@ static int __net_init xfrm_net_init(stru spin_lock_init(&net->xfrm.xfrm_policy_lock); seqcount_spinlock_init(&net->xfrm.xfrm_policy_hash_generation, &net->xfrm.xfrm_policy_lock); mutex_init(&net->xfrm.xfrm_cfg_mutex); @@ -199,8 +199,8 @@ Signed-off-by: Pavithra R #include "xfrm_hash.h" #define xfrm_state_deref_prot(table, net) \ -@@ -777,6 +775,7 @@ int __xfrm_state_delete(struct xfrm_stat - sock_put(rcu_dereference_raw(x->encap_sk)); +@@ -774,6 +772,7 @@ int __xfrm_state_delete(struct xfrm_stat + spin_unlock(&net->xfrm.xfrm_state_lock); xfrm_dev_state_delete(x); + xfrm_state_change_notify(x, XFRM_EVENT_STATE_DEL); @@ -314,7 +314,7 @@ Signed-off-by: Pavithra R +EXPORT_SYMBOL(xfrm_event_unregister_notifier); --- a/net/xfrm/xfrm_user.c +++ b/net/xfrm/xfrm_user.c -@@ -888,6 +888,8 @@ static struct xfrm_state *xfrm_state_con +@@ -900,6 +900,8 @@ static struct xfrm_state *xfrm_state_con goto error; } @@ -323,7 +323,7 @@ Signed-off-by: Pavithra R return x; error: -@@ -926,6 +928,7 @@ static int xfrm_add_sa(struct sk_buff *s +@@ -938,6 +940,7 @@ static int xfrm_add_sa(struct sk_buff *s if (err < 0) { x->km.state = XFRM_STATE_DEAD; xfrm_dev_state_delete(x); @@ -342,7 +342,7 @@ Signed-off-by: Pavithra R /* * Allocate an AEAD request structure with extra space for SG and IV. * -@@ -680,7 +682,7 @@ static int esp_output(struct xfrm_state +@@ -641,7 +643,7 @@ static int esp_output(struct xfrm_state struct xfrm_dst *dst = (struct xfrm_dst *)skb_dst(skb); u32 padto; @@ -351,7 +351,7 @@ Signed-off-by: Pavithra R if (skb->len < padto) esp.tfclen = padto - skb->len; } -@@ -980,6 +982,28 @@ out: +@@ -941,6 +943,28 @@ out: return err; } @@ -380,7 +380,7 @@ Signed-off-by: Pavithra R static int esp4_err(struct sk_buff *skb, u32 info) { struct net *net = dev_net(skb->dev); -@@ -1221,6 +1245,7 @@ static const struct xfrm_type esp_type = +@@ -1182,6 +1206,7 @@ static const struct xfrm_type esp_type = .flags = XFRM_TYPE_REPLAY_PROT, .init_state = esp_init_state, .destructor = esp_destroy, @@ -399,7 +399,7 @@ Signed-off-by: Pavithra R /* * Allocate an AEAD request structure with extra space for SG and IV. * -@@ -712,7 +714,7 @@ static int esp6_output(struct xfrm_state +@@ -673,7 +675,7 @@ static int esp6_output(struct xfrm_state struct xfrm_dst *dst = (struct xfrm_dst *)skb_dst(skb); u32 padto; @@ -408,7 +408,7 @@ Signed-off-by: Pavithra R if (skb->len < padto) esp.tfclen = padto - skb->len; } -@@ -1022,6 +1024,19 @@ out: +@@ -983,6 +985,19 @@ out: return ret; } @@ -428,7 +428,7 @@ Signed-off-by: Pavithra R static int esp6_err(struct sk_buff *skb, struct inet6_skb_parm *opt, u8 type, u8 code, int offset, __be32 info) { -@@ -1267,6 +1282,7 @@ static const struct xfrm_type esp6_type +@@ -1228,6 +1243,7 @@ static const struct xfrm_type esp6_type .flags = XFRM_TYPE_REPLAY_PROT, .init_state = esp6_init_state, .destructor = esp6_destroy, diff --git a/target/linux/qualcommax/patches-6.12/0818-arm64-dts-qcom-ipq5018-add-NSS-reserved-memory.patch b/target/linux/qualcommax/patches-6.12/0818-arm64-dts-qcom-ipq5018-add-NSS-reserved-memory.patch index ef3b4d10ca..9e51832d43 100644 --- a/target/linux/qualcommax/patches-6.12/0818-arm64-dts-qcom-ipq5018-add-NSS-reserved-memory.patch +++ b/target/linux/qualcommax/patches-6.12/0818-arm64-dts-qcom-ipq5018-add-NSS-reserved-memory.patch @@ -4,7 +4,7 @@ #size-cells = <2>; ranges; -+ nss_region: memory@40000000 { ++ nss_region: nss@40000000 { + no-map; + reg = <0x0 0x40000000 0x0 0x1000000>; + }; diff --git a/target/linux/qualcommax/patches-6.12/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch b/target/linux/qualcommax/patches-6.12/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch index e4f1809924..3ad1d87b14 100644 --- a/target/linux/qualcommax/patches-6.12/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch +++ b/target/linux/qualcommax/patches-6.12/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch @@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -1204,6 +1204,7 @@ +@@ -1203,6 +1203,7 @@ wcss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; diff --git a/target/linux/qualcommax/patches-6.12/0981-1-qca-skb_recycler-support.patch b/target/linux/qualcommax/patches-6.12/0981-1-qca-skb_recycler-support.patch index 0ed126eb37..65e7c42832 100644 --- a/target/linux/qualcommax/patches-6.12/0981-1-qca-skb_recycler-support.patch +++ b/target/linux/qualcommax/patches-6.12/0981-1-qca-skb_recycler-support.patch @@ -146,7 +146,7 @@ +obj-$(CONFIG_SKB_RECYCLER) += skbuff_recycle.o --- a/net/core/dev.c +++ b/net/core/dev.c -@@ -6183,12 +6183,18 @@ static int process_backlog(struct napi_s +@@ -6187,12 +6187,18 @@ static int process_backlog(struct napi_s napi->weight = READ_ONCE(net_hotdata.dev_rx_weight); while (again) { diff --git a/target/linux/qualcommbe/Makefile b/target/linux/qualcommbe/Makefile index d796e015d7..7e84612265 100644 --- a/target/linux/qualcommbe/Makefile +++ b/target/linux/qualcommbe/Makefile @@ -9,6 +9,7 @@ CPU_TYPE:=cortex-a53 SUBTARGETS:=ipq95xx KERNEL_PATCHVER:=6.6 +KERNEL_TESTING_PATCHVER:=6.12 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ diff --git a/target/linux/qualcommbe/config-6.12 b/target/linux/qualcommbe/config-6.12 new file mode 100644 index 0000000000..af5ba0f809 --- /dev/null +++ b/target/linux/qualcommbe/config-6.12 @@ -0,0 +1,626 @@ +CONFIG_64BIT=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_FORCE_MAX_ORDER=10 +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PKEY_BITS=3 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_EXECMEM_LATE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_2051678=y +CONFIG_ARM64_ERRATUM_2054223=y +CONFIG_ARM64_ERRATUM_2067961=y +CONFIG_ARM64_ERRATUM_2077057=y +CONFIG_ARM64_ERRATUM_2658417=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PLATFORM_DEVICES=y +CONFIG_ARM64_PTR_AUTH=y +CONFIG_ARM64_PTR_AUTH_KERNEL=y +CONFIG_ARM64_SVE=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_52 is not set +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +# CONFIG_ARM_MHU_V2 is not set +# CONFIG_ARM_MHU_V3 is not set +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_QCOM_CPUFREQ_HW is not set +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y +CONFIG_AT803X_PHY=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_AUXILIARY_BUS=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y +CONFIG_CAVIUM_TX2_ERRATUM_219=y +CONFIG_CC_HAVE_SHADOW_CALL_STACK=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +# CONFIG_CLK_QCM2290_GPUCC is not set +# CONFIG_CLK_X1E80100_CAMCC is not set +# CONFIG_CLK_X1E80100_DISPCC is not set +# CONFIG_CLK_X1E80100_GCC is not set +# CONFIG_CLK_X1E80100_GPUCC is not set +# CONFIG_CLK_X1E80100_TCSRCC is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +# CONFIG_COMPAT_32BIT_TIME is not set +# CONFIG_COMPRESSED_INSTALL is not set +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_COREDUMP=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_THERMAL=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRC16=y +CONFIG_CRC8=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DEV_QCE=y +CONFIG_CRYPTO_DEV_QCE_AEAD=y +# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set +CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y +# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set +# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set +CONFIG_CRYPTO_DEV_QCE_SHA=y +CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y +CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512 +CONFIG_CRYPTO_DEV_QCOM_RNG=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +CONFIG_DEV_COREDUMP=y +CONFIG_DMADEVICES=y +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_OF=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_DT_IDLE_STATES=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FUJITSU_ERRATUM_010001=y +CONFIG_FUNCTION_ALIGNMENT=4 +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HISILICON_ERRATUM_162100801=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +# CONFIG_I2C_QCOM_CCI is not set +CONFIG_I2C_QUP=y +# CONFIG_IDPF is not set +CONFIG_IIO=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INTERCONNECT=y +CONFIG_INTERCONNECT_CLK=y +# CONFIG_INTERCONNECT_QCOM is not set +CONFIG_IPQ_APSS_6018=y +CONFIG_IPQ_APSS_PLL=y +# CONFIG_IPQ_CMN_PLL is not set +# CONFIG_IPQ_GCC_4019 is not set +# CONFIG_IPQ_GCC_5018 is not set +# CONFIG_IPQ_GCC_5332 is not set +# CONFIG_IPQ_GCC_6018 is not set +# CONFIG_IPQ_GCC_8074 is not set +# CONFIG_IPQ_GCC_9574 is not set +# CONFIG_IPQ_NSSCC_QCA8K is not set +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_LIB=y +CONFIG_IRQ_WORK=y +# CONFIG_KPSS_XCC is not set +CONFIG_LEDS_TLC591XX=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LRU_GEN_WALKS_MMU=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_IPQ4019=y +# CONFIG_MFD_QCOM_RPM is not set +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_CQHCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_MSM=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MSM_GCC_8916 is not set +# CONFIG_MSM_GCC_8917 is not set +# CONFIG_MSM_GCC_8939 is not set +# CONFIG_MSM_GCC_8976 is not set +# CONFIG_MSM_GCC_8994 is not set +# CONFIG_MSM_GCC_8996 is not set +# CONFIG_MSM_GCC_8998 is not set +# CONFIG_MSM_GPUCC_8998 is not set +# CONFIG_MSM_MMCC_8996 is not set +# CONFIG_MSM_MMCC_8998 is not set +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_QCOM=y +CONFIG_MTD_QCOMSMEM_PARTS=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +# CONFIG_NSM is not set +CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y +CONFIG_NVMEM_QCOM_QFPROM=y +# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_NVMEM_U_BOOT_ENV=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_PME=y +CONFIG_PCIE_QCOM=y +CONFIG_PCIE_QCOM_COMMON=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +# CONFIG_PCS_QCOM_IPQ9574 is not set +CONFIG_PER_VMA_LOCK=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_QCOM_APQ8064_SATA is not set +# CONFIG_PHY_QCOM_EDP is not set +# CONFIG_PHY_QCOM_EUSB2_REPEATER is not set +# CONFIG_PHY_QCOM_IPQ4019_USB is not set +# CONFIG_PHY_QCOM_IPQ806X_SATA is not set +# CONFIG_PHY_QCOM_IPQ806X_USB is not set +# CONFIG_PHY_QCOM_M31_USB is not set +# CONFIG_PHY_QCOM_PCIE2 is not set +CONFIG_PHY_QCOM_QMP=y +CONFIG_PHY_QCOM_QMP_COMBO=y +CONFIG_PHY_QCOM_QMP_PCIE=y +CONFIG_PHY_QCOM_QMP_PCIE_8996=y +CONFIG_PHY_QCOM_QMP_UFS=y +CONFIG_PHY_QCOM_QMP_USB=y +# CONFIG_PHY_QCOM_QMP_USB_LEGACY is not set +CONFIG_PHY_QCOM_QUSB2=y +# CONFIG_PHY_QCOM_SGMII_ETH is not set +# CONFIG_PHY_QCOM_SNPS_EUSB2 is not set +# CONFIG_PHY_QCOM_USB_HS_28NM is not set +# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set +# CONFIG_PHY_QCOM_USB_SS is not set +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_IPQ5018 is not set +# CONFIG_PINCTRL_IPQ5332 is not set +# CONFIG_PINCTRL_IPQ6018 is not set +# CONFIG_PINCTRL_IPQ8074 is not set +# CONFIG_PINCTRL_IPQ9574 is not set +CONFIG_PINCTRL_MSM=y +# CONFIG_PINCTRL_MSM8916 is not set +# CONFIG_PINCTRL_MSM8976 is not set +# CONFIG_PINCTRL_MSM8994 is not set +# CONFIG_PINCTRL_MSM8996 is not set +# CONFIG_PINCTRL_MSM8998 is not set +# CONFIG_PINCTRL_QCM2290 is not set +# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set +# CONFIG_PINCTRL_QCS404 is not set +# CONFIG_PINCTRL_QDU1000 is not set +# CONFIG_PINCTRL_SA8775P is not set +# CONFIG_PINCTRL_SC7180 is not set +# CONFIG_PINCTRL_SC8280XP is not set +# CONFIG_PINCTRL_SDM660 is not set +# CONFIG_PINCTRL_SDM670 is not set +# CONFIG_PINCTRL_SDM845 is not set +# CONFIG_PINCTRL_SDX75 is not set +# CONFIG_PINCTRL_SM4450 is not set +# CONFIG_PINCTRL_SM6350 is not set +# CONFIG_PINCTRL_SM6375 is not set +# CONFIG_PINCTRL_SM7150 is not set +# CONFIG_PINCTRL_SM8150 is not set +# CONFIG_PINCTRL_SM8250 is not set +# CONFIG_PINCTRL_SM8450 is not set +# CONFIG_PINCTRL_SM8550 is not set +# CONFIG_PINCTRL_SM8650 is not set +# CONFIG_PINCTRL_X1E80100 is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_OPP=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_MSM is not set +CONFIG_POWER_SUPPLY=y +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_QCA807X_PHY=y +CONFIG_QCA808X_PHY=y +# CONFIG_QCM_DISPCC_2290 is not set +# CONFIG_QCM_GCC_2290 is not set +# CONFIG_QCOM_A53PLL is not set +# CONFIG_QCOM_AOSS_QMP is not set +CONFIG_QCOM_APCS_IPC=y +# CONFIG_QCOM_APR is not set +CONFIG_QCOM_BAM_DMA=y +# CONFIG_QCOM_CLK_APCC_MSM8996 is not set +# CONFIG_QCOM_CLK_APCS_MSM8916 is not set +# CONFIG_QCOM_COMMAND_DB is not set +# CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set +# CONFIG_QCOM_EBI2 is not set +# CONFIG_QCOM_FASTRPC is not set +# CONFIG_QCOM_GENI_SE is not set +# CONFIG_QCOM_GSBI is not set +# CONFIG_QCOM_HFPLL is not set +# CONFIG_QCOM_ICC_BWMON is not set +# CONFIG_QCOM_IPA is not set +# CONFIG_QCOM_IPCC is not set +# CONFIG_QCOM_LLCC is not set +CONFIG_QCOM_MDT_LOADER=y +# CONFIG_QCOM_MPM is not set +CONFIG_QCOM_NET_PHYLIB=y +# CONFIG_QCOM_OCMEM is not set +# CONFIG_QCOM_PDC is not set +CONFIG_QCOM_PIL_INFO=y +# CONFIG_QCOM_PPE is not set +# CONFIG_QCOM_Q6V5_ADSP is not set +CONFIG_QCOM_Q6V5_COMMON=y +# CONFIG_QCOM_Q6V5_MSS is not set +# CONFIG_QCOM_Q6V5_PAS is not set +CONFIG_QCOM_Q6V5_WCSS=y +# CONFIG_QCOM_QSEECOM is not set +# CONFIG_QCOM_RAMP_CTRL is not set +# CONFIG_QCOM_RMTFS_MEM is not set +# CONFIG_QCOM_RPMH is not set +# CONFIG_QCOM_RPM_MASTER_STATS is not set +CONFIG_QCOM_RPROC_COMMON=y +CONFIG_QCOM_SCM=y +# CONFIG_QCOM_SMD_RPM is not set +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMEM_STATE=y +CONFIG_QCOM_SMP2P=y +# CONFIG_QCOM_SMSM is not set +CONFIG_QCOM_SOCINFO=y +# CONFIG_QCOM_SPM is not set +# CONFIG_QCOM_STATS is not set +# CONFIG_QCOM_SYSMON is not set +CONFIG_QCOM_TSENS=y +CONFIG_QCOM_TZMEM=y +CONFIG_QCOM_TZMEM_MODE_GENERIC=y +# CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE is not set +# CONFIG_QCOM_WCNSS_CTRL is not set +# CONFIG_QCOM_WCNSS_PIL is not set +CONFIG_QCOM_WDT=y +# CONFIG_QCS_GCC_404 is not set +# CONFIG_QCS_Q6SSTOP_404 is not set +# CONFIG_QCS_TURING_404 is not set +# CONFIG_QDU_ECPRICC_1000 is not set +# CONFIG_QDU_GCC_1000 is not set +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set +CONFIG_RELOCATABLE=y +CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_QCOM_AOSS is not set +# CONFIG_RESET_QCOM_PDC is not set +CONFIG_RFS_ACCEL=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPMSG=y +CONFIG_RPMSG_CHAR=y +# CONFIG_RPMSG_CTRL is not set +# CONFIG_RPMSG_NS is not set +CONFIG_RPMSG_QCOM_GLINK=y +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_RPMSG_QCOM_SMD=y +# CONFIG_RPMSG_TTY is not set +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +# CONFIG_SA_GCC_8775P is not set +# CONFIG_SA_GPUCC_8775P is not set +# CONFIG_SCHED_CORE is not set +CONFIG_SCHED_HW_PRESSURE=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_PROC_FS is not set +# CONFIG_SC_CAMCC_7280 is not set +# CONFIG_SC_CAMCC_8280XP is not set +# CONFIG_SC_DISPCC_7180 is not set +# CONFIG_SC_DISPCC_8280XP is not set +# CONFIG_SC_GCC_7180 is not set +# CONFIG_SC_GCC_8280XP is not set +# CONFIG_SC_GPUCC_7180 is not set +# CONFIG_SC_LPASSCC_7280 is not set +# CONFIG_SC_LPASSCC_8280XP is not set +# CONFIG_SC_LPASS_CORECC_7180 is not set +# CONFIG_SC_LPASS_CORECC_7280 is not set +# CONFIG_SC_VIDEOCC_7180 is not set +# CONFIG_SDM_CAMCC_845 is not set +# CONFIG_SDM_DISPCC_845 is not set +# CONFIG_SDM_GCC_660 is not set +# CONFIG_SDM_GCC_845 is not set +# CONFIG_SDM_GPUCC_845 is not set +# CONFIG_SDM_LPASSCC_845 is not set +# CONFIG_SDM_VIDEOCC_845 is not set +# CONFIG_SDX_GCC_75 is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +# CONFIG_SM_CAMCC_4450 is not set +# CONFIG_SM_CAMCC_6350 is not set +# CONFIG_SM_CAMCC_7150 is not set +# CONFIG_SM_CAMCC_8150 is not set +# CONFIG_SM_CAMCC_8450 is not set +# CONFIG_SM_CAMCC_8550 is not set +# CONFIG_SM_CAMCC_8650 is not set +# CONFIG_SM_GCC_4450 is not set +# CONFIG_SM_GCC_7150 is not set +# CONFIG_SM_GCC_8150 is not set +# CONFIG_SM_GCC_8250 is not set +# CONFIG_SM_GCC_8450 is not set +# CONFIG_SM_GCC_8550 is not set +# CONFIG_SM_GCC_8650 is not set +# CONFIG_SM_GPUCC_4450 is not set +# CONFIG_SM_GPUCC_6115 is not set +# CONFIG_SM_GPUCC_6125 is not set +# CONFIG_SM_GPUCC_6350 is not set +# CONFIG_SM_GPUCC_6375 is not set +# CONFIG_SM_GPUCC_8150 is not set +# CONFIG_SM_GPUCC_8250 is not set +# CONFIG_SM_GPUCC_8350 is not set +# CONFIG_SM_GPUCC_8450 is not set +# CONFIG_SM_GPUCC_8550 is not set +# CONFIG_SM_GPUCC_8650 is not set +# CONFIG_SM_TCSRCC_8550 is not set +# CONFIG_SM_TCSRCC_8650 is not set +# CONFIG_SM_VIDEOCC_7150 is not set +# CONFIG_SM_VIDEOCC_8150 is not set +# CONFIG_SM_VIDEOCC_8250 is not set +# CONFIG_SM_VIDEOCC_8350 is not set +# CONFIG_SM_VIDEOCC_8450 is not set +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOC_BUS=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_QPIC_SNAND is not set +CONFIG_SPI_QUP=y +CONFIG_SPLIT_PMD_PTLOCKS=y +CONFIG_SPLIT_PTE_PTLOCKS=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +# CONFIG_TEST_FPU is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +# CONFIG_UCLAMP_TASK is not set +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_VDSO_GETRANDOM=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_ANCHOR=y +# CONFIG_VIRTIO_BLK is not set +# CONFIG_VIRTIO_DEBUG is not set +# CONFIG_VIRTIO_NET is not set +CONFIG_VMAP_STACK=y +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_SYSFS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/qualcommbe/ipq95xx/config-default b/target/linux/qualcommbe/ipq95xx/config-default index 3ac8eaf23c..60b386406b 100644 --- a/target/linux/qualcommbe/ipq95xx/config-default +++ b/target/linux/qualcommbe/ipq95xx/config-default @@ -2,11 +2,29 @@ CONFIG_AQUANTIA_PHY=y CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y CONFIG_DT_IDLE_GENPD=y CONFIG_GRO_CELLS=y +CONFIG_INTERCONNECT_QCOM=y +# CONFIG_INTERCONNECT_QCOM_MSM8909 is not set +# CONFIG_INTERCONNECT_QCOM_MSM8916 is not set +# CONFIG_INTERCONNECT_QCOM_MSM8937 is not set +# CONFIG_INTERCONNECT_QCOM_MSM8939 is not set +# CONFIG_INTERCONNECT_QCOM_MSM8953 is not set +# CONFIG_INTERCONNECT_QCOM_MSM8974 is not set +# CONFIG_INTERCONNECT_QCOM_MSM8976 is not set +# CONFIG_INTERCONNECT_QCOM_MSM8996 is not set +CONFIG_INTERCONNECT_QCOM_OSM_L3=y +# CONFIG_INTERCONNECT_QCOM_QCM2290 is not set +# CONFIG_INTERCONNECT_QCOM_QCS404 is not set +# CONFIG_INTERCONNECT_QCOM_SDM660 is not set +# CONFIG_INTERCONNECT_QCOM_SM6115 is not set +CONFIG_IPQ_CMN_PLL=y CONFIG_IPQ_GCC_9574=y +CONFIG_IPQ_NSSCC_9574=y +CONFIG_IPQ_NSSCC_QCA8K=y CONFIG_MDIO_BITBANG=y CONFIG_MDIO_GPIO=y # CONFIG_MFD_HI6421_SPMI is not set CONFIG_MFD_SPMI_PMIC=y +CONFIG_MTD_SPI_NAND=y CONFIG_NET_DEVLINK=y CONFIG_NET_DSA=y CONFIG_NET_DSA_QCA8K=y @@ -21,8 +39,12 @@ CONFIG_PM_GENERIC_DOMAINS_OF=y # CONFIG_POWER_RESET_QCOM_PON is not set CONFIG_QCA83XX_PHY=y CONFIG_QCOM_APM=y +# CONFIG_QCOM_CLK_SMD_RPM is not set # CONFIG_QCOM_COINCELL is not set CONFIG_QCOM_GDSC=y +CONFIG_QCOM_PPE=y +# CONFIG_QCOM_RPMPD is not set +CONFIG_QCOM_SMD_RPM=y CONFIG_QCOM_SPMI_ADC5=y # CONFIG_QCOM_SPMI_RRADC is not set CONFIG_QCOM_VADC_COMMON=y @@ -31,30 +53,13 @@ CONFIG_REGULATOR_CPR3=y # CONFIG_REGULATOR_CPR3_NPU is not set CONFIG_REGULATOR_CPR4_APSS=y # CONFIG_REGULATOR_QCOM_LABIBB is not set +CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SPMI=y # CONFIG_REGULATOR_QCOM_USB_VBUS is not set CONFIG_REGULATOR_USERSPACE_CONSUMER=y CONFIG_RTC_DRV_PM8XXX=y +CONFIG_SPI_QPIC_SNAND=y CONFIG_SPMI=y # CONFIG_SPMI_HISI3670 is not set CONFIG_SPMI_MSM_PMIC_ARB=y # CONFIG_SPMI_PMIC_CLKDIV is not set -CONFIG_SPI_QPIC_SNAND=y -CONFIG_IPQ_CMN_PLL=y -CONFIG_IPQ_NSSCC_9574=y -CONFIG_IPQ_NSSCC_QCA8K=y -CONFIG_QCOM_PPE=y -CONFIG_INTERCONNECT_QCOM=y -CONFIG_INTERCONNECT_QCOM_OSM_L3=y -CONFIG_MTD_SPI_NAND=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_REGULATOR_QCOM_SMD_RPM=y -# CONFIG_QCOM_CLK_SMD_RPM is not set -# CONFIG_QCOM_RPMPD is not set -# CONFIG_INTERCONNECT_QCOM_MSM8916 is not set -# CONFIG_INTERCONNECT_QCOM_MSM8939 is not set -# CONFIG_INTERCONNECT_QCOM_MSM8996 is not set -# CONFIG_INTERCONNECT_QCOM_MSM8974 is not set -# CONFIG_INTERCONNECT_QCOM_QCM2290 is not set -# CONFIG_INTERCONNECT_QCOM_QCS404 is not set -# CONFIG_INTERCONNECT_QCOM_SDM660 is not set diff --git a/target/linux/qualcommbe/ipq95xx/target.mk b/target/linux/qualcommbe/ipq95xx/target.mk index 0e8463e652..af166c4893 100644 --- a/target/linux/qualcommbe/ipq95xx/target.mk +++ b/target/linux/qualcommbe/ipq95xx/target.mk @@ -1,6 +1,6 @@ SUBTARGET:=ipq95xx BOARDNAME:=Qualcomm Atheros IPQ95xx -DEFAULT_PACKAGES += +DEFAULT_PACKAGES += define Target/Description Build firmware images for Qualcomm Atheros IPQ95XX based boards. diff --git a/target/linux/qualcommbe/patches-6.12/0002-v6.13-dt-bindings-PCI-qcom-Document-the-IPQ9574-PCIe.patch b/target/linux/qualcommbe/patches-6.12/0002-v6.13-dt-bindings-PCI-qcom-Document-the-IPQ9574-PCIe.patch new file mode 100644 index 0000000000..2c883030e3 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0002-v6.13-dt-bindings-PCI-qcom-Document-the-IPQ9574-PCIe.patch @@ -0,0 +1,101 @@ +From e3ccffe9335ce3bdba93640588fab4560d18485e Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 1 Aug 2024 11:18:00 +0530 +Subject: [PATCH 02/22] v6.13: dt-bindings: PCI: qcom: Document the IPQ9574 + PCIe controller +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Document the PCIe controller on IPQ9574 platform. + +Link: https://lore.kernel.org/r/20240801054803.3015572-2-quic_srichara@quicinc.com +Signed-off-by: devi priya +Signed-off-by: Sricharan Ramabadhran +Signed-off-by: Krzysztof Wilczyński +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Manivannan Sadhasivam +--- + .../devicetree/bindings/pci/qcom,pcie.yaml | 50 +++++++++++++++++++ + 1 file changed, 50 insertions(+) + +--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml ++++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +@@ -26,6 +26,7 @@ properties: + - qcom,pcie-ipq8064-v2 + - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 ++ - qcom,pcie-ipq9574 + - qcom,pcie-msm8996 + - qcom,pcie-qcs404 + - qcom,pcie-sdm845 +@@ -164,6 +165,7 @@ allOf: + enum: + - qcom,pcie-ipq6018 + - qcom,pcie-ipq8074-gen3 ++ - qcom,pcie-ipq9574 + then: + properties: + reg: +@@ -405,6 +407,53 @@ allOf: + compatible: + contains: + enum: ++ - qcom,pcie-ipq9574 ++ then: ++ properties: ++ clocks: ++ minItems: 6 ++ maxItems: 6 ++ clock-names: ++ items: ++ - const: axi_m # AXI Master clock ++ - const: axi_s # AXI Slave clock ++ - const: axi_bridge ++ - const: rchng ++ - const: ahb ++ - const: aux ++ ++ resets: ++ minItems: 8 ++ maxItems: 8 ++ reset-names: ++ items: ++ - const: pipe # PIPE reset ++ - const: sticky # Core Sticky reset ++ - const: axi_s_sticky # AXI Slave Sticky reset ++ - const: axi_s # AXI Slave reset ++ - const: axi_m_sticky # AXI Master Sticky reset ++ - const: axi_m # AXI Master reset ++ - const: aux # AUX Reset ++ - const: ahb # AHB Reset ++ ++ interrupts: ++ minItems: 8 ++ interrupt-names: ++ items: ++ - const: msi0 ++ - const: msi1 ++ - const: msi2 ++ - const: msi3 ++ - const: msi4 ++ - const: msi5 ++ - const: msi6 ++ - const: msi7 ++ ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: + - qcom,pcie-qcs404 + then: + properties: +@@ -510,6 +559,7 @@ allOf: + - qcom,pcie-ipq8064v2 + - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 ++ - qcom,pcie-ipq9574 + - qcom,pcie-qcs404 + then: + required: diff --git a/target/linux/qualcommbe/patches-6.12/0004-v6.14-arm64-dts-qcom-ipq9574-Add-PCIe-PHYs-and-contr.patch b/target/linux/qualcommbe/patches-6.12/0004-v6.14-arm64-dts-qcom-ipq9574-Add-PCIe-PHYs-and-contr.patch new file mode 100644 index 0000000000..db27e9e6f3 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0004-v6.14-arm64-dts-qcom-ipq9574-Add-PCIe-PHYs-and-contr.patch @@ -0,0 +1,468 @@ +From acb06ebe2d1f043fd597f5c33aff048ae1804293 Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 1 Aug 2024 11:18:01 +0530 +Subject: [PATCH 04/22] v6.14: arm64: dts: qcom: ipq9574: Add PCIe PHYs and + controller nodes + +Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices +found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3 +host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. + +Signed-off-by: devi priya +Signed-off-by: Sricharan Ramabadhran +Link: https://lore.kernel.org/r/20240801054803.3015572-3-quic_srichara@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 420 +++++++++++++++++++++++++- + 1 file changed, 416 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -226,6 +226,52 @@ + reg = <0x00060000 0x6000>; + }; + ++ pcie0_phy: phy@84000 { ++ compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; ++ reg = <0x00084000 0x1000>; ++ ++ clocks = <&gcc GCC_PCIE0_AUX_CLK>, ++ <&gcc GCC_PCIE0_AHB_CLK>, ++ <&gcc GCC_PCIE0_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE0_PHY_BCR>, ++ <&gcc GCC_PCIE0PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie0_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie2_phy: phy@8c000 { ++ compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; ++ reg = <0x0008c000 0x2000>; ++ ++ clocks = <&gcc GCC_PCIE2_AUX_CLK>, ++ <&gcc GCC_PCIE2_AHB_CLK>, ++ <&gcc GCC_PCIE2_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE2_PHY_BCR>, ++ <&gcc GCC_PCIE2PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie2_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + rng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; +@@ -243,6 +289,52 @@ + status = "disabled"; + }; + ++ pcie3_phy: phy@f4000 { ++ compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; ++ reg = <0x000f4000 0x2000>; ++ ++ clocks = <&gcc GCC_PCIE3_AUX_CLK>, ++ <&gcc GCC_PCIE3_AHB_CLK>, ++ <&gcc GCC_PCIE3_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE3_PHY_BCR>, ++ <&gcc GCC_PCIE3PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie3_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie1_phy: phy@fc000 { ++ compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; ++ reg = <0x000fc000 0x1000>; ++ ++ clocks = <&gcc GCC_PCIE1_AUX_CLK>, ++ <&gcc GCC_PCIE1_AHB_CLK>, ++ <&gcc GCC_PCIE1_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE1_PHY_BCR>, ++ <&gcc GCC_PCIE1PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie1_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + qfprom: efuse@a4000 { + compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x5a1>; +@@ -309,10 +401,10 @@ + clocks = <&xo_board_clk>, + <&sleep_clk>, + <0>, +- <0>, +- <0>, +- <0>, +- <0>, ++ <&pcie0_phy>, ++ <&pcie1_phy>, ++ <&pcie2_phy>, ++ <&pcie3_phy>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -756,6 +848,326 @@ + status = "disabled"; + }; + }; ++ ++ pcie1: pcie@10000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x10000000 0xf1d>, ++ <0x10000f20 0xa8>, ++ <0x10001000 0x1000>, ++ <0x000f8000 0x4000>, ++ <0x10100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <1>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>, ++ <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, ++ <&gcc GCC_PCIE1_AXI_S_CLK>, ++ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE1_RCHNG_CLK>, ++ <&gcc GCC_PCIE1_AHB_CLK>, ++ <&gcc GCC_PCIE1_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE1_PIPE_ARES>, ++ <&gcc GCC_PCIE1_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_S_ARES>, ++ <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_M_ARES>, ++ <&gcc GCC_PCIE1_AUX_ARES>, ++ <&gcc GCC_PCIE1_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie1_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, ++ <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ ++ pcie3: pcie@18000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x18000000 0xf1d>, ++ <0x18000f20 0xa8>, ++ <0x18001000 0x1000>, ++ <0x000f0000 0x4000>, ++ <0x18100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <3>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <2>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>, ++ <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, ++ <&gcc GCC_PCIE3_AXI_S_CLK>, ++ <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE3_RCHNG_CLK>, ++ <&gcc GCC_PCIE3_AHB_CLK>, ++ <&gcc GCC_PCIE3_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE3_PIPE_ARES>, ++ <&gcc GCC_PCIE3_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE3_AXI_S_ARES>, ++ <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE3_AXI_M_ARES>, ++ <&gcc GCC_PCIE3_AUX_ARES>, ++ <&gcc GCC_PCIE3_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie3_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, ++ <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ ++ pcie2: pcie@20000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x20000000 0xf1d>, ++ <0x20000f20 0xa8>, ++ <0x20001000 0x1000>, ++ <0x00088000 0x4000>, ++ <0x20100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <2>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <2>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>, ++ <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, ++ <&gcc GCC_PCIE2_AXI_S_CLK>, ++ <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE2_RCHNG_CLK>, ++ <&gcc GCC_PCIE2_AHB_CLK>, ++ <&gcc GCC_PCIE2_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE2_PIPE_ARES>, ++ <&gcc GCC_PCIE2_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE2_AXI_S_ARES>, ++ <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE2_AXI_M_ARES>, ++ <&gcc GCC_PCIE2_AUX_ARES>, ++ <&gcc GCC_PCIE2_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie2_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, ++ <&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ ++ pcie0: pci@28000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x28000000 0xf1d>, ++ <0x28000f20 0xa8>, ++ <0x28001000 0x1000>, ++ <0x00080000 0x4000>, ++ <0x28100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <0>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>, ++ <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, ++ <&gcc GCC_PCIE0_AXI_S_CLK>, ++ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE0_RCHNG_CLK>, ++ <&gcc GCC_PCIE0_AHB_CLK>, ++ <&gcc GCC_PCIE0_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE0_PIPE_ARES>, ++ <&gcc GCC_PCIE0_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_S_ARES>, ++ <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_M_ARES>, ++ <&gcc GCC_PCIE0_AUX_ARES>, ++ <&gcc GCC_PCIE0_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie0_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, ++ <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ + }; + + thermal-zones { diff --git a/target/linux/qualcommbe/patches-6.12/0005-v6.14-arm64-dts-qcom-ipq9574-Enable-PCIe-PHYs-and-co.patch b/target/linux/qualcommbe/patches-6.12/0005-v6.14-arm64-dts-qcom-ipq9574-Enable-PCIe-PHYs-and-co.patch new file mode 100644 index 0000000000..f07e422966 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0005-v6.14-arm64-dts-qcom-ipq9574-Enable-PCIe-PHYs-and-co.patch @@ -0,0 +1,152 @@ +From 695cb0b8f9c525fe6d3ffbc349bc6087acd71201 Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 1 Aug 2024 11:18:02 +0530 +Subject: [PATCH 05/22] v6.14: arm64: dts: qcom: ipq9574: Enable PCIe PHYs and + controllers + +Enable the PCIe controller and PHY nodes corresponding to RDP 433. + +Signed-off-by: devi priya +Signed-off-by: Sricharan Ramabadhran +Link: https://lore.kernel.org/r/20240801054803.3015572-4-quic_srichara@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 113 ++++++++++++++++++++ + 1 file changed, 113 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +@@ -8,6 +8,7 @@ + + /dts-v1/; + ++#include + #include "ipq9574-rdp-common.dtsi" + + / { +@@ -15,6 +16,45 @@ + compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; + }; + ++&pcie1_phy { ++ status = "okay"; ++}; ++ ++&pcie1 { ++ pinctrl-0 = <&pcie1_default>; ++ pinctrl-names = "default"; ++ ++ perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ status = "okay"; ++}; ++ ++&pcie2 { ++ pinctrl-0 = <&pcie2_default>; ++ pinctrl-names = "default"; ++ ++ perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pcie3_phy { ++ status = "okay"; ++}; ++ ++&pcie3 { ++ pinctrl-0 = <&pcie3_default>; ++ pinctrl-names = "default"; ++ ++ perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ + &sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; +@@ -28,6 +68,79 @@ + }; + + &tlmm { ++ ++ pcie1_default: pcie1-default-state { ++ clkreq-n-pins { ++ pins = "gpio25"; ++ function = "pcie1_clk"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ ++ perst-n-pins { ++ pins = "gpio26"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ output-low; ++ }; ++ ++ wake-n-pins { ++ pins = "gpio27"; ++ function = "pcie1_wake"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ }; ++ ++ pcie2_default: pcie2-default-state { ++ clkreq-n-pins { ++ pins = "gpio28"; ++ function = "pcie2_clk"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ ++ perst-n-pins { ++ pins = "gpio29"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ output-low; ++ }; ++ ++ wake-n-pins { ++ pins = "gpio30"; ++ function = "pcie2_wake"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ }; ++ ++ pcie3_default: pcie3-default-state { ++ clkreq-n-pins { ++ pins = "gpio31"; ++ function = "pcie3_clk"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ ++ perst-n-pins { ++ pins = "gpio32"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ output-low; ++ }; ++ ++ wake-n-pins { ++ pins = "gpio33"; ++ function = "pcie3_wake"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ }; ++ + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio5"; diff --git a/target/linux/qualcommbe/patches-6.12/0006-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-contr.patch b/target/linux/qualcommbe/patches-6.12/0006-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-contr.patch new file mode 100644 index 0000000000..f0087764a1 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0006-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-contr.patch @@ -0,0 +1,132 @@ +From f4b785b3360c594bb10bd6f1dc5096b3e93f86d9 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Fri, 3 Jan 2025 15:31:34 +0800 +Subject: [PATCH 06/22] v6.14: dt-bindings: clock: qcom: Add CMN PLL clock + controller for IPQ SoC + +The CMN PLL controller provides clocks to networking hardware blocks +and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the +on-chip Wi-Fi, and produces output clocks at fixed rates. These output +rates are predetermined, and are unrelated to the input clock rate. +The primary purpose of CMN PLL is to supply clocks to the networking +hardware such as PPE (packet process engine), PCS and the externally +connected switch or PHY device. The CMN PLL block also outputs fixed +rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep +clock supplied to GCC. + +Signed-off-by: Luo Jie +Reviewed-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com +Signed-off-by: Bjorn Andersson +--- + .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 77 +++++++++++++++++++ + include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 22 ++++++ + 2 files changed, 99 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml + create mode 100644 include/dt-bindings/clock/qcom,ipq-cmn-pll.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +@@ -0,0 +1,77 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Qualcomm CMN PLL Clock Controller on IPQ SoC ++ ++maintainers: ++ - Bjorn Andersson ++ - Luo Jie ++ ++description: ++ The CMN (or common) PLL clock controller expects a reference ++ input clock. This reference clock is from the on-board Wi-Fi. ++ The CMN PLL supplies a number of fixed rate output clocks to ++ the devices providing networking functions and to GCC. These ++ networking hardware include PPE (packet process engine), PCS ++ and the externally connected switch or PHY devices. The CMN ++ PLL block also outputs fixed rate clocks to GCC. The PLL's ++ primary function is to enable fixed rate output clocks for ++ networking hardware functions used with the IPQ SoC. ++ ++properties: ++ compatible: ++ enum: ++ - qcom,ipq9574-cmn-pll ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: The reference clock. The supported clock rates include ++ 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ. ++ - description: The AHB clock ++ - description: The SYS clock ++ description: ++ The reference clock is the source clock of CMN PLL, which is from the ++ Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL ++ clock registers. ++ ++ clock-names: ++ items: ++ - const: ref ++ - const: ahb ++ - const: sys ++ ++ "#clock-cells": ++ const: 1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - "#clock-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ++ cmn_pll: clock-controller@9b000 { ++ compatible = "qcom,ipq9574-cmn-pll"; ++ reg = <0x0009b000 0x800>; ++ clocks = <&cmn_pll_ref_clk>, ++ <&gcc GCC_CMN_12GPLL_AHB_CLK>, ++ <&gcc GCC_CMN_12GPLL_SYS_CLK>; ++ clock-names = "ref", "ahb", "sys"; ++ #clock-cells = <1>; ++ assigned-clocks = <&cmn_pll CMN_PLL_CLK>; ++ assigned-clock-rates-u64 = /bits/ 64 <12000000000>; ++ }; ++... +--- /dev/null ++++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h +@@ -0,0 +1,22 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H ++#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H ++ ++/* CMN PLL core clock. */ ++#define CMN_PLL_CLK 0 ++ ++/* The output clocks from CMN PLL of IPQ9574. */ ++#define XO_24MHZ_CLK 1 ++#define SLEEP_32KHZ_CLK 2 ++#define PCS_31P25MHZ_CLK 3 ++#define NSS_1200MHZ_CLK 4 ++#define PPE_353MHZ_CLK 5 ++#define ETH0_50MHZ_CLK 6 ++#define ETH1_50MHZ_CLK 7 ++#define ETH2_50MHZ_CLK 8 ++#define ETH_25MHZ_CLK 9 ++#endif diff --git a/target/linux/qualcommbe/patches-6.12/0007-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-f.patch b/target/linux/qualcommbe/patches-6.12/0007-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-f.patch new file mode 100644 index 0000000000..edbbf8e13d --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0007-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-f.patch @@ -0,0 +1,501 @@ +From 51c937f5d7a3b239b637555bbd4dc0017b5cccba Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Fri, 3 Jan 2025 15:31:35 +0800 +Subject: [PATCH 07/22] v6.14: clk: qcom: Add CMN PLL clock controller driver + for IPQ SoC + +The CMN PLL clock controller supplies clocks to the hardware +blocks that together make up the Ethernet function on Qualcomm +IPQ SoCs and to GCC. The driver is initially supported for +IPQ9574 SoC. + +The CMN PLL clock controller expects a reference input clock +from the on-board Wi-Fi block acting as clock source. The input +reference clock needs to be configured to one of the supported +clock rates. + +The controller supplies a number of fixed-rate output clocks. +For the IPQ9574, there is one output clock of 353 MHZ to PPE +(Packet Process Engine) hardware block, three 50 MHZ output +clocks and an additional 25 MHZ output clock supplied to the +connected Ethernet devices. The PLL also supplies a 24 MHZ +clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25 +MHZ clock to PCS. + +Signed-off-by: Luo Jie +Acked-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-2-c89fb4d4849d@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/Kconfig | 9 + + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/ipq-cmn-pll.c | 435 +++++++++++++++++++++++++++++++++ + 3 files changed, 445 insertions(+) + create mode 100644 drivers/clk/qcom/ipq-cmn-pll.c + +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -190,6 +190,15 @@ config IPQ_APSS_6018 + Say Y if you want to support CPU frequency scaling on + ipq based devices. + ++config IPQ_CMN_PLL ++ tristate "IPQ CMN PLL Clock Controller" ++ help ++ Support for CMN PLL clock controller on IPQ platform. The ++ CMN PLL consumes the AHB/SYS clocks from GCC and supplies ++ the output clocks to the networking hardware and GCC blocks. ++ Say Y or M if you want to support CMN PLL clock on the IPQ ++ based devices. ++ + config IPQ_GCC_4019 + tristate "IPQ4019 Global Clock Controller" + help +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcs + obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o + obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o + obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o ++obj-$(CONFIG_IPQ_CMN_PLL) += ipq-cmn-pll.o + obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o + obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o + obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o +--- /dev/null ++++ b/drivers/clk/qcom/ipq-cmn-pll.c +@@ -0,0 +1,435 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* ++ * CMN PLL block expects the reference clock from on-board Wi-Fi block, ++ * and supplies fixed rate clocks as output to the networking hardware ++ * blocks and to GCC. The networking related blocks include PPE (packet ++ * process engine), the externally connected PHY or switch devices, and ++ * the PCS. ++ * ++ * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock ++ * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch), ++ * and one clock with 353 MHZ to PPE. The other fixed rate output clocks ++ * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS ++ * with 31.25 MHZ. ++ * ++ * +---------+ ++ * | GCC | ++ * +--+---+--+ ++ * AHB CLK| |SYS CLK ++ * V V ++ * +-------+---+------+ ++ * | +-------------> eth0-50mhz ++ * REF CLK | IPQ9574 | ++ * -------->+ +-------------> eth1-50mhz ++ * | CMN PLL block | ++ * | +-------------> eth2-50mhz ++ * | | ++ * +----+----+----+---+-------------> eth-25mhz ++ * | | | ++ * V V V ++ * GCC PCS NSS/PPE ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define CMN_PLL_REFCLK_SRC_SELECTION 0x28 ++#define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) ++ ++#define CMN_PLL_LOCKED 0x64 ++#define CMN_PLL_CLKS_LOCKED BIT(8) ++ ++#define CMN_PLL_POWER_ON_AND_RESET 0x780 ++#define CMN_ANA_EN_SW_RSTN BIT(6) ++ ++#define CMN_PLL_REFCLK_CONFIG 0x784 ++#define CMN_PLL_REFCLK_EXTERNAL BIT(9) ++#define CMN_PLL_REFCLK_DIV GENMASK(8, 4) ++#define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) ++ ++#define CMN_PLL_CTRL 0x78c ++#define CMN_PLL_CTRL_LOCK_DETECT_EN BIT(15) ++ ++#define CMN_PLL_DIVIDER_CTRL 0x794 ++#define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) ++ ++/** ++ * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information ++ * @id: Clock specifier to be supplied ++ * @name: Clock name to be registered ++ * @rate: Clock rate ++ */ ++struct cmn_pll_fixed_output_clk { ++ unsigned int id; ++ const char *name; ++ unsigned long rate; ++}; ++ ++/** ++ * struct clk_cmn_pll - CMN PLL hardware specific data ++ * @regmap: hardware regmap. ++ * @hw: handle between common and hardware-specific interfaces ++ */ ++struct clk_cmn_pll { ++ struct regmap *regmap; ++ struct clk_hw hw; ++}; ++ ++#define CLK_PLL_OUTPUT(_id, _name, _rate) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .rate = _rate, \ ++} ++ ++#define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) ++ ++static const struct regmap_config ipq_cmn_pll_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x7fc, ++ .fast_io = true, ++}; ++ ++static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { ++ CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), ++ CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), ++ CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), ++ CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), ++ CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), ++ CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), ++ CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), ++ CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), ++ CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), ++}; ++ ++/* ++ * CMN PLL has the single parent clock, which supports the several ++ * possible parent clock rates, each parent clock rate is reflected ++ * by the specific reference index value in the hardware. ++ */ ++static int ipq_cmn_pll_find_freq_index(unsigned long parent_rate) ++{ ++ int index = -EINVAL; ++ ++ switch (parent_rate) { ++ case 25000000: ++ index = 3; ++ break; ++ case 31250000: ++ index = 4; ++ break; ++ case 40000000: ++ index = 6; ++ break; ++ case 48000000: ++ case 96000000: ++ /* ++ * Parent clock rate 48 MHZ and 96 MHZ take the same value ++ * of reference clock index. 96 MHZ needs the source clock ++ * divider to be programmed as 2. ++ */ ++ index = 7; ++ break; ++ case 50000000: ++ index = 8; ++ break; ++ default: ++ break; ++ } ++ ++ return index; ++} ++ ++static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); ++ u32 val, factor; ++ ++ /* ++ * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted ++ * by HW according to the parent clock rate. ++ */ ++ regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); ++ factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val); ++ ++ return parent_rate * 2 * factor; ++} ++ ++static int clk_cmn_pll_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ int ret; ++ ++ /* Validate the rate of the single parent clock. */ ++ ret = ipq_cmn_pll_find_freq_index(req->best_parent_rate); ++ ++ return ret < 0 ? ret : 0; ++} ++ ++/* ++ * This function is used to initialize the CMN PLL to enable the fixed ++ * rate output clocks. It is expected to be configured once. ++ */ ++static int clk_cmn_pll_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); ++ int ret, index; ++ u32 val; ++ ++ /* ++ * Configure the reference input clock selection as per the given ++ * parent clock. The output clock rates are always of fixed value. ++ */ ++ index = ipq_cmn_pll_find_freq_index(parent_rate); ++ if (index < 0) ++ return index; ++ ++ ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, ++ CMN_PLL_REFCLK_INDEX, ++ FIELD_PREP(CMN_PLL_REFCLK_INDEX, index)); ++ if (ret) ++ return ret; ++ ++ /* ++ * Update the source clock rate selection and source clock ++ * divider as 2 when the parent clock rate is 96 MHZ. ++ */ ++ if (parent_rate == 96000000) { ++ ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, ++ CMN_PLL_REFCLK_DIV, ++ FIELD_PREP(CMN_PLL_REFCLK_DIV, 2)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION, ++ CMN_PLL_REFCLK_SRC_DIV, ++ FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 0)); ++ if (ret) ++ return ret; ++ } ++ ++ /* Enable PLL locked detect. */ ++ ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL, ++ CMN_PLL_CTRL_LOCK_DETECT_EN); ++ if (ret) ++ return ret; ++ ++ /* ++ * Reset the CMN PLL block to ensure the updated configurations ++ * take effect. ++ */ ++ ret = regmap_clear_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, ++ CMN_ANA_EN_SW_RSTN); ++ if (ret) ++ return ret; ++ ++ usleep_range(1000, 1200); ++ ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, ++ CMN_ANA_EN_SW_RSTN); ++ if (ret) ++ return ret; ++ ++ /* Stability check of CMN PLL output clocks. */ ++ return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val, ++ (val & CMN_PLL_CLKS_LOCKED), ++ 100, 100 * USEC_PER_MSEC); ++} ++ ++static const struct clk_ops clk_cmn_pll_ops = { ++ .recalc_rate = clk_cmn_pll_recalc_rate, ++ .determine_rate = clk_cmn_pll_determine_rate, ++ .set_rate = clk_cmn_pll_set_rate, ++}; ++ ++static struct clk_hw *ipq_cmn_pll_clk_hw_register(struct platform_device *pdev) ++{ ++ struct clk_parent_data pdata = { .index = 0 }; ++ struct device *dev = &pdev->dev; ++ struct clk_init_data init = {}; ++ struct clk_cmn_pll *cmn_pll; ++ struct regmap *regmap; ++ void __iomem *base; ++ int ret; ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return ERR_CAST(base); ++ ++ regmap = devm_regmap_init_mmio(dev, base, &ipq_cmn_pll_regmap_config); ++ if (IS_ERR(regmap)) ++ return ERR_CAST(regmap); ++ ++ cmn_pll = devm_kzalloc(dev, sizeof(*cmn_pll), GFP_KERNEL); ++ if (!cmn_pll) ++ return ERR_PTR(-ENOMEM); ++ ++ init.name = "cmn_pll"; ++ init.parent_data = &pdata; ++ init.num_parents = 1; ++ init.ops = &clk_cmn_pll_ops; ++ ++ cmn_pll->hw.init = &init; ++ cmn_pll->regmap = regmap; ++ ++ ret = devm_clk_hw_register(dev, &cmn_pll->hw); ++ if (ret) ++ return ERR_PTR(ret); ++ ++ return &cmn_pll->hw; ++} ++ ++static int ipq_cmn_pll_register_clks(struct platform_device *pdev) ++{ ++ const struct cmn_pll_fixed_output_clk *fixed_clk; ++ struct clk_hw_onecell_data *hw_data; ++ struct device *dev = &pdev->dev; ++ struct clk_hw *cmn_pll_hw; ++ unsigned int num_clks; ++ struct clk_hw *hw; ++ int ret, i; ++ ++ fixed_clk = ipq9574_output_clks; ++ num_clks = ARRAY_SIZE(ipq9574_output_clks); ++ ++ hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1), ++ GFP_KERNEL); ++ if (!hw_data) ++ return -ENOMEM; ++ ++ /* ++ * Register the CMN PLL clock, which is the parent clock of ++ * the fixed rate output clocks. ++ */ ++ cmn_pll_hw = ipq_cmn_pll_clk_hw_register(pdev); ++ if (IS_ERR(cmn_pll_hw)) ++ return PTR_ERR(cmn_pll_hw); ++ ++ /* Register the fixed rate output clocks. */ ++ for (i = 0; i < num_clks; i++) { ++ hw = clk_hw_register_fixed_rate_parent_hw(dev, fixed_clk[i].name, ++ cmn_pll_hw, 0, ++ fixed_clk[i].rate); ++ if (IS_ERR(hw)) { ++ ret = PTR_ERR(hw); ++ goto unregister_fixed_clk; ++ } ++ ++ hw_data->hws[fixed_clk[i].id] = hw; ++ } ++ ++ /* ++ * Provide the CMN PLL clock. The clock rate of CMN PLL ++ * is configured to 12 GHZ by DT property assigned-clock-rates-u64. ++ */ ++ hw_data->hws[CMN_PLL_CLK] = cmn_pll_hw; ++ hw_data->num = num_clks + 1; ++ ++ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); ++ if (ret) ++ goto unregister_fixed_clk; ++ ++ platform_set_drvdata(pdev, hw_data); ++ ++ return 0; ++ ++unregister_fixed_clk: ++ while (i > 0) ++ clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]); ++ ++ return ret; ++} ++ ++static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ ret = devm_pm_runtime_enable(dev); ++ if (ret) ++ return ret; ++ ++ ret = devm_pm_clk_create(dev); ++ if (ret) ++ return ret; ++ ++ /* ++ * To access the CMN PLL registers, the GCC AHB & SYS clocks ++ * of CMN PLL block need to be enabled. ++ */ ++ ret = pm_clk_add(dev, "ahb"); ++ if (ret) ++ return dev_err_probe(dev, ret, "Fail to add AHB clock\n"); ++ ++ ret = pm_clk_add(dev, "sys"); ++ if (ret) ++ return dev_err_probe(dev, ret, "Fail to add SYS clock\n"); ++ ++ ret = pm_runtime_resume_and_get(dev); ++ if (ret) ++ return ret; ++ ++ /* Register CMN PLL clock and fixed rate output clocks. */ ++ ret = ipq_cmn_pll_register_clks(pdev); ++ pm_runtime_put(dev); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "Fail to register CMN PLL clocks\n"); ++ ++ return 0; ++} ++ ++static void ipq_cmn_pll_clk_remove(struct platform_device *pdev) ++{ ++ struct clk_hw_onecell_data *hw_data = platform_get_drvdata(pdev); ++ int i; ++ ++ /* ++ * The clock with index CMN_PLL_CLK is unregistered by ++ * device management. ++ */ ++ for (i = 0; i < hw_data->num; i++) { ++ if (i != CMN_PLL_CLK) ++ clk_hw_unregister(hw_data->hws[i]); ++ } ++} ++ ++static const struct dev_pm_ops ipq_cmn_pll_pm_ops = { ++ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) ++}; ++ ++static const struct of_device_id ipq_cmn_pll_clk_ids[] = { ++ { .compatible = "qcom,ipq9574-cmn-pll", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); ++ ++static struct platform_driver ipq_cmn_pll_clk_driver = { ++ .probe = ipq_cmn_pll_clk_probe, ++ .remove = ipq_cmn_pll_clk_remove, ++ .driver = { ++ .name = "ipq_cmn_pll", ++ .of_match_table = ipq_cmn_pll_clk_ids, ++ .pm = &ipq_cmn_pll_pm_ops, ++ }, ++}; ++module_platform_driver(ipq_cmn_pll_clk_driver); ++ ++MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/qualcommbe/patches-6.12/0008-v6.14-arm64-dts-qcom-ipq9574-Add-CMN-PLL-node.patch b/target/linux/qualcommbe/patches-6.12/0008-v6.14-arm64-dts-qcom-ipq9574-Add-CMN-PLL-node.patch new file mode 100644 index 0000000000..deaa7ca891 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0008-v6.14-arm64-dts-qcom-ipq9574-Add-CMN-PLL-node.patch @@ -0,0 +1,122 @@ +From 20a3597d994c8ac372bbb66d9f11bccb7f405154 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Fri, 3 Jan 2025 15:31:37 +0800 +Subject: [PATCH 08/22] v6.14: arm64: dts: qcom: ipq9574: Add CMN PLL node + +The CMN PLL clock controller allows selection of an input clock rate +from a defined set of input clock rates. It in-turn supplies fixed +rate output clocks to the hardware blocks that provide the ethernet +functions such as PPE (Packet Process Engine) and connected switch or +PHY, and to GCC. + +The reference clock of CMN PLL is routed from XO to the CMN PLL through +the internal WiFi block. +.XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)-->48 MHZ to CMN PLL. + +The reference input clock from WiFi to CMN PLL is fully controlled by +the bootstrap pins which select the XO frequency (48 MHZ or 96 MHZ). +Based on this frequency, the divider in the internal Wi-Fi block is +automatically configured by hardware (1 for 48 MHZ, 2 for 96 MHZ), to +ensure output clock to CMN PLL is 48 MHZ. + +Signed-off-by: Luo Jie +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-4-c89fb4d4849d@quicinc.com +Signed-off-by: Bjorn Andersson +--- + .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 17 +++++++++++- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 ++++++++++++++++++- + 2 files changed, 41 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -3,7 +3,7 @@ + * IPQ9574 RDP board common device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. +- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + + /dts-v1/; +@@ -164,6 +164,21 @@ + status = "okay"; + }; + ++/* ++ * The bootstrap pins for the board select the XO clock frequency ++ * (48 MHZ or 96 MHZ used for different RDP type board). This setting ++ * automatically enables the right dividers, to ensure the reference ++ * clock output from WiFi to the CMN PLL is 48 MHZ. ++ */ ++&ref_48mhz_clk { ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ + &xo_board_clk { + clock-frequency = <24000000>; + }; ++ ++&xo_clk { ++ clock-frequency = <48000000>; ++}; +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -3,10 +3,11 @@ + * IPQ9574 SoC device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. +- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include ++#include + #include + #include + #include +@@ -19,6 +20,12 @@ + #size-cells = <2>; + + clocks { ++ ref_48mhz_clk: ref-48mhz-clk { ++ compatible = "fixed-factor-clock"; ++ clocks = <&xo_clk>; ++ #clock-cells = <0>; ++ }; ++ + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; +@@ -28,6 +35,11 @@ + compatible = "fixed-clock"; + #clock-cells = <0>; + }; ++ ++ xo_clk: xo-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ }; + }; + + cpus { +@@ -335,6 +347,18 @@ + status = "disabled"; + }; + ++ cmn_pll: clock-controller@9b000 { ++ compatible = "qcom,ipq9574-cmn-pll"; ++ reg = <0x0009b000 0x800>; ++ clocks = <&ref_48mhz_clk>, ++ <&gcc GCC_CMN_12GPLL_AHB_CLK>, ++ <&gcc GCC_CMN_12GPLL_SYS_CLK>; ++ clock-names = "ref", "ahb", "sys"; ++ #clock-cells = <1>; ++ assigned-clocks = <&cmn_pll CMN_PLL_CLK>; ++ assigned-clock-rates-u64 = /bits/ 64 <12000000000>; ++ }; ++ + qfprom: efuse@a4000 { + compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x5a1>; diff --git a/target/linux/qualcommbe/patches-6.12/0009-v6.14-arm64-dts-qcom-ipq9574-Update-xo_board_clk-to-.patch b/target/linux/qualcommbe/patches-6.12/0009-v6.14-arm64-dts-qcom-ipq9574-Update-xo_board_clk-to-.patch new file mode 100644 index 0000000000..e27d7791a7 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0009-v6.14-arm64-dts-qcom-ipq9574-Update-xo_board_clk-to-.patch @@ -0,0 +1,48 @@ +From 62307c5e153de617cb0827509fb964df051caaac Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Fri, 3 Jan 2025 15:31:38 +0800 +Subject: [PATCH 09/22] v6.14: arm64: dts: qcom: ipq9574: Update xo_board_clk + to use fixed factor clock + +xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock +48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog +block routing channel. + +Reviewed-by: Konrad Dybcio +Signed-off-by: Luo Jie +Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-5-c89fb4d4849d@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 7 ++++++- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 3 ++- + 2 files changed, 8 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -175,8 +175,13 @@ + clock-mult = <1>; + }; + ++/* ++ * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed ++ * from WiFi output clock 48 MHZ divided by 2. ++ */ + &xo_board_clk { +- clock-frequency = <24000000>; ++ clock-div = <2>; ++ clock-mult = <1>; + }; + + &xo_clk { +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -32,7 +32,8 @@ + }; + + xo_board_clk: xo-board-clk { +- compatible = "fixed-clock"; ++ compatible = "fixed-factor-clock"; ++ clocks = <&ref_48mhz_clk>; + #clock-cells = <0>; + }; + diff --git a/target/linux/qualcommbe/patches-6.12/0010-v6.14-net-phy-add-phy_inband_caps.patch b/target/linux/qualcommbe/patches-6.12/0010-v6.14-net-phy-add-phy_inband_caps.patch new file mode 100644 index 0000000000..0cd3680176 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0010-v6.14-net-phy-add-phy_inband_caps.patch @@ -0,0 +1,118 @@ +From 7b0f0f00a301906cc78d3c8974ea14ad8db29f0c Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 3 Dec 2024 15:31:02 +0000 +Subject: [PATCH 10/22] v6.14: net: phy: add phy_inband_caps() + +Add a method to query the PHY's in-band capabilities for a PHY +interface mode. + +Where the interface mode does not have in-band capability, or the PHY +driver has not been updated to return this information, then +phy_inband_caps() should return zero. Otherwise, PHY drivers will +return a value consisting of the following flags: + +LINK_INBAND_DISABLE indicates that the hardware does not support +in-band signalling, or can have in-band signalling configured via +software to be disabled. + +LINK_INBAND_ENABLE indicates that the hardware will use in-band +signalling, or can have in-band signalling configured via software +to be enabled. + +LINK_INBAND_BYPASS indicates that the hardware has the ability to +bypass in-band signalling when enabled after a timeout if the link +partner does not respond to its in-band signalling. + +This reports the PHY capabilities for the particular interface mode, +not the current configuration. + +Reviewed-by: Andrew Lunn +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1tIUre-006ITz-KF@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/phy.c | 21 +++++++++++++++++++++ + include/linux/phy.h | 28 ++++++++++++++++++++++++++++ + 2 files changed, 49 insertions(+) + +--- a/drivers/net/phy/phy.c ++++ b/drivers/net/phy/phy.c +@@ -1049,6 +1049,27 @@ static int phy_check_link_status(struct + } + + /** ++ * phy_inband_caps - query which in-band signalling modes are supported ++ * @phydev: a pointer to a &struct phy_device ++ * @interface: the interface mode for the PHY ++ * ++ * Returns zero if it is unknown what in-band signalling is supported by the ++ * PHY (e.g. because the PHY driver doesn't implement the method.) Otherwise, ++ * returns a bit mask of the LINK_INBAND_* values from ++ * &enum link_inband_signalling to describe which inband modes are supported ++ * by the PHY for this interface mode. ++ */ ++unsigned int phy_inband_caps(struct phy_device *phydev, ++ phy_interface_t interface) ++{ ++ if (phydev->drv && phydev->drv->inband_caps) ++ return phydev->drv->inband_caps(phydev, interface); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(phy_inband_caps); ++ ++/** + * _phy_start_aneg - start auto-negotiation for this PHY device + * @phydev: the phy_device struct + * +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -819,6 +819,24 @@ struct phy_tdr_config { + #define PHY_PAIR_ALL -1 + + /** ++ * enum link_inband_signalling - in-band signalling modes that are supported ++ * ++ * @LINK_INBAND_DISABLE: in-band signalling can be disabled ++ * @LINK_INBAND_ENABLE: in-band signalling can be enabled without bypass ++ * @LINK_INBAND_BYPASS: in-band signalling can be enabled with bypass ++ * ++ * The possible and required bits can only be used if the valid bit is set. ++ * If possible is clear, that means inband signalling can not be used. ++ * Required is only valid when possible is set, and means that inband ++ * signalling must be used. ++ */ ++enum link_inband_signalling { ++ LINK_INBAND_DISABLE = BIT(0), ++ LINK_INBAND_ENABLE = BIT(1), ++ LINK_INBAND_BYPASS = BIT(2), ++}; ++ ++/** + * struct phy_plca_cfg - Configuration of the PLCA (Physical Layer Collision + * Avoidance) Reconciliation Sublayer. + * +@@ -958,6 +976,14 @@ struct phy_driver { + int (*get_features)(struct phy_device *phydev); + + /** ++ * @inband_caps: query whether in-band is supported for the given PHY ++ * interface mode. Returns a bitmask of bits defined by enum ++ * link_inband_signalling. ++ */ ++ unsigned int (*inband_caps)(struct phy_device *phydev, ++ phy_interface_t interface); ++ ++ /** + * @get_rate_matching: Get the supported type of rate matching for a + * particular phy interface. This is used by phy consumers to determine + * whether to advertise lower-speed modes for that interface. It is +@@ -1842,6 +1868,8 @@ int phy_config_aneg(struct phy_device *p + int _phy_start_aneg(struct phy_device *phydev); + int phy_start_aneg(struct phy_device *phydev); + int phy_aneg_done(struct phy_device *phydev); ++unsigned int phy_inband_caps(struct phy_device *phydev, ++ phy_interface_t interface); + int phy_speed_down(struct phy_device *phydev, bool sync); + int phy_speed_up(struct phy_device *phydev); + bool phy_check_valid(int speed, int duplex, unsigned long *features); diff --git a/target/linux/qualcommbe/patches-6.12/0011-v6.14-net-phylink-add-pcs_inband_caps-method.patch b/target/linux/qualcommbe/patches-6.12/0011-v6.14-net-phylink-add-pcs_inband_caps-method.patch new file mode 100644 index 0000000000..689428cb9e --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0011-v6.14-net-phylink-add-pcs_inband_caps-method.patch @@ -0,0 +1,159 @@ +From 2d530b1085104f6aa0dfa35c908ac7c531941bf6 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 3 Dec 2024 15:31:28 +0000 +Subject: [PATCH 11/22] v6.14: net: phylink: add pcs_inband_caps() method + +Add a pcs_inband_caps() method to query the PCS for its inband link +capabilities, and use this to determine whether link modes used with +optical SFPs can be supported. + +When a PCS does not provide a method, we allow inband negotiation to +be either on or off, making this a no-op until the pcs_inband_caps() +method is implemented by a PCS driver. + +Reviewed-by: Andrew Lunn +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1tIUs4-006IUU-7K@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/phylink.c | 60 +++++++++++++++++++++++++++++++++++++++ + include/linux/phylink.h | 17 +++++++++++ + 2 files changed, 77 insertions(+) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -988,6 +988,15 @@ static void phylink_resolve_an_pause(str + } + } + ++static unsigned int phylink_pcs_inband_caps(struct phylink_pcs *pcs, ++ phy_interface_t interface) ++{ ++ if (pcs && pcs->ops->pcs_inband_caps) ++ return pcs->ops->pcs_inband_caps(pcs, interface); ++ ++ return 0; ++} ++ + static void phylink_pcs_pre_config(struct phylink_pcs *pcs, + phy_interface_t interface) + { +@@ -1041,6 +1050,24 @@ static void phylink_pcs_link_up(struct p + pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex); + } + ++/* Query inband for a specific interface mode, asking the MAC for the ++ * PCS which will be used to handle the interface mode. ++ */ ++static unsigned int phylink_inband_caps(struct phylink *pl, ++ phy_interface_t interface) ++{ ++ struct phylink_pcs *pcs; ++ ++ if (!pl->mac_ops->mac_select_pcs) ++ return 0; ++ ++ pcs = pl->mac_ops->mac_select_pcs(pl->config, interface); ++ if (!pcs) ++ return 0; ++ ++ return phylink_pcs_inband_caps(pcs, interface); ++} ++ + static void phylink_pcs_poll_stop(struct phylink *pl) + { + if (pl->cfg_link_an_mode == MLO_AN_INBAND) +@@ -2532,6 +2559,26 @@ int phylink_ethtool_ksettings_get(struct + } + EXPORT_SYMBOL_GPL(phylink_ethtool_ksettings_get); + ++static bool phylink_validate_pcs_inband_autoneg(struct phylink *pl, ++ phy_interface_t interface, ++ unsigned long *adv) ++{ ++ unsigned int inband = phylink_inband_caps(pl, interface); ++ unsigned int mask; ++ ++ /* If the PCS doesn't implement inband support, be permissive. */ ++ if (!inband) ++ return true; ++ ++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, adv)) ++ mask = LINK_INBAND_ENABLE; ++ else ++ mask = LINK_INBAND_DISABLE; ++ ++ /* Check whether the PCS implements the required mode */ ++ return !!(inband & mask); ++} ++ + /** + * phylink_ethtool_ksettings_set() - set the link settings + * @pl: a pointer to a &struct phylink returned from phylink_create() +@@ -2667,6 +2714,13 @@ int phylink_ethtool_ksettings_set(struct + phylink_is_empty_linkmode(config.advertising)) + return -EINVAL; + ++ /* Validate the autonegotiation state. We don't have a PHY in this ++ * situation, so the PCS is the media-facing entity. ++ */ ++ if (!phylink_validate_pcs_inband_autoneg(pl, config.interface, ++ config.advertising)) ++ return -EINVAL; ++ + mutex_lock(&pl->state_mutex); + pl->link_config.speed = config.speed; + pl->link_config.duplex = config.duplex; +@@ -3351,6 +3405,12 @@ static int phylink_sfp_config_optical(st + phylink_dbg(pl, "optical SFP: chosen %s interface\n", + phy_modes(interface)); + ++ if (!phylink_validate_pcs_inband_autoneg(pl, interface, ++ config.advertising)) { ++ phylink_err(pl, "autoneg setting not compatible with PCS"); ++ return -EINVAL; ++ } ++ + config.interface = interface; + + /* Ignore errors if we're expecting a PHY to attach later */ +--- a/include/linux/phylink.h ++++ b/include/linux/phylink.h +@@ -419,6 +419,7 @@ struct phylink_pcs { + /** + * struct phylink_pcs_ops - MAC PCS operations structure. + * @pcs_validate: validate the link configuration. ++ * @pcs_inband_caps: query inband support for interface mode. + * @pcs_enable: enable the PCS. + * @pcs_disable: disable the PCS. + * @pcs_pre_config: pre-mac_config method (for errata) +@@ -434,6 +435,8 @@ struct phylink_pcs { + struct phylink_pcs_ops { + int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported, + const struct phylink_link_state *state); ++ unsigned int (*pcs_inband_caps)(struct phylink_pcs *pcs, ++ phy_interface_t interface); + int (*pcs_enable)(struct phylink_pcs *pcs); + void (*pcs_disable)(struct phylink_pcs *pcs); + void (*pcs_pre_config)(struct phylink_pcs *pcs, +@@ -471,6 +474,20 @@ int pcs_validate(struct phylink_pcs *pcs + const struct phylink_link_state *state); + + /** ++ * pcs_inband_caps - query PCS in-band capabilities for interface mode. ++ * @pcs: a pointer to a &struct phylink_pcs. ++ * @interface: interface mode to be queried ++ * ++ * Returns zero if it is unknown what in-band signalling is supported by the ++ * PHY (e.g. because the PHY driver doesn't implement the method.) Otherwise, ++ * returns a bit mask of the LINK_INBAND_* values from ++ * &enum link_inband_signalling to describe which inband modes are supported ++ * for this interface mode. ++ */ ++unsigned int pcs_inband_caps(struct phylink_pcs *pcs, ++ phy_interface_t interface); ++ ++/** + * pcs_enable() - enable the PCS. + * @pcs: a pointer to a &struct phylink_pcs. + */ diff --git a/target/linux/qualcommbe/patches-6.12/0016-v6.15-spi-dt-bindings-Introduce-qcom-spi-qpic-snand.patch b/target/linux/qualcommbe/patches-6.12/0016-v6.15-spi-dt-bindings-Introduce-qcom-spi-qpic-snand.patch new file mode 100644 index 0000000000..6a1627a67e --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0016-v6.15-spi-dt-bindings-Introduce-qcom-spi-qpic-snand.patch @@ -0,0 +1,105 @@ +From 66fde1c5d29006127cc4fc5a12a0c42415c098bd Mon Sep 17 00:00:00 2001 +From: Md Sadre Alam +Date: Mon, 24 Feb 2025 16:44:13 +0530 +Subject: [PATCH 16/22] v6.15: spi: dt-bindings: Introduce qcom,spi-qpic-snand + +Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs. +It can work both in serial and parallel mode and supports typical +SPI-NAND page cache operations. + +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Md Sadre Alam +Link: https://patch.msgid.link/20250224111414.2809669-2-quic_mdalam@quicinc.com +Signed-off-by: Mark Brown +--- + .../bindings/spi/qcom,spi-qpic-snand.yaml | 83 +++++++++++++++++++ + 1 file changed, 83 insertions(+) + create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml +@@ -0,0 +1,83 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Qualcomm QPIC NAND controller ++ ++maintainers: ++ - Md sadre Alam ++ ++description: ++ The QCOM QPIC-SPI-NAND flash controller is an extended version of ++ the QCOM QPIC NAND flash controller. It can work both in serial ++ and parallel mode. It supports typical SPI-NAND page cache ++ operations in single, dual or quad IO mode with pipelined ECC ++ encoding/decoding using the QPIC ECC HW engine. ++ ++allOf: ++ - $ref: /schemas/spi/spi-controller.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - qcom,ipq9574-snand ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 3 ++ ++ clock-names: ++ items: ++ - const: core ++ - const: aon ++ - const: iom ++ ++ dmas: ++ items: ++ - description: tx DMA channel ++ - description: rx DMA channel ++ - description: cmd DMA channel ++ ++ dma-names: ++ items: ++ - const: tx ++ - const: rx ++ - const: cmd ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ spi@79b0000 { ++ compatible = "qcom,ipq9574-snand"; ++ reg = <0x1ac00000 0x800>; ++ ++ clocks = <&gcc GCC_QPIC_CLK>, ++ <&gcc GCC_QPIC_AHB_CLK>, ++ <&gcc GCC_QPIC_IO_MACRO_CLK>; ++ clock-names = "core", "aon", "iom"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ nand-ecc-engine = <&qpic_nand>; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ }; ++ }; diff --git a/target/linux/qualcommbe/patches-6.12/0018-v6.15-dt-bindings-clock-gcc-ipq9574-Add-definition-f.patch b/target/linux/qualcommbe/patches-6.12/0018-v6.15-dt-bindings-clock-gcc-ipq9574-Add-definition-f.patch new file mode 100644 index 0000000000..dfe655df94 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0018-v6.15-dt-bindings-clock-gcc-ipq9574-Add-definition-f.patch @@ -0,0 +1,25 @@ +From 25ce13ad8852f14835e650132ccf4fc0bf127699 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 13 Mar 2025 16:33:54 +0530 +Subject: [PATCH 18/22] v6.15: dt-bindings: clock: gcc-ipq9574: Add definition + for GPLL0_OUT_AUX + +Add the definition for GPLL0_OUT_AUX clock. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Devi Priya +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313110359.242491-2-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 + + 1 file changed, 1 insertion(+) + +--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h ++++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h +@@ -220,4 +220,5 @@ + #define GCC_PCIE1_PIPE_CLK 211 + #define GCC_PCIE2_PIPE_CLK 212 + #define GCC_PCIE3_PIPE_CLK 213 ++#define GPLL0_OUT_AUX 214 + #endif diff --git a/target/linux/qualcommbe/patches-6.12/0019-v6.15-dt-bindings-clock-Add-ipq9574-NSSCC-clock-and-.patch b/target/linux/qualcommbe/patches-6.12/0019-v6.15-dt-bindings-clock-Add-ipq9574-NSSCC-clock-and-.patch new file mode 100644 index 0000000000..0552b07b1e --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0019-v6.15-dt-bindings-clock-Add-ipq9574-NSSCC-clock-and-.patch @@ -0,0 +1,415 @@ +From 5ed04d121a8d24cc3151aa57a21a6c944ad6d7f3 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 13 Mar 2025 16:33:56 +0530 +Subject: [PATCH 19/22] v6.15: dt-bindings: clock: Add ipq9574 NSSCC clock and + reset definitions + +Add NSSCC clock and reset definitions for ipq9574. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Devi Priya +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313110359.242491-4-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + .../bindings/clock/qcom,ipq9574-nsscc.yaml | 98 +++++++++++ + .../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 ++++++++++++++++++ + .../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 +++++++++++++++ + 3 files changed, 384 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml + create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h + create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml +@@ -0,0 +1,98 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 ++ ++maintainers: ++ - Bjorn Andersson ++ - Anusha Rao ++ ++description: | ++ Qualcomm networking sub system clock control module provides the clocks, ++ resets on IPQ9574 ++ ++ See also:: ++ include/dt-bindings/clock/qcom,ipq9574-nsscc.h ++ include/dt-bindings/reset/qcom,ipq9574-nsscc.h ++ ++properties: ++ compatible: ++ const: qcom,ipq9574-nsscc ++ ++ clocks: ++ items: ++ - description: Board XO source ++ - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source ++ - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source ++ - description: GCC GPLL0 OUT AUX clock source ++ - description: Uniphy0 NSS Rx clock source ++ - description: Uniphy0 NSS Tx clock source ++ - description: Uniphy1 NSS Rx clock source ++ - description: Uniphy1 NSS Tx clock source ++ - description: Uniphy2 NSS Rx clock source ++ - description: Uniphy2 NSS Tx clock source ++ - description: GCC NSSCC clock source ++ ++ '#interconnect-cells': ++ const: 1 ++ ++ clock-names: ++ items: ++ - const: xo ++ - const: nss_1200 ++ - const: ppe_353 ++ - const: gpll0_out ++ - const: uniphy0_rx ++ - const: uniphy0_tx ++ - const: uniphy1_rx ++ - const: uniphy1_tx ++ - const: uniphy2_rx ++ - const: uniphy2_tx ++ - const: bus ++ ++required: ++ - compatible ++ - clocks ++ - clock-names ++ ++allOf: ++ - $ref: qcom,gcc.yaml# ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ clock-controller@39b00000 { ++ compatible = "qcom,ipq9574-nsscc"; ++ reg = <0x39b00000 0x80000>; ++ clocks = <&xo_board_clk>, ++ <&cmn_pll NSS_1200MHZ_CLK>, ++ <&cmn_pll PPE_353MHZ_CLK>, ++ <&gcc GPLL0_OUT_AUX>, ++ <&uniphy 0>, ++ <&uniphy 1>, ++ <&uniphy 2>, ++ <&uniphy 3>, ++ <&uniphy 4>, ++ <&uniphy 5>, ++ <&gcc GCC_NSSCC_CLK>; ++ clock-names = "xo", ++ "nss_1200", ++ "ppe_353", ++ "gpll0_out", ++ "uniphy0_rx", ++ "uniphy0_tx", ++ "uniphy1_rx", ++ "uniphy1_tx", ++ "uniphy2_rx", ++ "uniphy2_tx", ++ "bus"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++... +--- /dev/null ++++ b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h +@@ -0,0 +1,152 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. ++ */ ++ ++#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H ++#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H ++ ++#define NSS_CC_CE_APB_CLK 0 ++#define NSS_CC_CE_AXI_CLK 1 ++#define NSS_CC_CE_CLK_SRC 2 ++#define NSS_CC_CFG_CLK_SRC 3 ++#define NSS_CC_CLC_AXI_CLK 4 ++#define NSS_CC_CLC_CLK_SRC 5 ++#define NSS_CC_CRYPTO_CLK 6 ++#define NSS_CC_CRYPTO_CLK_SRC 7 ++#define NSS_CC_CRYPTO_PPE_CLK 8 ++#define NSS_CC_HAQ_AHB_CLK 9 ++#define NSS_CC_HAQ_AXI_CLK 10 ++#define NSS_CC_HAQ_CLK_SRC 11 ++#define NSS_CC_IMEM_AHB_CLK 12 ++#define NSS_CC_IMEM_CLK_SRC 13 ++#define NSS_CC_IMEM_QSB_CLK 14 ++#define NSS_CC_INT_CFG_CLK_SRC 15 ++#define NSS_CC_NSS_CSR_CLK 16 ++#define NSS_CC_NSSNOC_CE_APB_CLK 17 ++#define NSS_CC_NSSNOC_CE_AXI_CLK 18 ++#define NSS_CC_NSSNOC_CLC_AXI_CLK 19 ++#define NSS_CC_NSSNOC_CRYPTO_CLK 20 ++#define NSS_CC_NSSNOC_HAQ_AHB_CLK 21 ++#define NSS_CC_NSSNOC_HAQ_AXI_CLK 22 ++#define NSS_CC_NSSNOC_IMEM_AHB_CLK 23 ++#define NSS_CC_NSSNOC_IMEM_QSB_CLK 24 ++#define NSS_CC_NSSNOC_NSS_CSR_CLK 25 ++#define NSS_CC_NSSNOC_PPE_CFG_CLK 26 ++#define NSS_CC_NSSNOC_PPE_CLK 27 ++#define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28 ++#define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29 ++#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30 ++#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31 ++#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32 ++#define NSS_CC_PORT1_MAC_CLK 33 ++#define NSS_CC_PORT1_RX_CLK 34 ++#define NSS_CC_PORT1_RX_CLK_SRC 35 ++#define NSS_CC_PORT1_RX_DIV_CLK_SRC 36 ++#define NSS_CC_PORT1_TX_CLK 37 ++#define NSS_CC_PORT1_TX_CLK_SRC 38 ++#define NSS_CC_PORT1_TX_DIV_CLK_SRC 39 ++#define NSS_CC_PORT2_MAC_CLK 40 ++#define NSS_CC_PORT2_RX_CLK 41 ++#define NSS_CC_PORT2_RX_CLK_SRC 42 ++#define NSS_CC_PORT2_RX_DIV_CLK_SRC 43 ++#define NSS_CC_PORT2_TX_CLK 44 ++#define NSS_CC_PORT2_TX_CLK_SRC 45 ++#define NSS_CC_PORT2_TX_DIV_CLK_SRC 46 ++#define NSS_CC_PORT3_MAC_CLK 47 ++#define NSS_CC_PORT3_RX_CLK 48 ++#define NSS_CC_PORT3_RX_CLK_SRC 49 ++#define NSS_CC_PORT3_RX_DIV_CLK_SRC 50 ++#define NSS_CC_PORT3_TX_CLK 51 ++#define NSS_CC_PORT3_TX_CLK_SRC 52 ++#define NSS_CC_PORT3_TX_DIV_CLK_SRC 53 ++#define NSS_CC_PORT4_MAC_CLK 54 ++#define NSS_CC_PORT4_RX_CLK 55 ++#define NSS_CC_PORT4_RX_CLK_SRC 56 ++#define NSS_CC_PORT4_RX_DIV_CLK_SRC 57 ++#define NSS_CC_PORT4_TX_CLK 58 ++#define NSS_CC_PORT4_TX_CLK_SRC 59 ++#define NSS_CC_PORT4_TX_DIV_CLK_SRC 60 ++#define NSS_CC_PORT5_MAC_CLK 61 ++#define NSS_CC_PORT5_RX_CLK 62 ++#define NSS_CC_PORT5_RX_CLK_SRC 63 ++#define NSS_CC_PORT5_RX_DIV_CLK_SRC 64 ++#define NSS_CC_PORT5_TX_CLK 65 ++#define NSS_CC_PORT5_TX_CLK_SRC 66 ++#define NSS_CC_PORT5_TX_DIV_CLK_SRC 67 ++#define NSS_CC_PORT6_MAC_CLK 68 ++#define NSS_CC_PORT6_RX_CLK 69 ++#define NSS_CC_PORT6_RX_CLK_SRC 70 ++#define NSS_CC_PORT6_RX_DIV_CLK_SRC 71 ++#define NSS_CC_PORT6_TX_CLK 72 ++#define NSS_CC_PORT6_TX_CLK_SRC 73 ++#define NSS_CC_PORT6_TX_DIV_CLK_SRC 74 ++#define NSS_CC_PPE_CLK_SRC 75 ++#define NSS_CC_PPE_EDMA_CFG_CLK 76 ++#define NSS_CC_PPE_EDMA_CLK 77 ++#define NSS_CC_PPE_SWITCH_BTQ_CLK 78 ++#define NSS_CC_PPE_SWITCH_CFG_CLK 79 ++#define NSS_CC_PPE_SWITCH_CLK 80 ++#define NSS_CC_PPE_SWITCH_IPE_CLK 81 ++#define NSS_CC_UBI0_CLK_SRC 82 ++#define NSS_CC_UBI0_DIV_CLK_SRC 83 ++#define NSS_CC_UBI1_CLK_SRC 84 ++#define NSS_CC_UBI1_DIV_CLK_SRC 85 ++#define NSS_CC_UBI2_CLK_SRC 86 ++#define NSS_CC_UBI2_DIV_CLK_SRC 87 ++#define NSS_CC_UBI32_AHB0_CLK 88 ++#define NSS_CC_UBI32_AHB1_CLK 89 ++#define NSS_CC_UBI32_AHB2_CLK 90 ++#define NSS_CC_UBI32_AHB3_CLK 91 ++#define NSS_CC_UBI32_AXI0_CLK 92 ++#define NSS_CC_UBI32_AXI1_CLK 93 ++#define NSS_CC_UBI32_AXI2_CLK 94 ++#define NSS_CC_UBI32_AXI3_CLK 95 ++#define NSS_CC_UBI32_CORE0_CLK 96 ++#define NSS_CC_UBI32_CORE1_CLK 97 ++#define NSS_CC_UBI32_CORE2_CLK 98 ++#define NSS_CC_UBI32_CORE3_CLK 99 ++#define NSS_CC_UBI32_INTR0_AHB_CLK 100 ++#define NSS_CC_UBI32_INTR1_AHB_CLK 101 ++#define NSS_CC_UBI32_INTR2_AHB_CLK 102 ++#define NSS_CC_UBI32_INTR3_AHB_CLK 103 ++#define NSS_CC_UBI32_NC_AXI0_CLK 104 ++#define NSS_CC_UBI32_NC_AXI1_CLK 105 ++#define NSS_CC_UBI32_NC_AXI2_CLK 106 ++#define NSS_CC_UBI32_NC_AXI3_CLK 107 ++#define NSS_CC_UBI32_UTCM0_CLK 108 ++#define NSS_CC_UBI32_UTCM1_CLK 109 ++#define NSS_CC_UBI32_UTCM2_CLK 110 ++#define NSS_CC_UBI32_UTCM3_CLK 111 ++#define NSS_CC_UBI3_CLK_SRC 112 ++#define NSS_CC_UBI3_DIV_CLK_SRC 113 ++#define NSS_CC_UBI_AXI_CLK_SRC 114 ++#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115 ++#define NSS_CC_UNIPHY_PORT1_RX_CLK 116 ++#define NSS_CC_UNIPHY_PORT1_TX_CLK 117 ++#define NSS_CC_UNIPHY_PORT2_RX_CLK 118 ++#define NSS_CC_UNIPHY_PORT2_TX_CLK 119 ++#define NSS_CC_UNIPHY_PORT3_RX_CLK 120 ++#define NSS_CC_UNIPHY_PORT3_TX_CLK 121 ++#define NSS_CC_UNIPHY_PORT4_RX_CLK 122 ++#define NSS_CC_UNIPHY_PORT4_TX_CLK 123 ++#define NSS_CC_UNIPHY_PORT5_RX_CLK 124 ++#define NSS_CC_UNIPHY_PORT5_TX_CLK 125 ++#define NSS_CC_UNIPHY_PORT6_RX_CLK 126 ++#define NSS_CC_UNIPHY_PORT6_TX_CLK 127 ++#define NSS_CC_XGMAC0_PTP_REF_CLK 128 ++#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129 ++#define NSS_CC_XGMAC1_PTP_REF_CLK 130 ++#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131 ++#define NSS_CC_XGMAC2_PTP_REF_CLK 132 ++#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133 ++#define NSS_CC_XGMAC3_PTP_REF_CLK 134 ++#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135 ++#define NSS_CC_XGMAC4_PTP_REF_CLK 136 ++#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137 ++#define NSS_CC_XGMAC5_PTP_REF_CLK 138 ++#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139 ++#define UBI32_PLL 140 ++#define UBI32_PLL_MAIN 141 ++ ++#endif +--- /dev/null ++++ b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h +@@ -0,0 +1,134 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. ++ */ ++ ++#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H ++#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H ++ ++#define EDMA_HW_RESET 0 ++#define NSS_CC_CE_BCR 1 ++#define NSS_CC_CLC_BCR 2 ++#define NSS_CC_EIP197_BCR 3 ++#define NSS_CC_HAQ_BCR 4 ++#define NSS_CC_IMEM_BCR 5 ++#define NSS_CC_MAC_BCR 6 ++#define NSS_CC_PPE_BCR 7 ++#define NSS_CC_UBI_BCR 8 ++#define NSS_CC_UNIPHY_BCR 9 ++#define UBI3_CLKRST_CLAMP_ENABLE 10 ++#define UBI3_CORE_CLAMP_ENABLE 11 ++#define UBI2_CLKRST_CLAMP_ENABLE 12 ++#define UBI2_CORE_CLAMP_ENABLE 13 ++#define UBI1_CLKRST_CLAMP_ENABLE 14 ++#define UBI1_CORE_CLAMP_ENABLE 15 ++#define UBI0_CLKRST_CLAMP_ENABLE 16 ++#define UBI0_CORE_CLAMP_ENABLE 17 ++#define NSSNOC_NSS_CSR_ARES 18 ++#define NSS_CSR_ARES 19 ++#define PPE_BTQ_ARES 20 ++#define PPE_IPE_ARES 21 ++#define PPE_ARES 22 ++#define PPE_CFG_ARES 23 ++#define PPE_EDMA_ARES 24 ++#define PPE_EDMA_CFG_ARES 25 ++#define CRY_PPE_ARES 26 ++#define NSSNOC_PPE_ARES 27 ++#define NSSNOC_PPE_CFG_ARES 28 ++#define PORT1_MAC_ARES 29 ++#define PORT2_MAC_ARES 30 ++#define PORT3_MAC_ARES 31 ++#define PORT4_MAC_ARES 32 ++#define PORT5_MAC_ARES 33 ++#define PORT6_MAC_ARES 34 ++#define XGMAC0_PTP_REF_ARES 35 ++#define XGMAC1_PTP_REF_ARES 36 ++#define XGMAC2_PTP_REF_ARES 37 ++#define XGMAC3_PTP_REF_ARES 38 ++#define XGMAC4_PTP_REF_ARES 39 ++#define XGMAC5_PTP_REF_ARES 40 ++#define HAQ_AHB_ARES 41 ++#define HAQ_AXI_ARES 42 ++#define NSSNOC_HAQ_AHB_ARES 43 ++#define NSSNOC_HAQ_AXI_ARES 44 ++#define CE_APB_ARES 45 ++#define CE_AXI_ARES 46 ++#define NSSNOC_CE_APB_ARES 47 ++#define NSSNOC_CE_AXI_ARES 48 ++#define CRYPTO_ARES 49 ++#define NSSNOC_CRYPTO_ARES 50 ++#define NSSNOC_NC_AXI0_1_ARES 51 ++#define UBI0_CORE_ARES 52 ++#define UBI1_CORE_ARES 53 ++#define UBI2_CORE_ARES 54 ++#define UBI3_CORE_ARES 55 ++#define NC_AXI0_ARES 56 ++#define UTCM0_ARES 57 ++#define NC_AXI1_ARES 58 ++#define UTCM1_ARES 59 ++#define NC_AXI2_ARES 60 ++#define UTCM2_ARES 61 ++#define NC_AXI3_ARES 62 ++#define UTCM3_ARES 63 ++#define NSSNOC_NC_AXI0_ARES 64 ++#define AHB0_ARES 65 ++#define INTR0_AHB_ARES 66 ++#define AHB1_ARES 67 ++#define INTR1_AHB_ARES 68 ++#define AHB2_ARES 69 ++#define INTR2_AHB_ARES 70 ++#define AHB3_ARES 71 ++#define INTR3_AHB_ARES 72 ++#define NSSNOC_AHB0_ARES 73 ++#define NSSNOC_INT0_AHB_ARES 74 ++#define AXI0_ARES 75 ++#define AXI1_ARES 76 ++#define AXI2_ARES 77 ++#define AXI3_ARES 78 ++#define NSSNOC_AXI0_ARES 79 ++#define IMEM_QSB_ARES 80 ++#define NSSNOC_IMEM_QSB_ARES 81 ++#define IMEM_AHB_ARES 82 ++#define NSSNOC_IMEM_AHB_ARES 83 ++#define UNIPHY_PORT1_RX_ARES 84 ++#define UNIPHY_PORT1_TX_ARES 85 ++#define UNIPHY_PORT2_RX_ARES 86 ++#define UNIPHY_PORT2_TX_ARES 87 ++#define UNIPHY_PORT3_RX_ARES 88 ++#define UNIPHY_PORT3_TX_ARES 89 ++#define UNIPHY_PORT4_RX_ARES 90 ++#define UNIPHY_PORT4_TX_ARES 91 ++#define UNIPHY_PORT5_RX_ARES 92 ++#define UNIPHY_PORT5_TX_ARES 93 ++#define UNIPHY_PORT6_RX_ARES 94 ++#define UNIPHY_PORT6_TX_ARES 95 ++#define PORT1_RX_ARES 96 ++#define PORT1_TX_ARES 97 ++#define PORT2_RX_ARES 98 ++#define PORT2_TX_ARES 99 ++#define PORT3_RX_ARES 100 ++#define PORT3_TX_ARES 101 ++#define PORT4_RX_ARES 102 ++#define PORT4_TX_ARES 103 ++#define PORT5_RX_ARES 104 ++#define PORT5_TX_ARES 105 ++#define PORT6_RX_ARES 106 ++#define PORT6_TX_ARES 107 ++#define PPE_FULL_RESET 108 ++#define UNIPHY0_SOFT_RESET 109 ++#define UNIPHY1_SOFT_RESET 110 ++#define UNIPHY2_SOFT_RESET 111 ++#define UNIPHY_PORT1_ARES 112 ++#define UNIPHY_PORT2_ARES 113 ++#define UNIPHY_PORT3_ARES 114 ++#define UNIPHY_PORT4_ARES 115 ++#define UNIPHY_PORT5_ARES 116 ++#define UNIPHY_PORT6_ARES 117 ++#define NSSPORT1_RESET 118 ++#define NSSPORT2_RESET 119 ++#define NSSPORT3_RESET 120 ++#define NSSPORT4_RESET 121 ++#define NSSPORT5_RESET 122 ++#define NSSPORT6_RESET 123 ++ ++#endif diff --git a/target/linux/qualcommbe/patches-6.12/0020-v6.15-clk-qcom-gcc-ipq9574-Add-support-for-gpll0_out.patch b/target/linux/qualcommbe/patches-6.12/0020-v6.15-clk-qcom-gcc-ipq9574-Add-support-for-gpll0_out.patch new file mode 100644 index 0000000000..357fb18a71 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0020-v6.15-clk-qcom-gcc-ipq9574-Add-support-for-gpll0_out.patch @@ -0,0 +1,49 @@ +From c4e7d95921b074980ffd389254bcbfc045dd2a49 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 13 Mar 2025 16:33:55 +0530 +Subject: [PATCH 20/22] v6.15: clk: qcom: gcc-ipq9574: Add support for + gpll0_out_aux clock + +Add support for gpll0_out_aux clock which acts as the parent for +certain networking subsystem (nss) clocks. + +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Devi Priya +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313110359.242491-3-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/gcc-ipq9574.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq9574.c ++++ b/drivers/clk/qcom/gcc-ipq9574.c +@@ -108,6 +108,20 @@ static struct clk_alpha_pll_postdiv gpll + }, + }; + ++static struct clk_alpha_pll_postdiv gpll0_out_aux = { ++ .offset = 0x20000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "gpll0_out_aux", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gpll0_main.clkr.hw ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ }, ++}; ++ + static struct clk_alpha_pll gpll4_main = { + .offset = 0x22000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], +@@ -4222,6 +4236,7 @@ static struct clk_regmap *gcc_ipq9574_cl + [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, + [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, + [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, ++ [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr, + }; + + static const struct qcom_reset_map gcc_ipq9574_resets[] = { diff --git a/target/linux/qualcommbe/patches-6.12/0021-v6.15-clk-qcom-Add-NSS-clock-Controller-driver-for-I.patch b/target/linux/qualcommbe/patches-6.12/0021-v6.15-clk-qcom-Add-NSS-clock-Controller-driver-for-I.patch new file mode 100644 index 0000000000..e6d95f8bf3 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0021-v6.15-clk-qcom-Add-NSS-clock-Controller-driver-for-I.patch @@ -0,0 +1,3160 @@ +From 8b42bea7cf2a21e854becf29760a947bef5cde0b Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 13 Mar 2025 16:33:57 +0530 +Subject: [PATCH 21/22] v6.15: clk: qcom: Add NSS clock Controller driver for + IPQ9574 + +Add Networking Sub System Clock Controller (NSSCC) driver for ipq9574 based +devices. + +Reviewed-by: Konrad Dybcio +Signed-off-by: Devi Priya +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313110359.242491-5-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/Kconfig | 7 + + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/nsscc-ipq9574.c | 3110 ++++++++++++++++++++++++++++++ + 3 files changed, 3118 insertions(+) + create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c + +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -264,6 +264,13 @@ config IPQ_GCC_9574 + i2c, USB, SD/eMMC, etc. Select this for the root clock + of ipq9574. + ++config IPQ_NSSCC_9574 ++ tristate "IPQ9574 NSS Clock Controller" ++ depends on ARM64 || COMPILE_TEST ++ depends on IPQ_GCC_9574 ++ help ++ Support for NSS clock controller on ipq9574 devices. ++ + config IPQ_NSSCC_QCA8K + tristate "QCA8K(QCA8386 or QCA8084) NSS Clock Controller" + depends on MDIO_BUS +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -37,6 +37,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq601 + obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o + obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o + obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o ++obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o + obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o + obj-$(CONFIG_IPQ_NSSCC_QCA8K) += nsscc-qca8k.o + obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o +--- /dev/null ++++ b/drivers/clk/qcom/nsscc-ipq9574.c +@@ -0,0 +1,3110 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2021, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "clk-alpha-pll.h" ++#include "clk-branch.h" ++#include "clk-pll.h" ++#include "clk-rcg.h" ++#include "clk-regmap.h" ++#include "clk-regmap-divider.h" ++#include "clk-regmap-mux.h" ++#include "common.h" ++#include "reset.h" ++ ++/* Need to match the order of clocks in DT binding */ ++enum { ++ DT_XO, ++ DT_BIAS_PLL_CC_CLK, ++ DT_BIAS_PLL_UBI_NC_CLK, ++ DT_GCC_GPLL0_OUT_AUX, ++ DT_UNIPHY0_NSS_RX_CLK, ++ DT_UNIPHY0_NSS_TX_CLK, ++ DT_UNIPHY1_NSS_RX_CLK, ++ DT_UNIPHY1_NSS_TX_CLK, ++ DT_UNIPHY2_NSS_RX_CLK, ++ DT_UNIPHY2_NSS_TX_CLK, ++}; ++ ++enum { ++ P_XO, ++ P_BIAS_PLL_CC_CLK, ++ P_BIAS_PLL_UBI_NC_CLK, ++ P_GCC_GPLL0_OUT_AUX, ++ P_UBI32_PLL_OUT_MAIN, ++ P_UNIPHY0_NSS_RX_CLK, ++ P_UNIPHY0_NSS_TX_CLK, ++ P_UNIPHY1_NSS_RX_CLK, ++ P_UNIPHY1_NSS_TX_CLK, ++ P_UNIPHY2_NSS_RX_CLK, ++ P_UNIPHY2_NSS_TX_CLK, ++}; ++ ++static const struct alpha_pll_config ubi32_pll_config = { ++ .l = 0x3e, ++ .alpha = 0x6666, ++ .config_ctl_val = 0x200d4aa8, ++ .config_ctl_hi_val = 0x3c, ++ .main_output_mask = BIT(0), ++ .aux_output_mask = BIT(1), ++ .pre_div_val = 0x0, ++ .pre_div_mask = BIT(12), ++ .post_div_val = 0x0, ++ .post_div_mask = GENMASK(9, 8), ++ .alpha_en_mask = BIT(24), ++ .test_ctl_val = 0x1c0000c0, ++ .test_ctl_hi_val = 0x4000, ++}; ++ ++static struct clk_alpha_pll ubi32_pll_main = { ++ .offset = 0x28000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], ++ .flags = SUPPORTS_DYNAMIC_UPDATE, ++ .clkr = { ++ .hw.init = &(const struct clk_init_data) { ++ .name = "ubi32_pll_main", ++ .parent_data = &(const struct clk_parent_data) { ++ .index = DT_XO, ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_huayra_ops, ++ }, ++ }, ++}; ++ ++static struct clk_alpha_pll_postdiv ubi32_pll = { ++ .offset = 0x28000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], ++ .width = 2, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "ubi32_pll", ++ .parent_hws = (const struct clk_hw *[]) { ++ &ubi32_pll_main.clkr.hw ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_0[] = { ++ { P_XO, 0 }, ++ { P_BIAS_PLL_CC_CLK, 1 }, ++ { P_UNIPHY0_NSS_RX_CLK, 2 }, ++ { P_UNIPHY0_NSS_TX_CLK, 3 }, ++ { P_UNIPHY1_NSS_RX_CLK, 4 }, ++ { P_UNIPHY1_NSS_TX_CLK, 5 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_0[] = { ++ { .index = DT_XO }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++ { .index = DT_UNIPHY0_NSS_RX_CLK }, ++ { .index = DT_UNIPHY0_NSS_TX_CLK }, ++ { .index = DT_UNIPHY1_NSS_RX_CLK }, ++ { .index = DT_UNIPHY1_NSS_TX_CLK }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_1[] = { ++ { P_XO, 0 }, ++ { P_BIAS_PLL_UBI_NC_CLK, 1 }, ++ { P_GCC_GPLL0_OUT_AUX, 2 }, ++ { P_BIAS_PLL_CC_CLK, 6 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_1[] = { ++ { .index = DT_XO }, ++ { .index = DT_BIAS_PLL_UBI_NC_CLK }, ++ { .index = DT_GCC_GPLL0_OUT_AUX }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_2[] = { ++ { P_XO, 0 }, ++ { P_UBI32_PLL_OUT_MAIN, 1 }, ++ { P_GCC_GPLL0_OUT_AUX, 2 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_2[] = { ++ { .index = DT_XO }, ++ { .hw = &ubi32_pll.clkr.hw }, ++ { .index = DT_GCC_GPLL0_OUT_AUX }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_3[] = { ++ { P_XO, 0 }, ++ { P_BIAS_PLL_CC_CLK, 1 }, ++ { P_GCC_GPLL0_OUT_AUX, 2 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_3[] = { ++ { .index = DT_XO }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++ { .index = DT_GCC_GPLL0_OUT_AUX }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_4[] = { ++ { P_XO, 0 }, ++ { P_BIAS_PLL_CC_CLK, 1 }, ++ { P_UNIPHY0_NSS_RX_CLK, 2 }, ++ { P_UNIPHY0_NSS_TX_CLK, 3 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_4[] = { ++ { .index = DT_XO }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++ { .index = DT_UNIPHY0_NSS_RX_CLK }, ++ { .index = DT_UNIPHY0_NSS_TX_CLK }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_5[] = { ++ { P_XO, 0 }, ++ { P_BIAS_PLL_CC_CLK, 1 }, ++ { P_UNIPHY2_NSS_RX_CLK, 2 }, ++ { P_UNIPHY2_NSS_TX_CLK, 3 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_5[] = { ++ { .index = DT_XO }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++ { .index = DT_UNIPHY2_NSS_RX_CLK }, ++ { .index = DT_UNIPHY2_NSS_TX_CLK }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_6[] = { ++ { P_XO, 0 }, ++ { P_GCC_GPLL0_OUT_AUX, 2 }, ++ { P_BIAS_PLL_CC_CLK, 6 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_6[] = { ++ { .index = DT_XO }, ++ { .index = DT_GCC_GPLL0_OUT_AUX }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_7[] = { ++ { P_XO, 0 }, ++ { P_UBI32_PLL_OUT_MAIN, 1 }, ++ { P_GCC_GPLL0_OUT_AUX, 2 }, ++ { P_BIAS_PLL_CC_CLK, 6 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_7[] = { ++ { .index = DT_XO }, ++ { .hw = &ubi32_pll.clkr.hw }, ++ { .index = DT_GCC_GPLL0_OUT_AUX }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++}; ++ ++static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(353000000, P_BIAS_PLL_UBI_NC_CLK, 1, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_ce_clk_src = { ++ .cmd_rcgr = 0x28404, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_1, ++ .freq_tbl = ftbl_nss_cc_ce_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ce_clk_src", ++ .parent_data = nss_cc_parent_data_1, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = { ++ F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_cfg_clk_src = { ++ .cmd_rcgr = 0x28104, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_3, ++ .freq_tbl = ftbl_nss_cc_cfg_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_cfg_clk_src", ++ .parent_data = nss_cc_parent_data_3, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_3), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_nss_cc_clc_clk_src[] = { ++ F(533333333, P_GCC_GPLL0_OUT_AUX, 1.5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_clc_clk_src = { ++ .cmd_rcgr = 0x28604, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_6, ++ .freq_tbl = ftbl_nss_cc_clc_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_clc_clk_src", ++ .parent_data = nss_cc_parent_data_6, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_6), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_nss_cc_crypto_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(300000000, P_BIAS_PLL_CC_CLK, 4, 0, 0), ++ F(600000000, P_BIAS_PLL_CC_CLK, 2, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_crypto_clk_src = { ++ .cmd_rcgr = 0x16008, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_3, ++ .freq_tbl = ftbl_nss_cc_crypto_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_crypto_clk_src", ++ .parent_data = nss_cc_parent_data_3, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_3), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_haq_clk_src = { ++ .cmd_rcgr = 0x28304, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_1, ++ .freq_tbl = ftbl_nss_cc_ce_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_haq_clk_src", ++ .parent_data = nss_cc_parent_data_1, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_imem_clk_src = { ++ .cmd_rcgr = 0xe008, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_1, ++ .freq_tbl = ftbl_nss_cc_ce_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_imem_clk_src", ++ .parent_data = nss_cc_parent_data_1, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_nss_cc_int_cfg_clk_src[] = { ++ F(200000000, P_GCC_GPLL0_OUT_AUX, 4, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_int_cfg_clk_src = { ++ .cmd_rcgr = 0x287b4, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_3, ++ .freq_tbl = ftbl_nss_cc_int_cfg_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_int_cfg_clk_src", ++ .parent_data = nss_cc_parent_data_3, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_3), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = { ++ C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = { ++ C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = { ++ FMS(24000000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25), ++ FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0), ++ FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125), ++ FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), ++ { } ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = { ++ C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = { ++ C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = { ++ FMS(24000000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25), ++ FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0), ++ FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125), ++ FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), ++ { } ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = { ++ C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = { ++ C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_312p5[] = { ++ C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0), ++ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_cc_port5_rx_clk_src[] = { ++ FMS(24000000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_cc_port5_rx_clk_src_25), ++ FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0), ++ FM(125000000, ftbl_nss_cc_port5_rx_clk_src_125), ++ FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0), ++ FM(312500000, ftbl_nss_cc_port5_rx_clk_src_312p5), ++ { } ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = { ++ C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = { ++ C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_312p5[] = { ++ C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0), ++ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_cc_port5_tx_clk_src[] = { ++ FMS(24000000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_cc_port5_tx_clk_src_25), ++ FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0), ++ FM(125000000, ftbl_nss_cc_port5_tx_clk_src_125), ++ FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0), ++ FM(312500000, ftbl_nss_cc_port5_tx_clk_src_312p5), ++ { } ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_25[] = { ++ C(P_UNIPHY2_NSS_RX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY2_NSS_RX_CLK, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_125[] = { ++ C(P_UNIPHY2_NSS_RX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY2_NSS_RX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_cc_port6_rx_clk_src[] = { ++ FMS(24000000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_cc_port6_rx_clk_src_25), ++ FMS(78125000, P_UNIPHY2_NSS_RX_CLK, 4, 0, 0), ++ FM(125000000, ftbl_nss_cc_port6_rx_clk_src_125), ++ FMS(156250000, P_UNIPHY2_NSS_RX_CLK, 2, 0, 0), ++ FMS(312500000, P_UNIPHY2_NSS_RX_CLK, 1, 0, 0), ++ { } ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_25[] = { ++ C(P_UNIPHY2_NSS_TX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY2_NSS_TX_CLK, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_125[] = { ++ C(P_UNIPHY2_NSS_TX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY2_NSS_TX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_cc_port6_tx_clk_src[] = { ++ FMS(24000000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_cc_port6_tx_clk_src_25), ++ FMS(78125000, P_UNIPHY2_NSS_TX_CLK, 4, 0, 0), ++ FM(125000000, ftbl_nss_cc_port6_tx_clk_src_125), ++ FMS(156250000, P_UNIPHY2_NSS_TX_CLK, 2, 0, 0), ++ FMS(312500000, P_UNIPHY2_NSS_TX_CLK, 1, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_port1_rx_clk_src = { ++ .cmd_rcgr = 0x28110, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_rx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port1_tx_clk_src = { ++ .cmd_rcgr = 0x2811c, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_tx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port2_rx_clk_src = { ++ .cmd_rcgr = 0x28128, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_rx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port2_tx_clk_src = { ++ .cmd_rcgr = 0x28134, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_tx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port3_rx_clk_src = { ++ .cmd_rcgr = 0x28140, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_rx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port3_tx_clk_src = { ++ .cmd_rcgr = 0x2814c, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_tx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port4_rx_clk_src = { ++ .cmd_rcgr = 0x28158, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_rx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port4_tx_clk_src = { ++ .cmd_rcgr = 0x28164, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_tx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port5_rx_clk_src = { ++ .cmd_rcgr = 0x28170, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_0, ++ .freq_multi_tbl = ftbl_nss_cc_port5_rx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_rx_clk_src", ++ .parent_data = nss_cc_parent_data_0, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port5_tx_clk_src = { ++ .cmd_rcgr = 0x2817c, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_0, ++ .freq_multi_tbl = ftbl_nss_cc_port5_tx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_tx_clk_src", ++ .parent_data = nss_cc_parent_data_0, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port6_rx_clk_src = { ++ .cmd_rcgr = 0x28188, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_5, ++ .freq_multi_tbl = ftbl_nss_cc_port6_rx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_rx_clk_src", ++ .parent_data = nss_cc_parent_data_5, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_5), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port6_tx_clk_src = { ++ .cmd_rcgr = 0x28194, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_5, ++ .freq_multi_tbl = ftbl_nss_cc_port6_tx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_tx_clk_src", ++ .parent_data = nss_cc_parent_data_5, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_5), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_ppe_clk_src = { ++ .cmd_rcgr = 0x28204, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_1, ++ .freq_tbl = ftbl_nss_cc_ce_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_clk_src", ++ .parent_data = nss_cc_parent_data_1, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_nss_cc_ubi0_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(187200000, P_UBI32_PLL_OUT_MAIN, 8, 0, 0), ++ F(748800000, P_UBI32_PLL_OUT_MAIN, 2, 0, 0), ++ F(1497600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0), ++ F(1689600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_ubi0_clk_src = { ++ .cmd_rcgr = 0x28704, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_2, ++ .freq_tbl = ftbl_nss_cc_ubi0_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi0_clk_src", ++ .parent_data = nss_cc_parent_data_2, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_ubi1_clk_src = { ++ .cmd_rcgr = 0x2870c, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_2, ++ .freq_tbl = ftbl_nss_cc_ubi0_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi1_clk_src", ++ .parent_data = nss_cc_parent_data_2, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_ubi2_clk_src = { ++ .cmd_rcgr = 0x28714, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_2, ++ .freq_tbl = ftbl_nss_cc_ubi0_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi2_clk_src", ++ .parent_data = nss_cc_parent_data_2, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_ubi3_clk_src = { ++ .cmd_rcgr = 0x2871c, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_2, ++ .freq_tbl = ftbl_nss_cc_ubi0_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi3_clk_src", ++ .parent_data = nss_cc_parent_data_2, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_ubi_axi_clk_src = { ++ .cmd_rcgr = 0x28724, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_7, ++ .freq_tbl = ftbl_nss_cc_clc_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi_axi_clk_src", ++ .parent_data = nss_cc_parent_data_7, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_7), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_ubi_nc_axi_bfdcd_clk_src = { ++ .cmd_rcgr = 0x2872c, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_1, ++ .freq_tbl = ftbl_nss_cc_ce_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi_nc_axi_bfdcd_clk_src", ++ .parent_data = nss_cc_parent_data_1, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = { ++ .reg = 0x28118, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_rx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port1_rx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = { ++ .reg = 0x28124, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_tx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port1_tx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = { ++ .reg = 0x28130, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_rx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port2_rx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = { ++ .reg = 0x2813c, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_tx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port2_tx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port3_rx_div_clk_src = { ++ .reg = 0x28148, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_rx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port3_rx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port3_tx_div_clk_src = { ++ .reg = 0x28154, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_tx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port3_tx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port4_rx_div_clk_src = { ++ .reg = 0x28160, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_rx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port4_rx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port4_tx_div_clk_src = { ++ .reg = 0x2816c, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_tx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port4_tx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port5_rx_div_clk_src = { ++ .reg = 0x28178, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_rx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port5_rx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port5_tx_div_clk_src = { ++ .reg = 0x28184, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_tx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port5_tx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port6_rx_div_clk_src = { ++ .reg = 0x28190, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_rx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port6_rx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port6_tx_div_clk_src = { ++ .reg = 0x2819c, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_tx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port6_tx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_ubi0_div_clk_src = { ++ .reg = 0x287a4, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi0_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi0_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_ubi1_div_clk_src = { ++ .reg = 0x287a8, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi1_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi1_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_ubi2_div_clk_src = { ++ .reg = 0x287ac, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi2_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi2_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_ubi3_div_clk_src = { ++ .reg = 0x287b0, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi3_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi3_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = { ++ .reg = 0x28214, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac0_ptp_ref_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = { ++ .reg = 0x28218, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac1_ptp_ref_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_xgmac2_ptp_ref_div_clk_src = { ++ .reg = 0x2821c, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac2_ptp_ref_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_xgmac3_ptp_ref_div_clk_src = { ++ .reg = 0x28220, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac3_ptp_ref_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_xgmac4_ptp_ref_div_clk_src = { ++ .reg = 0x28224, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac4_ptp_ref_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_xgmac5_ptp_ref_div_clk_src = { ++ .reg = 0x28228, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac5_ptp_ref_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ce_apb_clk = { ++ .halt_reg = 0x2840c, ++ .clkr = { ++ .enable_reg = 0x2840c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ce_apb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ce_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ce_axi_clk = { ++ .halt_reg = 0x28410, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28410, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ce_axi_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ce_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_clc_axi_clk = { ++ .halt_reg = 0x2860c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2860c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_clc_axi_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_clc_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_crypto_clk = { ++ .halt_reg = 0x1601c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x1601c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_crypto_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_crypto_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_crypto_ppe_clk = { ++ .halt_reg = 0x28240, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28240, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_crypto_ppe_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_haq_ahb_clk = { ++ .halt_reg = 0x2830c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2830c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_haq_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_haq_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_haq_axi_clk = { ++ .halt_reg = 0x28310, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28310, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_haq_axi_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_haq_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_imem_ahb_clk = { ++ .halt_reg = 0xe018, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0xe018, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_imem_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_imem_qsb_clk = { ++ .halt_reg = 0xe010, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0xe010, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_imem_qsb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_imem_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nss_csr_clk = { ++ .halt_reg = 0x281d0, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281d0, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nss_csr_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ce_apb_clk = { ++ .halt_reg = 0x28414, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28414, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ce_apb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ce_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ce_axi_clk = { ++ .halt_reg = 0x28418, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28418, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ce_axi_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ce_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_clc_axi_clk = { ++ .halt_reg = 0x28610, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28610, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_clc_axi_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_clc_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_crypto_clk = { ++ .halt_reg = 0x16020, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x16020, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_crypto_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_crypto_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_haq_ahb_clk = { ++ .halt_reg = 0x28314, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28314, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_haq_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_haq_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_haq_axi_clk = { ++ .halt_reg = 0x28318, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28318, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_haq_axi_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_haq_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_imem_ahb_clk = { ++ .halt_reg = 0xe01c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0xe01c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_imem_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_imem_qsb_clk = { ++ .halt_reg = 0xe014, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0xe014, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_imem_qsb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_imem_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_nss_csr_clk = { ++ .halt_reg = 0x281d4, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281d4, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_nss_csr_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = { ++ .halt_reg = 0x28248, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28248, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ppe_cfg_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ppe_clk = { ++ .halt_reg = 0x28244, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28244, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ppe_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ubi32_ahb0_clk = { ++ .halt_reg = 0x28788, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28788, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ubi32_ahb0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ubi32_axi0_clk = { ++ .halt_reg = 0x287a0, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x287a0, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ubi32_axi0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ubi32_int0_ahb_clk = { ++ .halt_reg = 0x2878c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2878c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ubi32_int0_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_int_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_1_clk = { ++ .halt_reg = 0x287bc, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x287bc, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ubi32_nc_axi0_1_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_clk = { ++ .halt_reg = 0x28764, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28764, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ubi32_nc_axi0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port1_mac_clk = { ++ .halt_reg = 0x2824c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2824c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_mac_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port1_rx_clk = { ++ .halt_reg = 0x281a0, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281a0, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port1_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port1_tx_clk = { ++ .halt_reg = 0x281a4, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281a4, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port1_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port2_mac_clk = { ++ .halt_reg = 0x28250, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28250, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_mac_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port2_rx_clk = { ++ .halt_reg = 0x281a8, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281a8, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port2_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port2_tx_clk = { ++ .halt_reg = 0x281ac, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281ac, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port2_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port3_mac_clk = { ++ .halt_reg = 0x28254, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28254, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_mac_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port3_rx_clk = { ++ .halt_reg = 0x281b0, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281b0, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port3_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port3_tx_clk = { ++ .halt_reg = 0x281b4, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281b4, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port3_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port4_mac_clk = { ++ .halt_reg = 0x28258, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28258, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_mac_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port4_rx_clk = { ++ .halt_reg = 0x281b8, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281b8, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port4_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port4_tx_clk = { ++ .halt_reg = 0x281bc, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281bc, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port4_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port5_mac_clk = { ++ .halt_reg = 0x2825c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2825c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_mac_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port5_rx_clk = { ++ .halt_reg = 0x281c0, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281c0, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port5_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port5_tx_clk = { ++ .halt_reg = 0x281c4, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281c4, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port5_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port6_mac_clk = { ++ .halt_reg = 0x28260, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28260, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_mac_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port6_rx_clk = { ++ .halt_reg = 0x281c8, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281c8, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port6_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port6_tx_clk = { ++ .halt_reg = 0x281cc, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281cc, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port6_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ppe_edma_cfg_clk = { ++ .halt_reg = 0x2823c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2823c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_edma_cfg_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ppe_edma_clk = { ++ .halt_reg = 0x28238, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28238, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_edma_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ppe_switch_btq_clk = { ++ .halt_reg = 0x2827c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2827c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_switch_btq_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ppe_switch_cfg_clk = { ++ .halt_reg = 0x28234, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28234, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_switch_cfg_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ppe_switch_clk = { ++ .halt_reg = 0x28230, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28230, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_switch_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ppe_switch_ipe_clk = { ++ .halt_reg = 0x2822c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2822c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_switch_ipe_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_ahb0_clk = { ++ .halt_reg = 0x28768, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28768, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_ahb0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_ahb1_clk = { ++ .halt_reg = 0x28770, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28770, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_ahb1_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_ahb2_clk = { ++ .halt_reg = 0x28778, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28778, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_ahb2_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_ahb3_clk = { ++ .halt_reg = 0x28780, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28780, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_ahb3_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_axi0_clk = { ++ .halt_reg = 0x28790, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28790, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_axi0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_axi1_clk = { ++ .halt_reg = 0x28794, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28794, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_axi1_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_axi2_clk = { ++ .halt_reg = 0x28798, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28798, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_axi2_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_axi3_clk = { ++ .halt_reg = 0x2879c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2879c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_axi3_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_core0_clk = { ++ .halt_reg = 0x28734, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28734, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_core0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi0_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_core1_clk = { ++ .halt_reg = 0x28738, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28738, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_core1_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi1_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_core2_clk = { ++ .halt_reg = 0x2873c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2873c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_core2_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi2_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_core3_clk = { ++ .halt_reg = 0x28740, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28740, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_core3_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi3_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_intr0_ahb_clk = { ++ .halt_reg = 0x2876c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2876c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_intr0_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_int_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_intr1_ahb_clk = { ++ .halt_reg = 0x28774, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28774, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_intr1_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_int_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_intr2_ahb_clk = { ++ .halt_reg = 0x2877c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2877c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_intr2_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_int_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_intr3_ahb_clk = { ++ .halt_reg = 0x28784, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28784, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_intr3_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_int_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_nc_axi0_clk = { ++ .halt_reg = 0x28744, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28744, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_nc_axi0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_nc_axi1_clk = { ++ .halt_reg = 0x2874c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2874c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_nc_axi1_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_nc_axi2_clk = { ++ .halt_reg = 0x28754, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28754, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_nc_axi2_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_nc_axi3_clk = { ++ .halt_reg = 0x2875c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2875c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_nc_axi3_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_utcm0_clk = { ++ .halt_reg = 0x28748, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28748, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_utcm0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_utcm1_clk = { ++ .halt_reg = 0x28750, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28750, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_utcm1_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_utcm2_clk = { ++ .halt_reg = 0x28758, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28758, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_utcm2_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_utcm3_clk = { ++ .halt_reg = 0x28760, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28760, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_utcm3_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port1_rx_clk = { ++ .halt_reg = 0x28904, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28904, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port1_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port1_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port1_tx_clk = { ++ .halt_reg = 0x28908, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28908, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port1_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port1_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port2_rx_clk = { ++ .halt_reg = 0x2890c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2890c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port2_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port2_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port2_tx_clk = { ++ .halt_reg = 0x28910, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28910, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port2_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port2_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port3_rx_clk = { ++ .halt_reg = 0x28914, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28914, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port3_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port3_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port3_tx_clk = { ++ .halt_reg = 0x28918, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28918, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port3_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port3_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port4_rx_clk = { ++ .halt_reg = 0x2891c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2891c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port4_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port4_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port4_tx_clk = { ++ .halt_reg = 0x28920, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28920, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port4_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port4_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port5_rx_clk = { ++ .halt_reg = 0x28924, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28924, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port5_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port5_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port5_tx_clk = { ++ .halt_reg = 0x28928, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28928, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port5_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port5_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port6_rx_clk = { ++ .halt_reg = 0x2892c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2892c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port6_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port6_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port6_tx_clk = { ++ .halt_reg = 0x28930, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28930, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port6_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port6_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = { ++ .halt_reg = 0x28264, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28264, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac0_ptp_ref_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = { ++ .halt_reg = 0x28268, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28268, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac1_ptp_ref_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_xgmac2_ptp_ref_clk = { ++ .halt_reg = 0x2826c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2826c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac2_ptp_ref_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_xgmac3_ptp_ref_clk = { ++ .halt_reg = 0x28270, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28270, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac3_ptp_ref_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_xgmac4_ptp_ref_clk = { ++ .halt_reg = 0x28274, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28274, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac4_ptp_ref_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_xgmac5_ptp_ref_clk = { ++ .halt_reg = 0x28278, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28278, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac5_ptp_ref_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_regmap *nss_cc_ipq9574_clocks[] = { ++ [NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr, ++ [NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr, ++ [NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr, ++ [NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr, ++ [NSS_CC_CLC_AXI_CLK] = &nss_cc_clc_axi_clk.clkr, ++ [NSS_CC_CLC_CLK_SRC] = &nss_cc_clc_clk_src.clkr, ++ [NSS_CC_CRYPTO_CLK] = &nss_cc_crypto_clk.clkr, ++ [NSS_CC_CRYPTO_CLK_SRC] = &nss_cc_crypto_clk_src.clkr, ++ [NSS_CC_CRYPTO_PPE_CLK] = &nss_cc_crypto_ppe_clk.clkr, ++ [NSS_CC_HAQ_AHB_CLK] = &nss_cc_haq_ahb_clk.clkr, ++ [NSS_CC_HAQ_AXI_CLK] = &nss_cc_haq_axi_clk.clkr, ++ [NSS_CC_HAQ_CLK_SRC] = &nss_cc_haq_clk_src.clkr, ++ [NSS_CC_IMEM_AHB_CLK] = &nss_cc_imem_ahb_clk.clkr, ++ [NSS_CC_IMEM_CLK_SRC] = &nss_cc_imem_clk_src.clkr, ++ [NSS_CC_IMEM_QSB_CLK] = &nss_cc_imem_qsb_clk.clkr, ++ [NSS_CC_INT_CFG_CLK_SRC] = &nss_cc_int_cfg_clk_src.clkr, ++ [NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr, ++ [NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr, ++ [NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr, ++ [NSS_CC_NSSNOC_CLC_AXI_CLK] = &nss_cc_nssnoc_clc_axi_clk.clkr, ++ [NSS_CC_NSSNOC_CRYPTO_CLK] = &nss_cc_nssnoc_crypto_clk.clkr, ++ [NSS_CC_NSSNOC_HAQ_AHB_CLK] = &nss_cc_nssnoc_haq_ahb_clk.clkr, ++ [NSS_CC_NSSNOC_HAQ_AXI_CLK] = &nss_cc_nssnoc_haq_axi_clk.clkr, ++ [NSS_CC_NSSNOC_IMEM_AHB_CLK] = &nss_cc_nssnoc_imem_ahb_clk.clkr, ++ [NSS_CC_NSSNOC_IMEM_QSB_CLK] = &nss_cc_nssnoc_imem_qsb_clk.clkr, ++ [NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr, ++ [NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr, ++ [NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr, ++ [NSS_CC_NSSNOC_UBI32_AHB0_CLK] = &nss_cc_nssnoc_ubi32_ahb0_clk.clkr, ++ [NSS_CC_NSSNOC_UBI32_AXI0_CLK] = &nss_cc_nssnoc_ubi32_axi0_clk.clkr, ++ [NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK] = ++ &nss_cc_nssnoc_ubi32_int0_ahb_clk.clkr, ++ [NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK] = ++ &nss_cc_nssnoc_ubi32_nc_axi0_1_clk.clkr, ++ [NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK] = ++ &nss_cc_nssnoc_ubi32_nc_axi0_clk.clkr, ++ [NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr, ++ [NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr, ++ [NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr, ++ [NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr, ++ [NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr, ++ [NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr, ++ [NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr, ++ [NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr, ++ [NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr, ++ [NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr, ++ [NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr, ++ [NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr, ++ [NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr, ++ [NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr, ++ [NSS_CC_PORT3_MAC_CLK] = &nss_cc_port3_mac_clk.clkr, ++ [NSS_CC_PORT3_RX_CLK] = &nss_cc_port3_rx_clk.clkr, ++ [NSS_CC_PORT3_RX_CLK_SRC] = &nss_cc_port3_rx_clk_src.clkr, ++ [NSS_CC_PORT3_RX_DIV_CLK_SRC] = &nss_cc_port3_rx_div_clk_src.clkr, ++ [NSS_CC_PORT3_TX_CLK] = &nss_cc_port3_tx_clk.clkr, ++ [NSS_CC_PORT3_TX_CLK_SRC] = &nss_cc_port3_tx_clk_src.clkr, ++ [NSS_CC_PORT3_TX_DIV_CLK_SRC] = &nss_cc_port3_tx_div_clk_src.clkr, ++ [NSS_CC_PORT4_MAC_CLK] = &nss_cc_port4_mac_clk.clkr, ++ [NSS_CC_PORT4_RX_CLK] = &nss_cc_port4_rx_clk.clkr, ++ [NSS_CC_PORT4_RX_CLK_SRC] = &nss_cc_port4_rx_clk_src.clkr, ++ [NSS_CC_PORT4_RX_DIV_CLK_SRC] = &nss_cc_port4_rx_div_clk_src.clkr, ++ [NSS_CC_PORT4_TX_CLK] = &nss_cc_port4_tx_clk.clkr, ++ [NSS_CC_PORT4_TX_CLK_SRC] = &nss_cc_port4_tx_clk_src.clkr, ++ [NSS_CC_PORT4_TX_DIV_CLK_SRC] = &nss_cc_port4_tx_div_clk_src.clkr, ++ [NSS_CC_PORT5_MAC_CLK] = &nss_cc_port5_mac_clk.clkr, ++ [NSS_CC_PORT5_RX_CLK] = &nss_cc_port5_rx_clk.clkr, ++ [NSS_CC_PORT5_RX_CLK_SRC] = &nss_cc_port5_rx_clk_src.clkr, ++ [NSS_CC_PORT5_RX_DIV_CLK_SRC] = &nss_cc_port5_rx_div_clk_src.clkr, ++ [NSS_CC_PORT5_TX_CLK] = &nss_cc_port5_tx_clk.clkr, ++ [NSS_CC_PORT5_TX_CLK_SRC] = &nss_cc_port5_tx_clk_src.clkr, ++ [NSS_CC_PORT5_TX_DIV_CLK_SRC] = &nss_cc_port5_tx_div_clk_src.clkr, ++ [NSS_CC_PORT6_MAC_CLK] = &nss_cc_port6_mac_clk.clkr, ++ [NSS_CC_PORT6_RX_CLK] = &nss_cc_port6_rx_clk.clkr, ++ [NSS_CC_PORT6_RX_CLK_SRC] = &nss_cc_port6_rx_clk_src.clkr, ++ [NSS_CC_PORT6_RX_DIV_CLK_SRC] = &nss_cc_port6_rx_div_clk_src.clkr, ++ [NSS_CC_PORT6_TX_CLK] = &nss_cc_port6_tx_clk.clkr, ++ [NSS_CC_PORT6_TX_CLK_SRC] = &nss_cc_port6_tx_clk_src.clkr, ++ [NSS_CC_PORT6_TX_DIV_CLK_SRC] = &nss_cc_port6_tx_div_clk_src.clkr, ++ [NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr, ++ [NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr, ++ [NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr, ++ [NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr, ++ [NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr, ++ [NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr, ++ [NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr, ++ [NSS_CC_UBI0_CLK_SRC] = &nss_cc_ubi0_clk_src.clkr, ++ [NSS_CC_UBI0_DIV_CLK_SRC] = &nss_cc_ubi0_div_clk_src.clkr, ++ [NSS_CC_UBI1_CLK_SRC] = &nss_cc_ubi1_clk_src.clkr, ++ [NSS_CC_UBI1_DIV_CLK_SRC] = &nss_cc_ubi1_div_clk_src.clkr, ++ [NSS_CC_UBI2_CLK_SRC] = &nss_cc_ubi2_clk_src.clkr, ++ [NSS_CC_UBI2_DIV_CLK_SRC] = &nss_cc_ubi2_div_clk_src.clkr, ++ [NSS_CC_UBI32_AHB0_CLK] = &nss_cc_ubi32_ahb0_clk.clkr, ++ [NSS_CC_UBI32_AHB1_CLK] = &nss_cc_ubi32_ahb1_clk.clkr, ++ [NSS_CC_UBI32_AHB2_CLK] = &nss_cc_ubi32_ahb2_clk.clkr, ++ [NSS_CC_UBI32_AHB3_CLK] = &nss_cc_ubi32_ahb3_clk.clkr, ++ [NSS_CC_UBI32_AXI0_CLK] = &nss_cc_ubi32_axi0_clk.clkr, ++ [NSS_CC_UBI32_AXI1_CLK] = &nss_cc_ubi32_axi1_clk.clkr, ++ [NSS_CC_UBI32_AXI2_CLK] = &nss_cc_ubi32_axi2_clk.clkr, ++ [NSS_CC_UBI32_AXI3_CLK] = &nss_cc_ubi32_axi3_clk.clkr, ++ [NSS_CC_UBI32_CORE0_CLK] = &nss_cc_ubi32_core0_clk.clkr, ++ [NSS_CC_UBI32_CORE1_CLK] = &nss_cc_ubi32_core1_clk.clkr, ++ [NSS_CC_UBI32_CORE2_CLK] = &nss_cc_ubi32_core2_clk.clkr, ++ [NSS_CC_UBI32_CORE3_CLK] = &nss_cc_ubi32_core3_clk.clkr, ++ [NSS_CC_UBI32_INTR0_AHB_CLK] = &nss_cc_ubi32_intr0_ahb_clk.clkr, ++ [NSS_CC_UBI32_INTR1_AHB_CLK] = &nss_cc_ubi32_intr1_ahb_clk.clkr, ++ [NSS_CC_UBI32_INTR2_AHB_CLK] = &nss_cc_ubi32_intr2_ahb_clk.clkr, ++ [NSS_CC_UBI32_INTR3_AHB_CLK] = &nss_cc_ubi32_intr3_ahb_clk.clkr, ++ [NSS_CC_UBI32_NC_AXI0_CLK] = &nss_cc_ubi32_nc_axi0_clk.clkr, ++ [NSS_CC_UBI32_NC_AXI1_CLK] = &nss_cc_ubi32_nc_axi1_clk.clkr, ++ [NSS_CC_UBI32_NC_AXI2_CLK] = &nss_cc_ubi32_nc_axi2_clk.clkr, ++ [NSS_CC_UBI32_NC_AXI3_CLK] = &nss_cc_ubi32_nc_axi3_clk.clkr, ++ [NSS_CC_UBI32_UTCM0_CLK] = &nss_cc_ubi32_utcm0_clk.clkr, ++ [NSS_CC_UBI32_UTCM1_CLK] = &nss_cc_ubi32_utcm1_clk.clkr, ++ [NSS_CC_UBI32_UTCM2_CLK] = &nss_cc_ubi32_utcm2_clk.clkr, ++ [NSS_CC_UBI32_UTCM3_CLK] = &nss_cc_ubi32_utcm3_clk.clkr, ++ [NSS_CC_UBI3_CLK_SRC] = &nss_cc_ubi3_clk_src.clkr, ++ [NSS_CC_UBI3_DIV_CLK_SRC] = &nss_cc_ubi3_div_clk_src.clkr, ++ [NSS_CC_UBI_AXI_CLK_SRC] = &nss_cc_ubi_axi_clk_src.clkr, ++ [NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC] = ++ &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr, ++ [NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT3_RX_CLK] = &nss_cc_uniphy_port3_rx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT3_TX_CLK] = &nss_cc_uniphy_port3_tx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT4_RX_CLK] = &nss_cc_uniphy_port4_rx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT4_TX_CLK] = &nss_cc_uniphy_port4_tx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT5_RX_CLK] = &nss_cc_uniphy_port5_rx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT5_TX_CLK] = &nss_cc_uniphy_port5_tx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT6_RX_CLK] = &nss_cc_uniphy_port6_rx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT6_TX_CLK] = &nss_cc_uniphy_port6_tx_clk.clkr, ++ [NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr, ++ [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] = ++ &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr, ++ [NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr, ++ [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] = ++ &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr, ++ [NSS_CC_XGMAC2_PTP_REF_CLK] = &nss_cc_xgmac2_ptp_ref_clk.clkr, ++ [NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC] = ++ &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr, ++ [NSS_CC_XGMAC3_PTP_REF_CLK] = &nss_cc_xgmac3_ptp_ref_clk.clkr, ++ [NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC] = ++ &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr, ++ [NSS_CC_XGMAC4_PTP_REF_CLK] = &nss_cc_xgmac4_ptp_ref_clk.clkr, ++ [NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC] = ++ &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr, ++ [NSS_CC_XGMAC5_PTP_REF_CLK] = &nss_cc_xgmac5_ptp_ref_clk.clkr, ++ [NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC] = ++ &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr, ++ [UBI32_PLL] = &ubi32_pll.clkr, ++ [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr, ++}; ++ ++static const struct qcom_reset_map nss_cc_ipq9574_resets[] = { ++ [NSS_CC_CE_BCR] = { 0x28400, 0 }, ++ [NSS_CC_CLC_BCR] = { 0x28600, 0 }, ++ [NSS_CC_EIP197_BCR] = { 0x16004, 0 }, ++ [NSS_CC_HAQ_BCR] = { 0x28300, 0 }, ++ [NSS_CC_IMEM_BCR] = { 0xe004, 0 }, ++ [NSS_CC_MAC_BCR] = { 0x28100, 0 }, ++ [NSS_CC_PPE_BCR] = { 0x28200, 0 }, ++ [NSS_CC_UBI_BCR] = { 0x28700, 0 }, ++ [NSS_CC_UNIPHY_BCR] = { 0x28900, 0 }, ++ [UBI3_CLKRST_CLAMP_ENABLE] = { 0x28a04, 9 }, ++ [UBI3_CORE_CLAMP_ENABLE] = { 0x28a04, 8 }, ++ [UBI2_CLKRST_CLAMP_ENABLE] = { 0x28a04, 7 }, ++ [UBI2_CORE_CLAMP_ENABLE] = { 0x28a04, 6 }, ++ [UBI1_CLKRST_CLAMP_ENABLE] = { 0x28a04, 5 }, ++ [UBI1_CORE_CLAMP_ENABLE] = { 0x28a04, 4 }, ++ [UBI0_CLKRST_CLAMP_ENABLE] = { 0x28a04, 3 }, ++ [UBI0_CORE_CLAMP_ENABLE] = { 0x28a04, 2 }, ++ [NSSNOC_NSS_CSR_ARES] = { 0x28a04, 1 }, ++ [NSS_CSR_ARES] = { 0x28a04, 0 }, ++ [PPE_BTQ_ARES] = { 0x28a08, 20 }, ++ [PPE_IPE_ARES] = { 0x28a08, 19 }, ++ [PPE_ARES] = { 0x28a08, 18 }, ++ [PPE_CFG_ARES] = { 0x28a08, 17 }, ++ [PPE_EDMA_ARES] = { 0x28a08, 16 }, ++ [PPE_EDMA_CFG_ARES] = { 0x28a08, 15 }, ++ [CRY_PPE_ARES] = { 0x28a08, 14 }, ++ [NSSNOC_PPE_ARES] = { 0x28a08, 13 }, ++ [NSSNOC_PPE_CFG_ARES] = { 0x28a08, 12 }, ++ [PORT1_MAC_ARES] = { 0x28a08, 11 }, ++ [PORT2_MAC_ARES] = { 0x28a08, 10 }, ++ [PORT3_MAC_ARES] = { 0x28a08, 9 }, ++ [PORT4_MAC_ARES] = { 0x28a08, 8 }, ++ [PORT5_MAC_ARES] = { 0x28a08, 7 }, ++ [PORT6_MAC_ARES] = { 0x28a08, 6 }, ++ [XGMAC0_PTP_REF_ARES] = { 0x28a08, 5 }, ++ [XGMAC1_PTP_REF_ARES] = { 0x28a08, 4 }, ++ [XGMAC2_PTP_REF_ARES] = { 0x28a08, 3 }, ++ [XGMAC3_PTP_REF_ARES] = { 0x28a08, 2 }, ++ [XGMAC4_PTP_REF_ARES] = { 0x28a08, 1 }, ++ [XGMAC5_PTP_REF_ARES] = { 0x28a08, 0 }, ++ [HAQ_AHB_ARES] = { 0x28a0c, 3 }, ++ [HAQ_AXI_ARES] = { 0x28a0c, 2 }, ++ [NSSNOC_HAQ_AHB_ARES] = { 0x28a0c, 1 }, ++ [NSSNOC_HAQ_AXI_ARES] = { 0x28a0c, 0 }, ++ [CE_APB_ARES] = { 0x28a10, 3 }, ++ [CE_AXI_ARES] = { 0x28a10, 2 }, ++ [NSSNOC_CE_APB_ARES] = { 0x28a10, 1 }, ++ [NSSNOC_CE_AXI_ARES] = { 0x28a10, 0 }, ++ [CRYPTO_ARES] = { 0x28a14, 1 }, ++ [NSSNOC_CRYPTO_ARES] = { 0x28a14, 0 }, ++ [NSSNOC_NC_AXI0_1_ARES] = { 0x28a1c, 28 }, ++ [UBI0_CORE_ARES] = { 0x28a1c, 27 }, ++ [UBI1_CORE_ARES] = { 0x28a1c, 26 }, ++ [UBI2_CORE_ARES] = { 0x28a1c, 25 }, ++ [UBI3_CORE_ARES] = { 0x28a1c, 24 }, ++ [NC_AXI0_ARES] = { 0x28a1c, 23 }, ++ [UTCM0_ARES] = { 0x28a1c, 22 }, ++ [NC_AXI1_ARES] = { 0x28a1c, 21 }, ++ [UTCM1_ARES] = { 0x28a1c, 20 }, ++ [NC_AXI2_ARES] = { 0x28a1c, 19 }, ++ [UTCM2_ARES] = { 0x28a1c, 18 }, ++ [NC_AXI3_ARES] = { 0x28a1c, 17 }, ++ [UTCM3_ARES] = { 0x28a1c, 16 }, ++ [NSSNOC_NC_AXI0_ARES] = { 0x28a1c, 15 }, ++ [AHB0_ARES] = { 0x28a1c, 14 }, ++ [INTR0_AHB_ARES] = { 0x28a1c, 13 }, ++ [AHB1_ARES] = { 0x28a1c, 12 }, ++ [INTR1_AHB_ARES] = { 0x28a1c, 11 }, ++ [AHB2_ARES] = { 0x28a1c, 10 }, ++ [INTR2_AHB_ARES] = { 0x28a1c, 9 }, ++ [AHB3_ARES] = { 0x28a1c, 8 }, ++ [INTR3_AHB_ARES] = { 0x28a1c, 7 }, ++ [NSSNOC_AHB0_ARES] = { 0x28a1c, 6 }, ++ [NSSNOC_INT0_AHB_ARES] = { 0x28a1c, 5 }, ++ [AXI0_ARES] = { 0x28a1c, 4 }, ++ [AXI1_ARES] = { 0x28a1c, 3 }, ++ [AXI2_ARES] = { 0x28a1c, 2 }, ++ [AXI3_ARES] = { 0x28a1c, 1 }, ++ [NSSNOC_AXI0_ARES] = { 0x28a1c, 0 }, ++ [IMEM_QSB_ARES] = { 0x28a20, 3 }, ++ [NSSNOC_IMEM_QSB_ARES] = { 0x28a20, 2 }, ++ [IMEM_AHB_ARES] = { 0x28a20, 1 }, ++ [NSSNOC_IMEM_AHB_ARES] = { 0x28a20, 0 }, ++ [UNIPHY_PORT1_RX_ARES] = { 0x28a24, 23 }, ++ [UNIPHY_PORT1_TX_ARES] = { 0x28a24, 22 }, ++ [UNIPHY_PORT2_RX_ARES] = { 0x28a24, 21 }, ++ [UNIPHY_PORT2_TX_ARES] = { 0x28a24, 20 }, ++ [UNIPHY_PORT3_RX_ARES] = { 0x28a24, 19 }, ++ [UNIPHY_PORT3_TX_ARES] = { 0x28a24, 18 }, ++ [UNIPHY_PORT4_RX_ARES] = { 0x28a24, 17 }, ++ [UNIPHY_PORT4_TX_ARES] = { 0x28a24, 16 }, ++ [UNIPHY_PORT5_RX_ARES] = { 0x28a24, 15 }, ++ [UNIPHY_PORT5_TX_ARES] = { 0x28a24, 14 }, ++ [UNIPHY_PORT6_RX_ARES] = { 0x28a24, 13 }, ++ [UNIPHY_PORT6_TX_ARES] = { 0x28a24, 12 }, ++ [PORT1_RX_ARES] = { 0x28a24, 11 }, ++ [PORT1_TX_ARES] = { 0x28a24, 10 }, ++ [PORT2_RX_ARES] = { 0x28a24, 9 }, ++ [PORT2_TX_ARES] = { 0x28a24, 8 }, ++ [PORT3_RX_ARES] = { 0x28a24, 7 }, ++ [PORT3_TX_ARES] = { 0x28a24, 6 }, ++ [PORT4_RX_ARES] = { 0x28a24, 5 }, ++ [PORT4_TX_ARES] = { 0x28a24, 4 }, ++ [PORT5_RX_ARES] = { 0x28a24, 3 }, ++ [PORT5_TX_ARES] = { 0x28a24, 2 }, ++ [PORT6_RX_ARES] = { 0x28a24, 1 }, ++ [PORT6_TX_ARES] = { 0x28a24, 0 }, ++ [PPE_FULL_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(20, 17) }, ++ [UNIPHY0_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(23, 14) }, ++ [UNIPHY1_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(15, 14) }, ++ [UNIPHY2_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(13, 12) }, ++ [UNIPHY_PORT1_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(23, 22) }, ++ [UNIPHY_PORT2_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(21, 20) }, ++ [UNIPHY_PORT3_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(19, 18) }, ++ [UNIPHY_PORT4_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(17, 16) }, ++ [UNIPHY_PORT5_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(15, 14) }, ++ [UNIPHY_PORT6_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(13, 12) }, ++ [NSSPORT1_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(11, 10) }, ++ [NSSPORT2_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(9, 8) }, ++ [NSSPORT3_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(7, 6) }, ++ [NSSPORT4_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(5, 4) }, ++ [NSSPORT5_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(3, 2) }, ++ [NSSPORT6_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(1, 0) }, ++ [EDMA_HW_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(16, 15) }, ++}; ++ ++static const struct regmap_config nss_cc_ipq9574_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x28a34, ++ .fast_io = true, ++}; ++ ++static struct qcom_icc_hws_data icc_ipq9574_nss_hws[] = { ++ { MASTER_NSSNOC_PPE, SLAVE_NSSNOC_PPE, NSS_CC_NSSNOC_PPE_CLK }, ++ { MASTER_NSSNOC_PPE_CFG, SLAVE_NSSNOC_PPE_CFG, NSS_CC_NSSNOC_PPE_CFG_CLK }, ++ { MASTER_NSSNOC_NSS_CSR, SLAVE_NSSNOC_NSS_CSR, NSS_CC_NSSNOC_NSS_CSR_CLK }, ++ { MASTER_NSSNOC_IMEM_QSB, SLAVE_NSSNOC_IMEM_QSB, NSS_CC_NSSNOC_IMEM_QSB_CLK }, ++ { MASTER_NSSNOC_IMEM_AHB, SLAVE_NSSNOC_IMEM_AHB, NSS_CC_NSSNOC_IMEM_AHB_CLK }, ++}; ++ ++#define IPQ_NSSCC_ID (9574 * 2) /* some unique value */ ++ ++static const struct qcom_cc_desc nss_cc_ipq9574_desc = { ++ .config = &nss_cc_ipq9574_regmap_config, ++ .clks = nss_cc_ipq9574_clocks, ++ .num_clks = ARRAY_SIZE(nss_cc_ipq9574_clocks), ++ .resets = nss_cc_ipq9574_resets, ++ .num_resets = ARRAY_SIZE(nss_cc_ipq9574_resets), ++ .icc_hws = icc_ipq9574_nss_hws, ++ .num_icc_hws = ARRAY_SIZE(icc_ipq9574_nss_hws), ++ .icc_first_node_id = IPQ_NSSCC_ID, ++}; ++ ++static const struct dev_pm_ops nss_cc_ipq9574_pm_ops = { ++ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) ++}; ++ ++static const struct of_device_id nss_cc_ipq9574_match_table[] = { ++ { .compatible = "qcom,ipq9574-nsscc" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table); ++ ++static int nss_cc_ipq9574_probe(struct platform_device *pdev) ++{ ++ struct regmap *regmap; ++ int ret; ++ ++ ret = devm_pm_runtime_enable(&pdev->dev); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Fail to enable runtime PM\n"); ++ ++ ret = devm_pm_clk_create(&pdev->dev); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Fail to create PM clock\n"); ++ ++ ret = pm_clk_add(&pdev->dev, "bus"); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Fail to add bus clock\n"); ++ ++ ret = pm_runtime_resume_and_get(&pdev->dev); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Fail to resume\n"); ++ ++ regmap = qcom_cc_map(pdev, &nss_cc_ipq9574_desc); ++ if (IS_ERR(regmap)) { ++ pm_runtime_put(&pdev->dev); ++ return dev_err_probe(&pdev->dev, PTR_ERR(regmap), ++ "Fail to map clock controller registers\n"); ++ } ++ ++ clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); ++ ++ ret = qcom_cc_really_probe(&pdev->dev, &nss_cc_ipq9574_desc, regmap); ++ pm_runtime_put(&pdev->dev); ++ ++ return ret; ++} ++ ++static struct platform_driver nss_cc_ipq9574_driver = { ++ .probe = nss_cc_ipq9574_probe, ++ .driver = { ++ .name = "qcom,nsscc-ipq9574", ++ .of_match_table = nss_cc_ipq9574_match_table, ++ .pm = &nss_cc_ipq9574_pm_ops, ++ .sync_state = icc_sync_state, ++ }, ++}; ++ ++module_platform_driver(nss_cc_ipq9574_driver); ++ ++MODULE_DESCRIPTION("Qualcomm Technologies, Inc. NSSCC IPQ9574 Driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/qualcommbe/patches-6.12/0022-v6.15-arm64-defconfig-Build-NSS-Clock-Controller-dri.patch b/target/linux/qualcommbe/patches-6.12/0022-v6.15-arm64-defconfig-Build-NSS-Clock-Controller-dri.patch new file mode 100644 index 0000000000..1f4dfd210c --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0022-v6.15-arm64-defconfig-Build-NSS-Clock-Controller-dri.patch @@ -0,0 +1,29 @@ +From 8f1b61ea1cb98735aa15a8875d729c21a2169fb9 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 13 Mar 2025 16:33:59 +0530 +Subject: [PATCH 22/22] v6.15: arm64: defconfig: Build NSS Clock Controller + driver for IPQ9574 + +NSSCC driver is needed to enable the ethernet interfaces present +in RDP433 based on IPQ9574. Since this is not necessary for bootup +enabling it as a module. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Devi Priya +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313110359.242491-7-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -1313,6 +1313,7 @@ CONFIG_IPQ_GCC_5332=y + CONFIG_IPQ_GCC_6018=y + CONFIG_IPQ_GCC_8074=y + CONFIG_IPQ_GCC_9574=y ++CONFIG_IPQ_NSSCC_9574=m + CONFIG_MSM_GCC_8916=y + CONFIG_MSM_MMCC_8994=m + CONFIG_MSM_GCC_8994=y diff --git a/target/linux/qualcommbe/patches-6.12/0100-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch b/target/linux/qualcommbe/patches-6.12/0100-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch new file mode 100644 index 0000000000..b746ed8d54 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0100-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch @@ -0,0 +1,54 @@ +From 52ebd52aa1906961142a2aba55d47a53b956847c Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 13 Mar 2025 16:33:58 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: Add nsscc node + +Add a node for the nss clock controller found on ipq9574 based devices. + +Reviewed-by: Konrad Dybcio +Signed-off-by: Devi Priya +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313110359.242491-6-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 29 +++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -1193,6 +1193,35 @@ + status = "disabled"; + }; + ++ nsscc: clock-controller@39b00000 { ++ compatible = "qcom,ipq9574-nsscc"; ++ reg = <0x39b00000 0x80000>; ++ clocks = <&xo_board_clk>, ++ <&cmn_pll NSS_1200MHZ_CLK>, ++ <&cmn_pll PPE_353MHZ_CLK>, ++ <&gcc GPLL0_OUT_AUX>, ++ <0>, ++ <0>, ++ <0>, ++ <0>, ++ <0>, ++ <0>, ++ <&gcc GCC_NSSCC_CLK>; ++ clock-names = "xo", ++ "nss_1200", ++ "ppe_353", ++ "gpll0_out", ++ "uniphy0_rx", ++ "uniphy0_tx", ++ "uniphy1_rx", ++ "uniphy1_tx", ++ "uniphy2_rx", ++ "uniphy2_tx", ++ "bus"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ #interconnect-cells = <1>; ++ }; + }; + + thermal-zones { diff --git a/target/linux/qualcommbe/patches-6.12/0101-arm64-dts-qcom-ipq9574-fix-the-msi-interrupt-numbers.patch b/target/linux/qualcommbe/patches-6.12/0101-arm64-dts-qcom-ipq9574-fix-the-msi-interrupt-numbers.patch new file mode 100644 index 0000000000..774e88a8aa --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0101-arm64-dts-qcom-ipq9574-fix-the-msi-interrupt-numbers.patch @@ -0,0 +1,44 @@ +From 2f2f5ae4d52ea882ba58f6b2fa6373a3d3db2bce Mon Sep 17 00:00:00 2001 +From: Manikanta Mylavarapu +Date: Thu, 13 Mar 2025 12:44:22 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: fix the msi interrupt numbers of + pcie3 + +The MSI interrupt numbers of the PCIe3 controller are incorrect. Due +to this, the functional bring up of the QDSP6 processor on the PCIe +endpoint has failed. Correct the MSI interrupt numbers to properly +bring up the QDSP6 processor on the PCIe endpoint. + +Fixes: d80c7fbfa908 ("arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes") +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313071422.510-1-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -972,14 +972,14 @@ + ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>, + <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>; + +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; + interrupt-names = "msi0", + "msi1", + "msi2", diff --git a/target/linux/qualcommbe/patches-6.12/0102-arm64-dts-qcom-ipq9574-Fix-USB-vdd-info.patch b/target/linux/qualcommbe/patches-6.12/0102-arm64-dts-qcom-ipq9574-Fix-USB-vdd-info.patch new file mode 100644 index 0000000000..dbf75c26d6 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0102-arm64-dts-qcom-ipq9574-Fix-USB-vdd-info.patch @@ -0,0 +1,55 @@ +From 3857f7cf650fa4ae0047b9b6fea6f7cd242de29c Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Fri, 7 Feb 2025 13:05:45 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: Fix USB vdd info + +USB phys in ipq9574 use the 'L5' regulator. The commit ec4f047679d5 +("arm64: dts: qcom: ipq9574: Enable USB") incorrectly specified it as +'L2'. Because of this when the phy module turns off/on its regulators, +the wrong regulator is turned off/on resulting in 2 issues, namely the +correct regulator related to the USB phy is not turned off/on and the +module powered by the incorrect regulator is affected. + +Fixes: ec4f047679d5 ("arm64: dts: qcom: ipq9574: Enable USB") +Signed-off-by: Varadarajan Narayanan +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20250207073545.1768990-2-quic_varada@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -111,6 +111,13 @@ + regulator-always-on; + regulator-boot-on; + }; ++ ++ mp5496_l5: l5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; + }; + }; + +@@ -146,7 +153,7 @@ + }; + + &usb_0_qmpphy { +- vdda-pll-supply = <&mp5496_l2>; ++ vdda-pll-supply = <&mp5496_l5>; + vdda-phy-supply = <®ulator_fixed_0p925>; + + status = "okay"; +@@ -154,7 +161,7 @@ + + &usb_0_qusbphy { + vdd-supply = <®ulator_fixed_0p925>; +- vdda-pll-supply = <&mp5496_l2>; ++ vdda-pll-supply = <&mp5496_l5>; + vdda-phy-dpdm-supply = <®ulator_fixed_3p3>; + + status = "okay"; diff --git a/target/linux/qualcommbe/patches-6.12/0103-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch b/target/linux/qualcommbe/patches-6.12/0103-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch new file mode 100644 index 0000000000..f37c08b250 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0103-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch @@ -0,0 +1,50 @@ +From 583299efa34c4a484b211f84c63aee78b6c2b469 Mon Sep 17 00:00:00 2001 +From: Md Sadre Alam +Date: Thu, 6 Mar 2025 17:03:55 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: Add SPI nand support + +Add SPI NAND support for ipq9574 SoC. + +Signed-off-by: Md Sadre Alam +Link: https://lore.kernel.org/r/20250306113357.126602-2-quic_mdalam@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -673,6 +673,33 @@ + status = "disabled"; + }; + ++ qpic_bam: dma-controller@7984000 { ++ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; ++ reg = <0x07984000 0x1c000>; ++ interrupts = ; ++ clocks = <&gcc GCC_QPIC_AHB_CLK>; ++ clock-names = "bam_clk"; ++ #dma-cells = <1>; ++ qcom,ee = <0>; ++ status = "disabled"; ++ }; ++ ++ qpic_nand: spi@79b0000 { ++ compatible = "qcom,ipq9574-snand"; ++ reg = <0x079b0000 0x10000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&gcc GCC_QPIC_CLK>, ++ <&gcc GCC_QPIC_AHB_CLK>, ++ <&gcc GCC_QPIC_IO_MACRO_CLK>; ++ clock-names = "core", "aon", "iom"; ++ dmas = <&qpic_bam 0>, ++ <&qpic_bam 1>, ++ <&qpic_bam 2>; ++ dma-names = "tx", "rx", "cmd"; ++ status = "disabled"; ++ }; ++ + usb_0_qusbphy: phy@7b000 { + compatible = "qcom,ipq9574-qusb2-phy"; + reg = <0x0007b000 0x180>; diff --git a/target/linux/qualcommbe/patches-6.12/0104-arm64-dts-qcom-ipq9574-Enable-SPI-NAND-for-ipq9574.patch b/target/linux/qualcommbe/patches-6.12/0104-arm64-dts-qcom-ipq9574-Enable-SPI-NAND-for-ipq9574.patch new file mode 100644 index 0000000000..393923a343 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0104-arm64-dts-qcom-ipq9574-Enable-SPI-NAND-for-ipq9574.patch @@ -0,0 +1,68 @@ +From a7c88bc81632974c0708308493aefb1f871b65fa Mon Sep 17 00:00:00 2001 +From: Md Sadre Alam +Date: Thu, 6 Mar 2025 17:03:56 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: Enable SPI NAND for ipq9574 + +Enable SPI NAND support for ipq9574 SoC. + +Reviewed-by: Konrad Dybcio +Signed-off-by: Md Sadre Alam +Link: https://lore.kernel.org/r/20250306113357.126602-3-quic_mdalam@quicinc.com +Signed-off-by: Bjorn Andersson +--- + .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 44 +++++++++++++++++++ + 1 file changed, 44 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -146,6 +146,50 @@ + drive-strength = <8>; + bias-pull-up; + }; ++ ++ qpic_snand_default_state: qpic-snand-default-state { ++ clock-pins { ++ pins = "gpio5"; ++ function = "qspi_clk"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ ++ cs-pins { ++ pins = "gpio4"; ++ function = "qspi_cs"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ ++ data-pins { ++ pins = "gpio0", "gpio1", "gpio2", "gpio3"; ++ function = "qspi_data"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++}; ++ ++&qpic_bam { ++ status = "okay"; ++}; ++ ++&qpic_nand { ++ pinctrl-0 = <&qpic_snand_default_state>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ nand-ecc-engine = <&qpic_nand>; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ }; + }; + + &usb_0_dwc3 { diff --git a/target/linux/qualcommbe/patches-6.12/0105-arm64-dts-qcom-ipq9574-Remove-eMMC-node.patch b/target/linux/qualcommbe/patches-6.12/0105-arm64-dts-qcom-ipq9574-Remove-eMMC-node.patch new file mode 100644 index 0000000000..d188539aaa --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0105-arm64-dts-qcom-ipq9574-Remove-eMMC-node.patch @@ -0,0 +1,37 @@ +From 0156e327aa854be5eb9cbec9d020be1026b5b446 Mon Sep 17 00:00:00 2001 +From: Md Sadre Alam +Date: Thu, 6 Mar 2025 17:03:57 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: Remove eMMC node + +Remove eMMC node for rdp433, since rdp433 +default boot mode is norplusnand + +Reviewed-by: Konrad Dybcio +Signed-off-by: Md Sadre Alam +Link: https://lore.kernel.org/r/20250306113357.126602-4-quic_mdalam@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 12 ------------ + 1 file changed, 12 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +@@ -55,18 +55,6 @@ + status = "okay"; + }; + +-&sdhc_1 { +- pinctrl-0 = <&sdc_default_state>; +- pinctrl-names = "default"; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- max-frequency = <384000000>; +- bus-width = <8>; +- status = "okay"; +-}; +- + &tlmm { + + pcie1_default: pcie1-default-state { diff --git a/target/linux/qualcommbe/patches-6.12/0301-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch b/target/linux/qualcommbe/patches-6.12/0301-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch new file mode 100644 index 0000000000..151396ec13 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0301-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch @@ -0,0 +1,49 @@ +From 657833a74f532262d415fa2ca354b69f4a97353c Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Thu, 23 Nov 2023 15:41:20 +0800 +Subject: [PATCH] arm64: dts: qcom: Add IPQ9574 MDIO device node + +The MDIO bus master block is used to accessing the MDIO slave +device (such as PHY device), the dedicated MDIO PINs needs to +be configured. + +Change-Id: Ia64083529e693256dbd8f8af4071c02afdded8f9 +Signed-off-by: Luo Jie +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -295,6 +295,8 @@ + mdio: mdio@90000 { + compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio"; + reg = <0x00090000 0x64>; ++ pinctrl-0 = <&mdio_pins>; ++ pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_MDIO_AHB_CLK>; +@@ -412,6 +414,22 @@ + interrupt-controller; + #interrupt-cells = <2>; + ++ mdio_pins: mdio-pins { ++ mdc-state { ++ pins = "gpio38"; ++ function = "mdc"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ ++ mdio-state { ++ pins = "gpio39"; ++ function = "mdio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ }; ++ + uart2_pins: uart2-state { + pins = "gpio34", "gpio35"; + function = "blsp2_uart"; diff --git a/target/linux/qualcommbe/patches-6.12/0302-arm64-dts-qcom-ipq9574-Use-usb-phy-for-node-names.patch b/target/linux/qualcommbe/patches-6.12/0302-arm64-dts-qcom-ipq9574-Use-usb-phy-for-node-names.patch new file mode 100644 index 0000000000..9928d8a768 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0302-arm64-dts-qcom-ipq9574-Use-usb-phy-for-node-names.patch @@ -0,0 +1,34 @@ +From 91467ca0db1654644b2168f882f223d47dcfb9c1 Mon Sep 17 00:00:00 2001 +From: Alexandru Gagniuc +Date: Sat, 30 Mar 2024 20:03:30 -0500 +Subject: [PATCH] arm64: dts: qcom: ipq9574: Use 'usb-phy' for node names + +The devicetree spec allows node names of "usb-phy". So be more +specific for the USB PHYs, and name the nodes "usb-phy" instead of +just "phy". + +Signed-off-by: Alexandru Gagniuc +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -718,7 +718,7 @@ + status = "disabled"; + }; + +- usb_0_qusbphy: phy@7b000 { ++ usb_0_qusbphy: usb-phy@7b000 { + compatible = "qcom,ipq9574-qusb2-phy"; + reg = <0x0007b000 0x180>; + #phy-cells = <0>; +@@ -732,7 +732,7 @@ + status = "disabled"; + }; + +- usb_0_qmpphy: phy@7d000 { ++ usb_0_qmpphy: usb-phy@7d000 { + compatible = "qcom,ipq9574-qmp-usb3-phy"; + reg = <0x0007d000 0xa00>; + #phy-cells = <0>; diff --git a/target/linux/qualcommbe/patches-6.12/0304-arm64-dts-qcom-ipq9574-add-QPIC-SPI-NAND-default-par.patch b/target/linux/qualcommbe/patches-6.12/0304-arm64-dts-qcom-ipq9574-add-QPIC-SPI-NAND-default-par.patch new file mode 100644 index 0000000000..e0b84b1218 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0304-arm64-dts-qcom-ipq9574-add-QPIC-SPI-NAND-default-par.patch @@ -0,0 +1,50 @@ +From be44d0251a2540f3b8d7205e0bc6659704366711 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 30 Jan 2025 00:39:30 +0100 +Subject: [PATCH] arm64: dts: qcom: ipq9574: add QPIC SPI NAND default + partition nodes + +Add QPIC SPI NAND default partition nodes for RDP reference board. + +Signed-off-by: Christian Marangi +--- + .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 28 +++++++++++++++++++ + 1 file changed, 28 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -189,6 +189,34 @@ + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "0:training"; ++ reg = <0x0 0x80000>; ++ read-only; ++ }; ++ ++ partition@80000 { ++ label = "0:license"; ++ reg = <0x80000 0x40000>; ++ read-only; ++ }; ++ ++ partition@c0000 { ++ label = "rootfs"; ++ reg = <0xc0000 0x3c00000>; ++ }; ++ ++ partition@3cc0000 { ++ label = "rootfs_1"; ++ reg = <0x3cc0000 0x3c00000>; ++ }; ++ }; + }; + }; + diff --git a/target/linux/qualcommbe/patches-6.12/0305-arm64-dts-qcom-add-partition-table-for-ipq9574-rdp-c.patch b/target/linux/qualcommbe/patches-6.12/0305-arm64-dts-qcom-add-partition-table-for-ipq9574-rdp-c.patch new file mode 100644 index 0000000000..2136fa224b --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0305-arm64-dts-qcom-add-partition-table-for-ipq9574-rdp-c.patch @@ -0,0 +1,171 @@ +From 47c7ae9715d76054d98e8407dbb8ca1cf42fd587 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 9 Dec 2024 17:50:31 +0100 +Subject: [PATCH] arm64: dts: qcom: add partition table for ipq9574 rdp common + +Add partition table for ipq9574 SoC common to every RDB board. + +Signed-off-by: Christian Marangi +--- + .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 146 +++++++++++++++++- + 1 file changed, 145 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -74,11 +74,155 @@ + status = "okay"; + + flash@0 { +- compatible = "micron,n25q128a11", "jedec,spi-nor"; ++ compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "0:sbl1"; ++ reg = <0x0 0xc0000>; ++ read-only; ++ }; ++ ++ partition@c0000 { ++ label = "0:mibib"; ++ reg = <0xc0000 0x10000>; ++ read-only; ++ }; ++ ++ partition@d0000 { ++ label = "0:bootconfig"; ++ reg = <0xd0000 0x20000>; ++ read-only; ++ }; ++ ++ partition@f0000 { ++ label = "0:bootconfig1"; ++ reg = <0xf0000 0x20000>; ++ read-only; ++ }; ++ ++ partition@110000 { ++ label = "0:qsee"; ++ reg = <0x110000 0x180000>; ++ read-only; ++ }; ++ ++ partition@290000 { ++ label = "0:qsee_1"; ++ reg = <0x290000 0x180000>; ++ read-only; ++ }; ++ ++ partition@410000 { ++ label = "0:devcfg"; ++ reg = <0x410000 0x10000>; ++ read-only; ++ }; ++ ++ partition@420000 { ++ label = "0:devcfg_1"; ++ reg = <0x420000 0x10000>; ++ read-only; ++ }; ++ ++ partition@430000 { ++ label = "0:apdp"; ++ reg = <0x430000 0x10000>; ++ read-only; ++ }; ++ ++ partition@440000 { ++ label = "0:apdp_1"; ++ reg = <0x440000 0x10000>; ++ read-only; ++ }; ++ ++ partition@450000 { ++ label = "0:tme"; ++ reg = <0x450000 0x40000>; ++ read-only; ++ }; ++ ++ partition@490000 { ++ label = "0:tme_1"; ++ reg = <0x490000 0x40000>; ++ read-only; ++ }; ++ ++ partition@4d0000 { ++ label = "0:rpm"; ++ reg = <0x4d0000 0x20000>; ++ read-only; ++ }; ++ ++ partition@4f0000 { ++ label = "0:rpm_1"; ++ reg = <0x4f0000 0x20000>; ++ read-only; ++ }; ++ ++ partition@510000 { ++ label = "0:cdt"; ++ reg = <0x510000 0x10000>; ++ read-only; ++ }; ++ ++ partition@520000 { ++ label = "0:cdt_1"; ++ reg = <0x520000 0x10000>; ++ read-only; ++ }; ++ ++ partition@530000 { ++ compatible = "u-boot,env"; ++ label = "0:appsblenv"; ++ reg = <0x530000 0x10000>; ++ ++ macaddr_lan: ethaddr { ++ #nvmem-cell-cells = <1>; ++ }; ++ }; ++ ++ partition@540000 { ++ label = "0:appsbl"; ++ reg = <0x540000 0xa0000>; ++ read-only; ++ }; ++ ++ partition@5e0000 { ++ label = "0:appsbl_1"; ++ reg = <0x5e0000 0xa0000>; ++ read-only; ++ }; ++ ++ partition@680000 { ++ label = "0:art"; ++ reg = <0x680000 0x100000>; ++ read-only; ++ }; ++ ++ partition@780000 { ++ label = "0:ethphyfw"; ++ reg = <0x780000 0x80000>; ++ read-only; ++ ++ nvmem-layout { ++ compatible = "fixed-layout"; ++ ++ aqr_fw: aqr-fw@0 { ++ reg = <0x0 0x5fc02>; ++ }; ++ }; ++ }; ++ }; + }; + }; + diff --git a/target/linux/qualcommbe/patches-6.12/0306-dt-bindings-net-Document-Qualcomm-QCA8084-PHY-packag.patch b/target/linux/qualcommbe/patches-6.12/0306-dt-bindings-net-Document-Qualcomm-QCA8084-PHY-packag.patch new file mode 100644 index 0000000000..1583258493 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0306-dt-bindings-net-Document-Qualcomm-QCA8084-PHY-packag.patch @@ -0,0 +1,244 @@ +From ae682f13d308682232069e5150e884fc10160598 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Mon, 29 Jan 2024 17:57:20 +0800 +Subject: [PATCH] dt-bindings: net: Document Qualcomm QCA8084 PHY package + +QCA8084 is quad PHY chip, which integrates 4 PHYs, 2 PCS +interfaces (PCS0 and PCS1) and clock controller, which can +also be integrated to the switch chip named as QCA8386. + +1. MDIO address of 4 PHYs, 2 PCS and 1 XPCS (PCS1 includes + PCS and XPCS, PCS0 includes PCS) can be configured. +2. The package mode of PHY is optionally configured for the + interface mode of two PCSes working correctly. +3. The package level clock and reset need to be initialized. +4. The clock and reset per PHY device need to be initialized + so that the PHY register can be accessed. + +Change-Id: Idb2338d2673152cbd3c57e95968faa59e9d4a80f +Signed-off-by: Luo Jie +--- + .../devicetree/bindings/net/qcom,qca8084.yaml | 198 ++++++++++++++++++ + include/dt-bindings/net/qcom,qca808x.h | 14 ++ + 2 files changed, 212 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/qcom,qca8084.yaml + create mode 100644 include/dt-bindings/net/qcom,qca808x.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/qcom,qca8084.yaml +@@ -0,0 +1,198 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/qcom,qca8084.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Qualcomm QCA8084 Ethernet Quad PHY ++ ++maintainers: ++ - Luo Jie ++ ++description: ++ Qualcomm QCA8084 is a four-port Ethernet transceiver, the ++ Ethernet port supports link speed 10/100/1000/2500 Mbps. ++ There are two PCSes (PCS0 and PCS1) integrated in the PHY ++ package, PCS1 includes XPCS and PCS to support the interface ++ mode 10G-QXGMII and SGMII, PCS0 includes a PCS to support the ++ interface mode SGMII only. There is also a clock controller ++ integrated in the PHY package. This four-port Ethernet ++ transceiver can also be integrated to the switch chip named ++ as QCA8386. The PHY package mode needs to be configured as the ++ correct value to apply the interface mode of two PCSes as ++ mentioned below. ++ ++ QCA8084 expects an input reference clock 50 MHZ as the clock ++ source of the integrated clock controller, the integrated ++ clock controller supplies the clocks and resets to the ++ integrated PHY, PCS and PHY package. ++ ++ - | ++ +--| |--+-------------------+--| |--+ ++ | PCS1 |<------------+---->| PCS0 | ++ +-------+ | +-------+ ++ | | | ++ Ref 50M clk +--------+ | | ++ ------------>| | clk & rst | | ++ GPIO Reset |QCA8K_CC+------------+ | ++ ------------>| | | | ++ +--------+ | | ++ | V | ++ +--------+--------+--------+--------+ ++ | PHY0 | PHY1 | PHY2 | PHY3 | ++ +--------+--------+--------+--------+ ++ ++$ref: ethernet-phy-package.yaml# ++ ++properties: ++ compatible: ++ const: qcom,qca8084-package ++ ++ clocks: ++ description: PHY package level initial common clocks, which are ++ needed to be enabled after GPIO reset on the PHY package, these ++ clocks are supplied from the PHY integrated clock controller ++ (QCA8K-CC). ++ items: ++ - description: APB bridge clock ++ - description: AHB clock ++ - description: Security control clock ++ - description: TLMM clock ++ - description: TLMM AHB clock ++ - description: CNOC AHB clock ++ - description: MDIO AHB clock ++ ++ clock-names: ++ items: ++ - const: apb_bridge ++ - const: ahb ++ - const: sec_ctrl_ahb ++ - const: tlmm ++ - const: tlmm_ahb ++ - const: cnoc_ahb ++ - const: mdio_ahb ++ ++ resets: ++ description: PHY package level initial common reset, which are ++ needed to be deasserted after GPIO reset on the PHY package, ++ this reset is provided by the PHY integrated clock controller ++ to do PHY DSP reset. ++ maxItems: 1 ++ ++ qcom,package-mode: ++ description: | ++ The package mode of PHY supports to be configured as 3 modes ++ to apply the combinations of interface mode of two PCSes ++ correctly. This value should use one of the values defined in ++ dt-bindings/net/qcom,qca808x.h. The package mode 10G-QXGMII of ++ Quad PHY is used by default. ++ ++ package mode PCS1 PCS0 ++ phy mode (0) 10G-QXGMII for not used ++ PHY0-PHY3 ++ ++ switch mode (1) SGMII for SGMII for ++ switch MAC0 switch MAC5 (optional) ++ ++ switch bypass MAC5 (2) SGMII for SGMII for ++ switch MAC0 PHY3 ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ enum: [0, 1, 2] ++ default: 0 ++ ++ qcom,phy-addr-fixup: ++ description: MDIO address for PHY0-PHY3, PCS0 and PCS1 including ++ PCS and XPCS, which can be optionally customized by programming ++ the security control register of PHY package. The hardware default ++ MDIO address of PHY0-PHY3, PCS0 and PCS1 including PCS and XPCS is ++ 0-6. ++ $ref: /schemas/types.yaml#/definitions/uint32-array ++ minItems: 7 ++ maxItems: 7 ++ ++patternProperties: ++ ^ethernet-phy(@[a-f0-9]+)?$: ++ $ref: ethernet-phy.yaml# ++ ++ properties: ++ compatible: ++ const: ethernet-phy-id004d.d180 ++ ++ required: ++ - compatible ++ - reg ++ - clocks ++ - resets ++ ++ unevaluatedProperties: false ++ ++required: ++ - compatible ++ - clocks ++ - clock-names ++ - resets ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ethernet-phy-package@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "qcom,qca8084-package"; ++ reg = <1>; ++ clocks = <&qca8k_nsscc NSS_CC_APB_BRIDGE_CLK>, ++ <&qca8k_nsscc NSS_CC_AHB_CLK>, ++ <&qca8k_nsscc NSS_CC_SEC_CTRL_AHB_CLK>, ++ <&qca8k_nsscc NSS_CC_TLMM_CLK>, ++ <&qca8k_nsscc NSS_CC_TLMM_AHB_CLK>, ++ <&qca8k_nsscc NSS_CC_CNOC_AHB_CLK>, ++ <&qca8k_nsscc NSS_CC_MDIO_AHB_CLK>; ++ clock-names = "apb_bridge", ++ "ahb", ++ "sec_ctrl_ahb", ++ "tlmm", ++ "tlmm_ahb", ++ "cnoc_ahb", ++ "mdio_ahb"; ++ resets = <&qca8k_nsscc NSS_CC_GEPHY_FULL_ARES>; ++ qcom,package-mode = ; ++ qcom,phy-addr-fixup = <1 2 3 4 5 6 7>; ++ ++ ethernet-phy@1 { ++ compatible = "ethernet-phy-id004d.d180"; ++ reg = <1>; ++ clocks = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_CLK>; ++ resets = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_ARES>; ++ }; ++ ++ ethernet-phy@2 { ++ compatible = "ethernet-phy-id004d.d180"; ++ reg = <2>; ++ clocks = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_CLK>; ++ resets = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_ARES>; ++ }; ++ ++ ethernet-phy@3 { ++ compatible = "ethernet-phy-id004d.d180"; ++ reg = <3>; ++ clocks = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_CLK>; ++ resets = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_ARES>; ++ }; ++ ++ ethernet-phy@4 { ++ compatible = "ethernet-phy-id004d.d180"; ++ reg = <4>; ++ clocks = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_CLK>; ++ resets = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_ARES>; ++ }; ++ }; ++ }; +--- /dev/null ++++ b/include/dt-bindings/net/qcom,qca808x.h +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Device Tree constants for the Qualcomm QCA808X PHYs ++ */ ++ ++#ifndef _DT_BINDINGS_QCOM_QCA808X_H ++#define _DT_BINDINGS_QCOM_QCA808X_H ++ ++/* PHY package modes of QCA8084 to apply the interface modes of two PCSes. */ ++#define QCA808X_PCS1_10G_QXGMII_PCS0_UNUNSED 0 ++#define QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_MAC 1 ++#define QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_PHY 2 ++ ++#endif diff --git a/target/linux/qualcommbe/patches-6.12/0307-net-phy-qca808x-Add-QCA8084-ethernet-phy-support.patch b/target/linux/qualcommbe/patches-6.12/0307-net-phy-qca808x-Add-QCA8084-ethernet-phy-support.patch new file mode 100644 index 0000000000..edfe8d1404 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0307-net-phy-qca808x-Add-QCA8084-ethernet-phy-support.patch @@ -0,0 +1,133 @@ +From 816bff9bcd2ff7c1e84dd14fc81c9c1bdaa609e7 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Thu, 6 Apr 2023 18:09:07 +0800 +Subject: [PATCH] net: phy: qca808x: Add QCA8084 ethernet phy support + +Add QCA8084 Quad-PHY support, which is a four-port PHY with +maximum link capability of 2.5 Gbps. The features of each port +are almost same as QCA8081. The slave seed and fast retrain +configs are not needed for QCA8084. It includes two PCSes. + +PCS0 of QCA8084 supports the interface modes: +PHY_INTERFACE_MODE_2500BASEX and PHY_INTERFACE_MODE_SGMII. + +PCS1 of QCA8084 supports the interface modes: +PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_2500BASEX and +PHY_INTERFACE_MODE_SGMII. + +The additional CDT configurations needed for QCA8084 compared +with QCA8081. + +Change-Id: I12555fa70662682474ab4432204405b5e752fef6 +Signed-off-by: Luo Jie +--- + drivers/net/phy/qcom/qca808x.c | 62 ++++++++++++++++++++++++++++++++-- + 1 file changed, 60 insertions(+), 2 deletions(-) + +--- a/drivers/net/phy/qcom/qca808x.c ++++ b/drivers/net/phy/qcom/qca808x.c +@@ -86,9 +86,16 @@ + #define QCA8081_PHY_FIFO_RSTN BIT(11) + + #define QCA8081_PHY_ID 0x004dd101 ++#define QCA8084_PHY_ID 0x004dd180 ++ ++#define QCA8084_MMD3_CDT_PULSE_CTRL 0x8075 ++#define QCA8084_CDT_PULSE_THRESH_VAL 0xa060 ++ ++#define QCA8084_MMD3_CDT_NEAR_CTRL 0x807f ++#define QCA8084_CDT_NEAR_BYPASS BIT(15) + + MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver"); +-MODULE_AUTHOR("Matus Ujhelyi"); ++MODULE_AUTHOR("Matus Ujhelyi, Luo Jie"); + MODULE_LICENSE("GPL"); + + struct qca808x_priv { +@@ -153,7 +160,9 @@ static bool qca808x_is_prefer_master(str + + static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) + { +- return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); ++ return phydev_id_compare(phydev, QCA8081_PHY_ID) && ++ linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, ++ phydev->supported); + } + + static bool qca808x_is_1g_only(struct phy_device *phydev) +@@ -273,6 +282,23 @@ static int qca808x_read_status(struct ph + return ret; + + if (phydev->link) { ++ /* There are two PCSes available for QCA8084, which support ++ * the following interface modes. ++ * ++ * 1. PHY_INTERFACE_MODE_10G_QXGMII utilizes PCS1 for all ++ * available 4 ports, which is for all link speeds. ++ * ++ * 2. PHY_INTERFACE_MODE_2500BASEX utilizes PCS0 for the ++ * fourth port, which is only for the link speed 2500M same ++ * as QCA8081. ++ * ++ * 3. PHY_INTERFACE_MODE_SGMII utilizes PCS0 for the fourth ++ * port, which is for the link speed 10M, 100M and 1000M same ++ * as QCA8081. ++ */ ++ if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) ++ return 0; ++ + if (phydev->speed == SPEED_2500) + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; + else +@@ -352,6 +378,18 @@ static int qca808x_cable_test_start(stru + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); + ++ if (phydev_id_compare(phydev, QCA8084_PHY_ID)) { ++ /* Adjust the positive and negative pulse thereshold of CDT. */ ++ phy_write_mmd(phydev, MDIO_MMD_PCS, ++ QCA8084_MMD3_CDT_PULSE_CTRL, ++ QCA8084_CDT_PULSE_THRESH_VAL); ++ ++ /* Disable the near bypass of CDT. */ ++ phy_modify_mmd(phydev, MDIO_MMD_PCS, ++ QCA8084_MMD3_CDT_NEAR_CTRL, ++ QCA8084_CDT_NEAR_BYPASS, 0); ++ } ++ + return 0; + } + +@@ -651,12 +689,32 @@ static struct phy_driver qca808x_driver[ + .led_hw_control_set = qca808x_led_hw_control_set, + .led_hw_control_get = qca808x_led_hw_control_get, + .led_polarity_set = qca808x_led_polarity_set, ++}, { ++ /* Qualcomm QCA8084 */ ++ PHY_ID_MATCH_MODEL(QCA8084_PHY_ID), ++ .name = "Qualcomm QCA8084", ++ .flags = PHY_POLL_CABLE_TEST, ++ .config_intr = at803x_config_intr, ++ .handle_interrupt = at803x_handle_interrupt, ++ .get_tunable = at803x_get_tunable, ++ .set_tunable = at803x_set_tunable, ++ .set_wol = at803x_set_wol, ++ .get_wol = at803x_get_wol, ++ .get_features = qca808x_get_features, ++ .config_aneg = qca808x_config_aneg, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_status = qca808x_read_status, ++ .soft_reset = qca808x_soft_reset, ++ .cable_test_start = qca808x_cable_test_start, ++ .cable_test_get_status = qca808x_cable_test_get_status, + }, }; + + module_phy_driver(qca808x_driver); + + static const struct mdio_device_id __maybe_unused qca808x_tbl[] = { + { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, ++ { PHY_ID_MATCH_MODEL(QCA8084_PHY_ID) }, + { } + }; + diff --git a/target/linux/qualcommbe/patches-6.12/0308-net-phy-qca808x-Add-config_init-function-for-QCA8084.patch b/target/linux/qualcommbe/patches-6.12/0308-net-phy-qca808x-Add-config_init-function-for-QCA8084.patch new file mode 100644 index 0000000000..196160188b --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0308-net-phy-qca808x-Add-config_init-function-for-QCA8084.patch @@ -0,0 +1,85 @@ +From 5a57611512593212b7fd9c23b4d96486bab6dee3 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Wed, 8 Nov 2023 16:18:02 +0800 +Subject: [PATCH] net: phy: qca808x: Add config_init function for QCA8084 + +1. The ADC of QCA8084 PHY must be configured as edge inverted +and falling whenever it is initialized or reset. In addition, +the default MSE (Mean square error) threshold value is adjusted, +which comes into play during link partner detection to detect +the valid link signal. + +2. Add the possible interface modes. + When QCA8084 works on the interface mode SGMII or 2500BASE-X, the + interface mode can be switched according to the PHY link speed. + + When QCA8084 works on the 10G-QXGMII mode, which will be the only + possible interface mode. + +Change-Id: I832c0d0b069e95cc411a8a7b680a5f60e1d6041a +Signed-off-by: Luo Jie +--- + drivers/net/phy/qcom/qca808x.c | 38 ++++++++++++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +--- a/drivers/net/phy/qcom/qca808x.c ++++ b/drivers/net/phy/qcom/qca808x.c +@@ -94,6 +94,15 @@ + #define QCA8084_MMD3_CDT_NEAR_CTRL 0x807f + #define QCA8084_CDT_NEAR_BYPASS BIT(15) + ++/* QCA8084 ADC clock edge */ ++#define QCA8084_ADC_CLK_SEL 0x8b80 ++#define QCA8084_ADC_CLK_SEL_ACLK GENMASK(7, 4) ++#define QCA8084_ADC_CLK_SEL_ACLK_FALL 0xf ++#define QCA8084_ADC_CLK_SEL_ACLK_RISE 0x0 ++ ++#define QCA8084_MSE_THRESHOLD 0x800a ++#define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 ++ + MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver"); + MODULE_AUTHOR("Matus Ujhelyi, Luo Jie"); + MODULE_LICENSE("GPL"); +@@ -660,6 +669,34 @@ static int qca808x_led_polarity_set(stru + active_low ? 0 : QCA808X_LED_ACTIVE_HIGH); + } + ++static int qca8084_config_init(struct phy_device *phydev) ++{ ++ int ret; ++ ++ if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) ++ __set_bit(PHY_INTERFACE_MODE_10G_QXGMII, ++ phydev->possible_interfaces); ++ else ++ qca808x_fill_possible_interfaces(phydev); ++ ++ /* Configure the ADC to convert the signal using falling edge ++ * instead of the default rising edge. ++ */ ++ ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL, ++ QCA8084_ADC_CLK_SEL_ACLK, ++ FIELD_PREP(QCA8084_ADC_CLK_SEL_ACLK, ++ QCA8084_ADC_CLK_SEL_ACLK_FALL)); ++ if (ret < 0) ++ return ret; ++ ++ /* Adjust MSE threshold value to avoid link issue with ++ * some link partner. ++ */ ++ return phy_write_mmd(phydev, MDIO_MMD_PMAPMD, ++ QCA8084_MSE_THRESHOLD, ++ QCA8084_MSE_THRESHOLD_2P5G_VAL); ++} ++ + static struct phy_driver qca808x_driver[] = { + { + /* Qualcomm QCA8081 */ +@@ -708,6 +745,7 @@ static struct phy_driver qca808x_driver[ + .soft_reset = qca808x_soft_reset, + .cable_test_start = qca808x_cable_test_start, + .cable_test_get_status = qca808x_cable_test_get_status, ++ .config_init = qca8084_config_init, + }, }; + + module_phy_driver(qca808x_driver); diff --git a/target/linux/qualcommbe/patches-6.12/0309-net-phy-qca808x-Add-link_change_notify-function-for-.patch b/target/linux/qualcommbe/patches-6.12/0309-net-phy-qca808x-Add-link_change_notify-function-for-.patch new file mode 100644 index 0000000000..429b5c0535 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0309-net-phy-qca808x-Add-link_change_notify-function-for-.patch @@ -0,0 +1,90 @@ +From d1f2a1810af1833196934977f57607432fda46b4 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Wed, 8 Nov 2023 18:01:14 +0800 +Subject: [PATCH] net: phy: qca808x: Add link_change_notify function for + QCA8084 + +When the link is changed, QCA8084 needs to do the fifo reset and +adjust the IPG level for the 10G-QXGMII link on the speed 1000M. + +Change-Id: I21de802c78496fb95f1c5119fe3894c9fdebbd65 +Signed-off-by: Luo Jie +--- + drivers/net/phy/qcom/qca808x.c | 52 ++++++++++++++++++++++++++++++++++ + 1 file changed, 52 insertions(+) + +--- a/drivers/net/phy/qcom/qca808x.c ++++ b/drivers/net/phy/qcom/qca808x.c +@@ -103,6 +103,14 @@ + #define QCA8084_MSE_THRESHOLD 0x800a + #define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 + ++/* QCA8084 FIFO reset control */ ++#define QCA8084_FIFO_CONTROL 0x19 ++#define QCA8084_FIFO_MAC_2_PHY BIT(1) ++#define QCA8084_FIFO_PHY_2_MAC BIT(0) ++ ++#define QCA8084_MMD7_IPG_OP 0x901d ++#define QCA8084_IPG_10_TO_11_EN BIT(0) ++ + MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver"); + MODULE_AUTHOR("Matus Ujhelyi, Luo Jie"); + MODULE_LICENSE("GPL"); +@@ -697,6 +705,49 @@ static int qca8084_config_init(struct ph + QCA8084_MSE_THRESHOLD_2P5G_VAL); + } + ++static void qca8084_link_change_notify(struct phy_device *phydev) ++{ ++ int ret; ++ ++ /* Assert the FIFO between PHY and MAC. */ ++ ret = phy_modify(phydev, QCA8084_FIFO_CONTROL, ++ QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC, ++ 0); ++ if (ret) { ++ phydev_err(phydev, "Asserting PHY FIFO failed\n"); ++ return; ++ } ++ ++ /* If the PHY is in 10G_QXGMII mode, the FIFO needs to be kept in ++ * reset state when link is down, otherwise the FIFO needs to be ++ * de-asserted after waiting 50 ms to make the assert completed. ++ */ ++ if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII || ++ phydev->link) { ++ msleep(50); ++ ++ /* Deassert the FIFO between PHY and MAC. */ ++ ret = phy_modify(phydev, QCA8084_FIFO_CONTROL, ++ QCA8084_FIFO_MAC_2_PHY | ++ QCA8084_FIFO_PHY_2_MAC, ++ QCA8084_FIFO_MAC_2_PHY | ++ QCA8084_FIFO_PHY_2_MAC); ++ if (ret) { ++ phydev_err(phydev, "De-asserting PHY FIFO failed\n"); ++ return; ++ } ++ } ++ ++ /* Enable IPG level 10 to 11 tuning for link speed 1000M in the ++ * 10G_QXGMII mode. ++ */ ++ if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) ++ phy_modify_mmd(phydev, MDIO_MMD_AN, QCA8084_MMD7_IPG_OP, ++ QCA8084_IPG_10_TO_11_EN, ++ phydev->speed == SPEED_1000 ? ++ QCA8084_IPG_10_TO_11_EN : 0); ++} ++ + static struct phy_driver qca808x_driver[] = { + { + /* Qualcomm QCA8081 */ +@@ -746,6 +797,7 @@ static struct phy_driver qca808x_driver[ + .cable_test_start = qca808x_cable_test_start, + .cable_test_get_status = qca808x_cable_test_get_status, + .config_init = qca8084_config_init, ++ .link_change_notify = qca8084_link_change_notify, + }, }; + + module_phy_driver(qca808x_driver); diff --git a/target/linux/qualcommbe/patches-6.12/0310-net-phy-qca808x-Add-register-access-support-routines.patch b/target/linux/qualcommbe/patches-6.12/0310-net-phy-qca808x-Add-register-access-support-routines.patch new file mode 100644 index 0000000000..899352a116 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0310-net-phy-qca808x-Add-register-access-support-routines.patch @@ -0,0 +1,125 @@ +From c17f19be3bec0bf5467f4e14a21573836910f671 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Wed, 29 Nov 2023 15:21:22 +0800 +Subject: [PATCH] net: phy: qca808x: Add register access support routines for + QCA8084 + +QCA8084 integrates clock controller and security control modules +besides of the PHY and PCS. The 32bit registers in these modules +are accessed using special MDIO sequences to read or write these +registers. + +The MDIO address of PHY and PCS are configured by writing to the +security control register. The package mode for QCA8084 is also +configured in a similar manner. + +Change-Id: I9317307ef9bbc738a6adcbc3ea1be8e6528d711e +Signed-off-by: Luo Jie +--- + drivers/net/phy/qcom/qca808x.c | 88 ++++++++++++++++++++++++++++++++++ + 1 file changed, 88 insertions(+) + +--- a/drivers/net/phy/qcom/qca808x.c ++++ b/drivers/net/phy/qcom/qca808x.c +@@ -111,6 +111,22 @@ + #define QCA8084_MMD7_IPG_OP 0x901d + #define QCA8084_IPG_10_TO_11_EN BIT(0) + ++/* QCA8084 includes secure control module, which supports customizing the ++ * MDIO address of PHY device and PCS device and configuring package mode ++ * for the interface mode of PCS. The register of secure control is accessed ++ * by MDIO bus with the special MDIO sequences, where the 32 bits register ++ * address is split into 3 MDIO operations with 16 bits address. ++ */ ++#define QCA8084_HIGH_ADDR_PREFIX 0x18 ++#define QCA8084_LOW_ADDR_PREFIX 0x10 ++ ++/* Bottom two bits of REG must be zero */ ++#define QCA8084_MII_REG_MASK GENMASK(4, 0) ++#define QCA8084_MII_PHY_ADDR_MASK GENMASK(7, 5) ++#define QCA8084_MII_PAGE_MASK GENMASK(23, 8) ++#define QCA8084_MII_SW_ADDR_MASK GENMASK(31, 24) ++#define QCA8084_MII_REG_DATA_UPPER_16_BITS BIT(1) ++ + MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver"); + MODULE_AUTHOR("Matus Ujhelyi, Luo Jie"); + MODULE_LICENSE("GPL"); +@@ -119,6 +135,78 @@ struct qca808x_priv { + int led_polarity_mode; + }; + ++static int __qca8084_set_page(struct mii_bus *bus, u16 sw_addr, u16 page) ++{ ++ return __mdiobus_write(bus, QCA8084_HIGH_ADDR_PREFIX | (sw_addr >> 5), ++ sw_addr & 0x1f, page); ++} ++ ++static int __qca8084_mii_read(struct mii_bus *bus, u16 addr, u16 reg, u32 *val) ++{ ++ int ret, data; ++ ++ ret = __mdiobus_read(bus, addr, reg); ++ if (ret < 0) ++ return ret; ++ ++ data = ret; ++ ret = __mdiobus_read(bus, addr, ++ reg | QCA8084_MII_REG_DATA_UPPER_16_BITS); ++ if (ret < 0) ++ return ret; ++ ++ *val = data | ret << 16; ++ ++ return 0; ++} ++ ++static int __qca8084_mii_write(struct mii_bus *bus, u16 addr, u16 reg, u32 val) ++{ ++ int ret; ++ ++ ret = __mdiobus_write(bus, addr, reg, lower_16_bits(val)); ++ if (!ret) ++ ret = __mdiobus_write(bus, addr, ++ reg | QCA8084_MII_REG_DATA_UPPER_16_BITS, ++ upper_16_bits(val)); ++ ++ return ret; ++} ++ ++static int qca8084_mii_modify(struct phy_device *phydev, u32 regaddr, ++ u32 clear, u32 set) ++{ ++ u16 reg, addr, page, sw_addr; ++ struct mii_bus *bus; ++ u32 val; ++ int ret; ++ ++ bus = phydev->mdio.bus; ++ mutex_lock(&bus->mdio_lock); ++ ++ reg = FIELD_GET(QCA8084_MII_REG_MASK, regaddr); ++ addr = FIELD_GET(QCA8084_MII_PHY_ADDR_MASK, regaddr); ++ page = FIELD_GET(QCA8084_MII_PAGE_MASK, regaddr); ++ sw_addr = FIELD_GET(QCA8084_MII_SW_ADDR_MASK, regaddr); ++ ++ ret = __qca8084_set_page(bus, sw_addr, page); ++ if (ret < 0) ++ goto qca8084_mii_modify_exit; ++ ++ ret = __qca8084_mii_read(bus, QCA8084_LOW_ADDR_PREFIX | addr, ++ reg, &val); ++ if (ret < 0) ++ goto qca8084_mii_modify_exit; ++ ++ val &= ~clear; ++ val |= set; ++ ret = __qca8084_mii_write(bus, QCA8084_LOW_ADDR_PREFIX | addr, ++ reg, val); ++qca8084_mii_modify_exit: ++ mutex_unlock(&bus->mdio_lock); ++ return ret; ++}; ++ + static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) + { + int ret; diff --git a/target/linux/qualcommbe/patches-6.12/0311-net-phy-qca808x-Add-QCA8084-probe-function.patch b/target/linux/qualcommbe/patches-6.12/0311-net-phy-qca808x-Add-QCA8084-probe-function.patch new file mode 100644 index 0000000000..b8c5e9ee91 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0311-net-phy-qca808x-Add-QCA8084-probe-function.patch @@ -0,0 +1,140 @@ +From 485f973c5b1d889bd1f48a188137d80d45004991 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Mon, 29 Jan 2024 10:51:38 +0800 +Subject: [PATCH] net: phy: qca808x: Add QCA8084 probe function + +Add the PHY package probe function. The MDIO slave address of +PHY, PCS and XPCS can be optionally customized by configuring +the PHY package level register. + +In addition, enable system clock of PHY and de-assert PHY in +the probe function so that the register of PHY device can be +accessed, and the features of PHY can be acquired. + +Change-Id: I2251b9c5c398a21a4ef547a727189a934ad3a44c +Signed-off-by: Luo Jie +--- + drivers/net/phy/qcom/qca808x.c | 91 ++++++++++++++++++++++++++++++++++ + 1 file changed, 91 insertions(+) + +--- a/drivers/net/phy/qcom/qca808x.c ++++ b/drivers/net/phy/qcom/qca808x.c +@@ -2,6 +2,8 @@ + + #include + #include ++#include ++#include + + #include "qcom.h" + +@@ -127,6 +129,21 @@ + #define QCA8084_MII_SW_ADDR_MASK GENMASK(31, 24) + #define QCA8084_MII_REG_DATA_UPPER_16_BITS BIT(1) + ++/* QCA8084 integrates 4 PHYs, PCS0 and PCS1(includes PCS and XPCS). */ ++#define QCA8084_MDIO_DEVICE_NUM 7 ++ ++#define QCA8084_PCS_CFG 0xc90f014 ++#define QCA8084_PCS_ADDR0_MASK GENMASK(4, 0) ++#define QCA8084_PCS_ADDR1_MASK GENMASK(9, 5) ++#define QCA8084_PCS_ADDR2_MASK GENMASK(14, 10) ++ ++#define QCA8084_EPHY_CFG 0xc90f018 ++#define QCA8084_EPHY_ADDR0_MASK GENMASK(4, 0) ++#define QCA8084_EPHY_ADDR1_MASK GENMASK(9, 5) ++#define QCA8084_EPHY_ADDR2_MASK GENMASK(14, 10) ++#define QCA8084_EPHY_ADDR3_MASK GENMASK(19, 15) ++#define QCA8084_EPHY_LDO_EN GENMASK(21, 20) ++ + MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver"); + MODULE_AUTHOR("Matus Ujhelyi, Luo Jie"); + MODULE_LICENSE("GPL"); +@@ -836,6 +853,79 @@ static void qca8084_link_change_notify(s + QCA8084_IPG_10_TO_11_EN : 0); + } + ++static int qca8084_phy_package_probe_once(struct phy_device *phydev) ++{ ++ int addr[QCA8084_MDIO_DEVICE_NUM] = {0, 1, 2, 3, 4, 5, 6}; ++ struct phy_package_shared *shared = phydev->shared; ++ int ret, clear, set; ++ ++ /* Program the MDIO address of PHY and PCS optionally, the MDIO ++ * address 0-6 is used for PHY and PCS MDIO devices by default. ++ */ ++ ret = of_property_read_u32_array(shared->np, ++ "qcom,phy-addr-fixup", ++ addr, ARRAY_SIZE(addr)); ++ if (ret && ret != -EINVAL) ++ return ret; ++ ++ /* Configure the MDIO addresses for the four PHY devices. */ ++ clear = QCA8084_EPHY_ADDR0_MASK | QCA8084_EPHY_ADDR1_MASK | ++ QCA8084_EPHY_ADDR2_MASK | QCA8084_EPHY_ADDR3_MASK; ++ set = FIELD_PREP(QCA8084_EPHY_ADDR0_MASK, addr[0]); ++ set |= FIELD_PREP(QCA8084_EPHY_ADDR1_MASK, addr[1]); ++ set |= FIELD_PREP(QCA8084_EPHY_ADDR2_MASK, addr[2]); ++ set |= FIELD_PREP(QCA8084_EPHY_ADDR3_MASK, addr[3]); ++ ++ ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG, clear, set); ++ if (ret) ++ return ret; ++ ++ /* Configure the MDIO addresses for PCS0 and PCS1 including ++ * PCS and XPCS. ++ */ ++ clear = QCA8084_PCS_ADDR0_MASK | QCA8084_PCS_ADDR1_MASK | ++ QCA8084_PCS_ADDR2_MASK; ++ set = FIELD_PREP(QCA8084_PCS_ADDR0_MASK, addr[4]); ++ set |= FIELD_PREP(QCA8084_PCS_ADDR1_MASK, addr[5]); ++ set |= FIELD_PREP(QCA8084_PCS_ADDR2_MASK, addr[6]); ++ ++ return qca8084_mii_modify(phydev, QCA8084_PCS_CFG, clear, set); ++} ++ ++static int qca8084_probe(struct phy_device *phydev) ++{ ++ struct device *dev = &phydev->mdio.dev; ++ struct reset_control *rstc; ++ struct clk *clk; ++ int ret; ++ ++ ret = devm_of_phy_package_join(dev, phydev, 0); ++ if (ret) ++ return ret; ++ ++ if (phy_package_probe_once(phydev)) { ++ ret = qca8084_phy_package_probe_once(phydev); ++ if (ret) ++ return ret; ++ } ++ ++ /* Enable clock of PHY device, so that the PHY register ++ * can be accessed to get PHY features. ++ */ ++ clk = devm_clk_get_enabled(dev, NULL); ++ if (IS_ERR(clk)) ++ return dev_err_probe(dev, PTR_ERR(clk), ++ "Enable PHY clock failed\n"); ++ ++ /* De-assert PHY reset after the clock of PHY enabled. */ ++ rstc = devm_reset_control_get_exclusive(dev, NULL); ++ if (IS_ERR(rstc)) ++ return dev_err_probe(dev, PTR_ERR(rstc), ++ "Get PHY reset failed\n"); ++ ++ return reset_control_deassert(rstc); ++} ++ + static struct phy_driver qca808x_driver[] = { + { + /* Qualcomm QCA8081 */ +@@ -886,6 +976,7 @@ static struct phy_driver qca808x_driver[ + .cable_test_get_status = qca808x_cable_test_get_status, + .config_init = qca8084_config_init, + .link_change_notify = qca8084_link_change_notify, ++ .probe = qca8084_probe, + }, }; + + module_phy_driver(qca808x_driver); diff --git a/target/linux/qualcommbe/patches-6.12/0312-net-phy-qca808x-Add-package-clocks-and-resets-for-QC.patch b/target/linux/qualcommbe/patches-6.12/0312-net-phy-qca808x-Add-package-clocks-and-resets-for-QC.patch new file mode 100644 index 0000000000..b41e725d30 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0312-net-phy-qca808x-Add-package-clocks-and-resets-for-QC.patch @@ -0,0 +1,132 @@ +From 685566f8b765f522b7f4d4deb06bf84a557dc4ac Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Tue, 9 Apr 2024 16:30:55 +0800 +Subject: [PATCH] net: phy: qca808x: Add package clocks and resets for QCA8084 + +Parse the PHY package clocks from the PHY package DTS node. +These package level clocks will be enabled in the PHY package +init function. + +Deassert PHY package reset, which is necessary for accessing +the PHY registers. + +Change-Id: I254d0aa0a1155d3618c6f1fc7d7a5b6ecadccbaa +Signed-off-by: Luo Jie +--- + drivers/net/phy/qcom/qca808x.c | 67 ++++++++++++++++++++++++++++++++-- + 1 file changed, 64 insertions(+), 3 deletions(-) + +--- a/drivers/net/phy/qcom/qca808x.c ++++ b/drivers/net/phy/qcom/qca808x.c +@@ -4,6 +4,7 @@ + #include + #include + #include ++#include + + #include "qcom.h" + +@@ -148,10 +149,35 @@ MODULE_DESCRIPTION("Qualcomm Atheros QCA + MODULE_AUTHOR("Matus Ujhelyi, Luo Jie"); + MODULE_LICENSE("GPL"); + ++enum { ++ APB_BRIDGE_CLK, ++ AHB_CLK, ++ SEC_CTRL_AHB_CLK, ++ TLMM_CLK, ++ TLMM_AHB_CLK, ++ CNOC_AHB_CLK, ++ MDIO_AHB_CLK, ++ PACKAGE_CLK_MAX ++}; ++ + struct qca808x_priv { + int led_polarity_mode; + }; + ++struct qca808x_shared_priv { ++ struct clk *clk[PACKAGE_CLK_MAX]; ++}; ++ ++static const char *const qca8084_package_clk_name[PACKAGE_CLK_MAX] = { ++ [APB_BRIDGE_CLK] = "apb_bridge", ++ [AHB_CLK] = "ahb", ++ [SEC_CTRL_AHB_CLK] = "sec_ctrl_ahb", ++ [TLMM_CLK] = "tlmm", ++ [TLMM_AHB_CLK] = "tlmm_ahb", ++ [CNOC_AHB_CLK] = "cnoc_ahb", ++ [MDIO_AHB_CLK] = "mdio_ahb", ++}; ++ + static int __qca8084_set_page(struct mii_bus *bus, u16 sw_addr, u16 page) + { + return __mdiobus_write(bus, QCA8084_HIGH_ADDR_PREFIX | (sw_addr >> 5), +@@ -853,11 +879,24 @@ static void qca8084_link_change_notify(s + QCA8084_IPG_10_TO_11_EN : 0); + } + ++/* QCA8084 is a four-port PHY, which integrates the clock controller, ++ * 4 PHY devices and 2 PCS interfaces (PCS0 and PCS1). PCS1 includes ++ * XPCS and PCS to support 10G-QXGMII and SGMII. PCS0 includes one PCS ++ * to support SGMII. ++ * ++ * The clocks and resets are sourced from the integrated clock controller ++ * of the PHY package. This integrated clock controller is driven by a ++ * QCA8K clock provider that supplies the clocks and resets to the four ++ * PHYs, PCS and PHY package. ++ */ + static int qca8084_phy_package_probe_once(struct phy_device *phydev) + { + int addr[QCA8084_MDIO_DEVICE_NUM] = {0, 1, 2, 3, 4, 5, 6}; + struct phy_package_shared *shared = phydev->shared; +- int ret, clear, set; ++ struct qca808x_shared_priv *shared_priv; ++ struct reset_control *rstc; ++ int i, ret, clear, set; ++ struct clk *clk; + + /* Program the MDIO address of PHY and PCS optionally, the MDIO + * address 0-6 is used for PHY and PCS MDIO devices by default. +@@ -889,17 +928,39 @@ static int qca8084_phy_package_probe_onc + set |= FIELD_PREP(QCA8084_PCS_ADDR1_MASK, addr[5]); + set |= FIELD_PREP(QCA8084_PCS_ADDR2_MASK, addr[6]); + +- return qca8084_mii_modify(phydev, QCA8084_PCS_CFG, clear, set); ++ ret = qca8084_mii_modify(phydev, QCA8084_PCS_CFG, clear, set); ++ if (ret) ++ return ret; ++ ++ shared_priv = shared->priv; ++ for (i = 0; i < ARRAY_SIZE(qca8084_package_clk_name); i++) { ++ clk = of_clk_get_by_name(shared->np, ++ qca8084_package_clk_name[i]); ++ if (IS_ERR(clk)) ++ return dev_err_probe(&phydev->mdio.dev, PTR_ERR(clk), ++ "package clock %s not ready\n", ++ qca8084_package_clk_name[i]); ++ shared_priv->clk[i] = clk; ++ } ++ ++ rstc = of_reset_control_get_exclusive(shared->np, NULL); ++ if (IS_ERR(rstc)) ++ return dev_err_probe(&phydev->mdio.dev, PTR_ERR(rstc), ++ "package reset not ready\n"); ++ ++ /* Deassert PHY package. */ ++ return reset_control_deassert(rstc); + } + + static int qca8084_probe(struct phy_device *phydev) + { ++ struct qca808x_shared_priv *shared_priv; + struct device *dev = &phydev->mdio.dev; + struct reset_control *rstc; + struct clk *clk; + int ret; + +- ret = devm_of_phy_package_join(dev, phydev, 0); ++ ret = devm_of_phy_package_join(dev, phydev, sizeof(*shared_priv)); + if (ret) + return ret; + diff --git a/target/linux/qualcommbe/patches-6.12/0313-net-phy-qca808x-Add-QCA8084-package-init-function.patch b/target/linux/qualcommbe/patches-6.12/0313-net-phy-qca808x-Add-QCA8084-package-init-function.patch new file mode 100644 index 0000000000..bb5d0728e4 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0313-net-phy-qca808x-Add-QCA8084-package-init-function.patch @@ -0,0 +1,171 @@ +From bf779b10b00fd79267d0ef625ae246df59ee23bd Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Thu, 25 Jan 2024 17:13:24 +0800 +Subject: [PATCH] net: phy: qca808x: Add QCA8084 package init function + +The package mode of PHY is configured for the interface mode of two +PCSes working correctly. + +The PHY package level clocks are enabled and their rates configured. + +Change-Id: I63d4b22d2a70ee713cc6a6818b0f3c7aa098a5f5 +Signed-off-by: Luo Jie +--- + drivers/net/phy/qcom/qca808x.c | 115 +++++++++++++++++++++++++++++++++ + 1 file changed, 115 insertions(+) + +--- a/drivers/net/phy/qcom/qca808x.c ++++ b/drivers/net/phy/qcom/qca808x.c +@@ -1,5 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0+ + ++#include + #include + #include + #include +@@ -145,6 +146,13 @@ + #define QCA8084_EPHY_ADDR3_MASK GENMASK(19, 15) + #define QCA8084_EPHY_LDO_EN GENMASK(21, 20) + ++#define QCA8084_WORK_MODE_CFG 0xc90f030 ++#define QCA8084_WORK_MODE_MASK GENMASK(5, 0) ++#define QCA8084_WORK_MODE_QXGMII (BIT(5) | GENMASK(3, 0)) ++#define QCA8084_WORK_MODE_QXGMII_PORT4_SGMII (BIT(5) | GENMASK(2, 0)) ++#define QCA8084_WORK_MODE_SWITCH BIT(4) ++#define QCA8084_WORK_MODE_SWITCH_PORT4_SGMII BIT(5) ++ + MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver"); + MODULE_AUTHOR("Matus Ujhelyi, Luo Jie"); + MODULE_LICENSE("GPL"); +@@ -165,6 +173,7 @@ struct qca808x_priv { + }; + + struct qca808x_shared_priv { ++ int package_mode; + struct clk *clk[PACKAGE_CLK_MAX]; + }; + +@@ -808,10 +817,107 @@ static int qca808x_led_polarity_set(stru + active_low ? 0 : QCA808X_LED_ACTIVE_HIGH); + } + ++static int qca8084_package_clock_init(struct qca808x_shared_priv *shared_priv) ++{ ++ int ret; ++ ++ /* Configure clock rate 312.5MHZ for the PHY package ++ * APB bridge clock tree. ++ */ ++ ret = clk_set_rate(shared_priv->clk[APB_BRIDGE_CLK], 312500000); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(shared_priv->clk[APB_BRIDGE_CLK]); ++ if (ret) ++ return ret; ++ ++ /* Configure clock rate 104.17MHZ for the PHY package ++ * AHB clock tree. ++ */ ++ ret = clk_set_rate(shared_priv->clk[AHB_CLK], 104170000); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(shared_priv->clk[AHB_CLK]); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(shared_priv->clk[SEC_CTRL_AHB_CLK]); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(shared_priv->clk[TLMM_CLK]); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(shared_priv->clk[TLMM_AHB_CLK]); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(shared_priv->clk[CNOC_AHB_CLK]); ++ if (ret) ++ return ret; ++ ++ return clk_prepare_enable(shared_priv->clk[MDIO_AHB_CLK]); ++} ++ ++static int qca8084_phy_package_config_init_once(struct phy_device *phydev) ++{ ++ struct phy_package_shared *shared = phydev->shared; ++ struct qca808x_shared_priv *shared_priv; ++ int ret, mode; ++ ++ shared_priv = shared->priv; ++ switch (shared_priv->package_mode) { ++ case QCA808X_PCS1_10G_QXGMII_PCS0_UNUNSED: ++ mode = QCA8084_WORK_MODE_QXGMII; ++ break; ++ case QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_MAC: ++ mode = QCA8084_WORK_MODE_SWITCH; ++ break; ++ case QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_PHY: ++ mode = QCA8084_WORK_MODE_SWITCH_PORT4_SGMII; ++ break; ++ default: ++ phydev_err(phydev, "Invalid qcom,package-mode %d\n", ++ shared_priv->package_mode); ++ return -EINVAL; ++ } ++ ++ ret = qca8084_mii_modify(phydev, QCA8084_WORK_MODE_CFG, ++ QCA8084_WORK_MODE_MASK, ++ FIELD_PREP(QCA8084_WORK_MODE_MASK, mode)); ++ if (ret) ++ return ret; ++ ++ /* Initialize the PHY package clock and reset, which is the ++ * necessary config sequence after GPIO reset on the PHY package. ++ */ ++ ret = qca8084_package_clock_init(shared_priv); ++ if (ret) ++ return ret; ++ ++ /* Enable efuse loading into analog circuit */ ++ ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG, ++ QCA8084_EPHY_LDO_EN, 0); ++ if (ret) ++ return ret; ++ ++ usleep_range(10000, 11000); ++ return ret; ++} ++ + static int qca8084_config_init(struct phy_device *phydev) + { + int ret; + ++ if (phy_package_init_once(phydev)) { ++ ret = qca8084_phy_package_config_init_once(phydev); ++ if (ret) ++ return ret; ++ } ++ + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) + __set_bit(PHY_INTERFACE_MODE_10G_QXGMII, + phydev->possible_interfaces); +@@ -948,6 +1054,15 @@ static int qca8084_phy_package_probe_onc + return dev_err_probe(&phydev->mdio.dev, PTR_ERR(rstc), + "package reset not ready\n"); + ++ /* The package mode 10G-QXGMII of PCS1 is used for Quad PHY and ++ * PCS0 is unused by default. ++ */ ++ shared_priv->package_mode = QCA808X_PCS1_10G_QXGMII_PCS0_UNUNSED; ++ ret = of_property_read_u32(shared->np, "qcom,package-mode", ++ &shared_priv->package_mode); ++ if (ret && ret != -EINVAL) ++ return ret; ++ + /* Deassert PHY package. */ + return reset_control_deassert(rstc); + } diff --git a/target/linux/qualcommbe/patches-6.12/0314-dt-bindings-net-pcs-Add-Ethernet-PCS-for-Qualcomm-IP.patch b/target/linux/qualcommbe/patches-6.12/0314-dt-bindings-net-pcs-Add-Ethernet-PCS-for-Qualcomm-IP.patch new file mode 100644 index 0000000000..1112d4e072 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0314-dt-bindings-net-pcs-Add-Ethernet-PCS-for-Qualcomm-IP.patch @@ -0,0 +1,234 @@ +From 5f650721c4b232a14a1a3e25b686f2234faee961 Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Fri, 7 Feb 2025 23:53:12 +0800 +Subject: [PATCH] dt-bindings: net: pcs: Add Ethernet PCS for Qualcomm IPQ9574 + SoC + +The 'UNIPHY' PCS block in the IPQ9574 SoC includes PCS and SerDes +functions. It supports different interface modes to enable Ethernet +MAC connections to different types of external PHYs/switch. It includes +PCS functions for 1Gbps and 2.5Gbps interface modes and XPCS functions +for 10Gbps interface modes. There are three UNIPHY (PCS) instances +in IPQ9574 SoC which provide PCS/XPCS functions to the six Ethernet +ports. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Lei Wei +--- + .../bindings/net/pcs/qcom,ipq9574-pcs.yaml | 190 ++++++++++++++++++ + include/dt-bindings/net/qcom,ipq9574-pcs.h | 15 ++ + 2 files changed, 205 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml + create mode 100644 include/dt-bindings/net/qcom,ipq9574-pcs.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml +@@ -0,0 +1,190 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/pcs/qcom,ipq9574-pcs.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Ethernet PCS for Qualcomm IPQ9574 SoC ++ ++maintainers: ++ - Lei Wei ++ ++description: ++ The UNIPHY hardware blocks in the Qualcomm IPQ SoC include PCS and SerDes ++ functions. They enable connectivity between the Ethernet MAC inside the ++ PPE (packet processing engine) and external Ethernet PHY/switch. There are ++ three UNIPHY instances in IPQ9574 SoC which provide PCS functions to the ++ six Ethernet ports. ++ ++ For SGMII (1Gbps PHY) or 2500BASE-X (2.5Gbps PHY) interface modes, the PCS ++ function is enabled by using the PCS block inside UNIPHY. For USXGMII (10Gbps ++ PHY), the XPCS block in UNIPHY is used. ++ ++ The SerDes provides 125M (1Gbps mode) or 312.5M (2.5Gbps and 10Gbps modes) ++ RX and TX clocks to the NSSCC (Networking Sub System Clock Controller). The ++ NSSCC divides these clocks and generates the MII RX and TX clocks to each ++ of the MII interfaces between the PCS and MAC, as per the link speeds and ++ interface modes. ++ ++ Different IPQ SoC may support different number of UNIPHYs (PCSes) since the ++ number of ports and their capabilities can be different between these SoCs ++ ++ Below diagram depicts the UNIPHY (PCS) connections for an IPQ9574 SoC based ++ board. In this example, the PCS0 has four GMIIs/XGMIIs, which can connect ++ with four MACs to support QSGMII (4 x 1Gbps) or 10G_QXGMII (4 x 2.5Gbps) ++ interface modes. ++ ++ - +-------+ +---------+ +-------------------------+ ++ +---------+CMN PLL| | GCC | | NSSCC (Divider) | ++ | +----+--+ +----+----+ +--+-------+--------------+ ++ | | | ^ | ++ | 31.25M | SYS/AHB|clk RX/TX|clk +------------+ ++ | ref clk| | | | | ++ | | v | MII RX|TX clk MAC| RX/TX clk ++ |25/50M +--+---------+----------+-------+---+ +-+---------+ ++ |ref clk | | +----------------+ | | | | PPE | ++ v | | | UNIPHY0 V | | V | ++ +-------+ | v | +-----------+ (X)GMII| | | ++ | | | +---+---+ | |--------|------|-- MAC0 | ++ | | | | | | | (X)GMII| | | ++ | Quad | | |SerDes | | PCS/XPCS |--------|------|-- MAC1 | ++ | +<----+ | | | | (X)GMII| | | ++ |(X)GPHY| | | | | |--------|------|-- MAC2 | ++ | | | | | | | (X)GMII| | | ++ | | | +-------+ | |--------|------|-- MAC3 | ++ +-------+ | | | | | | ++ | +-----------+ | | | ++ +-----------------------------------+ | | ++ +--+---------+----------+-------+---+ | | ++ +-------+ | UNIPHY1 | | | ++ | | | +-----------+ | | | ++ |(X)GPHY| | +-------+ | | (X)GMII| | | ++ | +<----+ |SerDes | | PCS/XPCS |--------|------|- MAC4 | ++ | | | | | | | | | | ++ +-------+ | +-------+ | | | | | ++ | +-----------+ | | | ++ +-----------------------------------+ | | ++ +--+---------+----------+-------+---+ | | ++ +-------+ | UNIPHY2 | | | ++ | | | +-----------+ | | | ++ |(X)GPHY| | +-------+ | | (X)GMII| | | ++ | +<----+ |SerDes | | PCS/XPCS |--------|------|- MAC5 | ++ | | | | | | | | | | ++ +-------+ | +-------+ | | | | | ++ | +-----------+ | | | ++ +-----------------------------------+ +-----------+ ++ ++properties: ++ compatible: ++ enum: ++ - qcom,ipq9574-pcs ++ ++ reg: ++ maxItems: 1 ++ ++ '#address-cells': ++ const: 1 ++ ++ '#size-cells': ++ const: 0 ++ ++ clocks: ++ items: ++ - description: System clock ++ - description: AHB clock needed for register interface access ++ ++ clock-names: ++ items: ++ - const: sys ++ - const: ahb ++ ++ '#clock-cells': ++ const: 1 ++ description: See include/dt-bindings/net/qcom,ipq9574-pcs.h for constants ++ ++patternProperties: ++ '^pcs-mii@[0-4]$': ++ type: object ++ description: PCS MII interface. ++ ++ properties: ++ reg: ++ minimum: 0 ++ maximum: 4 ++ description: MII index ++ ++ clocks: ++ items: ++ - description: PCS MII RX clock ++ - description: PCS MII TX clock ++ ++ clock-names: ++ items: ++ - const: rx ++ - const: tx ++ ++ required: ++ - reg ++ - clocks ++ - clock-names ++ ++ additionalProperties: false ++ ++required: ++ - compatible ++ - reg ++ - '#address-cells' ++ - '#size-cells' ++ - clocks ++ - clock-names ++ - '#clock-cells' ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ ++ ethernet-pcs@7a00000 { ++ compatible = "qcom,ipq9574-pcs"; ++ reg = <0x7a00000 0x10000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&gcc GCC_UNIPHY0_SYS_CLK>, ++ <&gcc GCC_UNIPHY0_AHB_CLK>; ++ clock-names = "sys", ++ "ahb"; ++ #clock-cells = <1>; ++ ++ pcs-mii@0 { ++ reg = <0>; ++ clocks = <&nsscc 116>, ++ <&nsscc 117>; ++ clock-names = "rx", ++ "tx"; ++ }; ++ ++ pcs-mii@1 { ++ reg = <1>; ++ clocks = <&nsscc 118>, ++ <&nsscc 119>; ++ clock-names = "rx", ++ "tx"; ++ }; ++ ++ pcs-mii@2 { ++ reg = <2>; ++ clocks = <&nsscc 120>, ++ <&nsscc 121>; ++ clock-names = "rx", ++ "tx"; ++ }; ++ ++ pcs-mii@3 { ++ reg = <3>; ++ clocks = <&nsscc 122>, ++ <&nsscc 123>; ++ clock-names = "rx", ++ "tx"; ++ }; ++ }; +--- /dev/null ++++ b/include/dt-bindings/net/qcom,ipq9574-pcs.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ * ++ * Device Tree constants for the Qualcomm IPQ9574 PCS ++ */ ++ ++#ifndef _DT_BINDINGS_PCS_QCOM_IPQ9574_H ++#define _DT_BINDINGS_PCS_QCOM_IPQ9574_H ++ ++/* The RX and TX clocks which are provided from the SerDes to NSSCC. */ ++#define PCS_RX_CLK 0 ++#define PCS_TX_CLK 1 ++ ++#endif /* _DT_BINDINGS_PCS_QCOM_IPQ9574_H */ diff --git a/target/linux/qualcommbe/patches-6.12/0315-net-pcs-Add-PCS-driver-for-Qualcomm-IPQ9574-SoC.patch b/target/linux/qualcommbe/patches-6.12/0315-net-pcs-Add-PCS-driver-for-Qualcomm-IPQ9574-SoC.patch new file mode 100644 index 0000000000..bae262a01c --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0315-net-pcs-Add-PCS-driver-for-Qualcomm-IPQ9574-SoC.patch @@ -0,0 +1,301 @@ +From e404519d9f3e5e7d661cb105d3766d87e37e4ef5 Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Fri, 7 Feb 2025 23:53:13 +0800 +Subject: [PATCH] net: pcs: Add PCS driver for Qualcomm IPQ9574 SoC + +The 'UNIPHY' PCS hardware block in Qualcomm's IPQ SoC supports +different interface modes to enable Ethernet MAC connections +for different types of external PHYs/switch. Each UNIPHY block +includes a SerDes and PCS/XPCS blocks, and can operate in either +PCS or XPCS modes. It supports 1Gbps and 2.5Gbps interface modes +(Ex: SGMII) using the PCS, and 10Gbps interface modes (Ex: USXGMII) +using the XPCS. There are three UNIPHY (PCS) instances in IPQ9574 +SoC which support the six Ethernet ports in the SoC. + +This patch adds support for the platform driver, probe and clock +registrations for the PCS driver. The platform driver creates an +'ipq_pcs' instance for each of the UNIPHY used on the given board. + +Signed-off-by: Lei Wei +--- + drivers/net/pcs/Kconfig | 9 ++ + drivers/net/pcs/Makefile | 1 + + drivers/net/pcs/pcs-qcom-ipq9574.c | 245 +++++++++++++++++++++++++++++ + 3 files changed, 255 insertions(+) + create mode 100644 drivers/net/pcs/pcs-qcom-ipq9574.c + +--- a/drivers/net/pcs/Kconfig ++++ b/drivers/net/pcs/Kconfig +@@ -36,6 +36,15 @@ config PCS_MTK_USXGMII + 1000Base-X, 2500Base-X and Cisco SGMII are supported on the same + differential pairs via an embedded LynxI PHY. + ++config PCS_QCOM_IPQ9574 ++ tristate "Qualcomm IPQ9574 PCS" ++ depends on OF && (ARCH_QCOM || COMPILE_TEST) ++ depends on HAS_IOMEM && COMMON_CLK ++ help ++ This module provides driver for UNIPHY PCS available on Qualcomm ++ IPQ9574 SoC. The UNIPHY PCS supports both PCS and XPCS functions ++ to support different interface modes for MAC to PHY connections. ++ + config PCS_RZN1_MIIC + tristate "Renesas RZ/N1 MII converter" + depends on OF && (ARCH_RZN1 || COMPILE_TEST) +--- a/drivers/net/pcs/Makefile ++++ b/drivers/net/pcs/Makefile +@@ -7,5 +7,6 @@ pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs. + obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o + obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o + obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o ++obj-$(CONFIG_PCS_QCOM_IPQ9574) += pcs-qcom-ipq9574.o + obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o + obj-$(CONFIG_PCS_MTK_USXGMII) += pcs-mtk-usxgmii.o +--- /dev/null ++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c +@@ -0,0 +1,245 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define XPCS_INDIRECT_ADDR 0x8000 ++#define XPCS_INDIRECT_AHB_ADDR 0x83fc ++#define XPCS_INDIRECT_ADDR_H GENMASK(20, 8) ++#define XPCS_INDIRECT_ADDR_L GENMASK(7, 0) ++#define XPCS_INDIRECT_DATA_ADDR(reg) (FIELD_PREP(GENMASK(15, 10), 0x20) | \ ++ FIELD_PREP(GENMASK(9, 2), \ ++ FIELD_GET(XPCS_INDIRECT_ADDR_L, reg))) ++ ++/* PCS private data */ ++struct ipq_pcs { ++ struct device *dev; ++ void __iomem *base; ++ struct regmap *regmap; ++ phy_interface_t interface; ++ ++ /* RX clock supplied to NSSCC */ ++ struct clk_hw rx_hw; ++ /* TX clock supplied to NSSCC */ ++ struct clk_hw tx_hw; ++}; ++ ++static unsigned long ipq_pcs_clk_rate_get(struct ipq_pcs *qpcs) ++{ ++ switch (qpcs->interface) { ++ case PHY_INTERFACE_MODE_USXGMII: ++ return 312500000; ++ default: ++ return 125000000; ++ } ++} ++ ++/* Return clock rate for the RX clock supplied to NSSCC ++ * as per the interface mode. ++ */ ++static unsigned long ipq_pcs_rx_clk_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct ipq_pcs *qpcs = container_of(hw, struct ipq_pcs, rx_hw); ++ ++ return ipq_pcs_clk_rate_get(qpcs); ++} ++ ++/* Return clock rate for the TX clock supplied to NSSCC ++ * as per the interface mode. ++ */ ++static unsigned long ipq_pcs_tx_clk_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct ipq_pcs *qpcs = container_of(hw, struct ipq_pcs, tx_hw); ++ ++ return ipq_pcs_clk_rate_get(qpcs); ++} ++ ++static int ipq_pcs_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ switch (req->rate) { ++ case 125000000: ++ case 312500000: ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++/* Clock ops for the RX clock supplied to NSSCC */ ++static const struct clk_ops ipq_pcs_rx_clk_ops = { ++ .determine_rate = ipq_pcs_clk_determine_rate, ++ .recalc_rate = ipq_pcs_rx_clk_recalc_rate, ++}; ++ ++/* Clock ops for the TX clock supplied to NSSCC */ ++static const struct clk_ops ipq_pcs_tx_clk_ops = { ++ .determine_rate = ipq_pcs_clk_determine_rate, ++ .recalc_rate = ipq_pcs_tx_clk_recalc_rate, ++}; ++ ++static struct clk_hw *ipq_pcs_clk_hw_get(struct of_phandle_args *clkspec, ++ void *data) ++{ ++ struct ipq_pcs *qpcs = data; ++ ++ switch (clkspec->args[0]) { ++ case PCS_RX_CLK: ++ return &qpcs->rx_hw; ++ case PCS_TX_CLK: ++ return &qpcs->tx_hw; ++ } ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++/* Register the RX and TX clock which are output from SerDes to ++ * the NSSCC. The NSSCC driver assigns the RX and TX clock as ++ * parent, divides them to generate the MII RX and TX clock to ++ * each MII interface of the PCS as per the link speeds and ++ * interface modes. ++ */ ++static int ipq_pcs_clk_register(struct ipq_pcs *qpcs) ++{ ++ struct clk_init_data init = { }; ++ int ret; ++ ++ init.ops = &ipq_pcs_rx_clk_ops; ++ init.name = devm_kasprintf(qpcs->dev, GFP_KERNEL, "%s::rx_clk", ++ dev_name(qpcs->dev)); ++ if (!init.name) ++ return -ENOMEM; ++ ++ qpcs->rx_hw.init = &init; ++ ret = devm_clk_hw_register(qpcs->dev, &qpcs->rx_hw); ++ if (ret) ++ return ret; ++ ++ init.ops = &ipq_pcs_tx_clk_ops; ++ init.name = devm_kasprintf(qpcs->dev, GFP_KERNEL, "%s::tx_clk", ++ dev_name(qpcs->dev)); ++ if (!init.name) ++ return -ENOMEM; ++ ++ qpcs->tx_hw.init = &init; ++ ret = devm_clk_hw_register(qpcs->dev, &qpcs->tx_hw); ++ if (ret) ++ return ret; ++ ++ return devm_of_clk_add_hw_provider(qpcs->dev, ipq_pcs_clk_hw_get, qpcs); ++} ++ ++static int ipq_pcs_regmap_read(void *context, unsigned int reg, ++ unsigned int *val) ++{ ++ struct ipq_pcs *qpcs = context; ++ ++ /* PCS uses direct AHB access while XPCS uses indirect AHB access */ ++ if (reg >= XPCS_INDIRECT_ADDR) { ++ writel(FIELD_GET(XPCS_INDIRECT_ADDR_H, reg), ++ qpcs->base + XPCS_INDIRECT_AHB_ADDR); ++ *val = readl(qpcs->base + XPCS_INDIRECT_DATA_ADDR(reg)); ++ } else { ++ *val = readl(qpcs->base + reg); ++ } ++ ++ return 0; ++} ++ ++static int ipq_pcs_regmap_write(void *context, unsigned int reg, ++ unsigned int val) ++{ ++ struct ipq_pcs *qpcs = context; ++ ++ /* PCS uses direct AHB access while XPCS uses indirect AHB access */ ++ if (reg >= XPCS_INDIRECT_ADDR) { ++ writel(FIELD_GET(XPCS_INDIRECT_ADDR_H, reg), ++ qpcs->base + XPCS_INDIRECT_AHB_ADDR); ++ writel(val, qpcs->base + XPCS_INDIRECT_DATA_ADDR(reg)); ++ } else { ++ writel(val, qpcs->base + reg); ++ } ++ ++ return 0; ++} ++ ++static const struct regmap_config ipq_pcs_regmap_cfg = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_read = ipq_pcs_regmap_read, ++ .reg_write = ipq_pcs_regmap_write, ++ .fast_io = true, ++}; ++ ++static int ipq9574_pcs_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ipq_pcs *qpcs; ++ struct clk *clk; ++ int ret; ++ ++ qpcs = devm_kzalloc(dev, sizeof(*qpcs), GFP_KERNEL); ++ if (!qpcs) ++ return -ENOMEM; ++ ++ qpcs->dev = dev; ++ ++ qpcs->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(qpcs->base)) ++ return dev_err_probe(dev, PTR_ERR(qpcs->base), ++ "Failed to ioremap resource\n"); ++ ++ qpcs->regmap = devm_regmap_init(dev, NULL, qpcs, &ipq_pcs_regmap_cfg); ++ if (IS_ERR(qpcs->regmap)) ++ return dev_err_probe(dev, PTR_ERR(qpcs->regmap), ++ "Failed to allocate register map\n"); ++ ++ clk = devm_clk_get_enabled(dev, "sys"); ++ if (IS_ERR(clk)) ++ return dev_err_probe(dev, PTR_ERR(clk), ++ "Failed to enable SYS clock\n"); ++ ++ clk = devm_clk_get_enabled(dev, "ahb"); ++ if (IS_ERR(clk)) ++ return dev_err_probe(dev, PTR_ERR(clk), ++ "Failed to enable AHB clock\n"); ++ ++ ret = ipq_pcs_clk_register(qpcs); ++ if (ret) ++ return ret; ++ ++ platform_set_drvdata(pdev, qpcs); ++ ++ return 0; ++} ++ ++static const struct of_device_id ipq9574_pcs_of_mtable[] = { ++ { .compatible = "qcom,ipq9574-pcs" }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, ipq9574_pcs_of_mtable); ++ ++static struct platform_driver ipq9574_pcs_driver = { ++ .driver = { ++ .name = "ipq9574_pcs", ++ .suppress_bind_attrs = true, ++ .of_match_table = ipq9574_pcs_of_mtable, ++ }, ++ .probe = ipq9574_pcs_probe, ++}; ++module_platform_driver(ipq9574_pcs_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Qualcomm IPQ9574 PCS driver"); ++MODULE_AUTHOR("Lei Wei "); diff --git a/target/linux/qualcommbe/patches-6.12/0316-net-pcs-qcom-ipq9574-Add-PCS-instantiation-and-phyli.patch b/target/linux/qualcommbe/patches-6.12/0316-net-pcs-qcom-ipq9574-Add-PCS-instantiation-and-phyli.patch new file mode 100644 index 0000000000..1e7453a35c --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0316-net-pcs-qcom-ipq9574-Add-PCS-instantiation-and-phyli.patch @@ -0,0 +1,554 @@ +From 240ae5e0ca2ed858e25d7da6d5291d9c1f2c660a Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Fri, 7 Feb 2025 23:53:14 +0800 +Subject: [PATCH] net: pcs: qcom-ipq9574: Add PCS instantiation and phylink + operations + +This patch adds the following PCS functionality for the PCS driver +for IPQ9574 SoC: + +a.) Parses PCS MII DT nodes and instantiate each MII PCS instance. +b.) Exports PCS instance get and put APIs. The network driver calls +the PCS get API to get and associate the PCS instance with the port +MAC. +c.) PCS phylink operations for SGMII/QSGMII interface modes. + +Signed-off-by: Lei Wei +--- + drivers/net/pcs/pcs-qcom-ipq9574.c | 469 +++++++++++++++++++++++++++ + include/linux/pcs/pcs-qcom-ipq9574.h | 15 + + 2 files changed, 484 insertions(+) + create mode 100644 include/linux/pcs/pcs-qcom-ipq9574.h + +--- a/drivers/net/pcs/pcs-qcom-ipq9574.c ++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c +@@ -6,12 +6,46 @@ + #include + #include + #include ++#include ++#include ++#include + #include ++#include + #include + #include + + #include + ++/* Maximum number of MIIs per PCS instance. There are 5 MIIs for PSGMII. */ ++#define PCS_MAX_MII_NRS 5 ++ ++#define PCS_CALIBRATION 0x1e0 ++#define PCS_CALIBRATION_DONE BIT(7) ++ ++#define PCS_MODE_CTRL 0x46c ++#define PCS_MODE_SEL_MASK GENMASK(12, 8) ++#define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4) ++#define PCS_MODE_QSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x1) ++ ++#define PCS_MII_CTRL(x) (0x480 + 0x18 * (x)) ++#define PCS_MII_ADPT_RESET BIT(11) ++#define PCS_MII_FORCE_MODE BIT(3) ++#define PCS_MII_SPEED_MASK GENMASK(2, 1) ++#define PCS_MII_SPEED_1000 FIELD_PREP(PCS_MII_SPEED_MASK, 0x2) ++#define PCS_MII_SPEED_100 FIELD_PREP(PCS_MII_SPEED_MASK, 0x1) ++#define PCS_MII_SPEED_10 FIELD_PREP(PCS_MII_SPEED_MASK, 0x0) ++ ++#define PCS_MII_STS(x) (0x488 + 0x18 * (x)) ++#define PCS_MII_LINK_STS BIT(7) ++#define PCS_MII_STS_DUPLEX_FULL BIT(6) ++#define PCS_MII_STS_SPEED_MASK GENMASK(5, 4) ++#define PCS_MII_STS_SPEED_10 0 ++#define PCS_MII_STS_SPEED_100 1 ++#define PCS_MII_STS_SPEED_1000 2 ++ ++#define PCS_PLL_RESET 0x780 ++#define PCS_ANA_SW_RESET BIT(6) ++ + #define XPCS_INDIRECT_ADDR 0x8000 + #define XPCS_INDIRECT_AHB_ADDR 0x83fc + #define XPCS_INDIRECT_ADDR_H GENMASK(20, 8) +@@ -20,6 +54,18 @@ + FIELD_PREP(GENMASK(9, 2), \ + FIELD_GET(XPCS_INDIRECT_ADDR_L, reg))) + ++/* Per PCS MII private data */ ++struct ipq_pcs_mii { ++ struct ipq_pcs *qpcs; ++ struct phylink_pcs pcs; ++ int index; ++ ++ /* RX clock from NSSCC to PCS MII */ ++ struct clk *rx_clk; ++ /* TX clock from NSSCC to PCS MII */ ++ struct clk *tx_clk; ++}; ++ + /* PCS private data */ + struct ipq_pcs { + struct device *dev; +@@ -31,8 +77,359 @@ struct ipq_pcs { + struct clk_hw rx_hw; + /* TX clock supplied to NSSCC */ + struct clk_hw tx_hw; ++ ++ struct ipq_pcs_mii *qpcs_mii[PCS_MAX_MII_NRS]; + }; + ++#define phylink_pcs_to_qpcs_mii(_pcs) \ ++ container_of(_pcs, struct ipq_pcs_mii, pcs) ++ ++static void ipq_pcs_get_state_sgmii(struct ipq_pcs *qpcs, ++ int index, ++ struct phylink_link_state *state) ++{ ++ unsigned int val; ++ int ret; ++ ++ ret = regmap_read(qpcs->regmap, PCS_MII_STS(index), &val); ++ if (ret) { ++ state->link = 0; ++ return; ++ } ++ ++ state->link = !!(val & PCS_MII_LINK_STS); ++ ++ if (!state->link) ++ return; ++ ++ switch (FIELD_GET(PCS_MII_STS_SPEED_MASK, val)) { ++ case PCS_MII_STS_SPEED_1000: ++ state->speed = SPEED_1000; ++ break; ++ case PCS_MII_STS_SPEED_100: ++ state->speed = SPEED_100; ++ break; ++ case PCS_MII_STS_SPEED_10: ++ state->speed = SPEED_10; ++ break; ++ default: ++ state->link = false; ++ return; ++ } ++ ++ if (val & PCS_MII_STS_DUPLEX_FULL) ++ state->duplex = DUPLEX_FULL; ++ else ++ state->duplex = DUPLEX_HALF; ++} ++ ++static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, ++ phy_interface_t interface) ++{ ++ unsigned int val; ++ int ret; ++ ++ /* Configure PCS interface mode */ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_SGMII: ++ val = PCS_MODE_SGMII; ++ break; ++ case PHY_INTERFACE_MODE_QSGMII: ++ val = PCS_MODE_QSGMII; ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ ret = regmap_update_bits(qpcs->regmap, PCS_MODE_CTRL, ++ PCS_MODE_SEL_MASK, val); ++ if (ret) ++ return ret; ++ ++ /* PCS PLL reset */ ++ ret = regmap_clear_bits(qpcs->regmap, PCS_PLL_RESET, PCS_ANA_SW_RESET); ++ if (ret) ++ return ret; ++ ++ fsleep(1000); ++ ret = regmap_set_bits(qpcs->regmap, PCS_PLL_RESET, PCS_ANA_SW_RESET); ++ if (ret) ++ return ret; ++ ++ /* Wait for calibration completion */ ++ ret = regmap_read_poll_timeout(qpcs->regmap, PCS_CALIBRATION, ++ val, val & PCS_CALIBRATION_DONE, ++ 1000, 100000); ++ if (ret) { ++ dev_err(qpcs->dev, "PCS calibration timed-out\n"); ++ return ret; ++ } ++ ++ qpcs->interface = interface; ++ ++ return 0; ++} ++ ++static int ipq_pcs_config_sgmii(struct ipq_pcs *qpcs, ++ int index, ++ unsigned int neg_mode, ++ phy_interface_t interface) ++{ ++ int ret; ++ ++ /* Configure the PCS mode if required */ ++ if (qpcs->interface != interface) { ++ ret = ipq_pcs_config_mode(qpcs, interface); ++ if (ret) ++ return ret; ++ } ++ ++ /* Nothing to do here as in-band autoneg mode is enabled ++ * by default for each PCS MII port. ++ */ ++ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) ++ return 0; ++ ++ /* Set force speed mode */ ++ return regmap_set_bits(qpcs->regmap, ++ PCS_MII_CTRL(index), PCS_MII_FORCE_MODE); ++} ++ ++static int ipq_pcs_link_up_config_sgmii(struct ipq_pcs *qpcs, ++ int index, ++ unsigned int neg_mode, ++ int speed) ++{ ++ unsigned int val; ++ int ret; ++ ++ /* PCS speed need not be configured if in-band autoneg is enabled */ ++ if (neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) { ++ /* PCS speed set for force mode */ ++ switch (speed) { ++ case SPEED_1000: ++ val = PCS_MII_SPEED_1000; ++ break; ++ case SPEED_100: ++ val = PCS_MII_SPEED_100; ++ break; ++ case SPEED_10: ++ val = PCS_MII_SPEED_10; ++ break; ++ default: ++ dev_err(qpcs->dev, "Invalid SGMII speed %d\n", speed); ++ return -EINVAL; ++ } ++ ++ ret = regmap_update_bits(qpcs->regmap, PCS_MII_CTRL(index), ++ PCS_MII_SPEED_MASK, val); ++ if (ret) ++ return ret; ++ } ++ ++ /* PCS adapter reset */ ++ ret = regmap_clear_bits(qpcs->regmap, ++ PCS_MII_CTRL(index), PCS_MII_ADPT_RESET); ++ if (ret) ++ return ret; ++ ++ return regmap_set_bits(qpcs->regmap, ++ PCS_MII_CTRL(index), PCS_MII_ADPT_RESET); ++} ++ ++static int ipq_pcs_validate(struct phylink_pcs *pcs, unsigned long *supported, ++ const struct phylink_link_state *state) ++{ ++ switch (state->interface) { ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_QSGMII: ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static unsigned int ipq_pcs_inband_caps(struct phylink_pcs *pcs, ++ phy_interface_t interface) ++{ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_QSGMII: ++ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; ++ default: ++ return 0; ++ } ++} ++ ++static int ipq_pcs_enable(struct phylink_pcs *pcs) ++{ ++ struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); ++ struct ipq_pcs *qpcs = qpcs_mii->qpcs; ++ int index = qpcs_mii->index; ++ int ret; ++ ++ ret = clk_prepare_enable(qpcs_mii->rx_clk); ++ if (ret) { ++ dev_err(qpcs->dev, "Failed to enable MII %d RX clock\n", index); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(qpcs_mii->tx_clk); ++ if (ret) { ++ /* This is a fatal event since phylink does not support unwinding ++ * the state back for this error. So, we only report the error ++ * and do not disable the clocks. ++ */ ++ dev_err(qpcs->dev, "Failed to enable MII %d TX clock\n", index); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void ipq_pcs_disable(struct phylink_pcs *pcs) ++{ ++ struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); ++ ++ clk_disable_unprepare(qpcs_mii->rx_clk); ++ clk_disable_unprepare(qpcs_mii->tx_clk); ++} ++ ++static void ipq_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, ++ struct phylink_link_state *state) ++{ ++ struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); ++ struct ipq_pcs *qpcs = qpcs_mii->qpcs; ++ int index = qpcs_mii->index; ++ ++ switch (state->interface) { ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_QSGMII: ++ ipq_pcs_get_state_sgmii(qpcs, index, state); ++ break; ++ default: ++ break; ++ } ++ ++ dev_dbg_ratelimited(qpcs->dev, ++ "mode=%s/%s/%s link=%u\n", ++ phy_modes(state->interface), ++ phy_speed_to_str(state->speed), ++ phy_duplex_to_str(state->duplex), ++ state->link); ++} ++ ++static int ipq_pcs_config(struct phylink_pcs *pcs, ++ unsigned int neg_mode, ++ phy_interface_t interface, ++ const unsigned long *advertising, ++ bool permit) ++{ ++ struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); ++ struct ipq_pcs *qpcs = qpcs_mii->qpcs; ++ int index = qpcs_mii->index; ++ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_QSGMII: ++ return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface); ++ default: ++ return -EOPNOTSUPP; ++ }; ++} ++ ++static void ipq_pcs_link_up(struct phylink_pcs *pcs, ++ unsigned int neg_mode, ++ phy_interface_t interface, ++ int speed, int duplex) ++{ ++ struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); ++ struct ipq_pcs *qpcs = qpcs_mii->qpcs; ++ int index = qpcs_mii->index; ++ int ret; ++ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_QSGMII: ++ ret = ipq_pcs_link_up_config_sgmii(qpcs, index, ++ neg_mode, speed); ++ break; ++ default: ++ return; ++ } ++ ++ if (ret) ++ dev_err(qpcs->dev, "PCS link up fail for interface %s\n", ++ phy_modes(interface)); ++} ++ ++static const struct phylink_pcs_ops ipq_pcs_phylink_ops = { ++ .pcs_validate = ipq_pcs_validate, ++ .pcs_inband_caps = ipq_pcs_inband_caps, ++ .pcs_enable = ipq_pcs_enable, ++ .pcs_disable = ipq_pcs_disable, ++ .pcs_get_state = ipq_pcs_get_state, ++ .pcs_config = ipq_pcs_config, ++ .pcs_link_up = ipq_pcs_link_up, ++}; ++ ++/* Parse the PCS MII DT nodes which are child nodes of the PCS node, ++ * and instantiate each MII PCS instance. ++ */ ++static int ipq_pcs_create_miis(struct ipq_pcs *qpcs) ++{ ++ struct device *dev = qpcs->dev; ++ struct ipq_pcs_mii *qpcs_mii; ++ struct device_node *mii_np; ++ u32 index; ++ int ret; ++ ++ for_each_available_child_of_node(dev->of_node, mii_np) { ++ ret = of_property_read_u32(mii_np, "reg", &index); ++ if (ret) { ++ dev_err(dev, "Failed to read MII index\n"); ++ of_node_put(mii_np); ++ return ret; ++ } ++ ++ if (index >= PCS_MAX_MII_NRS) { ++ dev_err(dev, "Invalid MII index\n"); ++ of_node_put(mii_np); ++ return -EINVAL; ++ } ++ ++ qpcs_mii = devm_kzalloc(dev, sizeof(*qpcs_mii), GFP_KERNEL); ++ if (!qpcs_mii) { ++ of_node_put(mii_np); ++ return -ENOMEM; ++ } ++ ++ qpcs_mii->qpcs = qpcs; ++ qpcs_mii->index = index; ++ qpcs_mii->pcs.ops = &ipq_pcs_phylink_ops; ++ qpcs_mii->pcs.neg_mode = true; ++ qpcs_mii->pcs.poll = true; ++ ++ qpcs_mii->rx_clk = devm_get_clk_from_child(dev, mii_np, "rx"); ++ if (IS_ERR(qpcs_mii->rx_clk)) { ++ of_node_put(mii_np); ++ return dev_err_probe(dev, PTR_ERR(qpcs_mii->rx_clk), ++ "Failed to get MII %d RX clock\n", index); ++ } ++ ++ qpcs_mii->tx_clk = devm_get_clk_from_child(dev, mii_np, "tx"); ++ if (IS_ERR(qpcs_mii->tx_clk)) { ++ of_node_put(mii_np); ++ return dev_err_probe(dev, PTR_ERR(qpcs_mii->tx_clk), ++ "Failed to get MII %d TX clock\n", index); ++ } ++ ++ qpcs->qpcs_mii[index] = qpcs_mii; ++ } ++ ++ return 0; ++} ++ + static unsigned long ipq_pcs_clk_rate_get(struct ipq_pcs *qpcs) + { + switch (qpcs->interface) { +@@ -219,6 +616,10 @@ static int ipq9574_pcs_probe(struct plat + if (ret) + return ret; + ++ ret = ipq_pcs_create_miis(qpcs); ++ if (ret) ++ return ret; ++ + platform_set_drvdata(pdev, qpcs); + + return 0; +@@ -230,6 +631,74 @@ static const struct of_device_id ipq9574 + }; + MODULE_DEVICE_TABLE(of, ipq9574_pcs_of_mtable); + ++/** ++ * ipq_pcs_get() - Get the IPQ PCS MII instance ++ * @np: Device tree node to the PCS MII ++ * ++ * Description: Get the phylink PCS instance for the given PCS MII node @np. ++ * This instance is associated with the specific MII of the PCS and the ++ * corresponding Ethernet netdevice. ++ * ++ * Return: A pointer to the phylink PCS instance or an error-pointer value. ++ */ ++struct phylink_pcs *ipq_pcs_get(struct device_node *np) ++{ ++ struct platform_device *pdev; ++ struct ipq_pcs_mii *qpcs_mii; ++ struct ipq_pcs *qpcs; ++ u32 index; ++ ++ if (of_property_read_u32(np, "reg", &index)) ++ return ERR_PTR(-EINVAL); ++ ++ if (index >= PCS_MAX_MII_NRS) ++ return ERR_PTR(-EINVAL); ++ ++ if (!of_match_node(ipq9574_pcs_of_mtable, np->parent)) ++ return ERR_PTR(-EINVAL); ++ ++ /* Get the parent device */ ++ pdev = of_find_device_by_node(np->parent); ++ if (!pdev) ++ return ERR_PTR(-ENODEV); ++ ++ qpcs = platform_get_drvdata(pdev); ++ if (!qpcs) { ++ put_device(&pdev->dev); ++ ++ /* If probe is not yet completed, return DEFER to ++ * the dependent driver. ++ */ ++ return ERR_PTR(-EPROBE_DEFER); ++ } ++ ++ qpcs_mii = qpcs->qpcs_mii[index]; ++ if (!qpcs_mii) { ++ put_device(&pdev->dev); ++ return ERR_PTR(-ENOENT); ++ } ++ ++ return &qpcs_mii->pcs; ++} ++EXPORT_SYMBOL(ipq_pcs_get); ++ ++/** ++ * ipq_pcs_put() - Release the IPQ PCS MII instance ++ * @pcs: PCS instance ++ * ++ * Description: Release a phylink PCS instance. ++ */ ++void ipq_pcs_put(struct phylink_pcs *pcs) ++{ ++ struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); ++ ++ /* Put reference taken by of_find_device_by_node() in ++ * ipq_pcs_get(). ++ */ ++ put_device(qpcs_mii->qpcs->dev); ++} ++EXPORT_SYMBOL(ipq_pcs_put); ++ + static struct platform_driver ipq9574_pcs_driver = { + .driver = { + .name = "ipq9574_pcs", +--- /dev/null ++++ b/include/linux/pcs/pcs-qcom-ipq9574.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#ifndef __LINUX_PCS_QCOM_IPQ9574_H ++#define __LINUX_PCS_QCOM_IPQ9574_H ++ ++struct device_node; ++struct phylink_pcs; ++ ++struct phylink_pcs *ipq_pcs_get(struct device_node *np); ++void ipq_pcs_put(struct phylink_pcs *pcs); ++ ++#endif /* __LINUX_PCS_QCOM_IPQ9574_H */ diff --git a/target/linux/qualcommbe/patches-6.12/0317-net-pcs-qcom-ipq9574-Add-USXGMII-interface-mode-supp.patch b/target/linux/qualcommbe/patches-6.12/0317-net-pcs-qcom-ipq9574-Add-USXGMII-interface-mode-supp.patch new file mode 100644 index 0000000000..b1cddffc6a --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0317-net-pcs-qcom-ipq9574-Add-USXGMII-interface-mode-supp.patch @@ -0,0 +1,272 @@ +From 4923ca63214a4e6bbee1b3f8f6b9b79f0fd3a3be Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Fri, 7 Feb 2025 23:53:15 +0800 +Subject: [PATCH] net: pcs: qcom-ipq9574: Add USXGMII interface mode support + +USXGMII mode is enabled by PCS when 10Gbps PHYs are connected, such as +Aquantia 10Gbps PHY. + +Signed-off-by: Lei Wei +--- + drivers/net/pcs/pcs-qcom-ipq9574.c | 170 +++++++++++++++++++++++++++++ + 1 file changed, 170 insertions(+) + +--- a/drivers/net/pcs/pcs-qcom-ipq9574.c ++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c +@@ -26,6 +26,7 @@ + #define PCS_MODE_SEL_MASK GENMASK(12, 8) + #define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4) + #define PCS_MODE_QSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x1) ++#define PCS_MODE_XPCS FIELD_PREP(PCS_MODE_SEL_MASK, 0x10) + + #define PCS_MII_CTRL(x) (0x480 + 0x18 * (x)) + #define PCS_MII_ADPT_RESET BIT(11) +@@ -54,6 +55,34 @@ + FIELD_PREP(GENMASK(9, 2), \ + FIELD_GET(XPCS_INDIRECT_ADDR_L, reg))) + ++#define XPCS_DIG_CTRL 0x38000 ++#define XPCS_USXG_ADPT_RESET BIT(10) ++#define XPCS_USXG_EN BIT(9) ++ ++#define XPCS_MII_CTRL 0x1f0000 ++#define XPCS_MII_AN_EN BIT(12) ++#define XPCS_DUPLEX_FULL BIT(8) ++#define XPCS_SPEED_MASK (BIT(13) | BIT(6) | BIT(5)) ++#define XPCS_SPEED_10000 (BIT(13) | BIT(6)) ++#define XPCS_SPEED_5000 (BIT(13) | BIT(5)) ++#define XPCS_SPEED_2500 BIT(5) ++#define XPCS_SPEED_1000 BIT(6) ++#define XPCS_SPEED_100 BIT(13) ++#define XPCS_SPEED_10 0 ++ ++#define XPCS_MII_AN_CTRL 0x1f8001 ++#define XPCS_MII_AN_8BIT BIT(8) ++ ++#define XPCS_MII_AN_INTR_STS 0x1f8002 ++#define XPCS_USXG_AN_LINK_STS BIT(14) ++#define XPCS_USXG_AN_SPEED_MASK GENMASK(12, 10) ++#define XPCS_USXG_AN_SPEED_10 0 ++#define XPCS_USXG_AN_SPEED_100 1 ++#define XPCS_USXG_AN_SPEED_1000 2 ++#define XPCS_USXG_AN_SPEED_2500 4 ++#define XPCS_USXG_AN_SPEED_5000 5 ++#define XPCS_USXG_AN_SPEED_10000 3 ++ + /* Per PCS MII private data */ + struct ipq_pcs_mii { + struct ipq_pcs *qpcs; +@@ -123,9 +152,54 @@ static void ipq_pcs_get_state_sgmii(stru + state->duplex = DUPLEX_HALF; + } + ++static void ipq_pcs_get_state_usxgmii(struct ipq_pcs *qpcs, ++ struct phylink_link_state *state) ++{ ++ unsigned int val; ++ int ret; ++ ++ ret = regmap_read(qpcs->regmap, XPCS_MII_AN_INTR_STS, &val); ++ if (ret) { ++ state->link = 0; ++ return; ++ } ++ ++ state->link = !!(val & XPCS_USXG_AN_LINK_STS); ++ ++ if (!state->link) ++ return; ++ ++ switch (FIELD_GET(XPCS_USXG_AN_SPEED_MASK, val)) { ++ case XPCS_USXG_AN_SPEED_10000: ++ state->speed = SPEED_10000; ++ break; ++ case XPCS_USXG_AN_SPEED_5000: ++ state->speed = SPEED_5000; ++ break; ++ case XPCS_USXG_AN_SPEED_2500: ++ state->speed = SPEED_2500; ++ break; ++ case XPCS_USXG_AN_SPEED_1000: ++ state->speed = SPEED_1000; ++ break; ++ case XPCS_USXG_AN_SPEED_100: ++ state->speed = SPEED_100; ++ break; ++ case XPCS_USXG_AN_SPEED_10: ++ state->speed = SPEED_10; ++ break; ++ default: ++ state->link = false; ++ return; ++ } ++ ++ state->duplex = DUPLEX_FULL; ++} ++ + static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, + phy_interface_t interface) + { ++ unsigned long rate = 125000000; + unsigned int val; + int ret; + +@@ -137,6 +211,10 @@ static int ipq_pcs_config_mode(struct ip + case PHY_INTERFACE_MODE_QSGMII: + val = PCS_MODE_QSGMII; + break; ++ case PHY_INTERFACE_MODE_USXGMII: ++ val = PCS_MODE_XPCS; ++ rate = 312500000; ++ break; + default: + return -EOPNOTSUPP; + } +@@ -167,6 +245,21 @@ static int ipq_pcs_config_mode(struct ip + + qpcs->interface = interface; + ++ /* Configure the RX and TX clock to NSSCC as 125M or 312.5M based ++ * on current interface mode. ++ */ ++ ret = clk_set_rate(qpcs->rx_hw.clk, rate); ++ if (ret) { ++ dev_err(qpcs->dev, "Failed to set RX clock rate\n"); ++ return ret; ++ } ++ ++ ret = clk_set_rate(qpcs->tx_hw.clk, rate); ++ if (ret) { ++ dev_err(qpcs->dev, "Failed to set TX clock rate\n"); ++ return ret; ++ } ++ + return 0; + } + +@@ -195,6 +288,29 @@ static int ipq_pcs_config_sgmii(struct i + PCS_MII_CTRL(index), PCS_MII_FORCE_MODE); + } + ++static int ipq_pcs_config_usxgmii(struct ipq_pcs *qpcs) ++{ ++ int ret; ++ ++ /* Configure the XPCS for USXGMII mode if required */ ++ if (qpcs->interface == PHY_INTERFACE_MODE_USXGMII) ++ return 0; ++ ++ ret = ipq_pcs_config_mode(qpcs, PHY_INTERFACE_MODE_USXGMII); ++ if (ret) ++ return ret; ++ ++ ret = regmap_set_bits(qpcs->regmap, XPCS_DIG_CTRL, XPCS_USXG_EN); ++ if (ret) ++ return ret; ++ ++ ret = regmap_set_bits(qpcs->regmap, XPCS_MII_AN_CTRL, XPCS_MII_AN_8BIT); ++ if (ret) ++ return ret; ++ ++ return regmap_set_bits(qpcs->regmap, XPCS_MII_CTRL, XPCS_MII_AN_EN); ++} ++ + static int ipq_pcs_link_up_config_sgmii(struct ipq_pcs *qpcs, + int index, + unsigned int neg_mode, +@@ -237,6 +353,46 @@ static int ipq_pcs_link_up_config_sgmii( + PCS_MII_CTRL(index), PCS_MII_ADPT_RESET); + } + ++static int ipq_pcs_link_up_config_usxgmii(struct ipq_pcs *qpcs, int speed) ++{ ++ unsigned int val; ++ int ret; ++ ++ switch (speed) { ++ case SPEED_10000: ++ val = XPCS_SPEED_10000; ++ break; ++ case SPEED_5000: ++ val = XPCS_SPEED_5000; ++ break; ++ case SPEED_2500: ++ val = XPCS_SPEED_2500; ++ break; ++ case SPEED_1000: ++ val = XPCS_SPEED_1000; ++ break; ++ case SPEED_100: ++ val = XPCS_SPEED_100; ++ break; ++ case SPEED_10: ++ val = XPCS_SPEED_10; ++ break; ++ default: ++ dev_err(qpcs->dev, "Invalid USXGMII speed %d\n", speed); ++ return -EINVAL; ++ } ++ ++ /* Configure XPCS speed */ ++ ret = regmap_update_bits(qpcs->regmap, XPCS_MII_CTRL, ++ XPCS_SPEED_MASK, val | XPCS_DUPLEX_FULL); ++ if (ret) ++ return ret; ++ ++ /* XPCS adapter reset */ ++ return regmap_set_bits(qpcs->regmap, ++ XPCS_DIG_CTRL, XPCS_USXG_ADPT_RESET); ++} ++ + static int ipq_pcs_validate(struct phylink_pcs *pcs, unsigned long *supported, + const struct phylink_link_state *state) + { +@@ -244,6 +400,11 @@ static int ipq_pcs_validate(struct phyli + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + return 0; ++ case PHY_INTERFACE_MODE_USXGMII: ++ /* USXGMII only supports full duplex mode */ ++ phylink_clear(supported, 100baseT_Half); ++ phylink_clear(supported, 10baseT_Half); ++ return 0; + default: + return -EINVAL; + } +@@ -255,6 +416,7 @@ static unsigned int ipq_pcs_inband_caps( + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: ++ case PHY_INTERFACE_MODE_USXGMII: + return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; + default: + return 0; +@@ -307,6 +469,9 @@ static void ipq_pcs_get_state(struct phy + case PHY_INTERFACE_MODE_QSGMII: + ipq_pcs_get_state_sgmii(qpcs, index, state); + break; ++ case PHY_INTERFACE_MODE_USXGMII: ++ ipq_pcs_get_state_usxgmii(qpcs, state); ++ break; + default: + break; + } +@@ -333,6 +498,8 @@ static int ipq_pcs_config(struct phylink + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface); ++ case PHY_INTERFACE_MODE_USXGMII: ++ return ipq_pcs_config_usxgmii(qpcs); + default: + return -EOPNOTSUPP; + }; +@@ -354,6 +521,9 @@ static void ipq_pcs_link_up(struct phyli + ret = ipq_pcs_link_up_config_sgmii(qpcs, index, + neg_mode, speed); + break; ++ case PHY_INTERFACE_MODE_USXGMII: ++ ret = ipq_pcs_link_up_config_usxgmii(qpcs, speed); ++ break; + default: + return; + } diff --git a/target/linux/qualcommbe/patches-6.12/0318-MAINTAINERS-Add-maintainer-for-Qualcomm-IPQ9574-PCS-.patch b/target/linux/qualcommbe/patches-6.12/0318-MAINTAINERS-Add-maintainer-for-Qualcomm-IPQ9574-PCS-.patch new file mode 100644 index 0000000000..8c90f9fbb8 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0318-MAINTAINERS-Add-maintainer-for-Qualcomm-IPQ9574-PCS-.patch @@ -0,0 +1,31 @@ +From 34d10a4eb8fea32bb79e3012dc9d8bd2dffb0df3 Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Fri, 7 Feb 2025 23:53:16 +0800 +Subject: [PATCH] MAINTAINERS: Add maintainer for Qualcomm IPQ9574 PCS driver + +Add maintainer for the Ethernet PCS driver supported for Qualcomm +IPQ9574 SoC. + +Signed-off-by: Lei Wei +--- + MAINTAINERS | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -19114,6 +19114,15 @@ S: Maintained + F: Documentation/devicetree/bindings/regulator/vqmmc-ipq4019-regulator.yaml + F: drivers/regulator/vqmmc-ipq4019-regulator.c + ++QUALCOMM IPQ9574 Ethernet PCS DRIVER ++M: Lei Wei ++L: netdev@vger.kernel.org ++S: Supported ++F: Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml ++F: drivers/net/pcs/pcs-qcom-ipq9574.c ++F: include/dt-bindings/net/qcom,ipq9574-pcs.h ++F: include/linux/pcs/pcs-qcom-ipq9574.h ++ + QUALCOMM NAND CONTROLLER DRIVER + M: Manivannan Sadhasivam + L: linux-mtd@lists.infradead.org diff --git a/target/linux/qualcommbe/patches-6.12/0319-net-pcs-qcom-ipq9574-remove-neg_mode-argument-from-i.patch b/target/linux/qualcommbe/patches-6.12/0319-net-pcs-qcom-ipq9574-remove-neg_mode-argument-from-i.patch new file mode 100644 index 0000000000..6fc9652f08 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0319-net-pcs-qcom-ipq9574-remove-neg_mode-argument-from-i.patch @@ -0,0 +1,29 @@ +From ffe2a80fb76ccdc1781f817f6bbc9a8aa919816e Mon Sep 17 00:00:00 2001 +From: Alexandru Gagniuc +Date: Mon, 12 May 2025 09:11:05 -0500 +Subject: [PATCH] net: pcs: qcom-ipq9574: remove "neg_mode" argument from + ipq_pcs_get_state + +Since commit c6739623c91bb ("net: phylink: pass neg_mode into +.pcs_get_state() method"), the "neg_mode" parameter is part of the +argument list of .pcs_get_state(). This is available starting with +v6.14. However, we want to use the backported IPQ9574 driver on v6.12. +Remove this parameter from ipq_pcs_get_state(), as it is not part of +.pcs_get_state() in v6.12. + +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/pcs/pcs-qcom-ipq9574.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/pcs/pcs-qcom-ipq9574.c ++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c +@@ -457,7 +457,7 @@ static void ipq_pcs_disable(struct phyli + clk_disable_unprepare(qpcs_mii->tx_clk); + } + +-static void ipq_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, ++static void ipq_pcs_get_state(struct phylink_pcs *pcs, + struct phylink_link_state *state) + { + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); diff --git a/target/linux/qualcommbe/patches-6.12/0320-net-pcs-qcom-ipq9574-delay-mii-clock-probing-until-i.patch b/target/linux/qualcommbe/patches-6.12/0320-net-pcs-qcom-ipq9574-delay-mii-clock-probing-until-i.patch new file mode 100644 index 0000000000..ac4c44a720 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0320-net-pcs-qcom-ipq9574-delay-mii-clock-probing-until-i.patch @@ -0,0 +1,82 @@ +From 5b2f02ccca7b9496f0a8da6ade063b82810c75e7 Mon Sep 17 00:00:00 2001 +From: Alexandru Gagniuc +Date: Mon, 12 May 2025 09:27:17 -0500 +Subject: [PATCH] net: pcs: qcom-ipq9574: delay mii clock probing until + ipq_pcs_get() + +NSSCC generates the SYS and AHB clocks for the PCS block The PCS then +feeds the uniphy clocks back to the NSSCC, which are in turn, used to +feed the PCS MII clocks. This works fine in hardware: + + GCC -> NSSCC -> PCS -> NSSCC -> PCS(MII) + +However, when the PCS MII clocks are probed within the .probe() of +the PCS block, it creates a circular dependency. The MII clocks depend +on the uniphy clocks, which depend on the PCS block being probed. +Since we are in the process of probing the PCS block, this results in +both blocks returning with -EPROBE_DEFER: + + platform 39b00000.clock-controller: deferred probe pending: platform: supplier 7a00000.ethernet-pcs not ready + mdio_bus 90000.mdio-1:18: deferred probe pending: mdio_bus: supplier 7a20000.ethernet-pcs not ready + mdio_bus 90000.mdio-1:00: deferred probe pending: mdio_bus: supplier 90000.mdio-1:18 not ready + mdio_bus 90000.mdio-1:01: deferred probe pending: mdio_bus: supplier 90000.mdio-1:18 not ready + mdio_bus 90000.mdio-1:02: deferred probe pending: mdio_bus: supplier 90000.mdio-1:18 not ready + mdio_bus 90000.mdio-1:03: deferred probe pending: mdio_bus: supplier 90000.mdio-1:18 not ready + platform 7a00000.ethernet-pcs: deferred probe pending: ipq9574_pcs: Failed to get MII 0 RX clock + platform 7a20000.ethernet-pcs: deferred probe pending: ipq9574_pcs: Failed to get MII 0 RX clock + platform 3a000000.qcom-ppe: deferred probe pending: platform: supplier 39b00000.clock-controller not ready + +To break this dependency, let the PCS block probe, and only probe the +PCS MII clocks from ipq_pcs_get(). + +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/pcs/pcs-qcom-ipq9574.c | 30 ++++++++++++++++-------------- + 1 file changed, 16 insertions(+), 14 deletions(-) + +--- a/drivers/net/pcs/pcs-qcom-ipq9574.c ++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c +@@ -580,20 +580,6 @@ static int ipq_pcs_create_miis(struct ip + qpcs_mii->pcs.neg_mode = true; + qpcs_mii->pcs.poll = true; + +- qpcs_mii->rx_clk = devm_get_clk_from_child(dev, mii_np, "rx"); +- if (IS_ERR(qpcs_mii->rx_clk)) { +- of_node_put(mii_np); +- return dev_err_probe(dev, PTR_ERR(qpcs_mii->rx_clk), +- "Failed to get MII %d RX clock\n", index); +- } +- +- qpcs_mii->tx_clk = devm_get_clk_from_child(dev, mii_np, "tx"); +- if (IS_ERR(qpcs_mii->tx_clk)) { +- of_node_put(mii_np); +- return dev_err_probe(dev, PTR_ERR(qpcs_mii->tx_clk), +- "Failed to get MII %d TX clock\n", index); +- } +- + qpcs->qpcs_mii[index] = qpcs_mii; + } + +@@ -848,6 +834,22 @@ struct phylink_pcs *ipq_pcs_get(struct d + return ERR_PTR(-ENOENT); + } + ++ qpcs_mii->rx_clk = devm_get_clk_from_child(&pdev->dev, np, "rx"); ++ if (IS_ERR(qpcs_mii->rx_clk)) { ++ put_device(&pdev->dev); ++ return dev_err_ptr_probe(&pdev->dev, PTR_ERR(qpcs_mii->rx_clk), ++ "Failed to get MII %d RX clock\n", ++ index); ++ } ++ ++ qpcs_mii->tx_clk = devm_get_clk_from_child(&pdev->dev, np, "tx"); ++ if (IS_ERR(qpcs_mii->tx_clk)) { ++ put_device(&pdev->dev); ++ return dev_err_ptr_probe(&pdev->dev, PTR_ERR(qpcs_mii->tx_clk), ++ "Failed to get MII %d TX clock\n", ++ index); ++ } ++ + return &qpcs_mii->pcs; + } + EXPORT_SYMBOL(ipq_pcs_get); diff --git a/target/linux/qualcommbe/patches-6.12/0321-net-pcs-qcom-ipq9574-add-changes-not-submitted-upstr.patch b/target/linux/qualcommbe/patches-6.12/0321-net-pcs-qcom-ipq9574-add-changes-not-submitted-upstr.patch new file mode 100644 index 0000000000..64a5bf6229 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0321-net-pcs-qcom-ipq9574-add-changes-not-submitted-upstr.patch @@ -0,0 +1,362 @@ +From 7de372abe7a4b5b380fdbeedd268445f234990c8 Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Mon, 29 Jan 2024 11:39:36 +0800 +Subject: [PATCH] net: pcs: qcom-ipq9574: add changes not submitted upstream + +Was ("net: pcs: Add driver for Qualcomm IPQ UNIPHY PCS"). + +The UNIPHY hardware block in Qualcomm's IPQ SoC based boards enables +PCS and XPCS functions, and helps in interfacing the Ethernet MAC in +IPQ SoC to external PHYs. + +This patch adds the PCS driver support for the UNIPHY hardware used in +IPQ SoC based boards. Support for SGMII/QSGMII/PSGMII and USXGMII +interface modes are added in the driver. + +Change-Id: Id2c8f993f121098f7b02186b53770b75bb539a93 +Signed-off-by: Lei Wei +Alex G: Rebase original patch on top of 20250207 uniphy submission + Remove mutex that is not required according to + https://lore.kernel.org/lkml/Z3ZwURgIErzpzpEr@shell.armlinux.org.uk/ +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/pcs/pcs-qcom-ipq9574.c | 180 +++++++++++++++++++++++- + include/linux/pcs/pcs-qcom-ipq-uniphy.h | 13 ++ + 2 files changed, 192 insertions(+), 1 deletion(-) + create mode 100644 include/linux/pcs/pcs-qcom-ipq-uniphy.h + +--- a/drivers/net/pcs/pcs-qcom-ipq9574.c ++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c +@@ -9,10 +9,12 @@ + #include + #include + #include ++#include + #include + #include + #include + #include ++#include + + #include + +@@ -26,6 +28,7 @@ + #define PCS_MODE_SEL_MASK GENMASK(12, 8) + #define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4) + #define PCS_MODE_QSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x1) ++#define PCS_MODE_PSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x2) + #define PCS_MODE_XPCS FIELD_PREP(PCS_MODE_SEL_MASK, 0x10) + + #define PCS_MII_CTRL(x) (0x480 + 0x18 * (x)) +@@ -43,6 +46,8 @@ + #define PCS_MII_STS_SPEED_10 0 + #define PCS_MII_STS_SPEED_100 1 + #define PCS_MII_STS_SPEED_1000 2 ++#define PCS_MII_STS_PAUSE_TX_EN BIT(1) ++#define PCS_MII_STS_PAUSE_RX_EN BIT(0) + + #define PCS_PLL_RESET 0x780 + #define PCS_ANA_SW_RESET BIT(6) +@@ -95,12 +100,35 @@ struct ipq_pcs_mii { + struct clk *tx_clk; + }; + ++/* UNIPHY PCS reset ID */ ++enum { ++ PCS_SYS_RESET, ++ PCS_AHB_RESET, ++ XPCS_RESET, ++ PCS_RESET_MAX ++}; ++ ++/* UNIPHY PCS reset name */ ++static const char *const pcs_reset_name[PCS_RESET_MAX] = { ++ "sys", ++ "ahb", ++ "xpcs", ++}; ++ ++/* UNIPHY PCS channel clock ID */ ++enum { ++ PCS_CH_RX_CLK, ++ PCS_CH_TX_CLK, ++ PCS_CH_CLK_MAX ++}; ++ + /* PCS private data */ + struct ipq_pcs { + struct device *dev; + void __iomem *base; + struct regmap *regmap; + phy_interface_t interface; ++ struct reset_control *reset[PCS_RESET_MAX]; + + /* RX clock supplied to NSSCC */ + struct clk_hw rx_hw; +@@ -150,6 +178,11 @@ static void ipq_pcs_get_state_sgmii(stru + state->duplex = DUPLEX_FULL; + else + state->duplex = DUPLEX_HALF; ++ ++ if (val & PCS_MII_STS_PAUSE_TX_EN) ++ state->pause |= MLO_PAUSE_TX; ++ if (val & PCS_MII_STS_PAUSE_RX_EN) ++ state->pause |= MLO_PAUSE_RX; + } + + static void ipq_pcs_get_state_usxgmii(struct ipq_pcs *qpcs, +@@ -203,6 +236,9 @@ static int ipq_pcs_config_mode(struct ip + unsigned int val; + int ret; + ++ /* Assert XPCS reset */ ++ reset_control_assert(qpcs->reset[XPCS_RESET]); ++ + /* Configure PCS interface mode */ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: +@@ -211,11 +247,16 @@ static int ipq_pcs_config_mode(struct ip + case PHY_INTERFACE_MODE_QSGMII: + val = PCS_MODE_QSGMII; + break; ++ case PHY_INTERFACE_MODE_PSGMII: ++ val = PCS_MODE_PSGMII; ++ break; + case PHY_INTERFACE_MODE_USXGMII: + val = PCS_MODE_XPCS; + rate = 312500000; + break; + default: ++ dev_err(qpcs->dev, ++ "interface %s not supported\n", phy_modes(interface)); + return -EOPNOTSUPP; + } + +@@ -300,6 +341,9 @@ static int ipq_pcs_config_usxgmii(struct + if (ret) + return ret; + ++ /* Deassert XPCS and configure XPCS USXGMII */ ++ reset_control_deassert(qpcs->reset[XPCS_RESET]); ++ + ret = regmap_set_bits(qpcs->regmap, XPCS_DIG_CTRL, XPCS_USXG_EN); + if (ret) + return ret; +@@ -311,6 +355,91 @@ static int ipq_pcs_config_usxgmii(struct + return regmap_set_bits(qpcs->regmap, XPCS_MII_CTRL, XPCS_MII_AN_EN); + } + ++static unsigned long ipq_unipcs_clock_rate_get_gmii(int speed) ++{ ++ unsigned long rate = 0; ++ ++ switch (speed) { ++ case SPEED_1000: ++ rate = 125000000; ++ break; ++ case SPEED_100: ++ rate = 25000000; ++ break; ++ case SPEED_10: ++ rate = 2500000; ++ break; ++ default: ++ break; ++ } ++ ++ return rate; ++} ++ ++static unsigned long ipq_unipcs_clock_rate_get_xgmii(int speed) ++{ ++ unsigned long rate = 0; ++ ++ switch (speed) { ++ case SPEED_10000: ++ rate = 312500000; ++ break; ++ case SPEED_5000: ++ rate = 156250000; ++ break; ++ case SPEED_2500: ++ rate = 78125000; ++ break; ++ case SPEED_1000: ++ rate = 125000000; ++ break; ++ case SPEED_100: ++ rate = 12500000; ++ break; ++ case SPEED_10: ++ rate = 1250000; ++ break; ++ default: ++ break; ++ } ++ ++ return rate; ++} ++ ++static void ++ipq_unipcs_link_up_clock_rate_set(struct ipq_pcs_mii *qunipcs_ch, ++ phy_interface_t interface, ++ int speed) ++{ ++ struct ipq_pcs *qpcs = qunipcs_ch->qpcs; ++ unsigned long rate = 0; ++ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_QSGMII: ++ case PHY_INTERFACE_MODE_PSGMII: ++ rate = ipq_unipcs_clock_rate_get_gmii(speed); ++ break; ++ case PHY_INTERFACE_MODE_USXGMII: ++ rate = ipq_unipcs_clock_rate_get_xgmii(speed); ++ break; ++ default: ++ dev_err(qpcs->dev, ++ "interface %s not supported\n", phy_modes(interface)); ++ return; ++ } ++ ++ if (rate == 0) { ++ dev_err(qpcs->dev, "Invalid PCS clock rate\n"); ++ return; ++ } ++ ++ clk_set_rate(qunipcs_ch->rx_clk, rate); ++ clk_set_rate(qunipcs_ch->tx_clk, rate); ++ ++ fsleep(10000); ++} ++ + static int ipq_pcs_link_up_config_sgmii(struct ipq_pcs *qpcs, + int index, + unsigned int neg_mode, +@@ -467,6 +596,7 @@ static void ipq_pcs_get_state(struct phy + switch (state->interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: ++ case PHY_INTERFACE_MODE_PSGMII: + ipq_pcs_get_state_sgmii(qpcs, index, state); + break; + case PHY_INTERFACE_MODE_USXGMII: +@@ -497,10 +627,13 @@ static int ipq_pcs_config(struct phylink + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: ++ case PHY_INTERFACE_MODE_PSGMII: + return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface); + case PHY_INTERFACE_MODE_USXGMII: + return ipq_pcs_config_usxgmii(qpcs); + default: ++ dev_err(qpcs->dev, ++ "interface %s not supported\n", phy_modes(interface)); + return -EOPNOTSUPP; + }; + } +@@ -515,9 +648,14 @@ static void ipq_pcs_link_up(struct phyli + int index = qpcs_mii->index; + int ret; + ++ /* Configure PCS channel interface clock rate */ ++ ipq_unipcs_link_up_clock_rate_set(qpcs_mii, interface, speed); ++ ++ /* Configure PCS speed and reset PCS adapter */ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: ++ case PHY_INTERFACE_MODE_PSGMII: + ret = ipq_pcs_link_up_config_sgmii(qpcs, index, + neg_mode, speed); + break; +@@ -525,6 +663,8 @@ static void ipq_pcs_link_up(struct phyli + ret = ipq_pcs_link_up_config_usxgmii(qpcs, speed); + break; + default: ++ dev_err(qpcs->dev, ++ "interface %s not supported\n", phy_modes(interface)); + return; + } + +@@ -735,12 +875,38 @@ static const struct regmap_config ipq_pc + .fast_io = true, + }; + ++/** ++ * ipq_unipcs_create() - Create Qualcomm IPQ UNIPHY PCS ++ * @np: Device tree node to the PCS ++ * ++ * Description: Create a phylink PCS instance for a PCS node @np. ++ * ++ * Return: A pointer to the phylink PCS instance or an error-pointer value. ++ */ ++struct phylink_pcs *ipq_unipcs_create(struct device_node *np) ++{ ++ return ipq_pcs_get(np); ++} ++EXPORT_SYMBOL(ipq_unipcs_create); ++ ++/** ++ * ipq_unipcs_destroy() - Destroy Qualcomm IPQ UNIPHY PCS ++ * @pcs: PCS instance ++ * ++ * Description: Destroy a phylink PCS instance. ++ */ ++void ipq_unipcs_destroy(struct phylink_pcs *pcs) ++{ ++ ipq_pcs_put(pcs); ++} ++EXPORT_SYMBOL(ipq_unipcs_destroy); ++ + static int ipq9574_pcs_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; + struct ipq_pcs *qpcs; + struct clk *clk; +- int ret; ++ int i, ret; + + qpcs = devm_kzalloc(dev, sizeof(*qpcs), GFP_KERNEL); + if (!qpcs) +@@ -762,11 +928,23 @@ static int ipq9574_pcs_probe(struct plat + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to enable SYS clock\n"); ++ clk_set_rate(clk, 24000000); + + clk = devm_clk_get_enabled(dev, "ahb"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to enable AHB clock\n"); ++ clk_set_rate(clk, 100000000); ++ ++ for (i = 0; i < PCS_RESET_MAX; i++) { ++ qpcs->reset[i] = ++ devm_reset_control_get_optional_exclusive(dev, ++ pcs_reset_name[i]); ++ ++ if (IS_ERR(qpcs->reset[i])) ++ dev_err(dev, "Failed to get the reset ID %s\n", ++ pcs_reset_name[i]); ++ } + + ret = ipq_pcs_clk_register(qpcs); + if (ret) +--- /dev/null ++++ b/include/linux/pcs/pcs-qcom-ipq-uniphy.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ * ++ */ ++ ++#ifndef __LINUX_PCS_QCOM_IPQ_UNIPHY_H ++#define __LINUX_PCS_QCOM_IPQ_UNIPHY_H ++ ++struct phylink_pcs *ipq_unipcs_create(struct device_node *np); ++void ipq_unipcs_destroy(struct phylink_pcs *pcs); ++ ++#endif /* __LINUX_PCS_QCOM_IPQ_UNIPHY_H */ diff --git a/target/linux/qualcommbe/patches-6.12/0322-arm64-dts-qcom-ipq9574-add-PCS-uniphy-nodes.patch b/target/linux/qualcommbe/patches-6.12/0322-arm64-dts-qcom-ipq9574-add-PCS-uniphy-nodes.patch new file mode 100644 index 0000000000..ede62bd840 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0322-arm64-dts-qcom-ipq9574-add-PCS-uniphy-nodes.patch @@ -0,0 +1,155 @@ +From 8c02b6438167e1b73b908040c4ec3d4877c16f83 Mon Sep 17 00:00:00 2001 +From: Alexandru Gagniuc +Date: Sun, 11 May 2025 18:21:00 -0500 +Subject: [PATCH] arm64: dts: qcom: ipq9574: add PCS uniphy nodes + +IPQ9574 has three uniphy blocks. IPQ9554 lacks uniphy1. They take +their system and AHB clocks from NSSCC, and also feed NSSCC with +the clocks that are intended for the PHYs. This is not a cirular +dependency. Add nodes for these uniphy blocks, and the clocks they +feed back to the NSSCC node. + +Signed-off-by: Alexandru Gagniuc +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 116 ++++++++++++++++++++++++-- + 1 file changed, 110 insertions(+), 6 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1245,12 +1246,12 @@ + <&cmn_pll NSS_1200MHZ_CLK>, + <&cmn_pll PPE_353MHZ_CLK>, + <&gcc GPLL0_OUT_AUX>, +- <0>, +- <0>, +- <0>, +- <0>, +- <0>, +- <0>, ++ <&pcs_uniphy0 0>, ++ <&pcs_uniphy0 1>, ++ <&pcs_uniphy1 0>, ++ <&pcs_uniphy1 1>, ++ <&pcs_uniphy2 0>, ++ <&pcs_uniphy2 1>, + <&gcc GCC_NSSCC_CLK>; + clock-names = "xo", + "nss_1200", +@@ -1267,6 +1268,109 @@ + #reset-cells = <1>; + #interconnect-cells = <1>; + }; ++ ++ pcs_uniphy0: ethernet-pcs@7a00000 { ++ compatible = "qcom,ipq9574-pcs"; ++ reg = <0x7a00000 0x10000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&gcc GCC_UNIPHY0_SYS_CLK>, ++ <&gcc GCC_UNIPHY0_AHB_CLK>; ++ clock-names = "sys", ++ "ahb"; ++ resets = <&gcc GCC_UNIPHY0_SYS_RESET>, ++ <&gcc GCC_UNIPHY0_AHB_RESET>, ++ <&gcc GCC_UNIPHY0_XPCS_RESET>; ++ reset-names = "sys", ++ "ahb", ++ "xpcs"; ++ ++ #clock-cells = <1>; ++ ++ pcsuniphy0_ch0: pcs-mii@0 { ++ reg = <0>; ++ clocks = <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK>, ++ <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK>; ++ clock-names = "rx", ++ "tx"; ++ }; ++ ++ pcsuniphy0_ch1: pcs-mii@1 { ++ reg = <1>; ++ clocks = <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>, ++ <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>; ++ clock-names = "rx", ++ "tx"; ++ }; ++ ++ pcsuniphy0_ch2: pcs-mii@2 { ++ reg = <2>; ++ clocks = <&nsscc NSS_CC_UNIPHY_PORT3_RX_CLK>, ++ <&nsscc NSS_CC_UNIPHY_PORT3_TX_CLK>; ++ clock-names = "rx", ++ "tx"; ++ }; ++ ++ pcsuniphy0_ch3: pcs-mii@3 { ++ reg = <3>; ++ clocks = <&nsscc NSS_CC_UNIPHY_PORT4_RX_CLK>, ++ <&nsscc NSS_CC_UNIPHY_PORT4_TX_CLK>; ++ clock-names = "rx", ++ "tx"; ++ }; ++ }; ++ ++ pcs_uniphy1: ethernet-uniphy@7a10000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "qcom,ipq9574-uniphy"; ++ reg = <0x7a10000 0x10000>; ++ clocks = <&gcc GCC_UNIPHY1_SYS_CLK>, ++ <&gcc GCC_UNIPHY1_AHB_CLK>; ++ clock-names = "sys", ++ "ahb"; ++ resets = <&gcc GCC_UNIPHY1_SYS_RESET>, ++ <&gcc GCC_UNIPHY1_AHB_RESET>, ++ <&gcc GCC_UNIPHY1_XPCS_RESET>; ++ reset-names = "sys", ++ "ahb", ++ "xpcs"; ++ #clock-cells = <1>; ++ ++ pcsuniphy1_ch0: uniphy-ch@0 { ++ reg = <0>; ++ clocks = <&nsscc NSS_CC_UNIPHY_PORT5_RX_CLK>, ++ <&nsscc NSS_CC_UNIPHY_PORT5_TX_CLK>; ++ clock-names = "rx", ++ "tx"; ++ }; ++ }; ++ ++ pcs_uniphy2: ethernet-pcs@7a20000 { ++ compatible = "qcom,ipq9574-pcs"; ++ reg = <0x7a20000 0x10000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&gcc GCC_UNIPHY2_SYS_CLK>, ++ <&gcc GCC_UNIPHY2_AHB_CLK>; ++ clock-names = "sys", ++ "ahb"; ++ resets = <&gcc GCC_UNIPHY2_SYS_RESET>, ++ <&gcc GCC_UNIPHY2_AHB_RESET>, ++ <&gcc GCC_UNIPHY2_XPCS_RESET>; ++ reset-names = "sys", ++ "ahb", ++ "xpcs"; ++ #clock-cells = <1>; ++ ++ pcsuniphy2_ch0: pcs-mii@0 { ++ reg = <0>; ++ clocks = <&nsscc NSS_CC_UNIPHY_PORT6_RX_CLK>, ++ <&nsscc NSS_CC_UNIPHY_PORT6_TX_CLK>; ++ clock-names = "rx", ++ "tx"; ++ }; ++ }; + }; + + thermal-zones { diff --git a/target/linux/qualcommbe/patches-6.12/0323-dt-bindings-net-Add-PPE-for-Qualcomm-IPQ9574-SoC.patch b/target/linux/qualcommbe/patches-6.12/0323-dt-bindings-net-Add-PPE-for-Qualcomm-IPQ9574-SoC.patch new file mode 100644 index 0000000000..89c09ff9ea --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0323-dt-bindings-net-Add-PPE-for-Qualcomm-IPQ9574-SoC.patch @@ -0,0 +1,432 @@ +From 48dc6d2fe28865a5c3d271aeb966b984a8085e7c Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Sun, 9 Feb 2025 22:29:35 +0800 +Subject: [PATCH] dt-bindings: net: Add PPE for Qualcomm IPQ9574 SoC + +The PPE (packet process engine) hardware block is available in Qualcomm +IPQ chipsets that support PPE architecture, such as IPQ9574. The PPE in +the IPQ9574 SoC includes six ethernet ports (6 GMAC and 6 XGMAC), which +are used to connect with external PHY devices by PCS. It includes an L2 +switch function for bridging packets among the 6 ethernet ports and the +CPU port. The CPU port enables packet transfer between the ethernet +ports and the ARM cores in the SoC, using the ethernet DMA. + +The PPE also includes packet processing offload capabilities for various +networking functions such as route and bridge flows, VLANs, different +tunnel protocols and VPN. + +Signed-off-by: Luo Jie +--- + .../bindings/net/qcom,ipq9574-ppe.yaml | 406 ++++++++++++++++++ + 1 file changed, 406 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml +@@ -0,0 +1,406 @@ ++# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Qualcomm IPQ packet process engine (PPE) ++ ++maintainers: ++ - Luo Jie ++ - Lei Wei ++ - Suruchi Agarwal ++ - Pavithra R > ++ ++description: ++ The Ethernet functionality in the PPE (Packet Process Engine) is comprised ++ of three components, the switch core, port wrapper and Ethernet DMA. ++ ++ The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and ++ two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet ++ port to host CPU communication using Ethernet DMA. The other is used ++ communicating to the EIP engine which is used for IPsec offload. On the ++ IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external ++ Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue ++ Management) and SCH (Scheduler) modules for supporting the packet processing. ++ ++ The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) ++ supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There ++ are 3 UNIPHY (PCS) instances supported on the IPQ9574. ++ ++ Ethernet DMA is used to transmit and receive packets between the six Ethernet ++ ports and ARM host CPU. ++ ++ The follow diagram shows the PPE hardware block along with its connectivity ++ to the external hardware blocks such clock hardware blocks (CMNPLL, GCC, ++ NSS clock controller) and ethernet PCS/PHY blocks. For depicting the PHY ++ connectivity, one 4x1 Gbps PHY (QCA8075) and two 10 GBps PHYs are used as an ++ example. ++ - | ++ +---------+ ++ | 48 MHZ | ++ +----+----+ ++ |(clock) ++ v ++ +----+----+ ++ +------| CMN PLL | ++ | +----+----+ ++ | |(clock) ++ | v ++ | +----+----+ +----+----+ (clock) +----+----+ ++ | +---| NSSCC | | GCC |--------->| MDIO | ++ | | +----+----+ +----+----+ +----+----+ ++ | | |(clock & reset) |(clock) ++ | | v v ++ | | +-----------------------------+----------+----------+---------+ ++ | | | +-----+ |EDMA FIFO | | EIP FIFO| ++ | | | | SCH | +----------+ +---------+ ++ | | | +-----+ | | | ++ | | | +------+ +------+ +-------------------+ | ++ | | | | BM | | QM | IPQ9574-PPE | L2/L3 Process | | ++ | | | +------+ +------+ +-------------------+ | ++ | | | | | ++ | | | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ | ++ | | | | MAC0 | | MAC1 | | MAC2 | | MAC3 | | XGMAC4| |XGMAC5 | | ++ | | | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ | ++ | | | | | | | | | | ++ | | +-----+---------+---------+---------+---------+---------+-----+ ++ | | | | | | | | ++ | | +---+---------+---------+---------+---+ +---+---+ +---+---+ ++ +--+---->| PCS0 | | PCS1 | | PCS2 | ++ |(clock) +---+---------+---------+---------+---+ +---+---+ +---+---+ ++ | | | | | | | ++ | +---+---------+---------+---------+---+ +---+---+ +---+---+ ++ +------->| QCA8075 PHY | | PHY4 | | PHY5 | ++ (clock) +-------------------------------------+ +-------+ +-------+ ++ ++properties: ++ compatible: ++ enum: ++ - qcom,ipq9574-ppe ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: PPE core clock from NSS clock controller ++ - description: PPE APB (Advanced Peripheral Bus) clock from NSS clock controller ++ - description: PPE ingress process engine clock from NSS clock controller ++ - description: PPE BM, QM and scheduler clock from NSS clock controller ++ ++ clock-names: ++ items: ++ - const: ppe ++ - const: apb ++ - const: ipe ++ - const: btq ++ ++ resets: ++ maxItems: 1 ++ description: PPE reset, which is necessary before configuring PPE hardware ++ ++ interconnects: ++ items: ++ - description: Clock path leading to PPE switch core function ++ - description: Clock path leading to PPE register access ++ - description: Clock path leading to QoS generation ++ - description: Clock path leading to timeout reference ++ - description: Clock path leading to NSS NOC from memory NOC ++ - description: Clock path leading to memory NOC from NSS NOC ++ - description: Clock path leading to enhanced memory NOC from NSS NOC ++ ++ interconnect-names: ++ items: ++ - const: ppe ++ - const: ppe_cfg ++ - const: qos_gen ++ - const: timeout_ref ++ - const: nssnoc_memnoc ++ - const: memnoc_nssnoc ++ - const: memnoc_nssnoc_1 ++ ++ ethernet-dma: ++ type: object ++ additionalProperties: false ++ description: ++ EDMA (Ethernet DMA) is used to transmit packets between PPE and ARM ++ host CPU. There are 32 TX descriptor rings, 32 TX completion rings, ++ 24 RX descriptor rings and 8 RX fill rings supported. ++ ++ properties: ++ clocks: ++ items: ++ - description: EDMA system clock from NSS Clock Controller ++ - description: EDMA APB (Advanced Peripheral Bus) clock from ++ NSS Clock Controller ++ ++ clock-names: ++ items: ++ - const: sys ++ - const: apb ++ ++ resets: ++ maxItems: 1 ++ description: EDMA reset from NSS clock controller ++ ++ interrupts: ++ minItems: 29 ++ maxItems: 57 ++ ++ interrupt-names: ++ minItems: 29 ++ maxItems: 57 ++ items: ++ pattern: '^(txcmpl_([0-9]|[1-2][0-9]|3[0-1])|rxdesc_([0-9]|1[0-9]|2[0-3])|misc)$' ++ description: ++ Interrupts "txcmpl_[0-31]" are the Ethernet DMA Tx completion ring interrupts. ++ Interrupts "rxdesc_[0-23]" are the Ethernet DMA Rx Descriptor ring interrupts. ++ Interrupt "misc" is the Ethernet DMA miscellaneous error interrupt. ++ ++ required: ++ - clocks ++ - clock-names ++ - resets ++ - interrupts ++ - interrupt-names ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - interconnects ++ - interconnect-names ++ - ethernet-dma ++ ++allOf: ++ - $ref: ethernet-switch.yaml ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ ++ ethernet-switch@3a000000 { ++ compatible = "qcom,ipq9574-ppe"; ++ reg = <0x3a000000 0xbef800>; ++ clocks = <&nsscc 80>, ++ <&nsscc 79>, ++ <&nsscc 81>, ++ <&nsscc 78>; ++ clock-names = "ppe", ++ "apb", ++ "ipe", ++ "btq"; ++ resets = <&nsscc 108>; ++ interconnects = <&nsscc MASTER_NSSNOC_PPE &nsscc SLAVE_NSSNOC_PPE>, ++ <&nsscc MASTER_NSSNOC_PPE_CFG &nsscc SLAVE_NSSNOC_PPE_CFG>, ++ <&gcc MASTER_NSSNOC_QOSGEN_REF &gcc SLAVE_NSSNOC_QOSGEN_REF>, ++ <&gcc MASTER_NSSNOC_TIMEOUT_REF &gcc SLAVE_NSSNOC_TIMEOUT_REF>, ++ <&gcc MASTER_MEM_NOC_NSSNOC &gcc SLAVE_MEM_NOC_NSSNOC>, ++ <&gcc MASTER_NSSNOC_MEMNOC &gcc SLAVE_NSSNOC_MEMNOC>, ++ <&gcc MASTER_NSSNOC_MEM_NOC_1 &gcc SLAVE_NSSNOC_MEM_NOC_1>; ++ interconnect-names = "ppe", ++ "ppe_cfg", ++ "qos_gen", ++ "timeout_ref", ++ "nssnoc_memnoc", ++ "memnoc_nssnoc", ++ "memnoc_nssnoc_1"; ++ ++ ethernet-dma { ++ clocks = <&nsscc 77>, ++ <&nsscc 76>; ++ clock-names = "sys", ++ "apb"; ++ resets = <&nsscc 0>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "txcmpl_8", ++ "txcmpl_9", ++ "txcmpl_10", ++ "txcmpl_11", ++ "txcmpl_12", ++ "txcmpl_13", ++ "txcmpl_14", ++ "txcmpl_15", ++ "txcmpl_16", ++ "txcmpl_17", ++ "txcmpl_18", ++ "txcmpl_19", ++ "txcmpl_20", ++ "txcmpl_21", ++ "txcmpl_22", ++ "txcmpl_23", ++ "txcmpl_24", ++ "txcmpl_25", ++ "txcmpl_26", ++ "txcmpl_27", ++ "txcmpl_28", ++ "txcmpl_29", ++ "txcmpl_30", ++ "txcmpl_31", ++ "rxdesc_20", ++ "rxdesc_21", ++ "rxdesc_22", ++ "rxdesc_23", ++ "misc"; ++ }; ++ ++ ethernet-ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ phy-mode = "qsgmii"; ++ managed = "in-band-status"; ++ phy-handle = <&phy0>; ++ pcs-handle = <&pcs0_mii0>; ++ clocks = <&nsscc 33>, ++ <&nsscc 34>, ++ <&nsscc 37>; ++ clock-names = "mac", ++ "rx", ++ "tx"; ++ resets = <&nsscc 29>, ++ <&nsscc 96>, ++ <&nsscc 97>; ++ reset-names = "mac", ++ "rx", ++ "tx"; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ phy-mode = "qsgmii"; ++ managed = "in-band-status"; ++ phy-handle = <&phy1>; ++ pcs-handle = <&pcs0_mii1>; ++ clocks = <&nsscc 40>, ++ <&nsscc 41>, ++ <&nsscc 44>; ++ clock-names = "mac", ++ "rx", ++ "tx"; ++ resets = <&nsscc 30>, ++ <&nsscc 98>, ++ <&nsscc 99>; ++ reset-names = "mac", ++ "rx", ++ "tx"; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ phy-mode = "qsgmii"; ++ managed = "in-band-status"; ++ phy-handle = <&phy2>; ++ pcs-handle = <&pcs0_mii2>; ++ clocks = <&nsscc 47>, ++ <&nsscc 48>, ++ <&nsscc 51>; ++ clock-names = "mac", ++ "rx", ++ "tx"; ++ resets = <&nsscc 31>, ++ <&nsscc 100>, ++ <&nsscc 101>; ++ reset-names = "mac", ++ "rx", ++ "tx"; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ phy-mode = "qsgmii"; ++ managed = "in-band-status"; ++ phy-handle = <&phy3>; ++ pcs-handle = <&pcs0_mii3>; ++ clocks = <&nsscc 54>, ++ <&nsscc 55>, ++ <&nsscc 58>; ++ clock-names = "mac", ++ "rx", ++ "tx"; ++ resets = <&nsscc 32>, ++ <&nsscc 102>, ++ <&nsscc 103>; ++ reset-names = "mac", ++ "rx", ++ "tx"; ++ }; ++ ++ port@5 { ++ reg = <5>; ++ phy-mode = "usxgmii"; ++ managed = "in-band-status"; ++ phy-handle = <&phy4>; ++ pcs-handle = <&pcs1_mii0>; ++ clocks = <&nsscc 61>, ++ <&nsscc 62>, ++ <&nsscc 65>; ++ clock-names = "mac", ++ "rx", ++ "tx"; ++ resets = <&nsscc 33>, ++ <&nsscc 104>, ++ <&nsscc 105>; ++ reset-names = "mac", ++ "rx", ++ "tx"; ++ }; ++ ++ port@6 { ++ reg = <6>; ++ phy-mode = "usxgmii"; ++ managed = "in-band-status"; ++ phy-handle = <&phy5>; ++ pcs-handle = <&pcs2_mii0>; ++ clocks = <&nsscc 68>, ++ <&nsscc 69>, ++ <&nsscc 72>; ++ clock-names = "mac", ++ "rx", ++ "tx"; ++ resets = <&nsscc 34>, ++ <&nsscc 106>, ++ <&nsscc 107>; ++ reset-names = "mac", ++ "rx", ++ "tx"; ++ }; ++ }; ++ }; diff --git a/target/linux/qualcommbe/patches-6.12/0324-docs-networking-Add-PPE-driver-documentation-for-Qua.patch b/target/linux/qualcommbe/patches-6.12/0324-docs-networking-Add-PPE-driver-documentation-for-Qua.patch new file mode 100644 index 0000000000..429006c7bc --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0324-docs-networking-Add-PPE-driver-documentation-for-Qua.patch @@ -0,0 +1,227 @@ +From 9973b6610830146af1a12fe02d2d6440eb80b0f9 Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Sun, 9 Feb 2025 22:29:36 +0800 +Subject: [PATCH] docs: networking: Add PPE driver documentation for Qualcomm + IPQ9574 SoC + +Add description and high-level diagram for PPE, driver overview and +module enable/debug information. + +Signed-off-by: Lei Wei +Signed-off-by: Luo Jie +--- + .../device_drivers/ethernet/index.rst | 1 + + .../ethernet/qualcomm/ppe/ppe.rst | 197 ++++++++++++++++++ + 2 files changed, 198 insertions(+) + create mode 100644 Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst + +--- a/Documentation/networking/device_drivers/ethernet/index.rst ++++ b/Documentation/networking/device_drivers/ethernet/index.rst +@@ -49,6 +49,7 @@ Contents: + neterion/s2io + netronome/nfp + pensando/ionic ++ qualcomm/ppe/ppe + smsc/smc9 + stmicro/stmmac + ti/cpsw +--- /dev/null ++++ b/Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst +@@ -0,0 +1,197 @@ ++.. SPDX-License-Identifier: GPL-2.0 ++ ++=============================================== ++PPE Ethernet Driver for Qualcomm IPQ SoC Family ++=============================================== ++ ++Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. ++ ++Author: Lei Wei ++ ++ ++Contents ++======== ++ ++- `PPE Overview`_ ++- `PPE Driver Overview`_ ++- `PPE Driver Supported SoCs`_ ++- `Enabling the Driver`_ ++- `Debugging`_ ++ ++ ++PPE Overview ++============ ++ ++IPQ (Qualcomm Internet Processor) SoC (System-on-Chip) series is Qualcomm's series of ++networking SoC for Wi-Fi access points. The PPE (Packet Process Engine) is the Ethernet ++packet process engine in the IPQ SoC. ++ ++Below is a simplified hardware diagram of IPQ9574 SoC which includes the PPE engine and ++other blocks which are in the SoC but outside the PPE engine. These blocks work together ++to enable the Ethernet for the IPQ SoC:: ++ ++ +------+ +------+ +------+ +------+ +------+ +------+ start +-------+ ++ |netdev| |netdev| |netdev| |netdev| |netdev| |netdev|<------|PHYLINK| ++ +------+ +------+ +------+ +------+ +------+ +------+ stop +-+-+-+-+ ++ | | | ^ ++ +-------+ +-------------------------+--------+----------------------+ | | | ++ | GCC | | | EDMA | | | | | ++ +---+---+ | PPE +---+----+ | | | | ++ | clk | | | | | | ++ +------>| +-----------------------+------+-----+---------------+ | | | | ++ | | Switch Core |Port0 | |Port7(EIP FIFO)| | | | | ++ | | +---+--+ +------+--------+ | | | | ++ | | | | | | | | | ++ +-------+ | | +------+---------------+----+ | | | | | ++ |CMN PLL| | | +---+ +---+ +----+ | +--------+ | | | | | | ++ +---+---+ | | |BM | |QM | |SCH | | | L2/L3 | ....... | | | | | | ++ | | | | +---+ +---+ +----+ | +--------+ | | | | | | ++ | | | | +------+--------------------+ | | | | | ++ | | | | | | | | | | ++ | v | | +-----+-+-----+-+-----+-+-+---+--+-----+-+-----+ | | | | | ++ | +------+ | | |Port1| |Port2| |Port3| |Port4| |Port5| |Port6| | | | | | ++ | |NSSCC | | | +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ | | mac| | | ++ | +-+-+--+ | | |MAC0 | |MAC1 | |MAC2 | |MAC3 | |MAC4 | |MAC5 | | |<---+ | | ++ | ^ | |clk | | +-----+-+-----+-+-----+-+-----+--+-----+-+-----+ | | ops | | ++ | | | +---->| +----|------|-------|-------|---------|--------|-----+ | | | ++ | | | +---------------------------------------------------------+ | | ++ | | | | | | | | | | | ++ | | | MII clk | QSGMII USXGMII USXGMII | | ++ | | +------------->| | | | | | | | ++ | | +-------------------------+ +---------+ +---------+ | | ++ | |125/312.5M clk| (PCS0) | | (PCS1) | | (PCS2) | pcs ops | | ++ | +--------------+ UNIPHY0 | | UNIPHY1 | | UNIPHY2 |<--------+ | ++ +--------------->| | | | | | | ++ | 31.25M ref clk +-------------------------+ +---------+ +---------+ | ++ | | | | | | | | ++ | +-----------------------------------------------------+ | ++ |25/50M ref clk| +-------------------------+ +------+ +------+ | link | ++ +------------->| | QUAD PHY | | PHY4 | | PHY5 | |---------+ ++ | +-------------------------+ +------+ +------+ | change ++ | | ++ | MDIO bus | ++ +-----------------------------------------------------+ ++ ++The CMN (Common) PLL, NSSCC (Networking Sub System Clock Controller) and GCC (Global ++Clock Controller) blocks are in the SoC and act as clock providers. ++ ++The UNIPHY block is in the SoC and provides the PCS (Physical Coding Sublayer) and ++XPCS (10-Gigabit Physical Coding Sublayer) functions to support different interface ++modes between the PPE MAC and the external PHY. ++ ++This documentation focuses on the descriptions of PPE engine and the PPE driver. ++ ++The Ethernet functionality in the PPE (Packet Process Engine) is comprised of three ++components: the switch core, port wrapper and Ethernet DMA. ++ ++The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and two FIFO ++interfaces. One of the two FIFO interfaces is used for Ethernet port to host CPU ++communication using Ethernet DMA. The other is used communicating to the EIP engine ++which is used for IPsec offload. On the IPQ9574, the PPE includes 6 GMAC/XGMACs that ++can be connected with external Ethernet PHY. Switch core also includes BM (Buffer ++Management), QM (Queue Management) and SCH (Scheduler) modules for supporting the ++packet processing. ++ ++The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) supporting ++various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There are 3 UNIPHY (PCS) ++instances supported on the IPQ9574. ++ ++Ethernet DMA is used to transmit and receive packets between the Ethernet subsystem ++and ARM host CPU. ++ ++The following lists the main blocks in the PPE engine which will be driven by this ++PPE driver: ++ ++- BM ++ BM is the hardware buffer manager for the PPE switch ports. ++- QM ++ Queue Manager for managing the egress hardware queues of the PPE switch ports. ++- SCH ++ The scheduler which manages the hardware traffic scheduling for the PPE switch ports. ++- L2 ++ The L2 block performs the packet bridging in the switch core. The bridge domain is ++ represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be ++ enabled based on the VSI domain and bridge forwarding occurs within the VSI domain. ++- MAC ++ The PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding ++ to six switch ports (port1 to port6). The MAC block is connected with external PHY ++ through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and ++ the switch port can select to use GMAC or XMAC through a MUX selection according to ++ the external PHY's capability. ++- EDMA (Ethernet DMA) ++ The Ethernet DMA is used to transmit and receive Ethernet packets between the PPE ++ ports and the ARM cores. ++ ++The received packet on a PPE MAC port can be forwarded to another PPE MAC port. It can ++be also forwarded to internal switch port0 so that the packet can be delivered to the ++ARM cores using the Ethernet DMA (EDMA) engine. The Ethernet DMA driver will deliver the ++packet to the corresponding 'netdevice' interface. ++ ++The software instantiations of the PPE MAC (netdevice), PCS and external PHYs interact ++with the Linux PHYLINK framework to manage the connectivity between the PPE ports and ++the connected PHYs, and the port link states. This is also illustrated in above diagram. ++ ++ ++PPE Driver Overview ++=================== ++PPE driver is Ethernet driver for the Qualcomm IPQ SoC. It is a single platform driver ++which includes the PPE part and Ethernet DMA part. The PPE part initializes and drives the ++various blocks in PPE switch core such as BM/QM/L2 blocks and the PPE MACs. The EDMA part ++drives the Ethernet DMA for packet transfer between PPE ports and ARM cores, and enables ++the netdevice driver for the PPE ports. ++ ++The PPE driver files in drivers/net/ethernet/qualcomm/ppe/ are listed as below: ++ ++- Makefile ++- ppe.c ++- ppe.h ++- ppe_config.c ++- ppe_config.h ++- ppe_debugfs.c ++- ppe_debugfs.h ++- ppe_regs.h ++ ++The ppe.c file contains the main PPE platform driver and undertakes the initialization of ++PPE switch core blocks such as QM, BM and L2. The configuration APIs for these hardware ++blocks are provided in the ppe_config.c file. ++ ++The ppe.h defines the PPE device data structure which will be used by PPE driver functions. ++ ++The ppe_debugfs.c enables the PPE statistics counters such as PPE port Rx and Tx counters, ++CPU code counters and queue counters. ++ ++ ++PPE Driver Supported SoCs ++========================= ++ ++The PPE driver supports the following IPQ SoC: ++ ++- IPQ9574 ++ ++ ++Enabling the Driver ++=================== ++ ++The driver is located in the menu structure at: ++ ++ -> Device Drivers ++ -> Network device support (NETDEVICES [=y]) ++ -> Ethernet driver support ++ -> Qualcomm devices ++ -> Qualcomm Technologies, Inc. PPE Ethernet support ++ ++If this driver is built as a module, we can use below commands to install and remove it: ++ ++- insmod qcom-ppe.ko ++- rmmod qcom-ppe.ko ++ ++The PPE driver functionally depends on the CMN PLL and NSSCC clock controller drivers. ++Please make sure the dependent modules are installed before installing the PPE driver ++module. ++ ++ ++Debugging ++========= ++ ++The PPE hardware counters are available in the debugfs and can be checked by the command ++``cat /sys/kernel/debug/ppe/packet_counters``. diff --git a/target/linux/qualcommbe/patches-6.12/0325-net-ethernet-qualcomm-Add-PPE-driver-for-IPQ9574-SoC.patch b/target/linux/qualcommbe/patches-6.12/0325-net-ethernet-qualcomm-Add-PPE-driver-for-IPQ9574-SoC.patch new file mode 100644 index 0000000000..f55879ae48 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0325-net-ethernet-qualcomm-Add-PPE-driver-for-IPQ9574-SoC.patch @@ -0,0 +1,339 @@ +From d1158f0282304c89217894aa346fc45364b95542 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Sun, 9 Feb 2025 22:29:37 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Add PPE driver for IPQ9574 SoC + +The PPE (Packet Process Engine) hardware block is available +on Qualcomm IPQ SoC that support PPE architecture, such as +IPQ9574. + +The PPE in IPQ9574 includes six integrated ethernet MAC +(for 6 PPE ports), buffer management, queue management and +scheduler functions. The MACs can connect with the external +PHY or switch devices using the UNIPHY PCS block available +in the SoC. + +The PPE also includes various packet processing offload +capabilities such as L3 routing and L2 bridging, VLAN and +tunnel processing offload. It also includes Ethernet DMA +function for transferring packets between ARM cores and +PPE ethernet ports. + +This patch adds the base source files and Makefiles for +the PPE driver such as platform driver registration, +clock initialization, and PPE reset routines. + +Signed-off-by: Luo Jie +--- + drivers/net/ethernet/qualcomm/Kconfig | 15 ++ + drivers/net/ethernet/qualcomm/Makefile | 1 + + drivers/net/ethernet/qualcomm/ppe/Makefile | 7 + + drivers/net/ethernet/qualcomm/ppe/ppe.c | 218 +++++++++++++++++++++ + drivers/net/ethernet/qualcomm/ppe/ppe.h | 36 ++++ + 5 files changed, 277 insertions(+) + create mode 100644 drivers/net/ethernet/qualcomm/ppe/Makefile + create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe.c + create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe.h + +--- a/drivers/net/ethernet/qualcomm/Kconfig ++++ b/drivers/net/ethernet/qualcomm/Kconfig +@@ -61,6 +61,21 @@ config QCOM_EMAC + low power, Receive-Side Scaling (RSS), and IEEE 1588-2008 + Precision Clock Synchronization Protocol. + ++config QCOM_PPE ++ tristate "Qualcomm Technologies, Inc. PPE Ethernet support" ++ depends on HAS_IOMEM && OF ++ depends on COMMON_CLK ++ select REGMAP_MMIO ++ help ++ This driver supports the Qualcomm Technologies, Inc. packet ++ process engine (PPE) available with IPQ SoC. The PPE includes ++ the ethernet MACs, Ethernet DMA (EDMA) and switch core that ++ supports L3 flow offload, L2 switch function, RSS and tunnel ++ offload. ++ ++ To compile this driver as a module, choose M here. The module ++ will be called qcom-ppe. ++ + source "drivers/net/ethernet/qualcomm/rmnet/Kconfig" + + endif # NET_VENDOR_QUALCOMM +--- a/drivers/net/ethernet/qualcomm/Makefile ++++ b/drivers/net/ethernet/qualcomm/Makefile +@@ -11,4 +11,5 @@ qcauart-objs := qca_uart.o + + obj-y += emac/ + ++obj-$(CONFIG_QCOM_PPE) += ppe/ + obj-$(CONFIG_RMNET) += rmnet/ +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/Makefile +@@ -0,0 +1,7 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++# ++# Makefile for the device driver of PPE (Packet Process Engine) in IPQ SoC ++# ++ ++obj-$(CONFIG_QCOM_PPE) += qcom-ppe.o ++qcom-ppe-objs := ppe.o +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe.c +@@ -0,0 +1,218 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* PPE platform device probe, DTSI parser and PPE clock initializations. */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ppe.h" ++ ++#define PPE_PORT_MAX 8 ++#define PPE_CLK_RATE 353000000 ++ ++/* ICC clocks for enabling PPE device. The avg_bw and peak_bw with value 0 ++ * will be updated by the clock rate of PPE. ++ */ ++static const struct icc_bulk_data ppe_icc_data[] = { ++ { ++ .name = "ppe", ++ .avg_bw = 0, ++ .peak_bw = 0, ++ }, ++ { ++ .name = "ppe_cfg", ++ .avg_bw = 0, ++ .peak_bw = 0, ++ }, ++ { ++ .name = "qos_gen", ++ .avg_bw = 6000, ++ .peak_bw = 6000, ++ }, ++ { ++ .name = "timeout_ref", ++ .avg_bw = 6000, ++ .peak_bw = 6000, ++ }, ++ { ++ .name = "nssnoc_memnoc", ++ .avg_bw = 533333, ++ .peak_bw = 533333, ++ }, ++ { ++ .name = "memnoc_nssnoc", ++ .avg_bw = 533333, ++ .peak_bw = 533333, ++ }, ++ { ++ .name = "memnoc_nssnoc_1", ++ .avg_bw = 533333, ++ .peak_bw = 533333, ++ }, ++}; ++ ++static const struct regmap_range ppe_readable_ranges[] = { ++ regmap_reg_range(0x0, 0x1ff), /* Global */ ++ regmap_reg_range(0x400, 0x5ff), /* LPI CSR */ ++ regmap_reg_range(0x1000, 0x11ff), /* GMAC0 */ ++ regmap_reg_range(0x1200, 0x13ff), /* GMAC1 */ ++ regmap_reg_range(0x1400, 0x15ff), /* GMAC2 */ ++ regmap_reg_range(0x1600, 0x17ff), /* GMAC3 */ ++ regmap_reg_range(0x1800, 0x19ff), /* GMAC4 */ ++ regmap_reg_range(0x1a00, 0x1bff), /* GMAC5 */ ++ regmap_reg_range(0xb000, 0xefff), /* PRX CSR */ ++ regmap_reg_range(0xf000, 0x1efff), /* IPE */ ++ regmap_reg_range(0x20000, 0x5ffff), /* PTX CSR */ ++ regmap_reg_range(0x60000, 0x9ffff), /* IPE L2 CSR */ ++ regmap_reg_range(0xb0000, 0xeffff), /* IPO CSR */ ++ regmap_reg_range(0x100000, 0x17ffff), /* IPE PC */ ++ regmap_reg_range(0x180000, 0x1bffff), /* PRE IPO CSR */ ++ regmap_reg_range(0x1d0000, 0x1dffff), /* Tunnel parser */ ++ regmap_reg_range(0x1e0000, 0x1effff), /* Ingress parse */ ++ regmap_reg_range(0x200000, 0x2fffff), /* IPE L3 */ ++ regmap_reg_range(0x300000, 0x3fffff), /* IPE tunnel */ ++ regmap_reg_range(0x400000, 0x4fffff), /* Scheduler */ ++ regmap_reg_range(0x500000, 0x503fff), /* XGMAC0 */ ++ regmap_reg_range(0x504000, 0x507fff), /* XGMAC1 */ ++ regmap_reg_range(0x508000, 0x50bfff), /* XGMAC2 */ ++ regmap_reg_range(0x50c000, 0x50ffff), /* XGMAC3 */ ++ regmap_reg_range(0x510000, 0x513fff), /* XGMAC4 */ ++ regmap_reg_range(0x514000, 0x517fff), /* XGMAC5 */ ++ regmap_reg_range(0x600000, 0x6fffff), /* BM */ ++ regmap_reg_range(0x800000, 0x9fffff), /* QM */ ++ regmap_reg_range(0xb00000, 0xbef800), /* EDMA */ ++}; ++ ++static const struct regmap_access_table ppe_reg_table = { ++ .yes_ranges = ppe_readable_ranges, ++ .n_yes_ranges = ARRAY_SIZE(ppe_readable_ranges), ++}; ++ ++static const struct regmap_config regmap_config_ipq9574 = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .rd_table = &ppe_reg_table, ++ .wr_table = &ppe_reg_table, ++ .max_register = 0xbef800, ++ .fast_io = true, ++}; ++ ++static int ppe_clock_init_and_reset(struct ppe_device *ppe_dev) ++{ ++ unsigned long ppe_rate = ppe_dev->clk_rate; ++ struct device *dev = ppe_dev->dev; ++ struct reset_control *rstc; ++ struct clk_bulk_data *clks; ++ struct clk *clk; ++ int ret, i; ++ ++ for (i = 0; i < ppe_dev->num_icc_paths; i++) { ++ ppe_dev->icc_paths[i].name = ppe_icc_data[i].name; ++ ppe_dev->icc_paths[i].avg_bw = ppe_icc_data[i].avg_bw ? : ++ Bps_to_icc(ppe_rate); ++ ppe_dev->icc_paths[i].peak_bw = ppe_icc_data[i].peak_bw ? : ++ Bps_to_icc(ppe_rate); ++ } ++ ++ ret = devm_of_icc_bulk_get(dev, ppe_dev->num_icc_paths, ++ ppe_dev->icc_paths); ++ if (ret) ++ return ret; ++ ++ ret = icc_bulk_set_bw(ppe_dev->num_icc_paths, ppe_dev->icc_paths); ++ if (ret) ++ return ret; ++ ++ /* The PPE clocks have a common parent clock. Setting the clock ++ * rate of "ppe" ensures the clock rate of all PPE clocks is ++ * configured to the same rate. ++ */ ++ clk = devm_clk_get(dev, "ppe"); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ ret = clk_set_rate(clk, ppe_rate); ++ if (ret) ++ return ret; ++ ++ ret = devm_clk_bulk_get_all_enable(dev, &clks); ++ if (ret < 0) ++ return ret; ++ ++ /* Reset the PPE. */ ++ rstc = devm_reset_control_get_exclusive(dev, NULL); ++ if (IS_ERR(rstc)) ++ return PTR_ERR(rstc); ++ ++ ret = reset_control_assert(rstc); ++ if (ret) ++ return ret; ++ ++ /* The delay 10 ms of assert is necessary for resetting PPE. */ ++ usleep_range(10000, 11000); ++ ++ return reset_control_deassert(rstc); ++} ++ ++static int qcom_ppe_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ppe_device *ppe_dev; ++ void __iomem *base; ++ int ret, num_icc; ++ ++ num_icc = ARRAY_SIZE(ppe_icc_data); ++ ppe_dev = devm_kzalloc(dev, struct_size(ppe_dev, icc_paths, num_icc), ++ GFP_KERNEL); ++ if (!ppe_dev) ++ return -ENOMEM; ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return dev_err_probe(dev, PTR_ERR(base), "PPE ioremap failed\n"); ++ ++ ppe_dev->regmap = devm_regmap_init_mmio(dev, base, ®map_config_ipq9574); ++ if (IS_ERR(ppe_dev->regmap)) ++ return dev_err_probe(dev, PTR_ERR(ppe_dev->regmap), ++ "PPE initialize regmap failed\n"); ++ ppe_dev->dev = dev; ++ ppe_dev->clk_rate = PPE_CLK_RATE; ++ ppe_dev->num_ports = PPE_PORT_MAX; ++ ppe_dev->num_icc_paths = num_icc; ++ ++ ret = ppe_clock_init_and_reset(ppe_dev); ++ if (ret) ++ return dev_err_probe(dev, ret, "PPE clock config failed\n"); ++ ++ platform_set_drvdata(pdev, ppe_dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id qcom_ppe_of_match[] = { ++ { .compatible = "qcom,ipq9574-ppe" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, qcom_ppe_of_match); ++ ++static struct platform_driver qcom_ppe_driver = { ++ .driver = { ++ .name = "qcom_ppe", ++ .of_match_table = qcom_ppe_of_match, ++ }, ++ .probe = qcom_ppe_probe, ++}; ++module_platform_driver(qcom_ppe_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ PPE driver"); +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe.h +@@ -0,0 +1,36 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * ++ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#ifndef __PPE_H__ ++#define __PPE_H__ ++ ++#include ++#include ++ ++struct device; ++struct regmap; ++ ++/** ++ * struct ppe_device - PPE device private data. ++ * @dev: PPE device structure. ++ * @regmap: PPE register map. ++ * @clk_rate: PPE clock rate. ++ * @num_ports: Number of PPE ports. ++ * @num_icc_paths: Number of interconnect paths. ++ * @icc_paths: Interconnect path array. ++ * ++ * PPE device is the instance of PPE hardware, which is used to ++ * configure PPE packet process modules such as BM (buffer management), ++ * QM (queue management), and scheduler. ++ */ ++struct ppe_device { ++ struct device *dev; ++ struct regmap *regmap; ++ unsigned long clk_rate; ++ unsigned int num_ports; ++ unsigned int num_icc_paths; ++ struct icc_bulk_data icc_paths[] __counted_by(num_icc_paths); ++}; ++#endif diff --git a/target/linux/qualcommbe/patches-6.12/0326-net-ethernet-qualcomm-Initialize-PPE-buffer-manageme.patch b/target/linux/qualcommbe/patches-6.12/0326-net-ethernet-qualcomm-Initialize-PPE-buffer-manageme.patch new file mode 100644 index 0000000000..5f38e25b37 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0326-net-ethernet-qualcomm-Initialize-PPE-buffer-manageme.patch @@ -0,0 +1,328 @@ +From 6e639ab45348ee7a697db8b481fa6f8555280f58 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Sun, 9 Feb 2025 22:29:38 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Initialize PPE buffer management for + IPQ9574 + +The BM (Buffer Management) config controls the pause frame generated +on the PPE port. There are maximum 15 BM ports and 4 groups supported, +all BM ports are assigned to group 0 by default. The number of hardware +buffers configured for the port influence the threshold of the flow +control for that port. + +Signed-off-by: Luo Jie +--- + drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +- + drivers/net/ethernet/qualcomm/ppe/ppe.c | 5 + + .../net/ethernet/qualcomm/ppe/ppe_config.c | 195 ++++++++++++++++++ + .../net/ethernet/qualcomm/ppe/ppe_config.h | 12 ++ + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 59 ++++++ + 5 files changed, 272 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe_config.c + create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe_config.h + create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe_regs.h + +--- a/drivers/net/ethernet/qualcomm/ppe/Makefile ++++ b/drivers/net/ethernet/qualcomm/ppe/Makefile +@@ -4,4 +4,4 @@ + # + + obj-$(CONFIG_QCOM_PPE) += qcom-ppe.o +-qcom-ppe-objs := ppe.o ++qcom-ppe-objs := ppe.o ppe_config.o +--- a/drivers/net/ethernet/qualcomm/ppe/ppe.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe.c +@@ -15,6 +15,7 @@ + #include + + #include "ppe.h" ++#include "ppe_config.h" + + #define PPE_PORT_MAX 8 + #define PPE_CLK_RATE 353000000 +@@ -194,6 +195,10 @@ static int qcom_ppe_probe(struct platfor + if (ret) + return dev_err_probe(dev, ret, "PPE clock config failed\n"); + ++ ret = ppe_hw_config(ppe_dev); ++ if (ret) ++ return dev_err_probe(dev, ret, "PPE HW config failed\n"); ++ + platform_set_drvdata(pdev, ppe_dev); + + return 0; +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +@@ -0,0 +1,195 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* PPE HW initialization configs such as BM(buffer management), ++ * QM(queue management) and scheduler configs. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "ppe.h" ++#include "ppe_config.h" ++#include "ppe_regs.h" ++ ++/** ++ * struct ppe_bm_port_config - PPE BM port configuration. ++ * @port_id_start: The fist BM port ID to configure. ++ * @port_id_end: The last BM port ID to configure. ++ * @pre_alloc: BM port dedicated buffer number. ++ * @in_fly_buf: Buffer number for receiving the packet after pause frame sent. ++ * @ceil: Ceil to generate the back pressure. ++ * @weight: Weight value. ++ * @resume_offset: Resume offset from the threshold value. ++ * @resume_ceil: Ceil to resume from the back pressure state. ++ * @dynamic: Dynamic threshold used or not. ++ * ++ * The is for configuring the threshold that impacts the port ++ * flow control. ++ */ ++struct ppe_bm_port_config { ++ unsigned int port_id_start; ++ unsigned int port_id_end; ++ unsigned int pre_alloc; ++ unsigned int in_fly_buf; ++ unsigned int ceil; ++ unsigned int weight; ++ unsigned int resume_offset; ++ unsigned int resume_ceil; ++ bool dynamic; ++}; ++ ++/* Assign the share buffer number 1550 to group 0 by default. */ ++static const int ipq9574_ppe_bm_group_config = 1550; ++ ++/* The buffer configurations per PPE port. There are 15 BM ports and ++ * 4 BM groups supported by PPE. BM port (0-7) is for EDMA port 0, ++ * BM port (8-13) is for PPE physical port 1-6 and BM port 14 is for ++ * EIP port. ++ */ ++static const struct ppe_bm_port_config ipq9574_ppe_bm_port_config[] = { ++ { ++ /* Buffer configuration for the BM port ID 0 of EDMA. */ ++ .port_id_start = 0, ++ .port_id_end = 0, ++ .pre_alloc = 0, ++ .in_fly_buf = 100, ++ .ceil = 1146, ++ .weight = 7, ++ .resume_offset = 8, ++ .resume_ceil = 0, ++ .dynamic = true, ++ }, ++ { ++ /* Buffer configuration for the BM port ID 1-7 of EDMA. */ ++ .port_id_start = 1, ++ .port_id_end = 7, ++ .pre_alloc = 0, ++ .in_fly_buf = 100, ++ .ceil = 250, ++ .weight = 4, ++ .resume_offset = 36, ++ .resume_ceil = 0, ++ .dynamic = true, ++ }, ++ { ++ /* Buffer configuration for the BM port ID 8-13 of PPE ports. */ ++ .port_id_start = 8, ++ .port_id_end = 13, ++ .pre_alloc = 0, ++ .in_fly_buf = 128, ++ .ceil = 250, ++ .weight = 4, ++ .resume_offset = 36, ++ .resume_ceil = 0, ++ .dynamic = true, ++ }, ++ { ++ /* Buffer configuration for the BM port ID 14 of EIP. */ ++ .port_id_start = 14, ++ .port_id_end = 14, ++ .pre_alloc = 0, ++ .in_fly_buf = 40, ++ .ceil = 250, ++ .weight = 4, ++ .resume_offset = 36, ++ .resume_ceil = 0, ++ .dynamic = true, ++ }, ++}; ++ ++static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id, ++ const struct ppe_bm_port_config port_cfg) ++{ ++ u32 reg, val, bm_fc_val[2]; ++ int ret; ++ ++ reg = PPE_BM_PORT_FC_CFG_TBL_ADDR + PPE_BM_PORT_FC_CFG_TBL_INC * bm_port_id; ++ ret = regmap_bulk_read(ppe_dev->regmap, reg, ++ bm_fc_val, ARRAY_SIZE(bm_fc_val)); ++ if (ret) ++ return ret; ++ ++ /* Configure BM flow control related threshold. */ ++ PPE_BM_PORT_FC_SET_WEIGHT(bm_fc_val, port_cfg.weight); ++ PPE_BM_PORT_FC_SET_RESUME_OFFSET(bm_fc_val, port_cfg.resume_offset); ++ PPE_BM_PORT_FC_SET_RESUME_THRESHOLD(bm_fc_val, port_cfg.resume_ceil); ++ PPE_BM_PORT_FC_SET_DYNAMIC(bm_fc_val, port_cfg.dynamic); ++ PPE_BM_PORT_FC_SET_REACT_LIMIT(bm_fc_val, port_cfg.in_fly_buf); ++ PPE_BM_PORT_FC_SET_PRE_ALLOC(bm_fc_val, port_cfg.pre_alloc); ++ ++ /* Configure low/high bits of the ceiling for the BM port. */ ++ val = FIELD_GET(GENMASK(2, 0), port_cfg.ceil); ++ PPE_BM_PORT_FC_SET_CEILING_LOW(bm_fc_val, val); ++ val = FIELD_GET(GENMASK(10, 3), port_cfg.ceil); ++ PPE_BM_PORT_FC_SET_CEILING_HIGH(bm_fc_val, val); ++ ++ ret = regmap_bulk_write(ppe_dev->regmap, reg, ++ bm_fc_val, ARRAY_SIZE(bm_fc_val)); ++ if (ret) ++ return ret; ++ ++ /* Assign the default group ID 0 to the BM port. */ ++ val = FIELD_PREP(PPE_BM_PORT_GROUP_ID_SHARED_GROUP_ID, 0); ++ reg = PPE_BM_PORT_GROUP_ID_ADDR + PPE_BM_PORT_GROUP_ID_INC * bm_port_id; ++ ret = regmap_update_bits(ppe_dev->regmap, reg, ++ PPE_BM_PORT_GROUP_ID_SHARED_GROUP_ID, ++ val); ++ if (ret) ++ return ret; ++ ++ /* Enable BM port flow control. */ ++ reg = PPE_BM_PORT_FC_MODE_ADDR + PPE_BM_PORT_FC_MODE_INC * bm_port_id; ++ ++ return regmap_set_bits(ppe_dev->regmap, reg, PPE_BM_PORT_FC_MODE_EN); ++} ++ ++/* Configure the buffer threshold for the port flow control function. */ ++static int ppe_config_bm(struct ppe_device *ppe_dev) ++{ ++ const struct ppe_bm_port_config *port_cfg; ++ unsigned int i, bm_port_id, port_cfg_cnt; ++ u32 reg, val; ++ int ret; ++ ++ /* Configure the allocated buffer number only for group 0. ++ * The buffer number of group 1-3 is already cleared to 0 ++ * after PPE reset during the probe of PPE driver. ++ */ ++ reg = PPE_BM_SHARED_GROUP_CFG_ADDR; ++ val = FIELD_PREP(PPE_BM_SHARED_GROUP_CFG_SHARED_LIMIT, ++ ipq9574_ppe_bm_group_config); ++ ret = regmap_update_bits(ppe_dev->regmap, reg, ++ PPE_BM_SHARED_GROUP_CFG_SHARED_LIMIT, ++ val); ++ if (ret) ++ goto bm_config_fail; ++ ++ /* Configure buffer thresholds for the BM ports. */ ++ port_cfg = ipq9574_ppe_bm_port_config; ++ port_cfg_cnt = ARRAY_SIZE(ipq9574_ppe_bm_port_config); ++ for (i = 0; i < port_cfg_cnt; i++) { ++ for (bm_port_id = port_cfg[i].port_id_start; ++ bm_port_id <= port_cfg[i].port_id_end; bm_port_id++) { ++ ret = ppe_config_bm_threshold(ppe_dev, bm_port_id, ++ port_cfg[i]); ++ if (ret) ++ goto bm_config_fail; ++ } ++ } ++ ++ return 0; ++ ++bm_config_fail: ++ dev_err(ppe_dev->dev, "PPE BM config error %d\n", ret); ++ return ret; ++} ++ ++int ppe_hw_config(struct ppe_device *ppe_dev) ++{ ++ return ppe_config_bm(ppe_dev); ++} +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * ++ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#ifndef __PPE_CONFIG_H__ ++#define __PPE_CONFIG_H__ ++ ++#include "ppe.h" ++ ++int ppe_hw_config(struct ppe_device *ppe_dev); ++#endif +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -0,0 +1,59 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * ++ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* PPE hardware register and table declarations. */ ++#ifndef __PPE_REGS_H__ ++#define __PPE_REGS_H__ ++ ++#include ++ ++/* There are 15 BM ports and 4 BM groups supported by PPE. ++ * BM port (0-7) is for EDMA port 0, BM port (8-13) is for ++ * PPE physical port 1-6 and BM port 14 is for EIP port. ++ */ ++#define PPE_BM_PORT_FC_MODE_ADDR 0x600100 ++#define PPE_BM_PORT_FC_MODE_ENTRIES 15 ++#define PPE_BM_PORT_FC_MODE_INC 0x4 ++#define PPE_BM_PORT_FC_MODE_EN BIT(0) ++ ++#define PPE_BM_PORT_GROUP_ID_ADDR 0x600180 ++#define PPE_BM_PORT_GROUP_ID_ENTRIES 15 ++#define PPE_BM_PORT_GROUP_ID_INC 0x4 ++#define PPE_BM_PORT_GROUP_ID_SHARED_GROUP_ID GENMASK(1, 0) ++ ++#define PPE_BM_SHARED_GROUP_CFG_ADDR 0x600290 ++#define PPE_BM_SHARED_GROUP_CFG_ENTRIES 4 ++#define PPE_BM_SHARED_GROUP_CFG_INC 0x4 ++#define PPE_BM_SHARED_GROUP_CFG_SHARED_LIMIT GENMASK(10, 0) ++ ++#define PPE_BM_PORT_FC_CFG_TBL_ADDR 0x601000 ++#define PPE_BM_PORT_FC_CFG_TBL_ENTRIES 15 ++#define PPE_BM_PORT_FC_CFG_TBL_INC 0x10 ++#define PPE_BM_PORT_FC_W0_REACT_LIMIT GENMASK(8, 0) ++#define PPE_BM_PORT_FC_W0_RESUME_THRESHOLD GENMASK(17, 9) ++#define PPE_BM_PORT_FC_W0_RESUME_OFFSET GENMASK(28, 18) ++#define PPE_BM_PORT_FC_W0_CEILING_LOW GENMASK(31, 29) ++#define PPE_BM_PORT_FC_W1_CEILING_HIGH GENMASK(7, 0) ++#define PPE_BM_PORT_FC_W1_WEIGHT GENMASK(10, 8) ++#define PPE_BM_PORT_FC_W1_DYNAMIC BIT(11) ++#define PPE_BM_PORT_FC_W1_PRE_ALLOC GENMASK(22, 12) ++ ++#define PPE_BM_PORT_FC_SET_REACT_LIMIT(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_BM_PORT_FC_W0_REACT_LIMIT) ++#define PPE_BM_PORT_FC_SET_RESUME_THRESHOLD(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_BM_PORT_FC_W0_RESUME_THRESHOLD) ++#define PPE_BM_PORT_FC_SET_RESUME_OFFSET(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_BM_PORT_FC_W0_RESUME_OFFSET) ++#define PPE_BM_PORT_FC_SET_CEILING_LOW(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_BM_PORT_FC_W0_CEILING_LOW) ++#define PPE_BM_PORT_FC_SET_CEILING_HIGH(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_BM_PORT_FC_W1_CEILING_HIGH) ++#define PPE_BM_PORT_FC_SET_WEIGHT(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_BM_PORT_FC_W1_WEIGHT) ++#define PPE_BM_PORT_FC_SET_DYNAMIC(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_BM_PORT_FC_W1_DYNAMIC) ++#define PPE_BM_PORT_FC_SET_PRE_ALLOC(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_BM_PORT_FC_W1_PRE_ALLOC) ++#endif diff --git a/target/linux/qualcommbe/patches-6.12/0327-net-ethernet-qualcomm-Initialize-PPE-queue-managemen.patch b/target/linux/qualcommbe/patches-6.12/0327-net-ethernet-qualcomm-Initialize-PPE-queue-managemen.patch new file mode 100644 index 0000000000..be16222b96 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0327-net-ethernet-qualcomm-Initialize-PPE-queue-managemen.patch @@ -0,0 +1,320 @@ +From 9be6c3590ef3c241e6a3cfd05291304a1f973bcf Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Sun, 9 Feb 2025 22:29:39 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Initialize PPE queue management for + IPQ9574 + +QM (queue management) configurations decide the length of PPE +queues and the queue depth for these queues which are used to +drop packets in events of congestion. + +There are two types of PPE queues - unicast queues (0-255) and +multicast queues (256-299). These queue types are used to forward +different types of traffic, and are configured with different +lengths. + +Signed-off-by: Luo Jie +--- + .../net/ethernet/qualcomm/ppe/ppe_config.c | 177 +++++++++++++++++- + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 85 +++++++++ + 2 files changed, 261 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +@@ -43,6 +43,29 @@ struct ppe_bm_port_config { + bool dynamic; + }; + ++/** ++ * struct ppe_qm_queue_config - PPE queue config. ++ * @queue_start: PPE start of queue ID. ++ * @queue_end: PPE end of queue ID. ++ * @prealloc_buf: Queue dedicated buffer number. ++ * @ceil: Ceil to start drop packet from queue. ++ * @weight: Weight value. ++ * @resume_offset: Resume offset from the threshold. ++ * @dynamic: Threshold value is decided dynamically or statically. ++ * ++ * Queue configuration decides the threshold to drop packet from PPE ++ * hardware queue. ++ */ ++struct ppe_qm_queue_config { ++ unsigned int queue_start; ++ unsigned int queue_end; ++ unsigned int prealloc_buf; ++ unsigned int ceil; ++ unsigned int weight; ++ unsigned int resume_offset; ++ bool dynamic; ++}; ++ + /* Assign the share buffer number 1550 to group 0 by default. */ + static const int ipq9574_ppe_bm_group_config = 1550; + +@@ -102,6 +125,33 @@ static const struct ppe_bm_port_config i + }, + }; + ++/* Default QM group settings for IPQ9754. */ ++static const int ipq9574_ppe_qm_group_config = 2000; ++ ++/* Default QM settings for unicast and multicast queues for IPQ9754. */ ++static const struct ppe_qm_queue_config ipq9574_ppe_qm_queue_config[] = { ++ { ++ /* QM settings for unicast queues 0 to 255. */ ++ .queue_start = 0, ++ .queue_end = 255, ++ .prealloc_buf = 0, ++ .ceil = 1200, ++ .weight = 7, ++ .resume_offset = 36, ++ .dynamic = true, ++ }, ++ { ++ /* QM settings for multicast queues 256 to 299. */ ++ .queue_start = 256, ++ .queue_end = 299, ++ .prealloc_buf = 0, ++ .ceil = 250, ++ .weight = 0, ++ .resume_offset = 36, ++ .dynamic = false, ++ }, ++}; ++ + static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id, + const struct ppe_bm_port_config port_cfg) + { +@@ -189,7 +239,132 @@ bm_config_fail: + return ret; + } + ++/* Configure PPE hardware queue depth, which is decided by the threshold ++ * of queue. ++ */ ++static int ppe_config_qm(struct ppe_device *ppe_dev) ++{ ++ const struct ppe_qm_queue_config *queue_cfg; ++ int ret, i, queue_id, queue_cfg_count; ++ u32 reg, multicast_queue_cfg[5]; ++ u32 unicast_queue_cfg[4]; ++ u32 group_cfg[3]; ++ ++ /* Assign the buffer number to the group 0 by default. */ ++ reg = PPE_AC_GRP_CFG_TBL_ADDR; ++ ret = regmap_bulk_read(ppe_dev->regmap, reg, ++ group_cfg, ARRAY_SIZE(group_cfg)); ++ if (ret) ++ goto qm_config_fail; ++ ++ PPE_AC_GRP_SET_BUF_LIMIT(group_cfg, ipq9574_ppe_qm_group_config); ++ ++ ret = regmap_bulk_write(ppe_dev->regmap, reg, ++ group_cfg, ARRAY_SIZE(group_cfg)); ++ if (ret) ++ goto qm_config_fail; ++ ++ queue_cfg = ipq9574_ppe_qm_queue_config; ++ queue_cfg_count = ARRAY_SIZE(ipq9574_ppe_qm_queue_config); ++ for (i = 0; i < queue_cfg_count; i++) { ++ queue_id = queue_cfg[i].queue_start; ++ ++ /* Configure threshold for dropping packets separately for ++ * unicast and multicast PPE queues. ++ */ ++ while (queue_id <= queue_cfg[i].queue_end) { ++ if (queue_id < PPE_AC_UNICAST_QUEUE_CFG_TBL_ENTRIES) { ++ reg = PPE_AC_UNICAST_QUEUE_CFG_TBL_ADDR + ++ PPE_AC_UNICAST_QUEUE_CFG_TBL_INC * queue_id; ++ ++ ret = regmap_bulk_read(ppe_dev->regmap, reg, ++ unicast_queue_cfg, ++ ARRAY_SIZE(unicast_queue_cfg)); ++ if (ret) ++ goto qm_config_fail; ++ ++ PPE_AC_UNICAST_QUEUE_SET_EN(unicast_queue_cfg, true); ++ PPE_AC_UNICAST_QUEUE_SET_GRP_ID(unicast_queue_cfg, 0); ++ PPE_AC_UNICAST_QUEUE_SET_PRE_LIMIT(unicast_queue_cfg, ++ queue_cfg[i].prealloc_buf); ++ PPE_AC_UNICAST_QUEUE_SET_DYNAMIC(unicast_queue_cfg, ++ queue_cfg[i].dynamic); ++ PPE_AC_UNICAST_QUEUE_SET_WEIGHT(unicast_queue_cfg, ++ queue_cfg[i].weight); ++ PPE_AC_UNICAST_QUEUE_SET_THRESHOLD(unicast_queue_cfg, ++ queue_cfg[i].ceil); ++ PPE_AC_UNICAST_QUEUE_SET_GRN_RESUME(unicast_queue_cfg, ++ queue_cfg[i].resume_offset); ++ ++ ret = regmap_bulk_write(ppe_dev->regmap, reg, ++ unicast_queue_cfg, ++ ARRAY_SIZE(unicast_queue_cfg)); ++ if (ret) ++ goto qm_config_fail; ++ } else { ++ reg = PPE_AC_MULTICAST_QUEUE_CFG_TBL_ADDR + ++ PPE_AC_MULTICAST_QUEUE_CFG_TBL_INC * queue_id; ++ ++ ret = regmap_bulk_read(ppe_dev->regmap, reg, ++ multicast_queue_cfg, ++ ARRAY_SIZE(multicast_queue_cfg)); ++ if (ret) ++ goto qm_config_fail; ++ ++ PPE_AC_MULTICAST_QUEUE_SET_EN(multicast_queue_cfg, true); ++ PPE_AC_MULTICAST_QUEUE_SET_GRN_GRP_ID(multicast_queue_cfg, 0); ++ PPE_AC_MULTICAST_QUEUE_SET_GRN_PRE_LIMIT(multicast_queue_cfg, ++ queue_cfg[i].prealloc_buf); ++ PPE_AC_MULTICAST_QUEUE_SET_GRN_THRESHOLD(multicast_queue_cfg, ++ queue_cfg[i].ceil); ++ PPE_AC_MULTICAST_QUEUE_SET_GRN_RESUME(multicast_queue_cfg, ++ queue_cfg[i].resume_offset); ++ ++ ret = regmap_bulk_write(ppe_dev->regmap, reg, ++ multicast_queue_cfg, ++ ARRAY_SIZE(multicast_queue_cfg)); ++ if (ret) ++ goto qm_config_fail; ++ } ++ ++ /* Enable enqueue. */ ++ reg = PPE_ENQ_OPR_TBL_ADDR + PPE_ENQ_OPR_TBL_INC * queue_id; ++ ret = regmap_clear_bits(ppe_dev->regmap, reg, ++ PPE_ENQ_OPR_TBL_ENQ_DISABLE); ++ if (ret) ++ goto qm_config_fail; ++ ++ /* Enable dequeue. */ ++ reg = PPE_DEQ_OPR_TBL_ADDR + PPE_DEQ_OPR_TBL_INC * queue_id; ++ ret = regmap_clear_bits(ppe_dev->regmap, reg, ++ PPE_DEQ_OPR_TBL_DEQ_DISABLE); ++ if (ret) ++ goto qm_config_fail; ++ ++ queue_id++; ++ } ++ } ++ ++ /* Enable queue counter for all PPE hardware queues. */ ++ ret = regmap_set_bits(ppe_dev->regmap, PPE_EG_BRIDGE_CONFIG_ADDR, ++ PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN); ++ if (ret) ++ goto qm_config_fail; ++ ++ return 0; ++ ++qm_config_fail: ++ dev_err(ppe_dev->dev, "PPE QM config error %d\n", ret); ++ return ret; ++} ++ + int ppe_hw_config(struct ppe_device *ppe_dev) + { +- return ppe_config_bm(ppe_dev); ++ int ret; ++ ++ ret = ppe_config_bm(ppe_dev); ++ if (ret) ++ return ret; ++ ++ return ppe_config_qm(ppe_dev); + } +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -9,6 +9,16 @@ + + #include + ++/* PPE queue counters enable/disable control. */ ++#define PPE_EG_BRIDGE_CONFIG_ADDR 0x20044 ++#define PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN BIT(2) ++ ++/* Table addresses for per-queue dequeue setting. */ ++#define PPE_DEQ_OPR_TBL_ADDR 0x430000 ++#define PPE_DEQ_OPR_TBL_ENTRIES 300 ++#define PPE_DEQ_OPR_TBL_INC 0x10 ++#define PPE_DEQ_OPR_TBL_DEQ_DISABLE BIT(0) ++ + /* There are 15 BM ports and 4 BM groups supported by PPE. + * BM port (0-7) is for EDMA port 0, BM port (8-13) is for + * PPE physical port 1-6 and BM port 14 is for EIP port. +@@ -56,4 +66,79 @@ + u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_BM_PORT_FC_W1_DYNAMIC) + #define PPE_BM_PORT_FC_SET_PRE_ALLOC(tbl_cfg, value) \ + u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_BM_PORT_FC_W1_PRE_ALLOC) ++ ++/* PPE unicast queue (0-255) configurations. */ ++#define PPE_AC_UNICAST_QUEUE_CFG_TBL_ADDR 0x848000 ++#define PPE_AC_UNICAST_QUEUE_CFG_TBL_ENTRIES 256 ++#define PPE_AC_UNICAST_QUEUE_CFG_TBL_INC 0x10 ++#define PPE_AC_UNICAST_QUEUE_CFG_W0_EN BIT(0) ++#define PPE_AC_UNICAST_QUEUE_CFG_W0_WRED_EN BIT(1) ++#define PPE_AC_UNICAST_QUEUE_CFG_W0_FC_EN BIT(2) ++#define PPE_AC_UNICAST_QUEUE_CFG_W0_CLR_AWARE BIT(3) ++#define PPE_AC_UNICAST_QUEUE_CFG_W0_GRP_ID GENMASK(5, 4) ++#define PPE_AC_UNICAST_QUEUE_CFG_W0_PRE_LIMIT GENMASK(16, 6) ++#define PPE_AC_UNICAST_QUEUE_CFG_W0_DYNAMIC BIT(17) ++#define PPE_AC_UNICAST_QUEUE_CFG_W0_WEIGHT GENMASK(20, 18) ++#define PPE_AC_UNICAST_QUEUE_CFG_W0_THRESHOLD GENMASK(31, 21) ++#define PPE_AC_UNICAST_QUEUE_CFG_W3_GRN_RESUME GENMASK(23, 13) ++ ++#define PPE_AC_UNICAST_QUEUE_SET_EN(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_UNICAST_QUEUE_CFG_W0_EN) ++#define PPE_AC_UNICAST_QUEUE_SET_GRP_ID(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_UNICAST_QUEUE_CFG_W0_GRP_ID) ++#define PPE_AC_UNICAST_QUEUE_SET_PRE_LIMIT(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_UNICAST_QUEUE_CFG_W0_PRE_LIMIT) ++#define PPE_AC_UNICAST_QUEUE_SET_DYNAMIC(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_UNICAST_QUEUE_CFG_W0_DYNAMIC) ++#define PPE_AC_UNICAST_QUEUE_SET_WEIGHT(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_UNICAST_QUEUE_CFG_W0_WEIGHT) ++#define PPE_AC_UNICAST_QUEUE_SET_THRESHOLD(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_UNICAST_QUEUE_CFG_W0_THRESHOLD) ++#define PPE_AC_UNICAST_QUEUE_SET_GRN_RESUME(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x3, value, PPE_AC_UNICAST_QUEUE_CFG_W3_GRN_RESUME) ++ ++/* PPE multicast queue (256-299) configurations. */ ++#define PPE_AC_MULTICAST_QUEUE_CFG_TBL_ADDR 0x84a000 ++#define PPE_AC_MULTICAST_QUEUE_CFG_TBL_ENTRIES 44 ++#define PPE_AC_MULTICAST_QUEUE_CFG_TBL_INC 0x10 ++#define PPE_AC_MULTICAST_QUEUE_CFG_W0_EN BIT(0) ++#define PPE_AC_MULTICAST_QUEUE_CFG_W0_FC_EN BIT(1) ++#define PPE_AC_MULTICAST_QUEUE_CFG_W0_CLR_AWARE BIT(2) ++#define PPE_AC_MULTICAST_QUEUE_CFG_W0_GRP_ID GENMASK(4, 3) ++#define PPE_AC_MULTICAST_QUEUE_CFG_W0_PRE_LIMIT GENMASK(15, 5) ++#define PPE_AC_MULTICAST_QUEUE_CFG_W0_THRESHOLD GENMASK(26, 16) ++#define PPE_AC_MULTICAST_QUEUE_CFG_W2_RESUME GENMASK(17, 7) ++ ++#define PPE_AC_MULTICAST_QUEUE_SET_EN(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_MULTICAST_QUEUE_CFG_W0_EN) ++#define PPE_AC_MULTICAST_QUEUE_SET_GRN_GRP_ID(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_MULTICAST_QUEUE_CFG_W0_GRP_ID) ++#define PPE_AC_MULTICAST_QUEUE_SET_GRN_PRE_LIMIT(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_MULTICAST_QUEUE_CFG_W0_PRE_LIMIT) ++#define PPE_AC_MULTICAST_QUEUE_SET_GRN_THRESHOLD(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_MULTICAST_QUEUE_CFG_W0_THRESHOLD) ++#define PPE_AC_MULTICAST_QUEUE_SET_GRN_RESUME(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x2, value, PPE_AC_MULTICAST_QUEUE_CFG_W2_RESUME) ++ ++/* PPE admission control group (0-3) configurations */ ++#define PPE_AC_GRP_CFG_TBL_ADDR 0x84c000 ++#define PPE_AC_GRP_CFG_TBL_ENTRIES 0x4 ++#define PPE_AC_GRP_CFG_TBL_INC 0x10 ++#define PPE_AC_GRP_W0_AC_EN BIT(0) ++#define PPE_AC_GRP_W0_AC_FC_EN BIT(1) ++#define PPE_AC_GRP_W0_CLR_AWARE BIT(2) ++#define PPE_AC_GRP_W0_THRESHOLD_LOW GENMASK(31, 25) ++#define PPE_AC_GRP_W1_THRESHOLD_HIGH GENMASK(3, 0) ++#define PPE_AC_GRP_W1_BUF_LIMIT GENMASK(14, 4) ++#define PPE_AC_GRP_W2_RESUME_GRN GENMASK(15, 5) ++#define PPE_AC_GRP_W2_PRE_ALLOC GENMASK(26, 16) ++ ++#define PPE_AC_GRP_SET_BUF_LIMIT(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_AC_GRP_W1_BUF_LIMIT) ++ ++/* Table addresses for per-queue enqueue setting. */ ++#define PPE_ENQ_OPR_TBL_ADDR 0x85c000 ++#define PPE_ENQ_OPR_TBL_ENTRIES 300 ++#define PPE_ENQ_OPR_TBL_INC 0x10 ++#define PPE_ENQ_OPR_TBL_ENQ_DISABLE BIT(0) + #endif diff --git a/target/linux/qualcommbe/patches-6.12/0328-net-ethernet-qualcomm-Initialize-the-PPE-scheduler-s.patch b/target/linux/qualcommbe/patches-6.12/0328-net-ethernet-qualcomm-Initialize-the-PPE-scheduler-s.patch new file mode 100644 index 0000000000..86949a2f3b --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0328-net-ethernet-qualcomm-Initialize-the-PPE-scheduler-s.patch @@ -0,0 +1,1000 @@ +From 333edaf474cd707b0a04c57f255b56bc3c015789 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Sun, 9 Feb 2025 22:29:40 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Initialize the PPE scheduler + settings + +The PPE scheduler settings determine the priority of scheduling the +packet across the different hardware queues per PPE port. + +Signed-off-by: Luo Jie +--- + .../net/ethernet/qualcomm/ppe/ppe_config.c | 788 +++++++++++++++++- + .../net/ethernet/qualcomm/ppe/ppe_config.h | 37 + + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 97 +++ + 3 files changed, 921 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +@@ -16,6 +16,8 @@ + #include "ppe_config.h" + #include "ppe_regs.h" + ++#define PPE_QUEUE_SCH_PRI_NUM 8 ++ + /** + * struct ppe_bm_port_config - PPE BM port configuration. + * @port_id_start: The fist BM port ID to configure. +@@ -66,6 +68,66 @@ struct ppe_qm_queue_config { + bool dynamic; + }; + ++/** ++ * struct ppe_scheduler_bm_config - PPE arbitration for buffer config. ++ * @valid: Arbitration entry valid or not. ++ * @is_egress: Arbitration entry for egress or not. ++ * @port: Port ID to use arbitration entry. ++ * @second_valid: Second port valid or not. ++ * @second_port: Second port to use. ++ * ++ * Configure the scheduler settings for accessing and releasing the PPE buffers. ++ */ ++struct ppe_scheduler_bm_config { ++ bool valid; ++ bool is_egress; ++ unsigned int port; ++ bool second_valid; ++ unsigned int second_port; ++}; ++ ++/** ++ * struct ppe_scheduler_qm_config - PPE arbitration for scheduler config. ++ * @ensch_port_bmp: Port bit map for enqueue scheduler. ++ * @ensch_port: Port ID to enqueue scheduler. ++ * @desch_port: Port ID to dequeue scheduler. ++ * @desch_second_valid: Dequeue for the second port valid or not. ++ * @desch_second_port: Second port ID to dequeue scheduler. ++ * ++ * Configure the scheduler settings for enqueuing and dequeuing packets on ++ * the PPE port. ++ */ ++struct ppe_scheduler_qm_config { ++ unsigned int ensch_port_bmp; ++ unsigned int ensch_port; ++ unsigned int desch_port; ++ bool desch_second_valid; ++ unsigned int desch_second_port; ++}; ++ ++/** ++ * struct ppe_scheduler_port_config - PPE port scheduler config. ++ * @port: Port ID to be scheduled. ++ * @flow_level: Scheduler flow level or not. ++ * @node_id: Node ID, for level 0, queue ID is used. ++ * @loop_num: Loop number of scheduler config. ++ * @pri_max: Max priority configured. ++ * @flow_id: Strict priority ID. ++ * @drr_node_id: Node ID for scheduler. ++ * ++ * PPE port scheduler configuration which decides the priority in the ++ * packet scheduler for the egress port. ++ */ ++struct ppe_scheduler_port_config { ++ unsigned int port; ++ bool flow_level; ++ unsigned int node_id; ++ unsigned int loop_num; ++ unsigned int pri_max; ++ unsigned int flow_id; ++ unsigned int drr_node_id; ++}; ++ + /* Assign the share buffer number 1550 to group 0 by default. */ + static const int ipq9574_ppe_bm_group_config = 1550; + +@@ -152,6 +214,599 @@ static const struct ppe_qm_queue_config + }, + }; + ++/* Scheduler configuration for the assigning and releasing buffers for the ++ * packet passing through PPE, which is different per SoC. ++ */ ++static const struct ppe_scheduler_bm_config ipq9574_ppe_sch_bm_config[] = { ++ {1, 0, 0, 0, 0}, ++ {1, 1, 0, 0, 0}, ++ {1, 0, 5, 0, 0}, ++ {1, 1, 5, 0, 0}, ++ {1, 0, 6, 0, 0}, ++ {1, 1, 6, 0, 0}, ++ {1, 0, 1, 0, 0}, ++ {1, 1, 1, 0, 0}, ++ {1, 0, 0, 0, 0}, ++ {1, 1, 0, 0, 0}, ++ {1, 0, 5, 0, 0}, ++ {1, 1, 5, 0, 0}, ++ {1, 0, 6, 0, 0}, ++ {1, 1, 6, 0, 0}, ++ {1, 0, 7, 0, 0}, ++ {1, 1, 7, 0, 0}, ++ {1, 0, 0, 0, 0}, ++ {1, 1, 0, 0, 0}, ++ {1, 0, 1, 0, 0}, ++ {1, 1, 1, 0, 0}, ++ {1, 0, 5, 0, 0}, ++ {1, 1, 5, 0, 0}, ++ {1, 0, 6, 0, 0}, ++ {1, 1, 6, 0, 0}, ++ {1, 0, 2, 0, 0}, ++ {1, 1, 2, 0, 0}, ++ {1, 0, 0, 0, 0}, ++ {1, 1, 0, 0, 0}, ++ {1, 0, 5, 0, 0}, ++ {1, 1, 5, 0, 0}, ++ {1, 0, 6, 0, 0}, ++ {1, 1, 6, 0, 0}, ++ {1, 0, 1, 0, 0}, ++ {1, 1, 1, 0, 0}, ++ {1, 0, 3, 0, 0}, ++ {1, 1, 3, 0, 0}, ++ {1, 0, 0, 0, 0}, ++ {1, 1, 0, 0, 0}, ++ {1, 0, 5, 0, 0}, ++ {1, 1, 5, 0, 0}, ++ {1, 0, 6, 0, 0}, ++ {1, 1, 6, 0, 0}, ++ {1, 0, 7, 0, 0}, ++ {1, 1, 7, 0, 0}, ++ {1, 0, 0, 0, 0}, ++ {1, 1, 0, 0, 0}, ++ {1, 0, 1, 0, 0}, ++ {1, 1, 1, 0, 0}, ++ {1, 0, 5, 0, 0}, ++ {1, 1, 5, 0, 0}, ++ {1, 0, 6, 0, 0}, ++ {1, 1, 6, 0, 0}, ++ {1, 0, 4, 0, 0}, ++ {1, 1, 4, 0, 0}, ++ {1, 0, 0, 0, 0}, ++ {1, 1, 0, 0, 0}, ++ {1, 0, 5, 0, 0}, ++ {1, 1, 5, 0, 0}, ++ {1, 0, 6, 0, 0}, ++ {1, 1, 6, 0, 0}, ++ {1, 0, 1, 0, 0}, ++ {1, 1, 1, 0, 0}, ++ {1, 0, 0, 0, 0}, ++ {1, 1, 0, 0, 0}, ++ {1, 0, 5, 0, 0}, ++ {1, 1, 5, 0, 0}, ++ {1, 0, 6, 0, 0}, ++ {1, 1, 6, 0, 0}, ++ {1, 0, 2, 0, 0}, ++ {1, 1, 2, 0, 0}, ++ {1, 0, 0, 0, 0}, ++ {1, 1, 0, 0, 0}, ++ {1, 0, 7, 0, 0}, ++ {1, 1, 7, 0, 0}, ++ {1, 0, 5, 0, 0}, ++ {1, 1, 5, 0, 0}, ++ {1, 0, 6, 0, 0}, ++ {1, 1, 6, 0, 0}, ++ {1, 0, 1, 0, 0}, ++ {1, 1, 1, 0, 0}, ++ {1, 0, 0, 0, 0}, ++ {1, 1, 0, 0, 0}, ++ {1, 0, 5, 0, 0}, ++ {1, 1, 5, 0, 0}, ++ {1, 0, 6, 0, 0}, ++ {1, 1, 6, 0, 0}, ++ {1, 0, 3, 0, 0}, ++ {1, 1, 3, 0, 0}, ++ {1, 0, 1, 0, 0}, ++ {1, 1, 1, 0, 0}, ++ {1, 0, 0, 0, 0}, ++ {1, 1, 0, 0, 0}, ++ {1, 0, 5, 0, 0}, ++ {1, 1, 5, 0, 0}, ++ {1, 0, 6, 0, 0}, ++ {1, 1, 6, 0, 0}, ++ {1, 0, 4, 0, 0}, ++ {1, 1, 4, 0, 0}, ++ {1, 0, 7, 0, 0}, ++ {1, 1, 7, 0, 0}, ++}; ++ ++/* Scheduler configuration for dispatching packet on PPE queues, which ++ * is different per SoC. ++ */ ++static const struct ppe_scheduler_qm_config ipq9574_ppe_sch_qm_config[] = { ++ {0x98, 6, 0, 1, 1}, ++ {0x94, 5, 6, 1, 3}, ++ {0x86, 0, 5, 1, 4}, ++ {0x8C, 1, 6, 1, 0}, ++ {0x1C, 7, 5, 1, 1}, ++ {0x98, 2, 6, 1, 0}, ++ {0x1C, 5, 7, 1, 1}, ++ {0x34, 3, 6, 1, 0}, ++ {0x8C, 4, 5, 1, 1}, ++ {0x98, 2, 6, 1, 0}, ++ {0x8C, 5, 4, 1, 1}, ++ {0xA8, 0, 6, 1, 2}, ++ {0x98, 5, 1, 1, 0}, ++ {0x98, 6, 5, 1, 2}, ++ {0x89, 1, 6, 1, 4}, ++ {0xA4, 3, 0, 1, 1}, ++ {0x8C, 5, 6, 1, 4}, ++ {0xA8, 0, 2, 1, 1}, ++ {0x98, 6, 5, 1, 0}, ++ {0xC4, 4, 3, 1, 1}, ++ {0x94, 6, 5, 1, 0}, ++ {0x1C, 7, 6, 1, 1}, ++ {0x98, 2, 5, 1, 0}, ++ {0x1C, 6, 7, 1, 1}, ++ {0x1C, 5, 6, 1, 0}, ++ {0x94, 3, 5, 1, 1}, ++ {0x8C, 4, 6, 1, 0}, ++ {0x94, 1, 5, 1, 3}, ++ {0x94, 6, 1, 1, 0}, ++ {0xD0, 3, 5, 1, 2}, ++ {0x98, 6, 0, 1, 1}, ++ {0x94, 5, 6, 1, 3}, ++ {0x94, 1, 5, 1, 0}, ++ {0x98, 2, 6, 1, 1}, ++ {0x8C, 4, 5, 1, 0}, ++ {0x1C, 7, 6, 1, 1}, ++ {0x8C, 0, 5, 1, 4}, ++ {0x89, 1, 6, 1, 2}, ++ {0x98, 5, 0, 1, 1}, ++ {0x94, 6, 5, 1, 3}, ++ {0x92, 0, 6, 1, 2}, ++ {0x98, 1, 5, 1, 0}, ++ {0x98, 6, 2, 1, 1}, ++ {0xD0, 0, 5, 1, 3}, ++ {0x94, 6, 0, 1, 1}, ++ {0x8C, 5, 6, 1, 4}, ++ {0x8C, 1, 5, 1, 0}, ++ {0x1C, 6, 7, 1, 1}, ++ {0x1C, 5, 6, 1, 0}, ++ {0xB0, 2, 3, 1, 1}, ++ {0xC4, 4, 5, 1, 0}, ++ {0x8C, 6, 4, 1, 1}, ++ {0xA4, 3, 6, 1, 0}, ++ {0x1C, 5, 7, 1, 1}, ++ {0x4C, 0, 5, 1, 4}, ++ {0x8C, 6, 0, 1, 1}, ++ {0x34, 7, 6, 1, 3}, ++ {0x94, 5, 0, 1, 1}, ++ {0x98, 6, 5, 1, 2}, ++}; ++ ++static const struct ppe_scheduler_port_config ppe_port_sch_config[] = { ++ { ++ .port = 0, ++ .flow_level = true, ++ .node_id = 0, ++ .loop_num = 1, ++ .pri_max = 1, ++ .flow_id = 0, ++ .drr_node_id = 0, ++ }, ++ { ++ .port = 0, ++ .flow_level = false, ++ .node_id = 0, ++ .loop_num = 8, ++ .pri_max = 8, ++ .flow_id = 0, ++ .drr_node_id = 0, ++ }, ++ { ++ .port = 0, ++ .flow_level = false, ++ .node_id = 8, ++ .loop_num = 8, ++ .pri_max = 8, ++ .flow_id = 0, ++ .drr_node_id = 0, ++ }, ++ { ++ .port = 0, ++ .flow_level = false, ++ .node_id = 16, ++ .loop_num = 8, ++ .pri_max = 8, ++ .flow_id = 0, ++ .drr_node_id = 0, ++ }, ++ { ++ .port = 0, ++ .flow_level = false, ++ .node_id = 24, ++ .loop_num = 8, ++ .pri_max = 8, ++ .flow_id = 0, ++ .drr_node_id = 0, ++ }, ++ { ++ .port = 0, ++ .flow_level = false, ++ .node_id = 32, ++ .loop_num = 8, ++ .pri_max = 8, ++ .flow_id = 0, ++ .drr_node_id = 0, ++ }, ++ { ++ .port = 0, ++ .flow_level = false, ++ .node_id = 40, ++ .loop_num = 8, ++ .pri_max = 8, ++ .flow_id = 0, ++ .drr_node_id = 0, ++ }, ++ { ++ .port = 0, ++ .flow_level = false, ++ .node_id = 48, ++ .loop_num = 8, ++ .pri_max = 8, ++ .flow_id = 0, ++ .drr_node_id = 0, ++ }, ++ { ++ .port = 0, ++ .flow_level = false, ++ .node_id = 56, ++ .loop_num = 8, ++ .pri_max = 8, ++ .flow_id = 0, ++ .drr_node_id = 0, ++ }, ++ { ++ .port = 0, ++ .flow_level = false, ++ .node_id = 256, ++ .loop_num = 8, ++ .pri_max = 8, ++ .flow_id = 0, ++ .drr_node_id = 0, ++ }, ++ { ++ .port = 0, ++ .flow_level = false, ++ .node_id = 264, ++ .loop_num = 8, ++ .pri_max = 8, ++ .flow_id = 0, ++ .drr_node_id = 0, ++ }, ++ { ++ .port = 1, ++ .flow_level = true, ++ .node_id = 36, ++ .loop_num = 2, ++ .pri_max = 0, ++ .flow_id = 1, ++ .drr_node_id = 8, ++ }, ++ { ++ .port = 1, ++ .flow_level = false, ++ .node_id = 144, ++ .loop_num = 16, ++ .pri_max = 8, ++ .flow_id = 36, ++ .drr_node_id = 48, ++ }, ++ { ++ .port = 1, ++ .flow_level = false, ++ .node_id = 272, ++ .loop_num = 4, ++ .pri_max = 4, ++ .flow_id = 36, ++ .drr_node_id = 48, ++ }, ++ { ++ .port = 2, ++ .flow_level = true, ++ .node_id = 40, ++ .loop_num = 2, ++ .pri_max = 0, ++ .flow_id = 2, ++ .drr_node_id = 12, ++ }, ++ { ++ .port = 2, ++ .flow_level = false, ++ .node_id = 160, ++ .loop_num = 16, ++ .pri_max = 8, ++ .flow_id = 40, ++ .drr_node_id = 64, ++ }, ++ { ++ .port = 2, ++ .flow_level = false, ++ .node_id = 276, ++ .loop_num = 4, ++ .pri_max = 4, ++ .flow_id = 40, ++ .drr_node_id = 64, ++ }, ++ { ++ .port = 3, ++ .flow_level = true, ++ .node_id = 44, ++ .loop_num = 2, ++ .pri_max = 0, ++ .flow_id = 3, ++ .drr_node_id = 16, ++ }, ++ { ++ .port = 3, ++ .flow_level = false, ++ .node_id = 176, ++ .loop_num = 16, ++ .pri_max = 8, ++ .flow_id = 44, ++ .drr_node_id = 80, ++ }, ++ { ++ .port = 3, ++ .flow_level = false, ++ .node_id = 280, ++ .loop_num = 4, ++ .pri_max = 4, ++ .flow_id = 44, ++ .drr_node_id = 80, ++ }, ++ { ++ .port = 4, ++ .flow_level = true, ++ .node_id = 48, ++ .loop_num = 2, ++ .pri_max = 0, ++ .flow_id = 4, ++ .drr_node_id = 20, ++ }, ++ { ++ .port = 4, ++ .flow_level = false, ++ .node_id = 192, ++ .loop_num = 16, ++ .pri_max = 8, ++ .flow_id = 48, ++ .drr_node_id = 96, ++ }, ++ { ++ .port = 4, ++ .flow_level = false, ++ .node_id = 284, ++ .loop_num = 4, ++ .pri_max = 4, ++ .flow_id = 48, ++ .drr_node_id = 96, ++ }, ++ { ++ .port = 5, ++ .flow_level = true, ++ .node_id = 52, ++ .loop_num = 2, ++ .pri_max = 0, ++ .flow_id = 5, ++ .drr_node_id = 24, ++ }, ++ { ++ .port = 5, ++ .flow_level = false, ++ .node_id = 208, ++ .loop_num = 16, ++ .pri_max = 8, ++ .flow_id = 52, ++ .drr_node_id = 112, ++ }, ++ { ++ .port = 5, ++ .flow_level = false, ++ .node_id = 288, ++ .loop_num = 4, ++ .pri_max = 4, ++ .flow_id = 52, ++ .drr_node_id = 112, ++ }, ++ { ++ .port = 6, ++ .flow_level = true, ++ .node_id = 56, ++ .loop_num = 2, ++ .pri_max = 0, ++ .flow_id = 6, ++ .drr_node_id = 28, ++ }, ++ { ++ .port = 6, ++ .flow_level = false, ++ .node_id = 224, ++ .loop_num = 16, ++ .pri_max = 8, ++ .flow_id = 56, ++ .drr_node_id = 128, ++ }, ++ { ++ .port = 6, ++ .flow_level = false, ++ .node_id = 292, ++ .loop_num = 4, ++ .pri_max = 4, ++ .flow_id = 56, ++ .drr_node_id = 128, ++ }, ++ { ++ .port = 7, ++ .flow_level = true, ++ .node_id = 60, ++ .loop_num = 2, ++ .pri_max = 0, ++ .flow_id = 7, ++ .drr_node_id = 32, ++ }, ++ { ++ .port = 7, ++ .flow_level = false, ++ .node_id = 240, ++ .loop_num = 16, ++ .pri_max = 8, ++ .flow_id = 60, ++ .drr_node_id = 144, ++ }, ++ { ++ .port = 7, ++ .flow_level = false, ++ .node_id = 296, ++ .loop_num = 4, ++ .pri_max = 4, ++ .flow_id = 60, ++ .drr_node_id = 144, ++ }, ++}; ++ ++/* Set the PPE queue level scheduler configuration. */ ++static int ppe_scheduler_l0_queue_map_set(struct ppe_device *ppe_dev, ++ int node_id, int port, ++ struct ppe_scheduler_cfg scheduler_cfg) ++{ ++ u32 val, reg; ++ int ret; ++ ++ reg = PPE_L0_FLOW_MAP_TBL_ADDR + node_id * PPE_L0_FLOW_MAP_TBL_INC; ++ val = FIELD_PREP(PPE_L0_FLOW_MAP_TBL_FLOW_ID, scheduler_cfg.flow_id); ++ val |= FIELD_PREP(PPE_L0_FLOW_MAP_TBL_C_PRI, scheduler_cfg.pri); ++ val |= FIELD_PREP(PPE_L0_FLOW_MAP_TBL_E_PRI, scheduler_cfg.pri); ++ val |= FIELD_PREP(PPE_L0_FLOW_MAP_TBL_C_NODE_WT, scheduler_cfg.drr_node_wt); ++ val |= FIELD_PREP(PPE_L0_FLOW_MAP_TBL_E_NODE_WT, scheduler_cfg.drr_node_wt); ++ ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ return ret; ++ ++ reg = PPE_L0_C_FLOW_CFG_TBL_ADDR + ++ (scheduler_cfg.flow_id * PPE_QUEUE_SCH_PRI_NUM + scheduler_cfg.pri) * ++ PPE_L0_C_FLOW_CFG_TBL_INC; ++ val = FIELD_PREP(PPE_L0_C_FLOW_CFG_TBL_NODE_ID, scheduler_cfg.drr_node_id); ++ val |= FIELD_PREP(PPE_L0_C_FLOW_CFG_TBL_NODE_CREDIT_UNIT, scheduler_cfg.unit_is_packet); ++ ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ return ret; ++ ++ reg = PPE_L0_E_FLOW_CFG_TBL_ADDR + ++ (scheduler_cfg.flow_id * PPE_QUEUE_SCH_PRI_NUM + scheduler_cfg.pri) * ++ PPE_L0_E_FLOW_CFG_TBL_INC; ++ val = FIELD_PREP(PPE_L0_E_FLOW_CFG_TBL_NODE_ID, scheduler_cfg.drr_node_id); ++ val |= FIELD_PREP(PPE_L0_E_FLOW_CFG_TBL_NODE_CREDIT_UNIT, scheduler_cfg.unit_is_packet); ++ ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ return ret; ++ ++ reg = PPE_L0_FLOW_PORT_MAP_TBL_ADDR + node_id * PPE_L0_FLOW_PORT_MAP_TBL_INC; ++ val = FIELD_PREP(PPE_L0_FLOW_PORT_MAP_TBL_PORT_NUM, port); ++ ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ return ret; ++ ++ reg = PPE_L0_COMP_CFG_TBL_ADDR + node_id * PPE_L0_COMP_CFG_TBL_INC; ++ val = FIELD_PREP(PPE_L0_COMP_CFG_TBL_NODE_METER_LEN, scheduler_cfg.frame_mode); ++ ++ return regmap_update_bits(ppe_dev->regmap, reg, ++ PPE_L0_COMP_CFG_TBL_NODE_METER_LEN, ++ val); ++} ++ ++/* Set the PPE flow level scheduler configuration. */ ++static int ppe_scheduler_l1_queue_map_set(struct ppe_device *ppe_dev, ++ int node_id, int port, ++ struct ppe_scheduler_cfg scheduler_cfg) ++{ ++ u32 val, reg; ++ int ret; ++ ++ val = FIELD_PREP(PPE_L1_FLOW_MAP_TBL_FLOW_ID, scheduler_cfg.flow_id); ++ val |= FIELD_PREP(PPE_L1_FLOW_MAP_TBL_C_PRI, scheduler_cfg.pri); ++ val |= FIELD_PREP(PPE_L1_FLOW_MAP_TBL_E_PRI, scheduler_cfg.pri); ++ val |= FIELD_PREP(PPE_L1_FLOW_MAP_TBL_C_NODE_WT, scheduler_cfg.drr_node_wt); ++ val |= FIELD_PREP(PPE_L1_FLOW_MAP_TBL_E_NODE_WT, scheduler_cfg.drr_node_wt); ++ reg = PPE_L1_FLOW_MAP_TBL_ADDR + node_id * PPE_L1_FLOW_MAP_TBL_INC; ++ ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ return ret; ++ ++ val = FIELD_PREP(PPE_L1_C_FLOW_CFG_TBL_NODE_ID, scheduler_cfg.drr_node_id); ++ val |= FIELD_PREP(PPE_L1_C_FLOW_CFG_TBL_NODE_CREDIT_UNIT, scheduler_cfg.unit_is_packet); ++ reg = PPE_L1_C_FLOW_CFG_TBL_ADDR + ++ (scheduler_cfg.flow_id * PPE_QUEUE_SCH_PRI_NUM + scheduler_cfg.pri) * ++ PPE_L1_C_FLOW_CFG_TBL_INC; ++ ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ return ret; ++ ++ val = FIELD_PREP(PPE_L1_E_FLOW_CFG_TBL_NODE_ID, scheduler_cfg.drr_node_id); ++ val |= FIELD_PREP(PPE_L1_E_FLOW_CFG_TBL_NODE_CREDIT_UNIT, scheduler_cfg.unit_is_packet); ++ reg = PPE_L1_E_FLOW_CFG_TBL_ADDR + ++ (scheduler_cfg.flow_id * PPE_QUEUE_SCH_PRI_NUM + scheduler_cfg.pri) * ++ PPE_L1_E_FLOW_CFG_TBL_INC; ++ ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ return ret; ++ ++ val = FIELD_PREP(PPE_L1_FLOW_PORT_MAP_TBL_PORT_NUM, port); ++ reg = PPE_L1_FLOW_PORT_MAP_TBL_ADDR + node_id * PPE_L1_FLOW_PORT_MAP_TBL_INC; ++ ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ return ret; ++ ++ reg = PPE_L1_COMP_CFG_TBL_ADDR + node_id * PPE_L1_COMP_CFG_TBL_INC; ++ val = FIELD_PREP(PPE_L1_COMP_CFG_TBL_NODE_METER_LEN, scheduler_cfg.frame_mode); ++ ++ return regmap_update_bits(ppe_dev->regmap, reg, PPE_L1_COMP_CFG_TBL_NODE_METER_LEN, val); ++} ++ ++/** ++ * ppe_queue_scheduler_set - Configure scheduler for PPE hardware queue ++ * @ppe_dev: PPE device ++ * @node_id: PPE queue ID or flow ID ++ * @flow_level: Flow level scheduler or queue level scheduler ++ * @port: PPE port ID set scheduler configuration ++ * @scheduler_cfg: PPE scheduler configuration ++ * ++ * PPE scheduler configuration supports queue level and flow level on ++ * the PPE egress port. ++ * ++ * Return: 0 on success, negative error code on failure. ++ */ ++int ppe_queue_scheduler_set(struct ppe_device *ppe_dev, ++ int node_id, bool flow_level, int port, ++ struct ppe_scheduler_cfg scheduler_cfg) ++{ ++ if (flow_level) ++ return ppe_scheduler_l1_queue_map_set(ppe_dev, node_id, ++ port, scheduler_cfg); ++ ++ return ppe_scheduler_l0_queue_map_set(ppe_dev, node_id, ++ port, scheduler_cfg); ++} ++ + static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id, + const struct ppe_bm_port_config port_cfg) + { +@@ -358,6 +1013,133 @@ qm_config_fail: + return ret; + } + ++static int ppe_node_scheduler_config(struct ppe_device *ppe_dev, ++ const struct ppe_scheduler_port_config config) ++{ ++ struct ppe_scheduler_cfg sch_cfg; ++ int ret, i; ++ ++ for (i = 0; i < config.loop_num; i++) { ++ if (!config.pri_max) { ++ /* Round robin scheduler without priority. */ ++ sch_cfg.flow_id = config.flow_id; ++ sch_cfg.pri = 0; ++ sch_cfg.drr_node_id = config.drr_node_id; ++ } else { ++ sch_cfg.flow_id = config.flow_id + (i / config.pri_max); ++ sch_cfg.pri = i % config.pri_max; ++ sch_cfg.drr_node_id = config.drr_node_id + i; ++ } ++ ++ /* Scheduler weight, must be more than 0. */ ++ sch_cfg.drr_node_wt = 1; ++ /* Byte based to be scheduled. */ ++ sch_cfg.unit_is_packet = false; ++ /* Frame + CRC calculated. */ ++ sch_cfg.frame_mode = PPE_SCH_WITH_FRAME_CRC; ++ ++ ret = ppe_queue_scheduler_set(ppe_dev, config.node_id + i, ++ config.flow_level, ++ config.port, ++ sch_cfg); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++/* Initialize scheduler settings for PPE buffer utilization and dispatching ++ * packet on PPE queue. ++ */ ++static int ppe_config_scheduler(struct ppe_device *ppe_dev) ++{ ++ const struct ppe_scheduler_port_config *port_cfg; ++ const struct ppe_scheduler_qm_config *qm_cfg; ++ const struct ppe_scheduler_bm_config *bm_cfg; ++ int ret, i, count; ++ u32 val, reg; ++ ++ count = ARRAY_SIZE(ipq9574_ppe_sch_bm_config); ++ bm_cfg = ipq9574_ppe_sch_bm_config; ++ ++ /* Configure the depth of BM scheduler entries. */ ++ val = FIELD_PREP(PPE_BM_SCH_CTRL_SCH_DEPTH, count); ++ val |= FIELD_PREP(PPE_BM_SCH_CTRL_SCH_OFFSET, 0); ++ val |= FIELD_PREP(PPE_BM_SCH_CTRL_SCH_EN, 1); ++ ++ ret = regmap_write(ppe_dev->regmap, PPE_BM_SCH_CTRL_ADDR, val); ++ if (ret) ++ goto sch_config_fail; ++ ++ /* Configure each BM scheduler entry with the valid ingress port and ++ * egress port, the second port takes effect when the specified port ++ * is in the inactive state. ++ */ ++ for (i = 0; i < count; i++) { ++ val = FIELD_PREP(PPE_BM_SCH_CFG_TBL_VALID, bm_cfg[i].valid); ++ val |= FIELD_PREP(PPE_BM_SCH_CFG_TBL_DIR, bm_cfg[i].is_egress); ++ val |= FIELD_PREP(PPE_BM_SCH_CFG_TBL_PORT_NUM, bm_cfg[i].port); ++ val |= FIELD_PREP(PPE_BM_SCH_CFG_TBL_SECOND_PORT_VALID, bm_cfg[i].second_valid); ++ val |= FIELD_PREP(PPE_BM_SCH_CFG_TBL_SECOND_PORT, bm_cfg[i].second_port); ++ ++ reg = PPE_BM_SCH_CFG_TBL_ADDR + i * PPE_BM_SCH_CFG_TBL_INC; ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ goto sch_config_fail; ++ } ++ ++ count = ARRAY_SIZE(ipq9574_ppe_sch_qm_config); ++ qm_cfg = ipq9574_ppe_sch_qm_config; ++ ++ /* Configure the depth of QM scheduler entries. */ ++ val = FIELD_PREP(PPE_PSCH_SCH_DEPTH_CFG_SCH_DEPTH, count); ++ ret = regmap_write(ppe_dev->regmap, PPE_PSCH_SCH_DEPTH_CFG_ADDR, val); ++ if (ret) ++ goto sch_config_fail; ++ ++ /* Configure each QM scheduler entry with enqueue port and dequeue ++ * port, the second port takes effect when the specified dequeue ++ * port is in the inactive port. ++ */ ++ for (i = 0; i < count; i++) { ++ val = FIELD_PREP(PPE_PSCH_SCH_CFG_TBL_ENS_PORT_BITMAP, ++ qm_cfg[i].ensch_port_bmp); ++ val |= FIELD_PREP(PPE_PSCH_SCH_CFG_TBL_ENS_PORT, ++ qm_cfg[i].ensch_port); ++ val |= FIELD_PREP(PPE_PSCH_SCH_CFG_TBL_DES_PORT, ++ qm_cfg[i].desch_port); ++ val |= FIELD_PREP(PPE_PSCH_SCH_CFG_TBL_DES_SECOND_PORT_EN, ++ qm_cfg[i].desch_second_valid); ++ val |= FIELD_PREP(PPE_PSCH_SCH_CFG_TBL_DES_SECOND_PORT, ++ qm_cfg[i].desch_second_port); ++ ++ reg = PPE_PSCH_SCH_CFG_TBL_ADDR + i * PPE_PSCH_SCH_CFG_TBL_INC; ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ goto sch_config_fail; ++ } ++ ++ count = ARRAY_SIZE(ppe_port_sch_config); ++ port_cfg = ppe_port_sch_config; ++ ++ /* Configure scheduler per PPE queue or flow. */ ++ for (i = 0; i < count; i++) { ++ if (port_cfg[i].port >= ppe_dev->num_ports) ++ break; ++ ++ ret = ppe_node_scheduler_config(ppe_dev, port_cfg[i]); ++ if (ret) ++ goto sch_config_fail; ++ } ++ ++ return 0; ++ ++sch_config_fail: ++ dev_err(ppe_dev->dev, "PPE scheduler arbitration config error %d\n", ret); ++ return ret; ++}; ++ + int ppe_hw_config(struct ppe_device *ppe_dev) + { + int ret; +@@ -366,5 +1148,9 @@ int ppe_hw_config(struct ppe_device *ppe + if (ret) + return ret; + +- return ppe_config_qm(ppe_dev); ++ ret = ppe_config_qm(ppe_dev); ++ if (ret) ++ return ret; ++ ++ return ppe_config_scheduler(ppe_dev); + } +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h +@@ -8,5 +8,42 @@ + + #include "ppe.h" + ++/** ++ * enum ppe_scheduler_frame_mode - PPE scheduler frame mode. ++ * @PPE_SCH_WITH_IPG_PREAMBLE_FRAME_CRC: The scheduled frame includes IPG, ++ * preamble, Ethernet packet and CRC. ++ * @PPE_SCH_WITH_FRAME_CRC: The scheduled frame includes Ethernet frame and CRC ++ * excluding IPG and preamble. ++ * @PPE_SCH_WITH_L3_PAYLOAD: The scheduled frame includes layer 3 packet data. ++ */ ++enum ppe_scheduler_frame_mode { ++ PPE_SCH_WITH_IPG_PREAMBLE_FRAME_CRC = 0, ++ PPE_SCH_WITH_FRAME_CRC = 1, ++ PPE_SCH_WITH_L3_PAYLOAD = 2, ++}; ++ ++/** ++ * struct ppe_scheduler_cfg - PPE scheduler configuration. ++ * @flow_id: PPE flow ID. ++ * @pri: Scheduler priority. ++ * @drr_node_id: Node ID for scheduled traffic. ++ * @drr_node_wt: Weight for scheduled traffic. ++ * @unit_is_packet: Packet based or byte based unit for scheduled traffic. ++ * @frame_mode: Packet mode to be scheduled. ++ * ++ * PPE scheduler supports commit rate and exceed rate configurations. ++ */ ++struct ppe_scheduler_cfg { ++ int flow_id; ++ int pri; ++ int drr_node_id; ++ int drr_node_wt; ++ bool unit_is_packet; ++ enum ppe_scheduler_frame_mode frame_mode; ++}; ++ + int ppe_hw_config(struct ppe_device *ppe_dev); ++int ppe_queue_scheduler_set(struct ppe_device *ppe_dev, ++ int node_id, bool flow_level, int port, ++ struct ppe_scheduler_cfg scheduler_cfg); + #endif +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -9,16 +9,113 @@ + + #include + ++/* PPE scheduler configurations for buffer manager block. */ ++#define PPE_BM_SCH_CTRL_ADDR 0xb000 ++#define PPE_BM_SCH_CTRL_INC 4 ++#define PPE_BM_SCH_CTRL_SCH_DEPTH GENMASK(7, 0) ++#define PPE_BM_SCH_CTRL_SCH_OFFSET GENMASK(14, 8) ++#define PPE_BM_SCH_CTRL_SCH_EN BIT(31) ++ ++#define PPE_BM_SCH_CFG_TBL_ADDR 0xc000 ++#define PPE_BM_SCH_CFG_TBL_ENTRIES 128 ++#define PPE_BM_SCH_CFG_TBL_INC 0x10 ++#define PPE_BM_SCH_CFG_TBL_PORT_NUM GENMASK(3, 0) ++#define PPE_BM_SCH_CFG_TBL_DIR BIT(4) ++#define PPE_BM_SCH_CFG_TBL_VALID BIT(5) ++#define PPE_BM_SCH_CFG_TBL_SECOND_PORT_VALID BIT(6) ++#define PPE_BM_SCH_CFG_TBL_SECOND_PORT GENMASK(11, 8) ++ + /* PPE queue counters enable/disable control. */ + #define PPE_EG_BRIDGE_CONFIG_ADDR 0x20044 + #define PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN BIT(2) + ++/* Port scheduler global config. */ ++#define PPE_PSCH_SCH_DEPTH_CFG_ADDR 0x400000 ++#define PPE_PSCH_SCH_DEPTH_CFG_INC 4 ++#define PPE_PSCH_SCH_DEPTH_CFG_SCH_DEPTH GENMASK(7, 0) ++ ++/* PPE queue level scheduler configurations. */ ++#define PPE_L0_FLOW_MAP_TBL_ADDR 0x402000 ++#define PPE_L0_FLOW_MAP_TBL_ENTRIES 300 ++#define PPE_L0_FLOW_MAP_TBL_INC 0x10 ++#define PPE_L0_FLOW_MAP_TBL_FLOW_ID GENMASK(5, 0) ++#define PPE_L0_FLOW_MAP_TBL_C_PRI GENMASK(8, 6) ++#define PPE_L0_FLOW_MAP_TBL_E_PRI GENMASK(11, 9) ++#define PPE_L0_FLOW_MAP_TBL_C_NODE_WT GENMASK(21, 12) ++#define PPE_L0_FLOW_MAP_TBL_E_NODE_WT GENMASK(31, 22) ++ ++#define PPE_L0_C_FLOW_CFG_TBL_ADDR 0x404000 ++#define PPE_L0_C_FLOW_CFG_TBL_ENTRIES 512 ++#define PPE_L0_C_FLOW_CFG_TBL_INC 0x10 ++#define PPE_L0_C_FLOW_CFG_TBL_NODE_ID GENMASK(7, 0) ++#define PPE_L0_C_FLOW_CFG_TBL_NODE_CREDIT_UNIT BIT(8) ++ ++#define PPE_L0_E_FLOW_CFG_TBL_ADDR 0x406000 ++#define PPE_L0_E_FLOW_CFG_TBL_ENTRIES 512 ++#define PPE_L0_E_FLOW_CFG_TBL_INC 0x10 ++#define PPE_L0_E_FLOW_CFG_TBL_NODE_ID GENMASK(7, 0) ++#define PPE_L0_E_FLOW_CFG_TBL_NODE_CREDIT_UNIT BIT(8) ++ ++#define PPE_L0_FLOW_PORT_MAP_TBL_ADDR 0x408000 ++#define PPE_L0_FLOW_PORT_MAP_TBL_ENTRIES 300 ++#define PPE_L0_FLOW_PORT_MAP_TBL_INC 0x10 ++#define PPE_L0_FLOW_PORT_MAP_TBL_PORT_NUM GENMASK(3, 0) ++ ++#define PPE_L0_COMP_CFG_TBL_ADDR 0x428000 ++#define PPE_L0_COMP_CFG_TBL_ENTRIES 300 ++#define PPE_L0_COMP_CFG_TBL_INC 0x10 ++#define PPE_L0_COMP_CFG_TBL_SHAPER_METER_LEN GENMASK(1, 0) ++#define PPE_L0_COMP_CFG_TBL_NODE_METER_LEN GENMASK(3, 2) ++ + /* Table addresses for per-queue dequeue setting. */ + #define PPE_DEQ_OPR_TBL_ADDR 0x430000 + #define PPE_DEQ_OPR_TBL_ENTRIES 300 + #define PPE_DEQ_OPR_TBL_INC 0x10 + #define PPE_DEQ_OPR_TBL_DEQ_DISABLE BIT(0) + ++/* PPE flow level scheduler configurations. */ ++#define PPE_L1_FLOW_MAP_TBL_ADDR 0x440000 ++#define PPE_L1_FLOW_MAP_TBL_ENTRIES 64 ++#define PPE_L1_FLOW_MAP_TBL_INC 0x10 ++#define PPE_L1_FLOW_MAP_TBL_FLOW_ID GENMASK(3, 0) ++#define PPE_L1_FLOW_MAP_TBL_C_PRI GENMASK(6, 4) ++#define PPE_L1_FLOW_MAP_TBL_E_PRI GENMASK(9, 7) ++#define PPE_L1_FLOW_MAP_TBL_C_NODE_WT GENMASK(19, 10) ++#define PPE_L1_FLOW_MAP_TBL_E_NODE_WT GENMASK(29, 20) ++ ++#define PPE_L1_C_FLOW_CFG_TBL_ADDR 0x442000 ++#define PPE_L1_C_FLOW_CFG_TBL_ENTRIES 64 ++#define PPE_L1_C_FLOW_CFG_TBL_INC 0x10 ++#define PPE_L1_C_FLOW_CFG_TBL_NODE_ID GENMASK(5, 0) ++#define PPE_L1_C_FLOW_CFG_TBL_NODE_CREDIT_UNIT BIT(6) ++ ++#define PPE_L1_E_FLOW_CFG_TBL_ADDR 0x444000 ++#define PPE_L1_E_FLOW_CFG_TBL_ENTRIES 64 ++#define PPE_L1_E_FLOW_CFG_TBL_INC 0x10 ++#define PPE_L1_E_FLOW_CFG_TBL_NODE_ID GENMASK(5, 0) ++#define PPE_L1_E_FLOW_CFG_TBL_NODE_CREDIT_UNIT BIT(6) ++ ++#define PPE_L1_FLOW_PORT_MAP_TBL_ADDR 0x446000 ++#define PPE_L1_FLOW_PORT_MAP_TBL_ENTRIES 64 ++#define PPE_L1_FLOW_PORT_MAP_TBL_INC 0x10 ++#define PPE_L1_FLOW_PORT_MAP_TBL_PORT_NUM GENMASK(3, 0) ++ ++#define PPE_L1_COMP_CFG_TBL_ADDR 0x46a000 ++#define PPE_L1_COMP_CFG_TBL_ENTRIES 64 ++#define PPE_L1_COMP_CFG_TBL_INC 0x10 ++#define PPE_L1_COMP_CFG_TBL_SHAPER_METER_LEN GENMASK(1, 0) ++#define PPE_L1_COMP_CFG_TBL_NODE_METER_LEN GENMASK(3, 2) ++ ++/* PPE port scheduler configurations for egress. */ ++#define PPE_PSCH_SCH_CFG_TBL_ADDR 0x47a000 ++#define PPE_PSCH_SCH_CFG_TBL_ENTRIES 128 ++#define PPE_PSCH_SCH_CFG_TBL_INC 0x10 ++#define PPE_PSCH_SCH_CFG_TBL_DES_PORT GENMASK(3, 0) ++#define PPE_PSCH_SCH_CFG_TBL_ENS_PORT GENMASK(7, 4) ++#define PPE_PSCH_SCH_CFG_TBL_ENS_PORT_BITMAP GENMASK(15, 8) ++#define PPE_PSCH_SCH_CFG_TBL_DES_SECOND_PORT_EN BIT(16) ++#define PPE_PSCH_SCH_CFG_TBL_DES_SECOND_PORT GENMASK(20, 17) ++ + /* There are 15 BM ports and 4 BM groups supported by PPE. + * BM port (0-7) is for EDMA port 0, BM port (8-13) is for + * PPE physical port 1-6 and BM port 14 is for EIP port. diff --git a/target/linux/qualcommbe/patches-6.12/0329-net-ethernet-qualcomm-Initialize-PPE-queue-settings.patch b/target/linux/qualcommbe/patches-6.12/0329-net-ethernet-qualcomm-Initialize-PPE-queue-settings.patch new file mode 100644 index 0000000000..fe29d76e36 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0329-net-ethernet-qualcomm-Initialize-PPE-queue-settings.patch @@ -0,0 +1,522 @@ +From 63874f7c2e46f192e43e6214d66236372e36396c Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Sun, 9 Feb 2025 22:29:41 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Initialize PPE queue settings + +Configure unicast and multicast hardware queues for the PPE +ports to enable packet forwarding between the ports. + +Each PPE port is assigned with a range of queues. The queue ID +selection for a packet is decided by the queue base and queue +offset that is configured based on the internal priority and +the RSS hash value of the packet. + +Signed-off-by: Luo Jie +--- + .../net/ethernet/qualcomm/ppe/ppe_config.c | 356 +++++++++++++++++- + .../net/ethernet/qualcomm/ppe/ppe_config.h | 63 ++++ + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 21 ++ + 3 files changed, 439 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +@@ -128,6 +128,34 @@ struct ppe_scheduler_port_config { + unsigned int drr_node_id; + }; + ++/** ++ * struct ppe_port_schedule_resource - PPE port scheduler resource. ++ * @ucastq_start: Unicast queue start ID. ++ * @ucastq_end: Unicast queue end ID. ++ * @mcastq_start: Multicast queue start ID. ++ * @mcastq_end: Multicast queue end ID. ++ * @flow_id_start: Flow start ID. ++ * @flow_id_end: Flow end ID. ++ * @l0node_start: Scheduler node start ID for queue level. ++ * @l0node_end: Scheduler node end ID for queue level. ++ * @l1node_start: Scheduler node start ID for flow level. ++ * @l1node_end: Scheduler node end ID for flow level. ++ * ++ * PPE scheduler resource allocated among the PPE ports. ++ */ ++struct ppe_port_schedule_resource { ++ unsigned int ucastq_start; ++ unsigned int ucastq_end; ++ unsigned int mcastq_start; ++ unsigned int mcastq_end; ++ unsigned int flow_id_start; ++ unsigned int flow_id_end; ++ unsigned int l0node_start; ++ unsigned int l0node_end; ++ unsigned int l1node_start; ++ unsigned int l1node_end; ++}; ++ + /* Assign the share buffer number 1550 to group 0 by default. */ + static const int ipq9574_ppe_bm_group_config = 1550; + +@@ -676,6 +704,111 @@ static const struct ppe_scheduler_port_c + }, + }; + ++/* The scheduler resource is applied to each PPE port, The resource ++ * includes the unicast & multicast queues, flow nodes and DRR nodes. ++ */ ++static const struct ppe_port_schedule_resource ppe_scheduler_res[] = { ++ { .ucastq_start = 0, ++ .ucastq_end = 63, ++ .mcastq_start = 256, ++ .mcastq_end = 271, ++ .flow_id_start = 0, ++ .flow_id_end = 0, ++ .l0node_start = 0, ++ .l0node_end = 7, ++ .l1node_start = 0, ++ .l1node_end = 0, ++ }, ++ { .ucastq_start = 144, ++ .ucastq_end = 159, ++ .mcastq_start = 272, ++ .mcastq_end = 275, ++ .flow_id_start = 36, ++ .flow_id_end = 39, ++ .l0node_start = 48, ++ .l0node_end = 63, ++ .l1node_start = 8, ++ .l1node_end = 11, ++ }, ++ { .ucastq_start = 160, ++ .ucastq_end = 175, ++ .mcastq_start = 276, ++ .mcastq_end = 279, ++ .flow_id_start = 40, ++ .flow_id_end = 43, ++ .l0node_start = 64, ++ .l0node_end = 79, ++ .l1node_start = 12, ++ .l1node_end = 15, ++ }, ++ { .ucastq_start = 176, ++ .ucastq_end = 191, ++ .mcastq_start = 280, ++ .mcastq_end = 283, ++ .flow_id_start = 44, ++ .flow_id_end = 47, ++ .l0node_start = 80, ++ .l0node_end = 95, ++ .l1node_start = 16, ++ .l1node_end = 19, ++ }, ++ { .ucastq_start = 192, ++ .ucastq_end = 207, ++ .mcastq_start = 284, ++ .mcastq_end = 287, ++ .flow_id_start = 48, ++ .flow_id_end = 51, ++ .l0node_start = 96, ++ .l0node_end = 111, ++ .l1node_start = 20, ++ .l1node_end = 23, ++ }, ++ { .ucastq_start = 208, ++ .ucastq_end = 223, ++ .mcastq_start = 288, ++ .mcastq_end = 291, ++ .flow_id_start = 52, ++ .flow_id_end = 55, ++ .l0node_start = 112, ++ .l0node_end = 127, ++ .l1node_start = 24, ++ .l1node_end = 27, ++ }, ++ { .ucastq_start = 224, ++ .ucastq_end = 239, ++ .mcastq_start = 292, ++ .mcastq_end = 295, ++ .flow_id_start = 56, ++ .flow_id_end = 59, ++ .l0node_start = 128, ++ .l0node_end = 143, ++ .l1node_start = 28, ++ .l1node_end = 31, ++ }, ++ { .ucastq_start = 240, ++ .ucastq_end = 255, ++ .mcastq_start = 296, ++ .mcastq_end = 299, ++ .flow_id_start = 60, ++ .flow_id_end = 63, ++ .l0node_start = 144, ++ .l0node_end = 159, ++ .l1node_start = 32, ++ .l1node_end = 35, ++ }, ++ { .ucastq_start = 64, ++ .ucastq_end = 143, ++ .mcastq_start = 0, ++ .mcastq_end = 0, ++ .flow_id_start = 1, ++ .flow_id_end = 35, ++ .l0node_start = 8, ++ .l0node_end = 47, ++ .l1node_start = 1, ++ .l1node_end = 7, ++ }, ++}; ++ + /* Set the PPE queue level scheduler configuration. */ + static int ppe_scheduler_l0_queue_map_set(struct ppe_device *ppe_dev, + int node_id, int port, +@@ -807,6 +940,149 @@ int ppe_queue_scheduler_set(struct ppe_d + port, scheduler_cfg); + } + ++/** ++ * ppe_queue_ucast_base_set - Set PPE unicast queue base ID and profile ID ++ * @ppe_dev: PPE device ++ * @queue_dst: PPE queue destination configuration ++ * @queue_base: PPE queue base ID ++ * @profile_id: Profile ID ++ * ++ * The PPE unicast queue base ID and profile ID are configured based on the ++ * destination port information that can be service code or CPU code or the ++ * destination port. ++ * ++ * Return: 0 on success, negative error code on failure. ++ */ ++int ppe_queue_ucast_base_set(struct ppe_device *ppe_dev, ++ struct ppe_queue_ucast_dest queue_dst, ++ int queue_base, int profile_id) ++{ ++ int index, profile_size; ++ u32 val, reg; ++ ++ profile_size = queue_dst.src_profile << 8; ++ if (queue_dst.service_code_en) ++ index = PPE_QUEUE_BASE_SERVICE_CODE + profile_size + ++ queue_dst.service_code; ++ else if (queue_dst.cpu_code_en) ++ index = PPE_QUEUE_BASE_CPU_CODE + profile_size + ++ queue_dst.cpu_code; ++ else ++ index = profile_size + queue_dst.dest_port; ++ ++ val = FIELD_PREP(PPE_UCAST_QUEUE_MAP_TBL_PROFILE_ID, profile_id); ++ val |= FIELD_PREP(PPE_UCAST_QUEUE_MAP_TBL_QUEUE_ID, queue_base); ++ reg = PPE_UCAST_QUEUE_MAP_TBL_ADDR + index * PPE_UCAST_QUEUE_MAP_TBL_INC; ++ ++ return regmap_write(ppe_dev->regmap, reg, val); ++} ++ ++/** ++ * ppe_queue_ucast_offset_pri_set - Set PPE unicast queue offset based on priority ++ * @ppe_dev: PPE device ++ * @profile_id: Profile ID ++ * @priority: PPE internal priority to be used to set queue offset ++ * @queue_offset: Queue offset used for calculating the destination queue ID ++ * ++ * The PPE unicast queue offset is configured based on the PPE ++ * internal priority. ++ * ++ * Return: 0 on success, negative error code on failure. ++ */ ++int ppe_queue_ucast_offset_pri_set(struct ppe_device *ppe_dev, ++ int profile_id, ++ int priority, ++ int queue_offset) ++{ ++ u32 val, reg; ++ int index; ++ ++ index = (profile_id << 4) + priority; ++ val = FIELD_PREP(PPE_UCAST_PRIORITY_MAP_TBL_CLASS, queue_offset); ++ reg = PPE_UCAST_PRIORITY_MAP_TBL_ADDR + index * PPE_UCAST_PRIORITY_MAP_TBL_INC; ++ ++ return regmap_write(ppe_dev->regmap, reg, val); ++} ++ ++/** ++ * ppe_queue_ucast_offset_hash_set - Set PPE unicast queue offset based on hash ++ * @ppe_dev: PPE device ++ * @profile_id: Profile ID ++ * @rss_hash: Packet hash value to be used to set queue offset ++ * @queue_offset: Queue offset used for calculating the destination queue ID ++ * ++ * The PPE unicast queue offset is configured based on the RSS hash value. ++ * ++ * Return: 0 on success, negative error code on failure. ++ */ ++int ppe_queue_ucast_offset_hash_set(struct ppe_device *ppe_dev, ++ int profile_id, ++ int rss_hash, ++ int queue_offset) ++{ ++ u32 val, reg; ++ int index; ++ ++ index = (profile_id << 8) + rss_hash; ++ val = FIELD_PREP(PPE_UCAST_HASH_MAP_TBL_HASH, queue_offset); ++ reg = PPE_UCAST_HASH_MAP_TBL_ADDR + index * PPE_UCAST_HASH_MAP_TBL_INC; ++ ++ return regmap_write(ppe_dev->regmap, reg, val); ++} ++ ++/** ++ * ppe_port_resource_get - Get PPE resource per port ++ * @ppe_dev: PPE device ++ * @port: PPE port ++ * @type: Resource type ++ * @res_start: Resource start ID returned ++ * @res_end: Resource end ID returned ++ * ++ * PPE resource is assigned per PPE port, which is acquired for QoS scheduler. ++ * ++ * Return: 0 on success, negative error code on failure. ++ */ ++int ppe_port_resource_get(struct ppe_device *ppe_dev, int port, ++ enum ppe_resource_type type, ++ int *res_start, int *res_end) ++{ ++ struct ppe_port_schedule_resource res; ++ ++ /* The reserved resource with the maximum port ID of PPE is ++ * also allowed to be acquired. ++ */ ++ if (port > ppe_dev->num_ports) ++ return -EINVAL; ++ ++ res = ppe_scheduler_res[port]; ++ switch (type) { ++ case PPE_RES_UCAST: ++ *res_start = res.ucastq_start; ++ *res_end = res.ucastq_end; ++ break; ++ case PPE_RES_MCAST: ++ *res_start = res.mcastq_start; ++ *res_end = res.mcastq_end; ++ break; ++ case PPE_RES_FLOW_ID: ++ *res_start = res.flow_id_start; ++ *res_end = res.flow_id_end; ++ break; ++ case PPE_RES_L0_NODE: ++ *res_start = res.l0node_start; ++ *res_end = res.l0node_end; ++ break; ++ case PPE_RES_L1_NODE: ++ *res_start = res.l1node_start; ++ *res_end = res.l1node_end; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ + static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id, + const struct ppe_bm_port_config port_cfg) + { +@@ -1140,6 +1416,80 @@ sch_config_fail: + return ret; + }; + ++/* Configure PPE queue destination of each PPE port. */ ++static int ppe_queue_dest_init(struct ppe_device *ppe_dev) ++{ ++ int ret, port_id, index, q_base, q_offset, res_start, res_end, pri_max; ++ struct ppe_queue_ucast_dest queue_dst; ++ ++ for (port_id = 0; port_id < ppe_dev->num_ports; port_id++) { ++ memset(&queue_dst, 0, sizeof(queue_dst)); ++ ++ ret = ppe_port_resource_get(ppe_dev, port_id, PPE_RES_UCAST, ++ &res_start, &res_end); ++ if (ret) ++ return ret; ++ ++ q_base = res_start; ++ queue_dst.dest_port = port_id; ++ ++ /* Configure queue base ID and profile ID that is same as ++ * physical port ID. ++ */ ++ ret = ppe_queue_ucast_base_set(ppe_dev, queue_dst, ++ q_base, port_id); ++ if (ret) ++ return ret; ++ ++ /* Queue priority range supported by each PPE port */ ++ ret = ppe_port_resource_get(ppe_dev, port_id, PPE_RES_L0_NODE, ++ &res_start, &res_end); ++ if (ret) ++ return ret; ++ ++ pri_max = res_end - res_start; ++ ++ /* Redirect ARP reply packet with the max priority on CPU port, ++ * which keeps the ARP reply directed to CPU (CPU code is 101) ++ * with highest priority queue of EDMA. ++ */ ++ if (port_id == 0) { ++ memset(&queue_dst, 0, sizeof(queue_dst)); ++ ++ queue_dst.cpu_code_en = true; ++ queue_dst.cpu_code = 101; ++ ret = ppe_queue_ucast_base_set(ppe_dev, queue_dst, ++ q_base + pri_max, ++ 0); ++ if (ret) ++ return ret; ++ } ++ ++ /* Initialize the queue offset of internal priority. */ ++ for (index = 0; index < PPE_QUEUE_INTER_PRI_NUM; index++) { ++ q_offset = index > pri_max ? pri_max : index; ++ ++ ret = ppe_queue_ucast_offset_pri_set(ppe_dev, port_id, ++ index, q_offset); ++ if (ret) ++ return ret; ++ } ++ ++ /* Initialize the queue offset of RSS hash as 0 to avoid the ++ * random hardware value that will lead to the unexpected ++ * destination queue generated. ++ */ ++ for (index = 0; index < PPE_QUEUE_HASH_NUM; index++) { ++ ret = ppe_queue_ucast_offset_hash_set(ppe_dev, port_id, ++ index, 0); ++ if (ret) ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ + int ppe_hw_config(struct ppe_device *ppe_dev) + { + int ret; +@@ -1152,5 +1502,9 @@ int ppe_hw_config(struct ppe_device *ppe + if (ret) + return ret; + +- return ppe_config_scheduler(ppe_dev); ++ ret = ppe_config_scheduler(ppe_dev); ++ if (ret) ++ return ret; ++ ++ return ppe_queue_dest_init(ppe_dev); + } +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h +@@ -8,6 +8,16 @@ + + #include "ppe.h" + ++/* There are different table index ranges for configuring queue base ID of ++ * the destination port, CPU code and service code. ++ */ ++#define PPE_QUEUE_BASE_DEST_PORT 0 ++#define PPE_QUEUE_BASE_CPU_CODE 1024 ++#define PPE_QUEUE_BASE_SERVICE_CODE 2048 ++ ++#define PPE_QUEUE_INTER_PRI_NUM 16 ++#define PPE_QUEUE_HASH_NUM 256 ++ + /** + * enum ppe_scheduler_frame_mode - PPE scheduler frame mode. + * @PPE_SCH_WITH_IPG_PREAMBLE_FRAME_CRC: The scheduled frame includes IPG, +@@ -42,8 +52,61 @@ struct ppe_scheduler_cfg { + enum ppe_scheduler_frame_mode frame_mode; + }; + ++/** ++ * enum ppe_resource_type - PPE resource type. ++ * @PPE_RES_UCAST: Unicast queue resource. ++ * @PPE_RES_MCAST: Multicast queue resource. ++ * @PPE_RES_L0_NODE: Level 0 for queue based node resource. ++ * @PPE_RES_L1_NODE: Level 1 for flow based node resource. ++ * @PPE_RES_FLOW_ID: Flow based node resource. ++ */ ++enum ppe_resource_type { ++ PPE_RES_UCAST, ++ PPE_RES_MCAST, ++ PPE_RES_L0_NODE, ++ PPE_RES_L1_NODE, ++ PPE_RES_FLOW_ID, ++}; ++ ++/** ++ * struct ppe_queue_ucast_dest - PPE unicast queue destination. ++ * @src_profile: Source profile. ++ * @service_code_en: Enable service code to map the queue base ID. ++ * @service_code: Service code. ++ * @cpu_code_en: Enable CPU code to map the queue base ID. ++ * @cpu_code: CPU code. ++ * @dest_port: destination port. ++ * ++ * PPE egress queue ID is decided by the service code if enabled, otherwise ++ * by the CPU code if enabled, or by destination port if both service code ++ * and CPU code are disabled. ++ */ ++struct ppe_queue_ucast_dest { ++ int src_profile; ++ bool service_code_en; ++ int service_code; ++ bool cpu_code_en; ++ int cpu_code; ++ int dest_port; ++}; ++ + int ppe_hw_config(struct ppe_device *ppe_dev); + int ppe_queue_scheduler_set(struct ppe_device *ppe_dev, + int node_id, bool flow_level, int port, + struct ppe_scheduler_cfg scheduler_cfg); ++int ppe_queue_ucast_base_set(struct ppe_device *ppe_dev, ++ struct ppe_queue_ucast_dest queue_dst, ++ int queue_base, ++ int profile_id); ++int ppe_queue_ucast_offset_pri_set(struct ppe_device *ppe_dev, ++ int profile_id, ++ int priority, ++ int queue_offset); ++int ppe_queue_ucast_offset_hash_set(struct ppe_device *ppe_dev, ++ int profile_id, ++ int rss_hash, ++ int queue_offset); ++int ppe_port_resource_get(struct ppe_device *ppe_dev, int port, ++ enum ppe_resource_type type, ++ int *res_start, int *res_end); + #endif +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -164,6 +164,27 @@ + #define PPE_BM_PORT_FC_SET_PRE_ALLOC(tbl_cfg, value) \ + u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_BM_PORT_FC_W1_PRE_ALLOC) + ++/* The queue base configurations based on destination port, ++ * service code or CPU code. ++ */ ++#define PPE_UCAST_QUEUE_MAP_TBL_ADDR 0x810000 ++#define PPE_UCAST_QUEUE_MAP_TBL_ENTRIES 3072 ++#define PPE_UCAST_QUEUE_MAP_TBL_INC 0x10 ++#define PPE_UCAST_QUEUE_MAP_TBL_PROFILE_ID GENMASK(3, 0) ++#define PPE_UCAST_QUEUE_MAP_TBL_QUEUE_ID GENMASK(11, 4) ++ ++/* The queue offset configurations based on RSS hash value. */ ++#define PPE_UCAST_HASH_MAP_TBL_ADDR 0x830000 ++#define PPE_UCAST_HASH_MAP_TBL_ENTRIES 4096 ++#define PPE_UCAST_HASH_MAP_TBL_INC 0x10 ++#define PPE_UCAST_HASH_MAP_TBL_HASH GENMASK(7, 0) ++ ++/* The queue offset configurations based on PPE internal priority. */ ++#define PPE_UCAST_PRIORITY_MAP_TBL_ADDR 0x842000 ++#define PPE_UCAST_PRIORITY_MAP_TBL_ENTRIES 256 ++#define PPE_UCAST_PRIORITY_MAP_TBL_INC 0x10 ++#define PPE_UCAST_PRIORITY_MAP_TBL_CLASS GENMASK(3, 0) ++ + /* PPE unicast queue (0-255) configurations. */ + #define PPE_AC_UNICAST_QUEUE_CFG_TBL_ADDR 0x848000 + #define PPE_AC_UNICAST_QUEUE_CFG_TBL_ENTRIES 256 diff --git a/target/linux/qualcommbe/patches-6.12/0330-net-ethernet-qualcomm-Initialize-PPE-service-code-se.patch b/target/linux/qualcommbe/patches-6.12/0330-net-ethernet-qualcomm-Initialize-PPE-service-code-se.patch new file mode 100644 index 0000000000..176b7d6bb4 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0330-net-ethernet-qualcomm-Initialize-PPE-service-code-se.patch @@ -0,0 +1,384 @@ +From 4147ce0d95816bded5c5e6cb276b1aa9f2620045 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Sun, 9 Feb 2025 22:29:42 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Initialize PPE service code settings + +PPE service code is a special code (0-255) that is defined by PPE for +PPE's packet processing stages, as per the network functions required +for the packet. + +For packet being sent out by ARM cores on Ethernet ports, The service +code 1 is used as the default service code. This service code is used +to bypass most of packet processing stages of the PPE before the packet +transmitted out PPE port, since the software network stack has already +processed the packet. + +Signed-off-by: Luo Jie +--- + .../net/ethernet/qualcomm/ppe/ppe_config.c | 95 +++++++++++- + .../net/ethernet/qualcomm/ppe/ppe_config.h | 145 ++++++++++++++++++ + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 53 +++++++ + 3 files changed, 292 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +@@ -8,6 +8,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -1083,6 +1084,75 @@ int ppe_port_resource_get(struct ppe_dev + return 0; + } + ++/** ++ * ppe_sc_config_set - Set PPE service code configuration ++ * @ppe_dev: PPE device ++ * @sc: Service ID, 0-255 supported by PPE ++ * @cfg: Service code configuration ++ * ++ * PPE service code is used by the PPE during its packet processing stages, ++ * to perform or bypass certain selected packet operations on the packet. ++ * ++ * Return: 0 on success, negative error code on failure. ++ */ ++int ppe_sc_config_set(struct ppe_device *ppe_dev, int sc, struct ppe_sc_cfg cfg) ++{ ++ u32 val, reg, servcode_val[2] = {}; ++ unsigned long bitmap_value; ++ int ret; ++ ++ val = FIELD_PREP(PPE_IN_L2_SERVICE_TBL_DST_PORT_ID_VALID, cfg.dest_port_valid); ++ val |= FIELD_PREP(PPE_IN_L2_SERVICE_TBL_DST_PORT_ID, cfg.dest_port); ++ val |= FIELD_PREP(PPE_IN_L2_SERVICE_TBL_DST_DIRECTION, cfg.is_src); ++ ++ bitmap_value = bitmap_read(cfg.bitmaps.egress, 0, PPE_SC_BYPASS_EGRESS_SIZE); ++ val |= FIELD_PREP(PPE_IN_L2_SERVICE_TBL_DST_BYPASS_BITMAP, bitmap_value); ++ val |= FIELD_PREP(PPE_IN_L2_SERVICE_TBL_RX_CNT_EN, ++ test_bit(PPE_SC_BYPASS_COUNTER_RX, cfg.bitmaps.counter)); ++ val |= FIELD_PREP(PPE_IN_L2_SERVICE_TBL_TX_CNT_EN, ++ test_bit(PPE_SC_BYPASS_COUNTER_TX, cfg.bitmaps.counter)); ++ reg = PPE_IN_L2_SERVICE_TBL_ADDR + PPE_IN_L2_SERVICE_TBL_INC * sc; ++ ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ return ret; ++ ++ bitmap_value = bitmap_read(cfg.bitmaps.ingress, 0, PPE_SC_BYPASS_INGRESS_SIZE); ++ PPE_SERVICE_SET_BYPASS_BITMAP(servcode_val, bitmap_value); ++ PPE_SERVICE_SET_RX_CNT_EN(servcode_val, ++ test_bit(PPE_SC_BYPASS_COUNTER_RX_VLAN, cfg.bitmaps.counter)); ++ reg = PPE_SERVICE_TBL_ADDR + PPE_SERVICE_TBL_INC * sc; ++ ++ ret = regmap_bulk_write(ppe_dev->regmap, reg, ++ servcode_val, ARRAY_SIZE(servcode_val)); ++ if (ret) ++ return ret; ++ ++ reg = PPE_EG_SERVICE_TBL_ADDR + PPE_EG_SERVICE_TBL_INC * sc; ++ ret = regmap_bulk_read(ppe_dev->regmap, reg, ++ servcode_val, ARRAY_SIZE(servcode_val)); ++ if (ret) ++ return ret; ++ ++ PPE_EG_SERVICE_SET_NEXT_SERVCODE(servcode_val, cfg.next_service_code); ++ PPE_EG_SERVICE_SET_UPDATE_ACTION(servcode_val, cfg.eip_field_update_bitmap); ++ PPE_EG_SERVICE_SET_HW_SERVICE(servcode_val, cfg.eip_hw_service); ++ PPE_EG_SERVICE_SET_OFFSET_SEL(servcode_val, cfg.eip_offset_sel); ++ PPE_EG_SERVICE_SET_TX_CNT_EN(servcode_val, ++ test_bit(PPE_SC_BYPASS_COUNTER_TX_VLAN, cfg.bitmaps.counter)); ++ ++ ret = regmap_bulk_write(ppe_dev->regmap, reg, ++ servcode_val, ARRAY_SIZE(servcode_val)); ++ if (ret) ++ return ret; ++ ++ bitmap_value = bitmap_read(cfg.bitmaps.tunnel, 0, PPE_SC_BYPASS_TUNNEL_SIZE); ++ val = FIELD_PREP(PPE_TL_SERVICE_TBL_BYPASS_BITMAP, bitmap_value); ++ reg = PPE_TL_SERVICE_TBL_ADDR + PPE_TL_SERVICE_TBL_INC * sc; ++ ++ return regmap_write(ppe_dev->regmap, reg, val); ++} ++ + static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id, + const struct ppe_bm_port_config port_cfg) + { +@@ -1490,6 +1560,25 @@ static int ppe_queue_dest_init(struct pp + return 0; + } + ++/* Initialize the service code 1 used by CPU port. */ ++static int ppe_servcode_init(struct ppe_device *ppe_dev) ++{ ++ struct ppe_sc_cfg sc_cfg = {}; ++ ++ bitmap_zero(sc_cfg.bitmaps.counter, PPE_SC_BYPASS_COUNTER_SIZE); ++ bitmap_zero(sc_cfg.bitmaps.tunnel, PPE_SC_BYPASS_TUNNEL_SIZE); ++ ++ bitmap_fill(sc_cfg.bitmaps.ingress, PPE_SC_BYPASS_INGRESS_SIZE); ++ clear_bit(PPE_SC_BYPASS_INGRESS_FAKE_MAC_HEADER, sc_cfg.bitmaps.ingress); ++ clear_bit(PPE_SC_BYPASS_INGRESS_SERVICE_CODE, sc_cfg.bitmaps.ingress); ++ clear_bit(PPE_SC_BYPASS_INGRESS_FAKE_L2_PROTO, sc_cfg.bitmaps.ingress); ++ ++ bitmap_fill(sc_cfg.bitmaps.egress, PPE_SC_BYPASS_EGRESS_SIZE); ++ clear_bit(PPE_SC_BYPASS_EGRESS_ACL_POST_ROUTING_CHECK, sc_cfg.bitmaps.egress); ++ ++ return ppe_sc_config_set(ppe_dev, PPE_EDMA_SC_BYPASS_ID, sc_cfg); ++} ++ + int ppe_hw_config(struct ppe_device *ppe_dev) + { + int ret; +@@ -1506,5 +1595,9 @@ int ppe_hw_config(struct ppe_device *ppe + if (ret) + return ret; + +- return ppe_queue_dest_init(ppe_dev); ++ ret = ppe_queue_dest_init(ppe_dev); ++ if (ret) ++ return ret; ++ ++ return ppe_servcode_init(ppe_dev); + } +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h +@@ -6,6 +6,8 @@ + #ifndef __PPE_CONFIG_H__ + #define __PPE_CONFIG_H__ + ++#include ++ + #include "ppe.h" + + /* There are different table index ranges for configuring queue base ID of +@@ -18,6 +20,9 @@ + #define PPE_QUEUE_INTER_PRI_NUM 16 + #define PPE_QUEUE_HASH_NUM 256 + ++/* The service code is used by EDMA port to transmit packet to PPE. */ ++#define PPE_EDMA_SC_BYPASS_ID 1 ++ + /** + * enum ppe_scheduler_frame_mode - PPE scheduler frame mode. + * @PPE_SCH_WITH_IPG_PREAMBLE_FRAME_CRC: The scheduled frame includes IPG, +@@ -90,6 +95,144 @@ struct ppe_queue_ucast_dest { + int dest_port; + }; + ++/* Hardware bitmaps for bypassing features of the ingress packet. */ ++enum ppe_sc_ingress_type { ++ PPE_SC_BYPASS_INGRESS_VLAN_TAG_FMT_CHECK = 0, ++ PPE_SC_BYPASS_INGRESS_VLAN_MEMBER_CHECK = 1, ++ PPE_SC_BYPASS_INGRESS_VLAN_TRANSLATE = 2, ++ PPE_SC_BYPASS_INGRESS_MY_MAC_CHECK = 3, ++ PPE_SC_BYPASS_INGRESS_DIP_LOOKUP = 4, ++ PPE_SC_BYPASS_INGRESS_FLOW_LOOKUP = 5, ++ PPE_SC_BYPASS_INGRESS_FLOW_ACTION = 6, ++ PPE_SC_BYPASS_INGRESS_ACL = 7, ++ PPE_SC_BYPASS_INGRESS_FAKE_MAC_HEADER = 8, ++ PPE_SC_BYPASS_INGRESS_SERVICE_CODE = 9, ++ PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L2 = 10, ++ PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L3_IPV4 = 11, ++ PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L3_IPV6 = 12, ++ PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L4 = 13, ++ PPE_SC_BYPASS_INGRESS_FLOW_SERVICE_CODE = 14, ++ PPE_SC_BYPASS_INGRESS_ACL_SERVICE_CODE = 15, ++ PPE_SC_BYPASS_INGRESS_FAKE_L2_PROTO = 16, ++ PPE_SC_BYPASS_INGRESS_PPPOE_TERMINATION = 17, ++ PPE_SC_BYPASS_INGRESS_DEFAULT_VLAN = 18, ++ PPE_SC_BYPASS_INGRESS_DEFAULT_PCP = 19, ++ PPE_SC_BYPASS_INGRESS_VSI_ASSIGN = 20, ++ /* Values 21-23 are not specified by hardware. */ ++ PPE_SC_BYPASS_INGRESS_VLAN_ASSIGN_FAIL = 24, ++ PPE_SC_BYPASS_INGRESS_SOURCE_GUARD = 25, ++ PPE_SC_BYPASS_INGRESS_MRU_MTU_CHECK = 26, ++ PPE_SC_BYPASS_INGRESS_FLOW_SRC_CHECK = 27, ++ PPE_SC_BYPASS_INGRESS_FLOW_QOS = 28, ++ /* This must be last as it determines the size of the BITMAP. */ ++ PPE_SC_BYPASS_INGRESS_SIZE, ++}; ++ ++/* Hardware bitmaps for bypassing features of the egress packet. */ ++enum ppe_sc_egress_type { ++ PPE_SC_BYPASS_EGRESS_VLAN_MEMBER_CHECK = 0, ++ PPE_SC_BYPASS_EGRESS_VLAN_TRANSLATE = 1, ++ PPE_SC_BYPASS_EGRESS_VLAN_TAG_FMT_CTRL = 2, ++ PPE_SC_BYPASS_EGRESS_FDB_LEARN = 3, ++ PPE_SC_BYPASS_EGRESS_FDB_REFRESH = 4, ++ PPE_SC_BYPASS_EGRESS_L2_SOURCE_SECURITY = 5, ++ PPE_SC_BYPASS_EGRESS_MANAGEMENT_FWD = 6, ++ PPE_SC_BYPASS_EGRESS_BRIDGING_FWD = 7, ++ PPE_SC_BYPASS_EGRESS_IN_STP_FLTR = 8, ++ PPE_SC_BYPASS_EGRESS_EG_STP_FLTR = 9, ++ PPE_SC_BYPASS_EGRESS_SOURCE_FLTR = 10, ++ PPE_SC_BYPASS_EGRESS_POLICER = 11, ++ PPE_SC_BYPASS_EGRESS_L2_PKT_EDIT = 12, ++ PPE_SC_BYPASS_EGRESS_L3_PKT_EDIT = 13, ++ PPE_SC_BYPASS_EGRESS_ACL_POST_ROUTING_CHECK = 14, ++ PPE_SC_BYPASS_EGRESS_PORT_ISOLATION = 15, ++ PPE_SC_BYPASS_EGRESS_PRE_ACL_QOS = 16, ++ PPE_SC_BYPASS_EGRESS_POST_ACL_QOS = 17, ++ PPE_SC_BYPASS_EGRESS_DSCP_QOS = 18, ++ PPE_SC_BYPASS_EGRESS_PCP_QOS = 19, ++ PPE_SC_BYPASS_EGRESS_PREHEADER_QOS = 20, ++ PPE_SC_BYPASS_EGRESS_FAKE_MAC_DROP = 21, ++ PPE_SC_BYPASS_EGRESS_TUNL_CONTEXT = 22, ++ PPE_SC_BYPASS_EGRESS_FLOW_POLICER = 23, ++ /* This must be last as it determines the size of the BITMAP. */ ++ PPE_SC_BYPASS_EGRESS_SIZE, ++}; ++ ++/* Hardware bitmaps for bypassing counter of packet. */ ++enum ppe_sc_counter_type { ++ PPE_SC_BYPASS_COUNTER_RX_VLAN = 0, ++ PPE_SC_BYPASS_COUNTER_RX = 1, ++ PPE_SC_BYPASS_COUNTER_TX_VLAN = 2, ++ PPE_SC_BYPASS_COUNTER_TX = 3, ++ /* This must be last as it determines the size of the BITMAP. */ ++ PPE_SC_BYPASS_COUNTER_SIZE, ++}; ++ ++/* Hardware bitmaps for bypassing features of tunnel packet. */ ++enum ppe_sc_tunnel_type { ++ PPE_SC_BYPASS_TUNNEL_SERVICE_CODE = 0, ++ PPE_SC_BYPASS_TUNNEL_TUNNEL_HANDLE = 1, ++ PPE_SC_BYPASS_TUNNEL_L3_IF_CHECK = 2, ++ PPE_SC_BYPASS_TUNNEL_VLAN_CHECK = 3, ++ PPE_SC_BYPASS_TUNNEL_DMAC_CHECK = 4, ++ PPE_SC_BYPASS_TUNNEL_UDP_CSUM_0_CHECK = 5, ++ PPE_SC_BYPASS_TUNNEL_TBL_DE_ACCE_CHECK = 6, ++ PPE_SC_BYPASS_TUNNEL_PPPOE_MC_TERM_CHECK = 7, ++ PPE_SC_BYPASS_TUNNEL_TTL_EXCEED_CHECK = 8, ++ PPE_SC_BYPASS_TUNNEL_MAP_SRC_CHECK = 9, ++ PPE_SC_BYPASS_TUNNEL_MAP_DST_CHECK = 10, ++ PPE_SC_BYPASS_TUNNEL_LPM_DST_LOOKUP = 11, ++ PPE_SC_BYPASS_TUNNEL_LPM_LOOKUP = 12, ++ PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L2 = 13, ++ PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L3_IPV4 = 14, ++ PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L3_IPV6 = 15, ++ PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L4 = 16, ++ PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_TUNNEL = 17, ++ /* Values 18-19 are not specified by hardware. */ ++ PPE_SC_BYPASS_TUNNEL_PRE_IPO = 20, ++ /* This must be last as it determines the size of the BITMAP. */ ++ PPE_SC_BYPASS_TUNNEL_SIZE, ++}; ++ ++/** ++ * struct ppe_sc_bypass - PPE service bypass bitmaps ++ * @ingress: Bitmap of features that can be bypassed on the ingress packet. ++ * @egress: Bitmap of features that can be bypassed on the egress packet. ++ * @counter: Bitmap of features that can be bypassed on the counter type. ++ * @tunnel: Bitmap of features that can be bypassed on the tunnel packet. ++ */ ++struct ppe_sc_bypass { ++ DECLARE_BITMAP(ingress, PPE_SC_BYPASS_INGRESS_SIZE); ++ DECLARE_BITMAP(egress, PPE_SC_BYPASS_EGRESS_SIZE); ++ DECLARE_BITMAP(counter, PPE_SC_BYPASS_COUNTER_SIZE); ++ DECLARE_BITMAP(tunnel, PPE_SC_BYPASS_TUNNEL_SIZE); ++}; ++ ++/** ++ * struct ppe_sc_cfg - PPE service code configuration. ++ * @dest_port_valid: Generate destination port or not. ++ * @dest_port: Destination port ID. ++ * @bitmaps: Bitmap of bypass features. ++ * @is_src: Destination port acts as source port, packet sent to CPU. ++ * @next_service_code: New service code generated. ++ * @eip_field_update_bitmap: Fields updated as actions taken for EIP. ++ * @eip_hw_service: Selected hardware functions for EIP. ++ * @eip_offset_sel: Packet offset selection, using packet's layer 4 offset ++ * or using packet's layer 3 offset for EIP. ++ * ++ * Service code is generated during the packet passing through PPE. ++ */ ++struct ppe_sc_cfg { ++ bool dest_port_valid; ++ int dest_port; ++ struct ppe_sc_bypass bitmaps; ++ bool is_src; ++ int next_service_code; ++ int eip_field_update_bitmap; ++ int eip_hw_service; ++ int eip_offset_sel; ++}; ++ + int ppe_hw_config(struct ppe_device *ppe_dev); + int ppe_queue_scheduler_set(struct ppe_device *ppe_dev, + int node_id, bool flow_level, int port, +@@ -109,4 +252,6 @@ int ppe_queue_ucast_offset_hash_set(stru + int ppe_port_resource_get(struct ppe_device *ppe_dev, int port, + enum ppe_resource_type type, + int *res_start, int *res_end); ++int ppe_sc_config_set(struct ppe_device *ppe_dev, int sc, ++ struct ppe_sc_cfg cfg); + #endif +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -25,10 +25,63 @@ + #define PPE_BM_SCH_CFG_TBL_SECOND_PORT_VALID BIT(6) + #define PPE_BM_SCH_CFG_TBL_SECOND_PORT GENMASK(11, 8) + ++/* PPE service code configuration for the ingress direction functions, ++ * including bypass configuration for relevant PPE switch core functions ++ * such as flow entry lookup bypass. ++ */ ++#define PPE_SERVICE_TBL_ADDR 0x15000 ++#define PPE_SERVICE_TBL_ENTRIES 256 ++#define PPE_SERVICE_TBL_INC 0x10 ++#define PPE_SERVICE_W0_BYPASS_BITMAP GENMASK(31, 0) ++#define PPE_SERVICE_W1_RX_CNT_EN BIT(0) ++ ++#define PPE_SERVICE_SET_BYPASS_BITMAP(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_SERVICE_W0_BYPASS_BITMAP) ++#define PPE_SERVICE_SET_RX_CNT_EN(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_SERVICE_W1_RX_CNT_EN) ++ + /* PPE queue counters enable/disable control. */ + #define PPE_EG_BRIDGE_CONFIG_ADDR 0x20044 + #define PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN BIT(2) + ++/* PPE service code configuration on the egress direction. */ ++#define PPE_EG_SERVICE_TBL_ADDR 0x43000 ++#define PPE_EG_SERVICE_TBL_ENTRIES 256 ++#define PPE_EG_SERVICE_TBL_INC 0x10 ++#define PPE_EG_SERVICE_W0_UPDATE_ACTION GENMASK(31, 0) ++#define PPE_EG_SERVICE_W1_NEXT_SERVCODE GENMASK(7, 0) ++#define PPE_EG_SERVICE_W1_HW_SERVICE GENMASK(13, 8) ++#define PPE_EG_SERVICE_W1_OFFSET_SEL BIT(14) ++#define PPE_EG_SERVICE_W1_TX_CNT_EN BIT(15) ++ ++#define PPE_EG_SERVICE_SET_UPDATE_ACTION(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_EG_SERVICE_W0_UPDATE_ACTION) ++#define PPE_EG_SERVICE_SET_NEXT_SERVCODE(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_EG_SERVICE_W1_NEXT_SERVCODE) ++#define PPE_EG_SERVICE_SET_HW_SERVICE(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_EG_SERVICE_W1_HW_SERVICE) ++#define PPE_EG_SERVICE_SET_OFFSET_SEL(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_EG_SERVICE_W1_OFFSET_SEL) ++#define PPE_EG_SERVICE_SET_TX_CNT_EN(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_EG_SERVICE_W1_TX_CNT_EN) ++ ++/* PPE service code configuration for destination port and counter. */ ++#define PPE_IN_L2_SERVICE_TBL_ADDR 0x66000 ++#define PPE_IN_L2_SERVICE_TBL_ENTRIES 256 ++#define PPE_IN_L2_SERVICE_TBL_INC 0x10 ++#define PPE_IN_L2_SERVICE_TBL_DST_PORT_ID_VALID BIT(0) ++#define PPE_IN_L2_SERVICE_TBL_DST_PORT_ID GENMASK(4, 1) ++#define PPE_IN_L2_SERVICE_TBL_DST_DIRECTION BIT(5) ++#define PPE_IN_L2_SERVICE_TBL_DST_BYPASS_BITMAP GENMASK(29, 6) ++#define PPE_IN_L2_SERVICE_TBL_RX_CNT_EN BIT(30) ++#define PPE_IN_L2_SERVICE_TBL_TX_CNT_EN BIT(31) ++ ++/* PPE service code configuration for the tunnel packet. */ ++#define PPE_TL_SERVICE_TBL_ADDR 0x306000 ++#define PPE_TL_SERVICE_TBL_ENTRIES 256 ++#define PPE_TL_SERVICE_TBL_INC 4 ++#define PPE_TL_SERVICE_TBL_BYPASS_BITMAP GENMASK(31, 0) ++ + /* Port scheduler global config. */ + #define PPE_PSCH_SCH_DEPTH_CFG_ADDR 0x400000 + #define PPE_PSCH_SCH_DEPTH_CFG_INC 4 diff --git a/target/linux/qualcommbe/patches-6.12/0331-net-ethernet-qualcomm-Initialize-PPE-port-control-se.patch b/target/linux/qualcommbe/patches-6.12/0331-net-ethernet-qualcomm-Initialize-PPE-port-control-se.patch new file mode 100644 index 0000000000..f1dcb51a87 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0331-net-ethernet-qualcomm-Initialize-PPE-port-control-se.patch @@ -0,0 +1,215 @@ +From 63af46200da794acda25cf8083bde0c1576b0859 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Sun, 9 Feb 2025 22:29:43 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Initialize PPE port control settings + +1. Enable port specific counters in PPE. +2. Configure the default action as drop when the packet size + is more than the configured MTU of physical port. + +Signed-off-by: Luo Jie +--- + .../net/ethernet/qualcomm/ppe/ppe_config.c | 86 ++++++++++++++++++- + .../net/ethernet/qualcomm/ppe/ppe_config.h | 15 ++++ + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 47 ++++++++++ + 3 files changed, 147 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +@@ -1153,6 +1153,44 @@ int ppe_sc_config_set(struct ppe_device + return regmap_write(ppe_dev->regmap, reg, val); + } + ++/** ++ * ppe_counter_enable_set - Set PPE port counter enabled ++ * @ppe_dev: PPE device ++ * @port: PPE port ID ++ * ++ * Enable PPE counters on the given port for the unicast packet, multicast ++ * packet and VLAN packet received and transmitted by PPE. ++ * ++ * Return: 0 on success, negative error code on failure. ++ */ ++int ppe_counter_enable_set(struct ppe_device *ppe_dev, int port) ++{ ++ u32 reg, mru_mtu_val[3]; ++ int ret; ++ ++ reg = PPE_MRU_MTU_CTRL_TBL_ADDR + PPE_MRU_MTU_CTRL_TBL_INC * port; ++ ret = regmap_bulk_read(ppe_dev->regmap, reg, ++ mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); ++ if (ret) ++ return ret; ++ ++ PPE_MRU_MTU_CTRL_SET_RX_CNT_EN(mru_mtu_val, true); ++ PPE_MRU_MTU_CTRL_SET_TX_CNT_EN(mru_mtu_val, true); ++ ret = regmap_bulk_write(ppe_dev->regmap, reg, ++ mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); ++ if (ret) ++ return ret; ++ ++ reg = PPE_MC_MTU_CTRL_TBL_ADDR + PPE_MC_MTU_CTRL_TBL_INC * port; ++ ret = regmap_set_bits(ppe_dev->regmap, reg, PPE_MC_MTU_CTRL_TBL_TX_CNT_EN); ++ if (ret) ++ return ret; ++ ++ reg = PPE_PORT_EG_VLAN_TBL_ADDR + PPE_PORT_EG_VLAN_TBL_INC * port; ++ ++ return regmap_set_bits(ppe_dev->regmap, reg, PPE_PORT_EG_VLAN_TBL_TX_COUNTING_EN); ++} ++ + static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id, + const struct ppe_bm_port_config port_cfg) + { +@@ -1579,6 +1617,48 @@ static int ppe_servcode_init(struct ppe_ + return ppe_sc_config_set(ppe_dev, PPE_EDMA_SC_BYPASS_ID, sc_cfg); + } + ++/* Initialize PPE port configurations. */ ++static int ppe_port_config_init(struct ppe_device *ppe_dev) ++{ ++ u32 reg, val, mru_mtu_val[3]; ++ int i, ret; ++ ++ /* MTU and MRU settings are not required for CPU port 0. */ ++ for (i = 1; i < ppe_dev->num_ports; i++) { ++ /* Enable Ethernet port counter */ ++ ret = ppe_counter_enable_set(ppe_dev, i); ++ if (ret) ++ return ret; ++ ++ reg = PPE_MRU_MTU_CTRL_TBL_ADDR + PPE_MRU_MTU_CTRL_TBL_INC * i; ++ ret = regmap_bulk_read(ppe_dev->regmap, reg, ++ mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); ++ if (ret) ++ return ret; ++ ++ /* Drop the packet when the packet size is more than ++ * the MTU or MRU of the physical interface. ++ */ ++ PPE_MRU_MTU_CTRL_SET_MRU_CMD(mru_mtu_val, PPE_ACTION_DROP); ++ PPE_MRU_MTU_CTRL_SET_MTU_CMD(mru_mtu_val, PPE_ACTION_DROP); ++ ret = regmap_bulk_write(ppe_dev->regmap, reg, ++ mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); ++ if (ret) ++ return ret; ++ ++ reg = PPE_MC_MTU_CTRL_TBL_ADDR + PPE_MC_MTU_CTRL_TBL_INC * i; ++ val = FIELD_PREP(PPE_MC_MTU_CTRL_TBL_MTU_CMD, PPE_ACTION_DROP); ++ ret = regmap_update_bits(ppe_dev->regmap, reg, ++ PPE_MC_MTU_CTRL_TBL_MTU_CMD, ++ val); ++ if (ret) ++ return ret; ++ } ++ ++ /* Enable CPU port counters. */ ++ return ppe_counter_enable_set(ppe_dev, 0); ++} ++ + int ppe_hw_config(struct ppe_device *ppe_dev) + { + int ret; +@@ -1599,5 +1679,9 @@ int ppe_hw_config(struct ppe_device *ppe + if (ret) + return ret; + +- return ppe_servcode_init(ppe_dev); ++ ret = ppe_servcode_init(ppe_dev); ++ if (ret) ++ return ret; ++ ++ return ppe_port_config_init(ppe_dev); + } +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h +@@ -233,6 +233,20 @@ struct ppe_sc_cfg { + int eip_offset_sel; + }; + ++/** ++ * enum ppe_action_type - PPE action of the received packet. ++ * @PPE_ACTION_FORWARD: Packet forwarded per L2/L3 process. ++ * @PPE_ACTION_DROP: Packet dropped by PPE. ++ * @PPE_ACTION_COPY_TO_CPU: Packet copied to CPU port per multicast queue. ++ * @PPE_ACTION_REDIRECT_TO_CPU: Packet redirected to CPU port per unicast queue. ++ */ ++enum ppe_action_type { ++ PPE_ACTION_FORWARD = 0, ++ PPE_ACTION_DROP = 1, ++ PPE_ACTION_COPY_TO_CPU = 2, ++ PPE_ACTION_REDIRECT_TO_CPU = 3, ++}; ++ + int ppe_hw_config(struct ppe_device *ppe_dev); + int ppe_queue_scheduler_set(struct ppe_device *ppe_dev, + int node_id, bool flow_level, int port, +@@ -254,4 +268,5 @@ int ppe_port_resource_get(struct ppe_dev + int *res_start, int *res_end); + int ppe_sc_config_set(struct ppe_device *ppe_dev, int sc, + struct ppe_sc_cfg cfg); ++int ppe_counter_enable_set(struct ppe_device *ppe_dev, int port); + #endif +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -40,6 +40,18 @@ + #define PPE_SERVICE_SET_RX_CNT_EN(tbl_cfg, value) \ + u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_SERVICE_W1_RX_CNT_EN) + ++/* PPE port egress VLAN configurations. */ ++#define PPE_PORT_EG_VLAN_TBL_ADDR 0x20020 ++#define PPE_PORT_EG_VLAN_TBL_ENTRIES 8 ++#define PPE_PORT_EG_VLAN_TBL_INC 4 ++#define PPE_PORT_EG_VLAN_TBL_VLAN_TYPE BIT(0) ++#define PPE_PORT_EG_VLAN_TBL_CTAG_MODE GENMASK(2, 1) ++#define PPE_PORT_EG_VLAN_TBL_STAG_MODE GENMASK(4, 3) ++#define PPE_PORT_EG_VLAN_TBL_VSI_TAG_MODE_EN BIT(5) ++#define PPE_PORT_EG_VLAN_TBL_PCP_PROP_CMD BIT(6) ++#define PPE_PORT_EG_VLAN_TBL_DEI_PROP_CMD BIT(7) ++#define PPE_PORT_EG_VLAN_TBL_TX_COUNTING_EN BIT(8) ++ + /* PPE queue counters enable/disable control. */ + #define PPE_EG_BRIDGE_CONFIG_ADDR 0x20044 + #define PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN BIT(2) +@@ -65,6 +77,41 @@ + #define PPE_EG_SERVICE_SET_TX_CNT_EN(tbl_cfg, value) \ + u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_EG_SERVICE_W1_TX_CNT_EN) + ++/* PPE port control configurations for the traffic to the multicast queues. */ ++#define PPE_MC_MTU_CTRL_TBL_ADDR 0x60a00 ++#define PPE_MC_MTU_CTRL_TBL_ENTRIES 8 ++#define PPE_MC_MTU_CTRL_TBL_INC 4 ++#define PPE_MC_MTU_CTRL_TBL_MTU GENMASK(13, 0) ++#define PPE_MC_MTU_CTRL_TBL_MTU_CMD GENMASK(15, 14) ++#define PPE_MC_MTU_CTRL_TBL_TX_CNT_EN BIT(16) ++ ++/* PPE port control configurations for the traffic to the unicast queues. */ ++#define PPE_MRU_MTU_CTRL_TBL_ADDR 0x65000 ++#define PPE_MRU_MTU_CTRL_TBL_ENTRIES 256 ++#define PPE_MRU_MTU_CTRL_TBL_INC 0x10 ++#define PPE_MRU_MTU_CTRL_W0_MRU GENMASK(13, 0) ++#define PPE_MRU_MTU_CTRL_W0_MRU_CMD GENMASK(15, 14) ++#define PPE_MRU_MTU_CTRL_W0_MTU GENMASK(29, 16) ++#define PPE_MRU_MTU_CTRL_W0_MTU_CMD GENMASK(31, 30) ++#define PPE_MRU_MTU_CTRL_W1_RX_CNT_EN BIT(0) ++#define PPE_MRU_MTU_CTRL_W1_TX_CNT_EN BIT(1) ++#define PPE_MRU_MTU_CTRL_W1_SRC_PROFILE GENMASK(3, 2) ++#define PPE_MRU_MTU_CTRL_W1_INNER_PREC_LOW BIT(31) ++#define PPE_MRU_MTU_CTRL_W2_INNER_PREC_HIGH GENMASK(1, 0) ++ ++#define PPE_MRU_MTU_CTRL_SET_MRU(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_MRU_MTU_CTRL_W0_MRU) ++#define PPE_MRU_MTU_CTRL_SET_MRU_CMD(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_MRU_MTU_CTRL_W0_MRU_CMD) ++#define PPE_MRU_MTU_CTRL_SET_MTU(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_MRU_MTU_CTRL_W0_MTU) ++#define PPE_MRU_MTU_CTRL_SET_MTU_CMD(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_MRU_MTU_CTRL_W0_MTU_CMD) ++#define PPE_MRU_MTU_CTRL_SET_RX_CNT_EN(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_MRU_MTU_CTRL_W1_RX_CNT_EN) ++#define PPE_MRU_MTU_CTRL_SET_TX_CNT_EN(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_MRU_MTU_CTRL_W1_TX_CNT_EN) ++ + /* PPE service code configuration for destination port and counter. */ + #define PPE_IN_L2_SERVICE_TBL_ADDR 0x66000 + #define PPE_IN_L2_SERVICE_TBL_ENTRIES 256 diff --git a/target/linux/qualcommbe/patches-6.12/0332-net-ethernet-qualcomm-Initialize-PPE-RSS-hash-settin.patch b/target/linux/qualcommbe/patches-6.12/0332-net-ethernet-qualcomm-Initialize-PPE-RSS-hash-settin.patch new file mode 100644 index 0000000000..fc0764284d --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0332-net-ethernet-qualcomm-Initialize-PPE-RSS-hash-settin.patch @@ -0,0 +1,344 @@ +From 796be78fffeebe77237a6464da7ebe9807d670f0 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Sun, 9 Feb 2025 22:29:44 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Initialize PPE RSS hash settings + +PPE RSS hash is generated during PPE receive, based on the packet +content (3 tuples or 5 tuples) and as per the configured RSS seed. +The hash is then used to select the queue to transmit the packet +to the ARM CPU. + +This patch initializes the RSS hash settings that are used to +generate the hash for the packet during PPE packet receive. + +Signed-off-by: Luo Jie +--- + .../net/ethernet/qualcomm/ppe/ppe_config.c | 194 +++++++++++++++++- + .../net/ethernet/qualcomm/ppe/ppe_config.h | 39 ++++ + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 40 ++++ + 3 files changed, 272 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +@@ -1191,6 +1191,143 @@ int ppe_counter_enable_set(struct ppe_de + return regmap_set_bits(ppe_dev->regmap, reg, PPE_PORT_EG_VLAN_TBL_TX_COUNTING_EN); + } + ++static int ppe_rss_hash_ipv4_config(struct ppe_device *ppe_dev, int index, ++ struct ppe_rss_hash_cfg cfg) ++{ ++ u32 reg, val; ++ ++ switch (index) { ++ case 0: ++ val = FIELD_PREP(PPE_RSS_HASH_MIX_IPV4_VAL, cfg.hash_sip_mix[0]); ++ break; ++ case 1: ++ val = FIELD_PREP(PPE_RSS_HASH_MIX_IPV4_VAL, cfg.hash_dip_mix[0]); ++ break; ++ case 2: ++ val = FIELD_PREP(PPE_RSS_HASH_MIX_IPV4_VAL, cfg.hash_protocol_mix); ++ break; ++ case 3: ++ val = FIELD_PREP(PPE_RSS_HASH_MIX_IPV4_VAL, cfg.hash_dport_mix); ++ break; ++ case 4: ++ val = FIELD_PREP(PPE_RSS_HASH_MIX_IPV4_VAL, cfg.hash_sport_mix); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ reg = PPE_RSS_HASH_MIX_IPV4_ADDR + index * PPE_RSS_HASH_MIX_IPV4_INC; ++ ++ return regmap_write(ppe_dev->regmap, reg, val); ++} ++ ++static int ppe_rss_hash_ipv6_config(struct ppe_device *ppe_dev, int index, ++ struct ppe_rss_hash_cfg cfg) ++{ ++ u32 reg, val; ++ ++ switch (index) { ++ case 0 ... 3: ++ val = FIELD_PREP(PPE_RSS_HASH_MIX_VAL, cfg.hash_sip_mix[index]); ++ break; ++ case 4 ... 7: ++ val = FIELD_PREP(PPE_RSS_HASH_MIX_VAL, cfg.hash_dip_mix[index - 4]); ++ break; ++ case 8: ++ val = FIELD_PREP(PPE_RSS_HASH_MIX_VAL, cfg.hash_protocol_mix); ++ break; ++ case 9: ++ val = FIELD_PREP(PPE_RSS_HASH_MIX_VAL, cfg.hash_dport_mix); ++ break; ++ case 10: ++ val = FIELD_PREP(PPE_RSS_HASH_MIX_VAL, cfg.hash_sport_mix); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ reg = PPE_RSS_HASH_MIX_ADDR + index * PPE_RSS_HASH_MIX_INC; ++ ++ return regmap_write(ppe_dev->regmap, reg, val); ++} ++ ++/** ++ * ppe_rss_hash_config_set - Configure the PPE hash settings for the packet received. ++ * @ppe_dev: PPE device. ++ * @mode: Configure RSS hash for the packet type IPv4 and IPv6. ++ * @cfg: RSS hash configuration. ++ * ++ * PPE RSS hash settings are configured for the packet type IPv4 and IPv6. ++ * ++ * Return: 0 on success, negative error code on failure. ++ */ ++int ppe_rss_hash_config_set(struct ppe_device *ppe_dev, int mode, ++ struct ppe_rss_hash_cfg cfg) ++{ ++ u32 val, reg; ++ int i, ret; ++ ++ if (mode & PPE_RSS_HASH_MODE_IPV4) { ++ val = FIELD_PREP(PPE_RSS_HASH_MASK_IPV4_HASH_MASK, cfg.hash_mask); ++ val |= FIELD_PREP(PPE_RSS_HASH_MASK_IPV4_FRAGMENT, cfg.hash_fragment_mode); ++ ret = regmap_write(ppe_dev->regmap, PPE_RSS_HASH_MASK_IPV4_ADDR, val); ++ if (ret) ++ return ret; ++ ++ val = FIELD_PREP(PPE_RSS_HASH_SEED_IPV4_VAL, cfg.hash_seed); ++ ret = regmap_write(ppe_dev->regmap, PPE_RSS_HASH_SEED_IPV4_ADDR, val); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < PPE_RSS_HASH_MIX_IPV4_ENTRIES; i++) { ++ ret = ppe_rss_hash_ipv4_config(ppe_dev, i, cfg); ++ if (ret) ++ return ret; ++ } ++ ++ for (i = 0; i < PPE_RSS_HASH_FIN_IPV4_ENTRIES; i++) { ++ val = FIELD_PREP(PPE_RSS_HASH_FIN_IPV4_INNER, cfg.hash_fin_inner[i]); ++ val |= FIELD_PREP(PPE_RSS_HASH_FIN_IPV4_OUTER, cfg.hash_fin_outer[i]); ++ reg = PPE_RSS_HASH_FIN_IPV4_ADDR + i * PPE_RSS_HASH_FIN_IPV4_INC; ++ ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ return ret; ++ } ++ } ++ ++ if (mode & PPE_RSS_HASH_MODE_IPV6) { ++ val = FIELD_PREP(PPE_RSS_HASH_MASK_HASH_MASK, cfg.hash_mask); ++ val |= FIELD_PREP(PPE_RSS_HASH_MASK_FRAGMENT, cfg.hash_fragment_mode); ++ ret = regmap_write(ppe_dev->regmap, PPE_RSS_HASH_MASK_ADDR, val); ++ if (ret) ++ return ret; ++ ++ val = FIELD_PREP(PPE_RSS_HASH_SEED_VAL, cfg.hash_seed); ++ ret = regmap_write(ppe_dev->regmap, PPE_RSS_HASH_SEED_ADDR, val); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < PPE_RSS_HASH_MIX_ENTRIES; i++) { ++ ret = ppe_rss_hash_ipv6_config(ppe_dev, i, cfg); ++ if (ret) ++ return ret; ++ } ++ ++ for (i = 0; i < PPE_RSS_HASH_FIN_ENTRIES; i++) { ++ val = FIELD_PREP(PPE_RSS_HASH_FIN_INNER, cfg.hash_fin_inner[i]); ++ val |= FIELD_PREP(PPE_RSS_HASH_FIN_OUTER, cfg.hash_fin_outer[i]); ++ reg = PPE_RSS_HASH_FIN_ADDR + i * PPE_RSS_HASH_FIN_INC; ++ ++ ret = regmap_write(ppe_dev->regmap, reg, val); ++ if (ret) ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ + static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id, + const struct ppe_bm_port_config port_cfg) + { +@@ -1659,6 +1796,57 @@ static int ppe_port_config_init(struct p + return ppe_counter_enable_set(ppe_dev, 0); + } + ++/* Initialize the PPE RSS configuration for IPv4 and IPv6 packet receive. ++ * RSS settings are to calculate the random RSS hash value generated during ++ * packet receive. This hash is then used to generate the queue offset used ++ * to determine the queue used to transmit the packet. ++ */ ++static int ppe_rss_hash_init(struct ppe_device *ppe_dev) ++{ ++ u16 fins[PPE_RSS_HASH_TUPLES] = { 0x205, 0x264, 0x227, 0x245, 0x201 }; ++ u8 ips[PPE_RSS_HASH_IP_LENGTH] = { 0x13, 0xb, 0x13, 0xb }; ++ struct ppe_rss_hash_cfg hash_cfg; ++ int i, ret; ++ ++ hash_cfg.hash_seed = get_random_u32(); ++ hash_cfg.hash_mask = 0xfff; ++ ++ /* Use 5 tuple as RSS hash key for the first fragment of TCP, UDP ++ * and UDP-Lite packets. ++ */ ++ hash_cfg.hash_fragment_mode = false; ++ ++ /* The final common seed configs used to calculate the RSS has value, ++ * which is available for both IPv4 and IPv6 packet. ++ */ ++ for (i = 0; i < ARRAY_SIZE(fins); i++) { ++ hash_cfg.hash_fin_inner[i] = fins[i] & 0x1f; ++ hash_cfg.hash_fin_outer[i] = fins[i] >> 5; ++ } ++ ++ /* RSS seeds for IP protocol, L4 destination & source port and ++ * destination & source IP used to calculate the RSS hash value. ++ */ ++ hash_cfg.hash_protocol_mix = 0x13; ++ hash_cfg.hash_dport_mix = 0xb; ++ hash_cfg.hash_sport_mix = 0x13; ++ hash_cfg.hash_dip_mix[0] = 0xb; ++ hash_cfg.hash_sip_mix[0] = 0x13; ++ ++ /* Configure RSS seed configs for IPv4 packet. */ ++ ret = ppe_rss_hash_config_set(ppe_dev, PPE_RSS_HASH_MODE_IPV4, hash_cfg); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < ARRAY_SIZE(ips); i++) { ++ hash_cfg.hash_sip_mix[i] = ips[i]; ++ hash_cfg.hash_dip_mix[i] = ips[i]; ++ } ++ ++ /* Configure RSS seed configs for IPv6 packet. */ ++ return ppe_rss_hash_config_set(ppe_dev, PPE_RSS_HASH_MODE_IPV6, hash_cfg); ++} ++ + int ppe_hw_config(struct ppe_device *ppe_dev) + { + int ret; +@@ -1683,5 +1871,9 @@ int ppe_hw_config(struct ppe_device *ppe + if (ret) + return ret; + +- return ppe_port_config_init(ppe_dev); ++ ret = ppe_port_config_init(ppe_dev); ++ if (ret) ++ return ret; ++ ++ return ppe_rss_hash_init(ppe_dev); + } +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h +@@ -23,6 +23,12 @@ + /* The service code is used by EDMA port to transmit packet to PPE. */ + #define PPE_EDMA_SC_BYPASS_ID 1 + ++/* The PPE RSS hash configured for IPv4 and IPv6 packet separately. */ ++#define PPE_RSS_HASH_MODE_IPV4 BIT(0) ++#define PPE_RSS_HASH_MODE_IPV6 BIT(1) ++#define PPE_RSS_HASH_IP_LENGTH 4 ++#define PPE_RSS_HASH_TUPLES 5 ++ + /** + * enum ppe_scheduler_frame_mode - PPE scheduler frame mode. + * @PPE_SCH_WITH_IPG_PREAMBLE_FRAME_CRC: The scheduled frame includes IPG, +@@ -247,6 +253,37 @@ enum ppe_action_type { + PPE_ACTION_REDIRECT_TO_CPU = 3, + }; + ++/** ++ * struct ppe_rss_hash_cfg - PPE RSS hash configuration. ++ * @hash_mask: Mask of the generated hash value. ++ * @hash_fragment_mode: Hash generation mode for the first fragment of TCP, ++ * UDP and UDP-Lite packets, to use either 3 tuple or 5 tuple for RSS hash ++ * key computation. ++ * @hash_seed: Seed to generate RSS hash. ++ * @hash_sip_mix: Source IP selection. ++ * @hash_dip_mix: Destination IP selection. ++ * @hash_protocol_mix: Protocol selection. ++ * @hash_sport_mix: Source L4 port selection. ++ * @hash_dport_mix: Destination L4 port selection. ++ * @hash_fin_inner: RSS hash value first selection. ++ * @hash_fin_outer: RSS hash value second selection. ++ * ++ * PPE RSS hash value is generated for the packet based on the RSS hash ++ * configured. ++ */ ++struct ppe_rss_hash_cfg { ++ u32 hash_mask; ++ bool hash_fragment_mode; ++ u32 hash_seed; ++ u8 hash_sip_mix[PPE_RSS_HASH_IP_LENGTH]; ++ u8 hash_dip_mix[PPE_RSS_HASH_IP_LENGTH]; ++ u8 hash_protocol_mix; ++ u8 hash_sport_mix; ++ u8 hash_dport_mix; ++ u8 hash_fin_inner[PPE_RSS_HASH_TUPLES]; ++ u8 hash_fin_outer[PPE_RSS_HASH_TUPLES]; ++}; ++ + int ppe_hw_config(struct ppe_device *ppe_dev); + int ppe_queue_scheduler_set(struct ppe_device *ppe_dev, + int node_id, bool flow_level, int port, +@@ -269,4 +306,6 @@ int ppe_port_resource_get(struct ppe_dev + int ppe_sc_config_set(struct ppe_device *ppe_dev, int sc, + struct ppe_sc_cfg cfg); + int ppe_counter_enable_set(struct ppe_device *ppe_dev, int port); ++int ppe_rss_hash_config_set(struct ppe_device *ppe_dev, int mode, ++ struct ppe_rss_hash_cfg hash_cfg); + #endif +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -16,6 +16,46 @@ + #define PPE_BM_SCH_CTRL_SCH_OFFSET GENMASK(14, 8) + #define PPE_BM_SCH_CTRL_SCH_EN BIT(31) + ++/* RSS settings are to calculate the random RSS hash value generated during ++ * packet receive to ARM cores. This hash is then used to generate the queue ++ * offset used to determine the queue used to transmit the packet to ARM cores. ++ */ ++#define PPE_RSS_HASH_MASK_ADDR 0xb4318 ++#define PPE_RSS_HASH_MASK_HASH_MASK GENMASK(20, 0) ++#define PPE_RSS_HASH_MASK_FRAGMENT BIT(28) ++ ++#define PPE_RSS_HASH_SEED_ADDR 0xb431c ++#define PPE_RSS_HASH_SEED_VAL GENMASK(31, 0) ++ ++#define PPE_RSS_HASH_MIX_ADDR 0xb4320 ++#define PPE_RSS_HASH_MIX_ENTRIES 11 ++#define PPE_RSS_HASH_MIX_INC 4 ++#define PPE_RSS_HASH_MIX_VAL GENMASK(4, 0) ++ ++#define PPE_RSS_HASH_FIN_ADDR 0xb4350 ++#define PPE_RSS_HASH_FIN_ENTRIES 5 ++#define PPE_RSS_HASH_FIN_INC 4 ++#define PPE_RSS_HASH_FIN_INNER GENMASK(4, 0) ++#define PPE_RSS_HASH_FIN_OUTER GENMASK(9, 5) ++ ++#define PPE_RSS_HASH_MASK_IPV4_ADDR 0xb4380 ++#define PPE_RSS_HASH_MASK_IPV4_HASH_MASK GENMASK(20, 0) ++#define PPE_RSS_HASH_MASK_IPV4_FRAGMENT BIT(28) ++ ++#define PPE_RSS_HASH_SEED_IPV4_ADDR 0xb4384 ++#define PPE_RSS_HASH_SEED_IPV4_VAL GENMASK(31, 0) ++ ++#define PPE_RSS_HASH_MIX_IPV4_ADDR 0xb4390 ++#define PPE_RSS_HASH_MIX_IPV4_ENTRIES 5 ++#define PPE_RSS_HASH_MIX_IPV4_INC 4 ++#define PPE_RSS_HASH_MIX_IPV4_VAL GENMASK(4, 0) ++ ++#define PPE_RSS_HASH_FIN_IPV4_ADDR 0xb43b0 ++#define PPE_RSS_HASH_FIN_IPV4_ENTRIES 5 ++#define PPE_RSS_HASH_FIN_IPV4_INC 4 ++#define PPE_RSS_HASH_FIN_IPV4_INNER GENMASK(4, 0) ++#define PPE_RSS_HASH_FIN_IPV4_OUTER GENMASK(9, 5) ++ + #define PPE_BM_SCH_CFG_TBL_ADDR 0xc000 + #define PPE_BM_SCH_CFG_TBL_ENTRIES 128 + #define PPE_BM_SCH_CFG_TBL_INC 0x10 diff --git a/target/linux/qualcommbe/patches-6.12/0333-net-ethernet-qualcomm-Initialize-PPE-queue-to-Ethern.patch b/target/linux/qualcommbe/patches-6.12/0333-net-ethernet-qualcomm-Initialize-PPE-queue-to-Ethern.patch new file mode 100644 index 0000000000..e05748f0f3 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0333-net-ethernet-qualcomm-Initialize-PPE-queue-to-Ethern.patch @@ -0,0 +1,122 @@ +From c4a321bc120fabc318df165a7fcdeddfcf052253 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Sun, 9 Feb 2025 22:29:45 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Initialize PPE queue to Ethernet DMA + ring mapping + +Configure the selected queues to map with an Ethernet DMA ring for the +packet to receive on ARM cores. + +As default initialization, all queues assigned to CPU port 0 are mapped +to the EDMA ring 0. This configuration is later updated during Ethernet +DMA initialization. + +Signed-off-by: Luo Jie +--- + .../net/ethernet/qualcomm/ppe/ppe_config.c | 47 ++++++++++++++++++- + .../net/ethernet/qualcomm/ppe/ppe_config.h | 6 +++ + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 5 ++ + 3 files changed, 57 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +@@ -1328,6 +1328,28 @@ int ppe_rss_hash_config_set(struct ppe_d + return 0; + } + ++/** ++ * ppe_ring_queue_map_set - Set the PPE queue to Ethernet DMA ring mapping ++ * @ppe_dev: PPE device ++ * @ring_id: Ethernet DMA ring ID ++ * @queue_map: Bit map of queue IDs to given Ethernet DMA ring ++ * ++ * Configure the mapping from a set of PPE queues to a given Ethernet DMA ring. ++ * ++ * Return: 0 on success, negative error code on failure. ++ */ ++int ppe_ring_queue_map_set(struct ppe_device *ppe_dev, int ring_id, u32 *queue_map) ++{ ++ u32 reg, queue_bitmap_val[PPE_RING_TO_QUEUE_BITMAP_WORD_CNT]; ++ ++ memcpy(queue_bitmap_val, queue_map, sizeof(queue_bitmap_val)); ++ reg = PPE_RING_Q_MAP_TBL_ADDR + PPE_RING_Q_MAP_TBL_INC * ring_id; ++ ++ return regmap_bulk_write(ppe_dev->regmap, reg, ++ queue_bitmap_val, ++ ARRAY_SIZE(queue_bitmap_val)); ++} ++ + static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id, + const struct ppe_bm_port_config port_cfg) + { +@@ -1847,6 +1869,25 @@ static int ppe_rss_hash_init(struct ppe_ + return ppe_rss_hash_config_set(ppe_dev, PPE_RSS_HASH_MODE_IPV6, hash_cfg); + } + ++/* Initialize mapping between PPE queues assigned to CPU port 0 ++ * to Ethernet DMA ring 0. ++ */ ++static int ppe_queues_to_ring_init(struct ppe_device *ppe_dev) ++{ ++ u32 queue_bmap[PPE_RING_TO_QUEUE_BITMAP_WORD_CNT] = {}; ++ int ret, queue_id, queue_max; ++ ++ ret = ppe_port_resource_get(ppe_dev, 0, PPE_RES_UCAST, ++ &queue_id, &queue_max); ++ if (ret) ++ return ret; ++ ++ for (; queue_id <= queue_max; queue_id++) ++ queue_bmap[queue_id / 32] |= BIT_MASK(queue_id % 32); ++ ++ return ppe_ring_queue_map_set(ppe_dev, 0, queue_bmap); ++} ++ + int ppe_hw_config(struct ppe_device *ppe_dev) + { + int ret; +@@ -1875,5 +1916,9 @@ int ppe_hw_config(struct ppe_device *ppe + if (ret) + return ret; + +- return ppe_rss_hash_init(ppe_dev); ++ ret = ppe_rss_hash_init(ppe_dev); ++ if (ret) ++ return ret; ++ ++ return ppe_queues_to_ring_init(ppe_dev); + } +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h +@@ -29,6 +29,9 @@ + #define PPE_RSS_HASH_IP_LENGTH 4 + #define PPE_RSS_HASH_TUPLES 5 + ++/* PPE supports 300 queues, each bit presents as one queue. */ ++#define PPE_RING_TO_QUEUE_BITMAP_WORD_CNT 10 ++ + /** + * enum ppe_scheduler_frame_mode - PPE scheduler frame mode. + * @PPE_SCH_WITH_IPG_PREAMBLE_FRAME_CRC: The scheduled frame includes IPG, +@@ -308,4 +311,7 @@ int ppe_sc_config_set(struct ppe_device + int ppe_counter_enable_set(struct ppe_device *ppe_dev, int port); + int ppe_rss_hash_config_set(struct ppe_device *ppe_dev, int mode, + struct ppe_rss_hash_cfg hash_cfg); ++int ppe_ring_queue_map_set(struct ppe_device *ppe_dev, ++ int ring_id, ++ u32 *queue_map); + #endif +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -207,6 +207,11 @@ + #define PPE_L0_COMP_CFG_TBL_SHAPER_METER_LEN GENMASK(1, 0) + #define PPE_L0_COMP_CFG_TBL_NODE_METER_LEN GENMASK(3, 2) + ++/* PPE queue to Ethernet DMA ring mapping table. */ ++#define PPE_RING_Q_MAP_TBL_ADDR 0x42a000 ++#define PPE_RING_Q_MAP_TBL_ENTRIES 24 ++#define PPE_RING_Q_MAP_TBL_INC 0x40 ++ + /* Table addresses for per-queue dequeue setting. */ + #define PPE_DEQ_OPR_TBL_ADDR 0x430000 + #define PPE_DEQ_OPR_TBL_ENTRIES 300 diff --git a/target/linux/qualcommbe/patches-6.12/0334-net-ethernet-qualcomm-Initialize-PPE-L2-bridge-setti.patch b/target/linux/qualcommbe/patches-6.12/0334-net-ethernet-qualcomm-Initialize-PPE-L2-bridge-setti.patch new file mode 100644 index 0000000000..28a48163a6 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0334-net-ethernet-qualcomm-Initialize-PPE-L2-bridge-setti.patch @@ -0,0 +1,193 @@ +From cf7282d1e5712953516fa1cc0ffaae405491b3ca Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Sun, 9 Feb 2025 22:29:46 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Initialize PPE L2 bridge settings + +Initialize the L2 bridge settings for the PPE ports to only enable +L2 frame forwarding between CPU port and PPE Ethernet ports. + +The per-port L2 bridge settings are initialized as follows: +For PPE CPU port, the PPE bridge TX is enabled and FDB learning is +disabled. For PPE physical ports, the default L2 forwarding action +is initialized to forward to CPU port only. + +L2/FDB learning and forwarding will not be enabled for PPE physical +ports yet, since the port's VSI (Virtual Switch Instance) and VSI +membership are not yet configured, which are required for FDB +forwarding. The VSI and FDB forwarding will later be enabled when +switchdev is enabled. + +Signed-off-by: Lei Wei +Signed-off-by: Luo Jie +--- + .../net/ethernet/qualcomm/ppe/ppe_config.c | 80 ++++++++++++++++++- + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 50 ++++++++++++ + 2 files changed, 129 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +@@ -1888,6 +1888,80 @@ static int ppe_queues_to_ring_init(struc + return ppe_ring_queue_map_set(ppe_dev, 0, queue_bmap); + } + ++/* Initialize PPE bridge settings to only enable L2 frame receive and ++ * transmit between CPU port and PPE Ethernet ports. ++ */ ++static int ppe_bridge_init(struct ppe_device *ppe_dev) ++{ ++ u32 reg, mask, port_cfg[4], vsi_cfg[2]; ++ int ret, i; ++ ++ /* Configure the following settings for CPU port0: ++ * a.) Enable Bridge TX ++ * b.) Disable FDB new address learning ++ * c.) Disable station move address learning ++ */ ++ mask = PPE_PORT_BRIDGE_TXMAC_EN; ++ mask |= PPE_PORT_BRIDGE_NEW_LRN_EN; ++ mask |= PPE_PORT_BRIDGE_STA_MOVE_LRN_EN; ++ ret = regmap_update_bits(ppe_dev->regmap, ++ PPE_PORT_BRIDGE_CTRL_ADDR, ++ mask, ++ PPE_PORT_BRIDGE_TXMAC_EN); ++ if (ret) ++ return ret; ++ ++ for (i = 1; i < ppe_dev->num_ports; i++) { ++ /* Enable invalid VSI forwarding for all the physical ports ++ * to CPU port0, in case no VSI is assigned to the physical ++ * port. ++ */ ++ reg = PPE_L2_VP_PORT_TBL_ADDR + PPE_L2_VP_PORT_TBL_INC * i; ++ ret = regmap_bulk_read(ppe_dev->regmap, reg, ++ port_cfg, ARRAY_SIZE(port_cfg)); ++ ++ if (ret) ++ return ret; ++ ++ PPE_L2_PORT_SET_INVALID_VSI_FWD_EN(port_cfg, true); ++ PPE_L2_PORT_SET_DST_INFO(port_cfg, 0); ++ ++ ret = regmap_bulk_write(ppe_dev->regmap, reg, ++ port_cfg, ARRAY_SIZE(port_cfg)); ++ if (ret) ++ return ret; ++ } ++ ++ for (i = 0; i < PPE_VSI_TBL_ENTRIES; i++) { ++ /* Set the VSI forward membership to include only CPU port0. ++ * FDB learning and forwarding take place only after switchdev ++ * is supported later to create the VSI and join the physical ++ * ports to the VSI port member. ++ */ ++ reg = PPE_VSI_TBL_ADDR + PPE_VSI_TBL_INC * i; ++ ret = regmap_bulk_read(ppe_dev->regmap, reg, ++ vsi_cfg, ARRAY_SIZE(vsi_cfg)); ++ if (ret) ++ return ret; ++ ++ PPE_VSI_SET_MEMBER_PORT_BITMAP(vsi_cfg, BIT(0)); ++ PPE_VSI_SET_UUC_BITMAP(vsi_cfg, BIT(0)); ++ PPE_VSI_SET_UMC_BITMAP(vsi_cfg, BIT(0)); ++ PPE_VSI_SET_BC_BITMAP(vsi_cfg, BIT(0)); ++ PPE_VSI_SET_NEW_ADDR_LRN_EN(vsi_cfg, true); ++ PPE_VSI_SET_NEW_ADDR_FWD_CMD(vsi_cfg, PPE_ACTION_FORWARD); ++ PPE_VSI_SET_STATION_MOVE_LRN_EN(vsi_cfg, true); ++ PPE_VSI_SET_STATION_MOVE_FWD_CMD(vsi_cfg, PPE_ACTION_FORWARD); ++ ++ ret = regmap_bulk_write(ppe_dev->regmap, reg, ++ vsi_cfg, ARRAY_SIZE(vsi_cfg)); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ + int ppe_hw_config(struct ppe_device *ppe_dev) + { + int ret; +@@ -1920,5 +1994,9 @@ int ppe_hw_config(struct ppe_device *ppe + if (ret) + return ret; + +- return ppe_queues_to_ring_init(ppe_dev); ++ ret = ppe_queues_to_ring_init(ppe_dev); ++ if (ret) ++ return ret; ++ ++ return ppe_bridge_init(ppe_dev); + } +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -117,6 +117,14 @@ + #define PPE_EG_SERVICE_SET_TX_CNT_EN(tbl_cfg, value) \ + u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_EG_SERVICE_W1_TX_CNT_EN) + ++/* PPE port bridge configuration */ ++#define PPE_PORT_BRIDGE_CTRL_ADDR 0x60300 ++#define PPE_PORT_BRIDGE_CTRL_ENTRIES 8 ++#define PPE_PORT_BRIDGE_CTRL_INC 4 ++#define PPE_PORT_BRIDGE_NEW_LRN_EN BIT(0) ++#define PPE_PORT_BRIDGE_STA_MOVE_LRN_EN BIT(3) ++#define PPE_PORT_BRIDGE_TXMAC_EN BIT(16) ++ + /* PPE port control configurations for the traffic to the multicast queues. */ + #define PPE_MC_MTU_CTRL_TBL_ADDR 0x60a00 + #define PPE_MC_MTU_CTRL_TBL_ENTRIES 8 +@@ -125,6 +133,36 @@ + #define PPE_MC_MTU_CTRL_TBL_MTU_CMD GENMASK(15, 14) + #define PPE_MC_MTU_CTRL_TBL_TX_CNT_EN BIT(16) + ++/* PPE VSI configurations */ ++#define PPE_VSI_TBL_ADDR 0x63800 ++#define PPE_VSI_TBL_ENTRIES 64 ++#define PPE_VSI_TBL_INC 0x10 ++#define PPE_VSI_W0_MEMBER_PORT_BITMAP GENMASK(7, 0) ++#define PPE_VSI_W0_UUC_BITMAP GENMASK(15, 8) ++#define PPE_VSI_W0_UMC_BITMAP GENMASK(23, 16) ++#define PPE_VSI_W0_BC_BITMAP GENMASK(31, 24) ++#define PPE_VSI_W1_NEW_ADDR_LRN_EN BIT(0) ++#define PPE_VSI_W1_NEW_ADDR_FWD_CMD GENMASK(2, 1) ++#define PPE_VSI_W1_STATION_MOVE_LRN_EN BIT(3) ++#define PPE_VSI_W1_STATION_MOVE_FWD_CMD GENMASK(5, 4) ++ ++#define PPE_VSI_SET_MEMBER_PORT_BITMAP(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_VSI_W0_MEMBER_PORT_BITMAP) ++#define PPE_VSI_SET_UUC_BITMAP(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_VSI_W0_UUC_BITMAP) ++#define PPE_VSI_SET_UMC_BITMAP(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_VSI_W0_UMC_BITMAP) ++#define PPE_VSI_SET_BC_BITMAP(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_VSI_W0_BC_BITMAP) ++#define PPE_VSI_SET_NEW_ADDR_LRN_EN(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_VSI_W1_NEW_ADDR_LRN_EN) ++#define PPE_VSI_SET_NEW_ADDR_FWD_CMD(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_VSI_W1_NEW_ADDR_FWD_CMD) ++#define PPE_VSI_SET_STATION_MOVE_LRN_EN(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_VSI_W1_STATION_MOVE_LRN_EN) ++#define PPE_VSI_SET_STATION_MOVE_FWD_CMD(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_VSI_W1_STATION_MOVE_FWD_CMD) ++ + /* PPE port control configurations for the traffic to the unicast queues. */ + #define PPE_MRU_MTU_CTRL_TBL_ADDR 0x65000 + #define PPE_MRU_MTU_CTRL_TBL_ENTRIES 256 +@@ -163,6 +201,18 @@ + #define PPE_IN_L2_SERVICE_TBL_RX_CNT_EN BIT(30) + #define PPE_IN_L2_SERVICE_TBL_TX_CNT_EN BIT(31) + ++/* L2 Port configurations */ ++#define PPE_L2_VP_PORT_TBL_ADDR 0x98000 ++#define PPE_L2_VP_PORT_TBL_ENTRIES 256 ++#define PPE_L2_VP_PORT_TBL_INC 0x10 ++#define PPE_L2_VP_PORT_W0_INVALID_VSI_FWD_EN BIT(0) ++#define PPE_L2_VP_PORT_W0_DST_INFO GENMASK(9, 2) ++ ++#define PPE_L2_PORT_SET_INVALID_VSI_FWD_EN(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_L2_VP_PORT_W0_INVALID_VSI_FWD_EN) ++#define PPE_L2_PORT_SET_DST_INFO(tbl_cfg, value) \ ++ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_L2_VP_PORT_W0_DST_INFO) ++ + /* PPE service code configuration for the tunnel packet. */ + #define PPE_TL_SERVICE_TBL_ADDR 0x306000 + #define PPE_TL_SERVICE_TBL_ENTRIES 256 diff --git a/target/linux/qualcommbe/patches-6.12/0335-net-ethernet-qualcomm-Add-PPE-debugfs-support-for-PP.patch b/target/linux/qualcommbe/patches-6.12/0335-net-ethernet-qualcomm-Add-PPE-debugfs-support-for-PP.patch new file mode 100644 index 0000000000..e748bca604 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0335-net-ethernet-qualcomm-Add-PPE-debugfs-support-for-PP.patch @@ -0,0 +1,950 @@ +From fc25088f79cccb934d69e563221068589565926f Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Sun, 9 Feb 2025 22:29:47 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Add PPE debugfs support for PPE + counters + +The PPE hardware counters maintain counters for packets handled by +the various functional blocks of PPE. They help in tracing the packets +passed through PPE and debugging any packet drops. + +The counters displayed by this debugfs file are ones that are common +for all Ethernet ports, and they do not include the counters that are +specific for a MAC port. Hence they cannot be displayed using ethtool. +The per-MAC counters will be supported using "ethtool -S" along with +the netdevice driver. + +The PPE hardware packet counters are made available through +the debugfs entry "/sys/kernel/debug/ppe/packet_counters". + +Signed-off-by: Luo Jie +--- + drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +- + drivers/net/ethernet/qualcomm/ppe/ppe.c | 11 + + drivers/net/ethernet/qualcomm/ppe/ppe.h | 3 + + .../net/ethernet/qualcomm/ppe/ppe_debugfs.c | 692 ++++++++++++++++++ + .../net/ethernet/qualcomm/ppe/ppe_debugfs.h | 16 + + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 102 +++ + 6 files changed, 825 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c + create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.h + +--- a/drivers/net/ethernet/qualcomm/ppe/Makefile ++++ b/drivers/net/ethernet/qualcomm/ppe/Makefile +@@ -4,4 +4,4 @@ + # + + obj-$(CONFIG_QCOM_PPE) += qcom-ppe.o +-qcom-ppe-objs := ppe.o ppe_config.o ++qcom-ppe-objs := ppe.o ppe_config.o ppe_debugfs.o +--- a/drivers/net/ethernet/qualcomm/ppe/ppe.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe.c +@@ -16,6 +16,7 @@ + + #include "ppe.h" + #include "ppe_config.h" ++#include "ppe_debugfs.h" + + #define PPE_PORT_MAX 8 + #define PPE_CLK_RATE 353000000 +@@ -199,11 +200,20 @@ static int qcom_ppe_probe(struct platfor + if (ret) + return dev_err_probe(dev, ret, "PPE HW config failed\n"); + ++ ppe_debugfs_setup(ppe_dev); + platform_set_drvdata(pdev, ppe_dev); + + return 0; + } + ++static void qcom_ppe_remove(struct platform_device *pdev) ++{ ++ struct ppe_device *ppe_dev; ++ ++ ppe_dev = platform_get_drvdata(pdev); ++ ppe_debugfs_teardown(ppe_dev); ++} ++ + static const struct of_device_id qcom_ppe_of_match[] = { + { .compatible = "qcom,ipq9574-ppe" }, + {} +@@ -216,6 +226,7 @@ static struct platform_driver qcom_ppe_d + .of_match_table = qcom_ppe_of_match, + }, + .probe = qcom_ppe_probe, ++ .remove = qcom_ppe_remove, + }; + module_platform_driver(qcom_ppe_driver); + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe.h +@@ -11,6 +11,7 @@ + + struct device; + struct regmap; ++struct dentry; + + /** + * struct ppe_device - PPE device private data. +@@ -18,6 +19,7 @@ struct regmap; + * @regmap: PPE register map. + * @clk_rate: PPE clock rate. + * @num_ports: Number of PPE ports. ++ * @debugfs_root: Debugfs root entry. + * @num_icc_paths: Number of interconnect paths. + * @icc_paths: Interconnect path array. + * +@@ -30,6 +32,7 @@ struct ppe_device { + struct regmap *regmap; + unsigned long clk_rate; + unsigned int num_ports; ++ struct dentry *debugfs_root; + unsigned int num_icc_paths; + struct icc_bulk_data icc_paths[] __counted_by(num_icc_paths); + }; +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c +@@ -0,0 +1,692 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* PPE debugfs routines for display of PPE counters useful for debug. */ ++ ++#include ++#include ++#include ++#include ++ ++#include "ppe.h" ++#include "ppe_config.h" ++#include "ppe_debugfs.h" ++#include "ppe_regs.h" ++ ++#define PPE_PKT_CNT_TBL_SIZE 3 ++#define PPE_DROP_PKT_CNT_TBL_SIZE 5 ++ ++#define PPE_W0_PKT_CNT GENMASK(31, 0) ++#define PPE_W2_DROP_PKT_CNT_LOW GENMASK(31, 8) ++#define PPE_W3_DROP_PKT_CNT_HIGH GENMASK(7, 0) ++ ++#define PPE_GET_PKT_CNT(tbl_cnt) \ ++ u32_get_bits(*((u32 *)(tbl_cnt)), PPE_W0_PKT_CNT) ++#define PPE_GET_DROP_PKT_CNT_LOW(tbl_cnt) \ ++ u32_get_bits(*((u32 *)(tbl_cnt) + 0x2), PPE_W2_DROP_PKT_CNT_LOW) ++#define PPE_GET_DROP_PKT_CNT_HIGH(tbl_cnt) \ ++ u32_get_bits(*((u32 *)(tbl_cnt) + 0x3), PPE_W3_DROP_PKT_CNT_HIGH) ++ ++#define PRINT_COUNTER_PREFIX(desc, cnt_type) \ ++ seq_printf(seq, "%-16s %16s", desc, cnt_type) ++ ++#define PRINT_CPU_CODE_COUNTER(cnt, code) \ ++ seq_printf(seq, "%10u(cpucode:%d)", cnt, code) ++ ++#define PRINT_DROP_CODE_COUNTER(cnt, port, code) \ ++ seq_printf(seq, "%10u(port=%d),dropcode:%d", cnt, port, code) ++ ++#define PRINT_SINGLE_COUNTER(tag, cnt, str, index) \ ++do { \ ++ if (!((tag) % 4)) \ ++ seq_printf(seq, "\n%-16s %16s", "", ""); \ ++ seq_printf(seq, "%10u(%s=%04d)", cnt, str, index); \ ++} while (0) ++ ++#define PRINT_TWO_COUNTERS(tag, cnt0, cnt1, str, index) \ ++do { \ ++ if (!((tag) % 4)) \ ++ seq_printf(seq, "\n%-16s %16s", "", ""); \ ++ seq_printf(seq, "%10u/%u(%s=%04d)", cnt0, cnt1, str, index); \ ++} while (0) ++ ++/** ++ * enum ppe_cnt_size_type - PPE counter size type ++ * @PPE_PKT_CNT_SIZE_1WORD: Counter size with single register ++ * @PPE_PKT_CNT_SIZE_3WORD: Counter size with table of 3 words ++ * @PPE_PKT_CNT_SIZE_5WORD: Counter size with table of 5 words ++ * ++ * PPE takes the different register size to record the packet counters. ++ * It uses single register, or register table with 3 words or 5 words. ++ * The counter with table size 5 words also records the drop counter. ++ * There are also some other counter types occupying sizes less than 32 ++ * bits, which is not covered by this enumeration type. ++ */ ++enum ppe_cnt_size_type { ++ PPE_PKT_CNT_SIZE_1WORD, ++ PPE_PKT_CNT_SIZE_3WORD, ++ PPE_PKT_CNT_SIZE_5WORD, ++}; ++ ++static int ppe_pkt_cnt_get(struct ppe_device *ppe_dev, u32 reg, ++ enum ppe_cnt_size_type cnt_type, ++ u32 *cnt, u32 *drop_cnt) ++{ ++ u32 drop_pkt_cnt[PPE_DROP_PKT_CNT_TBL_SIZE]; ++ u32 pkt_cnt[PPE_PKT_CNT_TBL_SIZE]; ++ u32 value; ++ int ret; ++ ++ switch (cnt_type) { ++ case PPE_PKT_CNT_SIZE_1WORD: ++ ret = regmap_read(ppe_dev->regmap, reg, &value); ++ if (ret) ++ return ret; ++ ++ *cnt = value; ++ break; ++ case PPE_PKT_CNT_SIZE_3WORD: ++ ret = regmap_bulk_read(ppe_dev->regmap, reg, ++ pkt_cnt, ARRAY_SIZE(pkt_cnt)); ++ if (ret) ++ return ret; ++ ++ *cnt = PPE_GET_PKT_CNT(pkt_cnt); ++ break; ++ case PPE_PKT_CNT_SIZE_5WORD: ++ ret = regmap_bulk_read(ppe_dev->regmap, reg, ++ drop_pkt_cnt, ARRAY_SIZE(drop_pkt_cnt)); ++ if (ret) ++ return ret; ++ ++ *cnt = PPE_GET_PKT_CNT(drop_pkt_cnt); ++ ++ /* Drop counter with low 24 bits. */ ++ value = PPE_GET_DROP_PKT_CNT_LOW(drop_pkt_cnt); ++ *drop_cnt = FIELD_PREP(GENMASK(23, 0), value); ++ ++ /* Drop counter with high 8 bits. */ ++ value = PPE_GET_DROP_PKT_CNT_HIGH(drop_pkt_cnt); ++ *drop_cnt |= FIELD_PREP(GENMASK(31, 24), value); ++ break; ++ } ++ ++ return 0; ++} ++ ++static void ppe_tbl_pkt_cnt_clear(struct ppe_device *ppe_dev, u32 reg, ++ enum ppe_cnt_size_type cnt_type) ++{ ++ u32 drop_pkt_cnt[PPE_DROP_PKT_CNT_TBL_SIZE] = {}; ++ u32 pkt_cnt[PPE_PKT_CNT_TBL_SIZE] = {}; ++ ++ switch (cnt_type) { ++ case PPE_PKT_CNT_SIZE_1WORD: ++ regmap_write(ppe_dev->regmap, reg, 0); ++ break; ++ case PPE_PKT_CNT_SIZE_3WORD: ++ regmap_bulk_write(ppe_dev->regmap, reg, ++ pkt_cnt, ARRAY_SIZE(pkt_cnt)); ++ break; ++ case PPE_PKT_CNT_SIZE_5WORD: ++ regmap_bulk_write(ppe_dev->regmap, reg, ++ drop_pkt_cnt, ARRAY_SIZE(drop_pkt_cnt)); ++ break; ++ } ++} ++ ++/* The number of packets dropped because of no buffer available, no PPE ++ * buffer assigned to these packets. ++ */ ++static void ppe_port_rx_drop_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ u32 reg, drop_cnt = 0; ++ int ret, i, tag = 0; ++ ++ PRINT_COUNTER_PREFIX("PRX_DROP_CNT", "SILENT_DROP:"); ++ for (i = 0; i < PPE_DROP_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_DROP_CNT_TBL_ADDR + i * PPE_DROP_CNT_TBL_INC; ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_1WORD, ++ &drop_cnt, NULL); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ if (drop_cnt > 0) { ++ tag++; ++ PRINT_SINGLE_COUNTER(tag, drop_cnt, "port", i); ++ } ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* The number of packets dropped because hardware buffers were available ++ * only partially for the packet. ++ */ ++static void ppe_port_rx_bm_drop_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ u32 reg, pkt_cnt = 0; ++ int ret, i, tag = 0; ++ ++ PRINT_COUNTER_PREFIX("PRX_BM_DROP_CNT", "OVERFLOW_DROP:"); ++ for (i = 0; i < PPE_DROP_STAT_TBL_ENTRIES; i++) { ++ reg = PPE_DROP_STAT_TBL_ADDR + PPE_DROP_STAT_TBL_INC * i; ++ ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD, ++ &pkt_cnt, NULL); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ if (pkt_cnt > 0) { ++ tag++; ++ PRINT_SINGLE_COUNTER(tag, pkt_cnt, "port", i); ++ } ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* The number of currently occupied buffers, that can't be flushed. */ ++static void ppe_port_rx_bm_port_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ int used_cnt, react_cnt; ++ int ret, i, tag = 0; ++ u32 reg, val; ++ ++ PRINT_COUNTER_PREFIX("PRX_BM_PORT_CNT", "USED/REACT:"); ++ for (i = 0; i < PPE_BM_USED_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_BM_USED_CNT_TBL_ADDR + i * PPE_BM_USED_CNT_TBL_INC; ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ /* The number of PPE buffers used for caching the received ++ * packets before the pause frame sent. ++ */ ++ used_cnt = FIELD_GET(PPE_BM_USED_CNT_VAL, val); ++ ++ reg = PPE_BM_REACT_CNT_TBL_ADDR + i * PPE_BM_REACT_CNT_TBL_INC; ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ /* The number of PPE buffers used for caching the received ++ * packets after pause frame sent out. ++ */ ++ react_cnt = FIELD_GET(PPE_BM_REACT_CNT_VAL, val); ++ ++ if (used_cnt > 0 || react_cnt > 0) { ++ tag++; ++ PRINT_TWO_COUNTERS(tag, used_cnt, react_cnt, "port", i); ++ } ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* The number of packets processed by the ingress parser module of PPE. */ ++static void ppe_parse_pkt_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ u32 reg, cnt = 0, tunnel_cnt = 0; ++ int i, ret, tag = 0; ++ ++ PRINT_COUNTER_PREFIX("IPR_PKT_CNT", "TPRX/IPRX:"); ++ for (i = 0; i < PPE_IPR_PKT_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_TPR_PKT_CNT_TBL_ADDR + i * PPE_TPR_PKT_CNT_TBL_INC; ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_1WORD, ++ &tunnel_cnt, NULL); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ reg = PPE_IPR_PKT_CNT_TBL_ADDR + i * PPE_IPR_PKT_CNT_TBL_INC; ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_1WORD, ++ &cnt, NULL); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ if (tunnel_cnt > 0 || cnt > 0) { ++ tag++; ++ PRINT_TWO_COUNTERS(tag, tunnel_cnt, cnt, "port", i); ++ } ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* The number of packets received or dropped on the ingress direction. */ ++static void ppe_port_rx_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ u32 reg, pkt_cnt = 0, drop_cnt = 0; ++ int ret, i, tag = 0; ++ ++ PRINT_COUNTER_PREFIX("PORT_RX_CNT", "RX/RX_DROP:"); ++ for (i = 0; i < PPE_PHY_PORT_RX_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_PHY_PORT_RX_CNT_TBL_ADDR + PPE_PHY_PORT_RX_CNT_TBL_INC * i; ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_5WORD, ++ &pkt_cnt, &drop_cnt); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ if (pkt_cnt > 0) { ++ tag++; ++ PRINT_TWO_COUNTERS(tag, pkt_cnt, drop_cnt, "port", i); ++ } ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* The number of packets received or dropped by the port. */ ++static void ppe_vp_rx_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ u32 reg, pkt_cnt = 0, drop_cnt = 0; ++ int ret, i, tag = 0; ++ ++ PRINT_COUNTER_PREFIX("VPORT_RX_CNT", "RX/RX_DROP:"); ++ for (i = 0; i < PPE_PORT_RX_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_PORT_RX_CNT_TBL_ADDR + PPE_PORT_RX_CNT_TBL_INC * i; ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_5WORD, ++ &pkt_cnt, &drop_cnt); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ if (pkt_cnt > 0) { ++ tag++; ++ PRINT_TWO_COUNTERS(tag, pkt_cnt, drop_cnt, "port", i); ++ } ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* The number of packets received or dropped by layer 2 processing. */ ++static void ppe_pre_l2_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ u32 reg, pkt_cnt = 0, drop_cnt = 0; ++ int ret, i, tag = 0; ++ ++ PRINT_COUNTER_PREFIX("PRE_L2_CNT", "RX/RX_DROP:"); ++ for (i = 0; i < PPE_PRE_L2_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_PRE_L2_CNT_TBL_ADDR + PPE_PRE_L2_CNT_TBL_INC * i; ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_5WORD, ++ &pkt_cnt, &drop_cnt); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ if (pkt_cnt > 0) { ++ tag++; ++ PRINT_TWO_COUNTERS(tag, pkt_cnt, drop_cnt, "vsi", i); ++ } ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* The number of VLAN packets received by PPE. */ ++static void ppe_vlan_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ u32 reg, pkt_cnt = 0; ++ int ret, i, tag = 0; ++ ++ PRINT_COUNTER_PREFIX("VLAN_CNT", "RX:"); ++ for (i = 0; i < PPE_VLAN_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_VLAN_CNT_TBL_ADDR + PPE_VLAN_CNT_TBL_INC * i; ++ ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD, ++ &pkt_cnt, NULL); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ if (pkt_cnt > 0) { ++ tag++; ++ PRINT_SINGLE_COUNTER(tag, pkt_cnt, "vsi", i); ++ } ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* The number of packets handed to CPU by PPE. */ ++static void ppe_cpu_code_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ u32 reg, pkt_cnt = 0; ++ int ret, i; ++ ++ PRINT_COUNTER_PREFIX("CPU_CODE_CNT", "CODE:"); ++ for (i = 0; i < PPE_DROP_CPU_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_DROP_CPU_CNT_TBL_ADDR + PPE_DROP_CPU_CNT_TBL_INC * i; ++ ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD, ++ &pkt_cnt, NULL); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ if (!pkt_cnt) ++ continue; ++ ++ /* There are 256 CPU codes saved in the first 256 entries ++ * of register table, and 128 drop codes for each PPE port ++ * (0-7), the total entries is 256 + 8 * 128. ++ */ ++ if (i < 256) ++ PRINT_CPU_CODE_COUNTER(pkt_cnt, i); ++ else ++ PRINT_DROP_CODE_COUNTER(pkt_cnt, (i - 256) % 8, ++ (i - 256) / 8); ++ seq_putc(seq, '\n'); ++ PRINT_COUNTER_PREFIX("", ""); ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* The number of packets forwarded by VLAN on the egress direction. */ ++static void ppe_eg_vsi_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ u32 reg, pkt_cnt = 0; ++ int ret, i, tag = 0; ++ ++ PRINT_COUNTER_PREFIX("EG_VSI_CNT", "TX:"); ++ for (i = 0; i < PPE_EG_VSI_COUNTER_TBL_ENTRIES; i++) { ++ reg = PPE_EG_VSI_COUNTER_TBL_ADDR + PPE_EG_VSI_COUNTER_TBL_INC * i; ++ ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD, ++ &pkt_cnt, NULL); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ if (pkt_cnt > 0) { ++ tag++; ++ PRINT_SINGLE_COUNTER(tag, pkt_cnt, "vsi", i); ++ } ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* The number of packets trasmitted or dropped by port. */ ++static void ppe_vp_tx_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ u32 reg, pkt_cnt = 0, drop_cnt = 0; ++ int ret, i, tag = 0; ++ ++ PRINT_COUNTER_PREFIX("VPORT_TX_CNT", "TX/TX_DROP:"); ++ for (i = 0; i < PPE_VPORT_TX_COUNTER_TBL_ENTRIES; i++) { ++ reg = PPE_VPORT_TX_COUNTER_TBL_ADDR + PPE_VPORT_TX_COUNTER_TBL_INC * i; ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD, ++ &pkt_cnt, NULL); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ reg = PPE_VPORT_TX_DROP_CNT_TBL_ADDR + PPE_VPORT_TX_DROP_CNT_TBL_INC * i; ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD, ++ &drop_cnt, NULL); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ if (pkt_cnt > 0 || drop_cnt > 0) { ++ tag++; ++ PRINT_TWO_COUNTERS(tag, pkt_cnt, drop_cnt, "port", i); ++ } ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* The number of packets trasmitted or dropped on the egress direction. */ ++static void ppe_port_tx_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ u32 reg, pkt_cnt = 0, drop_cnt = 0; ++ int ret, i, tag = 0; ++ ++ PRINT_COUNTER_PREFIX("PORT_TX_CNT", "TX/TX_DROP:"); ++ for (i = 0; i < PPE_PORT_TX_COUNTER_TBL_ENTRIES; i++) { ++ reg = PPE_PORT_TX_COUNTER_TBL_ADDR + PPE_PORT_TX_COUNTER_TBL_INC * i; ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD, ++ &pkt_cnt, NULL); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ reg = PPE_PORT_TX_DROP_CNT_TBL_ADDR + PPE_PORT_TX_DROP_CNT_TBL_INC * i; ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD, ++ &drop_cnt, NULL); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ if (pkt_cnt > 0 || drop_cnt > 0) { ++ tag++; ++ PRINT_TWO_COUNTERS(tag, pkt_cnt, drop_cnt, "port", i); ++ } ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* The number of packets transmitted or pending by the PPE queue. */ ++static void ppe_queue_tx_counter_get(struct ppe_device *ppe_dev, ++ struct seq_file *seq) ++{ ++ u32 reg, val, pkt_cnt = 0, pend_cnt = 0; ++ int ret, i, tag = 0; ++ ++ PRINT_COUNTER_PREFIX("QUEUE_TX_CNT", "TX/PEND:"); ++ for (i = 0; i < PPE_QUEUE_TX_COUNTER_TBL_ENTRIES; i++) { ++ reg = PPE_QUEUE_TX_COUNTER_TBL_ADDR + PPE_QUEUE_TX_COUNTER_TBL_INC * i; ++ ret = ppe_pkt_cnt_get(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD, ++ &pkt_cnt, NULL); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ if (i < PPE_AC_UNICAST_QUEUE_CFG_TBL_ENTRIES) { ++ reg = PPE_AC_UNICAST_QUEUE_CNT_TBL_ADDR + ++ PPE_AC_UNICAST_QUEUE_CNT_TBL_INC * i; ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ pend_cnt = FIELD_GET(PPE_AC_UNICAST_QUEUE_CNT_TBL_PEND_CNT, val); ++ } else { ++ reg = PPE_AC_MULTICAST_QUEUE_CNT_TBL_ADDR + ++ PPE_AC_MULTICAST_QUEUE_CNT_TBL_INC * ++ (i - PPE_AC_UNICAST_QUEUE_CFG_TBL_ENTRIES); ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) { ++ seq_printf(seq, "ERROR %d\n", ret); ++ return; ++ } ++ ++ pend_cnt = FIELD_GET(PPE_AC_MULTICAST_QUEUE_CNT_TBL_PEND_CNT, val); ++ } ++ ++ if (pkt_cnt > 0 || pend_cnt > 0) { ++ tag++; ++ PRINT_TWO_COUNTERS(tag, pkt_cnt, pend_cnt, "queue", i); ++ } ++ } ++ ++ seq_putc(seq, '\n'); ++} ++ ++/* Display the various packet counters of PPE. */ ++static int ppe_packet_counter_show(struct seq_file *seq, void *v) ++{ ++ struct ppe_device *ppe_dev = seq->private; ++ ++ ppe_port_rx_drop_counter_get(ppe_dev, seq); ++ ppe_port_rx_bm_drop_counter_get(ppe_dev, seq); ++ ppe_port_rx_bm_port_counter_get(ppe_dev, seq); ++ ppe_parse_pkt_counter_get(ppe_dev, seq); ++ ppe_port_rx_counter_get(ppe_dev, seq); ++ ppe_vp_rx_counter_get(ppe_dev, seq); ++ ppe_pre_l2_counter_get(ppe_dev, seq); ++ ppe_vlan_counter_get(ppe_dev, seq); ++ ppe_cpu_code_counter_get(ppe_dev, seq); ++ ppe_eg_vsi_counter_get(ppe_dev, seq); ++ ppe_vp_tx_counter_get(ppe_dev, seq); ++ ppe_port_tx_counter_get(ppe_dev, seq); ++ ppe_queue_tx_counter_get(ppe_dev, seq); ++ ++ return 0; ++} ++ ++static int ppe_packet_counter_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, ppe_packet_counter_show, inode->i_private); ++} ++ ++static ssize_t ppe_packet_counter_clear(struct file *file, ++ const char __user *buf, ++ size_t count, loff_t *pos) ++{ ++ struct ppe_device *ppe_dev = file_inode(file)->i_private; ++ u32 reg; ++ int i; ++ ++ for (i = 0; i < PPE_DROP_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_DROP_CNT_TBL_ADDR + i * PPE_DROP_CNT_TBL_INC; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_1WORD); ++ } ++ ++ for (i = 0; i < PPE_DROP_STAT_TBL_ENTRIES; i++) { ++ reg = PPE_DROP_STAT_TBL_ADDR + PPE_DROP_STAT_TBL_INC * i; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD); ++ } ++ ++ for (i = 0; i < PPE_IPR_PKT_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_IPR_PKT_CNT_TBL_ADDR + i * PPE_IPR_PKT_CNT_TBL_INC; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_1WORD); ++ ++ reg = PPE_TPR_PKT_CNT_TBL_ADDR + i * PPE_TPR_PKT_CNT_TBL_INC; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_1WORD); ++ } ++ ++ for (i = 0; i < PPE_VLAN_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_VLAN_CNT_TBL_ADDR + PPE_VLAN_CNT_TBL_INC * i; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD); ++ } ++ ++ for (i = 0; i < PPE_PRE_L2_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_PRE_L2_CNT_TBL_ADDR + PPE_PRE_L2_CNT_TBL_INC * i; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_5WORD); ++ } ++ ++ for (i = 0; i < PPE_PORT_TX_COUNTER_TBL_ENTRIES; i++) { ++ reg = PPE_PORT_TX_DROP_CNT_TBL_ADDR + PPE_PORT_TX_DROP_CNT_TBL_INC * i; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD); ++ ++ reg = PPE_PORT_TX_COUNTER_TBL_ADDR + PPE_PORT_TX_COUNTER_TBL_INC * i; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD); ++ } ++ ++ for (i = 0; i < PPE_EG_VSI_COUNTER_TBL_ENTRIES; i++) { ++ reg = PPE_EG_VSI_COUNTER_TBL_ADDR + PPE_EG_VSI_COUNTER_TBL_INC * i; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD); ++ } ++ ++ for (i = 0; i < PPE_VPORT_TX_COUNTER_TBL_ENTRIES; i++) { ++ reg = PPE_VPORT_TX_COUNTER_TBL_ADDR + PPE_VPORT_TX_COUNTER_TBL_INC * i; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD); ++ ++ reg = PPE_VPORT_TX_DROP_CNT_TBL_ADDR + PPE_VPORT_TX_DROP_CNT_TBL_INC * i; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD); ++ } ++ ++ for (i = 0; i < PPE_QUEUE_TX_COUNTER_TBL_ENTRIES; i++) { ++ reg = PPE_QUEUE_TX_COUNTER_TBL_ADDR + PPE_QUEUE_TX_COUNTER_TBL_INC * i; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD); ++ } ++ ++ ppe_tbl_pkt_cnt_clear(ppe_dev, PPE_EPE_DBG_IN_CNT_ADDR, PPE_PKT_CNT_SIZE_1WORD); ++ ppe_tbl_pkt_cnt_clear(ppe_dev, PPE_EPE_DBG_OUT_CNT_ADDR, PPE_PKT_CNT_SIZE_1WORD); ++ ++ for (i = 0; i < PPE_DROP_CPU_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_DROP_CPU_CNT_TBL_ADDR + PPE_DROP_CPU_CNT_TBL_INC * i; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_3WORD); ++ } ++ ++ for (i = 0; i < PPE_PORT_RX_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_PORT_RX_CNT_TBL_ADDR + PPE_PORT_RX_CNT_TBL_INC * i; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_5WORD); ++ } ++ ++ for (i = 0; i < PPE_PHY_PORT_RX_CNT_TBL_ENTRIES; i++) { ++ reg = PPE_PHY_PORT_RX_CNT_TBL_ADDR + PPE_PHY_PORT_RX_CNT_TBL_INC * i; ++ ppe_tbl_pkt_cnt_clear(ppe_dev, reg, PPE_PKT_CNT_SIZE_5WORD); ++ } ++ ++ return count; ++} ++ ++static const struct file_operations ppe_debugfs_packet_counter_fops = { ++ .owner = THIS_MODULE, ++ .open = ppe_packet_counter_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++ .write = ppe_packet_counter_clear, ++}; ++ ++void ppe_debugfs_setup(struct ppe_device *ppe_dev) ++{ ++ ppe_dev->debugfs_root = debugfs_create_dir("ppe", NULL); ++ debugfs_create_file("packet_counters", 0444, ++ ppe_dev->debugfs_root, ++ ppe_dev, ++ &ppe_debugfs_packet_counter_fops); ++} ++ ++void ppe_debugfs_teardown(struct ppe_device *ppe_dev) ++{ ++ debugfs_remove_recursive(ppe_dev->debugfs_root); ++ ppe_dev->debugfs_root = NULL; ++} +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.h +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * ++ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* PPE debugfs counters setup. */ ++ ++#ifndef __PPE_DEBUGFS_H__ ++#define __PPE_DEBUGFS_H__ ++ ++#include "ppe.h" ++ ++void ppe_debugfs_setup(struct ppe_device *ppe_dev); ++void ppe_debugfs_teardown(struct ppe_device *ppe_dev); ++ ++#endif +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -16,6 +16,39 @@ + #define PPE_BM_SCH_CTRL_SCH_OFFSET GENMASK(14, 8) + #define PPE_BM_SCH_CTRL_SCH_EN BIT(31) + ++/* PPE drop counters. */ ++#define PPE_DROP_CNT_TBL_ADDR 0xb024 ++#define PPE_DROP_CNT_TBL_ENTRIES 8 ++#define PPE_DROP_CNT_TBL_INC 4 ++ ++/* BM port drop counters. */ ++#define PPE_DROP_STAT_TBL_ADDR 0xe000 ++#define PPE_DROP_STAT_TBL_ENTRIES 30 ++#define PPE_DROP_STAT_TBL_INC 0x10 ++ ++#define PPE_EPE_DBG_IN_CNT_ADDR 0x26054 ++#define PPE_EPE_DBG_OUT_CNT_ADDR 0x26070 ++ ++/* Egress VLAN counters. */ ++#define PPE_EG_VSI_COUNTER_TBL_ADDR 0x41000 ++#define PPE_EG_VSI_COUNTER_TBL_ENTRIES 64 ++#define PPE_EG_VSI_COUNTER_TBL_INC 0x10 ++ ++/* Port TX counters. */ ++#define PPE_PORT_TX_COUNTER_TBL_ADDR 0x45000 ++#define PPE_PORT_TX_COUNTER_TBL_ENTRIES 8 ++#define PPE_PORT_TX_COUNTER_TBL_INC 0x10 ++ ++/* Virtual port TX counters. */ ++#define PPE_VPORT_TX_COUNTER_TBL_ADDR 0x47000 ++#define PPE_VPORT_TX_COUNTER_TBL_ENTRIES 256 ++#define PPE_VPORT_TX_COUNTER_TBL_INC 0x10 ++ ++/* Queue counters. */ ++#define PPE_QUEUE_TX_COUNTER_TBL_ADDR 0x4a000 ++#define PPE_QUEUE_TX_COUNTER_TBL_ENTRIES 300 ++#define PPE_QUEUE_TX_COUNTER_TBL_INC 0x10 ++ + /* RSS settings are to calculate the random RSS hash value generated during + * packet receive to ARM cores. This hash is then used to generate the queue + * offset used to determine the queue used to transmit the packet to ARM cores. +@@ -213,6 +246,51 @@ + #define PPE_L2_PORT_SET_DST_INFO(tbl_cfg, value) \ + u32p_replace_bits((u32 *)tbl_cfg, value, PPE_L2_VP_PORT_W0_DST_INFO) + ++/* Port RX and RX drop counters. */ ++#define PPE_PORT_RX_CNT_TBL_ADDR 0x150000 ++#define PPE_PORT_RX_CNT_TBL_ENTRIES 256 ++#define PPE_PORT_RX_CNT_TBL_INC 0x20 ++ ++/* Physical port RX and RX drop counters. */ ++#define PPE_PHY_PORT_RX_CNT_TBL_ADDR 0x156000 ++#define PPE_PHY_PORT_RX_CNT_TBL_ENTRIES 8 ++#define PPE_PHY_PORT_RX_CNT_TBL_INC 0x20 ++ ++/* Counters for the packet to CPU port. */ ++#define PPE_DROP_CPU_CNT_TBL_ADDR 0x160000 ++#define PPE_DROP_CPU_CNT_TBL_ENTRIES 1280 ++#define PPE_DROP_CPU_CNT_TBL_INC 0x10 ++ ++/* VLAN counters. */ ++#define PPE_VLAN_CNT_TBL_ADDR 0x178000 ++#define PPE_VLAN_CNT_TBL_ENTRIES 64 ++#define PPE_VLAN_CNT_TBL_INC 0x10 ++ ++/* PPE L2 counters. */ ++#define PPE_PRE_L2_CNT_TBL_ADDR 0x17c000 ++#define PPE_PRE_L2_CNT_TBL_ENTRIES 64 ++#define PPE_PRE_L2_CNT_TBL_INC 0x20 ++ ++/* Port TX drop counters. */ ++#define PPE_PORT_TX_DROP_CNT_TBL_ADDR 0x17d000 ++#define PPE_PORT_TX_DROP_CNT_TBL_ENTRIES 8 ++#define PPE_PORT_TX_DROP_CNT_TBL_INC 0x10 ++ ++/* Virtual port TX counters. */ ++#define PPE_VPORT_TX_DROP_CNT_TBL_ADDR 0x17e000 ++#define PPE_VPORT_TX_DROP_CNT_TBL_ENTRIES 256 ++#define PPE_VPORT_TX_DROP_CNT_TBL_INC 0x10 ++ ++/* Counters for the tunnel packet. */ ++#define PPE_TPR_PKT_CNT_TBL_ADDR 0x1d0080 ++#define PPE_TPR_PKT_CNT_TBL_ENTRIES 8 ++#define PPE_TPR_PKT_CNT_TBL_INC 4 ++ ++/* Counters for the all packet received. */ ++#define PPE_IPR_PKT_CNT_TBL_ADDR 0x1e0080 ++#define PPE_IPR_PKT_CNT_TBL_ENTRIES 8 ++#define PPE_IPR_PKT_CNT_TBL_INC 4 ++ + /* PPE service code configuration for the tunnel packet. */ + #define PPE_TL_SERVICE_TBL_ADDR 0x306000 + #define PPE_TL_SERVICE_TBL_ENTRIES 256 +@@ -325,6 +403,18 @@ + #define PPE_BM_PORT_GROUP_ID_INC 0x4 + #define PPE_BM_PORT_GROUP_ID_SHARED_GROUP_ID GENMASK(1, 0) + ++/* Counters for PPE buffers used for packets cached. */ ++#define PPE_BM_USED_CNT_TBL_ADDR 0x6001c0 ++#define PPE_BM_USED_CNT_TBL_ENTRIES 15 ++#define PPE_BM_USED_CNT_TBL_INC 0x4 ++#define PPE_BM_USED_CNT_VAL GENMASK(10, 0) ++ ++/* Counters for PPE buffers used for packets received after pause frame sent. */ ++#define PPE_BM_REACT_CNT_TBL_ADDR 0x600240 ++#define PPE_BM_REACT_CNT_TBL_ENTRIES 15 ++#define PPE_BM_REACT_CNT_TBL_INC 0x4 ++#define PPE_BM_REACT_CNT_VAL GENMASK(8, 0) ++ + #define PPE_BM_SHARED_GROUP_CFG_ADDR 0x600290 + #define PPE_BM_SHARED_GROUP_CFG_ENTRIES 4 + #define PPE_BM_SHARED_GROUP_CFG_INC 0x4 +@@ -449,6 +539,18 @@ + #define PPE_AC_GRP_SET_BUF_LIMIT(tbl_cfg, value) \ + u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_AC_GRP_W1_BUF_LIMIT) + ++/* Counters for packets handled by unicast queues (0-255). */ ++#define PPE_AC_UNICAST_QUEUE_CNT_TBL_ADDR 0x84e000 ++#define PPE_AC_UNICAST_QUEUE_CNT_TBL_ENTRIES 256 ++#define PPE_AC_UNICAST_QUEUE_CNT_TBL_INC 0x10 ++#define PPE_AC_UNICAST_QUEUE_CNT_TBL_PEND_CNT GENMASK(12, 0) ++ ++/* Counters for packets handled by multicast queues (256-299). */ ++#define PPE_AC_MULTICAST_QUEUE_CNT_TBL_ADDR 0x852000 ++#define PPE_AC_MULTICAST_QUEUE_CNT_TBL_ENTRIES 44 ++#define PPE_AC_MULTICAST_QUEUE_CNT_TBL_INC 0x10 ++#define PPE_AC_MULTICAST_QUEUE_CNT_TBL_PEND_CNT GENMASK(12, 0) ++ + /* Table addresses for per-queue enqueue setting. */ + #define PPE_ENQ_OPR_TBL_ADDR 0x85c000 + #define PPE_ENQ_OPR_TBL_ENTRIES 300 diff --git a/target/linux/qualcommbe/patches-6.12/0336-MAINTAINERS-Add-maintainer-for-Qualcomm-PPE-driver.patch b/target/linux/qualcommbe/patches-6.12/0336-MAINTAINERS-Add-maintainer-for-Qualcomm-PPE-driver.patch new file mode 100644 index 0000000000..1ed5c81f64 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0336-MAINTAINERS-Add-maintainer-for-Qualcomm-PPE-driver.patch @@ -0,0 +1,30 @@ +From 28098c348414fa97531449d4e27ba1587e67c2d9 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Sun, 9 Feb 2025 22:29:48 +0800 +Subject: [PATCH] MAINTAINERS: Add maintainer for Qualcomm PPE driver + +Add maintainer entry for PPE (Packet Process Engine) driver +supported for Qualcomm IPQ SoCs. + +Signed-off-by: Luo Jie +--- + MAINTAINERS | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -19131,6 +19131,14 @@ S: Maintained + F: Documentation/devicetree/bindings/mtd/qcom,nandc.yaml + F: drivers/mtd/nand/raw/qcom_nandc.c + ++QUALCOMM PPE DRIVER ++M: Luo Jie ++L: netdev@vger.kernel.org ++S: Supported ++F: Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml ++F: Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst ++F: drivers/net/ethernet/qualcomm/ppe/ ++ + QUALCOMM QSEECOM DRIVER + M: Maximilian Luz + L: linux-arm-msm@vger.kernel.org diff --git a/target/linux/qualcommbe/patches-6.12/0337-net-ethernet-qualcomm-Add-PPE-scheduler-config.patch b/target/linux/qualcommbe/patches-6.12/0337-net-ethernet-qualcomm-Add-PPE-scheduler-config.patch new file mode 100644 index 0000000000..d6292f8bf5 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0337-net-ethernet-qualcomm-Add-PPE-scheduler-config.patch @@ -0,0 +1,201 @@ +From 93cf3297818ee61607f0a8d1d34e4fb7fcde3cdf Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Tue, 26 Dec 2023 20:18:09 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Add PPE scheduler config + +PPE scheduler config determines the priority of scheduling the +packet. The scheduler config is used for supporting the QoS +offload in PPE hardware. + +Change-Id: I4811bd133074757371775a6a69a1cc3cfaa8d0d0 +Signed-off-by: Luo Jie +Alex G: rebase patch on top of PPE driver submission from 20250209. + Add the ppe_queue_priority_set() function and its + dependencies. They will be used in the edma support in + susequent changes. + ppe_queue_priority_set() used to be part of ppe_api.c, and + is hereby moved to ppe_config.c . +Signed-off-by: Alexandru Gagniuc +--- + .../net/ethernet/qualcomm/ppe/ppe_config.c | 141 ++++++++++++++++++ + .../net/ethernet/qualcomm/ppe/ppe_config.h | 5 + + 2 files changed, 146 insertions(+) + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +@@ -864,6 +864,51 @@ static int ppe_scheduler_l0_queue_map_se + val); + } + ++/* Get the first level scheduler configuration. */ ++static int ppe_scheduler_l0_queue_map_get(struct ppe_device *ppe_dev, ++ int node_id, int *port, ++ struct ppe_scheduler_cfg *scheduler_cfg) ++{ ++ u32 val, reg; ++ int ret; ++ ++ reg = PPE_L0_FLOW_MAP_TBL_ADDR + node_id * PPE_L0_FLOW_MAP_TBL_INC; ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) ++ return ret; ++ ++ scheduler_cfg->flow_id = FIELD_GET(PPE_L0_FLOW_MAP_TBL_FLOW_ID, val); ++ scheduler_cfg->pri = FIELD_GET(PPE_L0_FLOW_MAP_TBL_C_PRI, val); ++ scheduler_cfg->drr_node_wt = FIELD_GET(PPE_L0_FLOW_MAP_TBL_C_NODE_WT, val); ++ ++ reg = PPE_L0_C_FLOW_CFG_TBL_ADDR + ++ (scheduler_cfg->flow_id * PPE_QUEUE_SCH_PRI_NUM + scheduler_cfg->pri) * ++ PPE_L0_C_FLOW_CFG_TBL_INC; ++ ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) ++ return ret; ++ ++ scheduler_cfg->drr_node_id = FIELD_GET(PPE_L0_C_FLOW_CFG_TBL_NODE_ID, val); ++ scheduler_cfg->unit_is_packet = FIELD_GET(PPE_L0_C_FLOW_CFG_TBL_NODE_CREDIT_UNIT, val); ++ ++ reg = PPE_L0_FLOW_PORT_MAP_TBL_ADDR + node_id * PPE_L0_FLOW_PORT_MAP_TBL_INC; ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) ++ return ret; ++ ++ *port = FIELD_GET(PPE_L0_FLOW_PORT_MAP_TBL_PORT_NUM, val); ++ ++ reg = PPE_L0_COMP_CFG_TBL_ADDR + node_id * PPE_L0_COMP_CFG_TBL_INC; ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) ++ return ret; ++ ++ scheduler_cfg->frame_mode = FIELD_GET(PPE_L0_COMP_CFG_TBL_NODE_METER_LEN, val); ++ ++ return 0; ++} ++ + /* Set the PPE flow level scheduler configuration. */ + static int ppe_scheduler_l1_queue_map_set(struct ppe_device *ppe_dev, + int node_id, int port, +@@ -916,6 +961,50 @@ static int ppe_scheduler_l1_queue_map_se + return regmap_update_bits(ppe_dev->regmap, reg, PPE_L1_COMP_CFG_TBL_NODE_METER_LEN, val); + } + ++/* Get the second level scheduler configuration. */ ++static int ppe_scheduler_l1_queue_map_get(struct ppe_device *ppe_dev, ++ int node_id, int *port, ++ struct ppe_scheduler_cfg *scheduler_cfg) ++{ ++ u32 val, reg; ++ int ret; ++ ++ reg = PPE_L1_FLOW_MAP_TBL_ADDR + node_id * PPE_L1_FLOW_MAP_TBL_INC; ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) ++ return ret; ++ ++ scheduler_cfg->flow_id = FIELD_GET(PPE_L1_FLOW_MAP_TBL_FLOW_ID, val); ++ scheduler_cfg->pri = FIELD_GET(PPE_L1_FLOW_MAP_TBL_C_PRI, val); ++ scheduler_cfg->drr_node_wt = FIELD_GET(PPE_L1_FLOW_MAP_TBL_C_NODE_WT, val); ++ ++ reg = PPE_L1_C_FLOW_CFG_TBL_ADDR + ++ (scheduler_cfg->flow_id * PPE_QUEUE_SCH_PRI_NUM + scheduler_cfg->pri) * ++ PPE_L1_C_FLOW_CFG_TBL_INC; ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) ++ return ret; ++ ++ scheduler_cfg->drr_node_id = FIELD_GET(PPE_L1_C_FLOW_CFG_TBL_NODE_ID, val); ++ scheduler_cfg->unit_is_packet = FIELD_GET(PPE_L1_C_FLOW_CFG_TBL_NODE_CREDIT_UNIT, val); ++ ++ reg = PPE_L1_FLOW_PORT_MAP_TBL_ADDR + node_id * PPE_L1_FLOW_PORT_MAP_TBL_INC; ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) ++ return ret; ++ ++ *port = FIELD_GET(PPE_L1_FLOW_PORT_MAP_TBL_PORT_NUM, val); ++ ++ reg = PPE_L1_COMP_CFG_TBL_ADDR + node_id * PPE_L1_COMP_CFG_TBL_INC; ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) ++ return ret; ++ ++ scheduler_cfg->frame_mode = FIELD_GET(PPE_L1_COMP_CFG_TBL_NODE_METER_LEN, val); ++ ++ return 0; ++} ++ + /** + * ppe_queue_scheduler_set - Configure scheduler for PPE hardware queue + * @ppe_dev: PPE device +@@ -942,6 +1031,58 @@ int ppe_queue_scheduler_set(struct ppe_d + } + + /** ++ * ppe_queue_scheduler_get - get QoS scheduler of PPE hardware queue ++ * @ppe_dev: PPE device ++ * @node_id: PPE node ID ++ * @flow_level: Flow level scheduler or queue level scheduler ++ * @port: PPE port ID to get scheduler config ++ * @scheduler_cfg: QoS scheduler configuration ++ * ++ * The hardware QoS function is supported by PPE, the current scheduler ++ * configuration can be acquired based on the queue ID of PPE port. ++ * ++ * Return 0 on success, negative error code on failure. ++ */ ++int ppe_queue_scheduler_get(struct ppe_device *ppe_dev, ++ int node_id, bool flow_level, int *port, ++ struct ppe_scheduler_cfg *scheduler_cfg) ++{ ++ if (flow_level) ++ return ppe_scheduler_l1_queue_map_get(ppe_dev, node_id, ++ port, scheduler_cfg); ++ ++ return ppe_scheduler_l0_queue_map_get(ppe_dev, node_id, ++ port, scheduler_cfg); ++} ++ ++ ++/** ++ * ppe_queue_priority_set - set scheduler priority of PPE hardware queue ++ * @ppe_dev: PPE device ++ * @node_id: PPE hardware node ID, which is either queue ID or flow ID ++ * @priority: Qos scheduler priority ++ * ++ * Configure scheduler priority of PPE hardware queque, the maximum node ++ * ID supported is PPE_QUEUE_ID_NUM added by PPE_FLOW_ID_NUM, queue ID ++ * belongs to level 0, flow ID belongs to level 1 in the packet pipeline. ++ * ++ * Return 0 on success, negative error code on failure. ++ */ ++int ppe_queue_priority_set(struct ppe_device *ppe_dev, ++ int node_id, int priority) ++{ ++ struct ppe_scheduler_cfg sch_cfg; ++ int ret, port, level = 0; ++ ++ ret = ppe_queue_scheduler_get(ppe_dev, node_id, level, &port, &sch_cfg); ++ if (ret) ++ return ret; ++ ++ sch_cfg.pri = priority; ++ return ppe_queue_scheduler_set(ppe_dev, node_id, level, port, sch_cfg); ++} ++ ++/** + * ppe_queue_ucast_base_set - Set PPE unicast queue base ID and profile ID + * @ppe_dev: PPE device + * @queue_dst: PPE queue destination configuration +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h +@@ -291,6 +291,11 @@ int ppe_hw_config(struct ppe_device *ppe + int ppe_queue_scheduler_set(struct ppe_device *ppe_dev, + int node_id, bool flow_level, int port, + struct ppe_scheduler_cfg scheduler_cfg); ++int ppe_queue_scheduler_get(struct ppe_device *ppe_dev, ++ int node_id, bool flow_level, int *port, ++ struct ppe_scheduler_cfg *scheduler_cfg); ++int ppe_queue_priority_set(struct ppe_device *ppe_dev, ++ int queue_id, int priority); + int ppe_queue_ucast_base_set(struct ppe_device *ppe_dev, + struct ppe_queue_ucast_dest queue_dst, + int queue_base, diff --git a/target/linux/qualcommbe/patches-6.12/0338-net-ethernet-qualcomm-Add-phylink-support-for-PPE-MA.patch b/target/linux/qualcommbe/patches-6.12/0338-net-ethernet-qualcomm-Add-phylink-support-for-PPE-MA.patch new file mode 100644 index 0000000000..348e834f80 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0338-net-ethernet-qualcomm-Add-phylink-support-for-PPE-MA.patch @@ -0,0 +1,1040 @@ +From dbb3711ab25ea410ad5286b2f39dccd954cda225 Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Thu, 29 Feb 2024 16:59:53 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Add phylink support for PPE MAC + ports + +Add MAC initialization and phylink functions for PPE MAC ports. + +Change-Id: I39dcba671732392bcfa2e734473fd083989bfbec +Signed-off-by: Lei Wei +--- + drivers/net/ethernet/qualcomm/Kconfig | 3 + + drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +- + drivers/net/ethernet/qualcomm/ppe/ppe.c | 9 + + drivers/net/ethernet/qualcomm/ppe/ppe.h | 2 + + drivers/net/ethernet/qualcomm/ppe/ppe_port.c | 728 +++++++++++++++++++ + drivers/net/ethernet/qualcomm/ppe/ppe_port.h | 76 ++ + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 124 ++++ + 7 files changed, 943 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe_port.c + create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe_port.h + +--- a/drivers/net/ethernet/qualcomm/Kconfig ++++ b/drivers/net/ethernet/qualcomm/Kconfig +@@ -66,6 +66,9 @@ config QCOM_PPE + depends on HAS_IOMEM && OF + depends on COMMON_CLK + select REGMAP_MMIO ++ select PHYLINK ++ select PCS_QCOM_IPQ_UNIPHY ++ select SFP + help + This driver supports the Qualcomm Technologies, Inc. packet + process engine (PPE) available with IPQ SoC. The PPE includes +--- a/drivers/net/ethernet/qualcomm/ppe/Makefile ++++ b/drivers/net/ethernet/qualcomm/ppe/Makefile +@@ -4,4 +4,4 @@ + # + + obj-$(CONFIG_QCOM_PPE) += qcom-ppe.o +-qcom-ppe-objs := ppe.o ppe_config.o ppe_debugfs.o ++qcom-ppe-objs := ppe.o ppe_config.o ppe_debugfs.o ppe_port.o +--- a/drivers/net/ethernet/qualcomm/ppe/ppe.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe.c +@@ -17,6 +17,7 @@ + #include "ppe.h" + #include "ppe_config.h" + #include "ppe_debugfs.h" ++#include "ppe_port.h" + + #define PPE_PORT_MAX 8 + #define PPE_CLK_RATE 353000000 +@@ -200,6 +201,11 @@ static int qcom_ppe_probe(struct platfor + if (ret) + return dev_err_probe(dev, ret, "PPE HW config failed\n"); + ++ ret = ppe_port_mac_init(ppe_dev); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "PPE Port MAC initialization failed\n"); ++ + ppe_debugfs_setup(ppe_dev); + platform_set_drvdata(pdev, ppe_dev); + +@@ -212,6 +218,9 @@ static void qcom_ppe_remove(struct platf + + ppe_dev = platform_get_drvdata(pdev); + ppe_debugfs_teardown(ppe_dev); ++ ppe_port_mac_deinit(ppe_dev); ++ ++ platform_set_drvdata(pdev, NULL); + } + + static const struct of_device_id qcom_ppe_of_match[] = { +--- a/drivers/net/ethernet/qualcomm/ppe/ppe.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe.h +@@ -20,6 +20,7 @@ struct dentry; + * @clk_rate: PPE clock rate. + * @num_ports: Number of PPE ports. + * @debugfs_root: Debugfs root entry. ++ * @ports: PPE MAC ports. + * @num_icc_paths: Number of interconnect paths. + * @icc_paths: Interconnect path array. + * +@@ -33,6 +34,7 @@ struct ppe_device { + unsigned long clk_rate; + unsigned int num_ports; + struct dentry *debugfs_root; ++ struct ppe_ports *ports; + unsigned int num_icc_paths; + struct icc_bulk_data icc_paths[] __counted_by(num_icc_paths); + }; +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.c +@@ -0,0 +1,728 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* PPE Port MAC initialization and PPE port MAC functions. */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ppe.h" ++#include "ppe_port.h" ++#include "ppe_regs.h" ++ ++/* PPE MAC max frame size which including 4bytes FCS */ ++#define PPE_PORT_MAC_MAX_FRAME_SIZE 0x3000 ++ ++/* PPE BM port start for PPE MAC ports */ ++#define PPE_BM_PORT_MAC_START 7 ++ ++/* PPE port clock and reset name */ ++static const char * const ppe_port_clk_rst_name[] = { ++ [PPE_PORT_CLK_RST_MAC] = "port_mac", ++ [PPE_PORT_CLK_RST_RX] = "port_rx", ++ [PPE_PORT_CLK_RST_TX] = "port_tx", ++}; ++ ++/* PPE port and MAC reset */ ++static int ppe_port_mac_reset(struct ppe_port *ppe_port) ++{ ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ int ret; ++ ++ ret = reset_control_assert(ppe_port->rstcs[PPE_PORT_CLK_RST_MAC]); ++ if (ret) ++ goto error; ++ ++ ret = reset_control_assert(ppe_port->rstcs[PPE_PORT_CLK_RST_RX]); ++ if (ret) ++ goto error; ++ ++ ret = reset_control_assert(ppe_port->rstcs[PPE_PORT_CLK_RST_TX]); ++ if (ret) ++ goto error; ++ ++ /* 150ms delay is required by hardware to reset PPE port and MAC */ ++ msleep(150); ++ ++ ret = reset_control_deassert(ppe_port->rstcs[PPE_PORT_CLK_RST_MAC]); ++ if (ret) ++ goto error; ++ ++ ret = reset_control_deassert(ppe_port->rstcs[PPE_PORT_CLK_RST_RX]); ++ if (ret) ++ goto error; ++ ++ ret = reset_control_deassert(ppe_port->rstcs[PPE_PORT_CLK_RST_TX]); ++ if (ret) ++ goto error; ++ ++ return ret; ++ ++error: ++ dev_err(ppe_dev->dev, "%s: port %d reset fail %d\n", ++ __func__, ppe_port->port_id, ret); ++ return ret; ++} ++ ++/* PPE port MAC configuration for phylink */ ++static void ppe_port_mac_config(struct phylink_config *config, ++ unsigned int mode, ++ const struct phylink_link_state *state) ++{ ++ struct ppe_port *ppe_port = container_of(config, struct ppe_port, ++ phylink_config); ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ int port = ppe_port->port_id; ++ enum ppe_mac_type mac_type; ++ u32 val, mask; ++ int ret; ++ ++ switch (state->interface) { ++ case PHY_INTERFACE_MODE_2500BASEX: ++ case PHY_INTERFACE_MODE_USXGMII: ++ case PHY_INTERFACE_MODE_10GBASER: ++ case PHY_INTERFACE_MODE_10G_QXGMII: ++ mac_type = PPE_MAC_TYPE_XGMAC; ++ break; ++ case PHY_INTERFACE_MODE_QSGMII: ++ case PHY_INTERFACE_MODE_PSGMII: ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_1000BASEX: ++ mac_type = PPE_MAC_TYPE_GMAC; ++ break; ++ default: ++ dev_err(ppe_dev->dev, "%s: Unsupport interface %s\n", ++ __func__, phy_modes(state->interface)); ++ return; ++ } ++ ++ /* Reset Port MAC for GMAC */ ++ if (mac_type == PPE_MAC_TYPE_GMAC) { ++ ret = ppe_port_mac_reset(ppe_port); ++ if (ret) ++ goto err_mac_config; ++ } ++ ++ /* Port mux to select GMAC or XGMAC */ ++ mask = PPE_PORT_SEL_XGMAC(port); ++ val = mac_type == PPE_MAC_TYPE_GMAC ? 0 : mask; ++ ret = regmap_update_bits(ppe_dev->regmap, ++ PPE_PORT_MUX_CTRL_ADDR, ++ mask, val); ++ if (ret) ++ goto err_mac_config; ++ ++ ppe_port->mac_type = mac_type; ++ ++ return; ++ ++err_mac_config: ++ dev_err(ppe_dev->dev, "%s: port %d MAC config fail %d\n", ++ __func__, port, ret); ++} ++ ++/* PPE port GMAC link up configuration */ ++static int ppe_port_gmac_link_up(struct ppe_port *ppe_port, int speed, ++ int duplex, bool tx_pause, bool rx_pause) ++{ ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ int ret, port = ppe_port->port_id; ++ u32 reg, val; ++ ++ /* Set GMAC speed */ ++ switch (speed) { ++ case SPEED_1000: ++ val = GMAC_SPEED_1000; ++ break; ++ case SPEED_100: ++ val = GMAC_SPEED_100; ++ break; ++ case SPEED_10: ++ val = GMAC_SPEED_10; ++ break; ++ default: ++ dev_err(ppe_dev->dev, "%s: Invalid GMAC speed %s\n", ++ __func__, phy_speed_to_str(speed)); ++ return -EINVAL; ++ } ++ ++ reg = PPE_PORT_GMAC_ADDR(port); ++ ret = regmap_update_bits(ppe_dev->regmap, reg + GMAC_SPEED_ADDR, ++ GMAC_SPEED_M, val); ++ if (ret) ++ return ret; ++ ++ /* Set duplex, flow control and enable GMAC */ ++ val = GMAC_TRXEN; ++ if (duplex == DUPLEX_FULL) ++ val |= GMAC_DUPLEX_FULL; ++ if (tx_pause) ++ val |= GMAC_TXFCEN; ++ if (rx_pause) ++ val |= GMAC_RXFCEN; ++ ++ ret = regmap_update_bits(ppe_dev->regmap, reg + GMAC_ENABLE_ADDR, ++ GMAC_ENABLE_ALL, val); ++ ++ return ret; ++} ++ ++/* PPE port XGMAC link up configuration */ ++static int ppe_port_xgmac_link_up(struct ppe_port *ppe_port, ++ phy_interface_t interface, ++ int speed, int duplex, ++ bool tx_pause, bool rx_pause) ++{ ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ int ret, port = ppe_port->port_id; ++ u32 reg, val; ++ ++ /* Set XGMAC TX speed and enable TX */ ++ switch (speed) { ++ case SPEED_10000: ++ if (interface == PHY_INTERFACE_MODE_USXGMII) ++ val = XGMAC_SPEED_10000_USXGMII; ++ else ++ val = XGMAC_SPEED_10000; ++ break; ++ case SPEED_5000: ++ val = XGMAC_SPEED_5000; ++ break; ++ case SPEED_2500: ++ if (interface == PHY_INTERFACE_MODE_USXGMII || ++ interface == PHY_INTERFACE_MODE_10G_QXGMII) ++ val = XGMAC_SPEED_2500_USXGMII; ++ else ++ val = XGMAC_SPEED_2500; ++ break; ++ case SPEED_1000: ++ val = XGMAC_SPEED_1000; ++ break; ++ case SPEED_100: ++ val = XGMAC_SPEED_100; ++ break; ++ case SPEED_10: ++ val = XGMAC_SPEED_10; ++ break; ++ default: ++ dev_err(ppe_dev->dev, "%s: Invalid XGMAC speed %s\n", ++ __func__, phy_speed_to_str(speed)); ++ return -EINVAL; ++ } ++ ++ reg = PPE_PORT_XGMAC_ADDR(port); ++ val |= XGMAC_TXEN; ++ ret = regmap_update_bits(ppe_dev->regmap, reg + XGMAC_TX_CONFIG_ADDR, ++ XGMAC_SPEED_M | XGMAC_TXEN, val); ++ if (ret) ++ return ret; ++ ++ /* Set XGMAC TX flow control */ ++ val = FIELD_PREP(XGMAC_PAUSE_TIME_M, FIELD_MAX(XGMAC_PAUSE_TIME_M)); ++ val |= tx_pause ? XGMAC_TXFCEN : 0; ++ ret = regmap_update_bits(ppe_dev->regmap, reg + XGMAC_TX_FLOW_CTRL_ADDR, ++ XGMAC_PAUSE_TIME_M | XGMAC_TXFCEN, val); ++ if (ret) ++ return ret; ++ ++ /* Set XGMAC RX flow control */ ++ val = rx_pause ? XGMAC_RXFCEN : 0; ++ ret = regmap_update_bits(ppe_dev->regmap, reg + XGMAC_RX_FLOW_CTRL_ADDR, ++ XGMAC_RXFCEN, val); ++ if (ret) ++ return ret; ++ ++ /* Enable XGMAC RX*/ ++ ret = regmap_update_bits(ppe_dev->regmap, reg + XGMAC_RX_CONFIG_ADDR, ++ XGMAC_RXEN, XGMAC_RXEN); ++ ++ return ret; ++} ++ ++/* PPE port MAC link up configuration for phylink */ ++static void ppe_port_mac_link_up(struct phylink_config *config, ++ struct phy_device *phy, ++ unsigned int mode, ++ phy_interface_t interface, ++ int speed, int duplex, ++ bool tx_pause, bool rx_pause) ++{ ++ struct ppe_port *ppe_port = container_of(config, struct ppe_port, ++ phylink_config); ++ enum ppe_mac_type mac_type = ppe_port->mac_type; ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ int ret, port = ppe_port->port_id; ++ u32 reg, val; ++ ++ if (mac_type == PPE_MAC_TYPE_GMAC) ++ ret = ppe_port_gmac_link_up(ppe_port, ++ speed, duplex, tx_pause, rx_pause); ++ else ++ ret = ppe_port_xgmac_link_up(ppe_port, interface, ++ speed, duplex, tx_pause, rx_pause); ++ if (ret) ++ goto err_port_mac_link_up; ++ ++ /* Set PPE port BM flow control */ ++ reg = PPE_BM_PORT_FC_MODE_ADDR + ++ PPE_BM_PORT_FC_MODE_INC * (port + PPE_BM_PORT_MAC_START); ++ val = tx_pause ? PPE_BM_PORT_FC_MODE_EN : 0; ++ ret = regmap_update_bits(ppe_dev->regmap, reg, ++ PPE_BM_PORT_FC_MODE_EN, val); ++ if (ret) ++ goto err_port_mac_link_up; ++ ++ /* Enable PPE port TX */ ++ reg = PPE_PORT_BRIDGE_CTRL_ADDR + PPE_PORT_BRIDGE_CTRL_INC * port; ++ ret = regmap_update_bits(ppe_dev->regmap, reg, ++ PPE_PORT_BRIDGE_TXMAC_EN, ++ PPE_PORT_BRIDGE_TXMAC_EN); ++ if (ret) ++ goto err_port_mac_link_up; ++ ++ return; ++ ++err_port_mac_link_up: ++ dev_err(ppe_dev->dev, "%s: port %d link up fail %d\n", ++ __func__, port, ret); ++} ++ ++/* PPE port MAC link down configuration for phylink */ ++static void ppe_port_mac_link_down(struct phylink_config *config, ++ unsigned int mode, ++ phy_interface_t interface) ++{ ++ struct ppe_port *ppe_port = container_of(config, struct ppe_port, ++ phylink_config); ++ enum ppe_mac_type mac_type = ppe_port->mac_type; ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ int ret, port = ppe_port->port_id; ++ u32 reg; ++ ++ /* Disable PPE port TX */ ++ reg = PPE_PORT_BRIDGE_CTRL_ADDR + PPE_PORT_BRIDGE_CTRL_INC * port; ++ ret = regmap_update_bits(ppe_dev->regmap, reg, ++ PPE_PORT_BRIDGE_TXMAC_EN, 0); ++ if (ret) ++ goto err_port_mac_link_down; ++ ++ /* Disable PPE MAC */ ++ if (mac_type == PPE_MAC_TYPE_GMAC) { ++ reg = PPE_PORT_GMAC_ADDR(port) + GMAC_ENABLE_ADDR; ++ ret = regmap_update_bits(ppe_dev->regmap, reg, GMAC_TRXEN, 0); ++ if (ret) ++ goto err_port_mac_link_down; ++ } else { ++ reg = PPE_PORT_XGMAC_ADDR(port); ++ ret = regmap_update_bits(ppe_dev->regmap, ++ reg + XGMAC_RX_CONFIG_ADDR, ++ XGMAC_RXEN, 0); ++ if (ret) ++ goto err_port_mac_link_down; ++ ++ ret = regmap_update_bits(ppe_dev->regmap, ++ reg + XGMAC_TX_CONFIG_ADDR, ++ XGMAC_TXEN, 0); ++ if (ret) ++ goto err_port_mac_link_down; ++ } ++ ++ return; ++ ++err_port_mac_link_down: ++ dev_err(ppe_dev->dev, "%s: port %d link down fail %d\n", ++ __func__, port, ret); ++} ++ ++/* PPE port MAC PCS selection for phylink */ ++static ++struct phylink_pcs *ppe_port_mac_select_pcs(struct phylink_config *config, ++ phy_interface_t interface) ++{ ++ struct ppe_port *ppe_port = container_of(config, struct ppe_port, ++ phylink_config); ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ int ret, port = ppe_port->port_id; ++ u32 val; ++ ++ /* PPE port5 can connects with PCS0 or PCS1. In PSGMII ++ * mode, it selects PCS0; otherwise, it selects PCS1. ++ */ ++ if (port == 5) { ++ val = interface == PHY_INTERFACE_MODE_PSGMII ? ++ 0 : PPE_PORT5_SEL_PCS1; ++ ret = regmap_update_bits(ppe_dev->regmap, ++ PPE_PORT_MUX_CTRL_ADDR, ++ PPE_PORT5_SEL_PCS1, val); ++ if (ret) { ++ dev_err(ppe_dev->dev, "%s: port5 select PCS fail %d\n", ++ __func__, ret); ++ return NULL; ++ } ++ } ++ ++ return ppe_port->pcs; ++} ++ ++static const struct phylink_mac_ops ppe_phylink_ops = { ++ .mac_config = ppe_port_mac_config, ++ .mac_link_up = ppe_port_mac_link_up, ++ .mac_link_down = ppe_port_mac_link_down, ++ .mac_select_pcs = ppe_port_mac_select_pcs, ++}; ++ ++/** ++ * ppe_port_phylink_setup() - Set phylink instance for the given PPE port ++ * @ppe_port: PPE port ++ * @netdev: Netdevice ++ * ++ * Description: Wrapper function to help setup phylink for the PPE port ++ * specified by @ppe_port and associated with the net device @netdev. ++ * ++ * Return: 0 upon success or a negative error upon failure. ++ */ ++int ppe_port_phylink_setup(struct ppe_port *ppe_port, struct net_device *netdev) ++{ ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ struct device_node *pcs_node; ++ int ret; ++ ++ /* Create PCS */ ++ pcs_node = of_parse_phandle(ppe_port->np, "pcs-handle", 0); ++ if (!pcs_node) ++ return -ENODEV; ++ ++ ppe_port->pcs = ipq_unipcs_create(pcs_node); ++ of_node_put(pcs_node); ++ if (IS_ERR(ppe_port->pcs)) { ++ dev_err(ppe_dev->dev, "%s: port %d failed to create PCS\n", ++ __func__, ppe_port->port_id); ++ return PTR_ERR(ppe_port->pcs); ++ } ++ ++ /* Port phylink capability */ ++ ppe_port->phylink_config.dev = &netdev->dev; ++ ppe_port->phylink_config.type = PHYLINK_NETDEV; ++ ppe_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | ++ MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000 | ++ MAC_2500FD | MAC_5000FD | MAC_10000FD; ++ __set_bit(PHY_INTERFACE_MODE_QSGMII, ++ ppe_port->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_PSGMII, ++ ppe_port->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_SGMII, ++ ppe_port->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_1000BASEX, ++ ppe_port->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_2500BASEX, ++ ppe_port->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_USXGMII, ++ ppe_port->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_10GBASER, ++ ppe_port->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_10G_QXGMII, ++ ppe_port->phylink_config.supported_interfaces); ++ ++ /* Create phylink */ ++ ppe_port->phylink = phylink_create(&ppe_port->phylink_config, ++ of_fwnode_handle(ppe_port->np), ++ ppe_port->interface, ++ &ppe_phylink_ops); ++ if (IS_ERR(ppe_port->phylink)) { ++ dev_err(ppe_dev->dev, "%s: port %d failed to create phylink\n", ++ __func__, ppe_port->port_id); ++ ret = PTR_ERR(ppe_port->phylink); ++ goto err_free_pcs; ++ } ++ ++ /* Connect phylink */ ++ ret = phylink_of_phy_connect(ppe_port->phylink, ppe_port->np, 0); ++ if (ret) { ++ dev_err(ppe_dev->dev, "%s: port %d failed to connect phylink\n", ++ __func__, ppe_port->port_id); ++ goto err_free_phylink; ++ } ++ ++ return 0; ++ ++err_free_phylink: ++ phylink_destroy(ppe_port->phylink); ++ ppe_port->phylink = NULL; ++err_free_pcs: ++ ipq_unipcs_destroy(ppe_port->pcs); ++ ppe_port->pcs = NULL; ++ return ret; ++} ++ ++/** ++ * ppe_port_phylink_destroy() - Destroy phylink instance for the given PPE port ++ * @ppe_port: PPE port ++ * ++ * Description: Wrapper function to help destroy phylink for the PPE port ++ * specified by @ppe_port. ++ */ ++void ppe_port_phylink_destroy(struct ppe_port *ppe_port) ++{ ++ /* Destroy phylink */ ++ if (ppe_port->phylink) { ++ rtnl_lock(); ++ phylink_disconnect_phy(ppe_port->phylink); ++ rtnl_unlock(); ++ phylink_destroy(ppe_port->phylink); ++ ppe_port->phylink = NULL; ++ } ++ ++ /* Destroy PCS */ ++ if (ppe_port->pcs) { ++ ipq_unipcs_destroy(ppe_port->pcs); ++ ppe_port->pcs = NULL; ++ } ++} ++ ++/* PPE port clock initialization */ ++static int ppe_port_clock_init(struct ppe_port *ppe_port) ++{ ++ struct device_node *port_node = ppe_port->np; ++ struct reset_control *rstc; ++ struct clk *clk; ++ int i, j, ret; ++ ++ for (i = 0; i < PPE_PORT_CLK_RST_MAX; i++) { ++ /* Get PPE port resets which will be used to reset PPE ++ * port and MAC. ++ */ ++ rstc = of_reset_control_get_exclusive(port_node, ++ ppe_port_clk_rst_name[i]); ++ if (IS_ERR(rstc)) { ++ ret = PTR_ERR(rstc); ++ goto err_rst; ++ } ++ ++ clk = of_clk_get_by_name(port_node, ppe_port_clk_rst_name[i]); ++ if (IS_ERR(clk)) { ++ ret = PTR_ERR(clk); ++ goto err_clk_get; ++ } ++ ++ ret = clk_prepare_enable(clk); ++ if (ret) ++ goto err_clk_en; ++ ++ ppe_port->clks[i] = clk; ++ ppe_port->rstcs[i] = rstc; ++ } ++ ++ return 0; ++ ++err_clk_en: ++ clk_put(clk); ++err_clk_get: ++ reset_control_put(rstc); ++err_rst: ++ for (j = 0; j < i; j++) { ++ clk_disable_unprepare(ppe_port->clks[j]); ++ clk_put(ppe_port->clks[j]); ++ reset_control_put(ppe_port->rstcs[j]); ++ } ++ ++ return ret; ++} ++ ++/* PPE port clock deinitialization */ ++static void ppe_port_clock_deinit(struct ppe_port *ppe_port) ++{ ++ int i; ++ ++ for (i = 0; i < PPE_PORT_CLK_RST_MAX; i++) { ++ clk_disable_unprepare(ppe_port->clks[i]); ++ clk_put(ppe_port->clks[i]); ++ reset_control_put(ppe_port->rstcs[i]); ++ } ++} ++ ++/* PPE port MAC hardware init configuration */ ++static int ppe_port_mac_hw_init(struct ppe_port *ppe_port) ++{ ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ int ret, port = ppe_port->port_id; ++ u32 reg, val; ++ ++ /* GMAC RX and TX are initialized as disabled */ ++ reg = PPE_PORT_GMAC_ADDR(port); ++ ret = regmap_update_bits(ppe_dev->regmap, ++ reg + GMAC_ENABLE_ADDR, GMAC_TRXEN, 0); ++ if (ret) ++ return ret; ++ ++ /* GMAC max frame size configuration */ ++ val = FIELD_PREP(GMAC_JUMBO_SIZE_M, PPE_PORT_MAC_MAX_FRAME_SIZE); ++ ret = regmap_update_bits(ppe_dev->regmap, reg + GMAC_JUMBO_SIZE_ADDR, ++ GMAC_JUMBO_SIZE_M, val); ++ if (ret) ++ return ret; ++ ++ val = FIELD_PREP(GMAC_MAXFRAME_SIZE_M, PPE_PORT_MAC_MAX_FRAME_SIZE); ++ val |= FIELD_PREP(GMAC_TX_THD_M, 0x1); ++ ret = regmap_update_bits(ppe_dev->regmap, reg + GMAC_CTRL_ADDR, ++ GMAC_CTRL_MASK, val); ++ if (ret) ++ return ret; ++ ++ val = FIELD_PREP(GMAC_HIGH_IPG_M, 0xc); ++ ret = regmap_update_bits(ppe_dev->regmap, reg + GMAC_DBG_CTRL_ADDR, ++ GMAC_HIGH_IPG_M, val); ++ if (ret) ++ return ret; ++ ++ /* Enable and reset GMAC MIB counters and set as read clear ++ * mode, the GMAC MIB counters will be cleared after reading. ++ */ ++ ret = regmap_update_bits(ppe_dev->regmap, reg + GMAC_MIB_CTRL_ADDR, ++ GMAC_MIB_CTRL_MASK, GMAC_MIB_CTRL_MASK); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(ppe_dev->regmap, reg + GMAC_MIB_CTRL_ADDR, ++ GMAC_MIB_RST, 0); ++ if (ret) ++ return ret; ++ ++ /* XGMAC RX and TX disabled and max frame size configuration */ ++ reg = PPE_PORT_XGMAC_ADDR(port); ++ ret = regmap_update_bits(ppe_dev->regmap, reg + XGMAC_TX_CONFIG_ADDR, ++ XGMAC_TXEN | XGMAC_JD, XGMAC_JD); ++ if (ret) ++ return ret; ++ ++ val = FIELD_PREP(XGMAC_GPSL_M, PPE_PORT_MAC_MAX_FRAME_SIZE); ++ val |= XGMAC_GPSLEN; ++ val |= XGMAC_CST; ++ val |= XGMAC_ACS; ++ ret = regmap_update_bits(ppe_dev->regmap, reg + XGMAC_RX_CONFIG_ADDR, ++ XGMAC_RX_CONFIG_MASK, val); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(ppe_dev->regmap, reg + XGMAC_WD_TIMEOUT_ADDR, ++ XGMAC_WD_TIMEOUT_MASK, XGMAC_WD_TIMEOUT_VAL); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(ppe_dev->regmap, reg + XGMAC_PKT_FILTER_ADDR, ++ XGMAC_PKT_FILTER_MASK, XGMAC_PKT_FILTER_VAL); ++ if (ret) ++ return ret; ++ ++ /* Enable and reset XGMAC MIB counters */ ++ ret = regmap_update_bits(ppe_dev->regmap, reg + XGMAC_MMC_CTRL_ADDR, ++ XGMAC_MCF | XGMAC_CNTRST, XGMAC_CNTRST); ++ ++ return ret; ++} ++ ++/** ++ * ppe_port_mac_init() - Initialization of PPE ports for the PPE device ++ * @ppe_dev: PPE device ++ * ++ * Description: Initialize the PPE MAC ports on the PPE device specified ++ * by @ppe_dev. ++ * ++ * Return: 0 upon success or a negative error upon failure. ++ */ ++int ppe_port_mac_init(struct ppe_device *ppe_dev) ++{ ++ struct device_node *ports_node, *port_node; ++ int port, num, ret, j, i = 0; ++ struct ppe_ports *ppe_ports; ++ phy_interface_t phy_mode; ++ ++ ports_node = of_get_child_by_name(ppe_dev->dev->of_node, ++ "ethernet-ports"); ++ if (!ports_node) { ++ dev_err(ppe_dev->dev, "Failed to get ports node\n"); ++ return -ENODEV; ++ } ++ ++ num = of_get_available_child_count(ports_node); ++ ++ ppe_ports = devm_kzalloc(ppe_dev->dev, ++ struct_size(ppe_ports, port, num), ++ GFP_KERNEL); ++ if (!ppe_ports) { ++ ret = -ENOMEM; ++ goto err_ports_node; ++ } ++ ++ ppe_dev->ports = ppe_ports; ++ ppe_ports->num = num; ++ ++ for_each_available_child_of_node(ports_node, port_node) { ++ ret = of_property_read_u32(port_node, "reg", &port); ++ if (ret) { ++ dev_err(ppe_dev->dev, "Failed to get port id\n"); ++ goto err_port_node; ++ } ++ ++ ret = of_get_phy_mode(port_node, &phy_mode); ++ if (ret) { ++ dev_err(ppe_dev->dev, "Failed to get phy mode\n"); ++ goto err_port_node; ++ } ++ ++ ppe_ports->port[i].ppe_dev = ppe_dev; ++ ppe_ports->port[i].port_id = port; ++ ppe_ports->port[i].np = port_node; ++ ppe_ports->port[i].interface = phy_mode; ++ ++ ret = ppe_port_clock_init(&ppe_ports->port[i]); ++ if (ret) { ++ dev_err(ppe_dev->dev, "Failed to initialize port clocks\n"); ++ goto err_port_clk; ++ } ++ ++ ret = ppe_port_mac_hw_init(&ppe_ports->port[i]); ++ if (ret) { ++ dev_err(ppe_dev->dev, "Failed to initialize MAC hardware\n"); ++ goto err_port_node; ++ } ++ ++ i++; ++ } ++ ++ of_node_put(ports_node); ++ return 0; ++ ++err_port_clk: ++ for (j = 0; j < i; j++) ++ ppe_port_clock_deinit(&ppe_ports->port[j]); ++err_port_node: ++ of_node_put(port_node); ++err_ports_node: ++ of_node_put(ports_node); ++ return ret; ++} ++ ++/** ++ * ppe_port_mac_deinit() - Deinitialization of PPE ports for the PPE device ++ * @ppe_dev: PPE device ++ * ++ * Description: Deinitialize the PPE MAC ports on the PPE device specified ++ * by @ppe_dev. ++ */ ++void ppe_port_mac_deinit(struct ppe_device *ppe_dev) ++{ ++ struct ppe_port *ppe_port; ++ int i; ++ ++ for (i = 0; i < ppe_dev->ports->num; i++) { ++ ppe_port = &ppe_dev->ports->port[i]; ++ ppe_port_clock_deinit(ppe_port); ++ } ++} +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.h +@@ -0,0 +1,76 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#ifndef __PPE_PORT_H__ ++#define __PPE_PORT_H__ ++ ++#include ++ ++/** ++ * enum ppe_port_clk_rst_type - PPE port clock and reset ID type ++ * @PPE_PORT_CLK_RST_MAC: The clock and reset ID for port MAC ++ * @PPE_PORT_CLK_RST_RX: The clock and reset ID for port receive path ++ * @PPE_PORT_CLK_RST_TX: The clock and reset for port transmit path ++ * @PPE_PORT_CLK_RST_MAX: The maximum of port clock and reset ++ */ ++enum ppe_port_clk_rst_type { ++ PPE_PORT_CLK_RST_MAC, ++ PPE_PORT_CLK_RST_RX, ++ PPE_PORT_CLK_RST_TX, ++ PPE_PORT_CLK_RST_MAX, ++}; ++ ++/** ++ * enum ppe_mac_type - PPE MAC type ++ * @PPE_MAC_TYPE_GMAC: GMAC type ++ * @PPE_MAC_TYPE_XGMAC: XGMAC type ++ */ ++enum ppe_mac_type { ++ PPE_MAC_TYPE_GMAC, ++ PPE_MAC_TYPE_XGMAC, ++}; ++ ++/** ++ * struct ppe_port - Private data for each PPE port ++ * @phylink: Linux phylink instance ++ * @phylink_config: Linux phylink configurations ++ * @pcs: Linux phylink PCS instance ++ * @np: Port device tree node ++ * @ppe_dev: Back pointer to PPE device private data ++ * @interface: Port interface mode ++ * @mac_type: Port MAC type, GMAC or XGMAC ++ * @port_id: Port ID ++ * @clks: Port clocks ++ * @rstcs: Port resets ++ */ ++struct ppe_port { ++ struct phylink *phylink; ++ struct phylink_config phylink_config; ++ struct phylink_pcs *pcs; ++ struct device_node *np; ++ struct ppe_device *ppe_dev; ++ phy_interface_t interface; ++ enum ppe_mac_type mac_type; ++ int port_id; ++ struct clk *clks[PPE_PORT_CLK_RST_MAX]; ++ struct reset_control *rstcs[PPE_PORT_CLK_RST_MAX]; ++}; ++ ++/** ++ * struct ppe_ports - Array of PPE ports ++ * @num: Number of PPE ports ++ * @port: Each PPE port private data ++ */ ++struct ppe_ports { ++ unsigned int num; ++ struct ppe_port port[] __counted_by(num); ++}; ++ ++int ppe_port_mac_init(struct ppe_device *ppe_dev); ++void ppe_port_mac_deinit(struct ppe_device *ppe_dev); ++int ppe_port_phylink_setup(struct ppe_port *ppe_port, ++ struct net_device *netdev); ++void ppe_port_phylink_destroy(struct ppe_port *ppe_port); ++#endif +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -9,6 +9,17 @@ + + #include + ++/* PPE port mux select control register */ ++#define PPE_PORT_MUX_CTRL_ADDR 0x10 ++#define PPE_PORT6_SEL_XGMAC BIT(13) ++#define PPE_PORT5_SEL_XGMAC BIT(12) ++#define PPE_PORT4_SEL_XGMAC BIT(11) ++#define PPE_PORT3_SEL_XGMAC BIT(10) ++#define PPE_PORT2_SEL_XGMAC BIT(9) ++#define PPE_PORT1_SEL_XGMAC BIT(8) ++#define PPE_PORT5_SEL_PCS1 BIT(4) ++#define PPE_PORT_SEL_XGMAC(x) (BIT(8) << ((x) - 1)) ++ + /* PPE scheduler configurations for buffer manager block. */ + #define PPE_BM_SCH_CTRL_ADDR 0xb000 + #define PPE_BM_SCH_CTRL_INC 4 +@@ -556,4 +567,117 @@ + #define PPE_ENQ_OPR_TBL_ENTRIES 300 + #define PPE_ENQ_OPR_TBL_INC 0x10 + #define PPE_ENQ_OPR_TBL_ENQ_DISABLE BIT(0) ++ ++/* PPE GMAC and XGMAC register base address */ ++#define PPE_PORT_GMAC_ADDR(x) (0x001000 + ((x) - 1) * 0x200) ++#define PPE_PORT_XGMAC_ADDR(x) (0x500000 + ((x) - 1) * 0x4000) ++ ++/* GMAC enable register */ ++#define GMAC_ENABLE_ADDR 0x0 ++#define GMAC_TXFCEN BIT(6) ++#define GMAC_RXFCEN BIT(5) ++#define GMAC_DUPLEX_FULL BIT(4) ++#define GMAC_TXEN BIT(1) ++#define GMAC_RXEN BIT(0) ++ ++#define GMAC_TRXEN \ ++ (GMAC_TXEN | GMAC_RXEN) ++#define GMAC_ENABLE_ALL \ ++ (GMAC_TXFCEN | GMAC_RXFCEN | GMAC_DUPLEX_FULL | GMAC_TXEN | GMAC_RXEN) ++ ++/* GMAC speed register */ ++#define GMAC_SPEED_ADDR 0x4 ++#define GMAC_SPEED_M GENMASK(1, 0) ++#define GMAC_SPEED_10 0 ++#define GMAC_SPEED_100 1 ++#define GMAC_SPEED_1000 2 ++ ++/* GMAC control register */ ++#define GMAC_CTRL_ADDR 0x18 ++#define GMAC_TX_THD_M GENMASK(27, 24) ++#define GMAC_MAXFRAME_SIZE_M GENMASK(21, 8) ++#define GMAC_CRS_SEL BIT(6) ++ ++#define GMAC_CTRL_MASK \ ++ (GMAC_TX_THD_M | GMAC_MAXFRAME_SIZE_M | GMAC_CRS_SEL) ++ ++/* GMAC debug control register */ ++#define GMAC_DBG_CTRL_ADDR 0x1c ++#define GMAC_HIGH_IPG_M GENMASK(15, 8) ++ ++/* GMAC jumbo size register */ ++#define GMAC_JUMBO_SIZE_ADDR 0x30 ++#define GMAC_JUMBO_SIZE_M GENMASK(13, 0) ++ ++/* GMAC MIB control register */ ++#define GMAC_MIB_CTRL_ADDR 0x34 ++#define GMAC_MIB_RD_CLR BIT(2) ++#define GMAC_MIB_RST BIT(1) ++#define GMAC_MIB_EN BIT(0) ++ ++#define GMAC_MIB_CTRL_MASK \ ++ (GMAC_MIB_RD_CLR | GMAC_MIB_RST | GMAC_MIB_EN) ++ ++/* XGMAC TX configuration register */ ++#define XGMAC_TX_CONFIG_ADDR 0x0 ++#define XGMAC_SPEED_M GENMASK(31, 29) ++#define XGMAC_SPEED_10000_USXGMII FIELD_PREP(XGMAC_SPEED_M, 4) ++#define XGMAC_SPEED_10000 FIELD_PREP(XGMAC_SPEED_M, 0) ++#define XGMAC_SPEED_5000 FIELD_PREP(XGMAC_SPEED_M, 5) ++#define XGMAC_SPEED_2500_USXGMII FIELD_PREP(XGMAC_SPEED_M, 6) ++#define XGMAC_SPEED_2500 FIELD_PREP(XGMAC_SPEED_M, 2) ++#define XGMAC_SPEED_1000 FIELD_PREP(XGMAC_SPEED_M, 3) ++#define XGMAC_SPEED_100 XGMAC_SPEED_1000 ++#define XGMAC_SPEED_10 XGMAC_SPEED_1000 ++#define XGMAC_JD BIT(16) ++#define XGMAC_TXEN BIT(0) ++ ++/* XGMAC RX configuration register */ ++#define XGMAC_RX_CONFIG_ADDR 0x4 ++#define XGMAC_GPSL_M GENMASK(29, 16) ++#define XGMAC_WD BIT(7) ++#define XGMAC_GPSLEN BIT(6) ++#define XGMAC_CST BIT(2) ++#define XGMAC_ACS BIT(1) ++#define XGMAC_RXEN BIT(0) ++ ++#define XGMAC_RX_CONFIG_MASK \ ++ (XGMAC_GPSL_M | XGMAC_WD | XGMAC_GPSLEN | XGMAC_CST | \ ++ XGMAC_ACS | XGMAC_RXEN) ++ ++/* XGMAC packet filter register */ ++#define XGMAC_PKT_FILTER_ADDR 0x8 ++#define XGMAC_RA BIT(31) ++#define XGMAC_PCF_M GENMASK(7, 6) ++#define XGMAC_PR BIT(0) ++ ++#define XGMAC_PKT_FILTER_MASK \ ++ (XGMAC_RA | XGMAC_PCF_M | XGMAC_PR) ++#define XGMAC_PKT_FILTER_VAL \ ++ (XGMAC_RA | XGMAC_PR | FIELD_PREP(XGMAC_PCF_M, 0x2)) ++ ++/* XGMAC watchdog timeout register */ ++#define XGMAC_WD_TIMEOUT_ADDR 0xc ++#define XGMAC_PWE BIT(8) ++#define XGMAC_WTO_M GENMASK(3, 0) ++ ++#define XGMAC_WD_TIMEOUT_MASK \ ++ (XGMAC_PWE | XGMAC_WTO_M) ++#define XGMAC_WD_TIMEOUT_VAL \ ++ (XGMAC_PWE | FIELD_PREP(XGMAC_WTO_M, 0xb)) ++ ++/* XGMAC TX flow control register */ ++#define XGMAC_TX_FLOW_CTRL_ADDR 0x70 ++#define XGMAC_PAUSE_TIME_M GENMASK(31, 16) ++#define XGMAC_TXFCEN BIT(1) ++ ++/* XGMAC RX flow control register */ ++#define XGMAC_RX_FLOW_CTRL_ADDR 0x90 ++#define XGMAC_RXFCEN BIT(0) ++ ++/* XGMAC management counters control register */ ++#define XGMAC_MMC_CTRL_ADDR 0x800 ++#define XGMAC_MCF BIT(3) ++#define XGMAC_CNTRST BIT(0) ++ + #endif diff --git a/target/linux/qualcommbe/patches-6.12/0339-net-ethernet-qualcomm-Add-PPE-port-MAC-MIB-statistic.patch b/target/linux/qualcommbe/patches-6.12/0339-net-ethernet-qualcomm-Add-PPE-port-MAC-MIB-statistic.patch new file mode 100644 index 0000000000..1430692a6f --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0339-net-ethernet-qualcomm-Add-PPE-port-MAC-MIB-statistic.patch @@ -0,0 +1,673 @@ +From dbcc0d01241a1353d8e11e764cf7fcd390ae3f1f Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Thu, 29 Feb 2024 20:16:14 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Add PPE port MAC MIB statistics + functions + +Add PPE port MAC MIB statistics functions which are used by netdev +ops and ethtool. For GMAC, a polling task is scheduled to read the +MIB counters periodically to avoid 32bit register counter overflow. + +Change-Id: Ic20e240061278f77d703f652e1f7d959db8fac37 +Signed-off-by: Lei Wei +--- + drivers/net/ethernet/qualcomm/ppe/ppe_port.c | 465 +++++++++++++++++++ + drivers/net/ethernet/qualcomm/ppe/ppe_port.h | 13 + + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 91 ++++ + 3 files changed, 569 insertions(+) + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.c +@@ -23,6 +23,122 @@ + /* PPE BM port start for PPE MAC ports */ + #define PPE_BM_PORT_MAC_START 7 + ++/* Poll interval time to poll GMAC MIBs for overflow protection, ++ * the time should ensure that the 32bit GMAC packet counter ++ * register would not overflow within this time at line rate ++ * speed for 64B packet size. ++ */ ++#define PPE_GMIB_POLL_INTERVAL_MS 120000 ++ ++#define PPE_MAC_MIB_DESC(_s, _o, _n) \ ++ { \ ++ .size = (_s), \ ++ .offset = (_o), \ ++ .name = (_n), \ ++ } ++ ++/* PPE MAC MIB description */ ++struct ppe_mac_mib_info { ++ u32 size; ++ u32 offset; ++ const char *name; ++}; ++ ++/* PPE GMAC MIB statistics type */ ++enum ppe_gmib_stats_type { ++ gmib_rx_broadcast, ++ gmib_rx_pause, ++ gmib_rx_multicast, ++ gmib_rx_fcserr, ++ gmib_rx_alignerr, ++ gmib_rx_runt, ++ gmib_rx_frag, ++ gmib_rx_jumbofcserr, ++ gmib_rx_jumboalignerr, ++ gmib_rx_pkt64, ++ gmib_rx_pkt65to127, ++ gmib_rx_pkt128to255, ++ gmib_rx_pkt256to511, ++ gmib_rx_pkt512to1023, ++ gmib_rx_pkt1024to1518, ++ gmib_rx_pkt1519tomax, ++ gmib_rx_toolong, ++ gmib_rx_bytes_g, ++ gmib_rx_bytes_b, ++ gmib_rx_unicast, ++ gmib_tx_broadcast, ++ gmib_tx_pause, ++ gmib_tx_multicast, ++ gmib_tx_underrun, ++ gmib_tx_pkt64, ++ gmib_tx_pkt65to127, ++ gmib_tx_pkt128to255, ++ gmib_tx_pkt256to511, ++ gmib_tx_pkt512to1023, ++ gmib_tx_pkt1024to1518, ++ gmib_tx_pkt1519tomax, ++ gmib_tx_bytes, ++ gmib_tx_collisions, ++ gmib_tx_abortcol, ++ gmib_tx_multicol, ++ gmib_tx_singlecol, ++ gmib_tx_excdeffer, ++ gmib_tx_deffer, ++ gmib_tx_latecol, ++ gmib_tx_unicast, ++}; ++ ++/* PPE XGMAC MIB statistics type */ ++enum ppe_xgmib_stats_type { ++ xgmib_tx_bytes, ++ xgmib_tx_frames, ++ xgmib_tx_broadcast_g, ++ xgmib_tx_multicast_g, ++ xgmib_tx_pkt64, ++ xgmib_tx_pkt65to127, ++ xgmib_tx_pkt128to255, ++ xgmib_tx_pkt256to511, ++ xgmib_tx_pkt512to1023, ++ xgmib_tx_pkt1024tomax, ++ xgmib_tx_unicast, ++ xgmib_tx_multicast, ++ xgmib_tx_broadcast, ++ xgmib_tx_underflow_err, ++ xgmib_tx_bytes_g, ++ xgmib_tx_frames_g, ++ xgmib_tx_pause, ++ xgmib_tx_vlan_g, ++ xgmib_tx_lpi_usec, ++ xgmib_tx_lpi_tran, ++ xgmib_rx_frames, ++ xgmib_rx_bytes, ++ xgmib_rx_bytes_g, ++ xgmib_rx_broadcast_g, ++ xgmib_rx_multicast_g, ++ xgmib_rx_crc_err, ++ xgmib_rx_runt_err, ++ xgmib_rx_jabber_err, ++ xgmib_rx_undersize_g, ++ xgmib_rx_oversize_g, ++ xgmib_rx_pkt64, ++ xgmib_rx_pkt65to127, ++ xgmib_rx_pkt128to255, ++ xgmib_rx_pkt256to511, ++ xgmib_rx_pkt512to1023, ++ xgmib_rx_pkt1024tomax, ++ xgmib_rx_unicast_g, ++ xgmib_rx_len_err, ++ xgmib_rx_outofrange_err, ++ xgmib_rx_pause, ++ xgmib_rx_fifo_overflow, ++ xgmib_rx_vlan, ++ xgmib_rx_wdog_err, ++ xgmib_rx_lpi_usec, ++ xgmib_rx_lpi_tran, ++ xgmib_rx_drop_frames, ++ xgmib_rx_drop_bytes, ++}; ++ + /* PPE port clock and reset name */ + static const char * const ppe_port_clk_rst_name[] = { + [PPE_PORT_CLK_RST_MAC] = "port_mac", +@@ -30,6 +146,322 @@ static const char * const ppe_port_clk_r + [PPE_PORT_CLK_RST_TX] = "port_tx", + }; + ++/* PPE GMAC MIB statistics description information */ ++static const struct ppe_mac_mib_info gmib_info[] = { ++ PPE_MAC_MIB_DESC(4, GMAC_RXBROAD_ADDR, "rx_broadcast"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXPAUSE_ADDR, "rx_pause"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXMULTI_ADDR, "rx_multicast"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXFCSERR_ADDR, "rx_fcserr"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXALIGNERR_ADDR, "rx_alignerr"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXRUNT_ADDR, "rx_runt"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXFRAG_ADDR, "rx_frag"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXJUMBOFCSERR_ADDR, "rx_jumbofcserr"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXJUMBOALIGNERR_ADDR, "rx_jumboalignerr"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXPKT64_ADDR, "rx_pkt64"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXPKT65TO127_ADDR, "rx_pkt65to127"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXPKT128TO255_ADDR, "rx_pkt128to255"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXPKT256TO511_ADDR, "rx_pkt256to511"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXPKT512TO1023_ADDR, "rx_pkt512to1023"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXPKT1024TO1518_ADDR, "rx_pkt1024to1518"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXPKT1519TOX_ADDR, "rx_pkt1519tomax"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXTOOLONG_ADDR, "rx_toolong"), ++ PPE_MAC_MIB_DESC(8, GMAC_RXBYTE_G_ADDR, "rx_bytes_g"), ++ PPE_MAC_MIB_DESC(8, GMAC_RXBYTE_B_ADDR, "rx_bytes_b"), ++ PPE_MAC_MIB_DESC(4, GMAC_RXUNI_ADDR, "rx_unicast"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXBROAD_ADDR, "tx_broadcast"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXPAUSE_ADDR, "tx_pause"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXMULTI_ADDR, "tx_multicast"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXUNDERRUN_ADDR, "tx_underrun"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXPKT64_ADDR, "tx_pkt64"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXPKT65TO127_ADDR, "tx_pkt65to127"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXPKT128TO255_ADDR, "tx_pkt128to255"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXPKT256TO511_ADDR, "tx_pkt256to511"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXPKT512TO1023_ADDR, "tx_pkt512to1023"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXPKT1024TO1518_ADDR, "tx_pkt1024to1518"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXPKT1519TOX_ADDR, "tx_pkt1519tomax"), ++ PPE_MAC_MIB_DESC(8, GMAC_TXBYTE_ADDR, "tx_bytes"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXCOLLISIONS_ADDR, "tx_collisions"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXABORTCOL_ADDR, "tx_abortcol"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXMULTICOL_ADDR, "tx_multicol"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXSINGLECOL_ADDR, "tx_singlecol"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXEXCESSIVEDEFER_ADDR, "tx_excdeffer"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXDEFER_ADDR, "tx_deffer"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXLATECOL_ADDR, "tx_latecol"), ++ PPE_MAC_MIB_DESC(4, GMAC_TXUNI_ADDR, "tx_unicast"), ++}; ++ ++/* PPE XGMAC MIB statistics description information */ ++static const struct ppe_mac_mib_info xgmib_info[] = { ++ PPE_MAC_MIB_DESC(8, XGMAC_TXBYTE_GB_ADDR, "tx_bytes"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXPKT_GB_ADDR, "tx_frames"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXBROAD_G_ADDR, "tx_broadcast_g"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXMULTI_G_ADDR, "tx_multicast_g"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXPKT64_GB_ADDR, "tx_pkt64"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXPKT65TO127_GB_ADDR, "tx_pkt65to127"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXPKT128TO255_GB_ADDR, "tx_pkt128to255"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXPKT256TO511_GB_ADDR, "tx_pkt256to511"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXPKT512TO1023_GB_ADDR, "tx_pkt512to1023"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXPKT1024TOMAX_GB_ADDR, "tx_pkt1024tomax"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXUNI_GB_ADDR, "tx_unicast"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXMULTI_GB_ADDR, "tx_multicast"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXBROAD_GB_ADDR, "tx_broadcast"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXUNDERFLOW_ERR_ADDR, "tx_underflow_err"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXBYTE_G_ADDR, "tx_bytes_g"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXPKT_G_ADDR, "tx_frames_g"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXPAUSE_ADDR, "tx_pause"), ++ PPE_MAC_MIB_DESC(8, XGMAC_TXVLAN_G_ADDR, "tx_vlan_g"), ++ PPE_MAC_MIB_DESC(4, XGMAC_TXLPI_USEC_ADDR, "tx_lpi_usec"), ++ PPE_MAC_MIB_DESC(4, XGMAC_TXLPI_TRAN_ADDR, "tx_lpi_tran"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXPKT_GB_ADDR, "rx_frames"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXBYTE_GB_ADDR, "rx_bytes"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXBYTE_G_ADDR, "rx_bytes_g"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXBROAD_G_ADDR, "rx_broadcast_g"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXMULTI_G_ADDR, "rx_multicast_g"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXCRC_ERR_ADDR, "rx_crc_err"), ++ PPE_MAC_MIB_DESC(4, XGMAC_RXRUNT_ERR_ADDR, "rx_runt_err"), ++ PPE_MAC_MIB_DESC(4, XGMAC_RXJABBER_ERR_ADDR, "rx_jabber_err"), ++ PPE_MAC_MIB_DESC(4, XGMAC_RXUNDERSIZE_G_ADDR, "rx_undersize_g"), ++ PPE_MAC_MIB_DESC(4, XGMAC_RXOVERSIZE_G_ADDR, "rx_oversize_g"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXPKT64_GB_ADDR, "rx_pkt64"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXPKT65TO127_GB_ADDR, "rx_pkt65to127"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXPKT128TO255_GB_ADDR, "rx_pkt128to255"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXPKT256TO511_GB_ADDR, "rx_pkt256to511"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXPKT512TO1023_GB_ADDR, "rx_pkt512to1023"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXPKT1024TOMAX_GB_ADDR, "rx_pkt1024tomax"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXUNI_G_ADDR, "rx_unicast_g"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXLEN_ERR_ADDR, "rx_len_err"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXOUTOFRANGE_ADDR, "rx_outofrange_err"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXPAUSE_ADDR, "rx_pause"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXFIFOOVERFLOW_ADDR, "rx_fifo_overflow"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXVLAN_GB_ADDR, "rx_vlan"), ++ PPE_MAC_MIB_DESC(4, XGMAC_RXWATCHDOG_ERR_ADDR, "rx_wdog_err"), ++ PPE_MAC_MIB_DESC(4, XGMAC_RXLPI_USEC_ADDR, "rx_lpi_usec"), ++ PPE_MAC_MIB_DESC(4, XGMAC_RXLPI_TRAN_ADDR, "rx_lpi_tran"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXDISCARD_GB_ADDR, "rx_drop_frames"), ++ PPE_MAC_MIB_DESC(8, XGMAC_RXDISCARDBYTE_GB_ADDR, "rx_drop_bytes"), ++}; ++ ++/* Get GMAC MIBs from registers and accumulate to PPE port GMIB stats array */ ++static void ppe_port_gmib_update(struct ppe_port *ppe_port) ++{ ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ const struct ppe_mac_mib_info *mib; ++ int port = ppe_port->port_id; ++ u32 reg, val; ++ int i, ret; ++ ++ for (i = 0; i < ARRAY_SIZE(gmib_info); i++) { ++ mib = &gmib_info[i]; ++ reg = PPE_PORT_GMAC_ADDR(port) + mib->offset; ++ ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) { ++ dev_warn(ppe_dev->dev, "%s: %d\n", __func__, ret); ++ continue; ++ } ++ ++ ppe_port->gmib_stats[i] += val; ++ if (mib->size == 8) { ++ ret = regmap_read(ppe_dev->regmap, reg + 4, &val); ++ if (ret) { ++ dev_warn(ppe_dev->dev, "%s: %d\n", ++ __func__, ret); ++ continue; ++ } ++ ++ ppe_port->gmib_stats[i] += (u64)val << 32; ++ } ++ } ++} ++ ++/* Polling task to read GMIB statistics to avoid GMIB 32bit register overflow */ ++static void ppe_port_gmib_stats_poll(struct work_struct *work) ++{ ++ struct ppe_port *ppe_port = container_of(work, struct ppe_port, ++ gmib_read.work); ++ spin_lock(&ppe_port->gmib_stats_lock); ++ ppe_port_gmib_update(ppe_port); ++ spin_unlock(&ppe_port->gmib_stats_lock); ++ ++ schedule_delayed_work(&ppe_port->gmib_read, ++ msecs_to_jiffies(PPE_GMIB_POLL_INTERVAL_MS)); ++} ++ ++/* Get the XGMAC MIB counter based on the specific MIB stats type */ ++static u64 ppe_port_xgmib_get(struct ppe_port *ppe_port, ++ enum ppe_xgmib_stats_type xgmib_type) ++{ ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ const struct ppe_mac_mib_info *mib; ++ int port = ppe_port->port_id; ++ u32 reg, val; ++ u64 data = 0; ++ int ret; ++ ++ mib = &xgmib_info[xgmib_type]; ++ reg = PPE_PORT_XGMAC_ADDR(port) + mib->offset; ++ ++ ret = regmap_read(ppe_dev->regmap, reg, &val); ++ if (ret) { ++ dev_warn(ppe_dev->dev, "%s: %d\n", __func__, ret); ++ goto data_return; ++ } ++ ++ data = val; ++ if (mib->size == 8) { ++ ret = regmap_read(ppe_dev->regmap, reg + 4, &val); ++ if (ret) { ++ dev_warn(ppe_dev->dev, "%s: %d\n", __func__, ret); ++ goto data_return; ++ } ++ ++ data |= (u64)val << 32; ++ } ++ ++data_return: ++ return data; ++} ++ ++/** ++ * ppe_port_get_sset_count() - Get PPE port statistics string count ++ * @ppe_port: PPE port ++ * @sset: string set ID ++ * ++ * Description: Get the MAC statistics string count for the PPE port ++ * specified by @ppe_port. ++ * ++ * Return: The count of the statistics string. ++ */ ++int ppe_port_get_sset_count(struct ppe_port *ppe_port, int sset) ++{ ++ if (sset != ETH_SS_STATS) ++ return 0; ++ ++ if (ppe_port->mac_type == PPE_MAC_TYPE_GMAC) ++ return ARRAY_SIZE(gmib_info); ++ else ++ return ARRAY_SIZE(xgmib_info); ++} ++ ++/** ++ * ppe_port_get_strings() - Get PPE port statistics strings ++ * @ppe_port: PPE port ++ * @stringset: string set ID ++ * @data: pointer to statistics strings ++ * ++ * Description: Get the MAC statistics stings for the PPE port ++ * specified by @ppe_port. The strings are stored in the buffer ++ * indicated by @data which used in the ethtool ops. ++ */ ++void ppe_port_get_strings(struct ppe_port *ppe_port, u32 stringset, u8 *data) ++{ ++ int i; ++ ++ if (stringset != ETH_SS_STATS) ++ return; ++ ++ if (ppe_port->mac_type == PPE_MAC_TYPE_GMAC) { ++ for (i = 0; i < ARRAY_SIZE(gmib_info); i++) ++ strscpy(data + i * ETH_GSTRING_LEN, gmib_info[i].name, ++ ETH_GSTRING_LEN); ++ } else { ++ for (i = 0; i < ARRAY_SIZE(xgmib_info); i++) ++ strscpy(data + i * ETH_GSTRING_LEN, xgmib_info[i].name, ++ ETH_GSTRING_LEN); ++ } ++} ++ ++/** ++ * ppe_port_get_ethtool_stats() - Get PPE port ethtool statistics ++ * @ppe_port: PPE port ++ * @data: pointer to statistics data ++ * ++ * Description: Get the MAC statistics for the PPE port specified ++ * by @ppe_port. The statistics are stored in the buffer indicated ++ * by @data which used in the ethtool ops. ++ */ ++void ppe_port_get_ethtool_stats(struct ppe_port *ppe_port, u64 *data) ++{ ++ int i; ++ ++ if (ppe_port->mac_type == PPE_MAC_TYPE_GMAC) { ++ spin_lock(&ppe_port->gmib_stats_lock); ++ ++ ppe_port_gmib_update(ppe_port); ++ for (i = 0; i < ARRAY_SIZE(gmib_info); i++) ++ data[i] = ppe_port->gmib_stats[i]; ++ ++ spin_unlock(&ppe_port->gmib_stats_lock); ++ } else { ++ for (i = 0; i < ARRAY_SIZE(xgmib_info); i++) ++ data[i] = ppe_port_xgmib_get(ppe_port, i); ++ } ++} ++ ++/** ++ * ppe_port_get_stats64() - Get PPE port statistics ++ * @ppe_port: PPE port ++ * @s: statistics pointer ++ * ++ * Description: Get the MAC statistics for the PPE port specified ++ * by @ppe_port. ++ */ ++void ppe_port_get_stats64(struct ppe_port *ppe_port, ++ struct rtnl_link_stats64 *s) ++{ ++ if (ppe_port->mac_type == PPE_MAC_TYPE_GMAC) { ++ u64 *src = ppe_port->gmib_stats; ++ ++ spin_lock(&ppe_port->gmib_stats_lock); ++ ++ ppe_port_gmib_update(ppe_port); ++ ++ s->rx_packets = src[gmib_rx_unicast] + ++ src[gmib_rx_broadcast] + src[gmib_rx_multicast]; ++ ++ s->tx_packets = src[gmib_tx_unicast] + ++ src[gmib_tx_broadcast] + src[gmib_tx_multicast]; ++ ++ s->rx_bytes = src[gmib_rx_bytes_g]; ++ s->tx_bytes = src[gmib_tx_bytes]; ++ s->multicast = src[gmib_rx_multicast]; ++ ++ s->rx_crc_errors = src[gmib_rx_fcserr] + src[gmib_rx_frag]; ++ s->rx_frame_errors = src[gmib_rx_alignerr]; ++ s->rx_errors = s->rx_crc_errors + s->rx_frame_errors; ++ s->rx_dropped = src[gmib_rx_toolong] + s->rx_errors; ++ ++ s->tx_fifo_errors = src[gmib_tx_underrun]; ++ s->tx_aborted_errors = src[gmib_tx_abortcol]; ++ s->tx_errors = s->tx_fifo_errors + s->tx_aborted_errors; ++ s->collisions = src[gmib_tx_collisions]; ++ ++ spin_unlock(&ppe_port->gmib_stats_lock); ++ } else { ++ s->multicast = ppe_port_xgmib_get(ppe_port, xgmib_rx_multicast_g); ++ ++ s->rx_packets = s->multicast; ++ s->rx_packets += ppe_port_xgmib_get(ppe_port, xgmib_rx_unicast_g); ++ s->rx_packets += ppe_port_xgmib_get(ppe_port, xgmib_rx_broadcast_g); ++ ++ s->tx_packets = ppe_port_xgmib_get(ppe_port, xgmib_tx_frames); ++ s->rx_bytes = ppe_port_xgmib_get(ppe_port, xgmib_rx_bytes); ++ s->tx_bytes = ppe_port_xgmib_get(ppe_port, xgmib_tx_bytes); ++ ++ s->rx_crc_errors = ppe_port_xgmib_get(ppe_port, xgmib_rx_crc_err); ++ s->rx_fifo_errors = ppe_port_xgmib_get(ppe_port, xgmib_rx_fifo_overflow); ++ ++ s->rx_length_errors = ppe_port_xgmib_get(ppe_port, xgmib_rx_len_err); ++ s->rx_errors = s->rx_crc_errors + ++ s->rx_fifo_errors + s->rx_length_errors; ++ s->rx_dropped = s->rx_errors; ++ ++ s->tx_fifo_errors = ppe_port_xgmib_get(ppe_port, xgmib_tx_underflow_err); ++ s->tx_errors = s->tx_packets - ++ ppe_port_xgmib_get(ppe_port, xgmib_tx_frames_g); ++ } ++} ++ + /* PPE port and MAC reset */ + static int ppe_port_mac_reset(struct ppe_port *ppe_port) + { +@@ -261,6 +693,9 @@ static void ppe_port_mac_link_up(struct + int ret, port = ppe_port->port_id; + u32 reg, val; + ++ /* Start GMIB statistics polling */ ++ schedule_delayed_work(&ppe_port->gmib_read, 0); ++ + if (mac_type == PPE_MAC_TYPE_GMAC) + ret = ppe_port_gmac_link_up(ppe_port, + speed, duplex, tx_pause, rx_pause); +@@ -306,6 +741,9 @@ static void ppe_port_mac_link_down(struc + int ret, port = ppe_port->port_id; + u32 reg; + ++ /* Stop GMIB statistics polling */ ++ cancel_delayed_work_sync(&ppe_port->gmib_read); ++ + /* Disable PPE port TX */ + reg = PPE_PORT_BRIDGE_CTRL_ADDR + PPE_PORT_BRIDGE_CTRL_INC * port; + ret = regmap_update_bits(ppe_dev->regmap, reg, +@@ -627,6 +1065,27 @@ static int ppe_port_mac_hw_init(struct p + return ret; + } + ++/* PPE port MAC MIB work task initialization */ ++static int ppe_port_mac_mib_work_init(struct ppe_port *ppe_port) ++{ ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ u64 *gstats; ++ ++ gstats = devm_kzalloc(ppe_dev->dev, ++ sizeof(*gstats) * ARRAY_SIZE(gmib_info), ++ GFP_KERNEL); ++ if (!gstats) ++ return -ENOMEM; ++ ++ ppe_port->gmib_stats = gstats; ++ ++ spin_lock_init(&ppe_port->gmib_stats_lock); ++ INIT_DELAYED_WORK(&ppe_port->gmib_read, ++ ppe_port_gmib_stats_poll); ++ ++ return 0; ++} ++ + /** + * ppe_port_mac_init() - Initialization of PPE ports for the PPE device + * @ppe_dev: PPE device +@@ -693,6 +1152,12 @@ int ppe_port_mac_init(struct ppe_device + goto err_port_node; + } + ++ ret = ppe_port_mac_mib_work_init(&ppe_ports->port[i]); ++ if (ret) { ++ dev_err(ppe_dev->dev, "Failed to initialize MAC MIB work\n"); ++ goto err_port_node; ++ } ++ + i++; + } + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.h +@@ -8,6 +8,8 @@ + + #include + ++struct rtnl_link_stats64; ++ + /** + * enum ppe_port_clk_rst_type - PPE port clock and reset ID type + * @PPE_PORT_CLK_RST_MAC: The clock and reset ID for port MAC +@@ -44,6 +46,9 @@ enum ppe_mac_type { + * @port_id: Port ID + * @clks: Port clocks + * @rstcs: Port resets ++ * @gmib_read: Delay work task for GMAC MIB statistics polling function ++ * @gmib_stats: GMAC MIB statistics array ++ * @gmib_stats_lock: Lock to protect GMAC MIB statistics + */ + struct ppe_port { + struct phylink *phylink; +@@ -56,6 +61,9 @@ struct ppe_port { + int port_id; + struct clk *clks[PPE_PORT_CLK_RST_MAX]; + struct reset_control *rstcs[PPE_PORT_CLK_RST_MAX]; ++ struct delayed_work gmib_read; ++ u64 *gmib_stats; ++ spinlock_t gmib_stats_lock; /* Protects GMIB stats */ + }; + + /** +@@ -73,4 +81,9 @@ void ppe_port_mac_deinit(struct ppe_devi + int ppe_port_phylink_setup(struct ppe_port *ppe_port, + struct net_device *netdev); + void ppe_port_phylink_destroy(struct ppe_port *ppe_port); ++int ppe_port_get_sset_count(struct ppe_port *ppe_port, int sset); ++void ppe_port_get_strings(struct ppe_port *ppe_port, u32 stringset, u8 *data); ++void ppe_port_get_ethtool_stats(struct ppe_port *ppe_port, u64 *data); ++void ppe_port_get_stats64(struct ppe_port *ppe_port, ++ struct rtnl_link_stats64 *s); + #endif +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -618,6 +618,48 @@ + #define GMAC_MIB_CTRL_MASK \ + (GMAC_MIB_RD_CLR | GMAC_MIB_RST | GMAC_MIB_EN) + ++/* GMAC MIB counter registers */ ++#define GMAC_RXBROAD_ADDR 0x40 ++#define GMAC_RXPAUSE_ADDR 0x44 ++#define GMAC_RXMULTI_ADDR 0x48 ++#define GMAC_RXFCSERR_ADDR 0x4C ++#define GMAC_RXALIGNERR_ADDR 0x50 ++#define GMAC_RXRUNT_ADDR 0x54 ++#define GMAC_RXFRAG_ADDR 0x58 ++#define GMAC_RXJUMBOFCSERR_ADDR 0x5C ++#define GMAC_RXJUMBOALIGNERR_ADDR 0x60 ++#define GMAC_RXPKT64_ADDR 0x64 ++#define GMAC_RXPKT65TO127_ADDR 0x68 ++#define GMAC_RXPKT128TO255_ADDR 0x6C ++#define GMAC_RXPKT256TO511_ADDR 0x70 ++#define GMAC_RXPKT512TO1023_ADDR 0x74 ++#define GMAC_RXPKT1024TO1518_ADDR 0x78 ++#define GMAC_RXPKT1519TOX_ADDR 0x7C ++#define GMAC_RXTOOLONG_ADDR 0x80 ++#define GMAC_RXBYTE_G_ADDR 0x84 ++#define GMAC_RXBYTE_B_ADDR 0x8C ++#define GMAC_RXUNI_ADDR 0x94 ++#define GMAC_TXBROAD_ADDR 0xA0 ++#define GMAC_TXPAUSE_ADDR 0xA4 ++#define GMAC_TXMULTI_ADDR 0xA8 ++#define GMAC_TXUNDERRUN_ADDR 0xAC ++#define GMAC_TXPKT64_ADDR 0xB0 ++#define GMAC_TXPKT65TO127_ADDR 0xB4 ++#define GMAC_TXPKT128TO255_ADDR 0xB8 ++#define GMAC_TXPKT256TO511_ADDR 0xBC ++#define GMAC_TXPKT512TO1023_ADDR 0xC0 ++#define GMAC_TXPKT1024TO1518_ADDR 0xC4 ++#define GMAC_TXPKT1519TOX_ADDR 0xC8 ++#define GMAC_TXBYTE_ADDR 0xCC ++#define GMAC_TXCOLLISIONS_ADDR 0xD4 ++#define GMAC_TXABORTCOL_ADDR 0xD8 ++#define GMAC_TXMULTICOL_ADDR 0xDC ++#define GMAC_TXSINGLECOL_ADDR 0xE0 ++#define GMAC_TXEXCESSIVEDEFER_ADDR 0xE4 ++#define GMAC_TXDEFER_ADDR 0xE8 ++#define GMAC_TXLATECOL_ADDR 0xEC ++#define GMAC_TXUNI_ADDR 0xF0 ++ + /* XGMAC TX configuration register */ + #define XGMAC_TX_CONFIG_ADDR 0x0 + #define XGMAC_SPEED_M GENMASK(31, 29) +@@ -680,4 +722,53 @@ + #define XGMAC_MCF BIT(3) + #define XGMAC_CNTRST BIT(0) + ++/* XGMAC MIB counter registers */ ++#define XGMAC_TXBYTE_GB_ADDR 0x814 ++#define XGMAC_TXPKT_GB_ADDR 0x81C ++#define XGMAC_TXBROAD_G_ADDR 0x824 ++#define XGMAC_TXMULTI_G_ADDR 0x82C ++#define XGMAC_TXPKT64_GB_ADDR 0x834 ++#define XGMAC_TXPKT65TO127_GB_ADDR 0x83C ++#define XGMAC_TXPKT128TO255_GB_ADDR 0x844 ++#define XGMAC_TXPKT256TO511_GB_ADDR 0x84C ++#define XGMAC_TXPKT512TO1023_GB_ADDR 0x854 ++#define XGMAC_TXPKT1024TOMAX_GB_ADDR 0x85C ++#define XGMAC_TXUNI_GB_ADDR 0x864 ++#define XGMAC_TXMULTI_GB_ADDR 0x86C ++#define XGMAC_TXBROAD_GB_ADDR 0x874 ++#define XGMAC_TXUNDERFLOW_ERR_ADDR 0x87C ++#define XGMAC_TXBYTE_G_ADDR 0x884 ++#define XGMAC_TXPKT_G_ADDR 0x88C ++#define XGMAC_TXPAUSE_ADDR 0x894 ++#define XGMAC_TXVLAN_G_ADDR 0x89C ++#define XGMAC_TXLPI_USEC_ADDR 0x8A4 ++#define XGMAC_TXLPI_TRAN_ADDR 0x8A8 ++#define XGMAC_RXPKT_GB_ADDR 0x900 ++#define XGMAC_RXBYTE_GB_ADDR 0x908 ++#define XGMAC_RXBYTE_G_ADDR 0x910 ++#define XGMAC_RXBROAD_G_ADDR 0x918 ++#define XGMAC_RXMULTI_G_ADDR 0x920 ++#define XGMAC_RXCRC_ERR_ADDR 0x928 ++#define XGMAC_RXRUNT_ERR_ADDR 0x930 ++#define XGMAC_RXJABBER_ERR_ADDR 0x934 ++#define XGMAC_RXUNDERSIZE_G_ADDR 0x938 ++#define XGMAC_RXOVERSIZE_G_ADDR 0x93C ++#define XGMAC_RXPKT64_GB_ADDR 0x940 ++#define XGMAC_RXPKT65TO127_GB_ADDR 0x948 ++#define XGMAC_RXPKT128TO255_GB_ADDR 0x950 ++#define XGMAC_RXPKT256TO511_GB_ADDR 0x958 ++#define XGMAC_RXPKT512TO1023_GB_ADDR 0x960 ++#define XGMAC_RXPKT1024TOMAX_GB_ADDR 0x968 ++#define XGMAC_RXUNI_G_ADDR 0x970 ++#define XGMAC_RXLEN_ERR_ADDR 0x978 ++#define XGMAC_RXOUTOFRANGE_ADDR 0x980 ++#define XGMAC_RXPAUSE_ADDR 0x988 ++#define XGMAC_RXFIFOOVERFLOW_ADDR 0x990 ++#define XGMAC_RXVLAN_GB_ADDR 0x998 ++#define XGMAC_RXWATCHDOG_ERR_ADDR 0x9A0 ++#define XGMAC_RXLPI_USEC_ADDR 0x9A4 ++#define XGMAC_RXLPI_TRAN_ADDR 0x9A8 ++#define XGMAC_RXDISCARD_GB_ADDR 0x9AC ++#define XGMAC_RXDISCARDBYTE_GB_ADDR 0x9B4 ++ + #endif diff --git a/target/linux/qualcommbe/patches-6.12/0340-net-ethernet-qualcomm-Add-PPE-port-MAC-address-and-E.patch b/target/linux/qualcommbe/patches-6.12/0340-net-ethernet-qualcomm-Add-PPE-port-MAC-address-and-E.patch new file mode 100644 index 0000000000..856a1ed4cc --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0340-net-ethernet-qualcomm-Add-PPE-port-MAC-address-and-E.patch @@ -0,0 +1,172 @@ +From 55fbbc8ef90df27a16bca1613a793a578b79a384 Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Fri, 1 Mar 2024 13:36:26 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Add PPE port MAC address and EEE + functions + +Add PPE port MAC address set and EEE set API functions which +will be used by netdev ops and ethtool. + +Change-Id: Id2b3b06ae940b3b6f5227d927316329cdf3caeaa +Signed-off-by: Lei Wei +Alex G: use struct ethtool_keee instead of ethtool_eee +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/ethernet/qualcomm/ppe/ppe_port.c | 75 ++++++++++++++++++++ + drivers/net/ethernet/qualcomm/ppe/ppe_port.h | 3 + + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 29 ++++++++ + 3 files changed, 107 insertions(+) + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.c +@@ -462,6 +462,81 @@ void ppe_port_get_stats64(struct ppe_por + } + } + ++/** ++ * ppe_port_set_mac_address() - Set PPE port MAC address ++ * @ppe_port: PPE port ++ * @addr: MAC address ++ * ++ * Description: Set MAC address for the given PPE port. ++ * ++ * Return: 0 upon success or a negative error upon failure. ++ */ ++int ppe_port_set_mac_address(struct ppe_port *ppe_port, const u8 *addr) ++{ ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ int port = ppe_port->port_id; ++ u32 reg, val; ++ int ret; ++ ++ if (ppe_port->mac_type == PPE_MAC_TYPE_GMAC) { ++ reg = PPE_PORT_GMAC_ADDR(port); ++ val = (addr[5] << 8) | addr[4]; ++ ret = regmap_write(ppe_dev->regmap, reg + GMAC_GOL_ADDR0_ADDR, val); ++ if (ret) ++ return ret; ++ ++ val = (addr[0] << 24) | (addr[1] << 16) | ++ (addr[2] << 8) | addr[3]; ++ ret = regmap_write(ppe_dev->regmap, reg + GMAC_GOL_ADDR1_ADDR, val); ++ if (ret) ++ return ret; ++ } else { ++ reg = PPE_PORT_XGMAC_ADDR(port); ++ val = (addr[5] << 8) | addr[4] | XGMAC_ADDR_EN; ++ ret = regmap_write(ppe_dev->regmap, reg + XGMAC_ADDR0_H_ADDR, val); ++ if (ret) ++ return ret; ++ ++ val = (addr[3] << 24) | (addr[2] << 16) | ++ (addr[1] << 8) | addr[0]; ++ ret = regmap_write(ppe_dev->regmap, reg + XGMAC_ADDR0_L_ADDR, val); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++/** ++ * ppe_port_set_mac_eee() - Set EEE configuration for PPE port MAC ++ * @ppe_port: PPE port ++ * @eee: EEE settings ++ * ++ * Description: Set port MAC EEE settings for the given PPE port. ++ * ++ * Return: 0 upon success or a negative error upon failure. ++ */ ++int ppe_port_set_mac_eee(struct ppe_port *ppe_port, struct ethtool_keee *eee) ++{ ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ int port = ppe_port->port_id; ++ u32 val; ++ int ret; ++ ++ ret = regmap_read(ppe_dev->regmap, PPE_LPI_EN_ADDR, &val); ++ if (ret) ++ return ret; ++ ++ if (eee->tx_lpi_enabled) ++ val |= PPE_LPI_PORT_EN(port); ++ else ++ val &= ~PPE_LPI_PORT_EN(port); ++ ++ ret = regmap_write(ppe_dev->regmap, PPE_LPI_EN_ADDR, val); ++ ++ return ret; ++} ++ + /* PPE port and MAC reset */ + static int ppe_port_mac_reset(struct ppe_port *ppe_port) + { +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.h +@@ -8,6 +8,7 @@ + + #include + ++struct ethtool_keee; + struct rtnl_link_stats64; + + /** +@@ -86,4 +87,6 @@ void ppe_port_get_strings(struct ppe_por + void ppe_port_get_ethtool_stats(struct ppe_port *ppe_port, u64 *data); + void ppe_port_get_stats64(struct ppe_port *ppe_port, + struct rtnl_link_stats64 *s); ++int ppe_port_set_mac_address(struct ppe_port *ppe_port, const u8 *addr); ++int ppe_port_set_mac_eee(struct ppe_port *ppe_port, struct ethtool_keee *eee); + #endif +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -20,6 +20,16 @@ + #define PPE_PORT5_SEL_PCS1 BIT(4) + #define PPE_PORT_SEL_XGMAC(x) (BIT(8) << ((x) - 1)) + ++/* PPE port LPI enable register */ ++#define PPE_LPI_EN_ADDR 0x400 ++#define PPE_LPI_PORT1_EN BIT(0) ++#define PPE_LPI_PORT2_EN BIT(1) ++#define PPE_LPI_PORT3_EN BIT(2) ++#define PPE_LPI_PORT4_EN BIT(3) ++#define PPE_LPI_PORT5_EN BIT(4) ++#define PPE_LPI_PORT6_EN BIT(5) ++#define PPE_LPI_PORT_EN(x) (BIT(0) << ((x) - 1)) ++ + /* PPE scheduler configurations for buffer manager block. */ + #define PPE_BM_SCH_CTRL_ADDR 0xb000 + #define PPE_BM_SCH_CTRL_INC 4 +@@ -592,6 +602,17 @@ + #define GMAC_SPEED_100 1 + #define GMAC_SPEED_1000 2 + ++/* GMAC MAC address register */ ++#define GMAC_GOL_ADDR0_ADDR 0x8 ++#define GMAC_ADDR_BYTE5 GENMASK(15, 8) ++#define GMAC_ADDR_BYTE4 GENMASK(7, 0) ++ ++#define GMAC_GOL_ADDR1_ADDR 0xC ++#define GMAC_ADDR_BYTE0 GENMASK(31, 24) ++#define GMAC_ADDR_BYTE1 GENMASK(23, 16) ++#define GMAC_ADDR_BYTE2 GENMASK(15, 8) ++#define GMAC_ADDR_BYTE3 GENMASK(7, 0) ++ + /* GMAC control register */ + #define GMAC_CTRL_ADDR 0x18 + #define GMAC_TX_THD_M GENMASK(27, 24) +@@ -717,6 +738,14 @@ + #define XGMAC_RX_FLOW_CTRL_ADDR 0x90 + #define XGMAC_RXFCEN BIT(0) + ++/* XGMAC MAC address register */ ++#define XGMAC_ADDR0_H_ADDR 0x300 ++#define XGMAC_ADDR_EN BIT(31) ++#define XGMAC_ADDRH GENMASK(15, 0) ++ ++#define XGMAC_ADDR0_L_ADDR 0x304 ++#define XGMAC_ADDRL GENMASK(31, 0) ++ + /* XGMAC management counters control register */ + #define XGMAC_MMC_CTRL_ADDR 0x800 + #define XGMAC_MCF BIT(3) diff --git a/target/linux/qualcommbe/patches-6.12/0341-net-ethernet-qualcomm-Add-API-to-configure-PPE-port-.patch b/target/linux/qualcommbe/patches-6.12/0341-net-ethernet-qualcomm-Add-API-to-configure-PPE-port-.patch new file mode 100644 index 0000000000..ae81ddb19d --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0341-net-ethernet-qualcomm-Add-API-to-configure-PPE-port-.patch @@ -0,0 +1,78 @@ +From 3981aeae5dd43dea94a0ec10f0b2977ebd102560 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Tue, 5 Mar 2024 16:42:56 +0800 +Subject: [PATCH] net: ethernet: qualcomm: Add API to configure PPE port max + frame size + +This function is called when the MTU of an ethernet port is +configured. It limits the size of packet passed through the +ethernet port. + +Change-Id: I2a4dcd04407156d73770d2becbb7cbc0d56b3754 +Signed-off-by: Luo Jie +--- + drivers/net/ethernet/qualcomm/ppe/ppe_port.c | 44 ++++++++++++++++++++ + drivers/net/ethernet/qualcomm/ppe/ppe_port.h | 1 + + 2 files changed, 45 insertions(+) + +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.c +@@ -537,6 +537,50 @@ int ppe_port_set_mac_eee(struct ppe_port + return ret; + } + ++/** ++ * ppe_port_set_maxframe() - Set port maximum frame size ++ * @ppe_port: PPE port structure ++ * @maxframe_size: Maximum frame size supported by PPE port ++ * ++ * Description: Set MTU of network interface specified by @ppe_port. ++ * ++ * Return: 0 upon success or a negative error upon failure. ++ */ ++int ppe_port_set_maxframe(struct ppe_port *ppe_port, int maxframe_size) ++{ ++ struct ppe_device *ppe_dev = ppe_port->ppe_dev; ++ u32 reg, val, mru_mtu_val[3]; ++ int port = ppe_port->port_id; ++ int ret; ++ ++ /* The max frame size should be MTU added by ETH_HLEN in PPE. */ ++ maxframe_size += ETH_HLEN; ++ ++ /* MAC takes cover the FCS for the calculation of frame size. */ ++ if (maxframe_size > PPE_PORT_MAC_MAX_FRAME_SIZE - ETH_FCS_LEN) ++ return -EINVAL; ++ ++ reg = PPE_MC_MTU_CTRL_TBL_ADDR + PPE_MC_MTU_CTRL_TBL_INC * port; ++ val = FIELD_PREP(PPE_MC_MTU_CTRL_TBL_MTU, maxframe_size); ++ ret = regmap_update_bits(ppe_dev->regmap, reg, ++ PPE_MC_MTU_CTRL_TBL_MTU, ++ val); ++ if (ret) ++ return ret; ++ ++ reg = PPE_MRU_MTU_CTRL_TBL_ADDR + PPE_MRU_MTU_CTRL_TBL_INC * port; ++ ret = regmap_bulk_read(ppe_dev->regmap, reg, ++ mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); ++ if (ret) ++ return ret; ++ ++ PPE_MRU_MTU_CTRL_SET_MRU(mru_mtu_val, maxframe_size); ++ PPE_MRU_MTU_CTRL_SET_MTU(mru_mtu_val, maxframe_size); ++ ++ return regmap_bulk_write(ppe_dev->regmap, reg, ++ mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); ++} ++ + /* PPE port and MAC reset */ + static int ppe_port_mac_reset(struct ppe_port *ppe_port) + { +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.h +@@ -89,4 +89,5 @@ void ppe_port_get_stats64(struct ppe_por + struct rtnl_link_stats64 *s); + int ppe_port_set_mac_address(struct ppe_port *ppe_port, const u8 *addr); + int ppe_port_set_mac_eee(struct ppe_port *ppe_port, struct ethtool_keee *eee); ++int ppe_port_set_maxframe(struct ppe_port *ppe_port, int maxframe_size); + #endif diff --git a/target/linux/qualcommbe/patches-6.12/0342-net-ethernet-qualcomm-Add-EDMA-support-for-QCOM-IPQ9.patch b/target/linux/qualcommbe/patches-6.12/0342-net-ethernet-qualcomm-Add-EDMA-support-for-QCOM-IPQ9.patch new file mode 100644 index 0000000000..0160efdacb --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0342-net-ethernet-qualcomm-Add-EDMA-support-for-QCOM-IPQ9.patch @@ -0,0 +1,932 @@ +From 00d4f3cb4f5d1e6924151a4551f06b6a82bf0146 Mon Sep 17 00:00:00 2001 +From: Pavithra R +Date: Wed, 28 Feb 2024 11:25:15 +0530 +Subject: [PATCH] net: ethernet: qualcomm: Add EDMA support for QCOM IPQ9574 + chipset. + +Add the infrastructure functions such as Makefile, +EDMA hardware configuration, clock and IRQ initializations. + +Change-Id: I64f65e554e70e9095b0cf3636fec421569ae6895 +Signed-off-by: Pavithra R +Co-developed-by: Suruchi Agarwal +Signed-off-by: Suruchi Agarwal +Alex G: use "ppe_config.h" header instead of "ppe_api.h" + add missing definitions and functions from ppe_api: + - enum ppe_queue_class_type {} + - ppe_edma_queue_offset_config() +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/ethernet/qualcomm/ppe/Makefile | 3 + + drivers/net/ethernet/qualcomm/ppe/edma.c | 480 +++++++++++++++++++ + drivers/net/ethernet/qualcomm/ppe/edma.h | 113 +++++ + drivers/net/ethernet/qualcomm/ppe/ppe.c | 10 +- + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 253 ++++++++++ + 5 files changed, 858 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma.c + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma.h + +--- a/drivers/net/ethernet/qualcomm/ppe/Makefile ++++ b/drivers/net/ethernet/qualcomm/ppe/Makefile +@@ -5,3 +5,6 @@ + + obj-$(CONFIG_QCOM_PPE) += qcom-ppe.o + qcom-ppe-objs := ppe.o ppe_config.o ppe_debugfs.o ppe_port.o ++ ++#EDMA ++qcom-ppe-objs += edma.o +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.c +@@ -0,0 +1,480 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ /* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++ /* Qualcomm Ethernet DMA driver setup, HW configuration, clocks and ++ * interrupt initializations. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "edma.h" ++#include "ppe_regs.h" ++ ++#define EDMA_IRQ_NAME_SIZE 32 ++ ++/* Global EDMA context. */ ++struct edma_context *edma_ctx; ++ ++/* Priority to multi-queue mapping. */ ++static u8 edma_pri_map[PPE_QUEUE_INTER_PRI_NUM] = { ++ 0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7}; ++ ++enum edma_clk_id { ++ EDMA_CLK, ++ EDMA_CFG_CLK, ++ EDMA_CLK_MAX ++}; ++ ++static const char * const clock_name[EDMA_CLK_MAX] = { ++ [EDMA_CLK] = "edma", ++ [EDMA_CFG_CLK] = "edma-cfg", ++}; ++ ++/* Rx Fill ring info for IPQ9574. */ ++static struct edma_ring_info ipq9574_rxfill_ring_info = { ++ .max_rings = 8, ++ .ring_start = 4, ++ .num_rings = 4, ++}; ++ ++/* Rx ring info for IPQ9574. */ ++static struct edma_ring_info ipq9574_rx_ring_info = { ++ .max_rings = 24, ++ .ring_start = 20, ++ .num_rings = 4, ++}; ++ ++/* Tx ring info for IPQ9574. */ ++static struct edma_ring_info ipq9574_tx_ring_info = { ++ .max_rings = 32, ++ .ring_start = 8, ++ .num_rings = 24, ++}; ++ ++/* Tx complete ring info for IPQ9574. */ ++static struct edma_ring_info ipq9574_txcmpl_ring_info = { ++ .max_rings = 32, ++ .ring_start = 8, ++ .num_rings = 24, ++}; ++ ++/* HW info for IPQ9574. */ ++static struct edma_hw_info ipq9574_hw_info = { ++ .rxfill = &ipq9574_rxfill_ring_info, ++ .rx = &ipq9574_rx_ring_info, ++ .tx = &ipq9574_tx_ring_info, ++ .txcmpl = &ipq9574_txcmpl_ring_info, ++ .max_ports = 6, ++ .napi_budget_rx = 128, ++ .napi_budget_tx = 512, ++}; ++ ++static int edma_clock_set_and_enable(struct device *dev, ++ const char *id, unsigned long rate) ++{ ++ struct device_node *edma_np; ++ struct clk *clk = NULL; ++ int ret; ++ ++ edma_np = of_get_child_by_name(dev->of_node, "edma"); ++ ++ clk = devm_get_clk_from_child(dev, edma_np, id); ++ if (IS_ERR(clk)) { ++ dev_err(dev, "clk %s get failed\n", id); ++ of_node_put(edma_np); ++ return PTR_ERR(clk); ++ } ++ ++ ret = clk_set_rate(clk, rate); ++ if (ret) { ++ dev_err(dev, "set %lu rate for %s failed\n", rate, id); ++ of_node_put(edma_np); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(clk); ++ if (ret) { ++ dev_err(dev, "clk %s enable failed\n", id); ++ of_node_put(edma_np); ++ return ret; ++ } ++ ++ of_node_put(edma_np); ++ ++ dev_dbg(dev, "set %lu rate for %s\n", rate, id); ++ ++ return 0; ++} ++ ++static int edma_clock_init(void) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct device *dev = ppe_dev->dev; ++ unsigned long ppe_rate; ++ int ret; ++ ++ ppe_rate = ppe_dev->clk_rate; ++ ++ ret = edma_clock_set_and_enable(dev, clock_name[EDMA_CLK], ++ ppe_rate); ++ if (ret) ++ return ret; ++ ++ ret = edma_clock_set_and_enable(dev, clock_name[EDMA_CFG_CLK], ++ ppe_rate); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++/** ++ * edma_configure_ucast_prio_map_tbl - Configure unicast priority map table. ++ * ++ * Map int_priority values to priority class and initialize ++ * unicast priority map table for default profile_id. ++ */ ++static int edma_configure_ucast_prio_map_tbl(void) ++{ ++ u8 pri_class, int_pri; ++ int ret = 0; ++ ++ /* Set the priority class value for every possible priority. */ ++ for (int_pri = 0; int_pri < PPE_QUEUE_INTER_PRI_NUM; int_pri++) { ++ pri_class = edma_pri_map[int_pri]; ++ ++ /* Priority offset should be less than maximum supported ++ * queue priority. ++ */ ++ if (pri_class > EDMA_PRI_MAX_PER_CORE - 1) { ++ pr_err("Configured incorrect priority offset: %d\n", ++ pri_class); ++ return -EINVAL; ++ } ++ ++ ret = ppe_edma_queue_offset_config(edma_ctx->ppe_dev, ++ PPE_QUEUE_CLASS_PRIORITY, int_pri, pri_class); ++ ++ if (ret) { ++ pr_err("Failed with error: %d to set queue priority class for int_pri: %d for profile_id: %d\n", ++ ret, int_pri, 0); ++ return ret; ++ } ++ ++ pr_debug("profile_id: %d, int_priority: %d, pri_class: %d\n", ++ 0, int_pri, pri_class); ++ } ++ ++ return ret; ++} ++ ++static int edma_irq_init(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *txcmpl = hw_info->txcmpl; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct edma_ring_info *rx = hw_info->rx; ++ char edma_irq_name[EDMA_IRQ_NAME_SIZE]; ++ struct device *dev = ppe_dev->dev; ++ struct platform_device *pdev; ++ struct device_node *edma_np; ++ u32 i; ++ ++ pdev = to_platform_device(dev); ++ edma_np = of_get_child_by_name(dev->of_node, "edma"); ++ edma_ctx->intr_info.intr_txcmpl = kzalloc((sizeof(*edma_ctx->intr_info.intr_txcmpl) * ++ txcmpl->num_rings), GFP_KERNEL); ++ if (!edma_ctx->intr_info.intr_txcmpl) { ++ of_node_put(edma_np); ++ return -ENOMEM; ++ } ++ ++ /* Get TXCMPL rings IRQ numbers. */ ++ for (i = 0; i < txcmpl->num_rings; i++) { ++ snprintf(edma_irq_name, sizeof(edma_irq_name), "edma_txcmpl_%d", ++ txcmpl->ring_start + i); ++ edma_ctx->intr_info.intr_txcmpl[i] = of_irq_get_byname(edma_np, edma_irq_name); ++ if (edma_ctx->intr_info.intr_txcmpl[i] < 0) { ++ dev_err(dev, "%s: txcmpl_info.intr[%u] irq get failed\n", ++ edma_np->name, i); ++ of_node_put(edma_np); ++ kfree(edma_ctx->intr_info.intr_txcmpl); ++ return edma_ctx->intr_info.intr_txcmpl[i]; ++ } ++ ++ dev_dbg(dev, "%s: intr_info.intr_txcmpl[%u] = %u\n", ++ edma_np->name, i, edma_ctx->intr_info.intr_txcmpl[i]); ++ } ++ ++ edma_ctx->intr_info.intr_rx = kzalloc((sizeof(*edma_ctx->intr_info.intr_rx) * ++ rx->num_rings), GFP_KERNEL); ++ if (!edma_ctx->intr_info.intr_rx) { ++ of_node_put(edma_np); ++ kfree(edma_ctx->intr_info.intr_txcmpl); ++ return -ENOMEM; ++ } ++ ++ /* Get RXDESC rings IRQ numbers. */ ++ for (i = 0; i < rx->num_rings; i++) { ++ snprintf(edma_irq_name, sizeof(edma_irq_name), "edma_rxdesc_%d", ++ rx->ring_start + i); ++ edma_ctx->intr_info.intr_rx[i] = of_irq_get_byname(edma_np, edma_irq_name); ++ if (edma_ctx->intr_info.intr_rx[i] < 0) { ++ dev_err(dev, "%s: rx_queue_map_info.intr[%u] irq get failed\n", ++ edma_np->name, i); ++ of_node_put(edma_np); ++ kfree(edma_ctx->intr_info.intr_rx); ++ kfree(edma_ctx->intr_info.intr_txcmpl); ++ return edma_ctx->intr_info.intr_rx[i]; ++ } ++ ++ dev_dbg(dev, "%s: intr_info.intr_rx[%u] = %u\n", ++ edma_np->name, i, edma_ctx->intr_info.intr_rx[i]); ++ } ++ ++ /* Get misc IRQ number. */ ++ edma_ctx->intr_info.intr_misc = of_irq_get_byname(edma_np, "edma_misc"); ++ if (edma_ctx->intr_info.intr_misc < 0) { ++ dev_err(dev, "%s: misc_intr irq get failed\n", edma_np->name); ++ of_node_put(edma_np); ++ kfree(edma_ctx->intr_info.intr_rx); ++ kfree(edma_ctx->intr_info.intr_txcmpl); ++ return edma_ctx->intr_info.intr_misc; ++ } ++ ++ of_node_put(edma_np); ++ ++ dev_dbg(dev, "%s: misc IRQ:%u\n", edma_np->name, ++ edma_ctx->intr_info.intr_misc); ++ ++ return 0; ++} ++ ++static int edma_hw_reset(void) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct device *dev = ppe_dev->dev; ++ struct reset_control *edma_hw_rst; ++ struct device_node *edma_np; ++ const char *reset_string; ++ u32 count, i; ++ int ret; ++ ++ /* Count and parse reset names from DTSI. */ ++ edma_np = of_get_child_by_name(dev->of_node, "edma"); ++ count = of_property_count_strings(edma_np, "reset-names"); ++ if (count < 0) { ++ dev_err(dev, "EDMA reset entry not found\n"); ++ of_node_put(edma_np); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < count; i++) { ++ ret = of_property_read_string_index(edma_np, "reset-names", ++ i, &reset_string); ++ if (ret) { ++ dev_err(dev, "Error reading reset-names"); ++ of_node_put(edma_np); ++ return -EINVAL; ++ } ++ ++ edma_hw_rst = of_reset_control_get_exclusive(edma_np, reset_string); ++ if (IS_ERR(edma_hw_rst)) { ++ of_node_put(edma_np); ++ return PTR_ERR(edma_hw_rst); ++ } ++ ++ /* 100ms delay is required by hardware to reset EDMA. */ ++ reset_control_assert(edma_hw_rst); ++ fsleep(100); ++ ++ reset_control_deassert(edma_hw_rst); ++ fsleep(100); ++ ++ reset_control_put(edma_hw_rst); ++ dev_dbg(dev, "EDMA HW reset, i:%d reset_string:%s\n", i, reset_string); ++ } ++ ++ of_node_put(edma_np); ++ ++ return 0; ++} ++ ++static int edma_hw_configure(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 data, reg; ++ int ret; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_MAS_CTRL_ADDR; ++ ret = regmap_read(regmap, reg, &data); ++ if (ret) ++ return ret; ++ ++ pr_debug("EDMA ver %d hw init\n", data); ++ ++ /* Setup private data structure. */ ++ edma_ctx->intr_info.intr_mask_rx = EDMA_RXDESC_INT_MASK_PKT_INT; ++ edma_ctx->intr_info.intr_mask_txcmpl = EDMA_TX_INT_MASK_PKT_INT; ++ ++ /* Reset EDMA. */ ++ ret = edma_hw_reset(); ++ if (ret) { ++ pr_err("Error in resetting the hardware. ret: %d\n", ret); ++ return ret; ++ } ++ ++ /* Allocate memory for netdevices. */ ++ edma_ctx->netdev_arr = kzalloc((sizeof(**edma_ctx->netdev_arr) * ++ hw_info->max_ports), ++ GFP_KERNEL); ++ if (!edma_ctx->netdev_arr) ++ return -ENOMEM; ++ ++ /* Configure DMA request priority, DMA read burst length, ++ * and AXI write size. ++ */ ++ data = FIELD_PREP(EDMA_DMAR_BURST_LEN_MASK, EDMA_BURST_LEN_ENABLE); ++ data |= FIELD_PREP(EDMA_DMAR_REQ_PRI_MASK, 0); ++ data |= FIELD_PREP(EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK, 31); ++ data |= FIELD_PREP(EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK, 7); ++ data |= FIELD_PREP(EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK, 7); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_DMAR_CTRL_ADDR; ++ ret = regmap_write(regmap, reg, data); ++ if (ret) ++ return ret; ++ ++ /* Configure Tx Timeout Threshold. */ ++ data = EDMA_TX_TIMEOUT_THRESH_VAL; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TX_TIMEOUT_THRESH_ADDR; ++ ret = regmap_write(regmap, reg, data); ++ if (ret) ++ return ret; ++ ++ /* Set Miscellaneous error mask. */ ++ data = EDMA_MISC_AXI_RD_ERR_MASK | ++ EDMA_MISC_AXI_WR_ERR_MASK | ++ EDMA_MISC_RX_DESC_FIFO_FULL_MASK | ++ EDMA_MISC_RX_ERR_BUF_SIZE_MASK | ++ EDMA_MISC_TX_SRAM_FULL_MASK | ++ EDMA_MISC_TX_CMPL_BUF_FULL_MASK | ++ EDMA_MISC_DATA_LEN_ERR_MASK; ++ data |= EDMA_MISC_TX_TIMEOUT_MASK; ++ edma_ctx->intr_info.intr_mask_misc = data; ++ ++ /* Global EDMA enable and padding enable. */ ++ data = EDMA_PORT_PAD_EN | EDMA_PORT_EDMA_EN; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_PORT_CTRL_ADDR; ++ ret = regmap_write(regmap, reg, data); ++ if (ret) ++ return ret; ++ ++ /* Initialize unicast priority map table. */ ++ ret = (int)edma_configure_ucast_prio_map_tbl(); ++ if (ret) { ++ pr_err("Failed to initialize unicast priority map table: %d\n", ++ ret); ++ kfree(edma_ctx->netdev_arr); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++/** ++ * edma_destroy - EDMA Destroy. ++ * @ppe_dev: PPE device ++ * ++ * Free the memory allocated during setup. ++ */ ++void edma_destroy(struct ppe_device *ppe_dev) ++{ ++ kfree(edma_ctx->intr_info.intr_rx); ++ kfree(edma_ctx->intr_info.intr_txcmpl); ++ kfree(edma_ctx->netdev_arr); ++} ++ ++/** ++ * edma_setup - EDMA Setup. ++ * @ppe_dev: PPE device ++ * ++ * Configure Ethernet global ctx, clocks, hardware and interrupts. ++ * ++ * Return 0 on success, negative error code on failure. ++ */ ++int edma_setup(struct ppe_device *ppe_dev) ++{ ++ struct device *dev = ppe_dev->dev; ++ int ret; ++ ++ edma_ctx = devm_kzalloc(dev, sizeof(*edma_ctx), GFP_KERNEL); ++ if (!edma_ctx) ++ return -ENOMEM; ++ ++ edma_ctx->hw_info = &ipq9574_hw_info; ++ edma_ctx->ppe_dev = ppe_dev; ++ ++ /* Configure the EDMA common clocks. */ ++ ret = edma_clock_init(); ++ if (ret) { ++ dev_err(dev, "Error in configuring the EDMA clocks\n"); ++ return ret; ++ } ++ ++ dev_dbg(dev, "QCOM EDMA common clocks are configured\n"); ++ ++ ret = edma_hw_configure(); ++ if (ret) { ++ dev_err(dev, "Error in edma configuration\n"); ++ return ret; ++ } ++ ++ ret = edma_irq_init(); ++ if (ret) { ++ dev_err(dev, "Error in irq initialization\n"); ++ return ret; ++ } ++ ++ dev_info(dev, "EDMA configuration successful\n"); ++ ++ return 0; ++} ++ ++/** ++ * ppe_edma_queue_offset_config - Configure queue offset for EDMA interface ++ * @ppe_dev: PPE device ++ * @class: The class to configure queue offset ++ * @index: Class index, internal priority or hash value ++ * @queue_offset: Queue offset value ++ * ++ * PPE EDMA queue offset is configured based on the PPE internal priority or ++ * RSS hash value, the profile ID is fixed to 0 for EDMA interface. ++ * ++ * Return 0 on success, negative error code on failure. ++ */ ++int ppe_edma_queue_offset_config(struct ppe_device *ppe_dev, ++ enum ppe_queue_class_type class, ++ int index, int queue_offset) ++{ ++ if (class == PPE_QUEUE_CLASS_PRIORITY) ++ return ppe_queue_ucast_offset_pri_set(ppe_dev, 0, ++ index, queue_offset); ++ ++ return ppe_queue_ucast_offset_hash_set(ppe_dev, 0, ++ index, queue_offset); ++} +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.h +@@ -0,0 +1,113 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#ifndef __EDMA_MAIN__ ++#define __EDMA_MAIN__ ++ ++#include "ppe_config.h" ++ ++/* One clock cycle = 1/(EDMA clock frequency in Mhz) micro seconds. ++ * ++ * One timer unit is 128 clock cycles. ++ * ++ * So, therefore the microsecond to timer unit calculation is: ++ * Timer unit = time in microseconds / (one clock cycle in microsecond * cycles in 1 timer unit) ++ * = ('x' microsecond * EDMA clock frequency in MHz ('y') / 128). ++ * ++ */ ++#define EDMA_CYCLE_PER_TIMER_UNIT 128 ++#define EDMA_MICROSEC_TO_TIMER_UNIT(x, y) ((x) * (y) / EDMA_CYCLE_PER_TIMER_UNIT) ++#define MHZ 1000000UL ++ ++/* EDMA profile ID. */ ++#define EDMA_CPU_PORT_PROFILE_ID 0 ++ ++/* Number of PPE queue priorities supported per ARM core. */ ++#define EDMA_PRI_MAX_PER_CORE 8 ++ ++/** ++ * enum ppe_queue_class_type - PPE queue class type ++ * @PPE_QUEUE_CLASS_PRIORITY: Queue offset configured from internal priority ++ * @PPE_QUEUE_CLASS_HASH: Queue offset configured from RSS hash. ++ */ ++enum ppe_queue_class_type { ++ PPE_QUEUE_CLASS_PRIORITY, ++ PPE_QUEUE_CLASS_HASH, ++}; ++ ++/** ++ * struct edma_ring_info - EDMA ring data structure. ++ * @max_rings: Maximum number of rings ++ * @ring_start: Ring start ID ++ * @num_rings: Number of rings ++ */ ++struct edma_ring_info { ++ u32 max_rings; ++ u32 ring_start; ++ u32 num_rings; ++}; ++ ++/** ++ * struct edma_hw_info - EDMA hardware data structure. ++ * @rxfill: Rx Fill ring information ++ * @rx: Rx Desc ring information ++ * @tx: Tx Desc ring information ++ * @txcmpl: Tx complete ring information ++ * @max_ports: Maximum number of ports ++ * @napi_budget_rx: Rx NAPI budget ++ * @napi_budget_tx: Tx NAPI budget ++ */ ++struct edma_hw_info { ++ struct edma_ring_info *rxfill; ++ struct edma_ring_info *rx; ++ struct edma_ring_info *tx; ++ struct edma_ring_info *txcmpl; ++ u32 max_ports; ++ u32 napi_budget_rx; ++ u32 napi_budget_tx; ++}; ++ ++/** ++ * struct edma_intr_info - EDMA interrupt data structure. ++ * @intr_mask_rx: RX interrupt mask ++ * @intr_rx: Rx interrupts ++ * @intr_mask_txcmpl: Tx completion interrupt mask ++ * @intr_txcmpl: Tx completion interrupts ++ * @intr_mask_misc: Miscellaneous interrupt mask ++ * @intr_misc: Miscellaneous interrupts ++ */ ++struct edma_intr_info { ++ u32 intr_mask_rx; ++ u32 *intr_rx; ++ u32 intr_mask_txcmpl; ++ u32 *intr_txcmpl; ++ u32 intr_mask_misc; ++ u32 intr_misc; ++}; ++ ++/** ++ * struct edma_context - EDMA context. ++ * @netdev_arr: Net device for each EDMA port ++ * @ppe_dev: PPE device ++ * @hw_info: EDMA Hardware info ++ * @intr_info: EDMA Interrupt info ++ */ ++struct edma_context { ++ struct net_device **netdev_arr; ++ struct ppe_device *ppe_dev; ++ struct edma_hw_info *hw_info; ++ struct edma_intr_info intr_info; ++}; ++ ++/* Global EDMA context. */ ++extern struct edma_context *edma_ctx; ++ ++void edma_destroy(struct ppe_device *ppe_dev); ++int edma_setup(struct ppe_device *ppe_dev); ++int ppe_edma_queue_offset_config(struct ppe_device *ppe_dev, ++ enum ppe_queue_class_type class, ++ int index, int queue_offset); ++ ++ ++#endif +--- a/drivers/net/ethernet/qualcomm/ppe/ppe.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe.c +@@ -14,6 +14,7 @@ + #include + #include + ++#include "edma.h" + #include "ppe.h" + #include "ppe_config.h" + #include "ppe_debugfs.h" +@@ -201,10 +202,16 @@ static int qcom_ppe_probe(struct platfor + if (ret) + return dev_err_probe(dev, ret, "PPE HW config failed\n"); + +- ret = ppe_port_mac_init(ppe_dev); ++ ret = edma_setup(ppe_dev); + if (ret) ++ return dev_err_probe(dev, ret, "EDMA setup failed\n"); ++ ++ ret = ppe_port_mac_init(ppe_dev); ++ if (ret) { ++ edma_destroy(ppe_dev); + return dev_err_probe(dev, ret, + "PPE Port MAC initialization failed\n"); ++ } + + ppe_debugfs_setup(ppe_dev); + platform_set_drvdata(pdev, ppe_dev); +@@ -219,6 +226,7 @@ static void qcom_ppe_remove(struct platf + ppe_dev = platform_get_drvdata(pdev); + ppe_debugfs_teardown(ppe_dev); + ppe_port_mac_deinit(ppe_dev); ++ edma_destroy(ppe_dev); + + platform_set_drvdata(pdev, NULL); + } +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +@@ -800,4 +800,257 @@ + #define XGMAC_RXDISCARD_GB_ADDR 0x9AC + #define XGMAC_RXDISCARDBYTE_GB_ADDR 0x9B4 + ++#define EDMA_BASE_OFFSET 0xb00000 ++ ++/* EDMA register offsets */ ++#define EDMA_REG_MAS_CTRL_ADDR 0x0 ++#define EDMA_REG_PORT_CTRL_ADDR 0x4 ++#define EDMA_REG_VLAN_CTRL_ADDR 0x8 ++#define EDMA_REG_RXDESC2FILL_MAP_0_ADDR 0x14 ++#define EDMA_REG_RXDESC2FILL_MAP_1_ADDR 0x18 ++#define EDMA_REG_RXDESC2FILL_MAP_2_ADDR 0x1c ++#define EDMA_REG_TXQ_CTRL_ADDR 0x20 ++#define EDMA_REG_TXQ_CTRL_2_ADDR 0x24 ++#define EDMA_REG_TXQ_FC_0_ADDR 0x28 ++#define EDMA_REG_TXQ_FC_1_ADDR 0x30 ++#define EDMA_REG_TXQ_FC_2_ADDR 0x34 ++#define EDMA_REG_TXQ_FC_3_ADDR 0x38 ++#define EDMA_REG_RXQ_CTRL_ADDR 0x3c ++#define EDMA_REG_MISC_ERR_QID_ADDR 0x40 ++#define EDMA_REG_RXQ_FC_THRE_ADDR 0x44 ++#define EDMA_REG_DMAR_CTRL_ADDR 0x48 ++#define EDMA_REG_AXIR_CTRL_ADDR 0x4c ++#define EDMA_REG_AXIW_CTRL_ADDR 0x50 ++#define EDMA_REG_MIN_MSS_ADDR 0x54 ++#define EDMA_REG_LOOPBACK_CTRL_ADDR 0x58 ++#define EDMA_REG_MISC_INT_STAT_ADDR 0x5c ++#define EDMA_REG_MISC_INT_MASK_ADDR 0x60 ++#define EDMA_REG_DBG_CTRL_ADDR 0x64 ++#define EDMA_REG_DBG_DATA_ADDR 0x68 ++#define EDMA_REG_TX_TIMEOUT_THRESH_ADDR 0x6c ++#define EDMA_REG_REQ0_FIFO_THRESH_ADDR 0x80 ++#define EDMA_REG_WB_OS_THRESH_ADDR 0x84 ++#define EDMA_REG_MISC_ERR_QID_REG2_ADDR 0x88 ++#define EDMA_REG_TXDESC2CMPL_MAP_0_ADDR 0x8c ++#define EDMA_REG_TXDESC2CMPL_MAP_1_ADDR 0x90 ++#define EDMA_REG_TXDESC2CMPL_MAP_2_ADDR 0x94 ++#define EDMA_REG_TXDESC2CMPL_MAP_3_ADDR 0x98 ++#define EDMA_REG_TXDESC2CMPL_MAP_4_ADDR 0x9c ++#define EDMA_REG_TXDESC2CMPL_MAP_5_ADDR 0xa0 ++ ++/* Tx descriptor ring configuration register addresses */ ++#define EDMA_REG_TXDESC_BA(n) (0x1000 + (0x1000 * (n))) ++#define EDMA_REG_TXDESC_PROD_IDX(n) (0x1004 + (0x1000 * (n))) ++#define EDMA_REG_TXDESC_CONS_IDX(n) (0x1008 + (0x1000 * (n))) ++#define EDMA_REG_TXDESC_RING_SIZE(n) (0x100c + (0x1000 * (n))) ++#define EDMA_REG_TXDESC_CTRL(n) (0x1010 + (0x1000 * (n))) ++#define EDMA_REG_TXDESC_BA2(n) (0x1014 + (0x1000 * (n))) ++ ++/* RxFill ring configuration register addresses */ ++#define EDMA_REG_RXFILL_BA(n) (0x29000 + (0x1000 * (n))) ++#define EDMA_REG_RXFILL_PROD_IDX(n) (0x29004 + (0x1000 * (n))) ++#define EDMA_REG_RXFILL_CONS_IDX(n) (0x29008 + (0x1000 * (n))) ++#define EDMA_REG_RXFILL_RING_SIZE(n) (0x2900c + (0x1000 * (n))) ++#define EDMA_REG_RXFILL_BUFFER1_SIZE(n) (0x29010 + (0x1000 * (n))) ++#define EDMA_REG_RXFILL_FC_THRE(n) (0x29014 + (0x1000 * (n))) ++#define EDMA_REG_RXFILL_UGT_THRE(n) (0x29018 + (0x1000 * (n))) ++#define EDMA_REG_RXFILL_RING_EN(n) (0x2901c + (0x1000 * (n))) ++#define EDMA_REG_RXFILL_DISABLE(n) (0x29020 + (0x1000 * (n))) ++#define EDMA_REG_RXFILL_DISABLE_DONE(n) (0x29024 + (0x1000 * (n))) ++#define EDMA_REG_RXFILL_INT_STAT(n) (0x31000 + (0x1000 * (n))) ++#define EDMA_REG_RXFILL_INT_MASK(n) (0x31004 + (0x1000 * (n))) ++ ++/* Rx descriptor ring configuration register addresses */ ++#define EDMA_REG_RXDESC_BA(n) (0x39000 + (0x1000 * (n))) ++#define EDMA_REG_RXDESC_PROD_IDX(n) (0x39004 + (0x1000 * (n))) ++#define EDMA_REG_RXDESC_CONS_IDX(n) (0x39008 + (0x1000 * (n))) ++#define EDMA_REG_RXDESC_RING_SIZE(n) (0x3900c + (0x1000 * (n))) ++#define EDMA_REG_RXDESC_FC_THRE(n) (0x39010 + (0x1000 * (n))) ++#define EDMA_REG_RXDESC_UGT_THRE(n) (0x39014 + (0x1000 * (n))) ++#define EDMA_REG_RXDESC_CTRL(n) (0x39018 + (0x1000 * (n))) ++#define EDMA_REG_RXDESC_BPC(n) (0x3901c + (0x1000 * (n))) ++#define EDMA_REG_RXDESC_DISABLE(n) (0x39020 + (0x1000 * (n))) ++#define EDMA_REG_RXDESC_DISABLE_DONE(n) (0x39024 + (0x1000 * (n))) ++#define EDMA_REG_RXDESC_PREHEADER_BA(n) (0x39028 + (0x1000 * (n))) ++#define EDMA_REG_RXDESC_INT_STAT(n) (0x59000 + (0x1000 * (n))) ++#define EDMA_REG_RXDESC_INT_MASK(n) (0x59004 + (0x1000 * (n))) ++ ++#define EDMA_REG_RX_MOD_TIMER(n) (0x59008 + (0x1000 * (n))) ++#define EDMA_REG_RX_INT_CTRL(n) (0x5900c + (0x1000 * (n))) ++ ++/* Tx completion ring configuration register addresses */ ++#define EDMA_REG_TXCMPL_BA(n) (0x79000 + (0x1000 * (n))) ++#define EDMA_REG_TXCMPL_PROD_IDX(n) (0x79004 + (0x1000 * (n))) ++#define EDMA_REG_TXCMPL_CONS_IDX(n) (0x79008 + (0x1000 * (n))) ++#define EDMA_REG_TXCMPL_RING_SIZE(n) (0x7900c + (0x1000 * (n))) ++#define EDMA_REG_TXCMPL_UGT_THRE(n) (0x79010 + (0x1000 * (n))) ++#define EDMA_REG_TXCMPL_CTRL(n) (0x79014 + (0x1000 * (n))) ++#define EDMA_REG_TXCMPL_BPC(n) (0x79018 + (0x1000 * (n))) ++ ++#define EDMA_REG_TX_INT_STAT(n) (0x99000 + (0x1000 * (n))) ++#define EDMA_REG_TX_INT_MASK(n) (0x99004 + (0x1000 * (n))) ++#define EDMA_REG_TX_MOD_TIMER(n) (0x99008 + (0x1000 * (n))) ++#define EDMA_REG_TX_INT_CTRL(n) (0x9900c + (0x1000 * (n))) ++ ++/* EDMA_QID2RID_TABLE_MEM register field masks */ ++#define EDMA_RX_RING_ID_QUEUE0_MASK GENMASK(7, 0) ++#define EDMA_RX_RING_ID_QUEUE1_MASK GENMASK(15, 8) ++#define EDMA_RX_RING_ID_QUEUE2_MASK GENMASK(23, 16) ++#define EDMA_RX_RING_ID_QUEUE3_MASK GENMASK(31, 24) ++ ++/* EDMA_REG_PORT_CTRL register bit definitions */ ++#define EDMA_PORT_PAD_EN 0x1 ++#define EDMA_PORT_EDMA_EN 0x2 ++ ++/* EDMA_REG_DMAR_CTRL register field masks */ ++#define EDMA_DMAR_REQ_PRI_MASK GENMASK(2, 0) ++#define EDMA_DMAR_BURST_LEN_MASK BIT(3) ++#define EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK GENMASK(8, 4) ++#define EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK GENMASK(11, 9) ++#define EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK GENMASK(14, 12) ++ ++#define EDMA_BURST_LEN_ENABLE 0 ++ ++/* Tx timeout threshold */ ++#define EDMA_TX_TIMEOUT_THRESH_VAL 0xFFFF ++ ++/* Rx descriptor ring base address mask */ ++#define EDMA_RXDESC_BA_MASK 0xffffffff ++ ++/* Rx Descriptor ring pre-header base address mask */ ++#define EDMA_RXDESC_PREHEADER_BA_MASK 0xffffffff ++ ++/* Tx descriptor prod ring index mask */ ++#define EDMA_TXDESC_PROD_IDX_MASK 0xffff ++ ++/* Tx descriptor consumer ring index mask */ ++#define EDMA_TXDESC_CONS_IDX_MASK 0xffff ++ ++/* Tx descriptor ring size mask */ ++#define EDMA_TXDESC_RING_SIZE_MASK 0xffff ++ ++/* Tx descriptor ring enable */ ++#define EDMA_TXDESC_TX_ENABLE 0x1 ++ ++#define EDMA_TXDESC_CTRL_TXEN_MASK BIT(0) ++#define EDMA_TXDESC_CTRL_FC_GRP_ID_MASK GENMASK(3, 1) ++ ++/* Tx completion ring prod index mask */ ++#define EDMA_TXCMPL_PROD_IDX_MASK 0xffff ++ ++/* Tx completion ring urgent threshold mask */ ++#define EDMA_TXCMPL_LOW_THRE_MASK 0xffff ++#define EDMA_TXCMPL_LOW_THRE_SHIFT 0 ++ ++/* EDMA_REG_TX_MOD_TIMER mask */ ++#define EDMA_TX_MOD_TIMER_INIT_MASK 0xffff ++#define EDMA_TX_MOD_TIMER_INIT_SHIFT 0 ++ ++/* Rx fill ring prod index mask */ ++#define EDMA_RXFILL_PROD_IDX_MASK 0xffff ++ ++/* Rx fill ring consumer index mask */ ++#define EDMA_RXFILL_CONS_IDX_MASK 0xffff ++ ++/* Rx fill ring size mask */ ++#define EDMA_RXFILL_RING_SIZE_MASK 0xffff ++ ++/* Rx fill ring flow control threshold masks */ ++#define EDMA_RXFILL_FC_XON_THRE_MASK 0x7ff ++#define EDMA_RXFILL_FC_XON_THRE_SHIFT 12 ++#define EDMA_RXFILL_FC_XOFF_THRE_MASK 0x7ff ++#define EDMA_RXFILL_FC_XOFF_THRE_SHIFT 0 ++ ++/* Rx fill ring enable bit */ ++#define EDMA_RXFILL_RING_EN 0x1 ++ ++/* Rx desc ring prod index mask */ ++#define EDMA_RXDESC_PROD_IDX_MASK 0xffff ++ ++/* Rx descriptor ring cons index mask */ ++#define EDMA_RXDESC_CONS_IDX_MASK 0xffff ++ ++/* Rx descriptor ring size masks */ ++#define EDMA_RXDESC_RING_SIZE_MASK 0xffff ++#define EDMA_RXDESC_PL_OFFSET_MASK 0x1ff ++#define EDMA_RXDESC_PL_OFFSET_SHIFT 16 ++#define EDMA_RXDESC_PL_DEFAULT_VALUE 0 ++ ++/* Rx descriptor ring flow control threshold masks */ ++#define EDMA_RXDESC_FC_XON_THRE_MASK 0x7ff ++#define EDMA_RXDESC_FC_XON_THRE_SHIFT 12 ++#define EDMA_RXDESC_FC_XOFF_THRE_MASK 0x7ff ++#define EDMA_RXDESC_FC_XOFF_THRE_SHIFT 0 ++ ++/* Rx descriptor ring urgent threshold mask */ ++#define EDMA_RXDESC_LOW_THRE_MASK 0xffff ++#define EDMA_RXDESC_LOW_THRE_SHIFT 0 ++ ++/* Rx descriptor ring enable bit */ ++#define EDMA_RXDESC_RX_EN 0x1 ++ ++/* Tx interrupt status bit */ ++#define EDMA_TX_INT_MASK_PKT_INT 0x1 ++ ++/* Rx interrupt mask */ ++#define EDMA_RXDESC_INT_MASK_PKT_INT 0x1 ++ ++#define EDMA_MASK_INT_DISABLE 0x0 ++#define EDMA_MASK_INT_CLEAR 0x0 ++ ++/* EDMA_REG_RX_MOD_TIMER register field masks */ ++#define EDMA_RX_MOD_TIMER_INIT_MASK 0xffff ++#define EDMA_RX_MOD_TIMER_INIT_SHIFT 0 ++ ++/* EDMA Ring mask */ ++#define EDMA_RING_DMA_MASK 0xffffffff ++ ++/* RXDESC threshold interrupt. */ ++#define EDMA_RXDESC_UGT_INT_STAT 0x2 ++ ++/* RXDESC timer interrupt */ ++#define EDMA_RXDESC_PKT_INT_STAT 0x1 ++ ++/* RXDESC Interrupt status mask */ ++#define EDMA_RXDESC_RING_INT_STATUS_MASK \ ++ (EDMA_RXDESC_UGT_INT_STAT | EDMA_RXDESC_PKT_INT_STAT) ++ ++/* TXCMPL threshold interrupt. */ ++#define EDMA_TXCMPL_UGT_INT_STAT 0x2 ++ ++/* TXCMPL timer interrupt */ ++#define EDMA_TXCMPL_PKT_INT_STAT 0x1 ++ ++/* TXCMPL Interrupt status mask */ ++#define EDMA_TXCMPL_RING_INT_STATUS_MASK \ ++ (EDMA_TXCMPL_UGT_INT_STAT | EDMA_TXCMPL_PKT_INT_STAT) ++ ++#define EDMA_TXCMPL_RETMODE_OPAQUE 0x0 ++ ++#define EDMA_RXDESC_LOW_THRE 0 ++#define EDMA_RX_MOD_TIMER_INIT 1000 ++#define EDMA_RX_NE_INT_EN 0x2 ++ ++#define EDMA_TX_MOD_TIMER 150 ++ ++#define EDMA_TX_INITIAL_PROD_IDX 0x0 ++#define EDMA_TX_NE_INT_EN 0x2 ++ ++/* EDMA misc error mask */ ++#define EDMA_MISC_AXI_RD_ERR_MASK BIT(0) ++#define EDMA_MISC_AXI_WR_ERR_MASK BIT(1) ++#define EDMA_MISC_RX_DESC_FIFO_FULL_MASK BIT(2) ++#define EDMA_MISC_RX_ERR_BUF_SIZE_MASK BIT(3) ++#define EDMA_MISC_TX_SRAM_FULL_MASK BIT(4) ++#define EDMA_MISC_TX_CMPL_BUF_FULL_MASK BIT(5) ++ ++#define EDMA_MISC_DATA_LEN_ERR_MASK BIT(6) ++#define EDMA_MISC_TX_TIMEOUT_MASK BIT(7) ++ ++/* EDMA txdesc2cmpl map */ ++#define EDMA_TXDESC2CMPL_MAP_TXDESC_MASK 0x1F ++ ++/* EDMA rxdesc2fill map */ ++#define EDMA_RXDESC2FILL_MAP_RXDESC_MASK 0x7 ++ + #endif diff --git a/target/linux/qualcommbe/patches-6.12/0343-net-ethernet-qualcomm-Add-netdevice-support-for-QCOM.patch b/target/linux/qualcommbe/patches-6.12/0343-net-ethernet-qualcomm-Add-netdevice-support-for-QCOM.patch new file mode 100644 index 0000000000..55de486ed3 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0343-net-ethernet-qualcomm-Add-netdevice-support-for-QCOM.patch @@ -0,0 +1,397 @@ +From 5dc80c468c668d855d76b323f09bbadb95cc3147 Mon Sep 17 00:00:00 2001 +From: Suruchi Agarwal +Date: Thu, 21 Mar 2024 16:14:46 -0700 +Subject: [PATCH] net: ethernet: qualcomm: Add netdevice support for QCOM + IPQ9574 chipset. + +Add EDMA ports and netdevice operations for QCOM IPQ9574 chipset. + +Change-Id: I08b2eff52b4ef0d6d428c1c416f5580ef010973f +Co-developed-by: Pavithra R +Signed-off-by: Pavithra R +Signed-off-by: Suruchi Agarwal +--- + drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +- + drivers/net/ethernet/qualcomm/ppe/edma.h | 3 + + drivers/net/ethernet/qualcomm/ppe/edma_port.c | 270 ++++++++++++++++++ + drivers/net/ethernet/qualcomm/ppe/edma_port.h | 31 ++ + drivers/net/ethernet/qualcomm/ppe/ppe_port.c | 19 ++ + 5 files changed, 324 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_port.c + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_port.h + +--- a/drivers/net/ethernet/qualcomm/ppe/Makefile ++++ b/drivers/net/ethernet/qualcomm/ppe/Makefile +@@ -7,4 +7,4 @@ obj-$(CONFIG_QCOM_PPE) += qcom-ppe.o + qcom-ppe-objs := ppe.o ppe_config.o ppe_debugfs.o ppe_port.o + + #EDMA +-qcom-ppe-objs += edma.o ++qcom-ppe-objs += edma.o edma_port.o +--- a/drivers/net/ethernet/qualcomm/ppe/edma.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.h +@@ -26,6 +26,9 @@ + /* Number of PPE queue priorities supported per ARM core. */ + #define EDMA_PRI_MAX_PER_CORE 8 + ++/* Interface ID start. */ ++#define EDMA_START_IFNUM 1 ++ + /** + * enum ppe_queue_class_type - PPE queue class type + * @PPE_QUEUE_CLASS_PRIORITY: Queue offset configured from internal priority +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_port.c +@@ -0,0 +1,270 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ /* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* EDMA port initialization, configuration and netdevice ops handling */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "edma.h" ++#include "edma_port.h" ++#include "ppe_regs.h" ++ ++/* Number of netdev queues. */ ++#define EDMA_NETDEV_QUEUE_NUM 4 ++ ++static u16 __maybe_unused edma_port_select_queue(__maybe_unused struct net_device *netdev, ++ __maybe_unused struct sk_buff *skb, ++ __maybe_unused struct net_device *sb_dev) ++{ ++ int cpu = get_cpu(); ++ ++ put_cpu(); ++ ++ return cpu; ++} ++ ++static int edma_port_open(struct net_device *netdev) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct ppe_port *ppe_port; ++ ++ if (!port_priv) ++ return -EINVAL; ++ ++ /* Inform the Linux Networking stack about the hardware capability of ++ * checksum offloading and other features. Each port is ++ * responsible to maintain the feature set it supports. ++ */ ++ netdev->features |= EDMA_NETDEV_FEATURES; ++ netdev->hw_features |= EDMA_NETDEV_FEATURES; ++ netdev->vlan_features |= EDMA_NETDEV_FEATURES; ++ netdev->wanted_features |= EDMA_NETDEV_FEATURES; ++ ++ ppe_port = port_priv->ppe_port; ++ ++ if (ppe_port->phylink) ++ phylink_start(ppe_port->phylink); ++ ++ netif_start_queue(netdev); ++ ++ return 0; ++} ++ ++static int edma_port_close(struct net_device *netdev) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct ppe_port *ppe_port; ++ ++ if (!port_priv) ++ return -EINVAL; ++ ++ netif_stop_queue(netdev); ++ ++ ppe_port = port_priv->ppe_port; ++ ++ /* Phylink close. */ ++ if (ppe_port->phylink) ++ phylink_stop(ppe_port->phylink); ++ ++ return 0; ++} ++ ++static int edma_port_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct ppe_port *ppe_port; ++ int ret = -EINVAL; ++ ++ if (!port_priv) ++ return -EINVAL; ++ ++ ppe_port = port_priv->ppe_port; ++ if (ppe_port->phylink) ++ return phylink_mii_ioctl(ppe_port->phylink, ifr, cmd); ++ ++ return ret; ++} ++ ++static int edma_port_change_mtu(struct net_device *netdev, int mtu) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ ++ if (!port_priv) ++ return -EINVAL; ++ ++ netdev->mtu = mtu; ++ ++ return ppe_port_set_maxframe(port_priv->ppe_port, mtu); ++} ++ ++static netdev_features_t edma_port_feature_check(__maybe_unused struct sk_buff *skb, ++ __maybe_unused struct net_device *netdev, ++ netdev_features_t features) ++{ ++ return features; ++} ++ ++static void edma_port_get_stats64(struct net_device *netdev, ++ struct rtnl_link_stats64 *stats) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ ++ if (!port_priv) ++ return; ++ ++ ppe_port_get_stats64(port_priv->ppe_port, stats); ++} ++ ++static int edma_port_set_mac_address(struct net_device *netdev, void *macaddr) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct sockaddr *addr = (struct sockaddr *)macaddr; ++ int ret; ++ ++ if (!port_priv) ++ return -EINVAL; ++ ++ netdev_dbg(netdev, "AddrFamily: %d, %0x:%0x:%0x:%0x:%0x:%0x\n", ++ addr->sa_family, addr->sa_data[0], addr->sa_data[1], ++ addr->sa_data[2], addr->sa_data[3], addr->sa_data[4], ++ addr->sa_data[5]); ++ ++ ret = eth_prepare_mac_addr_change(netdev, addr); ++ if (ret) ++ return ret; ++ ++ if (ppe_port_set_mac_address(port_priv->ppe_port, (u8 *)addr)) { ++ netdev_err(netdev, "set mac address failed for dev: %s\n", netdev->name); ++ return -EINVAL; ++ } ++ ++ eth_commit_mac_addr_change(netdev, addr); ++ ++ return 0; ++} ++ ++static const struct net_device_ops edma_port_netdev_ops = { ++ .ndo_open = edma_port_open, ++ .ndo_stop = edma_port_close, ++ .ndo_get_stats64 = edma_port_get_stats64, ++ .ndo_set_mac_address = edma_port_set_mac_address, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_change_mtu = edma_port_change_mtu, ++ .ndo_eth_ioctl = edma_port_ioctl, ++ .ndo_features_check = edma_port_feature_check, ++ .ndo_select_queue = edma_port_select_queue, ++}; ++ ++/** ++ * edma_port_destroy - EDMA port destroy. ++ * @port: PPE port ++ * ++ * Unregister and free the netdevice. ++ */ ++void edma_port_destroy(struct ppe_port *port) ++{ ++ int port_id = port->port_id; ++ struct net_device *netdev = edma_ctx->netdev_arr[port_id - 1]; ++ ++ unregister_netdev(netdev); ++ free_netdev(netdev); ++ ppe_port_phylink_destroy(port); ++ edma_ctx->netdev_arr[port_id - 1] = NULL; ++} ++ ++/** ++ * edma_port_setup - EDMA port Setup. ++ * @port: PPE port ++ * ++ * Initialize and register the netdevice. ++ * ++ * Return 0 on success, negative error code on failure. ++ */ ++int edma_port_setup(struct ppe_port *port) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct device_node *np = port->np; ++ struct edma_port_priv *port_priv; ++ int port_id = port->port_id; ++ struct net_device *netdev; ++ u8 mac_addr[ETH_ALEN]; ++ int ret = 0; ++ u8 *maddr; ++ ++ netdev = alloc_etherdev_mqs(sizeof(struct edma_port_priv), ++ EDMA_NETDEV_QUEUE_NUM, EDMA_NETDEV_QUEUE_NUM); ++ if (!netdev) { ++ pr_err("alloc_etherdev() failed\n"); ++ return -ENOMEM; ++ } ++ ++ SET_NETDEV_DEV(netdev, ppe_dev->dev); ++ netdev->dev.of_node = np; ++ ++ /* max_mtu is set to 1500 in ether_setup(). */ ++ netdev->max_mtu = ETH_MAX_MTU; ++ ++ port_priv = netdev_priv(netdev); ++ memset((void *)port_priv, 0, sizeof(struct edma_port_priv)); ++ ++ port_priv->ppe_port = port; ++ port_priv->netdev = netdev; ++ netdev->watchdog_timeo = 5 * HZ; ++ netdev->priv_flags |= IFF_LIVE_ADDR_CHANGE; ++ netdev->netdev_ops = &edma_port_netdev_ops; ++ netdev->gso_max_segs = GSO_MAX_SEGS; ++ ++ maddr = mac_addr; ++ if (of_get_mac_address(np, maddr)) ++ maddr = NULL; ++ ++ if (maddr && is_valid_ether_addr(maddr)) { ++ eth_hw_addr_set(netdev, maddr); ++ } else { ++ eth_hw_addr_random(netdev); ++ netdev_info(netdev, "GMAC%d Using random MAC address - %pM\n", ++ port_id, netdev->dev_addr); ++ } ++ ++ netdev_dbg(netdev, "Configuring the port %s(qcom-id:%d)\n", ++ netdev->name, port_id); ++ ++ /* We expect 'port_id' to correspond to ports numbers on SoC. ++ * These begin from '1' and hence we subtract ++ * one when using it as an array index. ++ */ ++ edma_ctx->netdev_arr[port_id - 1] = netdev; ++ ++ /* Setup phylink. */ ++ ret = ppe_port_phylink_setup(port, netdev); ++ if (ret) { ++ netdev_dbg(netdev, "EDMA port phylink setup for netdevice %s\n", ++ netdev->name); ++ goto port_phylink_setup_fail; ++ } ++ ++ /* Register the network interface. */ ++ ret = register_netdev(netdev); ++ if (ret) { ++ netdev_dbg(netdev, "Error registering netdevice %s\n", ++ netdev->name); ++ goto register_netdev_fail; ++ } ++ ++ netdev_dbg(netdev, "Setup EDMA port GMAC%d done\n", port_id); ++ return ret; ++ ++register_netdev_fail: ++ ppe_port_phylink_destroy(port); ++port_phylink_setup_fail: ++ free_netdev(netdev); ++ edma_ctx->netdev_arr[port_id - 1] = NULL; ++ ++ return ret; ++} +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_port.h +@@ -0,0 +1,31 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#ifndef __EDMA_PORTS__ ++#define __EDMA_PORTS__ ++ ++#include "ppe_port.h" ++ ++#define EDMA_NETDEV_FEATURES (NETIF_F_FRAGLIST \ ++ | NETIF_F_SG \ ++ | NETIF_F_RXCSUM \ ++ | NETIF_F_HW_CSUM \ ++ | NETIF_F_TSO \ ++ | NETIF_F_TSO6) ++ ++/** ++ * struct edma_port_priv - EDMA port priv structure. ++ * @ppe_port: Pointer to PPE port ++ * @netdev: Corresponding netdevice ++ * @flags: Feature flags ++ */ ++struct edma_port_priv { ++ struct ppe_port *ppe_port; ++ struct net_device *netdev; ++ unsigned long flags; ++}; ++ ++void edma_port_destroy(struct ppe_port *port); ++int edma_port_setup(struct ppe_port *port); ++#endif +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.c +@@ -13,6 +13,7 @@ + #include + #include + ++#include "edma_port.h" + #include "ppe.h" + #include "ppe_port.h" + #include "ppe_regs.h" +@@ -1277,12 +1278,26 @@ int ppe_port_mac_init(struct ppe_device + goto err_port_node; + } + ++ ret = edma_port_setup(&ppe_ports->port[i]); ++ if (ret) { ++ dev_err(ppe_dev->dev, "QCOM EDMA port setup failed\n"); ++ i--; ++ goto err_port_setup; ++ } ++ + i++; + } + + of_node_put(ports_node); + return 0; + ++err_port_setup: ++ /* Destroy edma ports created till now */ ++ while (i >= 0) { ++ edma_port_destroy(&ppe_ports->port[i]); ++ i--; ++ } ++ + err_port_clk: + for (j = 0; j < i; j++) + ppe_port_clock_deinit(&ppe_ports->port[j]); +@@ -1307,6 +1322,10 @@ void ppe_port_mac_deinit(struct ppe_devi + + for (i = 0; i < ppe_dev->ports->num; i++) { + ppe_port = &ppe_dev->ports->port[i]; ++ ++ /* Destroy all phylinks and edma ports */ ++ edma_port_destroy(ppe_port); ++ + ppe_port_clock_deinit(ppe_port); + } + } diff --git a/target/linux/qualcommbe/patches-6.12/0344-net-ethernet-qualcomm-Add-Rx-Ethernet-DMA-support.patch b/target/linux/qualcommbe/patches-6.12/0344-net-ethernet-qualcomm-Add-Rx-Ethernet-DMA-support.patch new file mode 100644 index 0000000000..eb10a00745 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0344-net-ethernet-qualcomm-Add-Rx-Ethernet-DMA-support.patch @@ -0,0 +1,2454 @@ +From b5c8c5d3888328321e8be1db50b75dff8f514e51 Mon Sep 17 00:00:00 2001 +From: Suruchi Agarwal +Date: Thu, 21 Mar 2024 16:21:19 -0700 +Subject: [PATCH] net: ethernet: qualcomm: Add Rx Ethernet DMA support + +Add Rx queues, rings, descriptors configurations and +DMA support for the EDMA. + +Change-Id: I612bcd661e74d5bf3ecb33de10fd5298d18ff7e9 +Co-developed-by: Pavithra R +Signed-off-by: Pavithra R +Signed-off-by: Suruchi Agarwal +Alex G: add missing functions that were previously in ppe_api.c: + - ppe_edma_queue_resource_get() + - ppe_edma_ring_to_queues_config() +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +- + drivers/net/ethernet/qualcomm/ppe/edma.c | 214 +++- + drivers/net/ethernet/qualcomm/ppe/edma.h | 22 +- + .../net/ethernet/qualcomm/ppe/edma_cfg_rx.c | 964 ++++++++++++++++++ + .../net/ethernet/qualcomm/ppe/edma_cfg_rx.h | 48 + + drivers/net/ethernet/qualcomm/ppe/edma_port.c | 39 +- + drivers/net/ethernet/qualcomm/ppe/edma_port.h | 31 + + drivers/net/ethernet/qualcomm/ppe/edma_rx.c | 622 +++++++++++ + drivers/net/ethernet/qualcomm/ppe/edma_rx.h | 287 ++++++ + 9 files changed, 2224 insertions(+), 5 deletions(-) + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_rx.c + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_rx.h + +--- a/drivers/net/ethernet/qualcomm/ppe/Makefile ++++ b/drivers/net/ethernet/qualcomm/ppe/Makefile +@@ -7,4 +7,4 @@ obj-$(CONFIG_QCOM_PPE) += qcom-ppe.o + qcom-ppe-objs := ppe.o ppe_config.o ppe_debugfs.o ppe_port.o + + #EDMA +-qcom-ppe-objs += edma.o edma_port.o ++qcom-ppe-objs += edma.o edma_cfg_rx.o edma_port.o edma_rx.o +--- a/drivers/net/ethernet/qualcomm/ppe/edma.c ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.c +@@ -18,12 +18,23 @@ + #include + + #include "edma.h" ++#include "edma_cfg_rx.h" + #include "ppe_regs.h" + + #define EDMA_IRQ_NAME_SIZE 32 + + /* Global EDMA context. */ + struct edma_context *edma_ctx; ++static char **edma_rxdesc_irq_name; ++ ++/* Module params. */ ++static int page_mode; ++module_param(page_mode, int, 0); ++MODULE_PARM_DESC(page_mode, "Enable page mode (default:0)"); ++ ++static int rx_buff_size; ++module_param(rx_buff_size, int, 0640); ++MODULE_PARM_DESC(rx_buff_size, "Rx Buffer size for Jumbo MRU value (default:0)"); + + /* Priority to multi-queue mapping. */ + static u8 edma_pri_map[PPE_QUEUE_INTER_PRI_NUM] = { +@@ -178,6 +189,59 @@ static int edma_configure_ucast_prio_map + return ret; + } + ++static int edma_irq_register(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rx = hw_info->rx; ++ int ret; ++ u32 i; ++ ++ /* Request IRQ for RXDESC rings. */ ++ edma_rxdesc_irq_name = kzalloc((sizeof(char *) * rx->num_rings), ++ GFP_KERNEL); ++ if (!edma_rxdesc_irq_name) ++ return -ENOMEM; ++ ++ for (i = 0; i < rx->num_rings; i++) { ++ edma_rxdesc_irq_name[i] = kzalloc((sizeof(char *) * EDMA_IRQ_NAME_SIZE), ++ GFP_KERNEL); ++ if (!edma_rxdesc_irq_name[i]) { ++ ret = -ENOMEM; ++ goto rxdesc_irq_name_alloc_fail; ++ } ++ ++ snprintf(edma_rxdesc_irq_name[i], 20, "edma_rxdesc_%d", ++ rx->ring_start + i); ++ ++ irq_set_status_flags(edma_ctx->intr_info.intr_rx[i], IRQ_DISABLE_UNLAZY); ++ ++ ret = request_irq(edma_ctx->intr_info.intr_rx[i], ++ edma_rx_handle_irq, IRQF_SHARED, ++ edma_rxdesc_irq_name[i], ++ (void *)&edma_ctx->rx_rings[i]); ++ if (ret) { ++ pr_err("RXDESC ring IRQ:%d request failed\n", ++ edma_ctx->intr_info.intr_rx[i]); ++ goto rx_desc_ring_intr_req_fail; ++ } ++ ++ pr_debug("RXDESC ring: %d IRQ:%d request success: %s\n", ++ rx->ring_start + i, ++ edma_ctx->intr_info.intr_rx[i], ++ edma_rxdesc_irq_name[i]); ++ } ++ ++ return 0; ++ ++rx_desc_ring_intr_req_fail: ++ for (i = 0; i < rx->num_rings; i++) ++ kfree(edma_rxdesc_irq_name[i]); ++rxdesc_irq_name_alloc_fail: ++ kfree(edma_rxdesc_irq_name); ++ ++ return ret; ++} ++ + static int edma_irq_init(void) + { + struct edma_hw_info *hw_info = edma_ctx->hw_info; +@@ -260,6 +324,16 @@ static int edma_irq_init(void) + return 0; + } + ++static int edma_alloc_rings(void) ++{ ++ if (edma_cfg_rx_rings_alloc()) { ++ pr_err("Error in allocating Rx rings\n"); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ + static int edma_hw_reset(void) + { + struct ppe_device *ppe_dev = edma_ctx->ppe_dev; +@@ -343,6 +417,40 @@ static int edma_hw_configure(void) + if (!edma_ctx->netdev_arr) + return -ENOMEM; + ++ edma_ctx->dummy_dev = alloc_netdev_dummy(0); ++ if (!edma_ctx->dummy_dev) { ++ ret = -ENOMEM; ++ pr_err("Failed to allocate dummy device. ret: %d\n", ret); ++ goto dummy_dev_alloc_failed; ++ } ++ ++ /* Set EDMA jumbo MRU if enabled or set page mode. */ ++ if (edma_ctx->rx_buf_size) { ++ edma_ctx->rx_page_mode = false; ++ pr_debug("Rx Jumbo mru is enabled: %d\n", edma_ctx->rx_buf_size); ++ } else { ++ edma_ctx->rx_page_mode = page_mode; ++ } ++ ++ ret = edma_alloc_rings(); ++ if (ret) { ++ pr_err("Error in initializaing the rings. ret: %d\n", ret); ++ goto edma_alloc_rings_failed; ++ } ++ ++ /* Disable interrupts. */ ++ edma_cfg_rx_disable_interrupts(); ++ ++ edma_cfg_rx_rings_disable(); ++ ++ edma_cfg_rx_ring_mappings(); ++ ++ ret = edma_cfg_rx_rings(); ++ if (ret) { ++ pr_err("Error in configuring Rx rings. ret: %d\n", ret); ++ goto edma_cfg_rx_rings_failed; ++ } ++ + /* Configure DMA request priority, DMA read burst length, + * and AXI write size. + */ +@@ -376,6 +484,10 @@ static int edma_hw_configure(void) + data |= EDMA_MISC_TX_TIMEOUT_MASK; + edma_ctx->intr_info.intr_mask_misc = data; + ++ edma_cfg_rx_rings_enable(); ++ edma_cfg_rx_napi_add(); ++ edma_cfg_rx_napi_enable(); ++ + /* Global EDMA enable and padding enable. */ + data = EDMA_PORT_PAD_EN | EDMA_PORT_EDMA_EN; + +@@ -389,11 +501,32 @@ static int edma_hw_configure(void) + if (ret) { + pr_err("Failed to initialize unicast priority map table: %d\n", + ret); +- kfree(edma_ctx->netdev_arr); +- return ret; ++ goto configure_ucast_prio_map_tbl_failed; ++ } ++ ++ /* Initialize RPS hash map table. */ ++ ret = edma_cfg_rx_rps_hash_map(); ++ if (ret) { ++ pr_err("Failed to configure rps hash table: %d\n", ++ ret); ++ goto edma_cfg_rx_rps_hash_map_failed; + } + + return 0; ++ ++edma_cfg_rx_rps_hash_map_failed: ++configure_ucast_prio_map_tbl_failed: ++ edma_cfg_rx_napi_disable(); ++ edma_cfg_rx_napi_delete(); ++ edma_cfg_rx_rings_disable(); ++edma_cfg_rx_rings_failed: ++ edma_cfg_rx_rings_cleanup(); ++edma_alloc_rings_failed: ++ free_netdev(edma_ctx->dummy_dev); ++dummy_dev_alloc_failed: ++ kfree(edma_ctx->netdev_arr); ++ ++ return ret; + } + + /** +@@ -404,8 +537,31 @@ static int edma_hw_configure(void) + */ + void edma_destroy(struct ppe_device *ppe_dev) + { ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i; ++ ++ /* Disable interrupts. */ ++ edma_cfg_rx_disable_interrupts(); ++ ++ /* Free IRQ for RXDESC rings. */ ++ for (i = 0; i < rx->num_rings; i++) { ++ synchronize_irq(edma_ctx->intr_info.intr_rx[i]); ++ free_irq(edma_ctx->intr_info.intr_rx[i], ++ (void *)&edma_ctx->rx_rings[i]); ++ kfree(edma_rxdesc_irq_name[i]); ++ } ++ kfree(edma_rxdesc_irq_name); ++ + kfree(edma_ctx->intr_info.intr_rx); + kfree(edma_ctx->intr_info.intr_txcmpl); ++ ++ edma_cfg_rx_napi_disable(); ++ edma_cfg_rx_napi_delete(); ++ edma_cfg_rx_rings_disable(); ++ edma_cfg_rx_rings_cleanup(); ++ ++ free_netdev(edma_ctx->dummy_dev); + kfree(edma_ctx->netdev_arr); + } + +@@ -428,6 +584,7 @@ int edma_setup(struct ppe_device *ppe_de + + edma_ctx->hw_info = &ipq9574_hw_info; + edma_ctx->ppe_dev = ppe_dev; ++ edma_ctx->rx_buf_size = rx_buff_size; + + /* Configure the EDMA common clocks. */ + ret = edma_clock_init(); +@@ -450,6 +607,16 @@ int edma_setup(struct ppe_device *ppe_de + return ret; + } + ++ ret = edma_irq_register(); ++ if (ret) { ++ dev_err(dev, "Error in irq registration\n"); ++ kfree(edma_ctx->intr_info.intr_rx); ++ kfree(edma_ctx->intr_info.intr_txcmpl); ++ return ret; ++ } ++ ++ edma_cfg_rx_enable_interrupts(); ++ + dev_info(dev, "EDMA configuration successful\n"); + + return 0; +@@ -478,3 +645,46 @@ int ppe_edma_queue_offset_config(struct + return ppe_queue_ucast_offset_hash_set(ppe_dev, 0, + index, queue_offset); + } ++ ++/** ++ * ppe_edma_queue_resource_get - Get EDMA queue resource ++ * @ppe_dev: PPE device ++ * @type: Resource type ++ * @res_start: Resource start ID returned ++ * @res_end: Resource end ID returned ++ * ++ * PPE EDMA queue resource includes unicast queue and multicast queue. ++ * ++ * Return 0 on success, negative error code on failure. ++ */ ++int ppe_edma_queue_resource_get(struct ppe_device *ppe_dev, int type, ++ int *res_start, int *res_end) ++{ ++ if (type != PPE_RES_UCAST && type != PPE_RES_MCAST) ++ return -EINVAL; ++ ++ return ppe_port_resource_get(ppe_dev, 0, type, res_start, res_end); ++}; ++ ++/** ++ * ppe_edma_ring_to_queues_config - Map EDMA ring to PPE queues ++ * @ppe_dev: PPE device ++ * @ring_id: EDMA ring ID ++ * @num: Number of queues mapped to EDMA ring ++ * @queues: PPE queue IDs ++ * ++ * PPE queues are configured to map with the special EDMA ring ID. ++ * ++ * Return 0 on success, negative error code on failure. ++ */ ++int ppe_edma_ring_to_queues_config(struct ppe_device *ppe_dev, int ring_id, ++ int num, int queues[] __counted_by(num)) ++{ ++ u32 queue_bmap[PPE_RING_TO_QUEUE_BITMAP_WORD_CNT] = {}; ++ int index; ++ ++ for (index = 0; index < num; index++) ++ queue_bmap[queues[index] / 32] |= BIT_MASK(queues[index] % 32); ++ ++ return ppe_ring_queue_map_set(ppe_dev, ring_id, queue_bmap); ++} +--- a/drivers/net/ethernet/qualcomm/ppe/edma.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.h +@@ -6,6 +6,7 @@ + #define __EDMA_MAIN__ + + #include "ppe_config.h" ++#include "edma_rx.h" + + /* One clock cycle = 1/(EDMA clock frequency in Mhz) micro seconds. + * +@@ -29,6 +30,11 @@ + /* Interface ID start. */ + #define EDMA_START_IFNUM 1 + ++#define EDMA_DESC_AVAIL_COUNT(head, tail, _max) ({ \ ++ typeof(_max) (max) = (_max); \ ++ ((((head) - (tail)) + \ ++ (max)) & ((max) - 1)); }) ++ + /** + * enum ppe_queue_class_type - PPE queue class type + * @PPE_QUEUE_CLASS_PRIORITY: Queue offset configured from internal priority +@@ -92,18 +98,28 @@ struct edma_intr_info { + /** + * struct edma_context - EDMA context. + * @netdev_arr: Net device for each EDMA port ++ * @dummy_dev: Dummy netdevice for RX DMA + * @ppe_dev: PPE device + * @hw_info: EDMA Hardware info + * @intr_info: EDMA Interrupt info ++ * @rxfill_rings: Rx fill Rings, SW is producer ++ * @rx_rings: Rx Desc Rings, SW is consumer ++ * @rx_page_mode: Page mode enabled or disabled ++ * @rx_buf_size: Rx buffer size for Jumbo MRU + */ + struct edma_context { + struct net_device **netdev_arr; ++ struct net_device *dummy_dev; + struct ppe_device *ppe_dev; + struct edma_hw_info *hw_info; + struct edma_intr_info intr_info; ++ struct edma_rxfill_ring *rxfill_rings; ++ struct edma_rxdesc_ring *rx_rings; ++ u32 rx_page_mode; ++ u32 rx_buf_size; + }; + +-/* Global EDMA context. */ ++/* Global EDMA context */ + extern struct edma_context *edma_ctx; + + void edma_destroy(struct ppe_device *ppe_dev); +@@ -111,6 +127,10 @@ int edma_setup(struct ppe_device *ppe_de + int ppe_edma_queue_offset_config(struct ppe_device *ppe_dev, + enum ppe_queue_class_type class, + int index, int queue_offset); ++int ppe_edma_queue_resource_get(struct ppe_device *ppe_dev, int type, ++ int *res_start, int *res_end); ++int ppe_edma_ring_to_queues_config(struct ppe_device *ppe_dev, int ring_id, ++ int num, int queues[] __counted_by(num)); + + + #endif +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c +@@ -0,0 +1,964 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* Configure rings, Buffers and NAPI for receive path along with ++ * providing APIs to enable, disable, clean and map the Rx rings. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "edma.h" ++#include "edma_cfg_rx.h" ++#include "ppe.h" ++#include "ppe_regs.h" ++ ++/* EDMA Queue ID to Ring ID Table. */ ++#define EDMA_QID2RID_TABLE_MEM(q) (0xb9000 + (0x4 * (q))) ++ ++/* Rx ring queue offset. */ ++#define EDMA_QUEUE_OFFSET(q_id) ((q_id) / EDMA_MAX_PRI_PER_CORE) ++ ++/* Rx EDMA maximum queue supported. */ ++#define EDMA_CPU_PORT_QUEUE_MAX(queue_start) \ ++ ((queue_start) + (EDMA_MAX_PRI_PER_CORE * num_possible_cpus()) - 1) ++ ++/* EDMA Queue ID to Ring ID configuration. */ ++#define EDMA_QID2RID_NUM_PER_REG 4 ++ ++int rx_queues[] = {0, 8, 16, 24}; ++ ++static u32 edma_rx_ring_queue_map[][EDMA_MAX_CORE] = {{ 0, 8, 16, 24 }, ++ { 1, 9, 17, 25 }, ++ { 2, 10, 18, 26 }, ++ { 3, 11, 19, 27 }, ++ { 4, 12, 20, 28 }, ++ { 5, 13, 21, 29 }, ++ { 6, 14, 22, 30 }, ++ { 7, 15, 23, 31 }}; ++ ++static int edma_cfg_rx_desc_rings_reset_queue_mapping(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i, ret; ++ ++ for (i = 0; i < rx->num_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring; ++ ++ rxdesc_ring = &edma_ctx->rx_rings[i]; ++ ++ ret = ppe_edma_ring_to_queues_config(edma_ctx->ppe_dev, rxdesc_ring->ring_id, ++ ARRAY_SIZE(rx_queues), rx_queues); ++ if (ret) { ++ pr_err("Error in unmapping rxdesc ring %d to PPE queue mapping to disable its backpressure configuration\n", ++ i); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int edma_cfg_rx_desc_ring_reset_queue_priority(u32 rxdesc_ring_idx) ++{ ++ u32 i, queue_id, ret; ++ ++ for (i = 0; i < EDMA_MAX_PRI_PER_CORE; i++) { ++ queue_id = edma_rx_ring_queue_map[i][rxdesc_ring_idx]; ++ ++ ret = ppe_queue_priority_set(edma_ctx->ppe_dev, queue_id, i); ++ if (ret) { ++ pr_err("Error in resetting %u queue's priority\n", ++ queue_id); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int edma_cfg_rx_desc_ring_reset_queue_config(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i, ret; ++ ++ if (unlikely(rx->num_rings > num_possible_cpus())) { ++ pr_err("Invalid count of rxdesc rings: %d\n", ++ rx->num_rings); ++ return -EINVAL; ++ } ++ ++ /* Unmap Rxdesc ring to PPE queue mapping */ ++ ret = edma_cfg_rx_desc_rings_reset_queue_mapping(); ++ if (ret) { ++ pr_err("Error in resetting Rx desc ring backpressure config\n"); ++ return ret; ++ } ++ ++ /* Reset the priority for PPE queues mapped to Rx rings */ ++ for (i = 0; i < rx->num_rings; i++) { ++ ret = edma_cfg_rx_desc_ring_reset_queue_priority(i); ++ if (ret) { ++ pr_err("Error in resetting ring:%d queue's priority\n", ++ i + rx->ring_start); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int edma_cfg_rx_desc_ring_to_queue_mapping(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i; ++ int ret; ++ ++ /* Rxdesc ring to PPE queue mapping */ ++ for (i = 0; i < rx->num_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring; ++ ++ rxdesc_ring = &edma_ctx->rx_rings[i]; ++ ++ ret = ppe_edma_ring_to_queues_config(edma_ctx->ppe_dev, ++ rxdesc_ring->ring_id, ++ ARRAY_SIZE(rx_queues), rx_queues); ++ if (ret) { ++ pr_err("Error in configuring Rx ring to PPE queue mapping, ret: %d, id: %d\n", ++ ret, rxdesc_ring->ring_id); ++ if (!edma_cfg_rx_desc_rings_reset_queue_mapping()) ++ pr_err("Error in resetting Rx desc ringbackpressure configurations\n"); ++ ++ return ret; ++ } ++ ++ pr_debug("Rx desc ring %d to PPE queue mapping for backpressure:\n", ++ rxdesc_ring->ring_id); ++ } ++ ++ return 0; ++} ++ ++static void edma_cfg_rx_desc_ring_configure(struct edma_rxdesc_ring *rxdesc_ring) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 data, reg; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_BA(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, (u32)(rxdesc_ring->pdma & EDMA_RXDESC_BA_MASK)); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_PREHEADER_BA(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, (u32)(rxdesc_ring->sdma & EDMA_RXDESC_PREHEADER_BA_MASK)); ++ ++ data = rxdesc_ring->count & EDMA_RXDESC_RING_SIZE_MASK; ++ data |= (EDMA_RXDESC_PL_DEFAULT_VALUE & EDMA_RXDESC_PL_OFFSET_MASK) ++ << EDMA_RXDESC_PL_OFFSET_SHIFT; ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_RING_SIZE(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, data); ++ ++ /* Configure the Mitigation timer */ ++ data = EDMA_MICROSEC_TO_TIMER_UNIT(EDMA_RX_MITIGATION_TIMER_DEF, ++ ppe_dev->clk_rate / MHZ); ++ data = ((data & EDMA_RX_MOD_TIMER_INIT_MASK) ++ << EDMA_RX_MOD_TIMER_INIT_SHIFT); ++ pr_debug("EDMA Rx mitigation timer value: %d\n", data); ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RX_MOD_TIMER(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, data); ++ ++ /* Configure the Mitigation packet count */ ++ data = (EDMA_RX_MITIGATION_PKT_CNT_DEF & EDMA_RXDESC_LOW_THRE_MASK) ++ << EDMA_RXDESC_LOW_THRE_SHIFT; ++ pr_debug("EDMA Rx mitigation packet count value: %d\n", data); ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_UGT_THRE(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, data); ++ ++ /* Enable ring. Set ret mode to 'opaque'. */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RX_INT_CTRL(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, EDMA_RX_NE_INT_EN); ++} ++ ++static void edma_cfg_rx_qid_to_rx_desc_ring_mapping(void) ++{ ++ u32 desc_index, ring_index, reg_index, data, q_id; ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 mcast_start, mcast_end, reg; ++ int ret; ++ ++ desc_index = (rx->ring_start & EDMA_RX_RING_ID_MASK); ++ ++ /* Here map all the queues to ring. */ ++ for (q_id = EDMA_RX_QUEUE_START; ++ q_id <= EDMA_CPU_PORT_QUEUE_MAX(EDMA_RX_QUEUE_START); ++ q_id += EDMA_QID2RID_NUM_PER_REG) { ++ reg_index = q_id / EDMA_QID2RID_NUM_PER_REG; ++ ring_index = desc_index + EDMA_QUEUE_OFFSET(q_id); ++ ++ data = FIELD_PREP(EDMA_RX_RING_ID_QUEUE0_MASK, ring_index); ++ data |= FIELD_PREP(EDMA_RX_RING_ID_QUEUE1_MASK, ring_index); ++ data |= FIELD_PREP(EDMA_RX_RING_ID_QUEUE2_MASK, ring_index); ++ data |= FIELD_PREP(EDMA_RX_RING_ID_QUEUE3_MASK, ring_index); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_QID2RID_TABLE_MEM(reg_index); ++ regmap_write(regmap, reg, data); ++ pr_debug("Configure QID2RID: %d reg:0x%x to 0x%x, desc_index: %d, reg_index: %d\n", ++ q_id, EDMA_QID2RID_TABLE_MEM(reg_index), data, desc_index, reg_index); ++ } ++ ++ ret = ppe_edma_queue_resource_get(edma_ctx->ppe_dev, PPE_RES_MCAST, ++ &mcast_start, &mcast_end); ++ if (ret < 0) { ++ pr_err("Error in extracting multicast queue values\n"); ++ return; ++ } ++ ++ /* Map multicast queues to the first Rx ring. */ ++ desc_index = (rx->ring_start & EDMA_RX_RING_ID_MASK); ++ for (q_id = mcast_start; q_id <= mcast_end; ++ q_id += EDMA_QID2RID_NUM_PER_REG) { ++ reg_index = q_id / EDMA_QID2RID_NUM_PER_REG; ++ ++ data = FIELD_PREP(EDMA_RX_RING_ID_QUEUE0_MASK, desc_index); ++ data |= FIELD_PREP(EDMA_RX_RING_ID_QUEUE1_MASK, desc_index); ++ data |= FIELD_PREP(EDMA_RX_RING_ID_QUEUE2_MASK, desc_index); ++ data |= FIELD_PREP(EDMA_RX_RING_ID_QUEUE3_MASK, desc_index); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_QID2RID_TABLE_MEM(reg_index); ++ regmap_write(regmap, reg, data); ++ ++ pr_debug("Configure QID2RID: %d reg:0x%x to 0x%x\n", ++ q_id, EDMA_QID2RID_TABLE_MEM(reg_index), data); ++ } ++} ++ ++static void edma_cfg_rx_rings_to_rx_fill_mapping(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i, data, reg; ++ ++ regmap_write(regmap, EDMA_BASE_OFFSET + EDMA_REG_RXDESC2FILL_MAP_0_ADDR, 0); ++ regmap_write(regmap, EDMA_BASE_OFFSET + EDMA_REG_RXDESC2FILL_MAP_1_ADDR, 0); ++ regmap_write(regmap, EDMA_BASE_OFFSET + EDMA_REG_RXDESC2FILL_MAP_2_ADDR, 0); ++ ++ for (i = 0; i < rx->num_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring = &edma_ctx->rx_rings[i]; ++ u32 data, reg, ring_id; ++ ++ ring_id = rxdesc_ring->ring_id; ++ if (ring_id >= 0 && ring_id <= 9) ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC2FILL_MAP_0_ADDR; ++ else if (ring_id >= 10 && ring_id <= 19) ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC2FILL_MAP_1_ADDR; ++ else ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC2FILL_MAP_2_ADDR; ++ ++ pr_debug("Configure RXDESC:%u to use RXFILL:%u\n", ++ ring_id, ++ rxdesc_ring->rxfill->ring_id); ++ ++ /* Set the Rx fill ring number in the mapping register. */ ++ regmap_read(regmap, reg, &data); ++ data |= (rxdesc_ring->rxfill->ring_id & ++ EDMA_RXDESC2FILL_MAP_RXDESC_MASK) << ++ ((ring_id % 10) * 3); ++ regmap_write(regmap, reg, data); ++ } ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC2FILL_MAP_0_ADDR; ++ regmap_read(regmap, reg, &data); ++ pr_debug("EDMA_REG_RXDESC2FILL_MAP_0_ADDR: 0x%x\n", data); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC2FILL_MAP_1_ADDR; ++ regmap_read(regmap, reg, &data); ++ pr_debug("EDMA_REG_RXDESC2FILL_MAP_1_ADDR: 0x%x\n", data); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC2FILL_MAP_2_ADDR; ++ regmap_read(regmap, reg, &data); ++ pr_debug("EDMA_REG_RXDESC2FILL_MAP_2_ADDR: 0x%x\n", data); ++} ++ ++/** ++ * edma_cfg_rx_rings_enable - Enable Rx and Rxfill rings ++ * ++ * Enable Rx and Rxfill rings. ++ */ ++void edma_cfg_rx_rings_enable(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rxfill = hw_info->rxfill; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i, reg; ++ ++ /* Enable Rx rings */ ++ for (i = rx->ring_start; i < rx->ring_start + rx->num_rings; i++) { ++ u32 data; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_CTRL(i); ++ regmap_read(regmap, reg, &data); ++ data |= EDMA_RXDESC_RX_EN; ++ regmap_write(regmap, reg, data); ++ } ++ ++ for (i = rxfill->ring_start; i < rxfill->ring_start + rxfill->num_rings; i++) { ++ u32 data; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXFILL_RING_EN(i); ++ regmap_read(regmap, reg, &data); ++ data |= EDMA_RXFILL_RING_EN; ++ regmap_write(regmap, reg, data); ++ } ++} ++ ++/** ++ * edma_cfg_rx_rings_disable - Disable Rx and Rxfill rings ++ * ++ * Disable Rx and Rxfill rings. ++ */ ++void edma_cfg_rx_rings_disable(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rxfill = hw_info->rxfill; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i, reg; ++ ++ /* Disable Rx rings */ ++ for (i = 0; i < rx->num_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring = NULL; ++ u32 data; ++ ++ rxdesc_ring = &edma_ctx->rx_rings[i]; ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_CTRL(rxdesc_ring->ring_id); ++ regmap_read(regmap, reg, &data); ++ data &= ~EDMA_RXDESC_RX_EN; ++ regmap_write(regmap, reg, data); ++ } ++ ++ /* Disable RxFill Rings */ ++ for (i = 0; i < rxfill->num_rings; i++) { ++ struct edma_rxfill_ring *rxfill_ring = NULL; ++ u32 data; ++ ++ rxfill_ring = &edma_ctx->rxfill_rings[i]; ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXFILL_RING_EN(rxfill_ring->ring_id); ++ regmap_read(regmap, reg, &data); ++ data &= ~EDMA_RXFILL_RING_EN; ++ regmap_write(regmap, reg, data); ++ } ++} ++ ++/** ++ * edma_cfg_rx_mappings - Setup RX ring mapping ++ * ++ * Setup queue ID to Rx desc ring mapping. ++ */ ++void edma_cfg_rx_ring_mappings(void) ++{ ++ edma_cfg_rx_qid_to_rx_desc_ring_mapping(); ++ edma_cfg_rx_rings_to_rx_fill_mapping(); ++} ++ ++static void edma_cfg_rx_fill_ring_cleanup(struct edma_rxfill_ring *rxfill_ring) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct device *dev = ppe_dev->dev; ++ u16 cons_idx, curr_idx; ++ u32 data, reg; ++ ++ /* Get RxFill ring producer index */ ++ curr_idx = rxfill_ring->prod_idx & EDMA_RXFILL_PROD_IDX_MASK; ++ ++ /* Get RxFill ring consumer index */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXFILL_CONS_IDX(rxfill_ring->ring_id); ++ regmap_read(regmap, reg, &data); ++ cons_idx = data & EDMA_RXFILL_CONS_IDX_MASK; ++ ++ while (curr_idx != cons_idx) { ++ struct edma_rxfill_desc *rxfill_desc; ++ struct sk_buff *skb; ++ ++ /* Get RxFill descriptor */ ++ rxfill_desc = EDMA_RXFILL_DESC(rxfill_ring, cons_idx); ++ ++ cons_idx = (cons_idx + 1) & EDMA_RX_RING_SIZE_MASK; ++ ++ /* Get skb from opaque */ ++ skb = (struct sk_buff *)EDMA_RXFILL_OPAQUE_GET(rxfill_desc); ++ if (unlikely(!skb)) { ++ pr_err("Empty skb reference at index:%d\n", ++ cons_idx); ++ continue; ++ } ++ ++ dev_kfree_skb_any(skb); ++ } ++ ++ /* Free RxFill ring descriptors */ ++ dma_free_coherent(dev, (sizeof(struct edma_rxfill_desc) ++ * rxfill_ring->count), ++ rxfill_ring->desc, rxfill_ring->dma); ++ rxfill_ring->desc = NULL; ++ rxfill_ring->dma = (dma_addr_t)0; ++} ++ ++static int edma_cfg_rx_fill_ring_dma_alloc(struct edma_rxfill_ring *rxfill_ring) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct device *dev = ppe_dev->dev; ++ ++ /* Allocate RxFill ring descriptors */ ++ rxfill_ring->desc = dma_alloc_coherent(dev, (sizeof(struct edma_rxfill_desc) ++ * rxfill_ring->count), ++ &rxfill_ring->dma, ++ GFP_KERNEL | __GFP_ZERO); ++ if (unlikely(!rxfill_ring->desc)) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++static int edma_cfg_rx_desc_ring_dma_alloc(struct edma_rxdesc_ring *rxdesc_ring) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct device *dev = ppe_dev->dev; ++ ++ rxdesc_ring->pdesc = dma_alloc_coherent(dev, (sizeof(struct edma_rxdesc_pri) ++ * rxdesc_ring->count), ++ &rxdesc_ring->pdma, GFP_KERNEL | __GFP_ZERO); ++ if (unlikely(!rxdesc_ring->pdesc)) ++ return -ENOMEM; ++ ++ rxdesc_ring->sdesc = dma_alloc_coherent(dev, (sizeof(struct edma_rxdesc_sec) ++ * rxdesc_ring->count), ++ &rxdesc_ring->sdma, GFP_KERNEL | __GFP_ZERO); ++ if (unlikely(!rxdesc_ring->sdesc)) { ++ dma_free_coherent(dev, (sizeof(struct edma_rxdesc_pri) ++ * rxdesc_ring->count), ++ rxdesc_ring->pdesc, ++ rxdesc_ring->pdma); ++ rxdesc_ring->pdesc = NULL; ++ rxdesc_ring->pdma = (dma_addr_t)0; ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static void edma_cfg_rx_desc_ring_cleanup(struct edma_rxdesc_ring *rxdesc_ring) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct device *dev = ppe_dev->dev; ++ u32 prod_idx, cons_idx, reg; ++ ++ /* Get Rxdesc consumer & producer indices */ ++ cons_idx = rxdesc_ring->cons_idx & EDMA_RXDESC_CONS_IDX_MASK; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_PROD_IDX(rxdesc_ring->ring_id); ++ regmap_read(regmap, reg, &prod_idx); ++ prod_idx = prod_idx & EDMA_RXDESC_PROD_IDX_MASK; ++ ++ /* Free any buffers assigned to any descriptors */ ++ while (cons_idx != prod_idx) { ++ struct edma_rxdesc_pri *rxdesc_pri = ++ EDMA_RXDESC_PRI_DESC(rxdesc_ring, cons_idx); ++ struct sk_buff *skb; ++ ++ /* Update consumer index */ ++ cons_idx = (cons_idx + 1) & EDMA_RX_RING_SIZE_MASK; ++ ++ /* Get opaque from Rxdesc */ ++ skb = (struct sk_buff *)EDMA_RXDESC_OPAQUE_GET(rxdesc_pri); ++ if (unlikely(!skb)) { ++ pr_warn("Empty skb reference at index:%d\n", ++ cons_idx); ++ continue; ++ } ++ ++ dev_kfree_skb_any(skb); ++ } ++ ++ /* Update the consumer index */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_CONS_IDX(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, cons_idx); ++ ++ /* Free Rxdesc ring descriptor */ ++ dma_free_coherent(dev, (sizeof(struct edma_rxdesc_pri) ++ * rxdesc_ring->count), rxdesc_ring->pdesc, ++ rxdesc_ring->pdma); ++ rxdesc_ring->pdesc = NULL; ++ rxdesc_ring->pdma = (dma_addr_t)0; ++ ++ /* Free any buffers assigned to any secondary ring descriptors */ ++ dma_free_coherent(dev, (sizeof(struct edma_rxdesc_sec) ++ * rxdesc_ring->count), rxdesc_ring->sdesc, ++ rxdesc_ring->sdma); ++ rxdesc_ring->sdesc = NULL; ++ rxdesc_ring->sdma = (dma_addr_t)0; ++} ++ ++static int edma_cfg_rx_rings_setup(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rxfill = hw_info->rxfill; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 ring_idx, alloc_size, buf_len; ++ ++ /* Set buffer allocation size */ ++ if (edma_ctx->rx_buf_size) { ++ alloc_size = edma_ctx->rx_buf_size + ++ EDMA_RX_SKB_HEADROOM + NET_IP_ALIGN; ++ buf_len = alloc_size - EDMA_RX_SKB_HEADROOM - NET_IP_ALIGN; ++ } else if (edma_ctx->rx_page_mode) { ++ alloc_size = EDMA_RX_PAGE_MODE_SKB_SIZE + ++ EDMA_RX_SKB_HEADROOM + NET_IP_ALIGN; ++ buf_len = PAGE_SIZE; ++ } else { ++ alloc_size = EDMA_RX_BUFFER_SIZE; ++ buf_len = alloc_size - EDMA_RX_SKB_HEADROOM - NET_IP_ALIGN; ++ } ++ ++ pr_debug("EDMA ctx:%p rx_ring alloc_size=%d, buf_len=%d\n", ++ edma_ctx, alloc_size, buf_len); ++ ++ /* Allocate Rx fill ring descriptors */ ++ for (ring_idx = 0; ring_idx < rxfill->num_rings; ring_idx++) { ++ u32 ret; ++ struct edma_rxfill_ring *rxfill_ring = NULL; ++ ++ rxfill_ring = &edma_ctx->rxfill_rings[ring_idx]; ++ rxfill_ring->count = EDMA_RX_RING_SIZE; ++ rxfill_ring->ring_id = rxfill->ring_start + ring_idx; ++ rxfill_ring->alloc_size = alloc_size; ++ rxfill_ring->buf_len = buf_len; ++ rxfill_ring->page_mode = edma_ctx->rx_page_mode; ++ ++ ret = edma_cfg_rx_fill_ring_dma_alloc(rxfill_ring); ++ if (ret) { ++ pr_err("Error in setting up %d rxfill ring. ret: %d", ++ rxfill_ring->ring_id, ret); ++ while (--ring_idx >= 0) ++ edma_cfg_rx_fill_ring_cleanup(&edma_ctx->rxfill_rings[ring_idx]); ++ ++ return -ENOMEM; ++ } ++ } ++ ++ /* Allocate RxDesc ring descriptors */ ++ for (ring_idx = 0; ring_idx < rx->num_rings; ring_idx++) { ++ u32 index, queue_id = EDMA_RX_QUEUE_START; ++ struct edma_rxdesc_ring *rxdesc_ring = NULL; ++ u32 ret; ++ ++ rxdesc_ring = &edma_ctx->rx_rings[ring_idx]; ++ rxdesc_ring->count = EDMA_RX_RING_SIZE; ++ rxdesc_ring->ring_id = rx->ring_start + ring_idx; ++ ++ if (queue_id > EDMA_CPU_PORT_QUEUE_MAX(EDMA_RX_QUEUE_START)) { ++ pr_err("Invalid queue_id: %d\n", queue_id); ++ while (--ring_idx >= 0) ++ edma_cfg_rx_desc_ring_cleanup(&edma_ctx->rx_rings[ring_idx]); ++ ++ goto rxdesc_mem_alloc_fail; ++ } ++ ++ /* Create a mapping between RX Desc ring and Rx fill ring. ++ * Number of fill rings are lesser than the descriptor rings ++ * Share the fill rings across descriptor rings. ++ */ ++ index = rxfill->ring_start + ++ (ring_idx % rxfill->num_rings); ++ rxdesc_ring->rxfill = &edma_ctx->rxfill_rings[index ++ - rxfill->ring_start]; ++ ++ ret = edma_cfg_rx_desc_ring_dma_alloc(rxdesc_ring); ++ if (ret) { ++ pr_err("Error in setting up %d rxdesc ring. ret: %d", ++ rxdesc_ring->ring_id, ret); ++ while (--ring_idx >= 0) ++ edma_cfg_rx_desc_ring_cleanup(&edma_ctx->rx_rings[ring_idx]); ++ ++ goto rxdesc_mem_alloc_fail; ++ } ++ } ++ ++ pr_debug("Rx descriptor count for Rx desc and Rx fill rings : %d\n", ++ EDMA_RX_RING_SIZE); ++ ++ return 0; ++ ++rxdesc_mem_alloc_fail: ++ for (ring_idx = 0; ring_idx < rxfill->num_rings; ring_idx++) ++ edma_cfg_rx_fill_ring_cleanup(&edma_ctx->rxfill_rings[ring_idx]); ++ ++ return -ENOMEM; ++} ++ ++/** ++ * edma_cfg_rx_buff_size_setup - Configure EDMA Rx jumbo buffer ++ * ++ * Configure EDMA Rx jumbo buffer ++ */ ++void edma_cfg_rx_buff_size_setup(void) ++{ ++ if (edma_ctx->rx_buf_size) { ++ edma_ctx->rx_page_mode = false; ++ pr_debug("Rx Jumbo mru is enabled: %d\n", edma_ctx->rx_buf_size); ++ } ++} ++ ++/** ++ * edma_cfg_rx_rings_alloc - Allocate EDMA Rx rings ++ * ++ * Allocate EDMA Rx rings. ++ * ++ * Return 0 on success, negative error code on failure. ++ */ ++int edma_cfg_rx_rings_alloc(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rxfill = hw_info->rxfill; ++ struct edma_ring_info *rx = hw_info->rx; ++ int ret; ++ ++ edma_ctx->rxfill_rings = kzalloc((sizeof(*edma_ctx->rxfill_rings) * ++ rxfill->num_rings), ++ GFP_KERNEL); ++ if (!edma_ctx->rxfill_rings) ++ return -ENOMEM; ++ ++ edma_ctx->rx_rings = kzalloc((sizeof(*edma_ctx->rx_rings) * ++ rx->num_rings), ++ GFP_KERNEL); ++ if (!edma_ctx->rx_rings) ++ goto rxdesc_ring_alloc_fail; ++ ++ pr_debug("RxDesc:%u rx (%u-%u) RxFill:%u (%u-%u)\n", ++ rx->num_rings, rx->ring_start, ++ (rx->ring_start + rx->num_rings - 1), ++ rxfill->num_rings, rxfill->ring_start, ++ (rxfill->ring_start + rxfill->num_rings - 1)); ++ ++ if (edma_cfg_rx_rings_setup()) { ++ pr_err("Error in setting up Rx rings\n"); ++ goto rx_rings_setup_fail; ++ } ++ ++ /* Reset Rx descriptor ring mapped queue's configurations */ ++ ret = edma_cfg_rx_desc_ring_reset_queue_config(); ++ if (ret) { ++ pr_err("Error in resetting the Rx descriptor rings configurations\n"); ++ edma_cfg_rx_rings_cleanup(); ++ return ret; ++ } ++ ++ return 0; ++ ++rx_rings_setup_fail: ++ kfree(edma_ctx->rx_rings); ++ edma_ctx->rx_rings = NULL; ++rxdesc_ring_alloc_fail: ++ kfree(edma_ctx->rxfill_rings); ++ edma_ctx->rxfill_rings = NULL; ++ ++ return -ENOMEM; ++} ++ ++/** ++ * edma_cfg_rx_rings_cleanup - Cleanup EDMA Rx rings ++ * ++ * Cleanup EDMA Rx rings ++ */ ++void edma_cfg_rx_rings_cleanup(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rxfill = hw_info->rxfill; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i; ++ ++ /* Free RxFill ring descriptors */ ++ for (i = 0; i < rxfill->num_rings; i++) ++ edma_cfg_rx_fill_ring_cleanup(&edma_ctx->rxfill_rings[i]); ++ ++ /* Free Rx completion ring descriptors */ ++ for (i = 0; i < rx->num_rings; i++) ++ edma_cfg_rx_desc_ring_cleanup(&edma_ctx->rx_rings[i]); ++ ++ kfree(edma_ctx->rxfill_rings); ++ kfree(edma_ctx->rx_rings); ++ edma_ctx->rxfill_rings = NULL; ++ edma_ctx->rx_rings = NULL; ++} ++ ++static void edma_cfg_rx_fill_ring_configure(struct edma_rxfill_ring *rxfill_ring) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 ring_sz, reg; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXFILL_BA(rxfill_ring->ring_id); ++ regmap_write(regmap, reg, (u32)(rxfill_ring->dma & EDMA_RING_DMA_MASK)); ++ ++ ring_sz = rxfill_ring->count & EDMA_RXFILL_RING_SIZE_MASK; ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXFILL_RING_SIZE(rxfill_ring->ring_id); ++ regmap_write(regmap, reg, ring_sz); ++ ++ edma_rx_alloc_buffer(rxfill_ring, rxfill_ring->count - 1); ++} ++ ++static void edma_cfg_rx_desc_ring_flow_control(u32 threshold_xoff, u32 threshold_xon) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 data, i, reg; ++ ++ data = (threshold_xoff & EDMA_RXDESC_FC_XOFF_THRE_MASK) << EDMA_RXDESC_FC_XOFF_THRE_SHIFT; ++ data |= ((threshold_xon & EDMA_RXDESC_FC_XON_THRE_MASK) << EDMA_RXDESC_FC_XON_THRE_SHIFT); ++ ++ for (i = 0; i < rx->num_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring; ++ ++ rxdesc_ring = &edma_ctx->rx_rings[i]; ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_FC_THRE(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, data); ++ } ++} ++ ++static void edma_cfg_rx_fill_ring_flow_control(int threshold_xoff, int threshold_xon) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rxfill = hw_info->rxfill; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 data, i, reg; ++ ++ data = (threshold_xoff & EDMA_RXFILL_FC_XOFF_THRE_MASK) << EDMA_RXFILL_FC_XOFF_THRE_SHIFT; ++ data |= ((threshold_xon & EDMA_RXFILL_FC_XON_THRE_MASK) << EDMA_RXFILL_FC_XON_THRE_SHIFT); ++ ++ for (i = 0; i < rxfill->num_rings; i++) { ++ struct edma_rxfill_ring *rxfill_ring; ++ ++ rxfill_ring = &edma_ctx->rxfill_rings[i]; ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXFILL_FC_THRE(rxfill_ring->ring_id); ++ regmap_write(regmap, reg, data); ++ } ++} ++ ++/** ++ * edma_cfg_rx_rings - Configure EDMA Rx rings. ++ * ++ * Configure EDMA Rx rings. ++ */ ++int edma_cfg_rx_rings(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rxfill = hw_info->rxfill; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i; ++ ++ for (i = 0; i < rxfill->num_rings; i++) ++ edma_cfg_rx_fill_ring_configure(&edma_ctx->rxfill_rings[i]); ++ ++ for (i = 0; i < rx->num_rings; i++) ++ edma_cfg_rx_desc_ring_configure(&edma_ctx->rx_rings[i]); ++ ++ /* Configure Rx flow control configurations */ ++ edma_cfg_rx_desc_ring_flow_control(EDMA_RX_FC_XOFF_DEF, EDMA_RX_FC_XON_DEF); ++ edma_cfg_rx_fill_ring_flow_control(EDMA_RX_FC_XOFF_DEF, EDMA_RX_FC_XON_DEF); ++ ++ return edma_cfg_rx_desc_ring_to_queue_mapping(); ++} ++ ++/** ++ * edma_cfg_rx_disable_interrupts - EDMA disable RX interrupts ++ * ++ * Disable RX interrupt masks ++ */ ++void edma_cfg_rx_disable_interrupts(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i, reg; ++ ++ for (i = 0; i < rx->num_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring = ++ &edma_ctx->rx_rings[i]; ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, EDMA_MASK_INT_CLEAR); ++ } ++} ++ ++/** ++ * edma_cfg_rx_enable_interrupts - EDMA enable RX interrupts ++ * ++ * Enable RX interrupt masks ++ */ ++void edma_cfg_rx_enable_interrupts(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i, reg; ++ ++ for (i = 0; i < rx->num_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring = ++ &edma_ctx->rx_rings[i]; ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, edma_ctx->intr_info.intr_mask_rx); ++ } ++} ++ ++/** ++ * edma_cfg_rx_napi_disable - Disable NAPI for Rx ++ * ++ * Disable NAPI for Rx ++ */ ++void edma_cfg_rx_napi_disable(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i; ++ ++ for (i = 0; i < rx->num_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring; ++ ++ rxdesc_ring = &edma_ctx->rx_rings[i]; ++ ++ if (!rxdesc_ring->napi_added) ++ continue; ++ ++ napi_disable(&rxdesc_ring->napi); ++ } ++} ++ ++/** ++ * edma_cfg_rx_napi_enable - Enable NAPI for Rx ++ * ++ * Enable NAPI for Rx ++ */ ++void edma_cfg_rx_napi_enable(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i; ++ ++ for (i = 0; i < rx->num_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring; ++ ++ rxdesc_ring = &edma_ctx->rx_rings[i]; ++ ++ if (!rxdesc_ring->napi_added) ++ continue; ++ ++ napi_enable(&rxdesc_ring->napi); ++ } ++} ++ ++/** ++ * edma_cfg_rx_napi_delete - Delete Rx NAPI ++ * ++ * Delete RX NAPI ++ */ ++void edma_cfg_rx_napi_delete(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i; ++ ++ for (i = 0; i < rx->num_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring; ++ ++ rxdesc_ring = &edma_ctx->rx_rings[i]; ++ ++ if (!rxdesc_ring->napi_added) ++ continue; ++ ++ netif_napi_del(&rxdesc_ring->napi); ++ rxdesc_ring->napi_added = false; ++ } ++} ++ ++/* Add Rx NAPI */ ++/** ++ * edma_cfg_rx_napi_add - Add Rx NAPI ++ * @netdev: Netdevice ++ * ++ * Add RX NAPI ++ */ ++void edma_cfg_rx_napi_add(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rx = hw_info->rx; ++ u32 i; ++ ++ for (i = 0; i < rx->num_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring = &edma_ctx->rx_rings[i]; ++ ++ netif_napi_add_weight(edma_ctx->dummy_dev, &rxdesc_ring->napi, ++ edma_rx_napi_poll, hw_info->napi_budget_rx); ++ rxdesc_ring->napi_added = true; ++ } ++ ++ netdev_dbg(edma_ctx->dummy_dev, "Rx NAPI budget: %d\n", hw_info->napi_budget_rx); ++} ++ ++/** ++ * edma_cfg_rx_rps_hash_map - Configure rx rps hash map. ++ * ++ * Initialize and configure RPS hash map for queues ++ */ ++int edma_cfg_rx_rps_hash_map(void) ++{ ++ cpumask_t edma_rps_cpumask = {{EDMA_RX_DEFAULT_BITMAP}}; ++ int map_len = 0, idx = 0, ret = 0; ++ u32 q_off = EDMA_RX_QUEUE_START; ++ u32 q_map[EDMA_MAX_CORE] = {0}; ++ u32 hash, cpu; ++ ++ /* Map all possible hash values to queues used by the EDMA Rx ++ * rings based on a bitmask, which represents the cores to be mapped. ++ * These queues are expected to be mapped to different Rx rings ++ * which are assigned to different cores using IRQ affinity configuration. ++ */ ++ for_each_cpu(cpu, &edma_rps_cpumask) { ++ q_map[map_len] = q_off + (cpu * EDMA_MAX_PRI_PER_CORE); ++ map_len++; ++ } ++ ++ for (hash = 0; hash < PPE_QUEUE_HASH_NUM; hash++) { ++ ret = ppe_edma_queue_offset_config(edma_ctx->ppe_dev, ++ PPE_QUEUE_CLASS_HASH, hash, q_map[idx]); ++ if (ret) ++ return ret; ++ ++ pr_debug("profile_id: %u, hash: %u, q_off: %u\n", ++ EDMA_CPU_PORT_PROFILE_ID, hash, q_map[idx]); ++ idx = (idx + 1) % map_len; ++ } ++ ++ return 0; ++} +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h +@@ -0,0 +1,48 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#ifndef __EDMA_CFG_RX__ ++#define __EDMA_CFG_RX__ ++ ++/* SKB payload size used in page mode */ ++#define EDMA_RX_PAGE_MODE_SKB_SIZE 256 ++ ++/* Rx flow control X-OFF default value */ ++#define EDMA_RX_FC_XOFF_DEF 32 ++ ++/* Rx flow control X-ON default value */ ++#define EDMA_RX_FC_XON_DEF 64 ++ ++/* Rx AC flow control original threshold */ ++#define EDMA_RX_AC_FC_THRE_ORIG 0x190 ++ ++/* Rx AC flow control default threshold */ ++#define EDMA_RX_AC_FC_THRES_DEF 0x104 ++/* Rx mitigation timer's default value in microseconds */ ++#define EDMA_RX_MITIGATION_TIMER_DEF 25 ++ ++/* Rx mitigation packet count's default value */ ++#define EDMA_RX_MITIGATION_PKT_CNT_DEF 16 ++ ++/* Default bitmap of cores for RPS to ARM cores */ ++#define EDMA_RX_DEFAULT_BITMAP ((1 << EDMA_MAX_CORE) - 1) ++ ++int edma_cfg_rx_rings(void); ++int edma_cfg_rx_rings_alloc(void); ++void edma_cfg_rx_ring_mappings(void); ++void edma_cfg_rx_rings_cleanup(void); ++void edma_cfg_rx_disable_interrupts(void); ++void edma_cfg_rx_enable_interrupts(void); ++void edma_cfg_rx_napi_disable(void); ++void edma_cfg_rx_napi_enable(void); ++void edma_cfg_rx_napi_delete(void); ++void edma_cfg_rx_napi_add(void); ++void edma_cfg_rx_mapping(void); ++void edma_cfg_rx_rings_enable(void); ++void edma_cfg_rx_rings_disable(void); ++void edma_cfg_rx_buff_size_setup(void); ++int edma_cfg_rx_rps_hash_map(void); ++int edma_cfg_rx_rps(struct ctl_table *table, int write, ++ void *buffer, size_t *lenp, loff_t *ppos); ++#endif +--- a/drivers/net/ethernet/qualcomm/ppe/edma_port.c ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_port.c +@@ -12,12 +12,39 @@ + #include + + #include "edma.h" ++#include "edma_cfg_rx.h" + #include "edma_port.h" + #include "ppe_regs.h" + + /* Number of netdev queues. */ + #define EDMA_NETDEV_QUEUE_NUM 4 + ++static int edma_port_stats_alloc(struct net_device *netdev) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ ++ if (!port_priv) ++ return -EINVAL; ++ ++ /* Allocate per-cpu stats memory. */ ++ port_priv->pcpu_stats.rx_stats = ++ netdev_alloc_pcpu_stats(struct edma_port_rx_stats); ++ if (!port_priv->pcpu_stats.rx_stats) { ++ netdev_err(netdev, "Per-cpu EDMA Rx stats alloc failed for %s\n", ++ netdev->name); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static void edma_port_stats_free(struct net_device *netdev) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ ++ free_percpu(port_priv->pcpu_stats.rx_stats); ++} ++ + static u16 __maybe_unused edma_port_select_queue(__maybe_unused struct net_device *netdev, + __maybe_unused struct sk_buff *skb, + __maybe_unused struct net_device *sb_dev) +@@ -172,6 +199,7 @@ void edma_port_destroy(struct ppe_port * + int port_id = port->port_id; + struct net_device *netdev = edma_ctx->netdev_arr[port_id - 1]; + ++ edma_port_stats_free(netdev); + unregister_netdev(netdev); + free_netdev(netdev); + ppe_port_phylink_destroy(port); +@@ -232,6 +260,13 @@ int edma_port_setup(struct ppe_port *por + port_id, netdev->dev_addr); + } + ++ /* Allocate memory for EDMA port statistics. */ ++ ret = edma_port_stats_alloc(netdev); ++ if (ret) { ++ netdev_dbg(netdev, "EDMA port stats alloc failed\n"); ++ goto stats_alloc_fail; ++ } ++ + netdev_dbg(netdev, "Configuring the port %s(qcom-id:%d)\n", + netdev->name, port_id); + +@@ -263,8 +298,10 @@ int edma_port_setup(struct ppe_port *por + register_netdev_fail: + ppe_port_phylink_destroy(port); + port_phylink_setup_fail: +- free_netdev(netdev); + edma_ctx->netdev_arr[port_id - 1] = NULL; ++ edma_port_stats_free(netdev); ++stats_alloc_fail: ++ free_netdev(netdev); + + return ret; + } +--- a/drivers/net/ethernet/qualcomm/ppe/edma_port.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_port.h +@@ -15,14 +15,45 @@ + | NETIF_F_TSO6) + + /** ++ * struct edma_port_rx_stats - EDMA RX per CPU stats for the port. ++ * @rx_pkts: Number of Rx packets ++ * @rx_bytes: Number of Rx bytes ++ * @rx_drops: Number of Rx drops ++ * @rx_nr_frag_pkts: Number of Rx nr_frags packets ++ * @rx_fraglist_pkts: Number of Rx fraglist packets ++ * @rx_nr_frag_headroom_err: nr_frags headroom error packets ++ * @syncp: Synchronization pointer ++ */ ++struct edma_port_rx_stats { ++ u64 rx_pkts; ++ u64 rx_bytes; ++ u64 rx_drops; ++ u64 rx_nr_frag_pkts; ++ u64 rx_fraglist_pkts; ++ u64 rx_nr_frag_headroom_err; ++ struct u64_stats_sync syncp; ++}; ++ ++/** ++ * struct edma_port_pcpu_stats - EDMA per cpu stats data structure for the port. ++ * @rx_stats: Per CPU Rx statistics ++ */ ++struct edma_port_pcpu_stats { ++ struct edma_port_rx_stats __percpu *rx_stats; ++}; ++ ++/** + * struct edma_port_priv - EDMA port priv structure. + * @ppe_port: Pointer to PPE port + * @netdev: Corresponding netdevice ++ * @pcpu_stats: Per CPU netdev statistics ++ * @txr_map: Tx ring per-core mapping + * @flags: Feature flags + */ + struct edma_port_priv { + struct ppe_port *ppe_port; + struct net_device *netdev; ++ struct edma_port_pcpu_stats pcpu_stats; + unsigned long flags; + }; + +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_rx.c +@@ -0,0 +1,622 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* Provides APIs to alloc Rx Buffers, reap the buffers, receive and ++ * process linear and Scatter Gather packets. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "edma.h" ++#include "edma_cfg_rx.h" ++#include "edma_port.h" ++#include "ppe.h" ++#include "ppe_regs.h" ++ ++static int edma_rx_alloc_buffer_list(struct edma_rxfill_ring *rxfill_ring, int alloc_count) ++{ ++ struct edma_rxfill_stats *rxfill_stats = &rxfill_ring->rxfill_stats; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ u32 rx_alloc_size = rxfill_ring->alloc_size; ++ struct regmap *regmap = ppe_dev->regmap; ++ bool page_mode = rxfill_ring->page_mode; ++ struct edma_rxfill_desc *rxfill_desc; ++ u32 buf_len = rxfill_ring->buf_len; ++ struct device *dev = ppe_dev->dev; ++ u16 prod_idx, start_idx; ++ u16 num_alloc = 0; ++ u32 reg; ++ ++ prod_idx = rxfill_ring->prod_idx; ++ start_idx = prod_idx; ++ ++ while (likely(alloc_count--)) { ++ dma_addr_t buff_addr; ++ struct sk_buff *skb; ++ struct page *pg; ++ ++ rxfill_desc = EDMA_RXFILL_DESC(rxfill_ring, prod_idx); ++ ++ skb = dev_alloc_skb(rx_alloc_size); ++ if (unlikely(!skb)) { ++ u64_stats_update_begin(&rxfill_stats->syncp); ++ ++rxfill_stats->alloc_failed; ++ u64_stats_update_end(&rxfill_stats->syncp); ++ break; ++ } ++ ++ skb_reserve(skb, EDMA_RX_SKB_HEADROOM + NET_IP_ALIGN); ++ ++ if (likely(!page_mode)) { ++ buff_addr = dma_map_single(dev, skb->data, rx_alloc_size, DMA_FROM_DEVICE); ++ if (dma_mapping_error(dev, buff_addr)) { ++ dev_dbg(dev, "edma_context:%p Unable to dma for non page mode", ++ edma_ctx); ++ dev_kfree_skb_any(skb); ++ break; ++ } ++ } else { ++ pg = alloc_page(GFP_ATOMIC); ++ if (unlikely(!pg)) { ++ u64_stats_update_begin(&rxfill_stats->syncp); ++ ++rxfill_stats->page_alloc_failed; ++ u64_stats_update_end(&rxfill_stats->syncp); ++ dev_kfree_skb_any(skb); ++ dev_dbg(dev, "edma_context:%p Unable to allocate page", ++ edma_ctx); ++ break; ++ } ++ ++ buff_addr = dma_map_page(dev, pg, 0, PAGE_SIZE, DMA_FROM_DEVICE); ++ if (dma_mapping_error(dev, buff_addr)) { ++ dev_dbg(dev, "edma_context:%p Mapping error for page mode", ++ edma_ctx); ++ __free_page(pg); ++ dev_kfree_skb_any(skb); ++ break; ++ } ++ ++ skb_fill_page_desc(skb, 0, pg, 0, PAGE_SIZE); ++ } ++ ++ EDMA_RXFILL_BUFFER_ADDR_SET(rxfill_desc, buff_addr); ++ ++ EDMA_RXFILL_OPAQUE_LO_SET(rxfill_desc, skb); ++#ifdef __LP64__ ++ EDMA_RXFILL_OPAQUE_HI_SET(rxfill_desc, skb); ++#endif ++ EDMA_RXFILL_PACKET_LEN_SET(rxfill_desc, ++ (u32)(buf_len) & EDMA_RXFILL_BUF_SIZE_MASK); ++ prod_idx = (prod_idx + 1) & EDMA_RX_RING_SIZE_MASK; ++ num_alloc++; ++ } ++ ++ if (likely(num_alloc)) { ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXFILL_PROD_IDX(rxfill_ring->ring_id); ++ regmap_write(regmap, reg, prod_idx); ++ rxfill_ring->prod_idx = prod_idx; ++ } ++ ++ return num_alloc; ++} ++ ++/** ++ * edma_rx_alloc_buffer - EDMA Rx alloc buffer. ++ * @rxfill_ring: EDMA Rxfill ring ++ * @alloc_count: Number of rings to alloc ++ * ++ * Alloc Rx buffers for RxFill ring. ++ * ++ * Return the number of rings allocated. ++ */ ++int edma_rx_alloc_buffer(struct edma_rxfill_ring *rxfill_ring, int alloc_count) ++{ ++ return edma_rx_alloc_buffer_list(rxfill_ring, alloc_count); ++} ++ ++/* Mark ip_summed appropriately in the skb as per the L3/L4 checksum ++ * status in descriptor. ++ */ ++static void edma_rx_checksum_verify(struct edma_rxdesc_pri *rxdesc_pri, ++ struct sk_buff *skb) ++{ ++ u8 pid = EDMA_RXDESC_PID_GET(rxdesc_pri); ++ ++ skb_checksum_none_assert(skb); ++ ++ if (likely(EDMA_RX_PID_IS_IPV4(pid))) { ++ if (likely(EDMA_RXDESC_L3CSUM_STATUS_GET(rxdesc_pri)) && ++ likely(EDMA_RXDESC_L4CSUM_STATUS_GET(rxdesc_pri))) ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } else if (likely(EDMA_RX_PID_IS_IPV6(pid))) { ++ if (likely(EDMA_RXDESC_L4CSUM_STATUS_GET(rxdesc_pri))) ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } ++} ++ ++static void edma_rx_process_last_segment(struct edma_rxdesc_ring *rxdesc_ring, ++ struct edma_rxdesc_pri *rxdesc_pri, ++ struct sk_buff *skb) ++{ ++ bool page_mode = rxdesc_ring->rxfill->page_mode; ++ struct edma_port_pcpu_stats *pcpu_stats; ++ struct edma_port_rx_stats *rx_stats; ++ struct edma_port_priv *port_dev; ++ struct sk_buff *skb_head; ++ struct net_device *dev; ++ u32 pkt_length; ++ ++ /* Get packet length. */ ++ pkt_length = EDMA_RXDESC_PACKET_LEN_GET(rxdesc_pri); ++ ++ skb_head = rxdesc_ring->head; ++ dev = skb_head->dev; ++ ++ /* Check Rx checksum offload status. */ ++ if (likely(dev->features & NETIF_F_RXCSUM)) ++ edma_rx_checksum_verify(rxdesc_pri, skb_head); ++ ++ /* Get stats for the netdevice. */ ++ port_dev = netdev_priv(dev); ++ pcpu_stats = &port_dev->pcpu_stats; ++ rx_stats = this_cpu_ptr(pcpu_stats->rx_stats); ++ ++ if (unlikely(page_mode)) { ++ if (unlikely(!pskb_may_pull(skb_head, ETH_HLEN))) { ++ /* Discard the SKB that we have been building, ++ * in addition to the SKB linked to current descriptor. ++ */ ++ dev_kfree_skb_any(skb_head); ++ rxdesc_ring->head = NULL; ++ rxdesc_ring->last = NULL; ++ rxdesc_ring->pdesc_head = NULL; ++ ++ u64_stats_update_begin(&rx_stats->syncp); ++ rx_stats->rx_nr_frag_headroom_err++; ++ u64_stats_update_end(&rx_stats->syncp); ++ ++ return; ++ } ++ } ++ ++ if (unlikely(!pskb_pull(skb_head, EDMA_RXDESC_DATA_OFFSET_GET(rxdesc_ring->pdesc_head)))) { ++ dev_kfree_skb_any(skb_head); ++ rxdesc_ring->head = NULL; ++ rxdesc_ring->last = NULL; ++ rxdesc_ring->pdesc_head = NULL; ++ ++ u64_stats_update_begin(&rx_stats->syncp); ++ rx_stats->rx_nr_frag_headroom_err++; ++ u64_stats_update_end(&rx_stats->syncp); ++ ++ return; ++ } ++ ++ u64_stats_update_begin(&rx_stats->syncp); ++ rx_stats->rx_pkts++; ++ rx_stats->rx_bytes += skb_head->len; ++ rx_stats->rx_nr_frag_pkts += (u64)page_mode; ++ rx_stats->rx_fraglist_pkts += (u64)(!page_mode); ++ u64_stats_update_end(&rx_stats->syncp); ++ ++ pr_debug("edma_context:%p skb:%p Jumbo pkt_length:%u\n", ++ edma_ctx, skb_head, skb_head->len); ++ ++ skb_head->protocol = eth_type_trans(skb_head, dev); ++ ++ /* Send packet up the stack. */ ++ if (dev->features & NETIF_F_GRO) ++ napi_gro_receive(&rxdesc_ring->napi, skb_head); ++ else ++ netif_receive_skb(skb_head); ++ ++ rxdesc_ring->head = NULL; ++ rxdesc_ring->last = NULL; ++ rxdesc_ring->pdesc_head = NULL; ++} ++ ++static void edma_rx_handle_frag_list(struct edma_rxdesc_ring *rxdesc_ring, ++ struct edma_rxdesc_pri *rxdesc_pri, ++ struct sk_buff *skb) ++{ ++ u32 pkt_length; ++ ++ /* Get packet length. */ ++ pkt_length = EDMA_RXDESC_PACKET_LEN_GET(rxdesc_pri); ++ pr_debug("edma_context:%p skb:%p fragment pkt_length:%u\n", ++ edma_ctx, skb, pkt_length); ++ ++ if (!(rxdesc_ring->head)) { ++ skb_put(skb, pkt_length); ++ rxdesc_ring->head = skb; ++ rxdesc_ring->last = NULL; ++ rxdesc_ring->pdesc_head = rxdesc_pri; ++ ++ return; ++ } ++ ++ /* Append it to the fraglist of head if this is second frame ++ * If not second frame append to tail. ++ */ ++ skb_put(skb, pkt_length); ++ if (!skb_has_frag_list(rxdesc_ring->head)) ++ skb_shinfo(rxdesc_ring->head)->frag_list = skb; ++ else ++ rxdesc_ring->last->next = skb; ++ ++ rxdesc_ring->last = skb; ++ rxdesc_ring->last->next = NULL; ++ rxdesc_ring->head->len += pkt_length; ++ rxdesc_ring->head->data_len += pkt_length; ++ rxdesc_ring->head->truesize += skb->truesize; ++ ++ /* If there are more segments for this packet, ++ * then we have nothing to do. Otherwise process ++ * last segment and send packet to stack. ++ */ ++ if (EDMA_RXDESC_MORE_BIT_GET(rxdesc_pri)) ++ return; ++ ++ edma_rx_process_last_segment(rxdesc_ring, rxdesc_pri, skb); ++} ++ ++static void edma_rx_handle_nr_frags(struct edma_rxdesc_ring *rxdesc_ring, ++ struct edma_rxdesc_pri *rxdesc_pri, ++ struct sk_buff *skb) ++{ ++ skb_frag_t *frag = NULL; ++ u32 pkt_length; ++ ++ /* Get packet length. */ ++ pkt_length = EDMA_RXDESC_PACKET_LEN_GET(rxdesc_pri); ++ pr_debug("edma_context:%p skb:%p fragment pkt_length:%u\n", ++ edma_ctx, skb, pkt_length); ++ ++ if (!(rxdesc_ring->head)) { ++ skb->len = pkt_length; ++ skb->data_len = pkt_length; ++ skb->truesize = SKB_TRUESIZE(PAGE_SIZE); ++ rxdesc_ring->head = skb; ++ rxdesc_ring->last = NULL; ++ rxdesc_ring->pdesc_head = rxdesc_pri; ++ ++ return; ++ } ++ ++ frag = &skb_shinfo(skb)->frags[0]; ++ ++ /* Append current frag at correct index as nr_frag of parent. */ ++ skb_add_rx_frag(rxdesc_ring->head, skb_shinfo(rxdesc_ring->head)->nr_frags, ++ skb_frag_page(frag), 0, pkt_length, PAGE_SIZE); ++ skb_shinfo(skb)->nr_frags = 0; ++ ++ /* Free the SKB after we have appended its frag page to the head skb. */ ++ dev_kfree_skb_any(skb); ++ ++ /* If there are more segments for this packet, ++ * then we have nothing to do. Otherwise process ++ * last segment and send packet to stack. ++ */ ++ if (EDMA_RXDESC_MORE_BIT_GET(rxdesc_pri)) ++ return; ++ ++ edma_rx_process_last_segment(rxdesc_ring, rxdesc_pri, skb); ++} ++ ++static bool edma_rx_handle_linear_packets(struct edma_rxdesc_ring *rxdesc_ring, ++ struct edma_rxdesc_pri *rxdesc_pri, ++ struct sk_buff *skb) ++{ ++ bool page_mode = rxdesc_ring->rxfill->page_mode; ++ struct edma_port_pcpu_stats *pcpu_stats; ++ struct edma_port_rx_stats *rx_stats; ++ struct edma_port_priv *port_dev; ++ skb_frag_t *frag = NULL; ++ u32 pkt_length; ++ ++ /* Get stats for the netdevice. */ ++ port_dev = netdev_priv(skb->dev); ++ pcpu_stats = &port_dev->pcpu_stats; ++ rx_stats = this_cpu_ptr(pcpu_stats->rx_stats); ++ ++ /* Get packet length. */ ++ pkt_length = EDMA_RXDESC_PACKET_LEN_GET(rxdesc_pri); ++ ++ if (likely(!page_mode)) { ++ skb_put(skb, pkt_length); ++ goto send_to_stack; ++ } ++ ++ /* Handle linear packet in page mode. */ ++ frag = &skb_shinfo(skb)->frags[0]; ++ skb_add_rx_frag(skb, 0, skb_frag_page(frag), 0, pkt_length, PAGE_SIZE); ++ ++ /* Pull ethernet header into SKB data area for header processing. */ ++ if (unlikely(!pskb_may_pull(skb, ETH_HLEN))) { ++ u64_stats_update_begin(&rx_stats->syncp); ++ rx_stats->rx_nr_frag_headroom_err++; ++ u64_stats_update_end(&rx_stats->syncp); ++ dev_kfree_skb_any(skb); ++ ++ return false; ++ } ++ ++send_to_stack: ++ ++ __skb_pull(skb, EDMA_RXDESC_DATA_OFFSET_GET(rxdesc_pri)); ++ ++ /* Check Rx checksum offload status. */ ++ if (likely(skb->dev->features & NETIF_F_RXCSUM)) ++ edma_rx_checksum_verify(rxdesc_pri, skb); ++ ++ u64_stats_update_begin(&rx_stats->syncp); ++ rx_stats->rx_pkts++; ++ rx_stats->rx_bytes += pkt_length; ++ rx_stats->rx_nr_frag_pkts += (u64)page_mode; ++ u64_stats_update_end(&rx_stats->syncp); ++ ++ skb->protocol = eth_type_trans(skb, skb->dev); ++ if (skb->dev->features & NETIF_F_GRO) ++ napi_gro_receive(&rxdesc_ring->napi, skb); ++ else ++ netif_receive_skb(skb); ++ ++ netdev_dbg(skb->dev, "edma_context:%p, skb:%p pkt_length:%u\n", ++ edma_ctx, skb, skb->len); ++ ++ return true; ++} ++ ++static struct net_device *edma_rx_get_src_dev(struct edma_rxdesc_stats *rxdesc_stats, ++ struct edma_rxdesc_pri *rxdesc_pri, ++ struct sk_buff *skb) ++{ ++ u32 src_info = EDMA_RXDESC_SRC_INFO_GET(rxdesc_pri); ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct net_device *ndev = NULL; ++ u8 src_port_num; ++ ++ /* Check src_info. */ ++ if (likely((src_info & EDMA_RXDESC_SRCINFO_TYPE_MASK) ++ == EDMA_RXDESC_SRCINFO_TYPE_PORTID)) { ++ src_port_num = src_info & EDMA_RXDESC_PORTNUM_BITS; ++ } else { ++ if (net_ratelimit()) { ++ pr_warn("Invalid src info_type:0x%x. Drop skb:%p\n", ++ (src_info & EDMA_RXDESC_SRCINFO_TYPE_MASK), skb); ++ } ++ ++ u64_stats_update_begin(&rxdesc_stats->syncp); ++ ++rxdesc_stats->src_port_inval_type; ++ u64_stats_update_end(&rxdesc_stats->syncp); ++ ++ return NULL; ++ } ++ ++ /* Packet with PP source. */ ++ if (likely(src_port_num <= hw_info->max_ports)) { ++ if (unlikely(src_port_num < EDMA_START_IFNUM)) { ++ if (net_ratelimit()) ++ pr_warn("Port number error :%d. Drop skb:%p\n", ++ src_port_num, skb); ++ ++ u64_stats_update_begin(&rxdesc_stats->syncp); ++ ++rxdesc_stats->src_port_inval; ++ u64_stats_update_end(&rxdesc_stats->syncp); ++ ++ return NULL; ++ } ++ ++ /* Get netdev for this port using the source port ++ * number as index into the netdev array. We need to ++ * subtract one since the indices start form '0' and ++ * port numbers start from '1'. ++ */ ++ ndev = edma_ctx->netdev_arr[src_port_num - 1]; ++ } ++ ++ if (likely(ndev)) ++ return ndev; ++ ++ if (net_ratelimit()) ++ pr_warn("Netdev Null src_info_type:0x%x src port num:%d Drop skb:%p\n", ++ (src_info & EDMA_RXDESC_SRCINFO_TYPE_MASK), ++ src_port_num, skb); ++ ++ u64_stats_update_begin(&rxdesc_stats->syncp); ++ ++rxdesc_stats->src_port_inval_netdev; ++ u64_stats_update_end(&rxdesc_stats->syncp); ++ ++ return NULL; ++} ++ ++static int edma_rx_reap(struct edma_rxdesc_ring *rxdesc_ring, int budget) ++{ ++ struct edma_rxdesc_stats *rxdesc_stats = &rxdesc_ring->rxdesc_stats; ++ u32 alloc_size = rxdesc_ring->rxfill->alloc_size; ++ bool page_mode = rxdesc_ring->rxfill->page_mode; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct edma_rxdesc_pri *next_rxdesc_pri; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct device *dev = ppe_dev->dev; ++ u32 prod_idx, cons_idx, end_idx; ++ u32 work_to_do, work_done = 0; ++ struct sk_buff *next_skb; ++ u32 work_leftover, reg; ++ ++ /* Get Rx ring producer and consumer indices. */ ++ cons_idx = rxdesc_ring->cons_idx; ++ ++ if (likely(rxdesc_ring->work_leftover > EDMA_RX_MAX_PROCESS)) { ++ work_to_do = rxdesc_ring->work_leftover; ++ } else { ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_PROD_IDX(rxdesc_ring->ring_id); ++ regmap_read(regmap, reg, &prod_idx); ++ prod_idx = prod_idx & EDMA_RXDESC_PROD_IDX_MASK; ++ work_to_do = EDMA_DESC_AVAIL_COUNT(prod_idx, ++ cons_idx, EDMA_RX_RING_SIZE); ++ rxdesc_ring->work_leftover = work_to_do; ++ } ++ ++ if (work_to_do > budget) ++ work_to_do = budget; ++ ++ rxdesc_ring->work_leftover -= work_to_do; ++ end_idx = (cons_idx + work_to_do) & EDMA_RX_RING_SIZE_MASK; ++ next_rxdesc_pri = EDMA_RXDESC_PRI_DESC(rxdesc_ring, cons_idx); ++ ++ /* Get opaque from RXDESC. */ ++ next_skb = (struct sk_buff *)EDMA_RXDESC_OPAQUE_GET(next_rxdesc_pri); ++ ++ work_leftover = work_to_do & (EDMA_RX_MAX_PROCESS - 1); ++ while (likely(work_to_do--)) { ++ struct edma_rxdesc_pri *rxdesc_pri; ++ struct net_device *ndev; ++ struct sk_buff *skb; ++ dma_addr_t dma_addr; ++ ++ skb = next_skb; ++ rxdesc_pri = next_rxdesc_pri; ++ dma_addr = EDMA_RXDESC_BUFFER_ADDR_GET(rxdesc_pri); ++ ++ if (!page_mode) ++ dma_unmap_single(dev, dma_addr, alloc_size, ++ DMA_TO_DEVICE); ++ else ++ dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_TO_DEVICE); ++ ++ /* Update consumer index. */ ++ cons_idx = (cons_idx + 1) & EDMA_RX_RING_SIZE_MASK; ++ ++ /* Get the next Rx descriptor. */ ++ next_rxdesc_pri = EDMA_RXDESC_PRI_DESC(rxdesc_ring, cons_idx); ++ ++ /* Handle linear packets or initial segments first. */ ++ if (likely(!(rxdesc_ring->head))) { ++ ndev = edma_rx_get_src_dev(rxdesc_stats, rxdesc_pri, skb); ++ if (unlikely(!ndev)) { ++ dev_kfree_skb_any(skb); ++ goto next_rx_desc; ++ } ++ ++ /* Update skb fields for head skb. */ ++ skb->dev = ndev; ++ skb->skb_iif = ndev->ifindex; ++ ++ /* Handle linear packets. */ ++ if (likely(!EDMA_RXDESC_MORE_BIT_GET(rxdesc_pri))) { ++ next_skb = ++ (struct sk_buff *)EDMA_RXDESC_OPAQUE_GET(next_rxdesc_pri); ++ ++ if (unlikely(! ++ edma_rx_handle_linear_packets(rxdesc_ring, ++ rxdesc_pri, skb))) ++ dev_kfree_skb_any(skb); ++ ++ goto next_rx_desc; ++ } ++ } ++ ++ next_skb = (struct sk_buff *)EDMA_RXDESC_OPAQUE_GET(next_rxdesc_pri); ++ ++ /* Handle scatter frame processing for first/middle/last segments. */ ++ page_mode ? edma_rx_handle_nr_frags(rxdesc_ring, rxdesc_pri, skb) : ++ edma_rx_handle_frag_list(rxdesc_ring, rxdesc_pri, skb); ++ ++next_rx_desc: ++ /* Update work done. */ ++ work_done++; ++ ++ /* Check if we can refill EDMA_RX_MAX_PROCESS worth buffers, ++ * if yes, refill and update index before continuing. ++ */ ++ if (unlikely(!(work_done & (EDMA_RX_MAX_PROCESS - 1)))) { ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_CONS_IDX(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, cons_idx); ++ rxdesc_ring->cons_idx = cons_idx; ++ edma_rx_alloc_buffer_list(rxdesc_ring->rxfill, EDMA_RX_MAX_PROCESS); ++ } ++ } ++ ++ /* Check if we need to refill and update ++ * index for any buffers before exit. ++ */ ++ if (unlikely(work_leftover)) { ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_CONS_IDX(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, cons_idx); ++ rxdesc_ring->cons_idx = cons_idx; ++ edma_rx_alloc_buffer_list(rxdesc_ring->rxfill, work_leftover); ++ } ++ ++ return work_done; ++} ++ ++/** ++ * edma_rx_napi_poll - EDMA Rx napi poll. ++ * @napi: NAPI structure ++ * @budget: Rx NAPI budget ++ * ++ * EDMA RX NAPI handler to handle the NAPI poll. ++ * ++ * Return the number of packets processed. ++ */ ++int edma_rx_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct edma_rxdesc_ring *rxdesc_ring = (struct edma_rxdesc_ring *)napi; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ int work_done = 0; ++ u32 status, reg; ++ ++ do { ++ work_done += edma_rx_reap(rxdesc_ring, budget - work_done); ++ if (likely(work_done >= budget)) ++ return work_done; ++ ++ /* Check if there are more packets to process. */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_INT_STAT(rxdesc_ring->ring_id); ++ regmap_read(regmap, reg, &status); ++ status = status & EDMA_RXDESC_RING_INT_STATUS_MASK; ++ } while (likely(status)); ++ ++ napi_complete(napi); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, edma_ctx->intr_info.intr_mask_rx); ++ ++ return work_done; ++} ++ ++/** ++ * edma_rx_handle_irq - EDMA Rx handle irq. ++ * @irq: Interrupt to handle ++ * @ctx: Context ++ * ++ * Process RX IRQ and schedule NAPI. ++ * ++ * Return IRQ_HANDLED(1) on success. ++ */ ++irqreturn_t edma_rx_handle_irq(int irq, void *ctx) ++{ ++ struct edma_rxdesc_ring *rxdesc_ring = (struct edma_rxdesc_ring *)ctx; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 reg; ++ ++ if (likely(napi_schedule_prep(&rxdesc_ring->napi))) { ++ /* Disable RxDesc interrupt. */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->ring_id); ++ regmap_write(regmap, reg, EDMA_MASK_INT_DISABLE); ++ __napi_schedule(&rxdesc_ring->napi); ++ } ++ ++ return IRQ_HANDLED; ++} +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_rx.h +@@ -0,0 +1,287 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#ifndef __EDMA_RX__ ++#define __EDMA_RX__ ++ ++#include ++ ++#define EDMA_RXFILL_RING_PER_CORE_MAX 1 ++#define EDMA_RXDESC_RING_PER_CORE_MAX 1 ++ ++/* Max Rx processing without replenishing RxFill ring. */ ++#define EDMA_RX_MAX_PROCESS 32 ++ ++#define EDMA_RX_SKB_HEADROOM 128 ++#define EDMA_RX_QUEUE_START 0 ++#define EDMA_RX_BUFFER_SIZE 1984 ++#define EDMA_MAX_CORE 4 ++ ++#define EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[(i)])) ++#define EDMA_GET_PDESC(R, i, type) (&(((type *)((R)->pdesc))[(i)])) ++#define EDMA_GET_SDESC(R, i, type) (&(((type *)((R)->sdesc))[(i)])) ++#define EDMA_RXFILL_DESC(R, i) EDMA_GET_DESC(R, i, \ ++ struct edma_rxfill_desc) ++#define EDMA_RXDESC_PRI_DESC(R, i) EDMA_GET_PDESC(R, i, \ ++ struct edma_rxdesc_pri) ++#define EDMA_RXDESC_SEC_DESC(R, i) EDMA_GET_SDESC(R, i, \ ++ struct edma_rxdesc_sec) ++ ++#define EDMA_RX_RING_SIZE 2048 ++ ++#define EDMA_RX_RING_SIZE_MASK (EDMA_RX_RING_SIZE - 1) ++#define EDMA_RX_RING_ID_MASK 0x1F ++ ++#define EDMA_MAX_PRI_PER_CORE 8 ++#define EDMA_RX_PID_IPV4_MAX 0x3 ++#define EDMA_RX_PID_IPV6 0x4 ++#define EDMA_RX_PID_IS_IPV4(pid) (!((pid) & (~EDMA_RX_PID_IPV4_MAX))) ++#define EDMA_RX_PID_IS_IPV6(pid) (!(!((pid) & EDMA_RX_PID_IPV6))) ++ ++#define EDMA_RXDESC_BUFFER_ADDR_GET(desc) \ ++ ((u32)(le32_to_cpu((__force __le32)((desc)->word0)))) ++#define EDMA_RXDESC_OPAQUE_GET(_desc) ({ \ ++ typeof(_desc) (desc) = (_desc); \ ++ ((uintptr_t)((u64)((desc)->word2) | \ ++ ((u64)((desc)->word3) << 0x20))); }) ++ ++#define EDMA_RXDESC_SRCINFO_TYPE_PORTID 0x2000 ++#define EDMA_RXDESC_SRCINFO_TYPE_MASK 0xF000 ++#define EDMA_RXDESC_L3CSUM_STATUS_MASK BIT(13) ++#define EDMA_RXDESC_L4CSUM_STATUS_MASK BIT(12) ++#define EDMA_RXDESC_PORTNUM_BITS 0x0FFF ++ ++#define EDMA_RXDESC_PACKET_LEN_MASK 0x3FFFF ++#define EDMA_RXDESC_PACKET_LEN_GET(_desc) ({ \ ++ typeof(_desc) (desc) = (_desc); \ ++ ((le32_to_cpu((__force __le32)((desc)->word5))) & \ ++ EDMA_RXDESC_PACKET_LEN_MASK); }) ++ ++#define EDMA_RXDESC_MORE_BIT_MASK 0x40000000 ++#define EDMA_RXDESC_MORE_BIT_GET(desc) ((le32_to_cpu((__force __le32)((desc)->word1))) & \ ++ EDMA_RXDESC_MORE_BIT_MASK) ++#define EDMA_RXDESC_SRC_DST_INFO_GET(desc) \ ++ ((u32)((le32_to_cpu((__force __le32)((desc)->word4))))) ++ ++#define EDMA_RXDESC_L3_OFFSET_MASK GENMASK(23, 16) ++#define EDMA_RXDESC_L3_OFFSET_GET(desc) FIELD_GET(EDMA_RXDESC_L3_OFFSET_MASK, \ ++ le32_to_cpu((__force __le32)((desc)->word7))) ++ ++#define EDMA_RXDESC_PID_MASK GENMASK(15, 12) ++#define EDMA_RXDESC_PID_GET(desc) FIELD_GET(EDMA_RXDESC_PID_MASK, \ ++ le32_to_cpu((__force __le32)((desc)->word7))) ++ ++#define EDMA_RXDESC_DST_INFO_MASK GENMASK(31, 16) ++#define EDMA_RXDESC_DST_INFO_GET(desc) FIELD_GET(EDMA_RXDESC_DST_INFO_MASK, \ ++ le32_to_cpu((__force __le32)((desc)->word4))) ++ ++#define EDMA_RXDESC_SRC_INFO_MASK GENMASK(15, 0) ++#define EDMA_RXDESC_SRC_INFO_GET(desc) FIELD_GET(EDMA_RXDESC_SRC_INFO_MASK, \ ++ le32_to_cpu((__force __le32)((desc)->word4))) ++ ++#define EDMA_RXDESC_PORT_ID_MASK GENMASK(11, 0) ++#define EDMA_RXDESC_PORT_ID_GET(x) FIELD_GET(EDMA_RXDESC_PORT_ID_MASK, x) ++ ++#define EDMA_RXDESC_SRC_PORT_ID_GET(desc) (EDMA_RXDESC_PORT_ID_GET \ ++ (EDMA_RXDESC_SRC_INFO_GET(desc))) ++#define EDMA_RXDESC_DST_PORT_ID_GET(desc) (EDMA_RXDESC_PORT_ID_GET \ ++ (EDMA_RXDESC_DST_INFO_GET(desc))) ++ ++#define EDMA_RXDESC_DST_PORT (0x2 << EDMA_RXDESC_PID_SHIFT) ++ ++#define EDMA_RXDESC_L3CSUM_STATUS_GET(desc) FIELD_GET(EDMA_RXDESC_L3CSUM_STATUS_MASK, \ ++ le32_to_cpu((__force __le32)(desc)->word6)) ++#define EDMA_RXDESC_L4CSUM_STATUS_GET(desc) FIELD_GET(EDMA_RXDESC_L4CSUM_STATUS_MASK, \ ++ le32_to_cpu((__force __le32)(desc)->word6)) ++ ++#define EDMA_RXDESC_DATA_OFFSET_MASK GENMASK(11, 0) ++#define EDMA_RXDESC_DATA_OFFSET_GET(desc) FIELD_GET(EDMA_RXDESC_DATA_OFFSET_MASK, \ ++ le32_to_cpu((__force __le32)(desc)->word6)) ++ ++#define EDMA_RXFILL_BUF_SIZE_MASK 0xFFFF ++#define EDMA_RXFILL_BUF_SIZE_SHIFT 16 ++ ++/* Opaque values are not accessed by the EDMA HW, ++ * so endianness conversion is not needed. ++ */ ++ ++#define EDMA_RXFILL_OPAQUE_LO_SET(desc, ptr) (((desc)->word2) = \ ++ (u32)(uintptr_t)(ptr)) ++#ifdef __LP64__ ++#define EDMA_RXFILL_OPAQUE_HI_SET(desc, ptr) (((desc)->word3) = \ ++ (u32)((u64)(ptr) >> 0x20)) ++#endif ++ ++#define EDMA_RXFILL_OPAQUE_GET(_desc) ({ \ ++ typeof(_desc) (desc) = (_desc); \ ++ ((uintptr_t)((u64)((desc)->word2) | \ ++ ((u64)((desc)->word3) << 0x20))); }) ++ ++#define EDMA_RXFILL_PACKET_LEN_SET(desc, len) { \ ++ (((desc)->word1) = (u32)((((u32)len) << EDMA_RXFILL_BUF_SIZE_SHIFT) & \ ++ 0xFFFF0000)); \ ++} ++ ++#define EDMA_RXFILL_BUFFER_ADDR_SET(desc, addr) (((desc)->word0) = (u32)(addr)) ++ ++/* Opaque values are set in word2 and word3, they are not accessed by the EDMA HW, ++ * so endianness conversion is not needed. ++ */ ++#define EDMA_RXFILL_ENDIAN_SET(_desc) ({ \ ++ typeof(_desc) (desc) = (_desc); \ ++ cpu_to_le32s(&((desc)->word0)); \ ++ cpu_to_le32s(&((desc)->word1)); \ ++}) ++ ++/* RX DESC size shift to obtain index from descriptor pointer. */ ++#define EDMA_RXDESC_SIZE_SHIFT 5 ++ ++/** ++ * struct edma_rxdesc_stats - RX descriptor ring stats. ++ * @src_port_inval: Invalid source port number ++ * @src_port_inval_type: Source type is not PORT ID ++ * @src_port_inval_netdev: Invalid net device for the source port ++ * @syncp: Synchronization pointer ++ */ ++struct edma_rxdesc_stats { ++ u64 src_port_inval; ++ u64 src_port_inval_type; ++ u64 src_port_inval_netdev; ++ struct u64_stats_sync syncp; ++}; ++ ++/** ++ * struct edma_rxfill_stats - Rx fill descriptor ring stats. ++ * @alloc_failed: Buffer allocation failure count ++ * @page_alloc_failed: Page allocation failure count for page mode ++ * @syncp: Synchronization pointer ++ */ ++struct edma_rxfill_stats { ++ u64 alloc_failed; ++ u64 page_alloc_failed; ++ struct u64_stats_sync syncp; ++}; ++ ++/** ++ * struct edma_rxdesc_pri - Rx descriptor. ++ * @word0: Buffer address ++ * @word1: More bit, priority bit, service code ++ * @word2: Opaque low bits ++ * @word3: Opaque high bits ++ * @word4: Destination and source information ++ * @word5: WiFi QoS, data length ++ * @word6: Hash value, check sum status ++ * @word7: DSCP, packet offsets ++ */ ++struct edma_rxdesc_pri { ++ u32 word0; ++ u32 word1; ++ u32 word2; ++ u32 word3; ++ u32 word4; ++ u32 word5; ++ u32 word6; ++ u32 word7; ++}; ++ ++ /** ++ * struct edma_rxdesc_sec - Rx secondary descriptor. ++ * @word0: Timestamp ++ * @word1: Secondary checksum status ++ * @word2: QoS tag ++ * @word3: Flow index details ++ * @word4: Secondary packet offsets ++ * @word5: Multicast bit, checksum ++ * @word6: SVLAN, CVLAN ++ * @word7: Secondary SVLAN, CVLAN ++ */ ++struct edma_rxdesc_sec { ++ u32 word0; ++ u32 word1; ++ u32 word2; ++ u32 word3; ++ u32 word4; ++ u32 word5; ++ u32 word6; ++ u32 word7; ++}; ++ ++/** ++ * struct edma_rxfill_desc - RxFill descriptor. ++ * @word0: Buffer address ++ * @word1: Buffer size ++ * @word2: Opaque low bits ++ * @word3: Opaque high bits ++ */ ++struct edma_rxfill_desc { ++ u32 word0; ++ u32 word1; ++ u32 word2; ++ u32 word3; ++}; ++ ++/** ++ * struct edma_rxfill_ring - RxFill ring ++ * @ring_id: RxFill ring number ++ * @count: Number of descriptors in the ring ++ * @prod_idx: Ring producer index ++ * @alloc_size: Buffer size to allocate ++ * @desc: Descriptor ring virtual address ++ * @dma: Descriptor ring physical address ++ * @buf_len: Buffer length for rxfill descriptor ++ * @page_mode: Page mode for Rx processing ++ * @rx_fill_stats: Rx fill ring statistics ++ */ ++struct edma_rxfill_ring { ++ u32 ring_id; ++ u32 count; ++ u32 prod_idx; ++ u32 alloc_size; ++ struct edma_rxfill_desc *desc; ++ dma_addr_t dma; ++ u32 buf_len; ++ bool page_mode; ++ struct edma_rxfill_stats rxfill_stats; ++}; ++ ++/** ++ * struct edma_rxdesc_ring - RxDesc ring ++ * @napi: Pointer to napi ++ * @ring_id: Rxdesc ring number ++ * @count: Number of descriptors in the ring ++ * @work_leftover: Leftover descriptors to be processed ++ * @cons_idx: Ring consumer index ++ * @pdesc: Primary descriptor ring virtual address ++ * @pdesc_head: Primary descriptor head in case of scatter-gather frame ++ * @sdesc: Secondary descriptor ring virtual address ++ * @rxdesc_stats: Rx descriptor ring statistics ++ * @rxfill: RxFill ring used ++ * @napi_added: Flag to indicate NAPI add status ++ * @pdma: Primary descriptor ring physical address ++ * @sdma: Secondary descriptor ring physical address ++ * @head: Head of the skb list in case of scatter-gather frame ++ * @last: Last skb of the skb list in case of scatter-gather frame ++ */ ++struct edma_rxdesc_ring { ++ struct napi_struct napi; ++ u32 ring_id; ++ u32 count; ++ u32 work_leftover; ++ u32 cons_idx; ++ struct edma_rxdesc_pri *pdesc; ++ struct edma_rxdesc_pri *pdesc_head; ++ struct edma_rxdesc_sec *sdesc; ++ struct edma_rxdesc_stats rxdesc_stats; ++ struct edma_rxfill_ring *rxfill; ++ bool napi_added; ++ dma_addr_t pdma; ++ dma_addr_t sdma; ++ struct sk_buff *head; ++ struct sk_buff *last; ++}; ++ ++irqreturn_t edma_rx_handle_irq(int irq, void *ctx); ++int edma_rx_alloc_buffer(struct edma_rxfill_ring *rxfill_ring, int alloc_count); ++int edma_rx_napi_poll(struct napi_struct *napi, int budget); ++#endif diff --git a/target/linux/qualcommbe/patches-6.12/0345-net-ethernet-qualcomm-Add-Tx-Ethernet-DMA-support.patch b/target/linux/qualcommbe/patches-6.12/0345-net-ethernet-qualcomm-Add-Tx-Ethernet-DMA-support.patch new file mode 100644 index 0000000000..39d300de80 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0345-net-ethernet-qualcomm-Add-Tx-Ethernet-DMA-support.patch @@ -0,0 +1,2363 @@ +From 339d3a5365f150a78ed405684e379fee3acdbe90 Mon Sep 17 00:00:00 2001 +From: Suruchi Agarwal +Date: Thu, 21 Mar 2024 16:26:29 -0700 +Subject: [PATCH] net: ethernet: qualcomm: Add Tx Ethernet DMA support + +Add Tx queues, rings, descriptors configurations and +DMA support for the EDMA. + +Change-Id: Idfb0e1fe5ac494d614097d6c97dd15d63bbce8e6 +Co-developed-by: Pavithra R +Signed-off-by: Pavithra R +Signed-off-by: Suruchi Agarwal +--- + drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +- + drivers/net/ethernet/qualcomm/ppe/edma.c | 97 ++- + drivers/net/ethernet/qualcomm/ppe/edma.h | 7 + + .../net/ethernet/qualcomm/ppe/edma_cfg_tx.c | 648 ++++++++++++++ + .../net/ethernet/qualcomm/ppe/edma_cfg_tx.h | 28 + + drivers/net/ethernet/qualcomm/ppe/edma_port.c | 136 +++ + drivers/net/ethernet/qualcomm/ppe/edma_port.h | 35 + + drivers/net/ethernet/qualcomm/ppe/edma_tx.c | 808 ++++++++++++++++++ + drivers/net/ethernet/qualcomm/ppe/edma_tx.h | 302 +++++++ + 9 files changed, 2055 insertions(+), 8 deletions(-) + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.c + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.h + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_tx.c + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_tx.h + +--- a/drivers/net/ethernet/qualcomm/ppe/Makefile ++++ b/drivers/net/ethernet/qualcomm/ppe/Makefile +@@ -7,4 +7,4 @@ obj-$(CONFIG_QCOM_PPE) += qcom-ppe.o + qcom-ppe-objs := ppe.o ppe_config.o ppe_debugfs.o ppe_port.o + + #EDMA +-qcom-ppe-objs += edma.o edma_cfg_rx.o edma_port.o edma_rx.o ++qcom-ppe-objs += edma.o edma_cfg_rx.o edma_cfg_tx.o edma_port.o edma_rx.o edma_tx.o +--- a/drivers/net/ethernet/qualcomm/ppe/edma.c ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.c +@@ -18,6 +18,7 @@ + #include + + #include "edma.h" ++#include "edma_cfg_tx.h" + #include "edma_cfg_rx.h" + #include "ppe_regs.h" + +@@ -25,6 +26,7 @@ + + /* Global EDMA context. */ + struct edma_context *edma_ctx; ++static char **edma_txcmpl_irq_name; + static char **edma_rxdesc_irq_name; + + /* Module params. */ +@@ -192,22 +194,59 @@ static int edma_configure_ucast_prio_map + static int edma_irq_register(void) + { + struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *txcmpl = hw_info->txcmpl; + struct edma_ring_info *rx = hw_info->rx; + int ret; + u32 i; + ++ /* Request IRQ for TXCMPL rings. */ ++ edma_txcmpl_irq_name = kzalloc((sizeof(char *) * txcmpl->num_rings), GFP_KERNEL); ++ if (!edma_txcmpl_irq_name) ++ return -ENOMEM; ++ ++ for (i = 0; i < txcmpl->num_rings; i++) { ++ edma_txcmpl_irq_name[i] = kzalloc((sizeof(char *) * EDMA_IRQ_NAME_SIZE), ++ GFP_KERNEL); ++ if (!edma_txcmpl_irq_name[i]) { ++ ret = -ENOMEM; ++ goto txcmpl_ring_irq_name_alloc_fail; ++ } ++ ++ snprintf(edma_txcmpl_irq_name[i], EDMA_IRQ_NAME_SIZE, "edma_txcmpl_%d", ++ txcmpl->ring_start + i); ++ ++ irq_set_status_flags(edma_ctx->intr_info.intr_txcmpl[i], IRQ_DISABLE_UNLAZY); ++ ++ ret = request_irq(edma_ctx->intr_info.intr_txcmpl[i], ++ edma_tx_handle_irq, IRQF_SHARED, ++ edma_txcmpl_irq_name[i], ++ (void *)&edma_ctx->txcmpl_rings[i]); ++ if (ret) { ++ pr_err("TXCMPL ring IRQ:%d request %d failed\n", ++ edma_ctx->intr_info.intr_txcmpl[i], i); ++ goto txcmpl_ring_intr_req_fail; ++ } ++ ++ pr_debug("TXCMPL ring: %d IRQ:%d request success: %s\n", ++ txcmpl->ring_start + i, ++ edma_ctx->intr_info.intr_txcmpl[i], ++ edma_txcmpl_irq_name[i]); ++ } ++ + /* Request IRQ for RXDESC rings. */ + edma_rxdesc_irq_name = kzalloc((sizeof(char *) * rx->num_rings), + GFP_KERNEL); +- if (!edma_rxdesc_irq_name) +- return -ENOMEM; ++ if (!edma_rxdesc_irq_name) { ++ ret = -ENOMEM; ++ goto rxdesc_irq_name_alloc_fail; ++ } + + for (i = 0; i < rx->num_rings; i++) { + edma_rxdesc_irq_name[i] = kzalloc((sizeof(char *) * EDMA_IRQ_NAME_SIZE), + GFP_KERNEL); + if (!edma_rxdesc_irq_name[i]) { + ret = -ENOMEM; +- goto rxdesc_irq_name_alloc_fail; ++ goto rxdesc_ring_irq_name_alloc_fail; + } + + snprintf(edma_rxdesc_irq_name[i], 20, "edma_rxdesc_%d", +@@ -236,8 +275,19 @@ static int edma_irq_register(void) + rx_desc_ring_intr_req_fail: + for (i = 0; i < rx->num_rings; i++) + kfree(edma_rxdesc_irq_name[i]); +-rxdesc_irq_name_alloc_fail: ++rxdesc_ring_irq_name_alloc_fail: + kfree(edma_rxdesc_irq_name); ++rxdesc_irq_name_alloc_fail: ++ for (i = 0; i < txcmpl->num_rings; i++) { ++ synchronize_irq(edma_ctx->intr_info.intr_txcmpl[i]); ++ free_irq(edma_ctx->intr_info.intr_txcmpl[i], ++ (void *)&edma_ctx->txcmpl_rings[i]); ++ } ++txcmpl_ring_intr_req_fail: ++ for (i = 0; i < txcmpl->num_rings; i++) ++ kfree(edma_txcmpl_irq_name[i]); ++txcmpl_ring_irq_name_alloc_fail: ++ kfree(edma_txcmpl_irq_name); + + return ret; + } +@@ -326,12 +376,22 @@ static int edma_irq_init(void) + + static int edma_alloc_rings(void) + { ++ if (edma_cfg_tx_rings_alloc()) { ++ pr_err("Error in allocating Tx rings\n"); ++ return -ENOMEM; ++ } ++ + if (edma_cfg_rx_rings_alloc()) { + pr_err("Error in allocating Rx rings\n"); +- return -ENOMEM; ++ goto rx_rings_alloc_fail; + } + + return 0; ++ ++rx_rings_alloc_fail: ++ edma_cfg_tx_rings_cleanup(); ++ ++ return -ENOMEM; + } + + static int edma_hw_reset(void) +@@ -389,7 +449,7 @@ static int edma_hw_configure(void) + struct edma_hw_info *hw_info = edma_ctx->hw_info; + struct ppe_device *ppe_dev = edma_ctx->ppe_dev; + struct regmap *regmap = ppe_dev->regmap; +- u32 data, reg; ++ u32 data, reg, i; + int ret; + + reg = EDMA_BASE_OFFSET + EDMA_REG_MAS_CTRL_ADDR; +@@ -439,11 +499,17 @@ static int edma_hw_configure(void) + } + + /* Disable interrupts. */ ++ for (i = 1; i <= hw_info->max_ports; i++) ++ edma_cfg_tx_disable_interrupts(i); ++ + edma_cfg_rx_disable_interrupts(); + + edma_cfg_rx_rings_disable(); + + edma_cfg_rx_ring_mappings(); ++ edma_cfg_tx_ring_mappings(); ++ ++ edma_cfg_tx_rings(); + + ret = edma_cfg_rx_rings(); + if (ret) { +@@ -520,6 +586,7 @@ configure_ucast_prio_map_tbl_failed: + edma_cfg_rx_napi_delete(); + edma_cfg_rx_rings_disable(); + edma_cfg_rx_rings_failed: ++ edma_cfg_tx_rings_cleanup(); + edma_cfg_rx_rings_cleanup(); + edma_alloc_rings_failed: + free_netdev(edma_ctx->dummy_dev); +@@ -538,13 +605,27 @@ dummy_dev_alloc_failed: + void edma_destroy(struct ppe_device *ppe_dev) + { + struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *txcmpl = hw_info->txcmpl; + struct edma_ring_info *rx = hw_info->rx; + u32 i; + + /* Disable interrupts. */ ++ for (i = 1; i <= hw_info->max_ports; i++) ++ edma_cfg_tx_disable_interrupts(i); ++ + edma_cfg_rx_disable_interrupts(); + +- /* Free IRQ for RXDESC rings. */ ++ /* Free IRQ for TXCMPL rings. */ ++ for (i = 0; i < txcmpl->num_rings; i++) { ++ synchronize_irq(edma_ctx->intr_info.intr_txcmpl[i]); ++ ++ free_irq(edma_ctx->intr_info.intr_txcmpl[i], ++ (void *)&edma_ctx->txcmpl_rings[i]); ++ kfree(edma_txcmpl_irq_name[i]); ++ } ++ kfree(edma_txcmpl_irq_name); ++ ++ /* Free IRQ for RXDESC rings */ + for (i = 0; i < rx->num_rings; i++) { + synchronize_irq(edma_ctx->intr_info.intr_rx[i]); + free_irq(edma_ctx->intr_info.intr_rx[i], +@@ -560,6 +641,7 @@ void edma_destroy(struct ppe_device *ppe + edma_cfg_rx_napi_delete(); + edma_cfg_rx_rings_disable(); + edma_cfg_rx_rings_cleanup(); ++ edma_cfg_tx_rings_cleanup(); + + free_netdev(edma_ctx->dummy_dev); + kfree(edma_ctx->netdev_arr); +@@ -585,6 +667,7 @@ int edma_setup(struct ppe_device *ppe_de + edma_ctx->hw_info = &ipq9574_hw_info; + edma_ctx->ppe_dev = ppe_dev; + edma_ctx->rx_buf_size = rx_buff_size; ++ edma_ctx->tx_requeue_stop = false; + + /* Configure the EDMA common clocks. */ + ret = edma_clock_init(); +--- a/drivers/net/ethernet/qualcomm/ppe/edma.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.h +@@ -7,6 +7,7 @@ + + #include "ppe_config.h" + #include "edma_rx.h" ++#include "edma_tx.h" + + /* One clock cycle = 1/(EDMA clock frequency in Mhz) micro seconds. + * +@@ -104,8 +105,11 @@ struct edma_intr_info { + * @intr_info: EDMA Interrupt info + * @rxfill_rings: Rx fill Rings, SW is producer + * @rx_rings: Rx Desc Rings, SW is consumer ++ * @tx_rings: Tx Descriptor Ring, SW is producer ++ * @txcmpl_rings: Tx complete Ring, SW is consumer + * @rx_page_mode: Page mode enabled or disabled + * @rx_buf_size: Rx buffer size for Jumbo MRU ++ * @tx_requeue_stop: Tx requeue stop enabled or disabled + */ + struct edma_context { + struct net_device **netdev_arr; +@@ -115,8 +119,11 @@ struct edma_context { + struct edma_intr_info intr_info; + struct edma_rxfill_ring *rxfill_rings; + struct edma_rxdesc_ring *rx_rings; ++ struct edma_txdesc_ring *tx_rings; ++ struct edma_txcmpl_ring *txcmpl_rings; + u32 rx_page_mode; + u32 rx_buf_size; ++ bool tx_requeue_stop; + }; + + /* Global EDMA context */ +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.c +@@ -0,0 +1,648 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* Configure rings, Buffers and NAPI for transmit path along with ++ * providing APIs to enable, disable, clean and map the Tx rings. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "edma.h" ++#include "edma_cfg_tx.h" ++#include "edma_port.h" ++#include "ppe.h" ++#include "ppe_regs.h" ++ ++static void edma_cfg_txcmpl_ring_cleanup(struct edma_txcmpl_ring *txcmpl_ring) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct device *dev = ppe_dev->dev; ++ ++ /* Free any buffers assigned to any descriptors. */ ++ edma_tx_complete(EDMA_TX_RING_SIZE - 1, txcmpl_ring); ++ ++ /* Free TxCmpl ring descriptors. */ ++ dma_free_coherent(dev, sizeof(struct edma_txcmpl_desc) ++ * txcmpl_ring->count, txcmpl_ring->desc, ++ txcmpl_ring->dma); ++ txcmpl_ring->desc = NULL; ++ txcmpl_ring->dma = (dma_addr_t)0; ++} ++ ++static int edma_cfg_txcmpl_ring_setup(struct edma_txcmpl_ring *txcmpl_ring) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct device *dev = ppe_dev->dev; ++ ++ /* Allocate RxFill ring descriptors. */ ++ txcmpl_ring->desc = dma_alloc_coherent(dev, sizeof(struct edma_txcmpl_desc) ++ * txcmpl_ring->count, ++ &txcmpl_ring->dma, ++ GFP_KERNEL | __GFP_ZERO); ++ ++ if (unlikely(!txcmpl_ring->desc)) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++static void edma_cfg_tx_desc_ring_cleanup(struct edma_txdesc_ring *txdesc_ring) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_txdesc_pri *txdesc = NULL; ++ struct device *dev = ppe_dev->dev; ++ u32 prod_idx, cons_idx, data, reg; ++ struct sk_buff *skb = NULL; ++ ++ /* Free any buffers assigned to any descriptors. */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id); ++ regmap_read(regmap, reg, &data); ++ prod_idx = data & EDMA_TXDESC_PROD_IDX_MASK; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id); ++ regmap_read(regmap, reg, &data); ++ cons_idx = data & EDMA_TXDESC_CONS_IDX_MASK; ++ ++ /* Walk active list, obtain skb from descriptor and free it. */ ++ while (cons_idx != prod_idx) { ++ txdesc = EDMA_TXDESC_PRI_DESC(txdesc_ring, cons_idx); ++ skb = (struct sk_buff *)EDMA_TXDESC_OPAQUE_GET(txdesc); ++ dev_kfree_skb_any(skb); ++ ++ cons_idx = ((cons_idx + 1) & EDMA_TX_RING_SIZE_MASK); ++ } ++ ++ /* Free Tx ring descriptors. */ ++ dma_free_coherent(dev, (sizeof(struct edma_txdesc_pri) ++ * txdesc_ring->count), ++ txdesc_ring->pdesc, ++ txdesc_ring->pdma); ++ txdesc_ring->pdesc = NULL; ++ txdesc_ring->pdma = (dma_addr_t)0; ++ ++ /* Free any buffers assigned to any secondary descriptors. */ ++ dma_free_coherent(dev, (sizeof(struct edma_txdesc_sec) ++ * txdesc_ring->count), ++ txdesc_ring->sdesc, ++ txdesc_ring->sdma); ++ txdesc_ring->sdesc = NULL; ++ txdesc_ring->sdma = (dma_addr_t)0; ++} ++ ++static int edma_cfg_tx_desc_ring_setup(struct edma_txdesc_ring *txdesc_ring) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct device *dev = ppe_dev->dev; ++ ++ /* Allocate RxFill ring descriptors. */ ++ txdesc_ring->pdesc = dma_alloc_coherent(dev, sizeof(struct edma_txdesc_pri) ++ * txdesc_ring->count, ++ &txdesc_ring->pdma, ++ GFP_KERNEL | __GFP_ZERO); ++ ++ if (unlikely(!txdesc_ring->pdesc)) ++ return -ENOMEM; ++ ++ txdesc_ring->sdesc = dma_alloc_coherent(dev, sizeof(struct edma_txdesc_sec) ++ * txdesc_ring->count, ++ &txdesc_ring->sdma, ++ GFP_KERNEL | __GFP_ZERO); ++ ++ if (unlikely(!txdesc_ring->sdesc)) { ++ dma_free_coherent(dev, (sizeof(struct edma_txdesc_pri) ++ * txdesc_ring->count), ++ txdesc_ring->pdesc, ++ txdesc_ring->pdma); ++ txdesc_ring->pdesc = NULL; ++ txdesc_ring->pdma = (dma_addr_t)0; ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static void edma_cfg_tx_desc_ring_configure(struct edma_txdesc_ring *txdesc_ring) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 data, reg; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC_BA(txdesc_ring->id); ++ regmap_write(regmap, reg, (u32)(txdesc_ring->pdma & EDMA_RING_DMA_MASK)); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC_BA2(txdesc_ring->id); ++ regmap_write(regmap, reg, (u32)(txdesc_ring->sdma & EDMA_RING_DMA_MASK)); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC_RING_SIZE(txdesc_ring->id); ++ regmap_write(regmap, reg, (u32)(txdesc_ring->count & EDMA_TXDESC_RING_SIZE_MASK)); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id); ++ regmap_write(regmap, reg, (u32)EDMA_TX_INITIAL_PROD_IDX); ++ ++ data = FIELD_PREP(EDMA_TXDESC_CTRL_FC_GRP_ID_MASK, txdesc_ring->fc_grp_id); ++ ++ /* Configure group ID for flow control for this Tx ring. */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC_CTRL(txdesc_ring->id); ++ regmap_write(regmap, reg, data); ++} ++ ++static void edma_cfg_txcmpl_ring_configure(struct edma_txcmpl_ring *txcmpl_ring) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 data, reg; ++ ++ /* Configure TxCmpl ring base address. */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXCMPL_BA(txcmpl_ring->id); ++ regmap_write(regmap, reg, (u32)(txcmpl_ring->dma & EDMA_RING_DMA_MASK)); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXCMPL_RING_SIZE(txcmpl_ring->id); ++ regmap_write(regmap, reg, (u32)(txcmpl_ring->count & EDMA_TXDESC_RING_SIZE_MASK)); ++ ++ /* Set TxCmpl ret mode to opaque. */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXCMPL_CTRL(txcmpl_ring->id); ++ regmap_write(regmap, reg, EDMA_TXCMPL_RETMODE_OPAQUE); ++ ++ /* Configure the Mitigation timer. */ ++ data = EDMA_MICROSEC_TO_TIMER_UNIT(EDMA_TX_MITIGATION_TIMER_DEF, ++ ppe_dev->clk_rate / MHZ); ++ data = ((data & EDMA_TX_MOD_TIMER_INIT_MASK) ++ << EDMA_TX_MOD_TIMER_INIT_SHIFT); ++ pr_debug("EDMA Tx mitigation timer value: %d\n", data); ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TX_MOD_TIMER(txcmpl_ring->id); ++ regmap_write(regmap, reg, data); ++ ++ /* Configure the Mitigation packet count. */ ++ data = (EDMA_TX_MITIGATION_PKT_CNT_DEF & EDMA_TXCMPL_LOW_THRE_MASK) ++ << EDMA_TXCMPL_LOW_THRE_SHIFT; ++ pr_debug("EDMA Tx mitigation packet count value: %d\n", data); ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXCMPL_UGT_THRE(txcmpl_ring->id); ++ regmap_write(regmap, reg, data); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TX_INT_CTRL(txcmpl_ring->id); ++ regmap_write(regmap, reg, EDMA_TX_NE_INT_EN); ++} ++ ++/** ++ * edma_cfg_tx_fill_per_port_tx_map - Fill Tx ring mapping. ++ * @netdev: Netdevice. ++ * @port_id: Port ID. ++ * ++ * Fill per-port Tx ring mapping in net device private area. ++ */ ++void edma_cfg_tx_fill_per_port_tx_map(struct net_device *netdev, u32 port_id) ++{ ++ u32 i; ++ ++ /* Ring to core mapping is done in order starting from 0 for port 1. */ ++ for_each_possible_cpu(i) { ++ struct edma_port_priv *port_dev = (struct edma_port_priv *)netdev_priv(netdev); ++ struct edma_txdesc_ring *txdesc_ring; ++ u32 txdesc_ring_id; ++ ++ txdesc_ring_id = ((port_id - 1) * num_possible_cpus()) + i; ++ txdesc_ring = &edma_ctx->tx_rings[txdesc_ring_id]; ++ port_dev->txr_map[i] = txdesc_ring; ++ } ++} ++ ++/** ++ * edma_cfg_tx_rings_enable - Enable Tx rings. ++ * ++ * Enable Tx rings. ++ */ ++void edma_cfg_tx_rings_enable(u32 port_id) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_txdesc_ring *txdesc_ring; ++ u32 i, ring_idx, reg; ++ ++ for_each_possible_cpu(i) { ++ ring_idx = ((port_id - 1) * num_possible_cpus()) + i; ++ txdesc_ring = &edma_ctx->tx_rings[ring_idx]; ++ u32 data; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC_CTRL(txdesc_ring->id); ++ regmap_read(regmap, reg, &data); ++ data |= FIELD_PREP(EDMA_TXDESC_CTRL_TXEN_MASK, EDMA_TXDESC_TX_ENABLE); ++ ++ regmap_write(regmap, reg, data); ++ } ++} ++ ++/** ++ * edma_cfg_tx_rings_disable - Disable Tx rings. ++ * ++ * Disable Tx rings. ++ */ ++void edma_cfg_tx_rings_disable(u32 port_id) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_txdesc_ring *txdesc_ring; ++ u32 i, ring_idx, reg; ++ ++ for_each_possible_cpu(i) { ++ ring_idx = ((port_id - 1) * num_possible_cpus()) + i; ++ txdesc_ring = &edma_ctx->tx_rings[ring_idx]; ++ u32 data; ++ ++ txdesc_ring = &edma_ctx->tx_rings[i]; ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC_CTRL(txdesc_ring->id); ++ regmap_read(regmap, reg, &data); ++ data &= ~EDMA_TXDESC_TX_ENABLE; ++ regmap_write(regmap, reg, data); ++ } ++} ++ ++/** ++ * edma_cfg_tx_ring_mappings - Map Tx to Tx complete rings. ++ * ++ * Map Tx to Tx complete rings. ++ */ ++void edma_cfg_tx_ring_mappings(void) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *txcmpl = hw_info->txcmpl; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_ring_info *tx = hw_info->tx; ++ u32 desc_index, i, data, reg; ++ ++ /* Clear the TXDESC2CMPL_MAP_xx reg before setting up ++ * the mapping. This register holds TXDESC to TXFILL ring ++ * mapping. ++ */ ++ regmap_write(regmap, EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_0_ADDR, 0); ++ regmap_write(regmap, EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_1_ADDR, 0); ++ regmap_write(regmap, EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_2_ADDR, 0); ++ regmap_write(regmap, EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_3_ADDR, 0); ++ regmap_write(regmap, EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_4_ADDR, 0); ++ regmap_write(regmap, EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_5_ADDR, 0); ++ desc_index = txcmpl->ring_start; ++ ++ /* 6 registers to hold the completion mapping for total 32 ++ * TX desc rings (0-5, 6-11, 12-17, 18-23, 24-29 and rest). ++ * In each entry 5 bits hold the mapping for a particular TX desc ring. ++ */ ++ for (i = tx->ring_start; i < tx->ring_start + tx->num_rings; i++) { ++ u32 reg, data; ++ ++ if (i >= 0 && i <= 5) ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_0_ADDR; ++ else if (i >= 6 && i <= 11) ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_1_ADDR; ++ else if (i >= 12 && i <= 17) ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_2_ADDR; ++ else if (i >= 18 && i <= 23) ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_3_ADDR; ++ else if (i >= 24 && i <= 29) ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_4_ADDR; ++ else ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_5_ADDR; ++ ++ pr_debug("Configure Tx desc:%u to use TxCmpl:%u\n", i, desc_index); ++ ++ /* Set the Tx complete descriptor ring number in the mapping register. ++ * E.g. If (txcmpl ring)desc_index = 31, (txdesc ring)i = 28. ++ * reg = EDMA_REG_TXDESC2CMPL_MAP_4_ADDR ++ * data |= (desc_index & 0x1F) << ((i % 6) * 5); ++ * data |= (0x1F << 20); - ++ * This sets 11111 at 20th bit of register EDMA_REG_TXDESC2CMPL_MAP_4_ADDR. ++ */ ++ regmap_read(regmap, reg, &data); ++ data |= (desc_index & EDMA_TXDESC2CMPL_MAP_TXDESC_MASK) << ((i % 6) * 5); ++ regmap_write(regmap, reg, data); ++ ++ desc_index++; ++ if (desc_index == txcmpl->ring_start + txcmpl->num_rings) ++ desc_index = txcmpl->ring_start; ++ } ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_0_ADDR; ++ regmap_read(regmap, reg, &data); ++ pr_debug("EDMA_REG_TXDESC2CMPL_MAP_0_ADDR: 0x%x\n", data); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_1_ADDR; ++ regmap_read(regmap, reg, &data); ++ pr_debug("EDMA_REG_TXDESC2CMPL_MAP_1_ADDR: 0x%x\n", data); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_2_ADDR; ++ regmap_read(regmap, reg, &data); ++ pr_debug("EDMA_REG_TXDESC2CMPL_MAP_2_ADDR: 0x%x\n", data); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_3_ADDR; ++ regmap_read(regmap, reg, &data); ++ pr_debug("EDMA_REG_TXDESC2CMPL_MAP_3_ADDR: 0x%x\n", data); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_4_ADDR; ++ regmap_read(regmap, reg, &data); ++ pr_debug("EDMA_REG_TXDESC2CMPL_MAP_4_ADDR: 0x%x\n", data); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC2CMPL_MAP_5_ADDR; ++ regmap_read(regmap, reg, &data); ++ pr_debug("EDMA_REG_TXDESC2CMPL_MAP_5_ADDR: 0x%x\n", data); ++} ++ ++static int edma_cfg_tx_rings_setup(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *txcmpl = hw_info->txcmpl; ++ struct edma_ring_info *tx = hw_info->tx; ++ u32 i, j = 0; ++ ++ /* Set Txdesc flow control group id, same as port number. */ ++ for (i = 0; i < hw_info->max_ports; i++) { ++ for_each_possible_cpu(j) { ++ struct edma_txdesc_ring *txdesc_ring = NULL; ++ u32 txdesc_idx = (i * num_possible_cpus()) + j; ++ ++ txdesc_ring = &edma_ctx->tx_rings[txdesc_idx]; ++ txdesc_ring->fc_grp_id = i + 1; ++ } ++ } ++ ++ /* Allocate TxDesc ring descriptors. */ ++ for (i = 0; i < tx->num_rings; i++) { ++ struct edma_txdesc_ring *txdesc_ring = NULL; ++ int ret; ++ ++ txdesc_ring = &edma_ctx->tx_rings[i]; ++ txdesc_ring->count = EDMA_TX_RING_SIZE; ++ txdesc_ring->id = tx->ring_start + i; ++ ++ ret = edma_cfg_tx_desc_ring_setup(txdesc_ring); ++ if (ret) { ++ pr_err("Error in setting up %d txdesc ring. ret: %d", ++ txdesc_ring->id, ret); ++ while (i-- >= 0) ++ edma_cfg_tx_desc_ring_cleanup(&edma_ctx->tx_rings[i]); ++ ++ return -ENOMEM; ++ } ++ } ++ ++ /* Allocate TxCmpl ring descriptors. */ ++ for (i = 0; i < txcmpl->num_rings; i++) { ++ struct edma_txcmpl_ring *txcmpl_ring = NULL; ++ int ret; ++ ++ txcmpl_ring = &edma_ctx->txcmpl_rings[i]; ++ txcmpl_ring->count = EDMA_TX_RING_SIZE; ++ txcmpl_ring->id = txcmpl->ring_start + i; ++ ++ ret = edma_cfg_txcmpl_ring_setup(txcmpl_ring); ++ if (ret != 0) { ++ pr_err("Error in setting up %d TxCmpl ring. ret: %d", ++ txcmpl_ring->id, ret); ++ while (i-- >= 0) ++ edma_cfg_txcmpl_ring_cleanup(&edma_ctx->txcmpl_rings[i]); ++ ++ goto txcmpl_mem_alloc_fail; ++ } ++ } ++ ++ pr_debug("Tx descriptor count for Tx desc and Tx complete rings: %d\n", ++ EDMA_TX_RING_SIZE); ++ ++ return 0; ++ ++txcmpl_mem_alloc_fail: ++ for (i = 0; i < tx->num_rings; i++) ++ edma_cfg_tx_desc_ring_cleanup(&edma_ctx->tx_rings[i]); ++ ++ return -ENOMEM; ++} ++ ++/** ++ * edma_cfg_tx_rings_alloc - Allocate EDMA Tx rings. ++ * ++ * Allocate EDMA Tx rings. ++ */ ++int edma_cfg_tx_rings_alloc(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *txcmpl = hw_info->txcmpl; ++ struct edma_ring_info *tx = hw_info->tx; ++ ++ edma_ctx->tx_rings = kzalloc((sizeof(*edma_ctx->tx_rings) * tx->num_rings), ++ GFP_KERNEL); ++ if (!edma_ctx->tx_rings) ++ return -ENOMEM; ++ ++ edma_ctx->txcmpl_rings = kzalloc((sizeof(*edma_ctx->txcmpl_rings) * txcmpl->num_rings), ++ GFP_KERNEL); ++ if (!edma_ctx->txcmpl_rings) ++ goto txcmpl_ring_alloc_fail; ++ ++ pr_debug("Num rings - TxDesc:%u (%u-%u) TxCmpl:%u (%u-%u)\n", ++ tx->num_rings, tx->ring_start, ++ (tx->ring_start + tx->num_rings - 1), ++ txcmpl->num_rings, txcmpl->ring_start, ++ (txcmpl->ring_start + txcmpl->num_rings - 1)); ++ ++ if (edma_cfg_tx_rings_setup()) { ++ pr_err("Error in setting up tx rings\n"); ++ goto tx_rings_setup_fail; ++ } ++ ++ return 0; ++ ++tx_rings_setup_fail: ++ kfree(edma_ctx->txcmpl_rings); ++ edma_ctx->txcmpl_rings = NULL; ++ ++txcmpl_ring_alloc_fail: ++ kfree(edma_ctx->tx_rings); ++ edma_ctx->tx_rings = NULL; ++ ++ return -ENOMEM; ++} ++ ++/** ++ * edma_cfg_tx_rings_cleanup - Cleanup EDMA Tx rings. ++ * ++ * Cleanup EDMA Tx rings. ++ */ ++void edma_cfg_tx_rings_cleanup(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *txcmpl = hw_info->txcmpl; ++ struct edma_ring_info *tx = hw_info->tx; ++ u32 i; ++ ++ /* Free any buffers assigned to any descriptors. */ ++ for (i = 0; i < tx->num_rings; i++) ++ edma_cfg_tx_desc_ring_cleanup(&edma_ctx->tx_rings[i]); ++ ++ /* Free Tx completion descriptors. */ ++ for (i = 0; i < txcmpl->num_rings; i++) ++ edma_cfg_txcmpl_ring_cleanup(&edma_ctx->txcmpl_rings[i]); ++ ++ kfree(edma_ctx->tx_rings); ++ kfree(edma_ctx->txcmpl_rings); ++ edma_ctx->tx_rings = NULL; ++ edma_ctx->txcmpl_rings = NULL; ++} ++ ++/** ++ * edma_cfg_tx_rings - Configure EDMA Tx rings. ++ * ++ * Configure EDMA Tx rings. ++ */ ++void edma_cfg_tx_rings(void) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *txcmpl = hw_info->txcmpl; ++ struct edma_ring_info *tx = hw_info->tx; ++ u32 i; ++ ++ /* Configure Tx desc ring. */ ++ for (i = 0; i < tx->num_rings; i++) ++ edma_cfg_tx_desc_ring_configure(&edma_ctx->tx_rings[i]); ++ ++ /* Configure TxCmpl ring. */ ++ for (i = 0; i < txcmpl->num_rings; i++) ++ edma_cfg_txcmpl_ring_configure(&edma_ctx->txcmpl_rings[i]); ++} ++ ++/** ++ * edma_cfg_tx_disable_interrupts - EDMA disable TX interrupts. ++ * ++ * Disable TX interrupt masks. ++ */ ++void edma_cfg_tx_disable_interrupts(u32 port_id) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_txcmpl_ring *txcmpl_ring; ++ u32 i, ring_idx, reg; ++ ++ for_each_possible_cpu(i) { ++ ring_idx = ((port_id - 1) * num_possible_cpus()) + i; ++ txcmpl_ring = &edma_ctx->txcmpl_rings[ring_idx]; ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TX_INT_MASK(txcmpl_ring->id); ++ regmap_write(regmap, reg, EDMA_MASK_INT_CLEAR); ++ } ++} ++ ++/** ++ * edma_cfg_tx_enable_interrupts - EDMA enable TX interrupts. ++ * ++ * Enable TX interrupt masks. ++ */ ++void edma_cfg_tx_enable_interrupts(u32 port_id) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_txcmpl_ring *txcmpl_ring; ++ u32 i, ring_idx, reg; ++ ++ for_each_possible_cpu(i) { ++ ring_idx = ((port_id - 1) * num_possible_cpus()) + i; ++ txcmpl_ring = &edma_ctx->txcmpl_rings[ring_idx]; ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TX_INT_MASK(txcmpl_ring->id); ++ regmap_write(regmap, reg, edma_ctx->intr_info.intr_mask_txcmpl); ++ } ++} ++ ++/** ++ * edma_cfg_tx_napi_enable - EDMA Tx NAPI. ++ * @port_id: Port ID. ++ * ++ * Enable Tx NAPI. ++ */ ++void edma_cfg_tx_napi_enable(u32 port_id) ++{ ++ struct edma_txcmpl_ring *txcmpl_ring; ++ u32 i, ring_idx; ++ ++ /* Enabling Tx napi for a interface with each queue. */ ++ for_each_possible_cpu(i) { ++ ring_idx = ((port_id - 1) * num_possible_cpus()) + i; ++ txcmpl_ring = &edma_ctx->txcmpl_rings[ring_idx]; ++ if (!txcmpl_ring->napi_added) ++ continue; ++ ++ napi_enable(&txcmpl_ring->napi); ++ } ++} ++ ++/** ++ * edma_cfg_tx_napi_disable - Disable Tx NAPI. ++ * @port_id: Port ID. ++ * ++ * Disable Tx NAPI. ++ */ ++void edma_cfg_tx_napi_disable(u32 port_id) ++{ ++ struct edma_txcmpl_ring *txcmpl_ring; ++ u32 i, ring_idx; ++ ++ /* Disabling Tx napi for a interface with each queue. */ ++ for_each_possible_cpu(i) { ++ ring_idx = ((port_id - 1) * num_possible_cpus()) + i; ++ txcmpl_ring = &edma_ctx->txcmpl_rings[ring_idx]; ++ if (!txcmpl_ring->napi_added) ++ continue; ++ ++ napi_disable(&txcmpl_ring->napi); ++ } ++} ++ ++/** ++ * edma_cfg_tx_napi_delete - Delete Tx NAPI. ++ * @port_id: Port ID. ++ * ++ * Delete Tx NAPI. ++ */ ++void edma_cfg_tx_napi_delete(u32 port_id) ++{ ++ struct edma_txcmpl_ring *txcmpl_ring; ++ u32 i, ring_idx; ++ ++ /* Disabling Tx napi for a interface with each queue. */ ++ for_each_possible_cpu(i) { ++ ring_idx = ((port_id - 1) * num_possible_cpus()) + i; ++ txcmpl_ring = &edma_ctx->txcmpl_rings[ring_idx]; ++ if (!txcmpl_ring->napi_added) ++ continue; ++ ++ netif_napi_del(&txcmpl_ring->napi); ++ txcmpl_ring->napi_added = false; ++ } ++} ++ ++/** ++ * edma_cfg_tx_napi_add - TX NAPI add. ++ * @netdev: Netdevice. ++ * @port_id: Port ID. ++ * ++ * TX NAPI add. ++ */ ++void edma_cfg_tx_napi_add(struct net_device *netdev, u32 port_id) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_txcmpl_ring *txcmpl_ring; ++ u32 i, ring_idx; ++ ++ /* Adding tx napi for a interface with each queue. */ ++ for_each_possible_cpu(i) { ++ ring_idx = ((port_id - 1) * num_possible_cpus()) + i; ++ txcmpl_ring = &edma_ctx->txcmpl_rings[ring_idx]; ++ netif_napi_add_weight(netdev, &txcmpl_ring->napi, ++ edma_tx_napi_poll, hw_info->napi_budget_tx); ++ txcmpl_ring->napi_added = true; ++ netdev_dbg(netdev, "Napi added for txcmpl ring: %u\n", txcmpl_ring->id); ++ } ++ ++ netdev_dbg(netdev, "Tx NAPI budget: %d\n", hw_info->napi_budget_tx); ++} +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.h +@@ -0,0 +1,28 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#ifndef __EDMA_CFG_TX__ ++#define __EDMA_CFG_TX__ ++ ++/* Tx mitigation timer's default value. */ ++#define EDMA_TX_MITIGATION_TIMER_DEF 250 ++ ++/* Tx mitigation packet count default value. */ ++#define EDMA_TX_MITIGATION_PKT_CNT_DEF 16 ++ ++void edma_cfg_tx_rings(void); ++int edma_cfg_tx_rings_alloc(void); ++void edma_cfg_tx_rings_cleanup(void); ++void edma_cfg_tx_disable_interrupts(u32 port_id); ++void edma_cfg_tx_enable_interrupts(u32 port_id); ++void edma_cfg_tx_napi_enable(u32 port_id); ++void edma_cfg_tx_napi_disable(u32 port_id); ++void edma_cfg_tx_napi_delete(u32 port_id); ++void edma_cfg_tx_napi_add(struct net_device *netdevice, u32 macid); ++void edma_cfg_tx_ring_mappings(void); ++void edma_cfg_txcmpl_mapping_fill(void); ++void edma_cfg_tx_rings_enable(u32 port_id); ++void edma_cfg_tx_rings_disable(u32 port_id); ++void edma_cfg_tx_fill_per_port_tx_map(struct net_device *netdev, u32 macid); ++#endif +--- a/drivers/net/ethernet/qualcomm/ppe/edma_port.c ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_port.c +@@ -13,6 +13,7 @@ + + #include "edma.h" + #include "edma_cfg_rx.h" ++#include "edma_cfg_tx.h" + #include "edma_port.h" + #include "ppe_regs.h" + +@@ -35,6 +36,15 @@ static int edma_port_stats_alloc(struct + return -ENOMEM; + } + ++ port_priv->pcpu_stats.tx_stats = ++ netdev_alloc_pcpu_stats(struct edma_port_tx_stats); ++ if (!port_priv->pcpu_stats.tx_stats) { ++ netdev_err(netdev, "Per-cpu EDMA Tx stats alloc failed for %s\n", ++ netdev->name); ++ free_percpu(port_priv->pcpu_stats.rx_stats); ++ return -ENOMEM; ++ } ++ + return 0; + } + +@@ -43,6 +53,28 @@ static void edma_port_stats_free(struct + struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); + + free_percpu(port_priv->pcpu_stats.rx_stats); ++ free_percpu(port_priv->pcpu_stats.tx_stats); ++} ++ ++static void edma_port_configure(struct net_device *netdev) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct ppe_port *port = port_priv->ppe_port; ++ int port_id = port->port_id; ++ ++ edma_cfg_tx_fill_per_port_tx_map(netdev, port_id); ++ edma_cfg_tx_rings_enable(port_id); ++ edma_cfg_tx_napi_add(netdev, port_id); ++} ++ ++static void edma_port_deconfigure(struct net_device *netdev) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct ppe_port *port = port_priv->ppe_port; ++ int port_id = port->port_id; ++ ++ edma_cfg_tx_napi_delete(port_id); ++ edma_cfg_tx_rings_disable(port_id); + } + + static u16 __maybe_unused edma_port_select_queue(__maybe_unused struct net_device *netdev, +@@ -60,6 +92,7 @@ static int edma_port_open(struct net_dev + { + struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); + struct ppe_port *ppe_port; ++ int port_id; + + if (!port_priv) + return -EINVAL; +@@ -74,10 +107,14 @@ static int edma_port_open(struct net_dev + netdev->wanted_features |= EDMA_NETDEV_FEATURES; + + ppe_port = port_priv->ppe_port; ++ port_id = ppe_port->port_id; + + if (ppe_port->phylink) + phylink_start(ppe_port->phylink); + ++ edma_cfg_tx_napi_enable(port_id); ++ edma_cfg_tx_enable_interrupts(port_id); ++ + netif_start_queue(netdev); + + return 0; +@@ -87,13 +124,21 @@ static int edma_port_close(struct net_de + { + struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); + struct ppe_port *ppe_port; ++ int port_id; + + if (!port_priv) + return -EINVAL; + + netif_stop_queue(netdev); + ++ /* 20ms delay would provide a plenty of margin to take care of in-flight packets. */ ++ msleep(20); ++ + ppe_port = port_priv->ppe_port; ++ port_id = ppe_port->port_id; ++ ++ edma_cfg_tx_disable_interrupts(port_id); ++ edma_cfg_tx_napi_disable(port_id); + + /* Phylink close. */ + if (ppe_port->phylink) +@@ -137,6 +182,92 @@ static netdev_features_t edma_port_featu + return features; + } + ++static netdev_tx_t edma_port_xmit(struct sk_buff *skb, ++ struct net_device *dev) ++{ ++ struct edma_port_priv *port_priv = NULL; ++ struct edma_port_pcpu_stats *pcpu_stats; ++ struct edma_txdesc_ring *txdesc_ring; ++ struct edma_port_tx_stats *stats; ++ enum edma_tx_gso_status result; ++ struct sk_buff *segs = NULL; ++ u8 cpu_id; ++ u32 skbq; ++ int ret; ++ ++ if (!skb || !dev) ++ return NETDEV_TX_OK; ++ ++ port_priv = netdev_priv(dev); ++ ++ /* Select a TX ring. */ ++ skbq = (skb_get_queue_mapping(skb) & (num_possible_cpus() - 1)); ++ ++ txdesc_ring = (struct edma_txdesc_ring *)port_priv->txr_map[skbq]; ++ ++ pcpu_stats = &port_priv->pcpu_stats; ++ stats = this_cpu_ptr(pcpu_stats->tx_stats); ++ ++ /* HW does not support TSO for packets with more than or equal to ++ * 32 segments. Perform SW GSO for such packets. ++ */ ++ result = edma_tx_gso_segment(skb, dev, &segs); ++ if (likely(result == EDMA_TX_GSO_NOT_NEEDED)) { ++ /* Transmit the packet. */ ++ ret = edma_tx_ring_xmit(dev, skb, txdesc_ring, stats); ++ ++ if (unlikely(ret == EDMA_TX_FAIL_NO_DESC)) { ++ if (likely(!edma_ctx->tx_requeue_stop)) { ++ cpu_id = smp_processor_id(); ++ netdev_dbg(dev, "Stopping tx queue due to lack oftx descriptors\n"); ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->tx_queue_stopped[cpu_id]; ++ u64_stats_update_end(&stats->syncp); ++ netif_tx_stop_queue(netdev_get_tx_queue(dev, skbq)); ++ return NETDEV_TX_BUSY; ++ } ++ } ++ ++ if (unlikely(ret != EDMA_TX_OK)) { ++ dev_kfree_skb_any(skb); ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->tx_drops; ++ u64_stats_update_end(&stats->syncp); ++ } ++ ++ return NETDEV_TX_OK; ++ } else if (unlikely(result == EDMA_TX_GSO_FAIL)) { ++ netdev_dbg(dev, "%p: SW GSO failed for segment size: %d\n", ++ skb, skb_shinfo(skb)->gso_segs); ++ dev_kfree_skb_any(skb); ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->tx_gso_drop_pkts; ++ u64_stats_update_end(&stats->syncp); ++ return NETDEV_TX_OK; ++ } ++ ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->tx_gso_pkts; ++ u64_stats_update_end(&stats->syncp); ++ ++ dev_kfree_skb_any(skb); ++ while (segs) { ++ skb = segs; ++ segs = segs->next; ++ ++ /* Transmit the packet. */ ++ ret = edma_tx_ring_xmit(dev, skb, txdesc_ring, stats); ++ if (unlikely(ret != EDMA_TX_OK)) { ++ dev_kfree_skb_any(skb); ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->tx_drops; ++ u64_stats_update_end(&stats->syncp); ++ } ++ } ++ ++ return NETDEV_TX_OK; ++} ++ + static void edma_port_get_stats64(struct net_device *netdev, + struct rtnl_link_stats64 *stats) + { +@@ -179,6 +310,7 @@ static int edma_port_set_mac_address(str + static const struct net_device_ops edma_port_netdev_ops = { + .ndo_open = edma_port_open, + .ndo_stop = edma_port_close, ++ .ndo_start_xmit = edma_port_xmit, + .ndo_get_stats64 = edma_port_get_stats64, + .ndo_set_mac_address = edma_port_set_mac_address, + .ndo_validate_addr = eth_validate_addr, +@@ -199,6 +331,7 @@ void edma_port_destroy(struct ppe_port * + int port_id = port->port_id; + struct net_device *netdev = edma_ctx->netdev_arr[port_id - 1]; + ++ edma_port_deconfigure(netdev); + edma_port_stats_free(netdev); + unregister_netdev(netdev); + free_netdev(netdev); +@@ -276,6 +409,8 @@ int edma_port_setup(struct ppe_port *por + */ + edma_ctx->netdev_arr[port_id - 1] = netdev; + ++ edma_port_configure(netdev); ++ + /* Setup phylink. */ + ret = ppe_port_phylink_setup(port, netdev); + if (ret) { +@@ -298,6 +433,7 @@ int edma_port_setup(struct ppe_port *por + register_netdev_fail: + ppe_port_phylink_destroy(port); + port_phylink_setup_fail: ++ edma_port_deconfigure(netdev); + edma_ctx->netdev_arr[port_id - 1] = NULL; + edma_port_stats_free(netdev); + stats_alloc_fail: +--- a/drivers/net/ethernet/qualcomm/ppe/edma_port.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_port.h +@@ -7,6 +7,8 @@ + + #include "ppe_port.h" + ++#define EDMA_PORT_MAX_CORE 4 ++ + #define EDMA_NETDEV_FEATURES (NETIF_F_FRAGLIST \ + | NETIF_F_SG \ + | NETIF_F_RXCSUM \ +@@ -35,11 +37,43 @@ struct edma_port_rx_stats { + }; + + /** ++ * struct edma_port_tx_stats - EDMA TX port per CPU stats for the port. ++ * @tx_pkts: Number of Tx packets ++ * @tx_bytes: Number of Tx bytes ++ * @tx_drops: Number of Tx drops ++ * @tx_nr_frag_pkts: Number of Tx nr_frag packets ++ * @tx_fraglist_pkts: Number of Tx fraglist packets ++ * @tx_fraglist_with_nr_frags_pkts: Number of Tx packets with fraglist and nr_frags ++ * @tx_tso_pkts: Number of Tx TSO packets ++ * @tx_tso_drop_pkts: Number of Tx TSO drop packets ++ * @tx_gso_pkts: Number of Tx GSO packets ++ * @tx_gso_drop_pkts: Number of Tx GSO drop packets ++ * @tx_queue_stopped: Number of Tx queue stopped packets ++ * @syncp: Synchronization pointer ++ */ ++struct edma_port_tx_stats { ++ u64 tx_pkts; ++ u64 tx_bytes; ++ u64 tx_drops; ++ u64 tx_nr_frag_pkts; ++ u64 tx_fraglist_pkts; ++ u64 tx_fraglist_with_nr_frags_pkts; ++ u64 tx_tso_pkts; ++ u64 tx_tso_drop_pkts; ++ u64 tx_gso_pkts; ++ u64 tx_gso_drop_pkts; ++ u64 tx_queue_stopped[EDMA_PORT_MAX_CORE]; ++ struct u64_stats_sync syncp; ++}; ++ ++/** + * struct edma_port_pcpu_stats - EDMA per cpu stats data structure for the port. + * @rx_stats: Per CPU Rx statistics ++ * @tx_stats: Per CPU Tx statistics + */ + struct edma_port_pcpu_stats { + struct edma_port_rx_stats __percpu *rx_stats; ++ struct edma_port_tx_stats __percpu *tx_stats; + }; + + /** +@@ -54,6 +88,7 @@ struct edma_port_priv { + struct ppe_port *ppe_port; + struct net_device *netdev; + struct edma_port_pcpu_stats pcpu_stats; ++ struct edma_txdesc_ring *txr_map[EDMA_PORT_MAX_CORE]; + unsigned long flags; + }; + +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_tx.c +@@ -0,0 +1,808 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* Provide APIs to alloc Tx Buffers, fill the Tx descriptors and transmit ++ * Scatter Gather and linear packets, Tx complete to free the skb after transmit. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "edma.h" ++#include "edma_cfg_tx.h" ++#include "edma_port.h" ++#include "ppe.h" ++#include "ppe_regs.h" ++ ++static u32 edma_tx_num_descs_for_sg(struct sk_buff *skb) ++{ ++ u32 nr_frags_first = 0, num_tx_desc_needed = 0; ++ ++ /* Check if we have enough Tx descriptors for SG. */ ++ if (unlikely(skb_shinfo(skb)->nr_frags)) { ++ nr_frags_first = skb_shinfo(skb)->nr_frags; ++ WARN_ON_ONCE(nr_frags_first > MAX_SKB_FRAGS); ++ num_tx_desc_needed += nr_frags_first; ++ } ++ ++ /* Walk through fraglist skbs making a note of nr_frags ++ * One Tx desc for fraglist skb. Fraglist skb may have ++ * further nr_frags. ++ */ ++ if (unlikely(skb_has_frag_list(skb))) { ++ struct sk_buff *iter_skb; ++ ++ skb_walk_frags(skb, iter_skb) { ++ u32 nr_frags = skb_shinfo(iter_skb)->nr_frags; ++ ++ WARN_ON_ONCE(nr_frags > MAX_SKB_FRAGS); ++ num_tx_desc_needed += (1 + nr_frags); ++ } ++ } ++ ++ return (num_tx_desc_needed + 1); ++} ++ ++/** ++ * edma_tx_gso_segment - Tx GSO. ++ * @skb: Socket Buffer. ++ * @netdev: Netdevice. ++ * @segs: SKB segments from GSO. ++ * ++ * Format skbs into GSOs. ++ * ++ * Return 1 on success, error code on failure. ++ */ ++enum edma_tx_gso_status edma_tx_gso_segment(struct sk_buff *skb, ++ struct net_device *netdev, struct sk_buff **segs) ++{ ++ u32 num_tx_desc_needed; ++ ++ /* Check is skb is non-linear to proceed. */ ++ if (likely(!skb_is_nonlinear(skb))) ++ return EDMA_TX_GSO_NOT_NEEDED; ++ ++ /* Check if TSO is enabled. If so, return as skb doesn't ++ * need to be segmented by linux. ++ */ ++ if (netdev->features & (NETIF_F_TSO | NETIF_F_TSO6)) { ++ num_tx_desc_needed = edma_tx_num_descs_for_sg(skb); ++ if (likely(num_tx_desc_needed <= EDMA_TX_TSO_SEG_MAX)) ++ return EDMA_TX_GSO_NOT_NEEDED; ++ } ++ ++ /* GSO segmentation of the skb into multiple segments. */ ++ *segs = skb_gso_segment(skb, netdev->features ++ & ~(NETIF_F_TSO | NETIF_F_TSO6)); ++ ++ /* Check for error in GSO segmentation. */ ++ if (IS_ERR_OR_NULL(*segs)) { ++ netdev_info(netdev, "Tx gso fail\n"); ++ return EDMA_TX_GSO_FAIL; ++ } ++ ++ return EDMA_TX_GSO_SUCCEED; ++} ++ ++/** ++ * edma_tx_complete - Reap Tx completion descriptors. ++ * @work_to_do: Work to do. ++ * @txcmpl_ring: Tx Completion ring. ++ * ++ * Reap Tx completion descriptors of the transmitted ++ * packets and free the corresponding SKBs. ++ * ++ * Return the number descriptors for which Tx complete is done. ++ */ ++u32 edma_tx_complete(u32 work_to_do, struct edma_txcmpl_ring *txcmpl_ring) ++{ ++ struct edma_txcmpl_stats *txcmpl_stats = &txcmpl_ring->txcmpl_stats; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 cons_idx, end_idx, data, cpu_id; ++ struct device *dev = ppe_dev->dev; ++ u32 avail, count, txcmpl_errors; ++ struct edma_txcmpl_desc *txcmpl; ++ u32 prod_idx = 0, more_bit = 0; ++ struct netdev_queue *nq; ++ struct sk_buff *skb; ++ u32 reg; ++ ++ cons_idx = txcmpl_ring->cons_idx; ++ ++ if (likely(txcmpl_ring->avail_pkt >= work_to_do)) { ++ avail = work_to_do; ++ } else { ++ /* Get TXCMPL ring producer index. */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXCMPL_PROD_IDX(txcmpl_ring->id); ++ regmap_read(regmap, reg, &data); ++ prod_idx = data & EDMA_TXCMPL_PROD_IDX_MASK; ++ ++ avail = EDMA_DESC_AVAIL_COUNT(prod_idx, cons_idx, EDMA_TX_RING_SIZE); ++ txcmpl_ring->avail_pkt = avail; ++ ++ if (unlikely(!avail)) { ++ dev_dbg(dev, "No available descriptors are pending for %d txcmpl ring\n", ++ txcmpl_ring->id); ++ u64_stats_update_begin(&txcmpl_stats->syncp); ++ ++txcmpl_stats->no_pending_desc; ++ u64_stats_update_end(&txcmpl_stats->syncp); ++ return 0; ++ } ++ ++ avail = min(avail, work_to_do); ++ } ++ ++ count = avail; ++ ++ end_idx = (cons_idx + avail) & EDMA_TX_RING_SIZE_MASK; ++ txcmpl = EDMA_TXCMPL_DESC(txcmpl_ring, cons_idx); ++ ++ /* Instead of freeing the skb, it might be better to save and use ++ * for Rxfill. ++ */ ++ while (likely(avail--)) { ++ /* The last descriptor holds the SKB pointer for scattered frames. ++ * So skip the descriptors with more bit set. ++ */ ++ more_bit = EDMA_TXCMPL_MORE_BIT_GET(txcmpl); ++ if (unlikely(more_bit)) { ++ u64_stats_update_begin(&txcmpl_stats->syncp); ++ ++txcmpl_stats->desc_with_more_bit; ++ u64_stats_update_end(&txcmpl_stats->syncp); ++ cons_idx = ((cons_idx + 1) & EDMA_TX_RING_SIZE_MASK); ++ txcmpl = EDMA_TXCMPL_DESC(txcmpl_ring, cons_idx); ++ continue; ++ } ++ ++ /* Find and free the skb for Tx completion. */ ++ skb = (struct sk_buff *)EDMA_TXCMPL_OPAQUE_GET(txcmpl); ++ if (unlikely(!skb)) { ++ if (net_ratelimit()) ++ dev_warn(dev, "Invalid cons_idx:%u prod_idx:%u word2:%x word3:%x\n", ++ cons_idx, prod_idx, txcmpl->word2, txcmpl->word3); ++ ++ u64_stats_update_begin(&txcmpl_stats->syncp); ++ ++txcmpl_stats->invalid_buffer; ++ u64_stats_update_end(&txcmpl_stats->syncp); ++ } else { ++ dev_dbg(dev, "TXCMPL: skb:%p, skb->len %d, skb->data_len %d, cons_idx:%d prod_idx:%d word2:0x%x word3:0x%x\n", ++ skb, skb->len, skb->data_len, cons_idx, prod_idx, ++ txcmpl->word2, txcmpl->word3); ++ ++ txcmpl_errors = EDMA_TXCOMP_RING_ERROR_GET(txcmpl->word3); ++ if (unlikely(txcmpl_errors)) { ++ if (net_ratelimit()) ++ dev_err(dev, "Error 0x%0x observed in tx complete %d ring\n", ++ txcmpl_errors, txcmpl_ring->id); ++ ++ u64_stats_update_begin(&txcmpl_stats->syncp); ++ ++txcmpl_stats->errors; ++ u64_stats_update_end(&txcmpl_stats->syncp); ++ } ++ ++ /* Retrieve pool id for unmapping. ++ * 0 for linear skb and (pool id - 1) represents nr_frag index. ++ */ ++ if (!EDMA_TXCOMP_POOL_ID_GET(txcmpl)) { ++ dma_unmap_single(dev, virt_to_phys(skb->data), ++ skb->len, DMA_TO_DEVICE); ++ } else { ++ u8 frag_index = (EDMA_TXCOMP_POOL_ID_GET(txcmpl) - 1); ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_index]; ++ ++ dma_unmap_page(dev, virt_to_phys(frag), ++ PAGE_SIZE, DMA_TO_DEVICE); ++ } ++ ++ dev_kfree_skb(skb); ++ } ++ ++ cons_idx = ((cons_idx + 1) & EDMA_TX_RING_SIZE_MASK); ++ txcmpl = EDMA_TXCMPL_DESC(txcmpl_ring, cons_idx); ++ } ++ ++ txcmpl_ring->cons_idx = cons_idx; ++ txcmpl_ring->avail_pkt -= count; ++ ++ dev_dbg(dev, "TXCMPL:%u count:%u prod_idx:%u cons_idx:%u\n", ++ txcmpl_ring->id, count, prod_idx, cons_idx); ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXCMPL_CONS_IDX(txcmpl_ring->id); ++ regmap_write(regmap, reg, cons_idx); ++ ++ /* If tx_requeue_stop disabled (tx_requeue_stop = 0) ++ * Fetch the tx queue of interface and check if it is stopped. ++ * if queue is stopped and interface is up, wake up this queue. ++ */ ++ if (unlikely(!edma_ctx->tx_requeue_stop)) { ++ cpu_id = smp_processor_id(); ++ nq = netdev_get_tx_queue(txcmpl_ring->napi.dev, cpu_id); ++ if (unlikely(netif_tx_queue_stopped(nq)) && ++ netif_carrier_ok(txcmpl_ring->napi.dev)) { ++ dev_dbg(dev, "Waking queue number %d, for interface %s\n", ++ cpu_id, txcmpl_ring->napi.dev->name); ++ __netif_tx_lock(nq, cpu_id); ++ netif_tx_wake_queue(nq); ++ __netif_tx_unlock(nq); ++ } ++ } ++ ++ return count; ++} ++ ++/** ++ * edma_tx_napi_poll - EDMA TX NAPI handler. ++ * @napi: NAPI structure. ++ * @budget: Tx NAPI Budget. ++ * ++ * EDMA TX NAPI handler. ++ */ ++int edma_tx_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct edma_txcmpl_ring *txcmpl_ring = (struct edma_txcmpl_ring *)napi; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 txcmpl_intr_status; ++ int work_done = 0; ++ u32 data, reg; ++ ++ do { ++ work_done += edma_tx_complete(budget - work_done, txcmpl_ring); ++ if (work_done >= budget) ++ return work_done; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TX_INT_STAT(txcmpl_ring->id); ++ regmap_read(regmap, reg, &data); ++ txcmpl_intr_status = data & EDMA_TXCMPL_RING_INT_STATUS_MASK; ++ } while (txcmpl_intr_status); ++ ++ /* No more packets to process. Finish NAPI processing. */ ++ napi_complete(napi); ++ ++ /* Set TXCMPL ring interrupt mask. */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TX_INT_MASK(txcmpl_ring->id); ++ regmap_write(regmap, reg, edma_ctx->intr_info.intr_mask_txcmpl); ++ ++ return work_done; ++} ++ ++/** ++ * edma_tx_handle_irq - Tx IRQ Handler. ++ * @irq: Interrupt request. ++ * @ctx: Context. ++ * ++ * Process TX IRQ and schedule NAPI. ++ * ++ * Return IRQ handler code. ++ */ ++irqreturn_t edma_tx_handle_irq(int irq, void *ctx) ++{ ++ struct edma_txcmpl_ring *txcmpl_ring = (struct edma_txcmpl_ring *)ctx; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 reg; ++ ++ pr_debug("irq: irq=%d txcmpl_ring_id=%u\n", irq, txcmpl_ring->id); ++ if (likely(napi_schedule_prep(&txcmpl_ring->napi))) { ++ /* Disable TxCmpl intr. */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TX_INT_MASK(txcmpl_ring->id); ++ regmap_write(regmap, reg, EDMA_MASK_INT_DISABLE); ++ __napi_schedule(&txcmpl_ring->napi); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static void edma_tx_dma_unmap_frags(struct sk_buff *skb, u32 nr_frags) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct device *dev = ppe_dev->dev; ++ u32 buf_len = 0; ++ u8 i = 0; ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags - nr_frags; i++) { ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ ++ /* DMA mapping was not done for zero size segments. */ ++ buf_len = skb_frag_size(frag); ++ if (unlikely(buf_len == 0)) ++ continue; ++ ++ dma_unmap_page(dev, virt_to_phys(frag), PAGE_SIZE, ++ DMA_TO_DEVICE); ++ } ++} ++ ++static u32 edma_tx_skb_nr_frags(struct edma_txdesc_ring *txdesc_ring, ++ struct edma_txdesc_pri **txdesc, struct sk_buff *skb, ++ u32 *hw_next_to_use, u32 *invalid_frag) ++{ ++ u32 nr_frags = 0, buf_len = 0, num_descs = 0, start_idx = 0, end_idx = 0; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ u32 start_hw_next_to_use = *hw_next_to_use; ++ struct edma_txdesc_pri *txd = *txdesc; ++ struct device *dev = ppe_dev->dev; ++ u8 i = 0; ++ ++ /* Hold onto the index mapped to *txdesc. ++ * This will be the index previous to that of current *hw_next_to_use. ++ */ ++ start_idx = (((*hw_next_to_use) + EDMA_TX_RING_SIZE_MASK) ++ & EDMA_TX_RING_SIZE_MASK); ++ ++ /* Handle if the skb has nr_frags. */ ++ nr_frags = skb_shinfo(skb)->nr_frags; ++ num_descs = nr_frags; ++ i = 0; ++ ++ while (nr_frags--) { ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ dma_addr_t buff_addr; ++ ++ buf_len = skb_frag_size(frag); ++ ++ /* Zero size segment can lead EDMA HW to hang so, we don't want to ++ * process them. Zero size segment can happen during TSO operation ++ * if there is nothing but header in the primary segment. ++ */ ++ if (unlikely(buf_len == 0)) { ++ num_descs--; ++ i++; ++ continue; ++ } ++ ++ /* Setting the MORE bit on the previous Tx descriptor. ++ * Note: We will flush this descriptor as well later. ++ */ ++ EDMA_TXDESC_MORE_BIT_SET(txd, 1); ++ EDMA_TXDESC_ENDIAN_SET(txd); ++ ++ txd = EDMA_TXDESC_PRI_DESC(txdesc_ring, *hw_next_to_use); ++ memset(txd, 0, sizeof(struct edma_txdesc_pri)); ++ buff_addr = skb_frag_dma_map(dev, frag, 0, buf_len, ++ DMA_TO_DEVICE); ++ if (dma_mapping_error(dev, buff_addr)) { ++ dev_dbg(dev, "Unable to dma first descriptor for nr_frags tx\n"); ++ *hw_next_to_use = start_hw_next_to_use; ++ *invalid_frag = nr_frags; ++ return 0; ++ } ++ ++ EDMA_TXDESC_BUFFER_ADDR_SET(txd, buff_addr); ++ EDMA_TXDESC_DATA_LEN_SET(txd, buf_len); ++ EDMA_TXDESC_POOL_ID_SET(txd, (i + 1)); ++ ++ *hw_next_to_use = ((*hw_next_to_use + 1) & EDMA_TX_RING_SIZE_MASK); ++ i++; ++ } ++ ++ EDMA_TXDESC_ENDIAN_SET(txd); ++ ++ /* This will be the index previous to that of current *hw_next_to_use. */ ++ end_idx = (((*hw_next_to_use) + EDMA_TX_RING_SIZE_MASK) & EDMA_TX_RING_SIZE_MASK); ++ ++ *txdesc = txd; ++ ++ return num_descs; ++} ++ ++static void edma_tx_fill_pp_desc(struct edma_port_priv *port_priv, ++ struct edma_txdesc_pri *txd, struct sk_buff *skb, ++ struct edma_port_tx_stats *stats) ++{ ++ struct ppe_port *port = port_priv->ppe_port; ++ int port_id = port->port_id; ++ ++ /* Offload L3/L4 checksum computation. */ ++ if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { ++ EDMA_TXDESC_ADV_OFFLOAD_SET(txd); ++ EDMA_TXDESC_IP_CSUM_SET(txd); ++ EDMA_TXDESC_L4_CSUM_SET(txd); ++ } ++ ++ /* Check if the packet needs TSO ++ * This will be mostly true for SG packets. ++ */ ++ if (unlikely(skb_is_gso(skb))) { ++ if ((skb_shinfo(skb)->gso_type == SKB_GSO_TCPV4) || ++ (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6)) { ++ u32 mss = skb_shinfo(skb)->gso_size; ++ ++ /* If MSS<256, HW will do TSO using MSS=256, ++ * if MSS>10K, HW will do TSO using MSS=10K, ++ * else HW will report error 0x200000 in Tx Cmpl. ++ */ ++ if (mss < EDMA_TX_TSO_MSS_MIN) ++ mss = EDMA_TX_TSO_MSS_MIN; ++ else if (mss > EDMA_TX_TSO_MSS_MAX) ++ mss = EDMA_TX_TSO_MSS_MAX; ++ ++ EDMA_TXDESC_TSO_ENABLE_SET(txd, 1); ++ EDMA_TXDESC_MSS_SET(txd, mss); ++ ++ /* Update tso stats. */ ++ u64_stats_update_begin(&stats->syncp); ++ stats->tx_tso_pkts++; ++ u64_stats_update_end(&stats->syncp); ++ } ++ } ++ ++ /* Set destination information in the descriptor. */ ++ EDMA_TXDESC_SERVICE_CODE_SET(txd, PPE_EDMA_SC_BYPASS_ID); ++ EDMA_DST_INFO_SET(txd, port_id); ++} ++ ++static struct edma_txdesc_pri *edma_tx_skb_first_desc(struct edma_port_priv *port_priv, ++ struct edma_txdesc_ring *txdesc_ring, ++ struct sk_buff *skb, u32 *hw_next_to_use, ++ struct edma_port_tx_stats *stats) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct edma_txdesc_pri *txd = NULL; ++ struct device *dev = ppe_dev->dev; ++ dma_addr_t buff_addr; ++ u32 buf_len = 0; ++ ++ /* Get the packet length. */ ++ buf_len = skb_headlen(skb); ++ txd = EDMA_TXDESC_PRI_DESC(txdesc_ring, *hw_next_to_use); ++ memset(txd, 0, sizeof(struct edma_txdesc_pri)); ++ ++ /* Set the data pointer as the buffer address in the descriptor. */ ++ buff_addr = dma_map_single(dev, skb->data, buf_len, DMA_TO_DEVICE); ++ if (dma_mapping_error(dev, buff_addr)) { ++ dev_dbg(dev, "Unable to dma first descriptor for tx\n"); ++ return NULL; ++ } ++ ++ EDMA_TXDESC_BUFFER_ADDR_SET(txd, buff_addr); ++ EDMA_TXDESC_POOL_ID_SET(txd, 0); ++ edma_tx_fill_pp_desc(port_priv, txd, skb, stats); ++ ++ /* Set packet length in the descriptor. */ ++ EDMA_TXDESC_DATA_LEN_SET(txd, buf_len); ++ *hw_next_to_use = (*hw_next_to_use + 1) & EDMA_TX_RING_SIZE_MASK; ++ ++ return txd; ++} ++ ++static void edma_tx_handle_dma_err(struct sk_buff *skb, u32 num_sg_frag_list) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct device *dev = ppe_dev->dev; ++ struct sk_buff *iter_skb = NULL; ++ u32 cnt_sg_frag_list = 0; ++ ++ /* Walk through all fraglist skbs. */ ++ skb_walk_frags(skb, iter_skb) { ++ if (skb_headlen(iter_skb)) { ++ dma_unmap_single(dev, virt_to_phys(iter_skb->data), ++ skb_headlen(iter_skb), DMA_TO_DEVICE); ++ cnt_sg_frag_list += 1; ++ } ++ ++ if (cnt_sg_frag_list == num_sg_frag_list) ++ return; ++ ++ /* skb fraglist skb had nr_frags, unmap that memory. */ ++ u32 nr_frags = skb_shinfo(iter_skb)->nr_frags; ++ ++ if (nr_frags == 0) ++ continue; ++ ++ for (int i = 0; i < nr_frags; i++) { ++ skb_frag_t *frag = &skb_shinfo(iter_skb)->frags[i]; ++ ++ /* DMA mapping was not done for zero size segments. */ ++ if (unlikely(skb_frag_size(frag) == 0)) ++ continue; ++ ++ dma_unmap_page(dev, virt_to_phys(frag), ++ PAGE_SIZE, DMA_TO_DEVICE); ++ cnt_sg_frag_list += 1; ++ if (cnt_sg_frag_list == num_sg_frag_list) ++ return; ++ } ++ } ++} ++ ++static u32 edma_tx_skb_sg_fill_desc(struct edma_txdesc_ring *txdesc_ring, ++ struct edma_txdesc_pri **txdesc, ++ struct sk_buff *skb, u32 *hw_next_to_use, ++ struct edma_port_tx_stats *stats) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ u32 start_hw_next_to_use = 0, invalid_frag = 0; ++ struct edma_txdesc_pri *txd = *txdesc; ++ struct device *dev = ppe_dev->dev; ++ struct sk_buff *iter_skb = NULL; ++ u32 buf_len = 0, num_descs = 0; ++ u32 num_sg_frag_list = 0; ++ ++ /* Head skb processed already. */ ++ num_descs++; ++ ++ if (unlikely(skb_has_frag_list(skb))) { ++ struct edma_txdesc_pri *start_desc = NULL; ++ u32 start_idx = 0, end_idx = 0; ++ ++ /* Hold onto the index mapped to txd. ++ * This will be the index previous to that of current *hw_next_to_use. ++ */ ++ start_idx = (((*hw_next_to_use) + EDMA_TX_RING_SIZE_MASK) ++ & EDMA_TX_RING_SIZE_MASK); ++ start_desc = txd; ++ start_hw_next_to_use = *hw_next_to_use; ++ ++ /* Walk through all fraglist skbs. */ ++ skb_walk_frags(skb, iter_skb) { ++ dma_addr_t buff_addr; ++ u32 num_nr_frag = 0; ++ ++ /* This case could happen during the packet decapsulation. ++ * All header content might be removed. ++ */ ++ buf_len = skb_headlen(iter_skb); ++ if (unlikely(buf_len == 0)) ++ goto skip_primary; ++ ++ /* We make sure to flush this descriptor later. */ ++ EDMA_TXDESC_MORE_BIT_SET(txd, 1); ++ EDMA_TXDESC_ENDIAN_SET(txd); ++ ++ txd = EDMA_TXDESC_PRI_DESC(txdesc_ring, *hw_next_to_use); ++ memset(txd, 0, sizeof(struct edma_txdesc_pri)); ++ buff_addr = dma_map_single(dev, iter_skb->data, ++ buf_len, DMA_TO_DEVICE); ++ if (dma_mapping_error(dev, buff_addr)) { ++ dev_dbg(dev, "Unable to dma for fraglist\n"); ++ goto dma_err; ++ } ++ ++ EDMA_TXDESC_BUFFER_ADDR_SET(txd, buff_addr); ++ EDMA_TXDESC_DATA_LEN_SET(txd, buf_len); ++ EDMA_TXDESC_POOL_ID_SET(txd, 0); ++ ++ *hw_next_to_use = (*hw_next_to_use + 1) & EDMA_TX_RING_SIZE_MASK; ++ num_descs += 1; ++ num_sg_frag_list += 1; ++ ++ /* skb fraglist skb can have nr_frags. */ ++skip_primary: ++ if (unlikely(skb_shinfo(iter_skb)->nr_frags)) { ++ num_nr_frag = edma_tx_skb_nr_frags(txdesc_ring, &txd, ++ iter_skb, hw_next_to_use, ++ &invalid_frag); ++ if (unlikely(!num_nr_frag)) { ++ dev_dbg(dev, "No descriptor available for ring %d\n", ++ txdesc_ring->id); ++ edma_tx_dma_unmap_frags(iter_skb, invalid_frag); ++ goto dma_err; ++ } ++ ++ num_descs += num_nr_frag; ++ num_sg_frag_list += num_nr_frag; ++ ++ /* Update fraglist with nr_frag stats. */ ++ u64_stats_update_begin(&stats->syncp); ++ stats->tx_fraglist_with_nr_frags_pkts++; ++ u64_stats_update_end(&stats->syncp); ++ } ++ } ++ ++ EDMA_TXDESC_ENDIAN_SET(txd); ++ ++ /* This will be the index previous to ++ * that of current *hw_next_to_use. ++ */ ++ end_idx = (((*hw_next_to_use) + EDMA_TX_RING_SIZE_MASK) & ++ EDMA_TX_RING_SIZE_MASK); ++ ++ /* Update frag_list stats. */ ++ u64_stats_update_begin(&stats->syncp); ++ stats->tx_fraglist_pkts++; ++ u64_stats_update_end(&stats->syncp); ++ } else { ++ /* Process skb with nr_frags. */ ++ num_descs += edma_tx_skb_nr_frags(txdesc_ring, &txd, skb, ++ hw_next_to_use, &invalid_frag); ++ if (unlikely(!num_descs)) { ++ dev_dbg(dev, "No descriptor available for ring %d\n", txdesc_ring->id); ++ edma_tx_dma_unmap_frags(skb, invalid_frag); ++ *txdesc = NULL; ++ return num_descs; ++ } ++ ++ u64_stats_update_begin(&stats->syncp); ++ stats->tx_nr_frag_pkts++; ++ u64_stats_update_end(&stats->syncp); ++ } ++ ++ dev_dbg(dev, "skb:%p num_descs_filled: %u, nr_frags %u, frag_list fragments %u\n", ++ skb, num_descs, skb_shinfo(skb)->nr_frags, num_sg_frag_list); ++ ++ *txdesc = txd; ++ ++ return num_descs; ++ ++dma_err: ++ if (!num_sg_frag_list) ++ goto reset_state; ++ ++ edma_tx_handle_dma_err(skb, num_sg_frag_list); ++ ++reset_state: ++ *hw_next_to_use = start_hw_next_to_use; ++ *txdesc = NULL; ++ ++ return 0; ++} ++ ++static u32 edma_tx_avail_desc(struct edma_txdesc_ring *txdesc_ring, ++ u32 hw_next_to_use) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ u32 data = 0, avail = 0, hw_next_to_clean = 0; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 reg; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id); ++ regmap_read(regmap, reg, &data); ++ hw_next_to_clean = data & EDMA_TXDESC_CONS_IDX_MASK; ++ ++ avail = EDMA_DESC_AVAIL_COUNT(hw_next_to_clean - 1, ++ hw_next_to_use, EDMA_TX_RING_SIZE); ++ ++ return avail; ++} ++ ++/** ++ * edma_tx_ring_xmit - Transmit a packet. ++ * @netdev: Netdevice. ++ * @skb: Socket Buffer. ++ * @txdesc_ring: Tx Descriptor ring. ++ * @stats: EDMA Tx Statistics. ++ * ++ * Check for available descriptors, fill the descriptors ++ * and transmit both linear and non linear packets. ++ * ++ * Return 0 on success, negative error code on failure. ++ */ ++enum edma_tx_status edma_tx_ring_xmit(struct net_device *netdev, ++ struct sk_buff *skb, struct edma_txdesc_ring *txdesc_ring, ++ struct edma_port_tx_stats *stats) ++{ ++ struct edma_txdesc_stats *txdesc_stats = &txdesc_ring->txdesc_stats; ++ struct edma_port_priv *port_priv = netdev_priv(netdev); ++ u32 num_tx_desc_needed = 0, num_desc_filled = 0; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct ppe_port *port = port_priv->ppe_port; ++ struct regmap *regmap = ppe_dev->regmap; ++ struct edma_txdesc_pri *txdesc = NULL; ++ struct device *dev = ppe_dev->dev; ++ int port_id = port->port_id; ++ u32 hw_next_to_use = 0; ++ u32 reg; ++ ++ hw_next_to_use = txdesc_ring->prod_idx; ++ ++ if (unlikely(!(txdesc_ring->avail_desc))) { ++ txdesc_ring->avail_desc = edma_tx_avail_desc(txdesc_ring, ++ hw_next_to_use); ++ if (unlikely(!txdesc_ring->avail_desc)) { ++ netdev_dbg(netdev, "No available descriptors are present at %d ring\n", ++ txdesc_ring->id); ++ ++ u64_stats_update_begin(&txdesc_stats->syncp); ++ ++txdesc_stats->no_desc_avail; ++ u64_stats_update_end(&txdesc_stats->syncp); ++ return EDMA_TX_FAIL_NO_DESC; ++ } ++ } ++ ++ /* Process head skb for linear skb. ++ * Process head skb + nr_frags + fraglist for non linear skb. ++ */ ++ if (likely(!skb_is_nonlinear(skb))) { ++ txdesc = edma_tx_skb_first_desc(port_priv, txdesc_ring, skb, ++ &hw_next_to_use, stats); ++ if (unlikely(!txdesc)) { ++ netdev_dbg(netdev, "No descriptor available for ring %d\n", ++ txdesc_ring->id); ++ u64_stats_update_begin(&txdesc_stats->syncp); ++ ++txdesc_stats->no_desc_avail; ++ u64_stats_update_end(&txdesc_stats->syncp); ++ return EDMA_TX_FAIL_NO_DESC; ++ } ++ ++ EDMA_TXDESC_ENDIAN_SET(txdesc); ++ num_desc_filled++; ++ } else { ++ num_tx_desc_needed = edma_tx_num_descs_for_sg(skb); ++ ++ /* HW does not support TSO for packets with more than 32 segments. ++ * HW hangs up if it sees more than 32 segments. Kernel Perform GSO ++ * for such packets with netdev gso_max_segs set to 32. ++ */ ++ if (unlikely(num_tx_desc_needed > EDMA_TX_TSO_SEG_MAX)) { ++ netdev_dbg(netdev, "Number of segments %u more than %u for %d ring\n", ++ num_tx_desc_needed, EDMA_TX_TSO_SEG_MAX, txdesc_ring->id); ++ u64_stats_update_begin(&txdesc_stats->syncp); ++ ++txdesc_stats->tso_max_seg_exceed; ++ u64_stats_update_end(&txdesc_stats->syncp); ++ ++ u64_stats_update_begin(&stats->syncp); ++ stats->tx_tso_drop_pkts++; ++ u64_stats_update_end(&stats->syncp); ++ ++ return EDMA_TX_FAIL; ++ } ++ ++ if (unlikely(num_tx_desc_needed > txdesc_ring->avail_desc)) { ++ txdesc_ring->avail_desc = edma_tx_avail_desc(txdesc_ring, ++ hw_next_to_use); ++ if (num_tx_desc_needed > txdesc_ring->avail_desc) { ++ u64_stats_update_begin(&txdesc_stats->syncp); ++ ++txdesc_stats->no_desc_avail; ++ u64_stats_update_end(&txdesc_stats->syncp); ++ netdev_dbg(netdev, "Not enough available descriptors are present at %d ring for SG packet. Needed %d, currently available %d\n", ++ txdesc_ring->id, num_tx_desc_needed, ++ txdesc_ring->avail_desc); ++ return EDMA_TX_FAIL_NO_DESC; ++ } ++ } ++ ++ txdesc = edma_tx_skb_first_desc(port_priv, txdesc_ring, skb, ++ &hw_next_to_use, stats); ++ if (unlikely(!txdesc)) { ++ netdev_dbg(netdev, "No non-linear descriptor available for ring %d\n", ++ txdesc_ring->id); ++ u64_stats_update_begin(&txdesc_stats->syncp); ++ ++txdesc_stats->no_desc_avail; ++ u64_stats_update_end(&txdesc_stats->syncp); ++ return EDMA_TX_FAIL_NO_DESC; ++ } ++ ++ num_desc_filled = edma_tx_skb_sg_fill_desc(txdesc_ring, ++ &txdesc, skb, &hw_next_to_use, stats); ++ if (unlikely(!txdesc)) { ++ netdev_dbg(netdev, "No descriptor available for ring %d\n", ++ txdesc_ring->id); ++ dma_unmap_single(dev, virt_to_phys(skb->data), ++ skb->len, DMA_TO_DEVICE); ++ u64_stats_update_begin(&txdesc_stats->syncp); ++ ++txdesc_stats->no_desc_avail; ++ u64_stats_update_end(&txdesc_stats->syncp); ++ return EDMA_TX_FAIL_NO_DESC; ++ } ++ } ++ ++ /* Set the skb pointer to the descriptor's opaque field/s ++ * on the last descriptor of the packet/SG packet. ++ */ ++ EDMA_TXDESC_OPAQUE_SET(txdesc, skb); ++ ++ /* Update producer index. */ ++ txdesc_ring->prod_idx = hw_next_to_use & EDMA_TXDESC_PROD_IDX_MASK; ++ txdesc_ring->avail_desc -= num_desc_filled; ++ ++ netdev_dbg(netdev, "%s: skb:%p tx_ring:%u proto:0x%x skb->len:%d\n port:%u prod_idx:%u ip_summed:0x%x\n", ++ netdev->name, skb, txdesc_ring->id, ntohs(skb->protocol), ++ skb->len, port_id, hw_next_to_use, skb->ip_summed); ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id); ++ regmap_write(regmap, reg, txdesc_ring->prod_idx); ++ ++ u64_stats_update_begin(&stats->syncp); ++ stats->tx_pkts++; ++ stats->tx_bytes += skb->len; ++ u64_stats_update_end(&stats->syncp); ++ ++ return EDMA_TX_OK; ++} +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_tx.h +@@ -0,0 +1,302 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#ifndef __EDMA_TX__ ++#define __EDMA_TX__ ++ ++#include "edma_port.h" ++ ++#define EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[(i)])) ++#define EDMA_GET_PDESC(R, i, type) (&(((type *)((R)->pdesc))[(i)])) ++#define EDMA_GET_SDESC(R, i, type) (&(((type *)((R)->sdesc))[(i)])) ++#define EDMA_TXCMPL_DESC(R, i) EDMA_GET_DESC(R, i, \ ++ struct edma_txcmpl_desc) ++#define EDMA_TXDESC_PRI_DESC(R, i) EDMA_GET_PDESC(R, i, \ ++ struct edma_txdesc_pri) ++#define EDMA_TXDESC_SEC_DESC(R, i) EDMA_GET_SDESC(R, i, \ ++ struct edma_txdesc_sec) ++ ++#define EDMA_DESC_AVAIL_COUNT(head, tail, _max) ({ \ ++ typeof(_max) (max) = (_max); \ ++ ((((head) - (tail)) + \ ++ (max)) & ((max) - 1)); }) ++ ++#define EDMA_TX_RING_SIZE 2048 ++#define EDMA_TX_RING_SIZE_MASK (EDMA_TX_RING_SIZE - 1) ++ ++/* Max segment processing capacity of HW for TSO. */ ++#define EDMA_TX_TSO_SEG_MAX 32 ++ ++/* HW defined low and high MSS size. */ ++#define EDMA_TX_TSO_MSS_MIN 256 ++#define EDMA_TX_TSO_MSS_MAX 10240 ++ ++#define EDMA_DST_PORT_TYPE 2 ++#define EDMA_DST_PORT_TYPE_SHIFT 28 ++#define EDMA_DST_PORT_TYPE_MASK (0xf << EDMA_DST_PORT_TYPE_SHIFT) ++#define EDMA_DST_PORT_ID_SHIFT 16 ++#define EDMA_DST_PORT_ID_MASK (0xfff << EDMA_DST_PORT_ID_SHIFT) ++ ++#define EDMA_DST_PORT_TYPE_SET(x) (((x) << EDMA_DST_PORT_TYPE_SHIFT) & \ ++ EDMA_DST_PORT_TYPE_MASK) ++#define EDMA_DST_PORT_ID_SET(x) (((x) << EDMA_DST_PORT_ID_SHIFT) & \ ++ EDMA_DST_PORT_ID_MASK) ++#define EDMA_DST_INFO_SET(desc, x) ((desc)->word4 |= \ ++ (EDMA_DST_PORT_TYPE_SET(EDMA_DST_PORT_TYPE) | EDMA_DST_PORT_ID_SET(x))) ++ ++#define EDMA_TXDESC_TSO_ENABLE_MASK BIT(24) ++#define EDMA_TXDESC_TSO_ENABLE_SET(desc, x) ((desc)->word5 |= \ ++ FIELD_PREP(EDMA_TXDESC_TSO_ENABLE_MASK, x)) ++#define EDMA_TXDESC_MSS_MASK GENMASK(31, 16) ++#define EDMA_TXDESC_MSS_SET(desc, x) ((desc)->word6 |= \ ++ FIELD_PREP(EDMA_TXDESC_MSS_MASK, x)) ++#define EDMA_TXDESC_MORE_BIT_MASK BIT(30) ++#define EDMA_TXDESC_MORE_BIT_SET(desc, x) ((desc)->word1 |= \ ++ FIELD_PREP(EDMA_TXDESC_MORE_BIT_MASK, x)) ++ ++#define EDMA_TXDESC_ADV_OFFSET_BIT BIT(31) ++#define EDMA_TXDESC_ADV_OFFLOAD_SET(desc) ((desc)->word5 |= \ ++ FIELD_PREP(EDMA_TXDESC_ADV_OFFSET_BIT, 1)) ++#define EDMA_TXDESC_IP_CSUM_BIT BIT(25) ++#define EDMA_TXDESC_IP_CSUM_SET(desc) ((desc)->word5 |= \ ++ FIELD_PREP(EDMA_TXDESC_IP_CSUM_BIT, 1)) ++ ++#define EDMA_TXDESC_L4_CSUM_SET_MASK GENMASK(27, 26) ++#define EDMA_TXDESC_L4_CSUM_SET(desc) ((desc)->word5 |= \ ++ (FIELD_PREP(EDMA_TXDESC_L4_CSUM_SET_MASK, 1))) ++ ++#define EDMA_TXDESC_POOL_ID_SET_MASK GENMASK(24, 18) ++#define EDMA_TXDESC_POOL_ID_SET(desc, x) ((desc)->word5 |= \ ++ (FIELD_PREP(EDMA_TXDESC_POOL_ID_SET_MASK, x))) ++ ++#define EDMA_TXDESC_DATA_LEN_SET(desc, x) ((desc)->word5 |= ((x) & 0x1ffff)) ++#define EDMA_TXDESC_SERVICE_CODE_MASK GENMASK(24, 16) ++#define EDMA_TXDESC_SERVICE_CODE_SET(desc, x) ((desc)->word1 |= \ ++ (FIELD_PREP(EDMA_TXDESC_SERVICE_CODE_MASK, x))) ++#define EDMA_TXDESC_BUFFER_ADDR_SET(desc, addr) (((desc)->word0) = (addr)) ++ ++#ifdef __LP64__ ++#define EDMA_TXDESC_OPAQUE_GET(_desc) ({ \ ++ typeof(_desc) (desc) = (_desc); \ ++ (((u64)(desc)->word3 << 32) | (desc)->word2); }) ++ ++#define EDMA_TXCMPL_OPAQUE_GET(_desc) ({ \ ++ typeof(_desc) (desc) = (_desc); \ ++ (((u64)(desc)->word1 << 32) | \ ++ (desc)->word0); }) ++ ++#define EDMA_TXDESC_OPAQUE_LO_SET(desc, ptr) ((desc)->word2 = \ ++ (u32)(uintptr_t)(ptr)) ++ ++#define EDMA_TXDESC_OPAQUE_HI_SET(desc, ptr) ((desc)->word3 = \ ++ (u32)((u64)(ptr) >> 32)) ++ ++#define EDMA_TXDESC_OPAQUE_SET(_desc, _ptr) do { \ ++ typeof(_desc) (desc) = (_desc); \ ++ typeof(_ptr) (ptr) = (_ptr); \ ++ EDMA_TXDESC_OPAQUE_LO_SET(desc, ptr); \ ++ EDMA_TXDESC_OPAQUE_HI_SET(desc, ptr); \ ++} while (0) ++#else ++#define EDMA_TXCMPL_OPAQUE_GET(desc) ((desc)->word0) ++#define EDMA_TXDESC_OPAQUE_GET(desc) ((desc)->word2) ++#define EDMA_TXDESC_OPAQUE_LO_SET(desc, ptr) ((desc)->word2 = (u32)(uintptr_t)ptr) ++ ++#define EDMA_TXDESC_OPAQUE_SET(desc, ptr) \ ++ EDMA_TXDESC_OPAQUE_LO_SET(desc, ptr) ++#endif ++#define EDMA_TXCMPL_MORE_BIT_MASK BIT(30) ++ ++#define EDMA_TXCMPL_MORE_BIT_GET(desc) ((le32_to_cpu((__force __le32)((desc)->word2))) & \ ++ EDMA_TXCMPL_MORE_BIT_MASK) ++ ++#define EDMA_TXCOMP_RING_ERROR_MASK GENMASK(22, 0) ++ ++#define EDMA_TXCOMP_RING_ERROR_GET(x) ((le32_to_cpu((__force __le32)x)) & \ ++ EDMA_TXCOMP_RING_ERROR_MASK) ++ ++#define EDMA_TXCOMP_POOL_ID_MASK GENMASK(5, 0) ++ ++#define EDMA_TXCOMP_POOL_ID_GET(desc) ((le32_to_cpu((__force __le32)((desc)->word2))) & \ ++ EDMA_TXCOMP_POOL_ID_MASK) ++ ++/* Opaque values are set in word2 and word3, ++ * they are not accessed by the EDMA HW, ++ * so endianness conversion is not needed. ++ */ ++#define EDMA_TXDESC_ENDIAN_SET(_desc) ({ \ ++ typeof(_desc) (desc) = (_desc); \ ++ cpu_to_le32s(&((desc)->word0)); \ ++ cpu_to_le32s(&((desc)->word1)); \ ++ cpu_to_le32s(&((desc)->word4)); \ ++ cpu_to_le32s(&((desc)->word5)); \ ++ cpu_to_le32s(&((desc)->word6)); \ ++ cpu_to_le32s(&((desc)->word7)); \ ++}) ++ ++/* EDMA Tx GSO status */ ++enum edma_tx_status { ++ EDMA_TX_OK = 0, /* Tx success. */ ++ EDMA_TX_FAIL_NO_DESC = 1, /* Not enough descriptors. */ ++ EDMA_TX_FAIL = 2, /* Tx failure. */ ++}; ++ ++/* EDMA TX GSO status */ ++enum edma_tx_gso_status { ++ EDMA_TX_GSO_NOT_NEEDED = 0, ++ /* Packet has segment count less than TX_TSO_SEG_MAX. */ ++ EDMA_TX_GSO_SUCCEED = 1, ++ /* GSO Succeed. */ ++ EDMA_TX_GSO_FAIL = 2, ++ /* GSO failed, drop the packet. */ ++}; ++ ++/** ++ * struct edma_txcmpl_stats - EDMA TX complete ring statistics. ++ * @invalid_buffer: Invalid buffer address received. ++ * @errors: Other Tx complete descriptor errors indicated by the hardware. ++ * @desc_with_more_bit: Packet's segment transmit count. ++ * @no_pending_desc: No descriptor is pending for processing. ++ * @syncp: Synchronization pointer. ++ */ ++struct edma_txcmpl_stats { ++ u64 invalid_buffer; ++ u64 errors; ++ u64 desc_with_more_bit; ++ u64 no_pending_desc; ++ struct u64_stats_sync syncp; ++}; ++ ++/** ++ * struct edma_txdesc_stats - EDMA Tx descriptor ring statistics. ++ * @no_desc_avail: No descriptor available to transmit. ++ * @tso_max_seg_exceed: Packets extending EDMA_TX_TSO_SEG_MAX segments. ++ * @syncp: Synchronization pointer. ++ */ ++struct edma_txdesc_stats { ++ u64 no_desc_avail; ++ u64 tso_max_seg_exceed; ++ struct u64_stats_sync syncp; ++}; ++ ++/** ++ * struct edma_txdesc_pri - EDMA primary TX descriptor. ++ * @word0: Low 32-bit of buffer address. ++ * @word1: Buffer recycling, PTP tag flag, PRI valid flag. ++ * @word2: Low 32-bit of opaque value. ++ * @word3: High 32-bit of opaque value. ++ * @word4: Source/Destination port info. ++ * @word5: VLAN offload, csum mode, ip_csum_en, tso_en, data len. ++ * @word6: MSS/hash_value/PTP tag, data offset. ++ * @word7: L4/L3 offset, PROT type, L2 type, CVLAN/SVLAN tag, service code. ++ */ ++struct edma_txdesc_pri { ++ u32 word0; ++ u32 word1; ++ u32 word2; ++ u32 word3; ++ u32 word4; ++ u32 word5; ++ u32 word6; ++ u32 word7; ++}; ++ ++/** ++ * struct edma_txdesc_sec - EDMA secondary TX descriptor. ++ * @word0: Reserved. ++ * @word1: Custom csum offset, payload offset, TTL/NAT action. ++ * @word2: NAPT translated port, DSCP value, TTL value. ++ * @word3: Flow index value and valid flag. ++ * @word4: Reserved. ++ * @word5: Reserved. ++ * @word6: CVLAN/SVLAN command. ++ * @word7: CVLAN/SVLAN tag value. ++ */ ++struct edma_txdesc_sec { ++ u32 word0; ++ u32 word1; ++ u32 word2; ++ u32 word3; ++ u32 word4; ++ u32 word5; ++ u32 word6; ++ u32 word7; ++}; ++ ++/** ++ * struct edma_txcmpl_desc - EDMA TX complete descriptor. ++ * @word0: Low 32-bit opaque value. ++ * @word1: High 32-bit opaque value. ++ * @word2: More fragment, transmit ring id, pool id. ++ * @word3: Error indications. ++ */ ++struct edma_txcmpl_desc { ++ u32 word0; ++ u32 word1; ++ u32 word2; ++ u32 word3; ++}; ++ ++/** ++ * struct edma_txdesc_ring - EDMA TX descriptor ring ++ * @prod_idx: Producer index ++ * @id: Tx ring number ++ * @avail_desc: Number of available descriptor to process ++ * @pdesc: Primary descriptor ring virtual address ++ * @pdma: Primary descriptor ring physical address ++ * @sdesc: Secondary descriptor ring virtual address ++ * @tx_desc_stats: Tx descriptor ring statistics ++ * @sdma: Secondary descriptor ring physical address ++ * @count: Number of descriptors ++ * @fc_grp_id: Flow control group ID ++ */ ++struct edma_txdesc_ring { ++ u32 prod_idx; ++ u32 id; ++ u32 avail_desc; ++ struct edma_txdesc_pri *pdesc; ++ dma_addr_t pdma; ++ struct edma_txdesc_sec *sdesc; ++ struct edma_txdesc_stats txdesc_stats; ++ dma_addr_t sdma; ++ u32 count; ++ u8 fc_grp_id; ++}; ++ ++/** ++ * struct edma_txcmpl_ring - EDMA TX complete ring ++ * @napi: NAPI ++ * @cons_idx: Consumer index ++ * @avail_pkt: Number of available packets to process ++ * @desc: Descriptor ring virtual address ++ * @id: Txcmpl ring number ++ * @tx_cmpl_stats: Tx complete ring statistics ++ * @dma: Descriptor ring physical address ++ * @count: Number of descriptors in the ring ++ * @napi_added: Flag to indicate NAPI add status ++ */ ++struct edma_txcmpl_ring { ++ struct napi_struct napi; ++ u32 cons_idx; ++ u32 avail_pkt; ++ struct edma_txcmpl_desc *desc; ++ u32 id; ++ struct edma_txcmpl_stats txcmpl_stats; ++ dma_addr_t dma; ++ u32 count; ++ bool napi_added; ++}; ++ ++enum edma_tx_status edma_tx_ring_xmit(struct net_device *netdev, ++ struct sk_buff *skb, ++ struct edma_txdesc_ring *txdesc_ring, ++ struct edma_port_tx_stats *stats); ++u32 edma_tx_complete(u32 work_to_do, ++ struct edma_txcmpl_ring *txcmpl_ring); ++irqreturn_t edma_tx_handle_irq(int irq, void *ctx); ++int edma_tx_napi_poll(struct napi_struct *napi, int budget); ++enum edma_tx_gso_status edma_tx_gso_segment(struct sk_buff *skb, ++ struct net_device *netdev, struct sk_buff **segs); ++ ++#endif diff --git a/target/linux/qualcommbe/patches-6.12/0346-net-ethernet-qualcomm-Add-miscellaneous-error-interr.patch b/target/linux/qualcommbe/patches-6.12/0346-net-ethernet-qualcomm-Add-miscellaneous-error-interr.patch new file mode 100644 index 0000000000..0bdfb0c897 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0346-net-ethernet-qualcomm-Add-miscellaneous-error-interr.patch @@ -0,0 +1,730 @@ +From 8a924457c0b71acee96c8f78ef386e2a354a2aca Mon Sep 17 00:00:00 2001 +From: Suruchi Agarwal +Date: Thu, 21 Mar 2024 16:31:04 -0700 +Subject: [PATCH] net: ethernet: qualcomm: Add miscellaneous error interrupts + and counters + +Miscellaneous error interrupts, EDMA Tx/Rx and error counters are supported +using debugfs framework. + +Change-Id: I7da8b978a7e93947b03a45269a81b401f35da31c +Co-developed-by: Pavithra R +Signed-off-by: Pavithra R +Signed-off-by: Suruchi Agarwal +--- + drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +- + drivers/net/ethernet/qualcomm/ppe/edma.c | 162 ++++++++ + drivers/net/ethernet/qualcomm/ppe/edma.h | 30 ++ + .../net/ethernet/qualcomm/ppe/edma_debugfs.c | 370 ++++++++++++++++++ + .../net/ethernet/qualcomm/ppe/ppe_debugfs.c | 17 + + 5 files changed, 580 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_debugfs.c + +--- a/drivers/net/ethernet/qualcomm/ppe/Makefile ++++ b/drivers/net/ethernet/qualcomm/ppe/Makefile +@@ -7,4 +7,4 @@ obj-$(CONFIG_QCOM_PPE) += qcom-ppe.o + qcom-ppe-objs := ppe.o ppe_config.o ppe_debugfs.o ppe_port.o + + #EDMA +-qcom-ppe-objs += edma.o edma_cfg_rx.o edma_cfg_tx.o edma_port.o edma_rx.o edma_tx.o ++qcom-ppe-objs += edma.o edma_cfg_rx.o edma_cfg_tx.o edma_debugfs.o edma_port.o edma_rx.o edma_tx.o +--- a/drivers/net/ethernet/qualcomm/ppe/edma.c ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.c +@@ -152,6 +152,42 @@ static int edma_clock_init(void) + } + + /** ++ * edma_err_stats_alloc - Allocate stats memory ++ * ++ * Allocate memory for per-CPU error stats. ++ */ ++int edma_err_stats_alloc(void) ++{ ++ u32 i; ++ ++ edma_ctx->err_stats = alloc_percpu(*edma_ctx->err_stats); ++ if (!edma_ctx->err_stats) ++ return -ENOMEM; ++ ++ for_each_possible_cpu(i) { ++ struct edma_err_stats *stats; ++ ++ stats = per_cpu_ptr(edma_ctx->err_stats, i); ++ u64_stats_init(&stats->syncp); ++ } ++ ++ return 0; ++} ++ ++/** ++ * edma_err_stats_free - Free stats memory ++ * ++ * Free memory of per-CPU error stats. ++ */ ++void edma_err_stats_free(void) ++{ ++ if (edma_ctx->err_stats) { ++ free_percpu(edma_ctx->err_stats); ++ edma_ctx->err_stats = NULL; ++ } ++} ++ ++/** + * edma_configure_ucast_prio_map_tbl - Configure unicast priority map table. + * + * Map int_priority values to priority class and initialize +@@ -191,11 +227,113 @@ static int edma_configure_ucast_prio_map + return ret; + } + ++static void edma_disable_misc_interrupt(void) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 reg; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_MISC_INT_MASK_ADDR; ++ regmap_write(regmap, reg, EDMA_MASK_INT_CLEAR); ++} ++ ++static void edma_enable_misc_interrupt(void) ++{ ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 reg; ++ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_MISC_INT_MASK_ADDR; ++ regmap_write(regmap, reg, edma_ctx->intr_info.intr_mask_misc); ++} ++ ++static irqreturn_t edma_misc_handle_irq(int irq, ++ __maybe_unused void *ctx) ++{ ++ struct edma_err_stats *stats = this_cpu_ptr(edma_ctx->err_stats); ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; ++ struct regmap *regmap = ppe_dev->regmap; ++ u32 misc_intr_status, data, reg; ++ ++ /* Read Misc intr status */ ++ reg = EDMA_BASE_OFFSET + EDMA_REG_MISC_INT_STAT_ADDR; ++ regmap_read(regmap, reg, &data); ++ misc_intr_status = data & edma_ctx->intr_info.intr_mask_misc; ++ ++ pr_debug("Received misc irq %d, status: %d\n", irq, misc_intr_status); ++ ++ if (FIELD_GET(EDMA_MISC_AXI_RD_ERR_MASK, misc_intr_status)) { ++ pr_err("MISC AXI read error received\n"); ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->edma_axi_read_err; ++ u64_stats_update_end(&stats->syncp); ++ } ++ ++ if (FIELD_GET(EDMA_MISC_AXI_WR_ERR_MASK, misc_intr_status)) { ++ pr_err("MISC AXI write error received\n"); ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->edma_axi_write_err; ++ u64_stats_update_end(&stats->syncp); ++ } ++ ++ if (FIELD_GET(EDMA_MISC_RX_DESC_FIFO_FULL_MASK, misc_intr_status)) { ++ if (net_ratelimit()) ++ pr_err("MISC Rx descriptor fifo full error received\n"); ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->edma_rxdesc_fifo_full; ++ u64_stats_update_end(&stats->syncp); ++ } ++ ++ if (FIELD_GET(EDMA_MISC_RX_ERR_BUF_SIZE_MASK, misc_intr_status)) { ++ if (net_ratelimit()) ++ pr_err("MISC Rx buffer size error received\n"); ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->edma_rx_buf_size_err; ++ u64_stats_update_end(&stats->syncp); ++ } ++ ++ if (FIELD_GET(EDMA_MISC_TX_SRAM_FULL_MASK, misc_intr_status)) { ++ if (net_ratelimit()) ++ pr_err("MISC Tx SRAM full error received\n"); ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->edma_tx_sram_full; ++ u64_stats_update_end(&stats->syncp); ++ } ++ ++ if (FIELD_GET(EDMA_MISC_TX_CMPL_BUF_FULL_MASK, misc_intr_status)) { ++ if (net_ratelimit()) ++ pr_err("MISC Tx complete buffer full error received\n"); ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->edma_txcmpl_buf_full; ++ u64_stats_update_end(&stats->syncp); ++ } ++ ++ if (FIELD_GET(EDMA_MISC_DATA_LEN_ERR_MASK, misc_intr_status)) { ++ if (net_ratelimit()) ++ pr_err("MISC data length error received\n"); ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->edma_tx_data_len_err; ++ u64_stats_update_end(&stats->syncp); ++ } ++ ++ if (FIELD_GET(EDMA_MISC_TX_TIMEOUT_MASK, misc_intr_status)) { ++ if (net_ratelimit()) ++ pr_err("MISC Tx timeout error received\n"); ++ u64_stats_update_begin(&stats->syncp); ++ ++stats->edma_tx_timeout; ++ u64_stats_update_end(&stats->syncp); ++ } ++ ++ return IRQ_HANDLED; ++} ++ + static int edma_irq_register(void) + { + struct edma_hw_info *hw_info = edma_ctx->hw_info; + struct edma_ring_info *txcmpl = hw_info->txcmpl; ++ struct ppe_device *ppe_dev = edma_ctx->ppe_dev; + struct edma_ring_info *rx = hw_info->rx; ++ struct device *dev = ppe_dev->dev; + int ret; + u32 i; + +@@ -270,8 +408,25 @@ static int edma_irq_register(void) + edma_rxdesc_irq_name[i]); + } + ++ /* Request Misc IRQ */ ++ ret = request_irq(edma_ctx->intr_info.intr_misc, edma_misc_handle_irq, ++ IRQF_SHARED, "edma_misc", ++ (void *)dev); ++ if (ret) { ++ pr_err("MISC IRQ:%d request failed\n", ++ edma_ctx->intr_info.intr_misc); ++ goto misc_intr_req_fail; ++ } ++ + return 0; + ++misc_intr_req_fail: ++ /* Free IRQ for RXDESC rings */ ++ for (i = 0; i < rx->num_rings; i++) { ++ synchronize_irq(edma_ctx->intr_info.intr_rx[i]); ++ free_irq(edma_ctx->intr_info.intr_rx[i], ++ (void *)&edma_ctx->rx_rings[i]); ++ } + rx_desc_ring_intr_req_fail: + for (i = 0; i < rx->num_rings; i++) + kfree(edma_rxdesc_irq_name[i]); +@@ -503,6 +658,7 @@ static int edma_hw_configure(void) + edma_cfg_tx_disable_interrupts(i); + + edma_cfg_rx_disable_interrupts(); ++ edma_disable_misc_interrupt(); + + edma_cfg_rx_rings_disable(); + +@@ -614,6 +770,7 @@ void edma_destroy(struct ppe_device *ppe + edma_cfg_tx_disable_interrupts(i); + + edma_cfg_rx_disable_interrupts(); ++ edma_disable_misc_interrupt(); + + /* Free IRQ for TXCMPL rings. */ + for (i = 0; i < txcmpl->num_rings; i++) { +@@ -634,6 +791,10 @@ void edma_destroy(struct ppe_device *ppe + } + kfree(edma_rxdesc_irq_name); + ++ /* Free Misc IRQ */ ++ synchronize_irq(edma_ctx->intr_info.intr_misc); ++ free_irq(edma_ctx->intr_info.intr_misc, (void *)(ppe_dev->dev)); ++ + kfree(edma_ctx->intr_info.intr_rx); + kfree(edma_ctx->intr_info.intr_txcmpl); + +@@ -699,6 +860,7 @@ int edma_setup(struct ppe_device *ppe_de + } + + edma_cfg_rx_enable_interrupts(); ++ edma_enable_misc_interrupt(); + + dev_info(dev, "EDMA configuration successful\n"); + +--- a/drivers/net/ethernet/qualcomm/ppe/edma.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.h +@@ -47,6 +47,30 @@ enum ppe_queue_class_type { + }; + + /** ++ * struct edma_err_stats - EDMA error stats ++ * @edma_axi_read_err: AXI read error ++ * @edma_axi_write_err: AXI write error ++ * @edma_rxdesc_fifo_full: Rx desc FIFO full error ++ * @edma_rx_buf_size_err: Rx buffer size too small error ++ * @edma_tx_sram_full: Tx packet SRAM buffer full error ++ * @edma_tx_data_len_err: Tx data length error ++ * @edma_tx_timeout: Tx timeout error ++ * @edma_txcmpl_buf_full: Tx completion buffer full error ++ * @syncp: Synchronization pointer ++ */ ++struct edma_err_stats { ++ u64 edma_axi_read_err; ++ u64 edma_axi_write_err; ++ u64 edma_rxdesc_fifo_full; ++ u64 edma_rx_buf_size_err; ++ u64 edma_tx_sram_full; ++ u64 edma_tx_data_len_err; ++ u64 edma_tx_timeout; ++ u64 edma_txcmpl_buf_full; ++ struct u64_stats_sync syncp; ++}; ++ ++/** + * struct edma_ring_info - EDMA ring data structure. + * @max_rings: Maximum number of rings + * @ring_start: Ring start ID +@@ -107,6 +131,7 @@ struct edma_intr_info { + * @rx_rings: Rx Desc Rings, SW is consumer + * @tx_rings: Tx Descriptor Ring, SW is producer + * @txcmpl_rings: Tx complete Ring, SW is consumer ++ * @err_stats: Per CPU error statistics + * @rx_page_mode: Page mode enabled or disabled + * @rx_buf_size: Rx buffer size for Jumbo MRU + * @tx_requeue_stop: Tx requeue stop enabled or disabled +@@ -121,6 +146,7 @@ struct edma_context { + struct edma_rxdesc_ring *rx_rings; + struct edma_txdesc_ring *tx_rings; + struct edma_txcmpl_ring *txcmpl_rings; ++ struct edma_err_stats __percpu *err_stats; + u32 rx_page_mode; + u32 rx_buf_size; + bool tx_requeue_stop; +@@ -129,8 +155,12 @@ struct edma_context { + /* Global EDMA context */ + extern struct edma_context *edma_ctx; + ++int edma_err_stats_alloc(void); ++void edma_err_stats_free(void); + void edma_destroy(struct ppe_device *ppe_dev); + int edma_setup(struct ppe_device *ppe_dev); ++void edma_debugfs_teardown(void); ++int edma_debugfs_setup(struct ppe_device *ppe_dev); + int ppe_edma_queue_offset_config(struct ppe_device *ppe_dev, + enum ppe_queue_class_type class, + int index, int queue_offset); +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_debugfs.c +@@ -0,0 +1,370 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* EDMA debugfs routines for display of Tx/Rx counters. */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "edma.h" ++ ++#define EDMA_STATS_BANNER_MAX_LEN 80 ++#define EDMA_RX_RING_STATS_NODE_NAME "EDMA_RX" ++#define EDMA_TX_RING_STATS_NODE_NAME "EDMA_TX" ++#define EDMA_ERR_STATS_NODE_NAME "EDMA_ERR" ++ ++static struct dentry *edma_dentry; ++static struct dentry *stats_dentry; ++ ++static void edma_debugfs_print_banner(struct seq_file *m, char *node) ++{ ++ u32 banner_char_len, i; ++ ++ for (i = 0; i < EDMA_STATS_BANNER_MAX_LEN; i++) ++ seq_puts(m, "_"); ++ banner_char_len = (EDMA_STATS_BANNER_MAX_LEN - (strlen(node) + 2)) / 2; ++ seq_puts(m, "\n\n"); ++ ++ for (i = 0; i < banner_char_len; i++) ++ seq_puts(m, "<"); ++ seq_printf(m, " %s ", node); ++ ++ for (i = 0; i < banner_char_len; i++) ++ seq_puts(m, ">"); ++ seq_puts(m, "\n"); ++ ++ for (i = 0; i < EDMA_STATS_BANNER_MAX_LEN; i++) ++ seq_puts(m, "_"); ++ seq_puts(m, "\n\n"); ++} ++ ++static int edma_debugfs_rx_rings_stats_show(struct seq_file *m, ++ void __maybe_unused *p) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *rxfill = hw_info->rxfill; ++ struct edma_rxfill_stats *rxfill_stats; ++ struct edma_rxdesc_stats *rxdesc_stats; ++ struct edma_ring_info *rx = hw_info->rx; ++ unsigned int start; ++ u32 i; ++ ++ rxfill_stats = kcalloc(rxfill->num_rings, sizeof(*rxfill_stats), GFP_KERNEL); ++ if (!rxfill_stats) ++ return -ENOMEM; ++ ++ rxdesc_stats = kcalloc(rx->num_rings, sizeof(*rxdesc_stats), GFP_KERNEL); ++ if (!rxdesc_stats) { ++ kfree(rxfill_stats); ++ return -ENOMEM; ++ } ++ ++ /* Get stats for Rx fill rings. */ ++ for (i = 0; i < rxfill->num_rings; i++) { ++ struct edma_rxfill_ring *rxfill_ring; ++ struct edma_rxfill_stats *stats; ++ ++ rxfill_ring = &edma_ctx->rxfill_rings[i]; ++ stats = &rxfill_ring->rxfill_stats; ++ do { ++ start = u64_stats_fetch_begin(&stats->syncp); ++ rxfill_stats[i].alloc_failed = stats->alloc_failed; ++ rxfill_stats[i].page_alloc_failed = stats->page_alloc_failed; ++ } while (u64_stats_fetch_retry(&stats->syncp, start)); ++ } ++ ++ /* Get stats for Rx Desc rings. */ ++ for (i = 0; i < rx->num_rings; i++) { ++ struct edma_rxdesc_ring *rxdesc_ring; ++ struct edma_rxdesc_stats *stats; ++ ++ rxdesc_ring = &edma_ctx->rx_rings[i]; ++ stats = &rxdesc_ring->rxdesc_stats; ++ do { ++ start = u64_stats_fetch_begin(&stats->syncp); ++ rxdesc_stats[i].src_port_inval = stats->src_port_inval; ++ rxdesc_stats[i].src_port_inval_type = stats->src_port_inval_type; ++ rxdesc_stats[i].src_port_inval_netdev = stats->src_port_inval_netdev; ++ } while (u64_stats_fetch_retry(&stats->syncp, start)); ++ } ++ ++ edma_debugfs_print_banner(m, EDMA_RX_RING_STATS_NODE_NAME); ++ ++ seq_puts(m, "\n#EDMA RX descriptor rings stats:\n\n"); ++ for (i = 0; i < rx->num_rings; i++) { ++ seq_printf(m, "\t\tEDMA RX descriptor %d ring stats:\n", i + rx->ring_start); ++ seq_printf(m, "\t\t rxdesc[%d]:src_port_inval = %llu\n", ++ i + rx->ring_start, rxdesc_stats[i].src_port_inval); ++ seq_printf(m, "\t\t rxdesc[%d]:src_port_inval_type = %llu\n", ++ i + rx->ring_start, rxdesc_stats[i].src_port_inval_type); ++ seq_printf(m, "\t\t rxdesc[%d]:src_port_inval_netdev = %llu\n", ++ i + rx->ring_start, ++ rxdesc_stats[i].src_port_inval_netdev); ++ seq_puts(m, "\n"); ++ } ++ ++ seq_puts(m, "\n#EDMA RX fill rings stats:\n\n"); ++ for (i = 0; i < rxfill->num_rings; i++) { ++ seq_printf(m, "\t\tEDMA RX fill %d ring stats:\n", i + rxfill->ring_start); ++ seq_printf(m, "\t\t rxfill[%d]:alloc_failed = %llu\n", ++ i + rxfill->ring_start, rxfill_stats[i].alloc_failed); ++ seq_printf(m, "\t\t rxfill[%d]:page_alloc_failed = %llu\n", ++ i + rxfill->ring_start, rxfill_stats[i].page_alloc_failed); ++ seq_puts(m, "\n"); ++ } ++ ++ kfree(rxfill_stats); ++ kfree(rxdesc_stats); ++ return 0; ++} ++ ++static int edma_debugfs_tx_rings_stats_show(struct seq_file *m, ++ void __maybe_unused *p) ++{ ++ struct edma_hw_info *hw_info = edma_ctx->hw_info; ++ struct edma_ring_info *txcmpl = hw_info->txcmpl; ++ struct edma_ring_info *tx = hw_info->tx; ++ struct edma_txcmpl_stats *txcmpl_stats; ++ struct edma_txdesc_stats *txdesc_stats; ++ unsigned int start; ++ u32 i; ++ ++ txcmpl_stats = kcalloc(txcmpl->num_rings, sizeof(*txcmpl_stats), GFP_KERNEL); ++ if (!txcmpl_stats) ++ return -ENOMEM; ++ ++ txdesc_stats = kcalloc(tx->num_rings, sizeof(*txdesc_stats), GFP_KERNEL); ++ if (!txdesc_stats) { ++ kfree(txcmpl_stats); ++ return -ENOMEM; ++ } ++ ++ /* Get stats for Tx desc rings. */ ++ for (i = 0; i < tx->num_rings; i++) { ++ struct edma_txdesc_ring *txdesc_ring; ++ struct edma_txdesc_stats *stats; ++ ++ txdesc_ring = &edma_ctx->tx_rings[i]; ++ stats = &txdesc_ring->txdesc_stats; ++ do { ++ start = u64_stats_fetch_begin(&stats->syncp); ++ txdesc_stats[i].no_desc_avail = stats->no_desc_avail; ++ txdesc_stats[i].tso_max_seg_exceed = stats->tso_max_seg_exceed; ++ } while (u64_stats_fetch_retry(&stats->syncp, start)); ++ } ++ ++ /* Get stats for Tx Complete rings. */ ++ for (i = 0; i < txcmpl->num_rings; i++) { ++ struct edma_txcmpl_ring *txcmpl_ring; ++ struct edma_txcmpl_stats *stats; ++ ++ txcmpl_ring = &edma_ctx->txcmpl_rings[i]; ++ stats = &txcmpl_ring->txcmpl_stats; ++ do { ++ start = u64_stats_fetch_begin(&stats->syncp); ++ txcmpl_stats[i].invalid_buffer = stats->invalid_buffer; ++ txcmpl_stats[i].errors = stats->errors; ++ txcmpl_stats[i].desc_with_more_bit = stats->desc_with_more_bit; ++ txcmpl_stats[i].no_pending_desc = stats->no_pending_desc; ++ } while (u64_stats_fetch_retry(&stats->syncp, start)); ++ } ++ ++ edma_debugfs_print_banner(m, EDMA_TX_RING_STATS_NODE_NAME); ++ ++ seq_puts(m, "\n#EDMA TX complete rings stats:\n\n"); ++ for (i = 0; i < txcmpl->num_rings; i++) { ++ seq_printf(m, "\t\tEDMA TX complete %d ring stats:\n", i + txcmpl->ring_start); ++ seq_printf(m, "\t\t txcmpl[%d]:invalid_buffer = %llu\n", ++ i + txcmpl->ring_start, txcmpl_stats[i].invalid_buffer); ++ seq_printf(m, "\t\t txcmpl[%d]:errors = %llu\n", ++ i + txcmpl->ring_start, txcmpl_stats[i].errors); ++ seq_printf(m, "\t\t txcmpl[%d]:desc_with_more_bit = %llu\n", ++ i + txcmpl->ring_start, txcmpl_stats[i].desc_with_more_bit); ++ seq_printf(m, "\t\t txcmpl[%d]:no_pending_desc = %llu\n", ++ i + txcmpl->ring_start, txcmpl_stats[i].no_pending_desc); ++ seq_puts(m, "\n"); ++ } ++ ++ seq_puts(m, "\n#EDMA TX descriptor rings stats:\n\n"); ++ for (i = 0; i < tx->num_rings; i++) { ++ seq_printf(m, "\t\tEDMA TX descriptor %d ring stats:\n", i + tx->ring_start); ++ seq_printf(m, "\t\t txdesc[%d]:no_desc_avail = %llu\n", ++ i + tx->ring_start, txdesc_stats[i].no_desc_avail); ++ seq_printf(m, "\t\t txdesc[%d]:tso_max_seg_exceed = %llu\n", ++ i + tx->ring_start, txdesc_stats[i].tso_max_seg_exceed); ++ seq_puts(m, "\n"); ++ } ++ ++ kfree(txcmpl_stats); ++ kfree(txdesc_stats); ++ return 0; ++} ++ ++static int edma_debugfs_err_stats_show(struct seq_file *m, ++ void __maybe_unused *p) ++{ ++ struct edma_err_stats *err_stats, *pcpu_err_stats; ++ unsigned int start; ++ u32 cpu; ++ ++ err_stats = kzalloc(sizeof(*err_stats), GFP_KERNEL); ++ if (!err_stats) ++ return -ENOMEM; ++ ++ /* Get percpu EDMA miscellaneous stats. */ ++ for_each_possible_cpu(cpu) { ++ pcpu_err_stats = per_cpu_ptr(edma_ctx->err_stats, cpu); ++ do { ++ start = u64_stats_fetch_begin(&pcpu_err_stats->syncp); ++ err_stats->edma_axi_read_err += ++ pcpu_err_stats->edma_axi_read_err; ++ err_stats->edma_axi_write_err += ++ pcpu_err_stats->edma_axi_write_err; ++ err_stats->edma_rxdesc_fifo_full += ++ pcpu_err_stats->edma_rxdesc_fifo_full; ++ err_stats->edma_rx_buf_size_err += ++ pcpu_err_stats->edma_rx_buf_size_err; ++ err_stats->edma_tx_sram_full += ++ pcpu_err_stats->edma_tx_sram_full; ++ err_stats->edma_tx_data_len_err += ++ pcpu_err_stats->edma_tx_data_len_err; ++ err_stats->edma_tx_timeout += ++ pcpu_err_stats->edma_tx_timeout; ++ err_stats->edma_txcmpl_buf_full += ++ pcpu_err_stats->edma_txcmpl_buf_full; ++ } while (u64_stats_fetch_retry(&pcpu_err_stats->syncp, start)); ++ } ++ ++ edma_debugfs_print_banner(m, EDMA_ERR_STATS_NODE_NAME); ++ ++ seq_puts(m, "\n#EDMA error stats:\n\n"); ++ seq_printf(m, "\t\t axi read error = %llu\n", ++ err_stats->edma_axi_read_err); ++ seq_printf(m, "\t\t axi write error = %llu\n", ++ err_stats->edma_axi_write_err); ++ seq_printf(m, "\t\t Rx descriptor fifo full = %llu\n", ++ err_stats->edma_rxdesc_fifo_full); ++ seq_printf(m, "\t\t Rx buffer size error = %llu\n", ++ err_stats->edma_rx_buf_size_err); ++ seq_printf(m, "\t\t Tx SRAM full = %llu\n", ++ err_stats->edma_tx_sram_full); ++ seq_printf(m, "\t\t Tx data length error = %llu\n", ++ err_stats->edma_tx_data_len_err); ++ seq_printf(m, "\t\t Tx timeout = %llu\n", ++ err_stats->edma_tx_timeout); ++ seq_printf(m, "\t\t Tx completion buffer full = %llu\n", ++ err_stats->edma_txcmpl_buf_full); ++ ++ kfree(err_stats); ++ return 0; ++} ++ ++static int edma_debugs_rx_rings_stats_open(struct inode *inode, ++ struct file *file) ++{ ++ return single_open(file, edma_debugfs_rx_rings_stats_show, ++ inode->i_private); ++} ++ ++static const struct file_operations edma_debugfs_rx_rings_file_ops = { ++ .open = edma_debugs_rx_rings_stats_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = seq_release ++}; ++ ++static int edma_debugs_tx_rings_stats_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, edma_debugfs_tx_rings_stats_show, inode->i_private); ++} ++ ++static const struct file_operations edma_debugfs_tx_rings_file_ops = { ++ .open = edma_debugs_tx_rings_stats_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = seq_release ++}; ++ ++static int edma_debugs_err_stats_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, edma_debugfs_err_stats_show, inode->i_private); ++} ++ ++static const struct file_operations edma_debugfs_misc_file_ops = { ++ .open = edma_debugs_err_stats_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = seq_release ++}; ++ ++/** ++ * edma_debugfs_teardown - EDMA debugfs teardown. ++ * ++ * EDMA debugfs teardown and free stats memory. ++ */ ++void edma_debugfs_teardown(void) ++{ ++ /* Free EDMA miscellaneous stats memory */ ++ edma_err_stats_free(); ++ ++ debugfs_remove_recursive(edma_dentry); ++ edma_dentry = NULL; ++ stats_dentry = NULL; ++} ++ ++/** ++ * edma_debugfs_setup - EDMA debugfs setup. ++ * @ppe_dev: PPE Device ++ * ++ * EDMA debugfs setup. ++ */ ++int edma_debugfs_setup(struct ppe_device *ppe_dev) ++{ ++ edma_dentry = debugfs_create_dir("edma", ppe_dev->debugfs_root); ++ if (!edma_dentry) { ++ pr_err("Unable to create debugfs edma directory in debugfs\n"); ++ goto debugfs_dir_failed; ++ } ++ ++ stats_dentry = debugfs_create_dir("stats", edma_dentry); ++ if (!stats_dentry) { ++ pr_err("Unable to create debugfs stats directory in debugfs\n"); ++ goto debugfs_dir_failed; ++ } ++ ++ if (!debugfs_create_file("rx_ring_stats", 0444, stats_dentry, ++ NULL, &edma_debugfs_rx_rings_file_ops)) { ++ pr_err("Unable to create Rx rings statistics file entry in debugfs\n"); ++ goto debugfs_dir_failed; ++ } ++ ++ if (!debugfs_create_file("tx_ring_stats", 0444, stats_dentry, ++ NULL, &edma_debugfs_tx_rings_file_ops)) { ++ pr_err("Unable to create Tx rings statistics file entry in debugfs\n"); ++ goto debugfs_dir_failed; ++ } ++ ++ /* Allocate memory for EDMA miscellaneous stats */ ++ if (edma_err_stats_alloc() < 0) { ++ pr_err("Unable to allocate miscellaneous percpu stats\n"); ++ goto debugfs_dir_failed; ++ } ++ ++ if (!debugfs_create_file("err_stats", 0444, stats_dentry, ++ NULL, &edma_debugfs_misc_file_ops)) { ++ pr_err("Unable to create EDMA miscellaneous statistics file entry in debugfs\n"); ++ goto debugfs_dir_failed; ++ } ++ ++ return 0; ++ ++debugfs_dir_failed: ++ debugfs_remove_recursive(edma_dentry); ++ edma_dentry = NULL; ++ stats_dentry = NULL; ++ return -ENOMEM; ++} +--- a/drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c ++++ b/drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c +@@ -7,9 +7,11 @@ + + #include + #include ++#include + #include + #include + ++#include "edma.h" + #include "ppe.h" + #include "ppe_config.h" + #include "ppe_debugfs.h" +@@ -678,15 +680,30 @@ static const struct file_operations ppe_ + + void ppe_debugfs_setup(struct ppe_device *ppe_dev) + { ++ int ret; ++ + ppe_dev->debugfs_root = debugfs_create_dir("ppe", NULL); + debugfs_create_file("packet_counters", 0444, + ppe_dev->debugfs_root, + ppe_dev, + &ppe_debugfs_packet_counter_fops); ++ ++ if (!ppe_dev->debugfs_root) { ++ dev_err(ppe_dev->dev, "Error in PPE debugfs setup\n"); ++ return; ++ } ++ ++ ret = edma_debugfs_setup(ppe_dev); ++ if (ret) { ++ dev_err(ppe_dev->dev, "Error in EDMA debugfs setup API. ret: %d\n", ret); ++ debugfs_remove_recursive(ppe_dev->debugfs_root); ++ ppe_dev->debugfs_root = NULL; ++ } + } + + void ppe_debugfs_teardown(struct ppe_device *ppe_dev) + { ++ edma_debugfs_teardown(); + debugfs_remove_recursive(ppe_dev->debugfs_root); + ppe_dev->debugfs_root = NULL; + } diff --git a/target/linux/qualcommbe/patches-6.12/0347-net-ethernet-qualcomm-Add-ethtool-support-for-EDMA.patch b/target/linux/qualcommbe/patches-6.12/0347-net-ethernet-qualcomm-Add-ethtool-support-for-EDMA.patch new file mode 100644 index 0000000000..4e0103db57 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0347-net-ethernet-qualcomm-Add-ethtool-support-for-EDMA.patch @@ -0,0 +1,344 @@ +From bd61a680fb657eb65272225f18c93fe338c700da Mon Sep 17 00:00:00 2001 +From: Pavithra R +Date: Thu, 30 May 2024 20:46:36 +0530 +Subject: [PATCH] net: ethernet: qualcomm: Add ethtool support for EDMA + +ethtool ops can be used for EDMA netdevice configuration and statistics. + +Change-Id: I57fc19415dacbe51fed000520336463938220609 +Signed-off-by: Pavithra R +Alex G: use struct ethtool_keee instead of ethtool_eee +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +- + drivers/net/ethernet/qualcomm/ppe/edma.h | 1 + + .../net/ethernet/qualcomm/ppe/edma_ethtool.c | 294 ++++++++++++++++++ + drivers/net/ethernet/qualcomm/ppe/edma_port.c | 1 + + 4 files changed, 297 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_ethtool.c + +--- a/drivers/net/ethernet/qualcomm/ppe/Makefile ++++ b/drivers/net/ethernet/qualcomm/ppe/Makefile +@@ -7,4 +7,4 @@ obj-$(CONFIG_QCOM_PPE) += qcom-ppe.o + qcom-ppe-objs := ppe.o ppe_config.o ppe_debugfs.o ppe_port.o + + #EDMA +-qcom-ppe-objs += edma.o edma_cfg_rx.o edma_cfg_tx.o edma_debugfs.o edma_port.o edma_rx.o edma_tx.o ++qcom-ppe-objs += edma.o edma_cfg_rx.o edma_cfg_tx.o edma_debugfs.o edma_port.o edma_rx.o edma_tx.o edma_ethtool.o +--- a/drivers/net/ethernet/qualcomm/ppe/edma.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.h +@@ -161,6 +161,7 @@ void edma_destroy(struct ppe_device *ppe + int edma_setup(struct ppe_device *ppe_dev); + void edma_debugfs_teardown(void); + int edma_debugfs_setup(struct ppe_device *ppe_dev); ++void edma_set_ethtool_ops(struct net_device *netdev); + int ppe_edma_queue_offset_config(struct ppe_device *ppe_dev, + enum ppe_queue_class_type class, + int index, int queue_offset); +--- /dev/null ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_ethtool.c +@@ -0,0 +1,294 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* ethtool support for EDMA */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "edma.h" ++#include "edma_port.h" ++ ++struct edma_ethtool_stats { ++ u8 stat_string[ETH_GSTRING_LEN]; ++ u32 stat_offset; ++}; ++ ++/** ++ * struct edma_gmac_stats - Per-GMAC statistics. ++ * @rx_packets: Number of RX packets ++ * @rx_bytes: Number of RX bytes ++ * @rx_dropped: Number of RX dropped packets ++ * @rx_fraglist_packets: Number of RX fraglist packets ++ * @rx_nr_frag_packets: Number of RX nr fragment packets ++ * @rx_nr_frag_headroom_err: Number of RX nr fragment packets with headroom error ++ * @tx_packets: Number of TX packets ++ * @tx_bytes: Number of TX bytes ++ * @tx_dropped: Number of TX dropped packets ++ * @tx_nr_frag_packets: Number of TX nr fragment packets ++ * @tx_fraglist_packets: Number of TX fraglist packets ++ * @tx_fraglist_with_nr_frags_packets: Number of TX fraglist packets with nr fragments ++ * @tx_tso_packets: Number of TX TCP segmentation offload packets ++ * @tx_tso_drop_packets: Number of TX TCP segmentation dropped packets ++ * @tx_gso_packets: Number of TX SW GSO packets ++ * @tx_gso_drop_packets: Number of TX SW GSO dropped packets ++ * @tx_queue_stopped: Number of times Queue got stopped ++ */ ++struct edma_gmac_stats { ++ u64 rx_packets; ++ u64 rx_bytes; ++ u64 rx_dropped; ++ u64 rx_fraglist_packets; ++ u64 rx_nr_frag_packets; ++ u64 rx_nr_frag_headroom_err; ++ u64 tx_packets; ++ u64 tx_bytes; ++ u64 tx_dropped; ++ u64 tx_nr_frag_packets; ++ u64 tx_fraglist_packets; ++ u64 tx_fraglist_with_nr_frags_packets; ++ u64 tx_tso_packets; ++ u64 tx_tso_drop_packets; ++ u64 tx_gso_packets; ++ u64 tx_gso_drop_packets; ++ u64 tx_queue_stopped[EDMA_MAX_CORE]; ++}; ++ ++#define EDMA_STAT(m) offsetof(struct edma_gmac_stats, m) ++ ++static const struct edma_ethtool_stats edma_gstrings_stats[] = { ++ {"rx_bytes", EDMA_STAT(rx_bytes)}, ++ {"rx_packets", EDMA_STAT(rx_packets)}, ++ {"rx_dropped", EDMA_STAT(rx_dropped)}, ++ {"rx_fraglist_packets", EDMA_STAT(rx_fraglist_packets)}, ++ {"rx_nr_frag_packets", EDMA_STAT(rx_nr_frag_packets)}, ++ {"rx_nr_frag_headroom_err", EDMA_STAT(rx_nr_frag_headroom_err)}, ++ {"tx_bytes", EDMA_STAT(tx_bytes)}, ++ {"tx_packets", EDMA_STAT(tx_packets)}, ++ {"tx_dropped", EDMA_STAT(tx_dropped)}, ++ {"tx_nr_frag_packets", EDMA_STAT(tx_nr_frag_packets)}, ++ {"tx_fraglist_packets", EDMA_STAT(tx_fraglist_packets)}, ++ {"tx_fraglist_nr_frags_packets", EDMA_STAT(tx_fraglist_with_nr_frags_packets)}, ++ {"tx_tso_packets", EDMA_STAT(tx_tso_packets)}, ++ {"tx_tso_drop_packets", EDMA_STAT(tx_tso_drop_packets)}, ++ {"tx_gso_packets", EDMA_STAT(tx_gso_packets)}, ++ {"tx_gso_drop_packets", EDMA_STAT(tx_gso_drop_packets)}, ++ {"tx_queue_stopped_cpu0", EDMA_STAT(tx_queue_stopped[0])}, ++ {"tx_queue_stopped_cpu1", EDMA_STAT(tx_queue_stopped[1])}, ++ {"tx_queue_stopped_cpu2", EDMA_STAT(tx_queue_stopped[2])}, ++ {"tx_queue_stopped_cpu3", EDMA_STAT(tx_queue_stopped[3])}, ++}; ++ ++#define EDMA_STATS_LEN ARRAY_SIZE(edma_gstrings_stats) ++ ++static void edma_port_get_stats(struct net_device *netdev, ++ struct edma_gmac_stats *stats) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct edma_port_rx_stats *pcpu_rx_stats; ++ struct edma_port_tx_stats *pcpu_tx_stats; ++ int i; ++ ++ memset(stats, 0, sizeof(struct edma_port_pcpu_stats)); ++ ++ for_each_possible_cpu(i) { ++ struct edma_port_rx_stats rxp; ++ struct edma_port_tx_stats txp; ++ unsigned int start; ++ ++ pcpu_rx_stats = per_cpu_ptr(port_priv->pcpu_stats.rx_stats, i); ++ ++ do { ++ start = u64_stats_fetch_begin(&pcpu_rx_stats->syncp); ++ memcpy(&rxp, pcpu_rx_stats, sizeof(*pcpu_rx_stats)); ++ } while (u64_stats_fetch_retry(&pcpu_rx_stats->syncp, start)); ++ ++ stats->rx_packets += rxp.rx_pkts; ++ stats->rx_bytes += rxp.rx_bytes; ++ stats->rx_dropped += rxp.rx_drops; ++ stats->rx_nr_frag_packets += rxp.rx_nr_frag_pkts; ++ stats->rx_fraglist_packets += rxp.rx_fraglist_pkts; ++ stats->rx_nr_frag_headroom_err += rxp.rx_nr_frag_headroom_err; ++ ++ pcpu_tx_stats = per_cpu_ptr(port_priv->pcpu_stats.tx_stats, i); ++ ++ do { ++ start = u64_stats_fetch_begin(&pcpu_tx_stats->syncp); ++ memcpy(&txp, pcpu_tx_stats, sizeof(*pcpu_tx_stats)); ++ } while (u64_stats_fetch_retry(&pcpu_tx_stats->syncp, start)); ++ ++ stats->tx_packets += txp.tx_pkts; ++ stats->tx_bytes += txp.tx_bytes; ++ stats->tx_dropped += txp.tx_drops; ++ stats->tx_nr_frag_packets += txp.tx_nr_frag_pkts; ++ stats->tx_fraglist_packets += txp.tx_fraglist_pkts; ++ stats->tx_fraglist_with_nr_frags_packets += txp.tx_fraglist_with_nr_frags_pkts; ++ stats->tx_tso_packets += txp.tx_tso_pkts; ++ stats->tx_tso_drop_packets += txp.tx_tso_drop_pkts; ++ stats->tx_gso_packets += txp.tx_gso_pkts; ++ stats->tx_gso_drop_packets += txp.tx_gso_drop_pkts; ++ stats->tx_queue_stopped[i] += txp.tx_queue_stopped[i]; ++ } ++} ++ ++static void edma_get_ethtool_stats(struct net_device *netdev, ++ __maybe_unused struct ethtool_stats *stats, ++ u64 *data) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct edma_gmac_stats edma_stats; ++ u64 *mib_data; ++ int i; ++ u8 *p; ++ ++ if (!port_priv) ++ return; ++ ++ /* Get the DMA Driver statistics from the data plane if available. */ ++ memset(&edma_stats, 0, sizeof(struct edma_gmac_stats)); ++ edma_port_get_stats(netdev, &edma_stats); ++ ++ /* Populate data plane statistics. */ ++ for (i = 0; i < EDMA_STATS_LEN; i++) { ++ p = ((u8 *)(&edma_stats) + edma_gstrings_stats[i].stat_offset); ++ data[i] = *(u64 *)p; ++ } ++ ++ /* Get the GMAC MIB statistics along with the DMA driver statistics. */ ++ mib_data = &data[EDMA_STATS_LEN]; ++ ppe_port_get_ethtool_stats(port_priv->ppe_port, mib_data); ++} ++ ++static int edma_get_strset_count(struct net_device *netdev, int sset) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ int sset_count = 0; ++ ++ if (!port_priv || sset != ETH_SS_STATS) ++ return 0; ++ ++ sset_count = ppe_port_get_sset_count(port_priv->ppe_port, sset); ++ ++ return (EDMA_STATS_LEN + sset_count); ++} ++ ++static void edma_get_strings(struct net_device *netdev, u32 stringset, ++ u8 *data) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ int i; ++ ++ if (!port_priv || stringset != ETH_SS_STATS) ++ return; ++ ++ for (i = 0; i < EDMA_STATS_LEN; i++) { ++ memcpy(data, edma_gstrings_stats[i].stat_string, ++ strlen(edma_gstrings_stats[i].stat_string)); ++ data += ETH_GSTRING_LEN; ++ } ++ ++ ppe_port_get_strings(port_priv->ppe_port, stringset, data); ++} ++ ++static int edma_get_link_ksettings(struct net_device *netdev, ++ struct ethtool_link_ksettings *cmd) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct ppe_port *port = port_priv->ppe_port; ++ ++ if (!port_priv) ++ return -EINVAL; ++ ++ return phylink_ethtool_ksettings_get(port->phylink, cmd); ++} ++ ++static int edma_set_link_ksettings(struct net_device *netdev, ++ const struct ethtool_link_ksettings *cmd) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct ppe_port *port = port_priv->ppe_port; ++ ++ if (!port_priv) ++ return -EINVAL; ++ ++ return phylink_ethtool_ksettings_set(port->phylink, cmd); ++} ++ ++static void edma_get_pauseparam(struct net_device *netdev, ++ struct ethtool_pauseparam *pause) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct ppe_port *port = port_priv->ppe_port; ++ ++ if (!port_priv) ++ return; ++ ++ phylink_ethtool_get_pauseparam(port->phylink, pause); ++} ++ ++static int edma_set_pauseparam(struct net_device *netdev, ++ struct ethtool_pauseparam *pause) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct ppe_port *port = port_priv->ppe_port; ++ ++ if (!port_priv) ++ return -EINVAL; ++ ++ return phylink_ethtool_set_pauseparam(port->phylink, pause); ++} ++ ++static int edma_get_eee(struct net_device *netdev, struct ethtool_keee *eee) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct ppe_port *port = port_priv->ppe_port; ++ ++ if (!port_priv) ++ return -EINVAL; ++ ++ return phylink_ethtool_get_eee(port->phylink, eee); ++} ++ ++static int edma_set_eee(struct net_device *netdev, struct ethtool_keee *eee) ++{ ++ struct edma_port_priv *port_priv = (struct edma_port_priv *)netdev_priv(netdev); ++ struct ppe_port *port = port_priv->ppe_port; ++ int ret; ++ ++ if (!port_priv) ++ return -EINVAL; ++ ++ ret = ppe_port_set_mac_eee(port_priv->ppe_port, eee); ++ if (ret) ++ return ret; ++ ++ return phylink_ethtool_set_eee(port->phylink, eee); ++} ++ ++static const struct ethtool_ops edma_ethtool_ops = { ++ .get_strings = &edma_get_strings, ++ .get_sset_count = &edma_get_strset_count, ++ .get_ethtool_stats = &edma_get_ethtool_stats, ++ .get_link = ðtool_op_get_link, ++ .get_link_ksettings = edma_get_link_ksettings, ++ .set_link_ksettings = edma_set_link_ksettings, ++ .get_pauseparam = &edma_get_pauseparam, ++ .set_pauseparam = &edma_set_pauseparam, ++ .get_eee = &edma_get_eee, ++ .set_eee = &edma_set_eee, ++}; ++ ++/** ++ * edma_set_ethtool_ops - Set ethtool operations ++ * @netdev: Netdevice ++ * ++ * Set ethtool operations. ++ */ ++void edma_set_ethtool_ops(struct net_device *netdev) ++{ ++ netdev->ethtool_ops = &edma_ethtool_ops; ++} +--- a/drivers/net/ethernet/qualcomm/ppe/edma_port.c ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_port.c +@@ -380,6 +380,7 @@ int edma_port_setup(struct ppe_port *por + netdev->priv_flags |= IFF_LIVE_ADDR_CHANGE; + netdev->netdev_ops = &edma_port_netdev_ops; + netdev->gso_max_segs = GSO_MAX_SEGS; ++ edma_set_ethtool_ops(netdev); + + maddr = mac_addr; + if (of_get_mac_address(np, maddr)) diff --git a/target/linux/qualcommbe/patches-6.12/0348-net-ethernet-qualcomm-Add-module-parameters-for-driv.patch b/target/linux/qualcommbe/patches-6.12/0348-net-ethernet-qualcomm-Add-module-parameters-for-driv.patch new file mode 100644 index 0000000000..65eb3c6c20 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0348-net-ethernet-qualcomm-Add-module-parameters-for-driv.patch @@ -0,0 +1,286 @@ +From 2ecec7e47e269e05cdd393c34aae51d4866070c6 Mon Sep 17 00:00:00 2001 +From: Pavithra R +Date: Tue, 11 Jun 2024 00:00:46 +0530 +Subject: [PATCH] net: ethernet: qualcomm: Add module parameters for driver + tunings + +Add module params and corresponding functionality for Tx/Rx +mitigation timer/packet count, napi budget and tx requeue stop. + +Change-Id: I1717559c931bba4f355ee06ab89f289818400ca2 +Signed-off-by: Pavithra R +--- + drivers/net/ethernet/qualcomm/ppe/edma.c | 35 +++++++++++++++++++ + .../net/ethernet/qualcomm/ppe/edma_cfg_rx.c | 29 +++++++++++++-- + .../net/ethernet/qualcomm/ppe/edma_cfg_rx.h | 21 +++++++++++ + .../net/ethernet/qualcomm/ppe/edma_cfg_tx.c | 29 +++++++++++++-- + .../net/ethernet/qualcomm/ppe/edma_cfg_tx.h | 16 +++++++++ + drivers/net/ethernet/qualcomm/ppe/edma_rx.h | 4 +++ + drivers/net/ethernet/qualcomm/ppe/edma_tx.h | 4 +++ + 7 files changed, 134 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/qualcomm/ppe/edma.c ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.c +@@ -38,6 +38,38 @@ static int rx_buff_size; + module_param(rx_buff_size, int, 0640); + MODULE_PARM_DESC(rx_buff_size, "Rx Buffer size for Jumbo MRU value (default:0)"); + ++int edma_rx_napi_budget = EDMA_RX_NAPI_WORK_DEF; ++module_param(edma_rx_napi_budget, int, 0444); ++MODULE_PARM_DESC(edma_rx_napi_budget, "Rx NAPI budget (default:128, min:16, max:512)"); ++ ++int edma_tx_napi_budget = EDMA_TX_NAPI_WORK_DEF; ++module_param(edma_tx_napi_budget, int, 0444); ++MODULE_PARM_DESC(edma_tx_napi_budget, "Tx NAPI budget (default:512 for ipq95xx, min:16, max:512)"); ++ ++int edma_rx_mitigation_pkt_cnt = EDMA_RX_MITIGATION_PKT_CNT_DEF; ++module_param(edma_rx_mitigation_pkt_cnt, int, 0444); ++MODULE_PARM_DESC(edma_rx_mitigation_pkt_cnt, ++ "Rx mitigation packet count value (default:16, min:0, max: 256)"); ++ ++s32 edma_rx_mitigation_timer = EDMA_RX_MITIGATION_TIMER_DEF; ++module_param(edma_rx_mitigation_timer, int, 0444); ++MODULE_PARM_DESC(edma_dp_rx_mitigation_timer, ++ "Rx mitigation timer value in microseconds (default:25, min:0, max: 1000)"); ++ ++int edma_tx_mitigation_timer = EDMA_TX_MITIGATION_TIMER_DEF; ++module_param(edma_tx_mitigation_timer, int, 0444); ++MODULE_PARM_DESC(edma_tx_mitigation_timer, ++ "Tx mitigation timer value in microseconds (default:250, min:0, max: 1000)"); ++ ++int edma_tx_mitigation_pkt_cnt = EDMA_TX_MITIGATION_PKT_CNT_DEF; ++module_param(edma_tx_mitigation_pkt_cnt, int, 0444); ++MODULE_PARM_DESC(edma_tx_mitigation_pkt_cnt, ++ "Tx mitigation packet count value (default:16, min:0, max: 256)"); ++ ++static int tx_requeue_stop; ++module_param(tx_requeue_stop, int, 0640); ++MODULE_PARM_DESC(tx_requeue_stop, "Disable Tx requeue function (default:0)"); ++ + /* Priority to multi-queue mapping. */ + static u8 edma_pri_map[PPE_QUEUE_INTER_PRI_NUM] = { + 0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7}; +@@ -828,7 +860,10 @@ int edma_setup(struct ppe_device *ppe_de + edma_ctx->hw_info = &ipq9574_hw_info; + edma_ctx->ppe_dev = ppe_dev; + edma_ctx->rx_buf_size = rx_buff_size; ++ + edma_ctx->tx_requeue_stop = false; ++ if (tx_requeue_stop != 0) ++ edma_ctx->tx_requeue_stop = true; + + /* Configure the EDMA common clocks. */ + ret = edma_clock_init(); +--- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c +@@ -166,6 +166,24 @@ static void edma_cfg_rx_desc_ring_config + reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_RING_SIZE(rxdesc_ring->ring_id); + regmap_write(regmap, reg, data); + ++ /* Validate mitigation timer value */ ++ if (edma_rx_mitigation_timer < EDMA_RX_MITIGATION_TIMER_MIN || ++ edma_rx_mitigation_timer > EDMA_RX_MITIGATION_TIMER_MAX) { ++ pr_err("Invalid Rx mitigation timer configured:%d for ring:%d. Using the default timer value:%d\n", ++ edma_rx_mitigation_timer, rxdesc_ring->ring_id, ++ EDMA_RX_MITIGATION_TIMER_DEF); ++ edma_rx_mitigation_timer = EDMA_RX_MITIGATION_TIMER_DEF; ++ } ++ ++ /* Validate mitigation packet count value */ ++ if (edma_rx_mitigation_pkt_cnt < EDMA_RX_MITIGATION_PKT_CNT_MIN || ++ edma_rx_mitigation_pkt_cnt > EDMA_RX_MITIGATION_PKT_CNT_MAX) { ++ pr_err("Invalid Rx mitigation packet count configured:%d for ring:%d. Using the default packet counter value:%d\n", ++ edma_rx_mitigation_timer, rxdesc_ring->ring_id, ++ EDMA_RX_MITIGATION_PKT_CNT_DEF); ++ edma_rx_mitigation_pkt_cnt = EDMA_RX_MITIGATION_PKT_CNT_DEF; ++ } ++ + /* Configure the Mitigation timer */ + data = EDMA_MICROSEC_TO_TIMER_UNIT(EDMA_RX_MITIGATION_TIMER_DEF, + ppe_dev->clk_rate / MHZ); +@@ -176,7 +194,7 @@ static void edma_cfg_rx_desc_ring_config + regmap_write(regmap, reg, data); + + /* Configure the Mitigation packet count */ +- data = (EDMA_RX_MITIGATION_PKT_CNT_DEF & EDMA_RXDESC_LOW_THRE_MASK) ++ data = (edma_rx_mitigation_pkt_cnt & EDMA_RXDESC_LOW_THRE_MASK) + << EDMA_RXDESC_LOW_THRE_SHIFT; + pr_debug("EDMA Rx mitigation packet count value: %d\n", data); + reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_UGT_THRE(rxdesc_ring->ring_id); +@@ -915,6 +933,13 @@ void edma_cfg_rx_napi_add(void) + struct edma_ring_info *rx = hw_info->rx; + u32 i; + ++ if (edma_rx_napi_budget < EDMA_RX_NAPI_WORK_MIN || ++ edma_rx_napi_budget > EDMA_RX_NAPI_WORK_MAX) { ++ pr_err("Incorrect Rx NAPI budget: %d, setting to default: %d", ++ edma_rx_napi_budget, hw_info->napi_budget_rx); ++ edma_rx_napi_budget = hw_info->napi_budget_rx; ++ } ++ + for (i = 0; i < rx->num_rings; i++) { + struct edma_rxdesc_ring *rxdesc_ring = &edma_ctx->rx_rings[i]; + +@@ -923,7 +948,7 @@ void edma_cfg_rx_napi_add(void) + rxdesc_ring->napi_added = true; + } + +- netdev_dbg(edma_ctx->dummy_dev, "Rx NAPI budget: %d\n", hw_info->napi_budget_rx); ++ netdev_dbg(edma_ctx->dummy_dev, "Rx NAPI budget: %d\n", edma_rx_napi_budget); + } + + /** +--- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h +@@ -5,6 +5,15 @@ + #ifndef __EDMA_CFG_RX__ + #define __EDMA_CFG_RX__ + ++/* Rx default NAPI budget */ ++#define EDMA_RX_NAPI_WORK_DEF 128 ++ ++/* RX minimum NAPI budget */ ++#define EDMA_RX_NAPI_WORK_MIN 16 ++ ++/* Rx maximum NAPI budget */ ++#define EDMA_RX_NAPI_WORK_MAX 512 ++ + /* SKB payload size used in page mode */ + #define EDMA_RX_PAGE_MODE_SKB_SIZE 256 + +@@ -22,9 +31,21 @@ + /* Rx mitigation timer's default value in microseconds */ + #define EDMA_RX_MITIGATION_TIMER_DEF 25 + ++/* Rx mitigation timer's minimum value in microseconds */ ++#define EDMA_RX_MITIGATION_TIMER_MIN 0 ++ ++/* Rx mitigation timer's maximum value in microseconds */ ++#define EDMA_RX_MITIGATION_TIMER_MAX 1000 ++ + /* Rx mitigation packet count's default value */ + #define EDMA_RX_MITIGATION_PKT_CNT_DEF 16 + ++/* Rx mitigation packet count's minimum value */ ++#define EDMA_RX_MITIGATION_PKT_CNT_MIN 0 ++ ++/* Rx mitigation packet count's maximum value */ ++#define EDMA_RX_MITIGATION_PKT_CNT_MAX 256 ++ + /* Default bitmap of cores for RPS to ARM cores */ + #define EDMA_RX_DEFAULT_BITMAP ((1 << EDMA_MAX_CORE) - 1) + +--- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.c ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.c +@@ -170,6 +170,24 @@ static void edma_cfg_txcmpl_ring_configu + reg = EDMA_BASE_OFFSET + EDMA_REG_TXCMPL_CTRL(txcmpl_ring->id); + regmap_write(regmap, reg, EDMA_TXCMPL_RETMODE_OPAQUE); + ++ /* Validate mitigation timer value */ ++ if (edma_tx_mitigation_timer < EDMA_TX_MITIGATION_TIMER_MIN || ++ edma_tx_mitigation_timer > EDMA_TX_MITIGATION_TIMER_MAX) { ++ pr_err("Invalid Tx mitigation timer configured:%d for ring:%d. Using the default timer value:%d\n", ++ edma_tx_mitigation_timer, txcmpl_ring->id, ++ EDMA_TX_MITIGATION_TIMER_DEF); ++ edma_tx_mitigation_timer = EDMA_TX_MITIGATION_TIMER_DEF; ++ } ++ ++ /* Validate mitigation packet count value */ ++ if (edma_tx_mitigation_pkt_cnt < EDMA_TX_MITIGATION_PKT_CNT_MIN || ++ edma_tx_mitigation_pkt_cnt > EDMA_TX_MITIGATION_PKT_CNT_MAX) { ++ pr_err("Invalid Tx mitigation packet count configured:%d for ring:%d. Using the default packet counter value:%d\n", ++ edma_tx_mitigation_timer, txcmpl_ring->id, ++ EDMA_TX_MITIGATION_PKT_CNT_DEF); ++ edma_tx_mitigation_pkt_cnt = EDMA_TX_MITIGATION_PKT_CNT_DEF; ++ } ++ + /* Configure the Mitigation timer. */ + data = EDMA_MICROSEC_TO_TIMER_UNIT(EDMA_TX_MITIGATION_TIMER_DEF, + ppe_dev->clk_rate / MHZ); +@@ -180,7 +198,7 @@ static void edma_cfg_txcmpl_ring_configu + regmap_write(regmap, reg, data); + + /* Configure the Mitigation packet count. */ +- data = (EDMA_TX_MITIGATION_PKT_CNT_DEF & EDMA_TXCMPL_LOW_THRE_MASK) ++ data = (edma_tx_mitigation_pkt_cnt & EDMA_TXCMPL_LOW_THRE_MASK) + << EDMA_TXCMPL_LOW_THRE_SHIFT; + pr_debug("EDMA Tx mitigation packet count value: %d\n", data); + reg = EDMA_BASE_OFFSET + EDMA_REG_TXCMPL_UGT_THRE(txcmpl_ring->id); +@@ -634,6 +652,13 @@ void edma_cfg_tx_napi_add(struct net_dev + struct edma_txcmpl_ring *txcmpl_ring; + u32 i, ring_idx; + ++ if (edma_tx_napi_budget < EDMA_TX_NAPI_WORK_MIN || ++ edma_tx_napi_budget > EDMA_TX_NAPI_WORK_MAX) { ++ pr_err("Incorrect Tx NAPI budget: %d, setting to default: %d", ++ edma_tx_napi_budget, hw_info->napi_budget_tx); ++ edma_tx_napi_budget = hw_info->napi_budget_tx; ++ } ++ + /* Adding tx napi for a interface with each queue. */ + for_each_possible_cpu(i) { + ring_idx = ((port_id - 1) * num_possible_cpus()) + i; +@@ -644,5 +669,5 @@ void edma_cfg_tx_napi_add(struct net_dev + netdev_dbg(netdev, "Napi added for txcmpl ring: %u\n", txcmpl_ring->id); + } + +- netdev_dbg(netdev, "Tx NAPI budget: %d\n", hw_info->napi_budget_tx); ++ netdev_dbg(netdev, "Tx NAPI budget: %d\n", edma_tx_napi_budget); + } +--- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.h +@@ -5,12 +5,28 @@ + #ifndef __EDMA_CFG_TX__ + #define __EDMA_CFG_TX__ + ++#define EDMA_TX_NAPI_WORK_DEF 512 ++#define EDMA_TX_NAPI_WORK_MIN 16 ++#define EDMA_TX_NAPI_WORK_MAX 512 ++ + /* Tx mitigation timer's default value. */ + #define EDMA_TX_MITIGATION_TIMER_DEF 250 + ++/* Tx mitigation timer's minimum value in microseconds */ ++#define EDMA_TX_MITIGATION_TIMER_MIN 0 ++ ++/* Tx mitigation timer's maximum value in microseconds */ ++#define EDMA_TX_MITIGATION_TIMER_MAX 1000 ++ + /* Tx mitigation packet count default value. */ + #define EDMA_TX_MITIGATION_PKT_CNT_DEF 16 + ++/* Tx mitigation packet count's minimum value */ ++#define EDMA_TX_MITIGATION_PKT_CNT_MIN 0 ++ ++/* Tx mitigation packet count's maximum value */ ++#define EDMA_TX_MITIGATION_PKT_CNT_MAX 256 ++ + void edma_cfg_tx_rings(void); + int edma_cfg_tx_rings_alloc(void); + void edma_cfg_tx_rings_cleanup(void); +--- a/drivers/net/ethernet/qualcomm/ppe/edma_rx.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_rx.h +@@ -281,6 +281,10 @@ struct edma_rxdesc_ring { + struct sk_buff *last; + }; + ++extern int edma_rx_napi_budget; ++extern int edma_rx_mitigation_timer; ++extern int edma_rx_mitigation_pkt_cnt; ++ + irqreturn_t edma_rx_handle_irq(int irq, void *ctx); + int edma_rx_alloc_buffer(struct edma_rxfill_ring *rxfill_ring, int alloc_count); + int edma_rx_napi_poll(struct napi_struct *napi, int budget); +--- a/drivers/net/ethernet/qualcomm/ppe/edma_tx.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_tx.h +@@ -288,6 +288,10 @@ struct edma_txcmpl_ring { + bool napi_added; + }; + ++extern int edma_tx_napi_budget; ++extern int edma_tx_mitigation_timer; ++extern int edma_tx_mitigation_pkt_cnt; ++ + enum edma_tx_status edma_tx_ring_xmit(struct net_device *netdev, + struct sk_buff *skb, + struct edma_txdesc_ring *txdesc_ring, diff --git a/target/linux/qualcommbe/patches-6.12/0349-net-ethernet-qualcomm-Add-sysctl-for-RPS-bitmap.patch b/target/linux/qualcommbe/patches-6.12/0349-net-ethernet-qualcomm-Add-sysctl-for-RPS-bitmap.patch new file mode 100644 index 0000000000..c6970015d7 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0349-net-ethernet-qualcomm-Add-sysctl-for-RPS-bitmap.patch @@ -0,0 +1,145 @@ +From dcac735a715c13a817d65ae371564cf2793330b2 Mon Sep 17 00:00:00 2001 +From: Pavithra R +Date: Tue, 11 Jun 2024 01:43:22 +0530 +Subject: [PATCH] net: ethernet: qualcomm: Add sysctl for RPS bitmap + +Add sysctl to configure RPS bitmap for EDMA receive. +This bitmap is used to configure the set of ARM cores +used to receive packets from EDMA. + +Change-Id: Ie0e7d5971db93ea1494608a9e79c4abb13ce69b6 +Signed-off-by: Pavithra R +Alex G: Use **const** ctl_table argument for .proc_handler +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/ethernet/qualcomm/ppe/edma.c | 23 ++++++++++++++++ + drivers/net/ethernet/qualcomm/ppe/edma.h | 2 ++ + .../net/ethernet/qualcomm/ppe/edma_cfg_rx.c | 27 +++++++++++++++++++ + .../net/ethernet/qualcomm/ppe/edma_cfg_rx.h | 6 ++++- + 4 files changed, 57 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/qualcomm/ppe/edma.c ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.c +@@ -797,6 +797,11 @@ void edma_destroy(struct ppe_device *ppe + struct edma_ring_info *rx = hw_info->rx; + u32 i; + ++ if (edma_ctx->rx_rps_ctl_table_hdr) { ++ unregister_sysctl_table(edma_ctx->rx_rps_ctl_table_hdr); ++ edma_ctx->rx_rps_ctl_table_hdr = NULL; ++ } ++ + /* Disable interrupts. */ + for (i = 1; i <= hw_info->max_ports; i++) + edma_cfg_tx_disable_interrupts(i); +@@ -840,6 +845,17 @@ void edma_destroy(struct ppe_device *ppe + kfree(edma_ctx->netdev_arr); + } + ++/* EDMA Rx RPS core sysctl table */ ++static struct ctl_table edma_rx_rps_core_table[] = { ++ { ++ .procname = "rps_bitmap_cores", ++ .data = &edma_cfg_rx_rps_bitmap_cores, ++ .maxlen = sizeof(int), ++ .mode = 0644, ++ .proc_handler = edma_cfg_rx_rps_bitmap ++ }, ++}; ++ + /** + * edma_setup - EDMA Setup. + * @ppe_dev: PPE device +@@ -865,6 +881,13 @@ int edma_setup(struct ppe_device *ppe_de + if (tx_requeue_stop != 0) + edma_ctx->tx_requeue_stop = true; + ++ edma_ctx->rx_rps_ctl_table_hdr = register_sysctl("net/edma", ++ edma_rx_rps_core_table); ++ if (!edma_ctx->rx_rps_ctl_table_hdr) { ++ pr_err("Rx rps sysctl table configuration failed\n"); ++ return -EINVAL; ++ } ++ + /* Configure the EDMA common clocks. */ + ret = edma_clock_init(); + if (ret) { +--- a/drivers/net/ethernet/qualcomm/ppe/edma.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma.h +@@ -132,6 +132,7 @@ struct edma_intr_info { + * @tx_rings: Tx Descriptor Ring, SW is producer + * @txcmpl_rings: Tx complete Ring, SW is consumer + * @err_stats: Per CPU error statistics ++ * @rx_rps_ctl_table_hdr: Rx RPS sysctl table + * @rx_page_mode: Page mode enabled or disabled + * @rx_buf_size: Rx buffer size for Jumbo MRU + * @tx_requeue_stop: Tx requeue stop enabled or disabled +@@ -147,6 +148,7 @@ struct edma_context { + struct edma_txdesc_ring *tx_rings; + struct edma_txcmpl_ring *txcmpl_rings; + struct edma_err_stats __percpu *err_stats; ++ struct ctl_table_header *rx_rps_ctl_table_hdr; + u32 rx_page_mode; + u32 rx_buf_size; + bool tx_requeue_stop; +--- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c +@@ -43,6 +43,8 @@ static u32 edma_rx_ring_queue_map[][EDMA + { 6, 14, 22, 30 }, + { 7, 15, 23, 31 }}; + ++u32 edma_cfg_rx_rps_bitmap_cores = EDMA_RX_DEFAULT_BITMAP; ++ + static int edma_cfg_rx_desc_rings_reset_queue_mapping(void) + { + struct edma_hw_info *hw_info = edma_ctx->hw_info; +@@ -987,3 +989,28 @@ int edma_cfg_rx_rps_hash_map(void) + + return 0; + } ++ ++/* Configure RPS hash mapping based on bitmap */ ++int edma_cfg_rx_rps_bitmap(const struct ctl_table *table, int write, ++ void *buffer, size_t *lenp, loff_t *ppos) ++{ ++ int ret; ++ ++ ret = proc_dointvec(table, write, buffer, lenp, ppos); ++ ++ if (!write) ++ return ret; ++ ++ if (!edma_cfg_rx_rps_bitmap_cores || ++ edma_cfg_rx_rps_bitmap_cores > EDMA_RX_DEFAULT_BITMAP) { ++ pr_warn("Incorrect CPU bitmap: %x. Setting it to default value: %d", ++ edma_cfg_rx_rps_bitmap_cores, EDMA_RX_DEFAULT_BITMAP); ++ edma_cfg_rx_rps_bitmap_cores = EDMA_RX_DEFAULT_BITMAP; ++ } ++ ++ ret = edma_cfg_rx_rps_hash_map(); ++ ++ pr_info("EDMA RPS bitmap value: %d\n", edma_cfg_rx_rps_bitmap_cores); ++ ++ return ret; ++} +--- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h +@@ -49,6 +49,8 @@ + /* Default bitmap of cores for RPS to ARM cores */ + #define EDMA_RX_DEFAULT_BITMAP ((1 << EDMA_MAX_CORE) - 1) + ++extern u32 edma_cfg_rx_rps_bitmap_cores; ++ + int edma_cfg_rx_rings(void); + int edma_cfg_rx_rings_alloc(void); + void edma_cfg_rx_ring_mappings(void); +@@ -64,6 +66,8 @@ void edma_cfg_rx_rings_enable(void); + void edma_cfg_rx_rings_disable(void); + void edma_cfg_rx_buff_size_setup(void); + int edma_cfg_rx_rps_hash_map(void); +-int edma_cfg_rx_rps(struct ctl_table *table, int write, ++int edma_cfg_rx_rps(const struct ctl_table *table, int write, + void *buffer, size_t *lenp, loff_t *ppos); ++int edma_cfg_rx_rps_bitmap(const struct ctl_table *table, int write, ++ void *buffer, size_t *lenp, loff_t *ppos); + #endif diff --git a/target/linux/qualcommbe/patches-6.12/0350-net-ethernet-qualcomm-Add-support-for-label-property.patch b/target/linux/qualcommbe/patches-6.12/0350-net-ethernet-qualcomm-Add-support-for-label-property.patch new file mode 100644 index 0000000000..79af169c8e --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0350-net-ethernet-qualcomm-Add-support-for-label-property.patch @@ -0,0 +1,48 @@ +From a809433c9b6a418dd886f12a5dcb3376f73bf2a7 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 4 Dec 2024 01:37:05 +0100 +Subject: [PATCH] net: ethernet: qualcomm: Add support for label property for + EDMA port + +Add support for label property for EDMA port. This is useful to define +custom name in DTS for specific ethernet port instead of assigning a +dynamic name at runtime. + +This also improve the log output by using modern APIs. + +Signed-off-by: Christian Marangi +--- + drivers/net/ethernet/qualcomm/ppe/edma_port.c | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +--- a/drivers/net/ethernet/qualcomm/ppe/edma_port.c ++++ b/drivers/net/ethernet/qualcomm/ppe/edma_port.c +@@ -355,13 +355,25 @@ int edma_port_setup(struct ppe_port *por + int port_id = port->port_id; + struct net_device *netdev; + u8 mac_addr[ETH_ALEN]; ++ const char *name; ++ int assign_type; + int ret = 0; + u8 *maddr; + +- netdev = alloc_etherdev_mqs(sizeof(struct edma_port_priv), +- EDMA_NETDEV_QUEUE_NUM, EDMA_NETDEV_QUEUE_NUM); ++ name = of_get_property(np, "label", NULL); ++ if (name) { ++ assign_type = NET_NAME_PREDICTABLE; ++ } else { ++ name = "eth%d"; ++ assign_type = NET_NAME_ENUM; ++ } ++ ++ netdev = alloc_netdev_mqs(sizeof(struct edma_port_priv), ++ name, assign_type, ++ ether_setup, ++ EDMA_NETDEV_QUEUE_NUM, EDMA_NETDEV_QUEUE_NUM); + if (!netdev) { +- pr_err("alloc_etherdev() failed\n"); ++ dev_err(ppe_dev->dev, "alloc_netdev_mqs() failed\n"); + return -ENOMEM; + } + diff --git a/target/linux/qualcommbe/patches-6.12/0351-net-ethernet-qualcomm-ppe-Fix-unmet-dependency-with-.patch b/target/linux/qualcommbe/patches-6.12/0351-net-ethernet-qualcomm-ppe-Fix-unmet-dependency-with-.patch new file mode 100644 index 0000000000..a0d15cf2a0 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0351-net-ethernet-qualcomm-ppe-Fix-unmet-dependency-with-.patch @@ -0,0 +1,30 @@ +From 9c4ad75f17788a64c1e37d0b9e19ca157e01c80a Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 9 Dec 2024 18:19:06 +0100 +Subject: [PATCH] net: ethernet: qualcomm: ppe: Fix unmet dependency with + QCOM_PPE + +Fix unmet dependency with QCOM_PPE on selecting SFP. + +WARNING: unmet direct dependencies detected for SFP + Depends on [m]: NETDEVICES [=y] && PHYLIB [=y] && I2C [=y] && PHYLINK [=y] && (HWMON [=m] || HWMON [=m]=n [=n]) + Selected by [y]: + - QCOM_PPE [=y] && NETDEVICES [=y] && ETHERNET [=y] && NET_VENDOR_QUALCOMM [=y] && HAS_IOMEM [=y] && OF [=y] && COMMON_CLK [=y] + +This permit correct compilation of the modules with SFP enabled. + +Signed-off-by: Christian Marangi +--- + drivers/net/ethernet/qualcomm/Kconfig | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/net/ethernet/qualcomm/Kconfig ++++ b/drivers/net/ethernet/qualcomm/Kconfig +@@ -68,7 +68,6 @@ config QCOM_PPE + select REGMAP_MMIO + select PHYLINK + select PCS_QCOM_IPQ_UNIPHY +- select SFP + help + This driver supports the Qualcomm Technologies, Inc. packet + process engine (PPE) available with IPQ SoC. The PPE includes diff --git a/target/linux/qualcommbe/patches-6.12/0352-net-ethernet-qualcomm-ppe-select-correct-PCS-depende.patch b/target/linux/qualcommbe/patches-6.12/0352-net-ethernet-qualcomm-ppe-select-correct-PCS-depende.patch new file mode 100644 index 0000000000..3893c5cd8d --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0352-net-ethernet-qualcomm-ppe-select-correct-PCS-depende.patch @@ -0,0 +1,24 @@ +From ac41b401d274a4004027fa4000d801cd28c51f4c Mon Sep 17 00:00:00 2001 +From: Alexandru Gagniuc +Date: Tue, 13 May 2025 13:41:37 -0500 +Subject: [PATCH] net: ethernet: qualcomm: ppe: select correct PCS dependency + +The config symbol for the PCS driver has changed to PCS_QCOM_IPQ9574, +since the original submission. Update Kconfig accordingly. + +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/ethernet/qualcomm/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/qualcomm/Kconfig ++++ b/drivers/net/ethernet/qualcomm/Kconfig +@@ -67,7 +67,7 @@ config QCOM_PPE + depends on COMMON_CLK + select REGMAP_MMIO + select PHYLINK +- select PCS_QCOM_IPQ_UNIPHY ++ select PCS_QCOM_IPQ9574 + help + This driver supports the Qualcomm Technologies, Inc. packet + process engine (PPE) available with IPQ SoC. The PPE includes diff --git a/target/linux/qualcommbe/patches-6.12/0353-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch b/target/linux/qualcommbe/patches-6.12/0353-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch new file mode 100644 index 0000000000..a243c00961 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0353-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch @@ -0,0 +1,72 @@ +From bbf706ecfd4295d73c8217d5220573dd51d7a081 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Fri, 1 Mar 2024 14:46:45 +0800 +Subject: [PATCH] arm64: dts: qcom: Add IPQ9574 PPE base device node + +PPE is the packet process engine on the Qualcomm IPQ platform, +which is connected with the external switch or PHY device via +the UNIPHY (PCS). + +Change-Id: I254bd48c218aa4eab54f697a2ad149f5a93b682c +Signed-off-by: Luo Jie +Alex G: Add "qcom_ppe" label to PPE node +Signed-off-by: Alexandru Gagniuc +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 39 +++++++++++++++++++++++++++ + 1 file changed, 39 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + + / { +@@ -1269,6 +1270,44 @@ + #interconnect-cells = <1>; + }; + ++ qcom_ppe: ethernet@3a000000 { ++ compatible = "qcom,ipq9574-ppe"; ++ reg = <0x3a000000 0xbef800>; ++ ranges; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&nsscc NSS_CC_PPE_SWITCH_CLK>, ++ <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>, ++ <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>, ++ <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>; ++ clock-names = "ppe", ++ "ppe_cfg", ++ "ppe_ipe", ++ "ppe_btq"; ++ resets = <&nsscc PPE_FULL_RESET>; ++ interconnects = <&nsscc MASTER_NSSNOC_PPE ++ &nsscc SLAVE_NSSNOC_PPE>, ++ <&nsscc MASTER_NSSNOC_PPE_CFG ++ &nsscc SLAVE_NSSNOC_PPE_CFG>, ++ <&gcc MASTER_NSSNOC_QOSGEN_REF ++ &gcc SLAVE_NSSNOC_QOSGEN_REF>, ++ <&gcc MASTER_NSSNOC_TIMEOUT_REF ++ &gcc SLAVE_NSSNOC_TIMEOUT_REF>, ++ <&gcc MASTER_MEM_NOC_NSSNOC ++ &gcc SLAVE_MEM_NOC_NSSNOC>, ++ <&gcc MASTER_NSSNOC_MEMNOC ++ &gcc SLAVE_NSSNOC_MEMNOC>, ++ <&gcc MASTER_NSSNOC_MEM_NOC_1 ++ &gcc SLAVE_NSSNOC_MEM_NOC_1>; ++ interconnect-names = "ppe", ++ "ppe_cfg", ++ "qos_gen", ++ "timeout_ref", ++ "nssnoc_memnoc", ++ "memnoc_nssnoc", ++ "memnoc_nssnoc_1"; ++ }; ++ + pcs_uniphy0: ethernet-pcs@7a00000 { + compatible = "qcom,ipq9574-pcs"; + reg = <0x7a00000 0x10000>; diff --git a/target/linux/qualcommbe/patches-6.12/0354-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch b/target/linux/qualcommbe/patches-6.12/0354-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch new file mode 100644 index 0000000000..74187f532d --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0354-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch @@ -0,0 +1,91 @@ +From bd50babc7db2a35d98236a0386173dccd6c6374b Mon Sep 17 00:00:00 2001 +From: Pavithra R +Date: Wed, 6 Mar 2024 22:29:41 +0530 +Subject: [PATCH] arm64: dts: qcom: Add EDMA node for IPQ9574 + +Add EDMA (Ethernet DMA) device tree node for IPQ9574 to +enable ethernet support. + +Change-Id: I87d7c50f2485c8670948dce305000337f6499f8b +Signed-off-by: Pavithra R +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 68 +++++++++++++++++++++++++++ + 1 file changed, 68 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -1306,6 +1306,74 @@ + "nssnoc_memnoc", + "memnoc_nssnoc", + "memnoc_nssnoc_1"; ++ ++ edma { ++ compatible = "qcom,ipq9574-edma"; ++ clocks = <&nsscc NSS_CC_PPE_EDMA_CLK>, ++ <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>; ++ clock-names = "edma", ++ "edma-cfg"; ++ resets = <&nsscc EDMA_HW_RESET>; ++ reset-names = "edma_rst"; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "edma_txcmpl_8", ++ "edma_txcmpl_9", ++ "edma_txcmpl_10", ++ "edma_txcmpl_11", ++ "edma_txcmpl_12", ++ "edma_txcmpl_13", ++ "edma_txcmpl_14", ++ "edma_txcmpl_15", ++ "edma_txcmpl_16", ++ "edma_txcmpl_17", ++ "edma_txcmpl_18", ++ "edma_txcmpl_19", ++ "edma_txcmpl_20", ++ "edma_txcmpl_21", ++ "edma_txcmpl_22", ++ "edma_txcmpl_23", ++ "edma_txcmpl_24", ++ "edma_txcmpl_25", ++ "edma_txcmpl_26", ++ "edma_txcmpl_27", ++ "edma_txcmpl_28", ++ "edma_txcmpl_29", ++ "edma_txcmpl_30", ++ "edma_txcmpl_31", ++ "edma_rxdesc_20", ++ "edma_rxdesc_21", ++ "edma_rxdesc_22", ++ "edma_rxdesc_23", ++ "edma_misc"; ++ }; + }; + + pcs_uniphy0: ethernet-pcs@7a00000 { diff --git a/target/linux/qualcommbe/patches-6.12/0355-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch b/target/linux/qualcommbe/patches-6.12/0355-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch new file mode 100644 index 0000000000..708c0c8a63 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0355-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch @@ -0,0 +1,197 @@ +From 001b663ecc5f838dac143623badae0e472749d8a Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Tue, 14 May 2024 10:53:27 +0800 +Subject: [PATCH] arm64: dts: qcom: Add IPQ9574 RDP433 port node + +There are 6 PPE MAC ports available on RDP433. The port1-port4 are +connected with QCA8075 QUAD PHYs through UNIPHY0 PCS channel0-channel3. +The port5 is connected with Aquantia PHY through UNIPHY1 PCS channel0 +and the port6 is connected with Aquantia PHY through UNIPHY2 PCS +channel0. + +Change-Id: Ic16efdef2fe2cff7b1e80245619c0f82afb24cb9 +Signed-off-by: Lei Wei +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 167 ++++++++++++++++++++ + 1 file changed, 167 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +@@ -55,6 +55,46 @@ + status = "okay"; + }; + ++&mdio { ++ reset-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>; ++ clock-frequency = <6250000>; ++ status = "okay"; ++ ++ ethernet-phy-package@0 { ++ compatible = "qcom,qca8075-package"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x10>; ++ qcom,package-mode = "qsgmii"; ++ ++ phy0: ethernet-phy@10 { ++ reg = <0x10>; ++ }; ++ ++ phy1: ethernet-phy@11 { ++ reg = <0x11>; ++ }; ++ ++ phy2: ethernet-phy@12 { ++ reg = <0x12>; ++ }; ++ ++ phy3: ethernet-phy@13 { ++ reg = <0x13>; ++ }; ++ }; ++ ++ phy4: ethernet-phy@8 { ++ compatible ="ethernet-phy-ieee802.3-c45"; ++ reg = <8>; ++ }; ++ ++ phy5: ethernet-phy@0 { ++ compatible ="ethernet-phy-ieee802.3-c45"; ++ reg = <0>; ++ }; ++}; ++ + &tlmm { + + pcie1_default: pcie1-default-state { +@@ -161,3 +201,130 @@ + }; + }; + }; ++ ++&qcom_ppe { ++ ethernet-ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ phy-mode = "qsgmii"; ++ managed = "in-band-status"; ++ phy-handle = <&phy0>; ++ pcs-handle = <&pcsuniphy0_ch0>; ++ clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>, ++ <&nsscc NSS_CC_PORT1_RX_CLK>, ++ <&nsscc NSS_CC_PORT1_TX_CLK>; ++ clock-names = "port_mac", ++ "port_rx", ++ "port_tx"; ++ resets = <&nsscc PORT1_MAC_ARES>, ++ <&nsscc PORT1_RX_ARES>, ++ <&nsscc PORT1_TX_ARES>; ++ reset-names = "port_mac", ++ "port_rx", ++ "port_tx"; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ phy-mode = "qsgmii"; ++ managed = "in-band-status"; ++ phy-handle = <&phy1>; ++ pcs-handle = <&pcsuniphy0_ch1>; ++ clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>, ++ <&nsscc NSS_CC_PORT2_RX_CLK>, ++ <&nsscc NSS_CC_PORT2_TX_CLK>; ++ clock-names = "port_mac", ++ "port_rx", ++ "port_tx"; ++ resets = <&nsscc PORT2_MAC_ARES>, ++ <&nsscc PORT2_RX_ARES>, ++ <&nsscc PORT2_TX_ARES>; ++ reset-names = "port_mac", ++ "port_rx", ++ "port_tx"; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ phy-mode = "qsgmii"; ++ managed = "in-band-status"; ++ phy-handle = <&phy2>; ++ pcs-handle = <&pcsuniphy0_ch2>; ++ clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>, ++ <&nsscc NSS_CC_PORT3_RX_CLK>, ++ <&nsscc NSS_CC_PORT3_TX_CLK>; ++ clock-names = "port_mac", ++ "port_rx", ++ "port_tx"; ++ resets = <&nsscc PORT3_MAC_ARES>, ++ <&nsscc PORT3_RX_ARES>, ++ <&nsscc PORT3_TX_ARES>; ++ reset-names = "port_mac", ++ "port_rx", ++ "port_tx"; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ phy-mode = "qsgmii"; ++ managed = "in-band-status"; ++ phy-handle = <&phy3>; ++ pcs-handle = <&pcsuniphy0_ch3>; ++ clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>, ++ <&nsscc NSS_CC_PORT4_RX_CLK>, ++ <&nsscc NSS_CC_PORT4_TX_CLK>; ++ clock-names = "port_mac", ++ "port_rx", ++ "port_tx"; ++ resets = <&nsscc PORT4_MAC_ARES>, ++ <&nsscc PORT4_RX_ARES>, ++ <&nsscc PORT4_TX_ARES>; ++ reset-names = "port_mac", ++ "port_rx", ++ "port_tx"; ++ }; ++ ++ port@5 { ++ reg = <5>; ++ phy-mode = "usxgmii"; ++ managed = "in-band-status"; ++ phy-handle = <&phy4>; ++ pcs-handle = <&pcsuniphy1_ch0>; ++ clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>, ++ <&nsscc NSS_CC_PORT5_RX_CLK>, ++ <&nsscc NSS_CC_PORT5_TX_CLK>; ++ clock-names = "port_mac", ++ "port_rx", ++ "port_tx"; ++ resets = <&nsscc PORT5_MAC_ARES>, ++ <&nsscc PORT5_RX_ARES>, ++ <&nsscc PORT5_TX_ARES>; ++ reset-names = "port_mac", ++ "port_rx", ++ "port_tx"; ++ }; ++ ++ port@6 { ++ reg = <6>; ++ phy-mode = "usxgmii"; ++ managed = "in-band-status"; ++ phy-handle = <&phy5>; ++ pcs-handle = <&pcsuniphy2_ch0>; ++ clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>, ++ <&nsscc NSS_CC_PORT6_RX_CLK>, ++ <&nsscc NSS_CC_PORT6_TX_CLK>; ++ clock-names = "port_mac", ++ "port_rx", ++ "port_tx"; ++ resets = <&nsscc PORT6_MAC_ARES>, ++ <&nsscc PORT6_RX_ARES>, ++ <&nsscc PORT6_TX_ARES>; ++ reset-names = "port_mac", ++ "port_rx", ++ "port_tx"; ++ }; ++ }; ++}; diff --git a/target/linux/qualcommbe/patches-6.12/0356-arm64-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433.patch b/target/linux/qualcommbe/patches-6.12/0356-arm64-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433.patch new file mode 100644 index 0000000000..e508bad9a6 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0356-arm64-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433.patch @@ -0,0 +1,33 @@ +From 30b751f5984e295f0b5e7a2308b6103fae3322d2 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 9 Dec 2024 18:10:43 +0100 +Subject: [PATCH] arm64: dts: qcom: add AQR NVMEM node for IPQ9574 RDP433 board + +Add Aquantia NVMEM node for IPQ9574 RDP433 board to load the firmware +for the Aquantia PHY. + +Signed-off-by: Christian Marangi +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +@@ -87,11 +87,17 @@ + phy4: ethernet-phy@8 { + compatible ="ethernet-phy-ieee802.3-c45"; + reg = <8>; ++ ++ nvmem-cells = <&aqr_fw>; ++ nvmem-cell-names = "firmware"; + }; + + phy5: ethernet-phy@0 { + compatible ="ethernet-phy-ieee802.3-c45"; + reg = <0>; ++ ++ nvmem-cells = <&aqr_fw>; ++ nvmem-cell-names = "firmware"; + }; + }; + diff --git a/target/linux/qualcommbe/patches-6.12/0357-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch b/target/linux/qualcommbe/patches-6.12/0357-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch new file mode 100644 index 0000000000..bac7f16635 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0357-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch @@ -0,0 +1,62 @@ +From b297d12d434191845cf8ae359466dcd8312ed21d Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 4 Dec 2024 01:49:09 +0100 +Subject: [PATCH] arm64: dts: qcom: Add label to EDMA port for IPQ9574 RDP433 + +Add label to EDMA port for IPQ9574 RDP433 board. + +Signed-off-by: Christian Marangi +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +@@ -217,6 +217,7 @@ + reg = <1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; ++ label = "lan1"; + phy-handle = <&phy0>; + pcs-handle = <&pcsuniphy0_ch0>; + clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>, +@@ -237,6 +238,7 @@ + reg = <2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; ++ label = "lan2"; + phy-handle = <&phy1>; + pcs-handle = <&pcsuniphy0_ch1>; + clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>, +@@ -257,6 +259,7 @@ + reg = <3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; ++ label = "lan3"; + phy-handle = <&phy2>; + pcs-handle = <&pcsuniphy0_ch2>; + clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>, +@@ -277,6 +280,7 @@ + reg = <4>; + phy-mode = "qsgmii"; + managed = "in-band-status"; ++ label = "lan4"; + phy-handle = <&phy3>; + pcs-handle = <&pcsuniphy0_ch3>; + clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>, +@@ -297,6 +301,7 @@ + reg = <5>; + phy-mode = "usxgmii"; + managed = "in-band-status"; ++ label = "lan5"; + phy-handle = <&phy4>; + pcs-handle = <&pcsuniphy1_ch0>; + clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>, +@@ -317,6 +322,7 @@ + reg = <6>; + phy-mode = "usxgmii"; + managed = "in-band-status"; ++ label = "wan"; + phy-handle = <&phy5>; + pcs-handle = <&pcsuniphy2_ch0>; + clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>, diff --git a/target/linux/qualcommbe/patches-6.12/0358-clk-qcom-nsscc-Attach-required-NSSNOC-clock-to-PM-do.patch b/target/linux/qualcommbe/patches-6.12/0358-clk-qcom-nsscc-Attach-required-NSSNOC-clock-to-PM-do.patch new file mode 100644 index 0000000000..372572a24e --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0358-clk-qcom-nsscc-Attach-required-NSSNOC-clock-to-PM-do.patch @@ -0,0 +1,73 @@ +From 6417cb20e854194a845d4ab092b92fd753c0e405 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 30 Jan 2025 16:11:14 +0100 +Subject: [PATCH] clk: qcom: nsscc: Attach required NSSNOC clock to PM domain + +There is currently a problem with ICC clock disabling the NSSNOC clock +as there isn't any user for them on calling sync_state. +This cause the kernel to stall if NSS is enabled and reboot with the watchdog. + +This is caused by the fact that the NSSNOC clock nsscc, snoc and snoc_1 +are actually required to make the NSS work and make the system continue +booting. + +To attach these clock, setup pm-clk in nsscc and setup the correct +resume/suspend OPs. + +With this change, the clock gets correctly attached and are not disabled +when ICC call the sync_state. + +Suggested-by: Dmitry Baryshkov +Signed-off-by: Christian Marangi +Alex G: Retrieve clocks by name rather than index. +Signed-off-by: Alexandru Gagniuc +--- + drivers/clk/qcom/nsscc-ipq9574.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/drivers/clk/qcom/nsscc-ipq9574.c ++++ b/drivers/clk/qcom/nsscc-ipq9574.c +@@ -3060,6 +3060,7 @@ MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_m + + static int nss_cc_ipq9574_probe(struct platform_device *pdev) + { ++ struct device *dev = &pdev->dev; + struct regmap *regmap; + int ret; + +@@ -3075,6 +3076,18 @@ static int nss_cc_ipq9574_probe(struct p + if (ret) + return dev_err_probe(&pdev->dev, ret, "Fail to add bus clock\n"); + ++ ret = pm_clk_add(&pdev->dev, "nssnoc"); ++ if (ret) ++ return dev_err_probe(dev, ret,"failed to acquire nssnoc clock\n"); ++ ++ ret = pm_clk_add(&pdev->dev, "snoc"); ++ if (ret) ++ return dev_err_probe(dev, ret,"failed to acquire snoc clock\n"); ++ ++ ret = pm_clk_add(&pdev->dev, "snoc_1"); ++ if (ret) ++ return dev_err_probe(dev, ret,"failed to acquire snoc_1 clock\n"); ++ + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Fail to resume\n"); +@@ -3089,8 +3102,16 @@ static int nss_cc_ipq9574_probe(struct p + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + + ret = qcom_cc_really_probe(&pdev->dev, &nss_cc_ipq9574_desc, regmap); ++ if (ret) ++ goto err_put_pm; ++ + pm_runtime_put(&pdev->dev); + ++ return 0; ++ ++err_put_pm: ++ pm_runtime_put_sync(dev); ++ + return ret; + } + diff --git a/target/linux/qualcommbe/patches-6.12/0359-arm64-dts-qcom-ipq9574-add-NSSNOC-clock-to-nss-node.patch b/target/linux/qualcommbe/patches-6.12/0359-arm64-dts-qcom-ipq9574-add-NSSNOC-clock-to-nss-node.patch new file mode 100644 index 0000000000..774f3ed1a7 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0359-arm64-dts-qcom-ipq9574-add-NSSNOC-clock-to-nss-node.patch @@ -0,0 +1,42 @@ +From 372bbae100ffe14908bfd8448143c6cdbea17e8d Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 30 Jan 2025 16:23:03 +0100 +Subject: [PATCH] arm64: dts: qcom: ipq9574: add NSSNOC clock to nss node + +Add NSSNOC clock to nss node to attach the clock with PM clock and fix +the boot stall after ICC sync_state. + +Signed-off-by: Christian Marangi +Alex G: Do not remove GCC_NSSCC_CLK ("bus") clock + Add clock-names for the new clocks +Signed-off-by: Alexandru Gagniuc +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -1253,7 +1253,10 @@ + <&pcs_uniphy1 1>, + <&pcs_uniphy2 0>, + <&pcs_uniphy2 1>, +- <&gcc GCC_NSSCC_CLK>; ++ <&gcc GCC_NSSCC_CLK>, ++ <&gcc GCC_NSSNOC_NSSCC_CLK>, ++ <&gcc GCC_NSSNOC_SNOC_CLK>, ++ <&gcc GCC_NSSNOC_SNOC_1_CLK>; + clock-names = "xo", + "nss_1200", + "ppe_353", +@@ -1264,7 +1267,10 @@ + "uniphy1_tx", + "uniphy2_rx", + "uniphy2_tx", +- "bus"; ++ "bus", ++ "nssnoc", ++ "snoc", ++ "snoc_1"; + #clock-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; diff --git a/target/linux/qualcommbe/patches-6.12/0360-clk-qcom-nsscc-ipq9574-fix-port5-clock-config.patch b/target/linux/qualcommbe/patches-6.12/0360-clk-qcom-nsscc-ipq9574-fix-port5-clock-config.patch new file mode 100644 index 0000000000..725079c810 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0360-clk-qcom-nsscc-ipq9574-fix-port5-clock-config.patch @@ -0,0 +1,46 @@ +From fa691ff57c72a8f0bfeff1a9e86ae2d78765b0da Mon Sep 17 00:00:00 2001 +From: Mantas Pucka +Date: Mon, 31 Mar 2025 15:39:59 +0300 +Subject: [PATCH] clk: qcom: nsscc-ipq9574: fix port5 clock config + +Currently there is no configuration to derive 25/125MHz port5 clock +from uniphy1 running at 125MHz. This is needed for SGMII mode when +port5 is using uniphy1. + +Fix this by adding option such clock config option. + +Signed-off-by: Mantas Pucka +--- + drivers/clk/qcom/nsscc-ipq9574.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/clk/qcom/nsscc-ipq9574.c ++++ b/drivers/clk/qcom/nsscc-ipq9574.c +@@ -383,11 +383,13 @@ static const struct freq_multi_tbl ftbl_ + + static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = { + C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0), + }; + + static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = { + C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), + }; + +@@ -408,11 +410,13 @@ static const struct freq_multi_tbl ftbl_ + + static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = { + C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0), + }; + + static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = { + C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), + }; + diff --git a/target/linux/qualcommbe/patches-6.12/0361-net-pcs-Add-10GBASER-interface-mode-support-to-IPQ-U.patch b/target/linux/qualcommbe/patches-6.12/0361-net-pcs-Add-10GBASER-interface-mode-support-to-IPQ-U.patch new file mode 100644 index 0000000000..529f9f7005 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0361-net-pcs-Add-10GBASER-interface-mode-support-to-IPQ-U.patch @@ -0,0 +1,127 @@ +From e770b36f0353fd11c4628360fe412acb7f02f346 Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Wed, 6 Mar 2024 17:40:52 +0800 +Subject: [PATCH] net: pcs: Add 10GBASER interface mode support to IPQ UNIPHY + PCS driver + +10GBASER mode is used when PCS connects with a 10G SFP module. + +Change-Id: Ifc3c3bb23811807a9b34e88771aab2c830c2327c +Signed-off-by: Lei Wei +Alex G: Use regmap to read/write registers +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/pcs/pcs-qcom-ipq9574.c | 53 ++++++++++++++++++++++++++++++ + 1 file changed, 53 insertions(+) + +--- a/drivers/net/pcs/pcs-qcom-ipq9574.c ++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c +@@ -60,6 +60,9 @@ + FIELD_PREP(GENMASK(9, 2), \ + FIELD_GET(XPCS_INDIRECT_ADDR_L, reg))) + ++#define XPCS_10GBASER_STS 0x30020 ++#define XPCS_10GBASER_LINK_STS BIT(12) ++ + #define XPCS_DIG_CTRL 0x38000 + #define XPCS_USXG_ADPT_RESET BIT(10) + #define XPCS_USXG_EN BIT(9) +@@ -229,6 +232,28 @@ static void ipq_pcs_get_state_usxgmii(st + state->duplex = DUPLEX_FULL; + } + ++static void ipq_unipcs_get_state_10gbaser(struct ipq_pcs *qpcs, ++ struct phylink_link_state *state) ++{ ++ unsigned int val; ++ int ret; ++ ++ ret = regmap_read(qpcs->regmap, XPCS_10GBASER_STS, &val); ++ if (ret) { ++ state->link = 0; ++ return; ++ } ++ ++ state->link = !!(val & XPCS_10GBASER_LINK_STS); ++ ++ if (!state->link) ++ return; ++ ++ state->speed = SPEED_10000; ++ state->duplex = DUPLEX_FULL; ++ state->pause |= MLO_PAUSE_TXRX_MASK; ++} ++ + static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, + phy_interface_t interface) + { +@@ -251,6 +276,7 @@ static int ipq_pcs_config_mode(struct ip + val = PCS_MODE_PSGMII; + break; + case PHY_INTERFACE_MODE_USXGMII: ++ case PHY_INTERFACE_MODE_10GBASER: + val = PCS_MODE_XPCS; + rate = 312500000; + break; +@@ -355,6 +381,25 @@ static int ipq_pcs_config_usxgmii(struct + return regmap_set_bits(qpcs->regmap, XPCS_MII_CTRL, XPCS_MII_AN_EN); + } + ++static int ipq_unipcs_config_10gbaser(struct ipq_pcs *qpcs, ++ phy_interface_t interface) ++{ ++ int ret; ++ ++ if (qpcs->interface != interface) { ++ ret = ipq_pcs_config_mode(qpcs, interface); ++ if (ret) ++ return ret; ++ ++ /* Deassert XPCS */ ++ reset_control_deassert(qpcs->reset[XPCS_RESET]); ++ ++ qpcs->interface = interface; ++ } ++ ++ return 0; ++} ++ + static unsigned long ipq_unipcs_clock_rate_get_gmii(int speed) + { + unsigned long rate = 0; +@@ -421,6 +466,7 @@ ipq_unipcs_link_up_clock_rate_set(struct + rate = ipq_unipcs_clock_rate_get_gmii(speed); + break; + case PHY_INTERFACE_MODE_USXGMII: ++ case PHY_INTERFACE_MODE_10GBASER: + rate = ipq_unipcs_clock_rate_get_xgmii(speed); + break; + default: +@@ -602,6 +648,9 @@ static void ipq_pcs_get_state(struct phy + case PHY_INTERFACE_MODE_USXGMII: + ipq_pcs_get_state_usxgmii(qpcs, state); + break; ++ case PHY_INTERFACE_MODE_10GBASER: ++ ipq_unipcs_get_state_10gbaser(qpcs, state); ++ break; + default: + break; + } +@@ -631,6 +680,8 @@ static int ipq_pcs_config(struct phylink + return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface); + case PHY_INTERFACE_MODE_USXGMII: + return ipq_pcs_config_usxgmii(qpcs); ++ case PHY_INTERFACE_MODE_10GBASER: ++ return ipq_unipcs_config_10gbaser(qpcs, interface); + default: + dev_err(qpcs->dev, + "interface %s not supported\n", phy_modes(interface)); +@@ -662,6 +713,8 @@ static void ipq_pcs_link_up(struct phyli + case PHY_INTERFACE_MODE_USXGMII: + ret = ipq_pcs_link_up_config_usxgmii(qpcs, speed); + break; ++ case PHY_INTERFACE_MODE_10GBASER: ++ break; + default: + dev_err(qpcs->dev, + "interface %s not supported\n", phy_modes(interface)); diff --git a/target/linux/qualcommbe/patches-6.12/0362-net-pcs-Add-2500BASEX-interface-mode-support-to-IPQ-.patch b/target/linux/qualcommbe/patches-6.12/0362-net-pcs-Add-2500BASEX-interface-mode-support-to-IPQ-.patch new file mode 100644 index 0000000000..3bf5f1f798 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0362-net-pcs-Add-2500BASEX-interface-mode-support-to-IPQ-.patch @@ -0,0 +1,192 @@ +From a2e687df29e457621616d5d769688e6c972f9ac6 Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Tue, 2 Apr 2024 18:28:42 +0800 +Subject: [PATCH] net: pcs: Add 2500BASEX interface mode support to IPQ UNIPHY + PCS driver + +2500BASEX mode is used when PCS connects with QCA8386 switch in a fixed +2500M link. It is also used when PCS connectes with QCA8081 PHY which +works at 2500M link speed. In addition, it can be also used when PCS +connects with a 2.5G SFP module. + +Change-Id: I3fe61113c1b3685debc20659736a9488216a029d +Signed-off-by: Lei Wei +Alex G: use regmap to read/write registers +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/pcs/pcs-qcom-ipq9574.c | 94 ++++++++++++++++++++++++++++++ + 1 file changed, 94 insertions(+) + +--- a/drivers/net/pcs/pcs-qcom-ipq9574.c ++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c +@@ -29,6 +29,7 @@ + #define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4) + #define PCS_MODE_QSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x1) + #define PCS_MODE_PSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x2) ++#define PCS_MODE_SGMII_PLUS FIELD_PREP(PCS_MODE_SEL_MASK, 0x8) + #define PCS_MODE_XPCS FIELD_PREP(PCS_MODE_SEL_MASK, 0x10) + + #define PCS_MII_CTRL(x) (0x480 + 0x18 * (x)) +@@ -188,6 +189,30 @@ static void ipq_pcs_get_state_sgmii(stru + state->pause |= MLO_PAUSE_RX; + } + ++static void ipq_unipcs_get_state_2500basex(struct ipq_pcs *qpcs, ++ int index, ++ struct phylink_link_state *state) ++{ ++ unsigned int val; ++ int ret; ++ ++ ret = regmap_read(qpcs->regmap, PCS_MII_STS(index), &val); ++ if (ret) { ++ state->link = 0; ++ return; ++ } ++ ++ ++ state->link = !!(val & PCS_MII_LINK_STS); ++ ++ if (!state->link) ++ return; ++ ++ state->speed = SPEED_2500; ++ state->duplex = DUPLEX_FULL; ++ state->pause |= MLO_PAUSE_TXRX_MASK; ++} ++ + static void ipq_pcs_get_state_usxgmii(struct ipq_pcs *qpcs, + struct phylink_link_state *state) + { +@@ -272,6 +297,10 @@ static int ipq_pcs_config_mode(struct ip + case PHY_INTERFACE_MODE_QSGMII: + val = PCS_MODE_QSGMII; + break; ++ case PHY_INTERFACE_MODE_2500BASEX: ++ val = PCS_MODE_SGMII_PLUS; ++ rate = 312500000; ++ break; + case PHY_INTERFACE_MODE_PSGMII: + val = PCS_MODE_PSGMII; + break; +@@ -355,6 +384,22 @@ static int ipq_pcs_config_sgmii(struct i + PCS_MII_CTRL(index), PCS_MII_FORCE_MODE); + } + ++static int ipq_unipcs_config_2500basex(struct ipq_pcs *qpcs, ++ phy_interface_t interface) ++{ ++ int ret; ++ ++ if (qpcs->interface != interface) { ++ ret = ipq_pcs_config_mode(qpcs, interface); ++ if (ret) ++ return ret; ++ ++ qpcs->interface = interface; ++ } ++ ++ return 0; ++} ++ + static int ipq_pcs_config_usxgmii(struct ipq_pcs *qpcs) + { + int ret; +@@ -421,6 +466,21 @@ static unsigned long ipq_unipcs_clock_ra + return rate; + } + ++static unsigned long ipq_unipcs_clock_rate_get_gmiiplus(int speed) ++{ ++ unsigned long rate = 0; ++ ++ switch (speed) { ++ case SPEED_2500: ++ rate = 312500000; ++ break; ++ default: ++ break; ++ } ++ ++ return rate; ++} ++ + static unsigned long ipq_unipcs_clock_rate_get_xgmii(int speed) + { + unsigned long rate = 0; +@@ -465,6 +525,9 @@ ipq_unipcs_link_up_clock_rate_set(struct + case PHY_INTERFACE_MODE_PSGMII: + rate = ipq_unipcs_clock_rate_get_gmii(speed); + break; ++ case PHY_INTERFACE_MODE_2500BASEX: ++ rate = ipq_unipcs_clock_rate_get_gmiiplus(speed); ++ break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + rate = ipq_unipcs_clock_rate_get_xgmii(speed); +@@ -528,6 +591,25 @@ static int ipq_pcs_link_up_config_sgmii( + PCS_MII_CTRL(index), PCS_MII_ADPT_RESET); + } + ++static int ipq_unipcs_link_up_config_2500basex(struct ipq_pcs *qpcs, ++ int index, ++ int speed) ++{ ++ unsigned int val; ++ int ret; ++ ++ /* 2500BASEX do not support autoneg and do not need to ++ * configure PCS speed, only reset PCS adapter here. ++ */ ++ ret = regmap_clear_bits(qpcs->regmap, ++ PCS_MII_CTRL(index), PCS_MII_ADPT_RESET); ++ if (ret) ++ return ret; ++ ++ return regmap_set_bits(qpcs->regmap, ++ PCS_MII_CTRL(index), PCS_MII_ADPT_RESET); ++} ++ + static int ipq_pcs_link_up_config_usxgmii(struct ipq_pcs *qpcs, int speed) + { + unsigned int val; +@@ -575,6 +657,10 @@ static int ipq_pcs_validate(struct phyli + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + return 0; ++ case PHY_INTERFACE_MODE_2500BASEX: ++ /* In-band autoneg is not supported for 2500BASEX */ ++ phylink_clear(supported, Autoneg); ++ return 0; + case PHY_INTERFACE_MODE_USXGMII: + /* USXGMII only supports full duplex mode */ + phylink_clear(supported, 100baseT_Half); +@@ -645,6 +731,9 @@ static void ipq_pcs_get_state(struct phy + case PHY_INTERFACE_MODE_PSGMII: + ipq_pcs_get_state_sgmii(qpcs, index, state); + break; ++ case PHY_INTERFACE_MODE_2500BASEX: ++ ipq_unipcs_get_state_2500basex(qpcs, index, state); ++ break; + case PHY_INTERFACE_MODE_USXGMII: + ipq_pcs_get_state_usxgmii(qpcs, state); + break; +@@ -678,6 +767,8 @@ static int ipq_pcs_config(struct phylink + case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_PSGMII: + return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface); ++ case PHY_INTERFACE_MODE_2500BASEX: ++ return ipq_unipcs_config_2500basex(qpcs, interface); + case PHY_INTERFACE_MODE_USXGMII: + return ipq_pcs_config_usxgmii(qpcs); + case PHY_INTERFACE_MODE_10GBASER: +@@ -710,6 +801,9 @@ static void ipq_pcs_link_up(struct phyli + ret = ipq_pcs_link_up_config_sgmii(qpcs, index, + neg_mode, speed); + break; ++ case PHY_INTERFACE_MODE_2500BASEX: ++ ret = ipq_unipcs_link_up_config_2500basex(qpcs, index, speed); ++ break; + case PHY_INTERFACE_MODE_USXGMII: + ret = ipq_pcs_link_up_config_usxgmii(qpcs, speed); + break; diff --git a/target/linux/qualcommbe/patches-6.12/0363-net-pcs-Add-1000BASEX-interface-mode-support-to-IPQ-.patch b/target/linux/qualcommbe/patches-6.12/0363-net-pcs-Add-1000BASEX-interface-mode-support-to-IPQ-.patch new file mode 100644 index 0000000000..9153cabe24 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0363-net-pcs-Add-1000BASEX-interface-mode-support-to-IPQ-.patch @@ -0,0 +1,91 @@ +From 07f9bb8eb006e9664d651089a1f422d045e093e3 Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Tue, 9 Apr 2024 01:07:22 +0800 +Subject: [PATCH] net: pcs: Add 1000BASEX interface mode support to IPQ UNIPHY + PCS driver + +1000BASEX is used when PCS connects with a 1G SFP module. + +Change-Id: Ied7298de3c1ecba74e6457a07fdd6b3ceab79728 +Signed-off-by: Lei Wei +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/pcs/pcs-qcom-ipq9574.c | 18 ++++++++++++++++-- + 1 file changed, 16 insertions(+), 2 deletions(-) + +--- a/drivers/net/pcs/pcs-qcom-ipq9574.c ++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c +@@ -31,6 +31,9 @@ + #define PCS_MODE_PSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x2) + #define PCS_MODE_SGMII_PLUS FIELD_PREP(PCS_MODE_SEL_MASK, 0x8) + #define PCS_MODE_XPCS FIELD_PREP(PCS_MODE_SEL_MASK, 0x10) ++#define PCS_MODE_SGMII_CTRL_MASK GENMASK(6, 4) ++#define PCS_MODE_SGMII_CTRL_1000BASEX FIELD_PREP(PCS_MODE_SGMII_CTRL_MASK, \ ++ 0x0) + + #define PCS_MII_CTRL(x) (0x480 + 0x18 * (x)) + #define PCS_MII_ADPT_RESET BIT(11) +@@ -283,7 +286,7 @@ static int ipq_pcs_config_mode(struct ip + phy_interface_t interface) + { + unsigned long rate = 125000000; +- unsigned int val; ++ unsigned int val, mask = PCS_MODE_SEL_MASK; + int ret; + + /* Assert XPCS reset */ +@@ -297,6 +300,10 @@ static int ipq_pcs_config_mode(struct ip + case PHY_INTERFACE_MODE_QSGMII: + val = PCS_MODE_QSGMII; + break; ++ case PHY_INTERFACE_MODE_1000BASEX: ++ mask |= PCS_MODE_SGMII_CTRL_MASK; ++ val = PCS_MODE_SGMII | PCS_MODE_SGMII_CTRL_1000BASEX; ++ break; + case PHY_INTERFACE_MODE_2500BASEX: + val = PCS_MODE_SGMII_PLUS; + rate = 312500000; +@@ -316,7 +323,7 @@ static int ipq_pcs_config_mode(struct ip + } + + ret = regmap_update_bits(qpcs->regmap, PCS_MODE_CTRL, +- PCS_MODE_SEL_MASK, val); ++ mask, val); + if (ret) + return ret; + +@@ -523,6 +530,7 @@ ipq_unipcs_link_up_clock_rate_set(struct + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_PSGMII: ++ case PHY_INTERFACE_MODE_1000BASEX: + rate = ipq_unipcs_clock_rate_get_gmii(speed); + break; + case PHY_INTERFACE_MODE_2500BASEX: +@@ -729,6 +737,10 @@ static void ipq_pcs_get_state(struct phy + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_PSGMII: ++ case PHY_INTERFACE_MODE_1000BASEX: ++ /* SGMII and 1000BASEX in-band autoneg word format are decoded ++ * by PCS hardware and both placed to the same status register. ++ */ + ipq_pcs_get_state_sgmii(qpcs, index, state); + break; + case PHY_INTERFACE_MODE_2500BASEX: +@@ -766,6 +778,7 @@ static int ipq_pcs_config(struct phylink + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_PSGMII: ++ case PHY_INTERFACE_MODE_1000BASEX: + return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface); + case PHY_INTERFACE_MODE_2500BASEX: + return ipq_unipcs_config_2500basex(qpcs, interface); +@@ -798,6 +811,7 @@ static void ipq_pcs_link_up(struct phyli + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_PSGMII: ++ case PHY_INTERFACE_MODE_1000BASEX: + ret = ipq_pcs_link_up_config_sgmii(qpcs, index, + neg_mode, speed); + break; diff --git a/target/linux/qualcommbe/patches-6.12/0364-net-pcs-Add-10G_QXGMII-interface-mode-support-to-IPQ.patch b/target/linux/qualcommbe/patches-6.12/0364-net-pcs-Add-10G_QXGMII-interface-mode-support-to-IPQ.patch new file mode 100644 index 0000000000..6e75cdfb0b --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0364-net-pcs-Add-10G_QXGMII-interface-mode-support-to-IPQ.patch @@ -0,0 +1,267 @@ +From 77462c0d74e51a24408062b93c3fcc0256909d33 Mon Sep 17 00:00:00 2001 +From: Lei Wei +Date: Mon, 15 Apr 2024 11:06:02 +0800 +Subject: [PATCH] net: pcs: Add 10G_QXGMII interface mode support to IPQ UNIPHY + PCS driver + +10G_QXGMII is used when PCS connectes with QCA8084 four ports +2.5G PHYs. + +Change-Id: If3dc92a07ac3e51f7c9473fb05fa0668617916fb +Signed-off-by: Lei Wei +Signed-off-by: Alexandru Gagniuc +--- + drivers/net/pcs/pcs-qcom-ipq9574.c | 112 +++++++++++++++++++++++------ + 1 file changed, 91 insertions(+), 21 deletions(-) + +--- a/drivers/net/pcs/pcs-qcom-ipq9574.c ++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c +@@ -53,6 +53,9 @@ + #define PCS_MII_STS_PAUSE_TX_EN BIT(1) + #define PCS_MII_STS_PAUSE_RX_EN BIT(0) + ++#define PCS_QP_USXG_OPTION 0x584 ++#define PCS_QP_USXG_GMII_SRC_XPCS BIT(0) ++ + #define PCS_PLL_RESET 0x780 + #define PCS_ANA_SW_RESET BIT(6) + +@@ -68,10 +71,22 @@ + #define XPCS_10GBASER_LINK_STS BIT(12) + + #define XPCS_DIG_CTRL 0x38000 ++#define XPCS_SOFT_RESET BIT(15) + #define XPCS_USXG_ADPT_RESET BIT(10) + #define XPCS_USXG_EN BIT(9) + ++#define XPCS_KR_CTRL 0x38007 ++#define XPCS_USXG_MODE_MASK GENMASK(12, 10) ++#define XPCS_10G_QXGMII_MODE FIELD_PREP(XPCS_USXG_MODE_MASK, 0x5) ++ ++#define XPCS_DIG_STS 0x3800a ++#define XPCS_DIG_STS_AM_COUNT GENMASK(14, 0) ++ ++#define XPCS_CHANNEL_DIG_CTRL(x) (0x1a8000 + 0x10000 * ((x) - 1)) ++#define XPCS_CHANNEL_USXG_ADPT_RESET BIT(5) ++ + #define XPCS_MII_CTRL 0x1f0000 ++#define XPCS_CHANNEL_MII_CTRL(x) (0x1a0000 + 0x10000 * ((x) - 1)) + #define XPCS_MII_AN_EN BIT(12) + #define XPCS_DUPLEX_FULL BIT(8) + #define XPCS_SPEED_MASK (BIT(13) | BIT(6) | BIT(5)) +@@ -83,9 +98,11 @@ + #define XPCS_SPEED_10 0 + + #define XPCS_MII_AN_CTRL 0x1f8001 ++#define XPCS_CHANNEL_MII_AN_CTRL(x) (0x1a8001 + 0x10000 * ((x) - 1)) + #define XPCS_MII_AN_8BIT BIT(8) + + #define XPCS_MII_AN_INTR_STS 0x1f8002 ++#define XPCS_CHANNEL_MII_AN_INTR_STS(x) (0x1a8002 + 0x10000 * ((x) - 1)) + #define XPCS_USXG_AN_LINK_STS BIT(14) + #define XPCS_USXG_AN_SPEED_MASK GENMASK(12, 10) + #define XPCS_USXG_AN_SPEED_10 0 +@@ -95,6 +112,10 @@ + #define XPCS_USXG_AN_SPEED_5000 5 + #define XPCS_USXG_AN_SPEED_10000 3 + ++#define XPCS_XAUI_MODE_CTRL 0x1f8004 ++#define XPCS_CHANNEL_XAUI_MODE_CTRL(x) (0x1a8004 + 0x10000 * ((x) - 1)) ++#define XPCS_TX_IPG_CHECK_DIS BIT(0) ++ + /* Per PCS MII private data */ + struct ipq_pcs_mii { + struct ipq_pcs *qpcs; +@@ -217,12 +238,16 @@ static void ipq_unipcs_get_state_2500bas + } + + static void ipq_pcs_get_state_usxgmii(struct ipq_pcs *qpcs, ++ int index, + struct phylink_link_state *state) + { + unsigned int val; +- int ret; ++ int ret, reg; ++ ++ reg = (index == 0) ? XPCS_MII_AN_INTR_STS : ++ XPCS_CHANNEL_MII_AN_INTR_STS(index); + +- ret = regmap_read(qpcs->regmap, XPCS_MII_AN_INTR_STS, &val); ++ ret = regmap_read(qpcs->regmap, reg, &val); + if (ret) { + state->link = 0; + return; +@@ -316,6 +341,14 @@ static int ipq_pcs_config_mode(struct ip + val = PCS_MODE_XPCS; + rate = 312500000; + break; ++ case PHY_INTERFACE_MODE_10G_QXGMII: ++ val = PCS_MODE_XPCS; ++ rate = 312500000; ++ ret = regmap_set_bits(qpcs->regmap, PCS_QP_USXG_OPTION, ++ PCS_QP_USXG_GMII_SRC_XPCS); ++ if (ret) ++ return ret; ++ break; + default: + dev_err(qpcs->dev, + "interface %s not supported\n", phy_modes(interface)); +@@ -407,30 +440,55 @@ static int ipq_unipcs_config_2500basex(s + return 0; + } + +-static int ipq_pcs_config_usxgmii(struct ipq_pcs *qpcs) ++static int ipq_pcs_config_usxgmii(struct ipq_pcs *qpcs, ++ int index, ++ phy_interface_t interface) + { +- int ret; ++ int ret, reg; + + /* Configure the XPCS for USXGMII mode if required */ +- if (qpcs->interface == PHY_INTERFACE_MODE_USXGMII) +- return 0; +- +- ret = ipq_pcs_config_mode(qpcs, PHY_INTERFACE_MODE_USXGMII); +- if (ret) +- return ret; ++ if (qpcs->interface != interface) { ++ ret = ipq_pcs_config_mode(qpcs, interface); ++ if (ret) ++ return ret; ++ } + +- /* Deassert XPCS and configure XPCS USXGMII */ ++ /* Deassert XPCS and configure XPCS USXGMII or 10G_QXGMII */ + reset_control_deassert(qpcs->reset[XPCS_RESET]); + + ret = regmap_set_bits(qpcs->regmap, XPCS_DIG_CTRL, XPCS_USXG_EN); + if (ret) + return ret; + +- ret = regmap_set_bits(qpcs->regmap, XPCS_MII_AN_CTRL, XPCS_MII_AN_8BIT); ++ if (interface == PHY_INTERFACE_MODE_10G_QXGMII) { ++ regmap_update_bits(qpcs->regmap, XPCS_KR_CTRL, ++ XPCS_USXG_MODE_MASK, XPCS_10G_QXGMII_MODE); ++ ++ /* Set Alignment Marker Interval */ ++ regmap_update_bits(qpcs->regmap, XPCS_DIG_STS, ++ XPCS_DIG_STS_AM_COUNT, 0x6018); ++ ++ regmap_set_bits(qpcs->regmap, XPCS_DIG_CTRL, XPCS_SOFT_RESET); ++ } ++ ++ qpcs->interface = interface; ++ ++ /* Disable Tx IPG check for 10G_QXGMII */ ++ if (interface == PHY_INTERFACE_MODE_10G_QXGMII) { ++ reg = (index == 0) ? XPCS_XAUI_MODE_CTRL : ++ XPCS_CHANNEL_XAUI_MODE_CTRL(index); ++ ++ regmap_set_bits(qpcs->regmap, reg, XPCS_TX_IPG_CHECK_DIS); ++ } ++ ++ /* Enable autoneg */ ++ reg = (index == 0) ? XPCS_MII_AN_CTRL : XPCS_CHANNEL_MII_AN_CTRL(index); ++ ret = regmap_set_bits(qpcs->regmap, reg, XPCS_MII_AN_8BIT); + if (ret) + return ret; + +- return regmap_set_bits(qpcs->regmap, XPCS_MII_CTRL, XPCS_MII_AN_EN); ++ reg = (index == 0) ? XPCS_MII_CTRL : XPCS_CHANNEL_MII_CTRL(index); ++ return regmap_set_bits(qpcs->regmap, reg, XPCS_MII_AN_EN); + } + + static int ipq_unipcs_config_10gbaser(struct ipq_pcs *qpcs, +@@ -538,6 +596,7 @@ ipq_unipcs_link_up_clock_rate_set(struct + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: ++ case PHY_INTERFACE_MODE_10G_QXGMII: + rate = ipq_unipcs_clock_rate_get_xgmii(speed); + break; + default: +@@ -603,7 +662,6 @@ static int ipq_unipcs_link_up_config_250 + int index, + int speed) + { +- unsigned int val; + int ret; + + /* 2500BASEX do not support autoneg and do not need to +@@ -618,10 +676,12 @@ static int ipq_unipcs_link_up_config_250 + PCS_MII_CTRL(index), PCS_MII_ADPT_RESET); + } + +-static int ipq_pcs_link_up_config_usxgmii(struct ipq_pcs *qpcs, int speed) ++static int ipq_pcs_link_up_config_usxgmii(struct ipq_pcs *qpcs, ++ int channel, ++ int speed) + { + unsigned int val; +- int ret; ++ int ret, reg; + + switch (speed) { + case SPEED_10000: +@@ -648,14 +708,19 @@ static int ipq_pcs_link_up_config_usxgmi + } + + /* Configure XPCS speed */ +- ret = regmap_update_bits(qpcs->regmap, XPCS_MII_CTRL, ++ reg = (channel == 0) ? XPCS_MII_CTRL : XPCS_CHANNEL_MII_CTRL(channel); ++ ret = regmap_update_bits(qpcs->regmap, reg, + XPCS_SPEED_MASK, val | XPCS_DUPLEX_FULL); + if (ret) + return ret; + + /* XPCS adapter reset */ +- return regmap_set_bits(qpcs->regmap, ++ if (channel == 0) ++ return regmap_set_bits(qpcs->regmap, + XPCS_DIG_CTRL, XPCS_USXG_ADPT_RESET); ++ else ++ return regmap_set_bits(qpcs->regmap, XPCS_CHANNEL_DIG_CTRL(channel), ++ XPCS_CHANNEL_USXG_ADPT_RESET); + } + + static int ipq_pcs_validate(struct phylink_pcs *pcs, unsigned long *supported, +@@ -669,6 +734,7 @@ static int ipq_pcs_validate(struct phyli + /* In-band autoneg is not supported for 2500BASEX */ + phylink_clear(supported, Autoneg); + return 0; ++ case PHY_INTERFACE_MODE_10G_QXGMII: + case PHY_INTERFACE_MODE_USXGMII: + /* USXGMII only supports full duplex mode */ + phylink_clear(supported, 100baseT_Half); +@@ -747,7 +813,8 @@ static void ipq_pcs_get_state(struct phy + ipq_unipcs_get_state_2500basex(qpcs, index, state); + break; + case PHY_INTERFACE_MODE_USXGMII: +- ipq_pcs_get_state_usxgmii(qpcs, state); ++ case PHY_INTERFACE_MODE_10G_QXGMII: ++ ipq_pcs_get_state_usxgmii(qpcs, index, state); + break; + case PHY_INTERFACE_MODE_10GBASER: + ipq_unipcs_get_state_10gbaser(qpcs, state); +@@ -783,7 +850,9 @@ static int ipq_pcs_config(struct phylink + case PHY_INTERFACE_MODE_2500BASEX: + return ipq_unipcs_config_2500basex(qpcs, interface); + case PHY_INTERFACE_MODE_USXGMII: +- return ipq_pcs_config_usxgmii(qpcs); ++ case PHY_INTERFACE_MODE_10G_QXGMII: ++ return ipq_pcs_config_usxgmii(qpcs, index, ++ interface); + case PHY_INTERFACE_MODE_10GBASER: + return ipq_unipcs_config_10gbaser(qpcs, interface); + default: +@@ -819,7 +888,8 @@ static void ipq_pcs_link_up(struct phyli + ret = ipq_unipcs_link_up_config_2500basex(qpcs, index, speed); + break; + case PHY_INTERFACE_MODE_USXGMII: +- ret = ipq_pcs_link_up_config_usxgmii(qpcs, speed); ++ case PHY_INTERFACE_MODE_10G_QXGMII: ++ ret = ipq_pcs_link_up_config_usxgmii(qpcs, index, speed); + break; + case PHY_INTERFACE_MODE_10GBASER: + break; diff --git a/target/linux/ramips/image/common-sercomm.mk b/target/linux/ramips/image/common-sercomm.mk index 0987010911..0c1a18eb90 100644 --- a/target/linux/ramips/image/common-sercomm.mk +++ b/target/linux/ramips/image/common-sercomm.mk @@ -184,6 +184,7 @@ define Device/sercomm_cpj append-metadata ARTIFACTS := initramfs-factory.img DEVICE_PACKAGES := kmod-mt76x2 + DEFAULT := n endef define Device/sercomm_cxx_dxx diff --git a/target/linux/ramips/image/mt7620.mk b/target/linux/ramips/image/mt7620.mk index 5e8cf0ce25..f6a7793c4b 100644 --- a/target/linux/ramips/image/mt7620.mk +++ b/target/linux/ramips/image/mt7620.mk @@ -815,6 +815,7 @@ define Device/linksys_e1700 DEVICE_VENDOR := Linksys DEVICE_MODEL := E1700 SUPPORTED_DEVICES += e1700 + DEFAULT := n endef TARGET_DEVICES += linksys_e1700 @@ -951,6 +952,7 @@ define Device/netgear_wn3100rp-v2 DEVICE_VENDOR := NETGEAR DEVICE_MODEL := WN3100RP DEVICE_VARIANT := v2 + DEFAULT := n endef TARGET_DEVICES += netgear_wn3100rp-v2 @@ -1630,6 +1632,7 @@ define Device/zyxel_keenetic-lite-iii-a IMAGES += factory.bin IMAGE/factory.bin := $$(sysupgrade_bin) | pad-to 64k | check-size | \ zyimage -d 2102018 -v "ZyXEL Keenetic Lite III" + DEFAULT := n endef TARGET_DEVICES += zyxel_keenetic-lite-iii-a diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk index fc992b5350..03d56ba96f 100755 --- a/target/linux/ramips/image/mt7621.mk +++ b/target/linux/ramips/image/mt7621.mk @@ -1390,7 +1390,7 @@ define Device/gemtek_wvrtm-1xxacn IMAGE_SIZE := 122368k DEVICE_VENDOR := Gemtek DEVICE_PACKAGES := kmod-gpio-nxp-74hc164 kmod-spi-gpio \ - kmod-usb3 -uboot-envtools + kmod-usb3 -uboot-envtools endef define Device/gemtek_wvrtm-127acn @@ -2590,7 +2590,7 @@ define Device/sercomm_na502s DEVICE_VENDOR := SERCOMM DEVICE_MODEL := NA502S DEVICE_PACKAGES := kmod-mt76x2 kmod-mt7603 kmod-usb3 kmod-usb-serial \ - kmod-usb-serial-xr_usb_serial_common -uboot-envtools + kmod-usb-serial-xr -uboot-envtools endef TARGET_DEVICES += sercomm_na502s diff --git a/target/linux/ramips/image/mt76x8.mk b/target/linux/ramips/image/mt76x8.mk index 1e987e64ae..4d49a89d92 100644 --- a/target/linux/ramips/image/mt76x8.mk +++ b/target/linux/ramips/image/mt76x8.mk @@ -1256,7 +1256,7 @@ TARGET_DEVICES += xiaomi_miwifi-nano define Device/xiaomi_mi-ra75 IMAGE_SIZE := 14976k DEVICE_VENDOR := Xiaomi - DEVICE_MODEL := MiWiFi Range Extender AC1200 + DEVICE_MODEL := MiWiFi Range Extender AC1200 DEVICE_VARIANT := RA75 DEVICE_PACKAGES := kmod-mt76x2 SUPPORTED_DEVICES += xiaomi,mira75 diff --git a/target/linux/realtek/base-files/etc/board.d/02_network b/target/linux/realtek/base-files/etc/board.d/02_network index 16642c273a..839dcd85f2 100644 --- a/target/linux/realtek/base-files/etc/board.d/02_network +++ b/target/linux/realtek/base-files/etc/board.d/02_network @@ -91,7 +91,8 @@ d-link,dgs-1210-28p-f) ucidef_set_poe 193 "lan8 lan7 lan6 lan5 lan4 lan3 lan2 lan1 lan16 lan15 lan14 lan13 lan12 lan11 lan10 lan9 lan24 lan23 lan22 lan21 lan20 lan19 lan18 lan17" ;; -engenius,ews2910p) +engenius,ews2910p-v1|\ +engenius,ews2910p-v3) ucidef_set_poe 60 "$(filter_port_list "$lan_list" "lan9 lan10")" ;; hpe,1920-8g-poe-65w) diff --git a/target/linux/realtek/dts/rtl8380_engenius_ews2910p-v1.dts b/target/linux/realtek/dts/rtl8380_engenius_ews2910p-v1.dts new file mode 100644 index 0000000000..72f9ea7a90 --- /dev/null +++ b/target/linux/realtek/dts/rtl8380_engenius_ews2910p-v1.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "rtl8380_engenius_ews2910p.dtsi" + +/ { + compatible = "engenius,ews2910p-v1", "realtek,rtl838x-soc"; + model = "EnGenius EWS2910P v1"; +}; + +&firmware_partition_1 { + compatible = "openwrt,uimage"; + openwrt,ih-magic = <0x03802910>; +}; diff --git a/target/linux/realtek/dts/rtl8380_engenius_ews2910p-v3.dts b/target/linux/realtek/dts/rtl8380_engenius_ews2910p-v3.dts new file mode 100644 index 0000000000..eeab91e731 --- /dev/null +++ b/target/linux/realtek/dts/rtl8380_engenius_ews2910p-v3.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "rtl8380_engenius_ews2910p.dtsi" + +/ { + compatible = "engenius,ews2910p-v3", "realtek,rtl838x-soc"; + model = "EnGenius EWS2910P v3"; +}; + +&firmware_partition_1 { + compatible = "openwrt,uimage"; + openwrt,ih-magic = <0x03010500>; +}; diff --git a/target/linux/realtek/dts/rtl8380_engenius_ews2910p.dts b/target/linux/realtek/dts/rtl8380_engenius_ews2910p.dtsi similarity index 95% rename from target/linux/realtek/dts/rtl8380_engenius_ews2910p.dts rename to target/linux/realtek/dts/rtl8380_engenius_ews2910p.dtsi index b0f1e9b538..e8cc9d7b60 100644 --- a/target/linux/realtek/dts/rtl8380_engenius_ews2910p.dts +++ b/target/linux/realtek/dts/rtl8380_engenius_ews2910p.dtsi @@ -7,9 +7,6 @@ #include / { - compatible = "engenius,ews2910p", "realtek,rtl838x-soc"; - model = "EnGenius EWS2910P"; - aliases { led-boot = &led_power; led-failsafe = &led_fault; @@ -165,13 +162,11 @@ label = "jffs2-log"; reg = <0xe00000 0x200000>; }; - partition@1000000 { - compatible = "openwrt,uimage"; + firmware_partition_1: partition@1000000 { label = "firmware"; reg = <0x1000000 0x800000>; - openwrt,ih-magic = <0x03802910>; }; - partition@1800000 { + firmware_partition_2: partition@1800000 { label = "firmware2"; reg = <0x1800000 0x800000>; }; diff --git a/target/linux/realtek/files-6.6/arch/mips/rtl838x/prom.c b/target/linux/realtek/files-6.6/arch/mips/rtl838x/prom.c index 0452987247..f98fb5e93f 100644 --- a/target/linux/realtek/files-6.6/arch/mips/rtl838x/prom.c +++ b/target/linux/realtek/files-6.6/arch/mips/rtl838x/prom.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -95,7 +96,7 @@ void __init device_tree_init(void) register_up_smp_ops(); } -void __init identify_rtl9302(void) +static void __init identify_rtl9302(void) { switch (sw_r32(RTL93XX_MODEL_NAME_INFO) & 0xfffffff0) { case 0x93020810: diff --git a/target/linux/realtek/files-6.6/arch/mips/rtl838x/setup.c b/target/linux/realtek/files-6.6/arch/mips/rtl838x/setup.c index 546b2fa2f8..73d689058e 100644 --- a/target/linux/realtek/files-6.6/arch/mips/rtl838x/setup.c +++ b/target/linux/realtek/files-6.6/arch/mips/rtl838x/setup.c @@ -46,7 +46,7 @@ void __init plat_mem_setup(void) __dt_setup_arch(dtb); } -void plat_time_init_fallback(void) +static void plat_time_init_fallback(void) { struct device_node *np; u32 freq = 500000000; diff --git a/target/linux/realtek/files-6.6/drivers/clk/realtek/clk-rtl83xx.c b/target/linux/realtek/files-6.6/drivers/clk/realtek/clk-rtl83xx.c index 0cca32ab34..bdec59830d 100644 --- a/target/linux/realtek/files-6.6/drivers/clk/realtek/clk-rtl83xx.c +++ b/target/linux/realtek/files-6.6/drivers/clk/realtek/clk-rtl83xx.c @@ -504,7 +504,7 @@ static int rtcl_ccu_create(struct device_node *np) return 0; } -int rtcl_register_clkhw(int clk_idx) +static int rtcl_register_clkhw(int clk_idx) { int ret; struct clk *clk; @@ -592,7 +592,7 @@ err_hw_unregister: return ret; } -int rtcl_init_sram(void) +static int rtcl_init_sram(void) { struct gen_pool *sram_pool; phys_addr_t sram_pbase; @@ -665,7 +665,7 @@ err_put_device: return -ENXIO; } -void rtcl_ccu_log_early(void) +static void rtcl_ccu_log_early(void) { char meminfo[80], clkinfo[255], msg[255] = "rtl83xx-clk: initialized"; @@ -680,7 +680,7 @@ void rtcl_ccu_log_early(void) pr_info("%s\n", msg); } -void rtcl_ccu_log_late(void) +static void rtcl_ccu_log_late(void) { struct rtcl_clk *rclk; bool overclock = false; diff --git a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/common.c index d88a761209..ecea1601d8 100644 --- a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/common.c @@ -627,7 +627,7 @@ int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv) * Called from the L3 layer * The index in the L2 hash table is filled into nh->l2_id; */ -int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh) +static int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh) { struct rtl838x_l2_entry e; u64 seed = priv->r->l2_hash_seed(nh->mac, nh->rvid); @@ -694,7 +694,7 @@ int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_next * If it was static, the entire entry is removed, otherwise the nexthop bit is cleared * and we wait until the entry ages out */ -int rtl83xx_l2_nexthop_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh) +static int rtl83xx_l2_nexthop_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh) { struct rtl838x_l2_entry e; u32 key = nh->l2_id >> 2; @@ -819,7 +819,7 @@ static int rtl83xx_netdevice_event(struct notifier_block *this, return NOTIFY_DONE; } -const static struct rhashtable_params route_ht_params = { +static const struct rhashtable_params route_ht_params = { .key_len = sizeof(u32), .key_offset = offsetof(struct rtl83xx_route, gw_ip), .head_offset = offsetof(struct rtl83xx_route, linkage), @@ -954,7 +954,7 @@ static int rtl83xx_port_lower_walk(struct net_device *lower, struct netdev_neste return ret; } -int rtl83xx_port_dev_lower_find(struct net_device *dev, struct rtl838x_switch_priv *priv) +static int rtl83xx_port_dev_lower_find(struct net_device *dev, struct rtl838x_switch_priv *priv) { struct rtl83xx_walk_data data; struct netdev_nested_priv _priv; diff --git a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/debugfs.c index 92d6932dc5..7e6918df20 100644 --- a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/debugfs.c +++ b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/debugfs.c @@ -37,15 +37,6 @@ #define RTL930X_STAT_PRVTE_DROP_COUNTERS (0xB5B8) #define RTL931X_STAT_PRVTE_DROP_COUNTERS (0xd800) -int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port); -void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); -void rtl83xx_fast_age(struct dsa_switch *ds, int port); -u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port); -u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port); -int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate); -int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate); - - const char *rtl838x_drop_cntr[] = { "ALE_TX_GOOD_PKTS", "MAC_RX_DROP", "ACL_FWD_DROP", "HW_ATTACK_PREVENTION_DROP", "RMA_DROP", "VLAN_IGR_FLTR_DROP", "INNER_OUTER_CFI_EQUAL_1_DROP", "PORT_MOVE_DROP", @@ -449,7 +440,7 @@ static const struct debugfs_reg32 port_ctrl_regs[] = { { .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, }, }; -void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv) +static void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv) { debugfs_remove_recursive(priv->dbgfs_dir); diff --git a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/dsa.c index fd018108ce..30be051d3d 100644 --- a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/dsa.c @@ -1343,7 +1343,7 @@ void rtl83xx_fast_age(struct dsa_switch *ds, int port) mutex_unlock(&priv->reg_mutex); } -void rtl931x_fast_age(struct dsa_switch *ds, int port) +static void rtl931x_fast_age(struct dsa_switch *ds, int port) { struct rtl838x_switch_priv *priv = ds->priv; @@ -1358,7 +1358,7 @@ void rtl931x_fast_age(struct dsa_switch *ds, int port) mutex_unlock(&priv->reg_mutex); } -void rtl930x_fast_age(struct dsa_switch *ds, int port) +static void rtl930x_fast_age(struct dsa_switch *ds, int port) { struct rtl838x_switch_priv *priv = ds->priv; @@ -1862,7 +1862,7 @@ out: return err; } -int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port, +static int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port, const struct switchdev_obj_port_mdb *mdb, const struct dsa_db db) { @@ -2171,7 +2171,7 @@ out: return 0; } -int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg) +static int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg) { u32 val; u32 offset = 0; @@ -2190,7 +2190,7 @@ int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg) return val; } -int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val) +static int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val) { u32 offset = 0; struct rtl838x_switch_priv *priv = ds->priv; @@ -2217,8 +2217,8 @@ const struct dsa_switch_ops rtl83xx_switch_ops = { .get_tag_protocol = rtl83xx_get_tag_protocol, .setup = rtl83xx_setup, - .phy_read = dsa_phy_read, - .phy_write = dsa_phy_write, + .phy_read = rtl83xx_dsa_phy_read, + .phy_write = rtl83xx_dsa_phy_write, .phylink_get_caps = rtl83xx_phylink_get_caps, .phylink_mac_config = rtl83xx_phylink_mac_config, @@ -2275,8 +2275,8 @@ const struct dsa_switch_ops rtl930x_switch_ops = { .get_tag_protocol = rtl83xx_get_tag_protocol, .setup = rtl93xx_setup, - .phy_read = dsa_phy_read, - .phy_write = dsa_phy_write, + .phy_read = rtl83xx_dsa_phy_read, + .phy_write = rtl83xx_dsa_phy_write, .phylink_get_caps = rtl83xx_phylink_get_caps, .phylink_mac_config = rtl93xx_phylink_mac_config, diff --git a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/qos.c b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/qos.c index d101e1c97e..82cfbc966a 100644 --- a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/qos.c +++ b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/qos.c @@ -188,7 +188,7 @@ int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate /* Set the rate limit for a particular queue in Bits/s * units of the rate is 16Kbps */ -void rtl839x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port, +static void rtl839x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port, int queue, u32 rate) { int lsb = 128 + queue * 20; @@ -289,7 +289,7 @@ static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv) -void rtl838x_setup_prio2queue_matrix(int *min_queues) +static void rtl838x_setup_prio2queue_matrix(int *min_queues) { u32 v = 0; @@ -299,7 +299,7 @@ void rtl838x_setup_prio2queue_matrix(int *min_queues) sw_w32(v, RTL838X_QM_INTPRI2QID_CTRL); } -void rtl839x_setup_prio2queue_matrix(int *min_queues) +static void rtl839x_setup_prio2queue_matrix(int *min_queues) { pr_info("Current Intprio2queue setting: %08x\n", sw_r32(RTL839X_QM_INTPRI2QID_CTRL(0))); for (int i = 0; i < MAX_PRIOS; i++) { @@ -309,7 +309,7 @@ void rtl839x_setup_prio2queue_matrix(int *min_queues) } /* Sets the CPU queue depending on the internal priority of a packet */ -void rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues) +static void rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues) { int reg = soc_info.family == RTL8380_FAMILY_ID ? RTL838X_QM_PKT2CPU_INTPRI_MAP : RTL839X_QM_PKT2CPU_INTPRI_MAP; @@ -321,7 +321,7 @@ void rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues) sw_w32(v, reg); } -void rtl83xx_setup_default_prio2queue(void) +static void rtl83xx_setup_default_prio2queue(void) { if (soc_info.family == RTL8380_FAMILY_ID) { rtl838x_setup_prio2queue_matrix(max_available_queue); @@ -338,7 +338,7 @@ void rtl839x_set_egress_queue(int port, int queue) } /* Sets the priority assigned of an ingress port, the port can be the CPU-port */ -void rtl83xx_set_ingress_priority(int port, int priority) +static void rtl83xx_set_ingress_priority(int port, int priority) { if (soc_info.family == RTL8380_FAMILY_ID) sw_w32(priority << ((port % 10) *3), RTL838X_PRI_SEL_PORT_PRI(port)); @@ -346,7 +346,7 @@ void rtl83xx_set_ingress_priority(int port, int priority) sw_w32(priority << ((port % 10) *3), RTL839X_PRI_SEL_PORT_PRI(port)); } -int rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port) +static int rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port) { u32 v; @@ -363,7 +363,7 @@ int rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port) return WEIGHTED_FAIR_QUEUE; } -void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port, +static void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port, enum scheduler_type sched) { enum scheduler_type t = rtl839x_get_scheduling_algorithm(priv, port); @@ -421,7 +421,7 @@ void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port mutex_unlock(&priv->reg_mutex); } -void rtl839x_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv, int port, +static void rtl839x_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv, int port, int *queue_weights) { mutex_lock(&priv->reg_mutex); @@ -445,7 +445,7 @@ void rtl839x_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv, int mutex_unlock(&priv->reg_mutex); } -void rtl838x_config_qos(void) +static void rtl838x_config_qos(void) { u32 v; @@ -490,7 +490,7 @@ void rtl838x_config_qos(void) sw_w32_mask(0, 7, RTL838X_QM_PKT2CPU_INTPRI_1); } -void rtl839x_config_qos(void) +static void rtl839x_config_qos(void) { u32 v; struct rtl838x_switch_priv *priv = switch_priv; diff --git a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl838x.c index f3969a3cc2..7d44d61030 100644 --- a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl838x.c +++ b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl838x.c @@ -577,22 +577,22 @@ static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port priv->r->exec_tbl0_cmd(cmd); } -u64 rtl838x_traffic_get(int source) +static u64 rtl838x_traffic_get(int source) { return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source)); } -void rtl838x_traffic_set(int source, u64 dest_matrix) +static void rtl838x_traffic_set(int source, u64 dest_matrix) { rtl838x_set_port_reg(dest_matrix, rtl838x_port_iso_ctrl(source)); } -void rtl838x_traffic_enable(int source, int dest) +static void rtl838x_traffic_enable(int source, int dest) { rtl838x_mask_port_reg(0, BIT(dest), rtl838x_port_iso_ctrl(source)); } -void rtl838x_traffic_disable(int source, int dest) +static void rtl838x_traffic_disable(int source, int dest) { rtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source)); } @@ -1606,7 +1606,7 @@ static int rtl838x_l3_setup(struct rtl838x_switch_priv *priv) return 0; } -void rtl838x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) +static void rtl838x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) { sw_w32(FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK, keep_outer ? RTL838X_VLAN_PORT_TAG_STS_TAGGED : RTL838X_VLAN_PORT_TAG_STS_UNTAG) | @@ -1615,7 +1615,7 @@ void rtl838x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) RTL838X_VLAN_PORT_TAG_STS_CTRL(port)); } -void rtl838x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) +static void rtl838x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) { if (type == PBVLAN_TYPE_INNER) sw_w32_mask(0x3, mode, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); @@ -1623,7 +1623,7 @@ void rtl838x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan sw_w32_mask(0x3 << 14, mode << 14, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); } -void rtl838x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) +static void rtl838x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) { if (type == PBVLAN_TYPE_INNER) sw_w32_mask(0xfff << 2, pvid << 2, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); @@ -1659,7 +1659,7 @@ static void rtl838x_set_egr_filter(int port, enum egr_filter state) RTL838X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2))); } -void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) +static void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) { algoidx &= 1; /* RTL838X only supports 2 concurrent algorithms */ sw_w32_mask(1 << (group % 8), algoidx << (group % 8), @@ -1667,7 +1667,7 @@ void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) sw_w32(algomsk, RTL838X_TRK_HASH_CTRL + (algoidx << 2)); } -void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action) +static void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action) { switch(type) { case BPDU: diff --git a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl839x.c index 09422f68e2..29905964c4 100644 --- a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl839x.c @@ -529,22 +529,22 @@ static void rtl839x_vlan_profile_setup(int profile) rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x001fffffffffffff); } -u64 rtl839x_traffic_get(int source) +static u64 rtl839x_traffic_get(int source) { return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source)); } -void rtl839x_traffic_set(int source, u64 dest_matrix) +static void rtl839x_traffic_set(int source, u64 dest_matrix) { rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source)); } -void rtl839x_traffic_enable(int source, int dest) +static void rtl839x_traffic_enable(int source, int dest) { rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source)); } -void rtl839x_traffic_disable(int source, int dest) +static void rtl839x_traffic_disable(int source, int dest) { rtl839x_mask_port_reg_be(BIT_ULL(dest), 0, rtl839x_port_iso_ctrl(source)); } @@ -858,7 +858,7 @@ static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port } /* Enables or disables the EEE/EEEP capability of a port */ -void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable) +static void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable) { u32 v; @@ -881,7 +881,7 @@ void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enabl } /* Get EEE own capabilities and negotiation result */ -int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port) +static int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port) { u64 link, a; @@ -1127,7 +1127,7 @@ static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ * however the RTL9310 has 2 more registers / fields and the physical field-ids * On the RTL8390 the template mask registers are not word-aligned! */ -void rtl839x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) +static void rtl839x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) { for (int i = 0; i < N_FIXED_FIELDS; i++) { enum template_field_id field_type = t[i]; @@ -1400,7 +1400,7 @@ static void rtl839x_read_pie_action(u32 r[], struct pie_rule *pr) pr->bypass_ibc_sc = r[16] & BIT(7); } -void rtl839x_pie_rule_dump_raw(u32 r[]) +static void rtl839x_pie_rule_dump_raw(u32 r[]) { pr_debug("Raw IACL table entry:\n"); pr_debug("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]); @@ -1736,14 +1736,14 @@ static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv) } } -int rtl839x_l3_setup(struct rtl838x_switch_priv *priv) +static int rtl839x_l3_setup(struct rtl838x_switch_priv *priv) { rtl839x_setup_port_macs(priv); return 0; } -void rtl839x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) +static void rtl839x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) { sw_w32(FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK, keep_outer ? RTL839X_VLAN_PORT_TAG_STS_TAGGED : RTL839X_VLAN_PORT_TAG_STS_UNTAG) | @@ -1752,7 +1752,7 @@ void rtl839x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) RTL839X_VLAN_PORT_TAG_STS_CTRL(port)); } -void rtl839x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) +static void rtl839x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) { if (type == PBVLAN_TYPE_INNER) sw_w32_mask(0x3, mode, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); @@ -1760,7 +1760,7 @@ void rtl839x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan sw_w32_mask(0x3 << 14, mode << 14, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); } -void rtl839x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) +static void rtl839x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) { if (type == PBVLAN_TYPE_INNER) sw_w32_mask(0xfff << 2, pvid << 2, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); @@ -1796,14 +1796,14 @@ static void rtl839x_set_egr_filter(int port, enum egr_filter state) RTL839X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2))); } -void rtl839x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) +static void rtl839x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) { sw_w32_mask(3 << ((group & 0xf) << 1), algoidx << ((group & 0xf) << 1), RTL839X_TRK_HASH_IDX_CTRL + ((group >> 4) << 2)); sw_w32(algomsk, RTL839X_TRK_HASH_CTRL + (algoidx << 2)); } -void rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action) +static void rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action) { switch(type) { case BPDU: diff --git a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl83xx.h b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl83xx.h index 55a6851d46..56f7a8f534 100644 --- a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl83xx.h +++ b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl83xx.h @@ -75,32 +75,38 @@ inline void rtl_table_data_w(struct table_reg *r, u32 v, int i); void __init rtl83xx_setup_qos(struct rtl838x_switch_priv *priv); +void rtl83xx_fast_age(struct dsa_switch *ds, int port); int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv); - +int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port); int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_priv *priv); +void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); +int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data); int read_phy(u32 port, u32 page, u32 reg, u32 *val); int write_phy(u32 port, u32 page, u32 reg, u32 val); /* Port register accessor functions for the RTL839x and RTL931X SoCs */ void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg); +u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port); u64 rtl839x_get_port_reg_be(int reg); void rtl839x_set_port_reg_be(u64 set, int reg); void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg); +int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate); void rtl839x_set_port_reg_le(u64 set, int reg); u64 rtl839x_get_port_reg_le(int reg); /* Port register accessor functions for the RTL838x and RTL930X SoCs */ void rtl838x_mask_port_reg(u64 clear, u64 set, int reg); void rtl838x_set_port_reg(u64 set, int reg); +u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port); u64 rtl838x_get_port_reg(int reg); +int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate); /* RTL838x-specific */ u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed); irqreturn_t rtl838x_switch_irq(int irq, void *dev_id); void rtl8380_get_version(struct rtl838x_switch_priv *priv); void rtl838x_vlan_profile_dump(int index); -int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg); void rtl8380_sds_rst(int mac); int rtl8380_sds_power(int mac, int val); void rtl838x_print_matrix(void); @@ -110,7 +116,6 @@ u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed); irqreturn_t rtl839x_switch_irq(int irq, void *dev_id); void rtl8390_get_version(struct rtl838x_switch_priv *priv); void rtl839x_vlan_profile_dump(int index); -int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val); void rtl839x_exec_tbl2_cmd(u32 cmd); void rtl839x_print_matrix(void); @@ -120,17 +125,50 @@ irqreturn_t rtl930x_switch_irq(int irq, void *dev_id); irqreturn_t rtl839x_switch_irq(int irq, void *dev_id); void rtl930x_vlan_profile_dump(int index); int rtl9300_sds_power(int mac, int val); -void rtl9300_sds_rst(int sds_num, u32 mode); -int rtl9300_serdes_setup(int port, int sds_num, phy_interface_t phy_mode); +extern int rtl9300_serdes_setup(int port, int sds_num, phy_interface_t phy_mode); void rtl930x_print_matrix(void); /* RTL931x-specific */ irqreturn_t rtl931x_switch_irq(int irq, void *dev_id); int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode); int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode); -void rtl931x_sds_init(u32 sds, phy_interface_t mode); +extern void rtl931x_sds_init(u32 sds, phy_interface_t mode); int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_lag_upper_info *info); int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port); +/* phy functions that will need to be moved to the future mdio driver */ + +int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val); +int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val); + +int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); +int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); + +int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); +int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); + +int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); +int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); + +/* + * TODO: The following functions are currently not in use. So compiler will complain if + * they are static and not made available externally. To preserve them for future use + * collect them in this section. + */ + +void rtl838x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port, + int queue, u32 rate); + +int rtl8390_sds_power(int mac, int val); +void rtl839x_pie_rule_dump(struct pie_rule *pr); +void rtl839x_set_egress_queue(int port, int queue); + +void rtl9300_dump_debug(void); +void rtl930x_pie_rule_dump_raw(u32 r[]); + +void rtl931x_print_matrix(void); +void rtl931x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action); +void rtl931x_sw_init(struct rtl838x_switch_priv *priv); + #endif /* _NET_DSA_RTL83XX_H */ diff --git a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl930x.c index d45d5911a5..f278445b11 100644 --- a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl930x.c @@ -638,7 +638,7 @@ static void rtl930x_write_mcast_pmask(int idx, u64 portmask) rtl_table_release(q); } -u64 rtl930x_traffic_get(int source) +static u64 rtl930x_traffic_get(int source) { u32 v; struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); @@ -652,7 +652,7 @@ u64 rtl930x_traffic_get(int source) } /* Enable traffic between a source port and a destination port matrix */ -void rtl930x_traffic_set(int source, u64 dest_matrix) +static void rtl930x_traffic_set(int source, u64 dest_matrix) { struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); @@ -661,7 +661,7 @@ void rtl930x_traffic_set(int source, u64 dest_matrix) rtl_table_release(r); } -void rtl930x_traffic_enable(int source, int dest) +static void rtl930x_traffic_enable(int source, int dest) { struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); rtl_table_read(r, source); @@ -670,7 +670,7 @@ void rtl930x_traffic_enable(int source, int dest) rtl_table_release(r); } -void rtl930x_traffic_disable(int source, int dest) +static void rtl930x_traffic_disable(int source, int dest) { struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); rtl_table_read(r, source); @@ -892,7 +892,7 @@ u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed) } /* Enables or disables the EEE/EEEP capability of a port */ -void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable) +static void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable) { u32 v; @@ -914,7 +914,7 @@ void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enabl } /* Get EEE own capabilities and negotiation result */ -int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port) +static int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port) { u32 link, a; @@ -2204,7 +2204,7 @@ static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac) * - The router's MAC address on which routed packets are expected * - MAC addresses used as source macs of routed packets */ -int rtl930x_l3_setup(struct rtl838x_switch_priv *priv) +static int rtl930x_l3_setup(struct rtl838x_switch_priv *priv) { /* Setup MTU with id 0 for default interface */ for (int i = 0; i < MAX_INTF_MTUS; i++) @@ -2300,7 +2300,7 @@ static void rtl930x_packet_cntr_clear(int counter) rtl_table_release(r); } -void rtl930x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) +static void rtl930x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) { sw_w32(FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK, keep_outer ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG) | @@ -2309,7 +2309,7 @@ void rtl930x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) RTL930X_VLAN_PORT_TAG_STS_CTRL(port)); } -void rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) +static void rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) { if (type == PBVLAN_TYPE_INNER) sw_w32_mask(0x3, mode, RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); @@ -2317,7 +2317,7 @@ void rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan sw_w32_mask(0x3 << 14, mode << 14 ,RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); } -void rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) +static void rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) { if (type == PBVLAN_TYPE_INNER) sw_w32_mask(0xfff << 2, pvid << 2, RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); @@ -2353,7 +2353,7 @@ static void rtl930x_set_egr_filter(int port, enum egr_filter state) RTL930X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2))); } -void rtl930x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) +static void rtl930x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) { u32 l3shift = 0; u32 newmask = 0; diff --git a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl931x.c index 69f7c31653..27d6a4fbb9 100644 --- a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl931x.c +++ b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl931x.c @@ -136,7 +136,7 @@ inline int rtl931x_tbl_access_data_0(int i) return RTL931X_TBL_ACCESS_DATA_0(i); } -void rtl931x_vlan_profile_dump(int index) +static void rtl931x_vlan_profile_dump(int index) { u64 profile[4]; @@ -528,7 +528,7 @@ void rtl931x_set_receive_management_action(int port, rma_ctrl_t type, action_typ } } -u64 rtl931x_traffic_get(int source) +static u64 rtl931x_traffic_get(int source) { u32 v; struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6); @@ -542,7 +542,7 @@ u64 rtl931x_traffic_get(int source) } /* Enable traffic between a source port and a destination port matrix */ -void rtl931x_traffic_set(int source, u64 dest_matrix) +static void rtl931x_traffic_set(int source, u64 dest_matrix) { struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6); @@ -551,7 +551,7 @@ void rtl931x_traffic_set(int source, u64 dest_matrix) rtl_table_release(r); } -void rtl931x_traffic_enable(int source, int dest) +static void rtl931x_traffic_enable(int source, int dest) { struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6); rtl_table_read(r, source); @@ -560,7 +560,7 @@ void rtl931x_traffic_enable(int source, int dest) rtl_table_release(r); } -void rtl931x_traffic_disable(int source, int dest) +static void rtl931x_traffic_disable(int source, int dest) { struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6); rtl_table_read(r, source); @@ -941,7 +941,7 @@ static void rtl931x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int inde * pie_data_fill function for all SoCs, provided we have also for each SoC a * function to map between physical and intermediate field type */ -int rtl931x_pie_data_fill(enum template_field_id field_type, struct pie_rule *pr, u16 *data, u16 *data_m) +static int rtl931x_pie_data_fill(enum template_field_id field_type, struct pie_rule *pr, u16 *data, u16 *data_m) { *data = *data_m = 0; @@ -1233,7 +1233,7 @@ static void rtl931x_write_pie_action(u32 r[], struct pie_rule *pr) r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0; } -void rtl931x_pie_rule_dump_raw(u32 r[]) +static void rtl931x_pie_rule_dump_raw(u32 r[]) { pr_debug("Raw IACL table entry:\n"); pr_debug("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n", @@ -1477,12 +1477,12 @@ static void rtl931x_pie_init(struct rtl838x_switch_priv *priv) } -int rtl931x_l3_setup(struct rtl838x_switch_priv *priv) +static int rtl931x_l3_setup(struct rtl838x_switch_priv *priv) { return 0; } -void rtl931x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) +static void rtl931x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) { sw_w32(FIELD_PREP(RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK, keep_outer ? RTL931X_VLAN_PORT_TAG_STS_TAGGED : RTL931X_VLAN_PORT_TAG_STS_UNTAG) | @@ -1491,7 +1491,7 @@ void rtl931x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) RTL931X_VLAN_PORT_TAG_CTRL(port)); } -void rtl931x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) +static void rtl931x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) { if (type == PBVLAN_TYPE_INNER) sw_w32_mask(0x3 << 12, mode << 12, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); @@ -1499,7 +1499,7 @@ void rtl931x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan sw_w32_mask(0x3 << 26, mode << 26, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); } -void rtl931x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) +static void rtl931x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) { if (type == PBVLAN_TYPE_INNER) sw_w32_mask(0xfff, pvid, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); @@ -1519,7 +1519,7 @@ static void rtl931x_set_egr_filter(int port, enum egr_filter state) RTL931X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2))); } -void rtl931x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) +static void rtl931x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) { u32 l3shift = 0; u32 newmask = 0; diff --git a/target/linux/realtek/files-6.6/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.6/drivers/net/ethernet/rtl838x_eth.c index d6647b2806..5f020979c7 100644 --- a/target/linux/realtek/files-6.6/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-6.6/drivers/net/ethernet/rtl838x_eth.c @@ -25,6 +25,34 @@ extern struct rtl83xx_soc_info soc_info; +extern int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data); + +extern int rtl838x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); +extern int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +extern int rtl838x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); +extern int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val); + +extern int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); +extern int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg); +extern int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); +extern int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val); +extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v); + +extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); +extern int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg); +extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); +extern int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val); +extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v); + +extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); +extern int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +extern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg); +extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); +extern int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val); +extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v); + /* Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX * The ring is assigned by switch based on packet/port priortity * Maximum number of TX rings is 2, Ring 2 being the high priority @@ -204,35 +232,22 @@ struct rtl838x_eth_priv { u16 rxringlen; }; -extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv); -extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg); -extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg); -extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v); -extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg); -extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v); -extern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg); -extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v); -extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); -extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); -extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); -extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); - /* On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of * the rings. Writing x into these registers substracts x from its content. * When the content reaches the ring size, the ASIC no longer adds * packets to this receive queue. */ -void rtl838x_update_cntr(int r, int released) +static void rtl838x_update_cntr(int r, int released) { /* This feature is not available on RTL838x SoCs */ } -void rtl839x_update_cntr(int r, int released) +static void rtl839x_update_cntr(int r, int released) { /* This feature is not available on RTL839x SoCs */ } -void rtl930x_update_cntr(int r, int released) +static void rtl930x_update_cntr(int r, int released) { int pos = (r % 3) * 10; u32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2); @@ -244,7 +259,7 @@ void rtl930x_update_cntr(int r, int released) sw_w32(v, reg); } -void rtl931x_update_cntr(int r, int released) +static void rtl931x_update_cntr(int r, int released) { int pos = (r % 3) * 10; u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2); @@ -264,7 +279,7 @@ struct dsa_tag { bool crc_error; }; -bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t) +static bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t) { /* cpu_tag[0] is reserved. Fields are off-by-one */ t->reason = h->cpu_tag[4] & 0xf; @@ -281,7 +296,7 @@ bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t) return t->l2_offloaded; } -bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t) +static bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t) { /* cpu_tag[0] is reserved. Fields are off-by-one */ t->reason = h->cpu_tag[5] & 0x1f; @@ -299,7 +314,7 @@ bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t) return t->l2_offloaded; } -bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t) +static bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t) { t->reason = h->cpu_tag[7] & 0x3f; t->queue = (h->cpu_tag[2] >> 11) & 0x1f; @@ -315,7 +330,7 @@ bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t) return t->l2_offloaded; } -bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t) +static bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t) { t->reason = h->cpu_tag[7] & 0x3f; t->queue = (h->cpu_tag[2] >> 11) & 0x1f; @@ -371,7 +386,7 @@ struct fdb_update_work { u64 macs[NOTIFY_EVENTS + 1]; }; -void rtl838x_fdb_sync(struct work_struct *work) +static void rtl838x_fdb_sync(struct work_struct *work) { const struct fdb_update_work *uw = container_of(work, struct fdb_update_work, work); @@ -1198,7 +1213,7 @@ txdone: /* Return queue number for TX. On the RTL83XX, these queues have equal priority * so we do round-robin */ -u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb, +static u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb, struct net_device *sb_dev) { static u8 last = 0; @@ -1209,7 +1224,7 @@ u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb, /* Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue */ -u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb, +static u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb, struct net_device *sb_dev) { if (skb->priority >= TC_PRIO_CONTROL) @@ -1790,6 +1805,24 @@ int phy_port_read_paged(struct phy_device *phydev, int port, int page, u32 regnu return rtmdio_access(phydev, RTMDIO_READ | RTMDIO_ABS, port, page, regnum, 0); } +/* SerDes reader/writer functions for the ports without external phy. */ + +static int rtmdio_838x_read_sds(int addr, int regnum) +{ + int offset = addr == 26 ? 0x100 : 0x0; + + return sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2)) & 0xffff; +} + +static int rtmdio_838x_write_sds(int addr, int regnum, u16 val) +{ + int offset = addr == 26 ? 0x100 : 0x0; + + sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2)); + + return 0; +} + /* These are the core functions of our new Realtek SoC MDIO bus. */ static int rtmdio_read_c45(struct mii_bus *bus, int addr, int devnum, int regnum) @@ -1821,7 +1854,7 @@ static int rtmdio_83xx_read(struct mii_bus *bus, int addr, int regnum) return -ENODEV; if (addr >= 24 && addr <= 27 && priv->id == 0x8380) - return rtl838x_read_sds_phy(addr, regnum); + return rtmdio_838x_read_sds(addr, regnum); if (priv->family_id == RTL8390_FAMILY_ID && priv->phy_is_internal[addr]) return rtl839x_read_sds_phy(addr, regnum); @@ -1886,7 +1919,7 @@ static int rtmdio_write_c45(struct mii_bus *bus, int addr, int devnum, int regnu static int rtmdio_83xx_write(struct mii_bus *bus, int addr, int regnum, u16 val) { struct rtmdio_bus_priv *priv = bus->priv; - int err, page, offset = 0; + int err, page; if (regnum == RTMDIO_PORT_SELECT) { priv->extaddr = (s16)val; @@ -1901,12 +1934,8 @@ static int rtmdio_83xx_write(struct mii_bus *bus, int addr, int regnum, u16 val) page = priv->page[addr]; - if (addr >= 24 && addr <= 27 && priv->id == 0x8380) { - if (addr == 26) - offset = 0x100; - sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2)); - return 0; - } + if (addr >= 24 && addr <= 27 && priv->id == 0x8380) + return rtmdio_838x_write_sds(addr, regnum, val); if (priv->family_id == RTL8390_FAMILY_ID && priv->phy_is_internal[addr]) return rtl839x_write_sds_phy(addr, regnum, val); diff --git a/target/linux/realtek/files-6.6/drivers/net/ethernet/rtl838x_eth.h b/target/linux/realtek/files-6.6/drivers/net/ethernet/rtl838x_eth.h index 797d671957..8d138cabb9 100644 --- a/target/linux/realtek/files-6.6/drivers/net/ethernet/rtl838x_eth.h +++ b/target/linux/realtek/files-6.6/drivers/net/ethernet/rtl838x_eth.h @@ -445,18 +445,11 @@ struct rtl838x_eth_reg { bool (*decode_tag)(struct p_hdr *h, struct dsa_tag *tag); }; -int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val); -int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val); -int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val); -int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val); -int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val); -int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val); -int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); -int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); -int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val); -int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val); -int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val); -int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val); -int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data); +int phy_package_port_read_paged(struct phy_device *phydev, int port, int page, u32 regnum); +int phy_package_port_write_paged(struct phy_device *phydev, int port, int page, u32 regnum, u16 val); +int phy_package_read_paged(struct phy_device *phydev, int page, u32 regnum); +int phy_package_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val); +int phy_port_read_paged(struct phy_device *phydev, int port, int page, u32 regnum); +int phy_port_write_paged(struct phy_device *phydev, int port, int page, u32 regnum, u16 val); #endif /* _RTL838X_ETH_H */ diff --git a/target/linux/realtek/files-6.6/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-6.6/drivers/net/phy/rtl83xx-phy.c index 8ca8c2a3db..c4a2bac313 100644 --- a/target/linux/realtek/files-6.6/drivers/net/phy/rtl83xx-phy.c +++ b/target/linux/realtek/files-6.6/drivers/net/phy/rtl83xx-phy.c @@ -147,7 +147,7 @@ static int resume_polling(u64 saved_state) return 0; } -int rtl821x_match_phy_device(struct phy_device *phydev) +static int rtl821x_match_phy_device(struct phy_device *phydev) { u64 poll_state; int rawpage, port = phydev->mdio.addr & ~3; @@ -238,7 +238,7 @@ u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6}; /* Reset the SerDes by powering it off and set a new operation mode * of the SerDes. */ -void rtl9300_sds_rst(int sds_num, u32 mode) +static void rtl9300_sds_rst(int sds_num, u32 mode) { pr_info("%s %d\n", __func__, mode); if (sds_num < 0 || sds_num > 11) { @@ -275,7 +275,7 @@ void rtl9300_sds_set(int sds_num, u32 mode) sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4)); } -u32 rtl9300_sds_mode_get(int sds_num) +static u32 rtl9300_sds_mode_get(int sds_num) { u32 v; @@ -422,22 +422,6 @@ int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v) return 0; } -/* On the RTL838x SoCs, the internal SerDes is accessed through direct access to - * standard PHY registers, where a 32 bit register holds a 16 bit word as found - * in a standard page 0 of a PHY - */ -int rtl838x_read_sds_phy(int phy_addr, int phy_reg) -{ - int offset = 0; - u32 val; - - if (phy_addr == 26) - offset = 0x100; - val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff; - - return val; -} - int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v) { int offset = 0; @@ -1084,27 +1068,32 @@ static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre) } } -static int rtl8214fc_set_port(struct phy_device *phydev, int port) +static int rtl8214fc_set_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, const void *data) { - bool is_fibre = (port == PORT_FIBRE ? true : false); - int addr = phydev->mdio.addr; - - pr_debug("%s port %d to %d\n", __func__, addr, port); - - rtl8214fc_media_set(phydev, is_fibre); - - return 0; + /* + * The RTL8214FC driver usually detects insertion of SFP modules and automatically toggles + * between copper and fiber. There may be cases where the user wants to switch the port on + * demand. Usually ethtool offers to change the port of a multiport network card with + * "ethtool -s lan25 port fibre/tp" if the driver supports it. This does not work for + * attached phys. For more details see phy_ethtool_ksettings_set(). To avoid patching the + * kernel misuse the phy downshift tunable to offer that feature. For this use + * "ethtool --set-phy-tunable lan25 downshift on/off". + */ + switch (tuna->id) { + case ETHTOOL_PHY_DOWNSHIFT: + rtl8214fc_media_set(phydev, !rtl8214fc_media_is_fibre(phydev)); + return 0; + default: + return -EOPNOTSUPP; + } } -static int rtl8214fc_get_port(struct phy_device *phydev) +static int rtl8214fc_get_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, void *data) { - int addr = phydev->mdio.addr; - - pr_debug("%s: port %d\n", __func__, addr); - if (rtl8214fc_media_is_fibre(phydev)) - return PORT_FIBRE; - - return PORT_MII; + /* Needed to make rtl8214fc_set_tunable() work */ + return 0; } static int rtl8214fc_get_features(struct phy_device *phydev) @@ -1158,7 +1147,7 @@ static int rtl8214fc_config_aneg(struct phy_device *phydev) * but the only way that works since the kernel first enables EEE in the MAC * and then sets up the PHY. The MAC-based approach would require the oppsite. */ -void rtl8218d_eee_set(struct phy_device *phydev, bool enable) +static void rtl8218d_eee_set(struct phy_device *phydev, bool enable) { u32 val; bool an_enabled; @@ -1679,7 +1668,7 @@ static int rtl8390_configure_serdes(struct phy_device *phydev) return 0; } -void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v) +static void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v) { int l = end_bit - start_bit + 1; u32 data = v; @@ -1695,7 +1684,7 @@ void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, rtl930x_write_sds_phy(sds, page, reg, data); } -u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit) +static u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit) { int l = end_bit - start_bit + 1; u32 v = rtl930x_read_sds_phy(sds, page, reg); @@ -1763,7 +1752,7 @@ static int rtl9300_read_status(struct phy_device *phydev) return 0; } -void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if) +static void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if) { int page = 0x2e; /* 10GR and USXGMII */ @@ -1777,7 +1766,7 @@ void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if) /* Force PHY modes on 10GBit Serdes */ -void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) +static void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) { int lc_value; int sds_mode; @@ -1938,7 +1927,7 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode); } -void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if) +static void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if) { /* parameters: rtl9303_80G_txParam_s2 */ int impedance = 0x8; @@ -2005,7 +1994,7 @@ int rtl9300_sds_clock_wait(int timeout) return 1; } -void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal) +static void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal) { u32 v10, v1; @@ -2186,7 +2175,7 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) dcvs_list[1] = dcvs_coef_bin; } -void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray) +static void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray) { if (manual) { rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1); @@ -2197,7 +2186,7 @@ void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray) } } -void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset) +static void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset) { if (manual) { rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset); @@ -2208,7 +2197,7 @@ void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset) } #define GRAY_BITS 5 -u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code) +static u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code) { int i, j, m; u32 g[GRAY_BITS]; @@ -2234,7 +2223,7 @@ u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code) return leq_binary; } -u32 rtl9300_sds_rxcal_leq_read(int sds_num) +static u32 rtl9300_sds_rxcal_leq_read(int sds_num) { u32 leq_gray, leq_bin; bool leq_manual; @@ -2262,7 +2251,7 @@ u32 rtl9300_sds_rxcal_leq_read(int sds_num) return leq_bin; } -void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[]) +static void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[]) { if (manual) { rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1); @@ -2274,7 +2263,7 @@ void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[]) } } -void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[]) +static void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[]) { u32 vth_manual; @@ -2305,7 +2294,7 @@ void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[]) pr_info("Vth Maunal = %d", vth_manual); } -void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[]) +static void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[]) { if (manual) { switch(tap_id) { @@ -2352,7 +2341,7 @@ void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_ } } -void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[]) +static void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[]) { u32 tap0_sign_out; u32 tap0_coef_bin; @@ -2430,7 +2419,7 @@ void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[]) } } -void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode) +static void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode) { /* From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam */ int tap0_init_val = 0x1f; /* Initial Decision Fed Equalizer 0 tap */ @@ -2525,7 +2514,7 @@ void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode) pr_info("end_1.1.5\n"); } -void rtl9300_do_rx_calibration_2_1(u32 sds_num) +static void rtl9300_do_rx_calibration_2_1(u32 sds_num) { pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n"); @@ -2538,7 +2527,7 @@ void rtl9300_do_rx_calibration_2_1(u32 sds_num) pr_info("end_1.2.1"); } -void rtl9300_do_rx_calibration_2_2(int sds_num) +static void rtl9300_do_rx_calibration_2_2(int sds_num) { /* Force Rx-Run = 0 */ rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0); @@ -2546,7 +2535,7 @@ void rtl9300_do_rx_calibration_2_2(int sds_num) rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER); } -void rtl9300_do_rx_calibration_2_3(int sds_num) +static void rtl9300_do_rx_calibration_2_3(int sds_num) { u32 fgcal_binary, fgcal_gray; u32 offset_range; @@ -2593,7 +2582,7 @@ void rtl9300_do_rx_calibration_2_3(int sds_num) pr_info("%s: end_1.2.3\n", __func__); } -void rtl9300_do_rx_calibration_2(int sds) +static void rtl9300_do_rx_calibration_2(int sds) { rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER); rtl9300_do_rx_calibration_2_1(sds); @@ -2601,7 +2590,7 @@ void rtl9300_do_rx_calibration_2(int sds) rtl9300_do_rx_calibration_2_3(sds); } -void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode) +static void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode) { pr_info("start_1.3.1"); @@ -2617,7 +2606,7 @@ void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode) pr_info("end_1.3.1"); } -void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode) +static void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode) { u32 sum10 = 0, avg10, int10; int dac_long_cable_offset; @@ -2689,7 +2678,7 @@ void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode) rtl9300_sds_rxcal_3_2(sds_num, phy_mode); } -void rtl9300_do_rx_calibration_4_1(int sds_num) +static void rtl9300_do_rx_calibration_4_1(int sds_num) { u32 vth_list[2] = {0, 0}; u32 tap0_list[4] = {0, 0, 0, 0}; @@ -2704,7 +2693,7 @@ void rtl9300_do_rx_calibration_4_1(int sds_num) pr_info("end_1.4.1"); } -void rtl9300_do_rx_calibration_4_2(u32 sds_num) +static void rtl9300_do_rx_calibration_4_2(u32 sds_num) { u32 vth_list[2]; u32 tap_list[4]; @@ -2722,13 +2711,13 @@ void rtl9300_do_rx_calibration_4_2(u32 sds_num) pr_info("end_1.4.2"); } -void rtl9300_do_rx_calibration_4(u32 sds_num) +static void rtl9300_do_rx_calibration_4(u32 sds_num) { rtl9300_do_rx_calibration_4_1(sds_num); rtl9300_do_rx_calibration_4_2(sds_num); } -void rtl9300_do_rx_calibration_5_2(u32 sds_num) +static void rtl9300_do_rx_calibration_5_2(u32 sds_num) { u32 tap1_list[4] = {0}; u32 tap2_list[4] = {0}; @@ -2747,14 +2736,14 @@ void rtl9300_do_rx_calibration_5_2(u32 sds_num) pr_info("end_1.5.2"); } -void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode) +static void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode) { if (phy_mode == PHY_INTERFACE_MODE_10GBASER) /* dfeTap1_4Enable true */ rtl9300_do_rx_calibration_5_2(sds_num); } -void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num) +static void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num) { u32 tap1_list[4] = {0}; u32 tap2_list[4] = {0}; @@ -2769,7 +2758,7 @@ void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num) mdelay(10); } -void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode) +static void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode) { u32 latch_sts; @@ -2793,7 +2782,7 @@ void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode) } } -int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode) +static int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode) { switch (phy_mode) { case PHY_INTERFACE_MODE_XGMII: @@ -2820,7 +2809,7 @@ int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode) return 0; } -u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode) +static u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode) { u32 v = 0; @@ -2841,7 +2830,7 @@ u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode) return v; } -int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode) +static int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode) { u32 errors1, errors2; @@ -2876,7 +2865,7 @@ int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode) return 0; } -void rtl9300_phy_enable_10g_1g(int sds_num) +static void rtl9300_phy_enable_10g_1g(int sds_num) { u32 v; @@ -3118,7 +3107,7 @@ int rtl9300_sds_cmu_band_get(int sds) return cmu_band; } -void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v) +static void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v) { int l = end_bit - start_bit + 1; u32 data = v; @@ -3134,7 +3123,7 @@ void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, rtl931x_write_sds_phy(sds, page, reg, data); } -u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit) +static u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit) { int l = end_bit - start_bit + 1; u32 v = rtl931x_read_sds_phy(sds, page, reg); @@ -3954,13 +3943,13 @@ static struct phy_driver rtl83xx_phy_driver[] = { .config_aneg = rtl8214fc_config_aneg, .get_eee = rtl8214fc_get_eee, .get_features = rtl8214fc_get_features, - .get_port = rtl8214fc_get_port, + .get_tunable = rtl8214fc_get_tunable, .probe = rtl8214fc_phy_probe, .read_page = rtl821x_read_page, .read_status = rtl8214fc_read_status, .resume = rtl8214fc_resume, .set_eee = rtl8214fc_set_eee, - .set_port = rtl8214fc_set_port, + .set_tunable = rtl8214fc_set_tunable, .suspend = rtl8214fc_suspend, .write_page = rtl821x_write_page, }, diff --git a/target/linux/realtek/files-6.6/drivers/net/phy/rtl83xx-phy.h b/target/linux/realtek/files-6.6/drivers/net/phy/rtl83xx-phy.h index 781ecb3c7c..a081d0fdf7 100644 --- a/target/linux/realtek/files-6.6/drivers/net/phy/rtl83xx-phy.h +++ b/target/linux/realtek/files-6.6/drivers/net/phy/rtl83xx-phy.h @@ -67,3 +67,32 @@ struct __attribute__ ((__packed__)) fw_header { #define RTL931X_SERDES_MODE_CTRL (0x13cc) #define RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR (0x13F4) #define RTL931X_MAC_SERDES_MODE_CTRL(sds) (0x136C + (((sds) << 2))) + +int rtl839x_read_sds_phy(int phy_addr, int phy_reg); +int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v); + +int rtl9300_serdes_setup(int port, int sds_num, phy_interface_t phy_mode); +int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg); +int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v); + +int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg); +int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v); +int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode); +void rtl931x_sds_init(u32 sds, phy_interface_t mode); + +/* + * TODO: The following functions are currently not in use. So compiler will complain if + * they are static and not made available externally. Collect them in this section to + * preserve for future use. + */ + +void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode); +int rtl9300_sds_clock_wait(int timeout); +int rtl9300_sds_cmu_band_get(int sds); +void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]); +void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[]); +void rtl9300_sds_set(int sds_num, u32 mode); + +int rtl931x_link_sts_get(u32 sds); +void rtl931x_sds_fiber_disable(u32 sds); +int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode); \ No newline at end of file diff --git a/target/linux/realtek/image/common.mk b/target/linux/realtek/image/common.mk index e600b2347d..d68915ea90 100644 --- a/target/linux/realtek/image/common.mk +++ b/target/linux/realtek/image/common.mk @@ -31,6 +31,18 @@ define Device/d-link_dgs-1210 CAMEO_BOARD_VERSION := 32 endef +# The "IMG-" uImage name allows flashing the iniramfs from the vendor Web UI. +# Avoided for sysupgrade, as the vendor FW would do an incomplete flash. +define Device/engenius_ews2910p + IMAGE_SIZE := 8192k + DEVICE_VENDOR := EnGenius + KERNEL_INITRAMFS := \ + kernel-bin | \ + append-dtb | \ + libdeflate-gzip | \ + uImage gzip -n 'IMG-0.00.00-c0.0.00' +endef + define Device/hpe_1920 DEVICE_VENDOR := HPE IMAGE_SIZE := 29632k diff --git a/target/linux/realtek/image/rtl838x.mk b/target/linux/realtek/image/rtl838x.mk index a090390a50..714b69d90d 100644 --- a/target/linux/realtek/image/rtl838x.mk +++ b/target/linux/realtek/image/rtl838x.mk @@ -91,22 +91,25 @@ define Device/d-link_dgs-1210-28p-f endef TARGET_DEVICES += d-link_dgs-1210-28p-f -# The "IMG-" uImage name allows flashing the iniramfs from the vendor Web UI. -# Avoided for sysupgrade, as the vendor FW would do an incomplete flash. -define Device/engenius_ews2910p +define Device/engenius_ews2910p-v1 + $(Device/engenius_ews2910p) SOC := rtl8380 - IMAGE_SIZE := 8192k - DEVICE_VENDOR := EnGenius DEVICE_MODEL := EWS2910P + DEVICE_VARIANT := v1 DEVICE_PACKAGES += realtek-poe UIMAGE_MAGIC := 0x03802910 - KERNEL_INITRAMFS := \ - kernel-bin | \ - append-dtb | \ - libdeflate-gzip | \ - uImage gzip -n 'IMG-0.00.00-c0.0.00' + SUPPORTED_DEVICES += engenius,ews2910p endef -TARGET_DEVICES += engenius_ews2910p +TARGET_DEVICES += engenius_ews2910p-v1 + +define Device/engenius_ews2910p-v3 + $(Device/engenius_ews2910p) + SOC := rtl8380 + DEVICE_MODEL := EWS2910P + DEVICE_VARIANT := v3 + UIMAGE_MAGIC := 0x03010500 +endef +TARGET_DEVICES += engenius_ews2910p-v3 define Device/hpe_1920-8g $(Device/hpe_1920) diff --git a/target/linux/realtek/patches-6.6/700-dsa-mdio-increase-max-ports-for-rtl839x-rtl931x.patch b/target/linux/realtek/patches-6.6/700-dsa-mdio-increase-max-ports-for-rtl839x-rtl931x.patch new file mode 100644 index 0000000000..147e2c587b --- /dev/null +++ b/target/linux/realtek/patches-6.6/700-dsa-mdio-increase-max-ports-for-rtl839x-rtl931x.patch @@ -0,0 +1,132 @@ +From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 26 Nov 2020 12:02:21 +0100 +Subject: realtek dsa/phy: Increase max ports for RTL839X/RTL931X + +Linux standard can only support up to 32 devices per mdio bus and up to +12 ports per DSA switch. This is not enough for the large RTL839X and +RTL931X devices. Increase the max values accordingly. Additionally take +care about the functions that work on bit masks. + +Submitted-by: Bert Vermeulen +Submitted-by: Birger Koblitz +Submitted-by: Sander Vanheule +Submitted-by: Bjørn Mork +Submitted-by: John Crispin +Signed-off-by: Markus Stockhausen +--- + drivers/net/mdio/fwnode_mdio.c | 2 +- + include/linux/phy.h | 6 +++--- + include/linux/platform_data/dsa.h | 2 +- + include/net/dsa.h | 14 +++++++------- + net/dsa/slave.c | 4 ++-- + 5 files changed, 14 insertions(+), 14 deletions(-) + +--- a/drivers/net/mdio/fwnode_mdio.c ++++ b/drivers/net/mdio/fwnode_mdio.c +@@ -87,7 +87,7 @@ int fwnode_mdiobus_phy_device_register(s + } + + if (fwnode_property_read_bool(child, "broken-turn-around")) +- mdio->phy_ignore_ta_mask |= 1 << addr; ++ mdio->phy_ignore_ta_mask |= BIT_ULL(addr); + + fwnode_property_read_u32(child, "reset-assert-us", + &phy->mdio.reset_assert_delay); +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -294,7 +294,7 @@ static inline const char *phy_modes(phy_ + #define PHY_INIT_TIMEOUT 100000 + #define PHY_FORCE_TIMEOUT 10 + +-#define PHY_MAX_ADDR 32 ++#define PHY_MAX_ADDR 64 + + /* Used when trying to connect to a specific phy (mii bus id:phy device id) */ + #define PHY_ID_FMT "%s:%02x" +@@ -414,10 +414,10 @@ struct mii_bus { + struct mdio_device *mdio_map[PHY_MAX_ADDR]; + + /** @phy_mask: PHY addresses to be ignored when probing */ +- u32 phy_mask; ++ u64 phy_mask; + + /** @phy_ignore_ta_mask: PHY addresses to ignore the TA/read failure */ +- u32 phy_ignore_ta_mask; ++ u64 phy_ignore_ta_mask; + + /** + * @irq: An array of interrupts, each PHY's interrupt at the index +--- a/include/linux/platform_data/dsa.h ++++ b/include/linux/platform_data/dsa.h +@@ -6,7 +6,7 @@ struct device; + struct net_device; + + #define DSA_MAX_SWITCHES 4 +-#define DSA_MAX_PORTS 12 ++#define DSA_MAX_PORTS 54 + #define DSA_RTABLE_NONE -1 + + struct dsa_chip_data { +--- a/include/net/dsa.h ++++ b/include/net/dsa.h +@@ -465,7 +465,7 @@ struct dsa_switch { + /* + * Slave mii_bus and devices for the individual ports. + */ +- u32 phys_mii_mask; ++ u64 phys_mii_mask; + struct mii_bus *slave_mii_bus; + + /* Ageing Time limits in msecs */ +@@ -597,24 +597,24 @@ static inline bool dsa_is_user_port(stru + dsa_switch_for_each_port_continue_reverse((_dp), (_ds)) \ + if (dsa_port_is_cpu((_dp))) + +-static inline u32 dsa_user_ports(struct dsa_switch *ds) ++static inline u64 dsa_user_ports(struct dsa_switch *ds) + { + struct dsa_port *dp; +- u32 mask = 0; ++ u64 mask = 0; + + dsa_switch_for_each_user_port(dp, ds) +- mask |= BIT(dp->index); ++ mask |= BIT_ULL(dp->index); + + return mask; + } + +-static inline u32 dsa_cpu_ports(struct dsa_switch *ds) ++static inline u64 dsa_cpu_ports(struct dsa_switch *ds) + { + struct dsa_port *cpu_dp; +- u32 mask = 0; ++ u64 mask = 0; + + dsa_switch_for_each_cpu_port(cpu_dp, ds) +- mask |= BIT(cpu_dp->index); ++ mask |= BIT_ULL(cpu_dp->index); + + return mask; + } +--- a/net/dsa/slave.c ++++ b/net/dsa/slave.c +@@ -320,7 +320,7 @@ static int dsa_slave_phy_read(struct mii + { + struct dsa_switch *ds = bus->priv; + +- if (ds->phys_mii_mask & (1 << addr)) ++ if (ds->phys_mii_mask & BIT_ULL(addr)) + return ds->ops->phy_read(ds, addr, reg); + + return 0xffff; +@@ -330,7 +330,7 @@ static int dsa_slave_phy_write(struct mi + { + struct dsa_switch *ds = bus->priv; + +- if (ds->phys_mii_mask & (1 << addr)) ++ if (ds->phys_mii_mask & BIT_ULL(addr)) + return ds->ops->phy_write(ds, addr, reg, val); + + return 0; diff --git a/target/linux/realtek/patches-6.6/700-net-dsa-increase-dsa-max-ports-for-rtl838x.patch b/target/linux/realtek/patches-6.6/700-net-dsa-increase-dsa-max-ports-for-rtl838x.patch deleted file mode 100644 index 63991d373c..0000000000 --- a/target/linux/realtek/patches-6.6/700-net-dsa-increase-dsa-max-ports-for-rtl838x.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 26 Nov 2020 12:02:21 +0100 -Subject: net: dsa: Increase max ports for rtl838x - -* rename the target to realtek -* add refactored DSA driver -* add latest gpio driver -* lots of arch cleanups -* new irq driver -* additional boards - -Submitted-by: Bert Vermeulen -Submitted-by: Birger Koblitz -Submitted-by: Sander Vanheule -Submitted-by: Bjørn Mork -Submitted-by: John Crispin ---- - include/linux/platform_data/dsa.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/include/linux/platform_data/dsa.h -+++ b/include/linux/platform_data/dsa.h -@@ -6,7 +6,7 @@ struct device; - struct net_device; - - #define DSA_MAX_SWITCHES 4 --#define DSA_MAX_PORTS 12 -+#define DSA_MAX_PORTS 54 - #define DSA_RTABLE_NONE -1 - - struct dsa_chip_data { diff --git a/target/linux/realtek/patches-6.6/704-include-linux-phy-increase-phy-address-number-for-rtl839x.patch b/target/linux/realtek/patches-6.6/704-include-linux-phy-increase-phy-address-number-for-rtl839x.patch deleted file mode 100644 index f0fd702a6e..0000000000 --- a/target/linux/realtek/patches-6.6/704-include-linux-phy-increase-phy-address-number-for-rtl839x.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 26 Nov 2020 12:02:21 +0100 -Subject: PHY: Increase max PHY adddress number - -* rename the target to realtek -* add refactored DSA driver -* add latest gpio driver -* lots of arch cleanups -* new irq driver -* additional boards - -Submitted-by: Bert Vermeulen -Submitted-by: Birger Koblitz -Submitted-by: Sander Vanheule -Submitted-by: Bjørn Mork -Submitted-by: John Crispin ---- - include/linux/phy.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -297,7 +297,7 @@ static inline const char *phy_modes(phy_ - #define PHY_INIT_TIMEOUT 100000 - #define PHY_FORCE_TIMEOUT 10 - --#define PHY_MAX_ADDR 32 -+#define PHY_MAX_ADDR 64 - - /* Used when trying to connect to a specific phy (mii bus id:phy device id) */ - #define PHY_ID_FMT "%s:%02x" diff --git a/target/linux/realtek/patches-6.6/706-include-linux-add-phy-ops-for-rtl838x.patch b/target/linux/realtek/patches-6.6/706-include-linux-add-phy-ops-for-rtl838x.patch index 09255c5721..3404d55ed3 100644 --- a/target/linux/realtek/patches-6.6/706-include-linux-add-phy-ops-for-rtl838x.patch +++ b/target/linux/realtek/patches-6.6/706-include-linux-add-phy-ops-for-rtl838x.patch @@ -21,12 +21,10 @@ Submitted-by: John Crispin --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -1181,6 +1181,10 @@ struct phy_driver { +@@ -1181,6 +1181,8 @@ struct phy_driver { */ int (*led_polarity_set)(struct phy_device *dev, int index, unsigned long modes); -+ int (*get_port)(struct phy_device *dev); -+ int (*set_port)(struct phy_device *dev, int port); + int (*get_eee)(struct phy_device *dev, struct ethtool_eee *e); + int (*set_eee)(struct phy_device *dev, struct ethtool_eee *e); }; diff --git a/target/linux/realtek/patches-6.6/708-drivers-net-phy-eee-support-for-rtl838x.patch b/target/linux/realtek/patches-6.6/708-drivers-net-phy-eee-support-for-rtl838x.patch index a92045ba8a..44461992b1 100644 --- a/target/linux/realtek/patches-6.6/708-drivers-net-phy-eee-support-for-rtl838x.patch +++ b/target/linux/realtek/patches-6.6/708-drivers-net-phy-eee-support-for-rtl838x.patch @@ -21,19 +21,7 @@ Submitted-by: John Crispin --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -2503,6 +2503,11 @@ int phylink_ethtool_ksettings_set(struct - * the presence of a PHY, this should not be changed as that - * should be determined from the media side advertisement. - */ -+ if (pl->phydev->drv->get_port && pl->phydev->drv->set_port) { -+ if(pl->phydev->drv->get_port(pl->phydev) != kset->base.port) { -+ pl->phydev->drv->set_port(pl->phydev, kset->base.port); -+ } -+ } - return phy_ethtool_ksettings_set(pl->phydev, &phy_kset); - } - -@@ -2805,8 +2810,11 @@ int phylink_ethtool_get_eee(struct phyli +@@ -2805,8 +2805,11 @@ int phylink_ethtool_get_eee(struct phyli ASSERT_RTNL(); @@ -46,7 +34,7 @@ Submitted-by: John Crispin return ret; } -@@ -2823,8 +2831,11 @@ int phylink_ethtool_set_eee(struct phyli +@@ -2823,8 +2826,11 @@ int phylink_ethtool_set_eee(struct phyli ASSERT_RTNL(); diff --git a/target/linux/realtek/patches-6.6/710-net-phy-sfp-re-probe-modules-on-DEV_UP-event.patch b/target/linux/realtek/patches-6.6/710-net-phy-sfp-re-probe-modules-on-DEV_UP-event.patch deleted file mode 100644 index 9f9051045e..0000000000 --- a/target/linux/realtek/patches-6.6/710-net-phy-sfp-re-probe-modules-on-DEV_UP-event.patch +++ /dev/null @@ -1,37 +0,0 @@ -From a381ac0aa281fdb0b41a39d8a2bc08fd88f6db92 Mon Sep 17 00:00:00 2001 -From: Antoine Tenart -Date: Tue, 25 Feb 2020 16:32:37 +0100 -Subject: [PATCH 1/3] net: phy: sfp: re-probe modules on DEV_UP event - -Signed-off-by: Antoine Tenart ---- - drivers/net/phy/sfp.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/net/phy/sfp.c -+++ b/drivers/net/phy/sfp.c -@@ -1570,6 +1570,10 @@ static void sfp_hwmon_probe(struct work_ - struct sfp *sfp = container_of(work, struct sfp, hwmon_probe.work); - int err; - -+ /* Avoid duplicate hwmon devices when re-probing */ -+ if (sfp->hwmon_dev) -+ return; -+ - /* hwmon interface needs to access 16bit registers in atomic way to - * guarantee coherency of the diagnostic monitoring data. If it is not - * possible to guarantee coherency because EEPROM is broken in such way -@@ -2432,6 +2436,13 @@ static void sfp_sm_module(struct sfp *sf - return; - } - -+ /* Re-probe the SFP modules when an interface is brought up, as the MAC -+ * do not report its link status (This means Phylink wouldn't be -+ * triggered if the PHY had a link before a MAC is brought up). -+ */ -+ if (event == SFP_E_DEV_UP && sfp->sm_mod_state == SFP_MOD_PRESENT) -+ sfp_sm_mod_next(sfp, SFP_MOD_PROBE, T_SERIAL); -+ - switch (sfp->sm_mod_state) { - default: - if (event == SFP_E_INSERT) { diff --git a/target/linux/realtek/patches-6.6/714-net-phy-sfp-add-support-for-SMBus.patch b/target/linux/realtek/patches-6.6/714-net-phy-sfp-add-support-for-SMBus.patch index ea6149281d..4fb1e7f293 100644 --- a/target/linux/realtek/patches-6.6/714-net-phy-sfp-add-support-for-SMBus.patch +++ b/target/linux/realtek/patches-6.6/714-net-phy-sfp-add-support-for-SMBus.patch @@ -107,7 +107,7 @@ Signed-off-by: Antoine Tenart static void sfp_i2c_mdiobus_destroy(struct sfp *sfp) { mdiobus_unregister(sfp->i2c_mii); -@@ -1888,9 +1965,15 @@ static void sfp_sm_fault(struct sfp *sfp +@@ -1884,9 +1961,15 @@ static void sfp_sm_fault(struct sfp *sfp static int sfp_sm_add_mdio_bus(struct sfp *sfp) { diff --git a/target/linux/realtek/rtl838x/config-6.6 b/target/linux/realtek/rtl838x/config-6.6 index a9d406f98d..dd9a61a261 100644 --- a/target/linux/realtek/rtl838x/config-6.6 +++ b/target/linux/realtek/rtl838x/config-6.6 @@ -239,8 +239,8 @@ CONFIG_SYS_SUPPORTS_HIGHMEM=y CONFIG_SYS_SUPPORTS_MIPS16=y CONFIG_TARGET_ISA_REV=2 CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_GOV_STEP_WISE=y diff --git a/target/linux/realtek/rtl930x/config-6.6 b/target/linux/realtek/rtl930x/config-6.6 index 772240e4fc..c01fa172f4 100644 --- a/target/linux/realtek/rtl930x/config-6.6 +++ b/target/linux/realtek/rtl930x/config-6.6 @@ -218,8 +218,8 @@ CONFIG_SYS_SUPPORTS_MIPS16=y CONFIG_SYS_SUPPORTS_MULTITHREADING=y CONFIG_TARGET_ISA_REV=2 CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_GOV_STEP_WISE=y diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile index ec67ce77a3..16cfc32a09 100644 --- a/target/linux/rockchip/Makefile +++ b/target/linux/rockchip/Makefile @@ -7,8 +7,7 @@ BOARDNAME:=Rockchip FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs SUBTARGETS:=armv8 -KERNEL_PATCHVER:=6.6 -KERNEL_TESTING_PATCHVER:=6.12 +KERNEL_PATCHVER:=6.12 define Target/Description Build firmware image for Rockchip SoC devices. diff --git a/target/linux/rockchip/armv8/config-6.12 b/target/linux/rockchip/armv8/config-6.12 index ee54c7646f..f9323ef618 100644 --- a/target/linux/rockchip/armv8/config-6.12 +++ b/target/linux/rockchip/armv8/config-6.12 @@ -197,6 +197,7 @@ CONFIG_CRYPTO_CRC64_ROCKSOFT=y CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y CONFIG_CRYPTO_CRYPTD=y +# CONFIG_CRYPTO_DEV_ROCKCHIP is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG_MENU=y diff --git a/target/linux/rockchip/armv8/config-6.6 b/target/linux/rockchip/armv8/config-6.6 deleted file mode 100644 index fa7665a82c..0000000000 --- a/target/linux/rockchip/armv8/config-6.6 +++ /dev/null @@ -1,759 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_FORCE_MAX_ORDER=10 -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=33 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_SELECTS_KEXEC_FILE=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ARC_EMAC_CORE=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_ERRATUM_1024718=y -CONFIG_ARM64_ERRATUM_1165522=y -CONFIG_ARM64_ERRATUM_1286807=y -CONFIG_ARM64_ERRATUM_1319367=y -CONFIG_ARM64_ERRATUM_1463225=y -CONFIG_ARM64_ERRATUM_1530923=y -CONFIG_ARM64_ERRATUM_2051678=y -CONFIG_ARM64_ERRATUM_2054223=y -CONFIG_ARM64_ERRATUM_2067961=y -CONFIG_ARM64_ERRATUM_2077057=y -CONFIG_ARM64_ERRATUM_2441007=y -CONFIG_ARM64_ERRATUM_2441009=y -CONFIG_ARM64_ERRATUM_2658417=y -CONFIG_ARM64_ERRATUM_3117295=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_858921=y -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_PTR_AUTH_KERNEL=y -CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_SVE=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=48 -# CONFIG_ARM64_VA_BITS_39 is not set -CONFIG_ARM64_VA_BITS_48=y -CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y -CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y -CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y -CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y -CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MHU=y -CONFIG_ARM_MHU_V2=y -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ARM_RK3328_DMC_DEVFREQ=y -# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set -CONFIG_ARM_SCMI_CPUFREQ=y -CONFIG_ARM_SCMI_HAVE_SHMEM=y -CONFIG_ARM_SCMI_HAVE_TRANSPORT=y -CONFIG_ARM_SCMI_POWER_CONTROL=y -CONFIG_ARM_SCMI_POWER_DOMAIN=y -CONFIG_ARM_SCMI_PROTOCOL=y -# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set -CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y -CONFIG_ARM_SCMI_TRANSPORT_SMC=y -CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y -CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_SCPI_POWER_DOMAIN=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y -# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set -CONFIG_ARM_SMMU_V3=y -# CONFIG_ARM_SMMU_V3_SVA is not set -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_BLK_DEV_BSG_COMMON=y -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NVME=y -CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BRCMSTB_GISB_ARB=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_BUFFER_HEAD=y -CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CHARGER_GPIO=y -CONFIG_CHARGER_RK817=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLK_PX30=y -CONFIG_CLK_RK3308=y -CONFIG_CLK_RK3328=y -CONFIG_CLK_RK3368=y -CONFIG_CLK_RK3399=y -CONFIG_CLK_RK3568=y -CONFIG_CLK_RK3588=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=16 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SYSFS is not set -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_RK808=y -CONFIG_COMMON_CLK_ROCKCHIP=y -CONFIG_COMMON_CLK_SCMI=y -CONFIG_COMMON_CLK_SCPI=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CONTIG_ALLOC=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_ISOLATION=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MITIGATIONS=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y -CONFIG_CRC16=y -CONFIG_CRC64=y -CONFIG_CRC64_ROCKSOFT=y -CONFIG_CRC_T10DIF=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC64_ROCKSOFT=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y -CONFIG_CRYPTO_CRYPTD=y -# CONFIG_CRYPTO_DEV_ROCKCHIP is not set -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 -CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 -CONFIG_CRYPTO_JITTERENTROPY_OSR=1 -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_GF128MUL=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_POLYVAL=y -CONFIG_CRYPTO_POLYVAL_ARM64_CE=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA3=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SM3=y -CONFIG_CRYPTO_SM3_NEON=y -CONFIG_CRYPTO_SM4=y -CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y -CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y -CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y -CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_INFO=y -CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -CONFIG_DEVFREQ_GOV_PERFORMANCE=y -CONFIG_DEVFREQ_GOV_POWERSAVE=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_USERSPACE=y -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DEVMEM=y -# CONFIG_DEVPORT is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y -CONFIG_DMA_CMA=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DT_IDLE_GENPD=y -CONFIG_DT_IDLE_STATES=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DWMAC_DWC_QOS_ETH=y -CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_ROCKCHIP=y -CONFIG_DW_WATCHDOG=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -CONFIG_EMAC_ROCKCHIP=y -CONFIG_ENERGY_MODEL=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FANOTIFY=y -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FUNCTION_ALIGNMENT=4 -CONFIG_FUNCTION_ALIGNMENT_4B=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_ROCKCHIP=y -CONFIG_GPIO_SYSCON=y -CONFIG_GRO_CELLS=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HOTPLUG_CORE_SYNC=y -CONFIG_HOTPLUG_CORE_SYNC_DEAD=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_PCIE is not set -# CONFIG_HOTPLUG_PCI_SHPC is not set -CONFIG_HUGETLBFS=y -CONFIG_HUGETLB_PAGE=y -CONFIG_HWMON=y -CONFIG_HWSPINLOCK=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_ROCKCHIP=y -CONFIG_HZ=250 -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_RK3X=y -CONFIG_IIO=y -# CONFIG_IIO_SCMI is not set -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INDIRECT_PIO=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_MATRIXKMAP=y -CONFIG_INPUT_RK805_PWRKEY=y -# CONFIG_IOMMUFD is not set -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set -CONFIG_IOMMU_DEFAULT_DMA_STRICT=y -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -CONFIG_IOMMU_DMA=y -CONFIG_IOMMU_IOVA=y -CONFIG_IOMMU_IO_PGTABLE=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_DART is not set -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set -CONFIG_IOMMU_SUPPORT=y -# CONFIG_IO_STRICT_DEVMEM is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MSI_IOMMU=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JUMP_LABEL=y -CONFIG_KALLSYMS=y -CONFIG_KEXEC_CORE=y -CONFIG_KEXEC_FILE=y -CONFIG_KSM=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_LIBCRC32C=y -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOG_BUF_SHIFT=19 -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_BUS_MUX=y -CONFIG_MDIO_BUS_MUX_GPIO=y -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_GE_PHY=y -# CONFIG_MEDIATEK_GE_SOC_PHY is not set -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_KHADAS_MCU is not set -CONFIG_MFD_RK8XX=y -CONFIG_MFD_RK8XX_I2C=y -CONFIG_MFD_RK8XX_SPI=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_CQHCI=y -CONFIG_MMC_DW=y -# CONFIG_MMC_DW_BLUEFIELD is not set -# CONFIG_MMC_DW_EXYNOS is not set -# CONFIG_MMC_DW_HI3798CV200 is not set -# CONFIG_MMC_DW_K3 is not set -# CONFIG_MMC_DW_PCI is not set -CONFIG_MMC_DW_PLTFM=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_DWCMSHC=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMU_LAZY_TLB_REFCOUNT=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MOTORCOMM_PHY=y -CONFIG_MQ_IOSCHED_DEADLINE=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_FLAGS=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -CONFIG_NET_DSA_MT7530_MMIO=y -CONFIG_NET_DSA_REALTEK=y -CONFIG_NET_DSA_REALTEK_MDIO=y -CONFIG_NET_DSA_REALTEK_RTL8365MB=y -CONFIG_NET_DSA_REALTEK_RTL8366RB=y -CONFIG_NET_DSA_REALTEK_SMI=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_DSA_TAG_RTL4_A=y -CONFIG_NET_DSA_TAG_RTL8_4=y -CONFIG_NET_EGRESS=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_INGRESS=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_XGRESS=y -CONFIG_NLS=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=256 -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_NVMEM_ROCKCHIP_EFUSE=y -CONFIG_NVMEM_ROCKCHIP_OTP=y -CONFIG_NVMEM_SYSFS=y -CONFIG_NVME_CORE=y -# CONFIG_NVME_HWMON is not set -# CONFIG_NVME_MULTIPATH is not set -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -# CONFIG_OVERLAY_FS_XINO_AUTO is not set -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_PME=y -CONFIG_PCIE_ROCKCHIP=y -CONFIG_PCIE_ROCKCHIP_DW_HOST=y -CONFIG_PCIE_ROCKCHIP_HOST=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_STUB=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PCS_XPCS=y -CONFIG_PER_VMA_LOCK=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_ROCKCHIP_DP=y -# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set -CONFIG_PHY_ROCKCHIP_EMMC=y -# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set -# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set -# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y -CONFIG_PHY_ROCKCHIP_PCIE=y -# CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX is not set -CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y -CONFIG_PHY_ROCKCHIP_TYPEC=y -CONFIG_PHY_ROCKCHIP_USB=y -CONFIG_PHY_ROCKCHIP_USBDP=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_RK805=y -CONFIG_PINCTRL_ROCKCHIP=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PL330_DMA=y -CONFIG_PLATFORM_MHU=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -CONFIG_PM_DEVFREQ_EVENT=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PPS=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PRINTK_TIME=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_VMCORE=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_SYSFS=y -# CONFIG_QFMT_V2 is not set -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_QUOTA=y -CONFIG_QUOTACTL=y -CONFIG_RAID_ATTRS=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_RANDOMIZE_MODULE_REGION_FULL=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_RCU_TRACE=y -CONFIG_REALTEK_PHY=y -CONFIG_REALTEK_PHY_HWMON=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_IRQ=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_ARM_SCMI=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_RK808=y -CONFIG_RELOCATABLE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_SCMI=y -CONFIG_RFKILL_FULL=y -CONFIG_RFKILL_GPIO=y -CONFIG_RFKILL_LEDS=y -CONFIG_RFS_ACCEL=y -CONFIG_ROCKCHIP_CPUINFO=y -CONFIG_ROCKCHIP_ERRATUM_3568002=y -CONFIG_ROCKCHIP_ERRATUM_3588001=y -CONFIG_ROCKCHIP_GRF=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_ROCKCHIP_MBOX=y -CONFIG_ROCKCHIP_PHY=y -CONFIG_ROCKCHIP_PM_DOMAINS=y -# CONFIG_ROCKCHIP_SARADC is not set -CONFIG_ROCKCHIP_THERMAL=y -CONFIG_ROCKCHIP_TIMER=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RSEQ=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_HYM8563=y -CONFIG_RTC_DRV_RK808=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_NVMEM=y -# CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_CLUSTER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_PROC_FS is not set -CONFIG_SCSI_SAS_ATTRS=y -CONFIG_SCSI_SAS_HOST_SMP=y -CONFIG_SCSI_SAS_LIBSAS=y -# CONFIG_SECURITY_DMESG_RESTRICT is not set -CONFIG_SENSORS_ARM_SCMI=y -CONFIG_SENSORS_ARM_SCPI=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_EXAR=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_PCILIB=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_AMBAKMI=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_ROCKCHIP=y -CONFIG_SPI_ROCKCHIP_SFC=y -CONFIG_SPI_SPIDEV=y -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FILE_CACHE=y -# CONFIG_SQUASHFS_FILE_DIRECT is not set -CONFIG_SRAM=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_PER_TASK=y -CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_STACKTRACE=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -CONFIG_STRICT_DEVMEM=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_SWAP is not set -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYNC_FILE=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFS_SYSCALL=y -# CONFIG_TEXTSEARCH is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_CLOCK=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y -# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_TRANS_TABLE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_TYPEC=y -# CONFIG_TYPEC_ANX7411 is not set -CONFIG_TYPEC_FUSB302=y -# CONFIG_TYPEC_HD3SS3220 is not set -# CONFIG_TYPEC_MUX_FSA4480 is not set -# CONFIG_TYPEC_MUX_GPIO_SBU is not set -# CONFIG_TYPEC_MUX_NB7VPQ904M is not set -# CONFIG_TYPEC_MUX_PI3USB30532 is not set -# CONFIG_TYPEC_RT1719 is not set -# CONFIG_TYPEC_STUSB160X is not set -# CONFIG_TYPEC_TCPCI is not set -CONFIG_TYPEC_TCPM=y -# CONFIG_TYPEC_TPS6598X is not set -# CONFIG_TYPEC_WUSB3801 is not set -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UEVENT_HELPER is not set -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_HOST=y -CONFIG_USB_DWC3_OF_SIMPLE=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_ULPI_BUS=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PLATFORM=y -# CONFIG_VIRTIO_MENU is not set -CONFIG_VMAP_STACK=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XARRAY_MULTI=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts index 6e1d3983bc..5c4d1787ea 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts @@ -54,6 +54,7 @@ clock-names = "ext_clock"; pinctrl-names = "default"; pinctrl-0 = <&wifi_enable_h &clk32k_out1>; + post-power-on-delay-ms = <200>; reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; }; @@ -136,6 +137,7 @@ regulator-name = "vcc3v3_pi6c"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; vin-supply = <&vcc_syson>; }; @@ -147,6 +149,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; vin-supply = <&vcc3v3_pi6c>; }; @@ -237,7 +240,6 @@ }; &combphy0 { - rockchip,sgmii-mac-sel = <0>; status = "okay"; }; @@ -246,6 +248,7 @@ }; &combphy2 { + rockchip,sgmii-mac-sel = <0>; status = "okay"; }; @@ -391,6 +394,10 @@ }; &pcie3x2 { + max-link-speed = <1>; + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1m0_pins>; reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; @@ -493,7 +500,6 @@ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; sd-uhs-sdr25; sd-uhs-sdr50; - sd-uhs-sdr104; vmmc-supply = <&vcc3v3_sys>; vqmmc-supply = <&vcc_1v8>; #address-cells = <1>; diff --git a/target/linux/rockchip/patches-6.6/001-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch b/target/linux/rockchip/patches-6.6/001-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch deleted file mode 100644 index fb5015cf6e..0000000000 --- a/target/linux/rockchip/patches-6.6/001-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 36d9b3ae708e865cdab95692db5a24c5d975383d Mon Sep 17 00:00:00 2001 -From: Dragan Simic -Date: Tue, 12 Dec 2023 09:01:39 +0100 -Subject: [PATCH] arm64: dts: rockchip: Add ethernet0 alias to the dts for - RK3566 boards - -Add ethernet0 alias to the board dts files for a few supported RK3566 boards -that had it missing. Also, remove the ethernet0 alias from one RK3566 SoM -dtsi file, which doesn't enable the GMAC, and add the ethernet0 alias back to -the dependent board dts files, which actually enable the GMAC. - -Signed-off-by: Dragan Simic -Link: https://lore.kernel.org/r/d2a272e0ae0fff0adfab8bb0238243b11d348799.1702368023.git.dsimic@manjaro.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 1 + - 1 files changed, 1 insertions(+), 0 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -@@ -14,6 +14,7 @@ - compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566"; - - aliases { -+ ethernet0 = &gmac1; - mmc1 = &sdmmc0; - }; - diff --git a/target/linux/rockchip/patches-6.6/002-v6.7-arm64-dts-rockchip-Add-missing-sdmmc2-SDR-rates-to-rock-3.patch b/target/linux/rockchip/patches-6.6/002-v6.7-arm64-dts-rockchip-Add-missing-sdmmc2-SDR-rates-to-rock-3.patch deleted file mode 100644 index f70ba3c081..0000000000 --- a/target/linux/rockchip/patches-6.6/002-v6.7-arm64-dts-rockchip-Add-missing-sdmmc2-SDR-rates-to-rock-3.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 0597d85859e48c4366862a6252479698590ae39c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= -Date: Wed, 11 Oct 2023 19:14:56 +0000 -Subject: [PATCH] arm64: dts: rockchip: Add missing sdmmc2 SDR rates to rock-3a -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add missing UHS-I SDR rates to sdmmc2. Add explicit alias as mmc2 while at it. -It would be good to have matching timings enabled in case slower SDIO devices -are encountered. - -Signed-off-by: Tamás Szűcs -Link: https://lore.kernel.org/r/20231011191448.58936-1-tszucs@protonmail.ch -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -15,6 +15,7 @@ - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc0; -+ mmc2 = &sdmmc2; - }; - - chosen: chosen { -@@ -743,6 +744,9 @@ - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; -+ sd-uhs-sdr12; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sys>; - vqmmc-supply = <&vcc_1v8>; diff --git a/target/linux/rockchip/patches-6.6/003-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch b/target/linux/rockchip/patches-6.6/003-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch deleted file mode 100644 index 9be609f661..0000000000 --- a/target/linux/rockchip/patches-6.6/003-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 437644753208092f642b7669c69da606aa07dfb4 Mon Sep 17 00:00:00 2001 -From: Tim Lunn -Date: Wed, 14 Feb 2024 15:07:30 +1100 -Subject: [PATCH] arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board - -Adjust compatible string to match the board vendor of Sinovoip - -Signed-off-by: Tim Lunn -Reviewed-by: Dragan Simic -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20240214040731.3069111-4-tim@feathertop.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -13,7 +13,7 @@ - - / { - model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; -- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; -+ compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; diff --git a/target/linux/rockchip/patches-6.6/004-v6.10-arm64-dts-rockchip-Add-cache-information-to-the-SoC-dtsi-.patch b/target/linux/rockchip/patches-6.6/004-v6.10-arm64-dts-rockchip-Add-cache-information-to-the-SoC-dtsi-.patch deleted file mode 100644 index b23d7e06b9..0000000000 --- a/target/linux/rockchip/patches-6.6/004-v6.10-arm64-dts-rockchip-Add-cache-information-to-the-SoC-dtsi-.patch +++ /dev/null @@ -1,127 +0,0 @@ -From 8612169a05c5e979af033868b7a9b177e0f9fcdf Mon Sep 17 00:00:00 2001 -From: Dragan Simic -Date: Sat, 9 Mar 2024 05:25:06 +0100 -Subject: [PATCH] arm64: dts: rockchip: Add cache information to the SoC dtsi - for RK356x - -Add missing cache information to the Rockchip RK356x SoC dtsi, to allow -the userspace, which includes lscpu(1) that uses the virtual files provided -by the kernel under the /sys/devices/system/cpu directory, to display the -proper RK3566 and RK3568 cache information. - -Adding the cache information to the RK356x SoC dtsi also makes the following -warning message in the kernel log go away: - - cacheinfo: Unable to detect cache hierarchy for CPU 0 - -The cache parameters for the RK356x dtsi were obtained and partially derived -by hand from the cache size and layout specifications found in the following -datasheets and technical reference manuals: - - - Rockchip RK3566 datasheet, version 1.1 - - Rockchip RK3568 datasheet, version 1.3 - - ARM Cortex-A55 revision r1p0 TRM, version 0100-00 - - ARM DynamIQ Shared Unit revision r4p0 TRM, version 0400-02 - -For future reference, here's a rather detailed summary of the documentation, -which applies to both Rockchip RK3566 and RK3568 SoCs: - - - All caches employ the 64-byte cache line length - - Each Cortex-A55 core has 32 KB of L1 4-way, set-associative instruction - cache and 32 KB of L1 4-way, set-associative data cache - - There are no L2 caches, which are per-core and private in Cortex-A55, - because it belongs to the ARM DynamIQ IP core lineup - - The entire SoC has 512 KB of unified L3 16-way, set-associative cache, - which is shared among all four Cortex-A55 CPU cores - - Cortex-A55 cores can be configured without private per-core L2 caches, - in which case the shared L3 cache appears to them as an L2 cache; this - is the case for the RK356x SoCs, so let's use "cache-level = <2>" to - prevent the "huh, no L2 caches, but an L3 cache?" confusion among the - users viewing the data presented to the userspace; another option could - be to have additional 0 KB L2 caches defined, which may be technically - correct, but would probably be even more confusing - -Helped-by: Anand Moon -Tested-By: Diederik de Haas -Reviewed-by: Anand Moon -Signed-off-by: Dragan Simic -Link: https://lore.kernel.org/r/2dee6dad8460b0c5f3b5da53cf55f735840efef1.1709957777.git.dsimic@manjaro.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 41 ++++++++++++++++++++++++ - 1 file changed, 41 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -57,6 +57,13 @@ - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -+ i-cache-size = <0x8000>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <128>; -+ d-cache-size = <0x8000>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <128>; -+ next-level-cache = <&l3_cache>; - }; - - cpu1: cpu@100 { -@@ -66,6 +73,13 @@ - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -+ i-cache-size = <0x8000>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <128>; -+ d-cache-size = <0x8000>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <128>; -+ next-level-cache = <&l3_cache>; - }; - - cpu2: cpu@200 { -@@ -75,6 +89,13 @@ - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -+ i-cache-size = <0x8000>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <128>; -+ d-cache-size = <0x8000>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <128>; -+ next-level-cache = <&l3_cache>; - }; - - cpu3: cpu@300 { -@@ -84,9 +105,29 @@ - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -+ i-cache-size = <0x8000>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <128>; -+ d-cache-size = <0x8000>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <128>; -+ next-level-cache = <&l3_cache>; - }; - }; - -+ /* -+ * There are no private per-core L2 caches, but only the -+ * L3 cache that appears to the CPU cores as L2 caches -+ */ -+ l3_cache: l3-cache { -+ compatible = "cache"; -+ cache-level = <2>; -+ cache-unified; -+ cache-size = <0x80000>; -+ cache-line-size = <64>; -+ cache-sets = <512>; -+ }; -+ - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; diff --git a/target/linux/rockchip/patches-6.6/005-01-v6.8-arm64-dts-rockchip-add-gpio-line-names-to-rk3308-roc.patch b/target/linux/rockchip/patches-6.6/005-01-v6.8-arm64-dts-rockchip-add-gpio-line-names-to-rk3308-roc.patch deleted file mode 100644 index 83ebe67789..0000000000 --- a/target/linux/rockchip/patches-6.6/005-01-v6.8-arm64-dts-rockchip-add-gpio-line-names-to-rk3308-roc.patch +++ /dev/null @@ -1,84 +0,0 @@ -From c45de75d7a9ab44a15dedc7a121d6371d6891301 Mon Sep 17 00:00:00 2001 -From: Trevor Woerner -Date: Mon, 20 Nov 2023 11:22:32 -0500 -Subject: [PATCH] arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s - -Add names to the pins of the general-purpose expansion header as given in the -Radxa GPIO page[1] following the conventions in the kernel documentation[2] to -make it easier for users to correlate the pins with functions when using -utilities such as gpioinfo. - -[1] https://wiki.radxa.com/RockpiS/hardware/gpio -[2] Documentation/devicetree/bindings/gpio/gpio.txt - -Signed-off-by: Trevor Woerner -Link: https://lore.kernel.org/r/20231120162232.27653-1-twoerner@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 58 +++++++++++++++++++ - 1 file changed, 58 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -@@ -315,3 +315,61 @@ - &wdt { - status = "okay"; - }; -+ -+&gpio0 { -+ gpio-line-names = -+ /* GPIO0_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO0_B0 - B7 */ -+ "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]", -+ "", "", "header1-pin11 [GPIO0_B7]", -+ /* GPIO0_C0 - C7 */ -+ "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "", -+ "", "", "", -+ /* GPIO0_D0 - D8 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio1 { -+ gpio-line-names = -+ /* GPIO1_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO1_B0 - B7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO1_C0 - C7 */ -+ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", -+ "header1-pin19 [GPIO1_C7]", -+ /* GPIO1_D0 - D8 */ -+ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "", -+ "", "", ""; -+}; -+ -+&gpio2 { -+ gpio-line-names = -+ /* GPIO2_A0 - A7 */ -+ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "", -+ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", -+ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", -+ /* GPIO2_B0 - B7 */ -+ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", -+ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", -+ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", -+ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", -+ /* GPIO2_C0 - C7 */ -+ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", -+ /* GPIO2_D0 - D8 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio3 { -+ gpio-line-names = -+ /* GPIO3_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO3_B0 - B7 */ -+ "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]", -+ "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "", -+ /* GPIO3_C0 - C7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO3_D0 - D8 */ -+ "", "", "", "", "", "", "", ""; -+}; diff --git a/target/linux/rockchip/patches-6.6/005-02-v6.8-arm64-dts-rockchip-rk3308-rock-pi-s-gpio-line-names-.patch b/target/linux/rockchip/patches-6.6/005-02-v6.8-arm64-dts-rockchip-rk3308-rock-pi-s-gpio-line-names-.patch deleted file mode 100644 index 994644e142..0000000000 --- a/target/linux/rockchip/patches-6.6/005-02-v6.8-arm64-dts-rockchip-rk3308-rock-pi-s-gpio-line-names-.patch +++ /dev/null @@ -1,152 +0,0 @@ -From 085021cc825ed90a6ddc4406f608fb8a85745f81 Mon Sep 17 00:00:00 2001 -From: Trevor Woerner -Date: Tue, 19 Dec 2023 12:38:13 -0500 -Subject: [PATCH] arm64: dts: rockchip: rk3308-rock-pi-s gpio-line-names - cleanup - -Perform the following cleanups on a previous patch: -- indent lines after "gpio-line-names" -- fix D0-D8 -> D0-D7 -- sort phandle references - -Fixes: c45de75d7a9a ("arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s") -Signed-off-by: Trevor Woerner -Link: https://lore.kernel.org/r/20231219173814.1569-1-twoerner@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 120 +++++++++--------- - 1 file changed, 62 insertions(+), 58 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -@@ -166,6 +166,68 @@ - }; - }; - -+&gpio0 { -+ gpio-line-names = -+ /* GPIO0_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO0_B0 - B7 */ -+ "", "", "", "header1-pin3 [GPIO0_B3]", -+ "header1-pin5 [GPIO0_B4]", "", "", -+ "header1-pin11 [GPIO0_B7]", -+ /* GPIO0_C0 - C7 */ -+ "header1-pin13 [GPIO0_C0]", -+ "header1-pin15 [GPIO0_C1]", "", "", "", -+ "", "", "", -+ /* GPIO0_D0 - D7 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio1 { -+ gpio-line-names = -+ /* GPIO1_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO1_B0 - B7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO1_C0 - C7 */ -+ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", -+ "header1-pin19 [GPIO1_C7]", -+ /* GPIO1_D0 - D7 */ -+ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", -+ "", "", "", "", "", ""; -+}; -+ -+&gpio2 { -+ gpio-line-names = -+ /* GPIO2_A0 - A7 */ -+ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", -+ "", "", -+ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", -+ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", -+ /* GPIO2_B0 - B7 */ -+ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", -+ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", -+ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", -+ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", -+ /* GPIO2_C0 - C7 */ -+ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", -+ /* GPIO2_D0 - D7 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio3 { -+ gpio-line-names = -+ /* GPIO3_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO3_B0 - B7 */ -+ "", "", "header2-pin42 [GPIO3_B2]", -+ "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]", -+ "header2-pin39 [GPIO3_B5]", "", "", -+ /* GPIO3_C0 - C7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO3_D0 - D7 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ - &i2c1 { - status = "okay"; - }; -@@ -315,61 +377,3 @@ - &wdt { - status = "okay"; - }; -- --&gpio0 { -- gpio-line-names = -- /* GPIO0_A0 - A7 */ -- "", "", "", "", "", "", "", "", -- /* GPIO0_B0 - B7 */ -- "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]", -- "", "", "header1-pin11 [GPIO0_B7]", -- /* GPIO0_C0 - C7 */ -- "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "", -- "", "", "", -- /* GPIO0_D0 - D8 */ -- "", "", "", "", "", "", "", ""; --}; -- --&gpio1 { -- gpio-line-names = -- /* GPIO1_A0 - A7 */ -- "", "", "", "", "", "", "", "", -- /* GPIO1_B0 - B7 */ -- "", "", "", "", "", "", "", "", -- /* GPIO1_C0 - C7 */ -- "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", -- "header1-pin19 [GPIO1_C7]", -- /* GPIO1_D0 - D8 */ -- "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "", -- "", "", ""; --}; -- --&gpio2 { -- gpio-line-names = -- /* GPIO2_A0 - A7 */ -- "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "", -- "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", -- "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", -- /* GPIO2_B0 - B7 */ -- "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", -- "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", -- "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", -- "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", -- /* GPIO2_C0 - C7 */ -- "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", -- /* GPIO2_D0 - D8 */ -- "", "", "", "", "", "", "", ""; --}; -- --&gpio3 { -- gpio-line-names = -- /* GPIO3_A0 - A7 */ -- "", "", "", "", "", "", "", "", -- /* GPIO3_B0 - B7 */ -- "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]", -- "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "", -- /* GPIO3_C0 - C7 */ -- "", "", "", "", "", "", "", "", -- /* GPIO3_D0 - D8 */ -- "", "", "", "", "", "", "", ""; --}; diff --git a/target/linux/rockchip/patches-6.6/006-01-v6.11-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch b/target/linux/rockchip/patches-6.6/006-01-v6.11-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch deleted file mode 100644 index bb7f833977..0000000000 --- a/target/linux/rockchip/patches-6.6/006-01-v6.11-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 0536fa6e6fa3e48f4ca11855b586c277be524fbe Mon Sep 17 00:00:00 2001 -From: David Wu -Date: Tue, 21 May 2024 21:10:13 +0000 -Subject: [PATCH] soc: rockchip: io-domain: Add RK3308 IO voltage domains - -Add IO voltage domains support for the RK3308 SoC. - -Signed-off-by: David Wu -Signed-off-by: Jianqun Xu -Signed-off-by: Jonas Karlman -Link: https://lore.kernel.org/r/20240521211029.1236094-11-jonas@kwiboo.se -Signed-off-by: Heiko Stuebner ---- - drivers/soc/rockchip/io-domain.c | 40 ++++++++++++++++++++++++++++++++ - 1 file changed, 40 insertions(+) - ---- a/drivers/soc/rockchip/io-domain.c -+++ b/drivers/soc/rockchip/io-domain.c -@@ -39,6 +39,10 @@ - #define RK3288_SOC_CON2_FLASH0 BIT(7) - #define RK3288_SOC_FLASH_SUPPLY_NUM 2 - -+#define RK3308_SOC_CON0 0x300 -+#define RK3308_SOC_CON0_VCCIO3 BIT(8) -+#define RK3308_SOC_VCCIO3_SUPPLY_NUM 3 -+ - #define RK3328_SOC_CON4 0x410 - #define RK3328_SOC_CON4_VCCIO2 BIT(7) - #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1 -@@ -229,6 +233,25 @@ static void rk3288_iodomain_init(struct - dev_warn(iod->dev, "couldn't update flash0 ctrl\n"); - } - -+static void rk3308_iodomain_init(struct rockchip_iodomain *iod) -+{ -+ int ret; -+ u32 val; -+ -+ /* if no vccio3 supply we should leave things alone */ -+ if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg) -+ return; -+ -+ /* -+ * set vccio3 iodomain to also use this framework -+ * instead of a special gpio. -+ */ -+ val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16); -+ ret = regmap_write(iod->grf, RK3308_SOC_CON0, val); -+ if (ret < 0) -+ dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n"); -+} -+ - static void rk3328_iodomain_init(struct rockchip_iodomain *iod) - { - int ret; -@@ -376,6 +399,19 @@ static const struct rockchip_iodomain_so - .init = rk3288_iodomain_init, - }; - -+static const struct rockchip_iodomain_soc_data soc_data_rk3308 = { -+ .grf_offset = 0x300, -+ .supply_names = { -+ "vccio0", -+ "vccio1", -+ "vccio2", -+ "vccio3", -+ "vccio4", -+ "vccio5", -+ }, -+ .init = rk3308_iodomain_init, -+}; -+ - static const struct rockchip_iodomain_soc_data soc_data_rk3328 = { - .grf_offset = 0x410, - .supply_names = { -@@ -529,6 +565,10 @@ static const struct of_device_id rockchi - .data = &soc_data_rk3288 - }, - { -+ .compatible = "rockchip,rk3308-io-voltage-domain", -+ .data = &soc_data_rk3308 -+ }, -+ { - .compatible = "rockchip,rk3328-io-voltage-domain", - .data = &soc_data_rk3328 - }, diff --git a/target/linux/rockchip/patches-6.6/006-02-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch b/target/linux/rockchip/patches-6.6/006-02-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch deleted file mode 100644 index 3565acd2e4..0000000000 --- a/target/linux/rockchip/patches-6.6/006-02-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch +++ /dev/null @@ -1,28 +0,0 @@ -From d1829ba469d5743734e37d59fece73e3668ab084 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 21 May 2024 21:10:14 +0000 -Subject: [PATCH] arm64: dts: rockchip: Add rk3308 IO voltage domains - -Add a disabled RK3308 IO voltage domains node to SoC DT. - -Signed-off-by: Jonas Karlman -Link: https://lore.kernel.org/r/20240521211029.1236094-12-jonas@kwiboo.se -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3308.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -@@ -168,6 +168,11 @@ - compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff000000 0x0 0x08000>; - -+ io_domains: io-domains { -+ compatible = "rockchip,rk3308-io-voltage-domain"; -+ status = "disabled"; -+ }; -+ - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x500>; diff --git a/target/linux/rockchip/patches-6.6/007-01-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch b/target/linux/rockchip/patches-6.6/007-01-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch deleted file mode 100644 index ad746df3b0..0000000000 --- a/target/linux/rockchip/patches-6.6/007-01-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 100b3bdee6035192f6d4a1847970fe004bb505fb Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 21 May 2024 21:10:15 +0000 -Subject: [PATCH] arm64: dts: rockchip: Add io-domains to rk3308-rock-pi-s - -The VCCIO4 io-domain used for WiFi/BT is using 1v8 IO signal voltage. - -Add io-domains node with the VCCIO supplies connected on the board. - -Signed-off-by: Jonas Karlman -Link: https://lore.kernel.org/r/20240521211029.1236094-13-jonas@kwiboo.se -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -@@ -232,6 +232,16 @@ - status = "okay"; - }; - -+&io_domains { -+ vccio0-supply = <&vcc_io>; -+ vccio1-supply = <&vcc_io>; -+ vccio2-supply = <&vcc_io>; -+ vccio3-supply = <&vcc_io>; -+ vccio4-supply = <&vcc_1v8>; -+ vccio5-supply = <&vcc_io>; -+ status = "okay"; -+}; -+ - &pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; diff --git a/target/linux/rockchip/patches-6.6/008-v6.10-arm64-dts-rockchip-correct-the-model-name-for-Radxa-.patch b/target/linux/rockchip/patches-6.6/008-v6.10-arm64-dts-rockchip-correct-the-model-name-for-Radxa-.patch deleted file mode 100644 index d03039d978..0000000000 --- a/target/linux/rockchip/patches-6.6/008-v6.10-arm64-dts-rockchip-correct-the-model-name-for-Radxa-.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 626a479873b6a680b3227c4852bde4a1f2c17fdf Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Fri, 19 Apr 2024 18:30:19 +0800 -Subject: [PATCH] arm64: dts: rockchip: correct the model name for Radxa ROCK - 3A - -According to https://radxa.com/products/rock3/3a, -the name of this board should be "Radxa ROCK 3A". - -Suggested-by: FUKAUMI Naoki -Signed-off-by: Chukun Pan -Reviewed-by: Dragan Simic -Link: https://lore.kernel.org/r/20240419103019.992586-3-amadeus@jmu.edu.cn -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -8,7 +8,7 @@ - #include "rk3568.dtsi" - - / { -- model = "Radxa ROCK3 Model A"; -+ model = "Radxa ROCK 3A"; - compatible = "radxa,rock3a", "rockchip,rk3568"; - - aliases { diff --git a/target/linux/rockchip/patches-6.6/009-01-v6.10-arm64-dts-rockchip-Add-Radxa-ROCK-3C.patch b/target/linux/rockchip/patches-6.6/009-01-v6.10-arm64-dts-rockchip-Add-Radxa-ROCK-3C.patch deleted file mode 100644 index 164b65bdf5..0000000000 --- a/target/linux/rockchip/patches-6.6/009-01-v6.10-arm64-dts-rockchip-Add-Radxa-ROCK-3C.patch +++ /dev/null @@ -1,769 +0,0 @@ -From ee219017ddb50be14c60d3cbe3e51ac0b2008d40 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sun, 28 Apr 2024 20:36:18 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 3C - -The Radxa ROCK 3C is a development board with the -Rockchip RK3566 SoC. It has the following features: - -- 1/2/4GB LPDDR4 -- 1x HDMI Type A -- 1x PCIE 2.0 slot -- 1x FAN connector -- 3.5mm jack with mic -- 1GbE RTL8211F Ethernet -- 1x USB 3.0, 3x USB 2.0 -- 40-pin expansion header -- MicroSD card/eMMC socket -- 16MB SPI NOR (gd25lq128d) -- AP6256 or AIC8800 WiFi/BT - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20240428123618.72170-3-amadeus@jmu.edu.cn -[dropped rk809-sound and not specified pmic sound properties] -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3566-rock-3c.dts | 726 ++++++++++++++++++ - 2 files changed, 727 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qu - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts -@@ -0,0 +1,726 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include -+#include -+#include -+#include -+#include "rk3566.dtsi" -+ -+/ { -+ model = "Radxa ROCK 3C"; -+ compatible = "radxa,rock-3c", "rockchip,rk3566"; -+ -+ aliases { -+ ethernet0 = &gmac1; -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc0; -+ mmc2 = &sdmmc1; -+ }; -+ -+ chosen: chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ gmac1_clkin: external-gmac1-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "gmac1_clkin"; -+ #clock-cells = <0>; -+ }; -+ -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-0 { -+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; -+ function = LED_FUNCTION_HEARTBEAT; -+ color = ; -+ linux,default-trigger = "heartbeat"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&user_led2>; -+ }; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk809 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_reg_on_h>; -+ post-power-on-delay-ms = <100>; -+ power-off-delay-us = <5000000>; -+ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; -+ }; -+ -+ vcc5v_dcin: vcc5v-dcin-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc3v3_pcie: vcc3v3-pcie-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_pwr_en>; -+ regulator-name = "vcc3v3_pcie"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v_dcin>; -+ }; -+ -+ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb30_host_en>; -+ regulator-name = "vcc5v0_usb30_host"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_otg_en>; -+ regulator-name = "vcc5v0_usb_otg"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc_cam: vcc-cam-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_cam_en>; -+ regulator-name = "vcc_cam"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_mipi: vcc-mipi-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_mipi_en>; -+ regulator-name = "vcc_mipi"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&combphy1 { -+ status = "okay"; -+}; -+ -+&combphy2 { -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&gmac1 { -+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; -+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; -+ clock_in_out = "input"; -+ phy-handle = <&rgmii_phy1>; -+ phy-mode = "rgmii-id"; -+ phy-supply = <&vcc_3v3>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1m1_miim -+ &gmac1m1_tx_bus2 -+ &gmac1m1_rx_bus2 -+ &gmac1m1_rgmii_clk -+ &gmac1m1_rgmii_bus -+ &gmac1m1_clkinout>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ avdd-0v9-supply = <&vdda0v9_image>; -+ avdd-1v8-supply = <&vcca1v8_image>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ clock-output-names = "rk808-clkout1", "rk808-clkout2"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; -+ system-power-controller; -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ wakeup-source; -+ #clock-cells = <1>; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ -+ eeprom: eeprom@50 { -+ compatible = "belling,bl24c16a", "atmel,24c16"; -+ reg = <0x50>; -+ pagesize = <16>; -+ }; -+}; -+ -+&i2s0_8ch { -+ status = "okay"; -+}; -+ -+&i2s1_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; -+ rockchip,trcm-sync-tx-only; -+ status = "okay"; -+}; -+ -+&mdio1 { -+ rgmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0x1>; -+ reset-assert-us = <20000>; -+ reset-deassert-us = <100000>; -+ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_reset_h>; -+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ bluetooth { -+ bt_reg_on_h: bt-reg-on-h { -+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_host_h: bt-wake-host-h { -+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake_h: bt-host-wake-h { -+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ cam { -+ vcc_cam_en: vcc_cam_en { -+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ display { -+ vcc_mipi_en: vcc_mipi_en { -+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ leds { -+ user_led2: user-led2 { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie { -+ pcie_pwr_en: pcie-pwr-en { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_reset_h: pcie-reset-h { -+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb { -+ vcc5v0_usb30_host_en: vcc5v0-usb30-host-en { -+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { -+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ wifi { -+ wifi_host_wake_h: wifi-host-wake-h { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_reg_on_h: wifi-reg-on-h { -+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcca1v8_pmu>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio2-supply = <&vcc_1v8>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcca1v8_pmu>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc_3v3>; -+ vccio7-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca_1v8>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ mmc-hs200-1_8v; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ sd-uhs-sdr50; -+ vmmc-supply = <&vcc3v3_sys>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&sdmmc1 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v3_sys>; -+ vqmmc-supply = <&vcca1v8_pmu>; -+ status = "okay"; -+}; -+ -+&sfc { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0x0>; -+ spi-max-frequency = <120000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy0_host { -+ phy-supply = <&vcc5v0_usb30_host>; -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ phy-supply = <&vcc5v0_usb_otg>; -+ status = "okay"; -+}; -+ -+&usb2phy1 { -+ status = "okay"; -+}; -+ -+&usb2phy1_host { -+ phy-supply = <&vcc5v0_usb30_host>; -+ status = "okay"; -+}; -+ -+&usb2phy1_otg { -+ phy-supply = <&vcc5v0_usb30_host>; -+ status = "okay"; -+}; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.6/009-02-v6.11-arm64-dts-rockchip-change-spi-max-frequency-for-Radx.patch b/target/linux/rockchip/patches-6.6/009-02-v6.11-arm64-dts-rockchip-change-spi-max-frequency-for-Radx.patch deleted file mode 100644 index 936fe91c5d..0000000000 --- a/target/linux/rockchip/patches-6.6/009-02-v6.11-arm64-dts-rockchip-change-spi-max-frequency-for-Radx.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 06f6dd4d607766a527e37529f2f3f90dd1464293 Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Sun, 23 Jun 2024 11:33:29 +0900 -Subject: [PATCH] arm64: dts: rockchip: change spi-max-frequency for Radxa ROCK - 3C - -SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency. - -Signed-off-by: FUKAUMI Naoki -Link: https://lore.kernel.org/r/20240623023329.1044-3-naoki@radxa.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts -@@ -633,7 +633,7 @@ - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; -- spi-max-frequency = <120000000>; -+ spi-max-frequency = <104000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; diff --git a/target/linux/rockchip/patches-6.6/010-01-v6.11-arm64-dts-rockchip-Add-Radxa-ZERO-3W-3E.patch b/target/linux/rockchip/patches-6.6/010-01-v6.11-arm64-dts-rockchip-Add-Radxa-ZERO-3W-3E.patch deleted file mode 100644 index 19e6377ad1..0000000000 --- a/target/linux/rockchip/patches-6.6/010-01-v6.11-arm64-dts-rockchip-Add-Radxa-ZERO-3W-3E.patch +++ /dev/null @@ -1,657 +0,0 @@ -From 1a5c8d307c83c808a32686ed51afb4bac2092d39 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 21 May 2024 20:28:05 +0000 -Subject: [PATCH] arm64: dts: rockchip: Add Radxa ZERO 3W/3E - -The Radxa ZERO 3W/3E is an ultra-small, high-performance single board -computer based on the Rockchip RK3566, with a compact form factor and -rich interfaces. - -The ZERO 3W and ZERO 3E are basically the same size and model, but -differ only in storage and network interfaces. - -- eMMC (3W) -- SD-card (both) -- Ethernet (3E) -- WiFi/BT (3W) - -Add initial support for eMMC, SD-card, Ethernet, HDMI and USB. - -Signed-off-by: Jonas Karlman -Link: https://lore.kernel.org/r/20240521202810.1225636-3-jonas@kwiboo.se -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 2 + - .../dts/rockchip/rk3566-radxa-zero-3.dtsi | 463 ++++++++++++++++++ - .../dts/rockchip/rk3566-radxa-zero-3e.dts | 51 ++ - .../dts/rockchip/rk3566-radxa-zero-3w.dts | 91 ++++ - 4 files changed, 607 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi - create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts - create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -81,6 +81,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3e.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3w.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi -@@ -0,0 +1,463 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include -+#include -+#include -+#include "rk3566.dtsi" -+ -+/ { -+ aliases { -+ mmc0 = &sdmmc0; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "d"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&user_led2>; -+ -+ led-green { -+ color = ; -+ default-state = "on"; -+ function = LED_FUNCTION_HEARTBEAT; -+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ vcc_1v8: regulator-1v8-vcc { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc_1v8_p>; -+ }; -+ -+ vcca_1v8: regulator-1v8-vcca { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc_1v8_p>; -+ }; -+ -+ vcca1v8_image: regulator-1v8-vcca-image { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcca1v8_image"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc_1v8_p>; -+ }; -+ -+ vcc_3v3: regulator-3v3-vcc { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ vcc_sys: regulator-5v0-vcc-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&combphy1 { -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu_npu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ avdd-0v9-supply = <&vdda_0v9>; -+ avdd-1v8-supply = <&vcca1v8_image>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ rk817: pmic@20 { -+ compatible = "rockchip,rk817"; -+ reg = <0x20>; -+ #clock-cells = <1>; -+ clock-output-names = "rk817-clkout1", "rk817-clkout2"; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc5-supply = <&vcc_sys>; -+ vcc6-supply = <&vcc_sys>; -+ vcc7-supply = <&vcc_sys>; -+ vcc8-supply = <&vcc_sys>; -+ vcc9-supply = <&vcc5v_midu>; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vdd_gpu_npu: DCDC_REG2 { -+ regulator-name = "vdd_gpu_npu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sys: DCDC_REG4 { -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG1 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_1v8_p: LDO_REG7 { -+ regulator-name = "vcc_1v8_p"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_dvp: LDO_REG8 { -+ regulator-name = "vcc1v8_dvp"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc2v8_dvp: LDO_REG9 { -+ regulator-name = "vcc2v8_dvp"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2800000>; -+ regulator-max-microvolt = <2800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc5v_midu: BOOST { -+ regulator-name = "vcc5v_midu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vbus: OTG_SWITCH { -+ regulator-name = "vbus"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ -+ vdd_cpu: regulator@40 { -+ compatible = "rockchip,rk8600"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1390000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2s0_8ch { -+ status = "okay"; -+}; -+ -+&pinctrl { -+ leds { -+ user_led2: user-led2 { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcca1v8_pmu>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio2-supply = <&vcc_1v8>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcc_1v8>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc_3v3>; -+ vccio7-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca_1v8>; -+ status = "okay"; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ vmmc-supply = <&vcc3v3_sys>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy0_host { -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ status = "okay"; -+}; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts -@@ -0,0 +1,51 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include "rk3566-radxa-zero-3.dtsi" -+ -+/ { -+ model = "Radxa ZERO 3E"; -+ compatible = "radxa,zero-3e", "rockchip,rk3566"; -+ -+ aliases { -+ ethernet0 = &gmac1; -+ }; -+}; -+ -+&gmac1 { -+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; -+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; -+ clock_in_out = "input"; -+ phy-handle = <&rgmii_phy1>; -+ phy-mode = "rgmii-id"; -+ phy-supply = <&vcc_3v3>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1m1_miim -+ &gmac1m1_tx_bus2 -+ &gmac1m1_rx_bus2 -+ &gmac1m1_rgmii_clk -+ &gmac1m1_rgmii_bus -+ &gmac1m1_clkinout>; -+ status = "okay"; -+}; -+ -+&mdio1 { -+ rgmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1_rstn>; -+ reset-assert-us = <20000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&pinctrl { -+ gmac1 { -+ gmac1_rstn: gmac1-rstn { -+ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts -@@ -0,0 +1,91 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include "rk3566-radxa-zero-3.dtsi" -+ -+/ { -+ model = "Radxa ZERO 3W"; -+ compatible = "radxa,zero-3w", "rockchip,rk3566"; -+ -+ aliases { -+ mmc1 = &sdhci; -+ mmc2 = &sdmmc1; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk817 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_reg_on_h>; -+ post-power-on-delay-ms = <100>; -+ power-off-delay-us = <5000000>; -+ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&pinctrl { -+ bluetooth { -+ bt_reg_on_h: bt-reg-on-h { -+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_host_h: bt-wake-host-h { -+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ host_wake_bt_h: host-wake-bt-h { -+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ wifi { -+ wifi_reg_on_h: wifi-reg-on-h { -+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_wake_host_h: wifi-wake-host-h { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ cap-mmc-highspeed; -+ max-frequency = <200000000>; -+ mmc-hs200-1_8v; -+ no-sd; -+ no-sdio; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&sdmmc1 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ no-mmc; -+ no-sd; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; -+ uart-has-rtscts; -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.6/010-02-v6.11-arm64-dts-rockchip-fix-mmc-aliases-for-Radxa-ZERO-3E.patch b/target/linux/rockchip/patches-6.6/010-02-v6.11-arm64-dts-rockchip-fix-mmc-aliases-for-Radxa-ZERO-3E.patch deleted file mode 100644 index b96e8e1774..0000000000 --- a/target/linux/rockchip/patches-6.6/010-02-v6.11-arm64-dts-rockchip-fix-mmc-aliases-for-Radxa-ZERO-3E.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 060c1950037e4c54ca4d8186a8f46269e35db901 Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Fri, 21 Jun 2024 07:44:35 +0900 -Subject: [PATCH] arm64: dts: rockchip: fix mmc aliases for Radxa ZERO 3E/3W - -align with other Radxa products. - -- mmc0 is eMMC -- mmc1 is microSD - -for ZERO 3E, there is no eMMC, but aliases should start at 0, so mmc0 -is microSD as exception. - -Fixes: 1a5c8d307c83 ("arm64: dts: rockchip: Add Radxa ZERO 3W/3E") -Signed-off-by: FUKAUMI Naoki - -Changes in v3: -- fix syntax error in rk3566-radxa-zero-3e.dts -Changes in v2: -- microSD is mmc0 instead of mmc1 for ZERO 3E - -Link: https://lore.kernel.org/r/20240620224435.2752-1-naoki@radxa.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi | 4 ---- - arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts | 1 + - arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts | 3 ++- - 3 files changed, 3 insertions(+), 5 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi -@@ -6,10 +6,6 @@ - #include "rk3566.dtsi" - - / { -- aliases { -- mmc0 = &sdmmc0; -- }; -- - chosen { - stdout-path = "serial2:1500000n8"; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts -@@ -10,6 +10,7 @@ - - aliases { - ethernet0 = &gmac1; -+ mmc0 = &sdmmc0; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts -@@ -9,7 +9,8 @@ - compatible = "radxa,zero-3w", "rockchip,rk3566"; - - aliases { -- mmc1 = &sdhci; -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc0; - mmc2 = &sdmmc1; - }; - diff --git a/target/linux/rockchip/patches-6.6/010-03-v6.11-arm64-dts-rockchip-add-gpio-line-names-to-radxa-zero.patch b/target/linux/rockchip/patches-6.6/010-03-v6.11-arm64-dts-rockchip-add-gpio-line-names-to-radxa-zero.patch deleted file mode 100644 index 4c5107ab35..0000000000 --- a/target/linux/rockchip/patches-6.6/010-03-v6.11-arm64-dts-rockchip-add-gpio-line-names-to-radxa-zero.patch +++ /dev/null @@ -1,101 +0,0 @@ -From f7c742cbe664ebdedc075945e75443683d1175f7 Mon Sep 17 00:00:00 2001 -From: Trevor Woerner -Date: Wed, 19 Jun 2024 21:32:49 -0400 -Subject: [PATCH] arm64: dts: rockchip: add gpio-line-names to radxa-zero-3 - -Add names to the pins of the general-purpose expansion header as given -in the Radxa documentation[1] following the conventions in the kernel[2] -to make it easier for users to correlate pins with functions when using -utilities such as 'gpioinfo'. - -[1] https://docs.radxa.com/en/zero/zero3/hardware-design/hardware-interface -[2] https://www.kernel.org/doc/Documentation/devicetree/bindings/gpio/gpio.txt - -Signed-off-by: Trevor Woerner -Link: https://lore.kernel.org/r/20240620013301.33653-1-twoerner@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../dts/rockchip/rk3566-radxa-zero-3.dtsi | 72 +++++++++++++++++++ - 1 file changed, 72 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi -@@ -105,6 +105,78 @@ - cpu-supply = <&vdd_cpu>; - }; - -+&gpio0 { -+ gpio-line-names = -+ /* GPIO0_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO0_B0 - B7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO0_C0 - C7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO0_D0 - D7 */ -+ "pin-10 [GPIO0_D0]", "pin-08 [GPIO0_D1]", "", -+ "", "", "", "", ""; -+}; -+ -+&gpio1 { -+ gpio-line-names = -+ /* GPIO1_A0 - A7 */ -+ "pin-03 [GPIO1_A0]", "pin-05 [GPIO1_A1]", "", -+ "", "pin-37 [GPIO1_A4]", "", -+ "", "", -+ /* GPIO1_B0 - B7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO1_C0 - C7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO1_D0 - D7 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio2 { -+ gpio-line-names = -+ /* GPIO2_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO2_B0 - B7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO2_C0 - C7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO2_D0 - D7 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio3 { -+ gpio-line-names = -+ /* GPIO3_A0 - A7 */ -+ "", "pin-11 [GPIO3_A1]", "pin-13 [GPIO3_A2]", -+ "pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]", -+ "pin-38 [GPIO3_A6]", "pin-36 [GPIO3_A7]", -+ /* GPIO3_B0 - B7 */ -+ "pin-15 [GPIO3_B0]", "pin-16 [GPIO3_B1]", "pin-18 [GPIO3_B2]", -+ "pin-29 [GPIO3_B3]", "pin-31 [GPIO3_B4]", "", -+ "", "", -+ /* GPIO3_C0 - C7 */ -+ "", "pin-22 [GPIO3_C1]", "pin-32 [GPIO3_C2]", -+ "pin-33 [GPIO3_C3]", "pin-07 [GPIO3_C4]", "", -+ "", "", -+ /* GPIO3_D0 - D7 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = -+ /* GPIO4_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO4_B0 - B7 */ -+ "", "", "pin-27 [GPIO4_B2]", -+ "pin-28 [GPIO4_B3]", "", "", "", "", -+ /* GPIO4_C0 - C7 */ -+ "", "", "pin-23 [GPIO4_C2]", -+ "pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]", -+ "pin-24 [GPIO4_C6]", "", -+ /* GPIO4_D0 - D7 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ - &gpu { - mali-supply = <&vdd_gpu_npu>; - status = "okay"; diff --git a/target/linux/rockchip/patches-6.6/010-04-v6.11-arm64-dts-rockchip-Add-Radxa-ROCK-3B.patch b/target/linux/rockchip/patches-6.6/010-04-v6.11-arm64-dts-rockchip-Add-Radxa-ROCK-3B.patch deleted file mode 100644 index 4b2897f524..0000000000 --- a/target/linux/rockchip/patches-6.6/010-04-v6.11-arm64-dts-rockchip-Add-Radxa-ROCK-3B.patch +++ /dev/null @@ -1,815 +0,0 @@ -From 846ef7748fa9124c8eea76e2d5e833fa69b3ef7c Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Thu, 27 Jun 2024 21:17:31 +0000 -Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 3B - -The Radxa ROCK 3B is a single-board computer based on the Pico-ITX form -factor (100mm x 75mm). Two versions of the ROCK 3B exists, a community -version based on the RK3568 SoC and an industrial version based on the -RK3568J SoC. - -Add initial support for eMMC, SD-card, Ethernet, HDMI, PCIe and USB. - -Signed-off-by: Jonas Karlman -Link: https://lore.kernel.org/r/20240627211737.1985549-3-jonas@kwiboo.se -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3568-rock-3b.dts | 781 ++++++++++++++++++ - 2 files changed, 782 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-od - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts -@@ -0,0 +1,781 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include -+#include "rk3568.dtsi" -+ -+/ { -+ model = "Radxa ROCK 3B"; -+ compatible = "radxa,rock-3b", "rockchip,rk3568"; -+ -+ aliases { -+ ethernet0 = &gmac0; -+ ethernet1 = &gmac1; -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc0; -+ mmc2 = &sdmmc2; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm3_ir>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led>; -+ -+ led-0 { -+ color = ; -+ default-state = "on"; -+ function = LED_FUNCTION_HEARTBEAT; -+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ /* pi6c pcie clock generator */ -+ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_pwren_h>; -+ regulator-name = "vcc3v3_pi6c_03"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <10000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_sys: regulator-3v3-vcc-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_sys2: regulator-3v3-vcc-sys2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys2"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_sys: regulator-5v0-vcc-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc5v0_usb_host: regulator-5v0-vcc-usb-host { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb_host_pwren_h>; -+ regulator-name = "vcc5v0_usb_host"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb_otg_pwren_h>; -+ regulator-name = "vcc5v0_usb_otg"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk809 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_reg_on_h>; -+ post-power-on-delay-ms = <100>; -+ power-off-delay-us = <5000000>; -+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; -+ }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,name = "Analog RK809"; -+ simple-audio-card,mclk-fs = <256>; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s1_8ch>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&rk809>; -+ }; -+ }; -+}; -+ -+&combphy0 { -+ status = "okay"; -+}; -+ -+&combphy1 { -+ status = "okay"; -+}; -+ -+&combphy2 { -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&gmac0 { -+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; -+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; -+ clock_in_out = "input"; -+ phy-handle = <&rgmii_phy0>; -+ phy-mode = "rgmii-id"; -+ phy-supply = <&vcc_3v3>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac0_miim -+ &gmac0_tx_bus2 -+ &gmac0_rx_bus2 -+ &gmac0_rgmii_clk -+ &gmac0_rgmii_bus -+ &gmac0_clkinout>; -+ status = "okay"; -+}; -+ -+&gmac1 { -+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; -+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; -+ clock_in_out = "input"; -+ phy-handle = <&rgmii_phy1>; -+ phy-mode = "rgmii-id"; -+ phy-supply = <&vcc_3v3>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1m1_miim -+ &gmac1m1_tx_bus2 -+ &gmac1m1_rx_bus2 -+ &gmac1m1_rgmii_clk -+ &gmac1m1_rgmii_bus -+ &gmac1m1_clkinout>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ avdd-0v9-supply = <&vdda0v9_image>; -+ avdd-1v8-supply = <&vcca1v8_image>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; -+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; -+ #clock-cells = <1>; -+ clocks = <&cru I2S1_MCLKOUT_TX>; -+ clock-names = "mclk"; -+ clock-output-names = "rk809-clkout1", "rk809-clkout2"; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; -+ #sound-dai-cells = <0>; -+ system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c5 { -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ #clock-cells = <0>; -+ clock-output-names = "rtcic_32kout"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rtcic_int_l>; -+ wakeup-source; -+ }; -+}; -+ -+&i2s0_8ch { -+ status = "okay"; -+}; -+ -+&i2s1_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s1m0_sclktx -+ &i2s1m0_lrcktx -+ &i2s1m0_sdi0 -+ &i2s1m0_sdo0>; -+ rockchip,trcm-sync-tx-only; -+ status = "okay"; -+}; -+ -+&mdio0 { -+ rgmii_phy0: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ reset-assert-us = <20000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&mdio1 { -+ rgmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ reset-assert-us = <20000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie20m1_pins>; -+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_sys2>; -+ status = "okay"; -+}; -+ -+&pcie30phy { -+ status = "okay"; -+}; -+ -+&pcie3x2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie30x2m1_pins>; -+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ bluetooth { -+ bt_reg_on_h: bt-reg-on-h { -+ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_host_h: bt-wake-host-h { -+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ host_wake_bt_h: host-wake-bt-h { -+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ ir-receiver { -+ pwm3_ir: pwm3-ir { -+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ leds { -+ led: led { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie { -+ pcie_pwren_h: pcie-pwren-h { -+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie20 { -+ pcie20m1_pins: pcie20m1-pins { -+ rockchip,pins = -+ <2 RK_PD0 4 &pcfg_pull_none>, -+ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, -+ <2 RK_PD1 4 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie30x2 { -+ pcie30x2m1_pins: pcie30x2m1-pins { -+ rockchip,pins = -+ <2 RK_PD4 4 &pcfg_pull_none>, -+ <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>, -+ <2 RK_PD5 4 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rtc { -+ rtcic_int_l: rtcic-int-l { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb { -+ usb_host_pwren_h: usb-host-pwren-h { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ usb_otg_pwren_h: usb-otg-pwren-h { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ wifi { -+ wifi_reg_on_h: wifi-reg-on-h { -+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_wake_host_h: wifi-wake-host-h { -+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcc3v3_pmu>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio2-supply = <&vcc_1v8>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcc_1v8>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc_1v8>; -+ vccio7-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca_1v8>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ cap-mmc-highspeed; -+ max-frequency = <200000000>; -+ mmc-hs200-1_8v; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ vmmc-supply = <&vcc3v3_sd>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&sdmmc2 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v3_sys2>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "disabled"; -+}; -+ -+&sfc { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <104000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&uart8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; -+ uart-has-rtscts; -+ status = "disabled"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ extcon = <&usb2phy0>; -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy0_host { -+ phy-supply = <&vcc5v0_usb_host>; -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ phy-supply = <&vcc5v0_usb_otg>; -+ status = "okay"; -+}; -+ -+&usb2phy1 { -+ status = "okay"; -+}; -+ -+&usb2phy1_otg { -+ phy-supply = <&vcc5v0_usb_host>; -+ status = "okay"; -+}; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.6/011-01-v6.13-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R3S-board.patch b/target/linux/rockchip/patches-6.6/011-01-v6.13-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R3S-board.patch deleted file mode 100644 index 995393fa69..0000000000 --- a/target/linux/rockchip/patches-6.6/011-01-v6.13-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R3S-board.patch +++ /dev/null @@ -1,596 +0,0 @@ -From 50decd493c8394c52d04561fe4ede34df27a46ba Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Mon, 21 Oct 2024 01:39:46 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board - -The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps -Ethernet ports designed and developed by FriendlyElec for IoT -applications. - -Specification: -- Rockchip RK3566 -- 2GB LPDDR4X RAM -- optional 32GB eMMC module -- SD card slot -- 2x 1000 Base-T -- 3x LEDs (POWER, LAN, WAN) -- 2x Buttons (Reset, MaskROM) -- 1x USB 3.0 Port -- Type-C 5V 2A Power - -Signed-off-by: Tianling Shen -Link: https://lore.kernel.org/r/20241020173946.225960-2-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3566-nanopi-r3s.dts | 554 ++++++++++++++++++ - 2 files changed, 555 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -90,6 +90,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-so - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-nanopi-r3s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -@@ -0,0 +1,554 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd. -+ * -+ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2024 Tianling Shen -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include -+#include -+#include -+#include "rk3566.dtsi" -+ -+/ { -+ model = "FriendlyARM NanoPi R3S"; -+ compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566"; -+ -+ aliases { -+ ethernet0 = &gmac1; -+ mmc0 = &sdmmc0; -+ mmc1 = &sdhci; -+ }; -+ -+ chosen: chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&reset_button_pin>; -+ -+ button-reset { -+ label = "reset"; -+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <50>; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&power_led_pin>, <&lan_led_pin>, <&wan_led_pin>; -+ -+ power_led: led-0 { -+ color = ; -+ function = LED_FUNCTION_POWER; -+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ }; -+ -+ lan_led: led-1 { -+ color = ; -+ function = LED_FUNCTION_LAN; -+ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ wan_led: led-2 { -+ color = ; -+ function = LED_FUNCTION_WAN; -+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ vcc3v3_sys: regulator-vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_sys: regulator-vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vdd_usbc>; -+ }; -+ -+ vcc5v0_usb: regulator-vcc5v0_usb { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_host_en>; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vdd_usbc: regulator-vdd-usbc { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_usbc"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&combphy1 { -+ status = "okay"; -+}; -+ -+&combphy2 { -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&gmac1 { -+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; -+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; -+ assigned-clock-rates = <0>, <125000000>; -+ clock_in_out = "output"; -+ phy-mode = "rgmii-id"; -+ phy-handle = <&rgmii_phy1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1m0_miim -+ &gmac1m0_tx_bus2_level3 -+ &gmac1m0_rx_bus2 -+ &gmac1m0_rgmii_clk_level2 -+ &gmac1m0_rgmii_bus_level3>; -+ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ /* Reset time is 20ms, 100ms for rtl8211f */ -+ snps,reset-delays-us = <0 20000 100000>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ #clock-cells = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>; -+ system-power-controller; -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ wakeup-source; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <950000>; -+ regulator-max-microvolt = <950000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ clock-output-names = "hym8563"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ wakeup-source; -+ }; -+}; -+ -+&mdio1 { -+ rgmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ interrupt-parent = <&gpio4>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <ð_phy_reset_pin>; -+ }; -+}; -+ -+&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_reset_h>; -+ reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gpio-leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ power_led_pin: power-led-pin { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ gmac { -+ eth_phy_reset_pin: eth-phy-reset-pin { -+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ pcie { -+ pcie_reset_h: pcie-reset-h { -+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int: pmic-int { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rockchip-key { -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rtc { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb { -+ vcc5v0_usb_host_en: vcc5v0-usb-host-en { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ status = "okay"; -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcc3v3_pmu>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio2-supply = <&vcc_1v8>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcc_3v3>; -+ vccio5-supply = <&vcc_1v8>; -+ vccio6-supply = <&vcc_3v3>; -+ vccio7-supply = <&vcc_3v3>; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -+ status = "okay"; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ no-sdio; -+ no-mmc; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ sd-uhs-sdr50; -+ vmmc-supply = <&vcc3v3_sd>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy0_host { -+ phy-supply = <&vcc5v0_usb>; -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ extcon = <&usb2phy0>; -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ status = "okay"; -+}; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.6/011-02-v6.13-arm64-dts-rockchip-fix-model-name-for-FriendlyElec-NanoPi.patch b/target/linux/rockchip/patches-6.6/011-02-v6.13-arm64-dts-rockchip-fix-model-name-for-FriendlyElec-NanoPi.patch deleted file mode 100644 index f7dbaff7f0..0000000000 --- a/target/linux/rockchip/patches-6.6/011-02-v6.13-arm64-dts-rockchip-fix-model-name-for-FriendlyElec-NanoPi.patch +++ /dev/null @@ -1,38 +0,0 @@ -From b5bf84206a5c77528f9dd4cbca4e72caa063c102 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Wed, 23 Oct 2024 03:35:26 +0800 -Subject: [PATCH] arm64: dts: rockchip: fix model name for FriendlyElec NanoPi - R3S - -Use the marketing name for model name, this matches the dt-binding. -Also update the website url in copyright. - -Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") -Suggested-by: Jonas Karlman -Signed-off-by: Tianling Shen -Link: https://lore.kernel.org/r/20241022193537.1117919-2-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -@@ -3,7 +3,7 @@ - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - * - * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. -- * (http://www.friendlyarm.com) -+ * (http://www.friendlyelec.com) - * - * Copyright (c) 2024 Tianling Shen - */ -@@ -17,7 +17,7 @@ - #include "rk3566.dtsi" - - / { -- model = "FriendlyARM NanoPi R3S"; -+ model = "FriendlyElec NanoPi R3S"; - compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566"; - - aliases { diff --git a/target/linux/rockchip/patches-6.6/011-03-v1.13-arm64-dts-rockchip-replace-deprecated-snps-reset-props-fo.patch b/target/linux/rockchip/patches-6.6/011-03-v1.13-arm64-dts-rockchip-replace-deprecated-snps-reset-props-fo.patch deleted file mode 100644 index 2b7c092cab..0000000000 --- a/target/linux/rockchip/patches-6.6/011-03-v1.13-arm64-dts-rockchip-replace-deprecated-snps-reset-props-fo.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 82b2868937883b65732da498b26366d34db61510 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Wed, 23 Oct 2024 03:35:27 +0800 -Subject: [PATCH] arm64: dts: rockchip: replace deprecated snps,reset props for - NanoPi R3S - -Replace deprecated snps,reset props and move them to the PHY node. - -Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") -Suggested-by: Jonas Karlman -Signed-off-by: Tianling Shen -Link: https://lore.kernel.org/r/20241022193537.1117919-3-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 7 +++---- - 1 file changed, 3 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -@@ -149,10 +149,6 @@ - &gmac1m0_rx_bus2 - &gmac1m0_rgmii_clk_level2 - &gmac1m0_rgmii_bus_level3>; -- snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; -- snps,reset-active-low; -- /* Reset time is 20ms, 100ms for rtl8211f */ -- snps,reset-delays-us = <0 20000 100000>; - status = "okay"; - }; - -@@ -414,6 +410,9 @@ - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_reset_pin>; -+ reset-assert-us = <20000>; -+ reset-deassert-us = <100000>; -+ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; - diff --git a/target/linux/rockchip/patches-6.6/011-04-v6.13-arm64-dts-rockchip-sort-props-in-pmu_io_domains-node-for.patch b/target/linux/rockchip/patches-6.6/011-04-v6.13-arm64-dts-rockchip-sort-props-in-pmu_io_domains-node-for.patch deleted file mode 100644 index 6b09fc96a4..0000000000 --- a/target/linux/rockchip/patches-6.6/011-04-v6.13-arm64-dts-rockchip-sort-props-in-pmu_io_domains-node-for.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 17e150fdd983c7e59b9240e34a166285f3c3fb39 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Wed, 23 Oct 2024 03:35:28 +0800 -Subject: [PATCH] arm64: dts: rockchip: sort props in pmu_io_domains node for - NanoPi R3S - -The status prop is typically the last prop. - -Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") -Suggested-by: Jonas Karlman -Signed-off-by: Tianling Shen -Link: https://lore.kernel.org/r/20241022193537.1117919-4-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -@@ -476,7 +476,6 @@ - }; - - &pmu_io_domains { -- status = "okay"; - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; -@@ -486,6 +485,7 @@ - vccio5-supply = <&vcc_1v8>; - vccio6-supply = <&vcc_3v3>; - vccio7-supply = <&vcc_3v3>; -+ status = "okay"; - }; - - &sdhci { diff --git a/target/linux/rockchip/patches-6.6/011-05-v6.13-arm64-dts-rockchip-enable-eMMC-HS200-mode-for-NanoPi-R3S.patch b/target/linux/rockchip/patches-6.6/011-05-v6.13-arm64-dts-rockchip-enable-eMMC-HS200-mode-for-NanoPi-R3S.patch deleted file mode 100644 index bbe8ccfe69..0000000000 --- a/target/linux/rockchip/patches-6.6/011-05-v6.13-arm64-dts-rockchip-enable-eMMC-HS200-mode-for-NanoPi-R3S.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 1b5365034410f1ca21adadadd492b99bdf4f2c55 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Wed, 23 Oct 2024 03:35:29 +0800 -Subject: [PATCH] arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S - -It is required to boot from eMMC without additional patch in u-boot. - -Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") -Suggested-by: Jonas Karlman -Signed-off-by: Tianling Shen -Link: https://lore.kernel.org/r/20241022193537.1117919-5-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -@@ -491,6 +491,7 @@ - &sdhci { - bus-width = <8>; - max-frequency = <200000000>; -+ mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; diff --git a/target/linux/rockchip/patches-6.6/011-06-v6.13-arm64-dts-rockchip-reorder-mmc-aliases-for-NanoPi-R3S.patch b/target/linux/rockchip/patches-6.6/011-06-v6.13-arm64-dts-rockchip-reorder-mmc-aliases-for-NanoPi-R3S.patch deleted file mode 100644 index f262e251e2..0000000000 --- a/target/linux/rockchip/patches-6.6/011-06-v6.13-arm64-dts-rockchip-reorder-mmc-aliases-for-NanoPi-R3S.patch +++ /dev/null @@ -1,31 +0,0 @@ -From b7cd1115456d312f8c5e60c80fdc35fd35ea6eab Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Wed, 23 Oct 2024 03:35:30 +0800 -Subject: [PATCH] arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S - -Typically any non-removable storage (emmc) is listed before removable -storage (sd-card) options. Also U-Boot will try to override and use -mmc0=sdhci and mmc1=sdmmc0 for all rk356x boards. - -Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") -Suggested-by: Jonas Karlman -Signed-off-by: Tianling Shen -Link: https://lore.kernel.org/r/20241022193537.1117919-6-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -@@ -22,8 +22,8 @@ - - aliases { - ethernet0 = &gmac1; -- mmc0 = &sdmmc0; -- mmc1 = &sdhci; -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc0; - }; - - chosen: chosen { diff --git a/target/linux/rockchip/patches-6.6/011-07-v6.13-arm64-dts-rockchip-add-reset-names-for-combphy-on-rk3568.patch b/target/linux/rockchip/patches-6.6/011-07-v6.13-arm64-dts-rockchip-add-reset-names-for-combphy-on-rk3568.patch deleted file mode 100644 index 7a8f86a46f..0000000000 --- a/target/linux/rockchip/patches-6.6/011-07-v6.13-arm64-dts-rockchip-add-reset-names-for-combphy-on-rk3568.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 8b9c12757f919157752646faf3821abf2b7d2a64 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Fri, 22 Nov 2024 15:30:05 +0800 -Subject: [PATCH] arm64: dts: rockchip: add reset-names for combphy on rk3568 - -The reset-names of combphy are missing, add it. - -Signed-off-by: Chukun Pan -Fixes: fd3ac6e80497 ("dt-bindings: phy: rockchip: rk3588 has two reset lines") -Link: https://lore.kernel.org/r/20241122073006.99309-1-amadeus@jmu.edu.cn -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 1 + - arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 ++ - 2 files changed, 3 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -223,6 +223,7 @@ - assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_PIPEPHY0>; -+ reset-names = "phy"; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf0>; - #phy-cells = <1>; ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -1747,6 +1747,7 @@ - assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_PIPEPHY1>; -+ reset-names = "phy"; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf1>; - #phy-cells = <1>; -@@ -1763,6 +1764,7 @@ - assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_PIPEPHY2>; -+ reset-names = "phy"; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf2>; - #phy-cells = <1>; diff --git a/target/linux/rockchip/patches-6.6/011-08-v6.15-arm64-dts-rockchip-rk356x-Add-MSI-controller-node.patch b/target/linux/rockchip/patches-6.6/011-08-v6.15-arm64-dts-rockchip-rk356x-Add-MSI-controller-node.patch deleted file mode 100644 index a31e4595c4..0000000000 --- a/target/linux/rockchip/patches-6.6/011-08-v6.15-arm64-dts-rockchip-rk356x-Add-MSI-controller-node.patch +++ /dev/null @@ -1,51 +0,0 @@ -From f15be3d4a0a55db2b50f319c378a2d16ceb21f86 Mon Sep 17 00:00:00 2001 -From: Dmitry Osipenko -Date: Mon, 17 Feb 2025 01:16:33 +0300 -Subject: [PATCH] arm64: dts: rockchip: rk356x: Add MSI controller node - -Rockchip 356x SoC's GIC has two hardware integration issues that -affect MSI functionality of the GIC. Previously, both these GIC -issues were worked around by using MBI for MSI instead of ITS -because kernel GIC driver didn't have necessary quirks. - -First issue is about RK356x GIC not supporting programmable -shareability, while reporting it as supported in a GIC's feature -register. Rockchip assigned Erratum ID #3568001 for this issue. This -patch adds dma-noncoherent property to the GIC node, denoting that a SW -workaround is required for mitigating the issue. - -Second issue is about GIC AXI master interface addressing limited to -the first 4GB of physical address space. Rockchip assigned Erratum -ID #3568002 for this issue. - -Now that kernel supports quirks for both of the erratums, add -MSI controller node to RK356x device-tree. - -Signed-off-by: Dmitry Osipenko -Signed-off-by: Thomas Gleixner -Link: https://lore.kernel.org/all/20250216221634.364158-3-dmitry.osipenko@collabora.com ---- - arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -364,6 +364,18 @@ - mbi-alias = <0x0 0xfd410000>; - mbi-ranges = <296 24>; - msi-controller; -+ ranges; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ dma-noncoherent; -+ -+ its: msi-controller@fd440000 { -+ compatible = "arm,gic-v3-its"; -+ reg = <0x0 0xfd440000 0 0x20000>; -+ dma-noncoherent; -+ msi-controller; -+ #msi-cells = <1>; -+ }; - }; - - usb_host0_ehci: usb@fd800000 { diff --git a/target/linux/rockchip/patches-6.6/011-09-v6.15-arm64-dts-rockchip-rk356x-Move-PCIe-MSI-to-use-GIC.patch b/target/linux/rockchip/patches-6.6/011-09-v6.15-arm64-dts-rockchip-rk356x-Move-PCIe-MSI-to-use-GIC.patch deleted file mode 100644 index d1281332b4..0000000000 --- a/target/linux/rockchip/patches-6.6/011-09-v6.15-arm64-dts-rockchip-rk356x-Move-PCIe-MSI-to-use-GIC.patch +++ /dev/null @@ -1,28 +0,0 @@ -From b956c9de91757c9478e24fc9f6a57fd46f0a49f0 Mon Sep 17 00:00:00 2001 -From: Dmitry Osipenko -Date: Mon, 17 Feb 2025 01:16:34 +0300 -Subject: [PATCH] arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC - ITS instead of MBI - -Rockchip 356x device-tree now supports GIC ITS. Move PCIe controller's -MSI to use ITS instead of MBI. This removes extra CPU overhead of handling -PCIe MBIs by letting GIC's ITS to serve the PCIe MSIs. - -Signed-off-by: Dmitry Osipenko -Signed-off-by: Thomas Gleixner -Link: https://lore.kernel.org/all/20250216221634.364158-4-dmitry.osipenko@collabora.com ---- - arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -1043,7 +1043,7 @@ - num-ib-windows = <6>; - num-ob-windows = <2>; - max-link-speed = <2>; -- msi-map = <0x0 &gic 0x0 0x1000>; -+ msi-map = <0x0 &its 0x0 0x1000>; - num-lanes = <1>; - phys = <&combphy2 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; diff --git a/target/linux/rockchip/patches-6.6/011-10-v6.16-arm64-dts-rockchip-Move-rk3568-PCIe3-MSI-to-use-GIC-.patch b/target/linux/rockchip/patches-6.6/011-10-v6.16-arm64-dts-rockchip-Move-rk3568-PCIe3-MSI-to-use-GIC-.patch deleted file mode 100644 index c5bbaed492..0000000000 --- a/target/linux/rockchip/patches-6.6/011-10-v6.16-arm64-dts-rockchip-Move-rk3568-PCIe3-MSI-to-use-GIC-.patch +++ /dev/null @@ -1,54 +0,0 @@ -From fbea35a661ed100cee2f3bab8015fb0155508106 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sat, 8 Mar 2025 17:30:08 +0800 -Subject: [PATCH] arm64: dts: rockchip: Move rk3568 PCIe3 MSI to use GIC ITS - -Following commit b956c9de9175 ("arm64: dts: rockchip: rk356x: Move -PCIe MSI to use GIC ITS instead of MBI"), change the PCIe3 controller's -MSI on rk3568 to use ITS, so that all MSI-X can work properly. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20250308093008.568437-2-amadeus@jmu.edu.cn -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -64,7 +64,7 @@ - compatible = "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; -- bus-range = <0x0 0xf>; -+ bus-range = <0x10 0x1f>; - clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, - <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, - <&cru CLK_PCIE30X1_AUX_NDFT>; -@@ -87,7 +87,7 @@ - num-ib-windows = <6>; - num-ob-windows = <2>; - max-link-speed = <3>; -- msi-map = <0x0 &gic 0x1000 0x1000>; -+ msi-map = <0x1000 &its 0x1000 0x1000>; - num-lanes = <1>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; -@@ -117,7 +117,7 @@ - compatible = "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; -- bus-range = <0x0 0xf>; -+ bus-range = <0x20 0x2f>; - clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, - <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, - <&cru CLK_PCIE30X2_AUX_NDFT>; -@@ -140,7 +140,7 @@ - num-ib-windows = <6>; - num-ob-windows = <2>; - max-link-speed = <3>; -- msi-map = <0x0 &gic 0x2000 0x1000>; -+ msi-map = <0x2000 &its 0x2000 0x1000>; - num-lanes = <2>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; diff --git a/target/linux/rockchip/patches-6.6/020-01-v6.13-irqchip-gic-v3-its-Share-ITS-tables-with-a-non-trust.patch b/target/linux/rockchip/patches-6.6/020-01-v6.13-irqchip-gic-v3-its-Share-ITS-tables-with-a-non-trust.patch deleted file mode 100644 index 92e9bf6c86..0000000000 --- a/target/linux/rockchip/patches-6.6/020-01-v6.13-irqchip-gic-v3-its-Share-ITS-tables-with-a-non-trust.patch +++ /dev/null @@ -1,337 +0,0 @@ -From b08e2f42e86b5848add254da45b56fc672e2bced Mon Sep 17 00:00:00 2001 -From: Steven Price -Date: Wed, 2 Oct 2024 15:16:29 +0100 -Subject: [PATCH] irqchip/gic-v3-its: Share ITS tables with a non-trusted - hypervisor - -Within a realm guest the ITS is emulated by the host. This means the -allocations must have been made available to the host by a call to -set_memory_decrypted(). Introduce an allocation function which performs -this extra call. - -For the ITT use a custom genpool-based allocator that calls -set_memory_decrypted() for each page allocated, but then suballocates the -size needed for each ITT. Note that there is no mechanism implemented to -return pages from the genpool, but it is unlikely that the peak number of -devices will be much larger than the normal level - so this isn't expected -to be an issue. - -Co-developed-by: Suzuki K Poulose -Signed-off-by: Suzuki K Poulose -Signed-off-by: Steven Price -Signed-off-by: Thomas Gleixner -Tested-by: Will Deacon -Reviewed-by: Marc Zyngier -Link: https://lore.kernel.org/all/20241002141630.433502-2-steven.price@arm.com ---- - drivers/irqchip/irq-gic-v3-its.c | 138 +++++++++++++++++++++++++------ - 1 file changed, 115 insertions(+), 23 deletions(-) - ---- a/drivers/irqchip/irq-gic-v3-its.c -+++ b/drivers/irqchip/irq-gic-v3-its.c -@@ -12,12 +12,14 @@ - #include - #include - #include -+#include - #include - #include - #include - #include - #include - #include -+#include - #include - #include - #include -@@ -27,6 +29,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -163,6 +166,7 @@ struct its_device { - struct its_node *its; - struct event_lpi_map event_map; - void *itt; -+ u32 itt_sz; - u32 nr_ites; - u32 device_id; - bool shared; -@@ -198,6 +202,87 @@ static DEFINE_IDA(its_vpeid_ida); - #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) - #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) - -+static struct page *its_alloc_pages_node(int node, gfp_t gfp, -+ unsigned int order) -+{ -+ struct page *page; -+ int ret = 0; -+ -+ page = alloc_pages_node(node, gfp, order); -+ -+ if (!page) -+ return NULL; -+ -+ ret = set_memory_decrypted((unsigned long)page_address(page), -+ 1 << order); -+ /* -+ * If set_memory_decrypted() fails then we don't know what state the -+ * page is in, so we can't free it. Instead we leak it. -+ * set_memory_decrypted() will already have WARNed. -+ */ -+ if (ret) -+ return NULL; -+ -+ return page; -+} -+ -+static struct page *its_alloc_pages(gfp_t gfp, unsigned int order) -+{ -+ return its_alloc_pages_node(NUMA_NO_NODE, gfp, order); -+} -+ -+static void its_free_pages(void *addr, unsigned int order) -+{ -+ /* -+ * If the memory cannot be encrypted again then we must leak the pages. -+ * set_memory_encrypted() will already have WARNed. -+ */ -+ if (set_memory_encrypted((unsigned long)addr, 1 << order)) -+ return; -+ free_pages((unsigned long)addr, order); -+} -+ -+static struct gen_pool *itt_pool; -+ -+static void *itt_alloc_pool(int node, int size) -+{ -+ unsigned long addr; -+ struct page *page; -+ -+ if (size >= PAGE_SIZE) { -+ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, get_order(size)); -+ -+ return page ? page_address(page) : NULL; -+ } -+ -+ do { -+ addr = gen_pool_alloc(itt_pool, size); -+ if (addr) -+ break; -+ -+ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 1); -+ if (!page) -+ break; -+ -+ gen_pool_add(itt_pool, (unsigned long)page_address(page), PAGE_SIZE, node); -+ } while (!addr); -+ -+ return (void *)addr; -+} -+ -+static void itt_free_pool(void *addr, int size) -+{ -+ if (!addr) -+ return; -+ -+ if (size >= PAGE_SIZE) { -+ its_free_pages(addr, get_order(size)); -+ return; -+ } -+ -+ gen_pool_free(itt_pool, (unsigned long)addr, size); -+} -+ - /* - * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we - * always have vSGIs mapped. -@@ -2192,7 +2277,8 @@ static struct page *its_allocate_prop_ta - { - struct page *prop_page; - -- prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); -+ prop_page = its_alloc_pages(gfp_flags, -+ get_order(LPI_PROPBASE_SZ)); - if (!prop_page) - return NULL; - -@@ -2203,8 +2289,7 @@ static struct page *its_allocate_prop_ta - - static void its_free_prop_table(struct page *prop_page) - { -- free_pages((unsigned long)page_address(prop_page), -- get_order(LPI_PROPBASE_SZ)); -+ its_free_pages(page_address(prop_page), get_order(LPI_PROPBASE_SZ)); - } - - static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size) -@@ -2326,7 +2411,7 @@ static int its_setup_baser(struct its_no - order = get_order(GITS_BASER_PAGES_MAX * psz); - } - -- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); -+ page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); - if (!page) - return -ENOMEM; - -@@ -2339,7 +2424,7 @@ static int its_setup_baser(struct its_no - /* 52bit PA is supported only when PageSize=64K */ - if (psz != SZ_64K) { - pr_err("ITS: no 52bit PA support when psz=%d\n", psz); -- free_pages((unsigned long)base, order); -+ its_free_pages(base, order); - return -ENXIO; - } - -@@ -2395,7 +2480,7 @@ retry_baser: - pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", - &its->phys_base, its_base_type_string[type], - val, tmp); -- free_pages((unsigned long)base, order); -+ its_free_pages(base, order); - return -ENXIO; - } - -@@ -2534,8 +2619,7 @@ static void its_free_tables(struct its_n - - for (i = 0; i < GITS_BASER_NR_REGS; i++) { - if (its->tables[i].base) { -- free_pages((unsigned long)its->tables[i].base, -- its->tables[i].order); -+ its_free_pages(its->tables[i].base, its->tables[i].order); - its->tables[i].base = NULL; - } - } -@@ -2801,7 +2885,7 @@ static bool allocate_vpe_l2_table(int cp - - /* Allocate memory for 2nd level table */ - if (!table[idx]) { -- page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz)); -+ page = its_alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz)); - if (!page) - return false; - -@@ -2920,7 +3004,7 @@ static int allocate_vpe_l1_table(void) - - pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n", - np, npg, psz, epp, esz); -- page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE)); -+ page = its_alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE)); - if (!page) - return -ENOMEM; - -@@ -2966,8 +3050,7 @@ static struct page *its_allocate_pending - { - struct page *pend_page; - -- pend_page = alloc_pages(gfp_flags | __GFP_ZERO, -- get_order(LPI_PENDBASE_SZ)); -+ pend_page = its_alloc_pages(gfp_flags | __GFP_ZERO, get_order(LPI_PENDBASE_SZ)); - if (!pend_page) - return NULL; - -@@ -2979,7 +3062,7 @@ static struct page *its_allocate_pending - - static void its_free_pending_table(struct page *pt) - { -- free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ)); -+ its_free_pages(page_address(pt), get_order(LPI_PENDBASE_SZ)); - } - - /* -@@ -3314,8 +3397,8 @@ static bool its_alloc_table_entry(struct - - /* Allocate memory for 2nd level table */ - if (!table[idx]) { -- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, -- get_order(baser->psz)); -+ page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, -+ get_order(baser->psz)); - if (!page) - return false; - -@@ -3410,7 +3493,6 @@ static struct its_device *its_create_dev - if (WARN_ON(!is_power_of_2(nvecs))) - nvecs = roundup_pow_of_two(nvecs); - -- dev = kzalloc(sizeof(*dev), GFP_KERNEL); - /* - * Even if the device wants a single LPI, the ITT must be - * sized as a power of two (and you need at least one bit...). -@@ -3418,7 +3500,11 @@ static struct its_device *its_create_dev - nr_ites = max(2, nvecs); - sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); - sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; -- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); -+ -+ itt = itt_alloc_pool(its->numa_node, sz); -+ -+ dev = kzalloc(sizeof(*dev), GFP_KERNEL); -+ - if (alloc_lpis) { - lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); - if (lpi_map) -@@ -3430,9 +3516,9 @@ static struct its_device *its_create_dev - lpi_base = 0; - } - -- if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { -+ if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { - kfree(dev); -- kfree(itt); -+ itt_free_pool(itt, sz); - bitmap_free(lpi_map); - kfree(col_map); - return NULL; -@@ -3442,6 +3528,7 @@ static struct its_device *its_create_dev - - dev->its = its; - dev->itt = itt; -+ dev->itt_sz = sz; - dev->nr_ites = nr_ites; - dev->event_map.lpi_map = lpi_map; - dev->event_map.col_map = col_map; -@@ -3469,7 +3556,7 @@ static void its_free_device(struct its_d - list_del(&its_dev->entry); - raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); - kfree(its_dev->event_map.col_map); -- kfree(its_dev->itt); -+ itt_free_pool(its_dev->itt, its_dev->itt_sz); - kfree(its_dev); - } - -@@ -5112,8 +5199,9 @@ static int __init its_probe_one(struct i - } - } - -- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, -- get_order(ITS_CMD_QUEUE_SZ)); -+ page = its_alloc_pages_node(its->numa_node, -+ GFP_KERNEL | __GFP_ZERO, -+ get_order(ITS_CMD_QUEUE_SZ)); - if (!page) { - err = -ENOMEM; - goto out_unmap_sgir; -@@ -5177,7 +5265,7 @@ static int __init its_probe_one(struct i - out_free_tables: - its_free_tables(its); - out_free_cmd: -- free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); -+ its_free_pages(its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); - out_unmap_sgir: - if (its->sgir_base) - iounmap(its->sgir_base); -@@ -5659,6 +5747,10 @@ int __init its_init(struct fwnode_handle - bool has_v4_1 = false; - int err; - -+ itt_pool = gen_pool_create(get_order(ITS_ITT_ALIGN), -1); -+ if (!itt_pool) -+ return -ENOMEM; -+ - gic_rdists = rdists; - - its_parent = parent_domain; diff --git a/target/linux/rockchip/patches-6.6/020-02-v6.13-irqchip-gic-v3-its-Fix-over-allocation-in-itt_alloc.patch b/target/linux/rockchip/patches-6.6/020-02-v6.13-irqchip-gic-v3-its-Fix-over-allocation-in-itt_alloc.patch deleted file mode 100644 index a716cbee7d..0000000000 --- a/target/linux/rockchip/patches-6.6/020-02-v6.13-irqchip-gic-v3-its-Fix-over-allocation-in-itt_alloc.patch +++ /dev/null @@ -1,33 +0,0 @@ -From bc88d44bd7e45b992cf8c2c2ffbc7bb3e24db4a7 Mon Sep 17 00:00:00 2001 -From: Steven Price -Date: Mon, 21 Oct 2024 11:41:05 +0100 -Subject: [PATCH] irqchip/gic-v3-its: Fix over allocation in - itt_alloc_pool() - -itt_alloc_pool() calls its_alloc_pages_node() to allocate an individual -page to add to the pool (for allocations -Signed-off-by: Steven Price -Signed-off-by: Thomas Gleixner -Link: https://lore.kernel.org/all/1f6e19c4-1fb9-43ab-a8a2-a465c9cff84b@arm.com -Closes: https://lore.kernel.org/r/ed65312a-245c-4fa5-91ad-5d620cab7c6b%40nvidia.com ---- - drivers/irqchip/irq-gic-v3-its.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/irqchip/irq-gic-v3-its.c -+++ b/drivers/irqchip/irq-gic-v3-its.c -@@ -260,7 +260,7 @@ static void *itt_alloc_pool(int node, in - if (addr) - break; - -- page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 1); -+ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 0); - if (!page) - break; - diff --git a/target/linux/rockchip/patches-6.6/020-03-v6.15-irqchip-gic-v3-Add-Rockchip-3568002-erratum-workaround.patch b/target/linux/rockchip/patches-6.6/020-03-v6.15-irqchip-gic-v3-Add-Rockchip-3568002-erratum-workaround.patch deleted file mode 100644 index 9c9e643ff9..0000000000 --- a/target/linux/rockchip/patches-6.6/020-03-v6.15-irqchip-gic-v3-Add-Rockchip-3568002-erratum-workaround.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 2d81e1bb625238d40a686ed909ff3e1abab7556a Mon Sep 17 00:00:00 2001 -From: Dmitry Osipenko -Date: Mon, 17 Feb 2025 01:16:32 +0300 -Subject: [PATCH] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround - -Rockchip RK3566/RK3568 GIC600 integration has DDR addressing -limited to the first 32bit of physical address space. Rockchip -assigned Erratum ID #3568002 for this issue. Add driver quirk for -this Rockchip GIC Erratum. - -Note, that the 0x0201743b GIC600 ID is not Rockchip-specific and is -common for many ARM GICv3 implementations. Hence, there is an extra -of_machine_is_compatible() check. - -Signed-off-by: Dmitry Osipenko -Signed-off-by: Thomas Gleixner -Acked-by: Marc Zyngier -Link: https://lore.kernel.org/all/20250216221634.364158-2-dmitry.osipenko@collabora.com ---- - Documentation/arch/arm64/silicon-errata.rst | 2 ++ - arch/arm64/Kconfig | 9 ++++++++ - drivers/irqchip/irq-gic-v3-its.c | 23 ++++++++++++++++++++- - 3 files changed, 33 insertions(+), 1 deletion(-) - ---- a/Documentation/arch/arm64/silicon-errata.rst -+++ b/Documentation/arch/arm64/silicon-errata.rst -@@ -270,6 +270,8 @@ stable kernels. - +----------------+-----------------+-----------------+-----------------------------+ - | Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 | - +----------------+-----------------+-----------------+-----------------------------+ -+| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_3568002 | -++----------------+-----------------+-----------------+-----------------------------+ - - +----------------+-----------------+-----------------+-----------------------------+ - | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 | ---- a/arch/arm64/Kconfig -+++ b/arch/arm64/Kconfig -@@ -1267,6 +1267,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM - - If unsure, say Y. - -+config ROCKCHIP_ERRATUM_3568002 -+ bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" -+ default y -+ help -+ The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI -+ addressing limited to the first 32bit of physical address space. -+ -+ If unsure, say Y. -+ - config ROCKCHIP_ERRATUM_3588001 - bool "Rockchip 3588001: GIC600 can not support shareability attributes" - default y ---- a/drivers/irqchip/irq-gic-v3-its.c -+++ b/drivers/irqchip/irq-gic-v3-its.c -@@ -202,13 +202,15 @@ static DEFINE_IDA(its_vpeid_ida); - #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) - #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) - -+static gfp_t gfp_flags_quirk; -+ - static struct page *its_alloc_pages_node(int node, gfp_t gfp, - unsigned int order) - { - struct page *page; - int ret = 0; - -- page = alloc_pages_node(node, gfp, order); -+ page = alloc_pages_node(node, gfp | gfp_flags_quirk, order); - - if (!page) - return NULL; -@@ -4851,6 +4853,17 @@ static bool its_set_non_coherent(void *d - return true; - } - -+static bool __maybe_unused its_enable_rk3568002(void *data) -+{ -+ if (!of_machine_is_compatible("rockchip,rk3566") && -+ !of_machine_is_compatible("rockchip,rk3568")) -+ return false; -+ -+ gfp_flags_quirk |= GFP_DMA32; -+ -+ return true; -+} -+ - static const struct gic_quirk its_quirks[] = { - #ifdef CONFIG_CAVIUM_ERRATUM_22375 - { -@@ -4910,6 +4923,14 @@ static const struct gic_quirk its_quirks - .property = "dma-noncoherent", - .init = its_set_non_coherent, - }, -+#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002 -+ { -+ .desc = "ITS: Rockchip erratum RK3568002", -+ .iidr = 0x0201743b, -+ .mask = 0xffffffff, -+ .init = its_enable_rk3568002, -+ }, -+#endif - { - } - }; diff --git a/target/linux/rockchip/patches-6.6/030-01-v6.9-clk-rockchip-rk3588-fix-CLK_NR_CLKS-usage.patch b/target/linux/rockchip/patches-6.6/030-01-v6.9-clk-rockchip-rk3588-fix-CLK_NR_CLKS-usage.patch deleted file mode 100644 index 6becaf6e86..0000000000 --- a/target/linux/rockchip/patches-6.6/030-01-v6.9-clk-rockchip-rk3588-fix-CLK_NR_CLKS-usage.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 2dc66a5ab2c6fb532fbb16107ee7efcb0effbfa5 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Fri, 26 Jan 2024 19:18:22 +0100 -Subject: [PATCH] clk: rockchip: rk3588: fix CLK_NR_CLKS usage - -CLK_NR_CLKS is not part of the DT bindings and needs to be removed -from it, just like it recently happened for other platforms. This -takes care of it by introducing a new function identifying the -maximum used clock ID at runtime. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240126182919.48402-2-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3588.c | 5 ++++- - drivers/clk/rockchip/clk.c | 17 +++++++++++++++++ - drivers/clk/rockchip/clk.h | 2 ++ - 3 files changed, 23 insertions(+), 1 deletion(-) - ---- a/drivers/clk/rockchip/clk-rk3588.c -+++ b/drivers/clk/rockchip/clk-rk3588.c -@@ -2458,15 +2458,18 @@ static struct rockchip_clk_branch rk3588 - static void __init rk3588_clk_init(struct device_node *np) - { - struct rockchip_clk_provider *ctx; -+ unsigned long clk_nr_clks; - void __iomem *reg_base; - -+ clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches, -+ ARRAY_SIZE(rk3588_clk_branches)) + 1; - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("%s: could not map cru region\n", __func__); - return; - } - -- ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); -+ ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); - if (IS_ERR(ctx)) { - pr_err("%s: rockchip clk init failed\n", __func__); - iounmap(reg_base); ---- a/drivers/clk/rockchip/clk.c -+++ b/drivers/clk/rockchip/clk.c -@@ -429,6 +429,23 @@ void rockchip_clk_register_plls(struct r - } - EXPORT_SYMBOL_GPL(rockchip_clk_register_plls); - -+unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, -+ unsigned int nr_clk) -+{ -+ unsigned long max = 0; -+ unsigned int idx; -+ -+ for (idx = 0; idx < nr_clk; idx++, list++) { -+ if (list->id > max) -+ max = list->id; -+ if (list->child && list->child->id > max) -+ max = list->id; -+ } -+ -+ return max; -+} -+EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id); -+ - void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, - struct rockchip_clk_branch *list, - unsigned int nr_clk) ---- a/drivers/clk/rockchip/clk.h -+++ b/drivers/clk/rockchip/clk.h -@@ -973,6 +973,8 @@ struct rockchip_clk_provider *rockchip_c - void __iomem *base, unsigned long nr_clks); - void rockchip_clk_of_add_provider(struct device_node *np, - struct rockchip_clk_provider *ctx); -+unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, -+ unsigned int nr_clk); - void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, - struct rockchip_clk_branch *list, - unsigned int nr_clk); diff --git a/target/linux/rockchip/patches-6.6/030-02-v6.9-dt-bindings-clock-rk3588-drop-CLK_NR_CLKS.patch b/target/linux/rockchip/patches-6.6/030-02-v6.9-dt-bindings-clock-rk3588-drop-CLK_NR_CLKS.patch deleted file mode 100644 index c8117f08c5..0000000000 --- a/target/linux/rockchip/patches-6.6/030-02-v6.9-dt-bindings-clock-rk3588-drop-CLK_NR_CLKS.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 11a29dc2e41ead2be78cfa9d532edf924b461acc Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Fri, 26 Jan 2024 19:18:23 +0100 -Subject: [PATCH] dt-bindings: clock: rk3588: drop CLK_NR_CLKS - -CLK_NR_CLKS should not be part of the binding. Let's drop it, since -the kernel code no longer uses it either. - -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240126182919.48402-3-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - include/dt-bindings/clock/rockchip,rk3588-cru.h | 2 -- - 1 file changed, 2 deletions(-) - ---- a/include/dt-bindings/clock/rockchip,rk3588-cru.h -+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h -@@ -734,8 +734,6 @@ - #define PCLK_AV1_PRE 719 - #define HCLK_SDIO_PRE 720 - --#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1) -- - /* scmi-clocks indices */ - - #define SCMI_CLK_CPUL 0 diff --git a/target/linux/rockchip/patches-6.6/030-03-v6.9-dt-bindings-clock-rk3588-add-missing-PCLK_VO1GRF.patch b/target/linux/rockchip/patches-6.6/030-03-v6.9-dt-bindings-clock-rk3588-add-missing-PCLK_VO1GRF.patch deleted file mode 100644 index b960bc6197..0000000000 --- a/target/linux/rockchip/patches-6.6/030-03-v6.9-dt-bindings-clock-rk3588-add-missing-PCLK_VO1GRF.patch +++ /dev/null @@ -1,26 +0,0 @@ -From c81798cf9dd2f324934585b2b52a0398caefb88e Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Fri, 26 Jan 2024 19:18:24 +0100 -Subject: [PATCH] dt-bindings: clock: rk3588: add missing PCLK_VO1GRF - -Add PCLK_VO1GRF to complement PCLK_VO0GRF. This will be needed -for HDMI support. - -Acked-by: Krzysztof Kozlowski -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240126182919.48402-4-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - include/dt-bindings/clock/rockchip,rk3588-cru.h | 1 + - 1 file changed, 1 insertion(+) - ---- a/include/dt-bindings/clock/rockchip,rk3588-cru.h -+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h -@@ -733,6 +733,7 @@ - #define ACLK_AV1_PRE 718 - #define PCLK_AV1_PRE 719 - #define HCLK_SDIO_PRE 720 -+#define PCLK_VO1GRF 721 - - /* scmi-clocks indices */ - diff --git a/target/linux/rockchip/patches-6.6/030-04-v6.9-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch b/target/linux/rockchip/patches-6.6/030-04-v6.9-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch deleted file mode 100644 index e12b73fb30..0000000000 --- a/target/linux/rockchip/patches-6.6/030-04-v6.9-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 326be62eaf2e89767b7b9223f88eaf3c041b98d2 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Fri, 26 Jan 2024 19:18:25 +0100 -Subject: [PATCH] clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf - -Currently pclk_vo1grf is not exposed, but it should be referenced -from the vo1_grf syscon, which needs it enabled. That syscon is -required for HDMI RX and TX functionality among other things. - -Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates -and need the VO's hclk enabled in addition to their parent clock. - -No Fixes tag has been added, since the logic requiring these clocks -is not yet upstream anyways. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240126182919.48402-5-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3588.c | 10 ++++------ - 1 file changed, 4 insertions(+), 6 deletions(-) - ---- a/drivers/clk/rockchip/clk-rk3588.c -+++ b/drivers/clk/rockchip/clk-rk3588.c -@@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588 - RK3588_CLKGATE_CON(56), 0, GFLAGS), - GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, - RK3588_CLKGATE_CON(56), 1, GFLAGS), -- GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED, -- RK3588_CLKGATE_CON(55), 10, GFLAGS), - COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0, - RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(56), 11, GFLAGS), -@@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588 - RK3588_CLKGATE_CON(60), 9, GFLAGS), - GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0, - RK3588_CLKGATE_CON(60), 10, GFLAGS), -- GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED, -- RK3588_CLKGATE_CON(59), 12, GFLAGS), - GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0, - RK3588_CLKGATE_CON(59), 14, GFLAGS), - GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0, -@@ -2447,12 +2443,14 @@ static struct rockchip_clk_branch rk3588 - GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), - GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), - GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), -- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), -+ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), - GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), -- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), -+ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), - GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), - GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), - GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), -+ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS), -+ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), - }; - - static void __init rk3588_clk_init(struct device_node *np) diff --git a/target/linux/rockchip/patches-6.6/030-05-v6.9-clk-rockchip-rk3588-fix-indent.patch b/target/linux/rockchip/patches-6.6/030-05-v6.9-clk-rockchip-rk3588-fix-indent.patch deleted file mode 100644 index 27aa28edd5..0000000000 --- a/target/linux/rockchip/patches-6.6/030-05-v6.9-clk-rockchip-rk3588-fix-indent.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 2a6e4710672242281347103b64e01693aa823a29 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Fri, 26 Jan 2024 19:18:26 +0100 -Subject: [PATCH] clk: rockchip: rk3588: fix indent - -pclk_mailbox2 is the only RK3588 clock indented with one tab instead of -two tabs. Let's fix this. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240126182919.48402-6-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3588.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/rockchip/clk-rk3588.c -+++ b/drivers/clk/rockchip/clk-rk3588.c -@@ -1004,7 +1004,7 @@ static struct rockchip_clk_branch rk3588 - GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0, - RK3588_CLKGATE_CON(16), 12, GFLAGS), - GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0, -- RK3588_CLKGATE_CON(16), 13, GFLAGS), -+ RK3588_CLKGATE_CON(16), 13, GFLAGS), - GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL, - RK3588_CLKGATE_CON(19), 3, GFLAGS), - GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, diff --git a/target/linux/rockchip/patches-6.6/030-06-v6.9-clk-rockchip-rk3588-use-linked-clock-ID-for-GATE_LINK.patch b/target/linux/rockchip/patches-6.6/030-06-v6.9-clk-rockchip-rk3588-use-linked-clock-ID-for-GATE_LINK.patch deleted file mode 100644 index 949041fb9f..0000000000 --- a/target/linux/rockchip/patches-6.6/030-06-v6.9-clk-rockchip-rk3588-use-linked-clock-ID-for-GATE_LINK.patch +++ /dev/null @@ -1,78 +0,0 @@ -From dae3e57000fb2d6f491e3ee2956f5918326d6b72 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Fri, 26 Jan 2024 19:18:27 +0100 -Subject: [PATCH] clk: rockchip: rk3588: use linked clock ID for GATE_LINK - -In preparation for properly supporting GATE_LINK switch the unused -linked clock argument from the clock's name to its ID. This allows -easy and fast lookup of the 'struct clk'. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240126182919.48402-7-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3588.c | 46 +++++++++++++++---------------- - 1 file changed, 23 insertions(+), 23 deletions(-) - ---- a/drivers/clk/rockchip/clk-rk3588.c -+++ b/drivers/clk/rockchip/clk-rk3588.c -@@ -29,7 +29,7 @@ - * power, but avoids leaking implementation details into DT or hanging the - * system. - */ --#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \ -+#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \ - GATE(_id, cname, pname, f, o, b, gf) - #define RK3588_LINKED_CLK CLK_IS_CRITICAL - -@@ -2429,28 +2429,28 @@ static struct rockchip_clk_branch rk3588 - GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, - RK3588_CLKGATE_CON(68), 2, GFLAGS), - -- GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), -- GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), -- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), -- GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), -- GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), -- GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), -- GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), -- GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), -- GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), -- GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), -- GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), -- GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), -- GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), -- GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), -- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), -- GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), -- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), -- GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), -- GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), -- GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), -- GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS), -- GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), -+ GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), -+ GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), -+ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), -+ GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), -+ GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), -+ GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), -+ GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), -+ GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), -+ GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), -+ GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), -+ GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), -+ GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), -+ GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), -+ GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), -+ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), -+ GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), -+ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), -+ GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), -+ GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), -+ GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), -+ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS), -+ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), - }; - - static void __init rk3588_clk_init(struct device_node *np) diff --git a/target/linux/rockchip/patches-6.6/030-07-v6.10-dt-bindings-reset-Define-reset-id-used-for-HDMI-Receiver.patch b/target/linux/rockchip/patches-6.6/030-07-v6.10-dt-bindings-reset-Define-reset-id-used-for-HDMI-Receiver.patch deleted file mode 100644 index 0b9082f9b6..0000000000 --- a/target/linux/rockchip/patches-6.6/030-07-v6.10-dt-bindings-reset-Define-reset-id-used-for-HDMI-Receiver.patch +++ /dev/null @@ -1,24 +0,0 @@ -From ca151fd56b5736a7adbdba5675b9d87d70f20b23 Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Thu, 28 Mar 2024 04:20:52 +0530 -Subject: [PATCH] dt-bindings: reset: Define reset id used for HDMI Receiver - -Add reset id used for HDMI Receiver in RK3588 SoCs - -Acked-by: Rob Herring -Signed-off-by: Shreeya Patel -Link: https://lore.kernel.org/r/20240327225057.672304-2-shreeya.patel@collabora.com -Signed-off-by: Heiko Stuebner ---- - include/dt-bindings/reset/rockchip,rk3588-cru.h | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/include/dt-bindings/reset/rockchip,rk3588-cru.h -+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h -@@ -751,4 +751,6 @@ - #define SRST_P_TRNG_CHK 658 - #define SRST_TRNG_S 659 - -+#define SRST_A_HDMIRX_BIU 660 -+ - #endif diff --git a/target/linux/rockchip/patches-6.6/030-08-v6.10-clk-rockchip-rk3588-Add-reset-line-for-HDMI-Receiver.patch b/target/linux/rockchip/patches-6.6/030-08-v6.10-clk-rockchip-rk3588-Add-reset-line-for-HDMI-Receiver.patch deleted file mode 100644 index 6aa9c058a3..0000000000 --- a/target/linux/rockchip/patches-6.6/030-08-v6.10-clk-rockchip-rk3588-Add-reset-line-for-HDMI-Receiver.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 7af67019cd78d028ef377df689ac103d51905518 Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Thu, 28 Mar 2024 04:20:53 +0530 -Subject: [PATCH] clk: rockchip: rk3588: Add reset line for HDMI Receiver - -Export hdmirx_biu reset line required by the Synopsys -DesignWare HDMIRX Controller. - -Signed-off-by: Shreeya Patel -Link: https://lore.kernel.org/r/20240327225057.672304-3-shreeya.patel@collabora.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/rst-rk3588.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/clk/rockchip/rst-rk3588.c -+++ b/drivers/clk/rockchip/rst-rk3588.c -@@ -577,6 +577,7 @@ static const int rk3588_register_offset[ - - /* SOFTRST_CON59 */ - RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6), -+ RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX_BIU, 59, 7), - RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8), - RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9), - RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10), diff --git a/target/linux/rockchip/patches-6.6/030-09-v6.12-clk-rockchip-Add-new-pll-type-pll_rk3588_ddr.patch b/target/linux/rockchip/patches-6.6/030-09-v6.12-clk-rockchip-Add-new-pll-type-pll_rk3588_ddr.patch deleted file mode 100644 index 0d68f687fa..0000000000 --- a/target/linux/rockchip/patches-6.6/030-09-v6.12-clk-rockchip-Add-new-pll-type-pll_rk3588_ddr.patch +++ /dev/null @@ -1,51 +0,0 @@ -From e781bffc296766b55dbd048890d558655031e8d1 Mon Sep 17 00:00:00 2001 -From: Elaine Zhang -Date: Wed, 28 Aug 2024 15:42:52 +0000 -Subject: [PATCH] clk: rockchip: Add new pll type pll_rk3588_ddr - -That PLL type is similar to the other rk3588 pll types but the actual -rate is twice the configured rate. -Therefore, the returned calculated rate must be multiplied by two. - -Signed-off-by: Elaine Zhang -Signed-off-by: Detlev Casanova -Acked-by: Dragan Simic -Link: https://lore.kernel.org/r/0102019199a76ec4-9d5846d4-d76a-4e69-a241-c88c2983d607-000000@eu-west-1.amazonses.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-pll.c | 6 +++++- - drivers/clk/rockchip/clk.h | 1 + - 2 files changed, 6 insertions(+), 1 deletion(-) - ---- a/drivers/clk/rockchip/clk-pll.c -+++ b/drivers/clk/rockchip/clk-pll.c -@@ -914,7 +914,10 @@ static unsigned long rockchip_rk3588_pll - } - rate64 = rate64 >> cur.s; - -- return (unsigned long)rate64; -+ if (pll->type == pll_rk3588_ddr) -+ return (unsigned long)rate64 * 2; -+ else -+ return (unsigned long)rate64; - } - - static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, -@@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(st - break; - case pll_rk3588: - case pll_rk3588_core: -+ case pll_rk3588_ddr: - if (!pll->rate_table) - init.ops = &rockchip_rk3588_pll_clk_norate_ops; - else ---- a/drivers/clk/rockchip/clk.h -+++ b/drivers/clk/rockchip/clk.h -@@ -287,6 +287,7 @@ enum rockchip_pll_type { - pll_rk3399, - pll_rk3588, - pll_rk3588_core, -+ pll_rk3588_ddr, - }; - - #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ diff --git a/target/linux/rockchip/patches-6.6/030-10-v6.12-clk-rockchip-rk3588-drop-unused-code.patch b/target/linux/rockchip/patches-6.6/030-10-v6.12-clk-rockchip-rk3588-drop-unused-code.patch deleted file mode 100644 index 0164bf26e5..0000000000 --- a/target/linux/rockchip/patches-6.6/030-10-v6.12-clk-rockchip-rk3588-drop-unused-code.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 2e7b3daa8cb1ebd17e6a7f417ef5e6553203035c Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 25 Mar 2024 20:33:32 +0100 -Subject: [PATCH] clk: rockchip: rk3588: drop unused code - -All clocks are registered early using CLK_OF_DECLARE(), which marks -the DT node as processed. For the processed DT node the probe routine -is never called. Thus this whole code is never executed. This could -be "fixed" by using CLK_OF_DECLARE_DRIVER, which avoids marking the -DT node as processed. But then the probe routine would re-register -all the clocks by calling rk3588_clk_init() again. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240325193609.237182-2-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3588.c | 40 ------------------------------- - 1 file changed, 40 deletions(-) - ---- a/drivers/clk/rockchip/clk-rk3588.c -+++ b/drivers/clk/rockchip/clk-rk3588.c -@@ -2502,43 +2502,3 @@ static void __init rk3588_clk_init(struc - } - - CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init); -- --struct clk_rk3588_inits { -- void (*inits)(struct device_node *np); --}; -- --static const struct clk_rk3588_inits clk_3588_cru_init = { -- .inits = rk3588_clk_init, --}; -- --static const struct of_device_id clk_rk3588_match_table[] = { -- { -- .compatible = "rockchip,rk3588-cru", -- .data = &clk_3588_cru_init, -- }, -- { } --}; -- --static int __init clk_rk3588_probe(struct platform_device *pdev) --{ -- const struct clk_rk3588_inits *init_data; -- struct device *dev = &pdev->dev; -- -- init_data = device_get_match_data(dev); -- if (!init_data) -- return -EINVAL; -- -- if (init_data->inits) -- init_data->inits(dev->of_node); -- -- return 0; --} -- --static struct platform_driver clk_rk3588_driver = { -- .driver = { -- .name = "clk-rk3588", -- .of_match_table = clk_rk3588_match_table, -- .suppress_bind_attrs = true, -- }, --}; --builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe); diff --git a/target/linux/rockchip/patches-6.6/030-11-v6.13-clk-rockchip-fix-finding-of-maximum-clock-ID.patch b/target/linux/rockchip/patches-6.6/030-11-v6.13-clk-rockchip-fix-finding-of-maximum-clock-ID.patch deleted file mode 100644 index 912c2c7778..0000000000 --- a/target/linux/rockchip/patches-6.6/030-11-v6.13-clk-rockchip-fix-finding-of-maximum-clock-ID.patch +++ /dev/null @@ -1,29 +0,0 @@ -From ad1081a0da2744141d12e94ff816ac91feb871ca Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 12 Sep 2024 13:32:05 +0000 -Subject: [PATCH] clk: rockchip: fix finding of maximum clock ID - -If an ID of a branch's child is greater than current maximum, we should -set new maximum to the child's ID, instead of its parent's. - -Fixes: 2dc66a5ab2c6 ("clk: rockchip: rk3588: fix CLK_NR_CLKS usage") -Signed-off-by: Yao Zi -Link: https://lore.kernel.org/r/20240912133204.29089-2-ziyao@disroot.org -Reviewed-by: Sebastian Reichel -Reviewed-by: Heiko Stuebner -Signed-off-by: Stephen Boyd ---- - drivers/clk/rockchip/clk.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/rockchip/clk.c -+++ b/drivers/clk/rockchip/clk.c -@@ -439,7 +439,7 @@ unsigned long rockchip_clk_find_max_clk_ - if (list->id > max) - max = list->id; - if (list->child && list->child->id > max) -- max = list->id; -+ max = list->child->id; - } - - return max; diff --git a/target/linux/rockchip/patches-6.6/030-12-v6.14-clk-rockchip-support-clocks-registered-late.patch b/target/linux/rockchip/patches-6.6/030-12-v6.14-clk-rockchip-support-clocks-registered-late.patch deleted file mode 100644 index b5f32b2de6..0000000000 --- a/target/linux/rockchip/patches-6.6/030-12-v6.14-clk-rockchip-support-clocks-registered-late.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 9e89f02da718bc912f7f253b58804d4a52efed30 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Wed, 11 Dec 2024 17:58:50 +0100 -Subject: [PATCH] clk: rockchip: support clocks registered late - -When some clocks are registered late and some clocks are registered -early we need to make sure the late registered clocks report probe defer -until the final registration has happened. - -But we do not want to keep reporting probe defer after the late -registration has happened. Also not all Rockchip SoCs have late -registered clocks and may not need to report probe defer at all. - -This restructures code a bit, so that there is a new function -rockchip_clk_init_early(), which should be used for initializing the CRU -structure on SoCs making use of late initialization in addition to the -early init. These platforms should call rockchip_clk_finalize() -once all clocks have been registered. - -Signed-off-by: Sebastian Reichel -[added EXPORT_SYMBOL_GPL(rockchip_clk_finalize) to match the early function] -Link: https://lore.kernel.org/r/20241211165957.94922-2-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk.c | 36 ++++++++++++++++++++++++++++++++---- - drivers/clk/rockchip/clk.h | 3 +++ - 2 files changed, 35 insertions(+), 4 deletions(-) - ---- a/drivers/clk/rockchip/clk.c -+++ b/drivers/clk/rockchip/clk.c -@@ -359,14 +359,17 @@ static struct clk *rockchip_clk_register - return hw->clk; - } - --struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, -- void __iomem *base, -- unsigned long nr_clks) -+static struct rockchip_clk_provider *rockchip_clk_init_base( -+ struct device_node *np, void __iomem *base, -+ unsigned long nr_clks, bool has_late_clocks) - { - struct rockchip_clk_provider *ctx; - struct clk **clk_table; -+ struct clk *default_clk_val; - int i; - -+ default_clk_val = ERR_PTR(has_late_clocks ? -EPROBE_DEFER : -ENOENT); -+ - ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL); - if (!ctx) - return ERR_PTR(-ENOMEM); -@@ -376,7 +379,7 @@ struct rockchip_clk_provider *rockchip_c - goto err_free; - - for (i = 0; i < nr_clks; ++i) -- clk_table[i] = ERR_PTR(-ENOENT); -+ clk_table[i] = default_clk_val; - - ctx->reg_base = base; - ctx->clk_data.clks = clk_table; -@@ -393,8 +396,33 @@ err_free: - kfree(ctx); - return ERR_PTR(-ENOMEM); - } -+ -+struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, -+ void __iomem *base, -+ unsigned long nr_clks) -+{ -+ return rockchip_clk_init_base(np, base, nr_clks, false); -+} - EXPORT_SYMBOL_GPL(rockchip_clk_init); - -+struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np, -+ void __iomem *base, -+ unsigned long nr_clks) -+{ -+ return rockchip_clk_init_base(np, base, nr_clks, true); -+} -+EXPORT_SYMBOL_GPL(rockchip_clk_init_early); -+ -+void rockchip_clk_finalize(struct rockchip_clk_provider *ctx) -+{ -+ int i; -+ -+ for (i = 0; i < ctx->clk_data.clk_num; ++i) -+ if (ctx->clk_data.clks[i] == ERR_PTR(-EPROBE_DEFER)) -+ ctx->clk_data.clks[i] = ERR_PTR(-ENOENT); -+} -+EXPORT_SYMBOL_GPL(rockchip_clk_finalize); -+ - void rockchip_clk_of_add_provider(struct device_node *np, - struct rockchip_clk_provider *ctx) - { ---- a/drivers/clk/rockchip/clk.h -+++ b/drivers/clk/rockchip/clk.h -@@ -972,6 +972,9 @@ struct rockchip_clk_branch { - - struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, - void __iomem *base, unsigned long nr_clks); -+struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np, -+ void __iomem *base, unsigned long nr_clks); -+void rockchip_clk_finalize(struct rockchip_clk_provider *ctx); - void rockchip_clk_of_add_provider(struct device_node *np, - struct rockchip_clk_provider *ctx); - unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, diff --git a/target/linux/rockchip/patches-6.6/030-13-v6.14-clk-rockchip-rk3588-register-GATE_LINK-later.patch b/target/linux/rockchip/patches-6.6/030-13-v6.14-clk-rockchip-rk3588-register-GATE_LINK-later.patch deleted file mode 100644 index 5e47d89a8f..0000000000 --- a/target/linux/rockchip/patches-6.6/030-13-v6.14-clk-rockchip-rk3588-register-GATE_LINK-later.patch +++ /dev/null @@ -1,150 +0,0 @@ -From 33af96244a66f855baa43d424844bb437c79c30c Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Wed, 11 Dec 2024 17:58:51 +0100 -Subject: [PATCH] clk: rockchip: rk3588: register GATE_LINK later - -The proper GATE_LINK implementation will use runtime PM to handle the -linked gate clocks, which requires device context. Currently all clocks -are registered early via CLK_OF_DECLARE, which is before the kernel -knows about devices. - -Moving the full clocks registration to the probe routine does not work, -since the clocks needed for timers must be registered early. - -To work around this issue, most of the clock tree is registered early, -but GATE_LINK clocks are handled in the probe routine. Since the resets -are not needed early either, they have also been moved to the probe -routine. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20241211165957.94922-3-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3588.c | 66 +++++++++++++++++++++++++++---- - 1 file changed, 58 insertions(+), 8 deletions(-) - ---- a/drivers/clk/rockchip/clk-rk3588.c -+++ b/drivers/clk/rockchip/clk-rk3588.c -@@ -266,6 +266,8 @@ static struct rockchip_pll_rate_table rk - }, \ - } - -+static struct rockchip_clk_provider *early_ctx; -+ - static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = { - RK3588_CPUB01CLK_RATE(2496000000, 1), - RK3588_CPUB01CLK_RATE(2400000000, 1), -@@ -694,7 +696,7 @@ static struct rockchip_pll_clock rk3588_ - RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), - }; - --static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { -+static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { - /* - * CRU Clock-Architecture - */ -@@ -2428,7 +2430,9 @@ static struct rockchip_clk_branch rk3588 - RK3588_CLKGATE_CON(68), 5, GFLAGS), - GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, - RK3588_CLKGATE_CON(68), 2, GFLAGS), -+}; - -+static struct rockchip_clk_branch rk3588_clk_branches[] = { - GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), - GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), - GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), -@@ -2453,26 +2457,31 @@ static struct rockchip_clk_branch rk3588 - GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), - }; - --static void __init rk3588_clk_init(struct device_node *np) -+static void __init rk3588_clk_early_init(struct device_node *np) - { - struct rockchip_clk_provider *ctx; -- unsigned long clk_nr_clks; -+ unsigned long clk_nr_clks, max_clk_id1, max_clk_id2; - void __iomem *reg_base; - -- clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches, -- ARRAY_SIZE(rk3588_clk_branches)) + 1; -+ max_clk_id1 = rockchip_clk_find_max_clk_id(rk3588_clk_branches, -+ ARRAY_SIZE(rk3588_clk_branches)); -+ max_clk_id2 = rockchip_clk_find_max_clk_id(rk3588_early_clk_branches, -+ ARRAY_SIZE(rk3588_early_clk_branches)); -+ clk_nr_clks = max(max_clk_id1, max_clk_id2) + 1; -+ - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("%s: could not map cru region\n", __func__); - return; - } - -- ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); -+ ctx = rockchip_clk_init_early(np, reg_base, clk_nr_clks); - if (IS_ERR(ctx)) { - pr_err("%s: rockchip clk init failed\n", __func__); - iounmap(reg_base); - return; - } -+ early_ctx = ctx; - - rockchip_clk_register_plls(ctx, rk3588_pll_clks, - ARRAY_SIZE(rk3588_pll_clks), -@@ -2491,14 +2500,55 @@ static void __init rk3588_clk_init(struc - &rk3588_cpub1clk_data, rk3588_cpub1clk_rates, - ARRAY_SIZE(rk3588_cpub1clk_rates)); - -+ rockchip_clk_register_branches(ctx, rk3588_early_clk_branches, -+ ARRAY_SIZE(rk3588_early_clk_branches)); -+ -+ rockchip_clk_of_add_provider(np, ctx); -+} -+CLK_OF_DECLARE_DRIVER(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_early_init); -+ -+static int clk_rk3588_probe(struct platform_device *pdev) -+{ -+ struct rockchip_clk_provider *ctx = early_ctx; -+ struct device *dev = &pdev->dev; -+ struct device_node *np = dev->of_node; -+ - rockchip_clk_register_branches(ctx, rk3588_clk_branches, - ARRAY_SIZE(rk3588_clk_branches)); - -- rk3588_rst_init(np, reg_base); -+ rockchip_clk_finalize(ctx); - -+ rk3588_rst_init(np, ctx->reg_base); - rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL); - -+ /* -+ * Re-add clock provider, so that the newly added clocks are also -+ * re-parented and get their defaults configured. -+ */ -+ of_clk_del_provider(np); - rockchip_clk_of_add_provider(np, ctx); -+ -+ return 0; - } - --CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init); -+static const struct of_device_id clk_rk3588_match_table[] = { -+ { -+ .compatible = "rockchip,rk3588-cru", -+ }, -+ { } -+}; -+ -+static struct platform_driver clk_rk3588_driver = { -+ .probe = clk_rk3588_probe, -+ .driver = { -+ .name = "clk-rk3588", -+ .of_match_table = clk_rk3588_match_table, -+ .suppress_bind_attrs = true, -+ }, -+}; -+ -+static int __init rockchip_clk_rk3588_drv_register(void) -+{ -+ return platform_driver_register(&clk_rk3588_driver); -+} -+core_initcall(rockchip_clk_rk3588_drv_register); diff --git a/target/linux/rockchip/patches-6.6/030-14-v6.14-clk-rockchip-expose-rockchip_clk_set_lookup.patch b/target/linux/rockchip/patches-6.6/030-14-v6.14-clk-rockchip-expose-rockchip_clk_set_lookup.patch deleted file mode 100644 index 8711733f51..0000000000 --- a/target/linux/rockchip/patches-6.6/030-14-v6.14-clk-rockchip-expose-rockchip_clk_set_lookup.patch +++ /dev/null @@ -1,90 +0,0 @@ -From fe0fb6675fa48cade97d8bcd46226479c4a704df Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Wed, 11 Dec 2024 17:58:52 +0100 -Subject: [PATCH] clk: rockchip: expose rockchip_clk_set_lookup - -Move rockchip_clk_add_lookup to clk.h, so that it can be used -by sub-devices with their own driver. These might also have to -do a lookup, so rename the function to rockchip_clk_set_lookup -and add a matching rockchip_clk_get_lookup. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20241211165957.94922-4-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk.c | 14 ++++---------- - drivers/clk/rockchip/clk.h | 12 ++++++++++++ - 2 files changed, 16 insertions(+), 10 deletions(-) - ---- a/drivers/clk/rockchip/clk.c -+++ b/drivers/clk/rockchip/clk.c -@@ -197,12 +197,6 @@ static void rockchip_fractional_approxim - clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n); - } - --static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, -- struct clk *clk, unsigned int id) --{ -- ctx->clk_data.clks[id] = clk; --} -- - static struct clk *rockchip_clk_register_frac_branch( - struct rockchip_clk_provider *ctx, const char *name, - const char *const *parent_names, u8 num_parents, -@@ -292,7 +286,7 @@ static struct clk *rockchip_clk_register - return mux_clk; - } - -- rockchip_clk_add_lookup(ctx, mux_clk, child->id); -+ rockchip_clk_set_lookup(ctx, mux_clk, child->id); - - /* notifier on the fraction divider to catch rate changes */ - if (frac->mux_frac_idx >= 0) { -@@ -452,7 +446,7 @@ void rockchip_clk_register_plls(struct r - continue; - } - -- rockchip_clk_add_lookup(ctx, clk, list->id); -+ rockchip_clk_set_lookup(ctx, clk, list->id); - } - } - EXPORT_SYMBOL_GPL(rockchip_clk_register_plls); -@@ -614,7 +608,7 @@ void rockchip_clk_register_branches(stru - continue; - } - -- rockchip_clk_add_lookup(ctx, clk, list->id); -+ rockchip_clk_set_lookup(ctx, clk, list->id); - } - } - EXPORT_SYMBOL_GPL(rockchip_clk_register_branches); -@@ -638,7 +632,7 @@ void rockchip_clk_register_armclk(struct - return; - } - -- rockchip_clk_add_lookup(ctx, clk, lookup_id); -+ rockchip_clk_set_lookup(ctx, clk, lookup_id); - } - EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk); - ---- a/drivers/clk/rockchip/clk.h -+++ b/drivers/clk/rockchip/clk.h -@@ -970,6 +970,18 @@ struct rockchip_clk_branch { - #define SGRF_GATE(_id, cname, pname) \ - FACTOR(_id, cname, pname, 0, 1, 1) - -+static inline struct clk *rockchip_clk_get_lookup(struct rockchip_clk_provider *ctx, -+ unsigned int id) -+{ -+ return ctx->clk_data.clks[id]; -+} -+ -+static inline void rockchip_clk_set_lookup(struct rockchip_clk_provider *ctx, -+ struct clk *clk, unsigned int id) -+{ -+ ctx->clk_data.clks[id] = clk; -+} -+ - struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, - void __iomem *base, unsigned long nr_clks); - struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np, diff --git a/target/linux/rockchip/patches-6.6/030-15-v6.14-clk-rockchip-implement-linked-gate-clock-support.patch b/target/linux/rockchip/patches-6.6/030-15-v6.14-clk-rockchip-implement-linked-gate-clock-support.patch deleted file mode 100644 index 6e8da4c82c..0000000000 --- a/target/linux/rockchip/patches-6.6/030-15-v6.14-clk-rockchip-implement-linked-gate-clock-support.patch +++ /dev/null @@ -1,314 +0,0 @@ -From c62fa612cfa66ab58ab215e5afc95c43c613b513 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Wed, 11 Dec 2024 17:58:53 +0100 -Subject: [PATCH] clk: rockchip: implement linked gate clock support - -Recent Rockchip SoCs have a new hardware block called Native Interface -Unit (NIU), which gates clocks to devices behind them. These clock -gates will only have a running output clock when all of the following -conditions are met: - -1. the parent clock is enabled -2. the enable bit is set correctly -3. the linked clock is enabled - -To handle them this code registers them as a normal gate type clock, -which takes care of condition 1 + 2. The linked clock is handled by -using runtime PM clocks. Handling it via runtime PM requires setting -up a struct device for each of these clocks with a driver attached -to use the correct runtime PM operations. Thus the complete handling -of these clocks has been moved into its own driver. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20241211165957.94922-5-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/Makefile | 1 + - drivers/clk/rockchip/clk-rk3588.c | 23 +-------- - drivers/clk/rockchip/clk.c | 52 +++++++++++++++++++ - drivers/clk/rockchip/clk.h | 25 +++++++++ - drivers/clk/rockchip/gate-link.c | 85 +++++++++++++++++++++++++++++++ - 5 files changed, 165 insertions(+), 21 deletions(-) - create mode 100644 drivers/clk/rockchip/gate-link.c - ---- a/drivers/clk/rockchip/Makefile -+++ b/drivers/clk/rockchip/Makefile -@@ -13,6 +13,7 @@ clk-rockchip-y += clk-inverter.o - clk-rockchip-y += clk-mmc-phase.o - clk-rockchip-y += clk-muxgrf.o - clk-rockchip-y += clk-ddr.o -+clk-rockchip-y += gate-link.o - clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o - - obj-$(CONFIG_CLK_PX30) += clk-px30.o ---- a/drivers/clk/rockchip/clk-rk3588.c -+++ b/drivers/clk/rockchip/clk-rk3588.c -@@ -12,25 +12,6 @@ - #include - #include "clk.h" - --/* -- * Recent Rockchip SoCs have a new hardware block called Native Interface -- * Unit (NIU), which gates clocks to devices behind them. These effectively -- * need two parent clocks. -- * -- * Downstream enables the linked clock via runtime PM whenever the gate is -- * enabled. This implementation uses separate clock nodes for each of the -- * linked gate clocks, which leaks parts of the clock tree into DT. -- * -- * The GATE_LINK macro instead takes the second parent via 'linkname', but -- * ignores the information. Once the clock framework is ready to handle it, the -- * information should be passed on here. But since these clocks are required to -- * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked -- * clocks critical until a better solution is available. This will waste some -- * power, but avoids leaking implementation details into DT or hanging the -- * system. -- */ --#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \ -- GATE(_id, cname, pname, f, o, b, gf) - #define RK3588_LINKED_CLK CLK_IS_CRITICAL - - -@@ -2513,8 +2494,8 @@ static int clk_rk3588_probe(struct platf - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - -- rockchip_clk_register_branches(ctx, rk3588_clk_branches, -- ARRAY_SIZE(rk3588_clk_branches)); -+ rockchip_clk_register_late_branches(dev, ctx, rk3588_clk_branches, -+ ARRAY_SIZE(rk3588_clk_branches)); - - rockchip_clk_finalize(ctx); - ---- a/drivers/clk/rockchip/clk.c -+++ b/drivers/clk/rockchip/clk.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -468,6 +469,29 @@ unsigned long rockchip_clk_find_max_clk_ - } - EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id); - -+static struct platform_device *rockchip_clk_register_gate_link( -+ struct device *parent_dev, -+ struct rockchip_clk_provider *ctx, -+ struct rockchip_clk_branch *clkbr) -+{ -+ struct rockchip_gate_link_platdata gate_link_pdata = { -+ .ctx = ctx, -+ .clkbr = clkbr, -+ }; -+ -+ struct platform_device_info pdevinfo = { -+ .parent = parent_dev, -+ .name = "rockchip-gate-link-clk", -+ .id = clkbr->id, -+ .fwnode = dev_fwnode(parent_dev), -+ .of_node_reused = true, -+ .data = &gate_link_pdata, -+ .size_data = sizeof(gate_link_pdata), -+ }; -+ -+ return platform_device_register_full(&pdevinfo); -+} -+ - void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, - struct rockchip_clk_branch *list, - unsigned int nr_clk) -@@ -593,6 +617,9 @@ void rockchip_clk_register_branches(stru - list->div_width, list->div_flags, - ctx->reg_base, &ctx->lock); - break; -+ case branch_linked_gate: -+ /* must be registered late, fall-through for error message */ -+ break; - } - - /* none of the cases above matched */ -@@ -613,6 +640,31 @@ void rockchip_clk_register_branches(stru - } - EXPORT_SYMBOL_GPL(rockchip_clk_register_branches); - -+void rockchip_clk_register_late_branches(struct device *dev, -+ struct rockchip_clk_provider *ctx, -+ struct rockchip_clk_branch *list, -+ unsigned int nr_clk) -+{ -+ unsigned int idx; -+ -+ for (idx = 0; idx < nr_clk; idx++, list++) { -+ struct platform_device *pdev = NULL; -+ -+ switch (list->branch_type) { -+ case branch_linked_gate: -+ pdev = rockchip_clk_register_gate_link(dev, ctx, list); -+ break; -+ default: -+ dev_err(dev, "unknown clock type %d\n", list->branch_type); -+ break; -+ } -+ -+ if (!pdev) -+ dev_err(dev, "failed to register device for clock %s\n", list->name); -+ } -+} -+EXPORT_SYMBOL_GPL(rockchip_clk_register_late_branches); -+ - void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, - unsigned int lookup_id, - const char *name, const char *const *parent_names, ---- a/drivers/clk/rockchip/clk.h -+++ b/drivers/clk/rockchip/clk.h -@@ -518,6 +518,7 @@ enum rockchip_clk_branch_type { - branch_divider, - branch_fraction_divider, - branch_gate, -+ branch_linked_gate, - branch_mmc, - branch_inverter, - branch_factor, -@@ -545,6 +546,7 @@ struct rockchip_clk_branch { - int gate_offset; - u8 gate_shift; - u8 gate_flags; -+ unsigned int linked_clk_id; - struct rockchip_clk_branch *child; - }; - -@@ -843,6 +845,20 @@ struct rockchip_clk_branch { - .gate_flags = gf, \ - } - -+#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \ -+ { \ -+ .id = _id, \ -+ .branch_type = branch_linked_gate, \ -+ .name = cname, \ -+ .parent_names = (const char *[]){ pname }, \ -+ .linked_clk_id = linkedclk, \ -+ .num_parents = 1, \ -+ .flags = f, \ -+ .gate_offset = o, \ -+ .gate_shift = b, \ -+ .gate_flags = gf, \ -+ } -+ - #define MMC(_id, cname, pname, offset, shift) \ - { \ - .id = _id, \ -@@ -982,6 +998,11 @@ static inline void rockchip_clk_set_look - ctx->clk_data.clks[id] = clk; - } - -+struct rockchip_gate_link_platdata { -+ struct rockchip_clk_provider *ctx; -+ struct rockchip_clk_branch *clkbr; -+}; -+ - struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, - void __iomem *base, unsigned long nr_clks); - struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np, -@@ -994,6 +1015,10 @@ unsigned long rockchip_clk_find_max_clk_ - void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, - struct rockchip_clk_branch *list, - unsigned int nr_clk); -+void rockchip_clk_register_late_branches(struct device *dev, -+ struct rockchip_clk_provider *ctx, -+ struct rockchip_clk_branch *list, -+ unsigned int nr_clk); - void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, - struct rockchip_pll_clock *pll_list, - unsigned int nr_pll, int grf_lock_offset); ---- /dev/null -+++ b/drivers/clk/rockchip/gate-link.c -@@ -0,0 +1,85 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Copyright (c) 2024 Collabora Ltd. -+ * Author: Sebastian Reichel -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk.h" -+ -+static int rk_clk_gate_link_register(struct device *dev, -+ struct rockchip_clk_provider *ctx, -+ struct rockchip_clk_branch *clkbr) -+{ -+ unsigned long flags = clkbr->flags | CLK_SET_RATE_PARENT; -+ struct clk *clk; -+ -+ clk = clk_register_gate(dev, clkbr->name, clkbr->parent_names[0], -+ flags, ctx->reg_base + clkbr->gate_offset, -+ clkbr->gate_shift, clkbr->gate_flags, -+ &ctx->lock); -+ -+ if (IS_ERR(clk)) -+ return PTR_ERR(clk); -+ -+ rockchip_clk_set_lookup(ctx, clk, clkbr->id); -+ return 0; -+} -+ -+static int rk_clk_gate_link_probe(struct platform_device *pdev) -+{ -+ struct rockchip_gate_link_platdata *pdata; -+ struct device *dev = &pdev->dev; -+ struct clk *linked_clk; -+ int ret; -+ -+ pdata = dev_get_platdata(dev); -+ if (!pdata) -+ return dev_err_probe(dev, -ENODEV, "missing platform data"); -+ -+ ret = devm_pm_runtime_enable(dev); -+ if (ret) -+ return ret; -+ -+ ret = devm_pm_clk_create(dev); -+ if (ret) -+ return ret; -+ -+ linked_clk = rockchip_clk_get_lookup(pdata->ctx, pdata->clkbr->linked_clk_id); -+ ret = pm_clk_add_clk(dev, linked_clk); -+ if (ret) -+ return ret; -+ -+ ret = rk_clk_gate_link_register(dev, pdata->ctx, pdata->clkbr); -+ if (ret) -+ goto err; -+ -+ return 0; -+ -+err: -+ pm_clk_remove_clk(dev, linked_clk); -+ return ret; -+} -+ -+static const struct dev_pm_ops rk_clk_gate_link_pm_ops = { -+ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) -+}; -+ -+static struct platform_driver rk_clk_gate_link_driver = { -+ .probe = rk_clk_gate_link_probe, -+ .driver = { -+ .name = "rockchip-gate-link-clk", -+ .pm = &rk_clk_gate_link_pm_ops, -+ .suppress_bind_attrs = true, -+ }, -+}; -+ -+static int __init rk_clk_gate_link_drv_register(void) -+{ -+ return platform_driver_register(&rk_clk_gate_link_driver); -+} -+core_initcall(rk_clk_gate_link_drv_register); diff --git a/target/linux/rockchip/patches-6.6/030-16-v6.14-clk-rockchip-rk3588-drop-RK3588_LINKED_CLK.patch b/target/linux/rockchip/patches-6.6/030-16-v6.14-clk-rockchip-rk3588-drop-RK3588_LINKED_CLK.patch deleted file mode 100644 index 0e487f9b48..0000000000 --- a/target/linux/rockchip/patches-6.6/030-16-v6.14-clk-rockchip-rk3588-drop-RK3588_LINKED_CLK.patch +++ /dev/null @@ -1,112 +0,0 @@ -From e9cdd7d6cf2a5031a968dc21f4f566101b602150 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Wed, 11 Dec 2024 17:58:54 +0100 -Subject: [PATCH] clk: rockchip: rk3588: drop RK3588_LINKED_CLK - -With the proper GATE_LINK support, we no longer need to keep the -linked clocks always on. Thus it's time to drop the CLK_IS_CRITICAL -flag for them. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20241211165957.94922-6-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3588.c | 27 ++++++++++++--------------- - 1 file changed, 12 insertions(+), 15 deletions(-) - ---- a/drivers/clk/rockchip/clk-rk3588.c -+++ b/drivers/clk/rockchip/clk-rk3588.c -@@ -12,9 +12,6 @@ - #include - #include "clk.h" - --#define RK3588_LINKED_CLK CLK_IS_CRITICAL -- -- - #define RK3588_GRF_SOC_STATUS0 0x600 - #define RK3588_PHYREF_ALT_GATE 0xc38 - -@@ -1439,7 +1436,7 @@ static struct rockchip_clk_branch rk3588 - COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, - RK3588_CLKGATE_CON(31), 0, GFLAGS), -- COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK, -+ COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, - RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, - RK3588_CLKGATE_CON(31), 1, GFLAGS), - GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, -@@ -1668,13 +1665,13 @@ static struct rockchip_clk_branch rk3588 - RK3588_CLKGATE_CON(42), 9, GFLAGS), - - /* vdpu */ -- COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK, -+ COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, - RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(44), 0, GFLAGS), - COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, - RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, - RK3588_CLKGATE_CON(44), 1, GFLAGS), -- COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, -+ COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, - RK3588_CLKGATE_CON(44), 2, GFLAGS), - COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, -@@ -1725,9 +1722,9 @@ static struct rockchip_clk_branch rk3588 - COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, - RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, - RK3588_CLKGATE_CON(47), 1, GFLAGS), -- GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK, -+ GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, - RK3588_CLKGATE_CON(47), 4, GFLAGS), -- GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK, -+ GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, - RK3588_CLKGATE_CON(47), 5, GFLAGS), - COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, - RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, -@@ -1737,10 +1734,10 @@ static struct rockchip_clk_branch rk3588 - RK3588_CLKGATE_CON(48), 6, GFLAGS), - - /* vi */ -- COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK, -+ COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, - RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(49), 0, GFLAGS), -- COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, -+ COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, - RK3588_CLKGATE_CON(49), 1, GFLAGS), - COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, -@@ -1910,10 +1907,10 @@ static struct rockchip_clk_branch rk3588 - COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, - RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(52), 0, GFLAGS), -- COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK, -+ COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, - RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, - RK3588_CLKGATE_CON(52), 1, GFLAGS), -- COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, -+ COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, - RK3588_CLKGATE_CON(52), 2, GFLAGS), - COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, -@@ -2416,7 +2413,7 @@ static struct rockchip_clk_branch rk3588 - static struct rockchip_clk_branch rk3588_clk_branches[] = { - GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), - GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), -- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), -+ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, 0, RK3588_CLKGATE_CON(31), 2, GFLAGS), - GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), - GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), - GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), -@@ -2428,9 +2425,9 @@ static struct rockchip_clk_branch rk3588 - GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), - GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), - GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), -- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), -+ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), - GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), -- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), -+ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), - GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), - GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), - GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), diff --git a/target/linux/rockchip/patches-6.6/030-17-v6.14-clk-rockchip-rk3588-make-refclko25m_ethX-critical.patch b/target/linux/rockchip/patches-6.6/030-17-v6.14-clk-rockchip-rk3588-make-refclko25m_ethX-critical.patch deleted file mode 100644 index 76425559ad..0000000000 --- a/target/linux/rockchip/patches-6.6/030-17-v6.14-clk-rockchip-rk3588-make-refclko25m_ethX-critical.patch +++ /dev/null @@ -1,54 +0,0 @@ -From cd8b5366636bdff0449b789fb2d33abb20804255 Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Sat, 14 Dec 2024 23:48:19 +0100 -Subject: [PATCH] clk: rockchip: rk3588: make refclko25m_ethX critical - -Ethernet phys normally need a 25MHz refclk input. On a lot of boards -this is done with a dedicated 25MHz crystal. But the rk3588 CRU also -provides a means for that via the refclko25m_ethX clock outputs that -can be used for that function. - -The mdio bus normally probes devices on the bus at runtime, by reading -specific phy registers. This requires the phy to be running and thus -also being supplied by its reference clock. - -While there exist the possibility and dt-binding to declare these -input clocks for each phy in the phy-dt-node, this is only relevant -_after_ the phy has been detected and during the drivers probe-run. - -This results in a chicken-and-egg-problem. The refclks in the CRU are -running on boot of course, but phy-probing can very well happen after -clk_disable_unused has run. - -In the past I tried to make clock-handling part of the mdio bus code [0] -but that wasn't very well received, due to it being specific to OF and -clocks with the consensus being that resources needed for detection -need to be enabled before. - -So to make probing ethernet phys using the internal refclks possible, -make those 2 clocks critical. - -[0] https://lore.kernel.org/netdev/13590315.F0gNSz5aLb@diego/T/ - -Signed-off-by: Heiko Stuebner -Link: https://lore.kernel.org/r/20241214224820.200665-1-heiko@sntech.de -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3588.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/clk/rockchip/clk-rk3588.c -+++ b/drivers/clk/rockchip/clk-rk3588.c -@@ -772,10 +772,10 @@ static struct rockchip_clk_branch rk3588 - COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0, - RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS, - RK3588_CLKGATE_CON(5), 3, GFLAGS), -- COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0, -+ COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS, - RK3588_CLKGATE_CON(5), 4, GFLAGS), -- COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0, -+ COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS, - RK3588_CLKGATE_CON(5), 5, GFLAGS), - COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, diff --git a/target/linux/rockchip/patches-6.6/030-18-v6.15-clk-rockchip-rk3568-mark-hclk_vi-as-critical.patch b/target/linux/rockchip/patches-6.6/030-18-v6.15-clk-rockchip-rk3568-mark-hclk_vi-as-critical.patch deleted file mode 100644 index ab474ab81d..0000000000 --- a/target/linux/rockchip/patches-6.6/030-18-v6.15-clk-rockchip-rk3568-mark-hclk_vi-as-critical.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 83dbeca33f7422f4a30c8a91a79d6c0dba4fb6af Mon Sep 17 00:00:00 2001 -From: Michael Riesch -Date: Mon, 10 Feb 2025 09:29:02 +0100 -Subject: [PATCH] clk: rockchip: rk3568: mark hclk_vi as critical - -The clock 'pclk_vi_niu' has a dependency on 'hclk_vi_niu' according -to the Technical Reference Manual section '2.8.6 NIU Clock gating -reliance'. However, this kind of dependency cannot be addressed -properly at the moment (until the support for linked clocks is -implemented for the RK3568). -As an intermediate solution, mark the hclk_vi as critical on the -Rockchip RK3568. - -Suggested-by: Nicolas Frattaroli -Signed-off-by: Michael Riesch -Link: https://lore.kernel.org/r/20250210-rk3568-hclk-vi-v1-1-9ade2626f638@wolfvision.net -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3568.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -1593,6 +1593,7 @@ static const char *const rk3568_cru_crit - "hclk_php", - "pclk_php", - "hclk_usb", -+ "hclk_vi", - "hclk_vo", - }; - diff --git a/target/linux/rockchip/patches-6.6/031-01-v6.7-mfd-rk8xx-Add-support-for-standard-system-power-controlle.patch b/target/linux/rockchip/patches-6.6/031-01-v6.7-mfd-rk8xx-Add-support-for-standard-system-power-controlle.patch deleted file mode 100644 index 94d998fe93..0000000000 --- a/target/linux/rockchip/patches-6.6/031-01-v6.7-mfd-rk8xx-Add-support-for-standard-system-power-controlle.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 2a46cd97f401a669d71b3d36b78bd6653f8424ee Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Thu, 19 Oct 2023 18:57:25 +0200 -Subject: [PATCH] mfd: rk8xx: Add support for standard system-power-controller - property - -DT property rockchip,system-power-controller is now deprecated. - -Signed-off-by: Ondrej Jirman -Reviewed-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20231019165732.3818789-4-megi@xff.cz -Signed-off-by: Lee Jones ---- - drivers/mfd/rk8xx-core.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/mfd/rk8xx-core.c -+++ b/drivers/mfd/rk8xx-core.c -@@ -677,7 +677,8 @@ int rk8xx_probe(struct device *dev, int - if (ret) - return dev_err_probe(dev, ret, "failed to add MFD devices\n"); - -- if (device_property_read_bool(dev, "rockchip,system-power-controller")) { -+ if (device_property_read_bool(dev, "rockchip,system-power-controller") || -+ device_property_read_bool(dev, "system-power-controller")) { - ret = devm_register_sys_off_handler(dev, - SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH, - &rk808_power_off, rk808); diff --git a/target/linux/rockchip/patches-6.6/031-02-v6.7-mfd-rk8xx-Add-support-for-RK806-power-off.patch b/target/linux/rockchip/patches-6.6/031-02-v6.7-mfd-rk8xx-Add-support-for-RK806-power-off.patch deleted file mode 100644 index 2ac0ff537e..0000000000 --- a/target/linux/rockchip/patches-6.6/031-02-v6.7-mfd-rk8xx-Add-support-for-RK806-power-off.patch +++ /dev/null @@ -1,29 +0,0 @@ -From b0227e7081404448a0059b8698fdffd2dec280d2 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Thu, 19 Oct 2023 18:57:26 +0200 -Subject: [PATCH] mfd: rk8xx: Add support for RK806 power off - -Use DEV_OFF bit to power off the RK806 PMIC, when system-power-controller -is used in DTS. - -Signed-off-by: Ondrej Jirman -Reviewed-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20231019165732.3818789-5-megi@xff.cz -Signed-off-by: Lee Jones ---- - drivers/mfd/rk8xx-core.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mfd/rk8xx-core.c -+++ b/drivers/mfd/rk8xx-core.c -@@ -517,6 +517,10 @@ static int rk808_power_off(struct sys_of - reg = RK805_DEV_CTRL_REG; - bit = DEV_OFF; - break; -+ case RK806_ID: -+ reg = RK806_SYS_CFG3; -+ bit = DEV_OFF; -+ break; - case RK808_ID: - reg = RK808_DEVCTRL_REG, - bit = DEV_OFF_RST; diff --git a/target/linux/rockchip/patches-6.6/032-01-v6.9-phy-rockchip-Add-Samsung-HDMI-eDP-Combo-PHY-driver.patch b/target/linux/rockchip/patches-6.6/032-01-v6.9-phy-rockchip-Add-Samsung-HDMI-eDP-Combo-PHY-driver.patch deleted file mode 100644 index 30e14cd8b7..0000000000 --- a/target/linux/rockchip/patches-6.6/032-01-v6.9-phy-rockchip-Add-Samsung-HDMI-eDP-Combo-PHY-driver.patch +++ /dev/null @@ -1,1084 +0,0 @@ -From 553be2830c5f33308483e8118de748a2c69fe593 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Wed, 14 Feb 2024 13:45:37 +0200 -Subject: [PATCH] phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver - -Add driver for the HDMI/eDP TX Combo PHY found on Rockchip RK3588 SoC. - -The PHY is based on a Samsung IP block and supports HDMI 2.1 TMDS, FRL -and eDP links. The maximum data rate is 12Gbps (FRL), while the minimum -is 250Mbps (TMDS). - -Only the TMDS link is currently supported. - -Co-developed-by: Algea Cao -Signed-off-by: Algea Cao -Tested-by: Heiko Stuebner -Signed-off-by: Cristian Ciocaltea -Link: https://lore.kernel.org/r/20240214-phy-hdptx-v4-2-e7974f46c1a7@collabora.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/Kconfig | 8 + - drivers/phy/rockchip/Makefile | 1 + - .../phy/rockchip/phy-rockchip-samsung-hdptx.c | 1028 +++++++++++++++++ - 3 files changed, 1037 insertions(+) - create mode 100644 drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c - ---- a/drivers/phy/rockchip/Kconfig -+++ b/drivers/phy/rockchip/Kconfig -@@ -83,6 +83,14 @@ config PHY_ROCKCHIP_PCIE - help - Enable this to support the Rockchip PCIe PHY. - -+config PHY_ROCKCHIP_SAMSUNG_HDPTX -+ tristate "Rockchip Samsung HDMI/eDP Combo PHY driver" -+ depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF -+ select GENERIC_PHY -+ help -+ Enable this to support the Rockchip HDMI/eDP Combo PHY -+ with Samsung IP block. -+ - config PHY_ROCKCHIP_SNPS_PCIE3 - tristate "Rockchip Snps PCIe3 PHY Driver" - depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST ---- a/drivers/phy/rockchip/Makefile -+++ b/drivers/phy/rockchip/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += - obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o - obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o - obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o -+obj-$(CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX) += phy-rockchip-samsung-hdptx.o - obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o - obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o - obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o ---- /dev/null -+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -@@ -0,0 +1,1028 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. -+ * Copyright (c) 2024 Collabora Ltd. -+ * -+ * Author: Algea Cao -+ * Author: Cristian Ciocaltea -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define GRF_HDPTX_CON0 0x00 -+#define HDPTX_I_PLL_EN BIT(7) -+#define HDPTX_I_BIAS_EN BIT(6) -+#define HDPTX_I_BGR_EN BIT(5) -+#define GRF_HDPTX_STATUS 0x80 -+#define HDPTX_O_PLL_LOCK_DONE BIT(3) -+#define HDPTX_O_PHY_CLK_RDY BIT(2) -+#define HDPTX_O_PHY_RDY BIT(1) -+#define HDPTX_O_SB_RDY BIT(0) -+ -+#define HDTPX_REG(_n, _min, _max) \ -+ ( \ -+ BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \ -+ BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \ -+ ((0x##_n) * 4) \ -+ ) -+ -+#define CMN_REG(n) HDTPX_REG(n, 0000, 00a7) -+#define SB_REG(n) HDTPX_REG(n, 0100, 0129) -+#define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229) -+#define LANE_REG(n) HDTPX_REG(n, 0300, 062d) -+ -+/* CMN_REG(0008) */ -+#define LCPLL_EN_MASK BIT(6) -+#define LCPLL_LCVCO_MODE_EN_MASK BIT(4) -+/* CMN_REG(001e) */ -+#define LCPLL_PI_EN_MASK BIT(5) -+#define LCPLL_100M_CLK_EN_MASK BIT(0) -+/* CMN_REG(0025) */ -+#define LCPLL_PMS_IQDIV_RSTN BIT(4) -+/* CMN_REG(0028) */ -+#define LCPLL_SDC_FRAC_EN BIT(2) -+#define LCPLL_SDC_FRAC_RSTN BIT(0) -+/* CMN_REG(002d) */ -+#define LCPLL_SDC_N_MASK GENMASK(3, 1) -+/* CMN_REG(002e) */ -+#define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0) -+/* CMN_REG(002f) */ -+#define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2) -+#define LCPLL_SDC_NDIV_RSTN BIT(0) -+/* CMN_REG(003d) */ -+#define ROPLL_LCVCO_EN BIT(4) -+/* CMN_REG(004e) */ -+#define ROPLL_PI_EN BIT(5) -+/* CMN_REG(005c) */ -+#define ROPLL_PMS_IQDIV_RSTN BIT(5) -+/* CMN_REG(005e) */ -+#define ROPLL_SDM_EN_MASK BIT(6) -+#define ROPLL_SDM_FRAC_EN_RBR BIT(3) -+#define ROPLL_SDM_FRAC_EN_HBR BIT(2) -+#define ROPLL_SDM_FRAC_EN_HBR2 BIT(1) -+#define ROPLL_SDM_FRAC_EN_HBR3 BIT(0) -+/* CMN_REG(0064) */ -+#define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3) -+/* CMN_REG(0069) */ -+#define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0) -+/* CMN_REG(0074) */ -+#define ROPLL_SDC_NDIV_RSTN BIT(2) -+#define ROPLL_SSC_EN BIT(0) -+/* CMN_REG(0081) */ -+#define OVRD_PLL_CD_CLK_EN BIT(8) -+#define PLL_CD_HSCLK_EAST_EN BIT(0) -+/* CMN_REG(0086) */ -+#define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4) -+#define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1) -+#define PLL_PCG_CLK_EN BIT(0) -+/* CMN_REG(0087) */ -+#define PLL_FRL_MODE_EN BIT(3) -+#define PLL_TX_HS_CLK_EN BIT(2) -+/* CMN_REG(0089) */ -+#define LCPLL_ALONE_MODE BIT(1) -+/* CMN_REG(0097) */ -+#define DIG_CLK_SEL BIT(1) -+#define ROPLL_REF BIT(1) -+#define LCPLL_REF 0 -+/* CMN_REG(0099) */ -+#define CMN_ROPLL_ALONE_MODE BIT(2) -+#define ROPLL_ALONE_MODE BIT(2) -+/* CMN_REG(009a) */ -+#define HS_SPEED_SEL BIT(0) -+#define DIV_10_CLOCK BIT(0) -+/* CMN_REG(009b) */ -+#define IS_SPEED_SEL BIT(4) -+#define LINK_SYMBOL_CLOCK BIT(4) -+#define LINK_SYMBOL_CLOCK1_2 0 -+ -+/* SB_REG(0102) */ -+#define OVRD_SB_RXTERM_EN_MASK BIT(5) -+#define SB_RXTERM_EN_MASK BIT(4) -+#define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0) -+/* SB_REG(0103) */ -+#define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3) -+#define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1) -+#define SB_RX_RESCAL_DONE_MASK BIT(0) -+/* SB_REG(0104) */ -+#define OVRD_SB_EN_MASK BIT(5) -+#define SB_EN_MASK BIT(4) -+/* SB_REG(0105) */ -+#define OVRD_SB_EARC_CMDC_EN_MASK BIT(6) -+#define SB_EARC_CMDC_EN_MASK BIT(5) -+#define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0) -+/* SB_REG(0106) */ -+#define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4) -+/* SB_REG(0109) */ -+#define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0) -+/* SB_REG(010f) */ -+#define OVRD_SB_VREG_EN_MASK BIT(7) -+#define SB_VREG_EN_MASK BIT(6) -+#define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5) -+#define SB_VREG_LPF_BYPASS_MASK BIT(4) -+#define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0) -+/* SB_REG(0110) */ -+#define ANA_SB_VREG_REF_SEL_MASK BIT(0) -+/* SB_REG(0113) */ -+#define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4) -+#define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0) -+/* SB_REG(0114) */ -+#define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3) -+#define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0) -+/* SB_REG(0115) */ -+#define SB_READY_DELAY_TIME_MASK GENMASK(5, 3) -+#define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0) -+/* SB_REG(0116) */ -+#define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4) -+/* SB_REG(0117) */ -+#define FAST_PULSE_TIME_MASK GENMASK(3, 0) -+/* SB_REG(011b) */ -+#define SB_EARC_SIG_DET_BYPASS_MASK BIT(4) -+#define SB_AFC_TOL_MASK GENMASK(3, 0) -+/* SB_REG(011f) */ -+#define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2) -+#define SB_RCAL_RSTN_MASK BIT(1) -+/* SB_REG(0120) */ -+#define SB_EARC_EN_MASK BIT(1) -+#define SB_EARC_AFC_EN_MASK BIT(2) -+/* SB_REG(0123) */ -+#define OVRD_SB_READY_MASK BIT(5) -+#define SB_READY_MASK BIT(4) -+ -+/* LNTOP_REG(0200) */ -+#define PROTOCOL_SEL BIT(2) -+#define HDMI_MODE BIT(2) -+#define HDMI_TMDS_FRL_SEL BIT(1) -+/* LNTOP_REG(0206) */ -+#define DATA_BUS_SEL BIT(0) -+#define DATA_BUS_36_40 BIT(0) -+/* LNTOP_REG(0207) */ -+#define LANE_EN 0xf -+#define ALL_LANE_EN 0xf -+ -+/* LANE_REG(0312) */ -+#define LN0_TX_SER_RATE_SEL_RBR BIT(5) -+#define LN0_TX_SER_RATE_SEL_HBR BIT(4) -+#define LN0_TX_SER_RATE_SEL_HBR2 BIT(3) -+#define LN0_TX_SER_RATE_SEL_HBR3 BIT(2) -+/* LANE_REG(0412) */ -+#define LN1_TX_SER_RATE_SEL_RBR BIT(5) -+#define LN1_TX_SER_RATE_SEL_HBR BIT(4) -+#define LN1_TX_SER_RATE_SEL_HBR2 BIT(3) -+#define LN1_TX_SER_RATE_SEL_HBR3 BIT(2) -+/* LANE_REG(0512) */ -+#define LN2_TX_SER_RATE_SEL_RBR BIT(5) -+#define LN2_TX_SER_RATE_SEL_HBR BIT(4) -+#define LN2_TX_SER_RATE_SEL_HBR2 BIT(3) -+#define LN2_TX_SER_RATE_SEL_HBR3 BIT(2) -+/* LANE_REG(0612) */ -+#define LN3_TX_SER_RATE_SEL_RBR BIT(5) -+#define LN3_TX_SER_RATE_SEL_HBR BIT(4) -+#define LN3_TX_SER_RATE_SEL_HBR2 BIT(3) -+#define LN3_TX_SER_RATE_SEL_HBR3 BIT(2) -+ -+struct lcpll_config { -+ u32 bit_rate; -+ u8 lcvco_mode_en; -+ u8 pi_en; -+ u8 clk_en_100m; -+ u8 pms_mdiv; -+ u8 pms_mdiv_afc; -+ u8 pms_pdiv; -+ u8 pms_refdiv; -+ u8 pms_sdiv; -+ u8 pi_cdiv_rstn; -+ u8 pi_cdiv_sel; -+ u8 sdm_en; -+ u8 sdm_rstn; -+ u8 sdc_frac_en; -+ u8 sdc_rstn; -+ u8 sdm_deno; -+ u8 sdm_num_sign; -+ u8 sdm_num; -+ u8 sdc_n; -+ u8 sdc_n2; -+ u8 sdc_num; -+ u8 sdc_deno; -+ u8 sdc_ndiv_rstn; -+ u8 ssc_en; -+ u8 ssc_fm_dev; -+ u8 ssc_fm_freq; -+ u8 ssc_clk_div_sel; -+ u8 cd_tx_ser_rate_sel; -+}; -+ -+struct ropll_config { -+ u32 bit_rate; -+ u8 pms_mdiv; -+ u8 pms_mdiv_afc; -+ u8 pms_pdiv; -+ u8 pms_refdiv; -+ u8 pms_sdiv; -+ u8 pms_iqdiv_rstn; -+ u8 ref_clk_sel; -+ u8 sdm_en; -+ u8 sdm_rstn; -+ u8 sdc_frac_en; -+ u8 sdc_rstn; -+ u8 sdm_clk_div; -+ u8 sdm_deno; -+ u8 sdm_num_sign; -+ u8 sdm_num; -+ u8 sdc_n; -+ u8 sdc_num; -+ u8 sdc_deno; -+ u8 sdc_ndiv_rstn; -+ u8 ssc_en; -+ u8 ssc_fm_dev; -+ u8 ssc_fm_freq; -+ u8 ssc_clk_div_sel; -+ u8 ana_cpp_ctrl; -+ u8 ana_lpf_c_sel; -+ u8 cd_tx_ser_rate_sel; -+}; -+ -+enum rk_hdptx_reset { -+ RST_PHY = 0, -+ RST_APB, -+ RST_INIT, -+ RST_CMN, -+ RST_LANE, -+ RST_ROPLL, -+ RST_LCPLL, -+ RST_MAX -+}; -+ -+struct rk_hdptx_phy { -+ struct device *dev; -+ struct regmap *regmap; -+ struct regmap *grf; -+ -+ struct phy *phy; -+ struct phy_config *phy_cfg; -+ struct clk_bulk_data *clks; -+ int nr_clks; -+ struct reset_control_bulk_data rsts[RST_MAX]; -+}; -+ -+static const struct ropll_config ropll_tmds_cfg[] = { -+ { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, -+ 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, -+ 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, -+ 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, -+ 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, -+ 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, -+ 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, -+ 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, -+ 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, -+ 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, -+ 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, -+ 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, -+ 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, -+ 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, -+ 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, -+ 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, -+ 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, -+ 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, -+ 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, -+ 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, -+ 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+}; -+ -+static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = { -+ REG_SEQ0(CMN_REG(0009), 0x0c), -+ REG_SEQ0(CMN_REG(000a), 0x83), -+ REG_SEQ0(CMN_REG(000b), 0x06), -+ REG_SEQ0(CMN_REG(000c), 0x20), -+ REG_SEQ0(CMN_REG(000d), 0xb8), -+ REG_SEQ0(CMN_REG(000e), 0x0f), -+ REG_SEQ0(CMN_REG(000f), 0x0f), -+ REG_SEQ0(CMN_REG(0010), 0x04), -+ REG_SEQ0(CMN_REG(0011), 0x00), -+ REG_SEQ0(CMN_REG(0012), 0x26), -+ REG_SEQ0(CMN_REG(0013), 0x22), -+ REG_SEQ0(CMN_REG(0014), 0x24), -+ REG_SEQ0(CMN_REG(0015), 0x77), -+ REG_SEQ0(CMN_REG(0016), 0x08), -+ REG_SEQ0(CMN_REG(0017), 0x00), -+ REG_SEQ0(CMN_REG(0018), 0x04), -+ REG_SEQ0(CMN_REG(0019), 0x48), -+ REG_SEQ0(CMN_REG(001a), 0x01), -+ REG_SEQ0(CMN_REG(001b), 0x00), -+ REG_SEQ0(CMN_REG(001c), 0x01), -+ REG_SEQ0(CMN_REG(001d), 0x64), -+ REG_SEQ0(CMN_REG(001f), 0x00), -+ REG_SEQ0(CMN_REG(0026), 0x53), -+ REG_SEQ0(CMN_REG(0029), 0x01), -+ REG_SEQ0(CMN_REG(0030), 0x00), -+ REG_SEQ0(CMN_REG(0031), 0x20), -+ REG_SEQ0(CMN_REG(0032), 0x30), -+ REG_SEQ0(CMN_REG(0033), 0x0b), -+ REG_SEQ0(CMN_REG(0034), 0x23), -+ REG_SEQ0(CMN_REG(0035), 0x00), -+ REG_SEQ0(CMN_REG(0038), 0x00), -+ REG_SEQ0(CMN_REG(0039), 0x00), -+ REG_SEQ0(CMN_REG(003a), 0x00), -+ REG_SEQ0(CMN_REG(003b), 0x00), -+ REG_SEQ0(CMN_REG(003c), 0x80), -+ REG_SEQ0(CMN_REG(003e), 0x0c), -+ REG_SEQ0(CMN_REG(003f), 0x83), -+ REG_SEQ0(CMN_REG(0040), 0x06), -+ REG_SEQ0(CMN_REG(0041), 0x20), -+ REG_SEQ0(CMN_REG(0042), 0xb8), -+ REG_SEQ0(CMN_REG(0043), 0x00), -+ REG_SEQ0(CMN_REG(0044), 0x46), -+ REG_SEQ0(CMN_REG(0045), 0x24), -+ REG_SEQ0(CMN_REG(0046), 0xff), -+ REG_SEQ0(CMN_REG(0047), 0x00), -+ REG_SEQ0(CMN_REG(0048), 0x44), -+ REG_SEQ0(CMN_REG(0049), 0xfa), -+ REG_SEQ0(CMN_REG(004a), 0x08), -+ REG_SEQ0(CMN_REG(004b), 0x00), -+ REG_SEQ0(CMN_REG(004c), 0x01), -+ REG_SEQ0(CMN_REG(004d), 0x64), -+ REG_SEQ0(CMN_REG(004e), 0x14), -+ REG_SEQ0(CMN_REG(004f), 0x00), -+ REG_SEQ0(CMN_REG(0050), 0x00), -+ REG_SEQ0(CMN_REG(005d), 0x0c), -+ REG_SEQ0(CMN_REG(005f), 0x01), -+ REG_SEQ0(CMN_REG(006b), 0x04), -+ REG_SEQ0(CMN_REG(0073), 0x30), -+ REG_SEQ0(CMN_REG(0074), 0x00), -+ REG_SEQ0(CMN_REG(0075), 0x20), -+ REG_SEQ0(CMN_REG(0076), 0x30), -+ REG_SEQ0(CMN_REG(0077), 0x08), -+ REG_SEQ0(CMN_REG(0078), 0x0c), -+ REG_SEQ0(CMN_REG(0079), 0x00), -+ REG_SEQ0(CMN_REG(007b), 0x00), -+ REG_SEQ0(CMN_REG(007c), 0x00), -+ REG_SEQ0(CMN_REG(007d), 0x00), -+ REG_SEQ0(CMN_REG(007e), 0x00), -+ REG_SEQ0(CMN_REG(007f), 0x00), -+ REG_SEQ0(CMN_REG(0080), 0x00), -+ REG_SEQ0(CMN_REG(0081), 0x09), -+ REG_SEQ0(CMN_REG(0082), 0x04), -+ REG_SEQ0(CMN_REG(0083), 0x24), -+ REG_SEQ0(CMN_REG(0084), 0x20), -+ REG_SEQ0(CMN_REG(0085), 0x03), -+ REG_SEQ0(CMN_REG(0086), 0x01), -+ REG_SEQ0(CMN_REG(0087), 0x0c), -+ REG_SEQ0(CMN_REG(008a), 0x55), -+ REG_SEQ0(CMN_REG(008b), 0x25), -+ REG_SEQ0(CMN_REG(008c), 0x2c), -+ REG_SEQ0(CMN_REG(008d), 0x22), -+ REG_SEQ0(CMN_REG(008e), 0x14), -+ REG_SEQ0(CMN_REG(008f), 0x20), -+ REG_SEQ0(CMN_REG(0090), 0x00), -+ REG_SEQ0(CMN_REG(0091), 0x00), -+ REG_SEQ0(CMN_REG(0092), 0x00), -+ REG_SEQ0(CMN_REG(0093), 0x00), -+ REG_SEQ0(CMN_REG(009a), 0x11), -+ REG_SEQ0(CMN_REG(009b), 0x10), -+}; -+ -+static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = { -+ REG_SEQ0(CMN_REG(0008), 0x00), -+ REG_SEQ0(CMN_REG(0011), 0x01), -+ REG_SEQ0(CMN_REG(0017), 0x20), -+ REG_SEQ0(CMN_REG(001e), 0x14), -+ REG_SEQ0(CMN_REG(0020), 0x00), -+ REG_SEQ0(CMN_REG(0021), 0x00), -+ REG_SEQ0(CMN_REG(0022), 0x11), -+ REG_SEQ0(CMN_REG(0023), 0x00), -+ REG_SEQ0(CMN_REG(0024), 0x00), -+ REG_SEQ0(CMN_REG(0025), 0x53), -+ REG_SEQ0(CMN_REG(0026), 0x00), -+ REG_SEQ0(CMN_REG(0027), 0x00), -+ REG_SEQ0(CMN_REG(0028), 0x01), -+ REG_SEQ0(CMN_REG(002a), 0x00), -+ REG_SEQ0(CMN_REG(002b), 0x00), -+ REG_SEQ0(CMN_REG(002c), 0x00), -+ REG_SEQ0(CMN_REG(002d), 0x00), -+ REG_SEQ0(CMN_REG(002e), 0x04), -+ REG_SEQ0(CMN_REG(002f), 0x00), -+ REG_SEQ0(CMN_REG(0030), 0x20), -+ REG_SEQ0(CMN_REG(0031), 0x30), -+ REG_SEQ0(CMN_REG(0032), 0x0b), -+ REG_SEQ0(CMN_REG(0033), 0x23), -+ REG_SEQ0(CMN_REG(0034), 0x00), -+ REG_SEQ0(CMN_REG(003d), 0x40), -+ REG_SEQ0(CMN_REG(0042), 0x78), -+ REG_SEQ0(CMN_REG(004e), 0x34), -+ REG_SEQ0(CMN_REG(005c), 0x25), -+ REG_SEQ0(CMN_REG(005e), 0x4f), -+ REG_SEQ0(CMN_REG(0074), 0x04), -+ REG_SEQ0(CMN_REG(0081), 0x01), -+ REG_SEQ0(CMN_REG(0087), 0x04), -+ REG_SEQ0(CMN_REG(0089), 0x00), -+ REG_SEQ0(CMN_REG(0095), 0x00), -+ REG_SEQ0(CMN_REG(0097), 0x02), -+ REG_SEQ0(CMN_REG(0099), 0x04), -+ REG_SEQ0(CMN_REG(009b), 0x00), -+}; -+ -+static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = { -+ REG_SEQ0(SB_REG(0114), 0x00), -+ REG_SEQ0(SB_REG(0115), 0x00), -+ REG_SEQ0(SB_REG(0116), 0x00), -+ REG_SEQ0(SB_REG(0117), 0x00), -+}; -+ -+static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = { -+ REG_SEQ0(LNTOP_REG(0201), 0x00), -+ REG_SEQ0(LNTOP_REG(0202), 0x00), -+ REG_SEQ0(LNTOP_REG(0203), 0x0f), -+ REG_SEQ0(LNTOP_REG(0204), 0xff), -+ REG_SEQ0(LNTOP_REG(0205), 0xff), -+}; -+ -+static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = { -+ REG_SEQ0(LNTOP_REG(0201), 0x07), -+ REG_SEQ0(LNTOP_REG(0202), 0xc1), -+ REG_SEQ0(LNTOP_REG(0203), 0xf0), -+ REG_SEQ0(LNTOP_REG(0204), 0x7c), -+ REG_SEQ0(LNTOP_REG(0205), 0x1f), -+}; -+ -+static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = { -+ REG_SEQ0(LANE_REG(0303), 0x0c), -+ REG_SEQ0(LANE_REG(0307), 0x20), -+ REG_SEQ0(LANE_REG(030a), 0x17), -+ REG_SEQ0(LANE_REG(030b), 0x77), -+ REG_SEQ0(LANE_REG(030c), 0x77), -+ REG_SEQ0(LANE_REG(030d), 0x77), -+ REG_SEQ0(LANE_REG(030e), 0x38), -+ REG_SEQ0(LANE_REG(0310), 0x03), -+ REG_SEQ0(LANE_REG(0311), 0x0f), -+ REG_SEQ0(LANE_REG(0316), 0x02), -+ REG_SEQ0(LANE_REG(031b), 0x01), -+ REG_SEQ0(LANE_REG(031f), 0x15), -+ REG_SEQ0(LANE_REG(0320), 0xa0), -+ REG_SEQ0(LANE_REG(0403), 0x0c), -+ REG_SEQ0(LANE_REG(0407), 0x20), -+ REG_SEQ0(LANE_REG(040a), 0x17), -+ REG_SEQ0(LANE_REG(040b), 0x77), -+ REG_SEQ0(LANE_REG(040c), 0x77), -+ REG_SEQ0(LANE_REG(040d), 0x77), -+ REG_SEQ0(LANE_REG(040e), 0x38), -+ REG_SEQ0(LANE_REG(0410), 0x03), -+ REG_SEQ0(LANE_REG(0411), 0x0f), -+ REG_SEQ0(LANE_REG(0416), 0x02), -+ REG_SEQ0(LANE_REG(041b), 0x01), -+ REG_SEQ0(LANE_REG(041f), 0x15), -+ REG_SEQ0(LANE_REG(0420), 0xa0), -+ REG_SEQ0(LANE_REG(0503), 0x0c), -+ REG_SEQ0(LANE_REG(0507), 0x20), -+ REG_SEQ0(LANE_REG(050a), 0x17), -+ REG_SEQ0(LANE_REG(050b), 0x77), -+ REG_SEQ0(LANE_REG(050c), 0x77), -+ REG_SEQ0(LANE_REG(050d), 0x77), -+ REG_SEQ0(LANE_REG(050e), 0x38), -+ REG_SEQ0(LANE_REG(0510), 0x03), -+ REG_SEQ0(LANE_REG(0511), 0x0f), -+ REG_SEQ0(LANE_REG(0516), 0x02), -+ REG_SEQ0(LANE_REG(051b), 0x01), -+ REG_SEQ0(LANE_REG(051f), 0x15), -+ REG_SEQ0(LANE_REG(0520), 0xa0), -+ REG_SEQ0(LANE_REG(0603), 0x0c), -+ REG_SEQ0(LANE_REG(0607), 0x20), -+ REG_SEQ0(LANE_REG(060a), 0x17), -+ REG_SEQ0(LANE_REG(060b), 0x77), -+ REG_SEQ0(LANE_REG(060c), 0x77), -+ REG_SEQ0(LANE_REG(060d), 0x77), -+ REG_SEQ0(LANE_REG(060e), 0x38), -+ REG_SEQ0(LANE_REG(0610), 0x03), -+ REG_SEQ0(LANE_REG(0611), 0x0f), -+ REG_SEQ0(LANE_REG(0616), 0x02), -+ REG_SEQ0(LANE_REG(061b), 0x01), -+ REG_SEQ0(LANE_REG(061f), 0x15), -+ REG_SEQ0(LANE_REG(0620), 0xa0), -+}; -+ -+static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = { -+ REG_SEQ0(LANE_REG(0312), 0x00), -+ REG_SEQ0(LANE_REG(031e), 0x00), -+ REG_SEQ0(LANE_REG(0412), 0x00), -+ REG_SEQ0(LANE_REG(041e), 0x00), -+ REG_SEQ0(LANE_REG(0512), 0x00), -+ REG_SEQ0(LANE_REG(051e), 0x00), -+ REG_SEQ0(LANE_REG(0612), 0x00), -+ REG_SEQ0(LANE_REG(061e), 0x08), -+ REG_SEQ0(LANE_REG(0303), 0x2f), -+ REG_SEQ0(LANE_REG(0403), 0x2f), -+ REG_SEQ0(LANE_REG(0503), 0x2f), -+ REG_SEQ0(LANE_REG(0603), 0x2f), -+ REG_SEQ0(LANE_REG(0305), 0x03), -+ REG_SEQ0(LANE_REG(0405), 0x03), -+ REG_SEQ0(LANE_REG(0505), 0x03), -+ REG_SEQ0(LANE_REG(0605), 0x03), -+ REG_SEQ0(LANE_REG(0306), 0x1c), -+ REG_SEQ0(LANE_REG(0406), 0x1c), -+ REG_SEQ0(LANE_REG(0506), 0x1c), -+ REG_SEQ0(LANE_REG(0606), 0x1c), -+}; -+ -+static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg) -+{ -+ switch (reg) { -+ case 0x0000 ... 0x029c: -+ case 0x0400 ... 0x04a4: -+ case 0x0800 ... 0x08a4: -+ case 0x0c00 ... 0x0cb4: -+ case 0x1000 ... 0x10b4: -+ case 0x1400 ... 0x14b4: -+ case 0x1800 ... 0x18b4: -+ return true; -+ } -+ -+ return false; -+} -+ -+static const struct regmap_config rk_hdptx_phy_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .writeable_reg = rk_hdptx_phy_is_rw_reg, -+ .readable_reg = rk_hdptx_phy_is_rw_reg, -+ .fast_io = true, -+ .max_register = 0x18b4, -+}; -+ -+#define rk_hdptx_multi_reg_write(hdptx, seq) \ -+ regmap_multi_reg_write((hdptx)->regmap, seq, ARRAY_SIZE(seq)) -+ -+static void rk_hdptx_pre_power_up(struct rk_hdptx_phy *hdptx) -+{ -+ u32 val; -+ -+ reset_control_assert(hdptx->rsts[RST_APB].rstc); -+ usleep_range(20, 25); -+ reset_control_deassert(hdptx->rsts[RST_APB].rstc); -+ -+ reset_control_assert(hdptx->rsts[RST_LANE].rstc); -+ reset_control_assert(hdptx->rsts[RST_CMN].rstc); -+ reset_control_assert(hdptx->rsts[RST_INIT].rstc); -+ -+ val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; -+ regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); -+} -+ -+static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx) -+{ -+ u32 val; -+ int ret; -+ -+ reset_control_deassert(hdptx->rsts[RST_LANE].rstc); -+ -+ val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | -+ HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; -+ regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); -+ -+ ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, -+ (val & HDPTX_O_PHY_RDY) && -+ (val & HDPTX_O_PLL_LOCK_DONE), -+ 100, 5000); -+ if (ret) { -+ dev_err(hdptx->dev, "Failed to get PHY lane lock: %d\n", ret); -+ return ret; -+ } -+ -+ dev_dbg(hdptx->dev, "PHY lane locked\n"); -+ -+ return 0; -+} -+ -+static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx) -+{ -+ u32 val; -+ int ret; -+ -+ val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | -+ HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; -+ regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); -+ -+ usleep_range(10, 15); -+ reset_control_deassert(hdptx->rsts[RST_INIT].rstc); -+ -+ usleep_range(10, 15); -+ val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN; -+ regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); -+ -+ usleep_range(10, 15); -+ reset_control_deassert(hdptx->rsts[RST_CMN].rstc); -+ -+ ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, -+ val & HDPTX_O_PHY_CLK_RDY, 20, 400); -+ if (ret) { -+ dev_err(hdptx->dev, "Failed to get PHY clk ready: %d\n", ret); -+ return ret; -+ } -+ -+ dev_dbg(hdptx->dev, "PHY clk ready\n"); -+ -+ return 0; -+} -+ -+static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx) -+{ -+ u32 val; -+ -+ /* reset phy and apb, or phy locked flag may keep 1 */ -+ reset_control_assert(hdptx->rsts[RST_PHY].rstc); -+ usleep_range(20, 30); -+ reset_control_deassert(hdptx->rsts[RST_PHY].rstc); -+ -+ reset_control_assert(hdptx->rsts[RST_APB].rstc); -+ usleep_range(20, 30); -+ reset_control_deassert(hdptx->rsts[RST_APB].rstc); -+ -+ regmap_write(hdptx->regmap, LANE_REG(0300), 0x82); -+ regmap_write(hdptx->regmap, SB_REG(010f), 0xc1); -+ regmap_write(hdptx->regmap, SB_REG(0110), 0x1); -+ regmap_write(hdptx->regmap, LANE_REG(0301), 0x80); -+ regmap_write(hdptx->regmap, LANE_REG(0401), 0x80); -+ regmap_write(hdptx->regmap, LANE_REG(0501), 0x80); -+ regmap_write(hdptx->regmap, LANE_REG(0601), 0x80); -+ -+ reset_control_assert(hdptx->rsts[RST_LANE].rstc); -+ reset_control_assert(hdptx->rsts[RST_CMN].rstc); -+ reset_control_assert(hdptx->rsts[RST_INIT].rstc); -+ -+ val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; -+ regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); -+} -+ -+static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, -+ struct ropll_config *cfg) -+{ -+ const unsigned int fout = data_rate / 2, fref = 24000; -+ unsigned long k = 0, lc, k_sub, lc_sub; -+ unsigned int fvco, sdc; -+ u32 mdiv, sdiv, n = 8; -+ -+ if (fout > 0xfffffff) -+ return false; -+ -+ for (sdiv = 16; sdiv >= 1; sdiv--) { -+ if (sdiv % 2 && sdiv != 1) -+ continue; -+ -+ fvco = fout * sdiv; -+ -+ if (fvco < 2000000 || fvco > 4000000) -+ continue; -+ -+ mdiv = DIV_ROUND_UP(fvco, fref); -+ if (mdiv < 20 || mdiv > 255) -+ continue; -+ -+ if (fref * mdiv - fvco) { -+ for (sdc = 264000; sdc <= 750000; sdc += fref) -+ if (sdc * n > fref * mdiv) -+ break; -+ -+ if (sdc > 750000) -+ continue; -+ -+ rational_best_approximation(fref * mdiv - fvco, -+ sdc / 16, -+ GENMASK(6, 0), -+ GENMASK(7, 0), -+ &k, &lc); -+ -+ rational_best_approximation(sdc * n - fref * mdiv, -+ sdc, -+ GENMASK(6, 0), -+ GENMASK(7, 0), -+ &k_sub, &lc_sub); -+ } -+ -+ break; -+ } -+ -+ if (sdiv < 1) -+ return false; -+ -+ if (cfg) { -+ cfg->pms_mdiv = mdiv; -+ cfg->pms_mdiv_afc = mdiv; -+ cfg->pms_pdiv = 1; -+ cfg->pms_refdiv = 1; -+ cfg->pms_sdiv = sdiv - 1; -+ -+ cfg->sdm_en = k > 0 ? 1 : 0; -+ if (cfg->sdm_en) { -+ cfg->sdm_deno = lc; -+ cfg->sdm_num_sign = 1; -+ cfg->sdm_num = k; -+ cfg->sdc_n = n - 3; -+ cfg->sdc_num = k_sub; -+ cfg->sdc_deno = lc_sub; -+ } -+ } -+ -+ return true; -+} -+ -+static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, -+ unsigned int rate) -+{ -+ const struct ropll_config *cfg = NULL; -+ struct ropll_config rc = {0}; -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) -+ if (rate == ropll_tmds_cfg[i].bit_rate) { -+ cfg = &ropll_tmds_cfg[i]; -+ break; -+ } -+ -+ if (!cfg) { -+ if (rk_hdptx_phy_clk_pll_calc(rate, &rc)) { -+ cfg = &rc; -+ } else { -+ dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__); -+ return -EINVAL; -+ } -+ } -+ -+ dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u, sdm_en=%u, k_sign=%u, k=%u, lc=%u\n", -+ cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en, -+ cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); -+ -+ rk_hdptx_pre_power_up(hdptx); -+ -+ reset_control_assert(hdptx->rsts[RST_ROPLL].rstc); -+ usleep_range(20, 30); -+ reset_control_deassert(hdptx->rsts[RST_ROPLL].rstc); -+ -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq); -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq); -+ -+ regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv); -+ regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc); -+ regmap_write(hdptx->regmap, CMN_REG(0059), -+ (cfg->pms_pdiv << 4) | cfg->pms_refdiv); -+ regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK, -+ FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en)); -+ if (!cfg->sdm_en) -+ regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK, -+ FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign)); -+ -+ regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno); -+ regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK, -+ FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n)); -+ -+ regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num); -+ regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, -+ FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN, -+ PLL_PCG_CLK_EN); -+ -+ return rk_hdptx_post_enable_pll(hdptx); -+} -+ -+static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, -+ unsigned int rate) -+{ -+ u32 val; -+ int ret; -+ -+ ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); -+ if (ret) -+ return ret; -+ -+ if (!(val & HDPTX_O_PLL_LOCK_DONE)) { -+ ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); -+ if (ret) -+ return ret; -+ } -+ -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); -+ -+ regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); -+ -+ if (rate >= 3400000) { -+ /* For 1/40 bitrate clk */ -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); -+ } else { -+ /* For 1/10 bitrate clk */ -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq); -+ } -+ -+ regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07); -+ regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); -+ -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq); -+ -+ return rk_hdptx_post_enable_lane(hdptx); -+} -+ -+static int rk_hdptx_phy_power_on(struct phy *phy) -+{ -+ struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); -+ int ret, bus_width = phy_get_bus_width(hdptx->phy); -+ /* -+ * FIXME: Temporary workaround to pass pixel_clk_rate -+ * from the HDMI bridge driver until phy_configure_opts_hdmi -+ * becomes available in the PHY API. -+ */ -+ unsigned int rate = bus_width & 0xfffffff; -+ -+ dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n", -+ __func__, bus_width, rate); -+ -+ ret = pm_runtime_resume_and_get(hdptx->dev); -+ if (ret) { -+ dev_err(hdptx->dev, "Failed to resume phy: %d\n", ret); -+ return ret; -+ } -+ -+ ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate); -+ if (ret) -+ pm_runtime_put(hdptx->dev); -+ -+ return ret; -+} -+ -+static int rk_hdptx_phy_power_off(struct phy *phy) -+{ -+ struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); -+ u32 val; -+ int ret; -+ -+ ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); -+ if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) -+ rk_hdptx_phy_disable(hdptx); -+ -+ pm_runtime_put(hdptx->dev); -+ -+ return ret; -+} -+ -+static const struct phy_ops rk_hdptx_phy_ops = { -+ .power_on = rk_hdptx_phy_power_on, -+ .power_off = rk_hdptx_phy_power_off, -+ .owner = THIS_MODULE, -+}; -+ -+static int rk_hdptx_phy_runtime_suspend(struct device *dev) -+{ -+ struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); -+ -+ clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks); -+ -+ return 0; -+} -+ -+static int rk_hdptx_phy_runtime_resume(struct device *dev) -+{ -+ struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); -+ int ret; -+ -+ ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks); -+ if (ret) -+ dev_err(hdptx->dev, "Failed to enable clocks: %d\n", ret); -+ -+ return ret; -+} -+ -+static int rk_hdptx_phy_probe(struct platform_device *pdev) -+{ -+ struct phy_provider *phy_provider; -+ struct device *dev = &pdev->dev; -+ struct rk_hdptx_phy *hdptx; -+ void __iomem *regs; -+ int ret; -+ -+ hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL); -+ if (!hdptx) -+ return -ENOMEM; -+ -+ hdptx->dev = dev; -+ -+ regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(regs)) -+ return dev_err_probe(dev, PTR_ERR(regs), -+ "Failed to ioremap resource\n"); -+ -+ ret = devm_clk_bulk_get_all(dev, &hdptx->clks); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to get clocks\n"); -+ if (ret == 0) -+ return dev_err_probe(dev, -EINVAL, "Missing clocks\n"); -+ -+ hdptx->nr_clks = ret; -+ -+ hdptx->regmap = devm_regmap_init_mmio(dev, regs, -+ &rk_hdptx_phy_regmap_config); -+ if (IS_ERR(hdptx->regmap)) -+ return dev_err_probe(dev, PTR_ERR(hdptx->regmap), -+ "Failed to init regmap\n"); -+ -+ hdptx->rsts[RST_PHY].id = "phy"; -+ hdptx->rsts[RST_APB].id = "apb"; -+ hdptx->rsts[RST_INIT].id = "init"; -+ hdptx->rsts[RST_CMN].id = "cmn"; -+ hdptx->rsts[RST_LANE].id = "lane"; -+ hdptx->rsts[RST_ROPLL].id = "ropll"; -+ hdptx->rsts[RST_LCPLL].id = "lcpll"; -+ -+ ret = devm_reset_control_bulk_get_exclusive(dev, RST_MAX, hdptx->rsts); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to get resets\n"); -+ -+ hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node, -+ "rockchip,grf"); -+ if (IS_ERR(hdptx->grf)) -+ return dev_err_probe(dev, PTR_ERR(hdptx->grf), -+ "Could not get GRF syscon\n"); -+ -+ hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops); -+ if (IS_ERR(hdptx->phy)) -+ return dev_err_probe(dev, PTR_ERR(hdptx->phy), -+ "Failed to create HDMI PHY\n"); -+ -+ platform_set_drvdata(pdev, hdptx); -+ phy_set_drvdata(hdptx->phy, hdptx); -+ phy_set_bus_width(hdptx->phy, 8); -+ -+ ret = devm_pm_runtime_enable(dev); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); -+ -+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ if (IS_ERR(phy_provider)) -+ return dev_err_probe(dev, PTR_ERR(phy_provider), -+ "Failed to register PHY provider\n"); -+ -+ reset_control_deassert(hdptx->rsts[RST_APB].rstc); -+ reset_control_deassert(hdptx->rsts[RST_CMN].rstc); -+ reset_control_deassert(hdptx->rsts[RST_INIT].rstc); -+ -+ return 0; -+} -+ -+static const struct dev_pm_ops rk_hdptx_phy_pm_ops = { -+ RUNTIME_PM_OPS(rk_hdptx_phy_runtime_suspend, -+ rk_hdptx_phy_runtime_resume, NULL) -+}; -+ -+static const struct of_device_id rk_hdptx_phy_of_match[] = { -+ { .compatible = "rockchip,rk3588-hdptx-phy", }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, rk_hdptx_phy_of_match); -+ -+static struct platform_driver rk_hdptx_phy_driver = { -+ .probe = rk_hdptx_phy_probe, -+ .driver = { -+ .name = "rockchip-hdptx-phy", -+ .pm = &rk_hdptx_phy_pm_ops, -+ .of_match_table = rk_hdptx_phy_of_match, -+ }, -+}; -+module_platform_driver(rk_hdptx_phy_driver); -+ -+MODULE_AUTHOR("Algea Cao "); -+MODULE_AUTHOR("Cristian Ciocaltea "); -+MODULE_DESCRIPTION("Samsung HDMI/eDP Transmitter Combo PHY Driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/rockchip/patches-6.6/032-02-v6.10-phy-rockchip-add-usbdp-combo-phy-driver.patch b/target/linux/rockchip/patches-6.6/032-02-v6.10-phy-rockchip-add-usbdp-combo-phy-driver.patch deleted file mode 100644 index 64c9b57f63..0000000000 --- a/target/linux/rockchip/patches-6.6/032-02-v6.10-phy-rockchip-add-usbdp-combo-phy-driver.patch +++ /dev/null @@ -1,1670 +0,0 @@ -From 2f70bbddeb457580cef3ceb574506083b9272188 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 9 Apr 2024 00:50:29 +0200 -Subject: [PATCH] phy: rockchip: add usbdp combo phy driver - -This adds a new USBDP combo PHY with Samsung IP block driver. - -The driver get lane mux and mapping info in 2 ways, supporting -DisplayPort alternate mode or parsing from DT. When parsing from DT, -the property "rockchip,dp-lane-mux" provide the DP mux and mapping -info. This is needed when the PHY is not used with TypeC Alt-Mode. -For example if the USB3 interface of the PHY is connected to a USB -Type A connector and the DP interface is connected to a DisplayPort -connector. - -When do DP link training, need to set lane number, link rate, swing, -and pre-emphasis via PHY configure interface. - -Co-developed-by: Heiko Stuebner -Signed-off-by: Heiko Stuebner -Co-developed-by: Zhang Yubing -Signed-off-by: Zhang Yubing -Co-developed-by: Frank Wang -Signed-off-by: Frank Wang -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240408225109.128953-3-sebastian.reichel@collabora.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/Kconfig | 12 + - drivers/phy/rockchip/Makefile | 1 + - drivers/phy/rockchip/phy-rockchip-usbdp.c | 1608 +++++++++++++++++++++ - 3 files changed, 1621 insertions(+) - create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c - ---- a/drivers/phy/rockchip/Kconfig -+++ b/drivers/phy/rockchip/Kconfig -@@ -115,3 +115,15 @@ config PHY_ROCKCHIP_USB - select GENERIC_PHY - help - Enable this to support the Rockchip USB 2.0 PHY. -+ -+config PHY_ROCKCHIP_USBDP -+ tristate "Rockchip USBDP COMBO PHY Driver" -+ depends on ARCH_ROCKCHIP && OF -+ select GENERIC_PHY -+ select TYPEC -+ help -+ Enable this to support the Rockchip USB3.0/DP combo PHY with -+ Samsung IP block. This is required for USB3 support on RK3588. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called phy-rockchip-usbdp ---- a/drivers/phy/rockchip/Makefile -+++ b/drivers/phy/rockchip/Makefile -@@ -12,3 +12,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX) - obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o - obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o - obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o -+obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o ---- /dev/null -+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c -@@ -0,0 +1,1608 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Rockchip USBDP Combo PHY with Samsung IP block driver -+ * -+ * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd -+ * Copyright (C) 2024 Collabora Ltd -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* USBDP PHY Register Definitions */ -+#define UDPHY_PCS 0x4000 -+#define UDPHY_PMA 0x8000 -+ -+/* VO0 GRF Registers */ -+#define DP_SINK_HPD_CFG BIT(11) -+#define DP_SINK_HPD_SEL BIT(10) -+#define DP_AUX_DIN_SEL BIT(9) -+#define DP_AUX_DOUT_SEL BIT(8) -+#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) -+#define DP_LANE_SEL_ALL GENMASK(7, 0) -+ -+/* PMA CMN Registers */ -+#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ -+#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) -+#define CMN_DP_LANE_EN_N(n) BIT(n) -+#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) -+#define CMN_DP_LANE_EN_ALL GENMASK(3, 0) -+ -+#define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */ -+#define CMN_DP_TX_LINK_BW GENMASK(6, 5) -+#define CMN_DP_TX_LANE_SWAP_EN BIT(2) -+ -+#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */ -+#define CMN_ROPLL_SSC_EN BIT(1) -+#define CMN_LCPLL_SSC_EN BIT(0) -+ -+#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */ -+#define CMN_ANA_LCPLL_LOCK_DONE BIT(7) -+#define CMN_ANA_LCPLL_AFC_DONE BIT(6) -+ -+#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */ -+#define CMN_ANA_ROPLL_LOCK_DONE BIT(1) -+#define CMN_ANA_ROPLL_AFC_DONE BIT(0) -+ -+#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */ -+#define CMN_DP_INIT_RSTN BIT(3) -+#define CMN_DP_CMN_RSTN BIT(2) -+#define CMN_CDR_WTCHDG_EN BIT(1) -+#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0) -+ -+#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */ -+#define LN_ANA_TX_SER_TXCLK_INV BIT(1) -+ -+#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */ -+#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0) -+ -+#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ -+#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) -+ -+#define BIT_WRITEABLE_SHIFT 16 -+#define PHY_AUX_DP_DATA_POL_NORMAL 0 -+#define PHY_AUX_DP_DATA_POL_INVERT 1 -+#define PHY_LANE_MUX_USB 0 -+#define PHY_LANE_MUX_DP 1 -+ -+enum { -+ DP_BW_RBR, -+ DP_BW_HBR, -+ DP_BW_HBR2, -+ DP_BW_HBR3, -+}; -+ -+enum { -+ UDPHY_MODE_NONE = 0, -+ UDPHY_MODE_USB = BIT(0), -+ UDPHY_MODE_DP = BIT(1), -+ UDPHY_MODE_DP_USB = BIT(1) | BIT(0), -+}; -+ -+struct rk_udphy_grf_reg { -+ unsigned int offset; -+ unsigned int disable; -+ unsigned int enable; -+}; -+ -+#define _RK_UDPHY_GEN_GRF_REG(offset, mask, disable, enable) \ -+{\ -+ offset, \ -+ FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \ -+ FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \ -+} -+ -+#define RK_UDPHY_GEN_GRF_REG(offset, bitend, bitstart, disable, enable) \ -+ _RK_UDPHY_GEN_GRF_REG(offset, GENMASK(bitend, bitstart), disable, enable) -+ -+struct rk_udphy_grf_cfg { -+ /* u2phy-grf */ -+ struct rk_udphy_grf_reg bvalid_phy_con; -+ struct rk_udphy_grf_reg bvalid_grf_con; -+ -+ /* usb-grf */ -+ struct rk_udphy_grf_reg usb3otg0_cfg; -+ struct rk_udphy_grf_reg usb3otg1_cfg; -+ -+ /* usbdpphy-grf */ -+ struct rk_udphy_grf_reg low_pwrn; -+ struct rk_udphy_grf_reg rx_lfps; -+}; -+ -+struct rk_udphy_vogrf_cfg { -+ /* vo-grf */ -+ struct rk_udphy_grf_reg hpd_trigger; -+ u32 dp_lane_reg; -+}; -+ -+struct rk_udphy_dp_tx_drv_ctrl { -+ u32 trsv_reg0204; -+ u32 trsv_reg0205; -+ u32 trsv_reg0206; -+ u32 trsv_reg0207; -+}; -+ -+struct rk_udphy_cfg { -+ unsigned int num_phys; -+ unsigned int phy_ids[2]; -+ /* resets to be requested */ -+ const char * const *rst_list; -+ int num_rsts; -+ -+ struct rk_udphy_grf_cfg grfcfg; -+ struct rk_udphy_vogrf_cfg vogrfcfg[2]; -+ const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4]; -+ const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4]; -+}; -+ -+struct rk_udphy { -+ struct device *dev; -+ struct regmap *pma_regmap; -+ struct regmap *u2phygrf; -+ struct regmap *udphygrf; -+ struct regmap *usbgrf; -+ struct regmap *vogrf; -+ struct typec_switch_dev *sw; -+ struct typec_mux_dev *mux; -+ struct mutex mutex; /* mutex to protect access to individual PHYs */ -+ -+ /* clocks and rests */ -+ int num_clks; -+ struct clk_bulk_data *clks; -+ struct clk *refclk; -+ int num_rsts; -+ struct reset_control_bulk_data *rsts; -+ -+ /* PHY status management */ -+ bool flip; -+ bool mode_change; -+ u8 mode; -+ u8 status; -+ -+ /* utilized for USB */ -+ bool hs; /* flag for high-speed */ -+ -+ /* utilized for DP */ -+ struct gpio_desc *sbu1_dc_gpio; -+ struct gpio_desc *sbu2_dc_gpio; -+ u32 lane_mux_sel[4]; -+ u32 dp_lane_sel[4]; -+ u32 dp_aux_dout_sel; -+ u32 dp_aux_din_sel; -+ bool dp_sink_hpd_sel; -+ bool dp_sink_hpd_cfg; -+ u8 bw; -+ int id; -+ -+ bool dp_in_use; -+ -+ /* PHY const config */ -+ const struct rk_udphy_cfg *cfgs; -+ -+ /* PHY devices */ -+ struct phy *phy_dp; -+ struct phy *phy_u3; -+}; -+ -+static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = { -+ /* voltage swing 0, pre-emphasis 0->3 */ -+ { -+ { 0x20, 0x10, 0x42, 0xe5 }, -+ { 0x26, 0x14, 0x42, 0xe5 }, -+ { 0x29, 0x18, 0x42, 0xe5 }, -+ { 0x2b, 0x1c, 0x43, 0xe7 }, -+ }, -+ -+ /* voltage swing 1, pre-emphasis 0->2 */ -+ { -+ { 0x23, 0x10, 0x42, 0xe7 }, -+ { 0x2a, 0x17, 0x43, 0xe7 }, -+ { 0x2b, 0x1a, 0x43, 0xe7 }, -+ }, -+ -+ /* voltage swing 2, pre-emphasis 0->1 */ -+ { -+ { 0x27, 0x10, 0x42, 0xe7 }, -+ { 0x2b, 0x17, 0x43, 0xe7 }, -+ }, -+ -+ /* voltage swing 3, pre-emphasis 0 */ -+ { -+ { 0x29, 0x10, 0x43, 0xe7 }, -+ }, -+}; -+ -+static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = { -+ /* voltage swing 0, pre-emphasis 0->3 */ -+ { -+ { 0x20, 0x10, 0x42, 0xe5 }, -+ { 0x26, 0x14, 0x42, 0xe5 }, -+ { 0x29, 0x18, 0x42, 0xe5 }, -+ { 0x2b, 0x1c, 0x43, 0xe7 }, -+ }, -+ -+ /* voltage swing 1, pre-emphasis 0->2 */ -+ { -+ { 0x23, 0x10, 0x42, 0xe7 }, -+ { 0x2a, 0x17, 0x43, 0xe7 }, -+ { 0x2b, 0x1a, 0x43, 0xe7 }, -+ }, -+ -+ /* voltage swing 2, pre-emphasis 0->1 */ -+ { -+ { 0x27, 0x10, 0x43, 0x67 }, -+ { 0x2b, 0x17, 0x43, 0xe7 }, -+ }, -+ -+ /* voltage swing 3, pre-emphasis 0 */ -+ { -+ { 0x29, 0x10, 0x43, 0xe7 }, -+ }, -+}; -+ -+static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = { -+ /* voltage swing 0, pre-emphasis 0->3 */ -+ { -+ { 0x21, 0x10, 0x42, 0xe5 }, -+ { 0x26, 0x14, 0x42, 0xe5 }, -+ { 0x26, 0x16, 0x43, 0xe5 }, -+ { 0x2a, 0x19, 0x43, 0xe7 }, -+ }, -+ -+ /* voltage swing 1, pre-emphasis 0->2 */ -+ { -+ { 0x24, 0x10, 0x42, 0xe7 }, -+ { 0x2a, 0x17, 0x43, 0xe7 }, -+ { 0x2b, 0x1a, 0x43, 0xe7 }, -+ }, -+ -+ /* voltage swing 2, pre-emphasis 0->1 */ -+ { -+ { 0x28, 0x10, 0x42, 0xe7 }, -+ { 0x2b, 0x17, 0x43, 0xe7 }, -+ }, -+ -+ /* voltage swing 3, pre-emphasis 0 */ -+ { -+ { 0x28, 0x10, 0x43, 0xe7 }, -+ }, -+}; -+ -+static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = { -+ /* voltage swing 0, pre-emphasis 0->3 */ -+ { -+ { 0x21, 0x10, 0x42, 0xe5 }, -+ { 0x26, 0x14, 0x42, 0xe5 }, -+ { 0x26, 0x16, 0x43, 0xe5 }, -+ { 0x29, 0x18, 0x43, 0xe7 }, -+ }, -+ -+ /* voltage swing 1, pre-emphasis 0->2 */ -+ { -+ { 0x24, 0x10, 0x42, 0xe7 }, -+ { 0x2a, 0x18, 0x43, 0xe7 }, -+ { 0x2b, 0x1b, 0x43, 0xe7 } -+ }, -+ -+ /* voltage swing 2, pre-emphasis 0->1 */ -+ { -+ { 0x27, 0x10, 0x42, 0xe7 }, -+ { 0x2b, 0x18, 0x43, 0xe7 } -+ }, -+ -+ /* voltage swing 3, pre-emphasis 0 */ -+ { -+ { 0x28, 0x10, 0x43, 0xe7 }, -+ }, -+}; -+ -+static const struct reg_sequence rk_udphy_24m_refclk_cfg[] = { -+ {0x0090, 0x68}, {0x0094, 0x68}, -+ {0x0128, 0x24}, {0x012c, 0x44}, -+ {0x0130, 0x3f}, {0x0134, 0x44}, -+ {0x015c, 0xa9}, {0x0160, 0x71}, -+ {0x0164, 0x71}, {0x0168, 0xa9}, -+ {0x0174, 0xa9}, {0x0178, 0x71}, -+ {0x017c, 0x71}, {0x0180, 0xa9}, -+ {0x018c, 0x41}, {0x0190, 0x00}, -+ {0x0194, 0x05}, {0x01ac, 0x2a}, -+ {0x01b0, 0x17}, {0x01b4, 0x17}, -+ {0x01b8, 0x2a}, {0x01c8, 0x04}, -+ {0x01cc, 0x08}, {0x01d0, 0x08}, -+ {0x01d4, 0x04}, {0x01d8, 0x20}, -+ {0x01dc, 0x01}, {0x01e0, 0x09}, -+ {0x01e4, 0x03}, {0x01f0, 0x29}, -+ {0x01f4, 0x02}, {0x01f8, 0x02}, -+ {0x01fc, 0x29}, {0x0208, 0x2a}, -+ {0x020c, 0x17}, {0x0210, 0x17}, -+ {0x0214, 0x2a}, {0x0224, 0x20}, -+ {0x03f0, 0x0a}, {0x03f4, 0x07}, -+ {0x03f8, 0x07}, {0x03fc, 0x0c}, -+ {0x0404, 0x12}, {0x0408, 0x1a}, -+ {0x040c, 0x1a}, {0x0410, 0x3f}, -+ {0x0ce0, 0x68}, {0x0ce8, 0xd0}, -+ {0x0cf0, 0x87}, {0x0cf8, 0x70}, -+ {0x0d00, 0x70}, {0x0d08, 0xa9}, -+ {0x1ce0, 0x68}, {0x1ce8, 0xd0}, -+ {0x1cf0, 0x87}, {0x1cf8, 0x70}, -+ {0x1d00, 0x70}, {0x1d08, 0xa9}, -+ {0x0a3c, 0xd0}, {0x0a44, 0xd0}, -+ {0x0a48, 0x01}, {0x0a4c, 0x0d}, -+ {0x0a54, 0xe0}, {0x0a5c, 0xe0}, -+ {0x0a64, 0xa8}, {0x1a3c, 0xd0}, -+ {0x1a44, 0xd0}, {0x1a48, 0x01}, -+ {0x1a4c, 0x0d}, {0x1a54, 0xe0}, -+ {0x1a5c, 0xe0}, {0x1a64, 0xa8} -+}; -+ -+static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = { -+ {0x0830, 0x07}, {0x085c, 0x80}, -+ {0x1030, 0x07}, {0x105c, 0x80}, -+ {0x1830, 0x07}, {0x185c, 0x80}, -+ {0x2030, 0x07}, {0x205c, 0x80}, -+ {0x0228, 0x38}, {0x0104, 0x44}, -+ {0x0248, 0x44}, {0x038c, 0x02}, -+ {0x0878, 0x04}, {0x1878, 0x04}, -+ {0x0898, 0x77}, {0x1898, 0x77}, -+ {0x0054, 0x01}, {0x00e0, 0x38}, -+ {0x0060, 0x24}, {0x0064, 0x77}, -+ {0x0070, 0x76}, {0x0234, 0xe8}, -+ {0x0af4, 0x15}, {0x1af4, 0x15}, -+ {0x081c, 0xe5}, {0x181c, 0xe5}, -+ {0x099c, 0x48}, {0x199c, 0x48}, -+ {0x09a4, 0x07}, {0x09a8, 0x22}, -+ {0x19a4, 0x07}, {0x19a8, 0x22}, -+ {0x09b8, 0x3e}, {0x19b8, 0x3e}, -+ {0x09e4, 0x02}, {0x19e4, 0x02}, -+ {0x0a34, 0x1e}, {0x1a34, 0x1e}, -+ {0x0a98, 0x2f}, {0x1a98, 0x2f}, -+ {0x0c30, 0x0e}, {0x0c48, 0x06}, -+ {0x1c30, 0x0e}, {0x1c48, 0x06}, -+ {0x028c, 0x18}, {0x0af0, 0x00}, -+ {0x1af0, 0x00} -+}; -+ -+static const struct reg_sequence rk_udphy_init_sequence[] = { -+ {0x0104, 0x44}, {0x0234, 0xe8}, -+ {0x0248, 0x44}, {0x028c, 0x18}, -+ {0x081c, 0xe5}, {0x0878, 0x00}, -+ {0x0994, 0x1c}, {0x0af0, 0x00}, -+ {0x181c, 0xe5}, {0x1878, 0x00}, -+ {0x1994, 0x1c}, {0x1af0, 0x00}, -+ {0x0428, 0x60}, {0x0d58, 0x33}, -+ {0x1d58, 0x33}, {0x0990, 0x74}, -+ {0x0d64, 0x17}, {0x08c8, 0x13}, -+ {0x1990, 0x74}, {0x1d64, 0x17}, -+ {0x18c8, 0x13}, {0x0d90, 0x40}, -+ {0x0da8, 0x40}, {0x0dc0, 0x40}, -+ {0x0dd8, 0x40}, {0x1d90, 0x40}, -+ {0x1da8, 0x40}, {0x1dc0, 0x40}, -+ {0x1dd8, 0x40}, {0x03c0, 0x30}, -+ {0x03c4, 0x06}, {0x0e10, 0x00}, -+ {0x1e10, 0x00}, {0x043c, 0x0f}, -+ {0x0d2c, 0xff}, {0x1d2c, 0xff}, -+ {0x0d34, 0x0f}, {0x1d34, 0x0f}, -+ {0x08fc, 0x2a}, {0x0914, 0x28}, -+ {0x0a30, 0x03}, {0x0e38, 0x03}, -+ {0x0ecc, 0x27}, {0x0ed0, 0x22}, -+ {0x0ed4, 0x26}, {0x18fc, 0x2a}, -+ {0x1914, 0x28}, {0x1a30, 0x03}, -+ {0x1e38, 0x03}, {0x1ecc, 0x27}, -+ {0x1ed0, 0x22}, {0x1ed4, 0x26}, -+ {0x0048, 0x0f}, {0x0060, 0x3c}, -+ {0x0064, 0xf7}, {0x006c, 0x20}, -+ {0x0070, 0x7d}, {0x0074, 0x68}, -+ {0x0af4, 0x1a}, {0x1af4, 0x1a}, -+ {0x0440, 0x3f}, {0x10d4, 0x08}, -+ {0x20d4, 0x08}, {0x00d4, 0x30}, -+ {0x0024, 0x6e}, -+}; -+ -+static inline int rk_udphy_grfreg_write(struct regmap *base, -+ const struct rk_udphy_grf_reg *reg, bool en) -+{ -+ return regmap_write(base, reg->offset, en ? reg->enable : reg->disable); -+} -+ -+static int rk_udphy_clk_init(struct rk_udphy *udphy, struct device *dev) -+{ -+ int i; -+ -+ udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks); -+ if (udphy->num_clks < 1) -+ return -ENODEV; -+ -+ /* used for configure phy reference clock frequency */ -+ for (i = 0; i < udphy->num_clks; i++) { -+ if (!strncmp(udphy->clks[i].id, "refclk", 6)) { -+ udphy->refclk = udphy->clks[i].clk; -+ break; -+ } -+ } -+ -+ if (!udphy->refclk) -+ return dev_err_probe(udphy->dev, -EINVAL, "no refclk found\n"); -+ -+ return 0; -+} -+ -+static int rk_udphy_reset_assert_all(struct rk_udphy *udphy) -+{ -+ return reset_control_bulk_assert(udphy->num_rsts, udphy->rsts); -+} -+ -+static int rk_udphy_reset_deassert_all(struct rk_udphy *udphy) -+{ -+ return reset_control_bulk_deassert(udphy->num_rsts, udphy->rsts); -+} -+ -+static int rk_udphy_reset_deassert(struct rk_udphy *udphy, char *name) -+{ -+ struct reset_control_bulk_data *list = udphy->rsts; -+ int idx; -+ -+ for (idx = 0; idx < udphy->num_rsts; idx++) { -+ if (!strcmp(list[idx].id, name)) -+ return reset_control_deassert(list[idx].rstc); -+ } -+ -+ return -EINVAL; -+} -+ -+static int rk_udphy_reset_init(struct rk_udphy *udphy, struct device *dev) -+{ -+ const struct rk_udphy_cfg *cfg = udphy->cfgs; -+ int idx; -+ -+ udphy->num_rsts = cfg->num_rsts; -+ udphy->rsts = devm_kcalloc(dev, udphy->num_rsts, -+ sizeof(*udphy->rsts), GFP_KERNEL); -+ if (!udphy->rsts) -+ return -ENOMEM; -+ -+ for (idx = 0; idx < cfg->num_rsts; idx++) -+ udphy->rsts[idx].id = cfg->rst_list[idx]; -+ -+ return devm_reset_control_bulk_get_exclusive(dev, cfg->num_rsts, -+ udphy->rsts); -+} -+ -+static void rk_udphy_u3_port_disable(struct rk_udphy *udphy, u8 disable) -+{ -+ const struct rk_udphy_cfg *cfg = udphy->cfgs; -+ const struct rk_udphy_grf_reg *preg; -+ -+ preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; -+ rk_udphy_grfreg_write(udphy->usbgrf, preg, disable); -+} -+ -+static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable) -+{ -+ const struct rk_udphy_cfg *cfg = udphy->cfgs; -+ -+ rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); -+ rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); -+} -+ -+/* -+ * In usb/dp combo phy driver, here are 2 ways to mapping lanes. -+ * -+ * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping) -+ * --------------------------------------------------------------------------- -+ * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3 -+ * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) -+ * C/E(Normal) dpln3 dpln2 dpln0 dpln1 -+ * C/E(Flip ) dpln0 dpln1 dpln3 dpln2 -+ * D/F(Normal) usbrx usbtx dpln0 dpln1 -+ * D/F(Flip ) dpln0 dpln1 usbrx usbtx -+ * A(Normal ) dpln3 dpln1 dpln2 dpln0 -+ * A(Flip ) dpln2 dpln0 dpln3 dpln1 -+ * B(Normal ) usbrx usbtx dpln1 dpln0 -+ * B(Flip ) dpln1 dpln0 usbrx usbtx -+ * --------------------------------------------------------------------------- -+ * -+ * 2 Mapping the lanes in dtsi -+ * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = ; -+ * sample as follow: -+ * --------------------------------------------------------------------------- -+ * B11-B10 A2-A3 A11-A10 B2-B3 -+ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) -+ * <0 1 2 3> dpln0 dpln1 dpln2 dpln3 -+ * <2 3 0 1> dpln2 dpln3 dpln0 dpln1 -+ * --------------------------------------------------------------------------- -+ * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = ; -+ * sample as follow: -+ * --------------------------------------------------------------------------- -+ * B11-B10 A2-A3 A11-A10 B2-B3 -+ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) -+ * <0 1> dpln0 dpln1 usbrx usbtx -+ * <2 3> usbrx usbtx dpln0 dpln1 -+ * --------------------------------------------------------------------------- -+ */ -+ -+static void rk_udphy_dplane_select(struct rk_udphy *udphy) -+{ -+ const struct rk_udphy_cfg *cfg = udphy->cfgs; -+ u32 value = 0; -+ -+ switch (udphy->mode) { -+ case UDPHY_MODE_DP: -+ value |= 2 << udphy->dp_lane_sel[2] * 2; -+ value |= 3 << udphy->dp_lane_sel[3] * 2; -+ fallthrough; -+ -+ case UDPHY_MODE_DP_USB: -+ value |= 0 << udphy->dp_lane_sel[0] * 2; -+ value |= 1 << udphy->dp_lane_sel[1] * 2; -+ break; -+ -+ case UDPHY_MODE_USB: -+ break; -+ -+ default: -+ break; -+ } -+ -+ regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg, -+ ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) | -+ FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | -+ FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); -+} -+ -+static int rk_udphy_dplane_get(struct rk_udphy *udphy) -+{ -+ int dp_lanes; -+ -+ switch (udphy->mode) { -+ case UDPHY_MODE_DP: -+ dp_lanes = 4; -+ break; -+ -+ case UDPHY_MODE_DP_USB: -+ dp_lanes = 2; -+ break; -+ -+ case UDPHY_MODE_USB: -+ default: -+ dp_lanes = 0; -+ break; -+ } -+ -+ return dp_lanes; -+} -+ -+static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes) -+{ -+ u32 val = 0; -+ int i; -+ -+ for (i = 0; i < dp_lanes; i++) -+ val |= BIT(udphy->dp_lane_sel[i]); -+ -+ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL, -+ FIELD_PREP(CMN_DP_LANE_EN_ALL, val)); -+ -+ if (!dp_lanes) -+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, -+ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); -+} -+ -+static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd) -+{ -+ const struct rk_udphy_cfg *cfg = udphy->cfgs; -+ -+ udphy->dp_sink_hpd_sel = true; -+ udphy->dp_sink_hpd_cfg = hpd; -+ -+ if (!udphy->dp_in_use) -+ return; -+ -+ rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd); -+} -+ -+static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy) -+{ -+ if (udphy->flip) { -+ udphy->dp_lane_sel[0] = 0; -+ udphy->dp_lane_sel[1] = 1; -+ udphy->dp_lane_sel[2] = 3; -+ udphy->dp_lane_sel[3] = 2; -+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; -+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; -+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; -+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; -+ udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; -+ udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; -+ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1); -+ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); -+ } else { -+ udphy->dp_lane_sel[0] = 2; -+ udphy->dp_lane_sel[1] = 3; -+ udphy->dp_lane_sel[2] = 1; -+ udphy->dp_lane_sel[3] = 0; -+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; -+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; -+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; -+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; -+ udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; -+ udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; -+ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); -+ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1); -+ } -+ -+ udphy->mode = UDPHY_MODE_DP_USB; -+} -+ -+static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw, -+ enum typec_orientation orien) -+{ -+ struct rk_udphy *udphy = typec_switch_get_drvdata(sw); -+ -+ mutex_lock(&udphy->mutex); -+ -+ if (orien == TYPEC_ORIENTATION_NONE) { -+ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); -+ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); -+ /* unattached */ -+ rk_udphy_usb_bvalid_enable(udphy, false); -+ goto unlock_ret; -+ } -+ -+ udphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false; -+ rk_udphy_set_typec_default_mapping(udphy); -+ rk_udphy_usb_bvalid_enable(udphy, true); -+ -+unlock_ret: -+ mutex_unlock(&udphy->mutex); -+ return 0; -+} -+ -+static void rk_udphy_orien_switch_unregister(void *data) -+{ -+ struct rk_udphy *udphy = data; -+ -+ typec_switch_unregister(udphy->sw); -+} -+ -+static int rk_udphy_setup_orien_switch(struct rk_udphy *udphy) -+{ -+ struct typec_switch_desc sw_desc = { }; -+ -+ sw_desc.drvdata = udphy; -+ sw_desc.fwnode = dev_fwnode(udphy->dev); -+ sw_desc.set = rk_udphy_orien_sw_set; -+ -+ udphy->sw = typec_switch_register(udphy->dev, &sw_desc); -+ if (IS_ERR(udphy->sw)) { -+ dev_err(udphy->dev, "Error register typec orientation switch: %ld\n", -+ PTR_ERR(udphy->sw)); -+ return PTR_ERR(udphy->sw); -+ } -+ -+ return devm_add_action_or_reset(udphy->dev, -+ rk_udphy_orien_switch_unregister, udphy); -+} -+ -+static int rk_udphy_refclk_set(struct rk_udphy *udphy) -+{ -+ unsigned long rate; -+ int ret; -+ -+ /* configure phy reference clock */ -+ rate = clk_get_rate(udphy->refclk); -+ dev_dbg(udphy->dev, "refclk freq %ld\n", rate); -+ -+ switch (rate) { -+ case 24000000: -+ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_24m_refclk_cfg, -+ ARRAY_SIZE(rk_udphy_24m_refclk_cfg)); -+ if (ret) -+ return ret; -+ break; -+ -+ case 26000000: -+ /* register default is 26MHz */ -+ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_26m_refclk_cfg, -+ ARRAY_SIZE(rk_udphy_26m_refclk_cfg)); -+ if (ret) -+ return ret; -+ break; -+ -+ default: -+ dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int rk_udphy_status_check(struct rk_udphy *udphy) -+{ -+ unsigned int val; -+ int ret; -+ -+ /* LCPLL check */ -+ if (udphy->mode & UDPHY_MODE_USB) { -+ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET, -+ val, (val & CMN_ANA_LCPLL_AFC_DONE) && -+ (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000); -+ if (ret) { -+ dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); -+ /* -+ * If earlier software (U-Boot) enabled USB once already -+ * the PLL may have problems locking on the first try. -+ * It will be successful on the second try, so for the -+ * time being a -EPROBE_DEFER will solve the issue. -+ * -+ * This requires further investigation to understand the -+ * root cause, especially considering that the driver is -+ * asserting all reset lines at probe time. -+ */ -+ return -EPROBE_DEFER; -+ } -+ -+ if (!udphy->flip) { -+ ret = regmap_read_poll_timeout(udphy->pma_regmap, -+ TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val, -+ val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, -+ 200, 100000); -+ if (ret) -+ dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); -+ } else { -+ ret = regmap_read_poll_timeout(udphy->pma_regmap, -+ TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val, -+ val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, -+ 200, 100000); -+ if (ret) -+ dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); -+ } -+ } -+ -+ return 0; -+} -+ -+static int rk_udphy_init(struct rk_udphy *udphy) -+{ -+ const struct rk_udphy_cfg *cfg = udphy->cfgs; -+ int ret; -+ -+ rk_udphy_reset_assert_all(udphy); -+ usleep_range(10000, 11000); -+ -+ /* enable rx lfps for usb */ -+ if (udphy->mode & UDPHY_MODE_USB) -+ rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); -+ -+ /* Step 1: power on pma and deassert apb rstn */ -+ rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); -+ -+ rk_udphy_reset_deassert(udphy, "pma_apb"); -+ rk_udphy_reset_deassert(udphy, "pcs_apb"); -+ -+ /* Step 2: set init sequence and phy refclk */ -+ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_init_sequence, -+ ARRAY_SIZE(rk_udphy_init_sequence)); -+ if (ret) { -+ dev_err(udphy->dev, "init sequence set error %d\n", ret); -+ goto assert_resets; -+ } -+ -+ ret = rk_udphy_refclk_set(udphy); -+ if (ret) { -+ dev_err(udphy->dev, "refclk set error %d\n", ret); -+ goto assert_resets; -+ } -+ -+ /* Step 3: configure lane mux */ -+ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, -+ CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, -+ FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | -+ FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | -+ FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | -+ FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | -+ FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); -+ -+ /* Step 4: deassert init rstn and wait for 200ns from datasheet */ -+ if (udphy->mode & UDPHY_MODE_USB) -+ rk_udphy_reset_deassert(udphy, "init"); -+ -+ if (udphy->mode & UDPHY_MODE_DP) { -+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, -+ CMN_DP_INIT_RSTN, -+ FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); -+ } -+ -+ udelay(1); -+ -+ /* Step 5: deassert cmn/lane rstn */ -+ if (udphy->mode & UDPHY_MODE_USB) { -+ rk_udphy_reset_deassert(udphy, "cmn"); -+ rk_udphy_reset_deassert(udphy, "lane"); -+ } -+ -+ /* Step 6: wait for lock done of pll */ -+ ret = rk_udphy_status_check(udphy); -+ if (ret) -+ goto assert_resets; -+ -+ return 0; -+ -+assert_resets: -+ rk_udphy_reset_assert_all(udphy); -+ return ret; -+} -+ -+static int rk_udphy_setup(struct rk_udphy *udphy) -+{ -+ int ret; -+ -+ ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); -+ if (ret) { -+ dev_err(udphy->dev, "failed to enable clk\n"); -+ return ret; -+ } -+ -+ ret = rk_udphy_init(udphy); -+ if (ret) { -+ dev_err(udphy->dev, "failed to init combophy\n"); -+ clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void rk_udphy_disable(struct rk_udphy *udphy) -+{ -+ clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); -+ rk_udphy_reset_assert_all(udphy); -+} -+ -+static int rk_udphy_parse_lane_mux_data(struct rk_udphy *udphy) -+{ -+ int ret, i, num_lanes; -+ -+ num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux"); -+ if (num_lanes < 0) { -+ dev_dbg(udphy->dev, "no dp-lane-mux, following dp alt mode\n"); -+ udphy->mode = UDPHY_MODE_USB; -+ return 0; -+ } -+ -+ if (num_lanes != 2 && num_lanes != 4) -+ return dev_err_probe(udphy->dev, -EINVAL, -+ "invalid number of lane mux\n"); -+ -+ ret = device_property_read_u32_array(udphy->dev, "rockchip,dp-lane-mux", -+ udphy->dp_lane_sel, num_lanes); -+ if (ret) -+ return dev_err_probe(udphy->dev, ret, "get dp lane mux failed\n"); -+ -+ for (i = 0; i < num_lanes; i++) { -+ int j; -+ -+ if (udphy->dp_lane_sel[i] > 3) -+ return dev_err_probe(udphy->dev, -EINVAL, -+ "lane mux between 0 and 3, exceeding the range\n"); -+ -+ udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; -+ -+ for (j = i + 1; j < num_lanes; j++) { -+ if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) -+ return dev_err_probe(udphy->dev, -EINVAL, -+ "set repeat lane mux value\n"); -+ } -+ } -+ -+ udphy->mode = UDPHY_MODE_DP; -+ if (num_lanes == 2) { -+ udphy->mode |= UDPHY_MODE_USB; -+ udphy->flip = (udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP); -+ } -+ -+ return 0; -+} -+ -+static int rk_udphy_get_initial_status(struct rk_udphy *udphy) -+{ -+ int ret; -+ u32 value; -+ -+ ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); -+ if (ret) { -+ dev_err(udphy->dev, "failed to enable clk\n"); -+ return ret; -+ } -+ -+ rk_udphy_reset_deassert_all(udphy); -+ -+ regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value); -+ if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL, value)) -+ udphy->status = UDPHY_MODE_DP; -+ else -+ rk_udphy_disable(udphy); -+ -+ return 0; -+} -+ -+static int rk_udphy_parse_dt(struct rk_udphy *udphy) -+{ -+ struct device *dev = udphy->dev; -+ struct device_node *np = dev_of_node(dev); -+ enum usb_device_speed maximum_speed; -+ int ret; -+ -+ udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf"); -+ if (IS_ERR(udphy->u2phygrf)) -+ return dev_err_probe(dev, PTR_ERR(udphy->u2phygrf), "failed to get u2phy-grf\n"); -+ -+ udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf"); -+ if (IS_ERR(udphy->udphygrf)) -+ return dev_err_probe(dev, PTR_ERR(udphy->udphygrf), "failed to get usbdpphy-grf\n"); -+ -+ udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf"); -+ if (IS_ERR(udphy->usbgrf)) -+ return dev_err_probe(dev, PTR_ERR(udphy->usbgrf), "failed to get usb-grf\n"); -+ -+ udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf"); -+ if (IS_ERR(udphy->vogrf)) -+ return dev_err_probe(dev, PTR_ERR(udphy->vogrf), "failed to get vo-grf\n"); -+ -+ ret = rk_udphy_parse_lane_mux_data(udphy); -+ if (ret) -+ return ret; -+ -+ udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW); -+ if (IS_ERR(udphy->sbu1_dc_gpio)) -+ return PTR_ERR(udphy->sbu1_dc_gpio); -+ -+ udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW); -+ if (IS_ERR(udphy->sbu2_dc_gpio)) -+ return PTR_ERR(udphy->sbu2_dc_gpio); -+ -+ if (device_property_present(dev, "maximum-speed")) { -+ maximum_speed = usb_get_maximum_speed(dev); -+ udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false; -+ } -+ -+ ret = rk_udphy_clk_init(udphy, dev); -+ if (ret) -+ return ret; -+ -+ return rk_udphy_reset_init(udphy, dev); -+} -+ -+static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode) -+{ -+ int ret; -+ -+ if (!(udphy->mode & mode)) { -+ dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); -+ return 0; -+ } -+ -+ if (udphy->status == UDPHY_MODE_NONE) { -+ udphy->mode_change = false; -+ ret = rk_udphy_setup(udphy); -+ if (ret) -+ return ret; -+ -+ if (udphy->mode & UDPHY_MODE_USB) -+ rk_udphy_u3_port_disable(udphy, false); -+ } else if (udphy->mode_change) { -+ udphy->mode_change = false; -+ udphy->status = UDPHY_MODE_NONE; -+ if (udphy->mode == UDPHY_MODE_DP) -+ rk_udphy_u3_port_disable(udphy, true); -+ -+ rk_udphy_disable(udphy); -+ ret = rk_udphy_setup(udphy); -+ if (ret) -+ return ret; -+ } -+ -+ udphy->status |= mode; -+ -+ return 0; -+} -+ -+static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode) -+{ -+ if (!(udphy->mode & mode)) { -+ dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); -+ return; -+ } -+ -+ if (!udphy->status) -+ return; -+ -+ udphy->status &= ~mode; -+ -+ if (udphy->status == UDPHY_MODE_NONE) -+ rk_udphy_disable(udphy); -+} -+ -+static int rk_udphy_dp_phy_init(struct phy *phy) -+{ -+ struct rk_udphy *udphy = phy_get_drvdata(phy); -+ -+ mutex_lock(&udphy->mutex); -+ -+ udphy->dp_in_use = true; -+ rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); -+ -+ mutex_unlock(&udphy->mutex); -+ -+ return 0; -+} -+ -+static int rk_udphy_dp_phy_exit(struct phy *phy) -+{ -+ struct rk_udphy *udphy = phy_get_drvdata(phy); -+ -+ mutex_lock(&udphy->mutex); -+ udphy->dp_in_use = false; -+ mutex_unlock(&udphy->mutex); -+ return 0; -+} -+ -+static int rk_udphy_dp_phy_power_on(struct phy *phy) -+{ -+ struct rk_udphy *udphy = phy_get_drvdata(phy); -+ int ret, dp_lanes; -+ -+ mutex_lock(&udphy->mutex); -+ -+ dp_lanes = rk_udphy_dplane_get(udphy); -+ phy_set_bus_width(phy, dp_lanes); -+ -+ ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP); -+ if (ret) -+ goto unlock; -+ -+ rk_udphy_dplane_enable(udphy, dp_lanes); -+ -+ rk_udphy_dplane_select(udphy); -+ -+unlock: -+ mutex_unlock(&udphy->mutex); -+ /* -+ * If data send by aux channel too fast after phy power on, -+ * the aux may be not ready which will cause aux error. Adding -+ * delay to avoid this issue. -+ */ -+ usleep_range(10000, 11000); -+ return ret; -+} -+ -+static int rk_udphy_dp_phy_power_off(struct phy *phy) -+{ -+ struct rk_udphy *udphy = phy_get_drvdata(phy); -+ -+ mutex_lock(&udphy->mutex); -+ rk_udphy_dplane_enable(udphy, 0); -+ rk_udphy_power_off(udphy, UDPHY_MODE_DP); -+ mutex_unlock(&udphy->mutex); -+ -+ return 0; -+} -+ -+static int rk_udphy_dp_phy_verify_link_rate(unsigned int link_rate) -+{ -+ switch (link_rate) { -+ case 1620: -+ case 2700: -+ case 5400: -+ case 8100: -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int rk_udphy_dp_phy_verify_config(struct rk_udphy *udphy, -+ struct phy_configure_opts_dp *dp) -+{ -+ int i, ret; -+ -+ /* If changing link rate was required, verify it's supported. */ -+ ret = rk_udphy_dp_phy_verify_link_rate(dp->link_rate); -+ if (ret) -+ return ret; -+ -+ /* Verify lane count. */ -+ switch (dp->lanes) { -+ case 1: -+ case 2: -+ case 4: -+ /* valid lane count. */ -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ /* -+ * If changing voltages is required, check swing and pre-emphasis -+ * levels, per-lane. -+ */ -+ if (dp->set_voltages) { -+ /* Lane count verified previously. */ -+ for (i = 0; i < dp->lanes; i++) { -+ if (dp->voltage[i] > 3 || dp->pre[i] > 3) -+ return -EINVAL; -+ -+ /* -+ * Sum of voltage swing and pre-emphasis levels cannot -+ * exceed 3. -+ */ -+ if (dp->voltage[i] + dp->pre[i] > 3) -+ return -EINVAL; -+ } -+ } -+ -+ return 0; -+} -+ -+static void rk_udphy_dp_set_voltage(struct rk_udphy *udphy, u8 bw, -+ u32 voltage, u32 pre, u32 lane) -+{ -+ const struct rk_udphy_cfg *cfg = udphy->cfgs; -+ const struct rk_udphy_dp_tx_drv_ctrl (*dp_ctrl)[4]; -+ u32 offset = 0x800 * lane; -+ u32 val; -+ -+ if (udphy->mux) -+ dp_ctrl = cfg->dp_tx_ctrl_cfg_typec[bw]; -+ else -+ dp_ctrl = cfg->dp_tx_ctrl_cfg[bw]; -+ -+ val = dp_ctrl[voltage][pre].trsv_reg0204; -+ regmap_write(udphy->pma_regmap, 0x0810 + offset, val); -+ -+ val = dp_ctrl[voltage][pre].trsv_reg0205; -+ regmap_write(udphy->pma_regmap, 0x0814 + offset, val); -+ -+ val = dp_ctrl[voltage][pre].trsv_reg0206; -+ regmap_write(udphy->pma_regmap, 0x0818 + offset, val); -+ -+ val = dp_ctrl[voltage][pre].trsv_reg0207; -+ regmap_write(udphy->pma_regmap, 0x081c + offset, val); -+} -+ -+static int rk_udphy_dp_phy_configure(struct phy *phy, -+ union phy_configure_opts *opts) -+{ -+ struct rk_udphy *udphy = phy_get_drvdata(phy); -+ struct phy_configure_opts_dp *dp = &opts->dp; -+ u32 i, val, lane; -+ int ret; -+ -+ ret = rk_udphy_dp_phy_verify_config(udphy, dp); -+ if (ret) -+ return ret; -+ -+ if (dp->set_rate) { -+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, -+ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); -+ -+ switch (dp->link_rate) { -+ case 1620: -+ udphy->bw = DP_BW_RBR; -+ break; -+ -+ case 2700: -+ udphy->bw = DP_BW_HBR; -+ break; -+ -+ case 5400: -+ udphy->bw = DP_BW_HBR2; -+ break; -+ -+ case 8100: -+ udphy->bw = DP_BW_HBR3; -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW, -+ FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); -+ regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN, -+ FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); -+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN, -+ FIELD_PREP(CMN_DP_CMN_RSTN, 0x1)); -+ -+ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val, -+ FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) && -+ FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val), -+ 0, 1000); -+ if (ret) { -+ dev_err(udphy->dev, "ROPLL is not lock, set_rate failed\n"); -+ return ret; -+ } -+ } -+ -+ if (dp->set_voltages) { -+ for (i = 0; i < dp->lanes; i++) { -+ lane = udphy->dp_lane_sel[i]; -+ switch (dp->link_rate) { -+ case 1620: -+ case 2700: -+ regmap_update_bits(udphy->pma_regmap, -+ TRSV_ANA_TX_CLK_OFFSET_N(lane), -+ LN_ANA_TX_SER_TXCLK_INV, -+ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, -+ udphy->lane_mux_sel[lane])); -+ break; -+ -+ case 5400: -+ case 8100: -+ regmap_update_bits(udphy->pma_regmap, -+ TRSV_ANA_TX_CLK_OFFSET_N(lane), -+ LN_ANA_TX_SER_TXCLK_INV, -+ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0)); -+ break; -+ } -+ -+ rk_udphy_dp_set_voltage(udphy, udphy->bw, dp->voltage[i], -+ dp->pre[i], lane); -+ } -+ } -+ -+ return 0; -+} -+ -+static const struct phy_ops rk_udphy_dp_phy_ops = { -+ .init = rk_udphy_dp_phy_init, -+ .exit = rk_udphy_dp_phy_exit, -+ .power_on = rk_udphy_dp_phy_power_on, -+ .power_off = rk_udphy_dp_phy_power_off, -+ .configure = rk_udphy_dp_phy_configure, -+ .owner = THIS_MODULE, -+}; -+ -+static int rk_udphy_usb3_phy_init(struct phy *phy) -+{ -+ struct rk_udphy *udphy = phy_get_drvdata(phy); -+ int ret; -+ -+ mutex_lock(&udphy->mutex); -+ /* DP only or high-speed, disable U3 port */ -+ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { -+ rk_udphy_u3_port_disable(udphy, true); -+ goto unlock; -+ } -+ -+ ret = rk_udphy_power_on(udphy, UDPHY_MODE_USB); -+ -+unlock: -+ mutex_unlock(&udphy->mutex); -+ return ret; -+} -+ -+static int rk_udphy_usb3_phy_exit(struct phy *phy) -+{ -+ struct rk_udphy *udphy = phy_get_drvdata(phy); -+ -+ mutex_lock(&udphy->mutex); -+ /* DP only or high-speed */ -+ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) -+ goto unlock; -+ -+ rk_udphy_power_off(udphy, UDPHY_MODE_USB); -+ -+unlock: -+ mutex_unlock(&udphy->mutex); -+ return 0; -+} -+ -+static const struct phy_ops rk_udphy_usb3_phy_ops = { -+ .init = rk_udphy_usb3_phy_init, -+ .exit = rk_udphy_usb3_phy_exit, -+ .owner = THIS_MODULE, -+}; -+ -+static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux, -+ struct typec_mux_state *state) -+{ -+ struct rk_udphy *udphy = typec_mux_get_drvdata(mux); -+ u8 mode; -+ -+ mutex_lock(&udphy->mutex); -+ -+ switch (state->mode) { -+ case TYPEC_DP_STATE_C: -+ case TYPEC_DP_STATE_E: -+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; -+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; -+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; -+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; -+ mode = UDPHY_MODE_DP; -+ break; -+ -+ case TYPEC_DP_STATE_D: -+ default: -+ if (udphy->flip) { -+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; -+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; -+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; -+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; -+ } else { -+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; -+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; -+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; -+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; -+ } -+ mode = UDPHY_MODE_DP_USB; -+ break; -+ } -+ -+ if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) { -+ struct typec_displayport_data *data = state->data; -+ -+ if (!data) { -+ rk_udphy_dp_hpd_event_trigger(udphy, false); -+ } else if (data->status & DP_STATUS_IRQ_HPD) { -+ rk_udphy_dp_hpd_event_trigger(udphy, false); -+ usleep_range(750, 800); -+ rk_udphy_dp_hpd_event_trigger(udphy, true); -+ } else if (data->status & DP_STATUS_HPD_STATE) { -+ if (udphy->mode != mode) { -+ udphy->mode = mode; -+ udphy->mode_change = true; -+ } -+ rk_udphy_dp_hpd_event_trigger(udphy, true); -+ } else { -+ rk_udphy_dp_hpd_event_trigger(udphy, false); -+ } -+ } -+ -+ mutex_unlock(&udphy->mutex); -+ return 0; -+} -+ -+static void rk_udphy_typec_mux_unregister(void *data) -+{ -+ struct rk_udphy *udphy = data; -+ -+ typec_mux_unregister(udphy->mux); -+} -+ -+static int rk_udphy_setup_typec_mux(struct rk_udphy *udphy) -+{ -+ struct typec_mux_desc mux_desc = {}; -+ -+ mux_desc.drvdata = udphy; -+ mux_desc.fwnode = dev_fwnode(udphy->dev); -+ mux_desc.set = rk_udphy_typec_mux_set; -+ -+ udphy->mux = typec_mux_register(udphy->dev, &mux_desc); -+ if (IS_ERR(udphy->mux)) { -+ dev_err(udphy->dev, "Error register typec mux: %ld\n", -+ PTR_ERR(udphy->mux)); -+ return PTR_ERR(udphy->mux); -+ } -+ -+ return devm_add_action_or_reset(udphy->dev, rk_udphy_typec_mux_unregister, -+ udphy); -+} -+ -+static const struct regmap_config rk_udphy_pma_regmap_cfg = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .fast_io = true, -+ .max_register = 0x20dc, -+}; -+ -+static struct phy *rk_udphy_phy_xlate(struct device *dev, struct of_phandle_args *args) -+{ -+ struct rk_udphy *udphy = dev_get_drvdata(dev); -+ -+ if (args->args_count == 0) -+ return ERR_PTR(-EINVAL); -+ -+ switch (args->args[0]) { -+ case PHY_TYPE_USB3: -+ return udphy->phy_u3; -+ case PHY_TYPE_DP: -+ return udphy->phy_dp; -+ } -+ -+ return ERR_PTR(-EINVAL); -+} -+ -+static int rk_udphy_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct phy_provider *phy_provider; -+ struct resource *res; -+ struct rk_udphy *udphy; -+ void __iomem *base; -+ int id, ret; -+ -+ udphy = devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL); -+ if (!udphy) -+ return -ENOMEM; -+ -+ udphy->cfgs = device_get_match_data(dev); -+ if (!udphy->cfgs) -+ return dev_err_probe(dev, -EINVAL, "missing match data\n"); -+ -+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ /* find the phy-id from the io address */ -+ udphy->id = -ENODEV; -+ for (id = 0; id < udphy->cfgs->num_phys; id++) { -+ if (res->start == udphy->cfgs->phy_ids[id]) { -+ udphy->id = id; -+ break; -+ } -+ } -+ -+ if (udphy->id < 0) -+ return dev_err_probe(dev, -ENODEV, "no matching device found\n"); -+ -+ udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA, -+ &rk_udphy_pma_regmap_cfg); -+ if (IS_ERR(udphy->pma_regmap)) -+ return PTR_ERR(udphy->pma_regmap); -+ -+ udphy->dev = dev; -+ ret = rk_udphy_parse_dt(udphy); -+ if (ret) -+ return ret; -+ -+ ret = rk_udphy_get_initial_status(udphy); -+ if (ret) -+ return ret; -+ -+ mutex_init(&udphy->mutex); -+ platform_set_drvdata(pdev, udphy); -+ -+ if (device_property_present(dev, "orientation-switch")) { -+ ret = rk_udphy_setup_orien_switch(udphy); -+ if (ret) -+ return ret; -+ } -+ -+ if (device_property_present(dev, "mode-switch")) { -+ ret = rk_udphy_setup_typec_mux(udphy); -+ if (ret) -+ return ret; -+ } -+ -+ udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops); -+ if (IS_ERR(udphy->phy_u3)) { -+ ret = PTR_ERR(udphy->phy_u3); -+ return dev_err_probe(dev, ret, "failed to create USB3 phy\n"); -+ } -+ phy_set_drvdata(udphy->phy_u3, udphy); -+ -+ udphy->phy_dp = devm_phy_create(dev, dev->of_node, &rk_udphy_dp_phy_ops); -+ if (IS_ERR(udphy->phy_dp)) { -+ ret = PTR_ERR(udphy->phy_dp); -+ return dev_err_probe(dev, ret, "failed to create DP phy\n"); -+ } -+ phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy)); -+ udphy->phy_dp->attrs.max_link_rate = 8100; -+ phy_set_drvdata(udphy->phy_dp, udphy); -+ -+ phy_provider = devm_of_phy_provider_register(dev, rk_udphy_phy_xlate); -+ if (IS_ERR(phy_provider)) { -+ ret = PTR_ERR(phy_provider); -+ return dev_err_probe(dev, ret, "failed to register phy provider\n"); -+ } -+ -+ return 0; -+} -+ -+static int __maybe_unused rk_udphy_resume(struct device *dev) -+{ -+ struct rk_udphy *udphy = dev_get_drvdata(dev); -+ -+ if (udphy->dp_sink_hpd_sel) -+ rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); -+ -+ return 0; -+} -+ -+static const struct dev_pm_ops rk_udphy_pm_ops = { -+ SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rk_udphy_resume) -+}; -+ -+static const char * const rk_udphy_rst_list[] = { -+ "init", "cmn", "lane", "pcs_apb", "pma_apb" -+}; -+ -+static const struct rk_udphy_cfg rk3588_udphy_cfgs = { -+ .num_phys = 2, -+ .phy_ids = { -+ 0xfed80000, -+ 0xfed90000, -+ }, -+ .num_rsts = ARRAY_SIZE(rk_udphy_rst_list), -+ .rst_list = rk_udphy_rst_list, -+ .grfcfg = { -+ /* u2phy-grf */ -+ .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0008, 1, 0, 0x2, 0x3), -+ .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0010, 3, 2, 0x2, 0x3), -+ -+ /* usb-grf */ -+ .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x001c, 15, 0, 0x1100, 0x0188), -+ .usb3otg1_cfg = RK_UDPHY_GEN_GRF_REG(0x0034, 15, 0, 0x1100, 0x0188), -+ -+ /* usbdpphy-grf */ -+ .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1), -+ .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1), -+ }, -+ .vogrfcfg = { -+ { -+ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3), -+ .dp_lane_reg = 0x0000, -+ }, -+ { -+ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3), -+ .dp_lane_reg = 0x0008, -+ }, -+ }, -+ .dp_tx_ctrl_cfg = { -+ rk3588_dp_tx_drv_ctrl_rbr_hbr, -+ rk3588_dp_tx_drv_ctrl_rbr_hbr, -+ rk3588_dp_tx_drv_ctrl_hbr2, -+ rk3588_dp_tx_drv_ctrl_hbr3, -+ }, -+ .dp_tx_ctrl_cfg_typec = { -+ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, -+ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, -+ rk3588_dp_tx_drv_ctrl_hbr2, -+ rk3588_dp_tx_drv_ctrl_hbr3, -+ }, -+}; -+ -+static const struct of_device_id rk_udphy_dt_match[] = { -+ { -+ .compatible = "rockchip,rk3588-usbdp-phy", -+ .data = &rk3588_udphy_cfgs -+ }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, rk_udphy_dt_match); -+ -+static struct platform_driver rk_udphy_driver = { -+ .probe = rk_udphy_probe, -+ .driver = { -+ .name = "rockchip-usbdp-phy", -+ .of_match_table = rk_udphy_dt_match, -+ .pm = &rk_udphy_pm_ops, -+ }, -+}; -+module_platform_driver(rk_udphy_driver); -+ -+MODULE_AUTHOR("Frank Wang "); -+MODULE_AUTHOR("Zhang Yubing "); -+MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/rockchip/patches-6.6/032-03-v6.10-phy-rockchip-usbdp-fix-uninitialized-variable.patch b/target/linux/rockchip/patches-6.6/032-03-v6.10-phy-rockchip-usbdp-fix-uninitialized-variable.patch deleted file mode 100644 index 65bd8a7ed8..0000000000 --- a/target/linux/rockchip/patches-6.6/032-03-v6.10-phy-rockchip-usbdp-fix-uninitialized-variable.patch +++ /dev/null @@ -1,35 +0,0 @@ -From c9342d1a351ee1249fa98d936f756299a83d5684 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 16 Apr 2024 16:51:23 +0200 -Subject: [PATCH] phy: rockchip: usbdp: fix uninitialized variable - -The ret variable may not be initialized in rk_udphy_usb3_phy_init(), if -the PHY is not using USB3 mode. - -Since the DisplayPort part is handled separately and the PHY does not -support USB2 (which is routed to another PHY on Rockchip RK3588), the -right exit code for this case is 0. Thus let's initialize the variable -accordingly. - -Fixes: 2f70bbddeb457 ("phy: rockchip: add usbdp combo phy driver") -Reported-by: kernel test robot -Closes: https://lore.kernel.org/oe-kbuild-all/202404141048.qFAYDctQ-lkp@intel.com/ -Signed-off-by: Sebastian Reichel -Reviewed-by: Muhammad Usama Anjum -Link: https://lore.kernel.org/r/20240416145233.94687-1-sebastian.reichel@collabora.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-usbdp.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/phy/rockchip/phy-rockchip-usbdp.c -+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c -@@ -1285,7 +1285,7 @@ static const struct phy_ops rk_udphy_dp_ - static int rk_udphy_usb3_phy_init(struct phy *phy) - { - struct rk_udphy *udphy = phy_get_drvdata(phy); -- int ret; -+ int ret = 0; - - mutex_lock(&udphy->mutex); - /* DP only or high-speed, disable U3 port */ diff --git a/target/linux/rockchip/patches-6.6/032-04-v6.10-phy-rockchip-fix-CONFIG_TYPEC-dependency.patch b/target/linux/rockchip/patches-6.6/032-04-v6.10-phy-rockchip-fix-CONFIG_TYPEC-dependency.patch deleted file mode 100644 index e4c44feda0..0000000000 --- a/target/linux/rockchip/patches-6.6/032-04-v6.10-phy-rockchip-fix-CONFIG_TYPEC-dependency.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 9c79b779643e56d4253bd3ba6998c58c819943af Mon Sep 17 00:00:00 2001 -From: Arnd Bergmann -Date: Mon, 15 Apr 2024 19:42:25 +0200 -Subject: [PATCH] phy: rockchip: fix CONFIG_TYPEC dependency - -The newly added driver causes a warning about missing dependencies -by selecting CONFIG_TYPEC unconditionally: - -WARNING: unmet direct dependencies detected for TYPEC - Depends on [n]: USB_SUPPORT [=n] - Selected by [y]: - - PHY_ROCKCHIP_USBDP [=y] && ARCH_ROCKCHIP [=y] && OF [=y] - -WARNING: unmet direct dependencies detected for USB_COMMON - Depends on [n]: USB_SUPPORT [=n] - Selected by [y]: - - EXTCON_RTK_TYPE_C [=y] && EXTCON [=y] && (ARCH_REALTEK [=y] || COMPILE_TEST [=y]) && TYPEC [=y] - -Since that is a user-visible option, it should not really be selected -in the first place. Replace the 'select' with a 'depends on' as -we have for similar drivers. - -Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver") -Signed-off-by: Arnd Bergmann -Reviewed-by: Heiko Stuebner -Link: https://lore.kernel.org/r/20240415174241.77982-1-arnd@kernel.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/phy/rockchip/Kconfig -+++ b/drivers/phy/rockchip/Kconfig -@@ -119,8 +119,8 @@ config PHY_ROCKCHIP_USB - config PHY_ROCKCHIP_USBDP - tristate "Rockchip USBDP COMBO PHY Driver" - depends on ARCH_ROCKCHIP && OF -+ depends on TYPEC - select GENERIC_PHY -- select TYPEC - help - Enable this to support the Rockchip USB3.0/DP combo PHY with - Samsung IP block. This is required for USB3 support on RK3588. diff --git a/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-Fix-typo-in-function-names.patch b/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-Fix-typo-in-function-names.patch deleted file mode 100644 index 08620d66ec..0000000000 --- a/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-Fix-typo-in-function-names.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 9b6bfad9070a95d19973be17177e5d9220cbbf1f Mon Sep 17 00:00:00 2001 -From: Rick Wertenbroek -Date: Thu, 7 Mar 2024 10:53:18 +0100 -Subject: [PATCH] phy: rockchip: Fix typo in function names - -Several functions had "rochchip" instead of "rockchip" in their name. -Replace "rochchip" by "rockchip". - -Signed-off-By: Rick Wertenbroek -Reviewed-by: Heiko Stuebner -Link: https://lore.kernel.org/r/20240307095318.3651498-1-rick.wertenbroek@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 4 ++-- - drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 12 ++++++------ - 2 files changed, 8 insertions(+), 8 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -@@ -248,7 +248,7 @@ static int rockchip_combphy_exit(struct - return 0; - } - --static const struct phy_ops rochchip_combphy_ops = { -+static const struct phy_ops rockchip_combphy_ops = { - .init = rockchip_combphy_init, - .exit = rockchip_combphy_exit, - .owner = THIS_MODULE, -@@ -367,7 +367,7 @@ static int rockchip_combphy_probe(struct - return ret; - } - -- priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); -+ priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops); - if (IS_ERR(priv->phy)) { - dev_err(dev, "failed to create combphy\n"); - return PTR_ERR(priv->phy); ---- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -@@ -182,7 +182,7 @@ static const struct rockchip_p3phy_ops r - .phy_init = rockchip_p3phy_rk3588_init, - }; - --static int rochchip_p3phy_init(struct phy *phy) -+static int rockchip_p3phy_init(struct phy *phy) - { - struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); - int ret; -@@ -205,7 +205,7 @@ static int rochchip_p3phy_init(struct ph - return ret; - } - --static int rochchip_p3phy_exit(struct phy *phy) -+static int rockchip_p3phy_exit(struct phy *phy) - { - struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); - -@@ -214,9 +214,9 @@ static int rochchip_p3phy_exit(struct ph - return 0; - } - --static const struct phy_ops rochchip_p3phy_ops = { -- .init = rochchip_p3phy_init, -- .exit = rochchip_p3phy_exit, -+static const struct phy_ops rockchip_p3phy_ops = { -+ .init = rockchip_p3phy_init, -+ .exit = rockchip_p3phy_exit, - .set_mode = rockchip_p3phy_set_mode, - .owner = THIS_MODULE, - }; -@@ -275,7 +275,7 @@ static int rockchip_p3phy_probe(struct p - return priv->num_lanes; - } - -- priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); -+ priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops); - if (IS_ERR(priv->phy)) { - dev_err(dev, "failed to create combphy\n"); - return PTR_ERR(priv->phy); diff --git a/target/linux/rockchip/patches-6.6/032-08-v6.10-phy-rockchip-snps-pcie3-add-support-for.patch b/target/linux/rockchip/patches-6.6/032-08-v6.10-phy-rockchip-snps-pcie3-add-support-for.patch deleted file mode 100644 index 61c3e0e53c..0000000000 --- a/target/linux/rockchip/patches-6.6/032-08-v6.10-phy-rockchip-snps-pcie3-add-support-for.patch +++ /dev/null @@ -1,106 +0,0 @@ -From a1fe1eca0d8be69ccc1f3d615e5a529df1c82e66 Mon Sep 17 00:00:00 2001 -From: Niklas Cassel -Date: Fri, 12 Apr 2024 14:58:16 +0200 -Subject: [PATCH] phy: rockchip-snps-pcie3: add support for - rockchip,rx-common-refclk-mode - ->From the RK3588 Technical Reference Manual, Part1, -section 6.19 PCIe3PHY_GRF Register Description: -"rxX_cmn_refclk_mode" -RX common reference clock mode for lane X. This mode should be enabled -only when the far-end and near-end devices are running with a common -reference clock. - -The hardware reset value for this field is 0x1 (enabled). -Note that this register field is only available on RK3588, not on RK3568. - -The link training either fails or is highly unstable (link state will jump -continuously between L0 and recovery) when this mode is enabled while -using an endpoint running in Separate Reference Clock with No SSC (SRNS) -mode or Separate Reference Clock with SSC (SRIS) mode. -(Which is usually the case when using a real SoC as endpoint, e.g. the -RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) - -Add support for the device tree property rockchip,rx-common-refclk-mode, -such that the PCIe PHY can be used in configurations where the Root -Complex and Endpoint are not using a common reference clock. - -Signed-off-by: Niklas Cassel -Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org -Signed-off-by: Vinod Koul ---- - .../phy/rockchip/phy-rockchip-snps-pcie3.c | 37 +++++++++++++++++++ - 1 file changed, 37 insertions(+) - ---- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -@@ -35,11 +35,17 @@ - #define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 - #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 - #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 -+#define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1 0x1004 -+#define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1 0x1104 -+#define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1 0x2004 -+#define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1 0x2104 - #define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0)) - - #define RK3588_BIFURCATION_LANE_0_1 BIT(0) - #define RK3588_BIFURCATION_LANE_2_3 BIT(1) - #define RK3588_LANE_AGGREGATION BIT(2) -+#define RK3588_RX_CMN_REFCLK_MODE_EN ((BIT(7) << 16) | BIT(7)) -+#define RK3588_RX_CMN_REFCLK_MODE_DIS (BIT(7) << 16) - #define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16) - #define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16) - -@@ -60,6 +66,7 @@ struct rockchip_p3phy_priv { - int num_clks; - int num_lanes; - u32 lanes[4]; -+ u32 rx_cmn_refclk_mode[4]; - }; - - struct rockchip_p3phy_ops { -@@ -137,6 +144,19 @@ static int rockchip_p3phy_rk3588_init(st - u8 mode = RK3588_LANE_AGGREGATION; /* default */ - int ret; - -+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1, -+ priv->rx_cmn_refclk_mode[0] ? RK3588_RX_CMN_REFCLK_MODE_EN : -+ RK3588_RX_CMN_REFCLK_MODE_DIS); -+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1, -+ priv->rx_cmn_refclk_mode[1] ? RK3588_RX_CMN_REFCLK_MODE_EN : -+ RK3588_RX_CMN_REFCLK_MODE_DIS); -+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1, -+ priv->rx_cmn_refclk_mode[2] ? RK3588_RX_CMN_REFCLK_MODE_EN : -+ RK3588_RX_CMN_REFCLK_MODE_DIS); -+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1, -+ priv->rx_cmn_refclk_mode[3] ? RK3588_RX_CMN_REFCLK_MODE_EN : -+ RK3588_RX_CMN_REFCLK_MODE_DIS); -+ - /* Deassert PCIe PMA output clamp mode */ - regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); - -@@ -275,6 +295,23 @@ static int rockchip_p3phy_probe(struct p - return priv->num_lanes; - } - -+ ret = of_property_read_variable_u32_array(dev->of_node, -+ "rockchip,rx-common-refclk-mode", -+ priv->rx_cmn_refclk_mode, 1, -+ ARRAY_SIZE(priv->rx_cmn_refclk_mode)); -+ /* -+ * if no rockchip,rx-common-refclk-mode, assume enabled for all lanes in -+ * order to be DT backwards compatible. (Since HW reset val is enabled.) -+ */ -+ if (ret == -EINVAL) { -+ for (int i = 0; i < ARRAY_SIZE(priv->rx_cmn_refclk_mode); i++) -+ priv->rx_cmn_refclk_mode[i] = 1; -+ } else if (ret < 0) { -+ dev_err(dev, "failed to read rockchip,rx-common-refclk-mode property %d\n", -+ ret); -+ return ret; -+ } -+ - priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops); - if (IS_ERR(priv->phy)) { - dev_err(dev, "failed to create combphy\n"); diff --git a/target/linux/rockchip/patches-6.6/035-v6.7-usb-dwc3-add-optional-PHY-interface-clocks.patch b/target/linux/rockchip/patches-6.6/035-v6.7-usb-dwc3-add-optional-PHY-interface-clocks.patch deleted file mode 100644 index 4d358ea219..0000000000 --- a/target/linux/rockchip/patches-6.6/035-v6.7-usb-dwc3-add-optional-PHY-interface-clocks.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 97789b93b792fc97ad4476b79e0f38ffa8e7e0ee Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Fri, 20 Oct 2023 16:11:41 +0200 -Subject: [PATCH] usb: dwc3: add optional PHY interface clocks - -On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and -requires two extra clocks to be enabled. Without these extra clocks -hot-plugging USB devices is broken. - -Signed-off-by: Sebastian Reichel -Acked-by: Thinh Nguyen -Link: https://lore.kernel.org/r/20231020150022.48725-3-sebastian.reichel@collabora.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++ - drivers/usb/dwc3/core.h | 4 ++++ - 2 files changed, 32 insertions(+) - ---- a/drivers/usb/dwc3/core.c -+++ b/drivers/usb/dwc3/core.c -@@ -860,8 +860,20 @@ static int dwc3_clk_enable(struct dwc3 * - if (ret) - goto disable_ref_clk; - -+ ret = clk_prepare_enable(dwc->utmi_clk); -+ if (ret) -+ goto disable_susp_clk; -+ -+ ret = clk_prepare_enable(dwc->pipe_clk); -+ if (ret) -+ goto disable_utmi_clk; -+ - return 0; - -+disable_utmi_clk: -+ clk_disable_unprepare(dwc->utmi_clk); -+disable_susp_clk: -+ clk_disable_unprepare(dwc->susp_clk); - disable_ref_clk: - clk_disable_unprepare(dwc->ref_clk); - disable_bus_clk: -@@ -871,6 +883,8 @@ disable_bus_clk: - - static void dwc3_clk_disable(struct dwc3 *dwc) - { -+ clk_disable_unprepare(dwc->pipe_clk); -+ clk_disable_unprepare(dwc->utmi_clk); - clk_disable_unprepare(dwc->susp_clk); - clk_disable_unprepare(dwc->ref_clk); - clk_disable_unprepare(dwc->bus_clk); -@@ -1886,6 +1900,20 @@ static int dwc3_get_clocks(struct dwc3 * - } - } - -+ /* specific to Rockchip RK3588 */ -+ dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); -+ if (IS_ERR(dwc->utmi_clk)) { -+ return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), -+ "could not get utmi clock\n"); -+ } -+ -+ /* specific to Rockchip RK3588 */ -+ dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); -+ if (IS_ERR(dwc->pipe_clk)) { -+ return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), -+ "could not get pipe clock\n"); -+ } -+ - return 0; - } - ---- a/drivers/usb/dwc3/core.h -+++ b/drivers/usb/dwc3/core.h -@@ -1003,6 +1003,8 @@ struct dwc3_scratchpad_array { - * @bus_clk: clock for accessing the registers - * @ref_clk: reference clock - * @susp_clk: clock used when the SS phy is in low power (S3) state -+ * @utmi_clk: clock used for USB2 PHY communication -+ * @pipe_clk: clock used for USB3 PHY communication - * @reset: reset control - * @regs: base address for our registers - * @regs_size: address space size -@@ -1175,6 +1177,8 @@ struct dwc3 { - struct clk *bus_clk; - struct clk *ref_clk; - struct clk *susp_clk; -+ struct clk *utmi_clk; -+ struct clk *pipe_clk; - - struct reset_control *reset; - diff --git a/target/linux/rockchip/patches-6.6/050-01-v6.8-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch b/target/linux/rockchip/patches-6.6/050-01-v6.8-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch deleted file mode 100644 index fcbec5f63a..0000000000 --- a/target/linux/rockchip/patches-6.6/050-01-v6.8-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 3eaf2abd11aa7f3b2fb04d60c64b2c756fe030eb Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Mon, 9 Oct 2023 22:27:26 +0300 -Subject: [PATCH] arm64: dts: rockchip: Add sfc node to rk3588s - -Add SFC (SPI Flash) to RK3588S SOC. - -Reviewed-by: Dhruva Gole -Signed-off-by: Muhammed Efe Cetin -Link: https://lore.kernel.org/r/d36a64edfaede92ce2e158b0d9dc4f5998e019e3.1696878787.git.efectn@6tel.net -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1425,6 +1425,17 @@ - }; - }; - -+ sfc: spi@fe2b0000 { -+ compatible = "rockchip,sfc"; -+ reg = <0x0 0xfe2b0000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; -+ clock-names = "clk_sfc", "hclk_sfc"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - sdmmc: mmc@fe2c0000 { - compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; diff --git a/target/linux/rockchip/patches-6.6/050-02-v6.8-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk3588s.patch b/target/linux/rockchip/patches-6.6/050-02-v6.8-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk3588s.patch deleted file mode 100644 index 25526ba23c..0000000000 --- a/target/linux/rockchip/patches-6.6/050-02-v6.8-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk3588s.patch +++ /dev/null @@ -1,58 +0,0 @@ -From bf012368bb0ab69167d49715789fac34dfcd457e Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Sun, 8 Oct 2023 15:04:59 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s - -This is used on Orange Pi 5 Plus. - -Signed-off-by: Ondrej Jirman -Link: https://lore.kernel.org/r/20231008130515.1155664-2-megi@xff.cz -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588s-pinctrl.dtsi | 35 +++++++++++++++++++ - 1 file changed, 35 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi -@@ -1350,6 +1350,41 @@ - - i2s2 { - /omit-if-no-ref/ -+ i2s2m0_lrck: i2s2m0-lrck { -+ rockchip,pins = -+ /* i2s2m0_lrck */ -+ <2 RK_PC0 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m0_mclk: i2s2m0-mclk { -+ rockchip,pins = -+ /* i2s2m0_mclk */ -+ <2 RK_PB6 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m0_sclk: i2s2m0-sclk { -+ rockchip,pins = -+ /* i2s2m0_sclk */ -+ <2 RK_PB7 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m0_sdi: i2s2m0-sdi { -+ rockchip,pins = -+ /* i2s2m0_sdi */ -+ <2 RK_PC3 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m0_sdo: i2s2m0-sdo { -+ rockchip,pins = -+ /* i2s2m0_sdo */ -+ <4 RK_PC3 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ - i2s2m1_lrck: i2s2m1-lrck { - rockchip,pins = - /* i2s2m1_lrck */ diff --git a/target/linux/rockchip/patches-6.6/050-03-v6.8-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-rk3588.patch b/target/linux/rockchip/patches-6.6/050-03-v6.8-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-rk3588.patch deleted file mode 100644 index 4a9cb6ea39..0000000000 --- a/target/linux/rockchip/patches-6.6/050-03-v6.8-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-rk3588.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 3d77a3e51b0faed820a8db985dce5af1cc4eae32 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Sun, 8 Oct 2023 15:05:00 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s - -This is used on Orange Pi 5 Plus. - -Signed-off-by: Ondrej Jirman -Link: https://lore.kernel.org/r/20231008130515.1155664-3-megi@xff.cz -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi -@@ -3343,6 +3343,15 @@ - - uart9 { - /omit-if-no-ref/ -+ uart9m0_xfer: uart9m0-xfer { -+ rockchip,pins = -+ /* uart9_rx_m0 */ -+ <2 RK_PC4 10 &pcfg_pull_up>, -+ /* uart9_tx_m0 */ -+ <2 RK_PC2 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ - uart9m1_xfer: uart9m1-xfer { - rockchip,pins = - /* uart9_rx_m1 */ diff --git a/target/linux/rockchip/patches-6.6/050-04-v6.8-arm64-dts-rockchip-Add-AV1-decoder-node-to-rk3588s.patch b/target/linux/rockchip/patches-6.6/050-04-v6.8-arm64-dts-rockchip-Add-AV1-decoder-node-to-rk3588s.patch deleted file mode 100644 index 6fce4f0f4c..0000000000 --- a/target/linux/rockchip/patches-6.6/050-04-v6.8-arm64-dts-rockchip-Add-AV1-decoder-node-to-rk3588s.patch +++ /dev/null @@ -1,37 +0,0 @@ -From dd6dc0c4c1265129c229e26917bf4de1d97ff91f Mon Sep 17 00:00:00 2001 -From: Benjamin Gaignard -Date: Fri, 6 Oct 2023 08:53:34 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add AV1 decoder node to rk3588s - -Add node for AV1 video decoder. - -Signed-off-by: Benjamin Gaignard -Reviewed-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20231006065334.8117-1-benjamin.gaignard@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -2314,6 +2314,19 @@ - #interrupt-cells = <2>; - }; - }; -+ -+ av1d: video-codec@fdc70000 { -+ compatible = "rockchip,rk3588-av1-vpu"; -+ reg = <0x0 0xfdc70000 0x0 0x800>; -+ interrupts = ; -+ interrupt-names = "vdpu"; -+ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; -+ assigned-clock-rates = <400000000>, <400000000>; -+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; -+ clock-names = "aclk", "hclk"; -+ power-domains = <&power RK3588_PD_AV1>; -+ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; -+ }; - }; - - #include "rk3588s-pinctrl.dtsi" diff --git a/target/linux/rockchip/patches-6.6/050-05-v6.8-arm64-dts-rockchip-Add-DFI-to-rk3588s.patch b/target/linux/rockchip/patches-6.6/050-05-v6.8-arm64-dts-rockchip-Add-DFI-to-rk3588s.patch deleted file mode 100644 index 714dc4883b..0000000000 --- a/target/linux/rockchip/patches-6.6/050-05-v6.8-arm64-dts-rockchip-Add-DFI-to-rk3588s.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 5a6976b1040a2f99ab84eddbfa7cd072ac5d10fc Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Wed, 18 Oct 2023 08:17:14 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add DFI to rk3588s - -The DFI unit can be used to measure DRAM utilization using perf. Add the -node to the device tree. The DFI needs a rockchip,pmu phandle to the pmu -containing registers for SDRAM configuration details. This is added in -this patch as well. - -Reviewed-by: Sebastian Reichel -Signed-off-by: Sascha Hauer -Link: https://lore.kernel.org/r/20231018061714.3553817-27-s.hauer@pengutronix.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -443,6 +443,11 @@ - status = "disabled"; - }; - -+ pmu1grf: syscon@fd58a000 { -+ compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; -+ reg = <0x0 0xfd58a000 0x0 0x10000>; -+ }; -+ - sys_grf: syscon@fd58c000 { - compatible = "rockchip,rk3588-sys-grf", "syscon"; - reg = <0x0 0xfd58c000 0x0 0x1000>; -@@ -1330,6 +1335,17 @@ - }; - }; - -+ dfi: dfi@fe060000 { -+ reg = <0x00 0xfe060000 0x00 0x10000>; -+ compatible = "rockchip,rk3588-dfi"; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "ch0", "ch1", "ch2", "ch3"; -+ rockchip,pmu = <&pmu1grf>; -+ }; -+ - gmac1: ethernet@fe1c0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1c0000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.6/050-06-v6.8-arm64-dts-rockchip-rk3588s-Add-USB3-host-controller.patch b/target/linux/rockchip/patches-6.6/050-06-v6.8-arm64-dts-rockchip-rk3588s-Add-USB3-host-controller.patch deleted file mode 100644 index f4e835a9f5..0000000000 --- a/target/linux/rockchip/patches-6.6/050-06-v6.8-arm64-dts-rockchip-rk3588s-Add-USB3-host-controller.patch +++ /dev/null @@ -1,48 +0,0 @@ -From bbd3778da16b3d448832b843f80bcde1aff26290 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Fri, 20 Oct 2023 16:11:42 +0200 -Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add USB3 host controller - -RK3588 has three USB3 controllers. This adds the host-only controller, -which is using the naneng-combphy shared with PCIe and SATA. - -The other two are dual-role and using a different PHY that is not yet -supported upstream. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20231020150022.48725-4-sebastian.reichel@collabora.com -Signed-off-by: Greg Kroah-Hartman ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -443,6 +443,27 @@ - status = "disabled"; - }; - -+ usb_host2_xhci: usb@fcd00000 { -+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; -+ reg = <0x0 0xfcd00000 0x0 0x400000>; -+ interrupts = ; -+ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, -+ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, -+ <&cru CLK_PIPEPHY2_PIPE_U3_G>; -+ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; -+ dr_mode = "host"; -+ phys = <&combphy2_psu PHY_TYPE_USB3>; -+ phy-names = "usb3-phy"; -+ phy_type = "utmi_wide"; -+ resets = <&cru SRST_A_USB3OTG2>; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ snps,dis_rxdet_inp3_quirk; -+ status = "disabled"; -+ }; -+ - pmu1grf: syscon@fd58a000 { - compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfd58a000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.6/050-07-v6.7-arm64-dts-rockchip-drop-interrupt-names-property-from.patch b/target/linux/rockchip/patches-6.6/050-07-v6.7-arm64-dts-rockchip-drop-interrupt-names-property-from.patch deleted file mode 100644 index 9076ca2d13..0000000000 --- a/target/linux/rockchip/patches-6.6/050-07-v6.7-arm64-dts-rockchip-drop-interrupt-names-property-from.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 815f986f33eeb06652d59d8a4d405d4fdb4e59a8 Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Fri, 1 Dec 2023 14:48:59 +0100 -Subject: [PATCH] arm64: dts: rockchip: drop interrupt-names property from - rk3588s dfi - -The dfi binding does not specify interrupt names, with the interrupts -just specifying channels 0-x. So drop the unspecified property. - -Fixes: 5a6976b1040a ("arm64: dts: rockchip: Add DFI to rk3588s") -Reported-by: Jagan Teki -Signed-off-by: Heiko Stuebner -Link: https://lore.kernel.org/r/20231201134859.322491-1-heiko@sntech.de ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 - - 1 file changed, 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1363,7 +1363,6 @@ - , - , - ; -- interrupt-names = "ch0", "ch1", "ch2", "ch3"; - rockchip,pmu = <&pmu1grf>; - }; - diff --git a/target/linux/rockchip/patches-6.6/050-08-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/050-08-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch deleted file mode 100644 index 60c2b269b5..0000000000 --- a/target/linux/rockchip/patches-6.6/050-08-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch +++ /dev/null @@ -1,139 +0,0 @@ -From 9918d10d16665527e59fdb87c5acac70cc1cfe8f Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Tue, 5 Dec 2023 17:48:39 +0100 -Subject: [PATCH] arm64: dts: rockchip: move rk3588 serial aliases to soc dtsi - -The serial ports on rk3588 are named uart0 - uart9. Board schematics -also use these exact numbers and we want those names to also reflect -in the OS devices because everything else would just cause confusion. - -To prevent each board repeating their list of serial aliases, move them -to the soc dtsi, as all previous Rockchip soc do already. - -Signed-off-by: Heiko Stuebner -Reviewed-by: Dragan Simic -Link: https://lore.kernel.org/r/20231205164842.556684-2-heiko@sntech.de ---- - .../boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts | 4 ---- - .../boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts | 4 ---- - arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 1 - - .../boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 -- - .../boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 1 - - .../boot/dts/rockchip/rk3588s-khadas-edge2.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++ - 13 files changed, 13 insertions(+), 19 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts -@@ -12,10 +12,6 @@ - compatible = "edgeble,neural-compute-module-6a-io", - "edgeble,neural-compute-module-6a", "rockchip,rk3588"; - -- aliases { -- serial2 = &uart2; -- }; -- - chosen { - stdout-path = "serial2:1500000n8"; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts -@@ -12,10 +12,6 @@ - compatible = "edgeble,neural-compute-module-6b-io", - "edgeble,neural-compute-module-6b", "rockchip,rk3588"; - -- aliases { -- serial2 = &uart2; -- }; -- - chosen { - stdout-path = "serial2:1500000n8"; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -@@ -16,7 +16,6 @@ - - aliases { - mmc0 = &sdhci; -- serial2 = &uart2; - }; - - chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -19,7 +19,6 @@ - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; -- serial2 = &uart2; - }; - - chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -12,7 +12,6 @@ - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; -- serial2 = &uart2; - }; - - chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts -@@ -15,7 +15,6 @@ - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; -- serial2 = &uart2; - }; - - chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -12,7 +12,6 @@ - - aliases { - mmc0 = &sdhci; -- serial2 = &uart2; - }; - - chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -14,7 +14,6 @@ - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; -- serial2 = &uart2; - }; - - analog-sound { ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -18,6 +18,19 @@ - #address-cells = <2>; - #size-cells = <2>; - -+ aliases { -+ serial0 = &uart0; -+ serial1 = &uart1; -+ serial2 = &uart2; -+ serial3 = &uart3; -+ serial4 = &uart4; -+ serial5 = &uart5; -+ serial6 = &uart6; -+ serial7 = &uart7; -+ serial8 = &uart8; -+ serial9 = &uart9; -+ }; -+ - cpus { - #address-cells = <1>; - #size-cells = <0>; diff --git a/target/linux/rockchip/patches-6.6/050-09-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/050-09-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch deleted file mode 100644 index 2daaec3953..0000000000 --- a/target/linux/rockchip/patches-6.6/050-09-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 328e901b7b03d292c1520ffb38e9164feef4f1ea Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Tue, 5 Dec 2023 17:48:40 +0100 -Subject: [PATCH] arm64: dts: rockchip: add rk3588 i2c aliases to soc dtsi - -The i2c controllers on rk3588 are named i2c0 - i2c8. Board schematics -also use these exact numbers and we want those names to also reflect -in the OS devices because everything else would just cause confusion. -Userspace i2c access is a thing afterall. - -To prevent each board repeating their list of i2c aliases, define them -in the soc dtsi, as all previous Rockchip soc do already. - -Signed-off-by: Heiko Stuebner -Reviewed-by: Dragan Simic -Link: https://lore.kernel.org/r/20231205164842.556684-3-heiko@sntech.de ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -19,6 +19,15 @@ - #size-cells = <2>; - - aliases { -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2c2 = &i2c2; -+ i2c3 = &i2c3; -+ i2c4 = &i2c4; -+ i2c5 = &i2c5; -+ i2c6 = &i2c6; -+ i2c7 = &i2c7; -+ i2c8 = &i2c8; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; diff --git a/target/linux/rockchip/patches-6.6/050-10-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/050-10-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch deleted file mode 100644 index 19e6c6a4f5..0000000000 --- a/target/linux/rockchip/patches-6.6/050-10-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch +++ /dev/null @@ -1,34 +0,0 @@ -From a024abedbca99a20aeb96f5beec9ded13c85dcb3 Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Tue, 5 Dec 2023 17:48:41 +0100 -Subject: [PATCH] arm64: dts: rockchip: add rk3588 gpio aliases to soc dtsi - -The gpio controllers on rk3588 are named gpio0 - gpio4. Board schematics -also use these exact numbers and we want those names to also reflect -in the OS devices because everything else would just cause confusion. -Userspace gpio access is a thing afterall. - -To prevent each board repeating their list of gpio aliases, define them -in the soc dtsi, as previous Rockchip soc like the rk356x do already. - -Signed-off-by: Heiko Stuebner -Reviewed-by: Dragan Simic -Link: https://lore.kernel.org/r/20231205164842.556684-4-heiko@sntech.de ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -19,6 +19,11 @@ - #size-cells = <2>; - - aliases { -+ gpio0 = &gpio0; -+ gpio1 = &gpio1; -+ gpio2 = &gpio2; -+ gpio3 = &gpio3; -+ gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; diff --git a/target/linux/rockchip/patches-6.6/050-11-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/050-11-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch deleted file mode 100644 index 6a66d99668..0000000000 --- a/target/linux/rockchip/patches-6.6/050-11-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch +++ /dev/null @@ -1,34 +0,0 @@ -From a86e88043de929da76f7f6cf0990ba92aed8391a Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Tue, 5 Dec 2023 17:48:42 +0100 -Subject: [PATCH] arm64: dts: rockchip: add rk3588 spi aliases to soc dtsi - -The spi controllers on rk3588 are named spi0 - spi4. Board schematics -also use these exact numbers and we want those names to also reflect -in the OS devices because everything else would just cause confusion. -Userspace spi access is a thing afterall. - -To prevent each board repeating their list of spi aliases, define them -in the soc dtsi, as previous Rockchip soc like the rk356x do already. - -Signed-off-by: Heiko Stuebner -Reviewed-by: Dragan Simic -Link: https://lore.kernel.org/r/20231205164842.556684-5-heiko@sntech.de ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -43,6 +43,11 @@ - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; -+ spi0 = &spi0; -+ spi1 = &spi1; -+ spi2 = &spi2; -+ spi3 = &spi3; -+ spi4 = &spi4; - }; - - cpus { diff --git a/target/linux/rockchip/patches-6.6/050-12-v6.8-arm64-dts-rockchip-Add-vop-on-rk3588.patch b/target/linux/rockchip/patches-6.6/050-12-v6.8-arm64-dts-rockchip-Add-vop-on-rk3588.patch deleted file mode 100644 index 3936df7a73..0000000000 --- a/target/linux/rockchip/patches-6.6/050-12-v6.8-arm64-dts-rockchip-Add-vop-on-rk3588.patch +++ /dev/null @@ -1,120 +0,0 @@ -From d895dbef3f3a31ab50491bb48552e798cf555987 Mon Sep 17 00:00:00 2001 -From: Andy Yan -Date: Mon, 11 Dec 2023 20:00:04 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add vop on rk3588 - -Add vop dt node for rk3588. - -Signed-off-by: Andy Yan -Link: https://lore.kernel.org/r/20231211120004.1785616-1-andyshrk@163.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 83 +++++++++++++++++++++++ - 1 file changed, 83 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -394,6 +394,11 @@ - #clock-cells = <0>; - }; - -+ display_subsystem: display-subsystem { -+ compatible = "rockchip,display-subsystem"; -+ ports = <&vop_out>; -+ }; -+ - timer { - compatible = "arm,armv8-timer"; - interrupts = , -@@ -506,6 +511,16 @@ - reg = <0x0 0xfd58c000 0x0 0x1000>; - }; - -+ vop_grf: syscon@fd5a4000 { -+ compatible = "rockchip,rk3588-vop-grf", "syscon"; -+ reg = <0x0 0xfd5a4000 0x0 0x2000>; -+ }; -+ -+ vo1_grf: syscon@fd5a8000 { -+ compatible = "rockchip,rk3588-vo-grf", "syscon"; -+ reg = <0x0 0xfd5a8000 0x0 0x100>; -+ }; -+ - php_grf: syscon@fd5b0000 { - compatible = "rockchip,rk3588-php-grf", "syscon"; - reg = <0x0 0xfd5b0000 0x0 0x1000>; -@@ -625,6 +640,74 @@ - status = "disabled"; - }; - -+ vop: vop@fdd90000 { -+ compatible = "rockchip,rk3588-vop"; -+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; -+ reg-names = "vop", "gamma-lut"; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, -+ <&cru HCLK_VOP>, -+ <&cru DCLK_VOP0>, -+ <&cru DCLK_VOP1>, -+ <&cru DCLK_VOP2>, -+ <&cru DCLK_VOP3>, -+ <&cru PCLK_VOP_ROOT>; -+ clock-names = "aclk", -+ "hclk", -+ "dclk_vp0", -+ "dclk_vp1", -+ "dclk_vp2", -+ "dclk_vp3", -+ "pclk_vop"; -+ iommus = <&vop_mmu>; -+ power-domains = <&power RK3588_PD_VOP>; -+ rockchip,grf = <&sys_grf>; -+ rockchip,vop-grf = <&vop_grf>; -+ rockchip,vo1-grf = <&vo1_grf>; -+ rockchip,pmu = <&pmu>; -+ status = "disabled"; -+ -+ vop_out: ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ vp0: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ }; -+ -+ vp1: port@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ }; -+ -+ vp2: port@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ }; -+ -+ vp3: port@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <3>; -+ }; -+ }; -+ }; -+ -+ vop_mmu: iommu@fdd97e00 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; -+ clock-names = "aclk", "iface"; -+ #iommu-cells = <0>; -+ power-domains = <&power RK3588_PD_VOP>; -+ status = "disabled"; -+ }; -+ - uart0: serial@fd890000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfd890000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-6.6/050-13-v6.9-arm64-dts-rockchip-Add-HDMI0-PHY-to-rk3588.patch b/target/linux/rockchip/patches-6.6/050-13-v6.9-arm64-dts-rockchip-Add-HDMI0-PHY-to-rk3588.patch deleted file mode 100644 index d9bd3ab019..0000000000 --- a/target/linux/rockchip/patches-6.6/050-13-v6.9-arm64-dts-rockchip-Add-HDMI0-PHY-to-rk3588.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 11d28971aaaf5de6f50790fb21f1113fee21d320 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Mon, 19 Feb 2024 22:46:25 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add HDMI0 PHY to rk3588 - -Add DT nodes for HDMI0 PHY and related syscon found on RK3588 SoC. - -Signed-off-by: Cristian Ciocaltea -Link: https://lore.kernel.org/r/20240219204626.284399-1-cristian.ciocaltea@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -586,6 +586,11 @@ - }; - }; - -+ hdptxphy0_grf: syscon@fd5e0000 { -+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; -+ reg = <0x0 0xfd5e0000 0x0 0x100>; -+ }; -+ - ioc: syscon@fd5f0000 { - compatible = "rockchip,rk3588-ioc", "syscon"; - reg = <0x0 0xfd5f0000 0x0 0x10000>; -@@ -2358,6 +2363,22 @@ - #dma-cells = <1>; - }; - -+ hdptxphy_hdmi0: phy@fed60000 { -+ compatible = "rockchip,rk3588-hdptx-phy"; -+ reg = <0x0 0xfed60000 0x0 0x2000>; -+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; -+ clock-names = "ref", "apb"; -+ #phy-cells = <0>; -+ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, -+ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, -+ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, -+ <&cru SRST_HDPTX0_LCPLL>; -+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", -+ "lcpll"; -+ rockchip,grf = <&hdptxphy0_grf>; -+ status = "disabled"; -+ }; -+ - combphy0_ps: phy@fee00000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee00000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-6.6/050-14-v6.9-arm64-dts-rockchip-add-clock-to-vo1-grf-syscon-on-rk3588.patch b/target/linux/rockchip/patches-6.6/050-14-v6.9-arm64-dts-rockchip-add-clock-to-vo1-grf-syscon-on-rk3588.patch deleted file mode 100644 index 6ffc2c751a..0000000000 --- a/target/linux/rockchip/patches-6.6/050-14-v6.9-arm64-dts-rockchip-add-clock-to-vo1-grf-syscon-on-rk3588.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 2047366b9eff8fada2a118588b0478de6e92d02c Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Tue, 27 Feb 2024 22:05:21 +0100 -Subject: [PATCH] arm64: dts: rockchip: add clock to vo1-grf syscon on rk3588 - -The VO*-general-register-files need a clock, so add the correct one. - -Cc: Sebastian Reichel -Reviewed-by: Sebastian Reichel -Signed-off-by: Heiko Stuebner -Link: https://lore.kernel.org/r/20240227210521.724754-1-heiko@sntech.de ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -519,6 +519,7 @@ - vo1_grf: syscon@fd5a8000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; - reg = <0x0 0xfd5a8000 0x0 0x100>; -+ clocks = <&cru PCLK_VO1GRF>; - }; - - php_grf: syscon@fd5b0000 { diff --git a/target/linux/rockchip/patches-6.6/050-15-v6.10-arm64-dts-rockchip-Add-rk3588-GPU-node.patch b/target/linux/rockchip/patches-6.6/050-15-v6.10-arm64-dts-rockchip-Add-rk3588-GPU-node.patch deleted file mode 100644 index dafdd69d68..0000000000 --- a/target/linux/rockchip/patches-6.6/050-15-v6.10-arm64-dts-rockchip-Add-rk3588-GPU-node.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 6fca4edb93d335f29f81e484936f38a5eed6a9b1 Mon Sep 17 00:00:00 2001 -From: Boris Brezillon -Date: Tue, 26 Mar 2024 17:52:06 +0100 -Subject: [PATCH] arm64: dts: rockchip: Add rk3588 GPU node - -Add Mali GPU Node to the RK3588 SoC DT including GPU clock -operating points - -Signed-off-by: Boris Brezillon -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240326165232.73585-3-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 56 +++++++++++++++++++++++ - 1 file changed, 56 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -501,6 +501,62 @@ - status = "disabled"; - }; - -+ gpu: gpu@fb000000 { -+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; -+ reg = <0x0 0xfb000000 0x0 0x200000>; -+ #cooling-cells = <2>; -+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; -+ assigned-clock-rates = <200000000>; -+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, -+ <&cru CLK_GPU_STACKS>; -+ clock-names = "core", "coregroup", "stacks"; -+ dynamic-power-coefficient = <2982>; -+ interrupts = , -+ , -+ ; -+ interrupt-names = "job", "mmu", "gpu"; -+ operating-points-v2 = <&gpu_opp_table>; -+ power-domains = <&power RK3588_PD_GPU>; -+ status = "disabled"; -+ -+ gpu_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-500000000 { -+ opp-hz = /bits/ 64 <500000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-700000000 { -+ opp-hz = /bits/ 64 <700000000>; -+ opp-microvolt = <700000 700000 850000>; -+ }; -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <750000 750000 850000>; -+ }; -+ opp-900000000 { -+ opp-hz = /bits/ 64 <900000000>; -+ opp-microvolt = <800000 800000 850000>; -+ }; -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <850000 850000 850000>; -+ }; -+ }; -+ }; -+ - pmu1grf: syscon@fd58a000 { - compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfd58a000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.6/050-16-v6.10-arm64-dts-rockchip-Fix-ordering-of-nodes-on-rk3588s.patch b/target/linux/rockchip/patches-6.6/050-16-v6.10-arm64-dts-rockchip-Fix-ordering-of-nodes-on-rk3588s.patch deleted file mode 100644 index 7b69e0a195..0000000000 --- a/target/linux/rockchip/patches-6.6/050-16-v6.10-arm64-dts-rockchip-Fix-ordering-of-nodes-on-rk3588s.patch +++ /dev/null @@ -1,384 +0,0 @@ -From cbb97fe18e299ece1c0074924c630de6a19b320f Mon Sep 17 00:00:00 2001 -From: Diederik de Haas -Date: Sat, 6 Apr 2024 19:28:04 +0200 -Subject: [PATCH] arm64: dts: rockchip: Fix ordering of nodes on rk3588s - -Fix the ordering of the main nodes by sorting them alphabetically and -then the ones with a memory address sequentially by that address. - -Signed-off-by: Diederik de Haas -Link: https://lore.kernel.org/r/20240406172821.34173-1-didi.debian@cknow.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 304 +++++++++++----------- - 1 file changed, 152 insertions(+), 152 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -347,6 +347,11 @@ - }; - }; - -+ display_subsystem: display-subsystem { -+ compatible = "rockchip,display-subsystem"; -+ ports = <&vop_out>; -+ }; -+ - firmware { - optee: optee { - compatible = "linaro,optee-tz"; -@@ -394,11 +399,6 @@ - #clock-cells = <0>; - }; - -- display_subsystem: display-subsystem { -- compatible = "rockchip,display-subsystem"; -- ports = <&vop_out>; -- }; -- - timer { - compatible = "arm,armv8-timer"; - interrupts = , -@@ -436,6 +436,62 @@ - }; - }; - -+ gpu: gpu@fb000000 { -+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; -+ reg = <0x0 0xfb000000 0x0 0x200000>; -+ #cooling-cells = <2>; -+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; -+ assigned-clock-rates = <200000000>; -+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, -+ <&cru CLK_GPU_STACKS>; -+ clock-names = "core", "coregroup", "stacks"; -+ dynamic-power-coefficient = <2982>; -+ interrupts = , -+ , -+ ; -+ interrupt-names = "job", "mmu", "gpu"; -+ operating-points-v2 = <&gpu_opp_table>; -+ power-domains = <&power RK3588_PD_GPU>; -+ status = "disabled"; -+ -+ gpu_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-500000000 { -+ opp-hz = /bits/ 64 <500000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-700000000 { -+ opp-hz = /bits/ 64 <700000000>; -+ opp-microvolt = <700000 700000 850000>; -+ }; -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <750000 750000 850000>; -+ }; -+ opp-900000000 { -+ opp-hz = /bits/ 64 <900000000>; -+ opp-microvolt = <800000 800000 850000>; -+ }; -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <850000 850000 850000>; -+ }; -+ }; -+ }; -+ - usb_host0_ehci: usb@fc800000 { - compatible = "rockchip,rk3588-ehci", "generic-ehci"; - reg = <0x0 0xfc800000 0x0 0x40000>; -@@ -501,62 +557,6 @@ - status = "disabled"; - }; - -- gpu: gpu@fb000000 { -- compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; -- reg = <0x0 0xfb000000 0x0 0x200000>; -- #cooling-cells = <2>; -- assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; -- assigned-clock-rates = <200000000>; -- clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, -- <&cru CLK_GPU_STACKS>; -- clock-names = "core", "coregroup", "stacks"; -- dynamic-power-coefficient = <2982>; -- interrupts = , -- , -- ; -- interrupt-names = "job", "mmu", "gpu"; -- operating-points-v2 = <&gpu_opp_table>; -- power-domains = <&power RK3588_PD_GPU>; -- status = "disabled"; -- -- gpu_opp_table: opp-table { -- compatible = "operating-points-v2"; -- -- opp-300000000 { -- opp-hz = /bits/ 64 <300000000>; -- opp-microvolt = <675000 675000 850000>; -- }; -- opp-400000000 { -- opp-hz = /bits/ 64 <400000000>; -- opp-microvolt = <675000 675000 850000>; -- }; -- opp-500000000 { -- opp-hz = /bits/ 64 <500000000>; -- opp-microvolt = <675000 675000 850000>; -- }; -- opp-600000000 { -- opp-hz = /bits/ 64 <600000000>; -- opp-microvolt = <675000 675000 850000>; -- }; -- opp-700000000 { -- opp-hz = /bits/ 64 <700000000>; -- opp-microvolt = <700000 700000 850000>; -- }; -- opp-800000000 { -- opp-hz = /bits/ 64 <800000000>; -- opp-microvolt = <750000 750000 850000>; -- }; -- opp-900000000 { -- opp-hz = /bits/ 64 <900000000>; -- opp-microvolt = <800000 800000 850000>; -- }; -- opp-1000000000 { -- opp-hz = /bits/ 64 <1000000000>; -- opp-microvolt = <850000 850000 850000>; -- }; -- }; -- }; -- - pmu1grf: syscon@fd58a000 { - compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfd58a000 0x0 0x10000>; -@@ -702,74 +702,6 @@ - status = "disabled"; - }; - -- vop: vop@fdd90000 { -- compatible = "rockchip,rk3588-vop"; -- reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; -- reg-names = "vop", "gamma-lut"; -- interrupts = ; -- clocks = <&cru ACLK_VOP>, -- <&cru HCLK_VOP>, -- <&cru DCLK_VOP0>, -- <&cru DCLK_VOP1>, -- <&cru DCLK_VOP2>, -- <&cru DCLK_VOP3>, -- <&cru PCLK_VOP_ROOT>; -- clock-names = "aclk", -- "hclk", -- "dclk_vp0", -- "dclk_vp1", -- "dclk_vp2", -- "dclk_vp3", -- "pclk_vop"; -- iommus = <&vop_mmu>; -- power-domains = <&power RK3588_PD_VOP>; -- rockchip,grf = <&sys_grf>; -- rockchip,vop-grf = <&vop_grf>; -- rockchip,vo1-grf = <&vo1_grf>; -- rockchip,pmu = <&pmu>; -- status = "disabled"; -- -- vop_out: ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- vp0: port@0 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0>; -- }; -- -- vp1: port@1 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <1>; -- }; -- -- vp2: port@2 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <2>; -- }; -- -- vp3: port@3 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <3>; -- }; -- }; -- }; -- -- vop_mmu: iommu@fdd97e00 { -- compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -- reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; -- interrupts = ; -- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; -- clock-names = "aclk", "iface"; -- #iommu-cells = <0>; -- power-domains = <&power RK3588_PD_VOP>; -- status = "disabled"; -- }; -- - uart0: serial@fd890000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfd890000 0x0 0x100>; -@@ -1140,6 +1072,87 @@ - }; - }; - -+ av1d: video-codec@fdc70000 { -+ compatible = "rockchip,rk3588-av1-vpu"; -+ reg = <0x0 0xfdc70000 0x0 0x800>; -+ interrupts = ; -+ interrupt-names = "vdpu"; -+ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; -+ assigned-clock-rates = <400000000>, <400000000>; -+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; -+ clock-names = "aclk", "hclk"; -+ power-domains = <&power RK3588_PD_AV1>; -+ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; -+ }; -+ -+ vop: vop@fdd90000 { -+ compatible = "rockchip,rk3588-vop"; -+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; -+ reg-names = "vop", "gamma-lut"; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, -+ <&cru HCLK_VOP>, -+ <&cru DCLK_VOP0>, -+ <&cru DCLK_VOP1>, -+ <&cru DCLK_VOP2>, -+ <&cru DCLK_VOP3>, -+ <&cru PCLK_VOP_ROOT>; -+ clock-names = "aclk", -+ "hclk", -+ "dclk_vp0", -+ "dclk_vp1", -+ "dclk_vp2", -+ "dclk_vp3", -+ "pclk_vop"; -+ iommus = <&vop_mmu>; -+ power-domains = <&power RK3588_PD_VOP>; -+ rockchip,grf = <&sys_grf>; -+ rockchip,vop-grf = <&vop_grf>; -+ rockchip,vo1-grf = <&vo1_grf>; -+ rockchip,pmu = <&pmu>; -+ status = "disabled"; -+ -+ vop_out: ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ vp0: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ }; -+ -+ vp1: port@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ }; -+ -+ vp2: port@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ }; -+ -+ vp3: port@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <3>; -+ }; -+ }; -+ }; -+ -+ vop_mmu: iommu@fdd97e00 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; -+ clock-names = "aclk", "iface"; -+ #iommu-cells = <0>; -+ power-domains = <&power RK3588_PD_VOP>; -+ status = "disabled"; -+ }; -+ - i2s4_8ch: i2s@fddc0000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc0000 0x0 0x1000>; -@@ -1431,6 +1444,16 @@ - reg = <0x0 0xfdf82200 0x0 0x20>; - }; - -+ dfi: dfi@fe060000 { -+ reg = <0x00 0xfe060000 0x00 0x10000>; -+ compatible = "rockchip,rk3588-dfi"; -+ interrupts = , -+ , -+ , -+ ; -+ rockchip,pmu = <&pmu1grf>; -+ }; -+ - pcie2x1l1: pcie@fe180000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x30 0x3f>; -@@ -1533,16 +1556,6 @@ - }; - }; - -- dfi: dfi@fe060000 { -- reg = <0x00 0xfe060000 0x00 0x10000>; -- compatible = "rockchip,rk3588-dfi"; -- interrupts = , -- , -- , -- ; -- rockchip,pmu = <&pmu1grf>; -- }; -- - gmac1: ethernet@fe1c0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1c0000 0x0 0x10000>; -@@ -2543,19 +2556,6 @@ - #interrupt-cells = <2>; - }; - }; -- -- av1d: video-codec@fdc70000 { -- compatible = "rockchip,rk3588-av1-vpu"; -- reg = <0x0 0xfdc70000 0x0 0x800>; -- interrupts = ; -- interrupt-names = "vdpu"; -- assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; -- assigned-clock-rates = <400000000>, <400000000>; -- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; -- clock-names = "aclk", "hclk"; -- power-domains = <&power RK3588_PD_AV1>; -- resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; -- }; - }; - - #include "rk3588s-pinctrl.dtsi" diff --git a/target/linux/rockchip/patches-6.6/050-17-v6.10-arm64-dts-rockchip-fix-usb2phy-nodename-for-rk3588.patch b/target/linux/rockchip/patches-6.6/050-17-v6.10-arm64-dts-rockchip-fix-usb2phy-nodename-for-rk3588.patch deleted file mode 100644 index 065cb4b410..0000000000 --- a/target/linux/rockchip/patches-6.6/050-17-v6.10-arm64-dts-rockchip-fix-usb2phy-nodename-for-rk3588.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 4e07a95f7402de092cd71b2cb96c69f85c98f251 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 9 Apr 2024 00:50:31 +0200 -Subject: [PATCH] arm64: dts: rockchip: fix usb2phy nodename for rk3588 - -usb2-phy should be named usb2phy according to the DT binding, -so let's fix it up accordingly. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240408225109.128953-5-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -599,7 +599,7 @@ - #address-cells = <1>; - #size-cells = <1>; - -- u2phy2: usb2-phy@8000 { -+ u2phy2: usb2phy@8000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x8000 0x10>; - interrupts = ; -@@ -624,7 +624,7 @@ - #address-cells = <1>; - #size-cells = <1>; - -- u2phy3: usb2-phy@c000 { -+ u2phy3: usb2phy@c000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0xc000 0x10>; - interrupts = ; diff --git a/target/linux/rockchip/patches-6.6/050-18-v6.10-arm64-dts-rockchip-reorder-usb2phy-properties-for-rk3588.patch b/target/linux/rockchip/patches-6.6/050-18-v6.10-arm64-dts-rockchip-reorder-usb2phy-properties-for-rk3588.patch deleted file mode 100644 index 81e8ed1011..0000000000 --- a/target/linux/rockchip/patches-6.6/050-18-v6.10-arm64-dts-rockchip-reorder-usb2phy-properties-for-rk3588.patch +++ /dev/null @@ -1,53 +0,0 @@ -From abe68e0ca71dddce0e5419e35507cb464d61870d Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 9 Apr 2024 00:50:32 +0200 -Subject: [PATCH] arm64: dts: rockchip: reorder usb2phy properties for rk3588 - -Reorder common DT properties alphabetically for usb2phy, according -to latest DT style rules. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -602,13 +602,13 @@ - u2phy2: usb2phy@8000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x8000 0x10>; -- interrupts = ; -- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; -- reset-names = "phy", "apb"; -+ #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy2"; -- #clock-cells = <0>; -+ interrupts = ; -+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; -+ reset-names = "phy", "apb"; - status = "disabled"; - - u2phy2_host: host-port { -@@ -627,13 +627,13 @@ - u2phy3: usb2phy@c000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0xc000 0x10>; -- interrupts = ; -- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; -- reset-names = "phy", "apb"; -+ #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy3"; -- #clock-cells = <0>; -+ interrupts = ; -+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; -+ reset-names = "phy", "apb"; - status = "disabled"; - - u2phy3_host: host-port { diff --git a/target/linux/rockchip/patches-6.6/050-19-v6.10-arm64-dts-rockchip-add-USBDP-phys-on-rk3588.patch b/target/linux/rockchip/patches-6.6/050-19-v6.10-arm64-dts-rockchip-add-USBDP-phys-on-rk3588.patch deleted file mode 100644 index 985a799df1..0000000000 --- a/target/linux/rockchip/patches-6.6/050-19-v6.10-arm64-dts-rockchip-add-USBDP-phys-on-rk3588.patch +++ /dev/null @@ -1,175 +0,0 @@ -From e18e5e8188f2671abf63abe7db5f21555705130f Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 9 Apr 2024 00:50:33 +0200 -Subject: [PATCH] arm64: dts: rockchip: add USBDP phys on rk3588 - -Add both USB3-DisplayPort PHYs to RK3588 SoC DT. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588.dtsi | 52 +++++++++++++++++++ - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 63 +++++++++++++++++++++++ - 2 files changed, 115 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -@@ -17,6 +17,36 @@ - reg = <0x0 0xfd5c0000 0x0 0x100>; - }; - -+ usbdpphy1_grf: syscon@fd5cc000 { -+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; -+ reg = <0x0 0xfd5cc000 0x0 0x4000>; -+ }; -+ -+ usb2phy1_grf: syscon@fd5d4000 { -+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; -+ reg = <0x0 0xfd5d4000 0x0 0x4000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ u2phy1: usb2phy@4000 { -+ compatible = "rockchip,rk3588-usb2phy"; -+ reg = <0x4000 0x10>; -+ #clock-cells = <0>; -+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; -+ clock-names = "phyclk"; -+ clock-output-names = "usb480m_phy1"; -+ interrupts = ; -+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; -+ reset-names = "phy", "apb"; -+ status = "disabled"; -+ -+ u2phy1_otg: otg-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ - i2s8_8ch: i2s@fddc8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc8000 0x0 0x1000>; -@@ -310,6 +340,28 @@ - }; - }; - -+ usbdp_phy1: phy@fed90000 { -+ compatible = "rockchip,rk3588-usbdp-phy"; -+ reg = <0x0 0xfed90000 0x0 0x10000>; -+ #phy-cells = <1>; -+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, -+ <&cru CLK_USBDP_PHY1_IMMORTAL>, -+ <&cru PCLK_USBDPPHY1>, -+ <&u2phy1>; -+ clock-names = "refclk", "immortal", "pclk", "utmi"; -+ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, -+ <&cru SRST_USBDP_COMBO_PHY1_CMN>, -+ <&cru SRST_USBDP_COMBO_PHY1_LANE>, -+ <&cru SRST_USBDP_COMBO_PHY1_PCS>, -+ <&cru SRST_P_USBDPPHY1>; -+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; -+ rockchip,u2phy-grf = <&usb2phy1_grf>; -+ rockchip,usb-grf = <&usb_grf>; -+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>; -+ rockchip,vo-grf = <&vo0_grf>; -+ status = "disabled"; -+ }; -+ - combphy1_ps: phy@fee10000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee10000 0x0 0x100>; ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -572,12 +572,23 @@ - reg = <0x0 0xfd5a4000 0x0 0x2000>; - }; - -+ vo0_grf: syscon@fd5a6000 { -+ compatible = "rockchip,rk3588-vo-grf", "syscon"; -+ reg = <0x0 0xfd5a6000 0x0 0x2000>; -+ clocks = <&cru PCLK_VO0GRF>; -+ }; -+ - vo1_grf: syscon@fd5a8000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; - reg = <0x0 0xfd5a8000 0x0 0x100>; - clocks = <&cru PCLK_VO1GRF>; - }; - -+ usb_grf: syscon@fd5ac000 { -+ compatible = "rockchip,rk3588-usb-grf", "syscon"; -+ reg = <0x0 0xfd5ac000 0x0 0x4000>; -+ }; -+ - php_grf: syscon@fd5b0000 { - compatible = "rockchip,rk3588-php-grf", "syscon"; - reg = <0x0 0xfd5b0000 0x0 0x1000>; -@@ -593,6 +604,36 @@ - reg = <0x0 0xfd5c4000 0x0 0x100>; - }; - -+ usbdpphy0_grf: syscon@fd5c8000 { -+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; -+ reg = <0x0 0xfd5c8000 0x0 0x4000>; -+ }; -+ -+ usb2phy0_grf: syscon@fd5d0000 { -+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; -+ reg = <0x0 0xfd5d0000 0x0 0x4000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ u2phy0: usb2phy@0 { -+ compatible = "rockchip,rk3588-usb2phy"; -+ reg = <0x0 0x10>; -+ #clock-cells = <0>; -+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; -+ clock-names = "phyclk"; -+ clock-output-names = "usb480m_phy0"; -+ interrupts = ; -+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; -+ reset-names = "phy", "apb"; -+ status = "disabled"; -+ -+ u2phy0_otg: otg-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ - usb2phy2_grf: syscon@fd5d8000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d8000 0x0 0x4000>; -@@ -2449,6 +2490,28 @@ - status = "disabled"; - }; - -+ usbdp_phy0: phy@fed80000 { -+ compatible = "rockchip,rk3588-usbdp-phy"; -+ reg = <0x0 0xfed80000 0x0 0x10000>; -+ #phy-cells = <1>; -+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, -+ <&cru CLK_USBDP_PHY0_IMMORTAL>, -+ <&cru PCLK_USBDPPHY0>, -+ <&u2phy0>; -+ clock-names = "refclk", "immortal", "pclk", "utmi"; -+ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, -+ <&cru SRST_USBDP_COMBO_PHY0_CMN>, -+ <&cru SRST_USBDP_COMBO_PHY0_LANE>, -+ <&cru SRST_USBDP_COMBO_PHY0_PCS>, -+ <&cru SRST_P_USBDPPHY0>; -+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; -+ rockchip,u2phy-grf = <&usb2phy0_grf>; -+ rockchip,usb-grf = <&usb_grf>; -+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>; -+ rockchip,vo-grf = <&vo0_grf>; -+ status = "disabled"; -+ }; -+ - combphy0_ps: phy@fee00000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee00000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-6.6/050-20-v6.10-arm64-dts-rockchip-add-USB3-DRD-controllers-on-rk3588.patch b/target/linux/rockchip/patches-6.6/050-20-v6.10-arm64-dts-rockchip-add-USB3-DRD-controllers-on-rk3588.patch deleted file mode 100644 index 7bfa205514..0000000000 --- a/target/linux/rockchip/patches-6.6/050-20-v6.10-arm64-dts-rockchip-add-USB3-DRD-controllers-on-rk3588.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 33f393a2a990e16f56931ca708295f31d2b44415 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 9 Apr 2024 00:50:34 +0200 -Subject: [PATCH] arm64: dts: rockchip: add USB3 DRD controllers on rk3588 - -Add both USB3 dual-role controllers to the RK3588 devicetree. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588.dtsi | 20 ++++++++++++++++++++ - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++++ - 2 files changed, 42 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -@@ -7,6 +7,26 @@ - #include "rk3588-pinctrl.dtsi" - - / { -+ usb_host1_xhci: usb@fc400000 { -+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; -+ reg = <0x0 0xfc400000 0x0 0x400000>; -+ interrupts = ; -+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, -+ <&cru ACLK_USB3OTG1>; -+ clock-names = "ref_clk", "suspend_clk", "bus_clk"; -+ dr_mode = "otg"; -+ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi_wide"; -+ power-domains = <&power RK3588_PD_USB>; -+ resets = <&cru SRST_A_USB3OTG1>; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ status = "disabled"; -+ }; -+ - pcie30_phy_grf: syscon@fd5b8000 { - compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; - reg = <0x0 0xfd5b8000 0x0 0x10000>; ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -492,6 +492,28 @@ - }; - }; - -+ usb_host0_xhci: usb@fc000000 { -+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; -+ reg = <0x0 0xfc000000 0x0 0x400000>; -+ interrupts = ; -+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, -+ <&cru ACLK_USB3OTG0>; -+ clock-names = "ref_clk", "suspend_clk", "bus_clk"; -+ dr_mode = "otg"; -+ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi_wide"; -+ power-domains = <&power RK3588_PD_USB>; -+ resets = <&cru SRST_A_USB3OTG0>; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u1-entry-quirk; -+ snps,dis-u2-entry-quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ status = "disabled"; -+ }; -+ - usb_host0_ehci: usb@fc800000 { - compatible = "rockchip,rk3588-ehci", "generic-ehci"; - reg = <0x0 0xfc800000 0x0 0x40000>; diff --git a/target/linux/rockchip/patches-6.6/050-21-v6.10-arm64-dts-rockchip-add-rk3588-pcie-and-php-IOMMUs.patch b/target/linux/rockchip/patches-6.6/050-21-v6.10-arm64-dts-rockchip-add-rk3588-pcie-and-php-IOMMUs.patch deleted file mode 100644 index fa98e5ec70..0000000000 --- a/target/linux/rockchip/patches-6.6/050-21-v6.10-arm64-dts-rockchip-add-rk3588-pcie-and-php-IOMMUs.patch +++ /dev/null @@ -1,74 +0,0 @@ -From cd81d3a0695cc54ad6ac0ef4bbb67a7c8f55d592 Mon Sep 17 00:00:00 2001 -From: Niklas Cassel -Date: Thu, 2 May 2024 16:02:32 +0200 -Subject: [PATCH] arm64: dts: rockchip: add rk3588 pcie and php IOMMUs - -The mmu600_pcie is connected with the five PCIe controllers. -The mmu600_php is connected with the USB3 controller, the GMAC -controllers, and the SATA controllers. - -See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual). - -The IOMMUs are disabled by default, as further patches are needed to -program the SID/SSIDs in to the IOMMUs. - -iommu: Default domain type: Translated -iommu: DMA domain TLB invalidation policy: strict mode -arm-smmu-v3 fc900000.iommu: ias 48-bit, oas 48-bit (features 0x001c1eaf) -arm-smmu-v3 fc900000.iommu: allocated 65536 entries for cmdq -arm-smmu-v3 fc900000.iommu: allocated 32768 entries for evtq -arm-smmu-v3 fc900000.iommu: msi_domain absent - falling back to wired irqs - -Additionally, the IOMMU correctly triggers an IOMMU fault when -a PCIe device performs a write (since the device hasn't been -assigned a SID/SSID): -arm-smmu-v3 fc900000.iommu: event 0x02 received: -arm-smmu-v3 fc900000.iommu: 0x0000010000000002 -arm-smmu-v3 fc900000.iommu: 0x0000000000000000 -arm-smmu-v3 fc900000.iommu: 0x0000000000000000 -arm-smmu-v3 fc900000.iommu: 0x0000000000000000 - -While this doesn't provide much value as is, having the devices as -disabled in the device tree will allow developers to see that the rk3588 -actually has IOMMUs on the SoC. - -Signed-off-by: Niklas Cassel -Link: https://lore.kernel.org/r/20240502140231.477049-2-cassel@kernel.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 24 +++++++++++++++++++++++ - 1 file changed, 24 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -579,6 +579,30 @@ - status = "disabled"; - }; - -+ mmu600_pcie: iommu@fc900000 { -+ compatible = "arm,smmu-v3"; -+ reg = <0x0 0xfc900000 0x0 0x200000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; -+ #iommu-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ mmu600_php: iommu@fcb00000 { -+ compatible = "arm,smmu-v3"; -+ reg = <0x0 0xfcb00000 0x0 0x200000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; -+ #iommu-cells = <1>; -+ status = "disabled"; -+ }; -+ - pmu1grf: syscon@fd58a000 { - compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfd58a000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.6/050-22-v6.11-arm64-dts-rockchip-Prepare-RK3588-SoC-dtsi-files-for.patch b/target/linux/rockchip/patches-6.6/050-22-v6.11-arm64-dts-rockchip-Prepare-RK3588-SoC-dtsi-files-for.patch deleted file mode 100644 index 08460b5b41..0000000000 --- a/target/linux/rockchip/patches-6.6/050-22-v6.11-arm64-dts-rockchip-Prepare-RK3588-SoC-dtsi-files-for.patch +++ /dev/null @@ -1,14208 +0,0 @@ -From def88eb4d8365a4aa064d28405d03550a9d0a3be Mon Sep 17 00:00:00 2001 -From: Dragan Simic -Date: Sun, 9 Jun 2024 10:58:19 +0200 -Subject: [PATCH] arm64: dts: rockchip: Prepare RK3588 SoC dtsi files for - per-variant OPPs - -Rename the Rockchip RK3588 SoC dtsi files and, consequently, adjust their -contents appropriately, to prepare them for the ability to specify different -CPU and GPU OPPs for each of the supported RK3588 SoC variants. - -As already discussed, [1][2][3][4] some of the RK3588 SoC variants require -different OPPs, and it makes more sense to have the OPPs already defined when -a board dts(i) file includes one of the SoC variant dtsi files (rk3588.dtsi, -rk3588j.dtsi or rk3588s.dtsi), rather than requiring the board dts(i) file -to also include a separate rk3588*-opp.dtsi file. The choice of the SoC -variant is already made by the inclusion of the SoC dtsi file into the board -dts(i) file, and it doesn't make much sense to, effectively, allow the board -dts(i) file to include and use an incompatible set of OPPs for the already -selected RK3588 SoC variant. - -The new naming scheme for the RK3588 SoC dtsi files uses "-base" and "-extra" -suffixes to denote the DT data shared between all RK5588 SoC variants, and -the DT data shared between the unrestricted SoC variants, respectively. -For example, the DT data for the RK3588 includes both rk3588-base.dtsi and -rk3588-extra.dtsi, because it's an unrestricted SoC variant, while the DT -data for the RK3588S variant includes rk3588-base.dtsi only, because it's -a restricted SoC variant, feature- and interface-wise. This achieves a more -logical naming of the RK3588 SoC dtsi files, which reflects the way DT data -for the SoC variants is built by "stacking" the SoC variant features made -available through the "-base" and "-extra" SoC dtsi files. Additionally, -the SoC variant dtsi files (rk3588.dtsi, rk3588j.dtsi and rk3588s.dtsi) are -no longer parents to any other SoC variant dtsi files, which should help with -making the new "stacking" approach cleaner and easier to follow. - -The RK3588 pinctrl dtsi files are also renamed in the same way, for the sake -of consistency. This also keeps the "-base" and "-extra" groups of the dtsi -files together when looked at in a directory listing, which is helpful. - -The per-SoC-variant OPPs should go directly into the SoC dtsi files, if no -more than one SoC variant uses those OPPs, or be put into a separate "-opp" -dtsi file that's shared between and included from two or more SoC variant -dtsi files. An example for the former is the non-shared OPP data that should -go directly into the RK3588J SoC variant dtsi file (i.e. rk3588j.dtsi), and -an example for the latter is the shared OPP data that should be put into -rk3588-opp.dtsi and be included from the RK3588 and RK3588S SoC variant dtsi -files (i.e. rk3588.dtsi and rk3588s.dtsi, respectively). Consequently, if -the OPPs for the RK3588 and RK3588S SoC variants are ever made different, -the shared rk3588-opp.dtsi file should be deleted and the new OPPs should -be put directly into rk3588.dtsi and rk3588s.dtsi. [4] - -No functional changes are introduced, which was validated by decompiling and -comparing all affected dtb files before and after these changes. - -As a side note, due to the nature of introduced changes, this commit is best -viewed using the --break-rewrites option for git-log(1). - -[1] https://lore.kernel.org/linux-rockchip/646a33e0-5c1b-471c-8183-2c0df40ea51a@cherry.de/ -[2] https://lore.kernel.org/linux-rockchip/CABjd4Yxi=+3gkNnH3BysUzzYsji-=-yROtzEc8jM_g0roKB0-w@mail.gmail.com/ -[3] https://lore.kernel.org/linux-rockchip/035a274be262528012173d463e25b55f@manjaro.org/ -[4] https://lore.kernel.org/linux-rockchip/673dcf47596e7bc8ba065034e339bb1bbf9cdcb0.1716948159.git.dsimic@manjaro.org/T/#u - -Signed-off-by: Dragan Simic -Link: https://lore.kernel.org/r/9ffedc0e2ca7f167d9d795b2a8f43cb9f56a653b.1717923308.git.dsimic@manjaro.org -Signed-off-by: Heiko Stuebner ---- - ...-pinctrl.dtsi => rk3588-base-pinctrl.dtsi} | 0 - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2670 +++++++++++++++++ - ...pinctrl.dtsi => rk3588-extra-pinctrl.dtsi} | 0 - .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 413 +++ - arch/arm64/boot/dts/rockchip/rk3588.dtsi | 412 +-- - arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 2 +- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2669 +--------------- - 7 files changed, 3090 insertions(+), 3076 deletions(-) - rename arch/arm64/boot/dts/rockchip/{rk3588s-pinctrl.dtsi => rk3588-base-pinctrl.dtsi} (100%) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi - rename arch/arm64/boot/dts/rockchip/{rk3588-pinctrl.dtsi => rk3588-extra-pinctrl.dtsi} (100%) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi - ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -0,0 +1,2670 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ compatible = "rockchip,rk3588"; -+ -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ gpio0 = &gpio0; -+ gpio1 = &gpio1; -+ gpio2 = &gpio2; -+ gpio3 = &gpio3; -+ gpio4 = &gpio4; -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2c2 = &i2c2; -+ i2c3 = &i2c3; -+ i2c4 = &i2c4; -+ i2c5 = &i2c5; -+ i2c6 = &i2c6; -+ i2c7 = &i2c7; -+ i2c8 = &i2c8; -+ serial0 = &uart0; -+ serial1 = &uart1; -+ serial2 = &uart2; -+ serial3 = &uart3; -+ serial4 = &uart4; -+ serial5 = &uart5; -+ serial6 = &uart6; -+ serial7 = &uart7; -+ serial8 = &uart8; -+ serial9 = &uart9; -+ spi0 = &spi0; -+ spi1 = &spi1; -+ spi2 = &spi2; -+ spi3 = &spi3; -+ spi4 = &spi4; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu-map { -+ cluster0 { -+ core0 { -+ cpu = <&cpu_l0>; -+ }; -+ core1 { -+ cpu = <&cpu_l1>; -+ }; -+ core2 { -+ cpu = <&cpu_l2>; -+ }; -+ core3 { -+ cpu = <&cpu_l3>; -+ }; -+ }; -+ cluster1 { -+ core0 { -+ cpu = <&cpu_b0>; -+ }; -+ core1 { -+ cpu = <&cpu_b1>; -+ }; -+ }; -+ cluster2 { -+ core0 { -+ cpu = <&cpu_b2>; -+ }; -+ core1 { -+ cpu = <&cpu_b3>; -+ }; -+ }; -+ }; -+ -+ cpu_l0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a55"; -+ reg = <0x0>; -+ enable-method = "psci"; -+ capacity-dmips-mhz = <530>; -+ clocks = <&scmi_clk SCMI_CLK_CPUL>; -+ assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; -+ assigned-clock-rates = <816000000>; -+ cpu-idle-states = <&CPU_SLEEP>; -+ i-cache-size = <32768>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <128>; -+ d-cache-size = <32768>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <128>; -+ next-level-cache = <&l2_cache_l0>; -+ dynamic-power-coefficient = <228>; -+ #cooling-cells = <2>; -+ }; -+ -+ cpu_l1: cpu@100 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a55"; -+ reg = <0x100>; -+ enable-method = "psci"; -+ capacity-dmips-mhz = <530>; -+ clocks = <&scmi_clk SCMI_CLK_CPUL>; -+ cpu-idle-states = <&CPU_SLEEP>; -+ i-cache-size = <32768>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <128>; -+ d-cache-size = <32768>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <128>; -+ next-level-cache = <&l2_cache_l1>; -+ dynamic-power-coefficient = <228>; -+ #cooling-cells = <2>; -+ }; -+ -+ cpu_l2: cpu@200 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a55"; -+ reg = <0x200>; -+ enable-method = "psci"; -+ capacity-dmips-mhz = <530>; -+ clocks = <&scmi_clk SCMI_CLK_CPUL>; -+ cpu-idle-states = <&CPU_SLEEP>; -+ i-cache-size = <32768>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <128>; -+ d-cache-size = <32768>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <128>; -+ next-level-cache = <&l2_cache_l2>; -+ dynamic-power-coefficient = <228>; -+ #cooling-cells = <2>; -+ }; -+ -+ cpu_l3: cpu@300 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a55"; -+ reg = <0x300>; -+ enable-method = "psci"; -+ capacity-dmips-mhz = <530>; -+ clocks = <&scmi_clk SCMI_CLK_CPUL>; -+ cpu-idle-states = <&CPU_SLEEP>; -+ i-cache-size = <32768>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <128>; -+ d-cache-size = <32768>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <128>; -+ next-level-cache = <&l2_cache_l3>; -+ dynamic-power-coefficient = <228>; -+ #cooling-cells = <2>; -+ }; -+ -+ cpu_b0: cpu@400 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a76"; -+ reg = <0x400>; -+ enable-method = "psci"; -+ capacity-dmips-mhz = <1024>; -+ clocks = <&scmi_clk SCMI_CLK_CPUB01>; -+ assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; -+ assigned-clock-rates = <816000000>; -+ cpu-idle-states = <&CPU_SLEEP>; -+ i-cache-size = <65536>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <256>; -+ d-cache-size = <65536>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache_b0>; -+ dynamic-power-coefficient = <416>; -+ #cooling-cells = <2>; -+ }; -+ -+ cpu_b1: cpu@500 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a76"; -+ reg = <0x500>; -+ enable-method = "psci"; -+ capacity-dmips-mhz = <1024>; -+ clocks = <&scmi_clk SCMI_CLK_CPUB01>; -+ cpu-idle-states = <&CPU_SLEEP>; -+ i-cache-size = <65536>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <256>; -+ d-cache-size = <65536>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache_b1>; -+ dynamic-power-coefficient = <416>; -+ #cooling-cells = <2>; -+ }; -+ -+ cpu_b2: cpu@600 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a76"; -+ reg = <0x600>; -+ enable-method = "psci"; -+ capacity-dmips-mhz = <1024>; -+ clocks = <&scmi_clk SCMI_CLK_CPUB23>; -+ assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; -+ assigned-clock-rates = <816000000>; -+ cpu-idle-states = <&CPU_SLEEP>; -+ i-cache-size = <65536>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <256>; -+ d-cache-size = <65536>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache_b2>; -+ dynamic-power-coefficient = <416>; -+ #cooling-cells = <2>; -+ }; -+ -+ cpu_b3: cpu@700 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a76"; -+ reg = <0x700>; -+ enable-method = "psci"; -+ capacity-dmips-mhz = <1024>; -+ clocks = <&scmi_clk SCMI_CLK_CPUB23>; -+ cpu-idle-states = <&CPU_SLEEP>; -+ i-cache-size = <65536>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <256>; -+ d-cache-size = <65536>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache_b3>; -+ dynamic-power-coefficient = <416>; -+ #cooling-cells = <2>; -+ }; -+ -+ idle-states { -+ entry-method = "psci"; -+ CPU_SLEEP: cpu-sleep { -+ compatible = "arm,idle-state"; -+ local-timer-stop; -+ arm,psci-suspend-param = <0x0010000>; -+ entry-latency-us = <100>; -+ exit-latency-us = <120>; -+ min-residency-us = <1000>; -+ }; -+ }; -+ -+ l2_cache_l0: l2-cache-l0 { -+ compatible = "cache"; -+ cache-size = <131072>; -+ cache-line-size = <64>; -+ cache-sets = <512>; -+ cache-level = <2>; -+ cache-unified; -+ next-level-cache = <&l3_cache>; -+ }; -+ -+ l2_cache_l1: l2-cache-l1 { -+ compatible = "cache"; -+ cache-size = <131072>; -+ cache-line-size = <64>; -+ cache-sets = <512>; -+ cache-level = <2>; -+ cache-unified; -+ next-level-cache = <&l3_cache>; -+ }; -+ -+ l2_cache_l2: l2-cache-l2 { -+ compatible = "cache"; -+ cache-size = <131072>; -+ cache-line-size = <64>; -+ cache-sets = <512>; -+ cache-level = <2>; -+ cache-unified; -+ next-level-cache = <&l3_cache>; -+ }; -+ -+ l2_cache_l3: l2-cache-l3 { -+ compatible = "cache"; -+ cache-size = <131072>; -+ cache-line-size = <64>; -+ cache-sets = <512>; -+ cache-level = <2>; -+ cache-unified; -+ next-level-cache = <&l3_cache>; -+ }; -+ -+ l2_cache_b0: l2-cache-b0 { -+ compatible = "cache"; -+ cache-size = <524288>; -+ cache-line-size = <64>; -+ cache-sets = <1024>; -+ cache-level = <2>; -+ cache-unified; -+ next-level-cache = <&l3_cache>; -+ }; -+ -+ l2_cache_b1: l2-cache-b1 { -+ compatible = "cache"; -+ cache-size = <524288>; -+ cache-line-size = <64>; -+ cache-sets = <1024>; -+ cache-level = <2>; -+ cache-unified; -+ next-level-cache = <&l3_cache>; -+ }; -+ -+ l2_cache_b2: l2-cache-b2 { -+ compatible = "cache"; -+ cache-size = <524288>; -+ cache-line-size = <64>; -+ cache-sets = <1024>; -+ cache-level = <2>; -+ cache-unified; -+ next-level-cache = <&l3_cache>; -+ }; -+ -+ l2_cache_b3: l2-cache-b3 { -+ compatible = "cache"; -+ cache-size = <524288>; -+ cache-line-size = <64>; -+ cache-sets = <1024>; -+ cache-level = <2>; -+ cache-unified; -+ next-level-cache = <&l3_cache>; -+ }; -+ -+ l3_cache: l3-cache { -+ compatible = "cache"; -+ cache-size = <3145728>; -+ cache-line-size = <64>; -+ cache-sets = <4096>; -+ cache-level = <3>; -+ cache-unified; -+ }; -+ }; -+ -+ display_subsystem: display-subsystem { -+ compatible = "rockchip,display-subsystem"; -+ ports = <&vop_out>; -+ }; -+ -+ firmware { -+ optee: optee { -+ compatible = "linaro,optee-tz"; -+ method = "smc"; -+ }; -+ -+ scmi: scmi { -+ compatible = "arm,scmi-smc"; -+ arm,smc-id = <0x82000010>; -+ shmem = <&scmi_shmem>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ scmi_clk: protocol@14 { -+ reg = <0x14>; -+ #clock-cells = <1>; -+ }; -+ -+ scmi_reset: protocol@16 { -+ reg = <0x16>; -+ #reset-cells = <1>; -+ }; -+ }; -+ }; -+ -+ pmu-a55 { -+ compatible = "arm,cortex-a55-pmu"; -+ interrupts = ; -+ }; -+ -+ pmu-a76 { -+ compatible = "arm,cortex-a76-pmu"; -+ interrupts = ; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ spll: clock-0 { -+ compatible = "fixed-clock"; -+ clock-frequency = <702000000>; -+ clock-output-names = "spll"; -+ #clock-cells = <0>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; -+ }; -+ -+ xin24m: clock-1 { -+ compatible = "fixed-clock"; -+ clock-frequency = <24000000>; -+ clock-output-names = "xin24m"; -+ #clock-cells = <0>; -+ }; -+ -+ xin32k: clock-2 { -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+ clock-output-names = "xin32k"; -+ #clock-cells = <0>; -+ }; -+ -+ pmu_sram: sram@10f000 { -+ compatible = "mmio-sram"; -+ reg = <0x0 0x0010f000 0x0 0x100>; -+ ranges = <0 0x0 0x0010f000 0x100>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ scmi_shmem: sram@0 { -+ compatible = "arm,scmi-shmem"; -+ reg = <0x0 0x100>; -+ }; -+ }; -+ -+ gpu: gpu@fb000000 { -+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; -+ reg = <0x0 0xfb000000 0x0 0x200000>; -+ #cooling-cells = <2>; -+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; -+ assigned-clock-rates = <200000000>; -+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, -+ <&cru CLK_GPU_STACKS>; -+ clock-names = "core", "coregroup", "stacks"; -+ dynamic-power-coefficient = <2982>; -+ interrupts = , -+ , -+ ; -+ interrupt-names = "job", "mmu", "gpu"; -+ operating-points-v2 = <&gpu_opp_table>; -+ power-domains = <&power RK3588_PD_GPU>; -+ status = "disabled"; -+ -+ gpu_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-500000000 { -+ opp-hz = /bits/ 64 <500000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-700000000 { -+ opp-hz = /bits/ 64 <700000000>; -+ opp-microvolt = <700000 700000 850000>; -+ }; -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <750000 750000 850000>; -+ }; -+ opp-900000000 { -+ opp-hz = /bits/ 64 <900000000>; -+ opp-microvolt = <800000 800000 850000>; -+ }; -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <850000 850000 850000>; -+ }; -+ }; -+ }; -+ -+ usb_host0_xhci: usb@fc000000 { -+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; -+ reg = <0x0 0xfc000000 0x0 0x400000>; -+ interrupts = ; -+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, -+ <&cru ACLK_USB3OTG0>; -+ clock-names = "ref_clk", "suspend_clk", "bus_clk"; -+ dr_mode = "otg"; -+ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi_wide"; -+ power-domains = <&power RK3588_PD_USB>; -+ resets = <&cru SRST_A_USB3OTG0>; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u1-entry-quirk; -+ snps,dis-u2-entry-quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ status = "disabled"; -+ }; -+ -+ usb_host0_ehci: usb@fc800000 { -+ compatible = "rockchip,rk3588-ehci", "generic-ehci"; -+ reg = <0x0 0xfc800000 0x0 0x40000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; -+ phys = <&u2phy2_host>; -+ phy-names = "usb"; -+ power-domains = <&power RK3588_PD_USB>; -+ status = "disabled"; -+ }; -+ -+ usb_host0_ohci: usb@fc840000 { -+ compatible = "rockchip,rk3588-ohci", "generic-ohci"; -+ reg = <0x0 0xfc840000 0x0 0x40000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; -+ phys = <&u2phy2_host>; -+ phy-names = "usb"; -+ power-domains = <&power RK3588_PD_USB>; -+ status = "disabled"; -+ }; -+ -+ usb_host1_ehci: usb@fc880000 { -+ compatible = "rockchip,rk3588-ehci", "generic-ehci"; -+ reg = <0x0 0xfc880000 0x0 0x40000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; -+ phys = <&u2phy3_host>; -+ phy-names = "usb"; -+ power-domains = <&power RK3588_PD_USB>; -+ status = "disabled"; -+ }; -+ -+ usb_host1_ohci: usb@fc8c0000 { -+ compatible = "rockchip,rk3588-ohci", "generic-ohci"; -+ reg = <0x0 0xfc8c0000 0x0 0x40000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; -+ phys = <&u2phy3_host>; -+ phy-names = "usb"; -+ power-domains = <&power RK3588_PD_USB>; -+ status = "disabled"; -+ }; -+ -+ usb_host2_xhci: usb@fcd00000 { -+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; -+ reg = <0x0 0xfcd00000 0x0 0x400000>; -+ interrupts = ; -+ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, -+ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, -+ <&cru CLK_PIPEPHY2_PIPE_U3_G>; -+ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; -+ dr_mode = "host"; -+ phys = <&combphy2_psu PHY_TYPE_USB3>; -+ phy-names = "usb3-phy"; -+ phy_type = "utmi_wide"; -+ resets = <&cru SRST_A_USB3OTG2>; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ snps,dis_rxdet_inp3_quirk; -+ status = "disabled"; -+ }; -+ -+ mmu600_pcie: iommu@fc900000 { -+ compatible = "arm,smmu-v3"; -+ reg = <0x0 0xfc900000 0x0 0x200000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; -+ #iommu-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ mmu600_php: iommu@fcb00000 { -+ compatible = "arm,smmu-v3"; -+ reg = <0x0 0xfcb00000 0x0 0x200000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; -+ #iommu-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ pmu1grf: syscon@fd58a000 { -+ compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; -+ reg = <0x0 0xfd58a000 0x0 0x10000>; -+ }; -+ -+ sys_grf: syscon@fd58c000 { -+ compatible = "rockchip,rk3588-sys-grf", "syscon"; -+ reg = <0x0 0xfd58c000 0x0 0x1000>; -+ }; -+ -+ vop_grf: syscon@fd5a4000 { -+ compatible = "rockchip,rk3588-vop-grf", "syscon"; -+ reg = <0x0 0xfd5a4000 0x0 0x2000>; -+ }; -+ -+ vo0_grf: syscon@fd5a6000 { -+ compatible = "rockchip,rk3588-vo-grf", "syscon"; -+ reg = <0x0 0xfd5a6000 0x0 0x2000>; -+ clocks = <&cru PCLK_VO0GRF>; -+ }; -+ -+ vo1_grf: syscon@fd5a8000 { -+ compatible = "rockchip,rk3588-vo-grf", "syscon"; -+ reg = <0x0 0xfd5a8000 0x0 0x100>; -+ clocks = <&cru PCLK_VO1GRF>; -+ }; -+ -+ usb_grf: syscon@fd5ac000 { -+ compatible = "rockchip,rk3588-usb-grf", "syscon"; -+ reg = <0x0 0xfd5ac000 0x0 0x4000>; -+ }; -+ -+ php_grf: syscon@fd5b0000 { -+ compatible = "rockchip,rk3588-php-grf", "syscon"; -+ reg = <0x0 0xfd5b0000 0x0 0x1000>; -+ }; -+ -+ pipe_phy0_grf: syscon@fd5bc000 { -+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; -+ reg = <0x0 0xfd5bc000 0x0 0x100>; -+ }; -+ -+ pipe_phy2_grf: syscon@fd5c4000 { -+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; -+ reg = <0x0 0xfd5c4000 0x0 0x100>; -+ }; -+ -+ usbdpphy0_grf: syscon@fd5c8000 { -+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; -+ reg = <0x0 0xfd5c8000 0x0 0x4000>; -+ }; -+ -+ usb2phy0_grf: syscon@fd5d0000 { -+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; -+ reg = <0x0 0xfd5d0000 0x0 0x4000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ u2phy0: usb2phy@0 { -+ compatible = "rockchip,rk3588-usb2phy"; -+ reg = <0x0 0x10>; -+ #clock-cells = <0>; -+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; -+ clock-names = "phyclk"; -+ clock-output-names = "usb480m_phy0"; -+ interrupts = ; -+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; -+ reset-names = "phy", "apb"; -+ status = "disabled"; -+ -+ u2phy0_otg: otg-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ usb2phy2_grf: syscon@fd5d8000 { -+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; -+ reg = <0x0 0xfd5d8000 0x0 0x4000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ u2phy2: usb2phy@8000 { -+ compatible = "rockchip,rk3588-usb2phy"; -+ reg = <0x8000 0x10>; -+ #clock-cells = <0>; -+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; -+ clock-names = "phyclk"; -+ clock-output-names = "usb480m_phy2"; -+ interrupts = ; -+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; -+ reset-names = "phy", "apb"; -+ status = "disabled"; -+ -+ u2phy2_host: host-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ usb2phy3_grf: syscon@fd5dc000 { -+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; -+ reg = <0x0 0xfd5dc000 0x0 0x4000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ u2phy3: usb2phy@c000 { -+ compatible = "rockchip,rk3588-usb2phy"; -+ reg = <0xc000 0x10>; -+ #clock-cells = <0>; -+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; -+ clock-names = "phyclk"; -+ clock-output-names = "usb480m_phy3"; -+ interrupts = ; -+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; -+ reset-names = "phy", "apb"; -+ status = "disabled"; -+ -+ u2phy3_host: host-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ hdptxphy0_grf: syscon@fd5e0000 { -+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; -+ reg = <0x0 0xfd5e0000 0x0 0x100>; -+ }; -+ -+ ioc: syscon@fd5f0000 { -+ compatible = "rockchip,rk3588-ioc", "syscon"; -+ reg = <0x0 0xfd5f0000 0x0 0x10000>; -+ }; -+ -+ system_sram1: sram@fd600000 { -+ compatible = "mmio-sram"; -+ reg = <0x0 0xfd600000 0x0 0x100000>; -+ ranges = <0x0 0x0 0xfd600000 0x100000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; -+ -+ cru: clock-controller@fd7c0000 { -+ compatible = "rockchip,rk3588-cru"; -+ reg = <0x0 0xfd7c0000 0x0 0x5c000>; -+ assigned-clocks = -+ <&cru PLL_PPLL>, <&cru PLL_AUPLL>, -+ <&cru PLL_NPLL>, <&cru PLL_GPLL>, -+ <&cru ACLK_CENTER_ROOT>, -+ <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, -+ <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, -+ <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, -+ <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, -+ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, -+ <&cru CLK_GPU>; -+ assigned-clock-rates = -+ <1100000000>, <786432000>, -+ <850000000>, <1188000000>, -+ <702000000>, -+ <400000000>, <500000000>, -+ <800000000>, <100000000>, -+ <400000000>, <100000000>, -+ <200000000>, <500000000>, -+ <375000000>, <150000000>, -+ <200000000>; -+ rockchip,grf = <&php_grf>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ i2c0: i2c@fd880000 { -+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfd880000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; -+ clock-names = "i2c", "pclk"; -+ pinctrl-0 = <&i2c0m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ uart0: serial@fd890000 { -+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfd890000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 6>, <&dmac0 7>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart0m1_xfer>; -+ pinctrl-names = "default"; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ status = "disabled"; -+ }; -+ -+ pwm0: pwm@fd8b0000 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfd8b0000 0x0 0x10>; -+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm0m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm1: pwm@fd8b0010 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfd8b0010 0x0 0x10>; -+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm1m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm2: pwm@fd8b0020 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfd8b0020 0x0 0x10>; -+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm2m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm3: pwm@fd8b0030 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfd8b0030 0x0 0x10>; -+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm3m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pmu: power-management@fd8d8000 { -+ compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; -+ reg = <0x0 0xfd8d8000 0x0 0x400>; -+ -+ power: power-controller { -+ compatible = "rockchip,rk3588-power-controller"; -+ #address-cells = <1>; -+ #power-domain-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ /* These power domains are grouped by VD_NPU */ -+ power-domain@RK3588_PD_NPU { -+ reg = ; -+ #power-domain-cells = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ power-domain@RK3588_PD_NPUTOP { -+ reg = ; -+ clocks = <&cru HCLK_NPU_ROOT>, -+ <&cru PCLK_NPU_ROOT>, -+ <&cru CLK_NPU_DSU0>, -+ <&cru HCLK_NPU_CM0_ROOT>; -+ pm_qos = <&qos_npu0_mwr>, -+ <&qos_npu0_mro>, -+ <&qos_mcu_npu>; -+ #power-domain-cells = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ power-domain@RK3588_PD_NPU1 { -+ reg = ; -+ clocks = <&cru HCLK_NPU_ROOT>, -+ <&cru PCLK_NPU_ROOT>, -+ <&cru CLK_NPU_DSU0>; -+ pm_qos = <&qos_npu1>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_NPU2 { -+ reg = ; -+ clocks = <&cru HCLK_NPU_ROOT>, -+ <&cru PCLK_NPU_ROOT>, -+ <&cru CLK_NPU_DSU0>; -+ pm_qos = <&qos_npu2>; -+ #power-domain-cells = <0>; -+ }; -+ }; -+ }; -+ /* These power domains are grouped by VD_GPU */ -+ power-domain@RK3588_PD_GPU { -+ reg = ; -+ clocks = <&cru CLK_GPU>, -+ <&cru CLK_GPU_COREGROUP>, -+ <&cru CLK_GPU_STACKS>; -+ pm_qos = <&qos_gpu_m0>, -+ <&qos_gpu_m1>, -+ <&qos_gpu_m2>, -+ <&qos_gpu_m3>; -+ #power-domain-cells = <0>; -+ }; -+ /* These power domains are grouped by VD_VCODEC */ -+ power-domain@RK3588_PD_VCODEC { -+ reg = ; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #power-domain-cells = <0>; -+ -+ power-domain@RK3588_PD_RKVDEC0 { -+ reg = ; -+ clocks = <&cru HCLK_RKVDEC0>, -+ <&cru HCLK_VDPU_ROOT>, -+ <&cru ACLK_VDPU_ROOT>, -+ <&cru ACLK_RKVDEC0>, -+ <&cru ACLK_RKVDEC_CCU>; -+ pm_qos = <&qos_rkvdec0>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_RKVDEC1 { -+ reg = ; -+ clocks = <&cru HCLK_RKVDEC1>, -+ <&cru HCLK_VDPU_ROOT>, -+ <&cru ACLK_VDPU_ROOT>, -+ <&cru ACLK_RKVDEC1>; -+ pm_qos = <&qos_rkvdec1>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_VENC0 { -+ reg = ; -+ clocks = <&cru HCLK_RKVENC0>, -+ <&cru ACLK_RKVENC0>; -+ pm_qos = <&qos_rkvenc0_m0ro>, -+ <&qos_rkvenc0_m1ro>, -+ <&qos_rkvenc0_m2wo>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #power-domain-cells = <0>; -+ -+ power-domain@RK3588_PD_VENC1 { -+ reg = ; -+ clocks = <&cru HCLK_RKVENC1>, -+ <&cru HCLK_RKVENC0>, -+ <&cru ACLK_RKVENC0>, -+ <&cru ACLK_RKVENC1>; -+ pm_qos = <&qos_rkvenc1_m0ro>, -+ <&qos_rkvenc1_m1ro>, -+ <&qos_rkvenc1_m2wo>; -+ #power-domain-cells = <0>; -+ }; -+ }; -+ }; -+ /* These power domains are grouped by VD_LOGIC */ -+ power-domain@RK3588_PD_VDPU { -+ reg = ; -+ clocks = <&cru HCLK_VDPU_ROOT>, -+ <&cru ACLK_VDPU_LOW_ROOT>, -+ <&cru ACLK_VDPU_ROOT>, -+ <&cru ACLK_JPEG_DECODER_ROOT>, -+ <&cru ACLK_IEP2P0>, -+ <&cru HCLK_IEP2P0>, -+ <&cru ACLK_JPEG_ENCODER0>, -+ <&cru HCLK_JPEG_ENCODER0>, -+ <&cru ACLK_JPEG_ENCODER1>, -+ <&cru HCLK_JPEG_ENCODER1>, -+ <&cru ACLK_JPEG_ENCODER2>, -+ <&cru HCLK_JPEG_ENCODER2>, -+ <&cru ACLK_JPEG_ENCODER3>, -+ <&cru HCLK_JPEG_ENCODER3>, -+ <&cru ACLK_JPEG_DECODER>, -+ <&cru HCLK_JPEG_DECODER>, -+ <&cru ACLK_RGA2>, -+ <&cru HCLK_RGA2>; -+ pm_qos = <&qos_iep>, -+ <&qos_jpeg_dec>, -+ <&qos_jpeg_enc0>, -+ <&qos_jpeg_enc1>, -+ <&qos_jpeg_enc2>, -+ <&qos_jpeg_enc3>, -+ <&qos_rga2_mro>, -+ <&qos_rga2_mwo>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #power-domain-cells = <0>; -+ -+ -+ power-domain@RK3588_PD_AV1 { -+ reg = ; -+ clocks = <&cru PCLK_AV1>, -+ <&cru ACLK_AV1>, -+ <&cru HCLK_VDPU_ROOT>; -+ pm_qos = <&qos_av1>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_RKVDEC0 { -+ reg = ; -+ clocks = <&cru HCLK_RKVDEC0>, -+ <&cru HCLK_VDPU_ROOT>, -+ <&cru ACLK_VDPU_ROOT>, -+ <&cru ACLK_RKVDEC0>; -+ pm_qos = <&qos_rkvdec0>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_RKVDEC1 { -+ reg = ; -+ clocks = <&cru HCLK_RKVDEC1>, -+ <&cru HCLK_VDPU_ROOT>, -+ <&cru ACLK_VDPU_ROOT>; -+ pm_qos = <&qos_rkvdec1>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_RGA30 { -+ reg = ; -+ clocks = <&cru ACLK_RGA3_0>, -+ <&cru HCLK_RGA3_0>; -+ pm_qos = <&qos_rga3_0>; -+ #power-domain-cells = <0>; -+ }; -+ }; -+ power-domain@RK3588_PD_VOP { -+ reg = ; -+ clocks = <&cru PCLK_VOP_ROOT>, -+ <&cru HCLK_VOP_ROOT>, -+ <&cru ACLK_VOP>; -+ pm_qos = <&qos_vop_m0>, -+ <&qos_vop_m1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #power-domain-cells = <0>; -+ -+ power-domain@RK3588_PD_VO0 { -+ reg = ; -+ clocks = <&cru PCLK_VO0_ROOT>, -+ <&cru PCLK_VO0_S_ROOT>, -+ <&cru HCLK_VO0_S_ROOT>, -+ <&cru ACLK_VO0_ROOT>, -+ <&cru HCLK_HDCP0>, -+ <&cru ACLK_HDCP0>, -+ <&cru HCLK_VOP_ROOT>; -+ pm_qos = <&qos_hdcp0>; -+ #power-domain-cells = <0>; -+ }; -+ }; -+ power-domain@RK3588_PD_VO1 { -+ reg = ; -+ clocks = <&cru PCLK_VO1_ROOT>, -+ <&cru PCLK_VO1_S_ROOT>, -+ <&cru HCLK_VO1_S_ROOT>, -+ <&cru HCLK_HDCP1>, -+ <&cru ACLK_HDCP1>, -+ <&cru ACLK_HDMIRX_ROOT>, -+ <&cru HCLK_VO1USB_TOP_ROOT>; -+ pm_qos = <&qos_hdcp1>, -+ <&qos_hdmirx>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_VI { -+ reg = ; -+ clocks = <&cru HCLK_VI_ROOT>, -+ <&cru PCLK_VI_ROOT>, -+ <&cru HCLK_ISP0>, -+ <&cru ACLK_ISP0>, -+ <&cru HCLK_VICAP>, -+ <&cru ACLK_VICAP>; -+ pm_qos = <&qos_isp0_mro>, -+ <&qos_isp0_mwo>, -+ <&qos_vicap_m0>, -+ <&qos_vicap_m1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #power-domain-cells = <0>; -+ -+ power-domain@RK3588_PD_ISP1 { -+ reg = ; -+ clocks = <&cru HCLK_ISP1>, -+ <&cru ACLK_ISP1>, -+ <&cru HCLK_VI_ROOT>, -+ <&cru PCLK_VI_ROOT>; -+ pm_qos = <&qos_isp1_mwo>, -+ <&qos_isp1_mro>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_FEC { -+ reg = ; -+ clocks = <&cru HCLK_FISHEYE0>, -+ <&cru ACLK_FISHEYE0>, -+ <&cru HCLK_FISHEYE1>, -+ <&cru ACLK_FISHEYE1>, -+ <&cru PCLK_VI_ROOT>; -+ pm_qos = <&qos_fisheye0>, -+ <&qos_fisheye1>; -+ #power-domain-cells = <0>; -+ }; -+ }; -+ power-domain@RK3588_PD_RGA31 { -+ reg = ; -+ clocks = <&cru HCLK_RGA3_1>, -+ <&cru ACLK_RGA3_1>; -+ pm_qos = <&qos_rga3_1>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_USB { -+ reg = ; -+ clocks = <&cru PCLK_PHP_ROOT>, -+ <&cru ACLK_USB_ROOT>, -+ <&cru ACLK_USB>, -+ <&cru HCLK_USB_ROOT>, -+ <&cru HCLK_HOST0>, -+ <&cru HCLK_HOST_ARB0>, -+ <&cru HCLK_HOST1>, -+ <&cru HCLK_HOST_ARB1>; -+ pm_qos = <&qos_usb3_0>, -+ <&qos_usb3_1>, -+ <&qos_usb2host_0>, -+ <&qos_usb2host_1>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_GMAC { -+ reg = ; -+ clocks = <&cru PCLK_PHP_ROOT>, -+ <&cru ACLK_PCIE_ROOT>, -+ <&cru ACLK_PHP_ROOT>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_PCIE { -+ reg = ; -+ clocks = <&cru PCLK_PHP_ROOT>, -+ <&cru ACLK_PCIE_ROOT>, -+ <&cru ACLK_PHP_ROOT>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_SDIO { -+ reg = ; -+ clocks = <&cru HCLK_SDIO>, -+ <&cru HCLK_NVM_ROOT>; -+ pm_qos = <&qos_sdio>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_AUDIO { -+ reg = ; -+ clocks = <&cru HCLK_AUDIO_ROOT>, -+ <&cru PCLK_AUDIO_ROOT>; -+ #power-domain-cells = <0>; -+ }; -+ power-domain@RK3588_PD_SDMMC { -+ reg = ; -+ pm_qos = <&qos_sdmmc>; -+ #power-domain-cells = <0>; -+ }; -+ }; -+ }; -+ -+ av1d: video-codec@fdc70000 { -+ compatible = "rockchip,rk3588-av1-vpu"; -+ reg = <0x0 0xfdc70000 0x0 0x800>; -+ interrupts = ; -+ interrupt-names = "vdpu"; -+ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; -+ assigned-clock-rates = <400000000>, <400000000>; -+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; -+ clock-names = "aclk", "hclk"; -+ power-domains = <&power RK3588_PD_AV1>; -+ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; -+ }; -+ -+ vop: vop@fdd90000 { -+ compatible = "rockchip,rk3588-vop"; -+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; -+ reg-names = "vop", "gamma-lut"; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, -+ <&cru HCLK_VOP>, -+ <&cru DCLK_VOP0>, -+ <&cru DCLK_VOP1>, -+ <&cru DCLK_VOP2>, -+ <&cru DCLK_VOP3>, -+ <&cru PCLK_VOP_ROOT>; -+ clock-names = "aclk", -+ "hclk", -+ "dclk_vp0", -+ "dclk_vp1", -+ "dclk_vp2", -+ "dclk_vp3", -+ "pclk_vop"; -+ iommus = <&vop_mmu>; -+ power-domains = <&power RK3588_PD_VOP>; -+ rockchip,grf = <&sys_grf>; -+ rockchip,vop-grf = <&vop_grf>; -+ rockchip,vo1-grf = <&vo1_grf>; -+ rockchip,pmu = <&pmu>; -+ status = "disabled"; -+ -+ vop_out: ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ vp0: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ }; -+ -+ vp1: port@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ }; -+ -+ vp2: port@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ }; -+ -+ vp3: port@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <3>; -+ }; -+ }; -+ }; -+ -+ vop_mmu: iommu@fdd97e00 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; -+ clock-names = "aclk", "iface"; -+ #iommu-cells = <0>; -+ power-domains = <&power RK3588_PD_VOP>; -+ status = "disabled"; -+ }; -+ -+ i2s4_8ch: i2s@fddc0000 { -+ compatible = "rockchip,rk3588-i2s-tdm"; -+ reg = <0x0 0xfddc0000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; -+ assigned-clock-parents = <&cru PLL_AUPLL>; -+ dmas = <&dmac2 0>; -+ dma-names = "tx"; -+ power-domains = <&power RK3588_PD_VO0>; -+ resets = <&cru SRST_M_I2S4_8CH_TX>; -+ reset-names = "tx-m"; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2s5_8ch: i2s@fddf0000 { -+ compatible = "rockchip,rk3588-i2s-tdm"; -+ reg = <0x0 0xfddf0000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; -+ assigned-clock-parents = <&cru PLL_AUPLL>; -+ dmas = <&dmac2 2>; -+ dma-names = "tx"; -+ power-domains = <&power RK3588_PD_VO1>; -+ resets = <&cru SRST_M_I2S5_8CH_TX>; -+ reset-names = "tx-m"; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2s9_8ch: i2s@fddfc000 { -+ compatible = "rockchip,rk3588-i2s-tdm"; -+ reg = <0x0 0xfddfc000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; -+ assigned-clock-parents = <&cru PLL_AUPLL>; -+ dmas = <&dmac2 23>; -+ dma-names = "rx"; -+ power-domains = <&power RK3588_PD_VO1>; -+ resets = <&cru SRST_M_I2S9_8CH_RX>; -+ reset-names = "rx-m"; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ qos_gpu_m0: qos@fdf35000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf35000 0x0 0x20>; -+ }; -+ -+ qos_gpu_m1: qos@fdf35200 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf35200 0x0 0x20>; -+ }; -+ -+ qos_gpu_m2: qos@fdf35400 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf35400 0x0 0x20>; -+ }; -+ -+ qos_gpu_m3: qos@fdf35600 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf35600 0x0 0x20>; -+ }; -+ -+ qos_rga3_1: qos@fdf36000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf36000 0x0 0x20>; -+ }; -+ -+ qos_sdio: qos@fdf39000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf39000 0x0 0x20>; -+ }; -+ -+ qos_sdmmc: qos@fdf3d800 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf3d800 0x0 0x20>; -+ }; -+ -+ qos_usb3_1: qos@fdf3e000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf3e000 0x0 0x20>; -+ }; -+ -+ qos_usb3_0: qos@fdf3e200 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf3e200 0x0 0x20>; -+ }; -+ -+ qos_usb2host_0: qos@fdf3e400 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf3e400 0x0 0x20>; -+ }; -+ -+ qos_usb2host_1: qos@fdf3e600 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf3e600 0x0 0x20>; -+ }; -+ -+ qos_fisheye0: qos@fdf40000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf40000 0x0 0x20>; -+ }; -+ -+ qos_fisheye1: qos@fdf40200 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf40200 0x0 0x20>; -+ }; -+ -+ qos_isp0_mro: qos@fdf40400 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf40400 0x0 0x20>; -+ }; -+ -+ qos_isp0_mwo: qos@fdf40500 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf40500 0x0 0x20>; -+ }; -+ -+ qos_vicap_m0: qos@fdf40600 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf40600 0x0 0x20>; -+ }; -+ -+ qos_vicap_m1: qos@fdf40800 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf40800 0x0 0x20>; -+ }; -+ -+ qos_isp1_mwo: qos@fdf41000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf41000 0x0 0x20>; -+ }; -+ -+ qos_isp1_mro: qos@fdf41100 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf41100 0x0 0x20>; -+ }; -+ -+ qos_rkvenc0_m0ro: qos@fdf60000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf60000 0x0 0x20>; -+ }; -+ -+ qos_rkvenc0_m1ro: qos@fdf60200 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf60200 0x0 0x20>; -+ }; -+ -+ qos_rkvenc0_m2wo: qos@fdf60400 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf60400 0x0 0x20>; -+ }; -+ -+ qos_rkvenc1_m0ro: qos@fdf61000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf61000 0x0 0x20>; -+ }; -+ -+ qos_rkvenc1_m1ro: qos@fdf61200 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf61200 0x0 0x20>; -+ }; -+ -+ qos_rkvenc1_m2wo: qos@fdf61400 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf61400 0x0 0x20>; -+ }; -+ -+ qos_rkvdec0: qos@fdf62000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf62000 0x0 0x20>; -+ }; -+ -+ qos_rkvdec1: qos@fdf63000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf63000 0x0 0x20>; -+ }; -+ -+ qos_av1: qos@fdf64000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf64000 0x0 0x20>; -+ }; -+ -+ qos_iep: qos@fdf66000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf66000 0x0 0x20>; -+ }; -+ -+ qos_jpeg_dec: qos@fdf66200 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf66200 0x0 0x20>; -+ }; -+ -+ qos_jpeg_enc0: qos@fdf66400 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf66400 0x0 0x20>; -+ }; -+ -+ qos_jpeg_enc1: qos@fdf66600 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf66600 0x0 0x20>; -+ }; -+ -+ qos_jpeg_enc2: qos@fdf66800 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf66800 0x0 0x20>; -+ }; -+ -+ qos_jpeg_enc3: qos@fdf66a00 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf66a00 0x0 0x20>; -+ }; -+ -+ qos_rga2_mro: qos@fdf66c00 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf66c00 0x0 0x20>; -+ }; -+ -+ qos_rga2_mwo: qos@fdf66e00 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf66e00 0x0 0x20>; -+ }; -+ -+ qos_rga3_0: qos@fdf67000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf67000 0x0 0x20>; -+ }; -+ -+ qos_vdpu: qos@fdf67200 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf67200 0x0 0x20>; -+ }; -+ -+ qos_npu1: qos@fdf70000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf70000 0x0 0x20>; -+ }; -+ -+ qos_npu2: qos@fdf71000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf71000 0x0 0x20>; -+ }; -+ -+ qos_npu0_mwr: qos@fdf72000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf72000 0x0 0x20>; -+ }; -+ -+ qos_npu0_mro: qos@fdf72200 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf72200 0x0 0x20>; -+ }; -+ -+ qos_mcu_npu: qos@fdf72400 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf72400 0x0 0x20>; -+ }; -+ -+ qos_hdcp0: qos@fdf80000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf80000 0x0 0x20>; -+ }; -+ -+ qos_hdcp1: qos@fdf81000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf81000 0x0 0x20>; -+ }; -+ -+ qos_hdmirx: qos@fdf81200 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf81200 0x0 0x20>; -+ }; -+ -+ qos_vop_m0: qos@fdf82000 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf82000 0x0 0x20>; -+ }; -+ -+ qos_vop_m1: qos@fdf82200 { -+ compatible = "rockchip,rk3588-qos", "syscon"; -+ reg = <0x0 0xfdf82200 0x0 0x20>; -+ }; -+ -+ dfi: dfi@fe060000 { -+ reg = <0x00 0xfe060000 0x00 0x10000>; -+ compatible = "rockchip,rk3588-dfi"; -+ interrupts = , -+ , -+ , -+ ; -+ rockchip,pmu = <&pmu1grf>; -+ }; -+ -+ pcie2x1l1: pcie@fe180000 { -+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -+ bus-range = <0x30 0x3f>; -+ clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, -+ <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, -+ <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", -+ "aux", "pipe"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, -+ <0 0 0 2 &pcie2x1l1_intc 1>, -+ <0 0 0 3 &pcie2x1l1_intc 2>, -+ <0 0 0 4 &pcie2x1l1_intc 3>; -+ linux,pci-domain = <3>; -+ max-link-speed = <2>; -+ msi-map = <0x3000 &its0 0x3000 0x1000>; -+ num-lanes = <1>; -+ phys = <&combphy2_psu PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3588_PD_PCIE>; -+ ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, -+ <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, -+ <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; -+ reg = <0xa 0x40c00000 0x0 0x00400000>, -+ <0x0 0xfe180000 0x0 0x00010000>, -+ <0x0 0xf3000000 0x0 0x00100000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; -+ reset-names = "pwr", "pipe"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ status = "disabled"; -+ -+ pcie2x1l1_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ pcie2x1l2: pcie@fe190000 { -+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -+ bus-range = <0x40 0x4f>; -+ clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, -+ <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, -+ <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", -+ "aux", "pipe"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, -+ <0 0 0 2 &pcie2x1l2_intc 1>, -+ <0 0 0 3 &pcie2x1l2_intc 2>, -+ <0 0 0 4 &pcie2x1l2_intc 3>; -+ linux,pci-domain = <4>; -+ max-link-speed = <2>; -+ msi-map = <0x4000 &its0 0x4000 0x1000>; -+ num-lanes = <1>; -+ phys = <&combphy0_ps PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3588_PD_PCIE>; -+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, -+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, -+ <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; -+ reg = <0xa 0x41000000 0x0 0x00400000>, -+ <0x0 0xfe190000 0x0 0x00010000>, -+ <0x0 0xf4000000 0x0 0x00100000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; -+ reset-names = "pwr", "pipe"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ status = "disabled"; -+ -+ pcie2x1l2_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ gmac1: ethernet@fe1c0000 { -+ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; -+ reg = <0x0 0xfe1c0000 0x0 0x10000>; -+ interrupts = , -+ ; -+ interrupt-names = "macirq", "eth_wake_irq"; -+ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, -+ <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, -+ <&cru CLK_GMAC1_PTP_REF>; -+ clock-names = "stmmaceth", "clk_mac_ref", -+ "pclk_mac", "aclk_mac", -+ "ptp_ref"; -+ power-domains = <&power RK3588_PD_GMAC>; -+ resets = <&cru SRST_A_GMAC1>; -+ reset-names = "stmmaceth"; -+ rockchip,grf = <&sys_grf>; -+ rockchip,php-grf = <&php_grf>; -+ snps,axi-config = <&gmac1_stmmac_axi_setup>; -+ snps,mixed-burst; -+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; -+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; -+ snps,tso; -+ status = "disabled"; -+ -+ mdio1: mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ }; -+ -+ gmac1_stmmac_axi_setup: stmmac-axi-config { -+ snps,blen = <0 0 0 0 16 8 4>; -+ snps,wr_osr_lmt = <4>; -+ snps,rd_osr_lmt = <8>; -+ }; -+ -+ gmac1_mtl_rx_setup: rx-queues-config { -+ snps,rx-queues-to-use = <2>; -+ queue0 {}; -+ queue1 {}; -+ }; -+ -+ gmac1_mtl_tx_setup: tx-queues-config { -+ snps,tx-queues-to-use = <2>; -+ queue0 {}; -+ queue1 {}; -+ }; -+ }; -+ -+ sata0: sata@fe210000 { -+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; -+ reg = <0 0xfe210000 0 0x1000>; -+ interrupts = ; -+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, -+ <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, -+ <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; -+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; -+ ports-implemented = <0x1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sata-port@0 { -+ reg = <0>; -+ hba-port-cap = ; -+ phys = <&combphy0_ps PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ snps,rx-ts-max = <32>; -+ snps,tx-ts-max = <32>; -+ }; -+ }; -+ -+ sata2: sata@fe230000 { -+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; -+ reg = <0 0xfe230000 0 0x1000>; -+ interrupts = ; -+ clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, -+ <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, -+ <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; -+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; -+ ports-implemented = <0x1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sata-port@0 { -+ reg = <0>; -+ hba-port-cap = ; -+ phys = <&combphy2_psu PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ snps,rx-ts-max = <32>; -+ snps,tx-ts-max = <32>; -+ }; -+ }; -+ -+ sfc: spi@fe2b0000 { -+ compatible = "rockchip,sfc"; -+ reg = <0x0 0xfe2b0000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; -+ clock-names = "clk_sfc", "hclk_sfc"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ sdmmc: mmc@fe2c0000 { -+ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; -+ reg = <0x0 0xfe2c0000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, -+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; -+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -+ fifo-depth = <0x100>; -+ max-frequency = <200000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; -+ power-domains = <&power RK3588_PD_SDMMC>; -+ status = "disabled"; -+ }; -+ -+ sdio: mmc@fe2d0000 { -+ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; -+ reg = <0x00 0xfe2d0000 0x00 0x4000>; -+ interrupts = ; -+ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, -+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; -+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -+ fifo-depth = <0x100>; -+ max-frequency = <200000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdiom1_pins>; -+ power-domains = <&power RK3588_PD_SDIO>; -+ status = "disabled"; -+ }; -+ -+ sdhci: mmc@fe2e0000 { -+ compatible = "rockchip,rk3588-dwcmshc"; -+ reg = <0x0 0xfe2e0000 0x0 0x10000>; -+ interrupts = ; -+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; -+ assigned-clock-rates = <200000000>, <24000000>, <200000000>; -+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, -+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, -+ <&cru TMCLK_EMMC>; -+ clock-names = "core", "bus", "axi", "block", "timer"; -+ max-frequency = <200000000>; -+ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, -+ <&emmc_cmd>, <&emmc_data_strobe>; -+ pinctrl-names = "default"; -+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, -+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, -+ <&cru SRST_T_EMMC>; -+ reset-names = "core", "bus", "axi", "block", "timer"; -+ status = "disabled"; -+ }; -+ -+ i2s0_8ch: i2s@fe470000 { -+ compatible = "rockchip,rk3588-i2s-tdm"; -+ reg = <0x0 0xfe470000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; -+ assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; -+ dmas = <&dmac0 0>, <&dmac0 1>; -+ dma-names = "tx", "rx"; -+ power-domains = <&power RK3588_PD_AUDIO>; -+ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; -+ reset-names = "tx-m", "rx-m"; -+ rockchip,trcm-sync-tx-only; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s0_lrck -+ &i2s0_sclk -+ &i2s0_sdi0 -+ &i2s0_sdi1 -+ &i2s0_sdi2 -+ &i2s0_sdi3 -+ &i2s0_sdo0 -+ &i2s0_sdo1 -+ &i2s0_sdo2 -+ &i2s0_sdo3>; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2s1_8ch: i2s@fe480000 { -+ compatible = "rockchip,rk3588-i2s-tdm"; -+ reg = <0x0 0xfe480000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ dmas = <&dmac0 2>, <&dmac0 3>; -+ dma-names = "tx", "rx"; -+ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; -+ reset-names = "tx-m", "rx-m"; -+ rockchip,trcm-sync-tx-only; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s1m0_lrck -+ &i2s1m0_sclk -+ &i2s1m0_sdi0 -+ &i2s1m0_sdi1 -+ &i2s1m0_sdi2 -+ &i2s1m0_sdi3 -+ &i2s1m0_sdo0 -+ &i2s1m0_sdo1 -+ &i2s1m0_sdo2 -+ &i2s1m0_sdo3>; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2s2_2ch: i2s@fe490000 { -+ compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; -+ reg = <0x0 0xfe490000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; -+ clock-names = "i2s_clk", "i2s_hclk"; -+ assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; -+ assigned-clock-parents = <&cru PLL_AUPLL>; -+ dmas = <&dmac1 0>, <&dmac1 1>; -+ dma-names = "tx", "rx"; -+ power-domains = <&power RK3588_PD_AUDIO>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s2m1_lrck -+ &i2s2m1_sclk -+ &i2s2m1_sdi -+ &i2s2m1_sdo>; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2s3_2ch: i2s@fe4a0000 { -+ compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; -+ reg = <0x0 0xfe4a0000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; -+ clock-names = "i2s_clk", "i2s_hclk"; -+ assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; -+ assigned-clock-parents = <&cru PLL_AUPLL>; -+ dmas = <&dmac1 2>, <&dmac1 3>; -+ dma-names = "tx", "rx"; -+ power-domains = <&power RK3588_PD_AUDIO>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s3_lrck -+ &i2s3_sclk -+ &i2s3_sdi -+ &i2s3_sdo>; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ gic: interrupt-controller@fe600000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ -+ <0x0 0xfe680000 0 0x100000>; /* GICR */ -+ interrupts = ; -+ interrupt-controller; -+ mbi-alias = <0x0 0xfe610000>; -+ mbi-ranges = <424 56>; -+ msi-controller; -+ ranges; -+ #address-cells = <2>; -+ #interrupt-cells = <4>; -+ #size-cells = <2>; -+ -+ its0: msi-controller@fe640000 { -+ compatible = "arm,gic-v3-its"; -+ reg = <0x0 0xfe640000 0x0 0x20000>; -+ msi-controller; -+ #msi-cells = <1>; -+ }; -+ -+ its1: msi-controller@fe660000 { -+ compatible = "arm,gic-v3-its"; -+ reg = <0x0 0xfe660000 0x0 0x20000>; -+ msi-controller; -+ #msi-cells = <1>; -+ }; -+ -+ ppi-partitions { -+ ppi_partition0: interrupt-partition-0 { -+ affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; -+ }; -+ -+ ppi_partition1: interrupt-partition-1 { -+ affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; -+ }; -+ }; -+ }; -+ -+ dmac0: dma-controller@fea10000 { -+ compatible = "arm,pl330", "arm,primecell"; -+ reg = <0x0 0xfea10000 0x0 0x4000>; -+ interrupts = , -+ ; -+ arm,pl330-periph-burst; -+ clocks = <&cru ACLK_DMAC0>; -+ clock-names = "apb_pclk"; -+ #dma-cells = <1>; -+ }; -+ -+ dmac1: dma-controller@fea30000 { -+ compatible = "arm,pl330", "arm,primecell"; -+ reg = <0x0 0xfea30000 0x0 0x4000>; -+ interrupts = , -+ ; -+ arm,pl330-periph-burst; -+ clocks = <&cru ACLK_DMAC1>; -+ clock-names = "apb_pclk"; -+ #dma-cells = <1>; -+ }; -+ -+ i2c1: i2c@fea90000 { -+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfea90000 0x0 0x1000>; -+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; -+ clock-names = "i2c", "pclk"; -+ interrupts = ; -+ pinctrl-0 = <&i2c1m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@feaa0000 { -+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfeaa0000 0x0 0x1000>; -+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; -+ clock-names = "i2c", "pclk"; -+ interrupts = ; -+ pinctrl-0 = <&i2c2m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@feab0000 { -+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfeab0000 0x0 0x1000>; -+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; -+ clock-names = "i2c", "pclk"; -+ interrupts = ; -+ pinctrl-0 = <&i2c3m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@feac0000 { -+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfeac0000 0x0 0x1000>; -+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; -+ clock-names = "i2c", "pclk"; -+ interrupts = ; -+ pinctrl-0 = <&i2c4m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c5: i2c@fead0000 { -+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfead0000 0x0 0x1000>; -+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; -+ clock-names = "i2c", "pclk"; -+ interrupts = ; -+ pinctrl-0 = <&i2c5m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ timer0: timer@feae0000 { -+ compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; -+ reg = <0x0 0xfeae0000 0x0 0x20>; -+ interrupts = ; -+ clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; -+ clock-names = "pclk", "timer"; -+ }; -+ -+ wdt: watchdog@feaf0000 { -+ compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; -+ reg = <0x0 0xfeaf0000 0x0 0x100>; -+ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; -+ clock-names = "tclk", "pclk"; -+ interrupts = ; -+ }; -+ -+ spi0: spi@feb00000 { -+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; -+ reg = <0x0 0xfeb00000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; -+ clock-names = "spiclk", "apb_pclk"; -+ dmas = <&dmac0 14>, <&dmac0 15>; -+ dma-names = "tx", "rx"; -+ num-cs = <2>; -+ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@feb10000 { -+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; -+ reg = <0x0 0xfeb10000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; -+ clock-names = "spiclk", "apb_pclk"; -+ dmas = <&dmac0 16>, <&dmac0 17>; -+ dma-names = "tx", "rx"; -+ num-cs = <2>; -+ pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi2: spi@feb20000 { -+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; -+ reg = <0x0 0xfeb20000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; -+ clock-names = "spiclk", "apb_pclk"; -+ dmas = <&dmac1 15>, <&dmac1 16>; -+ dma-names = "tx", "rx"; -+ num-cs = <2>; -+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi3: spi@feb30000 { -+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; -+ reg = <0x0 0xfeb30000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; -+ clock-names = "spiclk", "apb_pclk"; -+ dmas = <&dmac1 17>, <&dmac1 18>; -+ dma-names = "tx", "rx"; -+ num-cs = <2>; -+ pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ uart1: serial@feb40000 { -+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfeb40000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 8>, <&dmac0 9>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart1m1_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@feb50000 { -+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfeb50000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 10>, <&dmac0 11>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart2m1_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart3: serial@feb60000 { -+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfeb60000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 12>, <&dmac0 13>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart3m1_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart4: serial@feb70000 { -+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfeb70000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac1 9>, <&dmac1 10>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart4m1_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart5: serial@feb80000 { -+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfeb80000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac1 11>, <&dmac1 12>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart5m1_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart6: serial@feb90000 { -+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfeb90000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac1 13>, <&dmac1 14>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart6m1_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart7: serial@feba0000 { -+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfeba0000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac2 7>, <&dmac2 8>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart7m1_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart8: serial@febb0000 { -+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfebb0000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac2 9>, <&dmac2 10>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart8m1_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart9: serial@febc0000 { -+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfebc0000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac2 11>, <&dmac2 12>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart9m1_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm4: pwm@febd0000 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfebd0000 0x0 0x10>; -+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm4m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm5: pwm@febd0010 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfebd0010 0x0 0x10>; -+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm5m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm6: pwm@febd0020 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfebd0020 0x0 0x10>; -+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm6m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm7: pwm@febd0030 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfebd0030 0x0 0x10>; -+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm7m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm8: pwm@febe0000 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfebe0000 0x0 0x10>; -+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm8m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm9: pwm@febe0010 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfebe0010 0x0 0x10>; -+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm9m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm10: pwm@febe0020 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfebe0020 0x0 0x10>; -+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm10m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm11: pwm@febe0030 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfebe0030 0x0 0x10>; -+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm11m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm12: pwm@febf0000 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfebf0000 0x0 0x10>; -+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm12m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm13: pwm@febf0010 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfebf0010 0x0 0x10>; -+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm13m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm14: pwm@febf0020 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfebf0020 0x0 0x10>; -+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm14m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm15: pwm@febf0030 { -+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfebf0030 0x0 0x10>; -+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm15m0_pins>; -+ pinctrl-names = "default"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ tsadc: tsadc@fec00000 { -+ compatible = "rockchip,rk3588-tsadc"; -+ reg = <0x0 0xfec00000 0x0 0x400>; -+ interrupts = ; -+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; -+ clock-names = "tsadc", "apb_pclk"; -+ assigned-clocks = <&cru CLK_TSADC>; -+ assigned-clock-rates = <2000000>; -+ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; -+ reset-names = "tsadc-apb", "tsadc"; -+ rockchip,hw-tshut-temp = <120000>; -+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ -+ pinctrl-0 = <&tsadc_gpio_func>; -+ pinctrl-1 = <&tsadc_shut>; -+ pinctrl-names = "gpio", "otpout"; -+ #thermal-sensor-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ saradc: adc@fec10000 { -+ compatible = "rockchip,rk3588-saradc"; -+ reg = <0x0 0xfec10000 0x0 0x10000>; -+ interrupts = ; -+ #io-channel-cells = <1>; -+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; -+ clock-names = "saradc", "apb_pclk"; -+ resets = <&cru SRST_P_SARADC>; -+ reset-names = "saradc-apb"; -+ status = "disabled"; -+ }; -+ -+ i2c6: i2c@fec80000 { -+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfec80000 0x0 0x1000>; -+ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; -+ clock-names = "i2c", "pclk"; -+ interrupts = ; -+ pinctrl-0 = <&i2c6m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c7: i2c@fec90000 { -+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfec90000 0x0 0x1000>; -+ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; -+ clock-names = "i2c", "pclk"; -+ interrupts = ; -+ pinctrl-0 = <&i2c7m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c8: i2c@feca0000 { -+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfeca0000 0x0 0x1000>; -+ clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; -+ clock-names = "i2c", "pclk"; -+ interrupts = ; -+ pinctrl-0 = <&i2c8m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi4: spi@fecb0000 { -+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; -+ reg = <0x0 0xfecb0000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; -+ clock-names = "spiclk", "apb_pclk"; -+ dmas = <&dmac2 13>, <&dmac2 14>; -+ dma-names = "tx", "rx"; -+ num-cs = <2>; -+ pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ otp: efuse@fecc0000 { -+ compatible = "rockchip,rk3588-otp"; -+ reg = <0x0 0xfecc0000 0x0 0x400>; -+ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, -+ <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; -+ clock-names = "otp", "apb_pclk", "phy", "arb"; -+ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, -+ <&cru SRST_OTPC_ARB>; -+ reset-names = "otp", "apb", "arb"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ cpu_code: cpu-code@2 { -+ reg = <0x02 0x2>; -+ }; -+ -+ otp_id: id@7 { -+ reg = <0x07 0x10>; -+ }; -+ -+ cpub0_leakage: cpu-leakage@17 { -+ reg = <0x17 0x1>; -+ }; -+ -+ cpub1_leakage: cpu-leakage@18 { -+ reg = <0x18 0x1>; -+ }; -+ -+ cpul_leakage: cpu-leakage@19 { -+ reg = <0x19 0x1>; -+ }; -+ -+ log_leakage: log-leakage@1a { -+ reg = <0x1a 0x1>; -+ }; -+ -+ gpu_leakage: gpu-leakage@1b { -+ reg = <0x1b 0x1>; -+ }; -+ -+ otp_cpu_version: cpu-version@1c { -+ reg = <0x1c 0x1>; -+ bits = <3 3>; -+ }; -+ -+ npu_leakage: npu-leakage@28 { -+ reg = <0x28 0x1>; -+ }; -+ -+ codec_leakage: codec-leakage@29 { -+ reg = <0x29 0x1>; -+ }; -+ }; -+ -+ dmac2: dma-controller@fed10000 { -+ compatible = "arm,pl330", "arm,primecell"; -+ reg = <0x0 0xfed10000 0x0 0x4000>; -+ interrupts = , -+ ; -+ arm,pl330-periph-burst; -+ clocks = <&cru ACLK_DMAC2>; -+ clock-names = "apb_pclk"; -+ #dma-cells = <1>; -+ }; -+ -+ hdptxphy_hdmi0: phy@fed60000 { -+ compatible = "rockchip,rk3588-hdptx-phy"; -+ reg = <0x0 0xfed60000 0x0 0x2000>; -+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; -+ clock-names = "ref", "apb"; -+ #phy-cells = <0>; -+ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, -+ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, -+ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, -+ <&cru SRST_HDPTX0_LCPLL>; -+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", -+ "lcpll"; -+ rockchip,grf = <&hdptxphy0_grf>; -+ status = "disabled"; -+ }; -+ -+ usbdp_phy0: phy@fed80000 { -+ compatible = "rockchip,rk3588-usbdp-phy"; -+ reg = <0x0 0xfed80000 0x0 0x10000>; -+ #phy-cells = <1>; -+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, -+ <&cru CLK_USBDP_PHY0_IMMORTAL>, -+ <&cru PCLK_USBDPPHY0>, -+ <&u2phy0>; -+ clock-names = "refclk", "immortal", "pclk", "utmi"; -+ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, -+ <&cru SRST_USBDP_COMBO_PHY0_CMN>, -+ <&cru SRST_USBDP_COMBO_PHY0_LANE>, -+ <&cru SRST_USBDP_COMBO_PHY0_PCS>, -+ <&cru SRST_P_USBDPPHY0>; -+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; -+ rockchip,u2phy-grf = <&usb2phy0_grf>; -+ rockchip,usb-grf = <&usb_grf>; -+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>; -+ rockchip,vo-grf = <&vo0_grf>; -+ status = "disabled"; -+ }; -+ -+ combphy0_ps: phy@fee00000 { -+ compatible = "rockchip,rk3588-naneng-combphy"; -+ reg = <0x0 0xfee00000 0x0 0x100>; -+ clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, -+ <&cru PCLK_PHP_ROOT>; -+ clock-names = "ref", "apb", "pipe"; -+ assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; -+ assigned-clock-rates = <100000000>; -+ #phy-cells = <1>; -+ resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; -+ reset-names = "phy", "apb"; -+ rockchip,pipe-grf = <&php_grf>; -+ rockchip,pipe-phy-grf = <&pipe_phy0_grf>; -+ status = "disabled"; -+ }; -+ -+ combphy2_psu: phy@fee20000 { -+ compatible = "rockchip,rk3588-naneng-combphy"; -+ reg = <0x0 0xfee20000 0x0 0x100>; -+ clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, -+ <&cru PCLK_PHP_ROOT>; -+ clock-names = "ref", "apb", "pipe"; -+ assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; -+ assigned-clock-rates = <100000000>; -+ #phy-cells = <1>; -+ resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; -+ reset-names = "phy", "apb"; -+ rockchip,pipe-grf = <&php_grf>; -+ rockchip,pipe-phy-grf = <&pipe_phy2_grf>; -+ status = "disabled"; -+ }; -+ -+ system_sram2: sram@ff001000 { -+ compatible = "mmio-sram"; -+ reg = <0x0 0xff001000 0x0 0xef000>; -+ ranges = <0x0 0x0 0xff001000 0xef000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; -+ -+ pinctrl: pinctrl { -+ compatible = "rockchip,rk3588-pinctrl"; -+ ranges; -+ rockchip,grf = <&ioc>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ gpio0: gpio@fd8a0000 { -+ compatible = "rockchip,gpio-bank"; -+ reg = <0x0 0xfd8a0000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; -+ gpio-controller; -+ gpio-ranges = <&pinctrl 0 0 32>; -+ interrupt-controller; -+ #gpio-cells = <2>; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio1: gpio@fec20000 { -+ compatible = "rockchip,gpio-bank"; -+ reg = <0x0 0xfec20000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; -+ gpio-controller; -+ gpio-ranges = <&pinctrl 0 32 32>; -+ interrupt-controller; -+ #gpio-cells = <2>; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio2: gpio@fec30000 { -+ compatible = "rockchip,gpio-bank"; -+ reg = <0x0 0xfec30000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; -+ gpio-controller; -+ gpio-ranges = <&pinctrl 0 64 32>; -+ interrupt-controller; -+ #gpio-cells = <2>; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio3: gpio@fec40000 { -+ compatible = "rockchip,gpio-bank"; -+ reg = <0x0 0xfec40000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; -+ gpio-controller; -+ gpio-ranges = <&pinctrl 0 96 32>; -+ interrupt-controller; -+ #gpio-cells = <2>; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio4: gpio@fec50000 { -+ compatible = "rockchip,gpio-bank"; -+ reg = <0x0 0xfec50000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; -+ gpio-controller; -+ gpio-ranges = <&pinctrl 0 128 32>; -+ interrupt-controller; -+ #gpio-cells = <2>; -+ #interrupt-cells = <2>; -+ }; -+ }; -+}; -+ -+#include "rk3588-base-pinctrl.dtsi" ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -0,0 +1,413 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ */ -+ -+#include "rk3588-base.dtsi" -+#include "rk3588-extra-pinctrl.dtsi" -+ -+/ { -+ usb_host1_xhci: usb@fc400000 { -+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; -+ reg = <0x0 0xfc400000 0x0 0x400000>; -+ interrupts = ; -+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, -+ <&cru ACLK_USB3OTG1>; -+ clock-names = "ref_clk", "suspend_clk", "bus_clk"; -+ dr_mode = "otg"; -+ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi_wide"; -+ power-domains = <&power RK3588_PD_USB>; -+ resets = <&cru SRST_A_USB3OTG1>; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ status = "disabled"; -+ }; -+ -+ pcie30_phy_grf: syscon@fd5b8000 { -+ compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; -+ reg = <0x0 0xfd5b8000 0x0 0x10000>; -+ }; -+ -+ pipe_phy1_grf: syscon@fd5c0000 { -+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; -+ reg = <0x0 0xfd5c0000 0x0 0x100>; -+ }; -+ -+ usbdpphy1_grf: syscon@fd5cc000 { -+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; -+ reg = <0x0 0xfd5cc000 0x0 0x4000>; -+ }; -+ -+ usb2phy1_grf: syscon@fd5d4000 { -+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; -+ reg = <0x0 0xfd5d4000 0x0 0x4000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ u2phy1: usb2phy@4000 { -+ compatible = "rockchip,rk3588-usb2phy"; -+ reg = <0x4000 0x10>; -+ #clock-cells = <0>; -+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; -+ clock-names = "phyclk"; -+ clock-output-names = "usb480m_phy1"; -+ interrupts = ; -+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; -+ reset-names = "phy", "apb"; -+ status = "disabled"; -+ -+ u2phy1_otg: otg-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ i2s8_8ch: i2s@fddc8000 { -+ compatible = "rockchip,rk3588-i2s-tdm"; -+ reg = <0x0 0xfddc8000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; -+ assigned-clock-parents = <&cru PLL_AUPLL>; -+ dmas = <&dmac2 22>; -+ dma-names = "tx"; -+ power-domains = <&power RK3588_PD_VO0>; -+ resets = <&cru SRST_M_I2S8_8CH_TX>; -+ reset-names = "tx-m"; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2s6_8ch: i2s@fddf4000 { -+ compatible = "rockchip,rk3588-i2s-tdm"; -+ reg = <0x0 0xfddf4000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; -+ assigned-clock-parents = <&cru PLL_AUPLL>; -+ dmas = <&dmac2 4>; -+ dma-names = "tx"; -+ power-domains = <&power RK3588_PD_VO1>; -+ resets = <&cru SRST_M_I2S6_8CH_TX>; -+ reset-names = "tx-m"; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2s7_8ch: i2s@fddf8000 { -+ compatible = "rockchip,rk3588-i2s-tdm"; -+ reg = <0x0 0xfddf8000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; -+ assigned-clock-parents = <&cru PLL_AUPLL>; -+ dmas = <&dmac2 21>; -+ dma-names = "rx"; -+ power-domains = <&power RK3588_PD_VO1>; -+ resets = <&cru SRST_M_I2S7_8CH_RX>; -+ reset-names = "rx-m"; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2s10_8ch: i2s@fde00000 { -+ compatible = "rockchip,rk3588-i2s-tdm"; -+ reg = <0x0 0xfde00000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; -+ assigned-clock-parents = <&cru PLL_AUPLL>; -+ dmas = <&dmac2 24>; -+ dma-names = "rx"; -+ power-domains = <&power RK3588_PD_VO1>; -+ resets = <&cru SRST_M_I2S10_8CH_RX>; -+ reset-names = "rx-m"; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ pcie3x4: pcie@fe150000 { -+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x00 0x0f>; -+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, -+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, -+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", -+ "aux", "pipe"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, -+ <0 0 0 2 &pcie3x4_intc 1>, -+ <0 0 0 3 &pcie3x4_intc 2>, -+ <0 0 0 4 &pcie3x4_intc 3>; -+ linux,pci-domain = <0>; -+ max-link-speed = <3>; -+ msi-map = <0x0000 &its1 0x0000 0x1000>; -+ num-lanes = <4>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3588_PD_PCIE>; -+ ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, -+ <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, -+ <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; -+ reg = <0xa 0x40000000 0x0 0x00400000>, -+ <0x0 0xfe150000 0x0 0x00010000>, -+ <0x0 0xf0000000 0x0 0x00100000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; -+ reset-names = "pwr", "pipe"; -+ status = "disabled"; -+ -+ pcie3x4_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ pcie3x2: pcie@fe160000 { -+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x10 0x1f>; -+ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, -+ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, -+ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", -+ "aux", "pipe"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, -+ <0 0 0 2 &pcie3x2_intc 1>, -+ <0 0 0 3 &pcie3x2_intc 2>, -+ <0 0 0 4 &pcie3x2_intc 3>; -+ linux,pci-domain = <1>; -+ max-link-speed = <3>; -+ msi-map = <0x1000 &its1 0x1000 0x1000>; -+ num-lanes = <2>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3588_PD_PCIE>; -+ ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, -+ <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, -+ <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; -+ reg = <0xa 0x40400000 0x0 0x00400000>, -+ <0x0 0xfe160000 0x0 0x00010000>, -+ <0x0 0xf1000000 0x0 0x00100000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; -+ reset-names = "pwr", "pipe"; -+ status = "disabled"; -+ -+ pcie3x2_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ pcie2x1l0: pcie@fe170000 { -+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -+ bus-range = <0x20 0x2f>; -+ clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, -+ <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, -+ <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", -+ "aux", "pipe"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, -+ <0 0 0 2 &pcie2x1l0_intc 1>, -+ <0 0 0 3 &pcie2x1l0_intc 2>, -+ <0 0 0 4 &pcie2x1l0_intc 3>; -+ linux,pci-domain = <2>; -+ max-link-speed = <2>; -+ msi-map = <0x2000 &its0 0x2000 0x1000>; -+ num-lanes = <1>; -+ phys = <&combphy1_ps PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3588_PD_PCIE>; -+ ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, -+ <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, -+ <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; -+ reg = <0xa 0x40800000 0x0 0x00400000>, -+ <0x0 0xfe170000 0x0 0x00010000>, -+ <0x0 0xf2000000 0x0 0x00100000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; -+ reset-names = "pwr", "pipe"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ status = "disabled"; -+ -+ pcie2x1l0_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ gmac0: ethernet@fe1b0000 { -+ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; -+ reg = <0x0 0xfe1b0000 0x0 0x10000>; -+ interrupts = , -+ ; -+ interrupt-names = "macirq", "eth_wake_irq"; -+ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, -+ <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, -+ <&cru CLK_GMAC0_PTP_REF>; -+ clock-names = "stmmaceth", "clk_mac_ref", -+ "pclk_mac", "aclk_mac", -+ "ptp_ref"; -+ power-domains = <&power RK3588_PD_GMAC>; -+ resets = <&cru SRST_A_GMAC0>; -+ reset-names = "stmmaceth"; -+ rockchip,grf = <&sys_grf>; -+ rockchip,php-grf = <&php_grf>; -+ snps,axi-config = <&gmac0_stmmac_axi_setup>; -+ snps,mixed-burst; -+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; -+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; -+ snps,tso; -+ status = "disabled"; -+ -+ mdio0: mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ }; -+ -+ gmac0_stmmac_axi_setup: stmmac-axi-config { -+ snps,blen = <0 0 0 0 16 8 4>; -+ snps,wr_osr_lmt = <4>; -+ snps,rd_osr_lmt = <8>; -+ }; -+ -+ gmac0_mtl_rx_setup: rx-queues-config { -+ snps,rx-queues-to-use = <2>; -+ queue0 {}; -+ queue1 {}; -+ }; -+ -+ gmac0_mtl_tx_setup: tx-queues-config { -+ snps,tx-queues-to-use = <2>; -+ queue0 {}; -+ queue1 {}; -+ }; -+ }; -+ -+ sata1: sata@fe220000 { -+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; -+ reg = <0 0xfe220000 0 0x1000>; -+ interrupts = ; -+ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, -+ <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, -+ <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; -+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; -+ ports-implemented = <0x1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sata-port@0 { -+ reg = <0>; -+ hba-port-cap = ; -+ phys = <&combphy1_ps PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ snps,rx-ts-max = <32>; -+ snps,tx-ts-max = <32>; -+ }; -+ }; -+ -+ usbdp_phy1: phy@fed90000 { -+ compatible = "rockchip,rk3588-usbdp-phy"; -+ reg = <0x0 0xfed90000 0x0 0x10000>; -+ #phy-cells = <1>; -+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, -+ <&cru CLK_USBDP_PHY1_IMMORTAL>, -+ <&cru PCLK_USBDPPHY1>, -+ <&u2phy1>; -+ clock-names = "refclk", "immortal", "pclk", "utmi"; -+ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, -+ <&cru SRST_USBDP_COMBO_PHY1_CMN>, -+ <&cru SRST_USBDP_COMBO_PHY1_LANE>, -+ <&cru SRST_USBDP_COMBO_PHY1_PCS>, -+ <&cru SRST_P_USBDPPHY1>; -+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; -+ rockchip,u2phy-grf = <&usb2phy1_grf>; -+ rockchip,usb-grf = <&usb_grf>; -+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>; -+ rockchip,vo-grf = <&vo0_grf>; -+ status = "disabled"; -+ }; -+ -+ combphy1_ps: phy@fee10000 { -+ compatible = "rockchip,rk3588-naneng-combphy"; -+ reg = <0x0 0xfee10000 0x0 0x100>; -+ clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, -+ <&cru PCLK_PHP_ROOT>; -+ clock-names = "ref", "apb", "pipe"; -+ assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; -+ assigned-clock-rates = <100000000>; -+ #phy-cells = <1>; -+ resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; -+ reset-names = "phy", "apb"; -+ rockchip,pipe-grf = <&php_grf>; -+ rockchip,pipe-phy-grf = <&pipe_phy1_grf>; -+ status = "disabled"; -+ }; -+ -+ pcie30phy: phy@fee80000 { -+ compatible = "rockchip,rk3588-pcie3-phy"; -+ reg = <0x0 0xfee80000 0x0 0x20000>; -+ #phy-cells = <0>; -+ clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; -+ clock-names = "pclk"; -+ resets = <&cru SRST_PCIE30_PHY>; -+ reset-names = "phy"; -+ rockchip,pipe-grf = <&php_grf>; -+ rockchip,phy-grf = <&pcie30_phy_grf>; -+ status = "disabled"; -+ }; -+}; ---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -@@ -1,413 +1,7 @@ - // SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /* -- * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd. -+ * - */ - --#include "rk3588s.dtsi" --#include "rk3588-pinctrl.dtsi" -- --/ { -- usb_host1_xhci: usb@fc400000 { -- compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; -- reg = <0x0 0xfc400000 0x0 0x400000>; -- interrupts = ; -- clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, -- <&cru ACLK_USB3OTG1>; -- clock-names = "ref_clk", "suspend_clk", "bus_clk"; -- dr_mode = "otg"; -- phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; -- phy-names = "usb2-phy", "usb3-phy"; -- phy_type = "utmi_wide"; -- power-domains = <&power RK3588_PD_USB>; -- resets = <&cru SRST_A_USB3OTG1>; -- snps,dis_enblslpm_quirk; -- snps,dis-u2-freeclk-exists-quirk; -- snps,dis-del-phy-power-chg-quirk; -- snps,dis-tx-ipgap-linecheck-quirk; -- status = "disabled"; -- }; -- -- pcie30_phy_grf: syscon@fd5b8000 { -- compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; -- reg = <0x0 0xfd5b8000 0x0 0x10000>; -- }; -- -- pipe_phy1_grf: syscon@fd5c0000 { -- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; -- reg = <0x0 0xfd5c0000 0x0 0x100>; -- }; -- -- usbdpphy1_grf: syscon@fd5cc000 { -- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; -- reg = <0x0 0xfd5cc000 0x0 0x4000>; -- }; -- -- usb2phy1_grf: syscon@fd5d4000 { -- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; -- reg = <0x0 0xfd5d4000 0x0 0x4000>; -- #address-cells = <1>; -- #size-cells = <1>; -- -- u2phy1: usb2phy@4000 { -- compatible = "rockchip,rk3588-usb2phy"; -- reg = <0x4000 0x10>; -- #clock-cells = <0>; -- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; -- clock-names = "phyclk"; -- clock-output-names = "usb480m_phy1"; -- interrupts = ; -- resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; -- reset-names = "phy", "apb"; -- status = "disabled"; -- -- u2phy1_otg: otg-port { -- #phy-cells = <0>; -- status = "disabled"; -- }; -- }; -- }; -- -- i2s8_8ch: i2s@fddc8000 { -- compatible = "rockchip,rk3588-i2s-tdm"; -- reg = <0x0 0xfddc8000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; -- clock-names = "mclk_tx", "mclk_rx", "hclk"; -- assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; -- assigned-clock-parents = <&cru PLL_AUPLL>; -- dmas = <&dmac2 22>; -- dma-names = "tx"; -- power-domains = <&power RK3588_PD_VO0>; -- resets = <&cru SRST_M_I2S8_8CH_TX>; -- reset-names = "tx-m"; -- #sound-dai-cells = <0>; -- status = "disabled"; -- }; -- -- i2s6_8ch: i2s@fddf4000 { -- compatible = "rockchip,rk3588-i2s-tdm"; -- reg = <0x0 0xfddf4000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; -- clock-names = "mclk_tx", "mclk_rx", "hclk"; -- assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; -- assigned-clock-parents = <&cru PLL_AUPLL>; -- dmas = <&dmac2 4>; -- dma-names = "tx"; -- power-domains = <&power RK3588_PD_VO1>; -- resets = <&cru SRST_M_I2S6_8CH_TX>; -- reset-names = "tx-m"; -- #sound-dai-cells = <0>; -- status = "disabled"; -- }; -- -- i2s7_8ch: i2s@fddf8000 { -- compatible = "rockchip,rk3588-i2s-tdm"; -- reg = <0x0 0xfddf8000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; -- clock-names = "mclk_tx", "mclk_rx", "hclk"; -- assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; -- assigned-clock-parents = <&cru PLL_AUPLL>; -- dmas = <&dmac2 21>; -- dma-names = "rx"; -- power-domains = <&power RK3588_PD_VO1>; -- resets = <&cru SRST_M_I2S7_8CH_RX>; -- reset-names = "rx-m"; -- #sound-dai-cells = <0>; -- status = "disabled"; -- }; -- -- i2s10_8ch: i2s@fde00000 { -- compatible = "rockchip,rk3588-i2s-tdm"; -- reg = <0x0 0xfde00000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; -- clock-names = "mclk_tx", "mclk_rx", "hclk"; -- assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; -- assigned-clock-parents = <&cru PLL_AUPLL>; -- dmas = <&dmac2 24>; -- dma-names = "rx"; -- power-domains = <&power RK3588_PD_VO1>; -- resets = <&cru SRST_M_I2S10_8CH_RX>; -- reset-names = "rx-m"; -- #sound-dai-cells = <0>; -- status = "disabled"; -- }; -- -- pcie3x4: pcie@fe150000 { -- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -- #address-cells = <3>; -- #size-cells = <2>; -- bus-range = <0x00 0x0f>; -- clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, -- <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, -- <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; -- clock-names = "aclk_mst", "aclk_slv", -- "aclk_dbi", "pclk", -- "aux", "pipe"; -- device_type = "pci"; -- interrupts = , -- , -- , -- , -- ; -- interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, -- <0 0 0 2 &pcie3x4_intc 1>, -- <0 0 0 3 &pcie3x4_intc 2>, -- <0 0 0 4 &pcie3x4_intc 3>; -- linux,pci-domain = <0>; -- max-link-speed = <3>; -- msi-map = <0x0000 &its1 0x0000 0x1000>; -- num-lanes = <4>; -- phys = <&pcie30phy>; -- phy-names = "pcie-phy"; -- power-domains = <&power RK3588_PD_PCIE>; -- ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, -- <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, -- <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; -- reg = <0xa 0x40000000 0x0 0x00400000>, -- <0x0 0xfe150000 0x0 0x00010000>, -- <0x0 0xf0000000 0x0 0x00100000>; -- reg-names = "dbi", "apb", "config"; -- resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; -- reset-names = "pwr", "pipe"; -- status = "disabled"; -- -- pcie3x4_intc: legacy-interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- interrupt-parent = <&gic>; -- interrupts = ; -- }; -- }; -- -- pcie3x2: pcie@fe160000 { -- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -- #address-cells = <3>; -- #size-cells = <2>; -- bus-range = <0x10 0x1f>; -- clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, -- <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, -- <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; -- clock-names = "aclk_mst", "aclk_slv", -- "aclk_dbi", "pclk", -- "aux", "pipe"; -- device_type = "pci"; -- interrupts = , -- , -- , -- , -- ; -- interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, -- <0 0 0 2 &pcie3x2_intc 1>, -- <0 0 0 3 &pcie3x2_intc 2>, -- <0 0 0 4 &pcie3x2_intc 3>; -- linux,pci-domain = <1>; -- max-link-speed = <3>; -- msi-map = <0x1000 &its1 0x1000 0x1000>; -- num-lanes = <2>; -- phys = <&pcie30phy>; -- phy-names = "pcie-phy"; -- power-domains = <&power RK3588_PD_PCIE>; -- ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, -- <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, -- <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; -- reg = <0xa 0x40400000 0x0 0x00400000>, -- <0x0 0xfe160000 0x0 0x00010000>, -- <0x0 0xf1000000 0x0 0x00100000>; -- reg-names = "dbi", "apb", "config"; -- resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; -- reset-names = "pwr", "pipe"; -- status = "disabled"; -- -- pcie3x2_intc: legacy-interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- interrupt-parent = <&gic>; -- interrupts = ; -- }; -- }; -- -- pcie2x1l0: pcie@fe170000 { -- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -- bus-range = <0x20 0x2f>; -- clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, -- <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, -- <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; -- clock-names = "aclk_mst", "aclk_slv", -- "aclk_dbi", "pclk", -- "aux", "pipe"; -- device_type = "pci"; -- interrupts = , -- , -- , -- , -- ; -- interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, -- <0 0 0 2 &pcie2x1l0_intc 1>, -- <0 0 0 3 &pcie2x1l0_intc 2>, -- <0 0 0 4 &pcie2x1l0_intc 3>; -- linux,pci-domain = <2>; -- max-link-speed = <2>; -- msi-map = <0x2000 &its0 0x2000 0x1000>; -- num-lanes = <1>; -- phys = <&combphy1_ps PHY_TYPE_PCIE>; -- phy-names = "pcie-phy"; -- power-domains = <&power RK3588_PD_PCIE>; -- ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, -- <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, -- <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; -- reg = <0xa 0x40800000 0x0 0x00400000>, -- <0x0 0xfe170000 0x0 0x00010000>, -- <0x0 0xf2000000 0x0 0x00100000>; -- reg-names = "dbi", "apb", "config"; -- resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; -- reset-names = "pwr", "pipe"; -- #address-cells = <3>; -- #size-cells = <2>; -- status = "disabled"; -- -- pcie2x1l0_intc: legacy-interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- interrupt-parent = <&gic>; -- interrupts = ; -- }; -- }; -- -- gmac0: ethernet@fe1b0000 { -- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; -- reg = <0x0 0xfe1b0000 0x0 0x10000>; -- interrupts = , -- ; -- interrupt-names = "macirq", "eth_wake_irq"; -- clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, -- <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, -- <&cru CLK_GMAC0_PTP_REF>; -- clock-names = "stmmaceth", "clk_mac_ref", -- "pclk_mac", "aclk_mac", -- "ptp_ref"; -- power-domains = <&power RK3588_PD_GMAC>; -- resets = <&cru SRST_A_GMAC0>; -- reset-names = "stmmaceth"; -- rockchip,grf = <&sys_grf>; -- rockchip,php-grf = <&php_grf>; -- snps,axi-config = <&gmac0_stmmac_axi_setup>; -- snps,mixed-burst; -- snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; -- snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; -- snps,tso; -- status = "disabled"; -- -- mdio0: mdio { -- compatible = "snps,dwmac-mdio"; -- #address-cells = <0x1>; -- #size-cells = <0x0>; -- }; -- -- gmac0_stmmac_axi_setup: stmmac-axi-config { -- snps,blen = <0 0 0 0 16 8 4>; -- snps,wr_osr_lmt = <4>; -- snps,rd_osr_lmt = <8>; -- }; -- -- gmac0_mtl_rx_setup: rx-queues-config { -- snps,rx-queues-to-use = <2>; -- queue0 {}; -- queue1 {}; -- }; -- -- gmac0_mtl_tx_setup: tx-queues-config { -- snps,tx-queues-to-use = <2>; -- queue0 {}; -- queue1 {}; -- }; -- }; -- -- sata1: sata@fe220000 { -- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; -- reg = <0 0xfe220000 0 0x1000>; -- interrupts = ; -- clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, -- <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, -- <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; -- clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; -- ports-implemented = <0x1>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- -- sata-port@0 { -- reg = <0>; -- hba-port-cap = ; -- phys = <&combphy1_ps PHY_TYPE_SATA>; -- phy-names = "sata-phy"; -- snps,rx-ts-max = <32>; -- snps,tx-ts-max = <32>; -- }; -- }; -- -- usbdp_phy1: phy@fed90000 { -- compatible = "rockchip,rk3588-usbdp-phy"; -- reg = <0x0 0xfed90000 0x0 0x10000>; -- #phy-cells = <1>; -- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, -- <&cru CLK_USBDP_PHY1_IMMORTAL>, -- <&cru PCLK_USBDPPHY1>, -- <&u2phy1>; -- clock-names = "refclk", "immortal", "pclk", "utmi"; -- resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, -- <&cru SRST_USBDP_COMBO_PHY1_CMN>, -- <&cru SRST_USBDP_COMBO_PHY1_LANE>, -- <&cru SRST_USBDP_COMBO_PHY1_PCS>, -- <&cru SRST_P_USBDPPHY1>; -- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; -- rockchip,u2phy-grf = <&usb2phy1_grf>; -- rockchip,usb-grf = <&usb_grf>; -- rockchip,usbdpphy-grf = <&usbdpphy1_grf>; -- rockchip,vo-grf = <&vo0_grf>; -- status = "disabled"; -- }; -- -- combphy1_ps: phy@fee10000 { -- compatible = "rockchip,rk3588-naneng-combphy"; -- reg = <0x0 0xfee10000 0x0 0x100>; -- clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, -- <&cru PCLK_PHP_ROOT>; -- clock-names = "ref", "apb", "pipe"; -- assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; -- assigned-clock-rates = <100000000>; -- #phy-cells = <1>; -- resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; -- reset-names = "phy", "apb"; -- rockchip,pipe-grf = <&php_grf>; -- rockchip,pipe-phy-grf = <&pipe_phy1_grf>; -- status = "disabled"; -- }; -- -- pcie30phy: phy@fee80000 { -- compatible = "rockchip,rk3588-pcie3-phy"; -- reg = <0x0 0xfee80000 0x0 0x20000>; -- #phy-cells = <0>; -- clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; -- clock-names = "pclk"; -- resets = <&cru SRST_PCIE30_PHY>; -- reset-names = "phy"; -- rockchip,pipe-grf = <&php_grf>; -- rockchip,phy-grf = <&pcie30_phy_grf>; -- status = "disabled"; -- }; --}; -+#include "rk3588-extra.dtsi" ---- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi -@@ -4,4 +4,4 @@ - * - */ - --#include "rk3588.dtsi" -+#include "rk3588-extra.dtsi" ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1,2670 +1,7 @@ - // SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /* -- * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd. -+ * - */ - --#include --#include --#include --#include --#include --#include --#include -- --/ { -- compatible = "rockchip,rk3588"; -- -- interrupt-parent = <&gic>; -- #address-cells = <2>; -- #size-cells = <2>; -- -- aliases { -- gpio0 = &gpio0; -- gpio1 = &gpio1; -- gpio2 = &gpio2; -- gpio3 = &gpio3; -- gpio4 = &gpio4; -- i2c0 = &i2c0; -- i2c1 = &i2c1; -- i2c2 = &i2c2; -- i2c3 = &i2c3; -- i2c4 = &i2c4; -- i2c5 = &i2c5; -- i2c6 = &i2c6; -- i2c7 = &i2c7; -- i2c8 = &i2c8; -- serial0 = &uart0; -- serial1 = &uart1; -- serial2 = &uart2; -- serial3 = &uart3; -- serial4 = &uart4; -- serial5 = &uart5; -- serial6 = &uart6; -- serial7 = &uart7; -- serial8 = &uart8; -- serial9 = &uart9; -- spi0 = &spi0; -- spi1 = &spi1; -- spi2 = &spi2; -- spi3 = &spi3; -- spi4 = &spi4; -- }; -- -- cpus { -- #address-cells = <1>; -- #size-cells = <0>; -- -- cpu-map { -- cluster0 { -- core0 { -- cpu = <&cpu_l0>; -- }; -- core1 { -- cpu = <&cpu_l1>; -- }; -- core2 { -- cpu = <&cpu_l2>; -- }; -- core3 { -- cpu = <&cpu_l3>; -- }; -- }; -- cluster1 { -- core0 { -- cpu = <&cpu_b0>; -- }; -- core1 { -- cpu = <&cpu_b1>; -- }; -- }; -- cluster2 { -- core0 { -- cpu = <&cpu_b2>; -- }; -- core1 { -- cpu = <&cpu_b3>; -- }; -- }; -- }; -- -- cpu_l0: cpu@0 { -- device_type = "cpu"; -- compatible = "arm,cortex-a55"; -- reg = <0x0>; -- enable-method = "psci"; -- capacity-dmips-mhz = <530>; -- clocks = <&scmi_clk SCMI_CLK_CPUL>; -- assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; -- assigned-clock-rates = <816000000>; -- cpu-idle-states = <&CPU_SLEEP>; -- i-cache-size = <32768>; -- i-cache-line-size = <64>; -- i-cache-sets = <128>; -- d-cache-size = <32768>; -- d-cache-line-size = <64>; -- d-cache-sets = <128>; -- next-level-cache = <&l2_cache_l0>; -- dynamic-power-coefficient = <228>; -- #cooling-cells = <2>; -- }; -- -- cpu_l1: cpu@100 { -- device_type = "cpu"; -- compatible = "arm,cortex-a55"; -- reg = <0x100>; -- enable-method = "psci"; -- capacity-dmips-mhz = <530>; -- clocks = <&scmi_clk SCMI_CLK_CPUL>; -- cpu-idle-states = <&CPU_SLEEP>; -- i-cache-size = <32768>; -- i-cache-line-size = <64>; -- i-cache-sets = <128>; -- d-cache-size = <32768>; -- d-cache-line-size = <64>; -- d-cache-sets = <128>; -- next-level-cache = <&l2_cache_l1>; -- dynamic-power-coefficient = <228>; -- #cooling-cells = <2>; -- }; -- -- cpu_l2: cpu@200 { -- device_type = "cpu"; -- compatible = "arm,cortex-a55"; -- reg = <0x200>; -- enable-method = "psci"; -- capacity-dmips-mhz = <530>; -- clocks = <&scmi_clk SCMI_CLK_CPUL>; -- cpu-idle-states = <&CPU_SLEEP>; -- i-cache-size = <32768>; -- i-cache-line-size = <64>; -- i-cache-sets = <128>; -- d-cache-size = <32768>; -- d-cache-line-size = <64>; -- d-cache-sets = <128>; -- next-level-cache = <&l2_cache_l2>; -- dynamic-power-coefficient = <228>; -- #cooling-cells = <2>; -- }; -- -- cpu_l3: cpu@300 { -- device_type = "cpu"; -- compatible = "arm,cortex-a55"; -- reg = <0x300>; -- enable-method = "psci"; -- capacity-dmips-mhz = <530>; -- clocks = <&scmi_clk SCMI_CLK_CPUL>; -- cpu-idle-states = <&CPU_SLEEP>; -- i-cache-size = <32768>; -- i-cache-line-size = <64>; -- i-cache-sets = <128>; -- d-cache-size = <32768>; -- d-cache-line-size = <64>; -- d-cache-sets = <128>; -- next-level-cache = <&l2_cache_l3>; -- dynamic-power-coefficient = <228>; -- #cooling-cells = <2>; -- }; -- -- cpu_b0: cpu@400 { -- device_type = "cpu"; -- compatible = "arm,cortex-a76"; -- reg = <0x400>; -- enable-method = "psci"; -- capacity-dmips-mhz = <1024>; -- clocks = <&scmi_clk SCMI_CLK_CPUB01>; -- assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; -- assigned-clock-rates = <816000000>; -- cpu-idle-states = <&CPU_SLEEP>; -- i-cache-size = <65536>; -- i-cache-line-size = <64>; -- i-cache-sets = <256>; -- d-cache-size = <65536>; -- d-cache-line-size = <64>; -- d-cache-sets = <256>; -- next-level-cache = <&l2_cache_b0>; -- dynamic-power-coefficient = <416>; -- #cooling-cells = <2>; -- }; -- -- cpu_b1: cpu@500 { -- device_type = "cpu"; -- compatible = "arm,cortex-a76"; -- reg = <0x500>; -- enable-method = "psci"; -- capacity-dmips-mhz = <1024>; -- clocks = <&scmi_clk SCMI_CLK_CPUB01>; -- cpu-idle-states = <&CPU_SLEEP>; -- i-cache-size = <65536>; -- i-cache-line-size = <64>; -- i-cache-sets = <256>; -- d-cache-size = <65536>; -- d-cache-line-size = <64>; -- d-cache-sets = <256>; -- next-level-cache = <&l2_cache_b1>; -- dynamic-power-coefficient = <416>; -- #cooling-cells = <2>; -- }; -- -- cpu_b2: cpu@600 { -- device_type = "cpu"; -- compatible = "arm,cortex-a76"; -- reg = <0x600>; -- enable-method = "psci"; -- capacity-dmips-mhz = <1024>; -- clocks = <&scmi_clk SCMI_CLK_CPUB23>; -- assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; -- assigned-clock-rates = <816000000>; -- cpu-idle-states = <&CPU_SLEEP>; -- i-cache-size = <65536>; -- i-cache-line-size = <64>; -- i-cache-sets = <256>; -- d-cache-size = <65536>; -- d-cache-line-size = <64>; -- d-cache-sets = <256>; -- next-level-cache = <&l2_cache_b2>; -- dynamic-power-coefficient = <416>; -- #cooling-cells = <2>; -- }; -- -- cpu_b3: cpu@700 { -- device_type = "cpu"; -- compatible = "arm,cortex-a76"; -- reg = <0x700>; -- enable-method = "psci"; -- capacity-dmips-mhz = <1024>; -- clocks = <&scmi_clk SCMI_CLK_CPUB23>; -- cpu-idle-states = <&CPU_SLEEP>; -- i-cache-size = <65536>; -- i-cache-line-size = <64>; -- i-cache-sets = <256>; -- d-cache-size = <65536>; -- d-cache-line-size = <64>; -- d-cache-sets = <256>; -- next-level-cache = <&l2_cache_b3>; -- dynamic-power-coefficient = <416>; -- #cooling-cells = <2>; -- }; -- -- idle-states { -- entry-method = "psci"; -- CPU_SLEEP: cpu-sleep { -- compatible = "arm,idle-state"; -- local-timer-stop; -- arm,psci-suspend-param = <0x0010000>; -- entry-latency-us = <100>; -- exit-latency-us = <120>; -- min-residency-us = <1000>; -- }; -- }; -- -- l2_cache_l0: l2-cache-l0 { -- compatible = "cache"; -- cache-size = <131072>; -- cache-line-size = <64>; -- cache-sets = <512>; -- cache-level = <2>; -- cache-unified; -- next-level-cache = <&l3_cache>; -- }; -- -- l2_cache_l1: l2-cache-l1 { -- compatible = "cache"; -- cache-size = <131072>; -- cache-line-size = <64>; -- cache-sets = <512>; -- cache-level = <2>; -- cache-unified; -- next-level-cache = <&l3_cache>; -- }; -- -- l2_cache_l2: l2-cache-l2 { -- compatible = "cache"; -- cache-size = <131072>; -- cache-line-size = <64>; -- cache-sets = <512>; -- cache-level = <2>; -- cache-unified; -- next-level-cache = <&l3_cache>; -- }; -- -- l2_cache_l3: l2-cache-l3 { -- compatible = "cache"; -- cache-size = <131072>; -- cache-line-size = <64>; -- cache-sets = <512>; -- cache-level = <2>; -- cache-unified; -- next-level-cache = <&l3_cache>; -- }; -- -- l2_cache_b0: l2-cache-b0 { -- compatible = "cache"; -- cache-size = <524288>; -- cache-line-size = <64>; -- cache-sets = <1024>; -- cache-level = <2>; -- cache-unified; -- next-level-cache = <&l3_cache>; -- }; -- -- l2_cache_b1: l2-cache-b1 { -- compatible = "cache"; -- cache-size = <524288>; -- cache-line-size = <64>; -- cache-sets = <1024>; -- cache-level = <2>; -- cache-unified; -- next-level-cache = <&l3_cache>; -- }; -- -- l2_cache_b2: l2-cache-b2 { -- compatible = "cache"; -- cache-size = <524288>; -- cache-line-size = <64>; -- cache-sets = <1024>; -- cache-level = <2>; -- cache-unified; -- next-level-cache = <&l3_cache>; -- }; -- -- l2_cache_b3: l2-cache-b3 { -- compatible = "cache"; -- cache-size = <524288>; -- cache-line-size = <64>; -- cache-sets = <1024>; -- cache-level = <2>; -- cache-unified; -- next-level-cache = <&l3_cache>; -- }; -- -- l3_cache: l3-cache { -- compatible = "cache"; -- cache-size = <3145728>; -- cache-line-size = <64>; -- cache-sets = <4096>; -- cache-level = <3>; -- cache-unified; -- }; -- }; -- -- display_subsystem: display-subsystem { -- compatible = "rockchip,display-subsystem"; -- ports = <&vop_out>; -- }; -- -- firmware { -- optee: optee { -- compatible = "linaro,optee-tz"; -- method = "smc"; -- }; -- -- scmi: scmi { -- compatible = "arm,scmi-smc"; -- arm,smc-id = <0x82000010>; -- shmem = <&scmi_shmem>; -- #address-cells = <1>; -- #size-cells = <0>; -- -- scmi_clk: protocol@14 { -- reg = <0x14>; -- #clock-cells = <1>; -- }; -- -- scmi_reset: protocol@16 { -- reg = <0x16>; -- #reset-cells = <1>; -- }; -- }; -- }; -- -- pmu-a55 { -- compatible = "arm,cortex-a55-pmu"; -- interrupts = ; -- }; -- -- pmu-a76 { -- compatible = "arm,cortex-a76-pmu"; -- interrupts = ; -- }; -- -- psci { -- compatible = "arm,psci-1.0"; -- method = "smc"; -- }; -- -- spll: clock-0 { -- compatible = "fixed-clock"; -- clock-frequency = <702000000>; -- clock-output-names = "spll"; -- #clock-cells = <0>; -- }; -- -- timer { -- compatible = "arm,armv8-timer"; -- interrupts = , -- , -- , -- , -- ; -- interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; -- }; -- -- xin24m: clock-1 { -- compatible = "fixed-clock"; -- clock-frequency = <24000000>; -- clock-output-names = "xin24m"; -- #clock-cells = <0>; -- }; -- -- xin32k: clock-2 { -- compatible = "fixed-clock"; -- clock-frequency = <32768>; -- clock-output-names = "xin32k"; -- #clock-cells = <0>; -- }; -- -- pmu_sram: sram@10f000 { -- compatible = "mmio-sram"; -- reg = <0x0 0x0010f000 0x0 0x100>; -- ranges = <0 0x0 0x0010f000 0x100>; -- #address-cells = <1>; -- #size-cells = <1>; -- -- scmi_shmem: sram@0 { -- compatible = "arm,scmi-shmem"; -- reg = <0x0 0x100>; -- }; -- }; -- -- gpu: gpu@fb000000 { -- compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; -- reg = <0x0 0xfb000000 0x0 0x200000>; -- #cooling-cells = <2>; -- assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; -- assigned-clock-rates = <200000000>; -- clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, -- <&cru CLK_GPU_STACKS>; -- clock-names = "core", "coregroup", "stacks"; -- dynamic-power-coefficient = <2982>; -- interrupts = , -- , -- ; -- interrupt-names = "job", "mmu", "gpu"; -- operating-points-v2 = <&gpu_opp_table>; -- power-domains = <&power RK3588_PD_GPU>; -- status = "disabled"; -- -- gpu_opp_table: opp-table { -- compatible = "operating-points-v2"; -- -- opp-300000000 { -- opp-hz = /bits/ 64 <300000000>; -- opp-microvolt = <675000 675000 850000>; -- }; -- opp-400000000 { -- opp-hz = /bits/ 64 <400000000>; -- opp-microvolt = <675000 675000 850000>; -- }; -- opp-500000000 { -- opp-hz = /bits/ 64 <500000000>; -- opp-microvolt = <675000 675000 850000>; -- }; -- opp-600000000 { -- opp-hz = /bits/ 64 <600000000>; -- opp-microvolt = <675000 675000 850000>; -- }; -- opp-700000000 { -- opp-hz = /bits/ 64 <700000000>; -- opp-microvolt = <700000 700000 850000>; -- }; -- opp-800000000 { -- opp-hz = /bits/ 64 <800000000>; -- opp-microvolt = <750000 750000 850000>; -- }; -- opp-900000000 { -- opp-hz = /bits/ 64 <900000000>; -- opp-microvolt = <800000 800000 850000>; -- }; -- opp-1000000000 { -- opp-hz = /bits/ 64 <1000000000>; -- opp-microvolt = <850000 850000 850000>; -- }; -- }; -- }; -- -- usb_host0_xhci: usb@fc000000 { -- compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; -- reg = <0x0 0xfc000000 0x0 0x400000>; -- interrupts = ; -- clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, -- <&cru ACLK_USB3OTG0>; -- clock-names = "ref_clk", "suspend_clk", "bus_clk"; -- dr_mode = "otg"; -- phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; -- phy-names = "usb2-phy", "usb3-phy"; -- phy_type = "utmi_wide"; -- power-domains = <&power RK3588_PD_USB>; -- resets = <&cru SRST_A_USB3OTG0>; -- snps,dis_enblslpm_quirk; -- snps,dis-u1-entry-quirk; -- snps,dis-u2-entry-quirk; -- snps,dis-u2-freeclk-exists-quirk; -- snps,dis-del-phy-power-chg-quirk; -- snps,dis-tx-ipgap-linecheck-quirk; -- status = "disabled"; -- }; -- -- usb_host0_ehci: usb@fc800000 { -- compatible = "rockchip,rk3588-ehci", "generic-ehci"; -- reg = <0x0 0xfc800000 0x0 0x40000>; -- interrupts = ; -- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; -- phys = <&u2phy2_host>; -- phy-names = "usb"; -- power-domains = <&power RK3588_PD_USB>; -- status = "disabled"; -- }; -- -- usb_host0_ohci: usb@fc840000 { -- compatible = "rockchip,rk3588-ohci", "generic-ohci"; -- reg = <0x0 0xfc840000 0x0 0x40000>; -- interrupts = ; -- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; -- phys = <&u2phy2_host>; -- phy-names = "usb"; -- power-domains = <&power RK3588_PD_USB>; -- status = "disabled"; -- }; -- -- usb_host1_ehci: usb@fc880000 { -- compatible = "rockchip,rk3588-ehci", "generic-ehci"; -- reg = <0x0 0xfc880000 0x0 0x40000>; -- interrupts = ; -- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; -- phys = <&u2phy3_host>; -- phy-names = "usb"; -- power-domains = <&power RK3588_PD_USB>; -- status = "disabled"; -- }; -- -- usb_host1_ohci: usb@fc8c0000 { -- compatible = "rockchip,rk3588-ohci", "generic-ohci"; -- reg = <0x0 0xfc8c0000 0x0 0x40000>; -- interrupts = ; -- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; -- phys = <&u2phy3_host>; -- phy-names = "usb"; -- power-domains = <&power RK3588_PD_USB>; -- status = "disabled"; -- }; -- -- usb_host2_xhci: usb@fcd00000 { -- compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; -- reg = <0x0 0xfcd00000 0x0 0x400000>; -- interrupts = ; -- clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, -- <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, -- <&cru CLK_PIPEPHY2_PIPE_U3_G>; -- clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; -- dr_mode = "host"; -- phys = <&combphy2_psu PHY_TYPE_USB3>; -- phy-names = "usb3-phy"; -- phy_type = "utmi_wide"; -- resets = <&cru SRST_A_USB3OTG2>; -- snps,dis_enblslpm_quirk; -- snps,dis-u2-freeclk-exists-quirk; -- snps,dis-del-phy-power-chg-quirk; -- snps,dis-tx-ipgap-linecheck-quirk; -- snps,dis_rxdet_inp3_quirk; -- status = "disabled"; -- }; -- -- mmu600_pcie: iommu@fc900000 { -- compatible = "arm,smmu-v3"; -- reg = <0x0 0xfc900000 0x0 0x200000>; -- interrupts = , -- , -- , -- ; -- interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; -- #iommu-cells = <1>; -- status = "disabled"; -- }; -- -- mmu600_php: iommu@fcb00000 { -- compatible = "arm,smmu-v3"; -- reg = <0x0 0xfcb00000 0x0 0x200000>; -- interrupts = , -- , -- , -- ; -- interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; -- #iommu-cells = <1>; -- status = "disabled"; -- }; -- -- pmu1grf: syscon@fd58a000 { -- compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; -- reg = <0x0 0xfd58a000 0x0 0x10000>; -- }; -- -- sys_grf: syscon@fd58c000 { -- compatible = "rockchip,rk3588-sys-grf", "syscon"; -- reg = <0x0 0xfd58c000 0x0 0x1000>; -- }; -- -- vop_grf: syscon@fd5a4000 { -- compatible = "rockchip,rk3588-vop-grf", "syscon"; -- reg = <0x0 0xfd5a4000 0x0 0x2000>; -- }; -- -- vo0_grf: syscon@fd5a6000 { -- compatible = "rockchip,rk3588-vo-grf", "syscon"; -- reg = <0x0 0xfd5a6000 0x0 0x2000>; -- clocks = <&cru PCLK_VO0GRF>; -- }; -- -- vo1_grf: syscon@fd5a8000 { -- compatible = "rockchip,rk3588-vo-grf", "syscon"; -- reg = <0x0 0xfd5a8000 0x0 0x100>; -- clocks = <&cru PCLK_VO1GRF>; -- }; -- -- usb_grf: syscon@fd5ac000 { -- compatible = "rockchip,rk3588-usb-grf", "syscon"; -- reg = <0x0 0xfd5ac000 0x0 0x4000>; -- }; -- -- php_grf: syscon@fd5b0000 { -- compatible = "rockchip,rk3588-php-grf", "syscon"; -- reg = <0x0 0xfd5b0000 0x0 0x1000>; -- }; -- -- pipe_phy0_grf: syscon@fd5bc000 { -- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; -- reg = <0x0 0xfd5bc000 0x0 0x100>; -- }; -- -- pipe_phy2_grf: syscon@fd5c4000 { -- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; -- reg = <0x0 0xfd5c4000 0x0 0x100>; -- }; -- -- usbdpphy0_grf: syscon@fd5c8000 { -- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; -- reg = <0x0 0xfd5c8000 0x0 0x4000>; -- }; -- -- usb2phy0_grf: syscon@fd5d0000 { -- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; -- reg = <0x0 0xfd5d0000 0x0 0x4000>; -- #address-cells = <1>; -- #size-cells = <1>; -- -- u2phy0: usb2phy@0 { -- compatible = "rockchip,rk3588-usb2phy"; -- reg = <0x0 0x10>; -- #clock-cells = <0>; -- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; -- clock-names = "phyclk"; -- clock-output-names = "usb480m_phy0"; -- interrupts = ; -- resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; -- reset-names = "phy", "apb"; -- status = "disabled"; -- -- u2phy0_otg: otg-port { -- #phy-cells = <0>; -- status = "disabled"; -- }; -- }; -- }; -- -- usb2phy2_grf: syscon@fd5d8000 { -- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; -- reg = <0x0 0xfd5d8000 0x0 0x4000>; -- #address-cells = <1>; -- #size-cells = <1>; -- -- u2phy2: usb2phy@8000 { -- compatible = "rockchip,rk3588-usb2phy"; -- reg = <0x8000 0x10>; -- #clock-cells = <0>; -- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; -- clock-names = "phyclk"; -- clock-output-names = "usb480m_phy2"; -- interrupts = ; -- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; -- reset-names = "phy", "apb"; -- status = "disabled"; -- -- u2phy2_host: host-port { -- #phy-cells = <0>; -- status = "disabled"; -- }; -- }; -- }; -- -- usb2phy3_grf: syscon@fd5dc000 { -- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; -- reg = <0x0 0xfd5dc000 0x0 0x4000>; -- #address-cells = <1>; -- #size-cells = <1>; -- -- u2phy3: usb2phy@c000 { -- compatible = "rockchip,rk3588-usb2phy"; -- reg = <0xc000 0x10>; -- #clock-cells = <0>; -- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; -- clock-names = "phyclk"; -- clock-output-names = "usb480m_phy3"; -- interrupts = ; -- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; -- reset-names = "phy", "apb"; -- status = "disabled"; -- -- u2phy3_host: host-port { -- #phy-cells = <0>; -- status = "disabled"; -- }; -- }; -- }; -- -- hdptxphy0_grf: syscon@fd5e0000 { -- compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; -- reg = <0x0 0xfd5e0000 0x0 0x100>; -- }; -- -- ioc: syscon@fd5f0000 { -- compatible = "rockchip,rk3588-ioc", "syscon"; -- reg = <0x0 0xfd5f0000 0x0 0x10000>; -- }; -- -- system_sram1: sram@fd600000 { -- compatible = "mmio-sram"; -- reg = <0x0 0xfd600000 0x0 0x100000>; -- ranges = <0x0 0x0 0xfd600000 0x100000>; -- #address-cells = <1>; -- #size-cells = <1>; -- }; -- -- cru: clock-controller@fd7c0000 { -- compatible = "rockchip,rk3588-cru"; -- reg = <0x0 0xfd7c0000 0x0 0x5c000>; -- assigned-clocks = -- <&cru PLL_PPLL>, <&cru PLL_AUPLL>, -- <&cru PLL_NPLL>, <&cru PLL_GPLL>, -- <&cru ACLK_CENTER_ROOT>, -- <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, -- <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, -- <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, -- <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, -- <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, -- <&cru CLK_GPU>; -- assigned-clock-rates = -- <1100000000>, <786432000>, -- <850000000>, <1188000000>, -- <702000000>, -- <400000000>, <500000000>, -- <800000000>, <100000000>, -- <400000000>, <100000000>, -- <200000000>, <500000000>, -- <375000000>, <150000000>, -- <200000000>; -- rockchip,grf = <&php_grf>; -- #clock-cells = <1>; -- #reset-cells = <1>; -- }; -- -- i2c0: i2c@fd880000 { -- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfd880000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; -- clock-names = "i2c", "pclk"; -- pinctrl-0 = <&i2c0m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- uart0: serial@fd890000 { -- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfd890000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 6>, <&dmac0 7>; -- dma-names = "tx", "rx"; -- pinctrl-0 = <&uart0m1_xfer>; -- pinctrl-names = "default"; -- reg-shift = <2>; -- reg-io-width = <4>; -- status = "disabled"; -- }; -- -- pwm0: pwm@fd8b0000 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfd8b0000 0x0 0x10>; -- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm0m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm1: pwm@fd8b0010 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfd8b0010 0x0 0x10>; -- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm1m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm2: pwm@fd8b0020 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfd8b0020 0x0 0x10>; -- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm2m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm3: pwm@fd8b0030 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfd8b0030 0x0 0x10>; -- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm3m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pmu: power-management@fd8d8000 { -- compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; -- reg = <0x0 0xfd8d8000 0x0 0x400>; -- -- power: power-controller { -- compatible = "rockchip,rk3588-power-controller"; -- #address-cells = <1>; -- #power-domain-cells = <1>; -- #size-cells = <0>; -- status = "okay"; -- -- /* These power domains are grouped by VD_NPU */ -- power-domain@RK3588_PD_NPU { -- reg = ; -- #power-domain-cells = <0>; -- #address-cells = <1>; -- #size-cells = <0>; -- -- power-domain@RK3588_PD_NPUTOP { -- reg = ; -- clocks = <&cru HCLK_NPU_ROOT>, -- <&cru PCLK_NPU_ROOT>, -- <&cru CLK_NPU_DSU0>, -- <&cru HCLK_NPU_CM0_ROOT>; -- pm_qos = <&qos_npu0_mwr>, -- <&qos_npu0_mro>, -- <&qos_mcu_npu>; -- #power-domain-cells = <0>; -- #address-cells = <1>; -- #size-cells = <0>; -- -- power-domain@RK3588_PD_NPU1 { -- reg = ; -- clocks = <&cru HCLK_NPU_ROOT>, -- <&cru PCLK_NPU_ROOT>, -- <&cru CLK_NPU_DSU0>; -- pm_qos = <&qos_npu1>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_NPU2 { -- reg = ; -- clocks = <&cru HCLK_NPU_ROOT>, -- <&cru PCLK_NPU_ROOT>, -- <&cru CLK_NPU_DSU0>; -- pm_qos = <&qos_npu2>; -- #power-domain-cells = <0>; -- }; -- }; -- }; -- /* These power domains are grouped by VD_GPU */ -- power-domain@RK3588_PD_GPU { -- reg = ; -- clocks = <&cru CLK_GPU>, -- <&cru CLK_GPU_COREGROUP>, -- <&cru CLK_GPU_STACKS>; -- pm_qos = <&qos_gpu_m0>, -- <&qos_gpu_m1>, -- <&qos_gpu_m2>, -- <&qos_gpu_m3>; -- #power-domain-cells = <0>; -- }; -- /* These power domains are grouped by VD_VCODEC */ -- power-domain@RK3588_PD_VCODEC { -- reg = ; -- #address-cells = <1>; -- #size-cells = <0>; -- #power-domain-cells = <0>; -- -- power-domain@RK3588_PD_RKVDEC0 { -- reg = ; -- clocks = <&cru HCLK_RKVDEC0>, -- <&cru HCLK_VDPU_ROOT>, -- <&cru ACLK_VDPU_ROOT>, -- <&cru ACLK_RKVDEC0>, -- <&cru ACLK_RKVDEC_CCU>; -- pm_qos = <&qos_rkvdec0>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_RKVDEC1 { -- reg = ; -- clocks = <&cru HCLK_RKVDEC1>, -- <&cru HCLK_VDPU_ROOT>, -- <&cru ACLK_VDPU_ROOT>, -- <&cru ACLK_RKVDEC1>; -- pm_qos = <&qos_rkvdec1>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_VENC0 { -- reg = ; -- clocks = <&cru HCLK_RKVENC0>, -- <&cru ACLK_RKVENC0>; -- pm_qos = <&qos_rkvenc0_m0ro>, -- <&qos_rkvenc0_m1ro>, -- <&qos_rkvenc0_m2wo>; -- #address-cells = <1>; -- #size-cells = <0>; -- #power-domain-cells = <0>; -- -- power-domain@RK3588_PD_VENC1 { -- reg = ; -- clocks = <&cru HCLK_RKVENC1>, -- <&cru HCLK_RKVENC0>, -- <&cru ACLK_RKVENC0>, -- <&cru ACLK_RKVENC1>; -- pm_qos = <&qos_rkvenc1_m0ro>, -- <&qos_rkvenc1_m1ro>, -- <&qos_rkvenc1_m2wo>; -- #power-domain-cells = <0>; -- }; -- }; -- }; -- /* These power domains are grouped by VD_LOGIC */ -- power-domain@RK3588_PD_VDPU { -- reg = ; -- clocks = <&cru HCLK_VDPU_ROOT>, -- <&cru ACLK_VDPU_LOW_ROOT>, -- <&cru ACLK_VDPU_ROOT>, -- <&cru ACLK_JPEG_DECODER_ROOT>, -- <&cru ACLK_IEP2P0>, -- <&cru HCLK_IEP2P0>, -- <&cru ACLK_JPEG_ENCODER0>, -- <&cru HCLK_JPEG_ENCODER0>, -- <&cru ACLK_JPEG_ENCODER1>, -- <&cru HCLK_JPEG_ENCODER1>, -- <&cru ACLK_JPEG_ENCODER2>, -- <&cru HCLK_JPEG_ENCODER2>, -- <&cru ACLK_JPEG_ENCODER3>, -- <&cru HCLK_JPEG_ENCODER3>, -- <&cru ACLK_JPEG_DECODER>, -- <&cru HCLK_JPEG_DECODER>, -- <&cru ACLK_RGA2>, -- <&cru HCLK_RGA2>; -- pm_qos = <&qos_iep>, -- <&qos_jpeg_dec>, -- <&qos_jpeg_enc0>, -- <&qos_jpeg_enc1>, -- <&qos_jpeg_enc2>, -- <&qos_jpeg_enc3>, -- <&qos_rga2_mro>, -- <&qos_rga2_mwo>; -- #address-cells = <1>; -- #size-cells = <0>; -- #power-domain-cells = <0>; -- -- -- power-domain@RK3588_PD_AV1 { -- reg = ; -- clocks = <&cru PCLK_AV1>, -- <&cru ACLK_AV1>, -- <&cru HCLK_VDPU_ROOT>; -- pm_qos = <&qos_av1>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_RKVDEC0 { -- reg = ; -- clocks = <&cru HCLK_RKVDEC0>, -- <&cru HCLK_VDPU_ROOT>, -- <&cru ACLK_VDPU_ROOT>, -- <&cru ACLK_RKVDEC0>; -- pm_qos = <&qos_rkvdec0>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_RKVDEC1 { -- reg = ; -- clocks = <&cru HCLK_RKVDEC1>, -- <&cru HCLK_VDPU_ROOT>, -- <&cru ACLK_VDPU_ROOT>; -- pm_qos = <&qos_rkvdec1>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_RGA30 { -- reg = ; -- clocks = <&cru ACLK_RGA3_0>, -- <&cru HCLK_RGA3_0>; -- pm_qos = <&qos_rga3_0>; -- #power-domain-cells = <0>; -- }; -- }; -- power-domain@RK3588_PD_VOP { -- reg = ; -- clocks = <&cru PCLK_VOP_ROOT>, -- <&cru HCLK_VOP_ROOT>, -- <&cru ACLK_VOP>; -- pm_qos = <&qos_vop_m0>, -- <&qos_vop_m1>; -- #address-cells = <1>; -- #size-cells = <0>; -- #power-domain-cells = <0>; -- -- power-domain@RK3588_PD_VO0 { -- reg = ; -- clocks = <&cru PCLK_VO0_ROOT>, -- <&cru PCLK_VO0_S_ROOT>, -- <&cru HCLK_VO0_S_ROOT>, -- <&cru ACLK_VO0_ROOT>, -- <&cru HCLK_HDCP0>, -- <&cru ACLK_HDCP0>, -- <&cru HCLK_VOP_ROOT>; -- pm_qos = <&qos_hdcp0>; -- #power-domain-cells = <0>; -- }; -- }; -- power-domain@RK3588_PD_VO1 { -- reg = ; -- clocks = <&cru PCLK_VO1_ROOT>, -- <&cru PCLK_VO1_S_ROOT>, -- <&cru HCLK_VO1_S_ROOT>, -- <&cru HCLK_HDCP1>, -- <&cru ACLK_HDCP1>, -- <&cru ACLK_HDMIRX_ROOT>, -- <&cru HCLK_VO1USB_TOP_ROOT>; -- pm_qos = <&qos_hdcp1>, -- <&qos_hdmirx>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_VI { -- reg = ; -- clocks = <&cru HCLK_VI_ROOT>, -- <&cru PCLK_VI_ROOT>, -- <&cru HCLK_ISP0>, -- <&cru ACLK_ISP0>, -- <&cru HCLK_VICAP>, -- <&cru ACLK_VICAP>; -- pm_qos = <&qos_isp0_mro>, -- <&qos_isp0_mwo>, -- <&qos_vicap_m0>, -- <&qos_vicap_m1>; -- #address-cells = <1>; -- #size-cells = <0>; -- #power-domain-cells = <0>; -- -- power-domain@RK3588_PD_ISP1 { -- reg = ; -- clocks = <&cru HCLK_ISP1>, -- <&cru ACLK_ISP1>, -- <&cru HCLK_VI_ROOT>, -- <&cru PCLK_VI_ROOT>; -- pm_qos = <&qos_isp1_mwo>, -- <&qos_isp1_mro>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_FEC { -- reg = ; -- clocks = <&cru HCLK_FISHEYE0>, -- <&cru ACLK_FISHEYE0>, -- <&cru HCLK_FISHEYE1>, -- <&cru ACLK_FISHEYE1>, -- <&cru PCLK_VI_ROOT>; -- pm_qos = <&qos_fisheye0>, -- <&qos_fisheye1>; -- #power-domain-cells = <0>; -- }; -- }; -- power-domain@RK3588_PD_RGA31 { -- reg = ; -- clocks = <&cru HCLK_RGA3_1>, -- <&cru ACLK_RGA3_1>; -- pm_qos = <&qos_rga3_1>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_USB { -- reg = ; -- clocks = <&cru PCLK_PHP_ROOT>, -- <&cru ACLK_USB_ROOT>, -- <&cru ACLK_USB>, -- <&cru HCLK_USB_ROOT>, -- <&cru HCLK_HOST0>, -- <&cru HCLK_HOST_ARB0>, -- <&cru HCLK_HOST1>, -- <&cru HCLK_HOST_ARB1>; -- pm_qos = <&qos_usb3_0>, -- <&qos_usb3_1>, -- <&qos_usb2host_0>, -- <&qos_usb2host_1>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_GMAC { -- reg = ; -- clocks = <&cru PCLK_PHP_ROOT>, -- <&cru ACLK_PCIE_ROOT>, -- <&cru ACLK_PHP_ROOT>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_PCIE { -- reg = ; -- clocks = <&cru PCLK_PHP_ROOT>, -- <&cru ACLK_PCIE_ROOT>, -- <&cru ACLK_PHP_ROOT>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_SDIO { -- reg = ; -- clocks = <&cru HCLK_SDIO>, -- <&cru HCLK_NVM_ROOT>; -- pm_qos = <&qos_sdio>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_AUDIO { -- reg = ; -- clocks = <&cru HCLK_AUDIO_ROOT>, -- <&cru PCLK_AUDIO_ROOT>; -- #power-domain-cells = <0>; -- }; -- power-domain@RK3588_PD_SDMMC { -- reg = ; -- pm_qos = <&qos_sdmmc>; -- #power-domain-cells = <0>; -- }; -- }; -- }; -- -- av1d: video-codec@fdc70000 { -- compatible = "rockchip,rk3588-av1-vpu"; -- reg = <0x0 0xfdc70000 0x0 0x800>; -- interrupts = ; -- interrupt-names = "vdpu"; -- assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; -- assigned-clock-rates = <400000000>, <400000000>; -- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; -- clock-names = "aclk", "hclk"; -- power-domains = <&power RK3588_PD_AV1>; -- resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; -- }; -- -- vop: vop@fdd90000 { -- compatible = "rockchip,rk3588-vop"; -- reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; -- reg-names = "vop", "gamma-lut"; -- interrupts = ; -- clocks = <&cru ACLK_VOP>, -- <&cru HCLK_VOP>, -- <&cru DCLK_VOP0>, -- <&cru DCLK_VOP1>, -- <&cru DCLK_VOP2>, -- <&cru DCLK_VOP3>, -- <&cru PCLK_VOP_ROOT>; -- clock-names = "aclk", -- "hclk", -- "dclk_vp0", -- "dclk_vp1", -- "dclk_vp2", -- "dclk_vp3", -- "pclk_vop"; -- iommus = <&vop_mmu>; -- power-domains = <&power RK3588_PD_VOP>; -- rockchip,grf = <&sys_grf>; -- rockchip,vop-grf = <&vop_grf>; -- rockchip,vo1-grf = <&vo1_grf>; -- rockchip,pmu = <&pmu>; -- status = "disabled"; -- -- vop_out: ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- vp0: port@0 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0>; -- }; -- -- vp1: port@1 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <1>; -- }; -- -- vp2: port@2 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <2>; -- }; -- -- vp3: port@3 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <3>; -- }; -- }; -- }; -- -- vop_mmu: iommu@fdd97e00 { -- compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -- reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; -- interrupts = ; -- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; -- clock-names = "aclk", "iface"; -- #iommu-cells = <0>; -- power-domains = <&power RK3588_PD_VOP>; -- status = "disabled"; -- }; -- -- i2s4_8ch: i2s@fddc0000 { -- compatible = "rockchip,rk3588-i2s-tdm"; -- reg = <0x0 0xfddc0000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; -- clock-names = "mclk_tx", "mclk_rx", "hclk"; -- assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; -- assigned-clock-parents = <&cru PLL_AUPLL>; -- dmas = <&dmac2 0>; -- dma-names = "tx"; -- power-domains = <&power RK3588_PD_VO0>; -- resets = <&cru SRST_M_I2S4_8CH_TX>; -- reset-names = "tx-m"; -- #sound-dai-cells = <0>; -- status = "disabled"; -- }; -- -- i2s5_8ch: i2s@fddf0000 { -- compatible = "rockchip,rk3588-i2s-tdm"; -- reg = <0x0 0xfddf0000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; -- clock-names = "mclk_tx", "mclk_rx", "hclk"; -- assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; -- assigned-clock-parents = <&cru PLL_AUPLL>; -- dmas = <&dmac2 2>; -- dma-names = "tx"; -- power-domains = <&power RK3588_PD_VO1>; -- resets = <&cru SRST_M_I2S5_8CH_TX>; -- reset-names = "tx-m"; -- #sound-dai-cells = <0>; -- status = "disabled"; -- }; -- -- i2s9_8ch: i2s@fddfc000 { -- compatible = "rockchip,rk3588-i2s-tdm"; -- reg = <0x0 0xfddfc000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; -- clock-names = "mclk_tx", "mclk_rx", "hclk"; -- assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; -- assigned-clock-parents = <&cru PLL_AUPLL>; -- dmas = <&dmac2 23>; -- dma-names = "rx"; -- power-domains = <&power RK3588_PD_VO1>; -- resets = <&cru SRST_M_I2S9_8CH_RX>; -- reset-names = "rx-m"; -- #sound-dai-cells = <0>; -- status = "disabled"; -- }; -- -- qos_gpu_m0: qos@fdf35000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf35000 0x0 0x20>; -- }; -- -- qos_gpu_m1: qos@fdf35200 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf35200 0x0 0x20>; -- }; -- -- qos_gpu_m2: qos@fdf35400 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf35400 0x0 0x20>; -- }; -- -- qos_gpu_m3: qos@fdf35600 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf35600 0x0 0x20>; -- }; -- -- qos_rga3_1: qos@fdf36000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf36000 0x0 0x20>; -- }; -- -- qos_sdio: qos@fdf39000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf39000 0x0 0x20>; -- }; -- -- qos_sdmmc: qos@fdf3d800 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf3d800 0x0 0x20>; -- }; -- -- qos_usb3_1: qos@fdf3e000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf3e000 0x0 0x20>; -- }; -- -- qos_usb3_0: qos@fdf3e200 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf3e200 0x0 0x20>; -- }; -- -- qos_usb2host_0: qos@fdf3e400 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf3e400 0x0 0x20>; -- }; -- -- qos_usb2host_1: qos@fdf3e600 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf3e600 0x0 0x20>; -- }; -- -- qos_fisheye0: qos@fdf40000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf40000 0x0 0x20>; -- }; -- -- qos_fisheye1: qos@fdf40200 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf40200 0x0 0x20>; -- }; -- -- qos_isp0_mro: qos@fdf40400 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf40400 0x0 0x20>; -- }; -- -- qos_isp0_mwo: qos@fdf40500 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf40500 0x0 0x20>; -- }; -- -- qos_vicap_m0: qos@fdf40600 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf40600 0x0 0x20>; -- }; -- -- qos_vicap_m1: qos@fdf40800 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf40800 0x0 0x20>; -- }; -- -- qos_isp1_mwo: qos@fdf41000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf41000 0x0 0x20>; -- }; -- -- qos_isp1_mro: qos@fdf41100 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf41100 0x0 0x20>; -- }; -- -- qos_rkvenc0_m0ro: qos@fdf60000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf60000 0x0 0x20>; -- }; -- -- qos_rkvenc0_m1ro: qos@fdf60200 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf60200 0x0 0x20>; -- }; -- -- qos_rkvenc0_m2wo: qos@fdf60400 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf60400 0x0 0x20>; -- }; -- -- qos_rkvenc1_m0ro: qos@fdf61000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf61000 0x0 0x20>; -- }; -- -- qos_rkvenc1_m1ro: qos@fdf61200 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf61200 0x0 0x20>; -- }; -- -- qos_rkvenc1_m2wo: qos@fdf61400 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf61400 0x0 0x20>; -- }; -- -- qos_rkvdec0: qos@fdf62000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf62000 0x0 0x20>; -- }; -- -- qos_rkvdec1: qos@fdf63000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf63000 0x0 0x20>; -- }; -- -- qos_av1: qos@fdf64000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf64000 0x0 0x20>; -- }; -- -- qos_iep: qos@fdf66000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf66000 0x0 0x20>; -- }; -- -- qos_jpeg_dec: qos@fdf66200 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf66200 0x0 0x20>; -- }; -- -- qos_jpeg_enc0: qos@fdf66400 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf66400 0x0 0x20>; -- }; -- -- qos_jpeg_enc1: qos@fdf66600 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf66600 0x0 0x20>; -- }; -- -- qos_jpeg_enc2: qos@fdf66800 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf66800 0x0 0x20>; -- }; -- -- qos_jpeg_enc3: qos@fdf66a00 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf66a00 0x0 0x20>; -- }; -- -- qos_rga2_mro: qos@fdf66c00 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf66c00 0x0 0x20>; -- }; -- -- qos_rga2_mwo: qos@fdf66e00 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf66e00 0x0 0x20>; -- }; -- -- qos_rga3_0: qos@fdf67000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf67000 0x0 0x20>; -- }; -- -- qos_vdpu: qos@fdf67200 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf67200 0x0 0x20>; -- }; -- -- qos_npu1: qos@fdf70000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf70000 0x0 0x20>; -- }; -- -- qos_npu2: qos@fdf71000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf71000 0x0 0x20>; -- }; -- -- qos_npu0_mwr: qos@fdf72000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf72000 0x0 0x20>; -- }; -- -- qos_npu0_mro: qos@fdf72200 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf72200 0x0 0x20>; -- }; -- -- qos_mcu_npu: qos@fdf72400 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf72400 0x0 0x20>; -- }; -- -- qos_hdcp0: qos@fdf80000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf80000 0x0 0x20>; -- }; -- -- qos_hdcp1: qos@fdf81000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf81000 0x0 0x20>; -- }; -- -- qos_hdmirx: qos@fdf81200 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf81200 0x0 0x20>; -- }; -- -- qos_vop_m0: qos@fdf82000 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf82000 0x0 0x20>; -- }; -- -- qos_vop_m1: qos@fdf82200 { -- compatible = "rockchip,rk3588-qos", "syscon"; -- reg = <0x0 0xfdf82200 0x0 0x20>; -- }; -- -- dfi: dfi@fe060000 { -- reg = <0x00 0xfe060000 0x00 0x10000>; -- compatible = "rockchip,rk3588-dfi"; -- interrupts = , -- , -- , -- ; -- rockchip,pmu = <&pmu1grf>; -- }; -- -- pcie2x1l1: pcie@fe180000 { -- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -- bus-range = <0x30 0x3f>; -- clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, -- <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, -- <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; -- clock-names = "aclk_mst", "aclk_slv", -- "aclk_dbi", "pclk", -- "aux", "pipe"; -- device_type = "pci"; -- interrupts = , -- , -- , -- , -- ; -- interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, -- <0 0 0 2 &pcie2x1l1_intc 1>, -- <0 0 0 3 &pcie2x1l1_intc 2>, -- <0 0 0 4 &pcie2x1l1_intc 3>; -- linux,pci-domain = <3>; -- max-link-speed = <2>; -- msi-map = <0x3000 &its0 0x3000 0x1000>; -- num-lanes = <1>; -- phys = <&combphy2_psu PHY_TYPE_PCIE>; -- phy-names = "pcie-phy"; -- power-domains = <&power RK3588_PD_PCIE>; -- ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, -- <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, -- <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; -- reg = <0xa 0x40c00000 0x0 0x00400000>, -- <0x0 0xfe180000 0x0 0x00010000>, -- <0x0 0xf3000000 0x0 0x00100000>; -- reg-names = "dbi", "apb", "config"; -- resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; -- reset-names = "pwr", "pipe"; -- #address-cells = <3>; -- #size-cells = <2>; -- status = "disabled"; -- -- pcie2x1l1_intc: legacy-interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- interrupt-parent = <&gic>; -- interrupts = ; -- }; -- }; -- -- pcie2x1l2: pcie@fe190000 { -- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -- bus-range = <0x40 0x4f>; -- clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, -- <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, -- <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; -- clock-names = "aclk_mst", "aclk_slv", -- "aclk_dbi", "pclk", -- "aux", "pipe"; -- device_type = "pci"; -- interrupts = , -- , -- , -- , -- ; -- interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, -- <0 0 0 2 &pcie2x1l2_intc 1>, -- <0 0 0 3 &pcie2x1l2_intc 2>, -- <0 0 0 4 &pcie2x1l2_intc 3>; -- linux,pci-domain = <4>; -- max-link-speed = <2>; -- msi-map = <0x4000 &its0 0x4000 0x1000>; -- num-lanes = <1>; -- phys = <&combphy0_ps PHY_TYPE_PCIE>; -- phy-names = "pcie-phy"; -- power-domains = <&power RK3588_PD_PCIE>; -- ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, -- <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, -- <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; -- reg = <0xa 0x41000000 0x0 0x00400000>, -- <0x0 0xfe190000 0x0 0x00010000>, -- <0x0 0xf4000000 0x0 0x00100000>; -- reg-names = "dbi", "apb", "config"; -- resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; -- reset-names = "pwr", "pipe"; -- #address-cells = <3>; -- #size-cells = <2>; -- status = "disabled"; -- -- pcie2x1l2_intc: legacy-interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- interrupt-parent = <&gic>; -- interrupts = ; -- }; -- }; -- -- gmac1: ethernet@fe1c0000 { -- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; -- reg = <0x0 0xfe1c0000 0x0 0x10000>; -- interrupts = , -- ; -- interrupt-names = "macirq", "eth_wake_irq"; -- clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, -- <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, -- <&cru CLK_GMAC1_PTP_REF>; -- clock-names = "stmmaceth", "clk_mac_ref", -- "pclk_mac", "aclk_mac", -- "ptp_ref"; -- power-domains = <&power RK3588_PD_GMAC>; -- resets = <&cru SRST_A_GMAC1>; -- reset-names = "stmmaceth"; -- rockchip,grf = <&sys_grf>; -- rockchip,php-grf = <&php_grf>; -- snps,axi-config = <&gmac1_stmmac_axi_setup>; -- snps,mixed-burst; -- snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; -- snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; -- snps,tso; -- status = "disabled"; -- -- mdio1: mdio { -- compatible = "snps,dwmac-mdio"; -- #address-cells = <0x1>; -- #size-cells = <0x0>; -- }; -- -- gmac1_stmmac_axi_setup: stmmac-axi-config { -- snps,blen = <0 0 0 0 16 8 4>; -- snps,wr_osr_lmt = <4>; -- snps,rd_osr_lmt = <8>; -- }; -- -- gmac1_mtl_rx_setup: rx-queues-config { -- snps,rx-queues-to-use = <2>; -- queue0 {}; -- queue1 {}; -- }; -- -- gmac1_mtl_tx_setup: tx-queues-config { -- snps,tx-queues-to-use = <2>; -- queue0 {}; -- queue1 {}; -- }; -- }; -- -- sata0: sata@fe210000 { -- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; -- reg = <0 0xfe210000 0 0x1000>; -- interrupts = ; -- clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, -- <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, -- <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; -- clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; -- ports-implemented = <0x1>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- -- sata-port@0 { -- reg = <0>; -- hba-port-cap = ; -- phys = <&combphy0_ps PHY_TYPE_SATA>; -- phy-names = "sata-phy"; -- snps,rx-ts-max = <32>; -- snps,tx-ts-max = <32>; -- }; -- }; -- -- sata2: sata@fe230000 { -- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; -- reg = <0 0xfe230000 0 0x1000>; -- interrupts = ; -- clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, -- <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, -- <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; -- clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; -- ports-implemented = <0x1>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- -- sata-port@0 { -- reg = <0>; -- hba-port-cap = ; -- phys = <&combphy2_psu PHY_TYPE_SATA>; -- phy-names = "sata-phy"; -- snps,rx-ts-max = <32>; -- snps,tx-ts-max = <32>; -- }; -- }; -- -- sfc: spi@fe2b0000 { -- compatible = "rockchip,sfc"; -- reg = <0x0 0xfe2b0000 0x0 0x4000>; -- interrupts = ; -- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; -- clock-names = "clk_sfc", "hclk_sfc"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- sdmmc: mmc@fe2c0000 { -- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; -- reg = <0x0 0xfe2c0000 0x0 0x4000>; -- interrupts = ; -- clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, -- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; -- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -- fifo-depth = <0x100>; -- max-frequency = <200000000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; -- power-domains = <&power RK3588_PD_SDMMC>; -- status = "disabled"; -- }; -- -- sdio: mmc@fe2d0000 { -- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; -- reg = <0x00 0xfe2d0000 0x00 0x4000>; -- interrupts = ; -- clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, -- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; -- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -- fifo-depth = <0x100>; -- max-frequency = <200000000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&sdiom1_pins>; -- power-domains = <&power RK3588_PD_SDIO>; -- status = "disabled"; -- }; -- -- sdhci: mmc@fe2e0000 { -- compatible = "rockchip,rk3588-dwcmshc"; -- reg = <0x0 0xfe2e0000 0x0 0x10000>; -- interrupts = ; -- assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; -- assigned-clock-rates = <200000000>, <24000000>, <200000000>; -- clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, -- <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, -- <&cru TMCLK_EMMC>; -- clock-names = "core", "bus", "axi", "block", "timer"; -- max-frequency = <200000000>; -- pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, -- <&emmc_cmd>, <&emmc_data_strobe>; -- pinctrl-names = "default"; -- resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, -- <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, -- <&cru SRST_T_EMMC>; -- reset-names = "core", "bus", "axi", "block", "timer"; -- status = "disabled"; -- }; -- -- i2s0_8ch: i2s@fe470000 { -- compatible = "rockchip,rk3588-i2s-tdm"; -- reg = <0x0 0xfe470000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; -- clock-names = "mclk_tx", "mclk_rx", "hclk"; -- assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; -- assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; -- dmas = <&dmac0 0>, <&dmac0 1>; -- dma-names = "tx", "rx"; -- power-domains = <&power RK3588_PD_AUDIO>; -- resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; -- reset-names = "tx-m", "rx-m"; -- rockchip,trcm-sync-tx-only; -- pinctrl-names = "default"; -- pinctrl-0 = <&i2s0_lrck -- &i2s0_sclk -- &i2s0_sdi0 -- &i2s0_sdi1 -- &i2s0_sdi2 -- &i2s0_sdi3 -- &i2s0_sdo0 -- &i2s0_sdo1 -- &i2s0_sdo2 -- &i2s0_sdo3>; -- #sound-dai-cells = <0>; -- status = "disabled"; -- }; -- -- i2s1_8ch: i2s@fe480000 { -- compatible = "rockchip,rk3588-i2s-tdm"; -- reg = <0x0 0xfe480000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; -- clock-names = "mclk_tx", "mclk_rx", "hclk"; -- dmas = <&dmac0 2>, <&dmac0 3>; -- dma-names = "tx", "rx"; -- resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; -- reset-names = "tx-m", "rx-m"; -- rockchip,trcm-sync-tx-only; -- pinctrl-names = "default"; -- pinctrl-0 = <&i2s1m0_lrck -- &i2s1m0_sclk -- &i2s1m0_sdi0 -- &i2s1m0_sdi1 -- &i2s1m0_sdi2 -- &i2s1m0_sdi3 -- &i2s1m0_sdo0 -- &i2s1m0_sdo1 -- &i2s1m0_sdo2 -- &i2s1m0_sdo3>; -- #sound-dai-cells = <0>; -- status = "disabled"; -- }; -- -- i2s2_2ch: i2s@fe490000 { -- compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; -- reg = <0x0 0xfe490000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; -- clock-names = "i2s_clk", "i2s_hclk"; -- assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; -- assigned-clock-parents = <&cru PLL_AUPLL>; -- dmas = <&dmac1 0>, <&dmac1 1>; -- dma-names = "tx", "rx"; -- power-domains = <&power RK3588_PD_AUDIO>; -- pinctrl-names = "default"; -- pinctrl-0 = <&i2s2m1_lrck -- &i2s2m1_sclk -- &i2s2m1_sdi -- &i2s2m1_sdo>; -- #sound-dai-cells = <0>; -- status = "disabled"; -- }; -- -- i2s3_2ch: i2s@fe4a0000 { -- compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; -- reg = <0x0 0xfe4a0000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; -- clock-names = "i2s_clk", "i2s_hclk"; -- assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; -- assigned-clock-parents = <&cru PLL_AUPLL>; -- dmas = <&dmac1 2>, <&dmac1 3>; -- dma-names = "tx", "rx"; -- power-domains = <&power RK3588_PD_AUDIO>; -- pinctrl-names = "default"; -- pinctrl-0 = <&i2s3_lrck -- &i2s3_sclk -- &i2s3_sdi -- &i2s3_sdo>; -- #sound-dai-cells = <0>; -- status = "disabled"; -- }; -- -- gic: interrupt-controller@fe600000 { -- compatible = "arm,gic-v3"; -- reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ -- <0x0 0xfe680000 0 0x100000>; /* GICR */ -- interrupts = ; -- interrupt-controller; -- mbi-alias = <0x0 0xfe610000>; -- mbi-ranges = <424 56>; -- msi-controller; -- ranges; -- #address-cells = <2>; -- #interrupt-cells = <4>; -- #size-cells = <2>; -- -- its0: msi-controller@fe640000 { -- compatible = "arm,gic-v3-its"; -- reg = <0x0 0xfe640000 0x0 0x20000>; -- msi-controller; -- #msi-cells = <1>; -- }; -- -- its1: msi-controller@fe660000 { -- compatible = "arm,gic-v3-its"; -- reg = <0x0 0xfe660000 0x0 0x20000>; -- msi-controller; -- #msi-cells = <1>; -- }; -- -- ppi-partitions { -- ppi_partition0: interrupt-partition-0 { -- affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; -- }; -- -- ppi_partition1: interrupt-partition-1 { -- affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; -- }; -- }; -- }; -- -- dmac0: dma-controller@fea10000 { -- compatible = "arm,pl330", "arm,primecell"; -- reg = <0x0 0xfea10000 0x0 0x4000>; -- interrupts = , -- ; -- arm,pl330-periph-burst; -- clocks = <&cru ACLK_DMAC0>; -- clock-names = "apb_pclk"; -- #dma-cells = <1>; -- }; -- -- dmac1: dma-controller@fea30000 { -- compatible = "arm,pl330", "arm,primecell"; -- reg = <0x0 0xfea30000 0x0 0x4000>; -- interrupts = , -- ; -- arm,pl330-periph-burst; -- clocks = <&cru ACLK_DMAC1>; -- clock-names = "apb_pclk"; -- #dma-cells = <1>; -- }; -- -- i2c1: i2c@fea90000 { -- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfea90000 0x0 0x1000>; -- clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; -- clock-names = "i2c", "pclk"; -- interrupts = ; -- pinctrl-0 = <&i2c1m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c2: i2c@feaa0000 { -- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfeaa0000 0x0 0x1000>; -- clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; -- clock-names = "i2c", "pclk"; -- interrupts = ; -- pinctrl-0 = <&i2c2m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c3: i2c@feab0000 { -- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfeab0000 0x0 0x1000>; -- clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; -- clock-names = "i2c", "pclk"; -- interrupts = ; -- pinctrl-0 = <&i2c3m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c4: i2c@feac0000 { -- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfeac0000 0x0 0x1000>; -- clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; -- clock-names = "i2c", "pclk"; -- interrupts = ; -- pinctrl-0 = <&i2c4m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c5: i2c@fead0000 { -- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfead0000 0x0 0x1000>; -- clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; -- clock-names = "i2c", "pclk"; -- interrupts = ; -- pinctrl-0 = <&i2c5m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- timer0: timer@feae0000 { -- compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; -- reg = <0x0 0xfeae0000 0x0 0x20>; -- interrupts = ; -- clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; -- clock-names = "pclk", "timer"; -- }; -- -- wdt: watchdog@feaf0000 { -- compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; -- reg = <0x0 0xfeaf0000 0x0 0x100>; -- clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; -- clock-names = "tclk", "pclk"; -- interrupts = ; -- }; -- -- spi0: spi@feb00000 { -- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; -- reg = <0x0 0xfeb00000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; -- clock-names = "spiclk", "apb_pclk"; -- dmas = <&dmac0 14>, <&dmac0 15>; -- dma-names = "tx", "rx"; -- num-cs = <2>; -- pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- spi1: spi@feb10000 { -- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; -- reg = <0x0 0xfeb10000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; -- clock-names = "spiclk", "apb_pclk"; -- dmas = <&dmac0 16>, <&dmac0 17>; -- dma-names = "tx", "rx"; -- num-cs = <2>; -- pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- spi2: spi@feb20000 { -- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; -- reg = <0x0 0xfeb20000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; -- clock-names = "spiclk", "apb_pclk"; -- dmas = <&dmac1 15>, <&dmac1 16>; -- dma-names = "tx", "rx"; -- num-cs = <2>; -- pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- spi3: spi@feb30000 { -- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; -- reg = <0x0 0xfeb30000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; -- clock-names = "spiclk", "apb_pclk"; -- dmas = <&dmac1 17>, <&dmac1 18>; -- dma-names = "tx", "rx"; -- num-cs = <2>; -- pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- uart1: serial@feb40000 { -- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfeb40000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 8>, <&dmac0 9>; -- dma-names = "tx", "rx"; -- pinctrl-0 = <&uart1m1_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart2: serial@feb50000 { -- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfeb50000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 10>, <&dmac0 11>; -- dma-names = "tx", "rx"; -- pinctrl-0 = <&uart2m1_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart3: serial@feb60000 { -- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfeb60000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 12>, <&dmac0 13>; -- dma-names = "tx", "rx"; -- pinctrl-0 = <&uart3m1_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart4: serial@feb70000 { -- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfeb70000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac1 9>, <&dmac1 10>; -- dma-names = "tx", "rx"; -- pinctrl-0 = <&uart4m1_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart5: serial@feb80000 { -- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfeb80000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac1 11>, <&dmac1 12>; -- dma-names = "tx", "rx"; -- pinctrl-0 = <&uart5m1_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart6: serial@feb90000 { -- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfeb90000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac1 13>, <&dmac1 14>; -- dma-names = "tx", "rx"; -- pinctrl-0 = <&uart6m1_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart7: serial@feba0000 { -- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfeba0000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac2 7>, <&dmac2 8>; -- dma-names = "tx", "rx"; -- pinctrl-0 = <&uart7m1_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart8: serial@febb0000 { -- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfebb0000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac2 9>, <&dmac2 10>; -- dma-names = "tx", "rx"; -- pinctrl-0 = <&uart8m1_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart9: serial@febc0000 { -- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfebc0000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac2 11>, <&dmac2 12>; -- dma-names = "tx", "rx"; -- pinctrl-0 = <&uart9m1_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- pwm4: pwm@febd0000 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfebd0000 0x0 0x10>; -- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm4m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm5: pwm@febd0010 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfebd0010 0x0 0x10>; -- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm5m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm6: pwm@febd0020 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfebd0020 0x0 0x10>; -- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm6m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm7: pwm@febd0030 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfebd0030 0x0 0x10>; -- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm7m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm8: pwm@febe0000 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfebe0000 0x0 0x10>; -- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm8m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm9: pwm@febe0010 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfebe0010 0x0 0x10>; -- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm9m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm10: pwm@febe0020 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfebe0020 0x0 0x10>; -- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm10m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm11: pwm@febe0030 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfebe0030 0x0 0x10>; -- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm11m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm12: pwm@febf0000 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfebf0000 0x0 0x10>; -- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm12m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm13: pwm@febf0010 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfebf0010 0x0 0x10>; -- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm13m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm14: pwm@febf0020 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfebf0020 0x0 0x10>; -- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm14m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm15: pwm@febf0030 { -- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfebf0030 0x0 0x10>; -- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm15m0_pins>; -- pinctrl-names = "default"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- tsadc: tsadc@fec00000 { -- compatible = "rockchip,rk3588-tsadc"; -- reg = <0x0 0xfec00000 0x0 0x400>; -- interrupts = ; -- clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; -- clock-names = "tsadc", "apb_pclk"; -- assigned-clocks = <&cru CLK_TSADC>; -- assigned-clock-rates = <2000000>; -- resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; -- reset-names = "tsadc-apb", "tsadc"; -- rockchip,hw-tshut-temp = <120000>; -- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ -- rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ -- pinctrl-0 = <&tsadc_gpio_func>; -- pinctrl-1 = <&tsadc_shut>; -- pinctrl-names = "gpio", "otpout"; -- #thermal-sensor-cells = <1>; -- status = "disabled"; -- }; -- -- saradc: adc@fec10000 { -- compatible = "rockchip,rk3588-saradc"; -- reg = <0x0 0xfec10000 0x0 0x10000>; -- interrupts = ; -- #io-channel-cells = <1>; -- clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; -- clock-names = "saradc", "apb_pclk"; -- resets = <&cru SRST_P_SARADC>; -- reset-names = "saradc-apb"; -- status = "disabled"; -- }; -- -- i2c6: i2c@fec80000 { -- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfec80000 0x0 0x1000>; -- clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; -- clock-names = "i2c", "pclk"; -- interrupts = ; -- pinctrl-0 = <&i2c6m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c7: i2c@fec90000 { -- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfec90000 0x0 0x1000>; -- clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; -- clock-names = "i2c", "pclk"; -- interrupts = ; -- pinctrl-0 = <&i2c7m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c8: i2c@feca0000 { -- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfeca0000 0x0 0x1000>; -- clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; -- clock-names = "i2c", "pclk"; -- interrupts = ; -- pinctrl-0 = <&i2c8m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- spi4: spi@fecb0000 { -- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; -- reg = <0x0 0xfecb0000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; -- clock-names = "spiclk", "apb_pclk"; -- dmas = <&dmac2 13>, <&dmac2 14>; -- dma-names = "tx", "rx"; -- num-cs = <2>; -- pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- otp: efuse@fecc0000 { -- compatible = "rockchip,rk3588-otp"; -- reg = <0x0 0xfecc0000 0x0 0x400>; -- clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, -- <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; -- clock-names = "otp", "apb_pclk", "phy", "arb"; -- resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, -- <&cru SRST_OTPC_ARB>; -- reset-names = "otp", "apb", "arb"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- cpu_code: cpu-code@2 { -- reg = <0x02 0x2>; -- }; -- -- otp_id: id@7 { -- reg = <0x07 0x10>; -- }; -- -- cpub0_leakage: cpu-leakage@17 { -- reg = <0x17 0x1>; -- }; -- -- cpub1_leakage: cpu-leakage@18 { -- reg = <0x18 0x1>; -- }; -- -- cpul_leakage: cpu-leakage@19 { -- reg = <0x19 0x1>; -- }; -- -- log_leakage: log-leakage@1a { -- reg = <0x1a 0x1>; -- }; -- -- gpu_leakage: gpu-leakage@1b { -- reg = <0x1b 0x1>; -- }; -- -- otp_cpu_version: cpu-version@1c { -- reg = <0x1c 0x1>; -- bits = <3 3>; -- }; -- -- npu_leakage: npu-leakage@28 { -- reg = <0x28 0x1>; -- }; -- -- codec_leakage: codec-leakage@29 { -- reg = <0x29 0x1>; -- }; -- }; -- -- dmac2: dma-controller@fed10000 { -- compatible = "arm,pl330", "arm,primecell"; -- reg = <0x0 0xfed10000 0x0 0x4000>; -- interrupts = , -- ; -- arm,pl330-periph-burst; -- clocks = <&cru ACLK_DMAC2>; -- clock-names = "apb_pclk"; -- #dma-cells = <1>; -- }; -- -- hdptxphy_hdmi0: phy@fed60000 { -- compatible = "rockchip,rk3588-hdptx-phy"; -- reg = <0x0 0xfed60000 0x0 0x2000>; -- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; -- clock-names = "ref", "apb"; -- #phy-cells = <0>; -- resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, -- <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, -- <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, -- <&cru SRST_HDPTX0_LCPLL>; -- reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", -- "lcpll"; -- rockchip,grf = <&hdptxphy0_grf>; -- status = "disabled"; -- }; -- -- usbdp_phy0: phy@fed80000 { -- compatible = "rockchip,rk3588-usbdp-phy"; -- reg = <0x0 0xfed80000 0x0 0x10000>; -- #phy-cells = <1>; -- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, -- <&cru CLK_USBDP_PHY0_IMMORTAL>, -- <&cru PCLK_USBDPPHY0>, -- <&u2phy0>; -- clock-names = "refclk", "immortal", "pclk", "utmi"; -- resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, -- <&cru SRST_USBDP_COMBO_PHY0_CMN>, -- <&cru SRST_USBDP_COMBO_PHY0_LANE>, -- <&cru SRST_USBDP_COMBO_PHY0_PCS>, -- <&cru SRST_P_USBDPPHY0>; -- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; -- rockchip,u2phy-grf = <&usb2phy0_grf>; -- rockchip,usb-grf = <&usb_grf>; -- rockchip,usbdpphy-grf = <&usbdpphy0_grf>; -- rockchip,vo-grf = <&vo0_grf>; -- status = "disabled"; -- }; -- -- combphy0_ps: phy@fee00000 { -- compatible = "rockchip,rk3588-naneng-combphy"; -- reg = <0x0 0xfee00000 0x0 0x100>; -- clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, -- <&cru PCLK_PHP_ROOT>; -- clock-names = "ref", "apb", "pipe"; -- assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; -- assigned-clock-rates = <100000000>; -- #phy-cells = <1>; -- resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; -- reset-names = "phy", "apb"; -- rockchip,pipe-grf = <&php_grf>; -- rockchip,pipe-phy-grf = <&pipe_phy0_grf>; -- status = "disabled"; -- }; -- -- combphy2_psu: phy@fee20000 { -- compatible = "rockchip,rk3588-naneng-combphy"; -- reg = <0x0 0xfee20000 0x0 0x100>; -- clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, -- <&cru PCLK_PHP_ROOT>; -- clock-names = "ref", "apb", "pipe"; -- assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; -- assigned-clock-rates = <100000000>; -- #phy-cells = <1>; -- resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; -- reset-names = "phy", "apb"; -- rockchip,pipe-grf = <&php_grf>; -- rockchip,pipe-phy-grf = <&pipe_phy2_grf>; -- status = "disabled"; -- }; -- -- system_sram2: sram@ff001000 { -- compatible = "mmio-sram"; -- reg = <0x0 0xff001000 0x0 0xef000>; -- ranges = <0x0 0x0 0xff001000 0xef000>; -- #address-cells = <1>; -- #size-cells = <1>; -- }; -- -- pinctrl: pinctrl { -- compatible = "rockchip,rk3588-pinctrl"; -- ranges; -- rockchip,grf = <&ioc>; -- #address-cells = <2>; -- #size-cells = <2>; -- -- gpio0: gpio@fd8a0000 { -- compatible = "rockchip,gpio-bank"; -- reg = <0x0 0xfd8a0000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; -- gpio-controller; -- gpio-ranges = <&pinctrl 0 0 32>; -- interrupt-controller; -- #gpio-cells = <2>; -- #interrupt-cells = <2>; -- }; -- -- gpio1: gpio@fec20000 { -- compatible = "rockchip,gpio-bank"; -- reg = <0x0 0xfec20000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; -- gpio-controller; -- gpio-ranges = <&pinctrl 0 32 32>; -- interrupt-controller; -- #gpio-cells = <2>; -- #interrupt-cells = <2>; -- }; -- -- gpio2: gpio@fec30000 { -- compatible = "rockchip,gpio-bank"; -- reg = <0x0 0xfec30000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; -- gpio-controller; -- gpio-ranges = <&pinctrl 0 64 32>; -- interrupt-controller; -- #gpio-cells = <2>; -- #interrupt-cells = <2>; -- }; -- -- gpio3: gpio@fec40000 { -- compatible = "rockchip,gpio-bank"; -- reg = <0x0 0xfec40000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; -- gpio-controller; -- gpio-ranges = <&pinctrl 0 96 32>; -- interrupt-controller; -- #gpio-cells = <2>; -- #interrupt-cells = <2>; -- }; -- -- gpio4: gpio@fec50000 { -- compatible = "rockchip,gpio-bank"; -- reg = <0x0 0xfec50000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; -- gpio-controller; -- gpio-ranges = <&pinctrl 0 128 32>; -- interrupt-controller; -- #gpio-cells = <2>; -- #interrupt-cells = <2>; -- }; -- }; --}; -- --#include "rk3588s-pinctrl.dtsi" -+#include "rk3588-base.dtsi" ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi -@@ -0,0 +1,3447 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ */ -+ -+#include -+#include "rockchip-pinconf.dtsi" -+ -+/* -+ * This file is auto generated by pin2dts tool, please keep these code -+ * by adding changes at end of this file. -+ */ -+&pinctrl { -+ auddsm { -+ /omit-if-no-ref/ -+ auddsm_pins: auddsm-pins { -+ rockchip,pins = -+ /* auddsm_ln */ -+ <3 RK_PA1 4 &pcfg_pull_none>, -+ /* auddsm_lp */ -+ <3 RK_PA2 4 &pcfg_pull_none>, -+ /* auddsm_rn */ -+ <3 RK_PA3 4 &pcfg_pull_none>, -+ /* auddsm_rp */ -+ <3 RK_PA4 4 &pcfg_pull_none>; -+ }; -+ }; -+ -+ bt1120 { -+ /omit-if-no-ref/ -+ bt1120_pins: bt1120-pins { -+ rockchip,pins = -+ /* bt1120_clkout */ -+ <4 RK_PB0 2 &pcfg_pull_none>, -+ /* bt1120_d0 */ -+ <4 RK_PA0 2 &pcfg_pull_none>, -+ /* bt1120_d1 */ -+ <4 RK_PA1 2 &pcfg_pull_none>, -+ /* bt1120_d2 */ -+ <4 RK_PA2 2 &pcfg_pull_none>, -+ /* bt1120_d3 */ -+ <4 RK_PA3 2 &pcfg_pull_none>, -+ /* bt1120_d4 */ -+ <4 RK_PA4 2 &pcfg_pull_none>, -+ /* bt1120_d5 */ -+ <4 RK_PA5 2 &pcfg_pull_none>, -+ /* bt1120_d6 */ -+ <4 RK_PA6 2 &pcfg_pull_none>, -+ /* bt1120_d7 */ -+ <4 RK_PA7 2 &pcfg_pull_none>, -+ /* bt1120_d8 */ -+ <4 RK_PB2 2 &pcfg_pull_none>, -+ /* bt1120_d9 */ -+ <4 RK_PB3 2 &pcfg_pull_none>, -+ /* bt1120_d10 */ -+ <4 RK_PB4 2 &pcfg_pull_none>, -+ /* bt1120_d11 */ -+ <4 RK_PB5 2 &pcfg_pull_none>, -+ /* bt1120_d12 */ -+ <4 RK_PB6 2 &pcfg_pull_none>, -+ /* bt1120_d13 */ -+ <4 RK_PB7 2 &pcfg_pull_none>, -+ /* bt1120_d14 */ -+ <4 RK_PC0 2 &pcfg_pull_none>, -+ /* bt1120_d15 */ -+ <4 RK_PC1 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ can0 { -+ /omit-if-no-ref/ -+ can0m0_pins: can0m0-pins { -+ rockchip,pins = -+ /* can0_rx_m0 */ -+ <0 RK_PC0 11 &pcfg_pull_none>, -+ /* can0_tx_m0 */ -+ <0 RK_PB7 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ can0m1_pins: can0m1-pins { -+ rockchip,pins = -+ /* can0_rx_m1 */ -+ <4 RK_PD5 9 &pcfg_pull_none>, -+ /* can0_tx_m1 */ -+ <4 RK_PD4 9 &pcfg_pull_none>; -+ }; -+ }; -+ -+ can1 { -+ /omit-if-no-ref/ -+ can1m0_pins: can1m0-pins { -+ rockchip,pins = -+ /* can1_rx_m0 */ -+ <3 RK_PB5 9 &pcfg_pull_none>, -+ /* can1_tx_m0 */ -+ <3 RK_PB6 9 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ can1m1_pins: can1m1-pins { -+ rockchip,pins = -+ /* can1_rx_m1 */ -+ <4 RK_PB2 12 &pcfg_pull_none>, -+ /* can1_tx_m1 */ -+ <4 RK_PB3 12 &pcfg_pull_none>; -+ }; -+ }; -+ -+ can2 { -+ /omit-if-no-ref/ -+ can2m0_pins: can2m0-pins { -+ rockchip,pins = -+ /* can2_rx_m0 */ -+ <3 RK_PC4 9 &pcfg_pull_none>, -+ /* can2_tx_m0 */ -+ <3 RK_PC5 9 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ can2m1_pins: can2m1-pins { -+ rockchip,pins = -+ /* can2_rx_m1 */ -+ <0 RK_PD4 10 &pcfg_pull_none>, -+ /* can2_tx_m1 */ -+ <0 RK_PD5 10 &pcfg_pull_none>; -+ }; -+ }; -+ -+ cif { -+ /omit-if-no-ref/ -+ cif_clk: cif-clk { -+ rockchip,pins = -+ /* cif_clkout */ -+ <4 RK_PB4 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ cif_dvp_clk: cif-dvp-clk { -+ rockchip,pins = -+ /* cif_clkin */ -+ <4 RK_PB0 1 &pcfg_pull_none>, -+ /* cif_href */ -+ <4 RK_PB2 1 &pcfg_pull_none>, -+ /* cif_vsync */ -+ <4 RK_PB3 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ cif_dvp_bus16: cif-dvp-bus16 { -+ rockchip,pins = -+ /* cif_d8 */ -+ <3 RK_PC4 1 &pcfg_pull_none>, -+ /* cif_d9 */ -+ <3 RK_PC5 1 &pcfg_pull_none>, -+ /* cif_d10 */ -+ <3 RK_PC6 1 &pcfg_pull_none>, -+ /* cif_d11 */ -+ <3 RK_PC7 1 &pcfg_pull_none>, -+ /* cif_d12 */ -+ <3 RK_PD0 1 &pcfg_pull_none>, -+ /* cif_d13 */ -+ <3 RK_PD1 1 &pcfg_pull_none>, -+ /* cif_d14 */ -+ <3 RK_PD2 1 &pcfg_pull_none>, -+ /* cif_d15 */ -+ <3 RK_PD3 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ cif_dvp_bus8: cif-dvp-bus8 { -+ rockchip,pins = -+ /* cif_d0 */ -+ <4 RK_PA0 1 &pcfg_pull_none>, -+ /* cif_d1 */ -+ <4 RK_PA1 1 &pcfg_pull_none>, -+ /* cif_d2 */ -+ <4 RK_PA2 1 &pcfg_pull_none>, -+ /* cif_d3 */ -+ <4 RK_PA3 1 &pcfg_pull_none>, -+ /* cif_d4 */ -+ <4 RK_PA4 1 &pcfg_pull_none>, -+ /* cif_d5 */ -+ <4 RK_PA5 1 &pcfg_pull_none>, -+ /* cif_d6 */ -+ <4 RK_PA6 1 &pcfg_pull_none>, -+ /* cif_d7 */ -+ <4 RK_PA7 1 &pcfg_pull_none>; -+ }; -+ }; -+ -+ clk32k { -+ /omit-if-no-ref/ -+ clk32k_in: clk32k-in { -+ rockchip,pins = -+ /* clk32k_in */ -+ <0 RK_PB2 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ clk32k_out0: clk32k-out0 { -+ rockchip,pins = -+ /* clk32k_out0 */ -+ <0 RK_PB2 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ cpu { -+ /omit-if-no-ref/ -+ cpu_pins: cpu-pins { -+ rockchip,pins = -+ /* cpu_big0_avs */ -+ <0 RK_PD1 2 &pcfg_pull_none>, -+ /* cpu_big1_avs */ -+ <0 RK_PD5 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ ddrphych0 { -+ /omit-if-no-ref/ -+ ddrphych0_pins: ddrphych0-pins { -+ rockchip,pins = -+ /* ddrphych0_dtb0 */ -+ <4 RK_PA0 7 &pcfg_pull_none>, -+ /* ddrphych0_dtb1 */ -+ <4 RK_PA1 7 &pcfg_pull_none>, -+ /* ddrphych0_dtb2 */ -+ <4 RK_PA2 7 &pcfg_pull_none>, -+ /* ddrphych0_dtb3 */ -+ <4 RK_PA3 7 &pcfg_pull_none>; -+ }; -+ }; -+ -+ ddrphych1 { -+ /omit-if-no-ref/ -+ ddrphych1_pins: ddrphych1-pins { -+ rockchip,pins = -+ /* ddrphych1_dtb0 */ -+ <4 RK_PA4 7 &pcfg_pull_none>, -+ /* ddrphych1_dtb1 */ -+ <4 RK_PA5 7 &pcfg_pull_none>, -+ /* ddrphych1_dtb2 */ -+ <4 RK_PA6 7 &pcfg_pull_none>, -+ /* ddrphych1_dtb3 */ -+ <4 RK_PA7 7 &pcfg_pull_none>; -+ }; -+ }; -+ -+ ddrphych2 { -+ /omit-if-no-ref/ -+ ddrphych2_pins: ddrphych2-pins { -+ rockchip,pins = -+ /* ddrphych2_dtb0 */ -+ <4 RK_PB0 7 &pcfg_pull_none>, -+ /* ddrphych2_dtb1 */ -+ <4 RK_PB1 7 &pcfg_pull_none>, -+ /* ddrphych2_dtb2 */ -+ <4 RK_PB2 7 &pcfg_pull_none>, -+ /* ddrphych2_dtb3 */ -+ <4 RK_PB3 7 &pcfg_pull_none>; -+ }; -+ }; -+ -+ ddrphych3 { -+ /omit-if-no-ref/ -+ ddrphych3_pins: ddrphych3-pins { -+ rockchip,pins = -+ /* ddrphych3_dtb0 */ -+ <4 RK_PB4 7 &pcfg_pull_none>, -+ /* ddrphych3_dtb1 */ -+ <4 RK_PB5 7 &pcfg_pull_none>, -+ /* ddrphych3_dtb2 */ -+ <4 RK_PB6 7 &pcfg_pull_none>, -+ /* ddrphych3_dtb3 */ -+ <4 RK_PB7 7 &pcfg_pull_none>; -+ }; -+ }; -+ -+ dp0 { -+ /omit-if-no-ref/ -+ dp0m0_pins: dp0m0-pins { -+ rockchip,pins = -+ /* dp0_hpdin_m0 */ -+ <4 RK_PB4 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ dp0m1_pins: dp0m1-pins { -+ rockchip,pins = -+ /* dp0_hpdin_m1 */ -+ <0 RK_PC4 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ dp0m2_pins: dp0m2-pins { -+ rockchip,pins = -+ /* dp0_hpdin_m2 */ -+ <1 RK_PA0 5 &pcfg_pull_none>; -+ }; -+ }; -+ -+ dp1 { -+ /omit-if-no-ref/ -+ dp1m0_pins: dp1m0-pins { -+ rockchip,pins = -+ /* dp1_hpdin_m0 */ -+ <3 RK_PD5 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ dp1m1_pins: dp1m1-pins { -+ rockchip,pins = -+ /* dp1_hpdin_m1 */ -+ <0 RK_PC5 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ dp1m2_pins: dp1m2-pins { -+ rockchip,pins = -+ /* dp1_hpdin_m2 */ -+ <1 RK_PA1 5 &pcfg_pull_none>; -+ }; -+ }; -+ -+ emmc { -+ /omit-if-no-ref/ -+ emmc_rstnout: emmc-rstnout { -+ rockchip,pins = -+ /* emmc_rstn */ -+ <2 RK_PA3 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ emmc_bus8: emmc-bus8 { -+ rockchip,pins = -+ /* emmc_d0 */ -+ <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, -+ /* emmc_d1 */ -+ <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, -+ /* emmc_d2 */ -+ <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, -+ /* emmc_d3 */ -+ <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, -+ /* emmc_d4 */ -+ <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, -+ /* emmc_d5 */ -+ <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, -+ /* emmc_d6 */ -+ <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, -+ /* emmc_d7 */ -+ <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; -+ }; -+ -+ /omit-if-no-ref/ -+ emmc_clk: emmc-clk { -+ rockchip,pins = -+ /* emmc_clkout */ -+ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; -+ }; -+ -+ /omit-if-no-ref/ -+ emmc_cmd: emmc-cmd { -+ rockchip,pins = -+ /* emmc_cmd */ -+ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; -+ }; -+ -+ /omit-if-no-ref/ -+ emmc_data_strobe: emmc-data-strobe { -+ rockchip,pins = -+ /* emmc_data_strobe */ -+ <2 RK_PA2 1 &pcfg_pull_down>; -+ }; -+ }; -+ -+ eth1 { -+ /omit-if-no-ref/ -+ eth1_pins: eth1-pins { -+ rockchip,pins = -+ /* eth1_refclko_25m */ -+ <3 RK_PA6 1 &pcfg_pull_none>; -+ }; -+ }; -+ -+ fspi { -+ /omit-if-no-ref/ -+ fspim0_pins: fspim0-pins { -+ rockchip,pins = -+ /* fspi_clk_m0 */ -+ <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>, -+ /* fspi_cs0n_m0 */ -+ <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>, -+ /* fspi_d0_m0 */ -+ <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>, -+ /* fspi_d1_m0 */ -+ <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>, -+ /* fspi_d2_m0 */ -+ <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>, -+ /* fspi_d3_m0 */ -+ <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>; -+ }; -+ -+ /omit-if-no-ref/ -+ fspim0_cs1: fspim0-cs1 { -+ rockchip,pins = -+ /* fspi_cs1n_m0 */ -+ <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; -+ }; -+ -+ /omit-if-no-ref/ -+ fspim2_pins: fspim2-pins { -+ rockchip,pins = -+ /* fspi_clk_m2 */ -+ <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>, -+ /* fspi_cs0n_m2 */ -+ <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>, -+ /* fspi_d0_m2 */ -+ <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>, -+ /* fspi_d1_m2 */ -+ <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, -+ /* fspi_d2_m2 */ -+ <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, -+ /* fspi_d3_m2 */ -+ <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>; -+ }; -+ -+ /omit-if-no-ref/ -+ fspim2_cs1: fspim2-cs1 { -+ rockchip,pins = -+ /* fspi_cs1n_m2 */ -+ <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>; -+ }; -+ }; -+ -+ gmac1 { -+ /omit-if-no-ref/ -+ gmac1_miim: gmac1-miim { -+ rockchip,pins = -+ /* gmac1_mdc */ -+ <3 RK_PC2 1 &pcfg_pull_none>, -+ /* gmac1_mdio */ -+ <3 RK_PC3 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac1_clkinout: gmac1-clkinout { -+ rockchip,pins = -+ /* gmac1_mclkinout */ -+ <3 RK_PB6 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac1_rx_bus2: gmac1-rx-bus2 { -+ rockchip,pins = -+ /* gmac1_rxd0 */ -+ <3 RK_PA7 1 &pcfg_pull_none>, -+ /* gmac1_rxd1 */ -+ <3 RK_PB0 1 &pcfg_pull_none>, -+ /* gmac1_rxdv_crs */ -+ <3 RK_PB1 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac1_tx_bus2: gmac1-tx-bus2 { -+ rockchip,pins = -+ /* gmac1_txd0 */ -+ <3 RK_PB3 1 &pcfg_pull_none>, -+ /* gmac1_txd1 */ -+ <3 RK_PB4 1 &pcfg_pull_none>, -+ /* gmac1_txen */ -+ <3 RK_PB5 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac1_rgmii_clk: gmac1-rgmii-clk { -+ rockchip,pins = -+ /* gmac1_rxclk */ -+ <3 RK_PA5 1 &pcfg_pull_none>, -+ /* gmac1_txclk */ -+ <3 RK_PA4 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac1_rgmii_bus: gmac1-rgmii-bus { -+ rockchip,pins = -+ /* gmac1_rxd2 */ -+ <3 RK_PA2 1 &pcfg_pull_none>, -+ /* gmac1_rxd3 */ -+ <3 RK_PA3 1 &pcfg_pull_none>, -+ /* gmac1_txd2 */ -+ <3 RK_PA0 1 &pcfg_pull_none>, -+ /* gmac1_txd3 */ -+ <3 RK_PA1 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac1_ppsclk: gmac1-ppsclk { -+ rockchip,pins = -+ /* gmac1_ppsclk */ -+ <3 RK_PC1 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac1_ppstrig: gmac1-ppstrig { -+ rockchip,pins = -+ /* gmac1_ppstrig */ -+ <3 RK_PC0 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { -+ rockchip,pins = -+ /* gmac1_ptp_ref_clk */ -+ <3 RK_PB7 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac1_txer: gmac1-txer { -+ rockchip,pins = -+ /* gmac1_txer */ -+ <3 RK_PB2 1 &pcfg_pull_none>; -+ }; -+ }; -+ -+ gpu { -+ /omit-if-no-ref/ -+ gpu_pins: gpu-pins { -+ rockchip,pins = -+ /* gpu_avs */ -+ <0 RK_PC5 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ hdmi { -+ /omit-if-no-ref/ -+ hdmim0_rx_cec: hdmim0-rx-cec { -+ rockchip,pins = -+ /* hdmim0_rx_cec */ -+ <4 RK_PB5 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim0_rx_hpdin: hdmim0-rx-hpdin { -+ rockchip,pins = -+ /* hdmim0_rx_hpdin */ -+ <4 RK_PB6 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim0_rx_scl: hdmim0-rx-scl { -+ rockchip,pins = -+ /* hdmim0_rx_scl */ -+ <0 RK_PD2 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim0_rx_sda: hdmim0-rx-sda { -+ rockchip,pins = -+ /* hdmim0_rx_sda */ -+ <0 RK_PD1 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim0_tx0_cec: hdmim0-tx0-cec { -+ rockchip,pins = -+ /* hdmim0_tx0_cec */ -+ <4 RK_PC1 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim0_tx0_hpd: hdmim0-tx0-hpd { -+ rockchip,pins = -+ /* hdmim0_tx0_hpd */ -+ <1 RK_PA5 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim0_tx0_scl: hdmim0-tx0-scl { -+ rockchip,pins = -+ /* hdmim0_tx0_scl */ -+ <4 RK_PB7 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim0_tx0_sda: hdmim0-tx0-sda { -+ rockchip,pins = -+ /* hdmim0_tx0_sda */ -+ <4 RK_PC0 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim0_tx1_hpd: hdmim0-tx1-hpd { -+ rockchip,pins = -+ /* hdmim0_tx1_hpd */ -+ <1 RK_PA6 5 &pcfg_pull_none>; -+ }; -+ /omit-if-no-ref/ -+ hdmim1_rx_cec: hdmim1-rx-cec { -+ rockchip,pins = -+ /* hdmim1_rx_cec */ -+ <3 RK_PD1 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_rx_hpdin: hdmim1-rx-hpdin { -+ rockchip,pins = -+ /* hdmim1_rx_hpdin */ -+ <3 RK_PD4 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_rx_scl: hdmim1-rx-scl { -+ rockchip,pins = -+ /* hdmim1_rx_scl */ -+ <3 RK_PD2 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_rx_sda: hdmim1-rx-sda { -+ rockchip,pins = -+ /* hdmim1_rx_sda */ -+ <3 RK_PD3 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_tx0_cec: hdmim1-tx0-cec { -+ rockchip,pins = -+ /* hdmim1_tx0_cec */ -+ <0 RK_PD1 13 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_tx0_hpd: hdmim1-tx0-hpd { -+ rockchip,pins = -+ /* hdmim1_tx0_hpd */ -+ <3 RK_PD4 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_tx0_scl: hdmim1-tx0-scl { -+ rockchip,pins = -+ /* hdmim1_tx0_scl */ -+ <0 RK_PD5 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_tx0_sda: hdmim1-tx0-sda { -+ rockchip,pins = -+ /* hdmim1_tx0_sda */ -+ <0 RK_PD4 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_tx1_cec: hdmim1-tx1-cec { -+ rockchip,pins = -+ /* hdmim1_tx1_cec */ -+ <0 RK_PD2 13 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_tx1_hpd: hdmim1-tx1-hpd { -+ rockchip,pins = -+ /* hdmim1_tx1_hpd */ -+ <3 RK_PB7 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_tx1_scl: hdmim1-tx1-scl { -+ rockchip,pins = -+ /* hdmim1_tx1_scl */ -+ <3 RK_PC6 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_tx1_sda: hdmim1-tx1-sda { -+ rockchip,pins = -+ /* hdmim1_tx1_sda */ -+ <3 RK_PC5 5 &pcfg_pull_none>; -+ }; -+ /omit-if-no-ref/ -+ hdmim2_rx_cec: hdmim2-rx-cec { -+ rockchip,pins = -+ /* hdmim2_rx_cec */ -+ <1 RK_PB7 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim2_rx_hpdin: hdmim2-rx-hpdin { -+ rockchip,pins = -+ /* hdmim2_rx_hpdin */ -+ <1 RK_PB6 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim2_rx_scl: hdmim2-rx-scl { -+ rockchip,pins = -+ /* hdmim2_rx_scl */ -+ <1 RK_PD6 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim2_rx_sda: hdmim2-rx-sda { -+ rockchip,pins = -+ /* hdmim2_rx_sda */ -+ <1 RK_PD7 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim2_tx0_scl: hdmim2-tx0-scl { -+ rockchip,pins = -+ /* hdmim2_tx0_scl */ -+ <3 RK_PC7 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim2_tx0_sda: hdmim2-tx0-sda { -+ rockchip,pins = -+ /* hdmim2_tx0_sda */ -+ <3 RK_PD0 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim2_tx1_cec: hdmim2-tx1-cec { -+ rockchip,pins = -+ /* hdmim2_tx1_cec */ -+ <3 RK_PC4 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim2_tx1_scl: hdmim2-tx1-scl { -+ rockchip,pins = -+ /* hdmim2_tx1_scl */ -+ <1 RK_PA4 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim2_tx1_sda: hdmim2-tx1-sda { -+ rockchip,pins = -+ /* hdmim2_tx1_sda */ -+ <1 RK_PA3 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmi_debug0: hdmi-debug0 { -+ rockchip,pins = -+ /* hdmi_debug0 */ -+ <1 RK_PA7 7 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmi_debug1: hdmi-debug1 { -+ rockchip,pins = -+ /* hdmi_debug1 */ -+ <1 RK_PB0 7 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmi_debug2: hdmi-debug2 { -+ rockchip,pins = -+ /* hdmi_debug2 */ -+ <1 RK_PB1 7 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmi_debug3: hdmi-debug3 { -+ rockchip,pins = -+ /* hdmi_debug3 */ -+ <1 RK_PB2 7 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmi_debug4: hdmi-debug4 { -+ rockchip,pins = -+ /* hdmi_debug4 */ -+ <1 RK_PB3 7 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmi_debug5: hdmi-debug5 { -+ rockchip,pins = -+ /* hdmi_debug5 */ -+ <1 RK_PB4 7 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmi_debug6: hdmi-debug6 { -+ rockchip,pins = -+ /* hdmi_debug6 */ -+ <1 RK_PA0 7 &pcfg_pull_none>; -+ }; -+ }; -+ -+ i2c0 { -+ /omit-if-no-ref/ -+ i2c0m0_xfer: i2c0m0-xfer { -+ rockchip,pins = -+ /* i2c0_scl_m0 */ -+ <0 RK_PB3 2 &pcfg_pull_none_smt>, -+ /* i2c0_sda_m0 */ -+ <0 RK_PA6 2 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c0m2_xfer: i2c0m2-xfer { -+ rockchip,pins = -+ /* i2c0_scl_m2 */ -+ <0 RK_PD1 3 &pcfg_pull_none_smt>, -+ /* i2c0_sda_m2 */ -+ <0 RK_PD2 3 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c1 { -+ /omit-if-no-ref/ -+ i2c1m0_xfer: i2c1m0-xfer { -+ rockchip,pins = -+ /* i2c1_scl_m0 */ -+ <0 RK_PB5 9 &pcfg_pull_none_smt>, -+ /* i2c1_sda_m0 */ -+ <0 RK_PB6 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c1m1_xfer: i2c1m1-xfer { -+ rockchip,pins = -+ /* i2c1_scl_m1 */ -+ <0 RK_PB0 2 &pcfg_pull_none_smt>, -+ /* i2c1_sda_m1 */ -+ <0 RK_PB1 2 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c1m2_xfer: i2c1m2-xfer { -+ rockchip,pins = -+ /* i2c1_scl_m2 */ -+ <0 RK_PD4 9 &pcfg_pull_none_smt>, -+ /* i2c1_sda_m2 */ -+ <0 RK_PD5 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c1m3_xfer: i2c1m3-xfer { -+ rockchip,pins = -+ /* i2c1_scl_m3 */ -+ <2 RK_PD4 9 &pcfg_pull_none_smt>, -+ /* i2c1_sda_m3 */ -+ <2 RK_PD5 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c1m4_xfer: i2c1m4-xfer { -+ rockchip,pins = -+ /* i2c1_scl_m4 */ -+ <1 RK_PD2 9 &pcfg_pull_none_smt>, -+ /* i2c1_sda_m4 */ -+ <1 RK_PD3 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c2 { -+ /omit-if-no-ref/ -+ i2c2m0_xfer: i2c2m0-xfer { -+ rockchip,pins = -+ /* i2c2_scl_m0 */ -+ <0 RK_PB7 9 &pcfg_pull_none_smt>, -+ /* i2c2_sda_m0 */ -+ <0 RK_PC0 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c2m2_xfer: i2c2m2-xfer { -+ rockchip,pins = -+ /* i2c2_scl_m2 */ -+ <2 RK_PA3 9 &pcfg_pull_none_smt>, -+ /* i2c2_sda_m2 */ -+ <2 RK_PA2 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c2m3_xfer: i2c2m3-xfer { -+ rockchip,pins = -+ /* i2c2_scl_m3 */ -+ <1 RK_PC5 9 &pcfg_pull_none_smt>, -+ /* i2c2_sda_m3 */ -+ <1 RK_PC4 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c2m4_xfer: i2c2m4-xfer { -+ rockchip,pins = -+ /* i2c2_scl_m4 */ -+ <1 RK_PA1 9 &pcfg_pull_none_smt>, -+ /* i2c2_sda_m4 */ -+ <1 RK_PA0 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c3 { -+ /omit-if-no-ref/ -+ i2c3m0_xfer: i2c3m0-xfer { -+ rockchip,pins = -+ /* i2c3_scl_m0 */ -+ <1 RK_PC1 9 &pcfg_pull_none_smt>, -+ /* i2c3_sda_m0 */ -+ <1 RK_PC0 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c3m1_xfer: i2c3m1-xfer { -+ rockchip,pins = -+ /* i2c3_scl_m1 */ -+ <3 RK_PB7 9 &pcfg_pull_none_smt>, -+ /* i2c3_sda_m1 */ -+ <3 RK_PC0 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c3m2_xfer: i2c3m2-xfer { -+ rockchip,pins = -+ /* i2c3_scl_m2 */ -+ <4 RK_PA4 9 &pcfg_pull_none_smt>, -+ /* i2c3_sda_m2 */ -+ <4 RK_PA5 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c3m4_xfer: i2c3m4-xfer { -+ rockchip,pins = -+ /* i2c3_scl_m4 */ -+ <4 RK_PD0 9 &pcfg_pull_none_smt>, -+ /* i2c3_sda_m4 */ -+ <4 RK_PD1 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c4 { -+ /omit-if-no-ref/ -+ i2c4m0_xfer: i2c4m0-xfer { -+ rockchip,pins = -+ /* i2c4_scl_m0 */ -+ <3 RK_PA6 9 &pcfg_pull_none_smt>, -+ /* i2c4_sda_m0 */ -+ <3 RK_PA5 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c4m2_xfer: i2c4m2-xfer { -+ rockchip,pins = -+ /* i2c4_scl_m2 */ -+ <0 RK_PC5 9 &pcfg_pull_none_smt>, -+ /* i2c4_sda_m2 */ -+ <0 RK_PC4 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c4m3_xfer: i2c4m3-xfer { -+ rockchip,pins = -+ /* i2c4_scl_m3 */ -+ <1 RK_PA3 9 &pcfg_pull_none_smt>, -+ /* i2c4_sda_m3 */ -+ <1 RK_PA2 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c4m4_xfer: i2c4m4-xfer { -+ rockchip,pins = -+ /* i2c4_scl_m4 */ -+ <1 RK_PC7 9 &pcfg_pull_none_smt>, -+ /* i2c4_sda_m4 */ -+ <1 RK_PC6 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c5 { -+ /omit-if-no-ref/ -+ i2c5m0_xfer: i2c5m0-xfer { -+ rockchip,pins = -+ /* i2c5_scl_m0 */ -+ <3 RK_PC7 9 &pcfg_pull_none_smt>, -+ /* i2c5_sda_m0 */ -+ <3 RK_PD0 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c5m1_xfer: i2c5m1-xfer { -+ rockchip,pins = -+ /* i2c5_scl_m1 */ -+ <4 RK_PB6 9 &pcfg_pull_none_smt>, -+ /* i2c5_sda_m1 */ -+ <4 RK_PB7 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c5m2_xfer: i2c5m2-xfer { -+ rockchip,pins = -+ /* i2c5_scl_m2 */ -+ <4 RK_PA6 9 &pcfg_pull_none_smt>, -+ /* i2c5_sda_m2 */ -+ <4 RK_PA7 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c5m3_xfer: i2c5m3-xfer { -+ rockchip,pins = -+ /* i2c5_scl_m3 */ -+ <1 RK_PB6 9 &pcfg_pull_none_smt>, -+ /* i2c5_sda_m3 */ -+ <1 RK_PB7 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c6 { -+ /omit-if-no-ref/ -+ i2c6m0_xfer: i2c6m0-xfer { -+ rockchip,pins = -+ /* i2c6_scl_m0 */ -+ <0 RK_PD0 9 &pcfg_pull_none_smt>, -+ /* i2c6_sda_m0 */ -+ <0 RK_PC7 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c6m1_xfer: i2c6m1-xfer { -+ rockchip,pins = -+ /* i2c6_scl_m1 */ -+ <1 RK_PC3 9 &pcfg_pull_none_smt>, -+ /* i2c6_sda_m1 */ -+ <1 RK_PC2 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c6m3_xfer: i2c6m3-xfer { -+ rockchip,pins = -+ /* i2c6_scl_m3 */ -+ <4 RK_PB1 9 &pcfg_pull_none_smt>, -+ /* i2c6_sda_m3 */ -+ <4 RK_PB0 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c6m4_xfer: i2c6m4-xfer { -+ rockchip,pins = -+ /* i2c6_scl_m4 */ -+ <3 RK_PA1 9 &pcfg_pull_none_smt>, -+ /* i2c6_sda_m4 */ -+ <3 RK_PA0 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c7 { -+ /omit-if-no-ref/ -+ i2c7m0_xfer: i2c7m0-xfer { -+ rockchip,pins = -+ /* i2c7_scl_m0 */ -+ <1 RK_PD0 9 &pcfg_pull_none_smt>, -+ /* i2c7_sda_m0 */ -+ <1 RK_PD1 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c7m2_xfer: i2c7m2-xfer { -+ rockchip,pins = -+ /* i2c7_scl_m2 */ -+ <3 RK_PD2 9 &pcfg_pull_none_smt>, -+ /* i2c7_sda_m2 */ -+ <3 RK_PD3 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c7m3_xfer: i2c7m3-xfer { -+ rockchip,pins = -+ /* i2c7_scl_m3 */ -+ <4 RK_PB2 9 &pcfg_pull_none_smt>, -+ /* i2c7_sda_m3 */ -+ <4 RK_PB3 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c8 { -+ /omit-if-no-ref/ -+ i2c8m0_xfer: i2c8m0-xfer { -+ rockchip,pins = -+ /* i2c8_scl_m0 */ -+ <4 RK_PD2 9 &pcfg_pull_none_smt>, -+ /* i2c8_sda_m0 */ -+ <4 RK_PD3 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c8m2_xfer: i2c8m2-xfer { -+ rockchip,pins = -+ /* i2c8_scl_m2 */ -+ <1 RK_PD6 9 &pcfg_pull_none_smt>, -+ /* i2c8_sda_m2 */ -+ <1 RK_PD7 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c8m3_xfer: i2c8m3-xfer { -+ rockchip,pins = -+ /* i2c8_scl_m3 */ -+ <4 RK_PC0 9 &pcfg_pull_none_smt>, -+ /* i2c8_sda_m3 */ -+ <4 RK_PC1 9 &pcfg_pull_none_smt>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c8m4_xfer: i2c8m4-xfer { -+ rockchip,pins = -+ /* i2c8_scl_m4 */ -+ <3 RK_PC2 9 &pcfg_pull_none_smt>, -+ /* i2c8_sda_m4 */ -+ <3 RK_PC3 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2s0 { -+ /omit-if-no-ref/ -+ i2s0_lrck: i2s0-lrck { -+ rockchip,pins = -+ /* i2s0_lrck */ -+ <1 RK_PC5 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s0_mclk: i2s0-mclk { -+ rockchip,pins = -+ /* i2s0_mclk */ -+ <1 RK_PC2 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s0_sclk: i2s0-sclk { -+ rockchip,pins = -+ /* i2s0_sclk */ -+ <1 RK_PC3 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s0_sdi0: i2s0-sdi0 { -+ rockchip,pins = -+ /* i2s0_sdi0 */ -+ <1 RK_PD4 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s0_sdi1: i2s0-sdi1 { -+ rockchip,pins = -+ /* i2s0_sdi1 */ -+ <1 RK_PD3 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s0_sdi2: i2s0-sdi2 { -+ rockchip,pins = -+ /* i2s0_sdi2 */ -+ <1 RK_PD2 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s0_sdi3: i2s0-sdi3 { -+ rockchip,pins = -+ /* i2s0_sdi3 */ -+ <1 RK_PD1 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s0_sdo0: i2s0-sdo0 { -+ rockchip,pins = -+ /* i2s0_sdo0 */ -+ <1 RK_PC7 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s0_sdo1: i2s0-sdo1 { -+ rockchip,pins = -+ /* i2s0_sdo1 */ -+ <1 RK_PD0 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s0_sdo2: i2s0-sdo2 { -+ rockchip,pins = -+ /* i2s0_sdo2 */ -+ <1 RK_PD1 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s0_sdo3: i2s0-sdo3 { -+ rockchip,pins = -+ /* i2s0_sdo3 */ -+ <1 RK_PD2 1 &pcfg_pull_none>; -+ }; -+ }; -+ -+ i2s1 { -+ /omit-if-no-ref/ -+ i2s1m0_lrck: i2s1m0-lrck { -+ rockchip,pins = -+ /* i2s1m0_lrck */ -+ <4 RK_PA2 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m0_mclk: i2s1m0-mclk { -+ rockchip,pins = -+ /* i2s1m0_mclk */ -+ <4 RK_PA0 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m0_sclk: i2s1m0-sclk { -+ rockchip,pins = -+ /* i2s1m0_sclk */ -+ <4 RK_PA1 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m0_sdi0: i2s1m0-sdi0 { -+ rockchip,pins = -+ /* i2s1m0_sdi0 */ -+ <4 RK_PA5 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m0_sdi1: i2s1m0-sdi1 { -+ rockchip,pins = -+ /* i2s1m0_sdi1 */ -+ <4 RK_PA6 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m0_sdi2: i2s1m0-sdi2 { -+ rockchip,pins = -+ /* i2s1m0_sdi2 */ -+ <4 RK_PA7 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m0_sdi3: i2s1m0-sdi3 { -+ rockchip,pins = -+ /* i2s1m0_sdi3 */ -+ <4 RK_PB0 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m0_sdo0: i2s1m0-sdo0 { -+ rockchip,pins = -+ /* i2s1m0_sdo0 */ -+ <4 RK_PB1 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m0_sdo1: i2s1m0-sdo1 { -+ rockchip,pins = -+ /* i2s1m0_sdo1 */ -+ <4 RK_PB2 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m0_sdo2: i2s1m0-sdo2 { -+ rockchip,pins = -+ /* i2s1m0_sdo2 */ -+ <4 RK_PB3 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m0_sdo3: i2s1m0-sdo3 { -+ rockchip,pins = -+ /* i2s1m0_sdo3 */ -+ <4 RK_PB4 3 &pcfg_pull_none>; -+ }; -+ /omit-if-no-ref/ -+ i2s1m1_lrck: i2s1m1-lrck { -+ rockchip,pins = -+ /* i2s1m1_lrck */ -+ <0 RK_PB7 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m1_mclk: i2s1m1-mclk { -+ rockchip,pins = -+ /* i2s1m1_mclk */ -+ <0 RK_PB5 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m1_sclk: i2s1m1-sclk { -+ rockchip,pins = -+ /* i2s1m1_sclk */ -+ <0 RK_PB6 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m1_sdi0: i2s1m1-sdi0 { -+ rockchip,pins = -+ /* i2s1m1_sdi0 */ -+ <0 RK_PC5 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m1_sdi1: i2s1m1-sdi1 { -+ rockchip,pins = -+ /* i2s1m1_sdi1 */ -+ <0 RK_PC6 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m1_sdi2: i2s1m1-sdi2 { -+ rockchip,pins = -+ /* i2s1m1_sdi2 */ -+ <0 RK_PC7 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m1_sdi3: i2s1m1-sdi3 { -+ rockchip,pins = -+ /* i2s1m1_sdi3 */ -+ <0 RK_PD0 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m1_sdo0: i2s1m1-sdo0 { -+ rockchip,pins = -+ /* i2s1m1_sdo0 */ -+ <0 RK_PD1 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m1_sdo1: i2s1m1-sdo1 { -+ rockchip,pins = -+ /* i2s1m1_sdo1 */ -+ <0 RK_PD2 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m1_sdo2: i2s1m1-sdo2 { -+ rockchip,pins = -+ /* i2s1m1_sdo2 */ -+ <0 RK_PD4 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s1m1_sdo3: i2s1m1-sdo3 { -+ rockchip,pins = -+ /* i2s1m1_sdo3 */ -+ <0 RK_PD5 1 &pcfg_pull_none>; -+ }; -+ }; -+ -+ i2s2 { -+ /omit-if-no-ref/ -+ i2s2m0_lrck: i2s2m0-lrck { -+ rockchip,pins = -+ /* i2s2m0_lrck */ -+ <2 RK_PC0 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m0_mclk: i2s2m0-mclk { -+ rockchip,pins = -+ /* i2s2m0_mclk */ -+ <2 RK_PB6 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m0_sclk: i2s2m0-sclk { -+ rockchip,pins = -+ /* i2s2m0_sclk */ -+ <2 RK_PB7 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m0_sdi: i2s2m0-sdi { -+ rockchip,pins = -+ /* i2s2m0_sdi */ -+ <2 RK_PC3 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m0_sdo: i2s2m0-sdo { -+ rockchip,pins = -+ /* i2s2m0_sdo */ -+ <4 RK_PC3 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m1_lrck: i2s2m1-lrck { -+ rockchip,pins = -+ /* i2s2m1_lrck */ -+ <3 RK_PB6 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m1_mclk: i2s2m1-mclk { -+ rockchip,pins = -+ /* i2s2m1_mclk */ -+ <3 RK_PB4 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m1_sclk: i2s2m1-sclk { -+ rockchip,pins = -+ /* i2s2m1_sclk */ -+ <3 RK_PB5 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m1_sdi: i2s2m1-sdi { -+ rockchip,pins = -+ /* i2s2m1_sdi */ -+ <3 RK_PB2 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m1_sdo: i2s2m1-sdo { -+ rockchip,pins = -+ /* i2s2m1_sdo */ -+ <3 RK_PB3 3 &pcfg_pull_none>; -+ }; -+ }; -+ -+ i2s3 { -+ /omit-if-no-ref/ -+ i2s3_lrck: i2s3-lrck { -+ rockchip,pins = -+ /* i2s3_lrck */ -+ <3 RK_PA2 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s3_mclk: i2s3-mclk { -+ rockchip,pins = -+ /* i2s3_mclk */ -+ <3 RK_PA0 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s3_sclk: i2s3-sclk { -+ rockchip,pins = -+ /* i2s3_sclk */ -+ <3 RK_PA1 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s3_sdi: i2s3-sdi { -+ rockchip,pins = -+ /* i2s3_sdi */ -+ <3 RK_PA4 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s3_sdo: i2s3-sdo { -+ rockchip,pins = -+ /* i2s3_sdo */ -+ <3 RK_PA3 3 &pcfg_pull_none>; -+ }; -+ }; -+ -+ jtag { -+ /omit-if-no-ref/ -+ jtagm0_pins: jtagm0-pins { -+ rockchip,pins = -+ /* jtag_tck_m0 */ -+ <4 RK_PD2 5 &pcfg_pull_none>, -+ /* jtag_tms_m0 */ -+ <4 RK_PD3 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ jtagm1_pins: jtagm1-pins { -+ rockchip,pins = -+ /* jtag_tck_m1 */ -+ <4 RK_PD0 5 &pcfg_pull_none>, -+ /* jtag_tms_m1 */ -+ <4 RK_PD1 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ jtagm2_pins: jtagm2-pins { -+ rockchip,pins = -+ /* jtag_tck_m2 */ -+ <0 RK_PB5 2 &pcfg_pull_none>, -+ /* jtag_tms_m2 */ -+ <0 RK_PB6 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ litcpu { -+ /omit-if-no-ref/ -+ litcpu_pins: litcpu-pins { -+ rockchip,pins = -+ /* litcpu_avs */ -+ <0 RK_PD3 1 &pcfg_pull_none>; -+ }; -+ }; -+ -+ mcu { -+ /omit-if-no-ref/ -+ mcum0_pins: mcum0-pins { -+ rockchip,pins = -+ /* mcu_jtag_tck_m0 */ -+ <4 RK_PD4 5 &pcfg_pull_none>, -+ /* mcu_jtag_tms_m0 */ -+ <4 RK_PD5 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ mcum1_pins: mcum1-pins { -+ rockchip,pins = -+ /* mcu_jtag_tck_m1 */ -+ <3 RK_PD4 6 &pcfg_pull_none>, -+ /* mcu_jtag_tms_m1 */ -+ <3 RK_PD5 6 &pcfg_pull_none>; -+ }; -+ }; -+ -+ mipi { -+ /omit-if-no-ref/ -+ mipim0_camera0_clk: mipim0-camera0-clk { -+ rockchip,pins = -+ /* mipim0_camera0_clk */ -+ <4 RK_PB1 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ mipim0_camera1_clk: mipim0-camera1-clk { -+ rockchip,pins = -+ /* mipim0_camera1_clk */ -+ <1 RK_PB6 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ mipim0_camera2_clk: mipim0-camera2-clk { -+ rockchip,pins = -+ /* mipim0_camera2_clk */ -+ <1 RK_PB7 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ mipim0_camera3_clk: mipim0-camera3-clk { -+ rockchip,pins = -+ /* mipim0_camera3_clk */ -+ <1 RK_PD6 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ mipim0_camera4_clk: mipim0-camera4-clk { -+ rockchip,pins = -+ /* mipim0_camera4_clk */ -+ <1 RK_PD7 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ mipim1_camera0_clk: mipim1-camera0-clk { -+ rockchip,pins = -+ /* mipim1_camera0_clk */ -+ <3 RK_PA5 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ mipim1_camera1_clk: mipim1-camera1-clk { -+ rockchip,pins = -+ /* mipim1_camera1_clk */ -+ <3 RK_PA6 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ mipim1_camera2_clk: mipim1-camera2-clk { -+ rockchip,pins = -+ /* mipim1_camera2_clk */ -+ <3 RK_PA7 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ mipim1_camera3_clk: mipim1-camera3-clk { -+ rockchip,pins = -+ /* mipim1_camera3_clk */ -+ <3 RK_PB0 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ mipim1_camera4_clk: mipim1-camera4-clk { -+ rockchip,pins = -+ /* mipim1_camera4_clk */ -+ <3 RK_PB1 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ mipi_te0: mipi-te0 { -+ rockchip,pins = -+ /* mipi_te0 */ -+ <3 RK_PC2 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ mipi_te1: mipi-te1 { -+ rockchip,pins = -+ /* mipi_te1 */ -+ <3 RK_PC3 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ npu { -+ /omit-if-no-ref/ -+ npu_pins: npu-pins { -+ rockchip,pins = -+ /* npu_avs */ -+ <0 RK_PC6 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie20x1 { -+ /omit-if-no-ref/ -+ pcie20x1m0_pins: pcie20x1m0-pins { -+ rockchip,pins = -+ /* pcie20x1_2_clkreqn_m0 */ -+ <3 RK_PC7 4 &pcfg_pull_none>, -+ /* pcie20x1_2_perstn_m0 */ -+ <3 RK_PD1 4 &pcfg_pull_none>, -+ /* pcie20x1_2_waken_m0 */ -+ <3 RK_PD0 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie20x1m1_pins: pcie20x1m1-pins { -+ rockchip,pins = -+ /* pcie20x1_2_clkreqn_m1 */ -+ <4 RK_PB7 4 &pcfg_pull_none>, -+ /* pcie20x1_2_perstn_m1 */ -+ <4 RK_PC1 4 &pcfg_pull_none>, -+ /* pcie20x1_2_waken_m1 */ -+ <4 RK_PC0 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { -+ rockchip,pins = -+ /* pcie20x1_2_button_rstn */ -+ <4 RK_PB3 4 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie30phy { -+ /omit-if-no-ref/ -+ pcie30phy_pins: pcie30phy-pins { -+ rockchip,pins = -+ /* pcie30phy_dtb0 */ -+ <1 RK_PC4 4 &pcfg_pull_none>, -+ /* pcie30phy_dtb1 */ -+ <1 RK_PD1 4 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie30x1 { -+ /omit-if-no-ref/ -+ pcie30x1m0_pins: pcie30x1m0-pins { -+ rockchip,pins = -+ /* pcie30x1_0_clkreqn_m0 */ -+ <0 RK_PC0 12 &pcfg_pull_none>, -+ /* pcie30x1_0_perstn_m0 */ -+ <0 RK_PC5 12 &pcfg_pull_none>, -+ /* pcie30x1_0_waken_m0 */ -+ <0 RK_PC4 12 &pcfg_pull_none>, -+ /* pcie30x1_1_clkreqn_m0 */ -+ <0 RK_PB5 12 &pcfg_pull_none>, -+ /* pcie30x1_1_perstn_m0 */ -+ <0 RK_PB7 12 &pcfg_pull_none>, -+ /* pcie30x1_1_waken_m0 */ -+ <0 RK_PB6 12 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m1_pins: pcie30x1m1-pins { -+ rockchip,pins = -+ /* pcie30x1_0_clkreqn_m1 */ -+ <4 RK_PA3 4 &pcfg_pull_none>, -+ /* pcie30x1_0_perstn_m1 */ -+ <4 RK_PA5 4 &pcfg_pull_none>, -+ /* pcie30x1_0_waken_m1 */ -+ <4 RK_PA4 4 &pcfg_pull_none>, -+ /* pcie30x1_1_clkreqn_m1 */ -+ <4 RK_PA0 4 &pcfg_pull_none>, -+ /* pcie30x1_1_perstn_m1 */ -+ <4 RK_PA2 4 &pcfg_pull_none>, -+ /* pcie30x1_1_waken_m1 */ -+ <4 RK_PA1 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m2_pins: pcie30x1m2-pins { -+ rockchip,pins = -+ /* pcie30x1_0_clkreqn_m2 */ -+ <1 RK_PB5 4 &pcfg_pull_none>, -+ /* pcie30x1_0_perstn_m2 */ -+ <1 RK_PB4 4 &pcfg_pull_none>, -+ /* pcie30x1_0_waken_m2 */ -+ <1 RK_PB3 4 &pcfg_pull_none>, -+ /* pcie30x1_1_clkreqn_m2 */ -+ <1 RK_PA0 4 &pcfg_pull_none>, -+ /* pcie30x1_1_perstn_m2 */ -+ <1 RK_PA7 4 &pcfg_pull_none>, -+ /* pcie30x1_1_waken_m2 */ -+ <1 RK_PA1 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { -+ rockchip,pins = -+ /* pcie30x1_0_button_rstn */ -+ <4 RK_PB1 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { -+ rockchip,pins = -+ /* pcie30x1_1_button_rstn */ -+ <4 RK_PB2 4 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie30x2 { -+ /omit-if-no-ref/ -+ pcie30x2m0_pins: pcie30x2m0-pins { -+ rockchip,pins = -+ /* pcie30x2_clkreqn_m0 */ -+ <0 RK_PD1 12 &pcfg_pull_none>, -+ /* pcie30x2_perstn_m0 */ -+ <0 RK_PD4 12 &pcfg_pull_none>, -+ /* pcie30x2_waken_m0 */ -+ <0 RK_PD2 12 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x2m1_pins: pcie30x2m1-pins { -+ rockchip,pins = -+ /* pcie30x2_clkreqn_m1 */ -+ <4 RK_PA6 4 &pcfg_pull_none>, -+ /* pcie30x2_perstn_m1 */ -+ <4 RK_PB0 4 &pcfg_pull_none>, -+ /* pcie30x2_waken_m1 */ -+ <4 RK_PA7 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x2m2_pins: pcie30x2m2-pins { -+ rockchip,pins = -+ /* pcie30x2_clkreqn_m2 */ -+ <3 RK_PD2 4 &pcfg_pull_none>, -+ /* pcie30x2_perstn_m2 */ -+ <3 RK_PD4 4 &pcfg_pull_none>, -+ /* pcie30x2_waken_m2 */ -+ <3 RK_PD3 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x2m3_pins: pcie30x2m3-pins { -+ rockchip,pins = -+ /* pcie30x2_clkreqn_m3 */ -+ <1 RK_PD7 4 &pcfg_pull_none>, -+ /* pcie30x2_perstn_m3 */ -+ <1 RK_PB7 4 &pcfg_pull_none>, -+ /* pcie30x2_waken_m3 */ -+ <1 RK_PB6 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x2_button_rstn: pcie30x2-button-rstn { -+ rockchip,pins = -+ /* pcie30x2_button_rstn */ -+ <3 RK_PC1 4 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie30x4 { -+ /omit-if-no-ref/ -+ pcie30x4m0_pins: pcie30x4m0-pins { -+ rockchip,pins = -+ /* pcie30x4_clkreqn_m0 */ -+ <0 RK_PC6 12 &pcfg_pull_none>, -+ /* pcie30x4_perstn_m0 */ -+ <0 RK_PD0 12 &pcfg_pull_none>, -+ /* pcie30x4_waken_m0 */ -+ <0 RK_PC7 12 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4m1_pins: pcie30x4m1-pins { -+ rockchip,pins = -+ /* pcie30x4_clkreqn_m1 */ -+ <4 RK_PB4 4 &pcfg_pull_none>, -+ /* pcie30x4_perstn_m1 */ -+ <4 RK_PB6 4 &pcfg_pull_none>, -+ /* pcie30x4_waken_m1 */ -+ <4 RK_PB5 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4m2_pins: pcie30x4m2-pins { -+ rockchip,pins = -+ /* pcie30x4_clkreqn_m2 */ -+ <3 RK_PC4 4 &pcfg_pull_none>, -+ /* pcie30x4_perstn_m2 */ -+ <3 RK_PC6 4 &pcfg_pull_none>, -+ /* pcie30x4_waken_m2 */ -+ <3 RK_PC5 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4m3_pins: pcie30x4m3-pins { -+ rockchip,pins = -+ /* pcie30x4_clkreqn_m3 */ -+ <1 RK_PB0 4 &pcfg_pull_none>, -+ /* pcie30x4_perstn_m3 */ -+ <1 RK_PB2 4 &pcfg_pull_none>, -+ /* pcie30x4_waken_m3 */ -+ <1 RK_PB1 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4_button_rstn: pcie30x4-button-rstn { -+ rockchip,pins = -+ /* pcie30x4_button_rstn */ -+ <3 RK_PD5 4 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pdm0 { -+ /omit-if-no-ref/ -+ pdm0m0_clk: pdm0m0-clk { -+ rockchip,pins = -+ /* pdm0_clk0_m0 */ -+ <1 RK_PC6 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm0m0_clk1: pdm0m0-clk1 { -+ rockchip,pins = -+ /* pdm0m0_clk1 */ -+ <1 RK_PC4 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm0m0_sdi0: pdm0m0-sdi0 { -+ rockchip,pins = -+ /* pdm0m0_sdi0 */ -+ <1 RK_PD5 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm0m0_sdi1: pdm0m0-sdi1 { -+ rockchip,pins = -+ /* pdm0m0_sdi1 */ -+ <1 RK_PD1 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm0m0_sdi2: pdm0m0-sdi2 { -+ rockchip,pins = -+ /* pdm0m0_sdi2 */ -+ <1 RK_PD2 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm0m0_sdi3: pdm0m0-sdi3 { -+ rockchip,pins = -+ /* pdm0m0_sdi3 */ -+ <1 RK_PD3 3 &pcfg_pull_none>; -+ }; -+ /omit-if-no-ref/ -+ pdm0m1_clk: pdm0m1-clk { -+ rockchip,pins = -+ /* pdm0_clk0_m1 */ -+ <0 RK_PC0 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm0m1_clk1: pdm0m1-clk1 { -+ rockchip,pins = -+ /* pdm0m1_clk1 */ -+ <0 RK_PC4 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm0m1_sdi0: pdm0m1-sdi0 { -+ rockchip,pins = -+ /* pdm0m1_sdi0 */ -+ <0 RK_PC7 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm0m1_sdi1: pdm0m1-sdi1 { -+ rockchip,pins = -+ /* pdm0m1_sdi1 */ -+ <0 RK_PD0 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm0m1_sdi2: pdm0m1-sdi2 { -+ rockchip,pins = -+ /* pdm0m1_sdi2 */ -+ <0 RK_PD4 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm0m1_sdi3: pdm0m1-sdi3 { -+ rockchip,pins = -+ /* pdm0m1_sdi3 */ -+ <0 RK_PD6 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pdm1 { -+ /omit-if-no-ref/ -+ pdm1m0_clk: pdm1m0-clk { -+ rockchip,pins = -+ /* pdm1_clk0_m0 */ -+ <4 RK_PD5 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm1m0_clk1: pdm1m0-clk1 { -+ rockchip,pins = -+ /* pdm1m0_clk1 */ -+ <4 RK_PD4 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm1m0_sdi0: pdm1m0-sdi0 { -+ rockchip,pins = -+ /* pdm1m0_sdi0 */ -+ <4 RK_PD3 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm1m0_sdi1: pdm1m0-sdi1 { -+ rockchip,pins = -+ /* pdm1m0_sdi1 */ -+ <4 RK_PD2 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm1m0_sdi2: pdm1m0-sdi2 { -+ rockchip,pins = -+ /* pdm1m0_sdi2 */ -+ <4 RK_PD1 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm1m0_sdi3: pdm1m0-sdi3 { -+ rockchip,pins = -+ /* pdm1m0_sdi3 */ -+ <4 RK_PD0 2 &pcfg_pull_none>; -+ }; -+ /omit-if-no-ref/ -+ pdm1m1_clk: pdm1m1-clk { -+ rockchip,pins = -+ /* pdm1_clk0_m1 */ -+ <1 RK_PB4 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm1m1_clk1: pdm1m1-clk1 { -+ rockchip,pins = -+ /* pdm1m1_clk1 */ -+ <1 RK_PB3 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm1m1_sdi0: pdm1m1-sdi0 { -+ rockchip,pins = -+ /* pdm1m1_sdi0 */ -+ <1 RK_PA7 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm1m1_sdi1: pdm1m1-sdi1 { -+ rockchip,pins = -+ /* pdm1m1_sdi1 */ -+ <1 RK_PB0 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm1m1_sdi2: pdm1m1-sdi2 { -+ rockchip,pins = -+ /* pdm1m1_sdi2 */ -+ <1 RK_PB1 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pdm1m1_sdi3: pdm1m1-sdi3 { -+ rockchip,pins = -+ /* pdm1m1_sdi3 */ -+ <1 RK_PB2 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ /omit-if-no-ref/ -+ pmic_pins: pmic-pins { -+ rockchip,pins = -+ /* pmic_int_l */ -+ <0 RK_PA7 0 &pcfg_pull_up>, -+ /* pmic_sleep1 */ -+ <0 RK_PA2 1 &pcfg_pull_none>, -+ /* pmic_sleep2 */ -+ <0 RK_PA3 1 &pcfg_pull_none>, -+ /* pmic_sleep3 */ -+ <0 RK_PC1 1 &pcfg_pull_none>, -+ /* pmic_sleep4 */ -+ <0 RK_PC2 1 &pcfg_pull_none>, -+ /* pmic_sleep5 */ -+ <0 RK_PC3 1 &pcfg_pull_none>, -+ /* pmic_sleep6 */ -+ <0 RK_PD6 1 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmu { -+ /omit-if-no-ref/ -+ pmu_pins: pmu-pins { -+ rockchip,pins = -+ /* pmu_debug */ -+ <0 RK_PA5 3 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm0 { -+ /omit-if-no-ref/ -+ pwm0m0_pins: pwm0m0-pins { -+ rockchip,pins = -+ /* pwm0_m0 */ -+ <0 RK_PB7 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm0m1_pins: pwm0m1-pins { -+ rockchip,pins = -+ /* pwm0_m1 */ -+ <1 RK_PD2 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm0m2_pins: pwm0m2-pins { -+ rockchip,pins = -+ /* pwm0_m2 */ -+ <1 RK_PA2 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm1 { -+ /omit-if-no-ref/ -+ pwm1m0_pins: pwm1m0-pins { -+ rockchip,pins = -+ /* pwm1_m0 */ -+ <0 RK_PC0 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1m1_pins: pwm1m1-pins { -+ rockchip,pins = -+ /* pwm1_m1 */ -+ <1 RK_PD3 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1m2_pins: pwm1m2-pins { -+ rockchip,pins = -+ /* pwm1_m2 */ -+ <1 RK_PA3 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm2 { -+ /omit-if-no-ref/ -+ pwm2m0_pins: pwm2m0-pins { -+ rockchip,pins = -+ /* pwm2_m0 */ -+ <0 RK_PC4 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2m1_pins: pwm2m1-pins { -+ rockchip,pins = -+ /* pwm2_m1 */ -+ <3 RK_PB1 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm3 { -+ /omit-if-no-ref/ -+ pwm3m0_pins: pwm3m0-pins { -+ rockchip,pins = -+ /* pwm3_ir_m0 */ -+ <0 RK_PD4 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3m1_pins: pwm3m1-pins { -+ rockchip,pins = -+ /* pwm3_ir_m1 */ -+ <3 RK_PB2 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3m2_pins: pwm3m2-pins { -+ rockchip,pins = -+ /* pwm3_ir_m2 */ -+ <1 RK_PC2 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3m3_pins: pwm3m3-pins { -+ rockchip,pins = -+ /* pwm3_ir_m3 */ -+ <1 RK_PA7 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm4 { -+ /omit-if-no-ref/ -+ pwm4m0_pins: pwm4m0-pins { -+ rockchip,pins = -+ /* pwm4_m0 */ -+ <0 RK_PC5 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm5 { -+ /omit-if-no-ref/ -+ pwm5m0_pins: pwm5m0-pins { -+ rockchip,pins = -+ /* pwm5_m0 */ -+ <0 RK_PB1 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm5m1_pins: pwm5m1-pins { -+ rockchip,pins = -+ /* pwm5_m1 */ -+ <0 RK_PC6 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm6 { -+ /omit-if-no-ref/ -+ pwm6m0_pins: pwm6m0-pins { -+ rockchip,pins = -+ /* pwm6_m0 */ -+ <0 RK_PC7 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm6m1_pins: pwm6m1-pins { -+ rockchip,pins = -+ /* pwm6_m1 */ -+ <4 RK_PC1 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm7 { -+ /omit-if-no-ref/ -+ pwm7m0_pins: pwm7m0-pins { -+ rockchip,pins = -+ /* pwm7_ir_m0 */ -+ <0 RK_PD0 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm7m1_pins: pwm7m1-pins { -+ rockchip,pins = -+ /* pwm7_ir_m1 */ -+ <4 RK_PD4 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm7m2_pins: pwm7m2-pins { -+ rockchip,pins = -+ /* pwm7_ir_m2 */ -+ <1 RK_PC3 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm8 { -+ /omit-if-no-ref/ -+ pwm8m0_pins: pwm8m0-pins { -+ rockchip,pins = -+ /* pwm8_m0 */ -+ <3 RK_PA7 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm8m1_pins: pwm8m1-pins { -+ rockchip,pins = -+ /* pwm8_m1 */ -+ <4 RK_PD0 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm8m2_pins: pwm8m2-pins { -+ rockchip,pins = -+ /* pwm8_m2 */ -+ <3 RK_PD0 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm9 { -+ /omit-if-no-ref/ -+ pwm9m0_pins: pwm9m0-pins { -+ rockchip,pins = -+ /* pwm9_m0 */ -+ <3 RK_PB0 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm9m1_pins: pwm9m1-pins { -+ rockchip,pins = -+ /* pwm9_m1 */ -+ <4 RK_PD1 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm9m2_pins: pwm9m2-pins { -+ rockchip,pins = -+ /* pwm9_m2 */ -+ <3 RK_PD1 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm10 { -+ /omit-if-no-ref/ -+ pwm10m0_pins: pwm10m0-pins { -+ rockchip,pins = -+ /* pwm10_m0 */ -+ <3 RK_PA0 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm10m1_pins: pwm10m1-pins { -+ rockchip,pins = -+ /* pwm10_m1 */ -+ <4 RK_PD3 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm10m2_pins: pwm10m2-pins { -+ rockchip,pins = -+ /* pwm10_m2 */ -+ <3 RK_PD3 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm11 { -+ /omit-if-no-ref/ -+ pwm11m0_pins: pwm11m0-pins { -+ rockchip,pins = -+ /* pwm11_ir_m0 */ -+ <3 RK_PA1 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm11m1_pins: pwm11m1-pins { -+ rockchip,pins = -+ /* pwm11_ir_m1 */ -+ <4 RK_PB4 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm11m2_pins: pwm11m2-pins { -+ rockchip,pins = -+ /* pwm11_ir_m2 */ -+ <1 RK_PC4 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm11m3_pins: pwm11m3-pins { -+ rockchip,pins = -+ /* pwm11_ir_m3 */ -+ <3 RK_PD5 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm12 { -+ /omit-if-no-ref/ -+ pwm12m0_pins: pwm12m0-pins { -+ rockchip,pins = -+ /* pwm12_m0 */ -+ <3 RK_PB5 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm12m1_pins: pwm12m1-pins { -+ rockchip,pins = -+ /* pwm12_m1 */ -+ <4 RK_PB5 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm13 { -+ /omit-if-no-ref/ -+ pwm13m0_pins: pwm13m0-pins { -+ rockchip,pins = -+ /* pwm13_m0 */ -+ <3 RK_PB6 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm13m1_pins: pwm13m1-pins { -+ rockchip,pins = -+ /* pwm13_m1 */ -+ <4 RK_PB6 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm13m2_pins: pwm13m2-pins { -+ rockchip,pins = -+ /* pwm13_m2 */ -+ <1 RK_PB7 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm14 { -+ /omit-if-no-ref/ -+ pwm14m0_pins: pwm14m0-pins { -+ rockchip,pins = -+ /* pwm14_m0 */ -+ <3 RK_PC2 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm14m1_pins: pwm14m1-pins { -+ rockchip,pins = -+ /* pwm14_m1 */ -+ <4 RK_PB2 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm14m2_pins: pwm14m2-pins { -+ rockchip,pins = -+ /* pwm14_m2 */ -+ <1 RK_PD6 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm15 { -+ /omit-if-no-ref/ -+ pwm15m0_pins: pwm15m0-pins { -+ rockchip,pins = -+ /* pwm15_ir_m0 */ -+ <3 RK_PC3 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm15m1_pins: pwm15m1-pins { -+ rockchip,pins = -+ /* pwm15_ir_m1 */ -+ <4 RK_PB3 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm15m2_pins: pwm15m2-pins { -+ rockchip,pins = -+ /* pwm15_ir_m2 */ -+ <1 RK_PC6 11 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm15m3_pins: pwm15m3-pins { -+ rockchip,pins = -+ /* pwm15_ir_m3 */ -+ <1 RK_PD7 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ refclk { -+ /omit-if-no-ref/ -+ refclk_pins: refclk-pins { -+ rockchip,pins = -+ /* refclk_out */ -+ <0 RK_PA0 1 &pcfg_pull_none>; -+ }; -+ }; -+ -+ sata { -+ /omit-if-no-ref/ -+ sata_pins: sata-pins { -+ rockchip,pins = -+ /* sata_cp_pod */ -+ <0 RK_PC6 13 &pcfg_pull_none>, -+ /* sata_cpdet */ -+ <0 RK_PD4 13 &pcfg_pull_none>, -+ /* sata_mp_switch */ -+ <0 RK_PD5 13 &pcfg_pull_none>; -+ }; -+ }; -+ -+ sata0 { -+ /omit-if-no-ref/ -+ sata0m0_pins: sata0m0-pins { -+ rockchip,pins = -+ /* sata0_act_led_m0 */ -+ <4 RK_PB6 6 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ sata0m1_pins: sata0m1-pins { -+ rockchip,pins = -+ /* sata0_act_led_m1 */ -+ <1 RK_PB3 6 &pcfg_pull_none>; -+ }; -+ }; -+ -+ sata1 { -+ /omit-if-no-ref/ -+ sata1m0_pins: sata1m0-pins { -+ rockchip,pins = -+ /* sata1_act_led_m0 */ -+ <4 RK_PB5 6 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ sata1m1_pins: sata1m1-pins { -+ rockchip,pins = -+ /* sata1_act_led_m1 */ -+ <1 RK_PA1 6 &pcfg_pull_none>; -+ }; -+ }; -+ -+ sata2 { -+ /omit-if-no-ref/ -+ sata2m0_pins: sata2m0-pins { -+ rockchip,pins = -+ /* sata2_act_led_m0 */ -+ <4 RK_PB1 6 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ sata2m1_pins: sata2m1-pins { -+ rockchip,pins = -+ /* sata2_act_led_m1 */ -+ <1 RK_PB7 6 &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdio { -+ /omit-if-no-ref/ -+ sdiom1_pins: sdiom1-pins { -+ rockchip,pins = -+ /* sdio_clk_m1 */ -+ <3 RK_PA5 2 &pcfg_pull_none>, -+ /* sdio_cmd_m1 */ -+ <3 RK_PA4 2 &pcfg_pull_none>, -+ /* sdio_d0_m1 */ -+ <3 RK_PA0 2 &pcfg_pull_none>, -+ /* sdio_d1_m1 */ -+ <3 RK_PA1 2 &pcfg_pull_none>, -+ /* sdio_d2_m1 */ -+ <3 RK_PA2 2 &pcfg_pull_none>, -+ /* sdio_d3_m1 */ -+ <3 RK_PA3 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdmmc { -+ /omit-if-no-ref/ -+ sdmmc_bus4: sdmmc-bus4 { -+ rockchip,pins = -+ /* sdmmc_d0 */ -+ <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, -+ /* sdmmc_d1 */ -+ <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, -+ /* sdmmc_d2 */ -+ <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, -+ /* sdmmc_d3 */ -+ <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; -+ }; -+ -+ /omit-if-no-ref/ -+ sdmmc_clk: sdmmc-clk { -+ rockchip,pins = -+ /* sdmmc_clk */ -+ <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; -+ }; -+ -+ /omit-if-no-ref/ -+ sdmmc_cmd: sdmmc-cmd { -+ rockchip,pins = -+ /* sdmmc_cmd */ -+ <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; -+ }; -+ -+ /omit-if-no-ref/ -+ sdmmc_det: sdmmc-det { -+ rockchip,pins = -+ /* sdmmc_det */ -+ <0 RK_PA4 1 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ sdmmc_pwren: sdmmc-pwren { -+ rockchip,pins = -+ /* sdmmc_pwren */ -+ <0 RK_PA5 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ spdif0 { -+ /omit-if-no-ref/ -+ spdif0m0_tx: spdif0m0-tx { -+ rockchip,pins = -+ /* spdif0m0_tx */ -+ <1 RK_PB6 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ spdif0m1_tx: spdif0m1-tx { -+ rockchip,pins = -+ /* spdif0m1_tx */ -+ <4 RK_PB4 6 &pcfg_pull_none>; -+ }; -+ }; -+ -+ spdif1 { -+ /omit-if-no-ref/ -+ spdif1m0_tx: spdif1m0-tx { -+ rockchip,pins = -+ /* spdif1m0_tx */ -+ <1 RK_PB7 3 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ spdif1m1_tx: spdif1m1-tx { -+ rockchip,pins = -+ /* spdif1m1_tx */ -+ <4 RK_PB1 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ spdif1m2_tx: spdif1m2-tx { -+ rockchip,pins = -+ /* spdif1m2_tx */ -+ <4 RK_PC1 3 &pcfg_pull_none>; -+ }; -+ }; -+ -+ spi0 { -+ /omit-if-no-ref/ -+ spi0m0_pins: spi0m0-pins { -+ rockchip,pins = -+ /* spi0_clk_m0 */ -+ <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>, -+ /* spi0_miso_m0 */ -+ <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>, -+ /* spi0_mosi_m0 */ -+ <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi0m0_cs0: spi0m0-cs0 { -+ rockchip,pins = -+ /* spi0_cs0_m0 */ -+ <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi0m0_cs1: spi0m0-cs1 { -+ rockchip,pins = -+ /* spi0_cs1_m0 */ -+ <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ /omit-if-no-ref/ -+ spi0m1_pins: spi0m1-pins { -+ rockchip,pins = -+ /* spi0_clk_m1 */ -+ <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>, -+ /* spi0_miso_m1 */ -+ <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>, -+ /* spi0_mosi_m1 */ -+ <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi0m1_cs0: spi0m1-cs0 { -+ rockchip,pins = -+ /* spi0_cs0_m1 */ -+ <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi0m1_cs1: spi0m1-cs1 { -+ rockchip,pins = -+ /* spi0_cs1_m1 */ -+ <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ /omit-if-no-ref/ -+ spi0m2_pins: spi0m2-pins { -+ rockchip,pins = -+ /* spi0_clk_m2 */ -+ <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>, -+ /* spi0_miso_m2 */ -+ <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>, -+ /* spi0_mosi_m2 */ -+ <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi0m2_cs0: spi0m2-cs0 { -+ rockchip,pins = -+ /* spi0_cs0_m2 */ -+ <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi0m2_cs1: spi0m2-cs1 { -+ rockchip,pins = -+ /* spi0_cs1_m2 */ -+ <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ /omit-if-no-ref/ -+ spi0m3_pins: spi0m3-pins { -+ rockchip,pins = -+ /* spi0_clk_m3 */ -+ <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>, -+ /* spi0_miso_m3 */ -+ <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>, -+ /* spi0_mosi_m3 */ -+ <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi0m3_cs0: spi0m3-cs0 { -+ rockchip,pins = -+ /* spi0_cs0_m3 */ -+ <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi0m3_cs1: spi0m3-cs1 { -+ rockchip,pins = -+ /* spi0_cs1_m3 */ -+ <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ }; -+ -+ spi1 { -+ /omit-if-no-ref/ -+ spi1m1_pins: spi1m1-pins { -+ rockchip,pins = -+ /* spi1_clk_m1 */ -+ <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>, -+ /* spi1_miso_m1 */ -+ <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>, -+ /* spi1_mosi_m1 */ -+ <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi1m1_cs0: spi1m1-cs0 { -+ rockchip,pins = -+ /* spi1_cs0_m1 */ -+ <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi1m1_cs1: spi1m1-cs1 { -+ rockchip,pins = -+ /* spi1_cs1_m1 */ -+ <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi1m2_pins: spi1m2-pins { -+ rockchip,pins = -+ /* spi1_clk_m2 */ -+ <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>, -+ /* spi1_miso_m2 */ -+ <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>, -+ /* spi1_mosi_m2 */ -+ <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi1m2_cs0: spi1m2-cs0 { -+ rockchip,pins = -+ /* spi1_cs0_m2 */ -+ <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi1m2_cs1: spi1m2-cs1 { -+ rockchip,pins = -+ /* spi1_cs1_m2 */ -+ <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ }; -+ -+ spi2 { -+ /omit-if-no-ref/ -+ spi2m0_pins: spi2m0-pins { -+ rockchip,pins = -+ /* spi2_clk_m0 */ -+ <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>, -+ /* spi2_miso_m0 */ -+ <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>, -+ /* spi2_mosi_m0 */ -+ <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi2m0_cs0: spi2m0-cs0 { -+ rockchip,pins = -+ /* spi2_cs0_m0 */ -+ <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi2m0_cs1: spi2m0-cs1 { -+ rockchip,pins = -+ /* spi2_cs1_m0 */ -+ <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi2m1_pins: spi2m1-pins { -+ rockchip,pins = -+ /* spi2_clk_m1 */ -+ <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>, -+ /* spi2_miso_m1 */ -+ <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>, -+ /* spi2_mosi_m1 */ -+ <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi2m1_cs0: spi2m1-cs0 { -+ rockchip,pins = -+ /* spi2_cs0_m1 */ -+ <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi2m1_cs1: spi2m1-cs1 { -+ rockchip,pins = -+ /* spi2_cs1_m1 */ -+ <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi2m2_pins: spi2m2-pins { -+ rockchip,pins = -+ /* spi2_clk_m2 */ -+ <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, -+ /* spi2_miso_m2 */ -+ <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, -+ /* spi2_mosi_m2 */ -+ <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi2m2_cs0: spi2m2-cs0 { -+ rockchip,pins = -+ /* spi2_cs0_m2 */ -+ <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi2m2_cs1: spi2m2-cs1 { -+ rockchip,pins = -+ /* spi2_cs1_m2 */ -+ <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>; -+ }; -+ }; -+ -+ spi3 { -+ /omit-if-no-ref/ -+ spi3m1_pins: spi3m1-pins { -+ rockchip,pins = -+ /* spi3_clk_m1 */ -+ <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>, -+ /* spi3_miso_m1 */ -+ <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>, -+ /* spi3_mosi_m1 */ -+ <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi3m1_cs0: spi3m1-cs0 { -+ rockchip,pins = -+ /* spi3_cs0_m1 */ -+ <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi3m1_cs1: spi3m1-cs1 { -+ rockchip,pins = -+ /* spi3_cs1_m1 */ -+ <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi3m2_pins: spi3m2-pins { -+ rockchip,pins = -+ /* spi3_clk_m2 */ -+ <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>, -+ /* spi3_miso_m2 */ -+ <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>, -+ /* spi3_mosi_m2 */ -+ <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi3m2_cs0: spi3m2-cs0 { -+ rockchip,pins = -+ /* spi3_cs0_m2 */ -+ <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi3m2_cs1: spi3m2-cs1 { -+ rockchip,pins = -+ /* spi3_cs1_m2 */ -+ <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi3m3_pins: spi3m3-pins { -+ rockchip,pins = -+ /* spi3_clk_m3 */ -+ <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>, -+ /* spi3_miso_m3 */ -+ <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>, -+ /* spi3_mosi_m3 */ -+ <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi3m3_cs0: spi3m3-cs0 { -+ rockchip,pins = -+ /* spi3_cs0_m3 */ -+ <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi3m3_cs1: spi3m3-cs1 { -+ rockchip,pins = -+ /* spi3_cs1_m3 */ -+ <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ }; -+ -+ spi4 { -+ /omit-if-no-ref/ -+ spi4m0_pins: spi4m0-pins { -+ rockchip,pins = -+ /* spi4_clk_m0 */ -+ <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>, -+ /* spi4_miso_m0 */ -+ <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>, -+ /* spi4_mosi_m0 */ -+ <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi4m0_cs0: spi4m0-cs0 { -+ rockchip,pins = -+ /* spi4_cs0_m0 */ -+ <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi4m0_cs1: spi4m0-cs1 { -+ rockchip,pins = -+ /* spi4_cs1_m0 */ -+ <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi4m1_pins: spi4m1-pins { -+ rockchip,pins = -+ /* spi4_clk_m1 */ -+ <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>, -+ /* spi4_miso_m1 */ -+ <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>, -+ /* spi4_mosi_m1 */ -+ <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi4m1_cs0: spi4m1-cs0 { -+ rockchip,pins = -+ /* spi4_cs0_m1 */ -+ <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi4m1_cs1: spi4m1-cs1 { -+ rockchip,pins = -+ /* spi4_cs1_m1 */ -+ <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi4m2_pins: spi4m2-pins { -+ rockchip,pins = -+ /* spi4_clk_m2 */ -+ <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>, -+ /* spi4_miso_m2 */ -+ <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>, -+ /* spi4_mosi_m2 */ -+ <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi4m2_cs0: spi4m2-cs0 { -+ rockchip,pins = -+ /* spi4_cs0_m2 */ -+ <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ }; -+ -+ tsadc { -+ /omit-if-no-ref/ -+ tsadcm1_shut: tsadcm1-shut { -+ rockchip,pins = -+ /* tsadcm1_shut */ -+ <0 RK_PA2 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ tsadc_shut: tsadc-shut { -+ rockchip,pins = -+ /* tsadc_shut */ -+ <0 RK_PA1 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ tsadc_shut_org: tsadc-shut-org { -+ rockchip,pins = -+ /* tsadc_shut_org */ -+ <0 RK_PA1 1 &pcfg_pull_none>; -+ }; -+ }; -+ -+ uart0 { -+ /omit-if-no-ref/ -+ uart0m0_xfer: uart0m0-xfer { -+ rockchip,pins = -+ /* uart0_rx_m0 */ -+ <0 RK_PC4 4 &pcfg_pull_up>, -+ /* uart0_tx_m0 */ -+ <0 RK_PC5 4 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart0m1_xfer: uart0m1-xfer { -+ rockchip,pins = -+ /* uart0_rx_m1 */ -+ <0 RK_PB0 4 &pcfg_pull_up>, -+ /* uart0_tx_m1 */ -+ <0 RK_PB1 4 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart0m2_xfer: uart0m2-xfer { -+ rockchip,pins = -+ /* uart0_rx_m2 */ -+ <4 RK_PA4 10 &pcfg_pull_up>, -+ /* uart0_tx_m2 */ -+ <4 RK_PA3 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart0_ctsn: uart0-ctsn { -+ rockchip,pins = -+ /* uart0_ctsn */ -+ <0 RK_PD1 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart0_rtsn: uart0-rtsn { -+ rockchip,pins = -+ /* uart0_rtsn */ -+ <0 RK_PC6 4 &pcfg_pull_none>; -+ }; -+ }; -+ -+ uart1 { -+ /omit-if-no-ref/ -+ uart1m1_xfer: uart1m1-xfer { -+ rockchip,pins = -+ /* uart1_rx_m1 */ -+ <1 RK_PB7 10 &pcfg_pull_up>, -+ /* uart1_tx_m1 */ -+ <1 RK_PB6 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart1m1_ctsn: uart1m1-ctsn { -+ rockchip,pins = -+ /* uart1m1_ctsn */ -+ <1 RK_PD7 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart1m1_rtsn: uart1m1-rtsn { -+ rockchip,pins = -+ /* uart1m1_rtsn */ -+ <1 RK_PD6 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart1m2_xfer: uart1m2-xfer { -+ rockchip,pins = -+ /* uart1_rx_m2 */ -+ <0 RK_PD2 10 &pcfg_pull_up>, -+ /* uart1_tx_m2 */ -+ <0 RK_PD1 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart1m2_ctsn: uart1m2-ctsn { -+ rockchip,pins = -+ /* uart1m2_ctsn */ -+ <0 RK_PD0 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart1m2_rtsn: uart1m2-rtsn { -+ rockchip,pins = -+ /* uart1m2_rtsn */ -+ <0 RK_PC7 10 &pcfg_pull_none>; -+ }; -+ }; -+ -+ uart2 { -+ /omit-if-no-ref/ -+ uart2m0_xfer: uart2m0-xfer { -+ rockchip,pins = -+ /* uart2_rx_m0 */ -+ <0 RK_PB6 10 &pcfg_pull_up>, -+ /* uart2_tx_m0 */ -+ <0 RK_PB5 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart2m1_xfer: uart2m1-xfer { -+ rockchip,pins = -+ /* uart2_rx_m1 */ -+ <4 RK_PD1 10 &pcfg_pull_up>, -+ /* uart2_tx_m1 */ -+ <4 RK_PD0 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart2m2_xfer: uart2m2-xfer { -+ rockchip,pins = -+ /* uart2_rx_m2 */ -+ <3 RK_PB2 10 &pcfg_pull_up>, -+ /* uart2_tx_m2 */ -+ <3 RK_PB1 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart2_ctsn: uart2-ctsn { -+ rockchip,pins = -+ /* uart2_ctsn */ -+ <3 RK_PB4 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart2_rtsn: uart2-rtsn { -+ rockchip,pins = -+ /* uart2_rtsn */ -+ <3 RK_PB3 10 &pcfg_pull_none>; -+ }; -+ }; -+ -+ uart3 { -+ /omit-if-no-ref/ -+ uart3m0_xfer: uart3m0-xfer { -+ rockchip,pins = -+ /* uart3_rx_m0 */ -+ <1 RK_PC0 10 &pcfg_pull_up>, -+ /* uart3_tx_m0 */ -+ <1 RK_PC1 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart3m1_xfer: uart3m1-xfer { -+ rockchip,pins = -+ /* uart3_rx_m1 */ -+ <3 RK_PB6 10 &pcfg_pull_up>, -+ /* uart3_tx_m1 */ -+ <3 RK_PB5 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart3m2_xfer: uart3m2-xfer { -+ rockchip,pins = -+ /* uart3_rx_m2 */ -+ <4 RK_PA6 10 &pcfg_pull_up>, -+ /* uart3_tx_m2 */ -+ <4 RK_PA5 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart3_ctsn: uart3-ctsn { -+ rockchip,pins = -+ /* uart3_ctsn */ -+ <1 RK_PC3 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart3_rtsn: uart3-rtsn { -+ rockchip,pins = -+ /* uart3_rtsn */ -+ <1 RK_PC2 10 &pcfg_pull_none>; -+ }; -+ }; -+ -+ uart4 { -+ /omit-if-no-ref/ -+ uart4m0_xfer: uart4m0-xfer { -+ rockchip,pins = -+ /* uart4_rx_m0 */ -+ <1 RK_PD3 10 &pcfg_pull_up>, -+ /* uart4_tx_m0 */ -+ <1 RK_PD2 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart4m1_xfer: uart4m1-xfer { -+ rockchip,pins = -+ /* uart4_rx_m1 */ -+ <3 RK_PD0 10 &pcfg_pull_up>, -+ /* uart4_tx_m1 */ -+ <3 RK_PD1 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart4m2_xfer: uart4m2-xfer { -+ rockchip,pins = -+ /* uart4_rx_m2 */ -+ <1 RK_PB2 10 &pcfg_pull_up>, -+ /* uart4_tx_m2 */ -+ <1 RK_PB3 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart4_ctsn: uart4-ctsn { -+ rockchip,pins = -+ /* uart4_ctsn */ -+ <1 RK_PC7 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart4_rtsn: uart4-rtsn { -+ rockchip,pins = -+ /* uart4_rtsn */ -+ <1 RK_PC5 10 &pcfg_pull_none>; -+ }; -+ }; -+ -+ uart5 { -+ /omit-if-no-ref/ -+ uart5m0_xfer: uart5m0-xfer { -+ rockchip,pins = -+ /* uart5_rx_m0 */ -+ <4 RK_PD4 10 &pcfg_pull_up>, -+ /* uart5_tx_m0 */ -+ <4 RK_PD5 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart5m0_ctsn: uart5m0-ctsn { -+ rockchip,pins = -+ /* uart5m0_ctsn */ -+ <4 RK_PD2 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart5m0_rtsn: uart5m0-rtsn { -+ rockchip,pins = -+ /* uart5m0_rtsn */ -+ <4 RK_PD3 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart5m1_xfer: uart5m1-xfer { -+ rockchip,pins = -+ /* uart5_rx_m1 */ -+ <3 RK_PC5 10 &pcfg_pull_up>, -+ /* uart5_tx_m1 */ -+ <3 RK_PC4 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart5m1_ctsn: uart5m1-ctsn { -+ rockchip,pins = -+ /* uart5m1_ctsn */ -+ <2 RK_PA2 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart5m1_rtsn: uart5m1-rtsn { -+ rockchip,pins = -+ /* uart5m1_rtsn */ -+ <2 RK_PA3 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart5m2_xfer: uart5m2-xfer { -+ rockchip,pins = -+ /* uart5_rx_m2 */ -+ <2 RK_PD4 10 &pcfg_pull_up>, -+ /* uart5_tx_m2 */ -+ <2 RK_PD5 10 &pcfg_pull_up>; -+ }; -+ }; -+ -+ uart6 { -+ /omit-if-no-ref/ -+ uart6m1_xfer: uart6m1-xfer { -+ rockchip,pins = -+ /* uart6_rx_m1 */ -+ <1 RK_PA0 10 &pcfg_pull_up>, -+ /* uart6_tx_m1 */ -+ <1 RK_PA1 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart6m1_ctsn: uart6m1-ctsn { -+ rockchip,pins = -+ /* uart6m1_ctsn */ -+ <1 RK_PA3 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart6m1_rtsn: uart6m1-rtsn { -+ rockchip,pins = -+ /* uart6m1_rtsn */ -+ <1 RK_PA2 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart6m2_xfer: uart6m2-xfer { -+ rockchip,pins = -+ /* uart6_rx_m2 */ -+ <1 RK_PD1 10 &pcfg_pull_up>, -+ /* uart6_tx_m2 */ -+ <1 RK_PD0 10 &pcfg_pull_up>; -+ }; -+ }; -+ -+ uart7 { -+ /omit-if-no-ref/ -+ uart7m1_xfer: uart7m1-xfer { -+ rockchip,pins = -+ /* uart7_rx_m1 */ -+ <3 RK_PC1 10 &pcfg_pull_up>, -+ /* uart7_tx_m1 */ -+ <3 RK_PC0 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart7m1_ctsn: uart7m1-ctsn { -+ rockchip,pins = -+ /* uart7m1_ctsn */ -+ <3 RK_PC3 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart7m1_rtsn: uart7m1-rtsn { -+ rockchip,pins = -+ /* uart7m1_rtsn */ -+ <3 RK_PC2 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart7m2_xfer: uart7m2-xfer { -+ rockchip,pins = -+ /* uart7_rx_m2 */ -+ <1 RK_PB4 10 &pcfg_pull_up>, -+ /* uart7_tx_m2 */ -+ <1 RK_PB5 10 &pcfg_pull_up>; -+ }; -+ }; -+ -+ uart8 { -+ /omit-if-no-ref/ -+ uart8m0_xfer: uart8m0-xfer { -+ rockchip,pins = -+ /* uart8_rx_m0 */ -+ <4 RK_PB1 10 &pcfg_pull_up>, -+ /* uart8_tx_m0 */ -+ <4 RK_PB0 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart8m0_ctsn: uart8m0-ctsn { -+ rockchip,pins = -+ /* uart8m0_ctsn */ -+ <4 RK_PB3 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart8m0_rtsn: uart8m0-rtsn { -+ rockchip,pins = -+ /* uart8m0_rtsn */ -+ <4 RK_PB2 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart8m1_xfer: uart8m1-xfer { -+ rockchip,pins = -+ /* uart8_rx_m1 */ -+ <3 RK_PA3 10 &pcfg_pull_up>, -+ /* uart8_tx_m1 */ -+ <3 RK_PA2 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart8m1_ctsn: uart8m1-ctsn { -+ rockchip,pins = -+ /* uart8m1_ctsn */ -+ <3 RK_PA5 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart8m1_rtsn: uart8m1-rtsn { -+ rockchip,pins = -+ /* uart8m1_rtsn */ -+ <3 RK_PA4 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart8_xfer: uart8-xfer { -+ rockchip,pins = -+ /* uart8_rx_ */ -+ <4 RK_PB1 10 &pcfg_pull_up>; -+ }; -+ }; -+ -+ uart9 { -+ /omit-if-no-ref/ -+ uart9m0_xfer: uart9m0-xfer { -+ rockchip,pins = -+ /* uart9_rx_m0 */ -+ <2 RK_PC4 10 &pcfg_pull_up>, -+ /* uart9_tx_m0 */ -+ <2 RK_PC2 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart9m1_xfer: uart9m1-xfer { -+ rockchip,pins = -+ /* uart9_rx_m1 */ -+ <4 RK_PB5 10 &pcfg_pull_up>, -+ /* uart9_tx_m1 */ -+ <4 RK_PB4 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart9m1_ctsn: uart9m1-ctsn { -+ rockchip,pins = -+ /* uart9m1_ctsn */ -+ <4 RK_PA1 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart9m1_rtsn: uart9m1-rtsn { -+ rockchip,pins = -+ /* uart9m1_rtsn */ -+ <4 RK_PA0 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart9m2_xfer: uart9m2-xfer { -+ rockchip,pins = -+ /* uart9_rx_m2 */ -+ <3 RK_PD4 10 &pcfg_pull_up>, -+ /* uart9_tx_m2 */ -+ <3 RK_PD5 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart9m2_ctsn: uart9m2-ctsn { -+ rockchip,pins = -+ /* uart9m2_ctsn */ -+ <3 RK_PD3 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart9m2_rtsn: uart9m2-rtsn { -+ rockchip,pins = -+ /* uart9m2_rtsn */ -+ <3 RK_PD2 10 &pcfg_pull_none>; -+ }; -+ }; -+ -+ vop { -+ /omit-if-no-ref/ -+ vop_pins: vop-pins { -+ rockchip,pins = -+ /* vop_post_empty */ -+ <1 RK_PA2 1 &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+/* -+ * This part is edited handly. -+ */ -+&pinctrl { -+ bt656 { -+ /omit-if-no-ref/ -+ bt656_pins: bt656-pins { -+ rockchip,pins = -+ /* bt1120_clkout */ -+ <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>, -+ /* bt1120_d0 */ -+ <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>, -+ /* bt1120_d1 */ -+ <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>, -+ /* bt1120_d2 */ -+ <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>, -+ /* bt1120_d3 */ -+ <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>, -+ /* bt1120_d4 */ -+ <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>, -+ /* bt1120_d5 */ -+ <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>, -+ /* bt1120_d6 */ -+ <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>, -+ /* bt1120_d7 */ -+ <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>; -+ }; -+ }; -+ -+ gpio-func { -+ /omit-if-no-ref/ -+ tsadc_gpio_func: tsadc-gpio-func { -+ rockchip,pins = -+ <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi -@@ -0,0 +1,516 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ */ -+ -+#include -+#include "rockchip-pinconf.dtsi" -+ -+/* -+ * This file is auto generated by pin2dts tool, please keep these code -+ * by adding changes at end of this file. -+ */ -+&pinctrl { -+ clk32k { -+ /omit-if-no-ref/ -+ clk32k_out1: clk32k-out1 { -+ rockchip,pins = -+ /* clk32k_out1 */ -+ <2 RK_PC5 1 &pcfg_pull_none>; -+ }; -+ -+ }; -+ -+ eth0 { -+ /omit-if-no-ref/ -+ eth0_pins: eth0-pins { -+ rockchip,pins = -+ /* eth0_refclko_25m */ -+ <2 RK_PC3 1 &pcfg_pull_none>; -+ }; -+ -+ }; -+ -+ fspi { -+ /omit-if-no-ref/ -+ fspim1_pins: fspim1-pins { -+ rockchip,pins = -+ /* fspi_clk_m1 */ -+ <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, -+ /* fspi_cs0n_m1 */ -+ <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, -+ /* fspi_d0_m1 */ -+ <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, -+ /* fspi_d1_m1 */ -+ <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, -+ /* fspi_d2_m1 */ -+ <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, -+ /* fspi_d3_m1 */ -+ <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; -+ }; -+ -+ /omit-if-no-ref/ -+ fspim1_cs1: fspim1-cs1 { -+ rockchip,pins = -+ /* fspi_cs1n_m1 */ -+ <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; -+ }; -+ }; -+ -+ gmac0 { -+ /omit-if-no-ref/ -+ gmac0_miim: gmac0-miim { -+ rockchip,pins = -+ /* gmac0_mdc */ -+ <4 RK_PC4 1 &pcfg_pull_none>, -+ /* gmac0_mdio */ -+ <4 RK_PC5 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac0_clkinout: gmac0-clkinout { -+ rockchip,pins = -+ /* gmac0_mclkinout */ -+ <4 RK_PC3 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac0_rx_bus2: gmac0-rx-bus2 { -+ rockchip,pins = -+ /* gmac0_rxd0 */ -+ <2 RK_PC1 1 &pcfg_pull_none>, -+ /* gmac0_rxd1 */ -+ <2 RK_PC2 1 &pcfg_pull_none>, -+ /* gmac0_rxdv_crs */ -+ <4 RK_PC2 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac0_tx_bus2: gmac0-tx-bus2 { -+ rockchip,pins = -+ /* gmac0_txd0 */ -+ <2 RK_PB6 1 &pcfg_pull_none>, -+ /* gmac0_txd1 */ -+ <2 RK_PB7 1 &pcfg_pull_none>, -+ /* gmac0_txen */ -+ <2 RK_PC0 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac0_rgmii_clk: gmac0-rgmii-clk { -+ rockchip,pins = -+ /* gmac0_rxclk */ -+ <2 RK_PB0 1 &pcfg_pull_none>, -+ /* gmac0_txclk */ -+ <2 RK_PB3 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac0_rgmii_bus: gmac0-rgmii-bus { -+ rockchip,pins = -+ /* gmac0_rxd2 */ -+ <2 RK_PA6 1 &pcfg_pull_none>, -+ /* gmac0_rxd3 */ -+ <2 RK_PA7 1 &pcfg_pull_none>, -+ /* gmac0_txd2 */ -+ <2 RK_PB1 1 &pcfg_pull_none>, -+ /* gmac0_txd3 */ -+ <2 RK_PB2 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac0_ppsclk: gmac0-ppsclk { -+ rockchip,pins = -+ /* gmac0_ppsclk */ -+ <2 RK_PC4 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac0_ppstring: gmac0-ppstring { -+ rockchip,pins = -+ /* gmac0_ppstring */ -+ <2 RK_PB5 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac0_ptp_refclk: gmac0-ptp-refclk { -+ rockchip,pins = -+ /* gmac0_ptp_refclk */ -+ <2 RK_PB4 1 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ gmac0_txer: gmac0-txer { -+ rockchip,pins = -+ /* gmac0_txer */ -+ <4 RK_PC6 1 &pcfg_pull_none>; -+ }; -+ -+ }; -+ -+ hdmi { -+ /omit-if-no-ref/ -+ hdmim0_tx1_cec: hdmim0-tx1-cec { -+ rockchip,pins = -+ /* hdmim0_tx1_cec */ -+ <2 RK_PC4 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim0_tx1_scl: hdmim0-tx1-scl { -+ rockchip,pins = -+ /* hdmim0_tx1_scl */ -+ <2 RK_PB5 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim0_tx1_sda: hdmim0-tx1-sda { -+ rockchip,pins = -+ /* hdmim0_tx1_sda */ -+ <2 RK_PB4 4 &pcfg_pull_none>; -+ }; -+ }; -+ -+ i2c0 { -+ /omit-if-no-ref/ -+ i2c0m1_xfer: i2c0m1-xfer { -+ rockchip,pins = -+ /* i2c0_scl_m1 */ -+ <4 RK_PC5 9 &pcfg_pull_none_smt>, -+ /* i2c0_sda_m1 */ -+ <4 RK_PC6 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c2 { -+ /omit-if-no-ref/ -+ i2c2m1_xfer: i2c2m1-xfer { -+ rockchip,pins = -+ /* i2c2_scl_m1 */ -+ <2 RK_PC1 9 &pcfg_pull_none_smt>, -+ /* i2c2_sda_m1 */ -+ <2 RK_PC0 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c3 { -+ /omit-if-no-ref/ -+ i2c3m3_xfer: i2c3m3-xfer { -+ rockchip,pins = -+ /* i2c3_scl_m3 */ -+ <2 RK_PB2 9 &pcfg_pull_none_smt>, -+ /* i2c3_sda_m3 */ -+ <2 RK_PB3 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c4 { -+ /omit-if-no-ref/ -+ i2c4m1_xfer: i2c4m1-xfer { -+ rockchip,pins = -+ /* i2c4_scl_m1 */ -+ <2 RK_PB5 9 &pcfg_pull_none_smt>, -+ /* i2c4_sda_m1 */ -+ <2 RK_PB4 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c5 { -+ /omit-if-no-ref/ -+ i2c5m4_xfer: i2c5m4-xfer { -+ rockchip,pins = -+ /* i2c5_scl_m4 */ -+ <2 RK_PB6 9 &pcfg_pull_none_smt>, -+ /* i2c5_sda_m4 */ -+ <2 RK_PB7 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c6 { -+ /omit-if-no-ref/ -+ i2c6m2_xfer: i2c6m2-xfer { -+ rockchip,pins = -+ /* i2c6_scl_m2 */ -+ <2 RK_PC3 9 &pcfg_pull_none_smt>, -+ /* i2c6_sda_m2 */ -+ <2 RK_PC2 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c7 { -+ /omit-if-no-ref/ -+ i2c7m1_xfer: i2c7m1-xfer { -+ rockchip,pins = -+ /* i2c7_scl_m1 */ -+ <4 RK_PC3 9 &pcfg_pull_none_smt>, -+ /* i2c7_sda_m1 */ -+ <4 RK_PC4 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2c8 { -+ /omit-if-no-ref/ -+ i2c8m1_xfer: i2c8m1-xfer { -+ rockchip,pins = -+ /* i2c8_scl_m1 */ -+ <2 RK_PB0 9 &pcfg_pull_none_smt>, -+ /* i2c8_sda_m1 */ -+ <2 RK_PB1 9 &pcfg_pull_none_smt>; -+ }; -+ }; -+ -+ i2s2 { -+ /omit-if-no-ref/ -+ i2s2m0_lrck: i2s2m0-lrck { -+ rockchip,pins = -+ /* i2s2m0_lrck */ -+ <2 RK_PC0 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m0_mclk: i2s2m0-mclk { -+ rockchip,pins = -+ /* i2s2m0_mclk */ -+ <2 RK_PB6 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m0_sclk: i2s2m0-sclk { -+ rockchip,pins = -+ /* i2s2m0_sclk */ -+ <2 RK_PB7 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m0_sdi: i2s2m0-sdi { -+ rockchip,pins = -+ /* i2s2m0_sdi */ -+ <2 RK_PC3 2 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ i2s2m0_sdo: i2s2m0-sdo { -+ rockchip,pins = -+ /* i2s2m0_sdo */ -+ <4 RK_PC3 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm2 { -+ /omit-if-no-ref/ -+ pwm2m2_pins: pwm2m2-pins { -+ rockchip,pins = -+ /* pwm2_m2 */ -+ <4 RK_PC2 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm4 { -+ /omit-if-no-ref/ -+ pwm4m1_pins: pwm4m1-pins { -+ rockchip,pins = -+ /* pwm4_m1 */ -+ <4 RK_PC3 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm5 { -+ /omit-if-no-ref/ -+ pwm5m2_pins: pwm5m2-pins { -+ rockchip,pins = -+ /* pwm5_m2 */ -+ <4 RK_PC4 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm6 { -+ /omit-if-no-ref/ -+ pwm6m2_pins: pwm6m2-pins { -+ rockchip,pins = -+ /* pwm6_m2 */ -+ <4 RK_PC5 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pwm7 { -+ /omit-if-no-ref/ -+ pwm7m3_pins: pwm7m3-pins { -+ rockchip,pins = -+ /* pwm7_ir_m3 */ -+ <4 RK_PC6 11 &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdio { -+ /omit-if-no-ref/ -+ sdiom0_pins: sdiom0-pins { -+ rockchip,pins = -+ /* sdio_clk_m0 */ -+ <2 RK_PB3 2 &pcfg_pull_none>, -+ /* sdio_cmd_m0 */ -+ <2 RK_PB2 2 &pcfg_pull_none>, -+ /* sdio_d0_m0 */ -+ <2 RK_PA6 2 &pcfg_pull_none>, -+ /* sdio_d1_m0 */ -+ <2 RK_PA7 2 &pcfg_pull_none>, -+ /* sdio_d2_m0 */ -+ <2 RK_PB0 2 &pcfg_pull_none>, -+ /* sdio_d3_m0 */ -+ <2 RK_PB1 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ spi1 { -+ /omit-if-no-ref/ -+ spi1m0_pins: spi1m0-pins { -+ rockchip,pins = -+ /* spi1_clk_m0 */ -+ <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, -+ /* spi1_miso_m0 */ -+ <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, -+ /* spi1_mosi_m0 */ -+ <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi1m0_cs0: spi1m0-cs0 { -+ rockchip,pins = -+ /* spi1_cs0_m0 */ -+ <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi1m0_cs1: spi1m0-cs1 { -+ rockchip,pins = -+ /* spi1_cs1_m0 */ -+ <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ }; -+ -+ spi3 { -+ /omit-if-no-ref/ -+ spi3m0_pins: spi3m0-pins { -+ rockchip,pins = -+ /* spi3_clk_m0 */ -+ <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, -+ /* spi3_miso_m0 */ -+ <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, -+ /* spi3_mosi_m0 */ -+ <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi3m0_cs0: spi3m0-cs0 { -+ rockchip,pins = -+ /* spi3_cs0_m0 */ -+ <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ -+ /omit-if-no-ref/ -+ spi3m0_cs1: spi3m0-cs1 { -+ rockchip,pins = -+ /* spi3_cs1_m0 */ -+ <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; -+ }; -+ }; -+ -+ uart1 { -+ /omit-if-no-ref/ -+ uart1m0_xfer: uart1m0-xfer { -+ rockchip,pins = -+ /* uart1_rx_m0 */ -+ <2 RK_PB6 10 &pcfg_pull_up>, -+ /* uart1_tx_m0 */ -+ <2 RK_PB7 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart1m0_ctsn: uart1m0-ctsn { -+ rockchip,pins = -+ /* uart1m0_ctsn */ -+ <2 RK_PC1 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart1m0_rtsn: uart1m0-rtsn { -+ rockchip,pins = -+ /* uart1m0_rtsn */ -+ <2 RK_PC0 10 &pcfg_pull_none>; -+ }; -+ }; -+ -+ uart6 { -+ /omit-if-no-ref/ -+ uart6m0_xfer: uart6m0-xfer { -+ rockchip,pins = -+ /* uart6_rx_m0 */ -+ <2 RK_PA6 10 &pcfg_pull_up>, -+ /* uart6_tx_m0 */ -+ <2 RK_PA7 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart6m0_ctsn: uart6m0-ctsn { -+ rockchip,pins = -+ /* uart6m0_ctsn */ -+ <2 RK_PB1 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart6m0_rtsn: uart6m0-rtsn { -+ rockchip,pins = -+ /* uart6m0_rtsn */ -+ <2 RK_PB0 10 &pcfg_pull_none>; -+ }; -+ }; -+ -+ uart7 { -+ /omit-if-no-ref/ -+ uart7m0_xfer: uart7m0-xfer { -+ rockchip,pins = -+ /* uart7_rx_m0 */ -+ <2 RK_PB4 10 &pcfg_pull_up>, -+ /* uart7_tx_m0 */ -+ <2 RK_PB5 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart7m0_ctsn: uart7m0-ctsn { -+ rockchip,pins = -+ /* uart7m0_ctsn */ -+ <4 RK_PC6 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart7m0_rtsn: uart7m0-rtsn { -+ rockchip,pins = -+ /* uart7m0_rtsn */ -+ <4 RK_PC2 10 &pcfg_pull_none>; -+ }; -+ }; -+ -+ uart9 { -+ /omit-if-no-ref/ -+ uart9m0_xfer: uart9m0-xfer { -+ rockchip,pins = -+ /* uart9_rx_m0 */ -+ <2 RK_PC4 10 &pcfg_pull_up>, -+ /* uart9_tx_m0 */ -+ <2 RK_PC2 10 &pcfg_pull_up>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart9m0_ctsn: uart9m0-ctsn { -+ rockchip,pins = -+ /* uart9m0_ctsn */ -+ <4 RK_PC5 10 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ uart9m0_rtsn: uart9m0-rtsn { -+ rockchip,pins = -+ /* uart9m0_rtsn */ -+ <4 RK_PC4 10 &pcfg_pull_none>; -+ }; -+ }; -+}; ---- a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi -+++ /dev/null -@@ -1,516 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR MIT) --/* -- * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -- */ -- --#include --#include "rockchip-pinconf.dtsi" -- --/* -- * This file is auto generated by pin2dts tool, please keep these code -- * by adding changes at end of this file. -- */ --&pinctrl { -- clk32k { -- /omit-if-no-ref/ -- clk32k_out1: clk32k-out1 { -- rockchip,pins = -- /* clk32k_out1 */ -- <2 RK_PC5 1 &pcfg_pull_none>; -- }; -- -- }; -- -- eth0 { -- /omit-if-no-ref/ -- eth0_pins: eth0-pins { -- rockchip,pins = -- /* eth0_refclko_25m */ -- <2 RK_PC3 1 &pcfg_pull_none>; -- }; -- -- }; -- -- fspi { -- /omit-if-no-ref/ -- fspim1_pins: fspim1-pins { -- rockchip,pins = -- /* fspi_clk_m1 */ -- <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, -- /* fspi_cs0n_m1 */ -- <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, -- /* fspi_d0_m1 */ -- <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, -- /* fspi_d1_m1 */ -- <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, -- /* fspi_d2_m1 */ -- <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, -- /* fspi_d3_m1 */ -- <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; -- }; -- -- /omit-if-no-ref/ -- fspim1_cs1: fspim1-cs1 { -- rockchip,pins = -- /* fspi_cs1n_m1 */ -- <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; -- }; -- }; -- -- gmac0 { -- /omit-if-no-ref/ -- gmac0_miim: gmac0-miim { -- rockchip,pins = -- /* gmac0_mdc */ -- <4 RK_PC4 1 &pcfg_pull_none>, -- /* gmac0_mdio */ -- <4 RK_PC5 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac0_clkinout: gmac0-clkinout { -- rockchip,pins = -- /* gmac0_mclkinout */ -- <4 RK_PC3 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac0_rx_bus2: gmac0-rx-bus2 { -- rockchip,pins = -- /* gmac0_rxd0 */ -- <2 RK_PC1 1 &pcfg_pull_none>, -- /* gmac0_rxd1 */ -- <2 RK_PC2 1 &pcfg_pull_none>, -- /* gmac0_rxdv_crs */ -- <4 RK_PC2 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac0_tx_bus2: gmac0-tx-bus2 { -- rockchip,pins = -- /* gmac0_txd0 */ -- <2 RK_PB6 1 &pcfg_pull_none>, -- /* gmac0_txd1 */ -- <2 RK_PB7 1 &pcfg_pull_none>, -- /* gmac0_txen */ -- <2 RK_PC0 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac0_rgmii_clk: gmac0-rgmii-clk { -- rockchip,pins = -- /* gmac0_rxclk */ -- <2 RK_PB0 1 &pcfg_pull_none>, -- /* gmac0_txclk */ -- <2 RK_PB3 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac0_rgmii_bus: gmac0-rgmii-bus { -- rockchip,pins = -- /* gmac0_rxd2 */ -- <2 RK_PA6 1 &pcfg_pull_none>, -- /* gmac0_rxd3 */ -- <2 RK_PA7 1 &pcfg_pull_none>, -- /* gmac0_txd2 */ -- <2 RK_PB1 1 &pcfg_pull_none>, -- /* gmac0_txd3 */ -- <2 RK_PB2 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac0_ppsclk: gmac0-ppsclk { -- rockchip,pins = -- /* gmac0_ppsclk */ -- <2 RK_PC4 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac0_ppstring: gmac0-ppstring { -- rockchip,pins = -- /* gmac0_ppstring */ -- <2 RK_PB5 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac0_ptp_refclk: gmac0-ptp-refclk { -- rockchip,pins = -- /* gmac0_ptp_refclk */ -- <2 RK_PB4 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac0_txer: gmac0-txer { -- rockchip,pins = -- /* gmac0_txer */ -- <4 RK_PC6 1 &pcfg_pull_none>; -- }; -- -- }; -- -- hdmi { -- /omit-if-no-ref/ -- hdmim0_tx1_cec: hdmim0-tx1-cec { -- rockchip,pins = -- /* hdmim0_tx1_cec */ -- <2 RK_PC4 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim0_tx1_scl: hdmim0-tx1-scl { -- rockchip,pins = -- /* hdmim0_tx1_scl */ -- <2 RK_PB5 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim0_tx1_sda: hdmim0-tx1-sda { -- rockchip,pins = -- /* hdmim0_tx1_sda */ -- <2 RK_PB4 4 &pcfg_pull_none>; -- }; -- }; -- -- i2c0 { -- /omit-if-no-ref/ -- i2c0m1_xfer: i2c0m1-xfer { -- rockchip,pins = -- /* i2c0_scl_m1 */ -- <4 RK_PC5 9 &pcfg_pull_none_smt>, -- /* i2c0_sda_m1 */ -- <4 RK_PC6 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c2 { -- /omit-if-no-ref/ -- i2c2m1_xfer: i2c2m1-xfer { -- rockchip,pins = -- /* i2c2_scl_m1 */ -- <2 RK_PC1 9 &pcfg_pull_none_smt>, -- /* i2c2_sda_m1 */ -- <2 RK_PC0 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c3 { -- /omit-if-no-ref/ -- i2c3m3_xfer: i2c3m3-xfer { -- rockchip,pins = -- /* i2c3_scl_m3 */ -- <2 RK_PB2 9 &pcfg_pull_none_smt>, -- /* i2c3_sda_m3 */ -- <2 RK_PB3 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c4 { -- /omit-if-no-ref/ -- i2c4m1_xfer: i2c4m1-xfer { -- rockchip,pins = -- /* i2c4_scl_m1 */ -- <2 RK_PB5 9 &pcfg_pull_none_smt>, -- /* i2c4_sda_m1 */ -- <2 RK_PB4 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c5 { -- /omit-if-no-ref/ -- i2c5m4_xfer: i2c5m4-xfer { -- rockchip,pins = -- /* i2c5_scl_m4 */ -- <2 RK_PB6 9 &pcfg_pull_none_smt>, -- /* i2c5_sda_m4 */ -- <2 RK_PB7 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c6 { -- /omit-if-no-ref/ -- i2c6m2_xfer: i2c6m2-xfer { -- rockchip,pins = -- /* i2c6_scl_m2 */ -- <2 RK_PC3 9 &pcfg_pull_none_smt>, -- /* i2c6_sda_m2 */ -- <2 RK_PC2 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c7 { -- /omit-if-no-ref/ -- i2c7m1_xfer: i2c7m1-xfer { -- rockchip,pins = -- /* i2c7_scl_m1 */ -- <4 RK_PC3 9 &pcfg_pull_none_smt>, -- /* i2c7_sda_m1 */ -- <4 RK_PC4 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c8 { -- /omit-if-no-ref/ -- i2c8m1_xfer: i2c8m1-xfer { -- rockchip,pins = -- /* i2c8_scl_m1 */ -- <2 RK_PB0 9 &pcfg_pull_none_smt>, -- /* i2c8_sda_m1 */ -- <2 RK_PB1 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2s2 { -- /omit-if-no-ref/ -- i2s2m0_lrck: i2s2m0-lrck { -- rockchip,pins = -- /* i2s2m0_lrck */ -- <2 RK_PC0 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m0_mclk: i2s2m0-mclk { -- rockchip,pins = -- /* i2s2m0_mclk */ -- <2 RK_PB6 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m0_sclk: i2s2m0-sclk { -- rockchip,pins = -- /* i2s2m0_sclk */ -- <2 RK_PB7 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m0_sdi: i2s2m0-sdi { -- rockchip,pins = -- /* i2s2m0_sdi */ -- <2 RK_PC3 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m0_sdo: i2s2m0-sdo { -- rockchip,pins = -- /* i2s2m0_sdo */ -- <4 RK_PC3 2 &pcfg_pull_none>; -- }; -- }; -- -- pwm2 { -- /omit-if-no-ref/ -- pwm2m2_pins: pwm2m2-pins { -- rockchip,pins = -- /* pwm2_m2 */ -- <4 RK_PC2 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm4 { -- /omit-if-no-ref/ -- pwm4m1_pins: pwm4m1-pins { -- rockchip,pins = -- /* pwm4_m1 */ -- <4 RK_PC3 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm5 { -- /omit-if-no-ref/ -- pwm5m2_pins: pwm5m2-pins { -- rockchip,pins = -- /* pwm5_m2 */ -- <4 RK_PC4 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm6 { -- /omit-if-no-ref/ -- pwm6m2_pins: pwm6m2-pins { -- rockchip,pins = -- /* pwm6_m2 */ -- <4 RK_PC5 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm7 { -- /omit-if-no-ref/ -- pwm7m3_pins: pwm7m3-pins { -- rockchip,pins = -- /* pwm7_ir_m3 */ -- <4 RK_PC6 11 &pcfg_pull_none>; -- }; -- }; -- -- sdio { -- /omit-if-no-ref/ -- sdiom0_pins: sdiom0-pins { -- rockchip,pins = -- /* sdio_clk_m0 */ -- <2 RK_PB3 2 &pcfg_pull_none>, -- /* sdio_cmd_m0 */ -- <2 RK_PB2 2 &pcfg_pull_none>, -- /* sdio_d0_m0 */ -- <2 RK_PA6 2 &pcfg_pull_none>, -- /* sdio_d1_m0 */ -- <2 RK_PA7 2 &pcfg_pull_none>, -- /* sdio_d2_m0 */ -- <2 RK_PB0 2 &pcfg_pull_none>, -- /* sdio_d3_m0 */ -- <2 RK_PB1 2 &pcfg_pull_none>; -- }; -- }; -- -- spi1 { -- /omit-if-no-ref/ -- spi1m0_pins: spi1m0-pins { -- rockchip,pins = -- /* spi1_clk_m0 */ -- <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, -- /* spi1_miso_m0 */ -- <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, -- /* spi1_mosi_m0 */ -- <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi1m0_cs0: spi1m0-cs0 { -- rockchip,pins = -- /* spi1_cs0_m0 */ -- <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi1m0_cs1: spi1m0-cs1 { -- rockchip,pins = -- /* spi1_cs1_m0 */ -- <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; -- }; -- }; -- -- spi3 { -- /omit-if-no-ref/ -- spi3m0_pins: spi3m0-pins { -- rockchip,pins = -- /* spi3_clk_m0 */ -- <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, -- /* spi3_miso_m0 */ -- <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, -- /* spi3_mosi_m0 */ -- <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi3m0_cs0: spi3m0-cs0 { -- rockchip,pins = -- /* spi3_cs0_m0 */ -- <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi3m0_cs1: spi3m0-cs1 { -- rockchip,pins = -- /* spi3_cs1_m0 */ -- <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; -- }; -- }; -- -- uart1 { -- /omit-if-no-ref/ -- uart1m0_xfer: uart1m0-xfer { -- rockchip,pins = -- /* uart1_rx_m0 */ -- <2 RK_PB6 10 &pcfg_pull_up>, -- /* uart1_tx_m0 */ -- <2 RK_PB7 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart1m0_ctsn: uart1m0-ctsn { -- rockchip,pins = -- /* uart1m0_ctsn */ -- <2 RK_PC1 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart1m0_rtsn: uart1m0-rtsn { -- rockchip,pins = -- /* uart1m0_rtsn */ -- <2 RK_PC0 10 &pcfg_pull_none>; -- }; -- }; -- -- uart6 { -- /omit-if-no-ref/ -- uart6m0_xfer: uart6m0-xfer { -- rockchip,pins = -- /* uart6_rx_m0 */ -- <2 RK_PA6 10 &pcfg_pull_up>, -- /* uart6_tx_m0 */ -- <2 RK_PA7 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart6m0_ctsn: uart6m0-ctsn { -- rockchip,pins = -- /* uart6m0_ctsn */ -- <2 RK_PB1 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart6m0_rtsn: uart6m0-rtsn { -- rockchip,pins = -- /* uart6m0_rtsn */ -- <2 RK_PB0 10 &pcfg_pull_none>; -- }; -- }; -- -- uart7 { -- /omit-if-no-ref/ -- uart7m0_xfer: uart7m0-xfer { -- rockchip,pins = -- /* uart7_rx_m0 */ -- <2 RK_PB4 10 &pcfg_pull_up>, -- /* uart7_tx_m0 */ -- <2 RK_PB5 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart7m0_ctsn: uart7m0-ctsn { -- rockchip,pins = -- /* uart7m0_ctsn */ -- <4 RK_PC6 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart7m0_rtsn: uart7m0-rtsn { -- rockchip,pins = -- /* uart7m0_rtsn */ -- <4 RK_PC2 10 &pcfg_pull_none>; -- }; -- }; -- -- uart9 { -- /omit-if-no-ref/ -- uart9m0_xfer: uart9m0-xfer { -- rockchip,pins = -- /* uart9_rx_m0 */ -- <2 RK_PC4 10 &pcfg_pull_up>, -- /* uart9_tx_m0 */ -- <2 RK_PC2 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart9m0_ctsn: uart9m0-ctsn { -- rockchip,pins = -- /* uart9m0_ctsn */ -- <4 RK_PC5 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart9m0_rtsn: uart9m0-rtsn { -- rockchip,pins = -- /* uart9m0_rtsn */ -- <4 RK_PC4 10 &pcfg_pull_none>; -- }; -- }; --}; ---- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi -+++ /dev/null -@@ -1,3447 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR MIT) --/* -- * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -- */ -- --#include --#include "rockchip-pinconf.dtsi" -- --/* -- * This file is auto generated by pin2dts tool, please keep these code -- * by adding changes at end of this file. -- */ --&pinctrl { -- auddsm { -- /omit-if-no-ref/ -- auddsm_pins: auddsm-pins { -- rockchip,pins = -- /* auddsm_ln */ -- <3 RK_PA1 4 &pcfg_pull_none>, -- /* auddsm_lp */ -- <3 RK_PA2 4 &pcfg_pull_none>, -- /* auddsm_rn */ -- <3 RK_PA3 4 &pcfg_pull_none>, -- /* auddsm_rp */ -- <3 RK_PA4 4 &pcfg_pull_none>; -- }; -- }; -- -- bt1120 { -- /omit-if-no-ref/ -- bt1120_pins: bt1120-pins { -- rockchip,pins = -- /* bt1120_clkout */ -- <4 RK_PB0 2 &pcfg_pull_none>, -- /* bt1120_d0 */ -- <4 RK_PA0 2 &pcfg_pull_none>, -- /* bt1120_d1 */ -- <4 RK_PA1 2 &pcfg_pull_none>, -- /* bt1120_d2 */ -- <4 RK_PA2 2 &pcfg_pull_none>, -- /* bt1120_d3 */ -- <4 RK_PA3 2 &pcfg_pull_none>, -- /* bt1120_d4 */ -- <4 RK_PA4 2 &pcfg_pull_none>, -- /* bt1120_d5 */ -- <4 RK_PA5 2 &pcfg_pull_none>, -- /* bt1120_d6 */ -- <4 RK_PA6 2 &pcfg_pull_none>, -- /* bt1120_d7 */ -- <4 RK_PA7 2 &pcfg_pull_none>, -- /* bt1120_d8 */ -- <4 RK_PB2 2 &pcfg_pull_none>, -- /* bt1120_d9 */ -- <4 RK_PB3 2 &pcfg_pull_none>, -- /* bt1120_d10 */ -- <4 RK_PB4 2 &pcfg_pull_none>, -- /* bt1120_d11 */ -- <4 RK_PB5 2 &pcfg_pull_none>, -- /* bt1120_d12 */ -- <4 RK_PB6 2 &pcfg_pull_none>, -- /* bt1120_d13 */ -- <4 RK_PB7 2 &pcfg_pull_none>, -- /* bt1120_d14 */ -- <4 RK_PC0 2 &pcfg_pull_none>, -- /* bt1120_d15 */ -- <4 RK_PC1 2 &pcfg_pull_none>; -- }; -- }; -- -- can0 { -- /omit-if-no-ref/ -- can0m0_pins: can0m0-pins { -- rockchip,pins = -- /* can0_rx_m0 */ -- <0 RK_PC0 11 &pcfg_pull_none>, -- /* can0_tx_m0 */ -- <0 RK_PB7 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- can0m1_pins: can0m1-pins { -- rockchip,pins = -- /* can0_rx_m1 */ -- <4 RK_PD5 9 &pcfg_pull_none>, -- /* can0_tx_m1 */ -- <4 RK_PD4 9 &pcfg_pull_none>; -- }; -- }; -- -- can1 { -- /omit-if-no-ref/ -- can1m0_pins: can1m0-pins { -- rockchip,pins = -- /* can1_rx_m0 */ -- <3 RK_PB5 9 &pcfg_pull_none>, -- /* can1_tx_m0 */ -- <3 RK_PB6 9 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- can1m1_pins: can1m1-pins { -- rockchip,pins = -- /* can1_rx_m1 */ -- <4 RK_PB2 12 &pcfg_pull_none>, -- /* can1_tx_m1 */ -- <4 RK_PB3 12 &pcfg_pull_none>; -- }; -- }; -- -- can2 { -- /omit-if-no-ref/ -- can2m0_pins: can2m0-pins { -- rockchip,pins = -- /* can2_rx_m0 */ -- <3 RK_PC4 9 &pcfg_pull_none>, -- /* can2_tx_m0 */ -- <3 RK_PC5 9 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- can2m1_pins: can2m1-pins { -- rockchip,pins = -- /* can2_rx_m1 */ -- <0 RK_PD4 10 &pcfg_pull_none>, -- /* can2_tx_m1 */ -- <0 RK_PD5 10 &pcfg_pull_none>; -- }; -- }; -- -- cif { -- /omit-if-no-ref/ -- cif_clk: cif-clk { -- rockchip,pins = -- /* cif_clkout */ -- <4 RK_PB4 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- cif_dvp_clk: cif-dvp-clk { -- rockchip,pins = -- /* cif_clkin */ -- <4 RK_PB0 1 &pcfg_pull_none>, -- /* cif_href */ -- <4 RK_PB2 1 &pcfg_pull_none>, -- /* cif_vsync */ -- <4 RK_PB3 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- cif_dvp_bus16: cif-dvp-bus16 { -- rockchip,pins = -- /* cif_d8 */ -- <3 RK_PC4 1 &pcfg_pull_none>, -- /* cif_d9 */ -- <3 RK_PC5 1 &pcfg_pull_none>, -- /* cif_d10 */ -- <3 RK_PC6 1 &pcfg_pull_none>, -- /* cif_d11 */ -- <3 RK_PC7 1 &pcfg_pull_none>, -- /* cif_d12 */ -- <3 RK_PD0 1 &pcfg_pull_none>, -- /* cif_d13 */ -- <3 RK_PD1 1 &pcfg_pull_none>, -- /* cif_d14 */ -- <3 RK_PD2 1 &pcfg_pull_none>, -- /* cif_d15 */ -- <3 RK_PD3 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- cif_dvp_bus8: cif-dvp-bus8 { -- rockchip,pins = -- /* cif_d0 */ -- <4 RK_PA0 1 &pcfg_pull_none>, -- /* cif_d1 */ -- <4 RK_PA1 1 &pcfg_pull_none>, -- /* cif_d2 */ -- <4 RK_PA2 1 &pcfg_pull_none>, -- /* cif_d3 */ -- <4 RK_PA3 1 &pcfg_pull_none>, -- /* cif_d4 */ -- <4 RK_PA4 1 &pcfg_pull_none>, -- /* cif_d5 */ -- <4 RK_PA5 1 &pcfg_pull_none>, -- /* cif_d6 */ -- <4 RK_PA6 1 &pcfg_pull_none>, -- /* cif_d7 */ -- <4 RK_PA7 1 &pcfg_pull_none>; -- }; -- }; -- -- clk32k { -- /omit-if-no-ref/ -- clk32k_in: clk32k-in { -- rockchip,pins = -- /* clk32k_in */ -- <0 RK_PB2 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- clk32k_out0: clk32k-out0 { -- rockchip,pins = -- /* clk32k_out0 */ -- <0 RK_PB2 2 &pcfg_pull_none>; -- }; -- }; -- -- cpu { -- /omit-if-no-ref/ -- cpu_pins: cpu-pins { -- rockchip,pins = -- /* cpu_big0_avs */ -- <0 RK_PD1 2 &pcfg_pull_none>, -- /* cpu_big1_avs */ -- <0 RK_PD5 2 &pcfg_pull_none>; -- }; -- }; -- -- ddrphych0 { -- /omit-if-no-ref/ -- ddrphych0_pins: ddrphych0-pins { -- rockchip,pins = -- /* ddrphych0_dtb0 */ -- <4 RK_PA0 7 &pcfg_pull_none>, -- /* ddrphych0_dtb1 */ -- <4 RK_PA1 7 &pcfg_pull_none>, -- /* ddrphych0_dtb2 */ -- <4 RK_PA2 7 &pcfg_pull_none>, -- /* ddrphych0_dtb3 */ -- <4 RK_PA3 7 &pcfg_pull_none>; -- }; -- }; -- -- ddrphych1 { -- /omit-if-no-ref/ -- ddrphych1_pins: ddrphych1-pins { -- rockchip,pins = -- /* ddrphych1_dtb0 */ -- <4 RK_PA4 7 &pcfg_pull_none>, -- /* ddrphych1_dtb1 */ -- <4 RK_PA5 7 &pcfg_pull_none>, -- /* ddrphych1_dtb2 */ -- <4 RK_PA6 7 &pcfg_pull_none>, -- /* ddrphych1_dtb3 */ -- <4 RK_PA7 7 &pcfg_pull_none>; -- }; -- }; -- -- ddrphych2 { -- /omit-if-no-ref/ -- ddrphych2_pins: ddrphych2-pins { -- rockchip,pins = -- /* ddrphych2_dtb0 */ -- <4 RK_PB0 7 &pcfg_pull_none>, -- /* ddrphych2_dtb1 */ -- <4 RK_PB1 7 &pcfg_pull_none>, -- /* ddrphych2_dtb2 */ -- <4 RK_PB2 7 &pcfg_pull_none>, -- /* ddrphych2_dtb3 */ -- <4 RK_PB3 7 &pcfg_pull_none>; -- }; -- }; -- -- ddrphych3 { -- /omit-if-no-ref/ -- ddrphych3_pins: ddrphych3-pins { -- rockchip,pins = -- /* ddrphych3_dtb0 */ -- <4 RK_PB4 7 &pcfg_pull_none>, -- /* ddrphych3_dtb1 */ -- <4 RK_PB5 7 &pcfg_pull_none>, -- /* ddrphych3_dtb2 */ -- <4 RK_PB6 7 &pcfg_pull_none>, -- /* ddrphych3_dtb3 */ -- <4 RK_PB7 7 &pcfg_pull_none>; -- }; -- }; -- -- dp0 { -- /omit-if-no-ref/ -- dp0m0_pins: dp0m0-pins { -- rockchip,pins = -- /* dp0_hpdin_m0 */ -- <4 RK_PB4 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- dp0m1_pins: dp0m1-pins { -- rockchip,pins = -- /* dp0_hpdin_m1 */ -- <0 RK_PC4 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- dp0m2_pins: dp0m2-pins { -- rockchip,pins = -- /* dp0_hpdin_m2 */ -- <1 RK_PA0 5 &pcfg_pull_none>; -- }; -- }; -- -- dp1 { -- /omit-if-no-ref/ -- dp1m0_pins: dp1m0-pins { -- rockchip,pins = -- /* dp1_hpdin_m0 */ -- <3 RK_PD5 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- dp1m1_pins: dp1m1-pins { -- rockchip,pins = -- /* dp1_hpdin_m1 */ -- <0 RK_PC5 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- dp1m2_pins: dp1m2-pins { -- rockchip,pins = -- /* dp1_hpdin_m2 */ -- <1 RK_PA1 5 &pcfg_pull_none>; -- }; -- }; -- -- emmc { -- /omit-if-no-ref/ -- emmc_rstnout: emmc-rstnout { -- rockchip,pins = -- /* emmc_rstn */ -- <2 RK_PA3 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- emmc_bus8: emmc-bus8 { -- rockchip,pins = -- /* emmc_d0 */ -- <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, -- /* emmc_d1 */ -- <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, -- /* emmc_d2 */ -- <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, -- /* emmc_d3 */ -- <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, -- /* emmc_d4 */ -- <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, -- /* emmc_d5 */ -- <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, -- /* emmc_d6 */ -- <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, -- /* emmc_d7 */ -- <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; -- }; -- -- /omit-if-no-ref/ -- emmc_clk: emmc-clk { -- rockchip,pins = -- /* emmc_clkout */ -- <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; -- }; -- -- /omit-if-no-ref/ -- emmc_cmd: emmc-cmd { -- rockchip,pins = -- /* emmc_cmd */ -- <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; -- }; -- -- /omit-if-no-ref/ -- emmc_data_strobe: emmc-data-strobe { -- rockchip,pins = -- /* emmc_data_strobe */ -- <2 RK_PA2 1 &pcfg_pull_down>; -- }; -- }; -- -- eth1 { -- /omit-if-no-ref/ -- eth1_pins: eth1-pins { -- rockchip,pins = -- /* eth1_refclko_25m */ -- <3 RK_PA6 1 &pcfg_pull_none>; -- }; -- }; -- -- fspi { -- /omit-if-no-ref/ -- fspim0_pins: fspim0-pins { -- rockchip,pins = -- /* fspi_clk_m0 */ -- <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>, -- /* fspi_cs0n_m0 */ -- <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>, -- /* fspi_d0_m0 */ -- <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>, -- /* fspi_d1_m0 */ -- <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>, -- /* fspi_d2_m0 */ -- <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>, -- /* fspi_d3_m0 */ -- <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>; -- }; -- -- /omit-if-no-ref/ -- fspim0_cs1: fspim0-cs1 { -- rockchip,pins = -- /* fspi_cs1n_m0 */ -- <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; -- }; -- -- /omit-if-no-ref/ -- fspim2_pins: fspim2-pins { -- rockchip,pins = -- /* fspi_clk_m2 */ -- <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>, -- /* fspi_cs0n_m2 */ -- <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>, -- /* fspi_d0_m2 */ -- <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>, -- /* fspi_d1_m2 */ -- <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, -- /* fspi_d2_m2 */ -- <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, -- /* fspi_d3_m2 */ -- <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>; -- }; -- -- /omit-if-no-ref/ -- fspim2_cs1: fspim2-cs1 { -- rockchip,pins = -- /* fspi_cs1n_m2 */ -- <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>; -- }; -- }; -- -- gmac1 { -- /omit-if-no-ref/ -- gmac1_miim: gmac1-miim { -- rockchip,pins = -- /* gmac1_mdc */ -- <3 RK_PC2 1 &pcfg_pull_none>, -- /* gmac1_mdio */ -- <3 RK_PC3 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac1_clkinout: gmac1-clkinout { -- rockchip,pins = -- /* gmac1_mclkinout */ -- <3 RK_PB6 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac1_rx_bus2: gmac1-rx-bus2 { -- rockchip,pins = -- /* gmac1_rxd0 */ -- <3 RK_PA7 1 &pcfg_pull_none>, -- /* gmac1_rxd1 */ -- <3 RK_PB0 1 &pcfg_pull_none>, -- /* gmac1_rxdv_crs */ -- <3 RK_PB1 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac1_tx_bus2: gmac1-tx-bus2 { -- rockchip,pins = -- /* gmac1_txd0 */ -- <3 RK_PB3 1 &pcfg_pull_none>, -- /* gmac1_txd1 */ -- <3 RK_PB4 1 &pcfg_pull_none>, -- /* gmac1_txen */ -- <3 RK_PB5 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac1_rgmii_clk: gmac1-rgmii-clk { -- rockchip,pins = -- /* gmac1_rxclk */ -- <3 RK_PA5 1 &pcfg_pull_none>, -- /* gmac1_txclk */ -- <3 RK_PA4 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac1_rgmii_bus: gmac1-rgmii-bus { -- rockchip,pins = -- /* gmac1_rxd2 */ -- <3 RK_PA2 1 &pcfg_pull_none>, -- /* gmac1_rxd3 */ -- <3 RK_PA3 1 &pcfg_pull_none>, -- /* gmac1_txd2 */ -- <3 RK_PA0 1 &pcfg_pull_none>, -- /* gmac1_txd3 */ -- <3 RK_PA1 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac1_ppsclk: gmac1-ppsclk { -- rockchip,pins = -- /* gmac1_ppsclk */ -- <3 RK_PC1 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac1_ppstrig: gmac1-ppstrig { -- rockchip,pins = -- /* gmac1_ppstrig */ -- <3 RK_PC0 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { -- rockchip,pins = -- /* gmac1_ptp_ref_clk */ -- <3 RK_PB7 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- gmac1_txer: gmac1-txer { -- rockchip,pins = -- /* gmac1_txer */ -- <3 RK_PB2 1 &pcfg_pull_none>; -- }; -- }; -- -- gpu { -- /omit-if-no-ref/ -- gpu_pins: gpu-pins { -- rockchip,pins = -- /* gpu_avs */ -- <0 RK_PC5 2 &pcfg_pull_none>; -- }; -- }; -- -- hdmi { -- /omit-if-no-ref/ -- hdmim0_rx_cec: hdmim0-rx-cec { -- rockchip,pins = -- /* hdmim0_rx_cec */ -- <4 RK_PB5 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim0_rx_hpdin: hdmim0-rx-hpdin { -- rockchip,pins = -- /* hdmim0_rx_hpdin */ -- <4 RK_PB6 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim0_rx_scl: hdmim0-rx-scl { -- rockchip,pins = -- /* hdmim0_rx_scl */ -- <0 RK_PD2 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim0_rx_sda: hdmim0-rx-sda { -- rockchip,pins = -- /* hdmim0_rx_sda */ -- <0 RK_PD1 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim0_tx0_cec: hdmim0-tx0-cec { -- rockchip,pins = -- /* hdmim0_tx0_cec */ -- <4 RK_PC1 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim0_tx0_hpd: hdmim0-tx0-hpd { -- rockchip,pins = -- /* hdmim0_tx0_hpd */ -- <1 RK_PA5 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim0_tx0_scl: hdmim0-tx0-scl { -- rockchip,pins = -- /* hdmim0_tx0_scl */ -- <4 RK_PB7 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim0_tx0_sda: hdmim0-tx0-sda { -- rockchip,pins = -- /* hdmim0_tx0_sda */ -- <4 RK_PC0 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim0_tx1_hpd: hdmim0-tx1-hpd { -- rockchip,pins = -- /* hdmim0_tx1_hpd */ -- <1 RK_PA6 5 &pcfg_pull_none>; -- }; -- /omit-if-no-ref/ -- hdmim1_rx_cec: hdmim1-rx-cec { -- rockchip,pins = -- /* hdmim1_rx_cec */ -- <3 RK_PD1 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim1_rx_hpdin: hdmim1-rx-hpdin { -- rockchip,pins = -- /* hdmim1_rx_hpdin */ -- <3 RK_PD4 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim1_rx_scl: hdmim1-rx-scl { -- rockchip,pins = -- /* hdmim1_rx_scl */ -- <3 RK_PD2 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim1_rx_sda: hdmim1-rx-sda { -- rockchip,pins = -- /* hdmim1_rx_sda */ -- <3 RK_PD3 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim1_tx0_cec: hdmim1-tx0-cec { -- rockchip,pins = -- /* hdmim1_tx0_cec */ -- <0 RK_PD1 13 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim1_tx0_hpd: hdmim1-tx0-hpd { -- rockchip,pins = -- /* hdmim1_tx0_hpd */ -- <3 RK_PD4 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim1_tx0_scl: hdmim1-tx0-scl { -- rockchip,pins = -- /* hdmim1_tx0_scl */ -- <0 RK_PD5 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim1_tx0_sda: hdmim1-tx0-sda { -- rockchip,pins = -- /* hdmim1_tx0_sda */ -- <0 RK_PD4 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim1_tx1_cec: hdmim1-tx1-cec { -- rockchip,pins = -- /* hdmim1_tx1_cec */ -- <0 RK_PD2 13 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim1_tx1_hpd: hdmim1-tx1-hpd { -- rockchip,pins = -- /* hdmim1_tx1_hpd */ -- <3 RK_PB7 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim1_tx1_scl: hdmim1-tx1-scl { -- rockchip,pins = -- /* hdmim1_tx1_scl */ -- <3 RK_PC6 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim1_tx1_sda: hdmim1-tx1-sda { -- rockchip,pins = -- /* hdmim1_tx1_sda */ -- <3 RK_PC5 5 &pcfg_pull_none>; -- }; -- /omit-if-no-ref/ -- hdmim2_rx_cec: hdmim2-rx-cec { -- rockchip,pins = -- /* hdmim2_rx_cec */ -- <1 RK_PB7 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim2_rx_hpdin: hdmim2-rx-hpdin { -- rockchip,pins = -- /* hdmim2_rx_hpdin */ -- <1 RK_PB6 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim2_rx_scl: hdmim2-rx-scl { -- rockchip,pins = -- /* hdmim2_rx_scl */ -- <1 RK_PD6 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim2_rx_sda: hdmim2-rx-sda { -- rockchip,pins = -- /* hdmim2_rx_sda */ -- <1 RK_PD7 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim2_tx0_scl: hdmim2-tx0-scl { -- rockchip,pins = -- /* hdmim2_tx0_scl */ -- <3 RK_PC7 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim2_tx0_sda: hdmim2-tx0-sda { -- rockchip,pins = -- /* hdmim2_tx0_sda */ -- <3 RK_PD0 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim2_tx1_cec: hdmim2-tx1-cec { -- rockchip,pins = -- /* hdmim2_tx1_cec */ -- <3 RK_PC4 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim2_tx1_scl: hdmim2-tx1-scl { -- rockchip,pins = -- /* hdmim2_tx1_scl */ -- <1 RK_PA4 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmim2_tx1_sda: hdmim2-tx1-sda { -- rockchip,pins = -- /* hdmim2_tx1_sda */ -- <1 RK_PA3 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmi_debug0: hdmi-debug0 { -- rockchip,pins = -- /* hdmi_debug0 */ -- <1 RK_PA7 7 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmi_debug1: hdmi-debug1 { -- rockchip,pins = -- /* hdmi_debug1 */ -- <1 RK_PB0 7 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmi_debug2: hdmi-debug2 { -- rockchip,pins = -- /* hdmi_debug2 */ -- <1 RK_PB1 7 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmi_debug3: hdmi-debug3 { -- rockchip,pins = -- /* hdmi_debug3 */ -- <1 RK_PB2 7 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmi_debug4: hdmi-debug4 { -- rockchip,pins = -- /* hdmi_debug4 */ -- <1 RK_PB3 7 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmi_debug5: hdmi-debug5 { -- rockchip,pins = -- /* hdmi_debug5 */ -- <1 RK_PB4 7 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- hdmi_debug6: hdmi-debug6 { -- rockchip,pins = -- /* hdmi_debug6 */ -- <1 RK_PA0 7 &pcfg_pull_none>; -- }; -- }; -- -- i2c0 { -- /omit-if-no-ref/ -- i2c0m0_xfer: i2c0m0-xfer { -- rockchip,pins = -- /* i2c0_scl_m0 */ -- <0 RK_PB3 2 &pcfg_pull_none_smt>, -- /* i2c0_sda_m0 */ -- <0 RK_PA6 2 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c0m2_xfer: i2c0m2-xfer { -- rockchip,pins = -- /* i2c0_scl_m2 */ -- <0 RK_PD1 3 &pcfg_pull_none_smt>, -- /* i2c0_sda_m2 */ -- <0 RK_PD2 3 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c1 { -- /omit-if-no-ref/ -- i2c1m0_xfer: i2c1m0-xfer { -- rockchip,pins = -- /* i2c1_scl_m0 */ -- <0 RK_PB5 9 &pcfg_pull_none_smt>, -- /* i2c1_sda_m0 */ -- <0 RK_PB6 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c1m1_xfer: i2c1m1-xfer { -- rockchip,pins = -- /* i2c1_scl_m1 */ -- <0 RK_PB0 2 &pcfg_pull_none_smt>, -- /* i2c1_sda_m1 */ -- <0 RK_PB1 2 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c1m2_xfer: i2c1m2-xfer { -- rockchip,pins = -- /* i2c1_scl_m2 */ -- <0 RK_PD4 9 &pcfg_pull_none_smt>, -- /* i2c1_sda_m2 */ -- <0 RK_PD5 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c1m3_xfer: i2c1m3-xfer { -- rockchip,pins = -- /* i2c1_scl_m3 */ -- <2 RK_PD4 9 &pcfg_pull_none_smt>, -- /* i2c1_sda_m3 */ -- <2 RK_PD5 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c1m4_xfer: i2c1m4-xfer { -- rockchip,pins = -- /* i2c1_scl_m4 */ -- <1 RK_PD2 9 &pcfg_pull_none_smt>, -- /* i2c1_sda_m4 */ -- <1 RK_PD3 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c2 { -- /omit-if-no-ref/ -- i2c2m0_xfer: i2c2m0-xfer { -- rockchip,pins = -- /* i2c2_scl_m0 */ -- <0 RK_PB7 9 &pcfg_pull_none_smt>, -- /* i2c2_sda_m0 */ -- <0 RK_PC0 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c2m2_xfer: i2c2m2-xfer { -- rockchip,pins = -- /* i2c2_scl_m2 */ -- <2 RK_PA3 9 &pcfg_pull_none_smt>, -- /* i2c2_sda_m2 */ -- <2 RK_PA2 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c2m3_xfer: i2c2m3-xfer { -- rockchip,pins = -- /* i2c2_scl_m3 */ -- <1 RK_PC5 9 &pcfg_pull_none_smt>, -- /* i2c2_sda_m3 */ -- <1 RK_PC4 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c2m4_xfer: i2c2m4-xfer { -- rockchip,pins = -- /* i2c2_scl_m4 */ -- <1 RK_PA1 9 &pcfg_pull_none_smt>, -- /* i2c2_sda_m4 */ -- <1 RK_PA0 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c3 { -- /omit-if-no-ref/ -- i2c3m0_xfer: i2c3m0-xfer { -- rockchip,pins = -- /* i2c3_scl_m0 */ -- <1 RK_PC1 9 &pcfg_pull_none_smt>, -- /* i2c3_sda_m0 */ -- <1 RK_PC0 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c3m1_xfer: i2c3m1-xfer { -- rockchip,pins = -- /* i2c3_scl_m1 */ -- <3 RK_PB7 9 &pcfg_pull_none_smt>, -- /* i2c3_sda_m1 */ -- <3 RK_PC0 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c3m2_xfer: i2c3m2-xfer { -- rockchip,pins = -- /* i2c3_scl_m2 */ -- <4 RK_PA4 9 &pcfg_pull_none_smt>, -- /* i2c3_sda_m2 */ -- <4 RK_PA5 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c3m4_xfer: i2c3m4-xfer { -- rockchip,pins = -- /* i2c3_scl_m4 */ -- <4 RK_PD0 9 &pcfg_pull_none_smt>, -- /* i2c3_sda_m4 */ -- <4 RK_PD1 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c4 { -- /omit-if-no-ref/ -- i2c4m0_xfer: i2c4m0-xfer { -- rockchip,pins = -- /* i2c4_scl_m0 */ -- <3 RK_PA6 9 &pcfg_pull_none_smt>, -- /* i2c4_sda_m0 */ -- <3 RK_PA5 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c4m2_xfer: i2c4m2-xfer { -- rockchip,pins = -- /* i2c4_scl_m2 */ -- <0 RK_PC5 9 &pcfg_pull_none_smt>, -- /* i2c4_sda_m2 */ -- <0 RK_PC4 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c4m3_xfer: i2c4m3-xfer { -- rockchip,pins = -- /* i2c4_scl_m3 */ -- <1 RK_PA3 9 &pcfg_pull_none_smt>, -- /* i2c4_sda_m3 */ -- <1 RK_PA2 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c4m4_xfer: i2c4m4-xfer { -- rockchip,pins = -- /* i2c4_scl_m4 */ -- <1 RK_PC7 9 &pcfg_pull_none_smt>, -- /* i2c4_sda_m4 */ -- <1 RK_PC6 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c5 { -- /omit-if-no-ref/ -- i2c5m0_xfer: i2c5m0-xfer { -- rockchip,pins = -- /* i2c5_scl_m0 */ -- <3 RK_PC7 9 &pcfg_pull_none_smt>, -- /* i2c5_sda_m0 */ -- <3 RK_PD0 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c5m1_xfer: i2c5m1-xfer { -- rockchip,pins = -- /* i2c5_scl_m1 */ -- <4 RK_PB6 9 &pcfg_pull_none_smt>, -- /* i2c5_sda_m1 */ -- <4 RK_PB7 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c5m2_xfer: i2c5m2-xfer { -- rockchip,pins = -- /* i2c5_scl_m2 */ -- <4 RK_PA6 9 &pcfg_pull_none_smt>, -- /* i2c5_sda_m2 */ -- <4 RK_PA7 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c5m3_xfer: i2c5m3-xfer { -- rockchip,pins = -- /* i2c5_scl_m3 */ -- <1 RK_PB6 9 &pcfg_pull_none_smt>, -- /* i2c5_sda_m3 */ -- <1 RK_PB7 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c6 { -- /omit-if-no-ref/ -- i2c6m0_xfer: i2c6m0-xfer { -- rockchip,pins = -- /* i2c6_scl_m0 */ -- <0 RK_PD0 9 &pcfg_pull_none_smt>, -- /* i2c6_sda_m0 */ -- <0 RK_PC7 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c6m1_xfer: i2c6m1-xfer { -- rockchip,pins = -- /* i2c6_scl_m1 */ -- <1 RK_PC3 9 &pcfg_pull_none_smt>, -- /* i2c6_sda_m1 */ -- <1 RK_PC2 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c6m3_xfer: i2c6m3-xfer { -- rockchip,pins = -- /* i2c6_scl_m3 */ -- <4 RK_PB1 9 &pcfg_pull_none_smt>, -- /* i2c6_sda_m3 */ -- <4 RK_PB0 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c6m4_xfer: i2c6m4-xfer { -- rockchip,pins = -- /* i2c6_scl_m4 */ -- <3 RK_PA1 9 &pcfg_pull_none_smt>, -- /* i2c6_sda_m4 */ -- <3 RK_PA0 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c7 { -- /omit-if-no-ref/ -- i2c7m0_xfer: i2c7m0-xfer { -- rockchip,pins = -- /* i2c7_scl_m0 */ -- <1 RK_PD0 9 &pcfg_pull_none_smt>, -- /* i2c7_sda_m0 */ -- <1 RK_PD1 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c7m2_xfer: i2c7m2-xfer { -- rockchip,pins = -- /* i2c7_scl_m2 */ -- <3 RK_PD2 9 &pcfg_pull_none_smt>, -- /* i2c7_sda_m2 */ -- <3 RK_PD3 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c7m3_xfer: i2c7m3-xfer { -- rockchip,pins = -- /* i2c7_scl_m3 */ -- <4 RK_PB2 9 &pcfg_pull_none_smt>, -- /* i2c7_sda_m3 */ -- <4 RK_PB3 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2c8 { -- /omit-if-no-ref/ -- i2c8m0_xfer: i2c8m0-xfer { -- rockchip,pins = -- /* i2c8_scl_m0 */ -- <4 RK_PD2 9 &pcfg_pull_none_smt>, -- /* i2c8_sda_m0 */ -- <4 RK_PD3 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c8m2_xfer: i2c8m2-xfer { -- rockchip,pins = -- /* i2c8_scl_m2 */ -- <1 RK_PD6 9 &pcfg_pull_none_smt>, -- /* i2c8_sda_m2 */ -- <1 RK_PD7 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c8m3_xfer: i2c8m3-xfer { -- rockchip,pins = -- /* i2c8_scl_m3 */ -- <4 RK_PC0 9 &pcfg_pull_none_smt>, -- /* i2c8_sda_m3 */ -- <4 RK_PC1 9 &pcfg_pull_none_smt>; -- }; -- -- /omit-if-no-ref/ -- i2c8m4_xfer: i2c8m4-xfer { -- rockchip,pins = -- /* i2c8_scl_m4 */ -- <3 RK_PC2 9 &pcfg_pull_none_smt>, -- /* i2c8_sda_m4 */ -- <3 RK_PC3 9 &pcfg_pull_none_smt>; -- }; -- }; -- -- i2s0 { -- /omit-if-no-ref/ -- i2s0_lrck: i2s0-lrck { -- rockchip,pins = -- /* i2s0_lrck */ -- <1 RK_PC5 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s0_mclk: i2s0-mclk { -- rockchip,pins = -- /* i2s0_mclk */ -- <1 RK_PC2 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s0_sclk: i2s0-sclk { -- rockchip,pins = -- /* i2s0_sclk */ -- <1 RK_PC3 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s0_sdi0: i2s0-sdi0 { -- rockchip,pins = -- /* i2s0_sdi0 */ -- <1 RK_PD4 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s0_sdi1: i2s0-sdi1 { -- rockchip,pins = -- /* i2s0_sdi1 */ -- <1 RK_PD3 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s0_sdi2: i2s0-sdi2 { -- rockchip,pins = -- /* i2s0_sdi2 */ -- <1 RK_PD2 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s0_sdi3: i2s0-sdi3 { -- rockchip,pins = -- /* i2s0_sdi3 */ -- <1 RK_PD1 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s0_sdo0: i2s0-sdo0 { -- rockchip,pins = -- /* i2s0_sdo0 */ -- <1 RK_PC7 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s0_sdo1: i2s0-sdo1 { -- rockchip,pins = -- /* i2s0_sdo1 */ -- <1 RK_PD0 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s0_sdo2: i2s0-sdo2 { -- rockchip,pins = -- /* i2s0_sdo2 */ -- <1 RK_PD1 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s0_sdo3: i2s0-sdo3 { -- rockchip,pins = -- /* i2s0_sdo3 */ -- <1 RK_PD2 1 &pcfg_pull_none>; -- }; -- }; -- -- i2s1 { -- /omit-if-no-ref/ -- i2s1m0_lrck: i2s1m0-lrck { -- rockchip,pins = -- /* i2s1m0_lrck */ -- <4 RK_PA2 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m0_mclk: i2s1m0-mclk { -- rockchip,pins = -- /* i2s1m0_mclk */ -- <4 RK_PA0 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m0_sclk: i2s1m0-sclk { -- rockchip,pins = -- /* i2s1m0_sclk */ -- <4 RK_PA1 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m0_sdi0: i2s1m0-sdi0 { -- rockchip,pins = -- /* i2s1m0_sdi0 */ -- <4 RK_PA5 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m0_sdi1: i2s1m0-sdi1 { -- rockchip,pins = -- /* i2s1m0_sdi1 */ -- <4 RK_PA6 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m0_sdi2: i2s1m0-sdi2 { -- rockchip,pins = -- /* i2s1m0_sdi2 */ -- <4 RK_PA7 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m0_sdi3: i2s1m0-sdi3 { -- rockchip,pins = -- /* i2s1m0_sdi3 */ -- <4 RK_PB0 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m0_sdo0: i2s1m0-sdo0 { -- rockchip,pins = -- /* i2s1m0_sdo0 */ -- <4 RK_PB1 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m0_sdo1: i2s1m0-sdo1 { -- rockchip,pins = -- /* i2s1m0_sdo1 */ -- <4 RK_PB2 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m0_sdo2: i2s1m0-sdo2 { -- rockchip,pins = -- /* i2s1m0_sdo2 */ -- <4 RK_PB3 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m0_sdo3: i2s1m0-sdo3 { -- rockchip,pins = -- /* i2s1m0_sdo3 */ -- <4 RK_PB4 3 &pcfg_pull_none>; -- }; -- /omit-if-no-ref/ -- i2s1m1_lrck: i2s1m1-lrck { -- rockchip,pins = -- /* i2s1m1_lrck */ -- <0 RK_PB7 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m1_mclk: i2s1m1-mclk { -- rockchip,pins = -- /* i2s1m1_mclk */ -- <0 RK_PB5 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m1_sclk: i2s1m1-sclk { -- rockchip,pins = -- /* i2s1m1_sclk */ -- <0 RK_PB6 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m1_sdi0: i2s1m1-sdi0 { -- rockchip,pins = -- /* i2s1m1_sdi0 */ -- <0 RK_PC5 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m1_sdi1: i2s1m1-sdi1 { -- rockchip,pins = -- /* i2s1m1_sdi1 */ -- <0 RK_PC6 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m1_sdi2: i2s1m1-sdi2 { -- rockchip,pins = -- /* i2s1m1_sdi2 */ -- <0 RK_PC7 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m1_sdi3: i2s1m1-sdi3 { -- rockchip,pins = -- /* i2s1m1_sdi3 */ -- <0 RK_PD0 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m1_sdo0: i2s1m1-sdo0 { -- rockchip,pins = -- /* i2s1m1_sdo0 */ -- <0 RK_PD1 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m1_sdo1: i2s1m1-sdo1 { -- rockchip,pins = -- /* i2s1m1_sdo1 */ -- <0 RK_PD2 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m1_sdo2: i2s1m1-sdo2 { -- rockchip,pins = -- /* i2s1m1_sdo2 */ -- <0 RK_PD4 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s1m1_sdo3: i2s1m1-sdo3 { -- rockchip,pins = -- /* i2s1m1_sdo3 */ -- <0 RK_PD5 1 &pcfg_pull_none>; -- }; -- }; -- -- i2s2 { -- /omit-if-no-ref/ -- i2s2m0_lrck: i2s2m0-lrck { -- rockchip,pins = -- /* i2s2m0_lrck */ -- <2 RK_PC0 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m0_mclk: i2s2m0-mclk { -- rockchip,pins = -- /* i2s2m0_mclk */ -- <2 RK_PB6 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m0_sclk: i2s2m0-sclk { -- rockchip,pins = -- /* i2s2m0_sclk */ -- <2 RK_PB7 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m0_sdi: i2s2m0-sdi { -- rockchip,pins = -- /* i2s2m0_sdi */ -- <2 RK_PC3 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m0_sdo: i2s2m0-sdo { -- rockchip,pins = -- /* i2s2m0_sdo */ -- <4 RK_PC3 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m1_lrck: i2s2m1-lrck { -- rockchip,pins = -- /* i2s2m1_lrck */ -- <3 RK_PB6 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m1_mclk: i2s2m1-mclk { -- rockchip,pins = -- /* i2s2m1_mclk */ -- <3 RK_PB4 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m1_sclk: i2s2m1-sclk { -- rockchip,pins = -- /* i2s2m1_sclk */ -- <3 RK_PB5 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m1_sdi: i2s2m1-sdi { -- rockchip,pins = -- /* i2s2m1_sdi */ -- <3 RK_PB2 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s2m1_sdo: i2s2m1-sdo { -- rockchip,pins = -- /* i2s2m1_sdo */ -- <3 RK_PB3 3 &pcfg_pull_none>; -- }; -- }; -- -- i2s3 { -- /omit-if-no-ref/ -- i2s3_lrck: i2s3-lrck { -- rockchip,pins = -- /* i2s3_lrck */ -- <3 RK_PA2 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s3_mclk: i2s3-mclk { -- rockchip,pins = -- /* i2s3_mclk */ -- <3 RK_PA0 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s3_sclk: i2s3-sclk { -- rockchip,pins = -- /* i2s3_sclk */ -- <3 RK_PA1 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s3_sdi: i2s3-sdi { -- rockchip,pins = -- /* i2s3_sdi */ -- <3 RK_PA4 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- i2s3_sdo: i2s3-sdo { -- rockchip,pins = -- /* i2s3_sdo */ -- <3 RK_PA3 3 &pcfg_pull_none>; -- }; -- }; -- -- jtag { -- /omit-if-no-ref/ -- jtagm0_pins: jtagm0-pins { -- rockchip,pins = -- /* jtag_tck_m0 */ -- <4 RK_PD2 5 &pcfg_pull_none>, -- /* jtag_tms_m0 */ -- <4 RK_PD3 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- jtagm1_pins: jtagm1-pins { -- rockchip,pins = -- /* jtag_tck_m1 */ -- <4 RK_PD0 5 &pcfg_pull_none>, -- /* jtag_tms_m1 */ -- <4 RK_PD1 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- jtagm2_pins: jtagm2-pins { -- rockchip,pins = -- /* jtag_tck_m2 */ -- <0 RK_PB5 2 &pcfg_pull_none>, -- /* jtag_tms_m2 */ -- <0 RK_PB6 2 &pcfg_pull_none>; -- }; -- }; -- -- litcpu { -- /omit-if-no-ref/ -- litcpu_pins: litcpu-pins { -- rockchip,pins = -- /* litcpu_avs */ -- <0 RK_PD3 1 &pcfg_pull_none>; -- }; -- }; -- -- mcu { -- /omit-if-no-ref/ -- mcum0_pins: mcum0-pins { -- rockchip,pins = -- /* mcu_jtag_tck_m0 */ -- <4 RK_PD4 5 &pcfg_pull_none>, -- /* mcu_jtag_tms_m0 */ -- <4 RK_PD5 5 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- mcum1_pins: mcum1-pins { -- rockchip,pins = -- /* mcu_jtag_tck_m1 */ -- <3 RK_PD4 6 &pcfg_pull_none>, -- /* mcu_jtag_tms_m1 */ -- <3 RK_PD5 6 &pcfg_pull_none>; -- }; -- }; -- -- mipi { -- /omit-if-no-ref/ -- mipim0_camera0_clk: mipim0-camera0-clk { -- rockchip,pins = -- /* mipim0_camera0_clk */ -- <4 RK_PB1 1 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- mipim0_camera1_clk: mipim0-camera1-clk { -- rockchip,pins = -- /* mipim0_camera1_clk */ -- <1 RK_PB6 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- mipim0_camera2_clk: mipim0-camera2-clk { -- rockchip,pins = -- /* mipim0_camera2_clk */ -- <1 RK_PB7 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- mipim0_camera3_clk: mipim0-camera3-clk { -- rockchip,pins = -- /* mipim0_camera3_clk */ -- <1 RK_PD6 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- mipim0_camera4_clk: mipim0-camera4-clk { -- rockchip,pins = -- /* mipim0_camera4_clk */ -- <1 RK_PD7 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- mipim1_camera0_clk: mipim1-camera0-clk { -- rockchip,pins = -- /* mipim1_camera0_clk */ -- <3 RK_PA5 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- mipim1_camera1_clk: mipim1-camera1-clk { -- rockchip,pins = -- /* mipim1_camera1_clk */ -- <3 RK_PA6 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- mipim1_camera2_clk: mipim1-camera2-clk { -- rockchip,pins = -- /* mipim1_camera2_clk */ -- <3 RK_PA7 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- mipim1_camera3_clk: mipim1-camera3-clk { -- rockchip,pins = -- /* mipim1_camera3_clk */ -- <3 RK_PB0 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- mipim1_camera4_clk: mipim1-camera4-clk { -- rockchip,pins = -- /* mipim1_camera4_clk */ -- <3 RK_PB1 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- mipi_te0: mipi-te0 { -- rockchip,pins = -- /* mipi_te0 */ -- <3 RK_PC2 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- mipi_te1: mipi-te1 { -- rockchip,pins = -- /* mipi_te1 */ -- <3 RK_PC3 2 &pcfg_pull_none>; -- }; -- }; -- -- npu { -- /omit-if-no-ref/ -- npu_pins: npu-pins { -- rockchip,pins = -- /* npu_avs */ -- <0 RK_PC6 2 &pcfg_pull_none>; -- }; -- }; -- -- pcie20x1 { -- /omit-if-no-ref/ -- pcie20x1m0_pins: pcie20x1m0-pins { -- rockchip,pins = -- /* pcie20x1_2_clkreqn_m0 */ -- <3 RK_PC7 4 &pcfg_pull_none>, -- /* pcie20x1_2_perstn_m0 */ -- <3 RK_PD1 4 &pcfg_pull_none>, -- /* pcie20x1_2_waken_m0 */ -- <3 RK_PD0 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie20x1m1_pins: pcie20x1m1-pins { -- rockchip,pins = -- /* pcie20x1_2_clkreqn_m1 */ -- <4 RK_PB7 4 &pcfg_pull_none>, -- /* pcie20x1_2_perstn_m1 */ -- <4 RK_PC1 4 &pcfg_pull_none>, -- /* pcie20x1_2_waken_m1 */ -- <4 RK_PC0 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { -- rockchip,pins = -- /* pcie20x1_2_button_rstn */ -- <4 RK_PB3 4 &pcfg_pull_none>; -- }; -- }; -- -- pcie30phy { -- /omit-if-no-ref/ -- pcie30phy_pins: pcie30phy-pins { -- rockchip,pins = -- /* pcie30phy_dtb0 */ -- <1 RK_PC4 4 &pcfg_pull_none>, -- /* pcie30phy_dtb1 */ -- <1 RK_PD1 4 &pcfg_pull_none>; -- }; -- }; -- -- pcie30x1 { -- /omit-if-no-ref/ -- pcie30x1m0_pins: pcie30x1m0-pins { -- rockchip,pins = -- /* pcie30x1_0_clkreqn_m0 */ -- <0 RK_PC0 12 &pcfg_pull_none>, -- /* pcie30x1_0_perstn_m0 */ -- <0 RK_PC5 12 &pcfg_pull_none>, -- /* pcie30x1_0_waken_m0 */ -- <0 RK_PC4 12 &pcfg_pull_none>, -- /* pcie30x1_1_clkreqn_m0 */ -- <0 RK_PB5 12 &pcfg_pull_none>, -- /* pcie30x1_1_perstn_m0 */ -- <0 RK_PB7 12 &pcfg_pull_none>, -- /* pcie30x1_1_waken_m0 */ -- <0 RK_PB6 12 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie30x1m1_pins: pcie30x1m1-pins { -- rockchip,pins = -- /* pcie30x1_0_clkreqn_m1 */ -- <4 RK_PA3 4 &pcfg_pull_none>, -- /* pcie30x1_0_perstn_m1 */ -- <4 RK_PA5 4 &pcfg_pull_none>, -- /* pcie30x1_0_waken_m1 */ -- <4 RK_PA4 4 &pcfg_pull_none>, -- /* pcie30x1_1_clkreqn_m1 */ -- <4 RK_PA0 4 &pcfg_pull_none>, -- /* pcie30x1_1_perstn_m1 */ -- <4 RK_PA2 4 &pcfg_pull_none>, -- /* pcie30x1_1_waken_m1 */ -- <4 RK_PA1 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie30x1m2_pins: pcie30x1m2-pins { -- rockchip,pins = -- /* pcie30x1_0_clkreqn_m2 */ -- <1 RK_PB5 4 &pcfg_pull_none>, -- /* pcie30x1_0_perstn_m2 */ -- <1 RK_PB4 4 &pcfg_pull_none>, -- /* pcie30x1_0_waken_m2 */ -- <1 RK_PB3 4 &pcfg_pull_none>, -- /* pcie30x1_1_clkreqn_m2 */ -- <1 RK_PA0 4 &pcfg_pull_none>, -- /* pcie30x1_1_perstn_m2 */ -- <1 RK_PA7 4 &pcfg_pull_none>, -- /* pcie30x1_1_waken_m2 */ -- <1 RK_PA1 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { -- rockchip,pins = -- /* pcie30x1_0_button_rstn */ -- <4 RK_PB1 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { -- rockchip,pins = -- /* pcie30x1_1_button_rstn */ -- <4 RK_PB2 4 &pcfg_pull_none>; -- }; -- }; -- -- pcie30x2 { -- /omit-if-no-ref/ -- pcie30x2m0_pins: pcie30x2m0-pins { -- rockchip,pins = -- /* pcie30x2_clkreqn_m0 */ -- <0 RK_PD1 12 &pcfg_pull_none>, -- /* pcie30x2_perstn_m0 */ -- <0 RK_PD4 12 &pcfg_pull_none>, -- /* pcie30x2_waken_m0 */ -- <0 RK_PD2 12 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie30x2m1_pins: pcie30x2m1-pins { -- rockchip,pins = -- /* pcie30x2_clkreqn_m1 */ -- <4 RK_PA6 4 &pcfg_pull_none>, -- /* pcie30x2_perstn_m1 */ -- <4 RK_PB0 4 &pcfg_pull_none>, -- /* pcie30x2_waken_m1 */ -- <4 RK_PA7 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie30x2m2_pins: pcie30x2m2-pins { -- rockchip,pins = -- /* pcie30x2_clkreqn_m2 */ -- <3 RK_PD2 4 &pcfg_pull_none>, -- /* pcie30x2_perstn_m2 */ -- <3 RK_PD4 4 &pcfg_pull_none>, -- /* pcie30x2_waken_m2 */ -- <3 RK_PD3 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie30x2m3_pins: pcie30x2m3-pins { -- rockchip,pins = -- /* pcie30x2_clkreqn_m3 */ -- <1 RK_PD7 4 &pcfg_pull_none>, -- /* pcie30x2_perstn_m3 */ -- <1 RK_PB7 4 &pcfg_pull_none>, -- /* pcie30x2_waken_m3 */ -- <1 RK_PB6 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie30x2_button_rstn: pcie30x2-button-rstn { -- rockchip,pins = -- /* pcie30x2_button_rstn */ -- <3 RK_PC1 4 &pcfg_pull_none>; -- }; -- }; -- -- pcie30x4 { -- /omit-if-no-ref/ -- pcie30x4m0_pins: pcie30x4m0-pins { -- rockchip,pins = -- /* pcie30x4_clkreqn_m0 */ -- <0 RK_PC6 12 &pcfg_pull_none>, -- /* pcie30x4_perstn_m0 */ -- <0 RK_PD0 12 &pcfg_pull_none>, -- /* pcie30x4_waken_m0 */ -- <0 RK_PC7 12 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie30x4m1_pins: pcie30x4m1-pins { -- rockchip,pins = -- /* pcie30x4_clkreqn_m1 */ -- <4 RK_PB4 4 &pcfg_pull_none>, -- /* pcie30x4_perstn_m1 */ -- <4 RK_PB6 4 &pcfg_pull_none>, -- /* pcie30x4_waken_m1 */ -- <4 RK_PB5 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie30x4m2_pins: pcie30x4m2-pins { -- rockchip,pins = -- /* pcie30x4_clkreqn_m2 */ -- <3 RK_PC4 4 &pcfg_pull_none>, -- /* pcie30x4_perstn_m2 */ -- <3 RK_PC6 4 &pcfg_pull_none>, -- /* pcie30x4_waken_m2 */ -- <3 RK_PC5 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie30x4m3_pins: pcie30x4m3-pins { -- rockchip,pins = -- /* pcie30x4_clkreqn_m3 */ -- <1 RK_PB0 4 &pcfg_pull_none>, -- /* pcie30x4_perstn_m3 */ -- <1 RK_PB2 4 &pcfg_pull_none>, -- /* pcie30x4_waken_m3 */ -- <1 RK_PB1 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pcie30x4_button_rstn: pcie30x4-button-rstn { -- rockchip,pins = -- /* pcie30x4_button_rstn */ -- <3 RK_PD5 4 &pcfg_pull_none>; -- }; -- }; -- -- pdm0 { -- /omit-if-no-ref/ -- pdm0m0_clk: pdm0m0-clk { -- rockchip,pins = -- /* pdm0_clk0_m0 */ -- <1 RK_PC6 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm0m0_clk1: pdm0m0-clk1 { -- rockchip,pins = -- /* pdm0m0_clk1 */ -- <1 RK_PC4 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm0m0_sdi0: pdm0m0-sdi0 { -- rockchip,pins = -- /* pdm0m0_sdi0 */ -- <1 RK_PD5 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm0m0_sdi1: pdm0m0-sdi1 { -- rockchip,pins = -- /* pdm0m0_sdi1 */ -- <1 RK_PD1 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm0m0_sdi2: pdm0m0-sdi2 { -- rockchip,pins = -- /* pdm0m0_sdi2 */ -- <1 RK_PD2 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm0m0_sdi3: pdm0m0-sdi3 { -- rockchip,pins = -- /* pdm0m0_sdi3 */ -- <1 RK_PD3 3 &pcfg_pull_none>; -- }; -- /omit-if-no-ref/ -- pdm0m1_clk: pdm0m1-clk { -- rockchip,pins = -- /* pdm0_clk0_m1 */ -- <0 RK_PC0 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm0m1_clk1: pdm0m1-clk1 { -- rockchip,pins = -- /* pdm0m1_clk1 */ -- <0 RK_PC4 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm0m1_sdi0: pdm0m1-sdi0 { -- rockchip,pins = -- /* pdm0m1_sdi0 */ -- <0 RK_PC7 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm0m1_sdi1: pdm0m1-sdi1 { -- rockchip,pins = -- /* pdm0m1_sdi1 */ -- <0 RK_PD0 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm0m1_sdi2: pdm0m1-sdi2 { -- rockchip,pins = -- /* pdm0m1_sdi2 */ -- <0 RK_PD4 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm0m1_sdi3: pdm0m1-sdi3 { -- rockchip,pins = -- /* pdm0m1_sdi3 */ -- <0 RK_PD6 2 &pcfg_pull_none>; -- }; -- }; -- -- pdm1 { -- /omit-if-no-ref/ -- pdm1m0_clk: pdm1m0-clk { -- rockchip,pins = -- /* pdm1_clk0_m0 */ -- <4 RK_PD5 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm1m0_clk1: pdm1m0-clk1 { -- rockchip,pins = -- /* pdm1m0_clk1 */ -- <4 RK_PD4 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm1m0_sdi0: pdm1m0-sdi0 { -- rockchip,pins = -- /* pdm1m0_sdi0 */ -- <4 RK_PD3 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm1m0_sdi1: pdm1m0-sdi1 { -- rockchip,pins = -- /* pdm1m0_sdi1 */ -- <4 RK_PD2 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm1m0_sdi2: pdm1m0-sdi2 { -- rockchip,pins = -- /* pdm1m0_sdi2 */ -- <4 RK_PD1 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm1m0_sdi3: pdm1m0-sdi3 { -- rockchip,pins = -- /* pdm1m0_sdi3 */ -- <4 RK_PD0 2 &pcfg_pull_none>; -- }; -- /omit-if-no-ref/ -- pdm1m1_clk: pdm1m1-clk { -- rockchip,pins = -- /* pdm1_clk0_m1 */ -- <1 RK_PB4 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm1m1_clk1: pdm1m1-clk1 { -- rockchip,pins = -- /* pdm1m1_clk1 */ -- <1 RK_PB3 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm1m1_sdi0: pdm1m1-sdi0 { -- rockchip,pins = -- /* pdm1m1_sdi0 */ -- <1 RK_PA7 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm1m1_sdi1: pdm1m1-sdi1 { -- rockchip,pins = -- /* pdm1m1_sdi1 */ -- <1 RK_PB0 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm1m1_sdi2: pdm1m1-sdi2 { -- rockchip,pins = -- /* pdm1m1_sdi2 */ -- <1 RK_PB1 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pdm1m1_sdi3: pdm1m1-sdi3 { -- rockchip,pins = -- /* pdm1m1_sdi3 */ -- <1 RK_PB2 2 &pcfg_pull_none>; -- }; -- }; -- -- pmic { -- /omit-if-no-ref/ -- pmic_pins: pmic-pins { -- rockchip,pins = -- /* pmic_int_l */ -- <0 RK_PA7 0 &pcfg_pull_up>, -- /* pmic_sleep1 */ -- <0 RK_PA2 1 &pcfg_pull_none>, -- /* pmic_sleep2 */ -- <0 RK_PA3 1 &pcfg_pull_none>, -- /* pmic_sleep3 */ -- <0 RK_PC1 1 &pcfg_pull_none>, -- /* pmic_sleep4 */ -- <0 RK_PC2 1 &pcfg_pull_none>, -- /* pmic_sleep5 */ -- <0 RK_PC3 1 &pcfg_pull_none>, -- /* pmic_sleep6 */ -- <0 RK_PD6 1 &pcfg_pull_none>; -- }; -- }; -- -- pmu { -- /omit-if-no-ref/ -- pmu_pins: pmu-pins { -- rockchip,pins = -- /* pmu_debug */ -- <0 RK_PA5 3 &pcfg_pull_none>; -- }; -- }; -- -- pwm0 { -- /omit-if-no-ref/ -- pwm0m0_pins: pwm0m0-pins { -- rockchip,pins = -- /* pwm0_m0 */ -- <0 RK_PB7 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm0m1_pins: pwm0m1-pins { -- rockchip,pins = -- /* pwm0_m1 */ -- <1 RK_PD2 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm0m2_pins: pwm0m2-pins { -- rockchip,pins = -- /* pwm0_m2 */ -- <1 RK_PA2 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm1 { -- /omit-if-no-ref/ -- pwm1m0_pins: pwm1m0-pins { -- rockchip,pins = -- /* pwm1_m0 */ -- <0 RK_PC0 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm1m1_pins: pwm1m1-pins { -- rockchip,pins = -- /* pwm1_m1 */ -- <1 RK_PD3 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm1m2_pins: pwm1m2-pins { -- rockchip,pins = -- /* pwm1_m2 */ -- <1 RK_PA3 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm2 { -- /omit-if-no-ref/ -- pwm2m0_pins: pwm2m0-pins { -- rockchip,pins = -- /* pwm2_m0 */ -- <0 RK_PC4 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm2m1_pins: pwm2m1-pins { -- rockchip,pins = -- /* pwm2_m1 */ -- <3 RK_PB1 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm3 { -- /omit-if-no-ref/ -- pwm3m0_pins: pwm3m0-pins { -- rockchip,pins = -- /* pwm3_ir_m0 */ -- <0 RK_PD4 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm3m1_pins: pwm3m1-pins { -- rockchip,pins = -- /* pwm3_ir_m1 */ -- <3 RK_PB2 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm3m2_pins: pwm3m2-pins { -- rockchip,pins = -- /* pwm3_ir_m2 */ -- <1 RK_PC2 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm3m3_pins: pwm3m3-pins { -- rockchip,pins = -- /* pwm3_ir_m3 */ -- <1 RK_PA7 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm4 { -- /omit-if-no-ref/ -- pwm4m0_pins: pwm4m0-pins { -- rockchip,pins = -- /* pwm4_m0 */ -- <0 RK_PC5 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm5 { -- /omit-if-no-ref/ -- pwm5m0_pins: pwm5m0-pins { -- rockchip,pins = -- /* pwm5_m0 */ -- <0 RK_PB1 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm5m1_pins: pwm5m1-pins { -- rockchip,pins = -- /* pwm5_m1 */ -- <0 RK_PC6 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm6 { -- /omit-if-no-ref/ -- pwm6m0_pins: pwm6m0-pins { -- rockchip,pins = -- /* pwm6_m0 */ -- <0 RK_PC7 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm6m1_pins: pwm6m1-pins { -- rockchip,pins = -- /* pwm6_m1 */ -- <4 RK_PC1 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm7 { -- /omit-if-no-ref/ -- pwm7m0_pins: pwm7m0-pins { -- rockchip,pins = -- /* pwm7_ir_m0 */ -- <0 RK_PD0 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm7m1_pins: pwm7m1-pins { -- rockchip,pins = -- /* pwm7_ir_m1 */ -- <4 RK_PD4 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm7m2_pins: pwm7m2-pins { -- rockchip,pins = -- /* pwm7_ir_m2 */ -- <1 RK_PC3 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm8 { -- /omit-if-no-ref/ -- pwm8m0_pins: pwm8m0-pins { -- rockchip,pins = -- /* pwm8_m0 */ -- <3 RK_PA7 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm8m1_pins: pwm8m1-pins { -- rockchip,pins = -- /* pwm8_m1 */ -- <4 RK_PD0 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm8m2_pins: pwm8m2-pins { -- rockchip,pins = -- /* pwm8_m2 */ -- <3 RK_PD0 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm9 { -- /omit-if-no-ref/ -- pwm9m0_pins: pwm9m0-pins { -- rockchip,pins = -- /* pwm9_m0 */ -- <3 RK_PB0 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm9m1_pins: pwm9m1-pins { -- rockchip,pins = -- /* pwm9_m1 */ -- <4 RK_PD1 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm9m2_pins: pwm9m2-pins { -- rockchip,pins = -- /* pwm9_m2 */ -- <3 RK_PD1 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm10 { -- /omit-if-no-ref/ -- pwm10m0_pins: pwm10m0-pins { -- rockchip,pins = -- /* pwm10_m0 */ -- <3 RK_PA0 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm10m1_pins: pwm10m1-pins { -- rockchip,pins = -- /* pwm10_m1 */ -- <4 RK_PD3 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm10m2_pins: pwm10m2-pins { -- rockchip,pins = -- /* pwm10_m2 */ -- <3 RK_PD3 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm11 { -- /omit-if-no-ref/ -- pwm11m0_pins: pwm11m0-pins { -- rockchip,pins = -- /* pwm11_ir_m0 */ -- <3 RK_PA1 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm11m1_pins: pwm11m1-pins { -- rockchip,pins = -- /* pwm11_ir_m1 */ -- <4 RK_PB4 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm11m2_pins: pwm11m2-pins { -- rockchip,pins = -- /* pwm11_ir_m2 */ -- <1 RK_PC4 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm11m3_pins: pwm11m3-pins { -- rockchip,pins = -- /* pwm11_ir_m3 */ -- <3 RK_PD5 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm12 { -- /omit-if-no-ref/ -- pwm12m0_pins: pwm12m0-pins { -- rockchip,pins = -- /* pwm12_m0 */ -- <3 RK_PB5 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm12m1_pins: pwm12m1-pins { -- rockchip,pins = -- /* pwm12_m1 */ -- <4 RK_PB5 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm13 { -- /omit-if-no-ref/ -- pwm13m0_pins: pwm13m0-pins { -- rockchip,pins = -- /* pwm13_m0 */ -- <3 RK_PB6 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm13m1_pins: pwm13m1-pins { -- rockchip,pins = -- /* pwm13_m1 */ -- <4 RK_PB6 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm13m2_pins: pwm13m2-pins { -- rockchip,pins = -- /* pwm13_m2 */ -- <1 RK_PB7 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm14 { -- /omit-if-no-ref/ -- pwm14m0_pins: pwm14m0-pins { -- rockchip,pins = -- /* pwm14_m0 */ -- <3 RK_PC2 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm14m1_pins: pwm14m1-pins { -- rockchip,pins = -- /* pwm14_m1 */ -- <4 RK_PB2 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm14m2_pins: pwm14m2-pins { -- rockchip,pins = -- /* pwm14_m2 */ -- <1 RK_PD6 11 &pcfg_pull_none>; -- }; -- }; -- -- pwm15 { -- /omit-if-no-ref/ -- pwm15m0_pins: pwm15m0-pins { -- rockchip,pins = -- /* pwm15_ir_m0 */ -- <3 RK_PC3 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm15m1_pins: pwm15m1-pins { -- rockchip,pins = -- /* pwm15_ir_m1 */ -- <4 RK_PB3 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm15m2_pins: pwm15m2-pins { -- rockchip,pins = -- /* pwm15_ir_m2 */ -- <1 RK_PC6 11 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- pwm15m3_pins: pwm15m3-pins { -- rockchip,pins = -- /* pwm15_ir_m3 */ -- <1 RK_PD7 11 &pcfg_pull_none>; -- }; -- }; -- -- refclk { -- /omit-if-no-ref/ -- refclk_pins: refclk-pins { -- rockchip,pins = -- /* refclk_out */ -- <0 RK_PA0 1 &pcfg_pull_none>; -- }; -- }; -- -- sata { -- /omit-if-no-ref/ -- sata_pins: sata-pins { -- rockchip,pins = -- /* sata_cp_pod */ -- <0 RK_PC6 13 &pcfg_pull_none>, -- /* sata_cpdet */ -- <0 RK_PD4 13 &pcfg_pull_none>, -- /* sata_mp_switch */ -- <0 RK_PD5 13 &pcfg_pull_none>; -- }; -- }; -- -- sata0 { -- /omit-if-no-ref/ -- sata0m0_pins: sata0m0-pins { -- rockchip,pins = -- /* sata0_act_led_m0 */ -- <4 RK_PB6 6 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- sata0m1_pins: sata0m1-pins { -- rockchip,pins = -- /* sata0_act_led_m1 */ -- <1 RK_PB3 6 &pcfg_pull_none>; -- }; -- }; -- -- sata1 { -- /omit-if-no-ref/ -- sata1m0_pins: sata1m0-pins { -- rockchip,pins = -- /* sata1_act_led_m0 */ -- <4 RK_PB5 6 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- sata1m1_pins: sata1m1-pins { -- rockchip,pins = -- /* sata1_act_led_m1 */ -- <1 RK_PA1 6 &pcfg_pull_none>; -- }; -- }; -- -- sata2 { -- /omit-if-no-ref/ -- sata2m0_pins: sata2m0-pins { -- rockchip,pins = -- /* sata2_act_led_m0 */ -- <4 RK_PB1 6 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- sata2m1_pins: sata2m1-pins { -- rockchip,pins = -- /* sata2_act_led_m1 */ -- <1 RK_PB7 6 &pcfg_pull_none>; -- }; -- }; -- -- sdio { -- /omit-if-no-ref/ -- sdiom1_pins: sdiom1-pins { -- rockchip,pins = -- /* sdio_clk_m1 */ -- <3 RK_PA5 2 &pcfg_pull_none>, -- /* sdio_cmd_m1 */ -- <3 RK_PA4 2 &pcfg_pull_none>, -- /* sdio_d0_m1 */ -- <3 RK_PA0 2 &pcfg_pull_none>, -- /* sdio_d1_m1 */ -- <3 RK_PA1 2 &pcfg_pull_none>, -- /* sdio_d2_m1 */ -- <3 RK_PA2 2 &pcfg_pull_none>, -- /* sdio_d3_m1 */ -- <3 RK_PA3 2 &pcfg_pull_none>; -- }; -- }; -- -- sdmmc { -- /omit-if-no-ref/ -- sdmmc_bus4: sdmmc-bus4 { -- rockchip,pins = -- /* sdmmc_d0 */ -- <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, -- /* sdmmc_d1 */ -- <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, -- /* sdmmc_d2 */ -- <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, -- /* sdmmc_d3 */ -- <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; -- }; -- -- /omit-if-no-ref/ -- sdmmc_clk: sdmmc-clk { -- rockchip,pins = -- /* sdmmc_clk */ -- <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; -- }; -- -- /omit-if-no-ref/ -- sdmmc_cmd: sdmmc-cmd { -- rockchip,pins = -- /* sdmmc_cmd */ -- <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; -- }; -- -- /omit-if-no-ref/ -- sdmmc_det: sdmmc-det { -- rockchip,pins = -- /* sdmmc_det */ -- <0 RK_PA4 1 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- sdmmc_pwren: sdmmc-pwren { -- rockchip,pins = -- /* sdmmc_pwren */ -- <0 RK_PA5 2 &pcfg_pull_none>; -- }; -- }; -- -- spdif0 { -- /omit-if-no-ref/ -- spdif0m0_tx: spdif0m0-tx { -- rockchip,pins = -- /* spdif0m0_tx */ -- <1 RK_PB6 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- spdif0m1_tx: spdif0m1-tx { -- rockchip,pins = -- /* spdif0m1_tx */ -- <4 RK_PB4 6 &pcfg_pull_none>; -- }; -- }; -- -- spdif1 { -- /omit-if-no-ref/ -- spdif1m0_tx: spdif1m0-tx { -- rockchip,pins = -- /* spdif1m0_tx */ -- <1 RK_PB7 3 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- spdif1m1_tx: spdif1m1-tx { -- rockchip,pins = -- /* spdif1m1_tx */ -- <4 RK_PB1 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- spdif1m2_tx: spdif1m2-tx { -- rockchip,pins = -- /* spdif1m2_tx */ -- <4 RK_PC1 3 &pcfg_pull_none>; -- }; -- }; -- -- spi0 { -- /omit-if-no-ref/ -- spi0m0_pins: spi0m0-pins { -- rockchip,pins = -- /* spi0_clk_m0 */ -- <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>, -- /* spi0_miso_m0 */ -- <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>, -- /* spi0_mosi_m0 */ -- <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi0m0_cs0: spi0m0-cs0 { -- rockchip,pins = -- /* spi0_cs0_m0 */ -- <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi0m0_cs1: spi0m0-cs1 { -- rockchip,pins = -- /* spi0_cs1_m0 */ -- <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>; -- }; -- /omit-if-no-ref/ -- spi0m1_pins: spi0m1-pins { -- rockchip,pins = -- /* spi0_clk_m1 */ -- <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>, -- /* spi0_miso_m1 */ -- <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>, -- /* spi0_mosi_m1 */ -- <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi0m1_cs0: spi0m1-cs0 { -- rockchip,pins = -- /* spi0_cs0_m1 */ -- <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi0m1_cs1: spi0m1-cs1 { -- rockchip,pins = -- /* spi0_cs1_m1 */ -- <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>; -- }; -- /omit-if-no-ref/ -- spi0m2_pins: spi0m2-pins { -- rockchip,pins = -- /* spi0_clk_m2 */ -- <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>, -- /* spi0_miso_m2 */ -- <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>, -- /* spi0_mosi_m2 */ -- <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi0m2_cs0: spi0m2-cs0 { -- rockchip,pins = -- /* spi0_cs0_m2 */ -- <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi0m2_cs1: spi0m2-cs1 { -- rockchip,pins = -- /* spi0_cs1_m2 */ -- <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>; -- }; -- /omit-if-no-ref/ -- spi0m3_pins: spi0m3-pins { -- rockchip,pins = -- /* spi0_clk_m3 */ -- <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>, -- /* spi0_miso_m3 */ -- <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>, -- /* spi0_mosi_m3 */ -- <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi0m3_cs0: spi0m3-cs0 { -- rockchip,pins = -- /* spi0_cs0_m3 */ -- <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi0m3_cs1: spi0m3-cs1 { -- rockchip,pins = -- /* spi0_cs1_m3 */ -- <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>; -- }; -- }; -- -- spi1 { -- /omit-if-no-ref/ -- spi1m1_pins: spi1m1-pins { -- rockchip,pins = -- /* spi1_clk_m1 */ -- <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>, -- /* spi1_miso_m1 */ -- <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>, -- /* spi1_mosi_m1 */ -- <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi1m1_cs0: spi1m1-cs0 { -- rockchip,pins = -- /* spi1_cs0_m1 */ -- <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi1m1_cs1: spi1m1-cs1 { -- rockchip,pins = -- /* spi1_cs1_m1 */ -- <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi1m2_pins: spi1m2-pins { -- rockchip,pins = -- /* spi1_clk_m2 */ -- <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>, -- /* spi1_miso_m2 */ -- <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>, -- /* spi1_mosi_m2 */ -- <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi1m2_cs0: spi1m2-cs0 { -- rockchip,pins = -- /* spi1_cs0_m2 */ -- <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi1m2_cs1: spi1m2-cs1 { -- rockchip,pins = -- /* spi1_cs1_m2 */ -- <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>; -- }; -- }; -- -- spi2 { -- /omit-if-no-ref/ -- spi2m0_pins: spi2m0-pins { -- rockchip,pins = -- /* spi2_clk_m0 */ -- <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>, -- /* spi2_miso_m0 */ -- <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>, -- /* spi2_mosi_m0 */ -- <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi2m0_cs0: spi2m0-cs0 { -- rockchip,pins = -- /* spi2_cs0_m0 */ -- <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi2m0_cs1: spi2m0-cs1 { -- rockchip,pins = -- /* spi2_cs1_m0 */ -- <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi2m1_pins: spi2m1-pins { -- rockchip,pins = -- /* spi2_clk_m1 */ -- <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>, -- /* spi2_miso_m1 */ -- <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>, -- /* spi2_mosi_m1 */ -- <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi2m1_cs0: spi2m1-cs0 { -- rockchip,pins = -- /* spi2_cs0_m1 */ -- <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi2m1_cs1: spi2m1-cs1 { -- rockchip,pins = -- /* spi2_cs1_m1 */ -- <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi2m2_pins: spi2m2-pins { -- rockchip,pins = -- /* spi2_clk_m2 */ -- <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, -- /* spi2_miso_m2 */ -- <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, -- /* spi2_mosi_m2 */ -- <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi2m2_cs0: spi2m2-cs0 { -- rockchip,pins = -- /* spi2_cs0_m2 */ -- <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi2m2_cs1: spi2m2-cs1 { -- rockchip,pins = -- /* spi2_cs1_m2 */ -- <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>; -- }; -- }; -- -- spi3 { -- /omit-if-no-ref/ -- spi3m1_pins: spi3m1-pins { -- rockchip,pins = -- /* spi3_clk_m1 */ -- <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>, -- /* spi3_miso_m1 */ -- <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>, -- /* spi3_mosi_m1 */ -- <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi3m1_cs0: spi3m1-cs0 { -- rockchip,pins = -- /* spi3_cs0_m1 */ -- <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi3m1_cs1: spi3m1-cs1 { -- rockchip,pins = -- /* spi3_cs1_m1 */ -- <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi3m2_pins: spi3m2-pins { -- rockchip,pins = -- /* spi3_clk_m2 */ -- <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>, -- /* spi3_miso_m2 */ -- <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>, -- /* spi3_mosi_m2 */ -- <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi3m2_cs0: spi3m2-cs0 { -- rockchip,pins = -- /* spi3_cs0_m2 */ -- <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi3m2_cs1: spi3m2-cs1 { -- rockchip,pins = -- /* spi3_cs1_m2 */ -- <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi3m3_pins: spi3m3-pins { -- rockchip,pins = -- /* spi3_clk_m3 */ -- <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>, -- /* spi3_miso_m3 */ -- <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>, -- /* spi3_mosi_m3 */ -- <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi3m3_cs0: spi3m3-cs0 { -- rockchip,pins = -- /* spi3_cs0_m3 */ -- <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi3m3_cs1: spi3m3-cs1 { -- rockchip,pins = -- /* spi3_cs1_m3 */ -- <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>; -- }; -- }; -- -- spi4 { -- /omit-if-no-ref/ -- spi4m0_pins: spi4m0-pins { -- rockchip,pins = -- /* spi4_clk_m0 */ -- <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>, -- /* spi4_miso_m0 */ -- <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>, -- /* spi4_mosi_m0 */ -- <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi4m0_cs0: spi4m0-cs0 { -- rockchip,pins = -- /* spi4_cs0_m0 */ -- <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi4m0_cs1: spi4m0-cs1 { -- rockchip,pins = -- /* spi4_cs1_m0 */ -- <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi4m1_pins: spi4m1-pins { -- rockchip,pins = -- /* spi4_clk_m1 */ -- <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>, -- /* spi4_miso_m1 */ -- <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>, -- /* spi4_mosi_m1 */ -- <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi4m1_cs0: spi4m1-cs0 { -- rockchip,pins = -- /* spi4_cs0_m1 */ -- <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi4m1_cs1: spi4m1-cs1 { -- rockchip,pins = -- /* spi4_cs1_m1 */ -- <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi4m2_pins: spi4m2-pins { -- rockchip,pins = -- /* spi4_clk_m2 */ -- <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>, -- /* spi4_miso_m2 */ -- <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>, -- /* spi4_mosi_m2 */ -- <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>; -- }; -- -- /omit-if-no-ref/ -- spi4m2_cs0: spi4m2-cs0 { -- rockchip,pins = -- /* spi4_cs0_m2 */ -- <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>; -- }; -- }; -- -- tsadc { -- /omit-if-no-ref/ -- tsadcm1_shut: tsadcm1-shut { -- rockchip,pins = -- /* tsadcm1_shut */ -- <0 RK_PA2 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- tsadc_shut: tsadc-shut { -- rockchip,pins = -- /* tsadc_shut */ -- <0 RK_PA1 2 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- tsadc_shut_org: tsadc-shut-org { -- rockchip,pins = -- /* tsadc_shut_org */ -- <0 RK_PA1 1 &pcfg_pull_none>; -- }; -- }; -- -- uart0 { -- /omit-if-no-ref/ -- uart0m0_xfer: uart0m0-xfer { -- rockchip,pins = -- /* uart0_rx_m0 */ -- <0 RK_PC4 4 &pcfg_pull_up>, -- /* uart0_tx_m0 */ -- <0 RK_PC5 4 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart0m1_xfer: uart0m1-xfer { -- rockchip,pins = -- /* uart0_rx_m1 */ -- <0 RK_PB0 4 &pcfg_pull_up>, -- /* uart0_tx_m1 */ -- <0 RK_PB1 4 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart0m2_xfer: uart0m2-xfer { -- rockchip,pins = -- /* uart0_rx_m2 */ -- <4 RK_PA4 10 &pcfg_pull_up>, -- /* uart0_tx_m2 */ -- <4 RK_PA3 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart0_ctsn: uart0-ctsn { -- rockchip,pins = -- /* uart0_ctsn */ -- <0 RK_PD1 4 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart0_rtsn: uart0-rtsn { -- rockchip,pins = -- /* uart0_rtsn */ -- <0 RK_PC6 4 &pcfg_pull_none>; -- }; -- }; -- -- uart1 { -- /omit-if-no-ref/ -- uart1m1_xfer: uart1m1-xfer { -- rockchip,pins = -- /* uart1_rx_m1 */ -- <1 RK_PB7 10 &pcfg_pull_up>, -- /* uart1_tx_m1 */ -- <1 RK_PB6 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart1m1_ctsn: uart1m1-ctsn { -- rockchip,pins = -- /* uart1m1_ctsn */ -- <1 RK_PD7 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart1m1_rtsn: uart1m1-rtsn { -- rockchip,pins = -- /* uart1m1_rtsn */ -- <1 RK_PD6 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart1m2_xfer: uart1m2-xfer { -- rockchip,pins = -- /* uart1_rx_m2 */ -- <0 RK_PD2 10 &pcfg_pull_up>, -- /* uart1_tx_m2 */ -- <0 RK_PD1 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart1m2_ctsn: uart1m2-ctsn { -- rockchip,pins = -- /* uart1m2_ctsn */ -- <0 RK_PD0 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart1m2_rtsn: uart1m2-rtsn { -- rockchip,pins = -- /* uart1m2_rtsn */ -- <0 RK_PC7 10 &pcfg_pull_none>; -- }; -- }; -- -- uart2 { -- /omit-if-no-ref/ -- uart2m0_xfer: uart2m0-xfer { -- rockchip,pins = -- /* uart2_rx_m0 */ -- <0 RK_PB6 10 &pcfg_pull_up>, -- /* uart2_tx_m0 */ -- <0 RK_PB5 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart2m1_xfer: uart2m1-xfer { -- rockchip,pins = -- /* uart2_rx_m1 */ -- <4 RK_PD1 10 &pcfg_pull_up>, -- /* uart2_tx_m1 */ -- <4 RK_PD0 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart2m2_xfer: uart2m2-xfer { -- rockchip,pins = -- /* uart2_rx_m2 */ -- <3 RK_PB2 10 &pcfg_pull_up>, -- /* uart2_tx_m2 */ -- <3 RK_PB1 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart2_ctsn: uart2-ctsn { -- rockchip,pins = -- /* uart2_ctsn */ -- <3 RK_PB4 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart2_rtsn: uart2-rtsn { -- rockchip,pins = -- /* uart2_rtsn */ -- <3 RK_PB3 10 &pcfg_pull_none>; -- }; -- }; -- -- uart3 { -- /omit-if-no-ref/ -- uart3m0_xfer: uart3m0-xfer { -- rockchip,pins = -- /* uart3_rx_m0 */ -- <1 RK_PC0 10 &pcfg_pull_up>, -- /* uart3_tx_m0 */ -- <1 RK_PC1 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart3m1_xfer: uart3m1-xfer { -- rockchip,pins = -- /* uart3_rx_m1 */ -- <3 RK_PB6 10 &pcfg_pull_up>, -- /* uart3_tx_m1 */ -- <3 RK_PB5 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart3m2_xfer: uart3m2-xfer { -- rockchip,pins = -- /* uart3_rx_m2 */ -- <4 RK_PA6 10 &pcfg_pull_up>, -- /* uart3_tx_m2 */ -- <4 RK_PA5 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart3_ctsn: uart3-ctsn { -- rockchip,pins = -- /* uart3_ctsn */ -- <1 RK_PC3 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart3_rtsn: uart3-rtsn { -- rockchip,pins = -- /* uart3_rtsn */ -- <1 RK_PC2 10 &pcfg_pull_none>; -- }; -- }; -- -- uart4 { -- /omit-if-no-ref/ -- uart4m0_xfer: uart4m0-xfer { -- rockchip,pins = -- /* uart4_rx_m0 */ -- <1 RK_PD3 10 &pcfg_pull_up>, -- /* uart4_tx_m0 */ -- <1 RK_PD2 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart4m1_xfer: uart4m1-xfer { -- rockchip,pins = -- /* uart4_rx_m1 */ -- <3 RK_PD0 10 &pcfg_pull_up>, -- /* uart4_tx_m1 */ -- <3 RK_PD1 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart4m2_xfer: uart4m2-xfer { -- rockchip,pins = -- /* uart4_rx_m2 */ -- <1 RK_PB2 10 &pcfg_pull_up>, -- /* uart4_tx_m2 */ -- <1 RK_PB3 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart4_ctsn: uart4-ctsn { -- rockchip,pins = -- /* uart4_ctsn */ -- <1 RK_PC7 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart4_rtsn: uart4-rtsn { -- rockchip,pins = -- /* uart4_rtsn */ -- <1 RK_PC5 10 &pcfg_pull_none>; -- }; -- }; -- -- uart5 { -- /omit-if-no-ref/ -- uart5m0_xfer: uart5m0-xfer { -- rockchip,pins = -- /* uart5_rx_m0 */ -- <4 RK_PD4 10 &pcfg_pull_up>, -- /* uart5_tx_m0 */ -- <4 RK_PD5 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart5m0_ctsn: uart5m0-ctsn { -- rockchip,pins = -- /* uart5m0_ctsn */ -- <4 RK_PD2 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart5m0_rtsn: uart5m0-rtsn { -- rockchip,pins = -- /* uart5m0_rtsn */ -- <4 RK_PD3 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart5m1_xfer: uart5m1-xfer { -- rockchip,pins = -- /* uart5_rx_m1 */ -- <3 RK_PC5 10 &pcfg_pull_up>, -- /* uart5_tx_m1 */ -- <3 RK_PC4 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart5m1_ctsn: uart5m1-ctsn { -- rockchip,pins = -- /* uart5m1_ctsn */ -- <2 RK_PA2 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart5m1_rtsn: uart5m1-rtsn { -- rockchip,pins = -- /* uart5m1_rtsn */ -- <2 RK_PA3 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart5m2_xfer: uart5m2-xfer { -- rockchip,pins = -- /* uart5_rx_m2 */ -- <2 RK_PD4 10 &pcfg_pull_up>, -- /* uart5_tx_m2 */ -- <2 RK_PD5 10 &pcfg_pull_up>; -- }; -- }; -- -- uart6 { -- /omit-if-no-ref/ -- uart6m1_xfer: uart6m1-xfer { -- rockchip,pins = -- /* uart6_rx_m1 */ -- <1 RK_PA0 10 &pcfg_pull_up>, -- /* uart6_tx_m1 */ -- <1 RK_PA1 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart6m1_ctsn: uart6m1-ctsn { -- rockchip,pins = -- /* uart6m1_ctsn */ -- <1 RK_PA3 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart6m1_rtsn: uart6m1-rtsn { -- rockchip,pins = -- /* uart6m1_rtsn */ -- <1 RK_PA2 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart6m2_xfer: uart6m2-xfer { -- rockchip,pins = -- /* uart6_rx_m2 */ -- <1 RK_PD1 10 &pcfg_pull_up>, -- /* uart6_tx_m2 */ -- <1 RK_PD0 10 &pcfg_pull_up>; -- }; -- }; -- -- uart7 { -- /omit-if-no-ref/ -- uart7m1_xfer: uart7m1-xfer { -- rockchip,pins = -- /* uart7_rx_m1 */ -- <3 RK_PC1 10 &pcfg_pull_up>, -- /* uart7_tx_m1 */ -- <3 RK_PC0 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart7m1_ctsn: uart7m1-ctsn { -- rockchip,pins = -- /* uart7m1_ctsn */ -- <3 RK_PC3 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart7m1_rtsn: uart7m1-rtsn { -- rockchip,pins = -- /* uart7m1_rtsn */ -- <3 RK_PC2 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart7m2_xfer: uart7m2-xfer { -- rockchip,pins = -- /* uart7_rx_m2 */ -- <1 RK_PB4 10 &pcfg_pull_up>, -- /* uart7_tx_m2 */ -- <1 RK_PB5 10 &pcfg_pull_up>; -- }; -- }; -- -- uart8 { -- /omit-if-no-ref/ -- uart8m0_xfer: uart8m0-xfer { -- rockchip,pins = -- /* uart8_rx_m0 */ -- <4 RK_PB1 10 &pcfg_pull_up>, -- /* uart8_tx_m0 */ -- <4 RK_PB0 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart8m0_ctsn: uart8m0-ctsn { -- rockchip,pins = -- /* uart8m0_ctsn */ -- <4 RK_PB3 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart8m0_rtsn: uart8m0-rtsn { -- rockchip,pins = -- /* uart8m0_rtsn */ -- <4 RK_PB2 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart8m1_xfer: uart8m1-xfer { -- rockchip,pins = -- /* uart8_rx_m1 */ -- <3 RK_PA3 10 &pcfg_pull_up>, -- /* uart8_tx_m1 */ -- <3 RK_PA2 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart8m1_ctsn: uart8m1-ctsn { -- rockchip,pins = -- /* uart8m1_ctsn */ -- <3 RK_PA5 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart8m1_rtsn: uart8m1-rtsn { -- rockchip,pins = -- /* uart8m1_rtsn */ -- <3 RK_PA4 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart8_xfer: uart8-xfer { -- rockchip,pins = -- /* uart8_rx_ */ -- <4 RK_PB1 10 &pcfg_pull_up>; -- }; -- }; -- -- uart9 { -- /omit-if-no-ref/ -- uart9m0_xfer: uart9m0-xfer { -- rockchip,pins = -- /* uart9_rx_m0 */ -- <2 RK_PC4 10 &pcfg_pull_up>, -- /* uart9_tx_m0 */ -- <2 RK_PC2 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart9m1_xfer: uart9m1-xfer { -- rockchip,pins = -- /* uart9_rx_m1 */ -- <4 RK_PB5 10 &pcfg_pull_up>, -- /* uart9_tx_m1 */ -- <4 RK_PB4 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart9m1_ctsn: uart9m1-ctsn { -- rockchip,pins = -- /* uart9m1_ctsn */ -- <4 RK_PA1 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart9m1_rtsn: uart9m1-rtsn { -- rockchip,pins = -- /* uart9m1_rtsn */ -- <4 RK_PA0 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart9m2_xfer: uart9m2-xfer { -- rockchip,pins = -- /* uart9_rx_m2 */ -- <3 RK_PD4 10 &pcfg_pull_up>, -- /* uart9_tx_m2 */ -- <3 RK_PD5 10 &pcfg_pull_up>; -- }; -- -- /omit-if-no-ref/ -- uart9m2_ctsn: uart9m2-ctsn { -- rockchip,pins = -- /* uart9m2_ctsn */ -- <3 RK_PD3 10 &pcfg_pull_none>; -- }; -- -- /omit-if-no-ref/ -- uart9m2_rtsn: uart9m2-rtsn { -- rockchip,pins = -- /* uart9m2_rtsn */ -- <3 RK_PD2 10 &pcfg_pull_none>; -- }; -- }; -- -- vop { -- /omit-if-no-ref/ -- vop_pins: vop-pins { -- rockchip,pins = -- /* vop_post_empty */ -- <1 RK_PA2 1 &pcfg_pull_none>; -- }; -- }; --}; -- --/* -- * This part is edited handly. -- */ --&pinctrl { -- bt656 { -- /omit-if-no-ref/ -- bt656_pins: bt656-pins { -- rockchip,pins = -- /* bt1120_clkout */ -- <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>, -- /* bt1120_d0 */ -- <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>, -- /* bt1120_d1 */ -- <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>, -- /* bt1120_d2 */ -- <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>, -- /* bt1120_d3 */ -- <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>, -- /* bt1120_d4 */ -- <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>, -- /* bt1120_d5 */ -- <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>, -- /* bt1120_d6 */ -- <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>, -- /* bt1120_d7 */ -- <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>; -- }; -- }; -- -- gpio-func { -- /omit-if-no-ref/ -- tsadc_gpio_func: tsadc-gpio-func { -- rockchip,pins = -- <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; --}; diff --git a/target/linux/rockchip/patches-6.6/050-23-v6.11-arm64-dts-rockchip-add-thermal-zones-information-on-RK358.patch b/target/linux/rockchip/patches-6.6/050-23-v6.11-arm64-dts-rockchip-add-thermal-zones-information-on-RK358.patch deleted file mode 100644 index 1a18eb9358..0000000000 --- a/target/linux/rockchip/patches-6.6/050-23-v6.11-arm64-dts-rockchip-add-thermal-zones-information-on-RK358.patch +++ /dev/null @@ -1,193 +0,0 @@ -From 510cd9e688453166b2bff3999ed21cac97385bb5 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 17 Jun 2024 22:28:51 +0400 -Subject: [PATCH] arm64: dts: rockchip: add thermal zones information on RK3588 - -This includes the necessary device tree data to allow thermal -monitoring on RK3588(s) using the on-chip TSADC device, along with -trip points for automatic thermal management. - -Each of the CPU clusters (one for the little cores and two for -the big cores) get a passive cooling trip point at 85C, which -will trigger DVFS throttling of the respective cluster upon -reaching a high temperature condition. - -All zones also have a critical trip point at 115C, which will -trigger a reset. - -Signed-off-by: Alexey Charkov -Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-1-c1f5f3267f1e@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 153 ++++++++++++++++++ - 1 file changed, 153 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - - / { - compatible = "rockchip,rk3588"; -@@ -2368,6 +2369,158 @@ - status = "disabled"; - }; - -+ thermal_zones: thermal-zones { -+ /* sensor near the center of the SoC */ -+ package_thermal: package-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 0>; -+ -+ trips { -+ package_crit: package-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ /* sensor between A76 cores 0 and 1 */ -+ bigcore0_thermal: bigcore0-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 1>; -+ -+ trips { -+ bigcore0_alert: bigcore0-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ bigcore0_crit: bigcore0-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&bigcore0_alert>; -+ cooling-device = -+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ /* sensor between A76 cores 2 and 3 */ -+ bigcore2_thermal: bigcore2-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 2>; -+ -+ trips { -+ bigcore2_alert: bigcore2-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ bigcore2_crit: bigcore2-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&bigcore2_alert>; -+ cooling-device = -+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ /* sensor between the four A55 cores */ -+ little_core_thermal: littlecore-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 3>; -+ -+ trips { -+ littlecore_alert: littlecore-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ littlecore_crit: littlecore-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&littlecore_alert>; -+ cooling-device = -+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ /* sensor near the PD_CENTER power domain */ -+ center_thermal: center-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 4>; -+ -+ trips { -+ center_crit: center-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ gpu_thermal: gpu-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 5>; -+ -+ trips { -+ gpu_crit: gpu-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ npu_thermal: npu-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 6>; -+ -+ trips { -+ npu_crit: npu-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ - tsadc: tsadc@fec00000 { - compatible = "rockchip,rk3588-tsadc"; - reg = <0x0 0xfec00000 0x0 0x400>; diff --git a/target/linux/rockchip/patches-6.6/050-24-v6.11-arm64-dts-rockchip-add-passive-GPU-cooling-on-RK3588.patch b/target/linux/rockchip/patches-6.6/050-24-v6.11-arm64-dts-rockchip-add-passive-GPU-cooling-on-RK3588.patch deleted file mode 100644 index c7a8bb8aa9..0000000000 --- a/target/linux/rockchip/patches-6.6/050-24-v6.11-arm64-dts-rockchip-add-passive-GPU-cooling-on-RK3588.patch +++ /dev/null @@ -1,50 +0,0 @@ -From b78f87940a79321a444083aca46ac3e8e53d1a90 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 17 Jun 2024 22:28:53 +0400 -Subject: [PATCH] arm64: dts: rockchip: add passive GPU cooling on RK3588 - -As the GPU support on RK3588 has been merged upstream, along with OPP -values, add a corresponding cooling map for passive cooling using the GPU. - -Signed-off-by: Alexey Charkov -Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-3-c1f5f3267f1e@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 16 +++++++++++++++- - 1 file changed, 15 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -2493,17 +2493,31 @@ - }; - - gpu_thermal: gpu-thermal { -- polling-delay-passive = <0>; -+ polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&tsadc 5>; - - trips { -+ gpu_alert: gpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ - gpu_crit: gpu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&gpu_alert>; -+ cooling-device = -+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; - }; - - npu_thermal: npu-thermal { diff --git a/target/linux/rockchip/patches-6.6/050-25-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588.patch b/target/linux/rockchip/patches-6.6/050-25-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588.patch deleted file mode 100644 index cb5c254ffb..0000000000 --- a/target/linux/rockchip/patches-6.6/050-25-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588.patch +++ /dev/null @@ -1,205 +0,0 @@ -From 276856db91b46eaa7a4c19226c096a9dc899a3e9 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 17 Jun 2024 22:28:56 +0400 -Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588 - -By default the CPUs on RK3588 start up in a conservative performance -mode. Add frequency and voltage mappings to the device tree to enable -dynamic scaling via cpufreq. - -OPP values are adapted from Radxa's downstream kernel for Rock 5B [1], -stripping them down to the minimum frequency and voltage combinations -as expected by the generic upstream cpufreq-dt driver, and also dropping -those OPPs that don't differ in voltage but only in frequency (keeping -the top frequency OPP in each case). - -Note that this patch ignores voltage scaling for the CPU memory -interface which the downstream kernel does through a custom cpufreq -driver, and which is why the downstream version has two sets of voltage -values for each OPP (the second one being meant for the memory -interface supply regulator). This is done instead via regulator -coupling between CPU and memory interface supplies on affected boards. - -This has been tested on Rock 5B with u-boot 2023.11 compiled from -Collabora's integration tree [2] with binary bl31 and appears to be -stable both under active cooling and passive cooling (with throttling) - -[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -[2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot - -Signed-off-by: Alexey Charkov -Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-6-c1f5f3267f1e@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 149 +++++++++++++++++++ - arch/arm64/boot/dts/rockchip/rk3588.dtsi | 1 + - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 + - 3 files changed, 151 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi - ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi -@@ -0,0 +1,149 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/ { -+ cluster0_opp_table: opp-table-cluster0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1008000000 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <675000 675000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <712500 712500 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1416000000 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <762500 762500 950000>; -+ clock-latency-ns = <40000>; -+ opp-suspend; -+ }; -+ opp-1608000000 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <850000 850000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <950000 950000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ }; -+ -+ cluster1_opp_table: opp-table-cluster1 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <675000 675000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1416000000 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <725000 725000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1608000000 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <762500 762500 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <850000 850000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2016000000 { -+ opp-hz = /bits/ 64 <2016000000>; -+ opp-microvolt = <925000 925000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2208000000 { -+ opp-hz = /bits/ 64 <2208000000>; -+ opp-microvolt = <987500 987500 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2400000000 { -+ opp-hz = /bits/ 64 <2400000000>; -+ opp-microvolt = <1000000 1000000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ }; -+ -+ cluster2_opp_table: opp-table-cluster2 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <675000 675000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1416000000 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <725000 725000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1608000000 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <762500 762500 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <850000 850000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2016000000 { -+ opp-hz = /bits/ 64 <2016000000>; -+ opp-microvolt = <925000 925000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2208000000 { -+ opp-hz = /bits/ 64 <2208000000>; -+ opp-microvolt = <987500 987500 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2400000000 { -+ opp-hz = /bits/ 64 <2400000000>; -+ opp-microvolt = <1000000 1000000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ }; -+}; -+ -+&cpu_b0 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_b1 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_b2 { -+ operating-points-v2 = <&cluster2_opp_table>; -+}; -+ -+&cpu_b3 { -+ operating-points-v2 = <&cluster2_opp_table>; -+}; -+ -+&cpu_l0 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_l1 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_l2 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_l3 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; ---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -@@ -5,3 +5,4 @@ - */ - - #include "rk3588-extra.dtsi" -+#include "rk3588-opp.dtsi" ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -5,3 +5,4 @@ - */ - - #include "rk3588-base.dtsi" -+#include "rk3588-opp.dtsi" diff --git a/target/linux/rockchip/patches-6.6/050-26-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588j.patch b/target/linux/rockchip/patches-6.6/050-26-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588j.patch deleted file mode 100644 index 3b39a60ade..0000000000 --- a/target/linux/rockchip/patches-6.6/050-26-v6.11-arm64-dts-rockchip-Add-OPP-data-for-CPU-cores-on-RK3588j.patch +++ /dev/null @@ -1,140 +0,0 @@ -From 667885a6865832eb0678c7e02e47a3392f177ecb Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 17 Jun 2024 22:28:57 +0400 -Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588j - -RK3588j is the 'industrial' variant of RK3588, and it uses a different -set of OPPs both in terms of allowed frequencies and in terms of -applicable voltages at each frequency setpoint. - -Add the OPPs that apply to RK3588j (and apparently RK3588m too) to -enable dynamic CPU frequency scaling. - -OPP values are derived from Rockchip downstream sources [1] by taking -only those OPPs which have the highest frequency for a given voltage -level and dropping the rest (if they are included, the kernel complains -at boot time about them being inefficient) - -[1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi - -Signed-off-by: Alexey Charkov -Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-7-c1f5f3267f1e@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 108 ++++++++++++++++++++++ - 1 file changed, 108 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi -@@ -5,3 +5,111 @@ - */ - - #include "rk3588-extra.dtsi" -+ -+/ { -+ cluster0_opp_table: opp-table-cluster0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1416000000 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <750000 750000 950000>; -+ clock-latency-ns = <40000>; -+ opp-suspend; -+ }; -+ opp-1608000000 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <887500 887500 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1704000000 { -+ opp-hz = /bits/ 64 <1704000000>; -+ opp-microvolt = <937500 937500 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ }; -+ -+ cluster1_opp_table: opp-table-cluster1 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1416000000 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <750000 750000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1608000000 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <787500 787500 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <875000 875000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2016000000 { -+ opp-hz = /bits/ 64 <2016000000>; -+ opp-microvolt = <950000 950000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ }; -+ -+ cluster2_opp_table: opp-table-cluster2 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1416000000 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <750000 750000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1608000000 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <787500 787500 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <875000 875000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2016000000 { -+ opp-hz = /bits/ 64 <2016000000>; -+ opp-microvolt = <950000 950000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ }; -+}; -+ -+&cpu_b0 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_b1 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_b2 { -+ operating-points-v2 = <&cluster2_opp_table>; -+}; -+ -+&cpu_b3 { -+ operating-points-v2 = <&cluster2_opp_table>; -+}; -+ -+&cpu_l0 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_l1 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_l2 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_l3 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; diff --git a/target/linux/rockchip/patches-6.6/050-27-v6.11-arm64-dts-rockchip-Split-GPU-OPPs-of-RK3588-and-RK3588j.patch b/target/linux/rockchip/patches-6.6/050-27-v6.11-arm64-dts-rockchip-Split-GPU-OPPs-of-RK3588-and-RK3588j.patch deleted file mode 100644 index 06befc8af9..0000000000 --- a/target/linux/rockchip/patches-6.6/050-27-v6.11-arm64-dts-rockchip-Split-GPU-OPPs-of-RK3588-and-RK3588j.patch +++ /dev/null @@ -1,177 +0,0 @@ -From a7b2070505a2a09ea65fa0c8c480c97f62d1978d Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 17 Jun 2024 22:28:58 +0400 -Subject: [PATCH] arm64: dts: rockchip: Split GPU OPPs of RK3588 and RK3588j - -RK3588j uses a different set of OPPs for its GPU, both in terms of -allowed frequencies and in terms of voltages. - -Move the GPU OPPs table into per-variant .dtsi files to accommodate -for this difference. - -The table for RK3588j is adapted from Rockchip downstream sources [1], -while RK3588 one is moved verbatim into the per-variant .dtsi file. -The values provided for RK3588 in the downstream sources match those -in the original commit. - -[1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi - -Fixes: 6fca4edb93d3 ("arm64: dts: rockchip: Add rk3588 GPU node") -Signed-off-by: Alexey Charkov -Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-8-c1f5f3267f1e@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 38 ----------------- - arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 41 +++++++++++++++++++ - arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 33 +++++++++++++++ - 3 files changed, 74 insertions(+), 38 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -451,46 +451,8 @@ - , - ; - interrupt-names = "job", "mmu", "gpu"; -- operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power RK3588_PD_GPU>; - status = "disabled"; -- -- gpu_opp_table: opp-table { -- compatible = "operating-points-v2"; -- -- opp-300000000 { -- opp-hz = /bits/ 64 <300000000>; -- opp-microvolt = <675000 675000 850000>; -- }; -- opp-400000000 { -- opp-hz = /bits/ 64 <400000000>; -- opp-microvolt = <675000 675000 850000>; -- }; -- opp-500000000 { -- opp-hz = /bits/ 64 <500000000>; -- opp-microvolt = <675000 675000 850000>; -- }; -- opp-600000000 { -- opp-hz = /bits/ 64 <600000000>; -- opp-microvolt = <675000 675000 850000>; -- }; -- opp-700000000 { -- opp-hz = /bits/ 64 <700000000>; -- opp-microvolt = <700000 700000 850000>; -- }; -- opp-800000000 { -- opp-hz = /bits/ 64 <800000000>; -- opp-microvolt = <750000 750000 850000>; -- }; -- opp-900000000 { -- opp-hz = /bits/ 64 <900000000>; -- opp-microvolt = <800000 800000 850000>; -- }; -- opp-1000000000 { -- opp-hz = /bits/ 64 <1000000000>; -- opp-microvolt = <850000 850000 850000>; -- }; -- }; - }; - - usb_host0_xhci: usb@fc000000 { ---- a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi -@@ -114,6 +114,43 @@ - clock-latency-ns = <40000>; - }; - }; -+ -+ gpu_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-500000000 { -+ opp-hz = /bits/ 64 <500000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <675000 675000 850000>; -+ }; -+ opp-700000000 { -+ opp-hz = /bits/ 64 <700000000>; -+ opp-microvolt = <700000 700000 850000>; -+ }; -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <750000 750000 850000>; -+ }; -+ opp-900000000 { -+ opp-hz = /bits/ 64 <900000000>; -+ opp-microvolt = <800000 800000 850000>; -+ }; -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <850000 850000 850000>; -+ }; -+ }; - }; - - &cpu_b0 { -@@ -147,3 +184,7 @@ - &cpu_l3 { - operating-points-v2 = <&cluster0_opp_table>; - }; -+ -+&gpu { -+ operating-points-v2 = <&gpu_opp_table>; -+}; ---- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi -@@ -80,6 +80,35 @@ - clock-latency-ns = <40000>; - }; - }; -+ -+ gpu_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <750000 750000 850000>; -+ }; -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <750000 750000 850000>; -+ }; -+ opp-500000000 { -+ opp-hz = /bits/ 64 <500000000>; -+ opp-microvolt = <750000 750000 850000>; -+ }; -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <750000 750000 850000>; -+ }; -+ opp-700000000 { -+ opp-hz = /bits/ 64 <700000000>; -+ opp-microvolt = <750000 750000 850000>; -+ }; -+ opp-850000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <787500 787500 850000>; -+ }; -+ }; - }; - - &cpu_b0 { -@@ -113,3 +142,7 @@ - &cpu_l3 { - operating-points-v2 = <&cluster0_opp_table>; - }; -+ -+&gpu { -+ operating-points-v2 = <&gpu_opp_table>; -+}; diff --git a/target/linux/rockchip/patches-6.6/051-01-v6.8-arm64-dts-rockchip-add-USB3-host-to-rock-5a.patch b/target/linux/rockchip/patches-6.6/051-01-v6.8-arm64-dts-rockchip-add-USB3-host-to-rock-5a.patch deleted file mode 100644 index a9bf3986e2..0000000000 --- a/target/linux/rockchip/patches-6.6/051-01-v6.8-arm64-dts-rockchip-add-USB3-host-to-rock-5a.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 0773a4a199aabb60afe50f5a19a6772abf4ad0bf Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 6 Nov 2023 16:54:32 +0100 -Subject: [PATCH] arm64: dts: rockchip: add USB3 host to rock-5a - -Enable USB3 host controller for the Radxa ROCK 5 Model A. This adds -USB3 for the lower USB3 port (the one closer to the PCB). - -The upper USB3 port uses the RK3588 USB TypeC host controller, which -use a different PHY without upstream support. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20231106155934.80838-2-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -113,6 +113,10 @@ - }; - }; - -+&combphy2_psu { -+ status = "okay"; -+}; -+ - &cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - }; -@@ -734,3 +738,7 @@ - &usb_host1_ohci { - status = "okay"; - }; -+ -+&usb_host2_xhci { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.6/051-02-v6.10-arm64-dts-rockchip-add-upper-USB3-port-to-rock-5a.patch b/target/linux/rockchip/patches-6.6/051-02-v6.10-arm64-dts-rockchip-add-upper-USB3-port-to-rock-5a.patch deleted file mode 100644 index 5c1ebb85ea..0000000000 --- a/target/linux/rockchip/patches-6.6/051-02-v6.10-arm64-dts-rockchip-add-upper-USB3-port-to-rock-5a.patch +++ /dev/null @@ -1,56 +0,0 @@ -From af7ec140ddc1815bc462109792d95bcad05cfbc4 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 9 Apr 2024 00:50:36 +0200 -Subject: [PATCH] arm64: dts: rockchip: add upper USB3 port to rock-5a - -Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from -Radxa Rock 5 Model A. The lower one is already supported. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240408225109.128953-10-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588s-rock-5a.dts | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -698,6 +698,14 @@ - }; - }; - -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ - &u2phy2 { - status = "okay"; - }; -@@ -721,6 +729,11 @@ - status = "okay"; - }; - -+&usbdp_phy0 { -+ status = "okay"; -+ rockchip,dp-lane-mux = <2 3>; -+}; -+ - &usb_host0_ehci { - status = "okay"; - pinctrl-names = "default"; -@@ -731,6 +744,11 @@ - status = "okay"; - }; - -+&usb_host0_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ - &usb_host1_ehci { - status = "okay"; - }; diff --git a/target/linux/rockchip/patches-6.6/051-03-v6.11-arm64-dts-rockchip-add-but-disabled-SFC-node-for-Radxa.patch b/target/linux/rockchip/patches-6.6/051-03-v6.11-arm64-dts-rockchip-add-but-disabled-SFC-node-for-Radxa.patch deleted file mode 100644 index b71246f0ad..0000000000 --- a/target/linux/rockchip/patches-6.6/051-03-v6.11-arm64-dts-rockchip-add-but-disabled-SFC-node-for-Radxa.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 00224650dd45e166ea6eb1593f5f064583963ccf Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Sun, 23 Jun 2024 11:33:28 +0900 -Subject: [PATCH] arm64: dts: rockchip: add (but disabled) SFC node for Radxa - ROCK 5A - -This commit adds SFC node for Radxa ROCK 5A. - -since sdhci and sfc on RK3588s share pins(i.e. exclusive), it cannot -be enabled both nodes at the same time. so status = "okay" is omitted -here. - -you may be able to enable sfc (and disable sdhci) by fdt overlay. - -SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency. - -Signed-off-by: FUKAUMI Naoki -Link: https://lore.kernel.org/r/20240623023329.1044-2-naoki@radxa.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -376,6 +376,19 @@ - status = "okay"; - }; - -+&sfc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fspim0_pins>; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <104000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ - &spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; diff --git a/target/linux/rockchip/patches-6.6/051-04-v6.12-arm64-dts-rockchip-enable-PCIe-on-M.2-E-key-for-Radxa-ROC.patch b/target/linux/rockchip/patches-6.6/051-04-v6.12-arm64-dts-rockchip-enable-PCIe-on-M.2-E-key-for-Radxa-ROC.patch deleted file mode 100644 index e4fe686da9..0000000000 --- a/target/linux/rockchip/patches-6.6/051-04-v6.12-arm64-dts-rockchip-enable-PCIe-on-M.2-E-key-for-Radxa-ROC.patch +++ /dev/null @@ -1,110 +0,0 @@ -From b728d4c51f0ce9207daf502f3a85073785c46319 Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Mon, 26 Aug 2024 17:04:56 +0900 -Subject: [PATCH] arm64: dts: rockchip: enable PCIe on M.2 E key for Radxa ROCK - 5A - -Enable pcie2x1l2 and related combphy/regulator routed to M.2 E key -connector on Radxa ROCK 5A. - -Tested with Radxa Wireless Module A8: - -$ lspci -0004:40:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3588 (rev 01) -0004:41:00.0 Network controller: Realtek Semiconductor Co., Ltd. RTL8852BE PCIe 802.11ax Wireless Network Controller - -$ ip l -1: lo: mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000 - link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00 -2: end0: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 - link/ether c2:58:fc:70:55:86 brd ff:ff:ff:ff:ff:ff -3: wlP4p65s0: mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000 - link/ether 2c:05:47:65:5b:ed brd ff:ff:ff:ff:ff:ff - -$ lsusb -Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub -Bus 001 Device 002: ID 1a40:0101 Terminus Technology Inc. Hub -Bus 001 Device 003: ID 0bda:b85b Realtek Semiconductor Corp. Bluetooth Radio -Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub -Bus 003 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub -Bus 004 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub -Bus 005 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub -Bus 006 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub -Bus 006 Device 002: ID 0789:0336 Logitec Corp. LMD USB Device -Bus 007 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub -Bus 008 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub - -$ hciconfig -hci0: Type: Primary Bus: USB - BD Address: 2C:05:47:65:5B:EE ACL MTU: 1021:6 SCO MTU: 255:12 - UP RUNNING - RX bytes:2698 acl:0 sco:0 events:329 errors:0 - TX bytes:69393 acl:0 sco:0 commands:329 errors:0 - -Signed-off-by: FUKAUMI Naoki -Link: https://lore.kernel.org/r/20240826080456.525-1-naoki@radxa.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588s-rock-5a.dts | 30 +++++++++++++++++++ - 1 file changed, 30 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -64,6 +64,18 @@ - regulator-max-microvolt = <12000000>; - }; - -+ vcc3v3_wf: vcc3v3-wf-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_wf"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&pow_en>; -+ pinctrl-names = "default"; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; -@@ -113,6 +125,10 @@ - }; - }; - -+&combphy0_ps { -+ status = "okay"; -+}; -+ - &combphy2_psu { - status = "okay"; - }; -@@ -292,6 +308,14 @@ - }; - }; - -+&pcie2x1l2 { -+ pinctrl-0 = <&pcie20x1m0_pins>; -+ pinctrl-names = "default"; -+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_wf>; -+ status = "okay"; -+}; -+ - &pinctrl { - leds { - io_led: io-led { -@@ -299,6 +323,12 @@ - }; - }; - -+ pcie { -+ pow_en: pow-en { -+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - power { - vcc_5v0_en: vcc-5v0-en { - rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.6/052-01-v6.7-arm64-dts-rockchip-add-PCIe-network-controller-to-rock-5b.patch b/target/linux/rockchip/patches-6.6/052-01-v6.7-arm64-dts-rockchip-add-PCIe-network-controller-to-rock-5b.patch deleted file mode 100644 index 7ce349d5d8..0000000000 --- a/target/linux/rockchip/patches-6.6/052-01-v6.7-arm64-dts-rockchip-add-PCIe-network-controller-to-rock-5b.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 42145b7a823530f57983fb6e6897f40c0be278d5 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 18 Sep 2023 16:14:49 +0200 -Subject: [PATCH] arm64: dts: rockchip: add PCIe network controller to rock-5b - -Enable the RTL8125 network controller, which is connected via -PCIe. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20230918141451.131247-2-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588-rock-5b.dts | 27 +++++++++++++++++++ - 1 file changed, 27 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -43,6 +43,15 @@ - #cooling-cells = <2>; - }; - -+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie2x1l2"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <5000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; -@@ -77,6 +86,10 @@ - }; - }; - -+&combphy0_ps { -+ status = "okay"; -+}; -+ - &cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - }; -@@ -203,6 +216,14 @@ - }; - }; - -+&pcie2x1l2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_2_rst>; -+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; -+ status = "okay"; -+}; -+ - &pinctrl { - hym8563 { - hym8563_int: hym8563-int { -@@ -216,6 +237,12 @@ - }; - }; - -+ pcie2 { -+ pcie2_2_rst: pcie2-2-rst { -+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.6/052-02-v6.7-arm64-dts-rockchip-add-PCIe-for-M.2-M-key-to-rock-5b.patch b/target/linux/rockchip/patches-6.6/052-02-v6.7-arm64-dts-rockchip-add-PCIe-for-M.2-M-key-to-rock-5b.patch deleted file mode 100644 index 456474cb86..0000000000 --- a/target/linux/rockchip/patches-6.6/052-02-v6.7-arm64-dts-rockchip-add-PCIe-for-M.2-M-key-to-rock-5b.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 199cbd5f195adbc0e70ad218cdba82f45750f11b Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 18 Sep 2023 16:14:50 +0200 -Subject: [PATCH] arm64: dts: rockchip: add PCIe for M.2 M-key to rock-5b - -The Radxa Rock 5B has PCIe 3x4 routed to its M.2 M-key connector -on the board's back. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20230918141451.131247-3-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588-rock-5b.dts | 35 +++++++++++++++++++ - 1 file changed, 35 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -52,6 +52,19 @@ - vin-supply = <&vcc_3v3_s3>; - }; - -+ vcc3v3_pcie30: vcc3v3-pcie30-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie3_vcc3v3_en>; -+ regulator-name = "vcc3v3_pcie30"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <5000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; -@@ -224,6 +237,18 @@ - status = "okay"; - }; - -+&pcie30phy { -+ status = "okay"; -+}; -+ -+&pcie3x4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie3_rst>; -+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+}; -+ - &pinctrl { - hym8563 { - hym8563_int: hym8563-int { -@@ -243,6 +268,16 @@ - }; - }; - -+ pcie3 { -+ pcie3_rst: pcie3-rst { -+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie3_vcc3v3_en: pcie3-vcc3v3-en { -+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.6/052-03-v6.7-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5b.patch b/target/linux/rockchip/patches-6.6/052-03-v6.7-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5b.patch deleted file mode 100644 index 349a17eb77..0000000000 --- a/target/linux/rockchip/patches-6.6/052-03-v6.7-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5b.patch +++ /dev/null @@ -1,80 +0,0 @@ -From da447ec387800bdf2df1fb1d8c1522991d025952 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 18 Sep 2023 16:14:51 +0200 -Subject: [PATCH] arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b - -Enable PCIe2_0 controller and its voltage supply, which is routed -to the M.2 E-Key on the upper side of the Radxa Rock 5B. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20230918141451.131247-4-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588-rock-5b.dts | 35 +++++++++++++++++++ - 1 file changed, 35 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -43,6 +43,21 @@ - #cooling-cells = <2>; - }; - -+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_vcc3v3_en>; -+ regulator-name = "vcc3v3_pcie2x1l0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ - vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie2x1l2"; -@@ -103,6 +118,10 @@ - status = "okay"; - }; - -+&combphy1_ps { -+ status = "okay"; -+}; -+ - &cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - }; -@@ -229,6 +248,14 @@ - }; - }; - -+&pcie2x1l0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_rst>; -+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; -+ status = "okay"; -+}; -+ - &pcie2x1l2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; -@@ -263,6 +290,14 @@ - }; - - pcie2 { -+ pcie2_0_rst: pcie2-0-rst { -+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie2_0_vcc3v3_en: pcie2-0-vcc-en { -+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ - pcie2_2_rst: pcie2-2-rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; diff --git a/target/linux/rockchip/patches-6.6/052-04-v6.7-arm64-dts-rockchip-Add-sdio-node-to-rock-5b.patch b/target/linux/rockchip/patches-6.6/052-04-v6.7-arm64-dts-rockchip-Add-sdio-node-to-rock-5b.patch deleted file mode 100644 index cdf555f450..0000000000 --- a/target/linux/rockchip/patches-6.6/052-04-v6.7-arm64-dts-rockchip-Add-sdio-node-to-rock-5b.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 1c9a53ff7ece056eb995332f0d9523ca43fdcb5a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= -Date: Sun, 24 Sep 2023 20:37:45 +0000 -Subject: [PATCH] arm64: dts: rockchip: Add sdio node to rock-5b -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Enable SDIO on Radxa ROCK 5 Model B M.2 Key E. Add sdio node and alias as mmc2. -Add regulator for the 3.3 V rail bringing it up during boot. Make sure EKEY_EN -is muxed as GPIO. - -Signed-off-by: Tamás Szűcs -Reviewed-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20230924203740.65744-1-tszucs@protonmail.ch -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588-rock-5b.dts | 43 +++++++++++++++++++ - 1 file changed, 43 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -12,6 +12,7 @@ - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; -+ mmc2 = &sdio; - }; - - chosen { -@@ -112,6 +113,21 @@ - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -+ -+ vcc3v3_wf: vcc3v3-wf-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_wf"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc3v3_wf_en>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; - }; - - &combphy0_ps { -@@ -318,6 +334,12 @@ - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -+ -+ m2e { -+ vcc3v3_wf_en: vcc3v3-wf-en { -+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; - }; - - &pwm1 { -@@ -354,6 +376,27 @@ - status = "okay"; - }; - -+&sdio { -+ max-frequency = <200000000>; -+ no-sd; -+ no-mmc; -+ non-removable; -+ bus-width = <4>; -+ cap-sdio-irq; -+ disable-wp; -+ keep-power-in-suspend; -+ wakeup-source; -+ sd-uhs-sdr12; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v3_wf>; -+ vqmmc-supply = <&vcc_1v8_s3>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdiom0_pins>; -+ status = "okay"; -+}; -+ - &spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; diff --git a/target/linux/rockchip/patches-6.6/052-05-v6.8-arm64-dts-rockchip-Remove-duplicate-regulator-vcc3v3_wf.patch b/target/linux/rockchip/patches-6.6/052-05-v6.8-arm64-dts-rockchip-Remove-duplicate-regulator-vcc3v3_wf.patch deleted file mode 100644 index 3d1283d31f..0000000000 --- a/target/linux/rockchip/patches-6.6/052-05-v6.8-arm64-dts-rockchip-Remove-duplicate-regulator-vcc3v3_wf.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 0002c377e862140ad65b67b8b9dbf086d4578f95 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= -Date: Wed, 11 Oct 2023 18:18:05 +0000 -Subject: [PATCH] arm64: dts: rockchip: Remove duplicate regulator vcc3v3_wf - from rock-5b -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Regulator for VCC3V3_WF has been added as vcc3v3_pcie2x1l0 first. Clean this up. - -Fixes: 1c9a53ff7ece ("arm64: dts: rockchip: Add sdio node to rock-5b") -Signed-off-by: Tamás Szűcs -Link: https://lore.kernel.org/r/20231011181757.58047-1-tszucs@protonmail.ch -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588-rock-5b.dts | 23 +------------------ - 1 file changed, 1 insertion(+), 22 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -113,21 +113,6 @@ - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -- -- vcc3v3_wf: vcc3v3-wf-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc3v3_wf"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- enable-active-high; -- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&vcc3v3_wf_en>; -- startup-delay-us = <50000>; -- vin-supply = <&vcc5v0_sys>; -- }; - }; - - &combphy0_ps { -@@ -334,12 +319,6 @@ - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -- -- m2e { -- vcc3v3_wf_en: vcc3v3-wf-en { -- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; - }; - - &pwm1 { -@@ -390,7 +369,7 @@ - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; -- vmmc-supply = <&vcc3v3_wf>; -+ vmmc-supply = <&vcc3v3_pcie2x1l0>; - vqmmc-supply = <&vcc_1v8_s3>; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom0_pins>; diff --git a/target/linux/rockchip/patches-6.6/052-06-v6.8-arm64-dts-rockchip-Enable-UART6-on-rock-5b.patch b/target/linux/rockchip/patches-6.6/052-06-v6.8-arm64-dts-rockchip-Enable-UART6-on-rock-5b.patch deleted file mode 100644 index 41c108f01a..0000000000 --- a/target/linux/rockchip/patches-6.6/052-06-v6.8-arm64-dts-rockchip-Enable-UART6-on-rock-5b.patch +++ /dev/null @@ -1,32 +0,0 @@ -From a6169ab369236f15c79b45037074a2567d30b037 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= -Date: Fri, 13 Oct 2023 23:51:53 +0200 -Subject: [PATCH] arm64: dts: rockchip: Enable UART6 on rock-5b -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Enable UART lines on Radxa ROCK 5 Model B M.2 Key E. - -Signed-off-by: Tamás Szűcs -Link: https://lore.kernel.org/r/20231013215208.81345-1-szucst@iit.uni-miskolc.hu -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -376,6 +376,12 @@ - status = "okay"; - }; - -+&uart6 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; -+ status = "okay"; -+}; -+ - &spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; diff --git a/target/linux/rockchip/patches-6.6/052-07-v6.8-arm64-dts-rockchip-add-status-LED-to-rock-5b.patch b/target/linux/rockchip/patches-6.6/052-07-v6.8-arm64-dts-rockchip-add-status-LED-to-rock-5b.patch deleted file mode 100644 index 03d1ed860f..0000000000 --- a/target/linux/rockchip/patches-6.6/052-07-v6.8-arm64-dts-rockchip-add-status-LED-to-rock-5b.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 7952cbbda301f7d297c6ac761f9dfafb90205358 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 5 Oct 2023 15:40:37 +0200 -Subject: [PATCH] arm64: dts: rockchip: add status LED to rock-5b - -Describe the Rock 5B status LED in its device tree. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20231005134037.33231-1-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588-rock-5b.dts | 20 +++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -3,6 +3,7 @@ - /dts-v1/; - - #include -+#include - #include "rk3588.dtsi" - - / { -@@ -36,6 +37,19 @@ - pinctrl-0 = <&hp_detect>; - }; - -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_rgb_b>; -+ -+ led_rgb_b { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 95 145 195 255>; -@@ -284,6 +298,12 @@ - }; - }; - -+ leds { -+ led_rgb_b: led-rgb-b { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - sound { - hp_detect: hp-detect { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.6/052-08-v6.8-arm64-dts-rockchip-add-USB3-host-to-rock-5b.patch b/target/linux/rockchip/patches-6.6/052-08-v6.8-arm64-dts-rockchip-add-USB3-host-to-rock-5b.patch deleted file mode 100644 index b288ba858b..0000000000 --- a/target/linux/rockchip/patches-6.6/052-08-v6.8-arm64-dts-rockchip-add-USB3-host-to-rock-5b.patch +++ /dev/null @@ -1,39 +0,0 @@ -From f97d78b9f6cff4c680206a8c8b03f726f0dc2c8b Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 6 Nov 2023 16:54:31 +0100 -Subject: [PATCH] arm64: dts: rockchip: add USB3 host to rock-5b - -Enable USB3 host controller for the Radxa ROCK 5 Model B. This adds -USB3 for the upper USB3 port (the one further away from the PCB). - -The lower USB3 and the USB-C ports use the RK3588 USB TypeC host -controller, which use a different PHY without upstream support. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20231106155934.80838-1-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -137,6 +137,10 @@ - status = "okay"; - }; - -+&combphy2_psu { -+ status = "okay"; -+}; -+ - &cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - }; -@@ -764,3 +768,7 @@ - &usb_host1_ohci { - status = "okay"; - }; -+ -+&usb_host2_xhci { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.6/052-09-v6.9-arm64-dts-rockchip-support-poweroff-on-the-rock-5b.patch b/target/linux/rockchip/patches-6.6/052-09-v6.9-arm64-dts-rockchip-support-poweroff-on-the-rock-5b.patch deleted file mode 100644 index a1d2b7fe10..0000000000 --- a/target/linux/rockchip/patches-6.6/052-09-v6.9-arm64-dts-rockchip-support-poweroff-on-the-rock-5b.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 7738f551173540b3daa63a91b384b167eacd24fd Mon Sep 17 00:00:00 2001 -From: John Clark -Date: Mon, 25 Dec 2023 22:28:19 +0000 -Subject: [PATCH] arm64: dts: rockchip: support poweroff on the rock-5b - -Allow the rock-5b to poweroff its pmic. When issuing a "shutdown -h now" -on the rock-5b it reboots instead. Defining 'system-power-controller' -allows the rk806 to power down. - -Commit c699fbfdfd54 ("arm64: dts: rockchip: Support poweroff on -NanoPC-T6") similarly resolves this issue for the nanopc-t6. - -Signed-off-by: John Clark -Reviewed-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20231225222859.17153-1-inindev@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -426,6 +426,8 @@ - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - -+ system-power-controller; -+ - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; diff --git a/target/linux/rockchip/patches-6.6/052-10-v6.9-arm64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-rock-5b.patch b/target/linux/rockchip/patches-6.6/052-10-v6.9-arm64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-rock-5b.patch deleted file mode 100644 index 616f7a742f..0000000000 --- a/target/linux/rockchip/patches-6.6/052-10-v6.9-arm64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-rock-5b.patch +++ /dev/null @@ -1,27 +0,0 @@ -From aed6514c4e3aee843385ded4c5ee0921b51c30fa Mon Sep 17 00:00:00 2001 -From: John Clark -Date: Mon, 25 Dec 2023 22:28:20 +0000 -Subject: [PATCH] arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b - -Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and -gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1. - -Signed-off-by: John Clark -Reviewed-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20231225222859.17153-2-inindev@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -448,7 +448,7 @@ - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { -- pins = "gpio_pwrctrl2"; -+ pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - diff --git a/target/linux/rockchip/patches-6.6/052-11-v6.9-arm64-dts-rockchip-add-rfkill-node-for-M-2-Key-E-WiFi-on-.patch b/target/linux/rockchip/patches-6.6/052-11-v6.9-arm64-dts-rockchip-add-rfkill-node-for-M-2-Key-E-WiFi-on-.patch deleted file mode 100644 index 31ca0b8479..0000000000 --- a/target/linux/rockchip/patches-6.6/052-11-v6.9-arm64-dts-rockchip-add-rfkill-node-for-M-2-Key-E-WiFi-on-.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 82d40b141a4c7ab6608a84a5ce0c58b747cb7163 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Sun, 7 Jan 2024 00:26:45 +0400 -Subject: [PATCH] arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b - -By default the GPIO pin that connects to the WiFi enable signal -inside the M.2 Key E slot is driven low, resulting in impossibility -to connect to any network. Add a DT node to expose it as an RFKILL -device, which lets the WiFi driver or userspace toggle it as -required. - -Signed-off-by: Alexey Charkov -Link: https://lore.kernel.org/r/20240106202650.22310-1-alchark@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -58,6 +58,13 @@ - #cooling-cells = <2>; - }; - -+ rfkill { -+ compatible = "rfkill-gpio"; -+ label = "rfkill-pcie-wlan"; -+ radio-type = "wlan"; -+ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -+ }; -+ - vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { - compatible = "regulator-fixed"; - enable-active-high; diff --git a/target/linux/rockchip/patches-6.6/052-12-v6.10-arm64-dts-rockchip-Enable-GPU-on-rk3588-rock5b.patch b/target/linux/rockchip/patches-6.6/052-12-v6.10-arm64-dts-rockchip-Enable-GPU-on-rk3588-rock5b.patch deleted file mode 100644 index 69c0c2551e..0000000000 --- a/target/linux/rockchip/patches-6.6/052-12-v6.10-arm64-dts-rockchip-Enable-GPU-on-rk3588-rock5b.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 038347286941148b6fd0cc2c40afcd540315aa6f Mon Sep 17 00:00:00 2001 -From: Boris Brezillon -Date: Tue, 26 Mar 2024 17:52:07 +0100 -Subject: [PATCH] arm64: dts: rockchip: Enable GPU on rk3588-rock5b - -Enable the Mali GPU in the Rock 5B. - -Signed-off-by: Boris Brezillon -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240326165232.73585-4-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -180,6 +180,11 @@ - cpu-supply = <&vdd_cpu_lit_s0>; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu_s0>; -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; diff --git a/target/linux/rockchip/patches-6.6/052-13-v6.10-arm64-dts-rockchip-Correct-the-model-names-for-Radxa-ROCK.patch b/target/linux/rockchip/patches-6.6/052-13-v6.10-arm64-dts-rockchip-Correct-the-model-names-for-Radxa-ROCK.patch deleted file mode 100644 index 99e98a8655..0000000000 --- a/target/linux/rockchip/patches-6.6/052-13-v6.10-arm64-dts-rockchip-Correct-the-model-names-for-Radxa-ROCK.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 45e831033f7a00a14f64afa1e34c476a9ff0f9f0 Mon Sep 17 00:00:00 2001 -From: Dragan Simic -Date: Thu, 18 Apr 2024 18:26:20 +0200 -Subject: [PATCH] arm64: dts: rockchip: Correct the model names for Radxa ROCK - 5 boards - -Correct the descriptions of a few Radxa boards, according to the up-to-date -documentation from Radxa and the detailed explanation from Naoki. [1] To sum -it up, the short naming, as specified by Radxa, is preferred. - -[1] https://lore.kernel.org/linux-rockchip/B26C732A4DCEA9B3+282b8775-601b-4d4a-a513-4924b7940076@radxa.com/ - -Suggested-by: FUKAUMI Naoki -Signed-off-by: Dragan Simic -Link: https://lore.kernel.org/r/6931289a252dc2d6c7bfd2388835c5e98ba0d8c9.1713457260.git.dsimic@manjaro.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -7,7 +7,7 @@ - #include "rk3588.dtsi" - - / { -- model = "Radxa ROCK 5 Model B"; -+ model = "Radxa ROCK 5B"; - compatible = "radxa,rock-5b", "rockchip,rk3588"; - - aliases { ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -8,7 +8,7 @@ - #include "rk3588s.dtsi" - - / { -- model = "Radxa ROCK 5 Model A"; -+ model = "Radxa ROCK 5A"; - compatible = "radxa,rock-5a", "rockchip,rk3588s"; - - aliases { diff --git a/target/linux/rockchip/patches-6.6/052-13-v6.10-arm64-dts-rockchip-add-lower-USB3-port-to-rock-5b.patch b/target/linux/rockchip/patches-6.6/052-13-v6.10-arm64-dts-rockchip-add-lower-USB3-port-to-rock-5b.patch deleted file mode 100644 index 8a3fab1576..0000000000 --- a/target/linux/rockchip/patches-6.6/052-13-v6.10-arm64-dts-rockchip-add-lower-USB3-port-to-rock-5b.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 494532921aacb496529d544fedfdb3a7b43dfef0 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 9 Apr 2024 00:50:37 +0200 -Subject: [PATCH] arm64: dts: rockchip: add lower USB3 port to rock-5b - -Enable full support (XHCI, EHCI, OHCI) for the lower USB3 port from -Radxa Rock 5 Model B. The upper one is already supported. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20240408225109.128953-11-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -748,6 +748,14 @@ - status = "okay"; - }; - -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ - &u2phy2 { - status = "okay"; - }; -@@ -767,6 +775,10 @@ - status = "okay"; - }; - -+&usbdp_phy1 { -+ status = "okay"; -+}; -+ - &usb_host0_ehci { - status = "okay"; - }; -@@ -783,6 +795,11 @@ - status = "okay"; - }; - -+&usb_host1_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ - &usb_host2_xhci { - status = "okay"; - }; diff --git a/target/linux/rockchip/patches-6.6/052-14-v6.11-arm64-dts-rockchip-enable-automatic-fan-control-on-Rock-5.patch b/target/linux/rockchip/patches-6.6/052-14-v6.11-arm64-dts-rockchip-enable-automatic-fan-control-on-Rock-5.patch deleted file mode 100644 index 0b2d0a3dec..0000000000 --- a/target/linux/rockchip/patches-6.6/052-14-v6.11-arm64-dts-rockchip-enable-automatic-fan-control-on-Rock-5.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 4a152231b050590af771fa3cc8462ed08b691a24 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 17 Jun 2024 22:28:54 +0400 -Subject: [PATCH] arm64: dts: rockchip: enable automatic fan control on Rock 5B - -This links the PWM fan on Radxa Rock 5B as an active cooling device -managed automatically by the thermal subsystem, with a target SoC -temperature of 65C and a minimum-spin interval from 55C to 65C to -ensure airflow when the system gets warm - -Helped-by: Dragan Simic -Reviewed-by: Dragan Simic -Signed-off-by: Alexey Charkov -Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-4-c1f5f3267f1e@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588-rock-5b.dts | 32 ++++++++++++++++++- - 1 file changed, 31 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -52,7 +52,7 @@ - - fan: pwm-fan { - compatible = "pwm-fan"; -- cooling-levels = <0 95 145 195 255>; -+ cooling-levels = <0 120 150 180 210 240 255>; - fan-supply = <&vcc5v0_sys>; - pwms = <&pwm1 0 50000 0>; - #cooling-cells = <2>; -@@ -278,6 +278,36 @@ - }; - }; - }; -+ -+&package_thermal { -+ polling-delay = <1000>; -+ -+ trips { -+ package_fan0: package-fan0 { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ package_fan1: package-fan1 { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map1 { -+ trip = <&package_fan0>; -+ cooling-device = <&fan THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map2 { -+ trip = <&package_fan1>; -+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; - - &pcie2x1l0 { - pinctrl-names = "default"; diff --git a/target/linux/rockchip/patches-6.6/052-15-v6.11-arm64-dts-rockchip-add-SFC-support-for-Radxa-ROCK-5B.patch b/target/linux/rockchip/patches-6.6/052-15-v6.11-arm64-dts-rockchip-add-SFC-support-for-Radxa-ROCK-5B.patch deleted file mode 100644 index 043b983877..0000000000 --- a/target/linux/rockchip/patches-6.6/052-15-v6.11-arm64-dts-rockchip-add-SFC-support-for-Radxa-ROCK-5B.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 9204a7ecca96403ee3d61c14cb9eb87ec89b0fcd Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Sun, 23 Jun 2024 11:33:27 +0900 -Subject: [PATCH] arm64: dts: rockchip: add SFC support for Radxa ROCK 5B - -This commit adds support for SPI NOR flash on Radxa ROCK 5B. - -SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency. - -Signed-off-by: FUKAUMI Naoki -Link: https://lore.kernel.org/r/20240623023329.1044-1-naoki@radxa.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -442,6 +442,20 @@ - status = "okay"; - }; - -+&sfc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fspim2_pins>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <104000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ - &uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; diff --git a/target/linux/rockchip/patches-6.6/053-01-v6.8-arm64-dts-rockchip-Support-poweroff-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/053-01-v6.8-arm64-dts-rockchip-Support-poweroff-on-NanoPC-T6.patch deleted file mode 100644 index e8c9924e86..0000000000 --- a/target/linux/rockchip/patches-6.6/053-01-v6.8-arm64-dts-rockchip-Support-poweroff-on-NanoPC-T6.patch +++ /dev/null @@ -1,26 +0,0 @@ -From c699fbfdfd54630fc51b96da577f02e7b772eb37 Mon Sep 17 00:00:00 2001 -From: Hugh Cole-Baker -Date: Sat, 16 Dec 2023 21:21:34 +0000 -Subject: [PATCH] arm64: dts: rockchip: Support poweroff on NanoPC-T6 - -The RK806 on the NanoPC-T6 can be used to power on/off the whole board. -Mark it as the system power controller. - -Signed-off-by: Hugh Cole-Baker -Link: https://lore.kernel.org/r/20231216212134.23314-1-sigmaris@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -569,6 +569,8 @@ - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - -+ system-power-controller; -+ - vcc1-supply = <&vcc4v0_sys>; - vcc2-supply = <&vcc4v0_sys>; - vcc3-supply = <&vcc4v0_sys>; diff --git a/target/linux/rockchip/patches-6.6/053-02-v6.9-arm64-dts-rockchip-nanopc-t6-sdmmc-beautification.patch b/target/linux/rockchip/patches-6.6/053-02-v6.9-arm64-dts-rockchip-nanopc-t6-sdmmc-beautification.patch deleted file mode 100644 index 3f5dd481c9..0000000000 --- a/target/linux/rockchip/patches-6.6/053-02-v6.9-arm64-dts-rockchip-nanopc-t6-sdmmc-beautification.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 9e1faff1cbc877903d019a7943d37ddc5042704d Mon Sep 17 00:00:00 2001 -From: John Clark -Date: Thu, 28 Dec 2023 17:29:35 +0000 -Subject: [PATCH] arm64: dts: rockchip: nanopc-t6 sdmmc beautification - -drop max-frequency = <200000000> as it is already defined in rk3588s.dtsi -order no-sdio & no-mmc properties while we are here - -Signed-off-by: John Clark -Link: https://lore.kernel.org/r/20231228173011.2863-1-inindev@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 5 ++--- - 1 file changed, 2 insertions(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -536,13 +536,12 @@ - }; - - &sdmmc { -- max-frequency = <200000000>; -- no-sdio; -- no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -+ no-mmc; -+ no-sdio; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; diff --git a/target/linux/rockchip/patches-6.6/053-03-v6.9-arm64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-nanopc-t.patch b/target/linux/rockchip/patches-6.6/053-03-v6.9-arm64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-nanopc-t.patch deleted file mode 100644 index beab9154f8..0000000000 --- a/target/linux/rockchip/patches-6.6/053-03-v6.9-arm64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-nanopc-t.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 24559788384916041a0bbf54c32e2a16b612d247 Mon Sep 17 00:00:00 2001 -From: John Clark -Date: Mon, 25 Dec 2023 22:32:16 +0000 -Subject: [PATCH] arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6 - -Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and -gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1. - -Signed-off-by: John Clark -Link: https://lore.kernel.org/r/20231225223226.17690-1-inindev@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -590,7 +590,7 @@ - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { -- pins = "gpio_pwrctrl2"; -+ pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - diff --git a/target/linux/rockchip/patches-6.6/053-04-v6.9-arm64-dts-rockchip-enable-NanoPC-T6-MiniPCIe-power.patch b/target/linux/rockchip/patches-6.6/053-04-v6.9-arm64-dts-rockchip-enable-NanoPC-T6-MiniPCIe-power.patch deleted file mode 100644 index 1126bc3d38..0000000000 --- a/target/linux/rockchip/patches-6.6/053-04-v6.9-arm64-dts-rockchip-enable-NanoPC-T6-MiniPCIe-power.patch +++ /dev/null @@ -1,57 +0,0 @@ -From d235e65adf00f6db09331874c5a987b7fe18023b Mon Sep 17 00:00:00 2001 -From: Hugh Cole-Baker -Date: Tue, 9 Jan 2024 20:27:28 +0000 -Subject: [PATCH] arm64: dts: rockchip: enable NanoPC-T6 MiniPCIe power - -The NanoPC-T6 has a Mini PCIe slot intended to be used for a 4G or LTE -modem. This slot has no PCIe functionality, only USB 2.0 pins are wired -to the SoC, and USIM pins are wired to a SIM card slot on the board. -Define the 3.3v supply for the slot so it can be used. - -Signed-off-by: Hugh Cole-Baker -Link: https://lore.kernel.org/r/20240109202729.54292-1-sigmaris@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -159,6 +159,18 @@ - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; -+ -+ vdd_4g_3v3: vdd-4g-3v3-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pin_4g_lte_pwren>; -+ regulator-name = "vdd_4g_3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; - }; - - &combphy0_ps { -@@ -504,6 +516,10 @@ - }; - - usb { -+ pin_4g_lte_pwren: 4g-lte-pwren { -+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ - typec5v_pwren: typec5v-pwren { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; -@@ -884,6 +900,7 @@ - }; - - &u2phy2_host { -+ phy-supply = <&vdd_4g_3v3>; - status = "okay"; - }; - diff --git a/target/linux/rockchip/patches-6.6/053-05-v6.9-arm64-dts-rockchip-add-sdmmc-card-detect-to-the-nanopc-t6.patch b/target/linux/rockchip/patches-6.6/053-05-v6.9-arm64-dts-rockchip-add-sdmmc-card-detect-to-the-nanopc-t6.patch deleted file mode 100644 index 3709c10528..0000000000 --- a/target/linux/rockchip/patches-6.6/053-05-v6.9-arm64-dts-rockchip-add-sdmmc-card-detect-to-the-nanopc-t6.patch +++ /dev/null @@ -1,25 +0,0 @@ -From d8bb6c2311b6b2aad11b937f96db1d6c3393246a Mon Sep 17 00:00:00 2001 -From: John Clark -Date: Sat, 30 Dec 2023 11:50:53 -0500 -Subject: [PATCH] arm64: dts: rockchip: add sdmmc card detect to the nanopc-t6 - -The nanopc-t6 has an sdmmc card detect connected to gpio0_a4 which is -active low. - -Signed-off-by: John Clark -Link: https://lore.kernel.org/r/20231230165053.3781-1-inindev@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -555,6 +555,7 @@ - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - no-mmc; - no-sdio; diff --git a/target/linux/rockchip/patches-6.6/053-06-v6.9-arm64-dts-rockchip-fix-nanopc-t6-sdmmc-regulator.patch b/target/linux/rockchip/patches-6.6/053-06-v6.9-arm64-dts-rockchip-fix-nanopc-t6-sdmmc-regulator.patch deleted file mode 100644 index 1c17bc638f..0000000000 --- a/target/linux/rockchip/patches-6.6/053-06-v6.9-arm64-dts-rockchip-fix-nanopc-t6-sdmmc-regulator.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 6cb02674a061e4ef4f437ab60c91038d4c0d85ef Mon Sep 17 00:00:00 2001 -From: John Clark -Date: Tue, 2 Jan 2024 02:40:53 +0000 -Subject: [PATCH] arm64: dts: rockchip: fix nanopc-t6 sdmmc regulator - -sdmmc on the nanopc-t6 is powered by vcc3v3_sd_s0, not vcc_3v3_s3 -add the vcc3v3_sd_s0 regulator, and control it with gpio4_a5 - -Signed-off-by: John Clark -Link: https://lore.kernel.org/r/20240102024054.1030313-1-inindev@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 13 ++++++++++++- - 1 file changed, 12 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -160,6 +160,17 @@ - vin-supply = <&vcc5v0_sys>; - }; - -+ vcc3v3_sd_s0: vcc3v3-sd-s0-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-low; -+ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; -+ regulator-boot-on; -+ regulator-max-microvolt = <3300000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-name = "vcc3v3_sd_s0"; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ - vdd_4g_3v3: vdd-4g-3v3-regulator { - compatible = "regulator-fixed"; - enable-active-high; -@@ -560,7 +571,7 @@ - no-mmc; - no-sdio; - sd-uhs-sdr104; -- vmmc-supply = <&vcc_3v3_s3>; -+ vmmc-supply = <&vcc3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; - }; diff --git a/target/linux/rockchip/patches-6.6/053-08-v6.12-arm64-dts-rockchip-prepare-NanoPC-T6-for-LTS-board.patch b/target/linux/rockchip/patches-6.6/053-08-v6.12-arm64-dts-rockchip-prepare-NanoPC-T6-for-LTS-board.patch deleted file mode 100644 index 415c34fff6..0000000000 --- a/target/linux/rockchip/patches-6.6/053-08-v6.12-arm64-dts-rockchip-prepare-NanoPC-T6-for-LTS-board.patch +++ /dev/null @@ -1,1916 +0,0 @@ -From d14f3a4f1feabb6bb5935bf3b275a1e6bf2208eb Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:53 +0200 -Subject: [PATCH] arm64: dts: rockchip: prepare NanoPC-T6 for LTS board - -FriendlyELEC introduced a second version of NanoPC-T6 SBC. - -Create common include file and make NanoPC-T6 use it. Following -patches will add LTS version. - -Signed-off-by: Marcin Juszkiewicz -Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-2-edff247e8c02@linaro.org -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588-nanopc-t6.dts | 932 +---------------- - .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 945 ++++++++++++++++++ - 2 files changed, 947 insertions(+), 930 deletions(-) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -2,944 +2,16 @@ - /* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 Thomas McKahan -+ * Copyright (c) 2024 Linaro Ltd. - * - */ - - /dts-v1/; - --#include --#include --#include --#include "rk3588.dtsi" -+#include "rk3588-nanopc-t6.dtsi" - - / { - model = "FriendlyElec NanoPC-T6"; - compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; - -- aliases { -- mmc0 = &sdhci; -- mmc1 = &sdmmc; -- }; -- -- chosen { -- stdout-path = "serial2:1500000n8"; -- }; -- -- leds { -- compatible = "gpio-leds"; -- -- sys_led: led-0 { -- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -- label = "system-led"; -- linux,default-trigger = "heartbeat"; -- pinctrl-names = "default"; -- pinctrl-0 = <&sys_led_pin>; -- }; -- -- usr_led: led-1 { -- gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; -- label = "user-led"; -- pinctrl-names = "default"; -- pinctrl-0 = <&usr_led_pin>; -- }; -- }; -- -- sound { -- compatible = "simple-audio-card"; -- pinctrl-names = "default"; -- pinctrl-0 = <&hp_det>; -- -- simple-audio-card,name = "realtek,rt5616-codec"; -- simple-audio-card,format = "i2s"; -- simple-audio-card,mclk-fs = <256>; -- -- simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; -- simple-audio-card,hp-pin-name = "Headphones"; -- -- simple-audio-card,widgets = -- "Headphone", "Headphones", -- "Microphone", "Microphone Jack"; -- simple-audio-card,routing = -- "Headphones", "HPOL", -- "Headphones", "HPOR", -- "MIC1", "Microphone Jack", -- "Microphone Jack", "micbias1"; -- -- simple-audio-card,cpu { -- sound-dai = <&i2s0_8ch>; -- }; -- simple-audio-card,codec { -- sound-dai = <&rt5616>; -- }; -- }; -- -- vcc12v_dcin: vcc12v-dcin-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc12v_dcin"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <12000000>; -- regulator-max-microvolt = <12000000>; -- }; -- -- /* vcc5v0_sys powers peripherals */ -- vcc5v0_sys: vcc5v0-sys-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc5v0_sys"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- vin-supply = <&vcc12v_dcin>; -- }; -- -- /* vcc4v0_sys powers the RK806, RK860's */ -- vcc4v0_sys: vcc4v0-sys-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc4v0_sys"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <4000000>; -- regulator-max-microvolt = <4000000>; -- vin-supply = <&vcc12v_dcin>; -- }; -- -- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc-1v1-nldo-s3"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1100000>; -- regulator-max-microvolt = <1100000>; -- vin-supply = <&vcc4v0_sys>; -- }; -- -- vcc_3v3_pcie20: vcc3v3-pcie20-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc_3v3_pcie20"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc_3v3_s3>; -- }; -- -- vbus5v0_typec: vbus5v0-typec-regulator { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&typec5v_pwren>; -- regulator-name = "vbus5v0_typec"; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie_m2_1_pwren>; -- regulator-name = "vcc3v3_pcie2x1l0"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc3v3_pcie30: vcc3v3-pcie30-regulator { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie_m2_0_pwren>; -- regulator-name = "vcc3v3_pcie30"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc3v3_sd_s0: vcc3v3-sd-s0-regulator { -- compatible = "regulator-fixed"; -- enable-active-low; -- gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; -- regulator-boot-on; -- regulator-max-microvolt = <3300000>; -- regulator-min-microvolt = <3300000>; -- regulator-name = "vcc3v3_sd_s0"; -- vin-supply = <&vcc_3v3_s3>; -- }; -- -- vdd_4g_3v3: vdd-4g-3v3-regulator { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pin_4g_lte_pwren>; -- regulator-name = "vdd_4g_3v3"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc5v0_sys>; -- }; --}; -- --&combphy0_ps { -- status = "okay"; --}; -- --&combphy1_ps { -- status = "okay"; --}; -- --&combphy2_psu { -- status = "okay"; --}; -- --&cpu_l0 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_l1 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_l2 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_l3 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_b0{ -- cpu-supply = <&vdd_cpu_big0_s0>; --}; -- --&cpu_b1{ -- cpu-supply = <&vdd_cpu_big0_s0>; --}; -- --&cpu_b2{ -- cpu-supply = <&vdd_cpu_big1_s0>; --}; -- --&cpu_b3{ -- cpu-supply = <&vdd_cpu_big1_s0>; --}; -- --&gpio0 { -- gpio-line-names = /* GPIO0 A0-A7 */ -- "", "", "", "", -- "", "", "", "", -- /* GPIO0 B0-B7 */ -- "", "", "", "", -- "", "", "", "", -- /* GPIO0 C0-C7 */ -- "", "", "", "", -- "HEADER_10", "HEADER_08", "HEADER_32", "", -- /* GPIO0 D0-D7 */ -- "", "", "", "", -- "", "", "", ""; --}; -- --&gpio1 { -- gpio-line-names = /* GPIO1 A0-A7 */ -- "HEADER_27", "HEADER_28", "", "", -- "", "", "", "HEADER_15", -- /* GPIO1 B0-B7 */ -- "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23", -- "HEADER_24", "HEADER_22", "", "", -- /* GPIO1 C0-C7 */ -- "", "", "", "", -- "", "", "", "", -- /* GPIO1 D0-D7 */ -- "", "", "", "", -- "", "", "HEADER_05", "HEADER_03"; --}; -- --&gpio2 { -- gpio-line-names = /* GPIO2 A0-A7 */ -- "", "", "", "", -- "", "", "", "", -- /* GPIO2 B0-B7 */ -- "", "", "", "", -- "", "", "", "", -- /* GPIO2 C0-C7 */ -- "", "CSI1_11", "CSI1_12", "", -- "", "", "", "", -- /* GPIO2 D0-D7 */ -- "", "", "", "", -- "", "", "", ""; --}; -- --&gpio3 { -- gpio-line-names = /* GPIO3 A0-A7 */ -- "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36", -- "HEADER_37", "", "DSI0_12", "", -- /* GPIO3 B0-B7 */ -- "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16", -- "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12", -- /* GPIO3 C0-C7 */ -- "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13", -- "", "", "", "", -- /* GPIO3 D0-D7 */ -- "", "", "", "", -- "", "DSI1_10", "", ""; --}; -- --&gpio4 { -- gpio-line-names = /* GPIO4 A0-A7 */ -- "DSI1_08", "DSI1_14", "", "DSI1_12", -- "", "", "", "", -- /* GPIO4 B0-B7 */ -- "", "", "", "", -- "", "", "", "", -- /* GPIO4 C0-C7 */ -- "", "", "", "", -- "CSI0_11", "CSI0_12", "", "", -- /* GPIO4 D0-D7 */ -- "", "", "", "", -- "", "", "", ""; --}; -- --&i2c0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c0m2_xfer>; -- status = "okay"; -- -- vdd_cpu_big0_s0: regulator@42 { -- compatible = "rockchip,rk8602"; -- reg = <0x42>; -- fcs,suspend-voltage-selector = <1>; -- regulator-name = "vdd_cpu_big0_s0"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <1050000>; -- regulator-ramp-delay = <2300>; -- vin-supply = <&vcc4v0_sys>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_cpu_big1_s0: regulator@43 { -- compatible = "rockchip,rk8603", "rockchip,rk8602"; -- reg = <0x43>; -- fcs,suspend-voltage-selector = <1>; -- regulator-name = "vdd_cpu_big1_s0"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <1050000>; -- regulator-ramp-delay = <2300>; -- vin-supply = <&vcc4v0_sys>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; --}; -- --&i2c2 { -- status = "okay"; -- -- vdd_npu_s0: regulator@42 { -- compatible = "rockchip,rk8602"; -- reg = <0x42>; -- rockchip,suspend-voltage-selector = <1>; -- regulator-name = "vdd_npu_s0"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-ramp-delay = <2300>; -- vin-supply = <&vcc4v0_sys>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; --}; -- --&i2c6 { -- clock-frequency = <200000>; -- status = "okay"; -- -- fusb302: typec-portc@22 { -- compatible = "fcs,fusb302"; -- reg = <0x22>; -- interrupt-parent = <&gpio0>; -- interrupts = ; -- pinctrl-0 = <&usbc0_int>; -- pinctrl-names = "default"; -- vbus-supply = <&vbus5v0_typec>; -- -- connector { -- compatible = "usb-c-connector"; -- data-role = "dual"; -- label = "USB-C"; -- power-role = "dual"; -- try-power-role = "sink"; -- source-pdos = ; -- sink-pdos = ; -- op-sink-microwatt = <1000000>; -- }; -- }; -- -- hym8563: rtc@51 { -- compatible = "haoyu,hym8563"; -- reg = <0x51>; -- #clock-cells = <0>; -- clock-output-names = "hym8563"; -- pinctrl-names = "default"; -- pinctrl-0 = <&hym8563_int>; -- interrupt-parent = <&gpio0>; -- interrupts = ; -- wakeup-source; -- }; --}; -- --&i2c7 { -- clock-frequency = <200000>; -- status = "okay"; -- -- rt5616: codec@1b { -- compatible = "realtek,rt5616"; -- reg = <0x1b>; -- clocks = <&cru I2S0_8CH_MCLKOUT>; -- clock-names = "mclk"; -- #sound-dai-cells = <0>; -- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; -- assigned-clock-rates = <12288000>; -- -- port { -- rt5616_p0_0: endpoint { -- remote-endpoint = <&i2s0_8ch_p0_0>; -- }; -- }; -- }; -- -- /* connected with MIPI-CSI1 */ --}; -- --&i2c8 { -- pinctrl-0 = <&i2c8m2_xfer>; --}; -- --&i2s0_8ch { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2s0_lrck -- &i2s0_mclk -- &i2s0_sclk -- &i2s0_sdi0 -- &i2s0_sdo0>; -- status = "okay"; -- -- i2s0_8ch_p0: port { -- i2s0_8ch_p0_0: endpoint { -- dai-format = "i2s"; -- mclk-fs = <256>; -- remote-endpoint = <&rt5616_p0_0>; -- }; -- }; --}; -- --&pcie2x1l0 { -- reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc_3v3_pcie20>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_0_rst>; -- status = "okay"; --}; -- --&pcie2x1l1 { -- reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_1_rst>; -- status = "okay"; --}; -- --&pcie2x1l2 { -- reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc_3v3_pcie20>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_2_rst>; -- status = "okay"; --}; -- --&pcie30phy { -- status = "okay"; --}; -- --&pcie3x4 { -- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc3v3_pcie30>; -- status = "okay"; --}; -- --&pinctrl { -- gpio-leds { -- sys_led_pin: sys-led-pin { -- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- usr_led_pin: usr-led-pin { -- rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- headphone { -- hp_det: hp-det { -- rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- hym8563 { -- hym8563_int: hym8563-int { -- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; -- }; -- }; -- -- pcie { -- pcie2_0_rst: pcie2-0-rst { -- rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie2_1_rst: pcie2-1-rst { -- rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie2_2_rst: pcie2-2-rst { -- rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie_m2_0_pwren: pcie-m20-pwren { -- rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie_m2_1_pwren: pcie-m21-pwren { -- rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- usb { -- pin_4g_lte_pwren: 4g-lte-pwren { -- rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- typec5v_pwren: typec5v-pwren { -- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- usbc0_int: usbc0-int { -- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -- }; -- }; --}; -- --&pwm1 { -- pinctrl-0 = <&pwm1m1_pins>; -- status = "okay"; --}; -- --&saradc { -- vref-supply = <&avcc_1v8_s0>; -- status = "okay"; --}; -- --&sdhci { -- bus-width = <8>; -- no-sdio; -- no-sd; -- non-removable; -- max-frequency = <200000000>; -- mmc-hs400-1_8v; -- mmc-hs400-enhanced-strobe; -- status = "okay"; --}; -- --&sdmmc { -- bus-width = <4>; -- cap-mmc-highspeed; -- cap-sd-highspeed; -- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -- disable-wp; -- no-mmc; -- no-sdio; -- sd-uhs-sdr104; -- vmmc-supply = <&vcc3v3_sd_s0>; -- vqmmc-supply = <&vccio_sd_s0>; -- status = "okay"; --}; -- --&spi2 { -- status = "okay"; -- assigned-clocks = <&cru CLK_SPI2>; -- assigned-clock-rates = <200000000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -- num-cs = <1>; -- -- pmic@0 { -- compatible = "rockchip,rk806"; -- spi-max-frequency = <1000000>; -- reg = <0x0>; -- -- interrupt-parent = <&gpio0>; -- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -- -- pinctrl-names = "default"; -- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -- <&rk806_dvs2_null>, <&rk806_dvs3_null>; -- -- system-power-controller; -- -- vcc1-supply = <&vcc4v0_sys>; -- vcc2-supply = <&vcc4v0_sys>; -- vcc3-supply = <&vcc4v0_sys>; -- vcc4-supply = <&vcc4v0_sys>; -- vcc5-supply = <&vcc4v0_sys>; -- vcc6-supply = <&vcc4v0_sys>; -- vcc7-supply = <&vcc4v0_sys>; -- vcc8-supply = <&vcc4v0_sys>; -- vcc9-supply = <&vcc4v0_sys>; -- vcc10-supply = <&vcc4v0_sys>; -- vcc11-supply = <&vcc_2v0_pldo_s3>; -- vcc12-supply = <&vcc4v0_sys>; -- vcc13-supply = <&vcc_1v1_nldo_s3>; -- vcc14-supply = <&vcc_1v1_nldo_s3>; -- vcca-supply = <&vcc4v0_sys>; -- -- gpio-controller; -- #gpio-cells = <2>; -- -- rk806_dvs1_null: dvs1-null-pins { -- pins = "gpio_pwrctrl1"; -- function = "pin_fun0"; -- }; -- -- rk806_dvs2_null: dvs2-null-pins { -- pins = "gpio_pwrctrl2"; -- function = "pin_fun0"; -- }; -- -- rk806_dvs3_null: dvs3-null-pins { -- pins = "gpio_pwrctrl3"; -- function = "pin_fun0"; -- }; -- -- regulators { -- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_gpu_s0"; -- regulator-enable-ramp-delay = <400>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_cpu_lit_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_log_s0: dcdc-reg3 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <675000>; -- regulator-max-microvolt = <750000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_log_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <750000>; -- }; -- }; -- -- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-init-microvolt = <750000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_vdenc_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_ddr_s0: dcdc-reg5 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <675000>; -- regulator-max-microvolt = <900000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_ddr_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <850000>; -- }; -- }; -- -- vdd2_ddr_s3: dcdc-reg6 { -- regulator-always-on; -- regulator-boot-on; -- regulator-name = "vdd2_ddr_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- }; -- }; -- -- vcc_2v0_pldo_s3: dcdc-reg7 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <2000000>; -- regulator-max-microvolt = <2000000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_2v0_pldo_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <2000000>; -- }; -- }; -- -- vcc_3v3_s3: dcdc-reg8 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-name = "vcc_3v3_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <3300000>; -- }; -- }; -- -- vddq_ddr_s0: dcdc-reg9 { -- regulator-always-on; -- regulator-boot-on; -- regulator-name = "vddq_ddr_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_1v8_s3: dcdc-reg10 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "vcc_1v8_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- avcc_1v8_s0: pldo-reg1 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "avcc_1v8_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_1v8_s0: pldo-reg2 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "vcc_1v8_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- avdd_1v2_s0: pldo-reg3 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1200000>; -- regulator-max-microvolt = <1200000>; -- regulator-name = "avdd_1v2_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_3v3_s0: pldo-reg4 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vcc_3v3_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vccio_sd_s0: pldo-reg5 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <3300000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vccio_sd_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- pldo6_s3: pldo-reg6 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "pldo6_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- vdd_0v75_s3: nldo-reg1 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <750000>; -- regulator-max-microvolt = <750000>; -- regulator-name = "vdd_0v75_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <750000>; -- }; -- }; -- -- vdd_ddr_pll_s0: nldo-reg2 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <850000>; -- regulator-max-microvolt = <850000>; -- regulator-name = "vdd_ddr_pll_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <850000>; -- }; -- }; -- -- avdd_0v75_s0: nldo-reg3 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <750000>; -- regulator-max-microvolt = <750000>; -- regulator-name = "avdd_0v75_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_0v85_s0: nldo-reg4 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <850000>; -- regulator-max-microvolt = <850000>; -- regulator-name = "vdd_0v85_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_0v75_s0: nldo-reg5 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <750000>; -- regulator-max-microvolt = <750000>; -- regulator-name = "vdd_0v75_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- }; -- }; --}; -- --&tsadc { -- status = "okay"; --}; -- --&uart2 { -- pinctrl-0 = <&uart2m0_xfer>; -- status = "okay"; --}; -- --&u2phy2_host { -- phy-supply = <&vdd_4g_3v3>; -- status = "okay"; --}; -- --&u2phy3_host { -- status = "okay"; --}; -- --&u2phy2 { -- status = "okay"; --}; -- --&u2phy3 { -- status = "okay"; --}; -- --&usb_host0_ehci { -- status = "okay"; --}; -- --&usb_host0_ohci { -- status = "okay"; --}; -- --&usb_host1_ehci { -- status = "okay"; --}; -- --&usb_host1_ohci { -- status = "okay"; - }; ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -0,0 +1,945 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ * Copyright (c) 2023 Thomas McKahan -+ * -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include "rk3588.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPC-T6"; -+ compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; -+ -+ aliases { -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ sys_led: led-0 { -+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ label = "system-led"; -+ linux,default-trigger = "heartbeat"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sys_led_pin>; -+ }; -+ -+ usr_led: led-1 { -+ gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; -+ label = "user-led"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usr_led_pin>; -+ }; -+ }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_det>; -+ -+ simple-audio-card,name = "realtek,rt5616-codec"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ -+ simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; -+ simple-audio-card,hp-pin-name = "Headphones"; -+ -+ simple-audio-card,widgets = -+ "Headphone", "Headphones", -+ "Microphone", "Microphone Jack"; -+ simple-audio-card,routing = -+ "Headphones", "HPOL", -+ "Headphones", "HPOR", -+ "MIC1", "Microphone Jack", -+ "Microphone Jack", "micbias1"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s0_8ch>; -+ }; -+ simple-audio-card,codec { -+ sound-dai = <&rt5616>; -+ }; -+ }; -+ -+ vcc12v_dcin: vcc12v-dcin-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ /* vcc5v0_sys powers peripherals */ -+ vcc5v0_sys: vcc5v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ /* vcc4v0_sys powers the RK806, RK860's */ -+ vcc4v0_sys: vcc4v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc4v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-1v1-nldo-s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ vin-supply = <&vcc4v0_sys>; -+ }; -+ -+ vcc_3v3_pcie20: vcc3v3-pcie20-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_3v3_pcie20"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vbus5v0_typec: vbus5v0-typec-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&typec5v_pwren>; -+ regulator-name = "vbus5v0_typec"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_m2_1_pwren>; -+ regulator-name = "vcc3v3_pcie2x1l0"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_pcie30: vcc3v3-pcie30-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_m2_0_pwren>; -+ regulator-name = "vcc3v3_pcie30"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_sd_s0: vcc3v3-sd-s0-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-low; -+ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; -+ regulator-boot-on; -+ regulator-max-microvolt = <3300000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-name = "vcc3v3_sd_s0"; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vdd_4g_3v3: vdd-4g-3v3-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pin_4g_lte_pwren>; -+ regulator-name = "vdd_4g_3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&combphy0_ps { -+ status = "okay"; -+}; -+ -+&combphy1_ps { -+ status = "okay"; -+}; -+ -+&combphy2_psu { -+ status = "okay"; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b2 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_b3 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&gpio0 { -+ gpio-line-names = /* GPIO0 A0-A7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO0 B0-B7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO0 C0-C7 */ -+ "", "", "", "", -+ "HEADER_10", "HEADER_08", "HEADER_32", "", -+ /* GPIO0 D0-D7 */ -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio1 { -+ gpio-line-names = /* GPIO1 A0-A7 */ -+ "HEADER_27", "HEADER_28", "", "", -+ "", "", "", "HEADER_15", -+ /* GPIO1 B0-B7 */ -+ "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23", -+ "HEADER_24", "HEADER_22", "", "", -+ /* GPIO1 C0-C7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO1 D0-D7 */ -+ "", "", "", "", -+ "", "", "HEADER_05", "HEADER_03"; -+}; -+ -+&gpio2 { -+ gpio-line-names = /* GPIO2 A0-A7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO2 B0-B7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO2 C0-C7 */ -+ "", "CSI1_11", "CSI1_12", "", -+ "", "", "", "", -+ /* GPIO2 D0-D7 */ -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio3 { -+ gpio-line-names = /* GPIO3 A0-A7 */ -+ "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36", -+ "HEADER_37", "", "DSI0_12", "", -+ /* GPIO3 B0-B7 */ -+ "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16", -+ "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12", -+ /* GPIO3 C0-C7 */ -+ "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13", -+ "", "", "", "", -+ /* GPIO3 D0-D7 */ -+ "", "", "", "", -+ "", "DSI1_10", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = /* GPIO4 A0-A7 */ -+ "DSI1_08", "DSI1_14", "", "DSI1_12", -+ "", "", "", "", -+ /* GPIO4 B0-B7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO4 C0-C7 */ -+ "", "", "", "", -+ "CSI0_11", "CSI0_12", "", "", -+ /* GPIO4 D0-D7 */ -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0m2_xfer>; -+ status = "okay"; -+ -+ vdd_cpu_big0_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big0_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc4v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big1_s0: regulator@43 { -+ compatible = "rockchip,rk8603", "rockchip,rk8602"; -+ reg = <0x43>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big1_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc4v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ status = "okay"; -+ -+ vdd_npu_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ rockchip,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_npu_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc4v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c6 { -+ clock-frequency = <200000>; -+ status = "okay"; -+ -+ fusb302: typec-portc@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-0 = <&usbc0_int>; -+ pinctrl-names = "default"; -+ vbus-supply = <&vbus5v0_typec>; -+ -+ connector { -+ compatible = "usb-c-connector"; -+ data-role = "dual"; -+ label = "USB-C"; -+ power-role = "dual"; -+ try-power-role = "sink"; -+ source-pdos = ; -+ sink-pdos = ; -+ op-sink-microwatt = <1000000>; -+ }; -+ }; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ clock-output-names = "hym8563"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ wakeup-source; -+ }; -+}; -+ -+&i2c7 { -+ clock-frequency = <200000>; -+ status = "okay"; -+ -+ rt5616: codec@1b { -+ compatible = "realtek,rt5616"; -+ reg = <0x1b>; -+ clocks = <&cru I2S0_8CH_MCLKOUT>; -+ clock-names = "mclk"; -+ #sound-dai-cells = <0>; -+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; -+ assigned-clock-rates = <12288000>; -+ -+ port { -+ rt5616_p0_0: endpoint { -+ remote-endpoint = <&i2s0_8ch_p0_0>; -+ }; -+ }; -+ }; -+ -+ /* connected with MIPI-CSI1 */ -+}; -+ -+&i2c8 { -+ pinctrl-0 = <&i2c8m2_xfer>; -+}; -+ -+&i2s0_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s0_lrck -+ &i2s0_mclk -+ &i2s0_sclk -+ &i2s0_sdi0 -+ &i2s0_sdo0>; -+ status = "okay"; -+ -+ i2s0_8ch_p0: port { -+ i2s0_8ch_p0_0: endpoint { -+ dai-format = "i2s"; -+ mclk-fs = <256>; -+ remote-endpoint = <&rt5616_p0_0>; -+ }; -+ }; -+}; -+ -+&pcie2x1l0 { -+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc_3v3_pcie20>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_rst>; -+ status = "okay"; -+}; -+ -+&pcie2x1l1 { -+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_1_rst>; -+ status = "okay"; -+}; -+ -+&pcie2x1l2 { -+ reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc_3v3_pcie20>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_2_rst>; -+ status = "okay"; -+}; -+ -+&pcie30phy { -+ status = "okay"; -+}; -+ -+&pcie3x4 { -+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gpio-leds { -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ usr_led_pin: usr-led-pin { -+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ headphone { -+ hp_det: hp-det { -+ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ pcie { -+ pcie2_0_rst: pcie2-0-rst { -+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie2_1_rst: pcie2-1-rst { -+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie2_2_rst: pcie2-2-rst { -+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_m2_0_pwren: pcie-m20-pwren { -+ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_m2_1_pwren: pcie-m21-pwren { -+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb { -+ pin_4g_lte_pwren: 4g-lte-pwren { -+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ typec5v_pwren: typec5v-pwren { -+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ usbc0_int: usbc0-int { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pwm1 { -+ pinctrl-0 = <&pwm1m1_pins>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&avcc_1v8_s0>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ no-sdio; -+ no-sd; -+ non-removable; -+ max-frequency = <200000000>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ no-mmc; -+ no-sdio; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v3_sd_s0>; -+ vqmmc-supply = <&vccio_sd_s0>; -+ status = "okay"; -+}; -+ -+&spi2 { -+ status = "okay"; -+ assigned-clocks = <&cru CLK_SPI2>; -+ assigned-clock-rates = <200000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -+ num-cs = <1>; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ spi-max-frequency = <1000000>; -+ reg = <0x0>; -+ -+ interrupt-parent = <&gpio0>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -+ <&rk806_dvs2_null>, <&rk806_dvs3_null>; -+ -+ system-power-controller; -+ -+ vcc1-supply = <&vcc4v0_sys>; -+ vcc2-supply = <&vcc4v0_sys>; -+ vcc3-supply = <&vcc4v0_sys>; -+ vcc4-supply = <&vcc4v0_sys>; -+ vcc5-supply = <&vcc4v0_sys>; -+ vcc6-supply = <&vcc4v0_sys>; -+ vcc7-supply = <&vcc4v0_sys>; -+ vcc8-supply = <&vcc4v0_sys>; -+ vcc9-supply = <&vcc4v0_sys>; -+ vcc10-supply = <&vcc4v0_sys>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc4v0_sys>; -+ vcc13-supply = <&vcc_1v1_nldo_s3>; -+ vcc14-supply = <&vcc_1v1_nldo_s3>; -+ vcca-supply = <&vcc4v0_sys>; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ rk806_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl1"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ regulators { -+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_gpu_s0"; -+ regulator-enable-ramp-delay = <400>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_lit_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_log_s0: dcdc-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_log_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-init-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_vdenc_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_s0: dcdc-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <900000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_ddr_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vdd2_ddr_s3: dcdc-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vdd2_ddr_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2000000>; -+ regulator-max-microvolt = <2000000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_2v0_pldo_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vcc_3v3_s3: dcdc-reg8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vddq_ddr_s0: dcdc-reg9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vddq_ddr_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s3: dcdc-reg10 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avcc_1v8_s0: pldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "avcc_1v8_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s0: pldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avdd_1v2_s0: pldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-name = "avdd_1v2_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3_s0: pldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vccio_sd_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ pldo6_s3: pldo-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "pldo6_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_ddr_pll_s0: nldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_ddr_pll_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ avdd_0v75_s0: nldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "avdd_0v75_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v85_s0: nldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_0v85_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v75_s0: nldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m0_xfer>; -+ status = "okay"; -+}; -+ -+&u2phy2_host { -+ phy-supply = <&vdd_4g_3v3>; -+ status = "okay"; -+}; -+ -+&u2phy3_host { -+ status = "okay"; -+}; -+ -+&u2phy2 { -+ status = "okay"; -+}; -+ -+&u2phy3 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.6/053-09-v6.12-arm64-dts-rockchip-move-NanoPC-T6-parts-to-DTS.patch b/target/linux/rockchip/patches-6.6/053-09-v6.12-arm64-dts-rockchip-move-NanoPC-T6-parts-to-DTS.patch deleted file mode 100644 index ce78982a58..0000000000 --- a/target/linux/rockchip/patches-6.6/053-09-v6.12-arm64-dts-rockchip-move-NanoPC-T6-parts-to-DTS.patch +++ /dev/null @@ -1,85 +0,0 @@ -From aea8d84070fe0846961deb23228d9dd3f8caefb3 Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:54 +0200 -Subject: [PATCH] arm64: dts: rockchip: move NanoPC-T6 parts to DTS - -MiniPCIe slot is present only in first version of NanoPC-T6 (2301). - -Signed-off-by: Marcin Juszkiewicz -Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-3-edff247e8c02@linaro.org -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588-nanopc-t6.dts | 23 +++++++++++++++++++ - .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 17 -------------- - 2 files changed, 23 insertions(+), 17 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -14,4 +14,27 @@ - model = "FriendlyElec NanoPC-T6"; - compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; - -+ vdd_4g_3v3: vdd-4g-3v3-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pin_4g_lte_pwren>; -+ regulator-name = "vdd_4g_3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&pinctrl { -+ usb { -+ pin_4g_lte_pwren: 4g-lte-pwren { -+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&u2phy2_host { -+ phy-supply = <&vdd_4g_3v3>; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -170,18 +170,6 @@ - regulator-name = "vcc3v3_sd_s0"; - vin-supply = <&vcc_3v3_s3>; - }; -- -- vdd_4g_3v3: vdd-4g-3v3-regulator { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pin_4g_lte_pwren>; -- regulator-name = "vdd_4g_3v3"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc5v0_sys>; -- }; - }; - - &combphy0_ps { -@@ -527,10 +515,6 @@ - }; - - usb { -- pin_4g_lte_pwren: 4g-lte-pwren { -- rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- - typec5v_pwren: typec5v-pwren { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; -@@ -912,7 +896,6 @@ - }; - - &u2phy2_host { -- phy-supply = <&vdd_4g_3v3>; - status = "okay"; - }; - diff --git a/target/linux/rockchip/patches-6.6/053-10-v6.12-arm64-dts-rockchip-add-SPI-flash-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/053-10-v6.12-arm64-dts-rockchip-add-SPI-flash-on-NanoPC-T6.patch deleted file mode 100644 index 61fa3639a9..0000000000 --- a/target/linux/rockchip/patches-6.6/053-10-v6.12-arm64-dts-rockchip-add-SPI-flash-on-NanoPC-T6.patch +++ /dev/null @@ -1,40 +0,0 @@ -From a22a629c63b1addcf2d81eaf30383c1deca5b7a9 Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:56 +0200 -Subject: [PATCH] arm64: dts: rockchip: add SPI flash on NanoPC-T6 - -FriendlyELEC NanoPC-T6 has optional SPI flash chip on-board. -It is populated with 32MB one on LTS version. - -Signed-off-by: Marcin Juszkiewicz -Reviewed-by: Jonas Karlman -Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-5-edff247e8c02@linaro.org -Signed-off-by: Heiko Stuebner ---- - .../arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -560,6 +560,21 @@ - status = "okay"; - }; - -+/* optional on non-LTS, populated on LTS version */ -+&sfc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fspim1_pins>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <104000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ - &spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; diff --git a/target/linux/rockchip/patches-6.6/053-11-v6.12-arm64-dts-rockchip-add-IR-receiver-to-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/053-11-v6.12-arm64-dts-rockchip-add-IR-receiver-to-NanoPC-T6.patch deleted file mode 100644 index 34b2d182b4..0000000000 --- a/target/linux/rockchip/patches-6.6/053-11-v6.12-arm64-dts-rockchip-add-IR-receiver-to-NanoPC-T6.patch +++ /dev/null @@ -1,53 +0,0 @@ -From b70caff0f9592719b6c977e291c33192e959c9d4 Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:57 +0200 -Subject: [PATCH] arm64: dts: rockchip: add IR-receiver to NanoPC-T6 - -FriendlyELEC NanoPC-T6 has IR receiver connected to PWM3_IR_M0 line -which ends as GPIO0_D4. - -Signed-off-by: Marcin Juszkiewicz -Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-6-edff247e8c02@linaro.org -Signed-off-by: Heiko Stuebner ---- - .../arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 ++++++++++++++- - 1 file changed, 14 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -25,6 +25,13 @@ - stdout-path = "serial2:1500000n8"; - }; - -+ ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ir_receiver_pin>; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -228,7 +235,7 @@ - "HEADER_10", "HEADER_08", "HEADER_32", "", - /* GPIO0 D0-D7 */ - "", "", "", "", -- "", "", "", ""; -+ "IR receiver [PWM3_IR_M0]", "", "", ""; - }; - - &gpio1 { -@@ -492,6 +499,12 @@ - }; - }; - -+ ir-receiver { -+ ir_receiver_pin: ir-receiver-pin { -+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pcie { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.6/053-12-v6.12-arm64-dts-rockchip-enable-GPU-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/053-12-v6.12-arm64-dts-rockchip-enable-GPU-on-NanoPC-T6.patch deleted file mode 100644 index 40ebd638c1..0000000000 --- a/target/linux/rockchip/patches-6.6/053-12-v6.12-arm64-dts-rockchip-enable-GPU-on-NanoPC-T6.patch +++ /dev/null @@ -1,28 +0,0 @@ -From e86cbf999cda2d44f32ec622537024e3b923080d Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:58 +0200 -Subject: [PATCH] arm64: dts: rockchip: enable GPU on NanoPC-T6 - -Enable the Mali GPU on FriendlyELEC NanoPC-T6 - -Signed-off-by: Marcin Juszkiewicz -Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-7-edff247e8c02@linaro.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -298,6 +298,11 @@ - "", "", "", ""; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu_s0>; -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; diff --git a/target/linux/rockchip/patches-6.6/053-13-v6.12-arm64-dts-rockchip-enable-USB-C-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/053-13-v6.12-arm64-dts-rockchip-enable-USB-C-on-NanoPC-T6.patch deleted file mode 100644 index 89720c3825..0000000000 --- a/target/linux/rockchip/patches-6.6/053-13-v6.12-arm64-dts-rockchip-enable-USB-C-on-NanoPC-T6.patch +++ /dev/null @@ -1,130 +0,0 @@ -From c9ba75320e5a12dc9d574603acf29b38a920b40c Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:59 +0200 -Subject: [PATCH] arm64: dts: rockchip: enable USB-C on NanoPC-T6 - -Enable the USB-C port on FriendlyELEC NanoPC-T6. - -Works one way so far but still better than before. - -Signed-off-by: Marcin Juszkiewicz -Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-8-edff247e8c02@linaro.org -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 76 ++++++++++++++++++- - 1 file changed, 72 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -137,6 +137,8 @@ - gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; -+ regulator-always-on; -+ regulator-boot-on; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -@@ -381,11 +383,34 @@ - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; -- power-role = "dual"; -- try-power-role = "sink"; -+ power-role = "source"; - source-pdos = ; -- sink-pdos = ; -- op-sink-microwatt = <1000000>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usbc0_hs: endpoint { -+ remote-endpoint = <&usb_host0_xhci_drd_sw>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ usbc0_ss: endpoint { -+ remote-endpoint = <&usbdp_phy0_typec_ss>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ usbc0_sbu: endpoint { -+ remote-endpoint = <&usbdp_phy0_typec_sbu>; -+ }; -+ }; -+ }; - }; - }; - -@@ -928,6 +953,14 @@ - status = "okay"; - }; - -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ - &u2phy2_host { - status = "okay"; - }; -@@ -944,6 +977,29 @@ - status = "okay"; - }; - -+&usbdp_phy0 { -+ mode-switch; -+ orientation-switch; -+ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; -+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ usbdp_phy0_typec_ss: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&usbc0_ss>; -+ }; -+ -+ usbdp_phy0_typec_sbu: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&usbc0_sbu>; -+ }; -+ }; -+}; -+ - &usb_host0_ehci { - status = "okay"; - }; -@@ -952,6 +1008,18 @@ - status = "okay"; - }; - -+&usb_host0_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+ usb-role-switch; -+ -+ port { -+ usb_host0_xhci_drd_sw: endpoint { -+ remote-endpoint = <&usbc0_hs>; -+ }; -+ }; -+}; -+ - &usb_host1_ehci { - status = "okay"; - }; diff --git a/target/linux/rockchip/patches-6.6/053-14-v6.12-arm64-dts-rockchip-add-Mask-Rom-key-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/053-14-v6.12-arm64-dts-rockchip-add-Mask-Rom-key-on-NanoPC-T6.patch deleted file mode 100644 index cf179d9fa9..0000000000 --- a/target/linux/rockchip/patches-6.6/053-14-v6.12-arm64-dts-rockchip-add-Mask-Rom-key-on-NanoPC-T6.patch +++ /dev/null @@ -1,45 +0,0 @@ -From da439eed06ff6806f22341ab0468226afc555305 Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:27:00 +0200 -Subject: [PATCH] arm64: dts: rockchip: add Mask Rom key on NanoPC-T6 - -Mask Rom key is connected to SARADC and can be read from OS. - -Signed-off-by: Marcin Juszkiewicz -Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-9-edff247e8c02@linaro.org -Signed-off-by: Heiko Stuebner ---- - .../arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -8,6 +8,7 @@ - /dts-v1/; - - #include -+#include - #include - #include - #include "rk3588.dtsi" -@@ -21,6 +22,20 @@ - mmc1 = &sdmmc; - }; - -+ adc-keys-0 { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 0>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1800000>; -+ poll-interval = <100>; -+ -+ button-maskrom { -+ label = "Mask Rom"; -+ linux,code = ; -+ press-threshold-microvolt = <2000>; -+ }; -+ }; -+ - chosen { - stdout-path = "serial2:1500000n8"; - }; diff --git a/target/linux/rockchip/patches-6.6/053-15-v6.12-arm64-dts-rockchip-use-correct-fcs-suspend-voltage-selecto.patch b/target/linux/rockchip/patches-6.6/053-15-v6.12-arm64-dts-rockchip-use-correct-fcs-suspend-voltage-selecto.patch deleted file mode 100644 index d7d87e22e8..0000000000 --- a/target/linux/rockchip/patches-6.6/053-15-v6.12-arm64-dts-rockchip-use-correct-fcs-suspend-voltage-selecto.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 170c77276d470a63d22a2634a38846dd88538637 Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Thu, 29 Aug 2024 15:20:58 +0200 -Subject: [PATCH] arm64: dts: rockchip: use correct - fcs,suspend-voltage-selector on NanoPC-T6 - -A remant from moving from the vendor kernel, the regulator is using -a fairchild fcs prefix instead of rockchip,* in the mainline kernel -according to its binding. - -Signed-off-by: Heiko Stuebner -Link: https://lore.kernel.org/r/20240829132100.1723127-2-heiko@sntech.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -366,7 +366,7 @@ - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; -- rockchip,suspend-voltage-selector = <1>; -+ fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; diff --git a/target/linux/rockchip/patches-6.6/053-16-v6.13-arm64-dts-rockchip-enable-USB3-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/053-16-v6.13-arm64-dts-rockchip-enable-USB3-on-NanoPC-T6.patch deleted file mode 100644 index d3aa8b9cc3..0000000000 --- a/target/linux/rockchip/patches-6.6/053-16-v6.13-arm64-dts-rockchip-enable-USB3-on-NanoPC-T6.patch +++ /dev/null @@ -1,87 +0,0 @@ -From a6ae420439dc47a58550a6e61e596e9dd1562caf Mon Sep 17 00:00:00 2001 -From: Rick Wertenbroek -Date: Wed, 6 Nov 2024 14:03:13 +0100 -Subject: [PATCH] arm64: dts: rockchip: enable USB3 on NanoPC-T6 - -Enable the USB3 port on FriendlyELEC NanoPC-T6. - -Signed-off-by: Rick Wertenbroek -Link: https://lore.kernel.org/r/20241106130314.1289055-1-rick.wertenbroek@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 36 +++++++++++++++++++ - 1 file changed, 36 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -160,6 +160,20 @@ - vin-supply = <&vcc5v0_sys>; - }; - -+ vbus5v0_usb: vbus5v0-usb-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb5v_pwren>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vbus5v0_usb"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ - vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { - compatible = "regulator-fixed"; - enable-active-high; -@@ -577,6 +591,10 @@ - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - -+ usb5v_pwren: usb5v_pwren { -+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; -@@ -976,6 +994,14 @@ - status = "okay"; - }; - -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ - &u2phy2_host { - status = "okay"; - }; -@@ -1015,6 +1041,11 @@ - }; - }; - -+&usbdp_phy1 { -+ phy-supply = <&vbus5v0_usb>; -+ status = "okay"; -+}; -+ - &usb_host0_ehci { - status = "okay"; - }; -@@ -1035,6 +1066,11 @@ - }; - }; - -+&usb_host1_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ - &usb_host1_ehci { - status = "okay"; - }; diff --git a/target/linux/rockchip/patches-6.6/054-01-v6.7-arm64-dts-rockchip-Add-Orange-Pi-5.patch b/target/linux/rockchip/patches-6.6/054-01-v6.7-arm64-dts-rockchip-Add-Orange-Pi-5.patch deleted file mode 100644 index 0ae6dabb8e..0000000000 --- a/target/linux/rockchip/patches-6.6/054-01-v6.7-arm64-dts-rockchip-Add-Orange-Pi-5.patch +++ /dev/null @@ -1,693 +0,0 @@ -From b6bc755d806eac3fbddb7ea278fc7d2eb57dba4a Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Mon, 9 Oct 2023 22:27:27 +0300 -Subject: [PATCH] arm64: dts: rockchip: Add Orange Pi 5 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add initial support for OPi5 that includes support for USB2, PCIe2, Sata, -Sdmmc, SPI Flash, PMIC. - -Signed-off-by: Muhammed Efe Cetin -Reviewed-by: Ondřej Jirman -Link: https://lore.kernel.org/r/4212da199c9c532b60d380bf1dfa83490e16bc13.1696878787.git.efectn@6tel.net -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 662 ++++++++++++++++++ - 2 files changed, 663 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -111,3 +111,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts -@@ -0,0 +1,662 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include -+#include "rk3588s.dtsi" -+ -+/ { -+ model = "Xunlong Orange Pi 5"; -+ compatible = "xunlong,orangepi-5", "rockchip,rk3588s"; -+ -+ aliases { -+ mmc0 = &sdmmc; -+ serial2 = &uart2; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ adc-keys { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 1>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1800000>; -+ poll-interval = <100>; -+ -+ button-recovery { -+ label = "Recovery"; -+ linux,code = ; -+ press-threshold-microvolt = <1800>; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 =<&leds_gpio>; -+ -+ led-1 { -+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; -+ label = "status_led"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ vbus_typec: vbus-typec-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&typec5v_pwren>; -+ regulator-name = "vbus_typec"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-low; -+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; -+ regulator-name = "vcc_3v3_sd_s0"; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vcc3v3_pcie20: vcc3v3-pcie20-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc3v3_pcie20"; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&combphy0_ps { -+ status = "okay"; -+}; -+ -+&combphy2_psu { -+ status = "okay"; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b2 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_b3 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&gmac1 { -+ clock_in_out = "output"; -+ phy-handle = <&rgmii_phy1>; -+ phy-mode = "rgmii-rxid"; -+ pinctrl-0 = <&gmac1_miim -+ &gmac1_tx_bus2 -+ &gmac1_rx_bus2 -+ &gmac1_rgmii_clk -+ &gmac1_rgmii_bus>; -+ pinctrl-names = "default"; -+ tx_delay = <0x42>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0m2_xfer>; -+ status = "okay"; -+ -+ vdd_cpu_big0_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big0_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big1_s0: regulator@43 { -+ compatible = "rockchip,rk8603", "rockchip,rk8602"; -+ reg = <0x43>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big1_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ status = "okay"; -+ -+ vdd_npu_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_npu_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c6 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c6m3_xfer>; -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ clock-output-names = "hym8563"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ wakeup-source; -+ }; -+}; -+ -+&mdio1 { -+ rgmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0x1>; -+ reset-assert-us = <20000>; -+ reset-deassert-us = <100000>; -+ reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&pcie2x1l2 { -+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie20>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gpio-func { -+ leds_gpio: leds-gpio { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb-typec { -+ usbc0_int: usbc0-int { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ typec5v_pwren: typec5v-pwren { -+ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&saradc { -+ vref-supply = <&avcc_1v8_s0>; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ max-frequency = <150000000>; -+ no-mmc; -+ no-sdio; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3_sd_s0>; -+ vqmmc-supply = <&vccio_sd_s0>; -+ status = "okay"; -+}; -+ -+&sfc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fspim0_pins>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0x0>; -+ spi-max-frequency = <100000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ -+&spi2 { -+ status = "okay"; -+ assigned-clocks = <&cru CLK_SPI2>; -+ assigned-clock-rates = <200000000>; -+ num-cs = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ reg = <0x0>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -+ <&rk806_dvs2_null>, <&rk806_dvs3_null>; -+ spi-max-frequency = <1000000>; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc5v0_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc5v0_sys>; -+ vcc13-supply = <&vcc_1v1_nldo_s3>; -+ vcc14-supply = <&vcc_1v1_nldo_s3>; -+ vcca-supply = <&vcc5v0_sys>; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ rk806_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ regulators { -+ vdd_gpu_s0: dcdc-reg1 { -+ regulator-name = "vdd_gpu_s0"; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-enable-ramp-delay = <400>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_s0: dcdc-reg2 { -+ regulator-name = "vdd_cpu_lit_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_log_s0: dcdc-reg3 { -+ regulator-name = "vdd_log_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: dcdc-reg4 { -+ regulator-name = "vdd_vdenc_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_s0: dcdc-reg5 { -+ regulator-name = "vdd_ddr_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <900000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 { -+ regulator-name = "vdd2_ddr_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <1100000>; -+ regulator-min-microvolt = <1100000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-name = "vdd_2v0_pldo_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2000000>; -+ regulator-max-microvolt = <2000000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vcc_3v3_s3: dcdc-reg8 { -+ regulator-name = "vcc_3v3_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vddq_ddr_s0: dcdc-reg9 { -+ regulator-name = "vddq_ddr_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s3: dcdc-reg10 { -+ regulator-name = "vcc_1v8_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avcc_1v8_s0: pldo-reg1 { -+ regulator-name = "avcc_1v8_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s0: pldo-reg2 { -+ regulator-name = "vcc_1v8_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avdd_1v2_s0: pldo-reg3 { -+ regulator-name = "avdd_1v2_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3_s0: pldo-reg4 { -+ regulator-name = "vcc_3v3_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-name = "vccio_sd_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ pldo6_s3: pldo-reg6 { -+ regulator-name = "pldo6_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-name = "vdd_0v75_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_ddr_pll_s0: nldo-reg2 { -+ regulator-name = "vdd_ddr_pll_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ avdd_0v75_s0: nldo-reg3 { -+ regulator-name = "avdd_0v75_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v85_s0: nldo-reg4 { -+ regulator-name = "vdd_0v85_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v75_s0: nldo-reg5 { -+ regulator-name = "vdd_0v75_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&u2phy2 { -+ status = "okay"; -+}; -+ -+&u2phy2_host { -+ status = "okay"; -+}; -+ -+&u2phy3 { -+ status = "okay"; -+}; -+ -+&u2phy3_host { -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m0_xfer>; -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.6/054-02-v6.8-arm64-dts-rockchip-add-USB3-host-on-rk3588s-orangepi-5.patch b/target/linux/rockchip/patches-6.6/054-02-v6.8-arm64-dts-rockchip-add-USB3-host-on-rk3588s-orangepi-5.patch deleted file mode 100644 index a9da2e5ccb..0000000000 --- a/target/linux/rockchip/patches-6.6/054-02-v6.8-arm64-dts-rockchip-add-USB3-host-on-rk3588s-orangepi-5.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 9ecf44fedc17ff267968b5fff589bf6793fc7ddd Mon Sep 17 00:00:00 2001 -From: Jimmy Hon -Date: Sun, 26 Nov 2023 14:08:45 -0600 -Subject: [PATCH] arm64: dts: rockchip: add USB3 host on rk3588s-orangepi-5 - -Enable USB3 host controller for the Orange Pi 5. - -Signed-off-by: Jimmy Hon -Link: https://lore.kernel.org/r/20231126200845.1192-1-honyuenkwun@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts -@@ -660,3 +660,7 @@ - &usb_host1_ohci { - status = "okay"; - }; -+ -+&usb_host2_xhci { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.6/054-03-v6.8-arm64-dts-rockchip-Support-poweroff-on-Orange-Pi-5.patch b/target/linux/rockchip/patches-6.6/054-03-v6.8-arm64-dts-rockchip-Support-poweroff-on-Orange-Pi-5.patch deleted file mode 100644 index 86fe11bafc..0000000000 --- a/target/linux/rockchip/patches-6.6/054-03-v6.8-arm64-dts-rockchip-Support-poweroff-on-Orange-Pi-5.patch +++ /dev/null @@ -1,25 +0,0 @@ -From e9126f9d3c83acbc88461a535e24c949c7e0b6ca Mon Sep 17 00:00:00 2001 -From: Jimmy Hon -Date: Wed, 27 Dec 2023 14:32:11 -0600 -Subject: [PATCH] arm64: dts: rockchip: Support poweroff on Orange Pi 5 - -The RK806 on the Orange Pi 5 can be used to power on/off the whole board. -Mark it as the system power controller. - -Signed-off-by: Jimmy Hon -Link: https://lore.kernel.org/r/20231227203211.1047-1-honyuenkwun@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts -@@ -314,6 +314,7 @@ - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - spi-max-frequency = <1000000>; -+ system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; diff --git a/target/linux/rockchip/patches-6.6/054-04-v6.10-arm64-dts-rockchip-Enable-GPU-on-Orange-Pi-5.patch b/target/linux/rockchip/patches-6.6/054-04-v6.10-arm64-dts-rockchip-Enable-GPU-on-Orange-Pi-5.patch deleted file mode 100644 index 901d12060c..0000000000 --- a/target/linux/rockchip/patches-6.6/054-04-v6.10-arm64-dts-rockchip-Enable-GPU-on-Orange-Pi-5.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 8beafb228f2be5de03e73178ac1081847d0d411f Mon Sep 17 00:00:00 2001 -From: Jimmy Hon -Date: Thu, 25 Apr 2024 17:29:13 -0500 -Subject: [PATCH] arm64: dts: rockchip: Enable GPU on Orange Pi 5 - -Enable the Mali GPU in the Orange Pi 5 - -Signed-off-by: Jimmy Hon -Link: https://lore.kernel.org/r/20240425222913.1760-1-honyuenkwun@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts -@@ -146,6 +146,11 @@ - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu_s0>; -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; diff --git a/target/linux/rockchip/patches-6.6/054-05-v6.10-arm64-dts-rockchip-add-USB-C-support-to-rk3588s-orangepi-.patch b/target/linux/rockchip/patches-6.6/054-05-v6.10-arm64-dts-rockchip-add-USB-C-support-to-rk3588s-orangepi-.patch deleted file mode 100644 index c9ab84c88f..0000000000 --- a/target/linux/rockchip/patches-6.6/054-05-v6.10-arm64-dts-rockchip-add-USB-C-support-to-rk3588s-orangepi-.patch +++ /dev/null @@ -1,146 +0,0 @@ -From c57d1a970275aabfbfab4c56001394ada3456d8e Mon Sep 17 00:00:00 2001 -From: Jimmy Hon -Date: Wed, 17 Apr 2024 22:52:33 -0500 -Subject: [PATCH] arm64: dts: rockchip: add USB-C support to rk3588s-orangepi-5 - -Add support for using the Orange Pi 5 USB-C port for USB in OHCI, EHCI -or XHCI mode. Displayport AltMode is not yet supported. - -Signed-off-by: Jimmy Hon -Link: https://lore.kernel.org/r/20240418035232.35344-2-honyuenkwun@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 94 +++++++++++++++++++ - 1 file changed, 94 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts -@@ -6,6 +6,7 @@ - #include - #include - #include -+#include - #include "rk3588s.dtsi" - - / { -@@ -217,6 +218,56 @@ - pinctrl-0 = <&i2c6m3_xfer>; - status = "okay"; - -+ usbc0: usb-typec@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usbc0_int>; -+ vbus-supply = <&vbus_typec>; -+ status = "okay"; -+ -+ usb_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ data-role = "dual"; -+ op-sink-microwatt = <1000000>; -+ power-role = "dual"; -+ sink-pdos = -+ ; -+ source-pdos = -+ ; -+ try-power-role = "source"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usbc0_hs: endpoint { -+ remote-endpoint = <&usb_host0_xhci_drd_sw>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ usbc0_ss: endpoint { -+ remote-endpoint = <&usbdp_phy0_typec_ss>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ usbc0_sbu: endpoint { -+ remote-endpoint = <&usbdp_phy0_typec_sbu>; -+ }; -+ }; -+ }; -+ }; -+ }; -+ - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; -@@ -630,6 +681,14 @@ - status = "okay"; - }; - -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ - &u2phy2 { - status = "okay"; - }; -@@ -651,6 +710,29 @@ - status = "okay"; - }; - -+&usbdp_phy0 { -+ mode-switch; -+ orientation-switch; -+ sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; -+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ usbdp_phy0_typec_ss: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&usbc0_ss>; -+ }; -+ -+ usbdp_phy0_typec_sbu: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&usbc0_sbu>; -+ }; -+ }; -+}; -+ - &usb_host0_ehci { - status = "okay"; - }; -@@ -659,6 +741,18 @@ - status = "okay"; - }; - -+&usb_host0_xhci { -+ dr_mode = "otg"; -+ usb-role-switch; -+ status = "okay"; -+ -+ port { -+ usb_host0_xhci_drd_sw: endpoint { -+ remote-endpoint = <&usbc0_hs>; -+ }; -+ }; -+}; -+ - &usb_host1_ehci { - status = "okay"; - }; diff --git a/target/linux/rockchip/patches-6.6/055-01-v6.7-arm64-dts-rockchip-Add-board-device-tree-for.patch b/target/linux/rockchip/patches-6.6/055-01-v6.7-arm64-dts-rockchip-Add-board-device-tree-for.patch deleted file mode 100644 index fc2ace83c3..0000000000 --- a/target/linux/rockchip/patches-6.6/055-01-v6.7-arm64-dts-rockchip-Add-board-device-tree-for.patch +++ /dev/null @@ -1,897 +0,0 @@ -From 236d225e1ee72a28aa7c2b1e39894e4390bbf51c Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Sun, 8 Oct 2023 15:05:02 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add board device tree for - rk3588-orangepi-5-plus -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Orange Pi 5 Plus is RK3588 based SBC featuring: - -- 2x 2.5G ethernet ports – onboard NIC hooked to PCIe 2.0 interface -- 2x USB 2.0 host ports -- 2x USB 3.0 host ports (exposed over USB 3.0 hub) -- Type-C port featuring USB 2.0/3.0 and Alt-DP mode -- PCIe 2.0/USB 2.0/I2S/I2C/UART on E.KEY socket -- RTC -- ES8388 on-board sound codec – jack in/out, onboard mic, speaker amplifier -- SPI NOR flash -- RGB LED (R is always on) -- IR receiver -- PCIe 3.0 on the bottom for NVMe, etc. -- 40pin GPIO header (with gpio, I2C, SPI, PWM, UART) -- Power, recovery and Mask ROM buttons -- 2x HDMI out, 1x HDMI in -- Slots/connectors for eMMC, uSD card, fan, MIPI CSI/DSI - -Signed-off-by: Ondrej Jirman -Link: https://lore.kernel.org/r/20231008130515.1155664-5-megi@xff.cz -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../dts/rockchip/rk3588-orangepi-5-plus.dts | 848 ++++++++++++++++++ - 2 files changed, 849 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -107,6 +107,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ed - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -@@ -0,0 +1,848 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2023 Ondřej Jirman -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include -+#include -+#include "rk3588.dtsi" -+ -+/ { -+ model = "Xunlong Orange Pi 5 Plus"; -+ compatible = "xunlong,orangepi-5-plus", "rockchip,rk3588"; -+ -+ aliases { -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc; -+ serial2 = &uart2; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ adc-keys-0 { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 0>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1800000>; -+ poll-interval = <100>; -+ -+ button-maskrom { -+ label = "Mask Rom"; -+ linux,code = ; -+ press-threshold-microvolt = <2000>; -+ }; -+ }; -+ -+ adc-keys-1 { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 1>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1800000>; -+ poll-interval = <100>; -+ -+ button-recovery { -+ label = "Recovery"; -+ linux,code = ; -+ press-threshold-microvolt = <2000>; -+ }; -+ }; -+ -+ speaker_amp: speaker-audio-amplifier { -+ compatible = "simple-audio-amplifier"; -+ enable-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; -+ sound-name-prefix = "Speaker Amp"; -+ }; -+ -+ headphone_amp: headphones-audio-amplifier { -+ compatible = "simple-audio-amplifier"; -+ enable-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; -+ sound-name-prefix = "Headphones Amp"; -+ }; -+ -+ ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ir_receiver_pin>; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&blue_led_pin>; -+ -+ led { -+ color = ; -+ function = LED_FUNCTION_INDICATOR; -+ function-enumerator = <1>; -+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ cooling-levels = <0 70 75 80 100>; -+ fan-supply = <&vcc5v0_sys>; -+ pwms = <&pwm3 0 50000 0>; -+ #cooling-cells = <2>; -+ }; -+ -+ pwm-leds { -+ compatible = "pwm-leds"; -+ -+ led { -+ color = ; -+ function = LED_FUNCTION_INDICATOR; -+ function-enumerator = <2>; -+ max-brightness = <255>; -+ pwms = <&pwm2 0 25000 0>; -+ }; -+ }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_detect>; -+ simple-audio-card,name = "Analog"; -+ simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ simple-audio-card,hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; -+ simple-audio-card,bitclock-master = <&daicpu>; -+ simple-audio-card,frame-master = <&daicpu>; -+ /*TODO: SARADC_IN3 is used as MIC detection / key input */ -+ -+ simple-audio-card,widgets = -+ "Microphone", "Onboard Microphone", -+ "Microphone", "Microphone Jack", -+ "Speaker", "Speaker", -+ "Headphone", "Headphones"; -+ -+ simple-audio-card,routing = -+ "Headphones", "LOUT1", -+ "Headphones", "ROUT1", -+ "Speaker", "LOUT2", -+ "Speaker", "ROUT2", -+ -+ "Headphones", "Headphones Amp OUTL", -+ "Headphones", "Headphones Amp OUTR", -+ "Headphones Amp INL", "LOUT1", -+ "Headphones Amp INR", "ROUT1", -+ -+ "Speaker", "Speaker Amp OUTL", -+ "Speaker", "Speaker Amp OUTR", -+ "Speaker Amp INL", "LOUT2", -+ "Speaker Amp INR", "ROUT2", -+ -+ /* single ended signal to LINPUT1 */ -+ "LINPUT1", "Microphone Jack", -+ "RINPUT1", "Microphone Jack", -+ /* differential signal */ -+ "LINPUT2", "Onboard Microphone", -+ "RINPUT2", "Onboard Microphone"; -+ -+ daicpu: simple-audio-card,cpu { -+ sound-dai = <&i2s0_8ch>; -+ system-clock-frequency = <12288000>; -+ }; -+ -+ daicodec: simple-audio-card,codec { -+ sound-dai = <&es8388>; -+ system-clock-frequency = <12288000>; -+ }; -+ }; -+ -+ vcc3v3_pcie30: vcc3v3-pcie30-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc3v3_pcie30"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <5000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_pcie_eth: vcc3v3-pcie-eth-regulator { -+ compatible = "regulator-fixed"; -+ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; -+ regulator-name = "vcc3v3_pcie_eth"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_wf: vcc3v3-wf-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc3v3_wf"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc5v0_usb20: vcc5v0-usb20-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb20_en>; -+ regulator-name = "vcc5v0_usb20"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&combphy0_ps { -+ status = "okay"; -+}; -+ -+&combphy1_ps { -+ status = "okay"; -+}; -+ -+&combphy2_psu { -+ status = "okay"; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b2 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_b3 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0m2_xfer>; -+ status = "okay"; -+ -+ vdd_cpu_big0_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big0_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big1_s0: regulator@43 { -+ compatible = "rockchip,rk8603", "rockchip,rk8602"; -+ reg = <0x43>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big1_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c6 { -+ clock-frequency = <400000>; -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ #clock-cells = <0>; -+ clock-output-names = "hym8563"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ wakeup-source; -+ }; -+}; -+ -+&i2c7 { -+ status = "okay"; -+ -+ /* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */ -+ es8388: audio-codec@11 { -+ compatible = "everest,es8388"; -+ reg = <0x11>; -+ clocks = <&cru I2S0_8CH_MCLKOUT>; -+ clock-names = "mclk"; -+ AVDD-supply = <&vcc_1v8_s0>; -+ DVDD-supply = <&vcc_1v8_s0>; -+ HPVDD-supply = <&vcc_3v3_s0>; -+ PVDD-supply = <&vcc_3v3_s0>; -+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; -+ assigned-clock-rates = <12288000>; -+ #sound-dai-cells = <0>; -+ }; -+}; -+ -+&i2s0_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s0_lrck -+ &i2s0_mclk -+ &i2s0_sclk -+ &i2s0_sdi0 -+ &i2s0_sdo0>; -+ status = "okay"; -+}; -+ -+&i2s2_2ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s2m0_lrck -+ &i2s2m0_sclk -+ &i2s2m0_sdi -+ &i2s2m0_sdo>; -+ status = "okay"; -+}; -+ -+/* phy1 - M.KEY socket */ -+&pcie2x1l0 { -+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_wf>; -+ status = "okay"; -+}; -+ -+/* phy2 - right ethernet port */ -+&pcie2x1l1 { -+ reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie_eth>; -+ status = "okay"; -+}; -+ -+/* phy0 - left ethernet port */ -+&pcie2x1l2 { -+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie_eth>; -+ status = "okay"; -+}; -+ -+&pcie30phy { -+ status = "okay"; -+}; -+ -+&pcie3x4 { -+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ leds { -+ blue_led_pin: blue-led { -+ rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ ir-receiver { -+ ir_receiver_pin: ir-receiver-pin { -+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sound { -+ hp_detect: hp-detect { -+ rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb { -+ vcc5v0_usb20_en: vcc5v0-usb20-en { -+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pwm2 { -+ pinctrl-0 = <&pwm2m1_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ -+&pwm3 { -+ pinctrl-0 = <&pwm3m1_pins>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcc_1v8_s0>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ no-sdio; -+ no-sd; -+ non-removable; -+ max-frequency = <200000000>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ max-frequency = <150000000>; -+ no-sdio; -+ no-mmc; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3_s3>; -+ vqmmc-supply = <&vccio_sd_s0>; -+ status = "okay"; -+}; -+ -+&sfc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fspim1_pins>; -+ status = "okay"; -+ -+ spi_flash: flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0x0>; -+ spi-max-frequency = <100000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ -+&spi2 { -+ assigned-clocks = <&cru CLK_SPI2>; -+ assigned-clock-rates = <200000000>; -+ num-cs = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -+ status = "okay"; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ reg = <0x0>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -+ <&rk806_dvs2_null>, <&rk806_dvs3_null>; -+ spi-max-frequency = <1000000>; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc5v0_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc5v0_sys>; -+ vcc13-supply = <&vdd2_ddr_s3>; -+ vcc14-supply = <&vdd2_ddr_s3>; -+ vcca-supply = <&vcc5v0_sys>; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ rk806_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ regulators { -+ vdd_gpu_s0: dcdc-reg1 { -+ regulator-name = "vdd_gpu_s0"; -+ regulator-boot-on; -+ regulator-enable-ramp-delay = <400>; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_s0: dcdc-reg2 { -+ regulator-name = "vdd_cpu_lit_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_log_s0: dcdc-reg3 { -+ regulator-name = "vdd_log_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <825000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: dcdc-reg4 { -+ regulator-name = "vdd_vdenc_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <825000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_s0: dcdc-reg5 { -+ regulator-name = "vdd_ddr_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <900000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vdd2_ddr_s3: dcdc-reg6 { -+ regulator-name = "vdd2_ddr_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-name = "vdd_2v0_pldo_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2000000>; -+ regulator-max-microvolt = <2000000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vcc_3v3_s3: dcdc-reg8 { -+ regulator-name = "vcc_3v3_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vddq_ddr_s0: dcdc-reg9 { -+ regulator-name = "vddq_ddr_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s3: dcdc-reg10 { -+ regulator-name = "vcc_1v8_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avcc_1v8_s0: pldo-reg1 { -+ regulator-name = "avcc_1v8_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ /* shorted to avcc_1v8_s0 on the board */ -+ vcc_1v8_s0: pldo-reg2 { -+ regulator-name = "vcc_1v8_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avdd_1v2_s0: pldo-reg3 { -+ regulator-name = "avdd_1v2_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3_s0: pldo-reg4 { -+ regulator-name = "vcc_3v3_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-name = "vccio_sd_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ pldo6_s3: pldo-reg6 { -+ regulator-name = "pldo6_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-name = "vdd_0v75_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_ddr_pll_s0: nldo-reg2 { -+ regulator-name = "vdd_ddr_pll_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ avdd_0v75_s0: nldo-reg3 { -+ regulator-name = "avdd_0v75_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ /* -+ * The schematic mentions that actual setting -+ * should be 0.8375V. RK3588 datasheet specifies -+ * maximum as 0.825V. So we set datasheet max -+ * here. -+ */ -+ regulator-min-microvolt = <825000>; -+ regulator-max-microvolt = <825000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v85_s0: nldo-reg4 { -+ regulator-name = "vdd_0v85_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v75_s0: nldo-reg5 { -+ regulator-name = "vdd_0v75_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&u2phy2 { -+ status = "okay"; -+}; -+ -+&u2phy3 { -+ status = "okay"; -+}; -+ -+&u2phy2_host { -+ phy-supply = <&vcc5v0_usb20>; -+ status = "okay"; -+}; -+ -+&u2phy3_host { -+ phy-supply = <&vcc5v0_usb20>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m0_xfer>; -+ status = "okay"; -+}; -+ -+&uart9 { -+ pinctrl-0 = <&uart9m0_xfer>; -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.6/055-02-v6.9-arm64-dts-rockchip-remove-redundant-cd-gpios-from-rk3588.patch b/target/linux/rockchip/patches-6.6/055-02-v6.9-arm64-dts-rockchip-remove-redundant-cd-gpios-from-rk3588.patch deleted file mode 100644 index 39b1d8a2d6..0000000000 --- a/target/linux/rockchip/patches-6.6/055-02-v6.9-arm64-dts-rockchip-remove-redundant-cd-gpios-from-rk3588.patch +++ /dev/null @@ -1,55 +0,0 @@ -From d859ad305ed19d9a77d8c8ecd22459b73da36ba6 Mon Sep 17 00:00:00 2001 -From: Kever Yang -Date: Thu, 1 Feb 2024 11:46:21 +0800 -Subject: [PATCH] arm64: dts: rockchip: remove redundant cd-gpios from rk3588 - sdmmc nodes - -The sdmmc node already have a "&sdmmc_det" for pinctrl which switch the -GPIO0A4 to sdmmc detect function, no need to define a separate "cd-gpios". - -RK3588 has force_jtage feature which is enable JTAG function via sdmmc -pins automatically when there is no SD card insert, this feature will -need the GPIO0A4 works in sdmmc_det function like other mmc signal instead -of GPIO function, or else the force_jtag can not auto be disabled when -SD card insert. - -Signed-off-by: Kever Yang -Link: https://lore.kernel.org/r/20240201034621.1970279-1-kever.yang@rock-chips.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 - - 4 files changed, 4 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -@@ -445,7 +445,6 @@ - &sdmmc { - bus-width = <4>; - cap-sd-highspeed; -- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - no-sdio; ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -413,7 +413,6 @@ - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; -- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -395,7 +395,6 @@ - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; -- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - no-sdio; diff --git a/target/linux/rockchip/patches-6.6/056-01-v6.10-arm64-dts-rockchip-Add-ArmSom-Sige7-board.patch b/target/linux/rockchip/patches-6.6/056-01-v6.10-arm64-dts-rockchip-Add-ArmSom-Sige7-board.patch deleted file mode 100644 index cecbfe457c..0000000000 --- a/target/linux/rockchip/patches-6.6/056-01-v6.10-arm64-dts-rockchip-Add-ArmSom-Sige7-board.patch +++ /dev/null @@ -1,778 +0,0 @@ -From 81c828a67c78bb03ea75819c417c93c7f3d637b5 Mon Sep 17 00:00:00 2001 -From: Jianfeng Liu -Date: Sat, 20 Apr 2024 11:43:00 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add ArmSom Sige7 board -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Specification: - Rockchip Rk3588 SoC - 4x ARM Cortex-A76, 4x ARM Cortex-A55 - 8/16/32GB Memory LPDDR4/LPDDR4x - Mali G610MP4 GPU - 2× MIPI-CSI Connector - 1× MIPI-DSI Connector - 1x M.2 Key M (PCIe 3.0 4-lanes) - 2x RTL8125 2.5G Ethernet - Onboard AP6275P for WIFI6/BT5 - 32GB/64GB/128GB eMMC - MicroSD card slot - 1x USB2.0, 1x USB3.0 Type-A, 1x US3.0 Type-C - 1x HDMI Output, 1x type-C DP Output - -Functions work normally: - USB2.0 Host - USB3.0 Type-A Host - M.2 Key M (PCIe 3.0 4-lanes) - 2x RTL8125 2.5G Ethernet - eMMC - MicroSD card - -More information can be obtained from the following website - https://docs.armsom.org/armsom-sige7 - -Signed-off-by: Jianfeng Liu -Reviewed-by: Weizhao Ouyang -Link: https://lore.kernel.org/r/20240420034300.176920-4-liujianfeng1994@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3588-armsom-sige7.dts | 721 ++++++++++++++++++ - 2 files changed, 722 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -103,6 +103,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ra - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -@@ -0,0 +1,721 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include -+#include -+#include "rk3588.dtsi" -+ -+/ { -+ model = "ArmSoM Sige7"; -+ compatible = "armsom,sige7", "rockchip,rk3588"; -+ -+ aliases { -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ analog-sound { -+ compatible = "audio-graph-card"; -+ dais = <&i2s0_8ch_p0>; -+ label = "rk3588-es8316"; -+ hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_detect>; -+ routing = "MIC2", "Mic Jack", -+ "Headphones", "HPOL", -+ "Headphones", "HPOR"; -+ widgets = "Microphone", "Mic Jack", -+ "Headphone", "Headphones"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_rgb_g>; -+ -+ led_green: led-0 { -+ color = ; -+ function = LED_FUNCTION_STATUS; -+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led_red: led-1 { -+ color = ; -+ function = LED_FUNCTION_STATUS; -+ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "none"; -+ }; -+ }; -+ -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ cooling-levels = <0 95 145 195 255>; -+ fan-supply = <&vcc5v0_sys>; -+ pwms = <&pwm1 0 50000 0>; -+ #cooling-cells = <2>; -+ }; -+ -+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie2x1l2"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <5000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vcc3v3_pcie30: vcc3v3-pcie30-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc3v3_pcie30"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <5000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_host: vcc5v0-host-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_host"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host_en>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_1v1_nldo_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&combphy0_ps { -+ status = "okay"; -+}; -+ -+&combphy1_ps { -+ status = "okay"; -+}; -+ -+&combphy2_psu { -+ status = "okay"; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b2 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_b3 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu_s0>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0m2_xfer>; -+ status = "okay"; -+ -+ vdd_cpu_big0_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big0_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big1_s0: regulator@43 { -+ compatible = "rockchip,rk8603", "rockchip,rk8602"; -+ reg = <0x43>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big1_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c6 { -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ #clock-cells = <0>; -+ clock-output-names = "hym8563"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ wakeup-source; -+ }; -+}; -+ -+&i2c7 { -+ status = "okay"; -+ -+ es8316: audio-codec@11 { -+ compatible = "everest,es8316"; -+ reg = <0x11>; -+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; -+ assigned-clock-rates = <12288000>; -+ clocks = <&cru I2S0_8CH_MCLKOUT>; -+ clock-names = "mclk"; -+ #sound-dai-cells = <0>; -+ -+ port { -+ es8316_p0_0: endpoint { -+ remote-endpoint = <&i2s0_8ch_p0_0>; -+ }; -+ }; -+ }; -+}; -+ -+&i2s0_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s0_lrck -+ &i2s0_mclk -+ &i2s0_sclk -+ &i2s0_sdi0 -+ &i2s0_sdo0>; -+ status = "okay"; -+ -+ i2s0_8ch_p0: port { -+ i2s0_8ch_p0_0: endpoint { -+ dai-format = "i2s"; -+ mclk-fs = <256>; -+ remote-endpoint = <&es8316_p0_0>; -+ }; -+ }; -+}; -+ -+/* phy1 - right ethernet port */ -+&pcie2x1l0 { -+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+/* phy2 - WiFi */ -+&pcie2x1l1 { -+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+/* phy0 - left ethernet port */ -+&pcie2x1l2 { -+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&pcie30phy { -+ status = "okay"; -+}; -+ -+&pcie3x4 { -+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ leds { -+ led_rgb_g: led-rgb-g { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ led_rgb_r: led-rgb-r { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sound { -+ hp_detect: hp-detect { -+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb { -+ vcc5v0_host_en: vcc5v0-host-en { -+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&avcc_1v8_s0>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ no-sdio; -+ no-sd; -+ non-removable; -+ mmc-hs200-1_8v; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ max-frequency = <200000000>; -+ no-sdio; -+ no-mmc; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3_s3>; -+ vqmmc-supply = <&vccio_sd_s0>; -+ status = "okay"; -+}; -+ -+&spi2 { -+ assigned-clocks = <&cru CLK_SPI2>; -+ assigned-clock-rates = <200000000>; -+ num-cs = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -+ status = "okay"; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ spi-max-frequency = <1000000>; -+ reg = <0x0>; -+ -+ interrupt-parent = <&gpio0>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -+ <&rk806_dvs2_null>, <&rk806_dvs3_null>; -+ -+ system-power-controller; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc5v0_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc5v0_sys>; -+ vcc13-supply = <&vcc_1v1_nldo_s3>; -+ vcc14-supply = <&vcc_1v1_nldo_s3>; -+ vcca-supply = <&vcc5v0_sys>; -+ -+ rk806_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl1"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ regulators { -+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_gpu_s0"; -+ regulator-enable-ramp-delay = <400>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_lit_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_log_s0: dcdc-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_log_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_vdenc_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_s0: dcdc-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <900000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_ddr_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vdd2_ddr_s3: dcdc-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vdd2_ddr_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2000000>; -+ regulator-max-microvolt = <2000000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_2v0_pldo_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vcc_3v3_s3: dcdc-reg8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vddq_ddr_s0: dcdc-reg9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vddq_ddr_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s3: dcdc-reg10 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avcc_1v8_s0: pldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "avcc_1v8_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s0: pldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avdd_1v2_s0: pldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-name = "avdd_1v2_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3_s0: pldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vccio_sd_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ pldo6_s3: pldo-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "pldo6_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_ddr_pll_s0: nldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_ddr_pll_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ avdd_0v75_s0: nldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "avdd_0v75_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v85_s0: nldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_0v85_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v75_s0: nldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&u2phy3 { -+ status = "okay"; -+}; -+ -+&u2phy3_host { -+ phy-supply = <&vcc5v0_host>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m0_xfer>; -+ status = "okay"; -+}; -+ -+&usbdp_phy1 { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.6/056-02-v6.11-arm64-dts-rockchip-enable-thermal-management-on-all-RK358.patch b/target/linux/rockchip/patches-6.6/056-02-v6.11-arm64-dts-rockchip-enable-thermal-management-on-all-RK358.patch deleted file mode 100644 index 797ece88d1..0000000000 --- a/target/linux/rockchip/patches-6.6/056-02-v6.11-arm64-dts-rockchip-enable-thermal-management-on-all-RK358.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 2f8064b9c4a012b4d4e8383818f13b682b6c156a Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 17 Jun 2024 22:28:52 +0400 -Subject: [PATCH] arm64: dts: rockchip: enable thermal management on all RK3588 - boards - -This enables the on-chip thermal monitoring sensor (TSADC) on all -RK3588(s) boards that don't have it enabled yet. It provides temperature -monitoring for the SoC and emergency thermal shutdowns, and is thus -important to have in place before CPU DVFS is enabled, as high CPU -operating performance points can overheat the chip quickly in the -absence of thermal management. - -Signed-off-by: Alexey Charkov -Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-2-c1f5f3267f1e@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 4 ++++ - 8 files changed, 32 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -@@ -673,6 +673,10 @@ - }; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &u2phy0 { - status = "okay"; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -@@ -807,6 +807,10 @@ - status = "okay"; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &u2phy2 { - status = "okay"; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -786,6 +786,10 @@ - }; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -740,6 +740,10 @@ - }; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &u2phy0 { - status = "okay"; - }; diff --git a/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch deleted file mode 100644 index 19c50c342e..0000000000 --- a/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch +++ /dev/null @@ -1,685 +0,0 @@ -From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Fri, 10 Jul 2020 21:38:20 +0200 -Subject: [PATCH] rockchip: use system LED for OpenWrt - -Use the SYS LED on the casing for showing system status. - -This patch is kept separate from the NanoPi R2S support patch, as i plan -on submitting the device support upstream. - -Signed-off-by: David Bauer ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -@@ -18,6 +18,10 @@ - mmc0 = &emmc; - mmc1 = &sdmmc; - mmc2 = &sdio; -+ led-boot = &blue_led; -+ led-failsafe = &blue_led; -+ led-running = &blue_led; -+ led-upgrade = &blue_led; - }; - - chosen { -@@ -29,22 +33,19 @@ - pinctrl-names = "default"; - pinctrl-0 = <&green_led>, <&heartbeat_led>; - -- green-led { -+ led-0 { - color = ; - default-state = "on"; - function = LED_FUNCTION_POWER; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -- label = "rockpis:green:power"; - linux,default-trigger = "default-on"; - }; - -- blue-led { -+ blue_led: led-1 { - color = ; - default-state = "on"; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; -- label = "rockpis:blue:user"; -- linux,default-trigger = "heartbeat"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -6,6 +6,7 @@ - /dts-v1/; - - #include -+#include - #include - #include "rk3328.dtsi" - -@@ -16,6 +17,11 @@ - aliases { - ethernet1 = &rtl8153; - mmc0 = &sdmmc; -+ -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; - }; - - chosen { -@@ -48,19 +54,22 @@ - pinctrl-names = "default"; - - lan_led: led-0 { -+ color = ; -+ function = LED_FUNCTION_LAN; - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:green:lan"; - }; - - sys_led: led-1 { -+ color = ; -+ function = LED_FUNCTION_STATUS; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:red:sys"; - default-state = "on"; - }; - - wan_led: led-2 { -+ color = ; -+ function = LED_FUNCTION_WAN; - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:green:wan"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -17,6 +17,11 @@ - aliases { - ethernet1 = &rtl8153; - mmc0 = &sdmmc; -+ -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - chosen { -@@ -41,11 +46,10 @@ - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - }; - -- led-1 { -+ status_led: led-1 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - - led-2 { ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -13,6 +13,11 @@ - aliases { - mmc0 = &sdmmc; - mmc1 = &emmc; -+ -+ led-boot = &power_led; -+ led-failsafe = &power_led; -+ led-running = &power_led; -+ led-upgrade = &power_led; - }; - - chosen { -@@ -93,9 +98,7 @@ - - power_led: led-0 { - label = "firefly:blue:power"; -- linux,default-trigger = "heartbeat"; - gpios = <&rk805 1 GPIO_ACTIVE_LOW>; -- default-state = "on"; - }; - - user_led: led-1 { ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts -@@ -23,6 +23,11 @@ - aliases { - mmc0 = &sdmmc; - mmc1 = &emmc; -+ -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - chosen { -@@ -55,10 +60,9 @@ - pinctrl-0 = <&led_pin>; - pinctrl-names = "default"; - -- led-0 { -- color = ; -+ status_led: led-0 { -+ label = "blue:status"; - gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; -- linux,default-trigger = "heartbeat"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -@@ -15,6 +15,13 @@ - model = "FriendlyElec NanoPC-T4"; - compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; - -+ aliases { -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; -+ }; -+ - vcc12v0_sys: vcc12v0-sys { - compatible = "regulator-fixed"; - regulator-always-on; ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -19,6 +19,13 @@ - model = "FriendlyElec NanoPi R4S"; - compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; - -+ aliases { -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; -+ }; -+ - /delete-node/ display-subsystem; - - gpio-leds { ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts -@@ -17,6 +17,10 @@ - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; -+ led-boot = &led_blue; -+ led-failsafe = &led_blue; -+ led-running = &led_blue; -+ led-upgrade = &led_blue; - }; - - chosen { -@@ -44,11 +48,10 @@ - }; - - /* USER_LED2 */ -- led-1 { -+ led_blue: led-1 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -14,6 +14,10 @@ - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; -+ led-boot = &led_blue; -+ led-failsafe = &led_blue; -+ led-running = &led_blue; -+ led-upgrade = &led_blue; - }; - - chosen { -@@ -33,11 +37,10 @@ - pinctrl-0 = <&user_led2>; - - /* USER_LED2 */ -- led-0 { -+ led_blue: led-0 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -@@ -24,6 +24,11 @@ - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc0; -+ -+ led-boot = &power_led; -+ led-failsafe = &power_led; -+ led-running = &power_led; -+ led-upgrade = &power_led; - }; - - chosen: chosen { -@@ -52,7 +57,6 @@ - color = ; - function = LED_FUNCTION_POWER; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -- default-state = "on"; - }; - - lan_led: led-1 { ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi -@@ -17,7 +17,7 @@ - leds { - compatible = "gpio-leds"; - -- led-0 { -+ status_led: led-0 { - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_STATUS; ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -@@ -16,6 +16,10 @@ - aliases { - ethernet0 = &gmac1; - mmc1 = &sdmmc0; -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - chosen: chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi -@@ -6,6 +6,13 @@ - #include "rk3566.dtsi" - - / { -+ aliases { -+ led-boot = &led_green; -+ led-failsafe = &led_green; -+ led-running = &led_green; -+ led-upgrade = &led_green; -+ }; -+ - chosen { - stdout-path = "serial2:1500000n8"; - }; -@@ -26,12 +33,11 @@ - pinctrl-names = "default"; - pinctrl-0 = <&user_led2>; - -- led-green { -+ led_green: led-green { - color = ; - default-state = "on"; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi -@@ -9,6 +9,13 @@ - #include "rk3568.dtsi" - - / { -+ aliases { -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; -+ }; -+ - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; -@@ -35,7 +42,6 @@ - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts -@@ -40,7 +40,6 @@ - power_led: led-power { - color = ; - function = LED_FUNCTION_POWER; -- linux,default-trigger = "heartbeat"; - gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -@@ -39,7 +39,6 @@ - power_led: led-power { - color = ; - function = LED_FUNCTION_POWER; -- linux,default-trigger = "heartbeat"; - gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi -@@ -18,6 +18,11 @@ - aliases { - mmc0 = &sdmmc0; - mmc1 = &sdhci; -+ -+ led-boot = &power_led; -+ led-failsafe = &power_led; -+ led-running = &power_led; -+ led-upgrade = &power_led; - }; - - chosen: chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi -@@ -10,6 +10,11 @@ - - aliases { - mmc0 = &sdhci; -+ -+ led-boot = &led_user; -+ led-failsafe = &led_user; -+ led-running = &led_user; -+ led-upgrade = &led_user; - }; - - chosen { -@@ -23,7 +28,6 @@ - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - color = ; -- linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_user_en>; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts -@@ -16,6 +16,10 @@ - mmc0 = &sdhci; - mmc1 = &sdmmc0; - mmc2 = &sdmmc1; -+ led-boot = &led_blue; -+ led-failsafe = &led_blue; -+ led-running = &led_blue; -+ led-upgrade = &led_blue; - }; - - chosen: chosen { -@@ -43,11 +47,10 @@ - leds { - compatible = "gpio-leds"; - -- led-0 { -- gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; -- function = LED_FUNCTION_HEARTBEAT; -+ led_blue: led-0 { - color = ; -- linux,default-trigger = "heartbeat"; -+ function = LED_FUNCTION_HEARTBEAT; -+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&user_led2>; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts -@@ -19,6 +19,11 @@ - ethernet1 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; -+ -+ led-boot = &power_led; -+ led-failsafe = &power_led; -+ led-running = &power_led; -+ led-upgrade = &power_led; - }; - - chosen: chosen { -@@ -50,15 +55,17 @@ - - leds { - compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&power_led_pin>, <&user_led_pin>; -+ -+ power_led: led-power { -+ label = "red:power"; -+ gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; -+ }; - - led-user { -- label = "user-led"; -- default-state = "on"; -+ label = "blue:user"; - gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; -- pinctrl-names = "default"; -- pinctrl-0 = <&user_led_enable_h>; -- retain-state-suspended; - }; - }; - -@@ -490,7 +497,11 @@ - - &pinctrl { - leds { -- user_led_enable_h: user-led-enable-h { -+ power_led_pin: power-led-pin { -+ rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ user_led_pin: user-led-pin { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -16,6 +16,11 @@ - mmc0 = &sdhci; - mmc1 = &sdmmc0; - mmc2 = &sdmmc2; -+ -+ led-boot = &led_user; -+ led-failsafe = &led_user; -+ led-running = &led_user; -+ led-upgrade = &led_user; - }; - - chosen: chosen { -@@ -47,7 +52,6 @@ - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - color = ; -- linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_user_en>; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts -@@ -18,6 +18,10 @@ - mmc0 = &sdhci; - mmc1 = &sdmmc0; - mmc2 = &sdmmc2; -+ led-boot = &led_green; -+ led-failsafe = &led_green; -+ led-running = &led_green; -+ led-upgrade = &led_green; - }; - - chosen { -@@ -47,12 +51,11 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led>; - -- led-0 { -+ led_green: led-0 { - color = ; - default-state = "on"; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -@@ -13,6 +13,11 @@ - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; -+ -+ led-boot = &led_red; -+ led-failsafe = &led_red; -+ led-running = &led_red; -+ led-upgrade = &led_red; - }; - - chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -20,6 +20,10 @@ - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; - }; - - adc-keys-0 { -@@ -53,7 +57,6 @@ - sys_led: led-0 { - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - label = "system-led"; -- linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_pin>; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -@@ -20,6 +20,11 @@ - mmc0 = &sdhci; - mmc1 = &sdmmc; - serial2 = &uart2; -+ -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - chosen { -@@ -78,7 +83,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&blue_led_pin>; - -- led { -+ status_led: led { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -14,6 +14,11 @@ - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; -+ -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - chosen { -@@ -42,11 +47,10 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led_rgb_b>; - -- led_rgb_b { -+ status_led: led_rgb_b { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts -@@ -16,6 +16,11 @@ - aliases { - mmc0 = &sdmmc; - serial2 = &uart2; -+ -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - chosen { -@@ -41,10 +46,9 @@ - pinctrl-names = "default"; - pinctrl-0 =<&leds_gpio>; - -- led-1 { -+ status_led: led-1 { - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "status_led"; -- linux,default-trigger = "heartbeat"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -14,6 +14,11 @@ - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; -+ -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - analog-sound { -@@ -39,11 +44,10 @@ - pinctrl-names = "default"; - pinctrl-0 = <&io_led>; - -- io-led { -+ status_led: io-led { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - }; - diff --git a/target/linux/rockchip/patches-6.6/101-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch b/target/linux/rockchip/patches-6.6/101-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch deleted file mode 100644 index 89a0d9a8be..0000000000 --- a/target/linux/rockchip/patches-6.6/101-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch +++ /dev/null @@ -1,25 +0,0 @@ -From bc6c96d850419e71dbc9b0094ccc9b668ba9be43 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Mon, 28 Sep 2020 22:54:52 +0200 -Subject: [PATCH] rockchip: rk3328: add compatible to NanoPi R2S ethernet PHY - -This adds the compatible property to the NanoPi R2S ethernet PHY node. -Otherwise, the PHY might not be probed, as the PHY ID reads all 0xff -when it is still in reset. - -Signed-off-by: David Bauer ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -165,6 +165,8 @@ - #size-cells = <0>; - - rtl8211e: ethernet-phy@1 { -+ compatible = "ethernet-phy-id001c.c915", -+ "ethernet-phy-ieee802.3-c22"; - reg = <1>; - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; diff --git a/target/linux/rockchip/patches-6.6/102-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch b/target/linux/rockchip/patches-6.6/102-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch deleted file mode 100644 index 70c53ba3a4..0000000000 --- a/target/linux/rockchip/patches-6.6/102-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 3b7eb946b1d640d684a921e53e1e50985ab7eb89 Mon Sep 17 00:00:00 2001 -From: QiuSimons <45143996+QiuSimons@users.noreply.github.com> -Date: Tue, 4 Aug 2020 20:17:53 +0800 -Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s - ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4 ++++ - 1 files changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -177,6 +177,10 @@ - }; - }; - -+&i2c0 { -+ status = "okay"; -+}; -+ - &i2c1 { - status = "okay"; - diff --git a/target/linux/rockchip/patches-6.6/103-arm64-dts-rockchip-lower-mmc-speed.patch b/target/linux/rockchip/patches-6.6/103-arm64-dts-rockchip-lower-mmc-speed.patch deleted file mode 100644 index 174b785623..0000000000 --- a/target/linux/rockchip/patches-6.6/103-arm64-dts-rockchip-lower-mmc-speed.patch +++ /dev/null @@ -1,90 +0,0 @@ -From: David Bauer -Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S - -The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting -while U-Boot requires the card to be in 3.3V mode. - -Remove UHS support from the SD controller so the card remains in 3.3V -mode. This reduces transfer speeds but ensures a reboot whether from -userspace or following a kernel panic is always working. - -Signed-off-by: David Bauer - ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -333,7 +333,6 @@ - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; -- sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -119,6 +119,11 @@ - status = "disabled"; - }; - -+&sdmmc { -+ /delete-property/ sd-uhs-sdr104; -+ cap-sd-highspeed; -+}; -+ - &u2phy0_host { - phy-supply = <&vdd_5v>; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -@@ -346,7 +346,7 @@ - max-frequency = <200000000>; - no-sdio; - no-mmc; -- sd-uhs-sdr104; -+ sd-uhs-sdr50; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -620,8 +620,7 @@ - no-sd; - non-removable; - max-frequency = <200000000>; -- mmc-hs400-1_8v; -- mmc-hs400-enhanced-strobe; -+ mmc-hs200-1_8v; - status = "okay"; - }; - -@@ -633,7 +632,7 @@ - disable-wp; - no-mmc; - no-sdio; -- sd-uhs-sdr104; -+ sd-uhs-sdr50; - vmmc-supply = <&vcc3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -418,7 +418,7 @@ - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -- sd-uhs-sdr104; -+ sd-uhs-sdr50; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -403,7 +403,7 @@ - max-frequency = <150000000>; - no-sdio; - no-mmc; -- sd-uhs-sdr104; -+ sd-uhs-sdr50; - vmmc-supply = <&vcc_3v3_s0>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; diff --git a/target/linux/rockchip/patches-6.6/104-arm64-dts-rockchip-enable-wifi-and-bt-for-station-p2.patch b/target/linux/rockchip/patches-6.6/104-arm64-dts-rockchip-enable-wifi-and-bt-for-station-p2.patch deleted file mode 100644 index c0ecc726d4..0000000000 --- a/target/linux/rockchip/patches-6.6/104-arm64-dts-rockchip-enable-wifi-and-bt-for-station-p2.patch +++ /dev/null @@ -1,97 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts -@@ -69,6 +69,17 @@ - }; - }; - -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk809 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_enable_h>; -+ post-power-on-delay-ms = <100>; -+ power-off-delay-us = <5000000>; -+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; -+ }; -+ - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; -@@ -506,6 +517,26 @@ - }; - }; - -+ bt { -+ bt_enable: bt-enable { -+ rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake: bt-host-wake { -+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ bt_wake: bt-wake { -+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -@@ -577,6 +608,22 @@ - status = "okay"; - }; - -+&sdmmc2 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ disable-wp; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v3_sys>; -+ vqmmc-supply = <&vcca1v8_pmu>; -+ status = "okay"; -+}; -+ - &tsadc { - status = "okay"; - }; -@@ -585,6 +632,26 @@ - status = "okay"; - }; - -+&uart8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ clocks = <&rk809 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; -+ host-wakeup-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; -+ vbat-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcca1v8_pmu>; -+ }; -+}; -+ - &usb2phy0_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; diff --git a/target/linux/rockchip/patches-6.6/105-arm64-dts-rockchip-enable-wifi-and-bt-for-armsom-sige.patch b/target/linux/rockchip/patches-6.6/105-arm64-dts-rockchip-enable-wifi-and-bt-for-armsom-sige.patch deleted file mode 100644 index ee878e24fa..0000000000 --- a/target/linux/rockchip/patches-6.6/105-arm64-dts-rockchip-enable-wifi-and-bt-for-armsom-sige.patch +++ /dev/null @@ -1,87 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -@@ -273,6 +273,24 @@ - &pcie2x1l1 { - reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00300000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ wifi: wifi@30,0 { -+ compatible = "brcm,bcm4329-fmac", "pci14e4,449d"; -+ reg = <0x310000 0 0 0 0>; -+ clocks = <&hym8563>; -+ clock-names = "lpo"; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ interrupt-names = "host-wake"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_reg_on_h>; -+ }; -+ }; - }; - - /* phy0 - left ethernet port */ -@@ -292,12 +310,32 @@ - }; - - &pinctrl { -+ bt { -+ bt_reg_on_h: bt-reg-on-h { -+ rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake_h: bt-host-wake-h { -+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_h: bt-wake-h { -+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - -+ pcie { -+ wifi_reg_on_h: wifi-reg-on-h { -+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ - leds { - led_rgb_g: led-rgb-g { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -@@ -712,6 +750,26 @@ - status = "okay"; - }; - -+&uart6 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ clocks = <&hym8563>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -+ host-wakeup-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_host_wake_h &bt_wake_h &bt_reg_on_h>; -+ vbat-supply = <&vcc_3v3_s3>; -+ vddio-supply = <&vcc_1v8_s3>; -+ }; -+}; -+ - &usbdp_phy1 { - status = "okay"; - }; diff --git a/target/linux/rockchip/patches-6.6/112-01-math-h-add-DIV_ROUND_UP_NO_OVERFLOW.patch b/target/linux/rockchip/patches-6.6/112-01-math-h-add-DIV_ROUND_UP_NO_OVERFLOW.patch deleted file mode 100644 index 9cf051d7ec..0000000000 --- a/target/linux/rockchip/patches-6.6/112-01-math-h-add-DIV_ROUND_UP_NO_OVERFLOW.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 5c55891831f244cf2dde12055b1da8738094fef4 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 24 Oct 2023 16:09:35 +0200 -Subject: [PATCH] math.h: add DIV_ROUND_UP_NO_OVERFLOW - -Add a new DIV_ROUND_UP helper, which cannot overflow when -big numbers are being used. - -Signed-off-by: Sebastian Reichel ---- - include/linux/math.h | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/include/linux/math.h -+++ b/include/linux/math.h -@@ -36,6 +36,17 @@ - - #define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP - -+/** -+ * DIV_ROUND_UP_NO_OVERFLOW - divide two numbers and always round up -+ * @n: numerator / dividend -+ * @d: denominator / divisor -+ * -+ * This functions does the same as DIV_ROUND_UP, but internally uses a -+ * division and a modulo operation instead of math tricks. This way it -+ * avoids overflowing when handling big numbers. -+ */ -+#define DIV_ROUND_UP_NO_OVERFLOW(n, d) (((n) / (d)) + !!((n) % (d))) -+ - #define DIV_ROUND_DOWN_ULL(ll, d) \ - ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; }) - diff --git a/target/linux/rockchip/patches-6.6/112-02-clk-divider-Fix-divisor-masking-on-64-bit-platforms.patch b/target/linux/rockchip/patches-6.6/112-02-clk-divider-Fix-divisor-masking-on-64-bit-platforms.patch deleted file mode 100644 index ce28d53e8b..0000000000 --- a/target/linux/rockchip/patches-6.6/112-02-clk-divider-Fix-divisor-masking-on-64-bit-platforms.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 81f3db1af2934b19df3dd6a7103db558ce6281da Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 24 Oct 2023 16:13:50 +0200 -Subject: [PATCH] clk: divider: Fix divisor masking on 64 bit platforms - -The clock framework handles clock rates as "unsigned long", so u32 on -32-bit architectures and u64 on 64-bit architectures. - -The current code casts the dividend to u64 on 32-bit to avoid a -potential overflow. For example DIV_ROUND_UP(3000000000, 1500000000) -= (3.0G + 1.5G - 1) / 1.5G = = OVERFLOW / 1.5G, which has been -introduced in commit 9556f9dad8f5 ("clk: divider: handle integer overflow -when dividing large clock rates"). - -On 64 bit platforms this masks the divisor, so that only the lower -32 bit are used. Thus requesting a frequency >= 4.3GHz results -in incorrect values. For example requesting 4300000000 (4.3 GHz) will -effectively request ca. 5 MHz. Requesting clk_round_rate(clk, ULONG_MAX) -is a bit of a special case, since that still returns correct values as -long as the parent clock is below 8.5 GHz. - -Fix this by switching to DIV_ROUND_UP_NO_OVERFLOW, which cannot -overflow. This avoids any requirements on the arguments (except -that divisor should not be 0 obviously). - -Signed-off-by: Sebastian Reichel ---- - drivers/clk/clk-divider.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/clk/clk-divider.c -+++ b/drivers/clk/clk-divider.c -@@ -220,7 +220,7 @@ static int _div_round_up(const struct cl - unsigned long parent_rate, unsigned long rate, - unsigned long flags) - { -- int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); -+ int div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate); - - if (flags & CLK_DIVIDER_POWER_OF_TWO) - div = __roundup_pow_of_two(div); -@@ -237,7 +237,7 @@ static int _div_round_closest(const stru - int up, down; - unsigned long up_rate, down_rate; - -- up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); -+ up = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate); - down = parent_rate / rate; - - if (flags & CLK_DIVIDER_POWER_OF_TWO) { -@@ -473,7 +473,7 @@ int divider_get_val(unsigned long rate, - { - unsigned int div, value; - -- div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); -+ div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate); - - if (!_is_valid_div(table, div, flags)) - return -EINVAL; diff --git a/target/linux/rockchip/patches-6.6/112-03-clk-composite-replace-open-coded-abs_diff.patch b/target/linux/rockchip/patches-6.6/112-03-clk-composite-replace-open-coded-abs_diff.patch deleted file mode 100644 index 958e33be32..0000000000 --- a/target/linux/rockchip/patches-6.6/112-03-clk-composite-replace-open-coded-abs_diff.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 46254b2d8f2fb027df8597641878069ca11a7f11 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 24 Oct 2023 18:09:57 +0200 -Subject: [PATCH] clk: composite: replace open-coded abs_diff() - -Replace the open coded abs_diff() with the existing helper function. - -Suggested-by: Andy Shevchenko -Signed-off-by: Sebastian Reichel ---- - drivers/clk/clk-composite.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - ---- a/drivers/clk/clk-composite.c -+++ b/drivers/clk/clk-composite.c -@@ -6,6 +6,7 @@ - #include - #include - #include -+#include - #include - - static u8 clk_composite_get_parent(struct clk_hw *hw) -@@ -119,10 +120,7 @@ static int clk_composite_determine_rate( - if (ret) - continue; - -- if (req->rate >= tmp_req.rate) -- rate_diff = req->rate - tmp_req.rate; -- else -- rate_diff = tmp_req.rate - req->rate; -+ rate_diff = abs_diff(req->rate, tmp_req.rate); - - if (!rate_diff || !req->best_parent_hw - || best_rate_diff > rate_diff) { diff --git a/target/linux/rockchip/patches-6.6/123-07-arm64-dts-rockchip-rk3588-rock5b-add-USB-C-support.patch b/target/linux/rockchip/patches-6.6/123-07-arm64-dts-rockchip-rk3588-rock5b-add-USB-C-support.patch deleted file mode 100644 index 16b0b09911..0000000000 --- a/target/linux/rockchip/patches-6.6/123-07-arm64-dts-rockchip-rk3588-rock5b-add-USB-C-support.patch +++ /dev/null @@ -1,192 +0,0 @@ -From 152b46f9ad81fe60f2845c87b0298db84bbecdc9 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 25 Jul 2023 18:35:56 +0200 -Subject: [PATCH] [BROKEN] arm64: dts: rockchip: rk3588-rock5b: add USB-C - support - -Add support for using the Radxa Rock 5 Model B USB-C port for USB in -OHCI, EHCI or XHCI mode. Displayport AltMode is not yet supported. - -Note: Enabling support for the USB-C port results in a board reset -when the system is supplied with a PD capable power-supply. Until -this has been analyzed and fixed, let's disable support for the -Type-C port. - -Signed-off-by: Sebastian Reichel ---- - .../boot/dts/rockchip/rk3588-rock-5b.dts | 119 ++++++++++++++++++ - 1 file changed, 119 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -4,6 +4,7 @@ - - #include - #include -+#include - #include "rk3588.dtsi" - - / { -@@ -69,6 +70,15 @@ - shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - -+ vcc12v_dcin: vcc12v-dcin-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ - vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { - compatible = "regulator-fixed"; - enable-active-high; -@@ -127,6 +137,7 @@ - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { -@@ -229,6 +240,61 @@ - }; - }; - -+&i2c4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c4m1_xfer>; -+ status = "okay"; -+ -+ usbc0: usb-typec@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio3>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usbc0_int>; -+ vbus-supply = <&vcc12v_dcin>; -+ status = "disabled"; -+ -+ usb_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ data-role = "dual"; -+ power-role = "sink"; -+ try-power-role = "sink"; -+ op-sink-microwatt = <1000000>; -+ sink-pdos = -+ , -+ ; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usbc0_hs: endpoint { -+ remote-endpoint = <&usb_host0_xhci_drd_sw>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ usbc0_ss: endpoint { -+ remote-endpoint = <&usbdp_phy0_typec_ss>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ usbc0_sbu: endpoint { -+ remote-endpoint = <&usbdp_phy0_typec_sbu>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ - &i2c6 { - status = "okay"; - -@@ -388,6 +454,10 @@ - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ -+ usbc0_int: usbc0-int { -+ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; - }; - }; - -@@ -799,6 +869,14 @@ - status = "okay"; - }; - -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ - &u2phy1 { - status = "okay"; - }; -@@ -830,6 +908,29 @@ - status = "okay"; - }; - -+&usbdp_phy0 { -+ orientation-switch; -+ mode-switch; -+ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; -+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ usbdp_phy0_typec_ss: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&usbc0_ss>; -+ }; -+ -+ usbdp_phy0_typec_sbu: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&usbc0_sbu>; -+ }; -+ }; -+}; -+ - &usb_host0_ehci { - status = "okay"; - }; -@@ -838,6 +939,20 @@ - status = "okay"; - }; - -+&usb_host0_xhci { -+ usb-role-switch; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ usb_host0_xhci_drd_sw: endpoint { -+ remote-endpoint = <&usbc0_hs>; -+ }; -+ }; -+}; -+ - &usb_host1_ehci { - status = "okay"; - }; diff --git a/target/linux/rockchip/patches-6.6/130-arm64-dts-rockchip-rk3399-include-opp-table.patch b/target/linux/rockchip/patches-6.6/130-arm64-dts-rockchip-rk3399-include-opp-table.patch deleted file mode 100644 index a80a766ace..0000000000 --- a/target/linux/rockchip/patches-6.6/130-arm64-dts-rockchip-rk3399-include-opp-table.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3399-guangmiao-g4c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-guangmiao-g4c.dts -@@ -4,6 +4,7 @@ - #include - #include - #include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" - - / { - model = "Huake-Cloud GuangMiao G4C"; diff --git a/target/linux/rockchip/patches-6.6/300-nvmem-rockchip-otp-Add-support-for-rk3568-otp.patch b/target/linux/rockchip/patches-6.6/300-nvmem-rockchip-otp-Add-support-for-rk3568-otp.patch deleted file mode 100644 index 1d9ae07b33..0000000000 --- a/target/linux/rockchip/patches-6.6/300-nvmem-rockchip-otp-Add-support-for-rk3568-otp.patch +++ /dev/null @@ -1,134 +0,0 @@ -From 154292ae52bf21c77aa1b81035bd85343b416001 Mon Sep 17 00:00:00 2001 -From: Finley Xiao -Date: Thu, 12 Nov 2020 16:24:14 +0800 -Subject: [PATCH] nvmem: rockchip-otp: Add support for rk3568-otp - -This adds the necessary data for handling efuse on the rk3568. - -Signed-off-by: Finley Xiao -Change-Id: Ia74d77b68a6303223eaccdc08e882851a917f50f ---- - drivers/nvmem/rockchip-otp.c | 90 ++++++++++++++++++++++++++++++++++++ - 1 file changed, 90 insertions(+) - ---- a/drivers/nvmem/rockchip-otp.c -+++ b/drivers/nvmem/rockchip-otp.c -@@ -27,6 +27,7 @@ - #define OTPC_USER_CTRL 0x0100 - #define OTPC_USER_ADDR 0x0104 - #define OTPC_USER_ENABLE 0x0108 -+#define OTPC_USER_QP 0x0120 - #define OTPC_USER_Q 0x0124 - #define OTPC_INT_STATUS 0x0304 - #define OTPC_SBPI_CMD0_OFFSET 0x1000 -@@ -53,6 +54,7 @@ - #define SBPI_ENABLE_MASK GENMASK(16, 16) - - #define OTPC_TIMEOUT 10000 -+#define RK3568_NBYTES 2 - - /* RK3588 Register */ - #define RK3588_OTPC_AUTO_CTRL 0x04 -@@ -184,6 +186,73 @@ read_end: - return ret; - } - -+static int rk3568_otp_read(void *context, unsigned int offset, void *val, -+ size_t bytes) -+{ -+ struct rockchip_otp *otp = context; -+ unsigned int addr_start, addr_end, addr_offset, addr_len; -+ unsigned int otp_qp; -+ u32 data; -+ u8 *buf; -+ int ret, i = 0; -+ -+ addr_start = rounddown(offset, RK3568_NBYTES) / RK3568_NBYTES; -+ addr_end = roundup(offset + bytes, RK3568_NBYTES) / RK3568_NBYTES; -+ addr_offset = offset % RK3568_NBYTES; -+ addr_len = addr_end - addr_start; -+ -+ buf = kzalloc(array3_size(addr_len, RK3568_NBYTES, sizeof(*buf)), -+ GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ ret = rockchip_otp_reset(otp); -+ if (ret) { -+ dev_err(otp->dev, "failed to reset otp phy\n"); -+ return ret; -+ } -+ -+ ret = rockchip_otp_ecc_enable(otp, true); -+ if (ret < 0) { -+ dev_err(otp->dev, "rockchip_otp_ecc_enable err\n"); -+ return ret; -+ } -+ -+ writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); -+ udelay(5); -+ while (addr_len--) { -+ writel(addr_start++ | OTPC_USER_ADDR_MASK, -+ otp->base + OTPC_USER_ADDR); -+ writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK, -+ otp->base + OTPC_USER_ENABLE); -+ -+ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE); -+ if (ret < 0) { -+ dev_err(otp->dev, "timeout during read setup\n"); -+ goto read_end; -+ } -+ -+ otp_qp = readl(otp->base + OTPC_USER_QP); -+ if (((otp_qp & 0xc0) == 0xc0) || (otp_qp & 0x20)) { -+ ret = -EIO; -+ dev_err(otp->dev, "ecc check error during read setup\n"); -+ goto read_end; -+ } -+ -+ data = readl(otp->base + OTPC_USER_Q); -+ memcpy(&buf[i], &data, RK3568_NBYTES); -+ -+ i += RK3568_NBYTES; -+ } -+ -+ memcpy(val, buf + addr_offset, bytes); -+ -+read_end: -+ writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); -+ -+ return ret; -+} -+ - static int rk3588_otp_read(void *context, unsigned int offset, - void *val, size_t bytes) - { -@@ -274,6 +343,17 @@ static const struct rockchip_data px30_d - .reg_read = px30_otp_read, - }; - -+static const char * const rk3568_otp_clocks[] = { -+ "usr", "sbpi", "apb", "phy", -+}; -+ -+static const struct rockchip_data rk3568_data = { -+ .size = 0x80, -+ .clks = rk3568_otp_clocks, -+ .num_clks = ARRAY_SIZE(rk3568_otp_clocks), -+ .reg_read = rk3568_otp_read, -+}; -+ - static const char * const rk3588_otp_clocks[] = { - "otp", "apb_pclk", "phy", "arb", - }; -@@ -295,6 +375,10 @@ static const struct of_device_id rockchi - .data = &px30_data, - }, - { -+ .compatible = "rockchip,rk3568-otp", -+ .data = &rk3568_data, -+ }, -+ { - .compatible = "rockchip,rk3588-otp", - .data = &rk3588_data, - }, diff --git a/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-rk3568-Add-otp-device-node.patch b/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-rk3568-Add-otp-device-node.patch deleted file mode 100644 index c2fc33aa35..0000000000 --- a/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-rk3568-Add-otp-device-node.patch +++ /dev/null @@ -1,61 +0,0 @@ -From e8c0448b695911c5a0cc37cadaacaf71d16b04d2 Mon Sep 17 00:00:00 2001 -From: Finley Xiao -Date: Thu, 12 Nov 2020 15:43:28 +0800 -Subject: [PATCH] arm64: dts: rockchip: rk3568: Add otp device node - -Signed-off-by: Finley Xiao -Change-Id: I4ec51ba8d4e1381f787c0137cb475a21e546789d ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 29 ++++++++++++++++++++++++ - 1 file changed, 29 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -894,6 +894,47 @@ - }; - }; - -+ otp: otp@fe38c000 { -+ compatible = "rockchip,rk3568-otp"; -+ reg = <0x0 0xfe38c000 0x0 0x4000>; -+ clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>, -+ <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>; -+ clock-names = "usr", "sbpi", "apb", "phy"; -+ resets = <&cru SRST_OTPPHY>; -+ reset-names = "otp_phy"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ cpu_code: cpu-code@2 { -+ reg = <0x02 0x2>; -+ }; -+ -+ otp_cpu_version: cpu-version@8 { -+ reg = <0x08 0x1>; -+ bits = <3 3>; -+ }; -+ -+ otp_id: id@a { -+ reg = <0x0a 0x10>; -+ }; -+ -+ cpu_leakage: cpu-leakage@1a { -+ reg = <0x1a 0x1>; -+ }; -+ -+ log_leakage: log-leakage@1b { -+ reg = <0x1b 0x1>; -+ }; -+ -+ npu_leakage: npu-leakage@1c { -+ reg = <0x1c 0x1>; -+ }; -+ -+ gpu_leakage: gpu-leakage@1d { -+ reg = <0x1d 0x1>; -+ }; -+ }; -+ - qos_gpu: qos@fe128000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe128000 0x0 0x20>; diff --git a/target/linux/rockchip/patches-6.6/302-arm64-cpuinfo-add-system-serial-support.patch b/target/linux/rockchip/patches-6.6/302-arm64-cpuinfo-add-system-serial-support.patch deleted file mode 100644 index 5bf86c854b..0000000000 --- a/target/linux/rockchip/patches-6.6/302-arm64-cpuinfo-add-system-serial-support.patch +++ /dev/null @@ -1,36 +0,0 @@ -From a21e820a5ae04e1b6619f601430b9602c597db33 Mon Sep 17 00:00:00 2001 -From: Tao Huang -Date: Thu, 27 Oct 2016 19:41:45 +0800 -Subject: [PATCH] arm64: cpuinfo: add system serial support - -Change-Id: I4542f07226e47e67be1f2792cffaa71fd6401442 -Signed-off-by: Tao Huang ---- - arch/arm64/kernel/cpuinfo.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/kernel/cpuinfo.c -+++ b/arch/arm64/kernel/cpuinfo.c -@@ -25,6 +25,12 @@ - #include - #include - -+unsigned int system_serial_low; -+EXPORT_SYMBOL(system_serial_low); -+ -+unsigned int system_serial_high; -+EXPORT_SYMBOL(system_serial_high); -+ - /* - * In case the boot CPU is hotpluggable, we record its initial state and - * current state separately. Certain system registers may contain different -@@ -237,6 +243,9 @@ static int c_show(struct seq_file *m, vo - seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); - } - -+ seq_printf(m, "Serial\t\t: %08x%08x\n", -+ system_serial_high, system_serial_low); -+ - return 0; - } - diff --git a/target/linux/rockchip/patches-6.6/303-soc-rockchip-add-cpuinfo-support.patch b/target/linux/rockchip/patches-6.6/303-soc-rockchip-add-cpuinfo-support.patch deleted file mode 100644 index e8f99c11d5..0000000000 --- a/target/linux/rockchip/patches-6.6/303-soc-rockchip-add-cpuinfo-support.patch +++ /dev/null @@ -1,48 +0,0 @@ -From c336f64cf9a9c1bbeb0027f26c94ecfb29367ee1 Mon Sep 17 00:00:00 2001 -From: "Huang, Tao" -Date: Thu, 6 Apr 2017 20:27:14 +0800 -Subject: [PATCH] soc: rockchip: add cpuinfo support - -Set system_serial_low/high from eFuse ID. -Serial can read from /proc/cpuinfo. - -Change-Id: If412fc5a89a5e5092b510452fc5a126fdd374ac2 -Signed-off-by: Huang, Tao ---- - .../soc/rockchip/rockchip-cpuinfo.txt | 16 ++++ - drivers/soc/rockchip/Kconfig | 10 +++ - drivers/soc/rockchip/Makefile | 1 + - drivers/soc/rockchip/rockchip-cpuinfo.c | 75 +++++++++++++++++++ - 4 files changed, 102 insertions(+) - create mode 100644 Documentation/devicetree/bindings/soc/rockchip/rockchip-cpuinfo.txt - create mode 100644 drivers/soc/rockchip/rockchip-cpuinfo.c - ---- a/drivers/soc/rockchip/Kconfig -+++ b/drivers/soc/rockchip/Kconfig -@@ -5,6 +5,16 @@ if ARCH_ROCKCHIP || COMPILE_TEST - # Rockchip Soc drivers - # - -+config ROCKCHIP_CPUINFO -+ tristate "Rockchip cpuinfo support" -+ depends on (NVMEM_ROCKCHIP_EFUSE || NVMEM_ROCKCHIP_OTP) && (ARM64 || ARM) -+ help -+ Say y here to enable Rockchip cpuinfo support. -+ Set system_serial_low/high from eFuse ID. -+ Serial can read from /proc/cpuinfo. -+ -+ If unsure, say N. -+ - config ROCKCHIP_GRF - bool "Rockchip General Register Files support" if COMPILE_TEST - default y if ARCH_ROCKCHIP ---- a/drivers/soc/rockchip/Makefile -+++ b/drivers/soc/rockchip/Makefile -@@ -2,6 +2,7 @@ - # - # Rockchip Soc drivers - # -+obj-$(CONFIG_ROCKCHIP_CPUINFO) += cpuinfo.o - obj-$(CONFIG_ROCKCHIP_GRF) += grf.o - obj-$(CONFIG_ROCKCHIP_IODOMAIN) += io-domain.o - obj-$(CONFIG_ROCKCHIP_DTPM) += dtpm.o diff --git a/target/linux/rockchip/patches-6.6/304-01-arm64-dts-rockchip-add-cpuinfo-support-for-rk3328.patch b/target/linux/rockchip/patches-6.6/304-01-arm64-dts-rockchip-add-cpuinfo-support-for-rk3328.patch deleted file mode 100644 index a87a84e2ca..0000000000 --- a/target/linux/rockchip/patches-6.6/304-01-arm64-dts-rockchip-add-cpuinfo-support-for-rk3328.patch +++ /dev/null @@ -1,26 +0,0 @@ -From e9c54637e971995d06ac8fd7c6d3b57d62848249 Mon Sep 17 00:00:00 2001 -From: Chen Liang -Date: Fri, 7 Apr 2017 17:25:45 +0800 -Subject: [PATCH] ARM64: dts: rockchip: add cpuinfo support for rk3328 - -Change-Id: Iaaa400c09c2fb7c0d5e96fa4217065fa14066fc1 -Signed-off-by: Chen Liang ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -169,6 +169,12 @@ - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - -+ cpuinfo { -+ compatible = "rockchip,cpuinfo"; -+ nvmem-cells = <&efuse_id>, <&efuse_cpu_version>; -+ nvmem-cell-names = "id", "cpu-version"; -+ }; -+ - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; diff --git a/target/linux/rockchip/patches-6.6/304-02-arm64-dts-rockchip-add-cpuinfo-support-for-rk3399.patch b/target/linux/rockchip/patches-6.6/304-02-arm64-dts-rockchip-add-cpuinfo-support-for-rk3399.patch deleted file mode 100644 index e3d9cb3d57..0000000000 --- a/target/linux/rockchip/patches-6.6/304-02-arm64-dts-rockchip-add-cpuinfo-support-for-rk3399.patch +++ /dev/null @@ -1,27 +0,0 @@ -From f63140be2575c8ae35fdc29a23a9f4a819ec3cd5 Mon Sep 17 00:00:00 2001 -From: "Huang, Tao" -Date: Thu, 6 Apr 2017 20:30:11 +0800 -Subject: [PATCH] arm64: dts: rockchip: add cpuinfo support for rk3399-android - -Change-Id: I0eba0017a88added1a84f9c3add1705d8079cd00 -Signed-off-by: Huang, Tao ---- - arch/arm64/boot/dts/rockchip/rk3399-android.dtsi | 6 ++++++ - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 3 +++ - 2 files changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -173,6 +173,12 @@ - }; - }; - -+ cpuinfo { -+ compatible = "rockchip,cpuinfo"; -+ nvmem-cells = <&cpu_id>; -+ nvmem-cell-names = "id"; -+ }; -+ - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vopl_out>, <&vopb_out>; diff --git a/target/linux/rockchip/patches-6.6/304-03-arm64-dts-rockchip-add-cpuinfo-node-for-rk3568.patch b/target/linux/rockchip/patches-6.6/304-03-arm64-dts-rockchip-add-cpuinfo-node-for-rk3568.patch deleted file mode 100644 index ad917d473c..0000000000 --- a/target/linux/rockchip/patches-6.6/304-03-arm64-dts-rockchip-add-cpuinfo-node-for-rk3568.patch +++ /dev/null @@ -1,26 +0,0 @@ -From cc9529c8ba206aaed6bdd3674572a7eb7126d851 Mon Sep 17 00:00:00 2001 -From: Liang Chen -Date: Tue, 29 Dec 2020 15:22:03 +0800 -Subject: [PATCH] arm64: dts: rockchip: add cpuinfo node for rk3568 - -Change-Id: Ia98489355ca992d19f8c215978dd25699603c6ce -Signed-off-by: Liang Chen ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -170,6 +170,12 @@ - }; - }; - -+ cpuinfo { -+ compatible = "rockchip,cpuinfo"; -+ nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; -+ nvmem-cell-names = "id", "cpu-version", "cpu-code"; -+ }; -+ - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; diff --git a/target/linux/rockchip/patches-6.6/304-04-arm64-dts-rockchip-rk3588s-Add-cpuinfo-device-node.patch b/target/linux/rockchip/patches-6.6/304-04-arm64-dts-rockchip-rk3588s-Add-cpuinfo-device-node.patch deleted file mode 100644 index bd5c5f5b5a..0000000000 --- a/target/linux/rockchip/patches-6.6/304-04-arm64-dts-rockchip-rk3588s-Add-cpuinfo-device-node.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 16b5587b5f6c975c7b546805939dbd563bbc2099 Mon Sep 17 00:00:00 2001 -From: Finley Xiao -Date: Wed, 22 Dec 2021 17:37:31 +0800 -Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add cpuinfo device node - -Signed-off-by: Finley Xiao -Change-Id: I050cc7f6398500e705b27c588948201e571817ea ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -348,6 +348,12 @@ - }; - }; - -+ cpuinfo { -+ compatible = "rockchip,cpuinfo"; -+ nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; -+ nvmem-cell-names = "id", "cpu-version", "cpu-code"; -+ }; -+ - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; diff --git a/target/linux/rockchip/patches-6.6/501-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-6.6/501-mmc-core-set-initial-signal-voltage-on-power-off.patch deleted file mode 100644 index 0a58265be2..0000000000 --- a/target/linux/rockchip/patches-6.6/501-mmc-core-set-initial-signal-voltage-on-power-off.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Wed, 20 Feb 2019 07:38:34 +0000 -Subject: [PATCH] mmc: core: set initial signal voltage on power off - -Some boards have SD card connectors where the power rail cannot be switched -off by the driver. If the card has not been power cycled, it may still be -using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling -will fail to boot from a UHS card that continue to use 1.8V signaling. - -Set initial signal voltage in mmc_power_off() to allow re-boot to function. - -This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288), -same issue have been seen on some Rockchip RK3399 boards. - -I am sending this as a RFC because I have no insights into SD/MMC subsystem, -this change fix a re-boot issue on my boards and does not break emmc/sdio. -Is this an acceptable workaround? Any advice is appreciated. - -Signed-off-by: Jonas Karlman ---- - drivers/mmc/core/core.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/mmc/core/core.c -+++ b/drivers/mmc/core/core.c -@@ -1370,6 +1370,8 @@ void mmc_power_off(struct mmc_host *host - - mmc_pwrseq_power_off(host); - -+ mmc_set_initial_signal_voltage(host); -+ - host->ios.clock = 0; - host->ios.vdd = 0; - diff --git a/target/linux/rockchip/patches-6.6/600-ethernet-stmmac-Add-property-to-disable-VLAN-hw-filter.patch b/target/linux/rockchip/patches-6.6/600-ethernet-stmmac-Add-property-to-disable-VLAN-hw-filter.patch deleted file mode 100644 index c595dbb390..0000000000 --- a/target/linux/rockchip/patches-6.6/600-ethernet-stmmac-Add-property-to-disable-VLAN-hw-filter.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 32230f9e59438899c949a4bab178a8f10f17b903 Mon Sep 17 00:00:00 2001 -From: jensen -Date: Thu, 17 Nov 2022 18:35:43 +0800 -Subject: [PATCH] ethernet: stmmac: Add property to disable VLAN hw filter - -Since adding VLAN in promisc mode not supported, which makes unable to -setup bridge, add a configurable option to disable it. - -Signed-off-by: jensen ---- - drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +- - drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +++ - include/linux/stmmac.h | 1 + - 3 files changed, 5 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1633,6 +1633,7 @@ - snps,mixed-burst; - snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; -+ snps,no-vlhash; - snps,tso; - status = "disabled"; - ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -309,6 +309,7 @@ - snps,mixed-burst; - snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; -+ snps,no-vlhash; - snps,tso; - status = "disabled"; - ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -7572,7 +7572,7 @@ int stmmac_dvr_probe(struct device *devi - #ifdef STMMAC_VLAN_TAG_USED - /* Both mac100 and gmac support receive VLAN tag detection */ - ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; -- if (priv->dma_cap.vlhash) { -+ if (priv->plat->vlhash_en && priv->dma_cap.vlhash) { - ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; - ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; - } ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -@@ -589,6 +589,9 @@ stmmac_probe_config_dt(struct platform_d - "force_sf_dma_mode is ignored if force_thresh_dma_mode is set.\n"); - } - -+ /* To disable VLAN tag filter */ -+ plat->vlhash_en = !of_property_read_bool(np, "snps,no-vlhash"); -+ - of_property_read_u32(np, "snps,ps-speed", &plat->mac_port_sel_speed); - - plat->axi = stmmac_axi_setup(pdev); ---- a/include/linux/stmmac.h -+++ b/include/linux/stmmac.h -@@ -299,6 +299,7 @@ struct plat_stmmacenet_data { - int rss_en; - int mac_port_sel_speed; - int has_xgmac; -+ bool vlhash_en; - u8 vlan_fail_q; - unsigned int eee_usecs_rate; - struct pci_dev *pdev; diff --git a/target/linux/rockchip/patches-6.6/602-net-ethernet-r8169-add-devname-configuration-from-OF.patch b/target/linux/rockchip/patches-6.6/602-net-ethernet-r8169-add-devname-configuration-from-OF.patch deleted file mode 100644 index 45cd453568..0000000000 --- a/target/linux/rockchip/patches-6.6/602-net-ethernet-r8169-add-devname-configuration-from-OF.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/drivers/net/ethernet/realtek/r8169_main.c -+++ b/drivers/net/ethernet/realtek/r8169_main.c -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -5446,6 +5447,7 @@ static int rtl_init_one(struct pci_dev * - int jumbo_max, region, rc; - enum mac_version chipset; - struct net_device *dev; -+ const char *devname = of_get_property(pdev->dev.of_node, "label", NULL); - u32 txconfig; - u16 xid; - -@@ -5453,6 +5455,9 @@ static int rtl_init_one(struct pci_dev * - if (!dev) - return -ENOMEM; - -+ if (devname) -+ strscpy(dev->name, devname, IFNAMSIZ); -+ - SET_NETDEV_DEV(dev, &pdev->dev); - dev->netdev_ops = &rtl_netdev_ops; - tp = netdev_priv(dev); diff --git a/target/linux/rockchip/patches-6.6/603-net-ethernet-stmmac-add-devname-configuration-from-OF.patch b/target/linux/rockchip/patches-6.6/603-net-ethernet-stmmac-add-devname-configuration-from-OF.patch deleted file mode 100644 index 02455bc174..0000000000 --- a/target/linux/rockchip/patches-6.6/603-net-ethernet-stmmac-add-devname-configuration-from-OF.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -7398,6 +7398,7 @@ int stmmac_dvr_probe(struct device *devi - { - struct net_device *ndev = NULL; - struct stmmac_priv *priv; -+ const char *devname = of_get_property(device->of_node, "label", NULL); - u32 rxq; - int i, ret = 0; - -@@ -7406,6 +7407,9 @@ int stmmac_dvr_probe(struct device *devi - if (!ndev) - return -ENOMEM; - -+ if (devname) -+ strscpy(ndev->name, devname, IFNAMSIZ); -+ - SET_NETDEV_DEV(ndev, device); - - priv = netdev_priv(ndev); diff --git a/target/linux/rockchip/patches-6.6/610-arm64-rockchip-add-OF-node-for-eth.patch b/target/linux/rockchip/patches-6.6/610-arm64-rockchip-add-OF-node-for-eth.patch deleted file mode 100644 index 15dc332473..0000000000 --- a/target/linux/rockchip/patches-6.6/610-arm64-rockchip-add-OF-node-for-eth.patch +++ /dev/null @@ -1,502 +0,0 @@ -From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Sun, 26 Jul 2020 13:32:59 +0200 -Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S - -This adds the OF node for the USB3 ethernet adapter on the FriendlyARM -NanoPi R2S. Add the correct value for the RTL8153 LED configuration -register to match the blink behavior of the other port on the device. - -Signed-off-by: David Bauer ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts -@@ -29,6 +29,7 @@ - motorcomm,clk-out-frequency-hz = <125000000>; - motorcomm,keep-pll-enabled; - motorcomm,auto-sleep-disabled; -+ motorcomm,led-data = <0xe004 0x0 0x2600 0x0070 0x000a>; - - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; -@@ -38,3 +39,7 @@ - }; - }; - }; -+ -+&rtl8153 { -+ realtek,led-data = <0x78>; -+}; ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -409,9 +409,11 @@ - #size-cells = <0>; - - /* Second port is for USB 3.0 */ -- rtl8153: device@2 { -- compatible = "usbbda,8153"; -+ rtl8153: usb-eth@2 { -+ compatible = "realtek,rtl8153"; - reg = <2>; -+ -+ realtek,led-data = <0x87>; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -362,9 +362,11 @@ - #size-cells = <0>; - - /* Second port is for USB 3.0 */ -- rtl8153: device@2 { -- compatible = "usbbda,8153"; -+ rtl8153: usb-eth@2 { -+ compatible = "realtek,rtl8153"; - reg = <2>; -+ -+ realtek,led-data = <0x87>; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts -@@ -33,6 +33,7 @@ - motorcomm,keep-pll-enabled; - motorcomm,rx-clk-drv-microamp = <5020>; - motorcomm,rx-data-drv-microamp = <5020>; -+ motorcomm,led-data = <0xe004 0x0 0x2600 0x0070 0x000a>; - - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; -@@ -42,3 +43,7 @@ - }; - }; - }; -+ -+&rtl8153 { -+ realtek,led-data = <0x78>; -+}; ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -83,6 +83,19 @@ - max-link-speed = <1>; - num-lanes = <1>; - vpcie3v3-supply = <&vcc3v3_sys>; -+ -+ pcie@0 { -+ reg = <0x00000000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ pcie-eth@0,0 { -+ compatible = "pci10ec,8168"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x870>; -+ }; -+ }; - }; - - &pinctrl { ---- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -@@ -417,6 +417,25 @@ - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ led@1 { -+ reg = <1>; -+ color = ; -+ function = LED_FUNCTION_WAN; -+ default-state = "keep"; -+ }; -+ -+ led@2 { -+ reg = <2>; -+ color = ; -+ function = LED_FUNCTION_WAN; -+ default-state = "keep"; -+ }; -+ }; - }; - }; - -@@ -425,6 +444,18 @@ - pinctrl-0 = <&pcie_reset_h>; - reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00000000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ rtl8168: pcie@1,0 { -+ compatible = "pci10ec,8168"; -+ reg = <0x000000 0 0 0 0>; -+ realtek,led-data = <0x870>; -+ }; -+ }; - }; - - &pinctrl { ---- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi -@@ -369,6 +369,19 @@ - reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00100000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ rtl8125_1: pcie-eth@10,0 { -+ compatible = "pci10ec,8125"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x200 0x2b 0x0 0x0>; -+ }; -+ }; - }; - - &pcie3x2 { -@@ -376,6 +389,19 @@ - reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00200000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ rtl8125_2: pcie-eth@20,0 { -+ compatible = "pci10ec,8125"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x200 0x2b 0x0 0x0>; -+ }; -+ }; - }; - - &pinctrl { ---- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts -@@ -31,6 +31,7 @@ - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; -+ label = "eth0"; - phy-handle = <&rgmii_phy0>; - phy-mode = "rgmii-id"; - pinctrl-names = "default"; -@@ -53,6 +54,7 @@ - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; -+ label = "eth1"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-id"; - pinctrl-names = "default"; -@@ -76,6 +78,25 @@ - reg = <0x1>; - pinctrl-0 = <ð_phy0_reset_pin>; - pinctrl-names = "default"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ led@1 { -+ reg = <1>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ default-state = "keep"; -+ }; -+ -+ led@2 { -+ reg = <2>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ default-state = "keep"; -+ }; -+ }; - }; - }; - -@@ -85,6 +106,25 @@ - reg = <0x1>; - pinctrl-0 = <ð_phy1_reset_pin>; - pinctrl-names = "default"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ led@1 { -+ reg = <1>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ default-state = "keep"; -+ }; -+ -+ led@2 { -+ reg = <2>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ default-state = "keep"; -+ }; -+ }; - }; - }; - -@@ -106,6 +146,14 @@ - vccio3-supply = <&vcc_3v3>; - }; - -+&rtl8125_1 { -+ label = "eth3"; -+}; -+ -+&rtl8125_2 { -+ label = "eth2"; -+}; -+ - &sdhci { - bus-width = <8>; - max-frequency = <200000000>; ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts -@@ -69,6 +69,19 @@ - reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00100000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ rtl8125_1: pcie-eth@10,0 { -+ compatible = "pci10ec,8125"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x0 0x0 0x2b 0x200>; -+ }; -+ }; - }; - - &pcie3x2 { -@@ -76,6 +89,19 @@ - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00200000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ rtl8125_2: pcie-eth@20,0 { -+ compatible = "pci10ec,8125"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x0 0x0 0x2b 0x200>; -+ }; -+ }; - }; - - &pinctrl { ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -@@ -78,6 +78,25 @@ - reg = <1>; - pinctrl-0 = <ð_phy0_reset_pin>; - pinctrl-names = "default"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ led@1 { -+ reg = <1>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ default-state = "keep"; -+ }; -+ -+ led@2 { -+ reg = <2>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ default-state = "keep"; -+ }; -+ }; - }; - }; - -@@ -85,6 +104,19 @@ - num-lanes = <1>; - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00000000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ rtl8125_1: pcie@1,0 { -+ compatible = "pci10ec,8125"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x0 0x0 0x2b 0x200>; -+ }; -+ }; - }; - - &pcie30phy { -@@ -97,6 +129,19 @@ - reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00100000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ rtl8125_2: pcie@10,0 { -+ compatible = "pci10ec,8125"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x0 0x0 0x2b 0x200>; -+ }; -+ }; - }; - - &pcie3x2 { ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -591,6 +591,25 @@ - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ led@1 { -+ reg = <1>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ default-state = "keep"; -+ }; -+ -+ led@2 { -+ reg = <2>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ default-state = "keep"; -+ }; -+ }; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -@@ -267,6 +267,19 @@ - &pcie2x1l0 { - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00200000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ rtl8125_1: pcie@20,0 { -+ compatible = "pci10ec,8125"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x0 0x2b 0x200 0x0>; -+ }; -+ }; - }; - - /* phy2 - WiFi */ -@@ -297,6 +310,19 @@ - &pcie2x1l2 { - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00400000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ rtl8125_2: pcie@40,0 { -+ compatible = "pci10ec,8125"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x0 0x2b 0x200 0x0>; -+ }; -+ }; - }; - - &pcie30phy { ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -510,6 +510,20 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00200000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ rtl8125_1: pcie@20,0 { -+ compatible = "pci10ec,8125"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x0 0x0 0x2b 0x200>; -+ label = "eth2"; -+ }; -+ }; - }; - - &pcie2x1l1 { -@@ -526,6 +540,20 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00400000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ rtl8125_2: pcie@40,0 { -+ compatible = "pci10ec,8125"; -+ reg = <0x000000 0 0 0 0>; -+ -+ realtek,led-data = <0x0 0x0 0x2b 0x200>; -+ label = "eth1"; -+ }; -+ }; - }; - - &pcie30phy { diff --git a/target/linux/rockchip/patches-6.6/700-phy-rockchip-snps-pcie3-rk3568-update-fw-when-init.patch b/target/linux/rockchip/patches-6.6/700-phy-rockchip-snps-pcie3-rk3568-update-fw-when-init.patch deleted file mode 100644 index f587f5d671..0000000000 --- a/target/linux/rockchip/patches-6.6/700-phy-rockchip-snps-pcie3-rk3568-update-fw-when-init.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 91802f44a959582842bdbbd0190e68337ad4c60c Mon Sep 17 00:00:00 2001 -From: Kever Yang -Date: Mon, 11 Jul 2022 20:35:52 +0800 -Subject: [PATCH] phy: rockchip-snps-pcie3: rk3568: update fw when init - -This fw fix some RX issue: -1. connect detect error; -2. transfer error in ssd huge data write(more than 10GB). - -Signed-off-by: Kever Yang -Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2 ---- - drivers/phy/phy-rockchip-snps-pcie3.c | 36 +- - drivers/phy/phy-rockchip-snps-pcie3.fw | 8192 ++++++++++++++++++++++++ - 2 files changed, 8225 insertions(+), 3 deletions(-) - create mode 100644 drivers/phy/phy-rockchip-snps-pcie3.fw - ---- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -@@ -21,6 +21,7 @@ - - /* Register for RK3568 */ - #define GRF_PCIE30PHY_CON1 0x4 -+#define GRF_PCIE30PHY_CON4 0x10 - #define GRF_PCIE30PHY_CON6 0x18 - #define GRF_PCIE30PHY_CON9 0x24 - #define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31)) -@@ -73,6 +74,10 @@ struct rockchip_p3phy_ops { - int (*phy_init)(struct rockchip_p3phy_priv *priv); - }; - -+static u16 phy_fw[] = { -+ #include "p3phy.fw" -+}; -+ - static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) - { - struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); -@@ -97,13 +102,14 @@ static int rockchip_p3phy_rk3568_init(st - { - struct phy *phy = priv->phy; - bool bifurcation = false; -+ int i; - int ret; - u32 reg; - - /* Deassert PCIe PMA output clamp mode */ - regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM); - -- for (int i = 0; i < priv->num_lanes; i++) { -+ for (i = 0; i < priv->num_lanes; i++) { - dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); - if (priv->lanes[i] > 1) - bifurcation = true; -@@ -122,16 +128,35 @@ static int rockchip_p3phy_rk3568_init(st - GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1); - } - -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4, -+ (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4, -+ (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass -+ - reset_control_deassert(priv->p30phy); - - ret = regmap_read_poll_timeout(priv->phy_grf, - GRF_PCIE30PHY_STATUS0, - reg, SRAM_INIT_DONE(reg), - 0, 500); -- if (ret) -+ if (ret) { - dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", - __func__, reg); -- return ret; -+ return ret; -+ } -+ -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, -+ (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram -+ for (i = 0; i < 8192; i++) -+ writel(phy_fw[i], priv->mmio + (i<<2)); -+ -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, -+ (0x0 << 8) | (0x3 << (8 + 16))); -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4, -+ (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done -+ -+ dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n"); -+ return 0; - } - - static const struct rockchip_p3phy_ops rk3568_ops = { diff --git a/target/linux/rockchip/patches-6.6/710-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support-for.patch b/target/linux/rockchip/patches-6.6/710-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support-for.patch deleted file mode 100644 index 6f42196ccc..0000000000 --- a/target/linux/rockchip/patches-6.6/710-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support-for.patch +++ /dev/null @@ -1,320 +0,0 @@ -From ca89ea7e0760c096c6fd807d321ecb8416f8cd9d Mon Sep 17 00:00:00 2001 -From: David Wu -Date: Thu, 31 Dec 2020 18:32:03 +0800 -Subject: [PATCH] ethernet: stmicro: stmmac: Add SGMII/QSGMII support for - RK3568 - -After the completion of Clause 37 auto-negotiation, xpcs automatically -switches to the negotiated speed for 10/100/1000M. - -Change-Id: Iab9dd6ee61a35bf89fd3a0721f5d398de501a7ec -Signed-off-by: David Wu ---- - .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 228 +++++++++++++++++- - 1 file changed, 217 insertions(+), 11 deletions(-) - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -30,6 +31,8 @@ struct rk_gmac_ops { - void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, - int tx_delay, int rx_delay); - void (*set_to_rmii)(struct rk_priv_data *bsp_priv); -+ void (*set_to_sgmii)(struct rk_priv_data *bsp_priv); -+ void (*set_to_qsgmii)(struct rk_priv_data *bsp_priv); - void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); - void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); - void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, -@@ -40,7 +43,7 @@ struct rk_gmac_ops { - }; - - static const char * const rk_clocks[] = { -- "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed", -+ "aclk_mac", "pclk_mac", "pclk_xpcs", "clk_xpcs_eee", "mac_clk_tx", "clk_mac_speed", - }; - - static const char * const rk_rmii_clocks[] = { -@@ -50,6 +53,7 @@ static const char * const rk_rmii_clocks - enum rk_clocks_index { - RK_ACLK_MAC = 0, - RK_PCLK_MAC, -+ RK_PCLK_XPCS, - RK_MAC_CLK_TX, - RK_CLK_MAC_SPEED, - RK_MAC_CLK_RX, -@@ -81,6 +85,7 @@ struct rk_priv_data { - - struct regmap *grf; - struct regmap *php_grf; -+ struct regmap *xpcs; - }; - - #define HIWORD_UPDATE(val, mask, shift) \ -@@ -93,6 +98,128 @@ struct rk_priv_data { - (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ - ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) - -+/* XPCS */ -+#define XPCS_APB_INCREMENT (0x4) -+#define XPCS_APB_MASK GENMASK_ULL(20, 0) -+ -+#define SR_MII_BASE (0x1F0000) -+#define SR_MII1_BASE (0x1A0000) -+ -+#define VR_MII_DIG_CTRL1 (0x8000) -+#define VR_MII_AN_CTRL (0x8001) -+#define VR_MII_AN_INTR_STS (0x8002) -+#define VR_MII_LINK_TIMER_CTRL (0x800A) -+ -+#define SR_MII_CTRL_AN_ENABLE \ -+ (BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000) -+#define MII_MAC_AUTO_SW (0x0200) -+#define PCS_MODE_OFFSET (0x1) -+#define MII_AN_INTR_EN (0x1) -+#define PCS_SGMII_MODE (0x2 << PCS_MODE_OFFSET) -+#define PCS_QSGMII_MODE (0X3 << PCS_MODE_OFFSET) -+#define VR_MII_CTRL_SGMII_AN_EN (PCS_SGMII_MODE | MII_AN_INTR_EN) -+#define VR_MII_CTRL_QSGMII_AN_EN (PCS_QSGMII_MODE | MII_AN_INTR_EN) -+ -+#define SR_MII_OFFSET(_x) ({ \ -+ typeof(_x) (x) = (_x); \ -+ (((x) == 0) ? SR_MII_BASE : (SR_MII1_BASE + ((x) - 1) * 0x10000)); \ -+}) \ -+ -+static int xpcs_read(void *priv, int reg) -+{ -+ struct rk_priv_data *bsp_priv = (struct rk_priv_data *)priv; -+ int ret, val; -+ -+ ret = regmap_read(bsp_priv->xpcs, -+ (u32)(reg * XPCS_APB_INCREMENT) & XPCS_APB_MASK, -+ &val); -+ if (ret) -+ return ret; -+ -+ return val; -+} -+ -+static int xpcs_write(void *priv, int reg, u16 value) -+{ -+ struct rk_priv_data *bsp_priv = (struct rk_priv_data *)priv; -+ -+ return regmap_write(bsp_priv->xpcs, -+ (reg * XPCS_APB_INCREMENT) & XPCS_APB_MASK, value); -+} -+ -+static int xpcs_poll_reset(struct rk_priv_data *bsp_priv, int dev) -+{ -+ /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */ -+ unsigned int retries = 12; -+ int ret; -+ -+ do { -+ msleep(50); -+ ret = xpcs_read(bsp_priv, SR_MII_OFFSET(dev) + MDIO_CTRL1); -+ if (ret < 0) -+ return ret; -+ } while (ret & MDIO_CTRL1_RESET && --retries); -+ -+ return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0; -+} -+ -+static int xpcs_soft_reset(struct rk_priv_data *bsp_priv, int dev) -+{ -+ int ret; -+ -+ ret = xpcs_write(bsp_priv, SR_MII_OFFSET(dev) + MDIO_CTRL1, -+ MDIO_CTRL1_RESET); -+ if (ret < 0) -+ return ret; -+ -+ return xpcs_poll_reset(bsp_priv, dev); -+} -+ -+static int xpcs_setup(struct rk_priv_data *bsp_priv, int mode) -+{ -+ int ret, i, idx = bsp_priv->id; -+ u32 val; -+ -+ if (mode == PHY_INTERFACE_MODE_QSGMII && idx > 0) -+ return 0; -+ -+ ret = xpcs_soft_reset(bsp_priv, idx); -+ if (ret) { -+ dev_err(&bsp_priv->pdev->dev, "xpcs_soft_reset fail %d\n", ret); -+ return ret; -+ } -+ -+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_INTR_STS, 0x0); -+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_LINK_TIMER_CTRL, 0x1); -+ -+ if (mode == PHY_INTERFACE_MODE_SGMII) -+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_CTRL, -+ VR_MII_CTRL_SGMII_AN_EN); -+ else -+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_CTRL, -+ VR_MII_CTRL_QSGMII_AN_EN); -+ -+ if (mode == PHY_INTERFACE_MODE_QSGMII) { -+ for (i = 0; i < 4; i++) { -+ val = xpcs_read(bsp_priv, -+ SR_MII_OFFSET(i) + VR_MII_DIG_CTRL1); -+ xpcs_write(bsp_priv, -+ SR_MII_OFFSET(i) + VR_MII_DIG_CTRL1, -+ val | MII_MAC_AUTO_SW); -+ xpcs_write(bsp_priv, SR_MII_OFFSET(i) + MII_BMCR, -+ SR_MII_CTRL_AN_ENABLE); -+ } -+ } else { -+ val = xpcs_read(bsp_priv, SR_MII_OFFSET(idx) + VR_MII_DIG_CTRL1); -+ xpcs_write(bsp_priv, SR_MII_OFFSET(idx) + VR_MII_DIG_CTRL1, -+ val | MII_MAC_AUTO_SW); -+ xpcs_write(bsp_priv, SR_MII_OFFSET(idx) + MII_BMCR, -+ SR_MII_CTRL_AN_ENABLE); -+ } -+ -+ return ret; -+} -+ - #define PX30_GRF_GMAC_CON1 0x0904 - - /* PX30_GRF_GMAC_CON1 */ -@@ -1021,6 +1148,7 @@ static const struct rk_gmac_ops rk3399_o - #define RK3568_GRF_GMAC1_CON1 0x038c - - /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ -+#define RK3568_GMAC_GMII_MODE GRF_BIT(7) - #define RK3568_GMAC_PHY_INTF_SEL_RGMII \ - (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) - #define RK3568_GMAC_PHY_INTF_SEL_RMII \ -@@ -1036,6 +1164,46 @@ static const struct rk_gmac_ops rk3399_o - #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) - #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) - -+#define RK3568_PIPE_GRF_XPCS_CON0 0X0040 -+ -+#define RK3568_PIPE_GRF_XPCS_QGMII_MAC_SEL GRF_BIT(0) -+#define RK3568_PIPE_GRF_XPCS_SGMII_MAC_SEL GRF_BIT(1) -+#define RK3568_PIPE_GRF_XPCS_PHY_READY GRF_BIT(2) -+ -+static void rk3568_set_to_sgmii(struct rk_priv_data *bsp_priv) -+{ -+ struct device *dev = &bsp_priv->pdev->dev; -+ u32 con1; -+ -+ if (IS_ERR(bsp_priv->grf)) { -+ dev_err(dev, "Missing rockchip,grf property\n"); -+ return; -+ } -+ -+ con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : -+ RK3568_GRF_GMAC0_CON1; -+ regmap_write(bsp_priv->grf, con1, RK3568_GMAC_GMII_MODE); -+ -+ xpcs_setup(bsp_priv, PHY_INTERFACE_MODE_SGMII); -+} -+ -+static void rk3568_set_to_qsgmii(struct rk_priv_data *bsp_priv) -+{ -+ struct device *dev = &bsp_priv->pdev->dev; -+ u32 con1; -+ -+ if (IS_ERR(bsp_priv->grf)) { -+ dev_err(dev, "Missing rockchip,grf property\n"); -+ return; -+ } -+ -+ con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : -+ RK3568_GRF_GMAC0_CON1; -+ regmap_write(bsp_priv->grf, con1, RK3568_GMAC_GMII_MODE); -+ -+ xpcs_setup(bsp_priv, PHY_INTERFACE_MODE_QSGMII); -+} -+ - static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, - int tx_delay, int rx_delay) - { -@@ -1108,6 +1276,8 @@ static void rk3568_set_gmac_speed(struct - static const struct rk_gmac_ops rk3568_ops = { - .set_to_rgmii = rk3568_set_to_rgmii, - .set_to_rmii = rk3568_set_to_rmii, -+ .set_to_sgmii = rk3568_set_to_sgmii, -+ .set_to_qsgmii = rk3568_set_to_qsgmii, - .set_rgmii_speed = rk3568_set_gmac_speed, - .set_rmii_speed = rk3568_set_gmac_speed, - .regs_valid = true, -@@ -1580,7 +1750,7 @@ static int gmac_clk_enable(struct rk_pri - return 0; - } - --static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) -+static int rk_gmac_phy_power_on(struct rk_priv_data *bsp_priv, bool enable) - { - struct regulator *ldo = bsp_priv->regulator; - int ret; -@@ -1679,6 +1849,18 @@ static struct rk_priv_data *rk_gmac_setu - "rockchip,grf"); - bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node, - "rockchip,php-grf"); -+ bsp_priv->xpcs = syscon_regmap_lookup_by_phandle(dev->of_node, -+ "rockchip,xpcs"); -+ if (!IS_ERR(bsp_priv->xpcs)) { -+ struct phy *comphy; -+ -+ comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL); -+ if (IS_ERR(comphy)) -+ dev_err(dev, "devm_of_phy_get error\n"); -+ ret = phy_init(comphy); -+ if (ret) -+ dev_err(dev, "phy_init error\n"); -+ } - - if (plat->phy_node) { - bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, -@@ -1756,11 +1938,19 @@ static int rk_gmac_powerup(struct rk_pri - dev_info(dev, "init for RMII\n"); - bsp_priv->ops->set_to_rmii(bsp_priv); - break; -+ case PHY_INTERFACE_MODE_SGMII: -+ dev_info(dev, "init for SGMII\n"); -+ bsp_priv->ops->set_to_sgmii(bsp_priv); -+ break; -+ case PHY_INTERFACE_MODE_QSGMII: -+ dev_info(dev, "init for QSGMII\n"); -+ bsp_priv->ops->set_to_qsgmii(bsp_priv); -+ break; - default: - dev_err(dev, "NO interface defined!\n"); - } - -- ret = phy_power_on(bsp_priv, true); -+ ret = rk_gmac_phy_power_on(bsp_priv, true); - if (ret) { - gmac_clk_enable(bsp_priv, false); - return ret; -@@ -1781,7 +1971,7 @@ static void rk_gmac_powerdown(struct rk_ - - pm_runtime_put_sync(&gmac->pdev->dev); - -- phy_power_on(gmac, false); -+ rk_gmac_phy_power_on(gmac, false); - gmac_clk_enable(gmac, false); - } - -@@ -1802,6 +1992,9 @@ static void rk_fix_speed(void *priv, uns - if (bsp_priv->ops->set_rmii_speed) - bsp_priv->ops->set_rmii_speed(bsp_priv, speed); - break; -+ case PHY_INTERFACE_MODE_SGMII: -+ case PHY_INTERFACE_MODE_QSGMII: -+ break; - default: - dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); - } diff --git a/target/linux/rockchip/patches-6.6/711-arm64-dts-rockchip-rk3568-Add-xpcs-support.patch b/target/linux/rockchip/patches-6.6/711-arm64-dts-rockchip-rk3568-Add-xpcs-support.patch deleted file mode 100644 index 2f4aefb004..0000000000 --- a/target/linux/rockchip/patches-6.6/711-arm64-dts-rockchip-rk3568-Add-xpcs-support.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 1847729a77175ba5cd64adb419d15dca0f19eb48 Mon Sep 17 00:00:00 2001 -From: David Wu -Date: Thu, 31 Dec 2020 18:34:12 +0800 -Subject: [PATCH] arm64: dts: rockchip: rk3568: Add xpcs support - -Change-Id: I431393b2346f5f7fd6b0d74f79e643df9a586479 -Signed-off-by: David Wu ---- - arch/arm64/boot/dts/rockchip/rk3566.dtsi | 1 + - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 32 +++++++++++++++++++++--- - 2 files changed, 29 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -269,6 +269,13 @@ - arm,no-tick-in-suspend; - }; - -+ gmac1_xpcsclk: xpcs-gmac1-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clk_gmac1_xpcs_mii"; -+ #clock-cells = <0>; -+ }; -+ - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; -@@ -428,6 +435,12 @@ - status = "disabled"; - }; - -+ xpcs: syscon@fda00000 { -+ compatible = "rockchip,rk3568-xpcs", "syscon"; -+ reg = <0x0 0xfda00000 0x0 0x200000>; -+ status = "disabled"; -+ }; -+ - pmugrf: syscon@fdc20000 { - compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc20000 0x0 0x10000>; -@@ -727,11 +740,13 @@ - clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, - <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, -- <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; -+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>, -+ <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", -- "clk_mac_speed", "ptp_ref"; -+ "clk_mac_speed", "ptp_ref", -+ "pclk_xpcs", "clk_xpcs_eee"; - resets = <&cru SRST_A_GMAC1>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -8,6 +8,13 @@ - / { - compatible = "rockchip,rk3568"; - -+ gmac0_xpcsclk: xpcs-gmac0-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clk_gmac0_xpcs_mii"; -+ #clock-cells = <0>; -+ }; -+ - sata0: sata@fc000000 { - compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfc000000 0 0x1000>; -@@ -175,11 +182,13 @@ - clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, - <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, -- <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; -+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, -+ <&cru PCLK_XPCS>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", -- "clk_mac_speed", "ptp_ref"; -+ "clk_mac_speed", "ptp_ref", -+ "pclk_xpcs"; - resets = <&cru SRST_A_GMAC0>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; diff --git a/target/linux/rockchip/patches-6.6/712-phy-rockchip-naneng-combphy-add-sgmii-mac-sel.patch b/target/linux/rockchip/patches-6.6/712-phy-rockchip-naneng-combphy-add-sgmii-mac-sel.patch deleted file mode 100644 index 2318635ca4..0000000000 --- a/target/linux/rockchip/patches-6.6/712-phy-rockchip-naneng-combphy-add-sgmii-mac-sel.patch +++ /dev/null @@ -1,38 +0,0 @@ ---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -@@ -122,6 +122,7 @@ struct rockchip_combphy_grfcfg { - struct combphy_reg pipe_xpcs_phy_ready; - struct combphy_reg pipe_pcie1l0_sel; - struct combphy_reg pipe_pcie1l1_sel; -+ struct combphy_reg pipe_sgmii_mac_sel; - }; - - struct rockchip_combphy_cfg { -@@ -274,6 +275,7 @@ static struct phy *rockchip_combphy_xlat - - static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv) - { -+ int mac_id; - int i; - - priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); -@@ -309,6 +311,11 @@ static int rockchip_combphy_parse_dt(str - - priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); - -+ if (!device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &mac_id)) { -+ rockchip_combphy_param_write(priv->pipe_grf, &priv->cfg->grfcfg->pipe_sgmii_mac_sel, -+ (mac_id > 0) ? true : false); -+ } -+ - priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy"); - /* fallback to old behaviour */ - if (PTR_ERR(priv->phy_rst) == -ENOENT) -@@ -574,6 +581,7 @@ static const struct rockchip_combphy_grf - /* pipe-grf */ - .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, - .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, -+ .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, - }; - - static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { diff --git a/target/linux/rockchip/patches-6.6/801-01-hwrng-rockchip-add-support-for-Rockchip-HW-RNG.patch b/target/linux/rockchip/patches-6.6/801-01-hwrng-rockchip-add-support-for-Rockchip-HW-RNG.patch deleted file mode 100644 index 5844e8b7bd..0000000000 --- a/target/linux/rockchip/patches-6.6/801-01-hwrng-rockchip-add-support-for-Rockchip-HW-RNG.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 1f1992c51a3f44352253204a11fc34738b739d20 Mon Sep 17 00:00:00 2001 -From: Lin Jinhan -Date: Fri, 24 Aug 2018 09:15:03 +0800 -Subject: [PATCH] hwrng: rockchip - add support for Rockchip HW RNG - -Change-Id: Ia14bd624716eb6531ef8674843ccfbada3197d8e -Signed-off-by: Lin Jinhan ---- - drivers/char/hw_random/Kconfig | 12 ++ - drivers/char/hw_random/Makefile | 1 + - drivers/char/hw_random/rockchip-rng.c | 214 ++++++++++++++++++++++++++ - 3 files changed, 227 insertions(+) - create mode 100644 drivers/char/hw_random/rockchip-rng.c - ---- a/drivers/char/hw_random/Kconfig -+++ b/drivers/char/hw_random/Kconfig -@@ -383,6 +383,19 @@ config HW_RANDOM_STM32 - - If unsure, say N. - -+config HW_RANDOM_ROCKCHIP -+ tristate "Rockchip Random Number Generator support" -+ depends on ARCH_ROCKCHIP -+ default HW_RANDOM -+ help -+ This driver provides kernel-side support for the Random Number -+ Generator hardware found on Rockchip cpus. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called rockchip-rng. -+ -+ If unsure, say Y. -+ - config HW_RANDOM_PIC32 - tristate "Microchip PIC32 Random Number Generator support" - depends on MACH_PIC32 || COMPILE_TEST ---- a/drivers/char/hw_random/Makefile -+++ b/drivers/char/hw_random/Makefile -@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += - obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o - obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o - obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o -+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o - obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o - obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o - obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o diff --git a/target/linux/rockchip/patches-6.6/801-02-arm64-dts-rockchip-rk3328-add-rng-node.patch b/target/linux/rockchip/patches-6.6/801-02-arm64-dts-rockchip-rk3328-add-rng-node.patch deleted file mode 100644 index a6f054f0ea..0000000000 --- a/target/linux/rockchip/patches-6.6/801-02-arm64-dts-rockchip-rk3328-add-rng-node.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 2677d71222197dfab25876b013718a14a19c86c1 Mon Sep 17 00:00:00 2001 -From: Lin Jinhan -Date: Tue, 15 Oct 2019 10:12:29 +0800 -Subject: [PATCH] arm64: dts: rockchip: rk3328: add rng node - -Change-Id: Ic443f0e08ac427654008a2225eb9a8565b20fda5 -Signed-off-by: Lin Jinhan ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -287,6 +287,17 @@ - status = "disabled"; - }; - -+ rng: rng@ff060000 { -+ compatible = "rockchip,cryptov1-rng"; -+ reg = <0x0 0xff060000 0x0 0x4000>; -+ -+ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>; -+ clock-names = "clk_crypto", "hclk_crypto"; -+ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>; -+ assigned-clock-rates = <150000000>, <100000000>; -+ status = "disabled"; -+ }; -+ - grf: syscon@ff100000 { - compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff100000 0x0 0x1000>; diff --git a/target/linux/rockchip/patches-6.6/801-03-arm64-dts-rockchip-add-rng-node-for-rk3399.patch b/target/linux/rockchip/patches-6.6/801-03-arm64-dts-rockchip-add-rng-node-for-rk3399.patch deleted file mode 100644 index 05b8f4ca33..0000000000 --- a/target/linux/rockchip/patches-6.6/801-03-arm64-dts-rockchip-add-rng-node-for-rk3399.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 2b80fe5ba53f83c568072a7cdd7478d0b2b7c0fc Mon Sep 17 00:00:00 2001 -From: Lin Jinhan -Date: Sat, 12 Oct 2019 14:57:42 +0800 -Subject: [PATCH] arm64: dts: rockchip: add rng node for rk3399 - -use rng of crypto1 - -Change-Id: Ic8cd339d43012a356d981284726ac4d8158a2316 -Signed-off-by: Lin Jinhan ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -2120,6 +2120,15 @@ - }; - }; - -+ rng: rng@ff8b8000 { -+ compatible = "rockchip,cryptov1-rng"; -+ reg = <0x0 0xff8b8000 0x0 0x1000>; -+ clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; -+ clock-names = "clk_crypto", "hclk_crypto"; -+ assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; -+ assigned-clock-rates = <150000000>, <100000000>; -+ }; -+ - gpu: gpu@ff9a0000 { - compatible = "rockchip,rk3399-mali", "arm,mali-t860"; - reg = <0x0 0xff9a0000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.6/801-04-arm64-dts-rockchip-rk356x-add-rng-node.patch b/target/linux/rockchip/patches-6.6/801-04-arm64-dts-rockchip-rk356x-add-rng-node.patch deleted file mode 100644 index 6303f0b504..0000000000 --- a/target/linux/rockchip/patches-6.6/801-04-arm64-dts-rockchip-rk356x-add-rng-node.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 7d56fae4afef7a73e4973c491e324c7fde60203c Mon Sep 17 00:00:00 2001 -From: Lin Jinhan -Date: Mon, 30 Nov 2020 19:26:29 +0800 -Subject: [PATCH] arm64: dts: rockchip: rk3568: add rng node - -Change-Id: I2654c935554ef278c5805bbc4b5c712a65834925 -Signed-off-by: Lin Jinhan ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -267,6 +267,10 @@ - }; - }; - -+&rng { -+ status = "okay"; -+}; -+ - &usb_host0_xhci { - phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -1128,6 +1128,16 @@ - }; - }; - -+ rng: rng@fe388000 { -+ compatible = "rockchip,cryptov2-rng"; -+ reg = <0x0 0xfe388000 0x0 0x2000>; -+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; -+ clock-names = "clk_trng", "hclk_trng"; -+ resets = <&cru SRST_TRNG_NS>; -+ reset-names = "reset"; -+ status = "disabled"; -+ }; -+ - sdmmc0: mmc@fe2b0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; diff --git a/target/linux/rockchip/patches-6.6/801-05-arm64-dts-rockchip-rk3588s-add-rng-node.patch b/target/linux/rockchip/patches-6.6/801-05-arm64-dts-rockchip-rk3588s-add-rng-node.patch deleted file mode 100644 index a00d5f75f4..0000000000 --- a/target/linux/rockchip/patches-6.6/801-05-arm64-dts-rockchip-rk3588s-add-rng-node.patch +++ /dev/null @@ -1,30 +0,0 @@ -From b56b10f0075e78c72b0ab5bfe9ce64714be48151 Mon Sep 17 00:00:00 2001 -From: Lin Jinhan -Date: Sat, 18 Sep 2021 16:24:23 +0800 -Subject: [PATCH] arm64: dts: rockchip: rk3588s: add rng node - -Signed-off-by: Lin Jinhan -Change-Id: Ifb8964053daa6b593dd2c2c6a3b8caab8526e56d ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1770,6 +1770,16 @@ - status = "disabled"; - }; - -+ rng: rng@fe378000 { -+ compatible = "rockchip,trngv1"; -+ reg = <0x0 0xfe378000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; -+ clock-names = "hclk_trng"; -+ resets = <&scmi_reset SRST_H_TRNG_NS>; -+ reset-names = "reset"; -+ }; -+ - i2s0_8ch: i2s@fe470000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe470000 0x0 0x1000>; diff --git a/target/linux/rockchip/patches-6.6/801-06-hwrng-rockchip-fix-defer-probe.patch b/target/linux/rockchip/patches-6.6/801-06-hwrng-rockchip-fix-defer-probe.patch deleted file mode 100644 index f8f56f21d6..0000000000 --- a/target/linux/rockchip/patches-6.6/801-06-hwrng-rockchip-fix-defer-probe.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 9c44338fcafc666150d2b931decb2239b14cad53 Mon Sep 17 00:00:00 2001 -From: jjm2473 -Date: Mon, 24 Mar 2025 18:57:58 +0800 -Subject: [PATCH] drivers/rockchip-rng: fix -EPROBE_DEFER not propagating - upwards - -kernel should retry probe later ---- - drivers/char/hw_random/rockchip-rng.c | 7 +++---- - 1 file changed, 3 insertions(+), 4 deletions(-) - ---- a/drivers/char/hw_random/rockchip-rng.c -+++ b/drivers/char/hw_random/rockchip-rng.c -@@ -499,10 +499,9 @@ static int rk_rng_probe(struct platform_ - rk_rng->mem += rk_rng->soc_data->default_offset; - - rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks); -- if (rk_rng->clk_num < 0) { -- dev_err(&pdev->dev, "failed to get clks property\n"); -- return -ENODEV; -- } -+ if (rk_rng->clk_num < 0) -+ return dev_err_probe(&pdev->dev, rk_rng->clk_num, -+ "Failed to get clks property\n"); - - platform_set_drvdata(pdev, rk_rng); - diff --git a/target/linux/rockchip/patches-6.6/802-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch b/target/linux/rockchip/patches-6.6/802-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch deleted file mode 100644 index 58d2610919..0000000000 --- a/target/linux/rockchip/patches-6.6/802-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch +++ /dev/null @@ -1,211 +0,0 @@ -From 764e893ee82321938fc6f4349e9e7caf06a04410 Mon Sep 17 00:00:00 2001 -From: Tang Yun ping -Date: Thu, 4 May 2017 20:49:58 +0800 -Subject: [PATCH] clk: rockchip: support setting ddr clock via SIP Version 2 - APIs - -1. Add support setting ddr clock via SIP Version 2 APIs -2. RK3288 using SIP Vision 2. - -Change-Id: I935e43b1885a96650dc86e3eb6d79de6795062a9 -Signed-off-by: Tang Yun ping -Signed-off-by: hmz007 ---- - drivers/clk/rockchip/clk-ddr.c | 159 ++++++++++++++++++++++++++++++ - drivers/clk/rockchip/clk-rk3288.c | 2 +- - drivers/clk/rockchip/clk.h | 1 + - 3 files changed, 161 insertions(+), 1 deletion(-) - ---- a/drivers/clk/rockchip/clk-ddr.c -+++ b/drivers/clk/rockchip/clk-ddr.c -@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddr - .get_parent = rockchip_ddrclk_get_parent, - }; - -+/* See v4.4/include/dt-bindings/display/rk_fb.h */ -+#define SCREEN_NULL 0 -+#define SCREEN_HDMI 6 -+ -+static inline int rk_drm_get_lcdc_type(void) -+{ -+ return SCREEN_NULL; -+} -+ -+struct share_params { -+ u32 hz; -+ u32 lcdc_type; -+ u32 vop; -+ u32 vop_dclk_mode; -+ u32 sr_idle_en; -+ u32 addr_mcu_el3; -+ /* -+ * 1: need to wait flag1 -+ * 0: never wait flag1 -+ */ -+ u32 wait_flag1; -+ /* -+ * 1: need to wait flag1 -+ * 0: never wait flag1 -+ */ -+ u32 wait_flag0; -+ u32 complt_hwirq; -+ /* if need, add parameter after */ -+}; -+ -+struct rockchip_ddrclk_data { -+ u32 inited_flag; -+ void __iomem *share_memory; -+}; -+ -+static struct rockchip_ddrclk_data ddr_data; -+ -+static void rockchip_ddrclk_data_init(void) -+{ -+ struct arm_smccc_res res; -+ -+ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM, -+ 1, SHARE_PAGE_TYPE_DDR, 0, -+ 0, 0, 0, 0, &res); -+ -+ if (!res.a0) { -+ ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12); -+ ddr_data.inited_flag = 1; -+ } -+} -+ -+static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw, -+ unsigned long drate, -+ unsigned long prate) -+{ -+ struct share_params *p; -+ struct arm_smccc_res res; -+ -+ if (!ddr_data.inited_flag) -+ rockchip_ddrclk_data_init(); -+ -+ p = (struct share_params *)ddr_data.share_memory; -+ -+ p->hz = drate; -+ p->lcdc_type = rk_drm_get_lcdc_type(); -+ p->wait_flag1 = 1; -+ p->wait_flag0 = 1; -+ -+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, -+ SHARE_PAGE_TYPE_DDR, 0, -+ ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE, -+ 0, 0, 0, 0, &res); -+ -+ if ((int)res.a1 == -6) { -+ pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000); -+ /* TODO: rockchip_dmcfreq_wait_complete(); */ -+ } -+ -+ return res.a0; -+} -+ -+static unsigned long rockchip_ddrclk_sip_recalc_rate_v2 -+ (struct clk_hw *hw, unsigned long parent_rate) -+{ -+ struct arm_smccc_res res; -+ -+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, -+ SHARE_PAGE_TYPE_DDR, 0, -+ ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE, -+ 0, 0, 0, 0, &res); -+ if (!res.a0) -+ return res.a1; -+ else -+ return 0; -+} -+ -+static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw, -+ unsigned long rate, -+ unsigned long *prate) -+{ -+ struct share_params *p; -+ struct arm_smccc_res res; -+ -+ if (!ddr_data.inited_flag) -+ rockchip_ddrclk_data_init(); -+ -+ p = (struct share_params *)ddr_data.share_memory; -+ -+ p->hz = rate; -+ -+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, -+ SHARE_PAGE_TYPE_DDR, 0, -+ ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE, -+ 0, 0, 0, 0, &res); -+ if (!res.a0) -+ return res.a1; -+ else -+ return 0; -+} -+ -+static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = { -+ .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2, -+ .set_rate = rockchip_ddrclk_sip_set_rate_v2, -+ .round_rate = rockchip_ddrclk_sip_round_rate_v2, -+ .get_parent = rockchip_ddrclk_get_parent, -+}; -+ - struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, - const char *const *parent_names, - u8 num_parents, int mux_offset, -@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk - case ROCKCHIP_DDRCLK_SIP: - init.ops = &rockchip_ddrclk_sip_ops; - break; -+ case ROCKCHIP_DDRCLK_SIP_V2: -+ init.ops = &rockchip_ddrclk_sip_ops_v2; -+ break; - default: - pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag); - kfree(ddrclk); ---- a/drivers/clk/rockchip/clk-rk3328.c -+++ b/drivers/clk/rockchip/clk-rk3328.c -@@ -315,9 +315,10 @@ static struct rockchip_clk_branch rk3328 - RK3328_CLKGATE_CON(14), 1, GFLAGS), - - /* PD_DDR */ -- COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED, -- RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, -- RK3328_CLKGATE_CON(0), 4, GFLAGS), -+ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0, -+ RK3328_CLKSEL_CON(3), 8, 2, 0, 3, -+ ROCKCHIP_DDRCLK_SIP_V2), -+ - GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED, - RK3328_CLKGATE_CON(18), 6, GFLAGS), - GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, ---- a/drivers/clk/rockchip/clk.h -+++ b/drivers/clk/rockchip/clk.h -@@ -487,7 +487,8 @@ struct clk *rockchip_clk_register_mmc(co - * DDRCLK flags, including method of setting the rate - * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. - */ --#define ROCKCHIP_DDRCLK_SIP BIT(0) -+#define ROCKCHIP_DDRCLK_SIP 0x01 -+#define ROCKCHIP_DDRCLK_SIP_V2 0x03 - - struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, - const char *const *parent_names, ---- a/include/soc/rockchip/rockchip_sip.h -+++ b/include/soc/rockchip/rockchip_sip.h -@@ -16,5 +16,16 @@ - #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06 - #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 - #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08 -+#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08 -+ -+#define ROCKCHIP_SIP_SHARE_MEM 0x82000009 -+ -+/* Share mem page types */ -+typedef enum { -+ SHARE_PAGE_TYPE_INVALID = 0, -+ SHARE_PAGE_TYPE_UARTDBG, -+ SHARE_PAGE_TYPE_DDR, -+ SHARE_PAGE_TYPE_MAX, -+} share_page_type_t; - - #endif diff --git a/target/linux/rockchip/patches-6.6/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch b/target/linux/rockchip/patches-6.6/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch deleted file mode 100644 index 895dc8acf3..0000000000 --- a/target/linux/rockchip/patches-6.6/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch +++ /dev/null @@ -1,44 +0,0 @@ -From fcd9629c05f373771e85920e1c1d0ab252617878 Mon Sep 17 00:00:00 2001 -From: hmz007 -Date: Tue, 19 Nov 2019 13:53:25 +0800 -Subject: [PATCH] PM / devfreq: rockchip: add devfreq driver for rk3328 dmc - -Signed-off-by: hmz007 ---- - drivers/devfreq/Kconfig | 18 +- - drivers/devfreq/Makefile | 1 + - drivers/devfreq/rk3328_dmc.c | 846 +++++++++++++++++++++++++++++++++++ - 3 files changed, 862 insertions(+), 3 deletions(-) - create mode 100644 drivers/devfreq/rk3328_dmc.c - ---- a/drivers/devfreq/Kconfig -+++ b/drivers/devfreq/Kconfig -@@ -129,6 +129,18 @@ config ARM_MEDIATEK_CCI_DEVFREQ - buck voltages and update a proper CCI frequency. Use the notification - to get the regulator status. - -+config ARM_RK3328_DMC_DEVFREQ -+ tristate "ARM RK3328 DMC DEVFREQ Driver" -+ depends on ARCH_ROCKCHIP -+ select DEVFREQ_EVENT_ROCKCHIP_DFI -+ select DEVFREQ_GOV_SIMPLE_ONDEMAND -+ select PM_DEVFREQ_EVENT -+ select PM_OPP -+ help -+ This adds the DEVFREQ driver for the RK3328 DMC(Dynamic Memory Controller). -+ It sets the frequency for the memory controller and reads the usage counts -+ from hardware. -+ - config ARM_RK3399_DMC_DEVFREQ - tristate "ARM RK3399 DMC DEVFREQ Driver" - depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \ ---- a/drivers/devfreq/Makefile -+++ b/drivers/devfreq/Makefile -@@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx - obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o - obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o - obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o -+obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ) += rk3328_dmc.o - obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o - obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o - diff --git a/target/linux/rockchip/patches-6.6/804-01-PM-devfreq-rockchip-dfi-disable-irqs-during-accessing-ddr.patch b/target/linux/rockchip/patches-6.6/804-01-PM-devfreq-rockchip-dfi-disable-irqs-during-accessing-ddr.patch deleted file mode 100644 index 08085841ca..0000000000 --- a/target/linux/rockchip/patches-6.6/804-01-PM-devfreq-rockchip-dfi-disable-irqs-during-accessing-ddr.patch +++ /dev/null @@ -1,26 +0,0 @@ -From d85e70122d0357ce714aace7ad23d9ae40dce587 Mon Sep 17 00:00:00 2001 -From: Jianqun Xu -Date: Fri, 19 Aug 2016 15:44:14 +0800 -Subject: [PATCH] PM / devfreq: rockchip-dfi: disable irqs during accessing ddr - monitor - -Change-Id: Ie4817a77fcb1283f37f41ab097f02ed7dc9cd18c -Signed-off-by: Jianqun Xu ---- - drivers/devfreq/event/rockchip-dfi.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -151,8 +151,11 @@ static int rockchip_dfi_get_event(struct - { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); - int busier_ch; -+ unsigned long flags; - -+ local_irq_save(flags); - busier_ch = rockchip_dfi_get_busier_ch(edev); -+ local_irq_restore(flags); - - edata->load_count = info->ch_usage[busier_ch].access; - edata->total_count = info->ch_usage[busier_ch].total; diff --git a/target/linux/rockchip/patches-6.6/804-02-PM-devfreq-event-add-support-for-rk3368-dfi.patch b/target/linux/rockchip/patches-6.6/804-02-PM-devfreq-event-add-support-for-rk3368-dfi.patch deleted file mode 100644 index e1bbf285f6..0000000000 --- a/target/linux/rockchip/patches-6.6/804-02-PM-devfreq-event-add-support-for-rk3368-dfi.patch +++ /dev/null @@ -1,241 +0,0 @@ -From b495cbf3597ca0799c35c8bb4a12b8e70b911820 Mon Sep 17 00:00:00 2001 -From: Finley Xiao -Date: Mon, 27 Mar 2017 11:09:51 +0800 -Subject: [PATCH] PM / devfreq: event: add support for rk3368 dfi - -This adds the necessary data for handling dfi on the rk3368. -Access the dfi via registers provided by GRF (general register -files) module. - -Change-Id: I96c2b4dcd34d90731b749ebdbe6922f01559d8e6 -Signed-off-by: Finley Xiao ---- - .../bindings/devfreq/event/rockchip-dfi.txt | 11 +- - drivers/devfreq/event/rockchip-dfi.c | 157 ++++++++++++++++-- - 2 files changed, 148 insertions(+), 20 deletions(-) - ---- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt -+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt -@@ -1,8 +1,15 @@ - --* Rockchip rk3399 DFI device -+* Rockchip DFI device - - Required properties: --- compatible: Must be "rockchip,rk3399-dfi". -+- compatible: Should be one of the following. -+ - "rockchip,rk3368-dfi" - for RK3368 SoCs. -+ - "rockchip,rk3399-dfi" - for RK3399 SoCs. -+ -+Required properties for RK3368: -+- rockchip,grf: phandle to the syscon managing the "general register files" -+ -+Required properties for RK3399: - - reg: physical base address of each DFI and length of memory mapped region - - rockchip,pmu: phandle to the syscon managing the "pmu general register files" - - clocks: phandles for clock specified in "clock-names" property ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -20,6 +20,15 @@ - - #include - -+#define RK3368_GRF_DDRC0_CON0 0x600 -+#define RK3368_GRF_SOC_STATUS5 0x494 -+#define RK3368_GRF_SOC_STATUS6 0x498 -+#define RK3368_GRF_SOC_STATUS8 0x4a0 -+#define RK3368_GRF_SOC_STATUS9 0x4a4 -+#define RK3368_GRF_SOC_STATUS10 0x4a8 -+#define RK3368_DFI_EN (0x30003 << 5) -+#define RK3368_DFI_DIS (0x30000 << 5) -+ - #define RK3399_DMC_NUM_CH 2 - - /* DDRMON_CTRL */ -@@ -54,9 +63,77 @@ struct rockchip_dfi { - struct device *dev; - void __iomem *regs; - struct regmap *regmap_pmu; -+ struct regmap *regmap_grf; - struct clk *clk; - }; - -+static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev) -+{ -+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -+ -+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN); -+} -+ -+static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) -+{ -+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -+ -+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS); -+} -+ -+static int rk3368_dfi_disable(struct devfreq_event_dev *edev) -+{ -+ rk3368_dfi_stop_hardware_counter(edev); -+ -+ return 0; -+} -+ -+static int rk3368_dfi_enable(struct devfreq_event_dev *edev) -+{ -+ rk3368_dfi_start_hardware_counter(edev); -+ -+ return 0; -+} -+ -+static int rk3368_dfi_set_event(struct devfreq_event_dev *edev) -+{ -+ return 0; -+} -+ -+static int rk3368_dfi_get_event(struct devfreq_event_dev *edev, -+ struct devfreq_event_data *edata) -+{ -+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -+ unsigned long flags; -+ u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer; -+ -+ local_irq_save(flags); -+ -+ rk3368_dfi_stop_hardware_counter(edev); -+ -+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr); -+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd); -+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr); -+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd); -+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer); -+ -+ edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2; -+ edata->total_count = dfi_timer; -+ -+ rk3368_dfi_start_hardware_counter(edev); -+ -+ local_irq_restore(flags); -+ -+ return 0; -+} -+ -+static const struct devfreq_event_ops rk3368_dfi_ops = { -+ .disable = rk3368_dfi_disable, -+ .enable = rk3368_dfi_enable, -+ .get_event = rk3368_dfi_get_event, -+ .set_event = rk3368_dfi_set_event, -+}; -+ - static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) - { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -@@ -170,23 +247,31 @@ static const struct devfreq_event_ops ro - .set_event = rockchip_dfi_set_event, - }; - --static const struct of_device_id rockchip_dfi_id_match[] = { -- { .compatible = "rockchip,rk3399-dfi" }, -- { }, --}; --MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match); -+static __init int rk3368_dfi_init(struct platform_device *pdev, -+ struct rockchip_dfi *data, -+ struct devfreq_event_desc *desc) -+{ -+ struct device *dev = &pdev->dev; - --static int rockchip_dfi_probe(struct platform_device *pdev) -+ if (!dev->parent || !dev->parent->of_node) -+ return -EINVAL; -+ -+ data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node); -+ if (IS_ERR(data->regmap_grf)) -+ return PTR_ERR(data->regmap_grf); -+ -+ desc->ops = &rk3368_dfi_ops; -+ -+ return 0; -+} -+ -+static __init int rockchip_dfi_init(struct platform_device *pdev, -+ struct rockchip_dfi *data, -+ struct devfreq_event_desc *desc) - { - struct device *dev = &pdev->dev; -- struct rockchip_dfi *data; -- struct devfreq_event_desc *desc; - struct device_node *np = pdev->dev.of_node, *node; - -- data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL); -- if (!data) -- return -ENOMEM; -- - data->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(data->regs)) - return PTR_ERR(data->regs); -@@ -205,23 +290,58 @@ static int rockchip_dfi_probe(struct pla - if (IS_ERR(data->regmap_pmu)) - return PTR_ERR(data->regmap_pmu); - -- data->dev = dev; -+ desc->ops = &rockchip_dfi_ops; -+ -+ return 0; -+} -+ -+static const struct of_device_id rockchip_dfi_id_match[] = { -+ { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init }, -+ { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init }, -+ { }, -+}; -+ -+static int rockchip_dfi_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct rockchip_dfi *data; -+ struct devfreq_event_desc *desc; -+ struct device_node *np = pdev->dev.of_node; -+ const struct of_device_id *match; -+ int (*init)(struct platform_device *pdev, struct rockchip_dfi *data, -+ struct devfreq_event_desc *desc); -+ -+ data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL); -+ if (!data) -+ return -ENOMEM; - - desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); - if (!desc) - return -ENOMEM; - -- desc->ops = &rockchip_dfi_ops; -+ match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node); -+ if (match) { -+ init = match->data; -+ if (init) { -+ if (init(pdev, data, desc)) -+ return -EINVAL; -+ } else { -+ return 0; -+ } -+ } else { -+ return 0; -+ } -+ - desc->driver_data = data; - desc->name = np->name; -- data->desc = desc; - -- data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc); -+ data->edev = devm_devfreq_event_add_edev(dev, desc); - if (IS_ERR(data->edev)) { -- dev_err(&pdev->dev, -- "failed to add devfreq-event device\n"); -+ dev_err(dev, "failed to add devfreq-event device\n"); - return PTR_ERR(data->edev); - } -+ data->desc = desc; -+ data->dev = &pdev->dev; - - platform_set_drvdata(pdev, data); - diff --git a/target/linux/rockchip/patches-6.6/804-03-PM-devfreq-event-add-support-for-rk3288-dfi.patch b/target/linux/rockchip/patches-6.6/804-03-PM-devfreq-event-add-support-for-rk3288-dfi.patch deleted file mode 100644 index 2f52d6b4e3..0000000000 --- a/target/linux/rockchip/patches-6.6/804-03-PM-devfreq-event-add-support-for-rk3288-dfi.patch +++ /dev/null @@ -1,229 +0,0 @@ -From 0519cdf40c8cd04663e2eba614d57f11f002b88f Mon Sep 17 00:00:00 2001 -From: Tang Yun ping -Date: Wed, 12 Apr 2017 16:24:16 +0800 -Subject: [PATCH] PM / devfreq: event: add support for rk3288 dfi - -This adds the necessary data for handling dfi on the rk3288. -Access the dfi via registers provided by GRF (general register -files) module. - -Change-Id: Ic7241af3c20a269ab362055dea04d260e01c50de -Signed-off-by: Tang Yun ping ---- - .../bindings/devfreq/event/rockchip-dfi.txt | 1 + - drivers/devfreq/event/rockchip-dfi.c | 158 +++++++++++++++++- - 2 files changed, 150 insertions(+), 9 deletions(-) - ---- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt -+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt -@@ -3,6 +3,7 @@ - - Required properties: - - compatible: Should be one of the following. -+ - "rockchip,rk3288-dfi" - for RK3288 SoCs. - - "rockchip,rk3368-dfi" - for RK3368 SoCs. - - "rockchip,rk3399-dfi" - for RK3399 SoCs. - ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -20,6 +20,15 @@ - - #include - -+#define RK3288_PMU_SYS_REG2 0x9c -+#define RK3288_GRF_SOC_CON4 0x254 -+#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4) -+#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7) -+#define RK3288_DFI_EN (0x30003 << 14) -+#define RK3288_DFI_DIS (0x30000 << 14) -+#define RK3288_LPDDR_SEL (0x10001 << 13) -+#define RK3288_DDR3_SEL (0x10000 << 13) -+ - #define RK3368_GRF_DDRC0_CON0 0x600 - #define RK3368_GRF_SOC_STATUS5 0x494 - #define RK3368_GRF_SOC_STATUS6 0x498 -@@ -29,23 +38,30 @@ - #define RK3368_DFI_EN (0x30003 << 5) - #define RK3368_DFI_DIS (0x30000 << 5) - --#define RK3399_DMC_NUM_CH 2 -+#define RK3399_DMC_NUM_CH 2 - - /* DDRMON_CTRL */ --#define DDRMON_CTRL 0x04 --#define CLR_DDRMON_CTRL (0x1f0000 << 0) --#define LPDDR4_EN (0x10001 << 4) --#define HARDWARE_EN (0x10001 << 3) --#define LPDDR3_EN (0x10001 << 2) --#define SOFTWARE_EN (0x10001 << 1) --#define SOFTWARE_DIS (0x10000 << 1) --#define TIME_CNT_EN (0x10001 << 0) -+#define DDRMON_CTRL 0x04 -+#define CLR_DDRMON_CTRL (0x1f0000 << 0) -+#define LPDDR4_EN (0x10001 << 4) -+#define HARDWARE_EN (0x10001 << 3) -+#define LPDDR3_EN (0x10001 << 2) -+#define SOFTWARE_EN (0x10001 << 1) -+#define SOFTWARE_DIS (0x10000 << 1) -+#define TIME_CNT_EN (0x10001 << 0) - - #define DDRMON_CH0_COUNT_NUM 0x28 - #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c - #define DDRMON_CH1_COUNT_NUM 0x3c - #define DDRMON_CH1_DFI_ACCESS_NUM 0x40 - -+enum { -+ DDR3 = 3, -+ LPDDR3 = 6, -+ LPDDR4 = 7, -+ UNUSED = 0xFF -+}; -+ - struct dmc_usage { - u32 access; - u32 total; -@@ -67,6 +83,93 @@ struct rockchip_dfi { - struct clk *clk; - }; - -+static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev) -+{ -+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -+ -+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN); -+} -+ -+static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) -+{ -+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -+ -+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS); -+} -+ -+static int rk3288_dfi_disable(struct devfreq_event_dev *edev) -+{ -+ rk3288_dfi_stop_hardware_counter(edev); -+ -+ return 0; -+} -+ -+static int rk3288_dfi_enable(struct devfreq_event_dev *edev) -+{ -+ rk3288_dfi_start_hardware_counter(edev); -+ -+ return 0; -+} -+ -+static int rk3288_dfi_set_event(struct devfreq_event_dev *edev) -+{ -+ return 0; -+} -+ -+static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev) -+{ -+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -+ u32 tmp, max = 0; -+ u32 i, busier_ch = 0; -+ u32 rd_count, wr_count, total_count; -+ -+ rk3288_dfi_stop_hardware_counter(edev); -+ -+ /* Find out which channel is busier */ -+ for (i = 0; i < RK3399_DMC_NUM_CH; i++) { -+ regmap_read(info->regmap_grf, -+ RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count); -+ regmap_read(info->regmap_grf, -+ RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count); -+ regmap_read(info->regmap_grf, -+ RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count); -+ info->ch_usage[i].access = (wr_count + rd_count) * 4; -+ info->ch_usage[i].total = total_count; -+ tmp = info->ch_usage[i].access; -+ if (tmp > max) { -+ busier_ch = i; -+ max = tmp; -+ } -+ } -+ rk3288_dfi_start_hardware_counter(edev); -+ -+ return busier_ch; -+} -+ -+static int rk3288_dfi_get_event(struct devfreq_event_dev *edev, -+ struct devfreq_event_data *edata) -+{ -+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -+ int busier_ch; -+ unsigned long flags; -+ -+ local_irq_save(flags); -+ busier_ch = rk3288_dfi_get_busier_ch(edev); -+ local_irq_restore(flags); -+ -+ edata->load_count = info->ch_usage[busier_ch].access; -+ edata->total_count = info->ch_usage[busier_ch].total; -+ -+ return 0; -+} -+ -+static const struct devfreq_event_ops rk3288_dfi_ops = { -+ .disable = rk3288_dfi_disable, -+ .enable = rk3288_dfi_enable, -+ .get_event = rk3288_dfi_get_event, -+ .set_event = rk3288_dfi_set_event, -+}; -+ - static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev) - { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -@@ -247,6 +350,42 @@ static const struct devfreq_event_ops ro - .set_event = rockchip_dfi_set_event, - }; - -+static __init int rk3288_dfi_init(struct platform_device *pdev, -+ struct rockchip_dfi *data, -+ struct devfreq_event_desc *desc) -+{ -+ struct device_node *np = pdev->dev.of_node, *node; -+ u32 dram_type; -+ -+ node = of_parse_phandle(np, "rockchip,pmu", 0); -+ if (node) { -+ data->regmap_pmu = syscon_node_to_regmap(node); -+ if (IS_ERR(data->regmap_pmu)) -+ return PTR_ERR(data->regmap_pmu); -+ } -+ -+ node = of_parse_phandle(np, "rockchip,grf", 0); -+ if (node) { -+ data->regmap_grf = syscon_node_to_regmap(node); -+ if (IS_ERR(data->regmap_grf)) -+ return PTR_ERR(data->regmap_grf); -+ } -+ -+ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &dram_type); -+ dram_type = READ_DRAMTYPE_INFO(dram_type); -+ -+ if (dram_type == DDR3) -+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4, -+ RK3288_DDR3_SEL); -+ else -+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4, -+ RK3288_LPDDR_SEL); -+ -+ desc->ops = &rk3288_dfi_ops; -+ -+ return 0; -+} -+ - static __init int rk3368_dfi_init(struct platform_device *pdev, - struct rockchip_dfi *data, - struct devfreq_event_desc *desc) -@@ -296,6 +435,7 @@ static __init int rockchip_dfi_init(stru - } - - static const struct of_device_id rockchip_dfi_id_match[] = { -+ { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init }, - { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init }, - { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init }, - { }, diff --git a/target/linux/rockchip/patches-6.6/804-04-PM-devfreq-event-add-support-for-rk3128-dfi.patch b/target/linux/rockchip/patches-6.6/804-04-PM-devfreq-event-add-support-for-rk3128-dfi.patch deleted file mode 100644 index af7c3070fc..0000000000 --- a/target/linux/rockchip/patches-6.6/804-04-PM-devfreq-event-add-support-for-rk3128-dfi.patch +++ /dev/null @@ -1,152 +0,0 @@ -From 7d494650c32b81e22b0268b1209118ea11253a97 Mon Sep 17 00:00:00 2001 -From: Liang Chen -Date: Tue, 5 Sep 2017 15:32:02 +0800 -Subject: [PATCH] PM / devfreq: event: add support for rk3128 dfi - -This adds the necessary data for handling dfi on the rk3128. -Access the dfi via registers provided by GRF (general register -files) module. - -Change-Id: Ife9e9987224088434e878102b7d1c3b132e761ad -Signed-off-by: Liang Chen ---- - .../bindings/devfreq/event/rockchip-dfi.txt | 1 + - drivers/devfreq/event/rockchip-dfi.c | 96 +++++++++++++++++++ - 2 files changed, 97 insertions(+) - ---- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt -+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt -@@ -3,6 +3,7 @@ - - Required properties: - - compatible: Should be one of the following. -+ - "rockchip,rk3128-dfi" - for RK3128 SoCs. - - "rockchip,rk3288-dfi" - for RK3288 SoCs. - - "rockchip,rk3368-dfi" - for RK3368 SoCs. - - "rockchip,rk3399-dfi" - for RK3399 SoCs. ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -20,6 +20,14 @@ - - #include - -+#define RK3128_GRF_SOC_CON0 0x140 -+#define RK3128_GRF_OS_REG1 0x1cc -+#define RK3128_GRF_DFI_WRNUM 0x220 -+#define RK3128_GRF_DFI_RDNUM 0x224 -+#define RK3128_GRF_DFI_TIMERVAL 0x22c -+#define RK3128_DDR_MONITOR_EN ((1 << (16 + 6)) + (1 << 6)) -+#define RK3128_DDR_MONITOR_DISB ((1 << (16 + 6)) + (0 << 6)) -+ - #define RK3288_PMU_SYS_REG2 0x9c - #define RK3288_GRF_SOC_CON4 0x254 - #define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4) -@@ -83,6 +91,75 @@ struct rockchip_dfi { - struct clk *clk; - }; - -+static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev) -+{ -+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -+ -+ regmap_write(info->regmap_grf, -+ RK3128_GRF_SOC_CON0, -+ RK3128_DDR_MONITOR_EN); -+} -+ -+static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) -+{ -+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -+ -+ regmap_write(info->regmap_grf, -+ RK3128_GRF_SOC_CON0, -+ RK3128_DDR_MONITOR_DISB); -+} -+ -+static int rk3128_dfi_disable(struct devfreq_event_dev *edev) -+{ -+ rk3128_dfi_stop_hardware_counter(edev); -+ -+ return 0; -+} -+ -+static int rk3128_dfi_enable(struct devfreq_event_dev *edev) -+{ -+ rk3128_dfi_start_hardware_counter(edev); -+ -+ return 0; -+} -+ -+static int rk3128_dfi_set_event(struct devfreq_event_dev *edev) -+{ -+ return 0; -+} -+ -+static int rk3128_dfi_get_event(struct devfreq_event_dev *edev, -+ struct devfreq_event_data *edata) -+{ -+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -+ unsigned long flags; -+ u32 dfi_wr, dfi_rd, dfi_timer; -+ -+ local_irq_save(flags); -+ -+ rk3128_dfi_stop_hardware_counter(edev); -+ -+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr); -+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd); -+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer); -+ -+ edata->load_count = (dfi_wr + dfi_rd) * 4; -+ edata->total_count = dfi_timer; -+ -+ rk3128_dfi_start_hardware_counter(edev); -+ -+ local_irq_restore(flags); -+ -+ return 0; -+} -+ -+static const struct devfreq_event_ops rk3128_dfi_ops = { -+ .disable = rk3128_dfi_disable, -+ .enable = rk3128_dfi_enable, -+ .get_event = rk3128_dfi_get_event, -+ .set_event = rk3128_dfi_set_event, -+}; -+ - static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev) - { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); -@@ -350,6 +427,24 @@ static const struct devfreq_event_ops ro - .set_event = rockchip_dfi_set_event, - }; - -+static __init int rk3128_dfi_init(struct platform_device *pdev, -+ struct rockchip_dfi *data, -+ struct devfreq_event_desc *desc) -+{ -+ struct device_node *np = pdev->dev.of_node, *node; -+ -+ node = of_parse_phandle(np, "rockchip,grf", 0); -+ if (node) { -+ data->regmap_grf = syscon_node_to_regmap(node); -+ if (IS_ERR(data->regmap_grf)) -+ return PTR_ERR(data->regmap_grf); -+ } -+ -+ desc->ops = &rk3128_dfi_ops; -+ -+ return 0; -+} -+ - static __init int rk3288_dfi_init(struct platform_device *pdev, - struct rockchip_dfi *data, - struct devfreq_event_desc *desc) -@@ -435,6 +530,7 @@ static __init int rockchip_dfi_init(stru - } - - static const struct of_device_id rockchip_dfi_id_match[] = { -+ { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init }, - { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init }, - { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init }, - { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init }, diff --git a/target/linux/rockchip/patches-6.6/804-05-PM-devfreq-event-make-dfi-more-extension.patch b/target/linux/rockchip/patches-6.6/804-05-PM-devfreq-event-make-dfi-more-extension.patch deleted file mode 100644 index a07e8f8db3..0000000000 --- a/target/linux/rockchip/patches-6.6/804-05-PM-devfreq-event-make-dfi-more-extension.patch +++ /dev/null @@ -1,184 +0,0 @@ -From 0873229b2495f356d84a0182e50c5ea27ae46816 Mon Sep 17 00:00:00 2001 -From: CanYang He -Date: Sat, 23 Dec 2017 14:51:38 +0800 -Subject: [PATCH] PM / devfreq: event: make dfi more extension - -after modify, rockchip_dfi_ops can apply to other platform use such -version ddr monitor. regardless of channel count, only one channel -of rk3288,rk3399,rk3328 can work. and regardless of monitor clk, -some platform like rk3328 monitor clk is always on. - -Change-Id: Ia1c02a89116546ded385c5a6a3e36d020d66b7f3 -Signed-off-by: CanYang He ---- - drivers/devfreq/event/rockchip-dfi.c | 63 ++++++++++++++++++---------- - 1 file changed, 40 insertions(+), 23 deletions(-) - ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -31,7 +31,6 @@ - #define RK3288_PMU_SYS_REG2 0x9c - #define RK3288_GRF_SOC_CON4 0x254 - #define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4) --#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7) - #define RK3288_DFI_EN (0x30003 << 14) - #define RK3288_DFI_DIS (0x30000 << 14) - #define RK3288_LPDDR_SEL (0x10001 << 13) -@@ -46,7 +45,9 @@ - #define RK3368_DFI_EN (0x30003 << 5) - #define RK3368_DFI_DIS (0x30000 << 5) - --#define RK3399_DMC_NUM_CH 2 -+#define MAX_DMC_NUM_CH 2 -+#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7) -+#define READ_CH_INFO(n) (((n) >> 28) & 0x3) - - /* DDRMON_CTRL */ - #define DDRMON_CTRL 0x04 -@@ -63,6 +64,9 @@ - #define DDRMON_CH1_COUNT_NUM 0x3c - #define DDRMON_CH1_DFI_ACCESS_NUM 0x40 - -+/* pmu grf */ -+#define PMUGRF_OS_REG2 0x308 -+ - enum { - DDR3 = 3, - LPDDR3 = 6, -@@ -83,12 +87,18 @@ struct dmc_usage { - struct rockchip_dfi { - struct devfreq_event_dev *edev; - struct devfreq_event_desc *desc; -- struct dmc_usage ch_usage[RK3399_DMC_NUM_CH]; -+ struct dmc_usage ch_usage[MAX_DMC_NUM_CH]; - struct device *dev; - void __iomem *regs; - struct regmap *regmap_pmu; - struct regmap *regmap_grf; - struct clk *clk; -+ u32 dram_type; -+ /* -+ * available mask, 1: available, 0: not available -+ * each bit represent a channel -+ */ -+ u32 ch_msk; - }; - - static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev) -@@ -203,7 +213,9 @@ static int rk3288_dfi_get_busier_ch(stru - rk3288_dfi_stop_hardware_counter(edev); - - /* Find out which channel is busier */ -- for (i = 0; i < RK3399_DMC_NUM_CH; i++) { -+ for (i = 0; i < MAX_DMC_NUM_CH; i++) { -+ if (!(info->ch_msk & BIT(i))) -+ continue; - regmap_read(info->regmap_grf, - RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count); - regmap_read(info->regmap_grf, -@@ -318,21 +330,14 @@ static void rockchip_dfi_start_hardware_ - { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); - void __iomem *dfi_regs = info->regs; -- u32 val; -- u32 ddr_type; -- -- /* get ddr type */ -- regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); -- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & -- RK3399_PMUGRF_DDRTYPE_MASK; - - /* clear DDRMON_CTRL setting */ - writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); - - /* set ddr type to dfi */ -- if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3) -+ if (info->dram_type == LPDDR3) - writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); -- else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4) -+ else if (info->dram_type == LPDDR4) - writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); - - /* enable count, use software mode */ -@@ -357,7 +362,9 @@ static int rockchip_dfi_get_busier_ch(st - rockchip_dfi_stop_hardware_counter(edev); - - /* Find out which channel is busier */ -- for (i = 0; i < RK3399_DMC_NUM_CH; i++) { -+ for (i = 0; i < MAX_DMC_NUM_CH; i++) { -+ if (!(info->ch_msk & BIT(i))) -+ continue; - info->ch_usage[i].access = readl_relaxed(dfi_regs + - DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4; - info->ch_usage[i].total = readl_relaxed(dfi_regs + -@@ -378,7 +385,8 @@ static int rockchip_dfi_disable(struct d - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); - - rockchip_dfi_stop_hardware_counter(edev); -- clk_disable_unprepare(info->clk); -+ if (info->clk) -+ clk_disable_unprepare(info->clk); - - return 0; - } -@@ -388,10 +396,13 @@ static int rockchip_dfi_enable(struct de - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); - int ret; - -- ret = clk_prepare_enable(info->clk); -- if (ret) { -- dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret); -- return ret; -+ if (info->clk) { -+ ret = clk_prepare_enable(info->clk); -+ if (ret) { -+ dev_err(&edev->dev, "failed to enable dfi clk: %d\n", -+ ret); -+ return ret; -+ } - } - - rockchip_dfi_start_hardware_counter(edev); -@@ -450,7 +461,7 @@ static __init int rk3288_dfi_init(struct - struct devfreq_event_desc *desc) - { - struct device_node *np = pdev->dev.of_node, *node; -- u32 dram_type; -+ u32 val; - - node = of_parse_phandle(np, "rockchip,pmu", 0); - if (node) { -@@ -466,10 +477,11 @@ static __init int rk3288_dfi_init(struct - return PTR_ERR(data->regmap_grf); - } - -- regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &dram_type); -- dram_type = READ_DRAMTYPE_INFO(dram_type); -+ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val); -+ data->dram_type = READ_DRAMTYPE_INFO(val); -+ data->ch_msk = READ_CH_INFO(val); - -- if (dram_type == DDR3) -+ if (data->dram_type == DDR3) - regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4, - RK3288_DDR3_SEL); - else -@@ -505,6 +517,7 @@ static __init int rockchip_dfi_init(stru - { - struct device *dev = &pdev->dev; - struct device_node *np = pdev->dev.of_node, *node; -+ u32 val; - - data->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(data->regs)) -@@ -524,6 +537,10 @@ static __init int rockchip_dfi_init(stru - if (IS_ERR(data->regmap_pmu)) - return PTR_ERR(data->regmap_pmu); - -+ regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val); -+ data->dram_type = READ_DRAMTYPE_INFO(val); -+ data->ch_msk = READ_CH_INFO(val); -+ - desc->ops = &rockchip_dfi_ops; - - return 0; diff --git a/target/linux/rockchip/patches-6.6/804-06-PM-devfreq-event-add-support-for-rk3328-dfi.patch b/target/linux/rockchip/patches-6.6/804-06-PM-devfreq-event-add-support-for-rk3328-dfi.patch deleted file mode 100644 index 7f08e2729c..0000000000 --- a/target/linux/rockchip/patches-6.6/804-06-PM-devfreq-event-add-support-for-rk3328-dfi.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 8d4209ee0613dfea700bcfc2ecb6052dc9dc9956 Mon Sep 17 00:00:00 2001 -From: CanYang He -Date: Tue, 26 Dec 2017 10:19:46 +0800 -Subject: [PATCH] PM / devfreq: event: add support for rk3328 dfi - -This adds the necessary data for handling dfi on the rk3328. - -Change-Id: Id870f78dad3ddd6cb5771674a4e8905322f9e8ef -Signed-off-by: CanYang He ---- - .../bindings/devfreq/event/rockchip-dfi.txt | 1 + - drivers/devfreq/event/rockchip-dfi.c | 40 ++++++++++++++++++- - 2 files changed, 39 insertions(+), 2 deletions(-) - ---- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt -+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt -@@ -5,6 +5,7 @@ Required properties: - - compatible: Should be one of the following. - - "rockchip,rk3128-dfi" - for RK3128 SoCs. - - "rockchip,rk3288-dfi" - for RK3288 SoCs. -+ - "rockchip,rk3328-dfi" - for RK3328 SoCs. - - "rockchip,rk3368-dfi" - for RK3368 SoCs. - - "rockchip,rk3399-dfi" - for RK3399 SoCs. - ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -36,6 +36,8 @@ - #define RK3288_LPDDR_SEL (0x10001 << 13) - #define RK3288_DDR3_SEL (0x10000 << 13) - -+#define RK3328_GRF_OS_REG2 0x5d0 -+ - #define RK3368_GRF_DDRC0_CON0 0x600 - #define RK3368_GRF_SOC_STATUS5 0x494 - #define RK3368_GRF_SOC_STATUS6 0x498 -@@ -48,10 +50,10 @@ - #define MAX_DMC_NUM_CH 2 - #define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7) - #define READ_CH_INFO(n) (((n) >> 28) & 0x3) -- - /* DDRMON_CTRL */ - #define DDRMON_CTRL 0x04 --#define CLR_DDRMON_CTRL (0x1f0000 << 0) -+#define CLR_DDRMON_CTRL (0x3f0000 << 0) -+#define DDR4_EN (0x10001 << 5) - #define LPDDR4_EN (0x10001 << 4) - #define HARDWARE_EN (0x10001 << 3) - #define LPDDR3_EN (0x10001 << 2) -@@ -68,6 +70,7 @@ - #define PMUGRF_OS_REG2 0x308 - - enum { -+ DDR4 = 0, - DDR3 = 3, - LPDDR3 = 6, - LPDDR4 = 7, -@@ -339,6 +342,8 @@ static void rockchip_dfi_start_hardware_ - writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); - else if (info->dram_type == LPDDR4) - writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); -+ else if (info->dram_type == DDR4) -+ writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL); - - /* enable count, use software mode */ - writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL); -@@ -546,9 +551,40 @@ static __init int rockchip_dfi_init(stru - return 0; - } - -+static __init int rk3328_dfi_init(struct platform_device *pdev, -+ struct rockchip_dfi *data, -+ struct devfreq_event_desc *desc) -+{ -+ struct device_node *np = pdev->dev.of_node, *node; -+ struct resource *res; -+ u32 val; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ data->regs = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(data->regs)) -+ return PTR_ERR(data->regs); -+ -+ node = of_parse_phandle(np, "rockchip,grf", 0); -+ if (node) { -+ data->regmap_grf = syscon_node_to_regmap(node); -+ if (IS_ERR(data->regmap_grf)) -+ return PTR_ERR(data->regmap_grf); -+ } -+ -+ regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val); -+ data->dram_type = READ_DRAMTYPE_INFO(val); -+ data->ch_msk = 1; -+ data->clk = NULL; -+ -+ desc->ops = &rockchip_dfi_ops; -+ -+ return 0; -+} -+ - static const struct of_device_id rockchip_dfi_id_match[] = { - { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init }, - { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init }, -+ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init }, - { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init }, - { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init }, - { }, diff --git a/target/linux/rockchip/patches-6.6/804-07-PM-devfreq-event-add-support-for-px30-dfi.patch b/target/linux/rockchip/patches-6.6/804-07-PM-devfreq-event-add-support-for-px30-dfi.patch deleted file mode 100644 index 267dc0a642..0000000000 --- a/target/linux/rockchip/patches-6.6/804-07-PM-devfreq-event-add-support-for-px30-dfi.patch +++ /dev/null @@ -1,114 +0,0 @@ -From eefc791ec8040d6cacf3e940d778b7fc82c5e99e Mon Sep 17 00:00:00 2001 -From: YouMin Chen -Date: Mon, 5 Feb 2018 10:57:23 +0800 -Subject: [PATCH] PM / devfreq: event: add support for px30 dfi - -Change-Id: Ib6808d961b65d993fea05ab15d648d814d14a4a2 -Signed-off-by: YouMin Chen ---- - .../bindings/devfreq/event/rockchip-dfi.txt | 1 + - drivers/devfreq/event/rockchip-dfi.c | 41 +++++++++++++++++-- - 2 files changed, 39 insertions(+), 3 deletions(-) - ---- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt -+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt -@@ -3,6 +3,7 @@ - - Required properties: - - compatible: Should be one of the following. -+ - "rockchip,px30-dfi" - for PX30 SoCs. - - "rockchip,rk3128-dfi" - for RK3128 SoCs. - - "rockchip,rk3288-dfi" - for RK3288 SoCs. - - "rockchip,rk3328-dfi" - for RK3328 SoCs. ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -20,6 +20,8 @@ - - #include - -+#define PX30_PMUGRF_OS_REG2 0x208 -+ - #define RK3128_GRF_SOC_CON0 0x140 - #define RK3128_GRF_OS_REG1 0x1cc - #define RK3128_GRF_DFI_WRNUM 0x220 -@@ -56,7 +58,7 @@ - #define DDR4_EN (0x10001 << 5) - #define LPDDR4_EN (0x10001 << 4) - #define HARDWARE_EN (0x10001 << 3) --#define LPDDR3_EN (0x10001 << 2) -+#define LPDDR2_3_EN (0x10001 << 2) - #define SOFTWARE_EN (0x10001 << 1) - #define SOFTWARE_DIS (0x10000 << 1) - #define TIME_CNT_EN (0x10001 << 0) -@@ -72,6 +74,7 @@ - enum { - DDR4 = 0, - DDR3 = 3, -+ LPDDR2 = 5, - LPDDR3 = 6, - LPDDR4 = 7, - UNUSED = 0xFF -@@ -95,6 +98,7 @@ struct rockchip_dfi { - void __iomem *regs; - struct regmap *regmap_pmu; - struct regmap *regmap_grf; -+ struct regmap *regmap_pmugrf; - struct clk *clk; - u32 dram_type; - /* -@@ -338,8 +342,8 @@ static void rockchip_dfi_start_hardware_ - writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); - - /* set ddr type to dfi */ -- if (info->dram_type == LPDDR3) -- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); -+ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2) -+ writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL); - else if (info->dram_type == LPDDR4) - writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); - else if (info->dram_type == DDR4) -@@ -443,6 +447,36 @@ static const struct devfreq_event_ops ro - .set_event = rockchip_dfi_set_event, - }; - -+static __init int px30_dfi_init(struct platform_device *pdev, -+ struct rockchip_dfi *data, -+ struct devfreq_event_desc *desc) -+{ -+ struct device_node *np = pdev->dev.of_node, *node; -+ struct resource *res; -+ u32 val; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ data->regs = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(data->regs)) -+ return PTR_ERR(data->regs); -+ -+ node = of_parse_phandle(np, "rockchip,pmugrf", 0); -+ if (node) { -+ data->regmap_pmugrf = syscon_node_to_regmap(node); -+ if (IS_ERR(data->regmap_pmugrf)) -+ return PTR_ERR(data->regmap_pmugrf); -+ } -+ -+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val); -+ data->dram_type = READ_DRAMTYPE_INFO(val); -+ data->ch_msk = 1; -+ data->clk = NULL; -+ -+ desc->ops = &rockchip_dfi_ops; -+ -+ return 0; -+} -+ - static __init int rk3128_dfi_init(struct platform_device *pdev, - struct rockchip_dfi *data, - struct devfreq_event_desc *desc) -@@ -582,6 +616,7 @@ static __init int rk3328_dfi_init(struct - } - - static const struct of_device_id rockchip_dfi_id_match[] = { -+ { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init }, - { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init }, - { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init }, - { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init }, diff --git a/target/linux/rockchip/patches-6.6/804-08-PM-devfreq-rockchip-dfi-add-support-for-rk1808-dfi.patch b/target/linux/rockchip/patches-6.6/804-08-PM-devfreq-rockchip-dfi-add-support-for-rk1808-dfi.patch deleted file mode 100644 index 872b27b0c7..0000000000 --- a/target/linux/rockchip/patches-6.6/804-08-PM-devfreq-rockchip-dfi-add-support-for-rk1808-dfi.patch +++ /dev/null @@ -1,21 +0,0 @@ -From b949c38cbd8573cf1a3f9acc935324d2d5ecff94 Mon Sep 17 00:00:00 2001 -From: YouMin Chen -Date: Tue, 21 Aug 2018 15:31:58 +0800 -Subject: [PATCH] PM / devfreq: rockchip-dfi: add support for rk1808 dfi - -Change-Id: Id95eca244c666b103ce4f9676e2abbeb304196ac -Signed-off-by: YouMin Chen ---- - drivers/devfreq/event/rockchip-dfi.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -617,6 +617,7 @@ static __init int rk3328_dfi_init(struct - - static const struct of_device_id rockchip_dfi_id_match[] = { - { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init }, -+ { .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init }, - { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init }, - { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init }, - { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init }, diff --git a/target/linux/rockchip/patches-6.6/804-09-PM-devfreq-rockchip-dfi-fix-lpddr4-calculation-error.patch b/target/linux/rockchip/patches-6.6/804-09-PM-devfreq-rockchip-dfi-fix-lpddr4-calculation-error.patch deleted file mode 100644 index 59db8d7b66..0000000000 --- a/target/linux/rockchip/patches-6.6/804-09-PM-devfreq-rockchip-dfi-fix-lpddr4-calculation-error.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 354584ddce4f32563c41c5623f4b92f26713e3ae Mon Sep 17 00:00:00 2001 -From: YouMin Chen -Date: Tue, 5 Mar 2019 19:38:11 +0800 -Subject: [PATCH] PM / devfreq: rockchip-dfi: fix lpddr4 calculation error - -Fix lpddr4 calculation error about access. -LPDDR4 BL(burst length) = 16,other DDR type BL(burst length) = 8. - -Change-Id: Icc1b4f6764fa0b23ec1f7722bda8ffeff1da4ab7 -Signed-off-by: YouMin Chen ---- - drivers/devfreq/event/rockchip-dfi.c | 14 +++++++++++--- - 1 file changed, 11 insertions(+), 3 deletions(-) - ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -374,11 +374,19 @@ static int rockchip_dfi_get_busier_ch(st - for (i = 0; i < MAX_DMC_NUM_CH; i++) { - if (!(info->ch_msk & BIT(i))) - continue; -- info->ch_usage[i].access = readl_relaxed(dfi_regs + -- DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4; -+ - info->ch_usage[i].total = readl_relaxed(dfi_regs + - DDRMON_CH0_COUNT_NUM + i * 20); -- tmp = info->ch_usage[i].access; -+ -+ /* LPDDR4 BL = 16,other DDR type BL = 8 */ -+ tmp = readl_relaxed(dfi_regs + -+ DDRMON_CH0_DFI_ACCESS_NUM + i * 20); -+ if (info->dram_type == LPDDR4) -+ tmp *= 8; -+ else -+ tmp *= 4; -+ info->ch_usage[i].access = tmp; -+ - if (tmp > max) { - busier_ch = i; - max = tmp; diff --git a/target/linux/rockchip/patches-6.6/804-10-PM-devfreq-rockchip-dfi-add-support-for-rv1126-dfi.patch b/target/linux/rockchip/patches-6.6/804-10-PM-devfreq-rockchip-dfi-add-support-for-rv1126-dfi.patch deleted file mode 100644 index 8d74401f8d..0000000000 --- a/target/linux/rockchip/patches-6.6/804-10-PM-devfreq-rockchip-dfi-add-support-for-rv1126-dfi.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 0369dd4ab2a13544c6f179d85bc7b7be844e6d5e Mon Sep 17 00:00:00 2001 -From: YouMin Chen -Date: Thu, 19 Dec 2019 10:46:22 +0800 -Subject: [PATCH] PM / devfreq: rockchip-dfi: add support for rv1126 dfi - -Change-Id: I65a403424b68804022025309f9af82b55c044192 -Signed-off-by: YouMin Chen ---- - drivers/devfreq/event/rockchip-dfi.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -631,6 +631,7 @@ static const struct of_device_id rockchi - { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init }, - { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init }, - { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init }, -+ { .compatible = "rockchip,rv1126-dfi", .data = px30_dfi_init }, - { }, - }; - diff --git a/target/linux/rockchip/patches-6.6/804-11-PM-devfreq-rockchip-dfi-add-support-for-rk3568-dfi.patch b/target/linux/rockchip/patches-6.6/804-11-PM-devfreq-rockchip-dfi-add-support-for-rk3568-dfi.patch deleted file mode 100644 index 0f4f30f229..0000000000 --- a/target/linux/rockchip/patches-6.6/804-11-PM-devfreq-rockchip-dfi-add-support-for-rk3568-dfi.patch +++ /dev/null @@ -1,21 +0,0 @@ -From e0603b1c9931b2e90f06596e3f8a9a123a66202d Mon Sep 17 00:00:00 2001 -From: YouMin Chen -Date: Tue, 13 Oct 2020 17:32:01 +0800 -Subject: [PATCH] PM / devfreq: rockchip-dfi: add support for rk3568 dfi - -Change-Id: I62d21e31cd56e82c04de675be502b261ba3740da -Signed-off-by: YouMin Chen ---- - drivers/devfreq/event/rockchip-dfi.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -631,6 +631,7 @@ static const struct of_device_id rockchi - { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init }, - { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init }, - { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init }, -+ { .compatible = "rockchip,rk3568-dfi", .data = px30_dfi_init }, - { .compatible = "rockchip,rv1126-dfi", .data = px30_dfi_init }, - { }, - }; diff --git a/target/linux/rockchip/patches-6.6/804-12-PM-devfreq-rockchip-dfi-add-support-lpddr4x.patch b/target/linux/rockchip/patches-6.6/804-12-PM-devfreq-rockchip-dfi-add-support-lpddr4x.patch deleted file mode 100644 index 01402c44ff..0000000000 --- a/target/linux/rockchip/patches-6.6/804-12-PM-devfreq-rockchip-dfi-add-support-lpddr4x.patch +++ /dev/null @@ -1,84 +0,0 @@ -From a97e2d456d17e753c4540632fbc63fab825bbb6b Mon Sep 17 00:00:00 2001 -From: YouMin Chen -Date: Tue, 29 Jun 2021 17:49:53 +0800 -Subject: [PATCH] PM / devfreq: rockchip-dfi: add support lpddr4x - -Change-Id: Icd86a458dc9843e80d9206d620a1da6a71adf799 -Signed-off-by: YouMin Chen ---- - drivers/devfreq/event/rockchip-dfi.c | 20 ++++++++++++++------ - 1 file changed, 14 insertions(+), 6 deletions(-) - ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -21,6 +21,7 @@ - #include - - #define PX30_PMUGRF_OS_REG2 0x208 -+#define PX30_PMUGRF_OS_REG3 0x20c - - #define RK3128_GRF_SOC_CON0 0x140 - #define RK3128_GRF_OS_REG1 0x1cc -@@ -52,6 +53,8 @@ - #define MAX_DMC_NUM_CH 2 - #define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7) - #define READ_CH_INFO(n) (((n) >> 28) & 0x3) -+#define READ_DRAMTYPE_INFO_V3(n, m) ((((n) >> 13) & 0x7) | ((((m) >> 12) & 0x3) << 3)) -+#define READ_SYSREG_VERSION(m) (((m) >> 28) & 0xf) - /* DDRMON_CTRL */ - #define DDRMON_CTRL 0x04 - #define CLR_DDRMON_CTRL (0x3f0000 << 0) -@@ -77,6 +80,7 @@ enum { - LPDDR2 = 5, - LPDDR3 = 6, - LPDDR4 = 7, -+ LPDDR4X = 8, - UNUSED = 0xFF - }; - -@@ -344,7 +348,7 @@ static void rockchip_dfi_start_hardware_ - /* set ddr type to dfi */ - if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2) - writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL); -- else if (info->dram_type == LPDDR4) -+ else if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X) - writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); - else if (info->dram_type == DDR4) - writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL); -@@ -378,10 +382,10 @@ static int rockchip_dfi_get_busier_ch(st - info->ch_usage[i].total = readl_relaxed(dfi_regs + - DDRMON_CH0_COUNT_NUM + i * 20); - -- /* LPDDR4 BL = 16,other DDR type BL = 8 */ -+ /* LPDDR4 and LPDDR4X BL = 16,other DDR type BL = 8 */ - tmp = readl_relaxed(dfi_regs + - DDRMON_CH0_DFI_ACCESS_NUM + i * 20); -- if (info->dram_type == LPDDR4) -+ if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X) - tmp *= 8; - else - tmp *= 4; -@@ -461,7 +465,7 @@ static __init int px30_dfi_init(struct p - { - struct device_node *np = pdev->dev.of_node, *node; - struct resource *res; -- u32 val; -+ u32 val_2, val_3; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - data->regs = devm_ioremap_resource(&pdev->dev, res); -@@ -475,8 +479,12 @@ static __init int px30_dfi_init(struct p - return PTR_ERR(data->regmap_pmugrf); - } - -- regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val); -- data->dram_type = READ_DRAMTYPE_INFO(val); -+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val_2); -+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG3, &val_3); -+ if (READ_SYSREG_VERSION(val_3) >= 0x3) -+ data->dram_type = READ_DRAMTYPE_INFO_V3(val_2, val_3); -+ else -+ data->dram_type = READ_DRAMTYPE_INFO(val_2); - data->ch_msk = 1; - data->clk = NULL; - diff --git a/target/linux/rockchip/patches-6.6/804-13-PM-devfreq-rockchip-dfi-add-rk3588-dfi-support.patch b/target/linux/rockchip/patches-6.6/804-13-PM-devfreq-rockchip-dfi-add-rk3588-dfi-support.patch deleted file mode 100644 index 514b55d520..0000000000 --- a/target/linux/rockchip/patches-6.6/804-13-PM-devfreq-rockchip-dfi-add-rk3588-dfi-support.patch +++ /dev/null @@ -1,229 +0,0 @@ -From d9326406232efc48aa6ce446e5be754b2b75fcf0 Mon Sep 17 00:00:00 2001 -From: Zhihuan He -Date: Wed, 1 Dec 2021 11:06:17 +0800 -Subject: [PATCH] PM / devfreq: rockchip-dfi: add rk3588 dfi support - -Signed-off-by: Zhihuan He -Change-Id: I0bebfd16aa4897f770f70aca70b0e9a88808446f ---- - drivers/devfreq/event/rockchip-dfi.c | 127 +++++++++++++++++++++++---- - 1 file changed, 108 insertions(+), 19 deletions(-) - ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -23,6 +23,8 @@ - #define PX30_PMUGRF_OS_REG2 0x208 - #define PX30_PMUGRF_OS_REG3 0x20c - -+#define RK3588_PMUGRF_OS_REG(n) (0x200 + (n) * 4) -+ - #define RK3128_GRF_SOC_CON0 0x140 - #define RK3128_GRF_OS_REG1 0x1cc - #define RK3128_GRF_DFI_WRNUM 0x220 -@@ -50,14 +52,18 @@ - #define RK3368_DFI_EN (0x30003 << 5) - #define RK3368_DFI_DIS (0x30000 << 5) - --#define MAX_DMC_NUM_CH 2 -+#define MAX_DMC_NUM_CH 4 - #define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7) - #define READ_CH_INFO(n) (((n) >> 28) & 0x3) - #define READ_DRAMTYPE_INFO_V3(n, m) ((((n) >> 13) & 0x7) | ((((m) >> 12) & 0x3) << 3)) - #define READ_SYSREG_VERSION(m) (((m) >> 28) & 0xf) -+#define READ_LP5_BANK_MODE(m) (((m) >> 1) & 0x3) -+#define READ_LP5_CKR(m) (((m) >> 0) & 0x1) - /* DDRMON_CTRL */ - #define DDRMON_CTRL 0x04 --#define CLR_DDRMON_CTRL (0x3f0000 << 0) -+#define CLR_DDRMON_CTRL (0xffff0000 << 0) -+#define LPDDR5_BANK_MODE(m) ((0x30000 | ((m) & 0x3)) << 7) -+#define LPDDR5_EN (0x10001 << 6) - #define DDR4_EN (0x10001 << 5) - #define LPDDR4_EN (0x10001 << 4) - #define HARDWARE_EN (0x10001 << 3) -@@ -81,12 +87,14 @@ enum { - LPDDR3 = 6, - LPDDR4 = 7, - LPDDR4X = 8, -+ LPDDR5 = 9, -+ DDR5 = 10, - UNUSED = 0xFF - }; - - struct dmc_usage { -- u32 access; -- u32 total; -+ u64 access; -+ u64 total; - }; - - /* -@@ -105,6 +113,13 @@ struct rockchip_dfi { - struct regmap *regmap_pmugrf; - struct clk *clk; - u32 dram_type; -+ u32 mon_idx; -+ u32 count_rate; -+ u32 dram_dynamic_info_reg; -+ /* 0: BG mode, 1: 16 Bank mode, 2: 8 bank mode */ -+ u32 lp5_bank_mode; -+ /* 0: clk:dqs = 1:2, 1: 1:4 */ -+ u32 lp5_ckr; - /* - * available mask, 1: available, 0: not available - * each bit represent a channel -@@ -341,28 +356,56 @@ static void rockchip_dfi_start_hardware_ - { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); - void __iomem *dfi_regs = info->regs; -+ u32 mon_idx = 0, val_6 = 0; -+ u32 i; -+ -+ if (info->mon_idx) -+ mon_idx = info->mon_idx; -+ -+ if (info->dram_dynamic_info_reg) -+ regmap_read(info->regmap_pmugrf, info->dram_dynamic_info_reg, &val_6); -+ -+ if (info->dram_type == LPDDR5) { -+ info->lp5_bank_mode = READ_LP5_BANK_MODE(val_6); -+ info->lp5_ckr = READ_LP5_CKR(val_6); -+ } - -- /* clear DDRMON_CTRL setting */ -- writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); -+ for (i = 0; i < MAX_DMC_NUM_CH; i++) { -+ if (!(info->ch_msk & BIT(i))) -+ continue; -+ /* clear DDRMON_CTRL setting */ -+ writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + i * mon_idx + DDRMON_CTRL); - -- /* set ddr type to dfi */ -- if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2) -- writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL); -- else if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X) -- writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); -- else if (info->dram_type == DDR4) -- writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL); -+ /* set ddr type to dfi */ -+ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2) -+ writel_relaxed(LPDDR2_3_EN, dfi_regs + i * mon_idx + DDRMON_CTRL); -+ else if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X) -+ writel_relaxed(LPDDR4_EN, dfi_regs + i * mon_idx + DDRMON_CTRL); -+ else if (info->dram_type == DDR4) -+ writel_relaxed(DDR4_EN, dfi_regs + i * mon_idx + DDRMON_CTRL); -+ else if (info->dram_type == LPDDR5) -+ writel_relaxed(LPDDR5_EN | LPDDR5_BANK_MODE(info->lp5_bank_mode), -+ dfi_regs + i * mon_idx + DDRMON_CTRL); - -- /* enable count, use software mode */ -- writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL); -+ /* enable count, use software mode */ -+ writel_relaxed(SOFTWARE_EN, dfi_regs + i * mon_idx + DDRMON_CTRL); -+ } - } - - static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) - { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); - void __iomem *dfi_regs = info->regs; -+ u32 mon_idx = 0, i; -+ -+ if (info->mon_idx) -+ mon_idx = info->mon_idx; - -- writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL); -+ for (i = 0; i < MAX_DMC_NUM_CH; i++) { -+ if (!(info->ch_msk & BIT(i))) -+ continue; -+ writel_relaxed(SOFTWARE_DIS, dfi_regs + i * mon_idx + DDRMON_CTRL); -+ } - } - - static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev) -@@ -371,22 +414,31 @@ static int rockchip_dfi_get_busier_ch(st - u32 tmp, max = 0; - u32 i, busier_ch = 0; - void __iomem *dfi_regs = info->regs; -+ u32 mon_idx = 0x20, count_rate = 1; - - rockchip_dfi_stop_hardware_counter(edev); - -+ if (info->mon_idx) -+ mon_idx = info->mon_idx; -+ if (info->count_rate) -+ count_rate = info->count_rate; -+ - /* Find out which channel is busier */ - for (i = 0; i < MAX_DMC_NUM_CH; i++) { - if (!(info->ch_msk & BIT(i))) - continue; - -+ /* rk3588 counter is dfi clk rate */ - info->ch_usage[i].total = readl_relaxed(dfi_regs + -- DDRMON_CH0_COUNT_NUM + i * 20); -+ DDRMON_CH0_COUNT_NUM + i * mon_idx) * count_rate; - -- /* LPDDR4 and LPDDR4X BL = 16,other DDR type BL = 8 */ -+ /* LPDDR5 LPDDR4 and LPDDR4X BL = 16,other DDR type BL = 8 */ - tmp = readl_relaxed(dfi_regs + -- DDRMON_CH0_DFI_ACCESS_NUM + i * 20); -+ DDRMON_CH0_DFI_ACCESS_NUM + i * mon_idx); - if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X) - tmp *= 8; -+ else if (info->dram_type == LPDDR5) -+ tmp *= 16 / (4 << info->lp5_ckr); - else - tmp *= 4; - info->ch_usage[i].access = tmp; -@@ -459,6 +511,42 @@ static const struct devfreq_event_ops ro - .set_event = rockchip_dfi_set_event, - }; - -+static __init int rk3588_dfi_init(struct platform_device *pdev, -+ struct rockchip_dfi *data, -+ struct devfreq_event_desc *desc) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct resource *res; -+ u32 val_2, val_3, val_4; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ data->regs = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(data->regs)) -+ return PTR_ERR(data->regs); -+ -+ data->regmap_pmugrf = syscon_regmap_lookup_by_phandle(np, "rockchip,pmu_grf"); -+ if (IS_ERR(data->regmap_pmugrf)) -+ return PTR_ERR(data->regmap_pmugrf); -+ -+ regmap_read(data->regmap_pmugrf, RK3588_PMUGRF_OS_REG(2), &val_2); -+ regmap_read(data->regmap_pmugrf, RK3588_PMUGRF_OS_REG(3), &val_3); -+ regmap_read(data->regmap_pmugrf, RK3588_PMUGRF_OS_REG(4), &val_4); -+ if (READ_SYSREG_VERSION(val_3) >= 0x3) -+ data->dram_type = READ_DRAMTYPE_INFO_V3(val_2, val_3); -+ else -+ data->dram_type = READ_DRAMTYPE_INFO(val_2); -+ -+ data->mon_idx = 0x4000; -+ data->count_rate = 2; -+ data->dram_dynamic_info_reg = RK3588_PMUGRF_OS_REG(6); -+ data->ch_msk = READ_CH_INFO(val_2) | READ_CH_INFO(val_4) << 2; -+ data->clk = NULL; -+ -+ desc->ops = &rockchip_dfi_ops; -+ -+ return 0; -+} -+ - static __init int px30_dfi_init(struct platform_device *pdev, - struct rockchip_dfi *data, - struct devfreq_event_desc *desc) -@@ -640,6 +728,7 @@ static const struct of_device_id rockchi - { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init }, - { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init }, - { .compatible = "rockchip,rk3568-dfi", .data = px30_dfi_init }, -+ { .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init }, - { .compatible = "rockchip,rv1126-dfi", .data = px30_dfi_init }, - { }, - }; diff --git a/target/linux/rockchip/patches-6.6/805-arm64-dts-rockchip-add-rk3328-ddr-relate-node.patch b/target/linux/rockchip/patches-6.6/805-arm64-dts-rockchip-add-rk3328-ddr-relate-node.patch deleted file mode 100644 index d69ed590a5..0000000000 --- a/target/linux/rockchip/patches-6.6/805-arm64-dts-rockchip-add-rk3328-ddr-relate-node.patch +++ /dev/null @@ -1,109 +0,0 @@ -From 2d2a4b860ef60b4d10754d2e690d6fc170571a83 Mon Sep 17 00:00:00 2001 -From: Hecanyang -Date: Sat, 23 Dec 2017 15:40:21 +0800 -Subject: [PATCH] arm64: dts: rockchip: add rk3328 ddr relate node - -except add note to existing dts file, also add ddr timing and de-skew's -dts file. - -Change-Id: I92b7e9c2c6572babd4be00beadbbb75aae431707 -Signed-off-by: CanYang He -Signed-off-by: hmz007 ---- - .../rockchip/rk3328-dram-2layer-timing.dtsi | 257 +++++++++++++++ - .../rockchip/rk3328-dram-default-timing.dtsi | 311 ++++++++++++++++++ - .../boot/dts/rockchip/rk3328-evb-android.dts | 9 + - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 67 ++++ - 4 files changed, 644 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-2layer-timing.dtsi - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi - ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include "rk3328-dram-default-timing.dtsi" - - / { - compatible = "rockchip,rk3328"; -@@ -1040,6 +1041,78 @@ - status = "disabled"; - }; - -+ dfi: dfi@ff790000 { -+ reg = <0x00 0xff790000 0x00 0x400>; -+ compatible = "rockchip,rk3328-dfi"; -+ rockchip,grf = <&grf>; -+ status = "okay"; -+ }; -+ -+ dmc: dmc { -+ compatible = "rockchip,rk3328-dmc"; -+ devfreq-events = <&dfi>; -+ clocks = <&cru SCLK_DDRCLK>; -+ clock-names = "dmc_clk"; -+ operating-points-v2 = <&dmc_opp_table>; -+ ddr_timing = <&ddr_timing>; -+ upthreshold = <40>; -+ downdifferential = <20>; -+ auto-min-freq = <786000>; -+ auto-freq-en = <0>; -+ #cooling-cells = <2>; -+ status = "disabled"; -+ -+ ddr_power_model: ddr_power_model { -+ compatible = "ddr_power_model"; -+ dynamic-power-coefficient = <120>; -+ static-power-coefficient = <200>; -+ ts = <32000 4700 (-80) 2>; -+ thermal-zone = "soc-thermal"; -+ }; -+ }; -+ -+ dmc_opp_table: dmc-opp-table { -+ compatible = "operating-points-v2"; -+ -+ rockchip,leakage-voltage-sel = < -+ 1 10 0 -+ 11 254 1 -+ >; -+ nvmem-cells = <&logic_leakage>; -+ nvmem-cell-names = "ddr_leakage"; -+ -+ opp-786000000 { -+ opp-hz = /bits/ 64 <786000000>; -+ opp-microvolt = <1075000>; -+ opp-microvolt-L0 = <1075000>; -+ opp-microvolt-L1 = <1050000>; -+ }; -+ opp-798000000 { -+ opp-hz = /bits/ 64 <798000000>; -+ opp-microvolt = <1075000>; -+ opp-microvolt-L0 = <1075000>; -+ opp-microvolt-L1 = <1050000>; -+ }; -+ opp-840000000 { -+ opp-hz = /bits/ 64 <840000000>; -+ opp-microvolt = <1075000>; -+ opp-microvolt-L0 = <1075000>; -+ opp-microvolt-L1 = <1050000>; -+ }; -+ opp-924000000 { -+ opp-hz = /bits/ 64 <924000000>; -+ opp-microvolt = <1100000>; -+ opp-microvolt-L0 = <1100000>; -+ opp-microvolt-L1 = <1075000>; -+ }; -+ opp-1056000000 { -+ opp-hz = /bits/ 64 <1056000000>; -+ opp-microvolt = <1175000>; -+ opp-microvolt-L0 = <1175000>; -+ opp-microvolt-L1 = <1150000>; -+ }; -+ }; -+ - gic: interrupt-controller@ff811000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; diff --git a/target/linux/rockchip/patches-6.6/806-arm64-dts-rockchip-enable-dmc-for-rk3328-boards.patch b/target/linux/rockchip/patches-6.6/806-arm64-dts-rockchip-enable-dmc-for-rk3328-boards.patch deleted file mode 100644 index e9d7af8ae5..0000000000 --- a/target/linux/rockchip/patches-6.6/806-arm64-dts-rockchip-enable-dmc-for-rk3328-boards.patch +++ /dev/null @@ -1,213 +0,0 @@ -From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001 -From: hmz007 -Date: Tue, 19 Nov 2019 14:21:51 +0800 -Subject: [PATCH] arm64: dts: nanopi-r2: add rk3328-dmc relate node - -Signed-off-by: hmz007 ---- - .../rockchip/rk3328-dram-default-timing.dtsi | 311 ++++++++++++++++++ - .../dts/rockchip/rk3328-nanopi-r2-common.dtsi | 85 ++++- - include/dt-bindings/clock/rockchip-ddr.h | 63 ++++ - include/dt-bindings/memory/rk3328-dram.h | 159 +++++++++ - 4 files changed, 617 insertions(+), 1 deletion(-) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi - create mode 100644 include/dt-bindings/clock/rockchip-ddr.h - create mode 100644 include/dt-bindings/memory/rk3328-dram.h - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -145,6 +145,11 @@ - status = "disabled"; - }; - -+&dmc { -+ center-supply = <&vdd_log>; -+ status = "okay"; -+}; -+ - &gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -@@ -210,6 +215,7 @@ - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; -+ regulator-init-microvolt = <1075000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; -@@ -224,6 +230,7 @@ - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; -+ regulator-init-microvolt = <1225000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -111,6 +111,11 @@ - status = "disabled"; - }; - -+&dmc { -+ center-supply = <&vdd_log>; -+ status = "okay"; -+}; -+ - &gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -@@ -170,6 +175,7 @@ - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; -+ regulator-init-microvolt = <1075000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; -@@ -184,6 +190,7 @@ - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; -+ regulator-init-microvolt = <1225000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts -@@ -14,6 +14,21 @@ - compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; - }; - -+&dmc_opp_table { -+ opp-798000000 { -+ status = "disabled"; -+ }; -+ opp-840000000 { -+ status = "disabled"; -+ }; -+ opp-924000000 { -+ status = "disabled"; -+ }; -+ opp-1056000000 { -+ status = "disabled"; -+ }; -+}; -+ - &gmac2io { - /delete-property/ tx_delay; - /delete-property/ rx_delay; ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -134,6 +134,64 @@ - cpu-supply = <&vdd_arm>; - }; - -+&ddr_timing { -+ ddr3a1_ddr4a9_de-skew = <0>; -+ ddr3a0_ddr4a10_de-skew = <0>; -+ ddr3a3_ddr4a6_de-skew = <1>; -+ ddr3a2_ddr4a4_de-skew = <1>; -+ ddr3a5_ddr4a8_de-skew = <0>; -+ ddr3a4_ddr4a5_de-skew = <2>; -+ ddr3a7_ddr4a11_de-skew = <0>; -+ ddr3a6_ddr4a7_de-skew = <2>; -+ ddr3a9_ddr4a0_de-skew = <1>; -+ ddr3a8_ddr4a13_de-skew = <0>; -+ ddr3a11_ddr4a3_de-skew = <2>; -+ ddr3a10_ddr4cs0_de-skew = <0>; -+ ddr3a13_ddr4a2_de-skew = <1>; -+ ddr3a12_ddr4ba1_de-skew = <0>; -+ ddr3a15_ddr4odt0_de-skew = <0>; -+ ddr3a14_ddr4a1_de-skew = <1>; -+ ddr3ba1_ddr4a15_de-skew = <0>; -+ ddr3ba0_ddr4bg0_de-skew = <0>; -+ ddr3ras_ddr4cke_de-skew = <0>; -+ ddr3ba2_ddr4ba0_de-skew = <1>; -+ ddr3we_ddr4bg1_de-skew = <1>; -+ ddr3cas_ddr4a12_de-skew = <0>; -+ ddr3ckn_ddr4ckn_de-skew = <5>; -+ ddr3ckp_ddr4ckp_de-skew = <5>; -+ ddr3cke_ddr4a16_de-skew = <1>; -+ ddr3odt0_ddr4a14_de-skew = <0>; -+ ddr3cs0_ddr4act_de-skew = <1>; -+ ddr3reset_ddr4reset_de-skew = <0>; -+ ddr3cs1_ddr4cs1_de-skew = <0>; -+ ddr3odt1_ddr4odt1_de-skew = <0>; -+}; -+ -+&dmc { -+ center-supply = <&vdd_logic>; -+ status = "okay"; -+}; -+ -+&dmc_opp_table { -+ /delete-node/ opp-1056000000; -+ -+ opp-798000000 { -+ opp-microvolt-L1 = <12000000>; -+ }; -+ opp-840000000 { -+ opp-microvolt-L1 = <12000000>; -+ }; -+ opp-924000000 { -+ opp-microvolt-L1 = <12000000>; -+ }; -+ opp-1068000000 { -+ opp-hz = /bits/ 64 <1068000000>; -+ opp-microvolt = <1175000>; -+ opp-microvolt-L0 = <1175000>; -+ opp-microvolt-L1 = <12000000>; -+ }; -+}; -+ - &emmc { - bus-width = <8>; - cap-mmc-highspeed; -@@ -206,6 +264,7 @@ - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; -+ regulator-init-microvolt = <1075000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; -@@ -218,6 +277,7 @@ - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; -+ regulator-init-microvolt = <1225000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts -@@ -133,6 +133,11 @@ - cpu-supply = <&vdd_arm>; - }; - -+&dmc { -+ center-supply = <&vdd_log>; -+ status = "okay"; -+}; -+ - &emmc { - bus-width = <8>; - cap-mmc-highspeed; -@@ -213,6 +218,7 @@ - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; -+ regulator-init-microvolt = <1075000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; -@@ -227,6 +233,7 @@ - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; -+ regulator-init-microvolt = <1225000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; diff --git a/target/linux/rockchip/patches-6.6/900-arm64-boot-add-dts-files.patch b/target/linux/rockchip/patches-6.6/900-arm64-boot-add-dts-files.patch deleted file mode 100644 index db2343938a..0000000000 --- a/target/linux/rockchip/patches-6.6/900-arm64-boot-add-dts-files.patch +++ /dev/null @@ -1,52 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -39,6 +39,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gr - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-dumo.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-guangmiao-g4c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb -@@ -50,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-na - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4se.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s-enterprise.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb -@@ -91,19 +93,25 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-so - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-nanopi-r3s.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-armsom-sige3.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mmbox-anas3035.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lyt-t68m.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mrkaio-m68s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-cyber3588-aib.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb -@@ -112,5 +120,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-or - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb diff --git a/target/linux/rockchip/patches-6.6/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch b/target/linux/rockchip/patches-6.6/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch deleted file mode 100644 index 9a7ac8092b..0000000000 --- a/target/linux/rockchip/patches-6.6/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Leonidas P. Papadakos -Date: Fri, 1 Mar 2019 21:55:53 +0200 -Subject: [PATCH v2] arm64: dts: rockchip: add more cpu operating points for - RK3328 - -This allows for greater max frequency on rk3328 boards, -increasing performance. - -It has been included in Armbian (a linux distibution for ARM boards) -for a while now without any reported issues - -https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1392mhz-opp.patch -https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1512mhz-opp.patch - -Signed-off-by: Leonidas P. Papadakos ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 15 +++++++++++++++ - 1 files changed, 15 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -143,6 +143,16 @@ - opp-microvolt = <1300000>; - clock-latency-ns = <40000>; - }; -+ opp-1392000000 { -+ opp-hz = /bits/ 64 <1392000000>; -+ opp-microvolt = <1350000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1512000000 { -+ opp-hz = /bits/ 64 <1512000000>; -+ opp-microvolt = <1450000>; -+ clock-latency-ns = <40000>; -+ }; - }; - - analog_sound: analog-sound { diff --git a/target/linux/rockchip/patches-6.6/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch b/target/linux/rockchip/patches-6.6/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch deleted file mode 100644 index ee8527a2fc..0000000000 --- a/target/linux/rockchip/patches-6.6/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Mon, 18 Oct 2021 12:47:30 +0800 -Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz - -It's stable enough to overclock cpu frequency to 2.2/1.8 GHz, -and for better performance. - -Co-development-by: gzelvis -Signed-off-by: Tianling Shen ---- - arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi -@@ -33,6 +33,14 @@ - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1125000 1125000 1250000>; - }; -+ opp06 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <1225000>; -+ }; -+ opp07 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <1275000>; -+ }; - }; - - cluster1_opp: opp-table-1 { -@@ -72,6 +80,14 @@ - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1200000 1200000 1250000>; - }; -+ opp08 { -+ opp-hz = /bits/ 64 <2016000000>; -+ opp-microvolt = <1250000>; -+ }; -+ opp09 { -+ opp-hz = /bits/ 64 <2208000000>; -+ opp-microvolt = <1325000>; -+ }; - }; - - gpu_opp_table: opp-table-2 { diff --git a/target/linux/rockchip/patches-6.6/993-rockchip-rk3566-unlock-2.0-GHz.patch b/target/linux/rockchip/patches-6.6/993-rockchip-rk3566-unlock-2.0-GHz.patch deleted file mode 100644 index 2cbdef9372..0000000000 --- a/target/linux/rockchip/patches-6.6/993-rockchip-rk3566-unlock-2.0-GHz.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi -@@ -6,6 +6,13 @@ - compatible = "rockchip,rk3566"; - }; - -+&cpu0_opp_table { -+ opp-1992000000 { -+ opp-hz = /bits/ 64 <1992000000>; -+ opp-microvolt = <1150000 1150000 1150000>; -+ }; -+}; -+ - &pipegrf { - compatible = "rockchip,rk3566-pipe-grf", "syscon"; - }; diff --git a/target/linux/sifiveu/Makefile b/target/linux/sifiveu/Makefile index 70c6f433d9..1d60c0a026 100644 --- a/target/linux/sifiveu/Makefile +++ b/target/linux/sifiveu/Makefile @@ -11,8 +11,7 @@ FEATURES:=ext4 KERNELNAME:=Image dtbs SUBTARGETS:=generic -KERNEL_PATCHVER:=6.6 -KERNEL_TESTING_PATCHVER:=6.12 +KERNEL_PATCHVER:=6.12 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/sifiveu/config-6.6 b/target/linux/sifiveu/config-6.6 deleted file mode 100644 index e19ea64a85..0000000000 --- a/target/linux/sifiveu/config-6.6 +++ /dev/null @@ -1,403 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_ACPI is not set -CONFIG_ARCH_CLOCKSOURCE_INIT=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_RV64I=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -# CONFIG_ARCH_THEAD is not set -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ASN1=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_ATA=y -CONFIG_ATA_VERBOSE_ERROR=y -# CONFIG_AX45MP_L2_CACHE is not set -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CAVIUM_PTP=y -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y -CONFIG_CLK_SIFIVE=y -CONFIG_CLK_SIFIVE_PRCI=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y -CONFIG_CMODEL_MEDANY=y -# CONFIG_CMODEL_MEDLOW is not set -CONFIG_COMMON_CLK=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -# CONFIG_COMPAT_32BIT_TIME is not set -CONFIG_COMPAT_BRK=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_COREDUMP=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_CPU_ISOLATION=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC7=y -CONFIG_CRC_ITU_T=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_RSA=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_INFO=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EDAC=y -# CONFIG_EDAC_DEBUG is not set -CONFIG_EDAC_LEGACY_SYSFS=y -CONFIG_EDAC_SIFIVE=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EFI=y -CONFIG_EFIVAR_FS=m -# CONFIG_EFI_BOOTLOADER_CONTROL is not set -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_COCO_SECRET is not set -# CONFIG_EFI_DISABLE_PCI_DMA is not set -# CONFIG_EFI_DISABLE_RUNTIME is not set -CONFIG_EFI_EARLYCON=y -CONFIG_EFI_ESRT=y -CONFIG_EFI_GENERIC_STUB=y -CONFIG_EFI_PARAMS_FROM_FDT=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_STUB=y -# CONFIG_EFI_TEST is not set -# CONFIG_EFI_ZBOOT is not set -CONFIG_ELF_CORE=y -# CONFIG_ERRATA_ANDES is not set -CONFIG_ERRATA_SIFIVE=y -CONFIG_ERRATA_SIFIVE_CIP_1200=y -CONFIG_ERRATA_SIFIVE_CIP_453=y -# CONFIG_ERRATA_THEAD is not set -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_FAILOVER=y -CONFIG_FAT_FS=y -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FONT_8x16=y -CONFIG_FONT_AUTOSELECT=y -CONFIG_FONT_SUPPORT=y -CONFIG_FPU=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_INJECTION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_CDEV_V1=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_SIFIVE=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_CPCI is not set -CONFIG_HOTPLUG_PCI_PCIE=y -CONFIG_HOTPLUG_PCI_SHPC=y -CONFIG_HVC_DRIVER=y -CONFIG_HVC_RISCV_SBI=y -CONFIG_HW_CONSOLE=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_OCORES=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -# CONFIG_IOMMUFD is not set -# CONFIG_IOMMU_DEBUGFS is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_STACKS=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KEYS=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_MACB=y -# CONFIG_MACB_PCI is not set -CONFIG_MACB_USE_HWSTAMP=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MICROSEMI_PHY=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_CADENCE=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SPI=y -CONFIG_MMIOWB=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MODULE_SECTIONS=y -CONFIG_MPILIB=y -CONFIG_MQ_IOSCHED_DEADLINE=y -CONFIG_MQ_IOSCHED_KYBER=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_FAILOVER=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_NONPORTABLE is not set -CONFIG_NR_CPUS=8 -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DMA_DEFAULT_COHERENT=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OID_REGISTRY=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xff60000000000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_REPORTING=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEAER_INJECT=m -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DPC=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_ECRC=y -CONFIG_PCIE_FU740=y -CONFIG_PCIE_PTM=y -CONFIG_PCIE_XILINX=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_ECAM=y -CONFIG_PCI_HOST_COMMON=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_SW_SWITCHTEC=y -CONFIG_PGTABLE_LEVELS=5 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PORTABLE=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_POWER_RESET_RESTART=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_PPS=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_SIFIVE=y -CONFIG_PWM_SYSFS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RCU_TRACE=y -CONFIG_RD_GZIP=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -# CONFIG_RESET_ATTACK_MITIGATION is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_SIMPLE=y -CONFIG_RFS_ACCEL=y -CONFIG_RISCV=y -CONFIG_RISCV_ALTERNATIVE=y -CONFIG_RISCV_BASE_PMU=y -# CONFIG_RISCV_BOOT_SPINWAIT is not set -CONFIG_RISCV_DMA_NONCOHERENT=y -CONFIG_RISCV_INTC=y -CONFIG_RISCV_ISA_C=y -CONFIG_RISCV_ISA_FALLBACK=y -CONFIG_RISCV_ISA_SVNAPOT=y -CONFIG_RISCV_ISA_SVPBMT=y -CONFIG_RISCV_ISA_V=y -CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y -CONFIG_RISCV_ISA_ZBB=y -CONFIG_RISCV_ISA_ZICBOM=y -CONFIG_RISCV_ISA_ZICBOZ=y -CONFIG_RISCV_SBI=y -CONFIG_RISCV_SBI_V01=y -CONFIG_RISCV_TIMER=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_EFI is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_DEBUG=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_EXAR=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_EARLYCON_RISCV_SBI=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_SIFIVE=y -CONFIG_SERIAL_SIFIVE_CONSOLE=y -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SG_POOL=y -CONFIG_SIFIVE_CCACHE=y -CONFIG_SIFIVE_PLIC=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -# CONFIG_SOC_MICROCHIP_POLARFIRE is not set -CONFIG_SOC_SIFIVE=y -# CONFIG_SOC_STARFIVE is not set -# CONFIG_SOC_VIRT is not set -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_SIFIVE=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -# CONFIG_SYSFB_SIMPLEFB is not set -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_THREAD_SIZE_ORDER=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TOOLCHAIN_HAS_ZICBOM=y -CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y -CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y -CONFIG_TRACE_CLOCK=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_TUNE_GENERIC=y -CONFIG_UCS2_STRING=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -CONFIG_USB_EHCI_PCI=y -CONFIG_USB_HID=y -CONFIG_USB_NET_DRIVERS=y -CONFIG_USB_PCI=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -# CONFIG_USB_UHCI_HCD is not set -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PCI=y -# CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_VFAT_FS=y -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 -CONFIG_VMAP_STACK=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/sifiveu/patches-6.12/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch b/target/linux/sifiveu/patches-6.12/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch deleted file mode 100644 index 07170d7c76..0000000000 --- a/target/linux/sifiveu/patches-6.12/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Mon, 13 Sep 2021 02:18:30 -0700 -Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node - -Add gpio-poweroff node to allow powering off the system. - -Signed-off-by: David Abdurachmanov ---- - arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -@@ -86,6 +86,11 @@ - }; - }; - }; -+ -+ gpio-poweroff { -+ compatible = "gpio-poweroff"; -+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>; -+ }; - }; - - &uart0 { diff --git a/target/linux/sifiveu/patches-6.6/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch b/target/linux/sifiveu/patches-6.6/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch deleted file mode 100644 index 9a1c968139..0000000000 --- a/target/linux/sifiveu/patches-6.6/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch +++ /dev/null @@ -1,49 +0,0 @@ -From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Wed, 17 Feb 2021 06:06:14 -0800 -Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to - sifive,u74-mc - -Signed-off-by: David Abdurachmanov ---- - arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi -+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi -@@ -39,7 +39,7 @@ - }; - }; - cpu1: cpu@1 { -- compatible = "sifive,bullet0", "riscv"; -+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; -@@ -63,7 +63,7 @@ - }; - }; - cpu2: cpu@2 { -- compatible = "sifive,bullet0", "riscv"; -+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; -@@ -87,7 +87,7 @@ - }; - }; - cpu3: cpu@3 { -- compatible = "sifive,bullet0", "riscv"; -+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; -@@ -111,7 +111,7 @@ - }; - }; - cpu4: cpu@4 { -- compatible = "sifive,bullet0", "riscv"; -+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; diff --git a/target/linux/sifiveu/patches-6.6/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch b/target/linux/sifiveu/patches-6.6/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch deleted file mode 100644 index 07170d7c76..0000000000 --- a/target/linux/sifiveu/patches-6.6/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Mon, 13 Sep 2021 02:18:30 -0700 -Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node - -Add gpio-poweroff node to allow powering off the system. - -Signed-off-by: David Abdurachmanov ---- - arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -@@ -86,6 +86,11 @@ - }; - }; - }; -+ -+ gpio-poweroff { -+ compatible = "gpio-poweroff"; -+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>; -+ }; - }; - - &uart0 { diff --git a/target/linux/sifiveu/patches-6.6/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch b/target/linux/sifiveu/patches-6.6/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch deleted file mode 100644 index 905e3cccb7..0000000000 --- a/target/linux/sifiveu/patches-6.6/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch +++ /dev/null @@ -1,116 +0,0 @@ -From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Fri, 14 May 2021 05:27:51 -0700 -Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq) - -Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4 - -Signed-off-by: David Abdurachmanov ---- - arch/riscv/Kconfig | 8 +++++ - arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++ - .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++ - 3 files changed, 47 insertions(+) - ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -901,6 +901,14 @@ config PORTABLE - select MMU - select OF - -+menu "CPU Power Management" -+ -+source "drivers/cpuidle/Kconfig" -+ -+source "drivers/cpufreq/Kconfig" -+ -+endmenu -+ - menu "Power management options" - - source "kernel/power/Kconfig" ---- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi -+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi -@@ -30,6 +30,7 @@ - i-cache-size = <16384>; - reg = <0>; - riscv,isa = "rv64imac"; -+ clocks = <&prci FU540_PRCI_CLK_COREPLL>; - status = "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; -@@ -54,6 +55,7 @@ - reg = <1>; - riscv,isa = "rv64imafdc"; - tlb-split; -+ clocks = <&prci FU540_PRCI_CLK_COREPLL>; - next-level-cache = <&l2cache>; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; -@@ -78,6 +80,7 @@ - reg = <2>; - riscv,isa = "rv64imafdc"; - tlb-split; -+ clocks = <&prci FU540_PRCI_CLK_COREPLL>; - next-level-cache = <&l2cache>; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; -@@ -102,6 +105,7 @@ - reg = <3>; - riscv,isa = "rv64imafdc"; - tlb-split; -+ clocks = <&prci FU540_PRCI_CLK_COREPLL>; - next-level-cache = <&l2cache>; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; -@@ -126,6 +130,7 @@ - reg = <4>; - riscv,isa = "rv64imafdc"; - tlb-split; -+ clocks = <&prci FU540_PRCI_CLK_COREPLL>; - next-level-cache = <&l2cache>; - cpu4_intc: interrupt-controller { - #interrupt-cells = <1>; ---- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts -+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts -@@ -80,6 +80,40 @@ - label = "d4"; - }; - }; -+ -+ fu540_c000_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-350000000 { -+ opp-hz = /bits/ 64 <350000000>; -+ }; -+ opp-700000000 { -+ opp-hz = /bits/ 64 <700000000>; -+ }; -+ opp-999999999 { -+ opp-hz = /bits/ 64 <999999999>; -+ }; -+ opp-1400000000 { -+ opp-hz = /bits/ 64 <1400000000>; -+ }; -+ }; -+}; -+ -+&cpu0 { -+ operating-points-v2 = <&fu540_c000_opp_table>; -+}; -+&cpu1 { -+ operating-points-v2 = <&fu540_c000_opp_table>; -+}; -+&cpu2 { -+ operating-points-v2 = <&fu540_c000_opp_table>; -+}; -+&cpu3 { -+ operating-points-v2 = <&fu540_c000_opp_table>; -+}; -+&cpu4 { -+ operating-points-v2 = <&fu540_c000_opp_table>; - }; - - &uart0 { diff --git a/target/linux/stm32/stm32mp1/config-6.6 b/target/linux/stm32/stm32mp1/config-6.6 index b81f761394..b677322a25 100644 --- a/target/linux/stm32/stm32mp1/config-6.6 +++ b/target/linux/stm32/stm32mp1/config-6.6 @@ -44,6 +44,7 @@ CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y CONFIG_ARM_PSCI_FW=y CONFIG_ARM_SCMI_CPUFREQ=y +# CONFIG_ARM_SCMI_DEBUG_COUNTERS is not set CONFIG_ARM_SCMI_HAVE_MSG=y CONFIG_ARM_SCMI_HAVE_SHMEM=y CONFIG_ARM_SCMI_HAVE_TRANSPORT=y diff --git a/target/linux/sunxi/Makefile b/target/linux/sunxi/Makefile index 3d3c6c2916..9d4484d554 100644 --- a/target/linux/sunxi/Makefile +++ b/target/linux/sunxi/Makefile @@ -10,7 +10,7 @@ BOARDNAME:=Allwinner ARM SoCs FEATURES:=ext4 display rootfs-part rtc squashfs usb usbgadget SUBTARGETS:=cortexa8 cortexa7 cortexa53 -KERNEL_PATCHVER:=6.6 +KERNEL_PATCHVER:=6.12 KERNELNAME:=zImage dtbs diff --git a/target/linux/sunxi/config-6.6 b/target/linux/sunxi/config-6.12 similarity index 95% rename from target/linux/sunxi/config-6.6 rename to target/linux/sunxi/config-6.12 index 45dba7b4c3..d0fcde3500 100644 --- a/target/linux/sunxi/config-6.6 +++ b/target/linux/sunxi/config-6.12 @@ -68,6 +68,7 @@ CONFIG_CLK_SUNXI_PRCM_SUN9I=y CONFIG_CLONE_BACKWARDS=y CONFIG_COMMON_CLK=y CONFIG_COMPAT_32BIT_TIME=y +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_TRANSLATIONS=y @@ -115,10 +116,26 @@ CONFIG_CRYPTO_DEV_ALLWINNER=y CONFIG_CRYPTO_DEV_SUN4I_SS=y # CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y -# CONFIG_CRYPTO_DEV_SUN8I_CE is not set -# CONFIG_CRYPTO_DEV_SUN8I_SS is not set +CONFIG_CRYPTO_DEV_SUN8I_CE=y +# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y +CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y +CONFIG_CRYPTO_DEV_SUN8I_SS=y +# CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y +CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ENGINE=y CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y @@ -395,6 +412,7 @@ CONFIG_PWM_SUN4I=y CONFIG_PWM_SYSFS=y CONFIG_RATIONAL=y CONFIG_REALTEK_PHY=y +CONFIG_REALTEK_PHY_HWMON=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_IRQ=y @@ -404,6 +422,7 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_AXP20X=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_SUN20I=y CONFIG_REGULATOR_SY8106A=y CONFIG_RELAY=y CONFIG_RESET_CONTROLLER=y @@ -525,8 +544,6 @@ CONFIG_VFPv3=y CONFIG_VHOST=y CONFIG_VHOST_IOTLB=y CONFIG_VHOST_NET=y -# CONFIG_VIDEO_SUN4I_CSI is not set -# CONFIG_VIDEO_SUN6I_CSI is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_VT=y CONFIG_VT_CONSOLE=y diff --git a/target/linux/sunxi/cortexa53/config-6.6 b/target/linux/sunxi/cortexa53/config-6.12 similarity index 97% rename from target/linux/sunxi/cortexa53/config-6.6 rename to target/linux/sunxi/cortexa53/config-6.12 index e0cfb18d5a..0c2ed8722f 100644 --- a/target/linux/sunxi/cortexa53/config-6.6 +++ b/target/linux/sunxi/cortexa53/config-6.12 @@ -20,6 +20,7 @@ CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y CONFIG_ARM64_PAGE_SHIFT=12 CONFIG_ARM64_PA_BITS=48 CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PLATFORM_DEVICES=y CONFIG_ARM64_TAGGED_ADDR_ABI=y CONFIG_ARM64_VA_BITS=39 CONFIG_ARM64_VA_BITS_39=y @@ -90,6 +91,8 @@ CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_SUN6I=y # CONFIG_SCHED_CLUSTER is not set # CONFIG_SHADOW_CALL_STACK is not set # CONFIG_SND_SUN50I_CODEC_ANALOG is not set @@ -107,7 +110,7 @@ CONFIG_SUN50I_H616_CCU=y CONFIG_SUN50I_H6_CCU=y CONFIG_SUN50I_H6_R_CCU=y CONFIG_SUN50I_IOMMU=y -# CONFIG_SUN6I_RTC_CCU is not set +CONFIG_SUN6I_RTC_CCU=y CONFIG_SURFACE_PLATFORMS=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_THREAD_INFO_IN_TASK=y diff --git a/target/linux/sunxi/cortexa7/config-6.6 b/target/linux/sunxi/cortexa7/config-6.12 similarity index 100% rename from target/linux/sunxi/cortexa7/config-6.6 rename to target/linux/sunxi/cortexa7/config-6.12 diff --git a/target/linux/sunxi/cortexa8/config-6.6 b/target/linux/sunxi/cortexa8/config-6.12 similarity index 100% rename from target/linux/sunxi/cortexa8/config-6.6 rename to target/linux/sunxi/cortexa8/config-6.12 diff --git a/target/linux/sunxi/image/cortexa7.mk b/target/linux/sunxi/image/cortexa7.mk index 9068d3d736..744fa05762 100644 --- a/target/linux/sunxi/image/cortexa7.mk +++ b/target/linux/sunxi/image/cortexa7.mk @@ -186,6 +186,15 @@ define Device/olimex_a20-olinuxino-micro endef TARGET_DEVICES += olimex_a20-olinuxino-micro +define Device/roofull_beelink-x2 + DEVICE_VENDOR := Roofull + DEVICE_MODEL := Beelink-X2 + DEVICE_PACKAGES:=kmod-leds-gpio kmod-gpio-button-hotplug \ + kmod-brcmfmac cypress-firmware-43430-sdio wpad-basic-mbedtls + SOC := sun8i-h3 +endef +TARGET_DEVICES += roofull_beelink-x2 + define Device/sinovoip_bananapi-m2-plus DEVICE_VENDOR := Sinovoip DEVICE_MODEL := Banana Pi M2+ diff --git a/target/linux/sunxi/patches-6.6/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch b/target/linux/sunxi/patches-6.12/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch similarity index 100% rename from target/linux/sunxi/patches-6.6/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch rename to target/linux/sunxi/patches-6.12/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch diff --git a/target/linux/sunxi/patches-6.6/103-arm64-dts-allwinner-add-LED-configuration-to-Orange-Pi-Ze.patch b/target/linux/sunxi/patches-6.12/103-arm64-dts-allwinner-add-LED-configuration-to-Orange-Pi-Ze.patch similarity index 100% rename from target/linux/sunxi/patches-6.6/103-arm64-dts-allwinner-add-LED-configuration-to-Orange-Pi-Ze.patch rename to target/linux/sunxi/patches-6.12/103-arm64-dts-allwinner-add-LED-configuration-to-Orange-Pi-Ze.patch diff --git a/target/linux/sunxi/patches-6.6/301-orangepi_pc2_usb_otg_to_host_key_power.patch b/target/linux/sunxi/patches-6.12/301-orangepi_pc2_usb_otg_to_host_key_power.patch similarity index 100% rename from target/linux/sunxi/patches-6.6/301-orangepi_pc2_usb_otg_to_host_key_power.patch rename to target/linux/sunxi/patches-6.12/301-orangepi_pc2_usb_otg_to_host_key_power.patch diff --git a/target/linux/sunxi/patches-6.6/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch b/target/linux/sunxi/patches-6.12/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch similarity index 100% rename from target/linux/sunxi/patches-6.6/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch rename to target/linux/sunxi/patches-6.12/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch diff --git a/target/linux/sunxi/patches-6.6/410-sunxi-add-bananapi-p2-zero.patch b/target/linux/sunxi/patches-6.12/410-sunxi-add-bananapi-p2-zero.patch similarity index 99% rename from target/linux/sunxi/patches-6.6/410-sunxi-add-bananapi-p2-zero.patch rename to target/linux/sunxi/patches-6.12/410-sunxi-add-bananapi-p2-zero.patch index f605292dcd..eed2f0feff 100644 --- a/target/linux/sunxi/patches-6.6/410-sunxi-add-bananapi-p2-zero.patch +++ b/target/linux/sunxi/patches-6.12/410-sunxi-add-bananapi-p2-zero.patch @@ -1,6 +1,6 @@ --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile -@@ -219,6 +219,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ +@@ -220,6 +220,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dtb \ sun8i-h2-plus-bananapi-m2-zero.dtb \ diff --git a/target/linux/sunxi/patches-6.6/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch b/target/linux/sunxi/patches-6.12/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch similarity index 100% rename from target/linux/sunxi/patches-6.6/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch rename to target/linux/sunxi/patches-6.12/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch diff --git a/target/linux/sunxi/patches-6.6/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch b/target/linux/sunxi/patches-6.12/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch similarity index 100% rename from target/linux/sunxi/patches-6.6/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch rename to target/linux/sunxi/patches-6.12/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch diff --git a/target/linux/sunxi/patches-6.6/432-arm64-dts-allwinner-add-LED-aliases-to-Orange-Pi-Zer.patch b/target/linux/sunxi/patches-6.12/432-arm64-dts-allwinner-add-LED-aliases-to-Orange-Pi-Zer.patch similarity index 100% rename from target/linux/sunxi/patches-6.6/432-arm64-dts-allwinner-add-LED-aliases-to-Orange-Pi-Zer.patch rename to target/linux/sunxi/patches-6.12/432-arm64-dts-allwinner-add-LED-aliases-to-Orange-Pi-Zer.patch diff --git a/target/linux/sunxi/patches-6.6/442-arm64-dts-orangepi-one-plus-enable-PWM.patch b/target/linux/sunxi/patches-6.12/442-arm64-dts-orangepi-one-plus-enable-PWM.patch similarity index 100% rename from target/linux/sunxi/patches-6.6/442-arm64-dts-orangepi-one-plus-enable-PWM.patch rename to target/linux/sunxi/patches-6.12/442-arm64-dts-orangepi-one-plus-enable-PWM.patch diff --git a/target/linux/sunxi/patches-6.6/450-arm64-dts-enable-wifi-on-pine64-boards.patch b/target/linux/sunxi/patches-6.12/450-arm64-dts-enable-wifi-on-pine64-boards.patch similarity index 100% rename from target/linux/sunxi/patches-6.6/450-arm64-dts-enable-wifi-on-pine64-boards.patch rename to target/linux/sunxi/patches-6.12/450-arm64-dts-enable-wifi-on-pine64-boards.patch diff --git a/target/linux/sunxi/patches-6.6/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch b/target/linux/sunxi/patches-6.12/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch similarity index 100% rename from target/linux/sunxi/patches-6.6/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch rename to target/linux/sunxi/patches-6.12/451-sunxi-add-csi-video-support-for-nanopi-neo-air.patch diff --git a/target/linux/sunxi/patches-6.6/910-arm64-dts-allwinner-h5-add-more-cpu-operating-points-.patch b/target/linux/sunxi/patches-6.12/910-arm64-dts-allwinner-h5-add-more-cpu-operating-points-.patch similarity index 100% rename from target/linux/sunxi/patches-6.6/910-arm64-dts-allwinner-h5-add-more-cpu-operating-points-.patch rename to target/linux/sunxi/patches-6.12/910-arm64-dts-allwinner-h5-add-more-cpu-operating-points-.patch diff --git a/target/linux/sunxi/patches-6.6/911-arm64-dts-allwinner-h616-add-more-cpu-operating-points-.patch b/target/linux/sunxi/patches-6.12/911-arm64-dts-allwinner-h616-add-more-cpu-operating-points-.patch similarity index 72% rename from target/linux/sunxi/patches-6.6/911-arm64-dts-allwinner-h616-add-more-cpu-operating-points-.patch rename to target/linux/sunxi/patches-6.12/911-arm64-dts-allwinner-h616-add-more-cpu-operating-points-.patch index a0618e6809..f54d3870e0 100644 --- a/target/linux/sunxi/patches-6.6/911-arm64-dts-allwinner-h616-add-more-cpu-operating-points-.patch +++ b/target/linux/sunxi/patches-6.12/911-arm64-dts-allwinner-h616-add-more-cpu-operating-points-.patch @@ -4,7 +4,7 @@ opp-hz = /bits/ 64 <480000000>; opp-microvolt = <900000>; clock-latency-ns = <244144>; /* 8 32k periods */ -- opp-supported-hw = <0x1f>; +- opp-supported-hw = <0x3f>; }; opp-600000000 { @@ -18,7 +18,7 @@ opp-hz = /bits/ 64 <720000000>; opp-microvolt = <900000>; clock-latency-ns = <244144>; /* 8 32k periods */ -- opp-supported-hw = <0x0d>; +- opp-supported-hw = <0x2d>; }; opp-792000000 { @@ -37,27 +37,34 @@ }; opp-1008000000 { -@@ -51,7 +46,6 @@ - opp-microvolt-speed3 = <950000>; +@@ -52,14 +47,12 @@ opp-microvolt-speed4 = <1020000>; + opp-microvolt-speed5 = <900000>; clock-latency-ns = <244144>; /* 8 32k periods */ -- opp-supported-hw = <0x1f>; +- opp-supported-hw = <0x3f>; + }; + + opp-1032000000 { + opp-hz = /bits/ 64 <1032000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ +- opp-supported-hw = <0x20>; }; opp-1104000000 { -@@ -60,7 +54,6 @@ - opp-microvolt-speed2 = <1000000>; +@@ -69,7 +62,6 @@ opp-microvolt-speed3 = <1000000>; + opp-microvolt-speed5 = <950000>; clock-latency-ns = <244144>; /* 8 32k periods */ -- opp-supported-hw = <0x0d>; +- opp-supported-hw = <0x2d>; }; opp-1200000000 { -@@ -71,29 +64,24 @@ - opp-microvolt-speed3 = <1050000>; +@@ -81,21 +73,18 @@ opp-microvolt-speed4 = <1100000>; + opp-microvolt-speed5 = <1020000>; clock-latency-ns = <244144>; /* 8 32k periods */ -- opp-supported-hw = <0x1f>; +- opp-supported-hw = <0x3f>; }; opp-1320000000 { @@ -71,16 +78,15 @@ opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ -- opp-supported-hw = <0x0d>; +- opp-supported-hw = <0x2d>; }; opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; -- opp-microvolt-speed1 = <1100000>; -- opp-microvolt-speed3 = <1100000>; -+ opp-microvolt = <1100000>; +@@ -104,7 +93,6 @@ + opp-microvolt-speed3 = <1100000>; + opp-microvolt-speed5 = <1160000>; clock-latency-ns = <244144>; /* 8 32k periods */ -- opp-supported-hw = <0x0a>; +- opp-supported-hw = <0x2a>; }; }; }; diff --git a/target/linux/sunxi/patches-6.6/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch b/target/linux/sunxi/patches-6.6/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch deleted file mode 100644 index ce8add18ab..0000000000 --- a/target/linux/sunxi/patches-6.6/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 951992797378a2177946400438f4d23c9fceae5b Mon Sep 17 00:00:00 2001 -From: Martin Botka -Date: Tue, 12 Sep 2023 14:25:13 +0200 -Subject: [PATCH] arm64: dts: allwinner: h616: Add SID controller node - -Add node for the H616 SID controller - -Signed-off-by: Martin Botka -Acked-by: Jernej Skrabec -Link: https://lore.kernel.org/r/20230912-sid-h616-v3-2-ee18e1c5bbb5@somainline.org -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -133,6 +133,13 @@ - #reset-cells = <1>; - }; - -+ sid: efuse@3006000 { -+ compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; -+ reg = <0x03006000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; -+ - watchdog: watchdog@30090a0 { - compatible = "allwinner,sun50i-h616-wdt", - "allwinner,sun6i-a31-wdt"; diff --git a/target/linux/sunxi/patches-6.6/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch b/target/linux/sunxi/patches-6.6/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch deleted file mode 100644 index 5f9cb0273a..0000000000 --- a/target/linux/sunxi/patches-6.6/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 898d96c5464b69af44f6407c5de81ebc349d574b Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Mon, 19 Feb 2024 15:36:33 +0000 -Subject: [PATCH] soc: sunxi: sram: export register 0 for THS on H616 - -The Allwinner H616 SoC contains a mysterious bit at register offset 0x0 -in the SRAM control block. If bit 16 is set (the reset value), the -temperature readings of the THS are way off, leading to reports about -200C, at normal ambient temperatures. Clearing this bits brings the -reported values down to the expected values. -The BSP code clears this bit in firmware (U-Boot), and has an explicit -comment about this, but offers no real explanation. - -Experiments in U-Boot show that register 0x0 has no effect on the SRAM C -visibility: all tested bit settings still allow full read and write -access by the CPU to the whole of SRAM C. Only bit 24 of the register at -offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling -the THS switch functionality as an SRAM region would not reflect reality. - -Since we should not rely on firmware settings, allow other code (the THS -driver) to access this register, by exporting it through the already -existing regmap. This mimics what we already do for the LDO control and -the EMAC register. - -To avoid concurrent accesses to the same register at the same time, by -the SRAM switch code and the regmap code, use the same lock to protect -the access. The regmap subsystem allows to use an existing lock, so we -just need to hook in there. - -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20240219153639.179814-2-andre.przywara@arm.com ---- - drivers/soc/sunxi/sunxi_sram.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - ---- a/drivers/soc/sunxi/sunxi_sram.c -+++ b/drivers/soc/sunxi/sunxi_sram.c -@@ -287,6 +287,7 @@ EXPORT_SYMBOL(sunxi_sram_release); - struct sunxi_sramc_variant { - int num_emac_clocks; - bool has_ldo_ctrl; -+ bool has_ths_offset; - }; - - static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = { -@@ -308,8 +309,10 @@ static const struct sunxi_sramc_variant - - static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = { - .num_emac_clocks = 2, -+ .has_ths_offset = true, - }; - -+#define SUNXI_SRAM_THS_OFFSET_REG 0x0 - #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30 - #define SUNXI_SYS_LDO_CTRL_REG 0x150 - -@@ -318,6 +321,8 @@ static bool sunxi_sram_regmap_accessible - { - const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev); - -+ if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset) -+ return true; - if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG && - reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4) - return true; -@@ -327,6 +332,20 @@ static bool sunxi_sram_regmap_accessible - return false; - } - -+static void sunxi_sram_lock(void *_lock) -+{ -+ spinlock_t *lock = _lock; -+ -+ spin_lock(lock); -+} -+ -+static void sunxi_sram_unlock(void *_lock) -+{ -+ spinlock_t *lock = _lock; -+ -+ spin_unlock(lock); -+} -+ - static struct regmap_config sunxi_sram_regmap_config = { - .reg_bits = 32, - .val_bits = 32, -@@ -336,6 +355,9 @@ static struct regmap_config sunxi_sram_r - /* other devices have no business accessing other registers */ - .readable_reg = sunxi_sram_regmap_accessible_reg, - .writeable_reg = sunxi_sram_regmap_accessible_reg, -+ .lock = sunxi_sram_lock, -+ .unlock = sunxi_sram_unlock, -+ .lock_arg = &sram_lock, - }; - - static int __init sunxi_sram_probe(struct platform_device *pdev) diff --git a/target/linux/sunxi/patches-6.6/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch b/target/linux/sunxi/patches-6.6/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch deleted file mode 100644 index 66f576eb38..0000000000 --- a/target/linux/sunxi/patches-6.6/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch +++ /dev/null @@ -1,47 +0,0 @@ -From ebbf19e36d021f253425344b4d4b987f3b7d9be5 Mon Sep 17 00:00:00 2001 -From: Maxim Kiselev -Date: Mon, 18 Dec 2023 00:06:23 +0300 -Subject: [PATCH] thermal/drivers/sun8i: Add D1/T113s THS controller support - -This patch adds a thermal sensor controller support for the D1/T113s, -which is similar to the one on H6, but with only one sensor and -different scale and offset values. - -Signed-off-by: Maxim Kiselev -Acked-by: Jernej Skrabec -Reviewed-by: Andre Przywara -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20231217210629.131486-3-bigunclemax@gmail.com ---- - drivers/thermal/sun8i_thermal.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -606,6 +606,18 @@ static const struct ths_thermal_chip sun - .calc_temp = sun8i_ths_calc_temp, - }; - -+static const struct ths_thermal_chip sun20i_d1_ths = { -+ .sensor_num = 1, -+ .has_bus_clk_reset = true, -+ .offset = 188552, -+ .scale = 673, -+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA, -+ .calibrate = sun50i_h6_ths_calibrate, -+ .init = sun50i_h6_thermal_init, -+ .irq_ack = sun50i_h6_irq_ack, -+ .calc_temp = sun8i_ths_calc_temp, -+}; -+ - static const struct of_device_id of_ths_match[] = { - { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, - { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, -@@ -614,6 +626,7 @@ static const struct of_device_id of_ths_ - { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths }, - { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths }, - { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, -+ { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths }, - { /* sentinel */ }, - }; - MODULE_DEVICE_TABLE(of, of_ths_match); diff --git a/target/linux/sunxi/patches-6.6/011-v6.9-thermal-drivers-sun8i-Explain-unknown-H6-register-value.patch b/target/linux/sunxi/patches-6.6/011-v6.9-thermal-drivers-sun8i-Explain-unknown-H6-register-value.patch deleted file mode 100644 index b8138a3870..0000000000 --- a/target/linux/sunxi/patches-6.6/011-v6.9-thermal-drivers-sun8i-Explain-unknown-H6-register-value.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 14f118aa50fe7c7c7330f56d007ecacca487cea8 Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Mon, 19 Feb 2024 15:36:35 +0000 -Subject: [PATCH] thermal/drivers/sun8i: Explain unknown H6 register value - -So far we were ORing in some "unknown" value into the THS control -register on the Allwinner H6. This part of the register is not explained -in the H6 manual, but the H616 manual details those bits, and on closer -inspection the THS IP blocks in both SoCs seem very close: -- The BSP code for both SoCs writes the same values into THS_CTRL. -- The reset values of at least the first three registers are the same. - -Replace the "unknown" value with its proper meaning: "acquire time", -most probably the sample part of the sample & hold circuit of the ADC, -according to its explanation in the H616 manual. - -No functional change, just a macro rename and adjustment. - -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Acked-by: Vasily Khoruzhick -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20240219153639.179814-4-andre.przywara@arm.com ---- - drivers/thermal/sun8i_thermal.c | 29 ++++++++++++++++------------- - 1 file changed, 16 insertions(+), 13 deletions(-) - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -50,7 +50,8 @@ - #define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16) - #define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8) - --#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16) -+#define SUN50I_THS_CTRL0_T_ACQ(x) (GENMASK(15, 0) & ((x) - 1)) -+#define SUN50I_THS_CTRL0_T_SAMPLE_PER(x) ((GENMASK(15, 0) & ((x) - 1)) << 16) - #define SUN50I_THS_FILTER_EN BIT(2) - #define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x)) - #define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12) -@@ -410,25 +411,27 @@ static int sun8i_h3_thermal_init(struct - return 0; - } - --/* -- * Without this undocumented value, the returned temperatures would -- * be higher than real ones by about 20C. -- */ --#define SUN50I_H6_CTRL0_UNK 0x0000002f -- - static int sun50i_h6_thermal_init(struct ths_device *tmdev) - { - int val; - - /* -- * T_acq = 20us -- * clkin = 24MHz -- * -- * x = T_acq * clkin - 1 -- * = 479 -+ * The manual recommends an overall sample frequency of 50 KHz (20us, -+ * 480 cycles at 24 MHz), which provides plenty of time for both the -+ * acquisition time (>24 cycles) and the actual conversion time -+ * (>14 cycles). -+ * The lower half of the CTRL register holds the "acquire time", in -+ * clock cycles, which the manual recommends to be 2us: -+ * 24MHz * 2us = 48 cycles. -+ * The high half of THS_CTRL encodes the sample frequency, in clock -+ * cycles: 24MHz * 20us = 480 cycles. -+ * This is explained in the H616 manual, but apparently wrongly -+ * described in the H6 manual, although the BSP code does the same -+ * for both SoCs. - */ - regmap_write(tmdev->regmap, SUN50I_THS_CTRL0, -- SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479)); -+ SUN50I_THS_CTRL0_T_ACQ(48) | -+ SUN50I_THS_CTRL0_T_SAMPLE_PER(480)); - /* average over 4 samples */ - regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC, - SUN50I_THS_FILTER_EN | diff --git a/target/linux/sunxi/patches-6.6/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch b/target/linux/sunxi/patches-6.6/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch deleted file mode 100644 index a0dbad48c9..0000000000 --- a/target/linux/sunxi/patches-6.6/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 6c04a419a4c5fb18edefc44dd676fb95c7f6c55d Mon Sep 17 00:00:00 2001 -From: Maksim Kiselev -Date: Mon, 19 Feb 2024 15:36:36 +0000 -Subject: [PATCH] thermal/drivers/sun8i: Extend H6 calibration to support 4 - sensors - -The H616 SoC resembles the H6 thermal sensor controller, with a few -changes like four sensors. - -Extend sun50i_h6_ths_calibrate() function to support calibration of -these sensors. - -Co-developed-by: Martin Botka -Signed-off-by: Martin Botka -Signed-off-by: Maksim Kiselev -Reviewed-by: Andre Przywara -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Acked-by: Vasily Khoruzhick -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20240219153639.179814-5-andre.przywara@arm.com ---- - drivers/thermal/sun8i_thermal.c | 28 ++++++++++++++++++++-------- - 1 file changed, 20 insertions(+), 8 deletions(-) - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -222,16 +222,21 @@ static int sun50i_h6_ths_calibrate(struc - struct device *dev = tmdev->dev; - int i, ft_temp; - -- if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num) -+ if (!caldata[0]) - return -EINVAL; - - /* - * efuse layout: - * -- * 0 11 16 32 -- * +-------+-------+-------+ -- * |temp| |sensor0|sensor1| -- * +-------+-------+-------+ -+ * 0 11 16 27 32 43 48 57 -+ * +----------+-----------+-----------+-----------+ -+ * | temp | |sensor0| |sensor1| |sensor2| | -+ * +----------+-----------+-----------+-----------+ -+ * ^ ^ ^ -+ * | | | -+ * | | sensor3[11:8] -+ * | sensor3[7:4] -+ * sensor3[3:0] - * - * The calibration data on the H6 is the ambient temperature and - * sensor values that are filled during the factory test stage. -@@ -244,9 +249,16 @@ static int sun50i_h6_ths_calibrate(struc - ft_temp = (caldata[0] & FT_TEMP_MASK) * 100; - - for (i = 0; i < tmdev->chip->sensor_num; i++) { -- int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK; -- int cdata, offset; -- int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg); -+ int sensor_reg, sensor_temp, cdata, offset; -+ -+ if (i == 3) -+ sensor_reg = (caldata[1] >> 12) -+ | ((caldata[2] >> 12) << 4) -+ | ((caldata[3] >> 12) << 8); -+ else -+ sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK; -+ -+ sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg); - - /* - * Calibration data is CALIBRATE_DEFAULT - (calculated diff --git a/target/linux/sunxi/patches-6.6/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch b/target/linux/sunxi/patches-6.6/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch deleted file mode 100644 index 9b5e9d374f..0000000000 --- a/target/linux/sunxi/patches-6.6/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch +++ /dev/null @@ -1,126 +0,0 @@ -From f8b54d1120b81ed57bed96cc8e814ba08886d1e5 Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Mon, 19 Feb 2024 15:36:37 +0000 -Subject: [PATCH] thermal/drivers/sun8i: Add SRAM register access code - -The Allwinner H616 SoC needs to clear a bit in one register in the SRAM -controller, to report reasonable temperature values. On reset, bit 16 in -register 0x3000000 is set, which leads to the driver reporting -temperatures around 200C. Clearing this bit brings the values down to the -expected range. The BSP code does a one-time write in U-Boot, with a -comment just mentioning the effect on the THS, but offering no further -explanation. - -To not rely on firmware to set things up for us, add code that queries -the SRAM controller device via a DT phandle link, then clear just this -single bit. - -Signed-off-by: Andre Przywara -Acked-by: Vasily Khoruzhick -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20240219153639.179814-6-andre.przywara@arm.com ---- - drivers/thermal/sun8i_thermal.c | 51 +++++++++++++++++++++++++++++++++ - 1 file changed, 51 insertions(+) - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -66,6 +67,7 @@ struct tsensor { - struct ths_thermal_chip { - bool has_mod_clk; - bool has_bus_clk_reset; -+ bool needs_sram; - int sensor_num; - int offset; - int scale; -@@ -83,12 +85,16 @@ struct ths_device { - const struct ths_thermal_chip *chip; - struct device *dev; - struct regmap *regmap; -+ struct regmap_field *sram_regmap_field; - struct reset_control *reset; - struct clk *bus_clk; - struct clk *mod_clk; - struct tsensor sensor[MAX_SENSOR_NUM]; - }; - -+/* The H616 needs to have a bit 16 in the SRAM control register cleared. */ -+static const struct reg_field sun8i_ths_sram_reg_field = REG_FIELD(0x0, 16, 16); -+ - /* Temp Unit: millidegree Celsius */ - static int sun8i_ths_calc_temp(struct ths_device *tmdev, - int id, int reg) -@@ -337,6 +343,34 @@ static void sun8i_ths_reset_control_asse - reset_control_assert(data); - } - -+static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node) -+{ -+ struct device_node *sram_node; -+ struct platform_device *sram_pdev; -+ struct regmap *regmap = NULL; -+ -+ sram_node = of_parse_phandle(node, "allwinner,sram", 0); -+ if (!sram_node) -+ return ERR_PTR(-ENODEV); -+ -+ sram_pdev = of_find_device_by_node(sram_node); -+ if (!sram_pdev) { -+ /* platform device might not be probed yet */ -+ regmap = ERR_PTR(-EPROBE_DEFER); -+ goto out_put_node; -+ } -+ -+ /* If no regmap is found then the other device driver is at fault */ -+ regmap = dev_get_regmap(&sram_pdev->dev, NULL); -+ if (!regmap) -+ regmap = ERR_PTR(-EINVAL); -+ -+ platform_device_put(sram_pdev); -+out_put_node: -+ of_node_put(sram_node); -+ return regmap; -+} -+ - static int sun8i_ths_resource_init(struct ths_device *tmdev) - { - struct device *dev = tmdev->dev; -@@ -381,6 +415,19 @@ static int sun8i_ths_resource_init(struc - if (ret) - return ret; - -+ if (tmdev->chip->needs_sram) { -+ struct regmap *regmap; -+ -+ regmap = sun8i_ths_get_sram_regmap(dev->of_node); -+ if (IS_ERR(regmap)) -+ return PTR_ERR(regmap); -+ tmdev->sram_regmap_field = devm_regmap_field_alloc(dev, -+ regmap, -+ sun8i_ths_sram_reg_field); -+ if (IS_ERR(tmdev->sram_regmap_field)) -+ return PTR_ERR(tmdev->sram_regmap_field); -+ } -+ - ret = sun8i_ths_calibrate(tmdev); - if (ret) - return ret; -@@ -427,6 +474,10 @@ static int sun50i_h6_thermal_init(struct - { - int val; - -+ /* The H616 needs to have a bit in the SRAM control register cleared. */ -+ if (tmdev->sram_regmap_field) -+ regmap_field_write(tmdev->sram_regmap_field, 0); -+ - /* - * The manual recommends an overall sample frequency of 50 KHz (20us, - * 480 cycles at 24 MHz), which provides plenty of time for both the diff --git a/target/linux/sunxi/patches-6.6/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch b/target/linux/sunxi/patches-6.6/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch deleted file mode 100644 index 187bc0dd7b..0000000000 --- a/target/linux/sunxi/patches-6.6/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch +++ /dev/null @@ -1,50 +0,0 @@ -From e7dbfa19572a1440a2e67ef70f94ff204849a0a8 Mon Sep 17 00:00:00 2001 -From: Martin Botka -Date: Mon, 19 Feb 2024 15:36:38 +0000 -Subject: [PATCH] thermal/drivers/sun8i: Add support for H616 THS controller - -Add support for the thermal sensor found in H616 SoCs, is the same as -the H6 thermal sensor controller, but with four sensors. -Also the registers readings are wrong, unless a bit in the first SYS_CFG -register cleared, so set exercise the SRAM regmap to take care of that. - -Signed-off-by: Martin Botka -Signed-off-by: Andre Przywara -Acked-by: Vasily Khoruzhick -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20240219153639.179814-7-andre.przywara@arm.com ---- - drivers/thermal/sun8i_thermal.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -684,6 +684,20 @@ static const struct ths_thermal_chip sun - .calc_temp = sun8i_ths_calc_temp, - }; - -+static const struct ths_thermal_chip sun50i_h616_ths = { -+ .sensor_num = 4, -+ .has_bus_clk_reset = true, -+ .needs_sram = true, -+ .ft_deviation = 8000, -+ .offset = 263655, -+ .scale = 810, -+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA, -+ .calibrate = sun50i_h6_ths_calibrate, -+ .init = sun50i_h6_thermal_init, -+ .irq_ack = sun50i_h6_irq_ack, -+ .calc_temp = sun8i_ths_calc_temp, -+}; -+ - static const struct of_device_id of_ths_match[] = { - { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, - { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, -@@ -693,6 +707,7 @@ static const struct of_device_id of_ths_ - { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths }, - { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, - { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths }, -+ { .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths }, - { /* sentinel */ }, - }; - MODULE_DEVICE_TABLE(of, of_ths_match); diff --git a/target/linux/sunxi/patches-6.6/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch b/target/linux/sunxi/patches-6.6/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch deleted file mode 100644 index dd18cd953c..0000000000 --- a/target/linux/sunxi/patches-6.6/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 9ac53d5532cc4bb595bbee86ccba2172ccc336c3 Mon Sep 17 00:00:00 2001 -From: Mark Brown -Date: Tue, 23 Jan 2024 23:33:07 +0000 -Subject: [PATCH] thermal/drivers/sun8i: Don't fail probe due to zone - registration failure - -Currently the sun8i thermal driver will fail to probe if any of the -thermal zones it is registering fails to register with the thermal core. -Since we currently do not define any trip points for the GPU thermal -zones on at least A64 or H5 this means that we have no thermal support -on these platforms: - -[ 1.698703] thermal_sys: Failed to find 'trips' node -[ 1.698707] thermal_sys: Failed to find trip points for thermal-sensor id=1 - -even though the main CPU thermal zone on both SoCs is fully configured. -This does not seem ideal, while we may not be able to use all the zones -it seems better to have those zones which are usable be operational. -Instead just carry on registering zones if we get any non-deferral -error, allowing use of those zones which are usable. - -This means that we also need to update the interrupt handler to not -attempt to notify the core for events on zones which we have not -registered, I didn't see an ability to mask individual interrupts and -I would expect that interrupts would still be indicated in the ISR even -if they were masked. - -Reviewed-by: Vasily Khoruzhick -Acked-by: Jernej Skrabec -Signed-off-by: Mark Brown -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20240123-thermal-sun8i-registration-v3-1-3e5771b1bbdd@kernel.org ---- - drivers/thermal/sun8i_thermal.c | 16 ++++++++++++++-- - 1 file changed, 14 insertions(+), 2 deletions(-) - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -195,6 +195,9 @@ static irqreturn_t sun8i_irq_thread(int - int i; - - for_each_set_bit(i, &irq_bitmap, tmdev->chip->sensor_num) { -+ /* We allow some zones to not register. */ -+ if (IS_ERR(tmdev->sensor[i].tzd)) -+ continue; - thermal_zone_device_update(tmdev->sensor[i].tzd, - THERMAL_EVENT_UNSPECIFIED); - } -@@ -531,8 +534,17 @@ static int sun8i_ths_register(struct ths - i, - &tmdev->sensor[i], - &ths_ops); -- if (IS_ERR(tmdev->sensor[i].tzd)) -- return PTR_ERR(tmdev->sensor[i].tzd); -+ -+ /* -+ * If an individual zone fails to register for reasons -+ * other than probe deferral (eg, a bad DT) then carry -+ * on, other zones might register successfully. -+ */ -+ if (IS_ERR(tmdev->sensor[i].tzd)) { -+ if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER) -+ return PTR_ERR(tmdev->sensor[i].tzd); -+ continue; -+ } - - devm_thermal_add_hwmon_sysfs(tmdev->dev, tmdev->sensor[i].tzd); - } diff --git a/target/linux/sunxi/patches-6.6/016-v6.9-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch b/target/linux/sunxi/patches-6.6/016-v6.9-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch deleted file mode 100644 index cd6542bf14..0000000000 --- a/target/linux/sunxi/patches-6.6/016-v6.9-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch +++ /dev/null @@ -1,138 +0,0 @@ -From f4318af40544b8e7ff5a6b667ede60e6cf808262 Mon Sep 17 00:00:00 2001 -From: Martin Botka -Date: Mon, 19 Feb 2024 15:36:39 +0000 -Subject: [PATCH] arm64: dts: allwinner: h616: Add thermal sensor and zones - -There are four thermal sensors: -- CPU -- GPU -- VE -- DRAM - -Add the thermal sensor configuration and the thermal zones. - -Signed-off-by: Martin Botka -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Link: https://lore.kernel.org/r/20240219153639.179814-8-andre.przywara@arm.com -Signed-off-by: Jernej Skrabec ---- - .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 88 +++++++++++++++++++ - 1 file changed, 88 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - - / { - interrupt-parent = <&gic>; -@@ -138,6 +139,10 @@ - reg = <0x03006000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ ths_calibration: thermal-sensor-calibration@14 { -+ reg = <0x14 0x8>; -+ }; - }; - - watchdog: watchdog@30090a0 { -@@ -511,6 +516,19 @@ - }; - }; - -+ ths: thermal-sensor@5070400 { -+ compatible = "allwinner,sun50i-h616-ths"; -+ reg = <0x05070400 0x400>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_THS>; -+ clock-names = "bus"; -+ resets = <&ccu RST_BUS_THS>; -+ nvmem-cells = <&ths_calibration>; -+ nvmem-cell-names = "calibration"; -+ allwinner,sram = <&syscon>; -+ #thermal-sensor-cells = <1>; -+ }; -+ - usbotg: usb@5100000 { - compatible = "allwinner,sun50i-h616-musb", - "allwinner,sun8i-h3-musb"; -@@ -755,4 +773,74 @@ - #size-cells = <0>; - }; - }; -+ -+ thermal-zones { -+ cpu-thermal { -+ polling-delay-passive = <500>; -+ polling-delay = <1000>; -+ thermal-sensors = <&ths 2>; -+ sustainable-power = <1000>; -+ -+ trips { -+ cpu_threshold: cpu-trip-0 { -+ temperature = <60000>; -+ type = "passive"; -+ hysteresis = <0>; -+ }; -+ cpu_target: cpu-trip-1 { -+ temperature = <70000>; -+ type = "passive"; -+ hysteresis = <0>; -+ }; -+ cpu_critical: cpu-trip-2 { -+ temperature = <110000>; -+ type = "critical"; -+ hysteresis = <0>; -+ }; -+ }; -+ }; -+ -+ gpu-thermal { -+ polling-delay-passive = <500>; -+ polling-delay = <1000>; -+ thermal-sensors = <&ths 0>; -+ sustainable-power = <1100>; -+ -+ trips { -+ gpu_temp_critical: gpu-trip-0 { -+ temperature = <110000>; -+ type = "critical"; -+ hysteresis = <0>; -+ }; -+ }; -+ }; -+ -+ ve-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 1>; -+ -+ trips { -+ ve_temp_critical: ve-trip-0 { -+ temperature = <110000>; -+ type = "critical"; -+ hysteresis = <0>; -+ }; -+ }; -+ }; -+ -+ ddr-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 3>; -+ -+ trips { -+ ddr_temp_critical: ddr-trip-0 { -+ temperature = <110000>; -+ type = "critical"; -+ hysteresis = <0>; -+ }; -+ }; -+ }; -+ }; - }; diff --git a/target/linux/sunxi/patches-6.6/017-v6.10-firmware-smccc-Export-revision-soc_id-function.patch b/target/linux/sunxi/patches-6.6/017-v6.10-firmware-smccc-Export-revision-soc_id-function.patch deleted file mode 100644 index aacd0ba906..0000000000 --- a/target/linux/sunxi/patches-6.6/017-v6.10-firmware-smccc-Export-revision-soc_id-function.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 9cf3415ade2d7598d78d2ce6d35d6d6d06132201 Mon Sep 17 00:00:00 2001 -From: Martin Botka -Date: Thu, 18 Apr 2024 16:44:01 +0100 -Subject: [PATCH] firmware: smccc: Export revision soc_id function - -The "SoC ID revision" as provided via the SMCCC SOCID interface can be -valuable information for drivers, when certain functionality depends -on a die revision, for instance. -One example is the sun50i-cpufreq-nvmem driver, which needs this -information to determine the speed bin of the SoC. - -Export the arm_smccc_get_soc_id_revision() function so that it can be -called by any driver. - -Signed-off-by: Martin Botka -Signed-off-by: Andre Przywara -Acked-by: Sudeep Holla -Signed-off-by: Viresh Kumar ---- - drivers/firmware/smccc/smccc.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/firmware/smccc/smccc.c -+++ b/drivers/firmware/smccc/smccc.c -@@ -65,6 +65,7 @@ s32 arm_smccc_get_soc_id_revision(void) - { - return smccc_soc_id_revision; - } -+EXPORT_SYMBOL_GPL(arm_smccc_get_soc_id_revision); - - static int __init smccc_devices_init(void) - { diff --git a/target/linux/sunxi/patches-6.6/018-v6.10-cpufreq-dt-platdev-Blocklist-Allwinner-H616-618-SoCs.patch b/target/linux/sunxi/patches-6.6/018-v6.10-cpufreq-dt-platdev-Blocklist-Allwinner-H616-618-SoCs.patch deleted file mode 100644 index d67b35ee71..0000000000 --- a/target/linux/sunxi/patches-6.6/018-v6.10-cpufreq-dt-platdev-Blocklist-Allwinner-H616-618-SoCs.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 6ae07744cf334b750762ba881492c0cfba524b38 Mon Sep 17 00:00:00 2001 -From: Martin Botka -Date: Thu, 18 Apr 2024 16:44:02 +0100 -Subject: [PATCH] cpufreq: dt-platdev: Blocklist Allwinner H616/618 SoCs - -The AllWinner H616 SoC will use the (extended) H6 OPP driver, so add -them to the cpufreq-dt blocklist, to not create the device twice. -This also affects the closely related sibling SoCs H618 and H700. - -Signed-off-by: Martin Botka -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/cpufreq-dt-platdev.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/cpufreq/cpufreq-dt-platdev.c -+++ b/drivers/cpufreq/cpufreq-dt-platdev.c -@@ -104,6 +104,9 @@ static const struct of_device_id allowli - */ - static const struct of_device_id blocklist[] __initconst = { - { .compatible = "allwinner,sun50i-h6", }, -+ { .compatible = "allwinner,sun50i-h616", }, -+ { .compatible = "allwinner,sun50i-h618", }, -+ { .compatible = "allwinner,sun50i-h700", }, - - { .compatible = "apple,arm-platform", }, - diff --git a/target/linux/sunxi/patches-6.6/019-v6.10-cpufreq-sun50i-Refactor-speed-bin-decoding.patch b/target/linux/sunxi/patches-6.6/019-v6.10-cpufreq-sun50i-Refactor-speed-bin-decoding.patch deleted file mode 100644 index 9a81906996..0000000000 --- a/target/linux/sunxi/patches-6.6/019-v6.10-cpufreq-sun50i-Refactor-speed-bin-decoding.patch +++ /dev/null @@ -1,149 +0,0 @@ -From 6cc4bcceff9af0e6be9738096d95e4ba75e75123 Mon Sep 17 00:00:00 2001 -From: Brandon Cheo Fusi -Date: Thu, 18 Apr 2024 16:44:04 +0100 -Subject: [PATCH] cpufreq: sun50i: Refactor speed bin decoding - -Make converting the speed bin value into a speed grade generic and -determined by a platform specific callback. Also change the prototypes -involved to encode the speed bin directly in the return value. - -This allows to extend the driver more easily to support more SoCs. - -Signed-off-by: Brandon Cheo Fusi -[Andre: merge output into return value] -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/sun50i-cpufreq-nvmem.c | 74 +++++++++++++++++--------- - 1 file changed, 49 insertions(+), 25 deletions(-) - ---- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c -+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c -@@ -25,19 +25,52 @@ - - static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev; - -+struct sunxi_cpufreq_data { -+ u32 (*efuse_xlate)(u32 speedbin); -+}; -+ -+static u32 sun50i_h6_efuse_xlate(u32 speedbin) -+{ -+ u32 efuse_value; -+ -+ efuse_value = (speedbin >> NVMEM_SHIFT) & NVMEM_MASK; -+ -+ /* -+ * We treat unexpected efuse values as if the SoC was from -+ * the slowest bin. Expected efuse values are 1-3, slowest -+ * to fastest. -+ */ -+ if (efuse_value >= 1 && efuse_value <= 3) -+ return efuse_value - 1; -+ else -+ return 0; -+} -+ -+static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = { -+ .efuse_xlate = sun50i_h6_efuse_xlate, -+}; -+ -+static const struct of_device_id cpu_opp_match_list[] = { -+ { .compatible = "allwinner,sun50i-h6-operating-points", -+ .data = &sun50i_h6_cpufreq_data, -+ }, -+ {} -+}; -+ - /** - * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value -- * @versions: Set to the value parsed from efuse - * -- * Returns 0 if success. -+ * Returns non-negative speed bin index on success, a negative error -+ * value otherwise. - */ --static int sun50i_cpufreq_get_efuse(u32 *versions) -+static int sun50i_cpufreq_get_efuse(void) - { -+ const struct sunxi_cpufreq_data *opp_data; - struct nvmem_cell *speedbin_nvmem; -+ const struct of_device_id *match; - struct device_node *np; - struct device *cpu_dev; -- u32 *speedbin, efuse_value; -- size_t len; -+ u32 *speedbin; - int ret; - - cpu_dev = get_cpu_device(0); -@@ -48,12 +81,12 @@ static int sun50i_cpufreq_get_efuse(u32 - if (!np) - return -ENOENT; - -- ret = of_device_is_compatible(np, -- "allwinner,sun50i-h6-operating-points"); -- if (!ret) { -+ match = of_match_node(cpu_opp_match_list, np); -+ if (!match) { - of_node_put(np); - return -ENOENT; - } -+ opp_data = match->data; - - speedbin_nvmem = of_nvmem_cell_get(np, NULL); - of_node_put(np); -@@ -61,25 +94,16 @@ static int sun50i_cpufreq_get_efuse(u32 - return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem), - "Could not get nvmem cell\n"); - -- speedbin = nvmem_cell_read(speedbin_nvmem, &len); -+ speedbin = nvmem_cell_read(speedbin_nvmem, NULL); - nvmem_cell_put(speedbin_nvmem); - if (IS_ERR(speedbin)) - return PTR_ERR(speedbin); - -- efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK; -- -- /* -- * We treat unexpected efuse values as if the SoC was from -- * the slowest bin. Expected efuse values are 1-3, slowest -- * to fastest. -- */ -- if (efuse_value >= 1 && efuse_value <= 3) -- *versions = efuse_value - 1; -- else -- *versions = 0; -+ ret = opp_data->efuse_xlate(*speedbin); - - kfree(speedbin); -- return 0; -+ -+ return ret; - }; - - static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev) -@@ -87,7 +111,7 @@ static int sun50i_cpufreq_nvmem_probe(st - int *opp_tokens; - char name[MAX_NAME_LEN]; - unsigned int cpu; -- u32 speed = 0; -+ int speed; - int ret; - - opp_tokens = kcalloc(num_possible_cpus(), sizeof(*opp_tokens), -@@ -95,10 +119,10 @@ static int sun50i_cpufreq_nvmem_probe(st - if (!opp_tokens) - return -ENOMEM; - -- ret = sun50i_cpufreq_get_efuse(&speed); -- if (ret) { -+ speed = sun50i_cpufreq_get_efuse(); -+ if (speed < 0) { - kfree(opp_tokens); -- return ret; -+ return speed; - } - - snprintf(name, MAX_NAME_LEN, "speed%d", speed); diff --git a/target/linux/sunxi/patches-6.6/020-v6.10-cpufreq-sun50i-Add-support-for-opp_supported_hw.patch b/target/linux/sunxi/patches-6.6/020-v6.10-cpufreq-sun50i-Add-support-for-opp_supported_hw.patch deleted file mode 100644 index e0c68f9aad..0000000000 --- a/target/linux/sunxi/patches-6.6/020-v6.10-cpufreq-sun50i-Add-support-for-opp_supported_hw.patch +++ /dev/null @@ -1,132 +0,0 @@ -From fa5aec9561cfc4f4370983ca5818c90227c9d90e Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Thu, 18 Apr 2024 16:44:05 +0100 -Subject: [PATCH] cpufreq: sun50i: Add support for opp_supported_hw - -The opp_supported_hw DT property allows the DT to specify a mask of chip -revisions that a certain OPP is eligible for. This allows for easy -limiting of maximum frequencies, for instance. - -Add support for that in the sun50i-cpufreq-nvmem driver. We support both -the existing opp-microvolt suffix properties as well as the -opp-supported-hw property, the generic code figures out which is needed -automatically. -However if none of the DT OPP nodes contain an opp-supported-hw -property, the core code will ignore all OPPs and the driver will fail -probing. So check the DT's eligibility first before using that feature. - -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/sun50i-cpufreq-nvmem.c | 62 ++++++++++++++++++++++---- - 1 file changed, 54 insertions(+), 8 deletions(-) - ---- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c -+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c -@@ -58,6 +58,41 @@ static const struct of_device_id cpu_opp - }; - - /** -+ * dt_has_supported_hw() - Check if any OPPs use opp-supported-hw -+ * -+ * If we ask the cpufreq framework to use the opp-supported-hw feature, it -+ * will ignore every OPP node without that DT property. If none of the OPPs -+ * have it, the driver will fail probing, due to the lack of OPPs. -+ * -+ * Returns true if we have at least one OPP with the opp-supported-hw property. -+ */ -+static bool dt_has_supported_hw(void) -+{ -+ bool has_opp_supported_hw = false; -+ struct device_node *np, *opp; -+ struct device *cpu_dev; -+ -+ cpu_dev = get_cpu_device(0); -+ if (!cpu_dev) -+ return -ENODEV; -+ -+ np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); -+ if (!np) -+ return -ENOENT; -+ -+ for_each_child_of_node(np, opp) { -+ if (of_find_property(opp, "opp-supported-hw", NULL)) { -+ has_opp_supported_hw = true; -+ break; -+ } -+ } -+ -+ of_node_put(np); -+ -+ return has_opp_supported_hw; -+} -+ -+/** - * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value - * - * Returns non-negative speed bin index on success, a negative error -@@ -110,7 +145,8 @@ static int sun50i_cpufreq_nvmem_probe(st - { - int *opp_tokens; - char name[MAX_NAME_LEN]; -- unsigned int cpu; -+ unsigned int cpu, supported_hw; -+ struct dev_pm_opp_config config = {}; - int speed; - int ret; - -@@ -125,7 +161,18 @@ static int sun50i_cpufreq_nvmem_probe(st - return speed; - } - -+ /* -+ * We need at least one OPP with the "opp-supported-hw" property, -+ * or else the upper layers will ignore every OPP and will bail out. -+ */ -+ if (dt_has_supported_hw()) { -+ supported_hw = 1U << speed; -+ config.supported_hw = &supported_hw; -+ config.supported_hw_count = 1; -+ } -+ - snprintf(name, MAX_NAME_LEN, "speed%d", speed); -+ config.prop_name = name; - - for_each_possible_cpu(cpu) { - struct device *cpu_dev = get_cpu_device(cpu); -@@ -135,12 +182,11 @@ static int sun50i_cpufreq_nvmem_probe(st - goto free_opp; - } - -- opp_tokens[cpu] = dev_pm_opp_set_prop_name(cpu_dev, name); -- if (opp_tokens[cpu] < 0) { -- ret = opp_tokens[cpu]; -- pr_err("Failed to set prop name\n"); -+ ret = dev_pm_opp_set_config(cpu_dev, &config); -+ if (ret < 0) - goto free_opp; -- } -+ -+ opp_tokens[cpu] = ret; - } - - cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, -@@ -155,7 +201,7 @@ static int sun50i_cpufreq_nvmem_probe(st - - free_opp: - for_each_possible_cpu(cpu) -- dev_pm_opp_put_prop_name(opp_tokens[cpu]); -+ dev_pm_opp_clear_config(opp_tokens[cpu]); - kfree(opp_tokens); - - return ret; -@@ -169,7 +215,7 @@ static void sun50i_cpufreq_nvmem_remove( - platform_device_unregister(cpufreq_dt_pdev); - - for_each_possible_cpu(cpu) -- dev_pm_opp_put_prop_name(opp_tokens[cpu]); -+ dev_pm_opp_clear_config(opp_tokens[cpu]); - - kfree(opp_tokens); - } diff --git a/target/linux/sunxi/patches-6.6/021-v6.10-cpufreq-sun50i-Add-H616-support.patch b/target/linux/sunxi/patches-6.6/021-v6.10-cpufreq-sun50i-Add-H616-support.patch deleted file mode 100644 index c891f5722a..0000000000 --- a/target/linux/sunxi/patches-6.6/021-v6.10-cpufreq-sun50i-Add-H616-support.patch +++ /dev/null @@ -1,122 +0,0 @@ -From e2e2dcd2e944fe6167cb731864f8a1343f1bbee7 Mon Sep 17 00:00:00 2001 -From: Martin Botka -Date: Thu, 18 Apr 2024 16:44:06 +0100 -Subject: [PATCH] cpufreq: sun50i: Add H616 support - -The Allwinner H616/H618 SoCs have different OPP tables per SoC version -and die revision. The SoC version is stored in NVMEM, as before, though -encoded differently. The die revision is in a different register, in the -SRAM controller. Firmware already exports that value in a standardised -way, through the SMCCC SoCID mechanism. We need both values, as some chips -have the same SoC version, but they don't support the same frequencies and -they get differentiated by the die revision. - -Add the new compatible string and tie the new translation function to -it. This mechanism not only covers the original H616 SoC, but also its -very close sibling SoCs H618 and H700, so add them to the list as well. - -Signed-off-by: Martin Botka -Signed-off-by: Andre Przywara -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/sun50i-cpufreq-nvmem.c | 67 ++++++++++++++++++++++++++ - 1 file changed, 67 insertions(+) - ---- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c -+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c -@@ -10,6 +10,7 @@ - - #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -+#include - #include - #include - #include -@@ -46,14 +47,77 @@ static u32 sun50i_h6_efuse_xlate(u32 spe - return 0; - } - -+static int get_soc_id_revision(void) -+{ -+#ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY -+ return arm_smccc_get_soc_id_revision(); -+#else -+ return SMCCC_RET_NOT_SUPPORTED; -+#endif -+} -+ -+/* -+ * Judging by the OPP tables in the vendor BSP, the quality order of the -+ * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best. -+ * 0 and 2 seem identical from the OPP tables' point of view. -+ */ -+static u32 sun50i_h616_efuse_xlate(u32 speedbin) -+{ -+ int ver_bits = get_soc_id_revision(); -+ u32 value = 0; -+ -+ switch (speedbin & 0xffff) { -+ case 0x2000: -+ value = 0; -+ break; -+ case 0x2400: -+ case 0x7400: -+ case 0x2c00: -+ case 0x7c00: -+ if (ver_bits != SMCCC_RET_NOT_SUPPORTED && ver_bits <= 1) { -+ /* ic version A/B */ -+ value = 1; -+ } else { -+ /* ic version C and later version */ -+ value = 2; -+ } -+ break; -+ case 0x5000: -+ case 0x5400: -+ case 0x6000: -+ value = 3; -+ break; -+ case 0x5c00: -+ value = 4; -+ break; -+ case 0x5d00: -+ value = 0; -+ break; -+ default: -+ pr_warn("sun50i-cpufreq-nvmem: unknown speed bin 0x%x, using default bin 0\n", -+ speedbin & 0xffff); -+ value = 0; -+ break; -+ } -+ -+ return value; -+} -+ - static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = { - .efuse_xlate = sun50i_h6_efuse_xlate, - }; - -+static struct sunxi_cpufreq_data sun50i_h616_cpufreq_data = { -+ .efuse_xlate = sun50i_h616_efuse_xlate, -+}; -+ - static const struct of_device_id cpu_opp_match_list[] = { - { .compatible = "allwinner,sun50i-h6-operating-points", - .data = &sun50i_h6_cpufreq_data, - }, -+ { .compatible = "allwinner,sun50i-h616-operating-points", -+ .data = &sun50i_h616_cpufreq_data, -+ }, - {} - }; - -@@ -230,6 +294,9 @@ static struct platform_driver sun50i_cpu - - static const struct of_device_id sun50i_cpufreq_match_list[] = { - { .compatible = "allwinner,sun50i-h6" }, -+ { .compatible = "allwinner,sun50i-h616" }, -+ { .compatible = "allwinner,sun50i-h618" }, -+ { .compatible = "allwinner,sun50i-h700" }, - {} - }; - MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list); diff --git a/target/linux/sunxi/patches-6.6/022-v6.10-arm64-dts-allwinner-h616-Add-CPU-OPPs-table.patch b/target/linux/sunxi/patches-6.6/022-v6.10-arm64-dts-allwinner-h616-Add-CPU-OPPs-table.patch deleted file mode 100644 index 4665286d0f..0000000000 --- a/target/linux/sunxi/patches-6.6/022-v6.10-arm64-dts-allwinner-h616-Add-CPU-OPPs-table.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 3e057e05b3b281bcc29db573eb51f87ee6b5afc0 Mon Sep 17 00:00:00 2001 -From: Martin Botka -Date: Thu, 18 Apr 2024 16:44:07 +0100 -Subject: [PATCH] arm64: dts: allwinner: h616: Add CPU OPPs table - -Add an Operating Performance Points table for the CPU cores to enable -Dynamic Voltage & Frequency Scaling (DVFS) on the H616. -The values were taken from the BSP sources. There is a separate OPP set -seen on some H700 devices, but they didn't really work out in testing, so -they are not included for now. - -Also add the needed cpu_speed_grade nvmem cell and the cooling cells -properties, to enable passive cooling. - -Signed-off-by: Martin Botka -[Andre: rework to minimise opp-microvolt properties] -Signed-off-by: Andre Przywara -Acked-by: Jernej Skrabec -Signed-off-by: Viresh Kumar ---- - .../dts/allwinner/sun50i-h616-cpu-opp.dtsi | 115 ++++++++++++++++++ - .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 8 ++ - 2 files changed, 123 insertions(+) - create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi - ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi -@@ -0,0 +1,115 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+// Copyright (C) 2023 Martin Botka -+ -+/ { -+ cpu_opp_table: opp-table-cpu { -+ compatible = "allwinner,sun50i-h616-operating-points"; -+ nvmem-cells = <&cpu_speed_grade>; -+ opp-shared; -+ -+ opp-480000000 { -+ opp-hz = /bits/ 64 <480000000>; -+ opp-microvolt = <900000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ opp-supported-hw = <0x1f>; -+ }; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <900000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ opp-supported-hw = <0x12>; -+ }; -+ -+ opp-720000000 { -+ opp-hz = /bits/ 64 <720000000>; -+ opp-microvolt = <900000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ opp-supported-hw = <0x0d>; -+ }; -+ -+ opp-792000000 { -+ opp-hz = /bits/ 64 <792000000>; -+ opp-microvolt-speed1 = <900000>; -+ opp-microvolt-speed4 = <940000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ opp-supported-hw = <0x12>; -+ }; -+ -+ opp-936000000 { -+ opp-hz = /bits/ 64 <936000000>; -+ opp-microvolt = <900000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ opp-supported-hw = <0x0d>; -+ }; -+ -+ opp-1008000000 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt-speed0 = <950000>; -+ opp-microvolt-speed1 = <940000>; -+ opp-microvolt-speed2 = <950000>; -+ opp-microvolt-speed3 = <950000>; -+ opp-microvolt-speed4 = <1020000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ opp-supported-hw = <0x1f>; -+ }; -+ -+ opp-1104000000 { -+ opp-hz = /bits/ 64 <1104000000>; -+ opp-microvolt-speed0 = <1000000>; -+ opp-microvolt-speed2 = <1000000>; -+ opp-microvolt-speed3 = <1000000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ opp-supported-hw = <0x0d>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt-speed0 = <1050000>; -+ opp-microvolt-speed1 = <1020000>; -+ opp-microvolt-speed2 = <1050000>; -+ opp-microvolt-speed3 = <1050000>; -+ opp-microvolt-speed4 = <1100000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ opp-supported-hw = <0x1f>; -+ }; -+ -+ opp-1320000000 { -+ opp-hz = /bits/ 64 <1320000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ opp-supported-hw = <0x1d>; -+ }; -+ -+ opp-1416000000 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ opp-supported-hw = <0x0d>; -+ }; -+ -+ opp-1512000000 { -+ opp-hz = /bits/ 64 <1512000000>; -+ opp-microvolt-speed1 = <1100000>; -+ opp-microvolt-speed3 = <1100000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ opp-supported-hw = <0x0a>; -+ }; -+ }; -+}; -+ -+&cpu0 { -+ operating-points-v2 = <&cpu_opp_table>; -+}; -+ -+&cpu1 { -+ operating-points-v2 = <&cpu_opp_table>; -+}; -+ -+&cpu2 { -+ operating-points-v2 = <&cpu_opp_table>; -+}; -+ -+&cpu3 { -+ operating-points-v2 = <&cpu_opp_table>; -+}; ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -26,6 +26,7 @@ - reg = <0>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; -+ #cooling-cells = <2>; - }; - - cpu1: cpu@1 { -@@ -34,6 +35,7 @@ - reg = <1>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; -+ #cooling-cells = <2>; - }; - - cpu2: cpu@2 { -@@ -42,6 +44,7 @@ - reg = <2>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; -+ #cooling-cells = <2>; - }; - - cpu3: cpu@3 { -@@ -50,6 +53,7 @@ - reg = <3>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; -+ #cooling-cells = <2>; - }; - }; - -@@ -143,6 +147,10 @@ - ths_calibration: thermal-sensor-calibration@14 { - reg = <0x14 0x8>; - }; -+ -+ cpu_speed_grade: cpu-speed-grade@0 { -+ reg = <0x0 2>; -+ }; - }; - - watchdog: watchdog@30090a0 { diff --git a/target/linux/sunxi/patches-6.6/023-v6.10-arm64-dts-allwinner-h616-enable-DVFS-for-all-boards.patch b/target/linux/sunxi/patches-6.6/023-v6.10-arm64-dts-allwinner-h616-enable-DVFS-for-all-boards.patch deleted file mode 100644 index 8c91184117..0000000000 --- a/target/linux/sunxi/patches-6.6/023-v6.10-arm64-dts-allwinner-h616-enable-DVFS-for-all-boards.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 09d0aaa0ae9c80ff9569393b206226c1008801b1 Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Thu, 18 Apr 2024 16:44:08 +0100 -Subject: [PATCH] arm64: dts: allwinner: h616: enable DVFS for all boards - -With the DT bindings now describing the format of the CPU OPP tables, we -can include the OPP table in each board's .dts file, and specify the CPU -power supply. -This allows to enable DVFS, and get up to 50% of performance benefit in -the highest OPP, or up to 60% power savings in the lowest OPP, compared -to the fixed 1GHz @ 1.0V OPP we are running in by default at the moment. - -Signed-off-by: Andre Przywara -Acked-by: Jernej Skrabec -Signed-off-by: Viresh Kumar ---- - .../boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 5 +++++ - arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 5 +++++ - arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts | 5 +++++ - .../boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi | 5 +++++ - .../arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts | 5 +++++ - arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts | 5 +++++ - .../boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts | 5 +++++ - 7 files changed, 35 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts -@@ -6,12 +6,17 @@ - /dts-v1/; - - #include "sun50i-h616-orangepi-zero.dtsi" -+#include "sun50i-h616-cpu-opp.dtsi" - - / { - model = "OrangePi Zero2"; - compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; - }; - -+&cpu0 { -+ cpu-supply = <®_dcdca>; -+}; -+ - &emac0 { - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts -@@ -6,6 +6,7 @@ - /dts-v1/; - - #include "sun50i-h616.dtsi" -+#include "sun50i-h616-cpu-opp.dtsi" - - #include - #include -@@ -32,6 +33,10 @@ - }; - }; - -+&cpu0 { -+ cpu-supply = <®_dcdca>; -+}; -+ - &ehci0 { - status = "okay"; - }; ---- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts -@@ -6,12 +6,17 @@ - /dts-v1/; - - #include "sun50i-h616-orangepi-zero.dtsi" -+#include "sun50i-h616-cpu-opp.dtsi" - - / { - model = "OrangePi Zero3"; - compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; - }; - -+&cpu0 { -+ cpu-supply = <®_dcdc2>; -+}; -+ - &emac0 { - allwinner,tx-delay-ps = <700>; - phy-mode = "rgmii-rxid"; diff --git a/target/linux/sunxi/patches-6.6/024-v6.10-cpufreq-sun50i-Fix-build-warning-around-snprint.patch b/target/linux/sunxi/patches-6.6/024-v6.10-cpufreq-sun50i-Fix-build-warning-around-snprint.patch deleted file mode 100644 index 8bfd6c2d09..0000000000 --- a/target/linux/sunxi/patches-6.6/024-v6.10-cpufreq-sun50i-Fix-build-warning-around-snprint.patch +++ /dev/null @@ -1,51 +0,0 @@ -From d2059d3b548409905b20b4f52495bffbd7c8da8b Mon Sep 17 00:00:00 2001 -From: Viresh Kumar -Date: Mon, 22 Apr 2024 08:58:51 +0530 -Subject: [PATCH] cpufreq: sun50i: Fix build warning around snprint() - -The Sun50i driver generates a warning with W=1: - -warning: '%d' directive output may be truncated writing between 1 and 10 bytes into a region of size 2 [-Wformat-truncation=] - -Fix it by allocating a big enough array to print an integer. - -Reported-by: kernel test robot -Closes: https://lore.kernel.org/oe-kbuild-all/202404191715.LDwMm2gP-lkp@intel.com/ -Signed-off-by: Viresh Kumar -Acked-by: Chen-Yu Tsai -Reviewed-by: Andre Przywara -Tested-by: Andre Przywara -Reviewed-by: Julian Calaby ---- - drivers/cpufreq/sun50i-cpufreq-nvmem.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - ---- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c -+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c -@@ -19,8 +19,6 @@ - #include - #include - --#define MAX_NAME_LEN 7 -- - #define NVMEM_MASK 0x7 - #define NVMEM_SHIFT 5 - -@@ -208,7 +206,7 @@ static int sun50i_cpufreq_get_efuse(void - static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev) - { - int *opp_tokens; -- char name[MAX_NAME_LEN]; -+ char name[] = "speedXXXXXXXXXXX"; /* Integers can take 11 chars max */ - unsigned int cpu, supported_hw; - struct dev_pm_opp_config config = {}; - int speed; -@@ -235,7 +233,7 @@ static int sun50i_cpufreq_nvmem_probe(st - config.supported_hw_count = 1; - } - -- snprintf(name, MAX_NAME_LEN, "speed%d", speed); -+ snprintf(name, sizeof(name), "speed%d", speed); - config.prop_name = name; - - for_each_possible_cpu(cpu) { diff --git a/target/linux/sunxi/patches-6.6/025-v6.10-cpufreq-sun50i-fix-error-returns-in-dt_has_supported_hw.patch b/target/linux/sunxi/patches-6.6/025-v6.10-cpufreq-sun50i-fix-error-returns-in-dt_has_supported_hw.patch deleted file mode 100644 index 2304a6af79..0000000000 --- a/target/linux/sunxi/patches-6.6/025-v6.10-cpufreq-sun50i-fix-error-returns-in-dt_has_supported_hw.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 76a6fc5644b2a1c70868bec24a078f784600ef2a Mon Sep 17 00:00:00 2001 -From: Dan Carpenter -Date: Wed, 24 Apr 2024 14:40:11 +0300 -Subject: [PATCH] cpufreq: sun50i: fix error returns in dt_has_supported_hw() - -The dt_has_supported_hw() function returns type bool. That means these -negative error codes are cast to true but the function should return -false instead. - -Fixes: fa5aec9561cf ("cpufreq: sun50i: Add support for opp_supported_hw") -Signed-off-by: Dan Carpenter -Reviewed-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/sun50i-cpufreq-nvmem.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c -+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c -@@ -136,11 +136,11 @@ static bool dt_has_supported_hw(void) - - cpu_dev = get_cpu_device(0); - if (!cpu_dev) -- return -ENODEV; -+ return false; - - np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); - if (!np) -- return -ENOENT; -+ return false; - - for_each_child_of_node(np, opp) { - if (of_find_property(opp, "opp-supported-hw", NULL)) { diff --git a/target/linux/uml/Makefile b/target/linux/uml/Makefile index 62b0f83db6..d577d474bb 100644 --- a/target/linux/uml/Makefile +++ b/target/linux/uml/Makefile @@ -15,6 +15,7 @@ FEATURES:=audio ext4 rootfs-part squashfs SUBTARGETS:=generic KERNEL_PATCHVER:=6.6 +KERNEL_TESTING_PATCHVER:=6.12 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/uml/config-6.12 b/target/linux/uml/config-6.12 new file mode 100644 index 0000000000..d4f42f88b0 --- /dev/null +++ b/target/linux/uml/config-6.12 @@ -0,0 +1,161 @@ +CONFIG_3_LEVEL_PGTABLES=y +CONFIG_64BIT=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_BLK_DEV_COW_COMMON=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_UBD=y +CONFIG_BLK_DEV_UBD_SYNC=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BUFFER_HEAD=y +CONFIG_CDROM=y +# CONFIG_COMMON_CLK is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_CON_CHAN="xterm" +CONFIG_CON_ZERO_CHAN="fd:0,fd:1" +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_SUP_AMD=y +CONFIG_CPU_SUP_CENTAUR=y +CONFIG_CPU_SUP_HYGON=y +CONFIG_CPU_SUP_INTEL=y +CONFIG_CPU_SUP_ZHAOXIN=y +CONFIG_CRC16=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_SHA1=y +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_DEBUG_INFO is not set +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DNOTIFY=y +# CONFIG_EARLY_PRINTK is not set +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_F2FS_FS=y +CONFIG_FAILOVER=y +CONFIG_FORCE_NR_CPUS=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GPIO_CDEV=y +CONFIG_HOSTFS=y +CONFIG_HVC_DRIVER=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_PERIODIC=y +CONFIG_IA32_FEAT_CTL=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INIT_ENV_ARG_LIMIT=128 +CONFIG_IRQ_WORK=y +CONFIG_ISO9660_FS=y +CONFIG_JBD2=y +# CONFIG_JFFS2_FS is not set +CONFIG_KALLSYMS=y +CONFIG_KERNEL_STACK_ORDER=2 +CONFIG_LD_SCRIPT_DYN_RPATH=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_MATOM is not set +CONFIG_MAY_HAVE_RUNTIME_DEPS=y +CONFIG_MCONSOLE=y +# CONFIG_MCORE2 is not set +CONFIG_MIGRATION=y +# CONFIG_MK8 is not set +# CONFIG_MMAPPER is not set +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MPSC is not set +CONFIG_NAMESPACES=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FAILOVER=y +CONFIG_NET_INGRESS=y +# CONFIG_NET_NS is not set +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NO_DMA=y +CONFIG_NO_IOMEM=y +CONFIG_NO_IOPORT_MAP=y +CONFIG_NR_CPUS=1 +# CONFIG_NSM is not set +CONFIG_NULL_CHAN=y +# CONFIG_OF is not set +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PORT_CHAN=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_PROCESSOR_SELECT is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PTY_CHAN=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RELAY=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SG_POOL=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SSL=y +CONFIG_SSL_CHAN="pty" +CONFIG_STACKTRACE=y +CONFIG_STDERR_CONSOLE=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TINY_SRCU=y +CONFIG_TOOLS_SUPPORT_RELR=y +CONFIG_TTY_CHAN=y +CONFIG_UML=y +CONFIG_UML_NET=y +CONFIG_UML_NET_DAEMON=y +CONFIG_UML_NET_DAEMON_DEFAULT_SOCK="/tmp/uml.ctl" +CONFIG_UML_NET_DETERMINISTIC_MAC=y +CONFIG_UML_NET_ETHERTAP=y +CONFIG_UML_NET_MCAST=y +CONFIG_UML_NET_SLIP=y +CONFIG_UML_NET_SLIRP=y +CONFIG_UML_NET_TUNTAP=y +# CONFIG_UML_NET_VDE is not set +CONFIG_UML_NET_VECTOR=y +# CONFIG_UML_PCI_OVER_VIRTIO is not set +CONFIG_UML_RANDOM=y +CONFIG_UML_TIME_TRAVEL_SUPPORT=y +# CONFIG_UML_WATCHDOG is not set +CONFIG_UML_X86=y +# CONFIG_USER_NS is not set +CONFIG_VIRTIO=y +CONFIG_VIRTIO_ANCHOR=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +# CONFIG_VIRTIO_DEBUG is not set +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_UML=y +CONFIG_VMAP_STACK=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_CORE=y +CONFIG_X86_64=y +CONFIG_X86_CMOV=y +CONFIG_X86_CMPXCHG64=y +CONFIG_X86_HAVE_PAE=y +CONFIG_X86_INTERNODE_CACHE_SHIFT=6 +CONFIG_X86_L1_CACHE_SHIFT=6 +CONFIG_X86_MINIMUM_CPU_FAMILY=64 +CONFIG_X86_TSC=y +CONFIG_X86_VMX_FEATURE_NAMES=y +CONFIG_XTERM_CHAN=y +CONFIG_XTERM_CHAN_DEFAULT_EMULATOR="xterm" +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/uml/files/arch/um/include/uapi/asm/Kbuild b/target/linux/uml/files/arch/um/include/uapi/asm/Kbuild deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/target/linux/uml/patches-6.12/000-v6.13-asm-generic-io.h-rework-split-ioread64-iowrite64-hel.patch b/target/linux/uml/patches-6.12/000-v6.13-asm-generic-io.h-rework-split-ioread64-iowrite64-hel.patch new file mode 100644 index 0000000000..f4092aad3f --- /dev/null +++ b/target/linux/uml/patches-6.12/000-v6.13-asm-generic-io.h-rework-split-ioread64-iowrite64-hel.patch @@ -0,0 +1,301 @@ +From dc90c890363d3e4b0ec73cd21b5be592692723fd Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Mon, 3 Feb 2025 15:07:30 +0100 +Subject: [PATCH] asm-generic/io.h: rework split ioread64/iowrite64 helpers + +There are two incompatible sets of definitions of these eight functions: +On 64-bit architectures setting CONFIG_HAS_IOPORT, they turn into +either pair of 32-bit PIO (inl/outl) accesses or a single 64-bit MMIO +(readq/writeq). On other 64-bit architectures, they are always split +into 32-bit accesses. + +Depending on which header gets included in a driver, there are +additionally definitions for ioread64()/iowrite64() that are +expected to produce a 64-bit register MMIO access on all 64-bit +architectures. + +To separate the conflicting definitions, make the version in +include/linux/io-64-nonatomic-*.h visible on all architectures +but pick the one from lib/iomap.c on architectures that set +CONFIG_GENERIC_IOMAP in place of the default fallback. + +Acked-by: Andy Shevchenko +Signed-off-by: Arnd Bergmann +--- + include/asm-generic/iomap.h | 36 ++++++------------------ + include/linux/io-64-nonatomic-hi-lo.h | 16 +++++++++++ + include/linux/io-64-nonatomic-lo-hi.h | 16 +++++++++++ + lib/iomap.c | 40 +++++++++++++-------------- + 4 files changed, 60 insertions(+), 48 deletions(-) + +diff --git a/include/asm-generic/iomap.h b/include/asm-generic/iomap.h +index 196087a8126e..9f3f25d7fc58 100644 +--- a/include/asm-generic/iomap.h ++++ b/include/asm-generic/iomap.h +@@ -31,42 +31,22 @@ extern unsigned int ioread16(const void __iomem *); + extern unsigned int ioread16be(const void __iomem *); + extern unsigned int ioread32(const void __iomem *); + extern unsigned int ioread32be(const void __iomem *); +-#ifdef CONFIG_64BIT +-extern u64 ioread64(const void __iomem *); +-extern u64 ioread64be(const void __iomem *); +-#endif + +-#ifdef readq +-#define ioread64_lo_hi ioread64_lo_hi +-#define ioread64_hi_lo ioread64_hi_lo +-#define ioread64be_lo_hi ioread64be_lo_hi +-#define ioread64be_hi_lo ioread64be_hi_lo +-extern u64 ioread64_lo_hi(const void __iomem *addr); +-extern u64 ioread64_hi_lo(const void __iomem *addr); +-extern u64 ioread64be_lo_hi(const void __iomem *addr); +-extern u64 ioread64be_hi_lo(const void __iomem *addr); +-#endif ++extern u64 __ioread64_lo_hi(const void __iomem *addr); ++extern u64 __ioread64_hi_lo(const void __iomem *addr); ++extern u64 __ioread64be_lo_hi(const void __iomem *addr); ++extern u64 __ioread64be_hi_lo(const void __iomem *addr); + + extern void iowrite8(u8, void __iomem *); + extern void iowrite16(u16, void __iomem *); + extern void iowrite16be(u16, void __iomem *); + extern void iowrite32(u32, void __iomem *); + extern void iowrite32be(u32, void __iomem *); +-#ifdef CONFIG_64BIT +-extern void iowrite64(u64, void __iomem *); +-extern void iowrite64be(u64, void __iomem *); +-#endif + +-#ifdef writeq +-#define iowrite64_lo_hi iowrite64_lo_hi +-#define iowrite64_hi_lo iowrite64_hi_lo +-#define iowrite64be_lo_hi iowrite64be_lo_hi +-#define iowrite64be_hi_lo iowrite64be_hi_lo +-extern void iowrite64_lo_hi(u64 val, void __iomem *addr); +-extern void iowrite64_hi_lo(u64 val, void __iomem *addr); +-extern void iowrite64be_lo_hi(u64 val, void __iomem *addr); +-extern void iowrite64be_hi_lo(u64 val, void __iomem *addr); +-#endif ++extern void __iowrite64_lo_hi(u64 val, void __iomem *addr); ++extern void __iowrite64_hi_lo(u64 val, void __iomem *addr); ++extern void __iowrite64be_lo_hi(u64 val, void __iomem *addr); ++extern void __iowrite64be_hi_lo(u64 val, void __iomem *addr); + + /* + * "string" versions of the above. Note that they +diff --git a/include/linux/io-64-nonatomic-hi-lo.h b/include/linux/io-64-nonatomic-hi-lo.h +index f32522bb3aa5..d3eade7cf663 100644 +--- a/include/linux/io-64-nonatomic-hi-lo.h ++++ b/include/linux/io-64-nonatomic-hi-lo.h +@@ -101,22 +101,38 @@ static inline void iowrite64be_hi_lo(u64 val, void __iomem *addr) + + #ifndef ioread64 + #define ioread64_is_nonatomic ++#if defined(CONFIG_GENERIC_IOMAP) && defined(CONFIG_64BIT) ++#define ioread64 __ioread64_hi_lo ++#else + #define ioread64 ioread64_hi_lo + #endif ++#endif + + #ifndef iowrite64 + #define iowrite64_is_nonatomic ++#if defined(CONFIG_GENERIC_IOMAP) && defined(CONFIG_64BIT) ++#define iowrite64 __iowrite64_hi_lo ++#else + #define iowrite64 iowrite64_hi_lo + #endif ++#endif + + #ifndef ioread64be + #define ioread64be_is_nonatomic ++#if defined(CONFIG_GENERIC_IOMAP) && defined(CONFIG_64BIT) ++#define ioread64be __ioread64be_hi_lo ++#else + #define ioread64be ioread64be_hi_lo + #endif ++#endif + + #ifndef iowrite64be + #define iowrite64be_is_nonatomic ++#if defined(CONFIG_GENERIC_IOMAP) && defined(CONFIG_64BIT) ++#define iowrite64be __iowrite64be_hi_lo ++#else + #define iowrite64be iowrite64be_hi_lo + #endif ++#endif + + #endif /* _LINUX_IO_64_NONATOMIC_HI_LO_H_ */ +diff --git a/include/linux/io-64-nonatomic-lo-hi.h b/include/linux/io-64-nonatomic-lo-hi.h +index 448a21435dba..94e676ec3d3f 100644 +--- a/include/linux/io-64-nonatomic-lo-hi.h ++++ b/include/linux/io-64-nonatomic-lo-hi.h +@@ -101,22 +101,38 @@ static inline void iowrite64be_lo_hi(u64 val, void __iomem *addr) + + #ifndef ioread64 + #define ioread64_is_nonatomic ++#if defined(CONFIG_GENERIC_IOMAP) && defined(CONFIG_64BIT) ++#define ioread64 __ioread64_lo_hi ++#else + #define ioread64 ioread64_lo_hi + #endif ++#endif + + #ifndef iowrite64 + #define iowrite64_is_nonatomic ++#if defined(CONFIG_GENERIC_IOMAP) && defined(CONFIG_64BIT) ++#define iowrite64 __iowrite64_lo_hi ++#else + #define iowrite64 iowrite64_lo_hi + #endif ++#endif + + #ifndef ioread64be + #define ioread64be_is_nonatomic ++#if defined(CONFIG_GENERIC_IOMAP) && defined(CONFIG_64BIT) ++#define ioread64be __ioread64be_lo_hi ++#else + #define ioread64be ioread64be_lo_hi + #endif ++#endif + + #ifndef iowrite64be + #define iowrite64be_is_nonatomic ++#if defined(CONFIG_GENERIC_IOMAP) && defined(CONFIG_64BIT) ++#define iowrite64be __iowrite64be_lo_hi ++#else + #define iowrite64be iowrite64be_lo_hi + #endif ++#endif + + #endif /* _LINUX_IO_64_NONATOMIC_LO_HI_H_ */ +diff --git a/lib/iomap.c b/lib/iomap.c +index 4f8b31baa575..a65717cd86f7 100644 +--- a/lib/iomap.c ++++ b/lib/iomap.c +@@ -111,7 +111,7 @@ EXPORT_SYMBOL(ioread16be); + EXPORT_SYMBOL(ioread32); + EXPORT_SYMBOL(ioread32be); + +-#ifdef readq ++#ifdef CONFIG_64BIT + static u64 pio_read64_lo_hi(unsigned long port) + { + u64 lo, hi; +@@ -153,21 +153,21 @@ static u64 pio_read64be_hi_lo(unsigned long port) + } + + __no_kmsan_checks +-u64 ioread64_lo_hi(const void __iomem *addr) ++u64 __ioread64_lo_hi(const void __iomem *addr) + { + IO_COND(addr, return pio_read64_lo_hi(port), return readq(addr)); + return 0xffffffffffffffffULL; + } + + __no_kmsan_checks +-u64 ioread64_hi_lo(const void __iomem *addr) ++u64 __ioread64_hi_lo(const void __iomem *addr) + { + IO_COND(addr, return pio_read64_hi_lo(port), return readq(addr)); + return 0xffffffffffffffffULL; + } + + __no_kmsan_checks +-u64 ioread64be_lo_hi(const void __iomem *addr) ++u64 __ioread64be_lo_hi(const void __iomem *addr) + { + IO_COND(addr, return pio_read64be_lo_hi(port), + return mmio_read64be(addr)); +@@ -175,19 +175,19 @@ u64 ioread64be_lo_hi(const void __iomem *addr) + } + + __no_kmsan_checks +-u64 ioread64be_hi_lo(const void __iomem *addr) ++u64 __ioread64be_hi_lo(const void __iomem *addr) + { + IO_COND(addr, return pio_read64be_hi_lo(port), + return mmio_read64be(addr)); + return 0xffffffffffffffffULL; + } + +-EXPORT_SYMBOL(ioread64_lo_hi); +-EXPORT_SYMBOL(ioread64_hi_lo); +-EXPORT_SYMBOL(ioread64be_lo_hi); +-EXPORT_SYMBOL(ioread64be_hi_lo); ++EXPORT_SYMBOL(__ioread64_lo_hi); ++EXPORT_SYMBOL(__ioread64_hi_lo); ++EXPORT_SYMBOL(__ioread64be_lo_hi); ++EXPORT_SYMBOL(__ioread64be_hi_lo); + +-#endif /* readq */ ++#endif /* CONFIG_64BIT */ + + #ifndef pio_write16be + #define pio_write16be(val,port) outw(swab16(val),port) +@@ -236,7 +236,7 @@ EXPORT_SYMBOL(iowrite16be); + EXPORT_SYMBOL(iowrite32); + EXPORT_SYMBOL(iowrite32be); + +-#ifdef writeq ++#ifdef CONFIG_64BIT + static void pio_write64_lo_hi(u64 val, unsigned long port) + { + outl(val, port); +@@ -261,7 +261,7 @@ static void pio_write64be_hi_lo(u64 val, unsigned long port) + pio_write32be(val, port + sizeof(u32)); + } + +-void iowrite64_lo_hi(u64 val, void __iomem *addr) ++void __iowrite64_lo_hi(u64 val, void __iomem *addr) + { + /* Make sure uninitialized memory isn't copied to devices. */ + kmsan_check_memory(&val, sizeof(val)); +@@ -269,7 +269,7 @@ void iowrite64_lo_hi(u64 val, void __iomem *addr) + writeq(val, addr)); + } + +-void iowrite64_hi_lo(u64 val, void __iomem *addr) ++void __iowrite64_hi_lo(u64 val, void __iomem *addr) + { + /* Make sure uninitialized memory isn't copied to devices. */ + kmsan_check_memory(&val, sizeof(val)); +@@ -277,7 +277,7 @@ void iowrite64_hi_lo(u64 val, void __iomem *addr) + writeq(val, addr)); + } + +-void iowrite64be_lo_hi(u64 val, void __iomem *addr) ++void __iowrite64be_lo_hi(u64 val, void __iomem *addr) + { + /* Make sure uninitialized memory isn't copied to devices. */ + kmsan_check_memory(&val, sizeof(val)); +@@ -285,7 +285,7 @@ void iowrite64be_lo_hi(u64 val, void __iomem *addr) + mmio_write64be(val, addr)); + } + +-void iowrite64be_hi_lo(u64 val, void __iomem *addr) ++void __iowrite64be_hi_lo(u64 val, void __iomem *addr) + { + /* Make sure uninitialized memory isn't copied to devices. */ + kmsan_check_memory(&val, sizeof(val)); +@@ -293,12 +293,12 @@ void iowrite64be_hi_lo(u64 val, void __iomem *addr) + mmio_write64be(val, addr)); + } + +-EXPORT_SYMBOL(iowrite64_lo_hi); +-EXPORT_SYMBOL(iowrite64_hi_lo); +-EXPORT_SYMBOL(iowrite64be_lo_hi); +-EXPORT_SYMBOL(iowrite64be_hi_lo); ++EXPORT_SYMBOL(__iowrite64_lo_hi); ++EXPORT_SYMBOL(__iowrite64_hi_lo); ++EXPORT_SYMBOL(__iowrite64be_lo_hi); ++EXPORT_SYMBOL(__iowrite64be_hi_lo); + +-#endif /* readq */ ++#endif /* CONFIG_64BIT */ + + /* + * These are the "repeat MMIO read/write" functions. +-- +2.49.0 + diff --git a/target/linux/uml/patches-6.12/101-mconsole-exec.patch b/target/linux/uml/patches-6.12/101-mconsole-exec.patch new file mode 100644 index 0000000000..9ba4523a16 --- /dev/null +++ b/target/linux/uml/patches-6.12/101-mconsole-exec.patch @@ -0,0 +1,213 @@ +# +# Minimalist mconsole exec patch +# +# 3.10 version (with bit more synchronous behavior) by fingon at iki dot fi +# Adaptation to kernel 3.3.8 made by David Fernández (david at dit.upm.es) for +# Starting point: mconsole-exec-2.6.30.patch for kernel 2.6.30 +# Author of original patch: Paolo Giarrusso, aka Blaisorblade +# (http://www.user-mode-linux.org/~blaisorblade) +# +# Known misfeatures: +# +# - If output is too long, blocks (and breaks horribly) +# (this misfeature from 3.10 patches, when minimalizing the patch; +# workaround: redirect to a shared filesystem if long output is expected) +# +# - Nothing useful is done with stdin +# +--- a/arch/um/drivers/mconsole.h ++++ b/arch/um/drivers/mconsole.h +@@ -85,6 +85,7 @@ extern void mconsole_cad(struct mc_reque + extern void mconsole_stop(struct mc_request *req); + extern void mconsole_go(struct mc_request *req); + extern void mconsole_log(struct mc_request *req); ++extern void mconsole_exec(struct mc_request *req); + extern void mconsole_proc(struct mc_request *req); + extern void mconsole_stack(struct mc_request *req); + +--- a/arch/um/drivers/mconsole_kern.c ++++ b/arch/um/drivers/mconsole_kern.c +@@ -4,6 +4,7 @@ + * Copyright (C) 2001 - 2008 Jeff Dike (jdike@{addtoit,linux.intel}.com) + */ + ++#include + #include + #include + #include +@@ -27,6 +28,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -124,6 +126,59 @@ void mconsole_log(struct mc_request *req + mconsole_reply(req, "", 0, 0); + } + ++void mconsole_exec(struct mc_request *req) ++{ ++ struct subprocess_info *sub_info; ++ int res, len; ++ struct file *out; ++ char buf[MCONSOLE_MAX_DATA]; ++ ++ char *envp[] = { ++ "HOME=/", "TERM=linux", ++ "PATH=/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin", ++ NULL ++ }; ++ char *argv[] = { ++ "/bin/sh", "-c", ++ req->request.data + strlen("exec "), ++ NULL ++ }; ++ ++ sub_info = call_usermodehelper_setup("/bin/sh", argv, envp, GFP_ATOMIC, NULL, NULL, NULL); ++ if (sub_info == NULL) { ++ mconsole_reply(req, "call_usermodehelper_setup failed", 1, 0); ++ return; ++ } ++ res = call_usermodehelper_stdoutpipe(sub_info, &out); ++ if (res < 0) { ++ kfree(sub_info); ++ mconsole_reply(req, "call_usermodehelper_stdoutpipe failed", 1, 0); ++ return; ++ } ++ ++ res = call_usermodehelper_exec(sub_info, UMH_WAIT_PROC); ++ if (res < 0) { ++ kfree(sub_info); ++ mconsole_reply(req, "call_usermodehelper_exec failed", 1, 0); ++ return; ++ } ++ ++ for (;;) { ++ len = out->f_op->read(out, buf, sizeof(buf), &out->f_pos); ++ if (len < 0) { ++ mconsole_reply(req, "reading output failed", 1, 0); ++ break; ++ } ++ if (len == 0) ++ break; ++ mconsole_reply_len(req, buf, len, 0, 1); ++ } ++ fput(out); ++ ++ mconsole_reply_len(req, NULL, 0, 0, 0); ++} ++ ++ + void mconsole_proc(struct mc_request *req) + { + struct vfsmount *mnt = proc_mnt; +@@ -190,6 +245,7 @@ void mconsole_proc(struct mc_request *re + stop - pause the UML; it will do nothing until it receives a 'go' \n\ + go - continue the UML after a 'stop' \n\ + log - make UML enter into the kernel log\n\ ++ exec - pass to /bin/sh -c synchronously\n\ + proc - returns the contents of the UML's /proc/\n\ + stack - returns the stack of the specified pid\n\ + " +--- a/arch/um/drivers/mconsole_user.c ++++ b/arch/um/drivers/mconsole_user.c +@@ -30,6 +30,7 @@ static struct mconsole_command commands[ + { "stop", mconsole_stop, MCONSOLE_PROC }, + { "go", mconsole_go, MCONSOLE_INTR }, + { "log", mconsole_log, MCONSOLE_INTR }, ++ { "exec", mconsole_exec, MCONSOLE_PROC }, + { "proc", mconsole_proc, MCONSOLE_PROC }, + { "stack", mconsole_stack, MCONSOLE_INTR }, + }; +--- a/arch/um/os-Linux/file.c ++++ b/arch/um/os-Linux/file.c +@@ -578,6 +578,8 @@ int os_create_unix_socket(const char *fi + + addr.sun_family = AF_UNIX; + ++ if (len > sizeof(addr.sun_path)) ++ len = sizeof(addr.sun_path); + snprintf(addr.sun_path, len, "%s", file); + + err = bind(sock, (struct sockaddr *) &addr, sizeof(addr)); +--- a/include/linux/kmod.h ++++ b/include/linux/kmod.h +@@ -32,4 +32,6 @@ static inline int request_module_nowait( + #define try_then_request_module(x, mod...) (x) + #endif + ++int call_usermodehelper_stdoutpipe(struct subprocess_info *sub_info, struct file **filp); ++ + #endif /* __LINUX_KMOD_H__ */ +--- a/include/linux/umh.h ++++ b/include/linux/umh.h +@@ -23,6 +23,7 @@ struct subprocess_info { + const char *path; + char **argv; + char **envp; ++ struct file *stdout; + int wait; + int retval; + int (*init)(struct subprocess_info *info, struct cred *new); +--- a/kernel/umh.c ++++ b/kernel/umh.c +@@ -29,6 +29,7 @@ + #include + #include + #include ++#include + + #include + +@@ -71,6 +72,28 @@ static int call_usermodehelper_exec_asyn + flush_signal_handlers(current, 1); + spin_unlock_irq(¤t->sighand->siglock); + ++ /* Install output when needed */ ++ if (sub_info->stdout) { ++ struct files_struct *f = current->files; ++ struct fdtable *fdt; ++ ++ sys_close(1); ++ sys_close(2); ++ get_file(sub_info->stdout); ++ fd_install(1, sub_info->stdout); ++ fd_install(2, sub_info->stdout); ++ spin_lock(&f->file_lock); ++ fdt = files_fdtable(f); ++ __set_bit(1, fdt->open_fds); ++ __clear_bit(1, fdt->close_on_exec); ++ __set_bit(2, fdt->open_fds); ++ __clear_bit(2, fdt->close_on_exec); ++ spin_unlock(&f->file_lock); ++ ++ /* disallow core files */ ++ current->signal->rlim[RLIMIT_CORE] = (struct rlimit){0, 0}; ++ } ++ + /* + * Initial kernel threads share ther FS with init, in order to + * get the init root directory. But we've now created a new +@@ -330,6 +353,20 @@ static void helper_unlock(void) + wake_up(&running_helpers_waitq); + } + ++int call_usermodehelper_stdoutpipe(struct subprocess_info *sub_info, ++ struct file **filp) ++{ ++ struct file *f[2]; ++ ++ if (create_pipe_files(f, 0) < 0) ++ return PTR_ERR(f); ++ ++ sub_info->stdout = f[1]; ++ *filp = f[0]; ++ return 0; ++} ++EXPORT_SYMBOL(call_usermodehelper_stdoutpipe); ++ + /** + * call_usermodehelper_setup - prepare to call a usermode helper + * @path: path to usermode executable diff --git a/target/linux/uml/patches-6.12/102-pseudo-random-mac.patch b/target/linux/uml/patches-6.12/102-pseudo-random-mac.patch new file mode 100644 index 0000000000..2b42459fe8 --- /dev/null +++ b/target/linux/uml/patches-6.12/102-pseudo-random-mac.patch @@ -0,0 +1,151 @@ +=============================================================================== + +This patch makes MAC addresses of network interfaces predictable. In +particular, it adds a small routine that computes MAC addresses of based on +a SHA1 hash of the virtual machine name and interface ID. + +TECHNICAL INFORMATION: + +Applies to vanilla kernel 3.9.4. + +=============================================================================== +--- a/arch/um/drivers/Kconfig ++++ b/arch/um/drivers/Kconfig +@@ -143,6 +143,20 @@ config UML_NET + enable at least one of the following transport options to actually + make use of UML networking. + ++config UML_NET_DETERMINISTIC_MAC ++ bool "Use deterministic MAC addresses for network interfaces" ++ default y ++ depends on UML_NET ++ select CRYPTO_SHA1 ++ help ++ Virtual network devices inside a User-Mode Linux instance must be ++ assigned a MAC (Ethernet) address. If none is specified on the UML ++ command line, one must be automatically computed. If this option is ++ enabled, a randomly generated address is used. Otherwise, if this ++ option is disabled, the address is generated from a SHA1 hash of ++ the umid of the UML instance and the interface name. The latter choice ++ is useful to make MAC addresses predictable. ++ + config UML_NET_ETHERTAP + bool "Ethertap transport (obsolete)" + depends on UML_NET +--- a/arch/um/drivers/net_kern.c ++++ b/arch/um/drivers/net_kern.c +@@ -25,6 +25,14 @@ + #include + #include + ++#include ++#include ++#include ++#include ++#include ++#include ++#include "os.h" ++ + #define DRIVER_NAME "uml-netdev" + + static DEFINE_SPINLOCK(opened_lock); +@@ -274,9 +282,55 @@ static const struct ethtool_ops uml_net_ + .get_ts_info = ethtool_op_get_ts_info, + }; + ++#ifdef CONFIG_UML_NET_DETERMINISTIC_MAC ++ ++/* Compute a SHA1 hash of the UML instance's id and ++ * * an interface name. */ ++static int compute_hash(const char *umid, const char *ifname, char *hash) ++{ ++ struct ahash_request *desc = NULL; ++ struct crypto_ahash *tfm = NULL; ++ struct scatterlist sg; ++ char *vmif = NULL; ++ int ret = -ENOMEM; ++ ++ vmif = kmalloc(1024, GFP_KERNEL); ++ if (!vmif) ++ goto out; ++ ++ strcpy (vmif, umid); ++ strcat (vmif, ifname); ++ ++ tfm = crypto_alloc_ahash("sha1", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) ++ goto out; ++ ++ desc = ahash_request_alloc(tfm, GFP_KERNEL); ++ if (!desc) ++ goto out; ++ ++ crypto_ahash_clear_flags(tfm, ~0); ++ ++ sg_init_table(&sg, 1); ++ sg_set_buf(&sg, vmif, strlen(vmif)); ++ ++ ahash_request_set_crypt(desc, &sg, hash, strlen(vmif)); ++ ++ ret = crypto_ahash_digest(desc); ++out: ++ crypto_free_ahash(tfm); ++ ahash_request_free(desc); ++ kfree(vmif); ++ ++ return ret; ++} ++ ++#endif ++ + void uml_net_setup_etheraddr(struct net_device *dev, char *str) + { + u8 addr[ETH_ALEN]; ++ u8 hash[SHA1_DIGEST_SIZE]; + char *end; + int i; + +@@ -320,9 +374,26 @@ void uml_net_setup_etheraddr(struct net_ + return; + + random: ++#ifndef CONFIG_UML_NET_DETERMINISTIC_MAC + printk(KERN_INFO + "Choosing a random ethernet address for device %s\n", dev->name); + eth_hw_addr_random(dev); ++#else ++ printk(KERN_INFO ++ "Computing a digest to use as ethernet address for device %s\n", dev->name); ++ if (compute_hash(get_umid(), dev->name, hash) < 0) { ++ printk(KERN_WARNING ++ "Could not compute digest to use as ethernet address for device %s. " ++ "Using random address instead.\n", dev->name); ++ eth_random_addr(addr); ++ } ++ else { ++ for (i=0; i < 6; i++) ++ addr[i] = (hash[i] + hash[i+6]) % 0x100; ++ } ++ addr [0] &= 0xfe; /* clear multicast bit */ ++ addr [0] |= 0x02; /* set local assignment bit (IEEE802) */ ++#endif + } + + static DEFINE_SPINLOCK(devices_lock); +--- a/kernel/umh.c ++++ b/kernel/umh.c +@@ -354,12 +354,12 @@ static void helper_unlock(void) + } + + int call_usermodehelper_stdoutpipe(struct subprocess_info *sub_info, +- struct file **filp) ++ struct file **filp) + { + struct file *f[2]; + + if (create_pipe_files(f, 0) < 0) +- return PTR_ERR(f); ++ return PTR_ERR(f); + + sub_info->stdout = f[1]; + *filp = f[0]; diff --git a/target/linux/x86/64/config-6.12 b/target/linux/x86/64/config-6.12 index 5ab986a292..c55d5465ac 100644 --- a/target/linux/x86/64/config-6.12 +++ b/target/linux/x86/64/config-6.12 @@ -82,11 +82,11 @@ CONFIG_CDROM=y CONFIG_CONNECTOR=y CONFIG_CONTEXT_TRACKING=y CONFIG_CONTEXT_TRACKING_IDLE=y +# CONFIG_CPUSETS_V1 is not set CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPU_IDLE_GOV_HALTPOLL=y CONFIG_CPU_RMAP=y -# CONFIG_CPUSETS_V1 is not set CONFIG_CRASH_HOTPLUG=y CONFIG_CRASH_MAX_MEMORY_RANGES=8192 CONFIG_CRC64=y @@ -187,7 +187,6 @@ CONFIG_FB_CORE=y CONFIG_FB_DEFERRED_IO=y CONFIG_FB_DEVICE=y CONFIG_FB_EFI=y -# CONFIG_HUAWEI_WMI is not set CONFIG_FB_HYPERV=y CONFIG_FB_IOMEM_FOPS=y CONFIG_FB_IOMEM_HELPERS=y @@ -254,6 +253,7 @@ CONFIG_HOTPLUG_SMT=y CONFIG_HOTPLUG_SPLIT_STARTUP=y CONFIG_HPET=y CONFIG_HPET_MMAP=y +# CONFIG_HUAWEI_WMI is not set CONFIG_HVC_DRIVER=y CONFIG_HVC_IRQ=y CONFIG_HVC_XEN=y @@ -335,8 +335,8 @@ CONFIG_IRQ_REMAP=y CONFIG_ISO9660_FS=y CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KCMP=y -CONFIG_KVM_HYPERV=y CONFIG_KVM_GUEST=y +CONFIG_KVM_HYPERV=y CONFIG_LEDS_GPIO=y CONFIG_LEGACY_VSYSCALL_NONE=y # CONFIG_LEGACY_VSYSCALL_XONLY is not set @@ -370,13 +370,13 @@ CONFIG_MMC_SDHCI_PCI=y # CONFIG_MMC_SDHCI_PLTFM is not set # CONFIG_MMC_WBSD is not set CONFIG_MMU_NOTIFIER=y -# CONFIG_MXM_WMI is not set CONFIG_MODULES_USE_ELF_RELA=y # CONFIG_MPSC is not set # CONFIG_MSI_EC is not set # CONFIG_MSI_WMI is not set # CONFIG_MSI_WMI_PLATFORM is not set CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_MXM_WMI is not set CONFIG_ND_CLAIM=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_SG_DMA_FLAGS=y @@ -515,8 +515,8 @@ CONFIG_SMP=y # CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set # CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set # CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set -# CONFIG_SND_SOC_AMD_ACP_COMMON is not set # CONFIG_SND_SOC_AMD_ACP6x is not set +# CONFIG_SND_SOC_AMD_ACP_COMMON is not set # CONFIG_SND_SOC_AMD_RPL_ACP6x is not set # CONFIG_SND_SOC_INTEL_AVS is not set CONFIG_SOCK_RX_QUEUE_MAPPING=y @@ -552,8 +552,8 @@ CONFIG_USB_HIDDEV=y CONFIG_USB_STORAGE=y CONFIG_VDSO_GETRANDOM=y CONFIG_VIDEO=y -# CONFIG_VIDEO_IPU3_CIO2 is not set # CONFIG_VIDEO_INTEL_IPU6 is not set +# CONFIG_VIDEO_IPU3_CIO2 is not set CONFIG_VIRTIO=y CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO_BALLOON=y diff --git a/target/linux/x86/config-6.12 b/target/linux/x86/config-6.12 index 4418db541d..7a72dd2577 100644 --- a/target/linux/x86/config-6.12 +++ b/target/linux/x86/config-6.12 @@ -106,10 +106,10 @@ CONFIG_DMIID=y CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y CONFIG_DMI_SYSFS=y CONFIG_DNOTIFY=y +# CONFIG_DP83TG720_PHY is not set CONFIG_DRM_ACCEL=y # CONFIG_DRM_I915_GVT_KVMGT is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_DP83TG720_PHY is not set # CONFIG_DWC_PCIE_PMU is not set CONFIG_DYNAMIC_SIGFRAME=y CONFIG_EARLY_PRINTK=y @@ -256,8 +256,8 @@ CONFIG_MICROCODE_INITRD32=y CONFIG_MICROCODE_LATE_FORCE_MINREV=y CONFIG_MICROCODE_LATE_LOADING=y CONFIG_MIGRATION=y -CONFIG_MITIGATION_ITS=y CONFIG_MITIGATION_GDS=y +CONFIG_MITIGATION_ITS=y CONFIG_MITIGATION_L1TF=y CONFIG_MITIGATION_MDS=y CONFIG_MITIGATION_MMIO_STALE_DATA=y diff --git a/target/linux/x86/generic/config-6.12 b/target/linux/x86/generic/config-6.12 index 1ad034cb18..a14888a211 100644 --- a/target/linux/x86/generic/config-6.12 +++ b/target/linux/x86/generic/config-6.12 @@ -66,11 +66,11 @@ CONFIG_CDROM=y CONFIG_CONNECTOR=y CONFIG_CONTEXT_TRACKING=y CONFIG_CONTEXT_TRACKING_IDLE=y +# CONFIG_CPUSETS_V1 is not set CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPU_IDLE_GOV_HALTPOLL=y CONFIG_CPU_RMAP=y -# CONFIG_CPUSETS_V1 is not set CONFIG_CRASH_HOTPLUG=y CONFIG_CRASH_MAX_MEMORY_RANGES=8192 # CONFIG_CS89x0_ISA is not set @@ -86,9 +86,9 @@ CONFIG_DRM_BRIDGE=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_GEM_SHMEM_HELPER=y +# CONFIG_DRM_HYPERV is not set # CONFIG_DRM_I915_DEBUG_WAKEREF is not set # CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set -# CONFIG_DRM_HYPERV is not set CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_PANEL=y CONFIG_DRM_PANEL_BRIDGE=y @@ -430,8 +430,8 @@ CONFIG_SMP=y # CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set # CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set # CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set -# CONFIG_SND_SOC_AMD_ACP_COMMON is not set # CONFIG_SND_SOC_AMD_ACP6x is not set +# CONFIG_SND_SOC_AMD_ACP_COMMON is not set # CONFIG_SND_SOC_AMD_RPL_ACP6x is not set # CONFIG_SND_SOC_INTEL_AVS is not set CONFIG_SOCK_RX_QUEUE_MAPPING=y diff --git a/target/linux/x86/geode/config-6.12 b/target/linux/x86/geode/config-6.12 index ff884334f5..55051dfed5 100644 --- a/target/linux/x86/geode/config-6.12 +++ b/target/linux/x86/geode/config-6.12 @@ -162,12 +162,12 @@ CONFIG_SENSORS_LM90=y CONFIG_SERIAL_8250_PNP=y # CONFIG_SERIAL_MULTI_INSTANTIATE is not set # CONFIG_SILICOM_PLATFORM is not set -# CONFIG_SND_HDA_CTL_DEV_ID is not set # CONFIG_SND_HDA_CODEC_SENARYTECH is not set +# CONFIG_SND_HDA_CTL_DEV_ID is not set # CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set # CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set -# CONFIG_SND_SOC_AMD_ACP_COMMON is not set # CONFIG_SND_SOC_AMD_ACP6x is not set +# CONFIG_SND_SOC_AMD_ACP_COMMON is not set # CONFIG_SND_SOC_AMD_RPL_ACP6x is not set # CONFIG_SND_SOC_INTEL_AVS is not set # CONFIG_THINKPAD_LMI is not set diff --git a/target/linux/x86/legacy/config-6.12 b/target/linux/x86/legacy/config-6.12 index 216389edda..1727da3750 100644 --- a/target/linux/x86/legacy/config-6.12 +++ b/target/linux/x86/legacy/config-6.12 @@ -62,8 +62,6 @@ CONFIG_DRM=y CONFIG_DRM_AMDGPU=y # CONFIG_DRM_AMD_DC is not set # CONFIG_DRM_AMD_ISP is not set -# CONFIG_DRM_I915_DEBUG_WAKEREF is not set -# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set CONFIG_DRM_BOCHS=y CONFIG_DRM_BRIDGE=y CONFIG_DRM_BUDDY=y @@ -74,6 +72,8 @@ CONFIG_DRM_DISPLAY_HELPER=y CONFIG_DRM_EXEC=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_I915_DEBUG_WAKEREF is not set +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_PANEL=y CONFIG_DRM_PANEL_BRIDGE=y @@ -241,8 +241,8 @@ CONFIG_SERIAL_8250_PNP=y # CONFIG_SND_HDA_CTL_DEV_ID is not set # CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set # CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set -# CONFIG_SND_SOC_AMD_ACP_COMMON is not set # CONFIG_SND_SOC_AMD_ACP6x is not set +# CONFIG_SND_SOC_AMD_ACP_COMMON is not set # CONFIG_SND_SOC_AMD_RPL_ACP6x is not set # CONFIG_SND_SOC_INTEL_AVS is not set CONFIG_SYNC_FILE=y diff --git a/target/toolchain/files/wrapper.sh b/target/toolchain/files/wrapper.sh index 09a9cac928..ca5be14eeb 100755 --- a/target/toolchain/files/wrapper.sh +++ b/target/toolchain/files/wrapper.sh @@ -53,8 +53,8 @@ if [ ! -d "$TOOLCHAIN_SYSROOT" ]; then exit 1 fi -# -Wl,--dynamic-linker=$TOOLCHAIN_SYSROOT/lib/ld-uClibc.so.0 -# --dynamic-linker=$TOOLCHAIN_SYSROOT/lib/ld-uClibc.so.0 +# -Wl,--dynamic-linker=$TOOLCHAIN_SYSROOT/lib/ld-uClibc.so.0 +# --dynamic-linker=$TOOLCHAIN_SYSROOT/lib/ld-uClibc.so.0 case $TOOLCHAIN_PLATFORM in gnu|glibc|uclibc|musl) diff --git a/toolchain/gcc/common.mk b/toolchain/gcc/common.mk index 7df44f1267..18d9d0b529 100644 --- a/toolchain/gcc/common.mk +++ b/toolchain/gcc/common.mk @@ -186,8 +186,10 @@ GCC_CONFIGURE+= \ CXXFLAGS_FOR_TARGET="$(TARGET_CFLAGS)" \ GOCFLAGS_FOR_TARGET="$(TARGET_CFLAGS)" +GCC_MAKE_VARS:= GCC_MAKE:= \ export SHELL="$(BASH)"; \ + $(GCC_MAKE_VARS) \ $(MAKE) define Host/SetToolchainInfo diff --git a/toolchain/gcc/final/Makefile b/toolchain/gcc/final/Makefile index 78a5576bff..8c09699c8a 100644 --- a/toolchain/gcc/final/Makefile +++ b/toolchain/gcc/final/Makefile @@ -17,7 +17,7 @@ ifndef CONFIG_USE_GLIBC endif ifdef CONFIG_USE_MUSL - GCC_MAKE += gcc_cv_libc_provides_ssp=yes + GCC_MAKE_VARS += gcc_cv_libc_provides_ssp=yes endif ifneq ($(CONFIG_SJLJ_EXCEPTIONS),)