mediatek: build image for MT7987 RFB

Import and clean DT and DT-overlay files from MediaTek's SDK to build
an image with various DT-overlays for the MT7987 reference board.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>

target/linux/mediatek/dts/mt7987a-rfb-emmc.dtso

@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target-path = "/";
+		__overlay__ {
+			reg_3p3v: regulator-3p3v {
+				compatible = "regulator-fixed";
+				regulator-name = "fixed-3.3V";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+
+	fragment@1 {
+		target-path = "/soc/spi@11007800";
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+	fragment@2 {
+		target-path = "/soc/mmc@11230000";
+		__overlay__ {
+			pinctrl-names = "default", "state_uhs";
+			pinctrl-0 = <&mmc_pins_default>;
+			pinctrl-1 = <&mmc_pins_uhs>;
+			bus-width = <8>;
+			max-frequency = <48000000>;
+			cap-mmc-highspeed;
+			vmmc-supply = <&reg_3p3v>;
+			non-removable;
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			card@0 {
+				compatible = "mmc-card";
+				reg = <0>;
+
+				block {
+					compatible = "block-device";
+					partitions {
+						block-partition-env {
+							partname = "ubootenv";
+							nvmem-layout {
+								compatible = "u-boot,env";
+							};
+						};
+
+						block-partition-factory {
+							partname = "factory";
+
+							nvmem-layout {
+								compatible = "fixed-layout";
+								#address-cells = <1>;
+								#size-cells = <1>;
+
+								eeprom_factory_0: eeprom@0 {
+									reg = <0x0 0x1e00>;
+								};
+							};
+						};
+
+						emmc_rootfs: block-partition-production {
+							partname = "production";
+						};
+					};
+				};
+			};
+		};
+	};
+
+	fragment@3 {
+		target-path = "/chosen";
+		__overlay__ {
+			rootdisk-emmc = <&emmc_rootfs>;
+		};
+	};
+
+	fragment@4 {
+		target = <&pcie0>;
+		__overlay__ {
+			slot0: pcie@0,0 {
+				reg = <0x0000 0 0 0 0>;
+				mt7996@0,0 {
+					reg = <0x0000 0 0 0 0>;
+					nvmem-cells = <&eeprom_factory_0>;
+					nvmem-cell-names = "eeprom";
+				};
+			};
+		};
+	};
+};
+

target/linux/mediatek/dts/mt7987a-rfb-eth0-an8801sb.dtso

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	fragment@0 {
+		target = <&gmac0>;
+		__overlay__ {
+			phy-handle = <&phy31>;
+			phy-mode = "sgmii";
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target-path = "/soc_netsys/ethernet@15100000/mdio-bus";
+		__overlay__ {
+			phy31: phy@31 {
+				compatible = "ethernet-phy-idc0ff.0421";
+				reg = <31>;
+				reset-gpios = <&pio 48 GPIO_ACTIVE_LOW>;
+				reset-assert-us = <10000>;
+				reset-deassert-us = <10000>;
+				eee-broken-100tx;
+				eee-broken-1000t;
+			};
+		};
+	};
+};

target/linux/mediatek/dts/mt7987a-rfb-eth0-an8855.dtso

@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	fragment@0 {
+		target = <&gmac0>;
+		__overlay__ {
+			phy-mode = "2500base-x";
+			status = "okay";
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+
+	fragment@1 {
+		target-path = "/soc_netsys/ethernet@15100000/mdio-bus";
+		__overlay__ {
+			mfd: mfd@1 {
+				compatible = "airoha,an8855-mfd";
+				reg = <1>;
+				status = "okay";
+
+				efuse {
+					compatible = "airoha,an8855-efuse";
+					#nvmem-cell-cells = <0>;
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
+							reg = <0xc 0x4>;
+						};
+
+						shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
+							reg = <0x10 0x4>;
+						};
+
+						shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
+							reg = <0x14 0x4>;
+						};
+
+						shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
+							reg = <0x18 0x4>;
+						};
+
+						shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
+							reg = <0x1c 0x4>;
+						};
+
+						shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
+							reg = <0x20 0x4>;
+						};
+
+						shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
+							reg = <0x24 0x4>;
+						};
+
+						shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
+							reg = <0x28 0x4>;
+						};
+
+						shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c {
+							reg = <0x2c 0x4>;
+						};
+
+						shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 {
+							reg = <0x30 0x4>;
+						};
+
+						shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 {
+							reg = <0x34 0x4>;
+						};
+
+						shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 {
+							reg = <0x38 0x4>;
+						};
+
+						shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c {
+							reg = <0x4c 0x4>;
+						};
+
+						shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 {
+							reg = <0x50 0x4>;
+						};
+
+						shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 {
+							reg = <0x54 0x4>;
+						};
+
+						shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 {
+							reg = <0x58 0x4>;
+						};
+					};
+				};
+
+				ethernet-switch {
+					compatible = "airoha,an8855-switch";
+					reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
+					airoha,ext-surge;
+
+					ports {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						port@0 {
+							reg = <0>;
+							label = "lan0";
+							phy-mode = "internal";
+							phy-handle = <&internal_phy1>;
+						};
+
+						port@1 {
+							reg = <1>;
+							label = "lan1";
+							phy-mode = "internal";
+							phy-handle = <&internal_phy2>;
+						};
+
+						port@2 {
+							reg = <2>;
+							label = "lan2";
+							phy-mode = "internal";
+							phy-handle = <&internal_phy3>;
+						};
+
+						port@3 {
+							reg = <3>;
+							label = "lan3";
+							phy-mode = "internal";
+							phy-handle = <&internal_phy4>;
+						};
+
+						port@5 {
+							reg = <5>;
+							ethernet = <&gmac0>;
+							phy-mode = "2500base-x";
+
+							fixed-link {
+								speed = <2500>;
+								full-duplex;
+								pause;
+							};
+						};
+					};
+				};
+
+				mdio {
+					compatible = "airoha,an8855-mdio";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					internal_phy1: phy@1 {
+						reg = <1>;
+
+						nvmem-cells = <&shift_sel_port0_tx_a>,
+								<&shift_sel_port0_tx_b>,
+								<&shift_sel_port0_tx_c>,
+								<&shift_sel_port0_tx_d>;
+						nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+					};
+
+					internal_phy2: phy@2 {
+						reg = <2>;
+
+						nvmem-cells = <&shift_sel_port1_tx_a>,
+								<&shift_sel_port1_tx_b>,
+								<&shift_sel_port1_tx_c>,
+								<&shift_sel_port1_tx_d>;
+						nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+					};
+
+					internal_phy3: phy@3 {
+						reg = <3>;
+
+						nvmem-cells = <&shift_sel_port2_tx_a>,
+								<&shift_sel_port2_tx_b>,
+								<&shift_sel_port2_tx_c>,
+								<&shift_sel_port2_tx_d>;
+						nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+					};
+
+					internal_phy4: phy@4 {
+						reg = <4>;
+
+						nvmem-cells = <&shift_sel_port3_tx_a>,
+								<&shift_sel_port3_tx_b>,
+								<&shift_sel_port3_tx_c>,
+								<&shift_sel_port3_tx_d>;
+						nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+					};
+				};
+			};
+		};
+	};
+};

target/linux/mediatek/dts/mt7987a-rfb-eth0-e2p5g.dtso

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	fragment@0 {
+		target = <&gmac0>;
+		__overlay__ {
+			phy-handle = <&phy12>;
+			phy-mode = "2500base-x";
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target-path = "/soc_netsys/ethernet@15100000/mdio-bus";
+		__overlay__ {
+			phy12: phy@12 {
+				compatible = "ethernet-phy-id03a2.a411";
+				reg = <12>;
+				reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
+				reset-assert-us = <10000>;
+				reset-deassert-us = <10000>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+};

target/linux/mediatek/dts/mt7987a-rfb-eth0-mt7531.dtso

@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&gmac0>;
+		__overlay__ {
+			phy-mode = "2500base-x";
+			status = "okay";
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+
+	fragment@1 {
+		target-path = "/soc_netsys/ethernet@15100000/mdio-bus";
+		__overlay__ {
+			phy12: phy@12 {
+				compatible = "ethernet-phy-id03a2.a411";
+				reg = <12>;
+				reset-gpios = <&pio 49 1>;
+				reset-assert-us = <10000>;
+				reset-deassert-us = <10000>;
+				phy-mode = "2500base-x";
+				full-duplex;
+				pause;
+				airoha,pnswap-rx;
+			};
+
+			switch31: switch@31 {
+				compatible = "mediatek,mt7531";
+				reg = <31>;
+				reset-gpios = <&pio 42 0>;
+				status = "okay";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						label = "lan0";
+					};
+
+					port@1 {
+						reg = <1>;
+						label = "lan1";
+					};
+
+					port@2 {
+						reg = <2>;
+						label = "lan2";
+					};
+
+					port@3 {
+						reg = <3>;
+						label = "lan3";
+					};
+
+					port@5 {
+						reg = <5>;
+						label = "lan5";
+						phy-mode = "2500base-x";
+						phy-handle = <&phy12>;
+					};
+
+					port@6 {
+						reg = <6>;
+						label = "cpu";
+						ethernet = <&gmac0>;
+						phy-mode = "2500base-x";
+
+						fixed-link {
+							speed = <2500>;
+							full-duplex;
+							pause;
+						};
+					};
+				};
+
+			};
+		};
+	};
+};
+

target/linux/mediatek/dts/mt7987a-rfb-eth1-i2p5g.dtso

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&gmac1>;
+		__overlay__ {
+			phy-mode = "internal";
+			phy-handle = <&phy15>;
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target-path = "/soc_netsys/ethernet@15100000/mdio-bus";
+		__overlay__ {
+			/* built-in 2.5G Ethernet PHY */
+			phy15: phy@15 {
+				pinctrl-names = "i2p5gbe-led";
+				pinctrl-0 = <&i2p5gbe_led0_pins>;
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <15>;
+				phy-mode = "internal";
+			};
+		};
+	};
+};
+

target/linux/mediatek/dts/mt7987a-rfb-eth2-an8801sb.dtso

@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	fragment@0 {
+		target = <&gmac2>;
+		__overlay__ {
+			phy-handle = <&phy31>;
+			phy-mode = "sgmii";
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target-path = "/soc_netsys/ethernet@15100000/mdio-bus";
+		__overlay__ {
+			phy31: phy@31 {
+				compatible = "ethernet-phy-idc0ff.0421";
+				reg = <31>;
+				reset-gpios = <&pio 48 GPIO_ACTIVE_LOW>;
+				reset-assert-us = <10000>;
+				reset-deassert-us = <10000>;
+				eee-broken-100tx;
+				eee-broken-1000t;
+			};
+		};
+	};
+};
+

target/linux/mediatek/dts/mt7987a-rfb-eth2-e2p5g.dtso

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	fragment@0 {
+		target = <&gmac2>;
+		__overlay__ {
+			phy-handle = <&phy11>;
+			phy-mode = "2500base-x";
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target-path = "/soc_netsys/ethernet@15100000/mdio-bus";
+		__overlay__ {
+			reset-gpios = <&pio 48 GPIO_ACTIVE_LOW>;
+			reset-delay-us = <10000>;
+
+			phy11: phy@11 {
+				compatible = "ethernet-phy-id03a2.a411";
+				reg = <11>;
+			};
+		};
+	};
+};

target/linux/mediatek/dts/mt7987a-rfb-eth2-sfp.dtso

@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	fragment@0 {
+		target-path = "/";
+		__overlay__ {
+			sfp_cage0: sfp@0 {
+				compatible = "sff,sfp";
+				i2c-bus = <&i2c0>;
+				mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
+				los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
+				tx-disable-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
+				maximum-power-milliwatt = <3000>;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&gmac2>;
+		__overlay__ {
+			phy-mode = "2500base-x";
+			managed = "in-band-status";
+			sfp = <&sfp_cage0>;
+			status = "okay";
+		};
+	};
+
+	fragment@2 {
+		target-path = "/soc/i2c@11003000";
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins>;
+			status = "okay";
+		};
+	};
+};

target/linux/mediatek/dts/mt7987a-rfb-eth2-usb.dtso

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/phy/phy.h>
+
+/ {
+	fragment@0 {
+		target-path = "/soc/usb-phy@11c50000/usb-phy@11c50700";
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target-path = "/soc/usb@11200000";
+		__overlay__ {
+			phys = <&tphyu2port0 PHY_TYPE_USB2>,
+			       <&tphyu3port0 PHY_TYPE_USB3>;
+			mediatek,u3p-dis-msk=<0>;
+		};
+	};
+};
+

target/linux/mediatek/dts/mt7987a-rfb-sd.dtso

@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target-path = "/";
+		__overlay__ {
+			reg_3p3v: regulator-3p3v {
+				compatible = "regulator-fixed";
+				regulator-name = "fixed-3.3V";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+
+	fragment@1 {
+		target-path = "/soc/spi@11007800";
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+	fragment@2 {
+		target-path = "/soc/mmc@11230000";
+		__overlay__ {
+			pinctrl-names = "default", "state_uhs";
+			pinctrl-0 = <&sd_pins_default>;
+			pinctrl-1 = <&sd_pins_uhs>;
+			bus-width = <4>;
+			max-frequency = <48000000>;
+			cap-sd-highspeed;
+			vmmc-supply = <&reg_3p3v>;
+			vqmmc-supply = <&reg_3p3v>;
+			no-mmc;
+			no-sdio;
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			card@0 {
+				compatible = "mmc-card";
+				reg = <0>;
+
+				block {
+					compatible = "block-device";
+					partitions {
+						block-partition-env {
+							partname = "ubootenv";
+							nvmem-layout {
+								compatible = "u-boot,env";
+							};
+						};
+						sd_rootfs: block-partition-production {
+							partname = "production";
+						};
+					};
+				};
+			};
+		};
+	};
+
+	fragment@3 {
+		target-path = "/chosen";
+		__overlay__ {
+			rootdisk-sd = <&sd_rootfs>;
+		};
+	};
+};
+

target/linux/mediatek/dts/mt7987a-rfb-spim-nand.dtso

@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target-path = "/soc/spi@11007800";
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi0_flash_pins>;
+			status = "okay";
+
+			flash@0 {
+				compatible = "spi-nand";
+				reg = <0>;
+				spi-max-frequency = <52000000>;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				mediatek,nmbm;
+				mediatek,bmt-max-ratio = <1>;
+				mediatek,bmt-max-reserved-blocks = <64>;
+
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					partition@0 {
+						label = "BL2";
+						reg = <0x00000 0x0100000>;
+						read-only;
+					};
+
+					partition@100000 {
+						label = "u-boot-env";
+						reg = <0x0100000 0x0080000>;
+					};
+
+					factory: partition@180000 {
+						label = "Factory";
+						reg = <0x180000 0x0400000>;
+
+						nvmem-layout {
+							compatible = "fixed-layout";
+							#address-cells = <1>;
+							#size-cells = <1>;
+
+							gmac2_mac: eeprom@fffee {
+								reg = <0xfffee 0x6>;
+							};
+
+							gmac1_mac: eeprom@ffffa {
+								reg = <0xffffa 0x6>;
+							};
+
+							gmac0_mac: eeprom@ffff4 {
+								reg = <0xffff4 0x6>;
+							};
+						};
+					};
+
+					partition@580000 {
+						label = "FIP";
+						reg = <0x580000 0x0200000>;
+					};
+
+					partition@780000 {
+						label = "ubi";
+						reg = <0x780000 0x7080000>;
+						compatible = "linux,ubi";
+
+						volumes {
+							ubi_rootfs: ubi-volume-fit {
+								volname = "firmware";
+							};
+						};
+					};
+				};
+			};
+		};
+	};
+
+	fragment@1 {
+		target-path = "/chosen";
+		__overlay__ {
+			rootdisk-spim-nand = <&ubi_rootfs>;
+		};
+	};
+
+	fragment@2 {
+		target = <&pcie0>;
+		__overlay__ {
+			slot0: pcie@0,0 {
+				reg = <0x0000 0 0 0 0>;
+
+				mt7996@0,0 {
+					compatible = "mediatek,mt76";
+					reg = <0x0000 0 0 0 0>;
+					device_type = "pci";
+					mediatek,mtd-eeprom = <&factory 0x0>;
+				};
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&gmac0>;
+		__overlay__ {
+			nvmem-cell-names = "mac-address";
+			nvmem-cells = <&gmac0_mac>;
+		};
+	};
+
+	fragment@4 {
+		target = <&gmac1>;
+		__overlay__ {
+			nvmem-cell-names = "mac-address";
+			nvmem-cells = <&gmac1_mac>;
+		};
+	};
+
+	fragment@5 {
+		target = <&gmac2>;
+		__overlay__ {
+			nvmem-cell-names = "mac-address";
+			nvmem-cells = <&gmac2_mac>;
+		};
+	};
+};

target/linux/mediatek/dts/mt7987a-rfb-spim-nor.dtso

@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target-path = "/soc/spi@11009800";
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi2_flash_pins>;
+			status = "okay";
+
+			flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "jedec,spi-nor";
+				spi-cal-enable;
+				spi-cal-mode = "read-data";
+				spi-cal-datalen = <7>;
+				spi-cal-data = /bits/ 8 <
+					0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>;
+				spi-cal-addrlen = <1>;
+				spi-cal-addr = /bits/ 32 <0x0>;
+				reg = <0>;
+				spi-max-frequency = <52000000>;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+
+				partition@00000 {
+					label = "BL2";
+					reg = <0x00000 0x0040000>;
+				};
+				partition@40000 {
+					label = "u-boot-env";
+					reg = <0x40000 0x0010000>;
+				};
+				partition@50000 {
+					label = "Factory";
+					reg = <0x50000 0x0200000>;
+				};
+				partition@250000 {
+					label = "FIP";
+					reg = <0x250000 0x0080000>;
+				};
+				nor_rootdisk: partition@2D0000 {
+					label = "firmware";
+					reg = <0x2D0000 0x1D30000>;
+				};
+			};
+		};
+	};
+
+	fragment@1 {
+		target-path = "/chosen";
+		__overlay__ {
+			rootdisk-nor = <&nor_rootdisk>;
+		};
+	};
+};

target/linux/mediatek/dts/mt7987a-rfb.dts

@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+#include <dt-bindings/input/input.h>
+
+/* MT7987A RFB DTS for DT overlay-based device tree */
+/ {
+	model = "MediaTek MT7987A RFB";
+	compatible = "mediatek,mt7987a", "mediatek,mt7987";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    pci=pcie_bus_perf ubi.block=0,firmware \
+			    root=/dev/fit0 rootwait nosmp";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+			debounce-interval = <10>;
+		};
+
+		wps {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+			debounce-interval = <10>;
+		};
+	};
+
+	/* use pwm0 as led: share with fan/pwm_rgb */
+	pwm_led {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwm_pins>;
+		status = "okay";
+
+		led {
+			pwms = <&pwm 0 50000 0>;
+			max-brightness = <255>;
+			active-low;
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	/* use pwm0/1/2 as multicolor LED: share with fan/pwm_led */
+	pwm_rgb {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwm_rgb_pins>;
+		status = "disabled";
+
+		multi-led {
+			color = <LED_COLOR_ID_RGB>;
+			function = LED_FUNCTION_INDICATOR;
+			max-brightness = <255>;
+
+			led-red {
+				pwms = <&pwm 0 50000>;
+				color = <LED_COLOR_ID_RED>;
+			};
+
+			led-green {
+				pwms = <&pwm 1 50000>;
+				color = <LED_COLOR_ID_GREEN>;
+			};
+
+			led-blue {
+				pwms = <&pwm 2 50000>;
+				color = <LED_COLOR_ID_BLUE>;
+			};
+		};
+	};
+};
+
+&fan {
+	pwms = <&pwm 0 50000 0>;
+	status = "disabled";
+};

target/linux/mediatek/dts/mt7987a.dtsi

@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/leds/common.h>
+#include "mt7987.dtsi"
+
+/ {
+	compatible = "mediatek,mt7987a", "mediatek,mt7987";
+
+	memory {
+		reg = <0 0x40000000 0 0x10000000>;
+	};
+
+};
+
+&boottrap {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	status = "okay";
+};
+
+&infra_bus_prot {
+	status = "okay";
+};
+
+&lvts {
+	status = "okay";
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_pins>;
+	status = "okay";
+};
+
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+	status = "disabled";
+};
+
+&pwm {
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&ssusb {
+	status = "okay";
+};

target/linux/mediatek/dts/mt7987b.dtsi

@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+#include "mt7987-netsys-eth2-usb.dtsi"
+
+/ {
+	compatible = "mediatek,mt7987b", "mediatek,mt7987";
+
+	memory {
+		reg = <0 0x40000000 0 0x10000000>;
+	};
+
+	cpus {
+		/delete-node/ cpu@2;
+		/delete-node/ cpu@3;
+	};
+};
+
+&cpu_thermal {
+	cooling-maps {
+		cpu-active-hot {
+			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};

target/linux/mediatek/image/filogic.mk

@@ -24,6 +24,14 @@ define Build/mt7986-bl31-uboot
 	cat $(STAGING_DIR_IMAGE)/mt7986_$1-u-boot.fip >> $@
 endef
 
+define Build/mt7987-bl2
+	cat $(STAGING_DIR_IMAGE)/mt7987-$1-bl2.img >> $@
+endef
+
+define Build/mt7987-bl31-uboot
+	cat $(STAGING_DIR_IMAGE)/mt7987_$1-u-boot.fip >> $@
+endef
+
 define Build/mt7988-bl2
 	cat $(STAGING_DIR_IMAGE)/mt7988-$1-bl2.img >> $@
 endef
@@ -1612,6 +1620,57 @@ define Device/mediatek_mt7986b-rfb
 endef
 TARGET_DEVICES += mediatek_mt7986b-rfb
 
+define Device/mediatek_mt7987a-rfb
+  DEVICE_VENDOR := MediaTek
+  DEVICE_MODEL := MT7987A rfb
+  DEVICE_DTS := mt7987a-rfb
+  DEVICE_DTS_OVERLAY:= \
+	mt7987a-rfb-spim-nand \
+	mt7987a-rfb-spim-nor \
+	mt7987a-rfb-emmc \
+	mt7987a-rfb-sd \
+	mt7987a-rfb-eth0-an8801sb \
+	mt7987a-rfb-eth0-an8855 \
+	mt7987a-rfb-eth0-e2p5g \
+	mt7987a-rfb-eth0-mt7531 \
+	mt7987a-rfb-eth1-i2p5g \
+	mt7987a-rfb-eth2-an8801sb \
+	mt7987a-rfb-eth2-e2p5g \
+	mt7987a-rfb-eth2-sfp \
+	mt7987a-rfb-eth2-usb
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_DTC_FLAGS := --pad 4096
+  DEVICE_DTS_LOADADDR := 0x4ff00000
+  DEVICE_PACKAGES := mt798x-2p5g-phy-firmware-internal kmod-sfp blkid
+  KERNEL_LOADADDR := 0x40000000
+  KERNEL := kernel-bin | gzip
+  KERNEL_INITRAMFS := kernel-bin | lzma | \
+        fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+  IMAGES := sysupgrade.itb
+  KERNEL_INITRAMFS_SUFFIX := .itb
+  KERNEL_IN_UBI := 1
+  IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
+  IMAGES := sysupgrade.itb
+  IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata
+  ARTIFACTS := \
+	snand-preloader.bin \
+	snand-bl31-uboot.fip \
+	sdcard.img.gz
+  ARTIFACT/snand-preloader.bin	:= mt7987-bl2 spim-nand0-ubi-comb
+  ARTIFACT/snand-bl31-uboot.fip	:= mt7987-bl31-uboot rfb-spim-nand
+  ARTIFACT/sdcard.img.gz	:= mt798x-gpt sdmmc |\
+				   pad-to 17k | mt7987-bl2 sdmmc-comb |\
+				   pad-to 6656k | mt7987-bl31-uboot rfb-sd |\
+				$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\
+				  pad-to 12M | append-image-stage initramfs.itb | check-size 44m |\
+				) \
+				$(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\
+				  pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\
+				) \
+				  gzip
+endef
+TARGET_DEVICES += mediatek_mt7987a-rfb
+
 define Device/mediatek_mt7988a-rfb
   DEVICE_VENDOR := MediaTek
   DEVICE_MODEL := MT7988A rfb